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-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h242
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h120
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/hwmgr.h11
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h2
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h4
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h891
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h29
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h217
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu_types.h263
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h27
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h42
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h106
12 files changed, 1747 insertions, 207 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index a0f52c86d8c7..6109815a0401 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -26,6 +26,7 @@
#include "kgd_pp_interface.h"
#include "dm_pp_interface.h"
#include "dm_pp_smu.h"
+#include "smu_types.h"
#define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
#define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255
@@ -150,124 +151,6 @@ struct smu_power_state {
struct smu_hw_power_state hardware;
};
-enum smu_message_type
-{
- SMU_MSG_TestMessage = 0,
- SMU_MSG_GetSmuVersion,
- SMU_MSG_GetDriverIfVersion,
- SMU_MSG_SetAllowedFeaturesMaskLow,
- SMU_MSG_SetAllowedFeaturesMaskHigh,
- SMU_MSG_EnableAllSmuFeatures,
- SMU_MSG_DisableAllSmuFeatures,
- SMU_MSG_EnableSmuFeaturesLow,
- SMU_MSG_EnableSmuFeaturesHigh,
- SMU_MSG_DisableSmuFeaturesLow,
- SMU_MSG_DisableSmuFeaturesHigh,
- SMU_MSG_GetEnabledSmuFeaturesLow,
- SMU_MSG_GetEnabledSmuFeaturesHigh,
- SMU_MSG_SetWorkloadMask,
- SMU_MSG_SetPptLimit,
- SMU_MSG_SetDriverDramAddrHigh,
- SMU_MSG_SetDriverDramAddrLow,
- SMU_MSG_SetToolsDramAddrHigh,
- SMU_MSG_SetToolsDramAddrLow,
- SMU_MSG_TransferTableSmu2Dram,
- SMU_MSG_TransferTableDram2Smu,
- SMU_MSG_UseDefaultPPTable,
- SMU_MSG_UseBackupPPTable,
- SMU_MSG_RunBtc,
- SMU_MSG_RequestI2CBus,
- SMU_MSG_ReleaseI2CBus,
- SMU_MSG_SetFloorSocVoltage,
- SMU_MSG_SoftReset,
- SMU_MSG_StartBacoMonitor,
- SMU_MSG_CancelBacoMonitor,
- SMU_MSG_EnterBaco,
- SMU_MSG_SetSoftMinByFreq,
- SMU_MSG_SetSoftMaxByFreq,
- SMU_MSG_SetHardMinByFreq,
- SMU_MSG_SetHardMaxByFreq,
- SMU_MSG_GetMinDpmFreq,
- SMU_MSG_GetMaxDpmFreq,
- SMU_MSG_GetDpmFreqByIndex,
- SMU_MSG_GetDpmClockFreq,
- SMU_MSG_GetSsVoltageByDpm,
- SMU_MSG_SetMemoryChannelConfig,
- SMU_MSG_SetGeminiMode,
- SMU_MSG_SetGeminiApertureHigh,
- SMU_MSG_SetGeminiApertureLow,
- SMU_MSG_SetMinLinkDpmByIndex,
- SMU_MSG_OverridePcieParameters,
- SMU_MSG_OverDriveSetPercentage,
- SMU_MSG_SetMinDeepSleepDcefclk,
- SMU_MSG_ReenableAcDcInterrupt,
- SMU_MSG_NotifyPowerSource,
- SMU_MSG_SetUclkFastSwitch,
- SMU_MSG_SetUclkDownHyst,
- SMU_MSG_GfxDeviceDriverReset,
- SMU_MSG_GetCurrentRpm,
- SMU_MSG_SetVideoFps,
- SMU_MSG_SetTjMax,
- SMU_MSG_SetFanTemperatureTarget,
- SMU_MSG_PrepareMp1ForUnload,
- SMU_MSG_DramLogSetDramAddrHigh,
- SMU_MSG_DramLogSetDramAddrLow,
- SMU_MSG_DramLogSetDramSize,
- SMU_MSG_SetFanMaxRpm,
- SMU_MSG_SetFanMinPwm,
- SMU_MSG_ConfigureGfxDidt,
- SMU_MSG_NumOfDisplays,
- SMU_MSG_RemoveMargins,
- SMU_MSG_ReadSerialNumTop32,
- SMU_MSG_ReadSerialNumBottom32,
- SMU_MSG_SetSystemVirtualDramAddrHigh,
- SMU_MSG_SetSystemVirtualDramAddrLow,
- SMU_MSG_WaflTest,
- SMU_MSG_SetFclkGfxClkRatio,
- SMU_MSG_AllowGfxOff,
- SMU_MSG_DisallowGfxOff,
- SMU_MSG_GetPptLimit,
- SMU_MSG_GetDcModeMaxDpmFreq,
- SMU_MSG_GetDebugData,
- SMU_MSG_SetXgmiMode,
- SMU_MSG_RunAfllBtc,
- SMU_MSG_ExitBaco,
- SMU_MSG_PrepareMp1ForReset,
- SMU_MSG_PrepareMp1ForShutdown,
- SMU_MSG_SetMGpuFanBoostLimitRpm,
- SMU_MSG_GetAVFSVoltageByDpm,
- SMU_MSG_PowerUpVcn,
- SMU_MSG_PowerDownVcn,
- SMU_MSG_PowerUpJpeg,
- SMU_MSG_PowerDownJpeg,
- SMU_MSG_BacoAudioD3PME,
- SMU_MSG_ArmD3,
- SMU_MSG_MAX_COUNT,
-};
-
-enum smu_clk_type
-{
- SMU_GFXCLK,
- SMU_VCLK,
- SMU_DCLK,
- SMU_ECLK,
- SMU_SOCCLK,
- SMU_UCLK,
- SMU_DCEFCLK,
- SMU_DISPCLK,
- SMU_PIXCLK,
- SMU_PHYCLK,
- SMU_FCLK,
- SMU_SCLK,
- SMU_MCLK,
- SMU_PCIE,
- SMU_OD_SCLK,
- SMU_OD_MCLK,
- SMU_OD_VDDC_CURVE,
- SMU_OD_RANGE,
- SMU_CLK_COUNT,
-};
-
enum smu_power_src_type
{
SMU_POWER_SOURCE_AC,
@@ -275,63 +158,6 @@ enum smu_power_src_type
SMU_POWER_SOURCE_COUNT,
};
-enum smu_feature_mask
-{
- SMU_FEATURE_DPM_PREFETCHER_BIT,
- SMU_FEATURE_DPM_GFXCLK_BIT,
- SMU_FEATURE_DPM_UCLK_BIT,
- SMU_FEATURE_DPM_SOCCLK_BIT,
- SMU_FEATURE_DPM_UVD_BIT,
- SMU_FEATURE_DPM_VCE_BIT,
- SMU_FEATURE_ULV_BIT,
- SMU_FEATURE_DPM_MP0CLK_BIT,
- SMU_FEATURE_DPM_LINK_BIT,
- SMU_FEATURE_DPM_DCEFCLK_BIT,
- SMU_FEATURE_DS_GFXCLK_BIT,
- SMU_FEATURE_DS_SOCCLK_BIT,
- SMU_FEATURE_DS_LCLK_BIT,
- SMU_FEATURE_PPT_BIT,
- SMU_FEATURE_TDC_BIT,
- SMU_FEATURE_THERMAL_BIT,
- SMU_FEATURE_GFX_PER_CU_CG_BIT,
- SMU_FEATURE_RM_BIT,
- SMU_FEATURE_DS_DCEFCLK_BIT,
- SMU_FEATURE_ACDC_BIT,
- SMU_FEATURE_VR0HOT_BIT,
- SMU_FEATURE_VR1HOT_BIT,
- SMU_FEATURE_FW_CTF_BIT,
- SMU_FEATURE_LED_DISPLAY_BIT,
- SMU_FEATURE_FAN_CONTROL_BIT,
- SMU_FEATURE_GFX_EDC_BIT,
- SMU_FEATURE_GFXOFF_BIT,
- SMU_FEATURE_CG_BIT,
- SMU_FEATURE_DPM_FCLK_BIT,
- SMU_FEATURE_DS_FCLK_BIT,
- SMU_FEATURE_DS_MP1CLK_BIT,
- SMU_FEATURE_DS_MP0CLK_BIT,
- SMU_FEATURE_XGMI_BIT,
- SMU_FEATURE_DPM_GFX_PACE_BIT,
- SMU_FEATURE_MEM_VDDCI_SCALING_BIT,
- SMU_FEATURE_MEM_MVDD_SCALING_BIT,
- SMU_FEATURE_DS_UCLK_BIT,
- SMU_FEATURE_GFX_ULV_BIT,
- SMU_FEATURE_FW_DSTATE_BIT,
- SMU_FEATURE_BACO_BIT,
- SMU_FEATURE_VCN_PG_BIT,
- SMU_FEATURE_JPEG_PG_BIT,
- SMU_FEATURE_USB_PG_BIT,
- SMU_FEATURE_RSMU_SMN_CG_BIT,
- SMU_FEATURE_APCC_PLUS_BIT,
- SMU_FEATURE_GTHR_BIT,
- SMU_FEATURE_GFX_DCS_BIT,
- SMU_FEATURE_GFX_SS_BIT,
- SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,
- SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT,
- SMU_FEATURE_MMHUB_PG_BIT,
- SMU_FEATURE_ATHUB_PG_BIT,
- SMU_FEATURE_COUNT,
-};
-
enum smu_memory_pool_size
{
SMU_MEMORY_POOL_SIZE_ZERO = 0,
@@ -396,12 +222,17 @@ struct smu_bios_boot_up_values
uint16_t vdd_gfx;
uint8_t cooling_id;
uint32_t pp_table_id;
+ uint32_t format_revision;
+ uint32_t content_revision;
+ uint32_t fclk;
};
enum smu_table_id
{
SMU_TABLE_PPTABLE = 0,
SMU_TABLE_WATERMARKS,
+ SMU_TABLE_CUSTOM_DPM,
+ SMU_TABLE_DPMCLOCKS,
SMU_TABLE_AVFS,
SMU_TABLE_AVFS_PSM_DEBUG,
SMU_TABLE_AVFS_FUSE_OVERRIDE,
@@ -422,6 +253,7 @@ struct smu_table_context
void *hardcode_pptable;
unsigned long metrics_time;
void *metrics_table;
+ void *clocks_table;
void *max_sustainable_clocks;
struct smu_bios_boot_up_values boot_values;
@@ -540,6 +372,8 @@ struct smu_context
#define WATERMARKS_EXIST (1 << 0)
#define WATERMARKS_LOADED (1 << 1)
uint32_t watermarks_bitmap;
+ uint32_t hard_min_uclk_req_from_dal;
+ bool disable_uclk_switch;
uint32_t workload_mask;
uint32_t workload_prority[WORKLOAD_POLICY_MAX];
@@ -607,8 +441,6 @@ struct pptable_funcs {
uint32_t *mclk_mask,
uint32_t *soc_mask);
int (*set_cpu_power_state)(struct smu_context *smu);
- int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures);
- int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
bool (*is_dpm_running)(struct smu_context *smu);
int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
int (*set_thermal_fan_table)(struct smu_context *smu);
@@ -623,6 +455,10 @@ struct pptable_funcs {
int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
int (*set_default_od_settings)(struct smu_context *smu, bool initialize);
int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
+ int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
+ void (*dump_pptable)(struct smu_context *smu);
+ int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool asic_default);
+ int (*get_dpm_uclk_limited)(struct smu_context *smu, uint32_t *clock, bool max);
};
struct smu_funcs
@@ -639,8 +475,11 @@ struct smu_funcs
int (*get_clk_info_from_vbios)(struct smu_context *smu);
int (*check_pptable)(struct smu_context *smu);
int (*parse_pptable)(struct smu_context *smu);
- int (*populate_smc_pptable)(struct smu_context *smu);
+ int (*populate_smc_tables)(struct smu_context *smu);
int (*check_fw_version)(struct smu_context *smu);
+ int (*powergate_sdma)(struct smu_context *smu, bool gate);
+ int (*powergate_vcn)(struct smu_context *smu, bool gate);
+ int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
int (*write_pptable)(struct smu_context *smu);
int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
int (*set_tool_table_location)(struct smu_context *smu);
@@ -654,9 +493,7 @@ struct smu_funcs
int (*init_display_count)(struct smu_context *smu, uint32_t count);
int (*set_allowed_mask)(struct smu_context *smu);
int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
- int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
int (*notify_display_change)(struct smu_context *smu);
- int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool def);
int (*set_power_limit)(struct smu_context *smu, uint32_t n);
int (*get_current_clk_freq)(struct smu_context *smu, enum smu_clk_type clk_id, uint32_t *value);
int (*init_max_sustainable_clocks)(struct smu_context *smu);
@@ -700,7 +537,7 @@ struct smu_funcs
enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
int (*baco_reset)(struct smu_context *smu);
-
+ int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
};
#define smu_init_microcode(smu) \
@@ -719,6 +556,12 @@ struct smu_funcs
((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
#define smu_setup_pptable(smu) \
((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
+#define smu_powergate_sdma(smu, gate) \
+ ((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
+#define smu_powergate_vcn(smu, gate) \
+ ((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
+#define smu_set_gfx_cgpg(smu, enabled) \
+ ((smu)->funcs->set_gfx_cgpg ? (smu)->funcs->set_gfx_cgpg((smu), (enabled)) : 0)
#define smu_get_vbios_bootup_values(smu) \
((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
#define smu_get_clk_info_from_vbios(smu) \
@@ -727,8 +570,8 @@ struct smu_funcs
((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
#define smu_parse_pptable(smu) \
((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
-#define smu_populate_smc_pptable(smu) \
- ((smu)->funcs->populate_smc_pptable ? (smu)->funcs->populate_smc_pptable((smu)) : 0)
+#define smu_populate_smc_tables(smu) \
+ ((smu)->funcs->populate_smc_tables ? (smu)->funcs->populate_smc_tables((smu)) : 0)
#define smu_check_fw_version(smu) \
((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
#define smu_write_pptable(smu) \
@@ -770,8 +613,6 @@ struct smu_funcs
((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
#define smu_is_dpm_running(smu) \
((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
-#define smu_feature_update_enable_state(smu, feature_id, enabled) \
- ((smu)->funcs->update_feature_enable_state? (smu)->funcs->update_feature_enable_state((smu), (feature_id), (enabled)) : 0)
#define smu_notify_display_change(smu) \
((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
#define smu_store_powerplay_table(smu) \
@@ -787,7 +628,7 @@ struct smu_funcs
#define smu_set_default_od8_settings(smu) \
((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
#define smu_get_power_limit(smu, limit, def) \
- ((smu)->funcs->get_power_limit ? (smu)->funcs->get_power_limit((smu), (limit), (def)) : 0)
+ ((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit((smu), (limit), (def)) : 0)
#define smu_set_power_limit(smu, limit) \
((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0)
#define smu_get_current_clk_freq(smu, clk_id, value) \
@@ -809,9 +650,9 @@ struct smu_funcs
#define smu_start_thermal_control(smu) \
((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
#define smu_read_sensor(smu, sensor, data, size) \
- ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
-#define smu_asic_read_sensor(smu, sensor, data, size) \
((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
+#define smu_smc_read_sensor(smu, sensor, data, size) \
+ ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
#define smu_get_power_profile_mode(smu, buf) \
((smu)->ppt_funcs->get_power_profile_mode ? (smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
#define smu_set_power_profile_mode(smu, param, param_size) \
@@ -875,6 +716,8 @@ struct smu_funcs
((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
#define smu_display_clock_voltage_request(smu, clock_req) \
((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
+#define smu_display_disable_memory_clock_switch(smu, disable_memory_clock_switch) \
+ ((smu)->ppt_funcs->display_disable_memory_clock_switch ? (smu)->ppt_funcs->display_disable_memory_clock_switch((smu), (disable_memory_clock_switch)) : -EINVAL)
#define smu_get_dal_power_level(smu, clocks) \
((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
#define smu_get_perf_level(smu, designation, level) \
@@ -891,10 +734,6 @@ struct smu_funcs
((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
#define smu_set_xgmi_pstate(smu, pstate) \
((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
-#define smu_set_ppfeature_status(smu, ppfeatures) \
- ((smu)->ppt_funcs->set_ppfeature_status ? (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)
-#define smu_get_ppfeature_status(smu, buf) \
- ((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)
#define smu_set_watermarks_table(smu, tab, clock_ranges) \
((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
#define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
@@ -907,8 +746,8 @@ struct smu_funcs
((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
#define smu_set_azalia_d3_pme(smu) \
((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs->set_azalia_d3_pme((smu)) : 0)
-#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
- ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
+#define smu_get_dpm_ultimate_freq(smu, param, min, max) \
+ ((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
#define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
@@ -921,6 +760,10 @@ struct smu_funcs
((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
#define smu_asic_set_performance_level(smu, level) \
((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
+#define smu_dump_pptable(smu) \
+ ((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0)
+#define smu_get_dpm_uclk_limited(smu, clock, max) \
+ ((smu)->ppt_funcs->get_dpm_uclk_limited ? (smu)->ppt_funcs->get_dpm_uclk_limited((smu), (clock), (max)) : -EINVAL)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
@@ -930,6 +773,8 @@ extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
extern const struct amd_ip_funcs smu_ip_funcs;
extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
+extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
+
extern int smu_feature_init_dpm(struct smu_context *smu);
extern int smu_feature_is_enabled(struct smu_context *smu,
@@ -945,6 +790,7 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int
void *table_data, bool drv2smu);
bool is_support_sw_smu(struct amdgpu_device *adev);
+bool is_support_sw_smu_xgmi(struct amdgpu_device *adev);
int smu_reset(struct smu_context *smu);
int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
void *data, uint32_t *size);
@@ -963,6 +809,9 @@ extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, b
extern int smu_handle_task(struct smu_context *smu,
enum amd_dpm_forced_level level,
enum amd_pp_task task_id);
+int smu_switch_power_profile(struct smu_context *smu,
+ enum PP_SMC_POWER_PROFILE type,
+ bool en);
int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version);
int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
uint16_t level, uint32_t *value);
@@ -978,5 +827,10 @@ enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
int smu_set_display_count(struct smu_context *smu, uint32_t count);
bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
+int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);
+const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
+const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h
new file mode 100644
index 000000000000..78e5927b7711
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef ARCTURUS_PP_SMC_H
+#define ARCTURUS_PP_SMC_H
+
+#pragma pack(push, 1)
+
+// SMU Response Codes:
+#define PPSMC_Result_OK 0x1
+#define PPSMC_Result_Failed 0xFF
+#define PPSMC_Result_UnknownCmd 0xFE
+#define PPSMC_Result_CmdRejectedPrereq 0xFD
+#define PPSMC_Result_CmdRejectedBusy 0xFC
+
+// Message Definitions:
+// BASIC
+#define PPSMC_MSG_TestMessage 0x1
+#define PPSMC_MSG_GetSmuVersion 0x2
+#define PPSMC_MSG_GetDriverIfVersion 0x3
+#define PPSMC_MSG_SetAllowedFeaturesMaskLow 0x4
+#define PPSMC_MSG_SetAllowedFeaturesMaskHigh 0x5
+#define PPSMC_MSG_EnableAllSmuFeatures 0x6
+#define PPSMC_MSG_DisableAllSmuFeatures 0x7
+#define PPSMC_MSG_EnableSmuFeaturesLow 0x8
+#define PPSMC_MSG_EnableSmuFeaturesHigh 0x9
+#define PPSMC_MSG_DisableSmuFeaturesLow 0xA
+#define PPSMC_MSG_DisableSmuFeaturesHigh 0xB
+#define PPSMC_MSG_GetEnabledSmuFeaturesLow 0xC
+#define PPSMC_MSG_GetEnabledSmuFeaturesHigh 0xD
+#define PPSMC_MSG_SetDriverDramAddrHigh 0xE
+#define PPSMC_MSG_SetDriverDramAddrLow 0xF
+#define PPSMC_MSG_SetToolsDramAddrHigh 0x10
+#define PPSMC_MSG_SetToolsDramAddrLow 0x11
+#define PPSMC_MSG_TransferTableSmu2Dram 0x12
+#define PPSMC_MSG_TransferTableDram2Smu 0x13
+#define PPSMC_MSG_UseDefaultPPTable 0x14
+#define PPSMC_MSG_UseBackupPPTable 0x15
+#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x16
+#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x17
+
+//BACO/BAMACO/BOMACO
+#define PPSMC_MSG_EnterBaco 0x18
+#define PPSMC_MSG_ExitBaco 0x19
+#define PPSMC_MSG_ArmD3 0x1A
+
+//DPM
+#define PPSMC_MSG_SetSoftMinByFreq 0x1B
+#define PPSMC_MSG_SetSoftMaxByFreq 0x1C
+#define PPSMC_MSG_SetHardMinByFreq 0x1D
+#define PPSMC_MSG_SetHardMaxByFreq 0x1E
+#define PPSMC_MSG_GetMinDpmFreq 0x1F
+#define PPSMC_MSG_GetMaxDpmFreq 0x20
+#define PPSMC_MSG_GetDpmFreqByIndex 0x21
+
+#define PPSMC_MSG_SetWorkloadMask 0x22
+#define PPSMC_MSG_SetDfSwitchType 0x23
+#define PPSMC_MSG_GetVoltageByDpm 0x24
+#define PPSMC_MSG_GetVoltageByDpmOverdrive 0x25
+
+#define PPSMC_MSG_SetPptLimit 0x26
+#define PPSMC_MSG_GetPptLimit 0x27
+
+//Power Gating
+#define PPSMC_MSG_PowerUpVcn0 0x28
+#define PPSMC_MSG_PowerDownVcn0 0x29
+#define PPSMC_MSG_PowerUpVcn1 0x2A
+#define PPSMC_MSG_PowerDownVcn1 0x2B
+
+//Resets and reload
+#define PPSMC_MSG_PrepareMp1ForUnload 0x2C
+#define PPSMC_MSG_PrepareMp1ForReset 0x2D
+#define PPSMC_MSG_PrepareMp1ForShutdown 0x2E
+#define PPSMC_MSG_SoftReset 0x2F
+
+//BTC
+#define PPSMC_MSG_RunAfllBtc 0x30
+#define PPSMC_MSG_RunGfxDcBtc 0x31
+#define PPSMC_MSG_RunSocDcBtc 0x32
+
+//Debug
+#define PPSMC_MSG_DramLogSetDramAddrHigh 0x33
+#define PPSMC_MSG_DramLogSetDramAddrLow 0x34
+#define PPSMC_MSG_DramLogSetDramSize 0x35
+#define PPSMC_MSG_GetDebugData 0x36
+
+//WAFL and XGMI
+#define PPSMC_MSG_WaflTest 0x37
+#define PPSMC_MSG_SetXgmiMode 0x38
+
+//Others
+#define PPSMC_MSG_SetMemoryChannelEnable 0x39
+
+#define PPSMC_Message_Count 0x3A
+
+typedef uint32_t PPSMC_Result;
+typedef uint32_t PPSMC_Msg;
+#pragma pack(pop)
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index c5989cb38b1b..7bf9a14bfa0b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -189,6 +189,14 @@ struct phm_vce_clock_voltage_dependency_table {
struct phm_vce_clock_voltage_dependency_record entries[1];
};
+
+enum SMU_ASIC_RESET_MODE
+{
+ SMU_ASIC_RESET_MODE_0,
+ SMU_ASIC_RESET_MODE_1,
+ SMU_ASIC_RESET_MODE_2,
+};
+
struct pp_smumgr_func {
char *name;
int (*smu_init)(struct pp_hwmgr *hwmgr);
@@ -344,6 +352,9 @@ struct pp_hwmgr_func {
int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
+ int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
+ int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
+ int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire);
};
struct pp_table_func {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
index 90879e4092a3..df4677da736c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
@@ -59,7 +59,7 @@
#define PPSMC_MSG_SetDriverDramAddrLow 0x1B
#define PPSMC_MSG_TransferTableSmu2Dram 0x1C
#define PPSMC_MSG_TransferTableDram2Smu 0x1D
-#define PPSMC_MSG_ControlGfxRM 0x1E
+#define PPSMC_MSG_DeviceDriverReset 0x1E
#define PPSMC_MSG_SetGfxclkOverdriveByFreqVid 0x1F
#define PPSMC_MSG_SetHardMinDcefclkByFreq 0x20
#define PPSMC_MSG_SetHardMinSocclkByFreq 0x21
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
index 755d51f9c6a9..fdc6b7a57bc9 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
@@ -27,7 +27,9 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
-#define SMU11_DRIVER_IF_VERSION 0x13
+// Be aware of that the version should be updated in
+// smu_v11_0.h, rename is also needed.
+// #define SMU11_DRIVER_IF_VERSION 0x13
#define PPTABLE_V20_SMU_VERSION 3
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
new file mode 100644
index 000000000000..e02950b505fa
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
@@ -0,0 +1,891 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef SMU11_DRIVER_IF_ARCTURUS_H
+#define SMU11_DRIVER_IF_ARCTURUS_H
+
+// *** IMPORTANT ***
+// SMU TEAM: Always increment the interface version if
+// any structure is changed in this file
+//#define SMU11_DRIVER_IF_VERSION 0x09
+
+#define PPTABLE_ARCTURUS_SMU_VERSION 4
+
+#define NUM_GFXCLK_DPM_LEVELS 16
+#define NUM_VCLK_DPM_LEVELS 8
+#define NUM_DCLK_DPM_LEVELS 8
+#define NUM_MP0CLK_DPM_LEVELS 2
+#define NUM_SOCCLK_DPM_LEVELS 8
+#define NUM_UCLK_DPM_LEVELS 4
+#define NUM_FCLK_DPM_LEVELS 8
+#define NUM_XGMI_LEVELS 2
+#define NUM_XGMI_PSTATE_LEVELS 4
+
+#define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
+#define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
+#define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
+#define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
+#define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
+#define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
+#define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
+#define MAX_XGMI_LEVEL (NUM_XGMI_LEVELS - 1)
+#define MAX_XGMI_PSTATE_LEVEL (NUM_XGMI_PSTATE_LEVELS - 1)
+
+// Feature Control Defines
+// DPM
+#define FEATURE_DPM_PREFETCHER_BIT 0
+#define FEATURE_DPM_GFXCLK_BIT 1
+#define FEATURE_DPM_UCLK_BIT 2
+#define FEATURE_DPM_SOCCLK_BIT 3
+#define FEATURE_DPM_FCLK_BIT 4
+#define FEATURE_DPM_MP0CLK_BIT 5
+#define FEATURE_DPM_XGMI_BIT 6
+// Idle
+#define FEATURE_DS_GFXCLK_BIT 7
+#define FEATURE_DS_SOCCLK_BIT 8
+#define FEATURE_DS_LCLK_BIT 9
+#define FEATURE_DS_FCLK_BIT 10
+#define FEATURE_DS_UCLK_BIT 11
+#define FEATURE_GFX_ULV_BIT 12
+#define FEATURE_DPM_VCN_BIT 13
+#define FEATURE_RSMU_SMN_CG_BIT 14
+#define FEATURE_WAFL_CG_BIT 15
+// Throttler/Response
+#define FEATURE_PPT_BIT 16
+#define FEATURE_TDC_BIT 17
+#define FEATURE_APCC_PLUS_BIT 18
+#define FEATURE_VR0HOT_BIT 19
+#define FEATURE_VR1HOT_BIT 20
+#define FEATURE_FW_CTF_BIT 21
+#define FEATURE_FAN_CONTROL_BIT 22
+#define FEATURE_THERMAL_BIT 23
+// Other
+#define FEATURE_OUT_OF_BAND_MONITOR_BIT 24
+#define FEATURE_TEMP_DEPENDENT_VMIN_BIT 25
+
+#define FEATURE_SPARE_26_BIT 26
+#define FEATURE_SPARE_27_BIT 27
+#define FEATURE_SPARE_28_BIT 28
+#define FEATURE_SPARE_29_BIT 29
+#define FEATURE_SPARE_30_BIT 30
+#define FEATURE_SPARE_31_BIT 31
+#define FEATURE_SPARE_32_BIT 32
+#define FEATURE_SPARE_33_BIT 33
+#define FEATURE_SPARE_34_BIT 34
+#define FEATURE_SPARE_35_BIT 35
+#define FEATURE_SPARE_36_BIT 36
+#define FEATURE_SPARE_37_BIT 37
+#define FEATURE_SPARE_38_BIT 38
+#define FEATURE_SPARE_39_BIT 39
+#define FEATURE_SPARE_40_BIT 40
+#define FEATURE_SPARE_41_BIT 41
+#define FEATURE_SPARE_42_BIT 42
+#define FEATURE_SPARE_43_BIT 43
+#define FEATURE_SPARE_44_BIT 44
+#define FEATURE_SPARE_45_BIT 45
+#define FEATURE_SPARE_46_BIT 46
+#define FEATURE_SPARE_47_BIT 47
+#define FEATURE_SPARE_48_BIT 48
+#define FEATURE_SPARE_49_BIT 49
+#define FEATURE_SPARE_50_BIT 50
+#define FEATURE_SPARE_51_BIT 51
+#define FEATURE_SPARE_52_BIT 52
+#define FEATURE_SPARE_53_BIT 53
+#define FEATURE_SPARE_54_BIT 54
+#define FEATURE_SPARE_55_BIT 55
+#define FEATURE_SPARE_56_BIT 56
+#define FEATURE_SPARE_57_BIT 57
+#define FEATURE_SPARE_58_BIT 58
+#define FEATURE_SPARE_59_BIT 59
+#define FEATURE_SPARE_60_BIT 60
+#define FEATURE_SPARE_61_BIT 61
+#define FEATURE_SPARE_62_BIT 62
+#define FEATURE_SPARE_63_BIT 63
+
+#define NUM_FEATURES 64
+
+
+#define FEATURE_DPM_PREFETCHER_MASK (1 << FEATURE_DPM_PREFETCHER_BIT )
+#define FEATURE_DPM_GFXCLK_MASK (1 << FEATURE_DPM_GFXCLK_BIT )
+#define FEATURE_DPM_UCLK_MASK (1 << FEATURE_DPM_UCLK_BIT )
+#define FEATURE_DPM_SOCCLK_MASK (1 << FEATURE_DPM_SOCCLK_BIT )
+#define FEATURE_DPM_FCLK_MASK (1 << FEATURE_DPM_FCLK_BIT )
+#define FEATURE_DPM_MP0CLK_MASK (1 << FEATURE_DPM_MP0CLK_BIT )
+#define FEATURE_DPM_XGMI_MASK (1 << FEATURE_DPM_XGMI_BIT )
+
+#define FEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT )
+#define FEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT )
+#define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT )
+#define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT )
+#define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT )
+#define FEATURE_GFX_ULV_MASK (1 << FEATURE_GFX_ULV_BIT )
+#define FEATURE_VCN_PG_MASK (1 << FEATURE_VCN_PG_BIT )
+#define FEATURE_RSMU_SMN_CG_MASK (1 << FEATURE_RSMU_SMN_CG_BIT )
+#define FEATURE_WAFL_CG_MASK (1 << FEATURE_WAFL_CG_BIT )
+
+#define FEATURE_PPT_MASK (1 << FEATURE_PPT_BIT )
+#define FEATURE_TDC_MASK (1 << FEATURE_TDC_BIT )
+#define FEATURE_APCC_MASK (1 << FEATURE_APCC_BIT )
+#define FEATURE_VR0HOT_MASK (1 << FEATURE_VR0HOT_BIT )
+#define FEATURE_VR1HOT_MASK (1 << FEATURE_VR1HOT_BIT )
+#define FEATURE_FW_CTF_MASK (1 << FEATURE_FW_CTF_BIT )
+#define FEATURE_FAN_CONTROL_MASK (1 << FEATURE_FAN_CONTROL_BIT )
+#define FEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT )
+
+#define FEATURE_OUT_OF_BAND_MONITOR_MASK (1 << EATURE_OUT_OF_BAND_MONITOR_BIT )
+#define FEATURE_TEMP_DEPENDENT_VMIN_MASK (1 << FEATURE_TEMP_DEPENDENT_VMIN_MASK )
+
+
+//FIXME need updating
+// Debug Overrides Bitmask
+#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000001
+#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCN_FCLK 0x00000002
+
+// I2C Config Bit Defines
+#define I2C_CONTROLLER_ENABLED 1
+#define I2C_CONTROLLER_DISABLED 0
+
+// VR Mapping Bit Defines
+#define VR_MAPPING_VR_SELECT_MASK 0x01
+#define VR_MAPPING_VR_SELECT_SHIFT 0x00
+
+#define VR_MAPPING_PLANE_SELECT_MASK 0x02
+#define VR_MAPPING_PLANE_SELECT_SHIFT 0x01
+
+// PSI Bit Defines
+#define PSI_SEL_VR0_PLANE0_PSI0 0x01
+#define PSI_SEL_VR0_PLANE0_PSI1 0x02
+#define PSI_SEL_VR0_PLANE1_PSI0 0x04
+#define PSI_SEL_VR0_PLANE1_PSI1 0x08
+#define PSI_SEL_VR1_PLANE0_PSI0 0x10
+#define PSI_SEL_VR1_PLANE0_PSI1 0x20
+#define PSI_SEL_VR1_PLANE1_PSI0 0x40
+#define PSI_SEL_VR1_PLANE1_PSI1 0x80
+
+// Throttler Control/Status Bits
+#define THROTTLER_PADDING_BIT 0
+#define THROTTLER_TEMP_EDGE_BIT 1
+#define THROTTLER_TEMP_HOTSPOT_BIT 2
+#define THROTTLER_TEMP_MEM_BIT 3
+#define THROTTLER_TEMP_VR_GFX_BIT 4
+#define THROTTLER_TEMP_VR_MEM_BIT 5
+#define THROTTLER_TEMP_VR_SOC_BIT 6
+#define THROTTLER_TDC_GFX_BIT 7
+#define THROTTLER_TDC_SOC_BIT 8
+#define THROTTLER_PPT0_BIT 9
+#define THROTTLER_PPT1_BIT 10
+#define THROTTLER_PPT2_BIT 11
+#define THROTTLER_PPT3_BIT 12
+#define THROTTLER_PPM_BIT 13
+#define THROTTLER_FIT_BIT 14
+#define THROTTLER_APCC_BIT 15
+
+// Table transfer status
+#define TABLE_TRANSFER_OK 0x0
+#define TABLE_TRANSFER_FAILED 0xFF
+#define TABLE_TRANSFER_PENDING 0xAB
+
+// Workload bits
+#define WORKLOAD_PPLIB_DEFAULT_BIT 0
+#define WORKLOAD_PPLIB_POWER_SAVING_BIT 1
+#define WORKLOAD_PPLIB_VIDEO_BIT 2
+#define WORKLOAD_PPLIB_COMPUTE_BIT 3
+#define WORKLOAD_PPLIB_CUSTOM_BIT 4
+#define WORKLOAD_PPLIB_COUNT 5
+
+//XGMI performance states
+#define XGMI_STATE_D0 1
+#define XGMI_STATE_D3 0
+
+#define NUM_I2C_CONTROLLERS 8
+
+#define I2C_CONTROLLER_ENABLED 1
+#define I2C_CONTROLLER_DISABLED 0
+
+#define MAX_SW_I2C_COMMANDS 8
+
+typedef enum {
+ I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0
+ I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1
+ I2C_CONTROLLER_PORT_COUNT,
+} I2cControllerPort_e;
+
+typedef enum {
+ I2C_CONTROLLER_NAME_VR_GFX = 0,
+ I2C_CONTROLLER_NAME_VR_SOC,
+ I2C_CONTROLLER_NAME_VR_MEM,
+ I2C_CONTROLLER_NAME_SPARE,
+ I2C_CONTROLLER_NAME_COUNT,
+} I2cControllerName_e;
+
+typedef enum {
+ I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
+ I2C_CONTROLLER_THROTTLER_VR_GFX,
+ I2C_CONTROLLER_THROTTLER_VR_SOC,
+ I2C_CONTROLLER_THROTTLER_VR_MEM,
+ I2C_CONTROLLER_THROTTLER_COUNT,
+} I2cControllerThrottler_e;
+
+typedef enum {
+ I2C_CONTROLLER_PROTOCOL_VR_0,
+ I2C_CONTROLLER_PROTOCOL_VR_1,
+ I2C_CONTROLLER_PROTOCOL_TMP_0,
+ I2C_CONTROLLER_PROTOCOL_TMP_1,
+ I2C_CONTROLLER_PROTOCOL_SPARE_0,
+ I2C_CONTROLLER_PROTOCOL_SPARE_1,
+ I2C_CONTROLLER_PROTOCOL_COUNT,
+} I2cControllerProtocol_e;
+
+typedef struct {
+ uint8_t Enabled;
+ uint8_t Speed;
+ uint8_t Padding[2];
+ uint32_t SlaveAddress;
+ uint8_t ControllerPort;
+ uint8_t ControllerName;
+ uint8_t ThermalThrotter;
+ uint8_t I2cProtocol;
+} I2cControllerConfig_t;
+
+typedef enum {
+ I2C_PORT_SVD_SCL = 0,
+ I2C_PORT_GPIO,
+} I2cPort_e;
+
+typedef enum {
+ I2C_SPEED_FAST_50K = 0, //50 Kbits/s
+ I2C_SPEED_FAST_100K, //100 Kbits/s
+ I2C_SPEED_FAST_400K, //400 Kbits/s
+ I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode)
+ I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode)
+ I2C_SPEED_HIGH_2M, //2.3 Mbits/s
+ I2C_SPEED_COUNT,
+} I2cSpeed_e;
+
+typedef enum {
+ I2C_CMD_READ = 0,
+ I2C_CMD_WRITE,
+ I2C_CMD_COUNT,
+} I2cCmdType_e;
+
+#define CMDCONFIG_STOP_BIT 0
+#define CMDCONFIG_RESTART_BIT 1
+
+#define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT)
+#define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT)
+
+typedef struct {
+ uint8_t RegisterAddr; ////only valid for write, ignored for read
+ uint8_t Cmd; //Read(0) or Write(1)
+ uint8_t Data; //Return data for read. Data to send for write
+ uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command
+} SwI2cCmd_t; //SW I2C Command Table
+
+typedef struct {
+ uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)
+ uint8_t I2CSpeed; //Slow(0) or Fast(1)
+ uint16_t SlaveAddress;
+ uint8_t NumCmds; //Number of commands
+ uint8_t Padding[3];
+
+ SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS];
+
+ uint32_t MmHubPadding[8]; // SMU internal use
+
+} SwI2cRequest_t; // SW I2C Request Table
+
+//D3HOT sequences
+typedef enum {
+ BACO_SEQUENCE,
+ MSR_SEQUENCE,
+ BAMACO_SEQUENCE,
+ ULPS_SEQUENCE,
+ D3HOT_SEQUENCE_COUNT,
+}D3HOTSequence_e;
+
+//THis is aligned with RSMU PGFSM Register Mapping
+typedef enum {
+ PG_DYNAMIC_MODE = 0,
+ PG_STATIC_MODE,
+} PowerGatingMode_e;
+
+//This is aligned with RSMU PGFSM Register Mapping
+typedef enum {
+ PG_POWER_DOWN = 0,
+ PG_POWER_UP,
+} PowerGatingSettings_e;
+
+typedef struct {
+ uint32_t a; // store in IEEE float format in this variable
+ uint32_t b; // store in IEEE float format in this variable
+ uint32_t c; // store in IEEE float format in this variable
+} QuadraticInt_t;
+
+typedef struct {
+ uint32_t m; // store in IEEE float format in this variable
+ uint32_t b; // store in IEEE float format in this variable
+} LinearInt_t;
+
+typedef struct {
+ uint32_t a; // store in IEEE float format in this variable
+ uint32_t b; // store in IEEE float format in this variable
+ uint32_t c; // store in IEEE float format in this variable
+} DroopInt_t;
+
+typedef enum {
+ GFXCLK_SOURCE_PLL = 0,
+ GFXCLK_SOURCE_AFLL,
+ GFXCLK_SOURCE_COUNT,
+} GfxclkSrc_e;
+
+typedef enum {
+ PPCLK_GFXCLK,
+ PPCLK_VCLK,
+ PPCLK_DCLK,
+ PPCLK_SOCCLK,
+ PPCLK_UCLK,
+ PPCLK_FCLK,
+ PPCLK_COUNT,
+} PPCLK_e;
+
+typedef enum {
+ POWER_SOURCE_AC,
+ POWER_SOURCE_DC,
+ POWER_SOURCE_COUNT,
+} POWER_SOURCE_e;
+
+typedef enum {
+ TEMP_EDGE,
+ TEMP_HOTSPOT,
+ TEMP_MEM,
+ TEMP_VR_GFX,
+ TEMP_VR_SOC,
+ TEMP_VR_MEM,
+ TEMP_COUNT
+} TEMP_TYPE_e;
+
+typedef enum {
+ PPT_THROTTLER_PPT0,
+ PPT_THROTTLER_PPT1,
+ PPT_THROTTLER_PPT2,
+ PPT_THROTTLER_PPT3,
+ PPT_THROTTLER_COUNT
+} PPT_THROTTLER_e;
+
+typedef enum {
+ VOLTAGE_MODE_AVFS = 0,
+ VOLTAGE_MODE_AVFS_SS,
+ VOLTAGE_MODE_SS,
+ VOLTAGE_MODE_COUNT,
+} VOLTAGE_MODE_e;
+
+typedef enum {
+ AVFS_VOLTAGE_GFX = 0,
+ AVFS_VOLTAGE_SOC,
+ AVFS_VOLTAGE_COUNT,
+} AVFS_VOLTAGE_TYPE_e;
+
+typedef enum {
+ GPIO_INT_POLARITY_ACTIVE_LOW = 0,
+ GPIO_INT_POLARITY_ACTIVE_HIGH,
+} GpioIntPolarity_e;
+
+typedef enum {
+ MEMORY_TYPE_GDDR6 = 0,
+ MEMORY_TYPE_HBM,
+} MemoryType_e;
+
+typedef enum {
+ PWR_CONFIG_TDP = 0,
+ PWR_CONFIG_TGP,
+ PWR_CONFIG_TCP_ESTIMATED,
+ PWR_CONFIG_TCP_MEASURED,
+} PwrConfig_e;
+
+typedef enum {
+ XGMI_LINK_RATE_12 = 0, // 12Gbps
+ XGMI_LINK_RATE_16, // 16Gbps
+ XGMI_LINK_RATE_22, // 22Gbps
+ XGMI_LINK_RATE_25, // 25Gbps
+ XGMI_LINK_RATE_COUNT
+} XGMI_LINK_RATE_e;
+
+typedef enum {
+ XGMI_LINK_WIDTH_2 = 0, // x2
+ XGMI_LINK_WIDTH_4, // x4
+ XGMI_LINK_WIDTH_8, // x8
+ XGMI_LINK_WIDTH_16, // x16
+ XGMI_LINK_WIDTH_COUNT
+} XGMI_LINK_WIDTH_e;
+
+typedef struct {
+ uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only
+ uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
+ uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used
+ uint8_t padding;
+ LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
+ QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V)
+ uint16_t SsFmin; // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin
+ uint16_t Padding16;
+} DpmDescriptor_t;
+
+typedef struct {
+ uint32_t Version;
+
+ // SECTION: Feature Enablement
+ uint32_t FeaturesToRun[2];
+
+ // SECTION: Infrastructure Limits
+ uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT];
+ uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT];
+ uint16_t TdcLimitSoc; // Amps
+ uint16_t TdcLimitSocTau; // Time constant of LPF in ms
+ uint16_t TdcLimitGfx; // Amps
+ uint16_t TdcLimitGfxTau; // Time constant of LPF in ms
+
+ uint16_t TedgeLimit; // Celcius
+ uint16_t ThotspotLimit; // Celcius
+ uint16_t TmemLimit; // Celcius
+ uint16_t Tvr_gfxLimit; // Celcius
+ uint16_t Tvr_memLimit; // Celcius
+ uint16_t Tvr_socLimit; // Celcius
+ uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime)
+
+ uint16_t PpmPowerLimit; // Switch this this power limit when temperature is above PpmTempThreshold
+ uint16_t PpmTemperatureThreshold;
+
+ // SECTION: Throttler settings
+ uint32_t ThrottlerControlMask; // See Throtter masks defines
+
+ // SECTION: ULV Settings
+ uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
+ uint16_t UlvPadding; // Padding
+
+ uint8_t UlvGfxclkBypass; // 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV
+ uint8_t Padding234[3];
+
+ // SECTION: Voltage Control Parameters
+ uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
+ uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
+ uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
+ uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
+
+ uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits
+ uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits
+
+ //SECTION: DPM Config 1
+ DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
+
+ uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz
+ uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz
+ uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz
+ uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz
+ uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
+ uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
+
+ uint32_t Paddingclks[16];
+
+ // SECTION: DPM Config 2
+ uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz
+ uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2)
+
+ // GFXCLK DPM
+ uint16_t GfxclkFidle; // In MHz
+ uint16_t GfxclkSlewRate; // for PLL babystepping???
+ uint8_t Padding567[4];
+ uint16_t GfxclkDsMaxFreq; // In MHz
+ uint8_t GfxclkSource; // 0 = PLL, 1 = AFLL
+ uint8_t Padding456;
+
+ // GFXCLK Thermal DPM (formerly 'Boost' Settings)
+ uint16_t EnableTdpm;
+ uint16_t TdpmHighHystTemperature;
+ uint16_t TdpmLowHystTemperature;
+ uint16_t GfxclkFreqHighTempLimit; // High limit on GFXCLK when temperature is high, for reliability.
+
+ // SECTION: Fan Control
+ uint16_t FanStopTemp; //Celcius
+ uint16_t FanStartTemp; //Celcius
+
+ uint16_t FanGainEdge;
+ uint16_t FanGainHotspot;
+ uint16_t FanGainVrGfx;
+ uint16_t FanGainVrSoc;
+ uint16_t FanGainVrMem;
+ uint16_t FanGainHbm;
+ uint16_t FanPwmMin;
+ uint16_t FanAcousticLimitRpm;
+ uint16_t FanThrottlingRpm;
+ uint16_t FanMaximumRpm;
+ uint16_t FanTargetTemperature;
+ uint16_t FanTargetGfxclk;
+ uint8_t FanZeroRpmEnable;
+ uint8_t FanTachEdgePerRev;
+ uint8_t FanTempInputSelect;
+ uint8_t padding8_Fan;
+
+ // The following are AFC override parameters. Leave at 0 to use FW defaults.
+ int16_t FuzzyFan_ErrorSetDelta;
+ int16_t FuzzyFan_ErrorRateSetDelta;
+ int16_t FuzzyFan_PwmSetDelta;
+ uint16_t FuzzyFan_Reserved;
+
+
+ // SECTION: AVFS
+ // Overrides
+ uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
+ uint8_t Padding8_Avfs[2];
+
+ QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve
+ DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb
+ DroopInt_t dBtcGbGfxAfll; // GHz->V BtcGb
+ DroopInt_t dBtcGbSoc; // GHz->V BtcGb
+ LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V
+
+ QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V
+
+ uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2
+
+ uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT];
+ uint8_t Padding8_GfxBtc[2];
+
+ uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2
+ uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2
+
+ uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2
+
+ // SECTION: XGMI
+ uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3.
+ uint8_t XgmiDpmSpare[2];
+
+ // Temperature Dependent Vmin
+ uint16_t VDDGFX_TVmin; //Celcius
+ uint16_t VDDSOC_TVmin; //Celcius
+ uint16_t VDDGFX_Vmin_HiTemp; // mV Q2
+ uint16_t VDDGFX_Vmin_LoTemp; // mV Q2
+ uint16_t VDDSOC_Vmin_HiTemp; // mV Q2
+ uint16_t VDDSOC_Vmin_LoTemp; // mV Q2
+
+ uint16_t VDDGFX_TVminHystersis; // Celcius
+ uint16_t VDDSOC_TVminHystersis; // Celcius
+
+
+ // SECTION: Advanced Options
+ uint32_t DebugOverrides;
+ QuadraticInt_t ReservedEquation0;
+ QuadraticInt_t ReservedEquation1;
+ QuadraticInt_t ReservedEquation2;
+ QuadraticInt_t ReservedEquation3;
+
+ uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
+ uint16_t PaddingUlv; // Padding
+
+ // Total Power configuration, use defines from PwrConfig_e
+ uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured
+ uint8_t TotalPowerSpare1;
+ uint16_t TotalPowerSpare2;
+
+ // APCC Settings
+ uint16_t PccThresholdLow;
+ uint16_t PccThresholdHigh;
+ uint32_t PaddingAPCC[6]; //FIXME pending SPEC
+
+ // SECTION: Reserved
+ uint32_t Reserved[11];
+
+ // SECTION: BOARD PARAMETERS
+
+ // SVI2 Board Parameters
+ uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
+ uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
+
+ uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
+ uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
+ uint8_t VddMemVrMapping; // Use VR_MAPPING* bitfields
+ uint8_t BoardVrMapping; // Use VR_MAPPING* bitfields
+
+ uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
+ uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
+ uint8_t Padding8_V[2];
+
+ // Telemetry Settings
+ uint16_t GfxMaxCurrent; // in Amps
+ int8_t GfxOffset; // in Amps
+ uint8_t Padding_TelemetryGfx;
+
+ uint16_t SocMaxCurrent; // in Amps
+ int8_t SocOffset; // in Amps
+ uint8_t Padding_TelemetrySoc;
+
+ uint16_t MemMaxCurrent; // in Amps
+ int8_t MemOffset; // in Amps
+ uint8_t Padding_TelemetryMem;
+
+ uint16_t BoardMaxCurrent; // in Amps
+ int8_t BoardOffset; // in Amps
+ uint8_t Padding_TelemetryBoardInput;
+
+ // GPIO Settings
+ uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
+ uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
+ uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
+ uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
+
+ // GFXCLK PLL Spread Spectrum
+ uint8_t PllGfxclkSpreadEnabled; // on or off
+ uint8_t PllGfxclkSpreadPercent; // Q4.4
+ uint16_t PllGfxclkSpreadFreq; // kHz
+
+ // UCLK Spread Spectrum
+ uint8_t UclkSpreadEnabled; // on or off
+ uint8_t UclkSpreadPercent; // Q4.4
+ uint16_t UclkSpreadFreq; // kHz
+
+ // FCLK Spread Spectrum
+ uint8_t FclkSpreadEnabled; // on or off
+ uint8_t FclkSpreadPercent; // Q4.4
+ uint16_t FclkSpreadFreq; // kHz
+
+ // GFXCLK Fll Spread Spectrum
+ uint8_t FllGfxclkSpreadEnabled; // on or off
+ uint8_t FllGfxclkSpreadPercent; // Q4.4
+ uint16_t FllGfxclkSpreadFreq; // kHz
+
+ // I2C Controller Structure
+ I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS];
+
+ // Memory section
+ uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
+
+ uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines
+ uint8_t PaddingMem[3];
+
+ // Total board power
+ uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
+ uint16_t BoardPadding;
+
+ // SECTION: XGMI Training
+ uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS];
+ uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS];
+
+ uint16_t XgmiFclkFreq [NUM_XGMI_PSTATE_LEVELS];
+ uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS];
+
+ // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
+ uint8_t GpioI2cScl; // Serial Clock
+ uint8_t GpioI2cSda; // Serial Data
+ uint16_t GpioPadding;
+
+ uint32_t BoardReserved[9];
+
+ // Padding for MMHUB - do not modify this
+ uint32_t MmHubPadding[8]; // SMU internal use
+
+} PPTable_t;
+
+typedef struct {
+ // Time constant parameters for clock averages in ms
+ uint16_t GfxclkAverageLpfTau;
+ uint16_t SocclkAverageLpfTau;
+ uint16_t UclkAverageLpfTau;
+ uint16_t GfxActivityLpfTau;
+ uint16_t UclkActivityLpfTau;
+
+ uint16_t SocketPowerLpfTau;
+
+ // Padding - ignore
+ uint32_t MmHubPadding[8]; // SMU internal use
+} DriverSmuConfig_t;
+
+typedef struct {
+ uint16_t CurrClock[PPCLK_COUNT];
+ uint16_t AverageGfxclkFrequency;
+ uint16_t AverageSocclkFrequency;
+ uint16_t AverageUclkFrequency ;
+ uint16_t AverageGfxActivity ;
+ uint16_t AverageUclkActivity ;
+ uint8_t CurrSocVoltageOffset ;
+ uint8_t CurrGfxVoltageOffset ;
+ uint8_t CurrMemVidOffset ;
+ uint8_t Padding8 ;
+ uint16_t AverageSocketPower ;
+ uint16_t TemperatureEdge ;
+ uint16_t TemperatureHotspot ;
+ uint16_t TemperatureHBM ;
+ uint16_t TemperatureVrGfx ;
+ uint16_t TemperatureVrSoc ;
+ uint16_t TemperatureVrMem ;
+ uint32_t ThrottlerStatus ;
+
+ uint16_t CurrFanSpeed ;
+ uint16_t Padding16;
+
+ uint32_t Padding[4];
+
+ // Padding - ignore
+ uint32_t MmHubPadding[8]; // SMU internal use
+} SmuMetrics_t;
+
+
+typedef struct {
+ uint16_t avgPsmCount[75];
+ uint16_t minPsmCount[75];
+ float avgPsmVoltage[75];
+ float minPsmVoltage[75];
+
+ uint32_t MmHubPadding[8]; // SMU internal use
+} AvfsDebugTable_t;
+
+typedef struct {
+ uint8_t AvfsVersion;
+ uint8_t Padding;
+ uint8_t AvfsEn[AVFS_VOLTAGE_COUNT];
+
+ uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT];
+ uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
+
+ uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT];
+ uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT];
+ uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT];
+ uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT];
+
+ int32_t VFT0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
+ int32_t VFT0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
+ int32_t VFT0_b[AVFS_VOLTAGE_COUNT]; // Q32
+
+ int32_t VFT1_m1[AVFS_VOLTAGE_COUNT]; // Q8.16
+ int32_t VFT1_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
+ int32_t VFT1_b[AVFS_VOLTAGE_COUNT]; // Q32
+
+ int32_t VFT2_m1[AVFS_VOLTAGE_COUNT]; // Q8.16
+ int32_t VFT2_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
+ int32_t VFT2_b[AVFS_VOLTAGE_COUNT]; // Q32
+
+ int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
+ int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
+ int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT]; // Q32
+
+ int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
+ int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
+ int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT]; // Q32
+
+ uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT];
+ uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT];
+ uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT];
+
+ uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits
+
+
+ int32_t P2V_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
+ int32_t P2V_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
+ int32_t P2V_b[AVFS_VOLTAGE_COUNT]; // Q32
+
+ uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units
+
+ uint32_t EnabledAvfsModules[2];
+
+ uint32_t MmHubPadding[8]; // SMU internal use
+} AvfsFuseOverride_t;
+
+/* NOT CURRENTLY USED
+typedef struct {
+ uint8_t Gfx_ActiveHystLimit;
+ uint8_t Gfx_IdleHystLimit;
+ uint8_t Gfx_FPS;
+ uint8_t Gfx_MinActiveFreqType;
+ uint8_t Gfx_BoosterFreqType;
+ uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.
+ uint8_t Gfx_UseRlcBusy;
+ uint8_t PaddingGfx[3];
+ uint16_t Gfx_MinActiveFreq; // MHz
+ uint16_t Gfx_BoosterFreq; // MHz
+ uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms
+ uint32_t Gfx_PD_Data_limit_a; // Q16
+ uint32_t Gfx_PD_Data_limit_b; // Q16
+ uint32_t Gfx_PD_Data_limit_c; // Q16
+ uint32_t Gfx_PD_Data_error_coeff; // Q16
+ uint32_t Gfx_PD_Data_error_rate_coeff; // Q16
+
+ uint8_t Mem_ActiveHystLimit;
+ uint8_t Mem_IdleHystLimit;
+ uint8_t Mem_FPS;
+ uint8_t Mem_MinActiveFreqType;
+ uint8_t Mem_BoosterFreqType;
+ uint8_t Mem_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.
+ uint8_t Mem_UseRlcBusy;
+ uint8_t PaddingMem[3];
+ uint16_t Mem_MinActiveFreq; // MHz
+ uint16_t Mem_BoosterFreq; // MHz
+ uint16_t Mem_PD_Data_time_constant; // Time constant of PD controller in ms
+ uint32_t Mem_PD_Data_limit_a; // Q16
+ uint32_t Mem_PD_Data_limit_b; // Q16
+ uint32_t Mem_PD_Data_limit_c; // Q16
+ uint32_t Mem_PD_Data_error_coeff; // Q16
+ uint32_t Mem_PD_Data_error_rate_coeff; // Q16
+
+ uint32_t Mem_UpThreshold_Limit; // Q16
+ uint8_t Mem_UpHystLimit;
+ uint8_t Mem_DownHystLimit;
+ uint16_t Mem_Fps;
+
+ uint32_t MmHubPadding[8]; // SMU internal use
+} DpmActivityMonitorCoeffInt_t;
+*/
+
+// These defines are used with the following messages:
+// SMC_MSG_TransferTableDram2Smu
+// SMC_MSG_TransferTableSmu2Dram
+#define TABLE_PPTABLE 0
+#define TABLE_AVFS 1
+#define TABLE_AVFS_PSM_DEBUG 2
+#define TABLE_AVFS_FUSE_OVERRIDE 3
+#define TABLE_PMSTATUSLOG 4
+#define TABLE_SMU_METRICS 5
+#define TABLE_DRIVER_SMU_CONFIG 6
+//#define TABLE_ACTIVITY_MONITOR_COEFF 7
+#define TABLE_OVERDRIVE 7
+#define TABLE_WAFL_XGMI_TOPOLOGY 8
+#define TABLE_COUNT 9
+
+// These defines are used with the SMC_MSG_SetUclkFastSwitch message.
+typedef enum {
+ DF_SWITCH_TYPE_FAST = 0,
+ DF_SWITCH_TYPE_SLOW,
+ DF_SWITCH_TYPE_COUNT,
+} DF_SWITCH_TYPE_e;
+
+typedef enum {
+ DRAM_BIT_WIDTH_DISABLED = 0,
+ DRAM_BIT_WIDTH_X_8,
+ DRAM_BIT_WIDTH_X_16,
+ DRAM_BIT_WIDTH_X_32,
+ DRAM_BIT_WIDTH_X_64, // NOT USED.
+ DRAM_BIT_WIDTH_X_128,
+ DRAM_BIT_WIDTH_COUNT,
+} DRAM_BIT_WIDTH_TYPE_e;
+
+#define REMOVE_FMAX_MARGIN_BIT 0x0
+#define REMOVE_DCTOL_MARGIN_BIT 0x1
+#define REMOVE_PLATFORM_MARGIN_BIT 0x2
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
index adbbfebbb1e5..ac0120e384be 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
@@ -26,7 +26,9 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
-#define SMU11_DRIVER_IF_VERSION 0x33
+// Be aware of that the version should be updated in
+// smu_v11_0.h, maybe rename is also needed.
+// #define SMU11_DRIVER_IF_VERSION 0x33
#define PPTABLE_NV10_SMU_VERSION 8
@@ -504,10 +506,11 @@ typedef struct {
uint32_t Status;
uint16_t DieTemperature;
- uint16_t MemoryTemperature;
+ uint16_t CurrentMemoryTemperature;
- uint16_t SelectedCardPower;
- uint16_t Reserved4;
+ uint16_t MemoryTemperature;
+ uint8_t MemoryHotspotPosition;
+ uint8_t Reserved4;
uint32_t BoardLevelEnergyAccumulator;
} OutOfBandMonitor_t;
@@ -799,7 +802,12 @@ typedef struct {
// Mvdd Svi2 Div Ratio Setting
uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
- uint32_t BoardReserved[9];
+ uint8_t RenesesLoadLineEnabled;
+ uint8_t GfxLoadlineResistance;
+ uint8_t SocLoadlineResistance;
+ uint8_t Padding8_Loadline;
+
+ uint32_t BoardReserved[8];
// Padding for MMHUB - do not modify this
uint32_t MmHubPadding[8]; // SMU internal use
@@ -903,13 +911,22 @@ typedef struct {
} Watermarks_t;
typedef struct {
+ uint16_t avgPsmCount[28];
+ uint16_t minPsmCount[28];
+ float avgPsmVoltage[28];
+ float minPsmVoltage[28];
+
+ uint32_t MmHubPadding[32]; // SMU internal use
+} AvfsDebugTable_t_NV14;
+
+typedef struct {
uint16_t avgPsmCount[36];
uint16_t minPsmCount[36];
float avgPsmVoltage[36];
float minPsmVoltage[36];
uint32_t MmHubPadding[8]; // SMU internal use
-} AvfsDebugTable_t;
+} AvfsDebugTable_t_NV10;
typedef struct {
uint8_t AvfsVersion;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h
new file mode 100644
index 000000000000..c27c82851468
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h
@@ -0,0 +1,217 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef SMU12_DRIVER_IF_H
+#define SMU12_DRIVER_IF_H
+
+// *** IMPORTANT ***
+// SMU TEAM: Always increment the interface version if
+// any structure is changed in this file
+#define SMU12_DRIVER_IF_VERSION 10
+
+typedef struct {
+ int32_t value;
+ uint32_t numFractionalBits;
+} FloatInIntFormat_t;
+
+typedef enum {
+ DSPCLK_DCFCLK = 0,
+ DSPCLK_DISPCLK,
+ DSPCLK_PIXCLK,
+ DSPCLK_PHYCLK,
+ DSPCLK_COUNT,
+} DSPCLK_e;
+
+typedef struct {
+ uint16_t Freq; // in MHz
+ uint16_t Vid; // min voltage in SVI2 VID
+} DisplayClockTable_t;
+
+typedef struct {
+ uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
+ uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
+ uint16_t MinMclk;
+ uint16_t MaxMclk;
+
+ uint8_t WmSetting;
+ uint8_t WmType; // Used for normal pstate change or memory retraining
+ uint8_t Padding[2];
+} WatermarkRowGeneric_t;
+
+#define NUM_WM_RANGES 4
+#define WM_PSTATE_CHG 0
+#define WM_RETRAINING 1
+
+typedef enum {
+ WM_SOCCLK = 0,
+ WM_DCFCLK,
+ WM_COUNT,
+} WM_CLOCK_e;
+
+typedef struct {
+ // Watermarks
+ WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
+
+ uint32_t MmHubPadding[7]; // SMU internal use
+} Watermarks_t;
+
+typedef enum {
+ CUSTOM_DPM_SETTING_GFXCLK,
+ CUSTOM_DPM_SETTING_CCLK,
+ CUSTOM_DPM_SETTING_FCLK_CCX,
+ CUSTOM_DPM_SETTING_FCLK_GFX,
+ CUSTOM_DPM_SETTING_FCLK_STALLS,
+ CUSTOM_DPM_SETTING_LCLK,
+ CUSTOM_DPM_SETTING_COUNT,
+} CUSTOM_DPM_SETTING_e;
+
+typedef struct {
+ uint8_t ActiveHystLimit;
+ uint8_t IdleHystLimit;
+ uint8_t FPS;
+ uint8_t MinActiveFreqType;
+ FloatInIntFormat_t MinActiveFreq;
+ FloatInIntFormat_t PD_Data_limit;
+ FloatInIntFormat_t PD_Data_time_constant;
+ FloatInIntFormat_t PD_Data_error_coeff;
+ FloatInIntFormat_t PD_Data_error_rate_coeff;
+} DpmActivityMonitorCoeffExt_t;
+
+typedef struct {
+ DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
+} CustomDpmSettings_t;
+
+
+#define NUM_DCFCLK_DPM_LEVELS 8
+#define NUM_SOCCLK_DPM_LEVELS 8
+#define NUM_FCLK_DPM_LEVELS 4
+#define NUM_MEMCLK_DPM_LEVELS 4
+#define NUM_VCN_DPM_LEVELS 8
+
+typedef struct {
+ uint32_t Freq; // In MHz
+ uint32_t Vol; // Millivolts with 2 fractional bits
+} DpmClock_t;
+
+typedef struct {
+ DpmClock_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
+ DpmClock_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
+ DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS];
+ DpmClock_t MemClocks[NUM_MEMCLK_DPM_LEVELS];
+ DpmClock_t VClocks[NUM_VCN_DPM_LEVELS];
+ DpmClock_t DClocks[NUM_VCN_DPM_LEVELS];
+
+ uint8_t NumDcfClkDpmEnabled;
+ uint8_t NumSocClkDpmEnabled;
+ uint8_t NumFClkDpmEnabled;
+ uint8_t NumMemClkDpmEnabled;
+ uint8_t NumVClkDpmEnabled;
+ uint8_t NumDClkDpmEnabled;
+ uint8_t spare[2];
+} DpmClocks_t;
+
+
+typedef enum {
+ CLOCK_SMNCLK = 0,
+ CLOCK_SOCCLK,
+ CLOCK_MP0CLK,
+ CLOCK_MP1CLK,
+ CLOCK_MP2CLK,
+ CLOCK_VCLK,
+ CLOCK_LCLK,
+ CLOCK_DCLK,
+ CLOCK_ACLK,
+ CLOCK_ISPCLK,
+ CLOCK_SHUBCLK,
+ CLOCK_DISPCLK,
+ CLOCK_DPPCLK,
+ CLOCK_DPREFCLK,
+ CLOCK_DCFCLK,
+ CLOCK_FCLK,
+ CLOCK_UMCCLK,
+ CLOCK_GFXCLK,
+ CLOCK_COUNT,
+} CLOCK_IDs_e;
+
+// Throttler Status Bitmask
+#define THROTTLER_STATUS_BIT_SPL 0
+#define THROTTLER_STATUS_BIT_FPPT 1
+#define THROTTLER_STATUS_BIT_SPPT 2
+#define THROTTLER_STATUS_BIT_SPPT_APU 3
+#define THROTTLER_STATUS_BIT_THM_CORE 4
+#define THROTTLER_STATUS_BIT_THM_GFX 5
+#define THROTTLER_STATUS_BIT_THM_SOC 6
+#define THROTTLER_STATUS_BIT_TDC_VDD 7
+#define THROTTLER_STATUS_BIT_TDC_SOC 8
+
+typedef struct {
+ uint16_t ClockFrequency[CLOCK_COUNT]; //[MHz]
+
+ uint16_t AverageGfxclkFrequency; //[MHz]
+ uint16_t AverageSocclkFrequency; //[MHz]
+ uint16_t AverageVclkFrequency; //[MHz]
+ uint16_t AverageFclkFrequency; //[MHz]
+
+ uint16_t AverageGfxActivity; //[centi]
+ uint16_t AverageUvdActivity; //[centi]
+
+ uint16_t Voltage[2]; //[mV] indices: VDDCR_VDD, VDDCR_SOC
+ uint16_t Current[2]; //[mA] indices: VDDCR_VDD, VDDCR_SOC
+ uint16_t Power[2]; //[mW] indices: VDDCR_VDD, VDDCR_SOC
+
+ uint16_t FanPwm; //[milli]
+ uint16_t CurrentSocketPower; //[mW]
+
+ uint16_t CoreFrequency[8]; //[MHz]
+ uint16_t CorePower[8]; //[mW]
+ uint16_t CoreTemperature[8]; //[centi-Celsius]
+ uint16_t L3Frequency[2]; //[MHz]
+ uint16_t L3Temperature[2]; //[centi-Celsius]
+
+ uint16_t GfxTemperature; //[centi-Celsius]
+ uint16_t SocTemperature; //[centi-Celsius]
+ uint16_t ThrottlerStatus;
+ uint16_t spare;
+} SmuMetrics_t;
+
+
+// Workload bits
+#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
+#define WORKLOAD_PPLIB_VIDEO_BIT 2
+#define WORKLOAD_PPLIB_VR_BIT 3
+#define WORKLOAD_PPLIB_COMPUTE_BIT 4
+#define WORKLOAD_PPLIB_CUSTOM_BIT 5
+#define WORKLOAD_PPLIB_COUNT 6
+
+#define TABLE_BIOS_IF 0 // Called by BIOS
+#define TABLE_WATERMARKS 1 // Called by Driver
+#define TABLE_CUSTOM_DPM 2 // Called by Driver
+#define TABLE_SPARE1 3
+#define TABLE_DPMCLOCKS 4 // Called by Driver
+#define TABLE_MOMENTARY_PM 5 // Called by Tools
+#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
+#define TABLE_SMU_METRICS 7 // Called by Driver
+#define TABLE_COUNT 8
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
new file mode 100644
index 000000000000..b0dd05d431dd
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
@@ -0,0 +1,263 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __SMU_TYPES_H__
+#define __SMU_TYPES_H__
+
+#define SMU_MESSAGE_TYPES \
+ __SMU_DUMMY_MAP(TestMessage), \
+ __SMU_DUMMY_MAP(GetSmuVersion), \
+ __SMU_DUMMY_MAP(GetDriverIfVersion), \
+ __SMU_DUMMY_MAP(SetAllowedFeaturesMaskLow), \
+ __SMU_DUMMY_MAP(SetAllowedFeaturesMaskHigh), \
+ __SMU_DUMMY_MAP(EnableAllSmuFeatures), \
+ __SMU_DUMMY_MAP(DisableAllSmuFeatures), \
+ __SMU_DUMMY_MAP(EnableSmuFeaturesLow), \
+ __SMU_DUMMY_MAP(EnableSmuFeaturesHigh), \
+ __SMU_DUMMY_MAP(DisableSmuFeaturesLow), \
+ __SMU_DUMMY_MAP(DisableSmuFeaturesHigh), \
+ __SMU_DUMMY_MAP(GetEnabledSmuFeaturesLow), \
+ __SMU_DUMMY_MAP(GetEnabledSmuFeaturesHigh), \
+ __SMU_DUMMY_MAP(SetWorkloadMask), \
+ __SMU_DUMMY_MAP(SetPptLimit), \
+ __SMU_DUMMY_MAP(SetDriverDramAddrHigh), \
+ __SMU_DUMMY_MAP(SetDriverDramAddrLow), \
+ __SMU_DUMMY_MAP(SetToolsDramAddrHigh), \
+ __SMU_DUMMY_MAP(SetToolsDramAddrLow), \
+ __SMU_DUMMY_MAP(TransferTableSmu2Dram), \
+ __SMU_DUMMY_MAP(TransferTableDram2Smu), \
+ __SMU_DUMMY_MAP(UseDefaultPPTable), \
+ __SMU_DUMMY_MAP(UseBackupPPTable), \
+ __SMU_DUMMY_MAP(RunBtc), \
+ __SMU_DUMMY_MAP(RequestI2CBus), \
+ __SMU_DUMMY_MAP(ReleaseI2CBus), \
+ __SMU_DUMMY_MAP(SetFloorSocVoltage), \
+ __SMU_DUMMY_MAP(SoftReset), \
+ __SMU_DUMMY_MAP(StartBacoMonitor), \
+ __SMU_DUMMY_MAP(CancelBacoMonitor), \
+ __SMU_DUMMY_MAP(EnterBaco), \
+ __SMU_DUMMY_MAP(SetSoftMinByFreq), \
+ __SMU_DUMMY_MAP(SetSoftMaxByFreq), \
+ __SMU_DUMMY_MAP(SetHardMinByFreq), \
+ __SMU_DUMMY_MAP(SetHardMaxByFreq), \
+ __SMU_DUMMY_MAP(GetMinDpmFreq), \
+ __SMU_DUMMY_MAP(GetMaxDpmFreq), \
+ __SMU_DUMMY_MAP(GetDpmFreqByIndex), \
+ __SMU_DUMMY_MAP(GetDpmClockFreq), \
+ __SMU_DUMMY_MAP(GetSsVoltageByDpm), \
+ __SMU_DUMMY_MAP(SetMemoryChannelConfig), \
+ __SMU_DUMMY_MAP(SetGeminiMode), \
+ __SMU_DUMMY_MAP(SetGeminiApertureHigh), \
+ __SMU_DUMMY_MAP(SetGeminiApertureLow), \
+ __SMU_DUMMY_MAP(SetMinLinkDpmByIndex), \
+ __SMU_DUMMY_MAP(OverridePcieParameters), \
+ __SMU_DUMMY_MAP(OverDriveSetPercentage), \
+ __SMU_DUMMY_MAP(SetMinDeepSleepDcefclk), \
+ __SMU_DUMMY_MAP(ReenableAcDcInterrupt), \
+ __SMU_DUMMY_MAP(NotifyPowerSource), \
+ __SMU_DUMMY_MAP(SetUclkFastSwitch), \
+ __SMU_DUMMY_MAP(SetUclkDownHyst), \
+ __SMU_DUMMY_MAP(GfxDeviceDriverReset), \
+ __SMU_DUMMY_MAP(GetCurrentRpm), \
+ __SMU_DUMMY_MAP(SetVideoFps), \
+ __SMU_DUMMY_MAP(SetTjMax), \
+ __SMU_DUMMY_MAP(SetFanTemperatureTarget), \
+ __SMU_DUMMY_MAP(PrepareMp1ForUnload), \
+ __SMU_DUMMY_MAP(DramLogSetDramAddrHigh), \
+ __SMU_DUMMY_MAP(DramLogSetDramAddrLow), \
+ __SMU_DUMMY_MAP(DramLogSetDramSize), \
+ __SMU_DUMMY_MAP(SetFanMaxRpm), \
+ __SMU_DUMMY_MAP(SetFanMinPwm), \
+ __SMU_DUMMY_MAP(ConfigureGfxDidt), \
+ __SMU_DUMMY_MAP(NumOfDisplays), \
+ __SMU_DUMMY_MAP(RemoveMargins), \
+ __SMU_DUMMY_MAP(ReadSerialNumTop32), \
+ __SMU_DUMMY_MAP(ReadSerialNumBottom32), \
+ __SMU_DUMMY_MAP(SetSystemVirtualDramAddrHigh), \
+ __SMU_DUMMY_MAP(SetSystemVirtualDramAddrLow), \
+ __SMU_DUMMY_MAP(WaflTest), \
+ __SMU_DUMMY_MAP(SetFclkGfxClkRatio), \
+ __SMU_DUMMY_MAP(AllowGfxOff), \
+ __SMU_DUMMY_MAP(DisallowGfxOff), \
+ __SMU_DUMMY_MAP(GetPptLimit), \
+ __SMU_DUMMY_MAP(GetDcModeMaxDpmFreq), \
+ __SMU_DUMMY_MAP(GetDebugData), \
+ __SMU_DUMMY_MAP(SetXgmiMode), \
+ __SMU_DUMMY_MAP(RunAfllBtc), \
+ __SMU_DUMMY_MAP(ExitBaco), \
+ __SMU_DUMMY_MAP(PrepareMp1ForReset), \
+ __SMU_DUMMY_MAP(PrepareMp1ForShutdown), \
+ __SMU_DUMMY_MAP(SetMGpuFanBoostLimitRpm), \
+ __SMU_DUMMY_MAP(GetAVFSVoltageByDpm), \
+ __SMU_DUMMY_MAP(PowerUpVcn), \
+ __SMU_DUMMY_MAP(PowerDownVcn), \
+ __SMU_DUMMY_MAP(PowerUpJpeg), \
+ __SMU_DUMMY_MAP(PowerDownJpeg), \
+ __SMU_DUMMY_MAP(BacoAudioD3PME), \
+ __SMU_DUMMY_MAP(ArmD3), \
+ __SMU_DUMMY_MAP(RunGfxDcBtc), \
+ __SMU_DUMMY_MAP(RunSocDcBtc), \
+ __SMU_DUMMY_MAP(SetMemoryChannelEnable), \
+ __SMU_DUMMY_MAP(SetDfSwitchType), \
+ __SMU_DUMMY_MAP(GetVoltageByDpm), \
+ __SMU_DUMMY_MAP(GetVoltageByDpmOverdrive), \
+ __SMU_DUMMY_MAP(PowerUpVcn0), \
+ __SMU_DUMMY_MAP(PowerDownVcn0), \
+ __SMU_DUMMY_MAP(PowerUpVcn1), \
+ __SMU_DUMMY_MAP(PowerDownVcn1), \
+ __SMU_DUMMY_MAP(PowerUpGfx), \
+ __SMU_DUMMY_MAP(PowerDownIspByTile), \
+ __SMU_DUMMY_MAP(PowerUpIspByTile), \
+ __SMU_DUMMY_MAP(PowerDownSdma), \
+ __SMU_DUMMY_MAP(PowerUpSdma), \
+ __SMU_DUMMY_MAP(SetHardMinIspclkByFreq), \
+ __SMU_DUMMY_MAP(SetHardMinVcn), \
+ __SMU_DUMMY_MAP(Spare1), \
+ __SMU_DUMMY_MAP(Spare2), \
+ __SMU_DUMMY_MAP(SetAllowFclkSwitch), \
+ __SMU_DUMMY_MAP(SetMinVideoGfxclkFreq), \
+ __SMU_DUMMY_MAP(ActiveProcessNotify), \
+ __SMU_DUMMY_MAP(SetCustomPolicy), \
+ __SMU_DUMMY_MAP(QueryPowerLimit), \
+ __SMU_DUMMY_MAP(SetGfxclkOverdriveByFreqVid), \
+ __SMU_DUMMY_MAP(SetHardMinDcfclkByFreq), \
+ __SMU_DUMMY_MAP(SetHardMinSocclkByFreq), \
+ __SMU_DUMMY_MAP(ControlIgpuATS), \
+ __SMU_DUMMY_MAP(SetMinVideoFclkFreq), \
+ __SMU_DUMMY_MAP(SetMinDeepSleepDcfclk), \
+ __SMU_DUMMY_MAP(ForcePowerDownGfx), \
+ __SMU_DUMMY_MAP(SetPhyclkVoltageByFreq), \
+ __SMU_DUMMY_MAP(SetDppclkVoltageByFreq), \
+ __SMU_DUMMY_MAP(SetSoftMinVcn), \
+ __SMU_DUMMY_MAP(EnablePostCode), \
+ __SMU_DUMMY_MAP(GetGfxclkFrequency), \
+ __SMU_DUMMY_MAP(GetFclkFrequency), \
+ __SMU_DUMMY_MAP(GetMinGfxclkFrequency), \
+ __SMU_DUMMY_MAP(GetMaxGfxclkFrequency), \
+ __SMU_DUMMY_MAP(SetGfxCGPG), \
+ __SMU_DUMMY_MAP(SetSoftMaxGfxClk), \
+ __SMU_DUMMY_MAP(SetHardMinGfxClk), \
+ __SMU_DUMMY_MAP(SetSoftMaxSocclkByFreq), \
+ __SMU_DUMMY_MAP(SetSoftMaxFclkByFreq), \
+ __SMU_DUMMY_MAP(SetSoftMaxVcn), \
+ __SMU_DUMMY_MAP(PowerGateMmHub), \
+ __SMU_DUMMY_MAP(UpdatePmeRestore), \
+ __SMU_DUMMY_MAP(GpuChangeState), \
+ __SMU_DUMMY_MAP(SetPowerLimitPercentage), \
+ __SMU_DUMMY_MAP(ForceGfxContentSave), \
+ __SMU_DUMMY_MAP(EnableTmdp48MHzRefclkPwrDown), \
+ __SMU_DUMMY_MAP(PowerGateAtHub), \
+ __SMU_DUMMY_MAP(SetSoftMinJpeg), \
+ __SMU_DUMMY_MAP(SetHardMinFclkByFreq), \
+
+#undef __SMU_DUMMY_MAP
+#define __SMU_DUMMY_MAP(type) SMU_MSG_##type
+enum smu_message_type {
+ SMU_MESSAGE_TYPES
+ SMU_MSG_MAX_COUNT,
+};
+
+enum smu_clk_type {
+ SMU_GFXCLK,
+ SMU_VCLK,
+ SMU_DCLK,
+ SMU_ECLK,
+ SMU_SOCCLK,
+ SMU_UCLK,
+ SMU_DCEFCLK,
+ SMU_DISPCLK,
+ SMU_PIXCLK,
+ SMU_PHYCLK,
+ SMU_FCLK,
+ SMU_SCLK,
+ SMU_MCLK,
+ SMU_PCIE,
+ SMU_OD_SCLK,
+ SMU_OD_MCLK,
+ SMU_OD_VDDC_CURVE,
+ SMU_OD_RANGE,
+ SMU_CLK_COUNT,
+};
+
+#define SMU_FEATURE_MASKS \
+ __SMU_DUMMY_MAP(DPM_PREFETCHER), \
+ __SMU_DUMMY_MAP(DPM_GFXCLK), \
+ __SMU_DUMMY_MAP(DPM_UCLK), \
+ __SMU_DUMMY_MAP(DPM_SOCCLK), \
+ __SMU_DUMMY_MAP(DPM_UVD), \
+ __SMU_DUMMY_MAP(DPM_VCE), \
+ __SMU_DUMMY_MAP(ULV), \
+ __SMU_DUMMY_MAP(DPM_MP0CLK), \
+ __SMU_DUMMY_MAP(DPM_LINK), \
+ __SMU_DUMMY_MAP(DPM_DCEFCLK), \
+ __SMU_DUMMY_MAP(DS_GFXCLK), \
+ __SMU_DUMMY_MAP(DS_SOCCLK), \
+ __SMU_DUMMY_MAP(DS_LCLK), \
+ __SMU_DUMMY_MAP(PPT), \
+ __SMU_DUMMY_MAP(TDC), \
+ __SMU_DUMMY_MAP(THERMAL), \
+ __SMU_DUMMY_MAP(GFX_PER_CU_CG), \
+ __SMU_DUMMY_MAP(RM), \
+ __SMU_DUMMY_MAP(DS_DCEFCLK), \
+ __SMU_DUMMY_MAP(ACDC), \
+ __SMU_DUMMY_MAP(VR0HOT), \
+ __SMU_DUMMY_MAP(VR1HOT), \
+ __SMU_DUMMY_MAP(FW_CTF), \
+ __SMU_DUMMY_MAP(LED_DISPLAY), \
+ __SMU_DUMMY_MAP(FAN_CONTROL), \
+ __SMU_DUMMY_MAP(GFX_EDC), \
+ __SMU_DUMMY_MAP(GFXOFF), \
+ __SMU_DUMMY_MAP(CG), \
+ __SMU_DUMMY_MAP(DPM_FCLK), \
+ __SMU_DUMMY_MAP(DS_FCLK), \
+ __SMU_DUMMY_MAP(DS_MP1CLK), \
+ __SMU_DUMMY_MAP(DS_MP0CLK), \
+ __SMU_DUMMY_MAP(XGMI), \
+ __SMU_DUMMY_MAP(DPM_GFX_PACE), \
+ __SMU_DUMMY_MAP(MEM_VDDCI_SCALING), \
+ __SMU_DUMMY_MAP(MEM_MVDD_SCALING), \
+ __SMU_DUMMY_MAP(DS_UCLK), \
+ __SMU_DUMMY_MAP(GFX_ULV), \
+ __SMU_DUMMY_MAP(FW_DSTATE), \
+ __SMU_DUMMY_MAP(BACO), \
+ __SMU_DUMMY_MAP(VCN_PG), \
+ __SMU_DUMMY_MAP(JPEG_PG), \
+ __SMU_DUMMY_MAP(USB_PG), \
+ __SMU_DUMMY_MAP(RSMU_SMN_CG), \
+ __SMU_DUMMY_MAP(APCC_PLUS), \
+ __SMU_DUMMY_MAP(GTHR), \
+ __SMU_DUMMY_MAP(GFX_DCS), \
+ __SMU_DUMMY_MAP(GFX_SS), \
+ __SMU_DUMMY_MAP(OUT_OF_BAND_MONITOR), \
+ __SMU_DUMMY_MAP(TEMP_DEPENDENT_VMIN), \
+ __SMU_DUMMY_MAP(MMHUB_PG), \
+ __SMU_DUMMY_MAP(ATHUB_PG), \
+ __SMU_DUMMY_MAP(WAFL_CG),
+
+#undef __SMU_DUMMY_MAP
+#define __SMU_DUMMY_MAP(feature) SMU_FEATURE_##feature##_BIT
+enum smu_feature_mask {
+ SMU_FEATURE_MASKS
+ SMU_FEATURE_COUNT,
+};
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 2fff4b16cb4e..5bda8539447a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -25,6 +25,12 @@
#include "amdgpu_smu.h"
+#define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
+#define SMU11_DRIVER_IF_VERSION_VG20 0x13
+#define SMU11_DRIVER_IF_VERSION_ARCT 0x09
+#define SMU11_DRIVER_IF_VERSION_NV10 0x33
+#define SMU11_DRIVER_IF_VERSION_NV14 0x34
+
/* MP Apertures */
#define MP0_Public 0x03800000
#define MP0_SRAM 0x03900000
@@ -43,19 +49,30 @@
#define SMU11_TOOL_SIZE 0x19000
#define CLK_MAP(clk, index) \
- [SMU_##clk] = index
+ [SMU_##clk] = {1, (index)}
#define FEA_MAP(fea) \
- [SMU_FEATURE_##fea##_BIT] = FEATURE_##fea##_BIT
+ [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}
#define TAB_MAP(tab) \
- [SMU_TABLE_##tab] = TABLE_##tab
+ [SMU_TABLE_##tab] = {1, TABLE_##tab}
#define PWR_MAP(tab) \
- [SMU_POWER_SOURCE_##tab] = POWER_SOURCE_##tab
+ [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}
#define WORKLOAD_MAP(profile, workload) \
- [profile] = workload
+ [profile] = {1, (workload)}
+
+static const struct smu_temperature_range smu11_thermal_policy[] =
+{
+ {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
+ { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
+};
+
+struct smu_11_0_cmn2aisc_mapping {
+ int valid_mapping;
+ int map_to;
+};
struct smu_11_0_max_sustainable_clocks {
uint32_t display_clock;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
new file mode 100644
index 000000000000..acf3db12f59f
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __SMU_V12_0_H__
+#define __SMU_V12_0_H__
+
+#include "amdgpu_smu.h"
+
+/* MP Apertures */
+#define MP0_Public 0x03800000
+#define MP0_SRAM 0x03900000
+#define MP1_Public 0x03b00000
+#define MP1_SRAM 0x03c00004
+
+
+struct smu_12_0_cmn2aisc_mapping {
+ int valid_mapping;
+ int map_to;
+};
+
+void smu_v12_0_set_smu_funcs(struct smu_context *smu);
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h
new file mode 100644
index 000000000000..9ac9f3bd3664
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef SMU_12_0_PPSMC_H
+#define SMU_12_0_PPSMC_H
+
+// SMU Response Codes:
+#define PPSMC_Result_OK 0x1
+#define PPSMC_Result_Failed 0xFF
+#define PPSMC_Result_UnknownCmd 0xFE
+#define PPSMC_Result_CmdRejectedPrereq 0xFD
+#define PPSMC_Result_CmdRejectedBusy 0xFC
+
+
+// Message Definitions:
+#define PPSMC_MSG_TestMessage 0x1
+#define PPSMC_MSG_GetSmuVersion 0x2
+#define PPSMC_MSG_GetDriverIfVersion 0x3
+#define PPSMC_MSG_PowerUpGfx 0x6
+#define PPSMC_MSG_EnableGfxOff 0x7
+#define PPSMC_MSG_DisableGfxOff 0x8
+#define PPSMC_MSG_PowerDownIspByTile 0x9 // ISP is power gated by default
+#define PPSMC_MSG_PowerUpIspByTile 0xA
+#define PPSMC_MSG_PowerDownVcn 0xB // VCN is power gated by default
+#define PPSMC_MSG_PowerUpVcn 0xC
+#define PPSMC_MSG_PowerDownSdma 0xD // SDMA is power gated by default
+#define PPSMC_MSG_PowerUpSdma 0xE
+#define PPSMC_MSG_SetHardMinIspclkByFreq 0xF
+#define PPSMC_MSG_SetHardMinVcn 0x10 // For wireless display
+#define PPSMC_MSG_spare1 0x11
+#define PPSMC_MSG_spare2 0x12
+#define PPSMC_MSG_SetAllowFclkSwitch 0x13
+#define PPSMC_MSG_SetMinVideoGfxclkFreq 0x14
+#define PPSMC_MSG_ActiveProcessNotify 0x15
+#define PPSMC_MSG_SetCustomPolicy 0x16
+#define PPSMC_MSG_SetVideoFps 0x17
+#define PPSMC_MSG_SetDisplayCount 0x18 // Moved to VBIOS
+#define PPSMC_MSG_QueryPowerLimit 0x19 //Driver to look up sustainable clocks for VQ
+#define PPSMC_MSG_SetDriverDramAddrHigh 0x1A
+#define PPSMC_MSG_SetDriverDramAddrLow 0x1B
+#define PPSMC_MSG_TransferTableSmu2Dram 0x1C
+#define PPSMC_MSG_TransferTableDram2Smu 0x1D
+#define PPSMC_MSG_GfxDeviceDriverReset 0x1E
+#define PPSMC_MSG_SetGfxclkOverdriveByFreqVid 0x1F
+#define PPSMC_MSG_SetHardMinDcfclkByFreq 0x20 // Moved to VBIOS
+#define PPSMC_MSG_SetHardMinSocclkByFreq 0x21
+#define PPSMC_MSG_ControlIgpuATS 0x22
+#define PPSMC_MSG_SetMinVideoFclkFreq 0x23
+#define PPSMC_MSG_SetMinDeepSleepDcfclk 0x24 // Moved to VBIOS
+#define PPSMC_MSG_ForcePowerDownGfx 0x25
+#define PPSMC_MSG_SetPhyclkVoltageByFreq 0x26 // Moved to VBIOS
+#define PPSMC_MSG_SetDppclkVoltageByFreq 0x27 // Moved to VBIOS and is SetDppclkFreq
+#define PPSMC_MSG_SetSoftMinVcn 0x28
+#define PPSMC_MSG_EnablePostCode 0x29
+#define PPSMC_MSG_GetGfxclkFrequency 0x2A
+#define PPSMC_MSG_GetFclkFrequency 0x2B
+#define PPSMC_MSG_GetMinGfxclkFrequency 0x2C
+#define PPSMC_MSG_GetMaxGfxclkFrequency 0x2D
+#define PPSMC_MSG_SoftReset 0x2E // Not supported
+#define PPSMC_MSG_SetGfxCGPG 0x2F
+#define PPSMC_MSG_SetSoftMaxGfxClk 0x30
+#define PPSMC_MSG_SetHardMinGfxClk 0x31
+#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x32
+#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x33
+#define PPSMC_MSG_SetSoftMaxVcn 0x34
+#define PPSMC_MSG_PowerGateMmHub 0x35
+#define PPSMC_MSG_UpdatePmeRestore 0x36 // Moved to VBIOS
+#define PPSMC_MSG_GpuChangeState 0x37
+#define PPSMC_MSG_SetPowerLimitPercentage 0x38
+#define PPSMC_MSG_ForceGfxContentSave 0x39
+#define PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0x3A // Moved to VBIOS
+#define PPSMC_MSG_PowerDownJpeg 0x3B
+#define PPSMC_MSG_PowerUpJpeg 0x3C
+#define PPSMC_MSG_PowerGateAtHub 0x3D
+#define PPSMC_MSG_SetSoftMinJpeg 0x3E
+#define PPSMC_MSG_SetHardMinFclkByFreq 0x3F
+#define PPSMC_Message_Count 0x40
+
+
+//Argument for PPSMC_MSG_GpuChangeState
+enum {
+ eGpuChangeState_D0Entry = 1,
+ eGpuChangeState_D3Entry,
+};
+
+#endif
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.