diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dpll_mgr.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 677 |
1 files changed, 361 insertions, 316 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index c75e34d87111..e5bfe5245276 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -103,8 +103,8 @@ enum intel_dpll_id intel_get_shared_dpll_id(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) { - if (WARN_ON(pll < dev_priv->shared_dplls|| - pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll])) + if (drm_WARN_ON(&dev_priv->drm, pll < dev_priv->shared_dplls || + pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll])) return -1; return (enum intel_dpll_id) (pll - dev_priv->shared_dplls); @@ -118,7 +118,8 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv, bool cur_state; struct intel_dpll_hw_state hw_state; - if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state))) + if (drm_WARN(&dev_priv->drm, !pll, + "asserting DPLL %s with no DPLL\n", onoff(state))) return; cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state); @@ -140,14 +141,14 @@ void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_shared_dpll *pll = crtc_state->shared_dpll; - if (WARN_ON(pll == NULL)) + if (drm_WARN_ON(&dev_priv->drm, pll == NULL)) return; mutex_lock(&dev_priv->dpll_lock); - WARN_ON(!pll->state.crtc_mask); + drm_WARN_ON(&dev_priv->drm, !pll->state.crtc_mask); if (!pll->active_mask) { - DRM_DEBUG_DRIVER("setting up %s\n", pll->info->name); - WARN_ON(pll->on); + drm_dbg(&dev_priv->drm, "setting up %s\n", pll->info->name); + drm_WARN_ON(&dev_priv->drm, pll->on); assert_shared_dpll_disabled(dev_priv, pll); pll->info->funcs->prepare(dev_priv, pll); @@ -169,30 +170,31 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) unsigned int crtc_mask = drm_crtc_mask(&crtc->base); unsigned int old_mask; - if (WARN_ON(pll == NULL)) + if (drm_WARN_ON(&dev_priv->drm, pll == NULL)) return; mutex_lock(&dev_priv->dpll_lock); old_mask = pll->active_mask; - if (WARN_ON(!(pll->state.crtc_mask & crtc_mask)) || - WARN_ON(pll->active_mask & crtc_mask)) + if (drm_WARN_ON(&dev_priv->drm, !(pll->state.crtc_mask & crtc_mask)) || + drm_WARN_ON(&dev_priv->drm, pll->active_mask & crtc_mask)) goto out; pll->active_mask |= crtc_mask; - DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n", - pll->info->name, pll->active_mask, pll->on, - crtc->base.base.id); + drm_dbg_kms(&dev_priv->drm, + "enable %s (active %x, on? %d) for crtc %d\n", + pll->info->name, pll->active_mask, pll->on, + crtc->base.base.id); if (old_mask) { - WARN_ON(!pll->on); + drm_WARN_ON(&dev_priv->drm, !pll->on); assert_shared_dpll_enabled(dev_priv, pll); goto out; } - WARN_ON(pll->on); + drm_WARN_ON(&dev_priv->drm, pll->on); - DRM_DEBUG_KMS("enabling %s\n", pll->info->name); + drm_dbg_kms(&dev_priv->drm, "enabling %s\n", pll->info->name); pll->info->funcs->enable(dev_priv, pll); pll->on = true; @@ -221,21 +223,22 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) return; mutex_lock(&dev_priv->dpll_lock); - if (WARN_ON(!(pll->active_mask & crtc_mask))) + if (drm_WARN_ON(&dev_priv->drm, !(pll->active_mask & crtc_mask))) goto out; - DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n", - pll->info->name, pll->active_mask, pll->on, - crtc->base.base.id); + drm_dbg_kms(&dev_priv->drm, + "disable %s (active %x, on? %d) for crtc %d\n", + pll->info->name, pll->active_mask, pll->on, + crtc->base.base.id); assert_shared_dpll_enabled(dev_priv, pll); - WARN_ON(!pll->on); + drm_WARN_ON(&dev_priv->drm, !pll->on); pll->active_mask &= ~crtc_mask; if (pll->active_mask) goto out; - DRM_DEBUG_KMS("disabling %s\n", pll->info->name); + drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name); pll->info->funcs->disable(dev_priv, pll); pll->on = false; @@ -256,7 +259,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state, shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); - WARN_ON(dpll_mask & ~(BIT(I915_NUM_PLLS) - 1)); + drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1)); for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) { pll = &dev_priv->shared_dplls[i]; @@ -271,20 +274,21 @@ intel_find_shared_dpll(struct intel_atomic_state *state, if (memcmp(pll_state, &shared_dpll[i].hw_state, sizeof(*pll_state)) == 0) { - DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n", - crtc->base.base.id, crtc->base.name, - pll->info->name, - shared_dpll[i].crtc_mask, - pll->active_mask); + drm_dbg_kms(&dev_priv->drm, + "[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n", + crtc->base.base.id, crtc->base.name, + pll->info->name, + shared_dpll[i].crtc_mask, + pll->active_mask); return pll; } } /* Ok no matching timings, maybe there's a free one? */ if (unused_pll) { - DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n", - crtc->base.base.id, crtc->base.name, - unused_pll->info->name); + drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] allocated %s\n", + crtc->base.base.id, crtc->base.name, + unused_pll->info->name); return unused_pll; } @@ -297,6 +301,7 @@ intel_reference_shared_dpll(struct intel_atomic_state *state, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) { + struct drm_i915_private *i915 = to_i915(state->base.dev); struct intel_shared_dpll_state *shared_dpll; const enum intel_dpll_id id = pll->info->id; @@ -305,8 +310,8 @@ intel_reference_shared_dpll(struct intel_atomic_state *state, if (shared_dpll[id].crtc_mask == 0) shared_dpll[id].hw_state = *pll_state; - DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->info->name, - pipe_name(crtc->pipe)); + drm_dbg(&i915->drm, "using %s for pipe %c\n", pll->info->name, + pipe_name(crtc->pipe)); shared_dpll[id].crtc_mask |= 1 << crtc->pipe; } @@ -378,10 +383,10 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, if (!wakeref) return false; - val = I915_READ(PCH_DPLL(id)); + val = intel_de_read(dev_priv, PCH_DPLL(id)); hw_state->dpll = val; - hw_state->fp0 = I915_READ(PCH_FP0(id)); - hw_state->fp1 = I915_READ(PCH_FP1(id)); + hw_state->fp0 = intel_de_read(dev_priv, PCH_FP0(id)); + hw_state->fp1 = intel_de_read(dev_priv, PCH_FP1(id)); intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); @@ -393,8 +398,8 @@ static void ibx_pch_dpll_prepare(struct drm_i915_private *dev_priv, { const enum intel_dpll_id id = pll->info->id; - I915_WRITE(PCH_FP0(id), pll->state.hw_state.fp0); - I915_WRITE(PCH_FP1(id), pll->state.hw_state.fp1); + intel_de_write(dev_priv, PCH_FP0(id), pll->state.hw_state.fp0); + intel_de_write(dev_priv, PCH_FP1(id), pll->state.hw_state.fp1); } static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) @@ -404,7 +409,7 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); - val = I915_READ(PCH_DREF_CONTROL); + val = intel_de_read(dev_priv, PCH_DREF_CONTROL); enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | DREF_SUPERSPREAD_SOURCE_MASK)); I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); @@ -418,10 +423,10 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, /* PCH refclock must be enabled first */ ibx_assert_pch_refclk_enabled(dev_priv); - I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll); + intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); /* Wait for the clocks to stabilize. */ - POSTING_READ(PCH_DPLL(id)); + intel_de_posting_read(dev_priv, PCH_DPLL(id)); udelay(150); /* The pixel multiplier can only be updated once the @@ -429,8 +434,8 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, * * So write it again. */ - I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll); - POSTING_READ(PCH_DPLL(id)); + intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); + intel_de_posting_read(dev_priv, PCH_DPLL(id)); udelay(200); } @@ -439,8 +444,8 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, { const enum intel_dpll_id id = pll->info->id; - I915_WRITE(PCH_DPLL(id), 0); - POSTING_READ(PCH_DPLL(id)); + intel_de_write(dev_priv, PCH_DPLL(id), 0); + intel_de_posting_read(dev_priv, PCH_DPLL(id)); udelay(200); } @@ -459,9 +464,10 @@ static bool ibx_get_dpll(struct intel_atomic_state *state, i = (enum intel_dpll_id) crtc->pipe; pll = &dev_priv->shared_dplls[i]; - DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n", - crtc->base.base.id, crtc->base.name, - pll->info->name); + drm_dbg_kms(&dev_priv->drm, + "[CRTC:%d:%s] using pre-allocated %s\n", + crtc->base.base.id, crtc->base.name, + pll->info->name); } else { pll = intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state, @@ -484,12 +490,13 @@ static bool ibx_get_dpll(struct intel_atomic_state *state, static void ibx_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " - "fp0: 0x%x, fp1: 0x%x\n", - hw_state->dpll, - hw_state->dpll_md, - hw_state->fp0, - hw_state->fp1); + drm_dbg_kms(&dev_priv->drm, + "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " + "fp0: 0x%x, fp1: 0x%x\n", + hw_state->dpll, + hw_state->dpll_md, + hw_state->fp0, + hw_state->fp1); } static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = { @@ -504,16 +511,16 @@ static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv, { const enum intel_dpll_id id = pll->info->id; - I915_WRITE(WRPLL_CTL(id), pll->state.hw_state.wrpll); - POSTING_READ(WRPLL_CTL(id)); + intel_de_write(dev_priv, WRPLL_CTL(id), pll->state.hw_state.wrpll); + intel_de_posting_read(dev_priv, WRPLL_CTL(id)); udelay(20); } static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) { - I915_WRITE(SPLL_CTL, pll->state.hw_state.spll); - POSTING_READ(SPLL_CTL); + intel_de_write(dev_priv, SPLL_CTL, pll->state.hw_state.spll); + intel_de_posting_read(dev_priv, SPLL_CTL); udelay(20); } @@ -523,9 +530,9 @@ static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, const enum intel_dpll_id id = pll->info->id; u32 val; - val = I915_READ(WRPLL_CTL(id)); - I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE); - POSTING_READ(WRPLL_CTL(id)); + val = intel_de_read(dev_priv, WRPLL_CTL(id)); + intel_de_write(dev_priv, WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE); + intel_de_posting_read(dev_priv, WRPLL_CTL(id)); /* * Try to set up the PCH reference clock once all DPLLs @@ -541,9 +548,9 @@ static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, enum intel_dpll_id id = pll->info->id; u32 val; - val = I915_READ(SPLL_CTL); - I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); - POSTING_READ(SPLL_CTL); + val = intel_de_read(dev_priv, SPLL_CTL); + intel_de_write(dev_priv, SPLL_CTL, val & ~SPLL_PLL_ENABLE); + intel_de_posting_read(dev_priv, SPLL_CTL); /* * Try to set up the PCH reference clock once all DPLLs @@ -566,7 +573,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, if (!wakeref) return false; - val = I915_READ(WRPLL_CTL(id)); + val = intel_de_read(dev_priv, WRPLL_CTL(id)); hw_state->wrpll = val; intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); @@ -586,7 +593,7 @@ static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, if (!wakeref) return false; - val = I915_READ(SPLL_CTL); + val = intel_de_read(dev_priv, SPLL_CTL); hw_state->spll = val; intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); @@ -858,7 +865,8 @@ hsw_ddi_dp_get_dpll(struct intel_crtc_state *crtc_state) pll_id = DPLL_ID_LCPLL_2700; break; default: - DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock); + drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n", + clock); return NULL; } @@ -913,8 +921,8 @@ static bool hsw_get_dpll(struct intel_atomic_state *state, static void hsw_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", - hw_state->wrpll, hw_state->spll); + drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", + hw_state->wrpll, hw_state->spll); } static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = { @@ -989,15 +997,15 @@ static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv, const enum intel_dpll_id id = pll->info->id; u32 val; - val = I915_READ(DPLL_CTRL1); + val = intel_de_read(dev_priv, DPLL_CTRL1); val &= ~(DPLL_CTRL1_HDMI_MODE(id) | DPLL_CTRL1_SSC(id) | DPLL_CTRL1_LINK_RATE_MASK(id)); val |= pll->state.hw_state.ctrl1 << (id * 6); - I915_WRITE(DPLL_CTRL1, val); - POSTING_READ(DPLL_CTRL1); + intel_de_write(dev_priv, DPLL_CTRL1, val); + intel_de_posting_read(dev_priv, DPLL_CTRL1); } static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, @@ -1008,17 +1016,17 @@ static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, skl_ddi_pll_write_ctrl1(dev_priv, pll); - I915_WRITE(regs[id].cfgcr1, pll->state.hw_state.cfgcr1); - I915_WRITE(regs[id].cfgcr2, pll->state.hw_state.cfgcr2); - POSTING_READ(regs[id].cfgcr1); - POSTING_READ(regs[id].cfgcr2); + intel_de_write(dev_priv, regs[id].cfgcr1, pll->state.hw_state.cfgcr1); + intel_de_write(dev_priv, regs[id].cfgcr2, pll->state.hw_state.cfgcr2); + intel_de_posting_read(dev_priv, regs[id].cfgcr1); + intel_de_posting_read(dev_priv, regs[id].cfgcr2); /* the enable bit is always bit 31 */ - I915_WRITE(regs[id].ctl, - I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE); + intel_de_write(dev_priv, regs[id].ctl, + intel_de_read(dev_priv, regs[id].ctl) | LCPLL_PLL_ENABLE); if (intel_de_wait_for_set(dev_priv, DPLL_STATUS, DPLL_LOCK(id), 5)) - DRM_ERROR("DPLL %d not locked\n", id); + drm_err(&dev_priv->drm, "DPLL %d not locked\n", id); } static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv, @@ -1034,9 +1042,9 @@ static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, const enum intel_dpll_id id = pll->info->id; /* the enable bit is always bit 31 */ - I915_WRITE(regs[id].ctl, - I915_READ(regs[id].ctl) & ~LCPLL_PLL_ENABLE); - POSTING_READ(regs[id].ctl); + intel_de_write(dev_priv, regs[id].ctl, + intel_de_read(dev_priv, regs[id].ctl) & ~LCPLL_PLL_ENABLE); + intel_de_posting_read(dev_priv, regs[id].ctl); } static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv, @@ -1061,17 +1069,17 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, ret = false; - val = I915_READ(regs[id].ctl); + val = intel_de_read(dev_priv, regs[id].ctl); if (!(val & LCPLL_PLL_ENABLE)) goto out; - val = I915_READ(DPLL_CTRL1); + val = intel_de_read(dev_priv, DPLL_CTRL1); hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; /* avoid reading back stale values if HDMI mode is not enabled */ if (val & DPLL_CTRL1_HDMI_MODE(id)) { - hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1); - hw_state->cfgcr2 = I915_READ(regs[id].cfgcr2); + hw_state->cfgcr1 = intel_de_read(dev_priv, regs[id].cfgcr1); + hw_state->cfgcr2 = intel_de_read(dev_priv, regs[id].cfgcr2); } ret = true; @@ -1099,11 +1107,11 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv, ret = false; /* DPLL0 is always enabled since it drives CDCLK */ - val = I915_READ(regs[id].ctl); - if (WARN_ON(!(val & LCPLL_PLL_ENABLE))) + val = intel_de_read(dev_priv, regs[id].ctl); + if (drm_WARN_ON(&dev_priv->drm, !(val & LCPLL_PLL_ENABLE))) goto out; - val = I915_READ(DPLL_CTRL1); + val = intel_de_read(dev_priv, DPLL_CTRL1); hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; ret = true; @@ -1442,19 +1450,22 @@ static bool skl_get_dpll(struct intel_atomic_state *state, { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_shared_dpll *pll; bool bret; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { bret = skl_ddi_hdmi_pll_dividers(crtc_state); if (!bret) { - DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n"); + drm_dbg_kms(&i915->drm, + "Could not get HDMI pll dividers.\n"); return false; } } else if (intel_crtc_has_dp_encoder(crtc_state)) { bret = skl_ddi_dp_set_dpll_hw_state(crtc_state); if (!bret) { - DRM_DEBUG_KMS("Could not set DP dpll HW state.\n"); + drm_dbg_kms(&i915->drm, + "Could not set DP dpll HW state.\n"); return false; } } else { @@ -1485,7 +1496,7 @@ static bool skl_get_dpll(struct intel_atomic_state *state, static void skl_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - DRM_DEBUG_KMS("dpll_hw_state: " + drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: " "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", hw_state->ctrl1, hw_state->cfgcr1, @@ -1515,113 +1526,114 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); /* Non-SSC reference */ - temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); temp |= PORT_PLL_REF_SEL; - I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); + intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port), temp); if (IS_GEMINILAKE(dev_priv)) { - temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); temp |= PORT_PLL_POWER_ENABLE; - I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); + intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port), temp); - if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & + if (wait_for_us((intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_POWER_STATE), 200)) - DRM_ERROR("Power state not set for PLL:%d\n", port); + drm_err(&dev_priv->drm, + "Power state not set for PLL:%d\n", port); } /* Disable 10 bit clock */ - temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch)); temp &= ~PORT_PLL_10BIT_CLK_ENABLE; - I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp); + intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), temp); /* Write P1 & P2 */ - temp = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch)); temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); temp |= pll->state.hw_state.ebb0; - I915_WRITE(BXT_PORT_PLL_EBB_0(phy, ch), temp); + intel_de_write(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch), temp); /* Write M2 integer */ - temp = I915_READ(BXT_PORT_PLL(phy, ch, 0)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0)); temp &= ~PORT_PLL_M2_MASK; temp |= pll->state.hw_state.pll0; - I915_WRITE(BXT_PORT_PLL(phy, ch, 0), temp); + intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 0), temp); /* Write N */ - temp = I915_READ(BXT_PORT_PLL(phy, ch, 1)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 1)); temp &= ~PORT_PLL_N_MASK; temp |= pll->state.hw_state.pll1; - I915_WRITE(BXT_PORT_PLL(phy, ch, 1), temp); + intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 1), temp); /* Write M2 fraction */ - temp = I915_READ(BXT_PORT_PLL(phy, ch, 2)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 2)); temp &= ~PORT_PLL_M2_FRAC_MASK; temp |= pll->state.hw_state.pll2; - I915_WRITE(BXT_PORT_PLL(phy, ch, 2), temp); + intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 2), temp); /* Write M2 fraction enable */ - temp = I915_READ(BXT_PORT_PLL(phy, ch, 3)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 3)); temp &= ~PORT_PLL_M2_FRAC_ENABLE; temp |= pll->state.hw_state.pll3; - I915_WRITE(BXT_PORT_PLL(phy, ch, 3), temp); + intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 3), temp); /* Write coeff */ - temp = I915_READ(BXT_PORT_PLL(phy, ch, 6)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 6)); temp &= ~PORT_PLL_PROP_COEFF_MASK; temp &= ~PORT_PLL_INT_COEFF_MASK; temp &= ~PORT_PLL_GAIN_CTL_MASK; temp |= pll->state.hw_state.pll6; - I915_WRITE(BXT_PORT_PLL(phy, ch, 6), temp); + intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 6), temp); /* Write calibration val */ - temp = I915_READ(BXT_PORT_PLL(phy, ch, 8)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 8)); temp &= ~PORT_PLL_TARGET_CNT_MASK; temp |= pll->state.hw_state.pll8; - I915_WRITE(BXT_PORT_PLL(phy, ch, 8), temp); + intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 8), temp); - temp = I915_READ(BXT_PORT_PLL(phy, ch, 9)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 9)); temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK; temp |= pll->state.hw_state.pll9; - I915_WRITE(BXT_PORT_PLL(phy, ch, 9), temp); + intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 9), temp); - temp = I915_READ(BXT_PORT_PLL(phy, ch, 10)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 10)); temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; temp &= ~PORT_PLL_DCO_AMP_MASK; temp |= pll->state.hw_state.pll10; - I915_WRITE(BXT_PORT_PLL(phy, ch, 10), temp); + intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 10), temp); /* Recalibrate with new settings */ - temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch)); temp |= PORT_PLL_RECALIBRATE; - I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp); + intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), temp); temp &= ~PORT_PLL_10BIT_CLK_ENABLE; temp |= pll->state.hw_state.ebb4; - I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp); + intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), temp); /* Enable PLL */ - temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); temp |= PORT_PLL_ENABLE; - I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); - POSTING_READ(BXT_PORT_PLL_ENABLE(port)); + intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port), temp); + intel_de_posting_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); - if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK), + if (wait_for_us((intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK), 200)) - DRM_ERROR("PLL %d not locked\n", port); + drm_err(&dev_priv->drm, "PLL %d not locked\n", port); if (IS_GEMINILAKE(dev_priv)) { - temp = I915_READ(BXT_PORT_TX_DW5_LN0(phy, ch)); + temp = intel_de_read(dev_priv, BXT_PORT_TX_DW5_LN0(phy, ch)); temp |= DCC_DELAY_RANGE_2; - I915_WRITE(BXT_PORT_TX_DW5_GRP(phy, ch), temp); + intel_de_write(dev_priv, BXT_PORT_TX_DW5_GRP(phy, ch), temp); } /* * While we write to the group register to program all lanes at once we * can read only lane registers and we pick lanes 0/1 for that. */ - temp = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch)); + temp = intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN01(phy, ch)); temp &= ~LANE_STAGGER_MASK; temp &= ~LANESTAGGER_STRAP_OVRD; temp |= pll->state.hw_state.pcsdw12; - I915_WRITE(BXT_PORT_PCS_DW12_GRP(phy, ch), temp); + intel_de_write(dev_priv, BXT_PORT_PCS_DW12_GRP(phy, ch), temp); } static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, @@ -1630,19 +1642,20 @@ static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ u32 temp; - temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); temp &= ~PORT_PLL_ENABLE; - I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); - POSTING_READ(BXT_PORT_PLL_ENABLE(port)); + intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port), temp); + intel_de_posting_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); if (IS_GEMINILAKE(dev_priv)) { - temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); temp &= ~PORT_PLL_POWER_ENABLE; - I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); + intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port), temp); - if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) & - PORT_PLL_POWER_STATE), 200)) - DRM_ERROR("Power state not reset for PLL:%d\n", port); + if (wait_for_us(!(intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & + PORT_PLL_POWER_STATE), 200)) + drm_err(&dev_priv->drm, + "Power state not reset for PLL:%d\n", port); } } @@ -1666,40 +1679,40 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, ret = false; - val = I915_READ(BXT_PORT_PLL_ENABLE(port)); + val = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); if (!(val & PORT_PLL_ENABLE)) goto out; - hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch)); + hw_state->ebb0 = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch)); hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; - hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch)); + hw_state->ebb4 = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch)); hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; - hw_state->pll0 = I915_READ(BXT_PORT_PLL(phy, ch, 0)); + hw_state->pll0 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0)); hw_state->pll0 &= PORT_PLL_M2_MASK; - hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1)); + hw_state->pll1 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 1)); hw_state->pll1 &= PORT_PLL_N_MASK; - hw_state->pll2 = I915_READ(BXT_PORT_PLL(phy, ch, 2)); + hw_state->pll2 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 2)); hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; - hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3)); + hw_state->pll3 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 3)); hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; - hw_state->pll6 = I915_READ(BXT_PORT_PLL(phy, ch, 6)); + hw_state->pll6 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 6)); hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | PORT_PLL_INT_COEFF_MASK | PORT_PLL_GAIN_CTL_MASK; - hw_state->pll8 = I915_READ(BXT_PORT_PLL(phy, ch, 8)); + hw_state->pll8 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 8)); hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; - hw_state->pll9 = I915_READ(BXT_PORT_PLL(phy, ch, 9)); + hw_state->pll9 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 9)); hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; - hw_state->pll10 = I915_READ(BXT_PORT_PLL(phy, ch, 10)); + hw_state->pll10 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 10)); hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | PORT_PLL_DCO_AMP_MASK; @@ -1708,11 +1721,14 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, * can read only lane registers. We configure all lanes the same way, so * here just read out lanes 0/1 and output a note if lanes 2/3 differ. */ - hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch)); - if (I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) - DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", - hw_state->pcsdw12, - I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch))); + hw_state->pcsdw12 = intel_de_read(dev_priv, + BXT_PORT_PCS_DW12_LN01(phy, ch)); + if (intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) + drm_dbg(&dev_priv->drm, + "lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", + hw_state->pcsdw12, + intel_de_read(dev_priv, + BXT_PORT_PCS_DW12_LN23(phy, ch))); hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; ret = true; @@ -1751,6 +1767,7 @@ static bool bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state, struct bxt_clk_div *clk_div) { + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct dpll best_clock; @@ -1760,9 +1777,9 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state, * i9xx_crtc_compute_clock */ if (!bxt_find_best_dpll(crtc_state, &best_clock)) { - DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n", - crtc_state->port_clock, - pipe_name(crtc->pipe)); + drm_dbg(&i915->drm, "no PLL dividers found for clock %d pipe %c\n", + crtc_state->port_clock, + pipe_name(crtc->pipe)); return false; } @@ -1799,6 +1816,7 @@ static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state, static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state, const struct bxt_clk_div *clk_div) { + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state; int clock = crtc_state->port_clock; int vco = clk_div->vco; @@ -1824,7 +1842,7 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state, gain_ctl = 1; targ_cnt = 9; } else { - DRM_ERROR("Invalid VCO\n"); + drm_err(&i915->drm, "Invalid VCO\n"); return false; } @@ -1907,8 +1925,8 @@ static bool bxt_get_dpll(struct intel_atomic_state *state, id = (enum intel_dpll_id) encoder->port; pll = intel_get_shared_dpll_by_id(dev_priv, id); - DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n", - crtc->base.base.id, crtc->base.name, pll->info->name); + drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] using pre-allocated %s\n", + crtc->base.base.id, crtc->base.name, pll->info->name); intel_reference_shared_dpll(state, crtc, pll, &crtc_state->dpll_hw_state); @@ -1921,20 +1939,20 @@ static bool bxt_get_dpll(struct intel_atomic_state *state, static void bxt_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," - "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " - "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", - hw_state->ebb0, - hw_state->ebb4, - hw_state->pll0, - hw_state->pll1, - hw_state->pll2, - hw_state->pll3, - hw_state->pll6, - hw_state->pll8, - hw_state->pll9, - hw_state->pll10, - hw_state->pcsdw12); + drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," + "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " + "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", + hw_state->ebb0, + hw_state->ebb4, + hw_state->pll0, + hw_state->pll1, + hw_state->pll2, + hw_state->pll3, + hw_state->pll6, + hw_state->pll8, + hw_state->pll9, + hw_state->pll10, + hw_state->pcsdw12); } static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = { @@ -2024,32 +2042,32 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv, u32 val; /* 1. Enable DPLL power in DPLL_ENABLE. */ - val = I915_READ(CNL_DPLL_ENABLE(id)); + val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id)); val |= PLL_POWER_ENABLE; - I915_WRITE(CNL_DPLL_ENABLE(id), val); + intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val); /* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */ if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), PLL_POWER_STATE, 5)) - DRM_ERROR("PLL %d Power not enabled\n", id); + drm_err(&dev_priv->drm, "PLL %d Power not enabled\n", id); /* * 3. Configure DPLL_CFGCR0 to set SSC enable/disable, * select DP mode, and set DP link rate. */ val = pll->state.hw_state.cfgcr0; - I915_WRITE(CNL_DPLL_CFGCR0(id), val); + intel_de_write(dev_priv, CNL_DPLL_CFGCR0(id), val); /* 4. Reab back to ensure writes completed */ - POSTING_READ(CNL_DPLL_CFGCR0(id)); + intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR0(id)); /* 3. Configure DPLL_CFGCR0 */ /* Avoid touch CFGCR1 if HDMI mode is not enabled */ if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { val = pll->state.hw_state.cfgcr1; - I915_WRITE(CNL_DPLL_CFGCR1(id), val); + intel_de_write(dev_priv, CNL_DPLL_CFGCR1(id), val); /* 4. Reab back to ensure writes completed */ - POSTING_READ(CNL_DPLL_CFGCR1(id)); + intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR1(id)); } /* @@ -2062,13 +2080,13 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv, */ /* 6. Enable DPLL in DPLL_ENABLE. */ - val = I915_READ(CNL_DPLL_ENABLE(id)); + val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id)); val |= PLL_ENABLE; - I915_WRITE(CNL_DPLL_ENABLE(id), val); + intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val); /* 7. Wait for PLL lock status in DPLL_ENABLE. */ if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5)) - DRM_ERROR("PLL %d not locked\n", id); + drm_err(&dev_priv->drm, "PLL %d not locked\n", id); /* * 8. If the frequency will result in a change to the voltage @@ -2106,13 +2124,13 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv, */ /* 3. Disable DPLL through DPLL_ENABLE. */ - val = I915_READ(CNL_DPLL_ENABLE(id)); + val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id)); val &= ~PLL_ENABLE; - I915_WRITE(CNL_DPLL_ENABLE(id), val); + intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val); /* 4. Wait for PLL not locked status in DPLL_ENABLE. */ if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5)) - DRM_ERROR("PLL %d locked\n", id); + drm_err(&dev_priv->drm, "PLL %d locked\n", id); /* * 5. If the frequency will result in a change to the voltage @@ -2124,14 +2142,14 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv, */ /* 6. Disable DPLL power in DPLL_ENABLE. */ - val = I915_READ(CNL_DPLL_ENABLE(id)); + val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id)); val &= ~PLL_POWER_ENABLE; - I915_WRITE(CNL_DPLL_ENABLE(id), val); + intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val); /* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */ if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id), PLL_POWER_STATE, 5)) - DRM_ERROR("PLL %d Power not disabled\n", id); + drm_err(&dev_priv->drm, "PLL %d Power not disabled\n", id); } static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, @@ -2150,16 +2168,17 @@ static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, ret = false; - val = I915_READ(CNL_DPLL_ENABLE(id)); + val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id)); if (!(val & PLL_ENABLE)) goto out; - val = I915_READ(CNL_DPLL_CFGCR0(id)); + val = intel_de_read(dev_priv, CNL_DPLL_CFGCR0(id)); hw_state->cfgcr0 = val; /* avoid reading back stale values if HDMI mode is not enabled */ if (val & DPLL_CFGCR0_HDMI_MODE) { - hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(id)); + hw_state->cfgcr1 = intel_de_read(dev_priv, + CNL_DPLL_CFGCR1(id)); } ret = true; @@ -2395,24 +2414,28 @@ static bool cnl_get_dpll(struct intel_atomic_state *state, { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); struct intel_shared_dpll *pll; bool bret; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { bret = cnl_ddi_hdmi_pll_dividers(crtc_state); if (!bret) { - DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n"); + drm_dbg_kms(&i915->drm, + "Could not get HDMI pll dividers.\n"); return false; } } else if (intel_crtc_has_dp_encoder(crtc_state)) { bret = cnl_ddi_dp_set_dpll_hw_state(crtc_state); if (!bret) { - DRM_DEBUG_KMS("Could not set DP dpll HW state.\n"); + drm_dbg_kms(&i915->drm, + "Could not set DP dpll HW state.\n"); return false; } } else { - DRM_DEBUG_KMS("Skip DPLL setup for output_types 0x%x\n", - crtc_state->output_types); + drm_dbg_kms(&i915->drm, + "Skip DPLL setup for output_types 0x%x\n", + crtc_state->output_types); return false; } @@ -2422,7 +2445,7 @@ static bool cnl_get_dpll(struct intel_atomic_state *state, BIT(DPLL_ID_SKL_DPLL1) | BIT(DPLL_ID_SKL_DPLL0)); if (!pll) { - DRM_DEBUG_KMS("No PLL selected\n"); + drm_dbg_kms(&i915->drm, "No PLL selected\n"); return false; } @@ -2437,10 +2460,10 @@ static bool cnl_get_dpll(struct intel_atomic_state *state, static void cnl_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - DRM_DEBUG_KMS("dpll_hw_state: " - "cfgcr0: 0x%x, cfgcr1: 0x%x\n", - hw_state->cfgcr0, - hw_state->cfgcr1); + drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: " + "cfgcr0: 0x%x, cfgcr1: 0x%x\n", + hw_state->cfgcr0, + hw_state->cfgcr1); } static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = { @@ -2761,7 +2784,8 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz, pll_state, is_dkl)) { - DRM_DEBUG_KMS("Failed to find divisors for clock %d\n", clock); + drm_dbg_kms(&dev_priv->drm, + "Failed to find divisors for clock %d\n", clock); return false; } @@ -2774,8 +2798,9 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, } if (m2div_int > 255) { - DRM_DEBUG_KMS("Failed to find mdiv for clock %d\n", - clock); + drm_dbg_kms(&dev_priv->drm, + "Failed to find mdiv for clock %d\n", + clock); return false; } } @@ -2996,7 +3021,8 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, unsigned long dpll_mask; if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) { - DRM_DEBUG_KMS("Could not calculate combo PHY PLL state.\n"); + drm_dbg_kms(&dev_priv->drm, + "Could not calculate combo PHY PLL state.\n"); return false; } @@ -3013,8 +3039,9 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, &port_dpll->hw_state, dpll_mask); if (!port_dpll->pll) { - DRM_DEBUG_KMS("No combo PHY PLL found for [ENCODER:%d:%s]\n", - encoder->base.base.id, encoder->base.name); + drm_dbg_kms(&dev_priv->drm, + "No combo PHY PLL found for [ENCODER:%d:%s]\n", + encoder->base.base.id, encoder->base.name); return false; } @@ -3038,7 +3065,8 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state, port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) { - DRM_DEBUG_KMS("Could not calculate TBT PLL state.\n"); + drm_dbg_kms(&dev_priv->drm, + "Could not calculate TBT PLL state.\n"); return false; } @@ -3046,7 +3074,7 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state, &port_dpll->hw_state, BIT(DPLL_ID_ICL_TBTPLL)); if (!port_dpll->pll) { - DRM_DEBUG_KMS("No TBT-ALT PLL found\n"); + drm_dbg_kms(&dev_priv->drm, "No TBT-ALT PLL found\n"); return false; } intel_reference_shared_dpll(state, crtc, @@ -3055,7 +3083,8 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state, port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; if (!icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state)) { - DRM_DEBUG_KMS("Could not calculate MG PHY PLL state.\n"); + drm_dbg_kms(&dev_priv->drm, + "Could not calculate MG PHY PLL state.\n"); goto err_unreference_tbt_pll; } @@ -3065,7 +3094,7 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state, &port_dpll->hw_state, BIT(dpll_id)); if (!port_dpll->pll) { - DRM_DEBUG_KMS("No MG PHY PLL found\n"); + drm_dbg_kms(&dev_priv->drm, "No MG PHY PLL found\n"); goto err_unreference_tbt_pll; } intel_reference_shared_dpll(state, crtc, @@ -3140,35 +3169,37 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv, if (!wakeref) return false; - val = I915_READ(MG_PLL_ENABLE(tc_port)); + val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port)); if (!(val & PLL_ENABLE)) goto out; - hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(tc_port)); + hw_state->mg_refclkin_ctl = intel_de_read(dev_priv, + MG_REFCLKIN_CTL(tc_port)); hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; hw_state->mg_clktop2_coreclkctl1 = - I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port)); + intel_de_read(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port)); hw_state->mg_clktop2_coreclkctl1 &= MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; hw_state->mg_clktop2_hsclkctl = - I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port)); + intel_de_read(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port)); hw_state->mg_clktop2_hsclkctl &= MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK; - hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port)); - hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(tc_port)); - hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(tc_port)); - hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(tc_port)); - hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(tc_port)); + hw_state->mg_pll_div0 = intel_de_read(dev_priv, MG_PLL_DIV0(tc_port)); + hw_state->mg_pll_div1 = intel_de_read(dev_priv, MG_PLL_DIV1(tc_port)); + hw_state->mg_pll_lf = intel_de_read(dev_priv, MG_PLL_LF(tc_port)); + hw_state->mg_pll_frac_lock = intel_de_read(dev_priv, + MG_PLL_FRAC_LOCK(tc_port)); + hw_state->mg_pll_ssc = intel_de_read(dev_priv, MG_PLL_SSC(tc_port)); - hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(tc_port)); + hw_state->mg_pll_bias = intel_de_read(dev_priv, MG_PLL_BIAS(tc_port)); hw_state->mg_pll_tdc_coldst_bias = - I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port)); + intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port)); if (dev_priv->cdclk.hw.ref == 38400) { hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART; @@ -3202,7 +3233,7 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, if (!wakeref) return false; - val = I915_READ(MG_PLL_ENABLE(tc_port)); + val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port)); if (!(val & PLL_ENABLE)) goto out; @@ -3210,13 +3241,15 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, * All registers read here have the same HIP_INDEX_REG even though * they are on different building blocks */ - I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x2)); + intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), + HIP_INDEX_VAL(tc_port, 0x2)); - hw_state->mg_refclkin_ctl = I915_READ(DKL_REFCLKIN_CTL(tc_port)); + hw_state->mg_refclkin_ctl = intel_de_read(dev_priv, + DKL_REFCLKIN_CTL(tc_port)); hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; hw_state->mg_clktop2_hsclkctl = - I915_READ(DKL_CLKTOP2_HSCLKCTL(tc_port)); + intel_de_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)); hw_state->mg_clktop2_hsclkctl &= MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | @@ -3224,32 +3257,32 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK; hw_state->mg_clktop2_coreclkctl1 = - I915_READ(DKL_CLKTOP2_CORECLKCTL1(tc_port)); + intel_de_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)); hw_state->mg_clktop2_coreclkctl1 &= MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; - hw_state->mg_pll_div0 = I915_READ(DKL_PLL_DIV0(tc_port)); + hw_state->mg_pll_div0 = intel_de_read(dev_priv, DKL_PLL_DIV0(tc_port)); hw_state->mg_pll_div0 &= (DKL_PLL_DIV0_INTEG_COEFF_MASK | DKL_PLL_DIV0_PROP_COEFF_MASK | DKL_PLL_DIV0_FBPREDIV_MASK | DKL_PLL_DIV0_FBDIV_INT_MASK); - hw_state->mg_pll_div1 = I915_READ(DKL_PLL_DIV1(tc_port)); + hw_state->mg_pll_div1 = intel_de_read(dev_priv, DKL_PLL_DIV1(tc_port)); hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK | DKL_PLL_DIV1_TDC_TARGET_CNT_MASK); - hw_state->mg_pll_ssc = I915_READ(DKL_PLL_SSC(tc_port)); + hw_state->mg_pll_ssc = intel_de_read(dev_priv, DKL_PLL_SSC(tc_port)); hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | DKL_PLL_SSC_STEP_LEN_MASK | DKL_PLL_SSC_STEP_NUM_MASK | DKL_PLL_SSC_EN); - hw_state->mg_pll_bias = I915_READ(DKL_PLL_BIAS(tc_port)); + hw_state->mg_pll_bias = intel_de_read(dev_priv, DKL_PLL_BIAS(tc_port)); hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H | DKL_PLL_BIAS_FBDIV_FRAC_MASK); hw_state->mg_pll_tdc_coldst_bias = - I915_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port)); + intel_de_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK | DKL_PLL_TDC_FEED_FWD_GAIN_MASK); @@ -3274,20 +3307,26 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv, if (!wakeref) return false; - val = I915_READ(enable_reg); + val = intel_de_read(dev_priv, enable_reg); if (!(val & PLL_ENABLE)) goto out; if (INTEL_GEN(dev_priv) >= 12) { - hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id)); + hw_state->cfgcr0 = intel_de_read(dev_priv, + TGL_DPLL_CFGCR0(id)); + hw_state->cfgcr1 = intel_de_read(dev_priv, + TGL_DPLL_CFGCR1(id)); } else { if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) { - hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(4)); - hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(4)); + hw_state->cfgcr0 = intel_de_read(dev_priv, + ICL_DPLL_CFGCR0(4)); + hw_state->cfgcr1 = intel_de_read(dev_priv, + ICL_DPLL_CFGCR1(4)); } else { - hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id)); + hw_state->cfgcr0 = intel_de_read(dev_priv, + ICL_DPLL_CFGCR0(id)); + hw_state->cfgcr1 = intel_de_read(dev_priv, + ICL_DPLL_CFGCR1(id)); } } @@ -3338,9 +3377,9 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv, } } - I915_WRITE(cfgcr0_reg, hw_state->cfgcr0); - I915_WRITE(cfgcr1_reg, hw_state->cfgcr1); - POSTING_READ(cfgcr1_reg); + intel_de_write(dev_priv, cfgcr0_reg, hw_state->cfgcr0); + intel_de_write(dev_priv, cfgcr1_reg, hw_state->cfgcr1); + intel_de_posting_read(dev_priv, cfgcr1_reg); } static void icl_mg_pll_write(struct drm_i915_private *dev_priv, @@ -3356,41 +3395,42 @@ static void icl_mg_pll_write(struct drm_i915_private *dev_priv, * during the calc/readout phase if the mask depends on some other HW * state like refclk, see icl_calc_mg_pll_state(). */ - val = I915_READ(MG_REFCLKIN_CTL(tc_port)); + val = intel_de_read(dev_priv, MG_REFCLKIN_CTL(tc_port)); val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK; val |= hw_state->mg_refclkin_ctl; - I915_WRITE(MG_REFCLKIN_CTL(tc_port), val); + intel_de_write(dev_priv, MG_REFCLKIN_CTL(tc_port), val); - val = I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port)); + val = intel_de_read(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port)); val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; val |= hw_state->mg_clktop2_coreclkctl1; - I915_WRITE(MG_CLKTOP2_CORECLKCTL1(tc_port), val); + intel_de_write(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port), val); - val = I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port)); + val = intel_de_read(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port)); val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK); val |= hw_state->mg_clktop2_hsclkctl; - I915_WRITE(MG_CLKTOP2_HSCLKCTL(tc_port), val); + intel_de_write(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port), val); - I915_WRITE(MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); - I915_WRITE(MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); - I915_WRITE(MG_PLL_LF(tc_port), hw_state->mg_pll_lf); - I915_WRITE(MG_PLL_FRAC_LOCK(tc_port), hw_state->mg_pll_frac_lock); - I915_WRITE(MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); + intel_de_write(dev_priv, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); + intel_de_write(dev_priv, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); + intel_de_write(dev_priv, MG_PLL_LF(tc_port), hw_state->mg_pll_lf); + intel_de_write(dev_priv, MG_PLL_FRAC_LOCK(tc_port), + hw_state->mg_pll_frac_lock); + intel_de_write(dev_priv, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); - val = I915_READ(MG_PLL_BIAS(tc_port)); + val = intel_de_read(dev_priv, MG_PLL_BIAS(tc_port)); val &= ~hw_state->mg_pll_bias_mask; val |= hw_state->mg_pll_bias; - I915_WRITE(MG_PLL_BIAS(tc_port), val); + intel_de_write(dev_priv, MG_PLL_BIAS(tc_port), val); - val = I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port)); + val = intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port)); val &= ~hw_state->mg_pll_tdc_coldst_bias_mask; val |= hw_state->mg_pll_tdc_coldst_bias; - I915_WRITE(MG_PLL_TDC_COLDST_BIAS(tc_port), val); + intel_de_write(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port), val); - POSTING_READ(MG_PLL_TDC_COLDST_BIAS(tc_port)); + intel_de_posting_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port)); } static void dkl_pll_write(struct drm_i915_private *dev_priv, @@ -3404,62 +3444,63 @@ static void dkl_pll_write(struct drm_i915_private *dev_priv, * All registers programmed here have the same HIP_INDEX_REG even * though on different building block */ - I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x2)); + intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), + HIP_INDEX_VAL(tc_port, 0x2)); /* All the registers are RMW */ - val = I915_READ(DKL_REFCLKIN_CTL(tc_port)); + val = intel_de_read(dev_priv, DKL_REFCLKIN_CTL(tc_port)); val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK; val |= hw_state->mg_refclkin_ctl; - I915_WRITE(DKL_REFCLKIN_CTL(tc_port), val); + intel_de_write(dev_priv, DKL_REFCLKIN_CTL(tc_port), val); - val = I915_READ(DKL_CLKTOP2_CORECLKCTL1(tc_port)); + val = intel_de_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)); val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; val |= hw_state->mg_clktop2_coreclkctl1; - I915_WRITE(DKL_CLKTOP2_CORECLKCTL1(tc_port), val); + intel_de_write(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), val); - val = I915_READ(DKL_CLKTOP2_HSCLKCTL(tc_port)); + val = intel_de_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)); val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK); val |= hw_state->mg_clktop2_hsclkctl; - I915_WRITE(DKL_CLKTOP2_HSCLKCTL(tc_port), val); + intel_de_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), val); - val = I915_READ(DKL_PLL_DIV0(tc_port)); + val = intel_de_read(dev_priv, DKL_PLL_DIV0(tc_port)); val &= ~(DKL_PLL_DIV0_INTEG_COEFF_MASK | DKL_PLL_DIV0_PROP_COEFF_MASK | DKL_PLL_DIV0_FBPREDIV_MASK | DKL_PLL_DIV0_FBDIV_INT_MASK); val |= hw_state->mg_pll_div0; - I915_WRITE(DKL_PLL_DIV0(tc_port), val); + intel_de_write(dev_priv, DKL_PLL_DIV0(tc_port), val); - val = I915_READ(DKL_PLL_DIV1(tc_port)); + val = intel_de_read(dev_priv, DKL_PLL_DIV1(tc_port)); val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK | DKL_PLL_DIV1_TDC_TARGET_CNT_MASK); val |= hw_state->mg_pll_div1; - I915_WRITE(DKL_PLL_DIV1(tc_port), val); + intel_de_write(dev_priv, DKL_PLL_DIV1(tc_port), val); - val = I915_READ(DKL_PLL_SSC(tc_port)); + val = intel_de_read(dev_priv, DKL_PLL_SSC(tc_port)); val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | DKL_PLL_SSC_STEP_LEN_MASK | DKL_PLL_SSC_STEP_NUM_MASK | DKL_PLL_SSC_EN); val |= hw_state->mg_pll_ssc; - I915_WRITE(DKL_PLL_SSC(tc_port), val); + intel_de_write(dev_priv, DKL_PLL_SSC(tc_port), val); - val = I915_READ(DKL_PLL_BIAS(tc_port)); + val = intel_de_read(dev_priv, DKL_PLL_BIAS(tc_port)); val &= ~(DKL_PLL_BIAS_FRAC_EN_H | DKL_PLL_BIAS_FBDIV_FRAC_MASK); val |= hw_state->mg_pll_bias; - I915_WRITE(DKL_PLL_BIAS(tc_port), val); + intel_de_write(dev_priv, DKL_PLL_BIAS(tc_port), val); - val = I915_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port)); + val = intel_de_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK | DKL_PLL_TDC_FEED_FWD_GAIN_MASK); val |= hw_state->mg_pll_tdc_coldst_bias; - I915_WRITE(DKL_PLL_TDC_COLDST_BIAS(tc_port), val); + intel_de_write(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), val); - POSTING_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port)); + intel_de_posting_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); } static void icl_pll_power_enable(struct drm_i915_private *dev_priv, @@ -3468,16 +3509,17 @@ static void icl_pll_power_enable(struct drm_i915_private *dev_priv, { u32 val; - val = I915_READ(enable_reg); + val = intel_de_read(dev_priv, enable_reg); val |= PLL_POWER_ENABLE; - I915_WRITE(enable_reg, val); + intel_de_write(dev_priv, enable_reg, val); /* * The spec says we need to "wait" but it also says it should be * immediate. */ if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_POWER_STATE, 1)) - DRM_ERROR("PLL %d Power not enabled\n", pll->info->id); + drm_err(&dev_priv->drm, "PLL %d Power not enabled\n", + pll->info->id); } static void icl_pll_enable(struct drm_i915_private *dev_priv, @@ -3486,13 +3528,13 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv, { u32 val; - val = I915_READ(enable_reg); + val = intel_de_read(dev_priv, enable_reg); val |= PLL_ENABLE; - I915_WRITE(enable_reg, val); + intel_de_write(dev_priv, enable_reg, val); /* Timeout is actually 600us. */ if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 1)) - DRM_ERROR("PLL %d not locked\n", pll->info->id); + drm_err(&dev_priv->drm, "PLL %d not locked\n", pll->info->id); } static void combo_pll_enable(struct drm_i915_private *dev_priv, @@ -3584,26 +3626,27 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv, * nothign here. */ - val = I915_READ(enable_reg); + val = intel_de_read(dev_priv, enable_reg); val &= ~PLL_ENABLE; - I915_WRITE(enable_reg, val); + intel_de_write(dev_priv, enable_reg, val); /* Timeout is actually 1us. */ if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 1)) - DRM_ERROR("PLL %d locked\n", pll->info->id); + drm_err(&dev_priv->drm, "PLL %d locked\n", pll->info->id); /* DVFS post sequence would be here. See the comment above. */ - val = I915_READ(enable_reg); + val = intel_de_read(dev_priv, enable_reg); val &= ~PLL_POWER_ENABLE; - I915_WRITE(enable_reg, val); + intel_de_write(dev_priv, enable_reg, val); /* * The spec says we need to "wait" but it also says it should be * immediate. */ if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_POWER_STATE, 1)) - DRM_ERROR("PLL %d Power not disabled\n", pll->info->id); + drm_err(&dev_priv->drm, "PLL %d Power not disabled\n", + pll->info->id); } static void combo_pll_disable(struct drm_i915_private *dev_priv, @@ -3642,23 +3685,24 @@ static void mg_pll_disable(struct drm_i915_private *dev_priv, static void icl_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - DRM_DEBUG_KMS("dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, " - "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " - "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, " - "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " - "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, " - "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", - hw_state->cfgcr0, hw_state->cfgcr1, - hw_state->mg_refclkin_ctl, - hw_state->mg_clktop2_coreclkctl1, - hw_state->mg_clktop2_hsclkctl, - hw_state->mg_pll_div0, - hw_state->mg_pll_div1, - hw_state->mg_pll_lf, - hw_state->mg_pll_frac_lock, - hw_state->mg_pll_ssc, - hw_state->mg_pll_bias, - hw_state->mg_pll_tdc_coldst_bias); + drm_dbg_kms(&dev_priv->drm, + "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, " + "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " + "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, " + "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " + "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, " + "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", + hw_state->cfgcr0, hw_state->cfgcr1, + hw_state->mg_refclkin_ctl, + hw_state->mg_clktop2_coreclkctl1, + hw_state->mg_clktop2_hsclkctl, + hw_state->mg_pll_div0, + hw_state->mg_pll_div1, + hw_state->mg_pll_lf, + hw_state->mg_pll_frac_lock, + hw_state->mg_pll_ssc, + hw_state->mg_pll_bias, + hw_state->mg_pll_tdc_coldst_bias); } static const struct intel_shared_dpll_funcs combo_pll_funcs = { @@ -3777,7 +3821,7 @@ void intel_shared_dpll_init(struct drm_device *dev) dpll_info = dpll_mgr->dpll_info; for (i = 0; dpll_info[i].name; i++) { - WARN_ON(i != dpll_info[i].id); + drm_WARN_ON(dev, i != dpll_info[i].id); dev_priv->shared_dplls[i].info = &dpll_info[i]; } @@ -3814,7 +3858,7 @@ bool intel_reserve_shared_dplls(struct intel_atomic_state *state, struct drm_i915_private *dev_priv = to_i915(state->base.dev); const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr; - if (WARN_ON(!dpll_mgr)) + if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr)) return false; return dpll_mgr->get_dplls(state, crtc, encoder); @@ -3866,7 +3910,7 @@ void intel_update_active_dpll(struct intel_atomic_state *state, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr; - if (WARN_ON(!dpll_mgr)) + if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr)) return; dpll_mgr->update_active_dpll(state, crtc, encoder); @@ -3877,7 +3921,7 @@ void intel_update_active_dpll(struct intel_atomic_state *state, * @dev_priv: i915 drm device * @hw_state: hw state to be written to the log * - * Write the relevant values in @hw_state to dmesg using DRM_DEBUG_KMS. + * Write the relevant values in @hw_state to dmesg using drm_dbg_kms. */ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) @@ -3888,11 +3932,12 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, /* fallback for platforms that don't use the shared dpll * infrastructure */ - DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " - "fp0: 0x%x, fp1: 0x%x\n", - hw_state->dpll, - hw_state->dpll_md, - hw_state->fp0, - hw_state->fp1); + drm_dbg_kms(&dev_priv->drm, + "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " + "fp0: 0x%x, fp1: 0x%x\n", + hw_state->dpll, + hw_state->dpll_md, + hw_state->fp0, + hw_state->fp1); } } |