diff options
Diffstat (limited to 'drivers/gpu/drm/msm/disp/mdp5')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c | 11 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 15 |
3 files changed, 24 insertions, 9 deletions
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c index 4a53d7b42e9c..0c8f9f88301f 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c @@ -16,6 +16,7 @@ #include <drm/drm_vblank.h> #include "mdp5_kms.h" +#include "msm_gem.h" #define CURSOR_WIDTH 64 #define CURSOR_HEIGHT 64 @@ -577,9 +578,9 @@ static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc, mdp5_crtc->enabled = true; } -int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc, - struct drm_crtc_state *new_crtc_state, - bool need_right_mixer) +static int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc, + struct drm_crtc_state *new_crtc_state, + bool need_right_mixer) { struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(new_crtc_state); diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c index 030279d7b64b..81b0c7cf954e 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c @@ -216,7 +216,9 @@ static void send_start_signal(struct mdp5_ctl *ctl) /** * mdp5_ctl_set_encoder_state() - set the encoder state * - * @enable: true, when encoder is ready for data streaming; false, otherwise. + * @ctl: the CTL instance + * @pipeline: the encoder's INTF + MIXER configuration + * @enabled: true, when encoder is ready for data streaming; false, otherwise. * * Note: * This encoder state is needed to trigger START signal (data path kickoff). @@ -510,6 +512,13 @@ static void fix_for_single_flush(struct mdp5_ctl *ctl, u32 *flush_mask, /** * mdp5_ctl_commit() - Register Flush * + * @ctl: the CTL instance + * @pipeline: the encoder's INTF + MIXER configuration + * @flush_mask: bitmask of display controller hw blocks to flush + * @start: if true, immediately update flush registers and set START + * bit, otherwise accumulate flush_mask bits until we are + * ready to START + * * The flush register is used to indicate several registers are all * programmed, and are safe to update to the back copy of the double * buffered registers. diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c index e193865ce9a2..15aed45022bc 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c @@ -232,6 +232,8 @@ static void mdp5_kms_destroy(struct msm_kms *kms) aspace->mmu->funcs->detach(aspace->mmu); msm_gem_address_space_put(aspace); } + + mdp_kms_destroy(&mdp5_kms->base); } #ifdef CONFIG_DEBUG_FS @@ -294,7 +296,7 @@ static const struct mdp_kms_funcs kms_funcs = { .set_irqmask = mdp5_set_irqmask, }; -int mdp5_disable(struct mdp5_kms *mdp5_kms) +static int mdp5_disable(struct mdp5_kms *mdp5_kms) { DBG(""); @@ -314,7 +316,7 @@ int mdp5_disable(struct mdp5_kms *mdp5_kms) return 0; } -int mdp5_enable(struct mdp5_kms *mdp5_kms) +static int mdp5_enable(struct mdp5_kms *mdp5_kms) { DBG(""); @@ -592,11 +594,14 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) return NULL; mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); - - mdp_kms_init(&mdp5_kms->base, &kms_funcs); - pdev = mdp5_kms->pdev; + ret = mdp_kms_init(&mdp5_kms->base, &kms_funcs); + if (ret) { + DRM_DEV_ERROR(&pdev->dev, "failed to init kms\n"); + goto fail; + } + irq = irq_of_parse_and_map(pdev->dev.of_node, 0); if (irq < 0) { ret = irq; |