diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/engine/device')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/acpi.c | 59 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/acpi.h | 9 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/base.c | 715 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/ctrl.c | 205 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/gm100.c | 150 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/nv04.c | 89 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/nv10.c | 204 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/nv20.c | 131 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/nv30.c | 153 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/nv40.c | 427 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/nv50.c | 475 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/nvc0.c | 357 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 324 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/priv.h | 8 |
14 files changed, 0 insertions, 3306 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/acpi.c b/drivers/gpu/drm/nouveau/core/engine/device/acpi.c deleted file mode 100644 index 4dbf0ba89e5c..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/acpi.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2014 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "acpi.h" - -#ifdef CONFIG_ACPI -static int -nvkm_acpi_ntfy(struct notifier_block *nb, unsigned long val, void *data) -{ - struct nouveau_device *device = - container_of(nb, typeof(*device), acpi.nb); - struct acpi_bus_event *info = data; - - if (!strcmp(info->device_class, "ac_adapter")) - nvkm_event_send(&device->event, 1, 0, NULL, 0); - - return NOTIFY_DONE; -} -#endif - -int -nvkm_acpi_fini(struct nouveau_device *device, bool suspend) -{ -#ifdef CONFIG_ACPI - unregister_acpi_notifier(&device->acpi.nb); -#endif - return 0; -} - -int -nvkm_acpi_init(struct nouveau_device *device) -{ -#ifdef CONFIG_ACPI - device->acpi.nb.notifier_call = nvkm_acpi_ntfy; - register_acpi_notifier(&device->acpi.nb); -#endif - return 0; -} diff --git a/drivers/gpu/drm/nouveau/core/engine/device/acpi.h b/drivers/gpu/drm/nouveau/core/engine/device/acpi.h deleted file mode 100644 index cc49f4f568cd..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/acpi.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __NVKM_DEVICE_ACPI_H__ -#define __NVKM_DEVICE_ACPI_H__ - -#include <engine/device.h> - -int nvkm_acpi_init(struct nouveau_device *); -int nvkm_acpi_fini(struct nouveau_device *, bool); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c deleted file mode 100644 index 137e0b0faeae..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/base.c +++ /dev/null @@ -1,715 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <core/object.h> -#include <core/device.h> -#include <core/client.h> -#include <core/option.h> -#include <nvif/unpack.h> -#include <nvif/class.h> - -#include <subdev/bios.h> -#include <subdev/fb.h> -#include <subdev/instmem.h> - -#include "priv.h" -#include "acpi.h" - -static DEFINE_MUTEX(nv_devices_mutex); -static LIST_HEAD(nv_devices); - -struct nouveau_device * -nouveau_device_find(u64 name) -{ - struct nouveau_device *device, *match = NULL; - mutex_lock(&nv_devices_mutex); - list_for_each_entry(device, &nv_devices, head) { - if (device->handle == name) { - match = device; - break; - } - } - mutex_unlock(&nv_devices_mutex); - return match; -} - -int -nouveau_device_list(u64 *name, int size) -{ - struct nouveau_device *device; - int nr = 0; - mutex_lock(&nv_devices_mutex); - list_for_each_entry(device, &nv_devices, head) { - if (nr++ < size) - name[nr - 1] = device->handle; - } - mutex_unlock(&nv_devices_mutex); - return nr; -} - -/****************************************************************************** - * nouveau_devobj (0x0080): class implementation - *****************************************************************************/ - -struct nouveau_devobj { - struct nouveau_parent base; - struct nouveau_object *subdev[NVDEV_SUBDEV_NR]; -}; - -static int -nouveau_devobj_info(struct nouveau_object *object, void *data, u32 size) -{ - struct nouveau_device *device = nv_device(object); - struct nouveau_fb *pfb = nouveau_fb(device); - struct nouveau_instmem *imem = nouveau_instmem(device); - union { - struct nv_device_info_v0 v0; - } *args = data; - int ret; - - nv_ioctl(object, "device info size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { - nv_ioctl(object, "device info vers %d\n", args->v0.version); - } else - return ret; - - switch (device->chipset) { - case 0x01a: - case 0x01f: - case 0x04c: - case 0x04e: - case 0x063: - case 0x067: - case 0x068: - case 0x0aa: - case 0x0ac: - case 0x0af: - args->v0.platform = NV_DEVICE_INFO_V0_IGP; - break; - default: - if (device->pdev) { - if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP)) - args->v0.platform = NV_DEVICE_INFO_V0_AGP; - else - if (pci_is_pcie(device->pdev)) - args->v0.platform = NV_DEVICE_INFO_V0_PCIE; - else - args->v0.platform = NV_DEVICE_INFO_V0_PCI; - } else { - args->v0.platform = NV_DEVICE_INFO_V0_SOC; - } - break; - } - - switch (device->card_type) { - case NV_04: args->v0.family = NV_DEVICE_INFO_V0_TNT; break; - case NV_10: - case NV_11: args->v0.family = NV_DEVICE_INFO_V0_CELSIUS; break; - case NV_20: args->v0.family = NV_DEVICE_INFO_V0_KELVIN; break; - case NV_30: args->v0.family = NV_DEVICE_INFO_V0_RANKINE; break; - case NV_40: args->v0.family = NV_DEVICE_INFO_V0_CURIE; break; - case NV_50: args->v0.family = NV_DEVICE_INFO_V0_TESLA; break; - case NV_C0: args->v0.family = NV_DEVICE_INFO_V0_FERMI; break; - case NV_E0: args->v0.family = NV_DEVICE_INFO_V0_KEPLER; break; - case GM100: args->v0.family = NV_DEVICE_INFO_V0_MAXWELL; break; - default: - args->v0.family = 0; - break; - } - - args->v0.chipset = device->chipset; - args->v0.revision = device->chiprev; - if (pfb) args->v0.ram_size = args->v0.ram_user = pfb->ram->size; - else args->v0.ram_size = args->v0.ram_user = 0; - if (imem) args->v0.ram_user = args->v0.ram_user - imem->reserved; - return 0; -} - -static int -nouveau_devobj_mthd(struct nouveau_object *object, u32 mthd, - void *data, u32 size) -{ - switch (mthd) { - case NV_DEVICE_V0_INFO: - return nouveau_devobj_info(object, data, size); - default: - break; - } - return -EINVAL; -} - -static u8 -nouveau_devobj_rd08(struct nouveau_object *object, u64 addr) -{ - return nv_rd08(object->engine, addr); -} - -static u16 -nouveau_devobj_rd16(struct nouveau_object *object, u64 addr) -{ - return nv_rd16(object->engine, addr); -} - -static u32 -nouveau_devobj_rd32(struct nouveau_object *object, u64 addr) -{ - return nv_rd32(object->engine, addr); -} - -static void -nouveau_devobj_wr08(struct nouveau_object *object, u64 addr, u8 data) -{ - nv_wr08(object->engine, addr, data); -} - -static void -nouveau_devobj_wr16(struct nouveau_object *object, u64 addr, u16 data) -{ - nv_wr16(object->engine, addr, data); -} - -static void -nouveau_devobj_wr32(struct nouveau_object *object, u64 addr, u32 data) -{ - nv_wr32(object->engine, addr, data); -} - -static int -nouveau_devobj_map(struct nouveau_object *object, u64 *addr, u32 *size) -{ - struct nouveau_device *device = nv_device(object); - *addr = nv_device_resource_start(device, 0); - *size = nv_device_resource_len(device, 0); - return 0; -} - -static const u64 disable_map[] = { - [NVDEV_SUBDEV_VBIOS] = NV_DEVICE_V0_DISABLE_VBIOS, - [NVDEV_SUBDEV_DEVINIT] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_GPIO] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_I2C] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_CLOCK] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_MXM] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_MC] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_BUS] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_TIMER] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_FB] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_LTC] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_IBUS] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_INSTMEM] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_VM] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_BAR] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_VOLT] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_THERM] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_PWR] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_FUSE] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_ENGINE_DMAOBJ] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_ENGINE_PERFMON] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_ENGINE_FIFO] = NV_DEVICE_V0_DISABLE_FIFO, - [NVDEV_ENGINE_SW] = NV_DEVICE_V0_DISABLE_FIFO, - [NVDEV_ENGINE_GR] = NV_DEVICE_V0_DISABLE_GRAPH, - [NVDEV_ENGINE_MPEG] = NV_DEVICE_V0_DISABLE_MPEG, - [NVDEV_ENGINE_ME] = NV_DEVICE_V0_DISABLE_ME, - [NVDEV_ENGINE_VP] = NV_DEVICE_V0_DISABLE_VP, - [NVDEV_ENGINE_CRYPT] = NV_DEVICE_V0_DISABLE_CRYPT, - [NVDEV_ENGINE_BSP] = NV_DEVICE_V0_DISABLE_BSP, - [NVDEV_ENGINE_PPP] = NV_DEVICE_V0_DISABLE_PPP, - [NVDEV_ENGINE_COPY0] = NV_DEVICE_V0_DISABLE_COPY0, - [NVDEV_ENGINE_COPY1] = NV_DEVICE_V0_DISABLE_COPY1, - [NVDEV_ENGINE_COPY2] = NV_DEVICE_V0_DISABLE_COPY1, - [NVDEV_ENGINE_VIC] = NV_DEVICE_V0_DISABLE_VIC, - [NVDEV_ENGINE_VENC] = NV_DEVICE_V0_DISABLE_VENC, - [NVDEV_ENGINE_DISP] = NV_DEVICE_V0_DISABLE_DISP, - [NVDEV_SUBDEV_NR] = 0, -}; - -static void -nouveau_devobj_dtor(struct nouveau_object *object) -{ - struct nouveau_devobj *devobj = (void *)object; - int i; - - for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) - nouveau_object_ref(NULL, &devobj->subdev[i]); - - nouveau_parent_destroy(&devobj->base); -} - -static struct nouveau_oclass -nouveau_devobj_oclass_super = { - .handle = NV_DEVICE, - .ofuncs = &(struct nouveau_ofuncs) { - .dtor = nouveau_devobj_dtor, - .init = _nouveau_parent_init, - .fini = _nouveau_parent_fini, - .mthd = nouveau_devobj_mthd, - .map = nouveau_devobj_map, - .rd08 = nouveau_devobj_rd08, - .rd16 = nouveau_devobj_rd16, - .rd32 = nouveau_devobj_rd32, - .wr08 = nouveau_devobj_wr08, - .wr16 = nouveau_devobj_wr16, - .wr32 = nouveau_devobj_wr32, - } -}; - -static int -nouveau_devobj_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - union { - struct nv_device_v0 v0; - } *args = data; - struct nouveau_client *client = nv_client(parent); - struct nouveau_device *device; - struct nouveau_devobj *devobj; - u32 boot0, strap; - u64 disable, mmio_base, mmio_size; - void __iomem *map; - int ret, i, c; - - nv_ioctl(parent, "create device size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { - nv_ioctl(parent, "create device v%d device %016llx " - "disable %016llx debug0 %016llx\n", - args->v0.version, args->v0.device, - args->v0.disable, args->v0.debug0); - } else - return ret; - - /* give priviledged clients register access */ - if (client->super) - oclass = &nouveau_devobj_oclass_super; - - /* find the device subdev that matches what the client requested */ - device = nv_device(client->device); - if (args->v0.device != ~0) { - device = nouveau_device_find(args->v0.device); - if (!device) - return -ENODEV; - } - - ret = nouveau_parent_create(parent, nv_object(device), oclass, 0, - nouveau_control_oclass, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_FIFO) | - (1ULL << NVDEV_ENGINE_DISP) | - (1ULL << NVDEV_ENGINE_PERFMON), &devobj); - *pobject = nv_object(devobj); - if (ret) - return ret; - - mmio_base = nv_device_resource_start(device, 0); - mmio_size = nv_device_resource_len(device, 0); - - /* translate api disable mask into internal mapping */ - disable = args->v0.debug0; - for (i = 0; i < NVDEV_SUBDEV_NR; i++) { - if (args->v0.disable & disable_map[i]) - disable |= (1ULL << i); - } - - /* identify the chipset, and determine classes of subdev/engines */ - if (!(args->v0.disable & NV_DEVICE_V0_DISABLE_IDENTIFY) && - !device->card_type) { - map = ioremap(mmio_base, 0x102000); - if (map == NULL) - return -ENOMEM; - - /* switch mmio to cpu's native endianness */ -#ifndef __BIG_ENDIAN - if (ioread32_native(map + 0x000004) != 0x00000000) -#else - if (ioread32_native(map + 0x000004) == 0x00000000) -#endif - iowrite32_native(0x01000001, map + 0x000004); - - /* read boot0 and strapping information */ - boot0 = ioread32_native(map + 0x000000); - strap = ioread32_native(map + 0x101000); - iounmap(map); - - /* determine chipset and derive architecture from it */ - if ((boot0 & 0x1f000000) > 0) { - device->chipset = (boot0 & 0x1ff00000) >> 20; - device->chiprev = (boot0 & 0x000000ff); - switch (device->chipset & 0x1f0) { - case 0x010: { - if (0x461 & (1 << (device->chipset & 0xf))) - device->card_type = NV_10; - else - device->card_type = NV_11; - device->chiprev = 0x00; - break; - } - case 0x020: device->card_type = NV_20; break; - case 0x030: device->card_type = NV_30; break; - case 0x040: - case 0x060: device->card_type = NV_40; break; - case 0x050: - case 0x080: - case 0x090: - case 0x0a0: device->card_type = NV_50; break; - case 0x0c0: - case 0x0d0: device->card_type = NV_C0; break; - case 0x0e0: - case 0x0f0: - case 0x100: device->card_type = NV_E0; break; - case 0x110: - case 0x120: device->card_type = GM100; break; - default: - break; - } - } else - if ((boot0 & 0xff00fff0) == 0x20004000) { - if (boot0 & 0x00f00000) - device->chipset = 0x05; - else - device->chipset = 0x04; - device->card_type = NV_04; - } - - switch (device->card_type) { - case NV_04: ret = nv04_identify(device); break; - case NV_10: - case NV_11: ret = nv10_identify(device); break; - case NV_20: ret = nv20_identify(device); break; - case NV_30: ret = nv30_identify(device); break; - case NV_40: ret = nv40_identify(device); break; - case NV_50: ret = nv50_identify(device); break; - case NV_C0: ret = nvc0_identify(device); break; - case NV_E0: ret = nve0_identify(device); break; - case GM100: ret = gm100_identify(device); break; - default: - ret = -EINVAL; - break; - } - - if (ret) { - nv_error(device, "unknown chipset, 0x%08x\n", boot0); - return ret; - } - - nv_info(device, "BOOT0 : 0x%08x\n", boot0); - nv_info(device, "Chipset: %s (NV%02X)\n", - device->cname, device->chipset); - nv_info(device, "Family : NV%02X\n", device->card_type); - - /* determine frequency of timing crystal */ - if ( device->card_type <= NV_10 || device->chipset < 0x17 || - (device->chipset >= 0x20 && device->chipset < 0x25)) - strap &= 0x00000040; - else - strap &= 0x00400040; - - switch (strap) { - case 0x00000000: device->crystal = 13500; break; - case 0x00000040: device->crystal = 14318; break; - case 0x00400000: device->crystal = 27000; break; - case 0x00400040: device->crystal = 25000; break; - } - - nv_debug(device, "crystal freq: %dKHz\n", device->crystal); - } else - if ( (args->v0.disable & NV_DEVICE_V0_DISABLE_IDENTIFY)) { - device->cname = "NULL"; - device->oclass[NVDEV_SUBDEV_VBIOS] = &nouveau_bios_oclass; - } - - if (!(args->v0.disable & NV_DEVICE_V0_DISABLE_MMIO) && - !nv_subdev(device)->mmio) { - nv_subdev(device)->mmio = ioremap(mmio_base, mmio_size); - if (!nv_subdev(device)->mmio) { - nv_error(device, "unable to map device registers\n"); - return -ENOMEM; - } - } - - /* ensure requested subsystems are available for use */ - for (i = 1, c = 1; i < NVDEV_SUBDEV_NR; i++) { - if (!(oclass = device->oclass[i]) || (disable & (1ULL << i))) - continue; - - if (device->subdev[i]) { - nouveau_object_ref(device->subdev[i], - &devobj->subdev[i]); - continue; - } - - ret = nouveau_object_ctor(nv_object(device), NULL, - oclass, NULL, i, - &devobj->subdev[i]); - if (ret == -ENODEV) - continue; - if (ret) - return ret; - - device->subdev[i] = devobj->subdev[i]; - - /* note: can't init *any* subdevs until devinit has been run - * due to not knowing exactly what the vbios init tables will - * mess with. devinit also can't be run until all of its - * dependencies have been created. - * - * this code delays init of any subdev until all of devinit's - * dependencies have been created, and then initialises each - * subdev in turn as they're created. - */ - while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) { - struct nouveau_object *subdev = devobj->subdev[c++]; - if (subdev && !nv_iclass(subdev, NV_ENGINE_CLASS)) { - ret = nouveau_object_inc(subdev); - if (ret) - return ret; - atomic_dec(&nv_object(device)->usecount); - } else - if (subdev) { - nouveau_subdev_reset(subdev); - } - } - } - - return 0; -} - -static struct nouveau_ofuncs -nouveau_devobj_ofuncs = { - .ctor = nouveau_devobj_ctor, - .dtor = nouveau_devobj_dtor, - .init = _nouveau_parent_init, - .fini = _nouveau_parent_fini, - .mthd = nouveau_devobj_mthd, -}; - -/****************************************************************************** - * nouveau_device: engine functions - *****************************************************************************/ - -static struct nouveau_oclass -nouveau_device_sclass[] = { - { 0x0080, &nouveau_devobj_ofuncs }, - {} -}; - -static int -nouveau_device_event_ctor(struct nouveau_object *object, void *data, u32 size, - struct nvkm_notify *notify) -{ - if (!WARN_ON(size != 0)) { - notify->size = 0; - notify->types = 1; - notify->index = 0; - return 0; - } - return -EINVAL; -} - -static const struct nvkm_event_func -nouveau_device_event_func = { - .ctor = nouveau_device_event_ctor, -}; - -static int -nouveau_device_fini(struct nouveau_object *object, bool suspend) -{ - struct nouveau_device *device = (void *)object; - struct nouveau_object *subdev; - int ret, i; - - for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) { - if ((subdev = device->subdev[i])) { - if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { - ret = nouveau_object_dec(subdev, suspend); - if (ret && suspend) - goto fail; - } - } - } - - ret = nvkm_acpi_fini(device, suspend); -fail: - for (; ret && i < NVDEV_SUBDEV_NR; i++) { - if ((subdev = device->subdev[i])) { - if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { - ret = nouveau_object_inc(subdev); - if (ret) { - /* XXX */ - } - } - } - } - - return ret; -} - -static int -nouveau_device_init(struct nouveau_object *object) -{ - struct nouveau_device *device = (void *)object; - struct nouveau_object *subdev; - int ret, i = 0; - - ret = nvkm_acpi_init(device); - if (ret) - goto fail; - - for (i = 0; i < NVDEV_SUBDEV_NR; i++) { - if ((subdev = device->subdev[i])) { - if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { - ret = nouveau_object_inc(subdev); - if (ret) - goto fail; - } else { - nouveau_subdev_reset(subdev); - } - } - } - - ret = 0; -fail: - for (--i; ret && i >= 0; i--) { - if ((subdev = device->subdev[i])) { - if (!nv_iclass(subdev, NV_ENGINE_CLASS)) - nouveau_object_dec(subdev, false); - } - } - - if (ret) - nvkm_acpi_fini(device, false); - return ret; -} - -static void -nouveau_device_dtor(struct nouveau_object *object) -{ - struct nouveau_device *device = (void *)object; - - nvkm_event_fini(&device->event); - - mutex_lock(&nv_devices_mutex); - list_del(&device->head); - mutex_unlock(&nv_devices_mutex); - - if (nv_subdev(device)->mmio) - iounmap(nv_subdev(device)->mmio); - - nouveau_engine_destroy(&device->base); -} - -resource_size_t -nv_device_resource_start(struct nouveau_device *device, unsigned int bar) -{ - if (nv_device_is_pci(device)) { - return pci_resource_start(device->pdev, bar); - } else { - struct resource *res; - res = platform_get_resource(device->platformdev, - IORESOURCE_MEM, bar); - if (!res) - return 0; - return res->start; - } -} - -resource_size_t -nv_device_resource_len(struct nouveau_device *device, unsigned int bar) -{ - if (nv_device_is_pci(device)) { - return pci_resource_len(device->pdev, bar); - } else { - struct resource *res; - res = platform_get_resource(device->platformdev, - IORESOURCE_MEM, bar); - if (!res) - return 0; - return resource_size(res); - } -} - -int -nv_device_get_irq(struct nouveau_device *device, bool stall) -{ - if (nv_device_is_pci(device)) { - return device->pdev->irq; - } else { - return platform_get_irq_byname(device->platformdev, - stall ? "stall" : "nonstall"); - } -} - -static struct nouveau_oclass -nouveau_device_oclass = { - .handle = NV_ENGINE(DEVICE, 0x00), - .ofuncs = &(struct nouveau_ofuncs) { - .dtor = nouveau_device_dtor, - .init = nouveau_device_init, - .fini = nouveau_device_fini, - }, -}; - -int -nouveau_device_create_(void *dev, enum nv_bus_type type, u64 name, - const char *sname, const char *cfg, const char *dbg, - int length, void **pobject) -{ - struct nouveau_device *device; - int ret = -EEXIST; - - mutex_lock(&nv_devices_mutex); - list_for_each_entry(device, &nv_devices, head) { - if (device->handle == name) - goto done; - } - - ret = nouveau_engine_create_(NULL, NULL, &nouveau_device_oclass, true, - "DEVICE", "device", length, pobject); - device = *pobject; - if (ret) - goto done; - - switch (type) { - case NOUVEAU_BUS_PCI: - device->pdev = dev; - break; - case NOUVEAU_BUS_PLATFORM: - device->platformdev = dev; - break; - } - device->handle = name; - device->cfgopt = cfg; - device->dbgopt = dbg; - device->name = sname; - - nv_subdev(device)->debug = nouveau_dbgopt(device->dbgopt, "DEVICE"); - nv_engine(device)->sclass = nouveau_device_sclass; - list_add(&device->head, &nv_devices); - - ret = nvkm_event_init(&nouveau_device_event_func, 1, 1, - &device->event); -done: - mutex_unlock(&nv_devices_mutex); - return ret; -} diff --git a/drivers/gpu/drm/nouveau/core/engine/device/ctrl.c b/drivers/gpu/drm/nouveau/core/engine/device/ctrl.c deleted file mode 100644 index e34101a3490e..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/ctrl.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs <bskeggs@redhat.com> - */ - -#include <core/client.h> -#include <core/object.h> -#include <nvif/unpack.h> -#include <nvif/class.h> -#include <nvif/ioctl.h> - -#include <subdev/clock.h> - -#include "priv.h" - -static int -nouveau_control_mthd_pstate_info(struct nouveau_object *object, - void *data, u32 size) -{ - union { - struct nvif_control_pstate_info_v0 v0; - } *args = data; - struct nouveau_clock *clk = nouveau_clock(object); - int ret; - - nv_ioctl(object, "control pstate info size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { - nv_ioctl(object, "control pstate info vers %d\n", - args->v0.version); - } else - return ret; - - if (clk) { - args->v0.count = clk->state_nr; - args->v0.ustate_ac = clk->ustate_ac; - args->v0.ustate_dc = clk->ustate_dc; - args->v0.pwrsrc = clk->pwrsrc; - args->v0.pstate = clk->pstate; - } else { - args->v0.count = 0; - args->v0.ustate_ac = NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE; - args->v0.ustate_dc = NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE; - args->v0.pwrsrc = -ENOSYS; - args->v0.pstate = NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN; - } - - return 0; -} - -static int -nouveau_control_mthd_pstate_attr(struct nouveau_object *object, - void *data, u32 size) -{ - union { - struct nvif_control_pstate_attr_v0 v0; - } *args = data; - struct nouveau_clock *clk = nouveau_clock(object); - struct nouveau_clocks *domain; - struct nouveau_pstate *pstate; - struct nouveau_cstate *cstate; - int i = 0, j = -1; - u32 lo, hi; - int ret; - - nv_ioctl(object, "control pstate attr size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { - nv_ioctl(object, "control pstate attr vers %d state %d " - "index %d\n", - args->v0.version, args->v0.state, args->v0.index); - if (!clk) - return -ENODEV; - if (args->v0.state < NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT) - return -EINVAL; - if (args->v0.state >= clk->state_nr) - return -EINVAL; - } else - return ret; - domain = clk->domains; - - while (domain->name != nv_clk_src_max) { - if (domain->mname && ++j == args->v0.index) - break; - domain++; - } - - if (domain->name == nv_clk_src_max) - return -EINVAL; - - if (args->v0.state != NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT) { - list_for_each_entry(pstate, &clk->states, head) { - if (i++ == args->v0.state) - break; - } - - lo = pstate->base.domain[domain->name]; - hi = lo; - list_for_each_entry(cstate, &pstate->list, head) { - lo = min(lo, cstate->domain[domain->name]); - hi = max(hi, cstate->domain[domain->name]); - } - - args->v0.state = pstate->pstate; - } else { - lo = max(clk->read(clk, domain->name), 0); - hi = lo; - } - - snprintf(args->v0.name, sizeof(args->v0.name), "%s", domain->mname); - snprintf(args->v0.unit, sizeof(args->v0.unit), "MHz"); - args->v0.min = lo / domain->mdiv; - args->v0.max = hi / domain->mdiv; - - args->v0.index = 0; - while ((++domain)->name != nv_clk_src_max) { - if (domain->mname) { - args->v0.index = ++j; - break; - } - } - - return 0; -} - -static int -nouveau_control_mthd_pstate_user(struct nouveau_object *object, - void *data, u32 size) -{ - union { - struct nvif_control_pstate_user_v0 v0; - } *args = data; - struct nouveau_clock *clk = nouveau_clock(object); - int ret; - - nv_ioctl(object, "control pstate user size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { - nv_ioctl(object, "control pstate user vers %d ustate %d " - "pwrsrc %d\n", args->v0.version, - args->v0.ustate, args->v0.pwrsrc); - if (!clk) - return -ENODEV; - } else - return ret; - - if (args->v0.pwrsrc >= 0) { - ret |= nouveau_clock_ustate(clk, args->v0.ustate, args->v0.pwrsrc); - } else { - ret |= nouveau_clock_ustate(clk, args->v0.ustate, 0); - ret |= nouveau_clock_ustate(clk, args->v0.ustate, 1); - } - - return ret; -} - -static int -nouveau_control_mthd(struct nouveau_object *object, u32 mthd, - void *data, u32 size) -{ - switch (mthd) { - case NVIF_CONTROL_PSTATE_INFO: - return nouveau_control_mthd_pstate_info(object, data, size); - case NVIF_CONTROL_PSTATE_ATTR: - return nouveau_control_mthd_pstate_attr(object, data, size); - case NVIF_CONTROL_PSTATE_USER: - return nouveau_control_mthd_pstate_user(object, data, size); - default: - break; - } - return -EINVAL; -} - -static struct nouveau_ofuncs -nouveau_control_ofuncs = { - .ctor = _nouveau_object_ctor, - .dtor = nouveau_object_destroy, - .init = nouveau_object_init, - .fini = nouveau_object_fini, - .mthd = nouveau_control_mthd, -}; - -struct nouveau_oclass -nouveau_control_oclass[] = { - { .handle = NVIF_IOCTL_NEW_V0_CONTROL, - .ofuncs = &nouveau_control_ofuncs - }, - {} -}; diff --git a/drivers/gpu/drm/nouveau/core/engine/device/gm100.c b/drivers/gpu/drm/nouveau/core/engine/device/gm100.c deleted file mode 100644 index 4e74a3376de8..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/gm100.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <subdev/bios.h> -#include <subdev/bus.h> -#include <subdev/gpio.h> -#include <subdev/i2c.h> -#include <subdev/fuse.h> -#include <subdev/clock.h> -#include <subdev/therm.h> -#include <subdev/mxm.h> -#include <subdev/devinit.h> -#include <subdev/mc.h> -#include <subdev/timer.h> -#include <subdev/fb.h> -#include <subdev/ltc.h> -#include <subdev/ibus.h> -#include <subdev/instmem.h> -#include <subdev/vm.h> -#include <subdev/bar.h> -#include <subdev/pwr.h> -#include <subdev/volt.h> - -#include <engine/device.h> -#include <engine/dmaobj.h> -#include <engine/fifo.h> -#include <engine/software.h> -#include <engine/graph.h> -#include <engine/disp.h> -#include <engine/copy.h> -#include <engine/bsp.h> -#include <engine/vp.h> -#include <engine/ppp.h> -#include <engine/perfmon.h> - -int -gm100_identify(struct nouveau_device *device) -{ - switch (device->chipset) { - case 0x117: - device->cname = "GM107"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass; - -#if 0 - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; -#endif - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gm107_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; -#if 0 - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; -#endif - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; -#if 0 - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; -#endif - break; - case 0x124: - device->cname = "GM204"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass; -#if 0 - /* looks to be some non-trivial changes */ - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; - /* priv ring says no to 0x10eb14 writes */ - device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; -#endif - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass; -#if 0 - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; -#endif - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; -#if 0 - device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gm107_graph_oclass; -#endif - device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass; -#if 0 - device->oclass[NVDEV_ENGINE_COPY0 ] = &gm204_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &gm204_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &gm204_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; -#endif - break; - default: - nv_fatal(device, "unknown Maxwell chipset\n"); - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c b/drivers/gpu/drm/nouveau/core/engine/device/nv04.c deleted file mode 100644 index 573b55f5c2f9..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <subdev/bios.h> -#include <subdev/bus.h> -#include <subdev/i2c.h> -#include <subdev/clock.h> -#include <subdev/devinit.h> -#include <subdev/mc.h> -#include <subdev/timer.h> -#include <subdev/fb.h> -#include <subdev/instmem.h> -#include <subdev/vm.h> - -#include <engine/device.h> -#include <engine/dmaobj.h> -#include <engine/fifo.h> -#include <engine/software.h> -#include <engine/graph.h> -#include <engine/disp.h> - -int -nv04_identify(struct nouveau_device *device) -{ - switch (device->chipset) { - case 0x04: - device->cname = "NV04"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - case 0x05: - device->cname = "NV05"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - default: - nv_fatal(device, "unknown RIVA chipset\n"); - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c b/drivers/gpu/drm/nouveau/core/engine/device/nv10.c deleted file mode 100644 index 183a85a6204e..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <subdev/bios.h> -#include <subdev/bus.h> -#include <subdev/gpio.h> -#include <subdev/i2c.h> -#include <subdev/clock.h> -#include <subdev/devinit.h> -#include <subdev/mc.h> -#include <subdev/timer.h> -#include <subdev/fb.h> -#include <subdev/instmem.h> -#include <subdev/vm.h> - -#include <engine/device.h> -#include <engine/dmaobj.h> -#include <engine/fifo.h> -#include <engine/software.h> -#include <engine/graph.h> -#include <engine/disp.h> - -int -nv10_identify(struct nouveau_device *device) -{ - switch (device->chipset) { - case 0x10: - device->cname = "NV10"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - case 0x15: - device->cname = "NV15"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - case 0x16: - device->cname = "NV16"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - case 0x1a: - device->cname = "nForce"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - case 0x11: - device->cname = "NV11"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - case 0x17: - device->cname = "NV17"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - case 0x1f: - device->cname = "nForce2"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - case 0x18: - device->cname = "NV18"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - default: - nv_fatal(device, "unknown Celsius chipset\n"); - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c b/drivers/gpu/drm/nouveau/core/engine/device/nv20.c deleted file mode 100644 index aa564c68a920..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <subdev/bios.h> -#include <subdev/bus.h> -#include <subdev/gpio.h> -#include <subdev/i2c.h> -#include <subdev/clock.h> -#include <subdev/therm.h> -#include <subdev/devinit.h> -#include <subdev/mc.h> -#include <subdev/timer.h> -#include <subdev/fb.h> -#include <subdev/instmem.h> -#include <subdev/vm.h> - -#include <engine/device.h> -#include <engine/dmaobj.h> -#include <engine/fifo.h> -#include <engine/software.h> -#include <engine/graph.h> -#include <engine/disp.h> - -int -nv20_identify(struct nouveau_device *device) -{ - switch (device->chipset) { - case 0x20: - device->cname = "NV20"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv20_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - case 0x25: - device->cname = "NV25"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - case 0x28: - device->cname = "NV28"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - case 0x2a: - device->cname = "NV2A"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv2a_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - default: - nv_fatal(device, "unknown Kelvin chipset\n"); - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c b/drivers/gpu/drm/nouveau/core/engine/device/nv30.c deleted file mode 100644 index 11bd31da82ab..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <subdev/bios.h> -#include <subdev/bus.h> -#include <subdev/gpio.h> -#include <subdev/i2c.h> -#include <subdev/clock.h> -#include <subdev/devinit.h> -#include <subdev/mc.h> -#include <subdev/timer.h> -#include <subdev/fb.h> -#include <subdev/instmem.h> -#include <subdev/vm.h> - -#include <engine/device.h> -#include <engine/dmaobj.h> -#include <engine/fifo.h> -#include <engine/software.h> -#include <engine/graph.h> -#include <engine/mpeg.h> -#include <engine/disp.h> - -int -nv30_identify(struct nouveau_device *device) -{ - switch (device->chipset) { - case 0x30: - device->cname = "NV30"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - case 0x35: - device->cname = "NV35"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - case 0x31: - device->cname = "NV31"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - case 0x36: - device->cname = "NV36"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - case 0x34: - device->cname = "NV34"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv34_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - break; - default: - nv_fatal(device, "unknown Rankine chipset\n"); - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c b/drivers/gpu/drm/nouveau/core/engine/device/nv40.c deleted file mode 100644 index e96c223cb797..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c +++ /dev/null @@ -1,427 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <subdev/bios.h> -#include <subdev/bus.h> -#include <subdev/vm.h> -#include <subdev/gpio.h> -#include <subdev/i2c.h> -#include <subdev/clock.h> -#include <subdev/therm.h> -#include <subdev/devinit.h> -#include <subdev/mc.h> -#include <subdev/timer.h> -#include <subdev/fb.h> -#include <subdev/instmem.h> -#include <subdev/vm.h> -#include <subdev/volt.h> - -#include <engine/device.h> -#include <engine/dmaobj.h> -#include <engine/fifo.h> -#include <engine/software.h> -#include <engine/graph.h> -#include <engine/mpeg.h> -#include <engine/disp.h> -#include <engine/perfmon.h> - -int -nv40_identify(struct nouveau_device *device) -{ - switch (device->chipset) { - case 0x40: - device->cname = "NV40"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; - break; - case 0x41: - device->cname = "NV41"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; - break; - case 0x42: - device->cname = "NV42"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; - break; - case 0x43: - device->cname = "NV43"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; - break; - case 0x45: - device->cname = "NV45"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; - break; - case 0x47: - device->cname = "G70"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; - break; - case 0x49: - device->cname = "G71"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; - break; - case 0x4b: - device->cname = "G73"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; - break; - case 0x44: - device->cname = "NV44"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; - break; - case 0x46: - device->cname = "G72"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; - break; - case 0x4a: - device->cname = "NV44A"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; - break; - case 0x4c: - device->cname = "C61"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; - break; - case 0x4e: - device->cname = "C51"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv4e_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; - break; - case 0x63: - device->cname = "C73"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; - break; - case 0x67: - device->cname = "C67"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; - break; - case 0x68: - device->cname = "C68"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; - break; - default: - nv_fatal(device, "unknown Curie chipset\n"); - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c deleted file mode 100644 index 96f568d1321b..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c +++ /dev/null @@ -1,475 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <subdev/bios.h> -#include <subdev/bus.h> -#include <subdev/gpio.h> -#include <subdev/i2c.h> -#include <subdev/fuse.h> -#include <subdev/clock.h> -#include <subdev/therm.h> -#include <subdev/mxm.h> -#include <subdev/devinit.h> -#include <subdev/mc.h> -#include <subdev/timer.h> -#include <subdev/fb.h> -#include <subdev/instmem.h> -#include <subdev/vm.h> -#include <subdev/bar.h> -#include <subdev/pwr.h> -#include <subdev/volt.h> - -#include <engine/device.h> -#include <engine/dmaobj.h> -#include <engine/fifo.h> -#include <engine/software.h> -#include <engine/graph.h> -#include <engine/mpeg.h> -#include <engine/vp.h> -#include <engine/crypt.h> -#include <engine/bsp.h> -#include <engine/ppp.h> -#include <engine/copy.h> -#include <engine/disp.h> -#include <engine/perfmon.h> - -int -nv50_identify(struct nouveau_device *device) -{ - switch (device->chipset) { - case 0x50: - device->cname = "G80"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv50_perfmon_oclass; - break; - case 0x84: - device->cname = "G84"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; - break; - case 0x86: - device->cname = "G86"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; - break; - case 0x92: - device->cname = "G92"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; - break; - case 0x94: - device->cname = "G94"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; - break; - case 0x96: - device->cname = "G96"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; - break; - case 0x98: - device->cname = "G98"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; - break; - case 0xa0: - device->cname = "G200"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva0_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; - break; - case 0xaa: - device->cname = "MCP77/MCP78"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; - break; - case 0xac: - device->cname = "MCP79/MCP7A"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; - break; - case 0xa3: - device->cname = "GT215"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; - break; - case 0xa5: - device->cname = "GT216"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; - break; - case 0xa8: - device->cname = "GT218"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; - break; - case 0xaf: - device->cname = "MCP89"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; - break; - default: - nv_fatal(device, "unknown Tesla chipset\n"); - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c deleted file mode 100644 index 72a40f95d048..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c +++ /dev/null @@ -1,357 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <subdev/bios.h> -#include <subdev/bus.h> -#include <subdev/gpio.h> -#include <subdev/i2c.h> -#include <subdev/fuse.h> -#include <subdev/clock.h> -#include <subdev/therm.h> -#include <subdev/mxm.h> -#include <subdev/devinit.h> -#include <subdev/mc.h> -#include <subdev/timer.h> -#include <subdev/fb.h> -#include <subdev/ltc.h> -#include <subdev/ibus.h> -#include <subdev/instmem.h> -#include <subdev/vm.h> -#include <subdev/bar.h> -#include <subdev/pwr.h> -#include <subdev/volt.h> - -#include <engine/device.h> -#include <engine/dmaobj.h> -#include <engine/fifo.h> -#include <engine/software.h> -#include <engine/graph.h> -#include <engine/vp.h> -#include <engine/bsp.h> -#include <engine/ppp.h> -#include <engine/copy.h> -#include <engine/disp.h> -#include <engine/perfmon.h> - -int -nvc0_identify(struct nouveau_device *device) -{ - switch (device->chipset) { - case 0xc0: - device->cname = "GF100"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc0_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; - break; - case 0xc4: - device->cname = "GF104"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; - break; - case 0xc3: - device->cname = "GF106"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; - break; - case 0xce: - device->cname = "GF114"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; - break; - case 0xcf: - device->cname = "GF116"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; - break; - case 0xc1: - device->cname = "GF108"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc1_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; - break; - case 0xc8: - device->cname = "GF110"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc8_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; - break; - case 0xd9: - device->cname = "GF119"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; - break; - case 0xd7: - device->cname = "GF117"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; - break; - default: - nv_fatal(device, "unknown Fermi chipset\n"); - return -EINVAL; - } - - return 0; - } diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c deleted file mode 100644 index 732922690653..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c +++ /dev/null @@ -1,324 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <subdev/bios.h> -#include <subdev/bus.h> -#include <subdev/gpio.h> -#include <subdev/i2c.h> -#include <subdev/fuse.h> -#include <subdev/clock.h> -#include <subdev/therm.h> -#include <subdev/mxm.h> -#include <subdev/devinit.h> -#include <subdev/mc.h> -#include <subdev/timer.h> -#include <subdev/fb.h> -#include <subdev/ltc.h> -#include <subdev/ibus.h> -#include <subdev/instmem.h> -#include <subdev/vm.h> -#include <subdev/bar.h> -#include <subdev/pwr.h> -#include <subdev/volt.h> - -#include <engine/device.h> -#include <engine/dmaobj.h> -#include <engine/fifo.h> -#include <engine/software.h> -#include <engine/graph.h> -#include <engine/disp.h> -#include <engine/copy.h> -#include <engine/bsp.h> -#include <engine/vp.h> -#include <engine/ppp.h> -#include <engine/perfmon.h> - -int -nve0_identify(struct nouveau_device *device) -{ - switch (device->chipset) { - case 0xe4: - device->cname = "GK104"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = gk104_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; - break; - case 0xe7: - device->cname = "GK107"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; - break; - case 0xe6: - device->cname = "GK106"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = gk104_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; - break; - case 0xea: - device->cname = "GK20A"; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &gk20a_clock_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk20a_graph_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass; - break; - case 0xf0: - device->cname = "GK110"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass; - break; - case 0xf1: - device->cname = "GK110B"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk110b_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass; - break; - case 0x106: - device->cname = "GK208B"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - break; - case 0x108: - device->cname = "GK208"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - break; - default: - nv_fatal(device, "unknown Kepler chipset\n"); - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/core/engine/device/priv.h b/drivers/gpu/drm/nouveau/core/engine/device/priv.h deleted file mode 100644 index 035fd5b9cfc3..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/priv.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __NVKM_DEVICE_PRIV_H__ -#define __NVKM_DEVICE_PRIV_H__ - -#include <engine/device.h> - -extern struct nouveau_oclass nouveau_control_oclass[]; - -#endif |