550 files changed, 0 insertions, 112594 deletions

diff --git a/drivers/gpu/drm/nouveau/core/core/client.c b/drivers/gpu/drm/nouveau/core/core/client.c
deleted file mode 100644
index e962433294c3..000000000000
--- a/drivers/gpu/drm/nouveau/core/core/client.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/object.h>
-#include <core/client.h>
-#include <core/handle.h>
-#include <core/option.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <nvif/unpack.h>
-#include <nvif/event.h>
-
-#include <engine/device.h>
-
-struct nvkm_client_notify {
-	struct nouveau_client *client;
-	struct nvkm_notify n;
-	u8 version;
-	u8 size;
-	union {
-		struct nvif_notify_rep_v0 v0;
-	} rep;
-};
-
-static int
-nvkm_client_notify(struct nvkm_notify *n)
-{
-	struct nvkm_client_notify *notify = container_of(n, typeof(*notify), n);
-	struct nouveau_client *client = notify->client;
-	return client->ntfy(&notify->rep, notify->size, n->data, n->size);
-}
-
-int
-nvkm_client_notify_put(struct nouveau_client *client, int index)
-{
-	if (index < ARRAY_SIZE(client->notify)) {
-		if (client->notify[index]) {
-			nvkm_notify_put(&client->notify[index]->n);
-			return 0;
-		}
-	}
-	return -ENOENT;
-}
-
-int
-nvkm_client_notify_get(struct nouveau_client *client, int index)
-{
-	if (index < ARRAY_SIZE(client->notify)) {
-		if (client->notify[index]) {
-			nvkm_notify_get(&client->notify[index]->n);
-			return 0;
-		}
-	}
-	return -ENOENT;
-}
-
-int
-nvkm_client_notify_del(struct nouveau_client *client, int index)
-{
-	if (index < ARRAY_SIZE(client->notify)) {
-		if (client->notify[index]) {
-			nvkm_notify_fini(&client->notify[index]->n);
-			kfree(client->notify[index]);
-			client->notify[index] = NULL;
-			return 0;
-		}
-	}
-	return -ENOENT;
-}
-
-int
-nvkm_client_notify_new(struct nouveau_object *object,
-		       struct nvkm_event *event, void *data, u32 size)
-{
-	struct nouveau_client *client = nouveau_client(object);
-	struct nvkm_client_notify *notify;
-	union {
-		struct nvif_notify_req_v0 v0;
-	} *req = data;
-	u8  index, reply;
-	int ret;
-
-	for (index = 0; index < ARRAY_SIZE(client->notify); index++) {
-		if (!client->notify[index])
-			break;
-	}
-
-	if (index == ARRAY_SIZE(client->notify))
-		return -ENOSPC;
-
-	notify = kzalloc(sizeof(*notify), GFP_KERNEL);
-	if (!notify)
-		return -ENOMEM;
-
-	nv_ioctl(client, "notify new size %d\n", size);
-	if (nvif_unpack(req->v0, 0, 0, true)) {
-		nv_ioctl(client, "notify new vers %d reply %d route %02x "
-				 "token %llx\n", req->v0.version,
-			 req->v0.reply, req->v0.route, req->v0.token);
-		notify->version = req->v0.version;
-		notify->size = sizeof(notify->rep.v0);
-		notify->rep.v0.version = req->v0.version;
-		notify->rep.v0.route = req->v0.route;
-		notify->rep.v0.token = req->v0.token;
-		reply = req->v0.reply;
-	}
-
-	if (ret == 0) {
-		ret = nvkm_notify_init(object, event, nvkm_client_notify,
-				       false, data, size, reply, &notify->n);
-		if (ret == 0) {
-			client->notify[index] = notify;
-			notify->client = client;
-			return index;
-		}
-	}
-
-	kfree(notify);
-	return ret;
-}
-
-static int
-nouveau_client_devlist(struct nouveau_object *object, void *data, u32 size)
-{
-	union {
-		struct nv_client_devlist_v0 v0;
-	} *args = data;
-	int ret;
-
-	nv_ioctl(object, "client devlist size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, true)) {
-		nv_ioctl(object, "client devlist vers %d count %d\n",
-			 args->v0.version, args->v0.count);
-		if (size == sizeof(args->v0.device[0]) * args->v0.count) {
-			ret = nouveau_device_list(args->v0.device,
-						  args->v0.count);
-			if (ret >= 0) {
-				args->v0.count = ret;
-				ret = 0;
-			}
-		} else {
-			ret = -EINVAL;
-		}
-	}
-
-	return ret;
-}
-
-static int
-nouveau_client_mthd(struct nouveau_object *object, u32 mthd,
-		    void *data, u32 size)
-{
-	switch (mthd) {
-	case NV_CLIENT_DEVLIST:
-		return nouveau_client_devlist(object, data, size);
-	default:
-		break;
-	}
-	return -EINVAL;
-}
-
-static void
-nouveau_client_dtor(struct nouveau_object *object)
-{
-	struct nouveau_client *client = (void *)object;
-	int i;
-	for (i = 0; i < ARRAY_SIZE(client->notify); i++)
-		nvkm_client_notify_del(client, i);
-	nouveau_object_ref(NULL, &client->device);
-	nouveau_handle_destroy(client->root);
-	nouveau_namedb_destroy(&client->base);
-}
-
-static struct nouveau_oclass
-nouveau_client_oclass = {
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.dtor = nouveau_client_dtor,
-		.mthd = nouveau_client_mthd,
-	},
-};
-
-int
-nouveau_client_create_(const char *name, u64 devname, const char *cfg,
-		       const char *dbg, int length, void **pobject)
-{
-	struct nouveau_object *device;
-	struct nouveau_client *client;
-	int ret;
-
-	device = (void *)nouveau_device_find(devname);
-	if (!device)
-		return -ENODEV;
-
-	ret = nouveau_namedb_create_(NULL, NULL, &nouveau_client_oclass,
-				     NV_CLIENT_CLASS, NULL,
-				     (1ULL << NVDEV_ENGINE_DEVICE),
-				     length, pobject);
-	client = *pobject;
-	if (ret)
-		return ret;
-
-	ret = nouveau_handle_create(nv_object(client), ~0, ~0,
-				    nv_object(client), &client->root);
-	if (ret)
-		return ret;
-
-	/* prevent init/fini being called, os in in charge of this */
-	atomic_set(&nv_object(client)->usecount, 2);
-
-	nouveau_object_ref(device, &client->device);
-	snprintf(client->name, sizeof(client->name), "%s", name);
-	client->debug = nouveau_dbgopt(dbg, "CLIENT");
-	return 0;
-}
-
-int
-nouveau_client_init(struct nouveau_client *client)
-{
-	int ret;
-	nv_debug(client, "init running\n");
-	ret = nouveau_handle_init(client->root);
-	nv_debug(client, "init completed with %d\n", ret);
-	return ret;
-}
-
-int
-nouveau_client_fini(struct nouveau_client *client, bool suspend)
-{
-	const char *name[2] = { "fini", "suspend" };
-	int ret, i;
-	nv_debug(client, "%s running\n", name[suspend]);
-	nv_debug(client, "%s notify\n", name[suspend]);
-	for (i = 0; i < ARRAY_SIZE(client->notify); i++)
-		nvkm_client_notify_put(client, i);
-	nv_debug(client, "%s object\n", name[suspend]);
-	ret = nouveau_handle_fini(client->root, suspend);
-	nv_debug(client, "%s completed with %d\n", name[suspend], ret);
-	return ret;
-}
-
-const char *
-nouveau_client_name(void *obj)
-{
-	const char *client_name = "unknown";
-	struct nouveau_client *client = nouveau_client(obj);
-	if (client)
-		client_name = client->name;
-	return client_name;
-}
diff --git a/drivers/gpu/drm/nouveau/core/core/engctx.c b/drivers/gpu/drm/nouveau/core/core/engctx.c
deleted file mode 100644
index 84c71fad2b6c..000000000000
--- a/drivers/gpu/drm/nouveau/core/core/engctx.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/object.h>
-#include <core/namedb.h>
-#include <core/handle.h>
-#include <core/client.h>
-#include <core/engctx.h>
-
-#include <subdev/vm.h>
-
-static inline int
-nouveau_engctx_exists(struct nouveau_object *parent,
-		      struct nouveau_engine *engine, void **pobject)
-{
-	struct nouveau_engctx *engctx;
-	struct nouveau_object *parctx;
-
-	list_for_each_entry(engctx, &engine->contexts, head) {
-		parctx = nv_pclass(nv_object(engctx), NV_PARENT_CLASS);
-		if (parctx == parent) {
-			atomic_inc(&nv_object(engctx)->refcount);
-			*pobject = engctx;
-			return 1;
-		}
-	}
-
-	return 0;
-}
-
-int
-nouveau_engctx_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engobj,
-		       struct nouveau_oclass *oclass,
-		       struct nouveau_object *pargpu,
-		       u32 size, u32 align, u32 flags,
-		       int length, void **pobject)
-{
-	struct nouveau_client *client = nouveau_client(parent);
-	struct nouveau_engine *engine = nv_engine(engobj);
-	struct nouveau_object *engctx;
-	unsigned long save;
-	int ret;
-
-	/* check if this engine already has a context for the parent object,
-	 * and reference it instead of creating a new one
-	 */
-	spin_lock_irqsave(&engine->lock, save);
-	ret = nouveau_engctx_exists(parent, engine, pobject);
-	spin_unlock_irqrestore(&engine->lock, save);
-	if (ret)
-		return ret;
-
-	/* create the new context, supports creating both raw objects and
-	 * objects backed by instance memory
-	 */
-	if (size) {
-		ret = nouveau_gpuobj_create_(parent, engobj, oclass,
-					     NV_ENGCTX_CLASS,
-					     pargpu, size, align, flags,
-					     length, pobject);
-	} else {
-		ret = nouveau_object_create_(parent, engobj, oclass,
-					     NV_ENGCTX_CLASS, length, pobject);
-	}
-
-	engctx = *pobject;
-	if (ret)
-		return ret;
-
-	/* must take the lock again and re-check a context doesn't already
-	 * exist (in case of a race) - the lock had to be dropped before as
-	 * it's not possible to allocate the object with it held.
-	 */
-	spin_lock_irqsave(&engine->lock, save);
-	ret = nouveau_engctx_exists(parent, engine, pobject);
-	if (ret) {
-		spin_unlock_irqrestore(&engine->lock, save);
-		nouveau_object_ref(NULL, &engctx);
-		return ret;
-	}
-
-	if (client->vm)
-		atomic_inc(&client->vm->engref[nv_engidx(engobj)]);
-	list_add(&nv_engctx(engctx)->head, &engine->contexts);
-	nv_engctx(engctx)->addr = ~0ULL;
-	spin_unlock_irqrestore(&engine->lock, save);
-	return 0;
-}
-
-void
-nouveau_engctx_destroy(struct nouveau_engctx *engctx)
-{
-	struct nouveau_object *engobj = nv_object(engctx)->engine;
-	struct nouveau_engine *engine = nv_engine(engobj);
-	struct nouveau_client *client = nouveau_client(engctx);
-	unsigned long save;
-
-	nouveau_gpuobj_unmap(&engctx->vma);
-	spin_lock_irqsave(&engine->lock, save);
-	list_del(&engctx->head);
-	spin_unlock_irqrestore(&engine->lock, save);
-
-	if (client->vm)
-		atomic_dec(&client->vm->engref[nv_engidx(engobj)]);
-
-	if (engctx->base.size)
-		nouveau_gpuobj_destroy(&engctx->base);
-	else
-		nouveau_object_destroy(&engctx->base.base);
-}
-
-int
-nouveau_engctx_init(struct nouveau_engctx *engctx)
-{
-	struct nouveau_object *object = nv_object(engctx);
-	struct nouveau_subdev *subdev = nv_subdev(object->engine);
-	struct nouveau_object *parent;
-	struct nouveau_subdev *pardev;
-	int ret;
-
-	ret = nouveau_gpuobj_init(&engctx->base);
-	if (ret)
-		return ret;
-
-	parent = nv_pclass(object->parent, NV_PARENT_CLASS);
-	pardev = nv_subdev(parent->engine);
-	if (nv_parent(parent)->context_attach) {
-		mutex_lock(&pardev->mutex);
-		ret = nv_parent(parent)->context_attach(parent, object);
-		mutex_unlock(&pardev->mutex);
-	}
-
-	if (ret) {
-		nv_error(parent, "failed to attach %s context, %d\n",
-			 subdev->name, ret);
-		return ret;
-	}
-
-	nv_debug(parent, "attached %s context\n", subdev->name);
-	return 0;
-}
-
-int
-nouveau_engctx_fini(struct nouveau_engctx *engctx, bool suspend)
-{
-	struct nouveau_object *object = nv_object(engctx);
-	struct nouveau_subdev *subdev = nv_subdev(object->engine);
-	struct nouveau_object *parent;
-	struct nouveau_subdev *pardev;
-	int ret = 0;
-
-	parent = nv_pclass(object->parent, NV_PARENT_CLASS);
-	pardev = nv_subdev(parent->engine);
-	if (nv_parent(parent)->context_detach) {
-		mutex_lock(&pardev->mutex);
-		ret = nv_parent(parent)->context_detach(parent, suspend, object);
-		mutex_unlock(&pardev->mutex);
-	}
-
-	if (ret) {
-		nv_error(parent, "failed to detach %s context, %d\n",
-			 subdev->name, ret);
-		return ret;
-	}
-
-	nv_debug(parent, "detached %s context\n", subdev->name);
-	return nouveau_gpuobj_fini(&engctx->base, suspend);
-}
-
-int
-_nouveau_engctx_ctor(struct nouveau_object *parent,
-		     struct nouveau_object *engine,
-		     struct nouveau_oclass *oclass, void *data, u32 size,
-		     struct nouveau_object **pobject)
-{
-	struct nouveau_engctx *engctx;
-	int ret;
-
-	ret = nouveau_engctx_create(parent, engine, oclass, NULL, 256, 256,
-				    NVOBJ_FLAG_ZERO_ALLOC, &engctx);
-	*pobject = nv_object(engctx);
-	return ret;
-}
-
-void
-_nouveau_engctx_dtor(struct nouveau_object *object)
-{
-	nouveau_engctx_destroy(nv_engctx(object));
-}
-
-int
-_nouveau_engctx_init(struct nouveau_object *object)
-{
-	return nouveau_engctx_init(nv_engctx(object));
-}
-
-
-int
-_nouveau_engctx_fini(struct nouveau_object *object, bool suspend)
-{
-	return nouveau_engctx_fini(nv_engctx(object), suspend);
-}
-
-struct nouveau_object *
-nouveau_engctx_get(struct nouveau_engine *engine, u64 addr)
-{
-	struct nouveau_engctx *engctx;
-	unsigned long flags;
-
-	spin_lock_irqsave(&engine->lock, flags);
-	list_for_each_entry(engctx, &engine->contexts, head) {
-		if (engctx->addr == addr) {
-			engctx->save = flags;
-			return nv_object(engctx);
-		}
-	}
-	spin_unlock_irqrestore(&engine->lock, flags);
-	return NULL;
-}
-
-void
-nouveau_engctx_put(struct nouveau_object *object)
-{
-	if (object) {
-		struct nouveau_engine *engine = nv_engine(object->engine);
-		struct nouveau_engctx *engctx = nv_engctx(object);
-		spin_unlock_irqrestore(&engine->lock, engctx->save);
-	}
-}
diff --git a/drivers/gpu/drm/nouveau/core/core/engine.c b/drivers/gpu/drm/nouveau/core/core/engine.c
deleted file mode 100644
index 1f6954ae9dd3..000000000000
--- a/drivers/gpu/drm/nouveau/core/core/engine.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/device.h>
-#include <core/engine.h>
-#include <core/option.h>
-
-int
-nouveau_engine_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engobj,
-		       struct nouveau_oclass *oclass, bool enable,
-		       const char *iname, const char *fname,
-		       int length, void **pobject)
-{
-	struct nouveau_engine *engine;
-	int ret;
-
-	ret = nouveau_subdev_create_(parent, engobj, oclass, NV_ENGINE_CLASS,
-				     iname, fname, length, pobject);
-	engine = *pobject;
-	if (ret)
-		return ret;
-
-	if (parent) {
-		struct nouveau_device *device = nv_device(parent);
-		int engidx = nv_engidx(nv_object(engine));
-
-		if (device->disable_mask & (1ULL << engidx)) {
-			if (!nouveau_boolopt(device->cfgopt, iname, false)) {
-				nv_debug(engine, "engine disabled by hw/fw\n");
-				return -ENODEV;
-			}
-
-			nv_warn(engine, "ignoring hw/fw engine disable\n");
-		}
-
-		if (!nouveau_boolopt(device->cfgopt, iname, enable)) {
-			if (!enable)
-				nv_warn(engine, "disabled, %s=1 to enable\n", iname);
-			return -ENODEV;
-		}
-	}
-
-	INIT_LIST_HEAD(&engine->contexts);
-	spin_lock_init(&engine->lock);
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/core/enum.c b/drivers/gpu/drm/nouveau/core/core/enum.c
deleted file mode 100644
index dd434790ccc4..000000000000
--- a/drivers/gpu/drm/nouveau/core/core/enum.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 2010 Nouveau Project
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include <core/os.h>
-#include <core/enum.h>
-
-const struct nouveau_enum *
-nouveau_enum_find(const struct nouveau_enum *en, u32 value)
-{
-	while (en->name) {
-		if (en->value == value)
-			return en;
-		en++;
-	}
-
-	return NULL;
-}
-
-const struct nouveau_enum *
-nouveau_enum_print(const struct nouveau_enum *en, u32 value)
-{
-	en = nouveau_enum_find(en, value);
-	if (en)
-		pr_cont("%s", en->name);
-	else
-		pr_cont("(unknown enum 0x%08x)", value);
-	return en;
-}
-
-void
-nouveau_bitfield_print(const struct nouveau_bitfield *bf, u32 value)
-{
-	while (bf->name) {
-		if (value & bf->mask) {
-			pr_cont(" %s", bf->name);
-			value &= ~bf->mask;
-		}
-
-		bf++;
-	}
-
-	if (value)
-		pr_cont(" (unknown bits 0x%08x)", value);
-}
diff --git a/drivers/gpu/drm/nouveau/core/core/event.c b/drivers/gpu/drm/nouveau/core/core/event.c
deleted file mode 100644
index 760947e380c9..000000000000
--- a/drivers/gpu/drm/nouveau/core/core/event.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright 2013-2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <core/object.h>
-#include <core/event.h>
-
-void
-nvkm_event_put(struct nvkm_event *event, u32 types, int index)
-{
-	assert_spin_locked(&event->refs_lock);
-	while (types) {
-		int type = __ffs(types); types &= ~(1 << type);
-		if (--event->refs[index * event->types_nr + type] == 0) {
-			if (event->func->fini)
-				event->func->fini(event, 1 << type, index);
-		}
-	}
-}
-
-void
-nvkm_event_get(struct nvkm_event *event, u32 types, int index)
-{
-	assert_spin_locked(&event->refs_lock);
-	while (types) {
-		int type = __ffs(types); types &= ~(1 << type);
-		if (++event->refs[index * event->types_nr + type] == 1) {
-			if (event->func->init)
-				event->func->init(event, 1 << type, index);
-		}
-	}
-}
-
-void
-nvkm_event_send(struct nvkm_event *event, u32 types, int index,
-		void *data, u32 size)
-{
-	struct nvkm_notify *notify;
-	unsigned long flags;
-
-	if (!event->refs || WARN_ON(index >= event->index_nr))
-		return;
-
-	spin_lock_irqsave(&event->list_lock, flags);
-	list_for_each_entry(notify, &event->list, head) {
-		if (notify->index == index && (notify->types & types)) {
-			if (event->func->send) {
-				event->func->send(data, size, notify);
-				continue;
-			}
-			nvkm_notify_send(notify, data, size);
-		}
-	}
-	spin_unlock_irqrestore(&event->list_lock, flags);
-}
-
-void
-nvkm_event_fini(struct nvkm_event *event)
-{
-	if (event->refs) {
-		kfree(event->refs);
-		event->refs = NULL;
-	}
-}
-
-int
-nvkm_event_init(const struct nvkm_event_func *func, int types_nr, int index_nr,
-		struct nvkm_event *event)
-{
-	event->refs = kzalloc(sizeof(*event->refs) * index_nr * types_nr,
-			      GFP_KERNEL);
-	if (!event->refs)
-		return -ENOMEM;
-
-	event->func = func;
-	event->types_nr = types_nr;
-	event->index_nr = index_nr;
-	spin_lock_init(&event->refs_lock);
-	spin_lock_init(&event->list_lock);
-	INIT_LIST_HEAD(&event->list);
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/core/gpuobj.c b/drivers/gpu/drm/nouveau/core/core/gpuobj.c
deleted file mode 100644
index daee87702502..000000000000
--- a/drivers/gpu/drm/nouveau/core/core/gpuobj.c
+++ /dev/null
@@ -1,323 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/object.h>
-#include <core/gpuobj.h>
-
-#include <subdev/instmem.h>
-#include <subdev/bar.h>
-#include <subdev/vm.h>
-
-void
-nouveau_gpuobj_destroy(struct nouveau_gpuobj *gpuobj)
-{
-	int i;
-
-	if (gpuobj->flags & NVOBJ_FLAG_ZERO_FREE) {
-		for (i = 0; i < gpuobj->size; i += 4)
-			nv_wo32(gpuobj, i, 0x00000000);
-	}
-
-	if (gpuobj->node) {
-		nouveau_mm_free(&nv_gpuobj(gpuobj->parent)->heap,
-				&gpuobj->node);
-	}
-
-	if (gpuobj->heap.block_size)
-		nouveau_mm_fini(&gpuobj->heap);
-
-	nouveau_object_destroy(&gpuobj->base);
-}
-
-int
-nouveau_gpuobj_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, u32 pclass,
-		       struct nouveau_object *pargpu,
-		       u32 size, u32 align, u32 flags,
-		       int length, void **pobject)
-{
-	struct nouveau_instmem *imem = nouveau_instmem(parent);
-	struct nouveau_bar *bar = nouveau_bar(parent);
-	struct nouveau_gpuobj *gpuobj;
-	struct nouveau_mm *heap = NULL;
-	int ret, i;
-	u64 addr;
-
-	*pobject = NULL;
-
-	if (pargpu) {
-		while ((pargpu = nv_pclass(pargpu, NV_GPUOBJ_CLASS))) {
-			if (nv_gpuobj(pargpu)->heap.block_size)
-				break;
-			pargpu = pargpu->parent;
-		}
-
-		if (unlikely(pargpu == NULL)) {
-			nv_error(parent, "no gpuobj heap\n");
-			return -EINVAL;
-		}
-
-		addr =  nv_gpuobj(pargpu)->addr;
-		heap = &nv_gpuobj(pargpu)->heap;
-		atomic_inc(&parent->refcount);
-	} else {
-		ret = imem->alloc(imem, parent, size, align, &parent);
-		pargpu = parent;
-		if (ret)
-			return ret;
-
-		addr = nv_memobj(pargpu)->addr;
-		size = nv_memobj(pargpu)->size;
-
-		if (bar && bar->alloc) {
-			struct nouveau_instobj *iobj = (void *)parent;
-			struct nouveau_mem **mem = (void *)(iobj + 1);
-			struct nouveau_mem *node = *mem;
-			if (!bar->alloc(bar, parent, node, &pargpu)) {
-				nouveau_object_ref(NULL, &parent);
-				parent = pargpu;
-			}
-		}
-	}
-
-	ret = nouveau_object_create_(parent, engine, oclass, pclass |
-				     NV_GPUOBJ_CLASS, length, pobject);
-	nouveau_object_ref(NULL, &parent);
-	gpuobj = *pobject;
-	if (ret)
-		return ret;
-
-	gpuobj->parent = pargpu;
-	gpuobj->flags = flags;
-	gpuobj->addr = addr;
-	gpuobj->size = size;
-
-	if (heap) {
-		ret = nouveau_mm_head(heap, 0, 1, size, size,
-				      max(align, (u32)1), &gpuobj->node);
-		if (ret)
-			return ret;
-
-		gpuobj->addr += gpuobj->node->offset;
-	}
-
-	if (gpuobj->flags & NVOBJ_FLAG_HEAP) {
-		ret = nouveau_mm_init(&gpuobj->heap, 0, gpuobj->size, 1);
-		if (ret)
-			return ret;
-	}
-
-	if (flags & NVOBJ_FLAG_ZERO_ALLOC) {
-		for (i = 0; i < gpuobj->size; i += 4)
-			nv_wo32(gpuobj, i, 0x00000000);
-	}
-
-	return ret;
-}
-
-struct nouveau_gpuobj_class {
-	struct nouveau_object *pargpu;
-	u64 size;
-	u32 align;
-	u32 flags;
-};
-
-static int
-_nouveau_gpuobj_ctor(struct nouveau_object *parent,
-		     struct nouveau_object *engine,
-		     struct nouveau_oclass *oclass, void *data, u32 size,
-		     struct nouveau_object **pobject)
-{
-	struct nouveau_gpuobj_class *args = data;
-	struct nouveau_gpuobj *object;
-	int ret;
-
-	ret = nouveau_gpuobj_create(parent, engine, oclass, 0, args->pargpu,
-				    args->size, args->align, args->flags,
-				    &object);
-	*pobject = nv_object(object);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-void
-_nouveau_gpuobj_dtor(struct nouveau_object *object)
-{
-	nouveau_gpuobj_destroy(nv_gpuobj(object));
-}
-
-int
-_nouveau_gpuobj_init(struct nouveau_object *object)
-{
-	return nouveau_gpuobj_init(nv_gpuobj(object));
-}
-
-int
-_nouveau_gpuobj_fini(struct nouveau_object *object, bool suspend)
-{
-	return nouveau_gpuobj_fini(nv_gpuobj(object), suspend);
-}
-
-u32
-_nouveau_gpuobj_rd32(struct nouveau_object *object, u64 addr)
-{
-	struct nouveau_gpuobj *gpuobj = nv_gpuobj(object);
-	struct nouveau_ofuncs *pfuncs = nv_ofuncs(gpuobj->parent);
-	if (gpuobj->node)
-		addr += gpuobj->node->offset;
-	return pfuncs->rd32(gpuobj->parent, addr);
-}
-
-void
-_nouveau_gpuobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
-{
-	struct nouveau_gpuobj *gpuobj = nv_gpuobj(object);
-	struct nouveau_ofuncs *pfuncs = nv_ofuncs(gpuobj->parent);
-	if (gpuobj->node)
-		addr += gpuobj->node->offset;
-	pfuncs->wr32(gpuobj->parent, addr, data);
-}
-
-static struct nouveau_oclass
-_nouveau_gpuobj_oclass = {
-	.handle = 0x00000000,
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_gpuobj_ctor,
-		.dtor = _nouveau_gpuobj_dtor,
-		.init = _nouveau_gpuobj_init,
-		.fini = _nouveau_gpuobj_fini,
-		.rd32 = _nouveau_gpuobj_rd32,
-		.wr32 = _nouveau_gpuobj_wr32,
-	},
-};
-
-int
-nouveau_gpuobj_new(struct nouveau_object *parent, struct nouveau_object *pargpu,
-		   u32 size, u32 align, u32 flags,
-		   struct nouveau_gpuobj **pgpuobj)
-{
-	struct nouveau_object *engine = parent;
-	struct nouveau_gpuobj_class args = {
-		.pargpu = pargpu,
-		.size = size,
-		.align = align,
-		.flags = flags,
-	};
-
-	if (!nv_iclass(engine, NV_SUBDEV_CLASS))
-		engine = engine->engine;
-	BUG_ON(engine == NULL);
-
-	return nouveau_object_ctor(parent, engine, &_nouveau_gpuobj_oclass,
-				   &args, sizeof(args),
-				   (struct nouveau_object **)pgpuobj);
-}
-
-int
-nouveau_gpuobj_map(struct nouveau_gpuobj *gpuobj, u32 access,
-		   struct nouveau_vma *vma)
-{
-	struct nouveau_bar *bar = nouveau_bar(gpuobj);
-	int ret = -EINVAL;
-
-	if (bar && bar->umap) {
-		struct nouveau_instobj *iobj = (void *)
-			nv_pclass(nv_object(gpuobj), NV_MEMOBJ_CLASS);
-		struct nouveau_mem **mem = (void *)(iobj + 1);
-		ret = bar->umap(bar, *mem, access, vma);
-	}
-
-	return ret;
-}
-
-int
-nouveau_gpuobj_map_vm(struct nouveau_gpuobj *gpuobj, struct nouveau_vm *vm,
-		      u32 access, struct nouveau_vma *vma)
-{
-	struct nouveau_instobj *iobj = (void *)
-		nv_pclass(nv_object(gpuobj), NV_MEMOBJ_CLASS);
-	struct nouveau_mem **mem = (void *)(iobj + 1);
-	int ret;
-
-	ret = nouveau_vm_get(vm, gpuobj->size, 12, access, vma);
-	if (ret)
-		return ret;
-
-	nouveau_vm_map(vma, *mem);
-	return 0;
-}
-
-void
-nouveau_gpuobj_unmap(struct nouveau_vma *vma)
-{
-	if (vma->node) {
-		nouveau_vm_unmap(vma);
-		nouveau_vm_put(vma);
-	}
-}
-
-/* the below is basically only here to support sharing the paged dma object
- * for PCI(E)GART on <=nv4x chipsets, and should *not* be expected to work
- * anywhere else.
- */
-
-static void
-nouveau_gpudup_dtor(struct nouveau_object *object)
-{
-	struct nouveau_gpuobj *gpuobj = (void *)object;
-	nouveau_object_ref(NULL, &gpuobj->parent);
-	nouveau_object_destroy(&gpuobj->base);
-}
-
-static struct nouveau_oclass
-nouveau_gpudup_oclass = {
-	.handle = NV_GPUOBJ_CLASS,
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.dtor = nouveau_gpudup_dtor,
-		.init = nouveau_object_init,
-		.fini = nouveau_object_fini,
-	},
-};
-
-int
-nouveau_gpuobj_dup(struct nouveau_object *parent, struct nouveau_gpuobj *base,
-		   struct nouveau_gpuobj **pgpuobj)
-{
-	struct nouveau_gpuobj *gpuobj;
-	int ret;
-
-	ret = nouveau_object_create(parent, parent->engine,
-				   &nouveau_gpudup_oclass, 0, &gpuobj);
-	*pgpuobj = gpuobj;
-	if (ret)
-		return ret;
-
-	nouveau_object_ref(nv_object(base), &gpuobj->parent);
-	gpuobj->addr = base->addr;
-	gpuobj->size = base->size;
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/core/handle.c b/drivers/gpu/drm/nouveau/core/core/handle.c
deleted file mode 100644
index 13f816cb08bd..000000000000
--- a/drivers/gpu/drm/nouveau/core/core/handle.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/object.h>
-#include <core/handle.h>
-#include <core/client.h>
-
-#define hprintk(h,l,f,a...) do {                                               \
-	struct nouveau_client *c = nouveau_client((h)->object);                \
-	struct nouveau_handle *p = (h)->parent; u32 n = p ? p->name : ~0;      \
-	nv_printk((c), l, "0x%08x:0x%08x "f, n, (h)->name, ##a);               \
-} while(0)
-
-int
-nouveau_handle_init(struct nouveau_handle *handle)
-{
-	struct nouveau_handle *item;
-	int ret;
-
-	hprintk(handle, TRACE, "init running\n");
-	ret = nouveau_object_inc(handle->object);
-	if (ret)
-		return ret;
-
-	hprintk(handle, TRACE, "init children\n");
-	list_for_each_entry(item, &handle->tree, head) {
-		ret = nouveau_handle_init(item);
-		if (ret)
-			goto fail;
-	}
-
-	hprintk(handle, TRACE, "init completed\n");
-	return 0;
-fail:
-	hprintk(handle, ERROR, "init failed with %d\n", ret);
-	list_for_each_entry_continue_reverse(item, &handle->tree, head) {
-		nouveau_handle_fini(item, false);
-	}
-
-	nouveau_object_dec(handle->object, false);
-	return ret;
-}
-
-int
-nouveau_handle_fini(struct nouveau_handle *handle, bool suspend)
-{
-	static char *name[2] = { "fini", "suspend" };
-	struct nouveau_handle *item;
-	int ret;
-
-	hprintk(handle, TRACE, "%s children\n", name[suspend]);
-	list_for_each_entry(item, &handle->tree, head) {
-		ret = nouveau_handle_fini(item, suspend);
-		if (ret && suspend)
-			goto fail;
-	}
-
-	hprintk(handle, TRACE, "%s running\n", name[suspend]);
-	if (handle->object) {
-		ret = nouveau_object_dec(handle->object, suspend);
-		if (ret && suspend)
-			goto fail;
-	}
-
-	hprintk(handle, TRACE, "%s completed\n", name[suspend]);
-	return 0;
-fail:
-	hprintk(handle, ERROR, "%s failed with %d\n", name[suspend], ret);
-	list_for_each_entry_continue_reverse(item, &handle->tree, head) {
-		int rret = nouveau_handle_init(item);
-		if (rret)
-			hprintk(handle, FATAL, "failed to restart, %d\n", rret);
-	}
-
-	return ret;
-}
-
-int
-nouveau_handle_create(struct nouveau_object *parent, u32 _parent, u32 _handle,
-		      struct nouveau_object *object,
-		      struct nouveau_handle **phandle)
-{
-	struct nouveau_object *namedb;
-	struct nouveau_handle *handle;
-	int ret;
-
-	namedb = parent;
-	while (!nv_iclass(namedb, NV_NAMEDB_CLASS))
-		namedb = namedb->parent;
-
-	handle = kzalloc(sizeof(*handle), GFP_KERNEL);
-	if (!handle)
-		return -ENOMEM;
-
-	INIT_LIST_HEAD(&handle->head);
-	INIT_LIST_HEAD(&handle->tree);
-	handle->name = _handle;
-	handle->priv = ~0;
-
-	ret = nouveau_namedb_insert(nv_namedb(namedb), _handle, object, handle);
-	if (ret) {
-		kfree(handle);
-		return ret;
-	}
-
-	if (nv_parent(parent)->object_attach) {
-		ret = nv_parent(parent)->object_attach(parent, object, _handle);
-		if (ret < 0) {
-			nouveau_handle_destroy(handle);
-			return ret;
-		}
-
-		handle->priv = ret;
-	}
-
-	if (object != namedb) {
-		while (!nv_iclass(namedb, NV_CLIENT_CLASS))
-			namedb = namedb->parent;
-
-		handle->parent = nouveau_namedb_get(nv_namedb(namedb), _parent);
-		if (handle->parent) {
-			list_add(&handle->head, &handle->parent->tree);
-			nouveau_namedb_put(handle->parent);
-		}
-	}
-
-	hprintk(handle, TRACE, "created\n");
-	*phandle = handle;
-	return 0;
-}
-
-void
-nouveau_handle_destroy(struct nouveau_handle *handle)
-{
-	struct nouveau_handle *item, *temp;
-
-	hprintk(handle, TRACE, "destroy running\n");
-	list_for_each_entry_safe(item, temp, &handle->tree, head) {
-		nouveau_handle_destroy(item);
-	}
-	list_del(&handle->head);
-
-	if (handle->priv != ~0) {
-		struct nouveau_object *parent = handle->parent->object;
-		nv_parent(parent)->object_detach(parent, handle->priv);
-	}
-
-	hprintk(handle, TRACE, "destroy completed\n");
-	nouveau_namedb_remove(handle);
-	kfree(handle);
-}
-
-struct nouveau_object *
-nouveau_handle_ref(struct nouveau_object *parent, u32 name)
-{
-	struct nouveau_object *object = NULL;
-	struct nouveau_handle *handle;
-
-	while (!nv_iclass(parent, NV_NAMEDB_CLASS))
-		parent = parent->parent;
-
-	handle = nouveau_namedb_get(nv_namedb(parent), name);
-	if (handle) {
-		nouveau_object_ref(handle->object, &object);
-		nouveau_namedb_put(handle);
-	}
-
-	return object;
-}
-
-struct nouveau_handle *
-nouveau_handle_get_class(struct nouveau_object *engctx, u16 oclass)
-{
-	struct nouveau_namedb *namedb;
-	if (engctx && (namedb = (void *)nv_pclass(engctx, NV_NAMEDB_CLASS)))
-		return nouveau_namedb_get_class(namedb, oclass);
-	return NULL;
-}
-
-struct nouveau_handle *
-nouveau_handle_get_vinst(struct nouveau_object *engctx, u64 vinst)
-{
-	struct nouveau_namedb *namedb;
-	if (engctx && (namedb = (void *)nv_pclass(engctx, NV_NAMEDB_CLASS)))
-		return nouveau_namedb_get_vinst(namedb, vinst);
-	return NULL;
-}
-
-struct nouveau_handle *
-nouveau_handle_get_cinst(struct nouveau_object *engctx, u32 cinst)
-{
-	struct nouveau_namedb *namedb;
-	if (engctx && (namedb = (void *)nv_pclass(engctx, NV_NAMEDB_CLASS)))
-		return nouveau_namedb_get_cinst(namedb, cinst);
-	return NULL;
-}
-
-void
-nouveau_handle_put(struct nouveau_handle *handle)
-{
-	if (handle)
-		nouveau_namedb_put(handle);
-}
diff --git a/drivers/gpu/drm/nouveau/core/core/ioctl.c b/drivers/gpu/drm/nouveau/core/core/ioctl.c
deleted file mode 100644
index 692aa92dd850..000000000000
--- a/drivers/gpu/drm/nouveau/core/core/ioctl.c
+++ /dev/null
@@ -1,530 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include <core/object.h>
-#include <core/parent.h>
-#include <core/handle.h>
-#include <core/namedb.h>
-#include <core/client.h>
-#include <core/device.h>
-#include <core/ioctl.h>
-#include <core/event.h>
-
-#include <nvif/unpack.h>
-#include <nvif/ioctl.h>
-
-static int
-nvkm_ioctl_nop(struct nouveau_handle *handle, void *data, u32 size)
-{
-	struct nouveau_object *object = handle->object;
-	union {
-		struct nvif_ioctl_nop none;
-	} *args = data;
-	int ret;
-
-	nv_ioctl(object, "nop size %d\n", size);
-	if (nvif_unvers(args->none)) {
-		nv_ioctl(object, "nop\n");
-	}
-
-	return ret;
-}
-
-static int
-nvkm_ioctl_sclass(struct nouveau_handle *handle, void *data, u32 size)
-{
-	struct nouveau_object *object = handle->object;
-	union {
-		struct nvif_ioctl_sclass_v0 v0;
-	} *args = data;
-	int ret;
-
-	if (!nv_iclass(object, NV_PARENT_CLASS)) {
-		nv_debug(object, "cannot have children (sclass)\n");
-		return -ENODEV;
-	}
-
-	nv_ioctl(object, "sclass size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, true)) {
-		nv_ioctl(object, "sclass vers %d count %d\n",
-			 args->v0.version, args->v0.count);
-		if (size == args->v0.count * sizeof(args->v0.oclass[0])) {
-			ret = nouveau_parent_lclass(object, args->v0.oclass,
-							    args->v0.count);
-			if (ret >= 0) {
-				args->v0.count = ret;
-				ret = 0;
-			}
-		} else {
-			ret = -EINVAL;
-		}
-	}
-
-	return ret;
-}
-
-static int
-nvkm_ioctl_new(struct nouveau_handle *parent, void *data, u32 size)
-{
-	union {
-		struct nvif_ioctl_new_v0 v0;
-	} *args = data;
-	struct nouveau_client *client = nouveau_client(parent->object);
-	struct nouveau_object *engctx = NULL;
-	struct nouveau_object *object = NULL;
-	struct nouveau_object *engine;
-	struct nouveau_oclass *oclass;
-	struct nouveau_handle *handle;
-	u32 _handle, _oclass;
-	int ret;
-
-	nv_ioctl(client, "new size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, true)) {
-		_handle = args->v0.handle;
-		_oclass = args->v0.oclass;
-	} else
-		return ret;
-
-	nv_ioctl(client, "new vers %d handle %08x class %08x "
-			 "route %02x token %llx\n",
-		args->v0.version, _handle, _oclass,
-		args->v0.route, args->v0.token);
-
-	if (!nv_iclass(parent->object, NV_PARENT_CLASS)) {
-		nv_debug(parent->object, "cannot have children (ctor)\n");
-		ret = -ENODEV;
-		goto fail_class;
-	}
-
-	/* check that parent supports the requested subclass */
-	ret = nouveau_parent_sclass(parent->object, _oclass, &engine, &oclass);
-	if (ret) {
-		nv_debug(parent->object, "illegal class 0x%04x\n", _oclass);
-		goto fail_class;
-	}
-
-	/* make sure engine init has been completed *before* any objects
-	 * it controls are created - the constructors may depend on
-	 * state calculated at init (ie. default context construction)
-	 */
-	if (engine) {
-		ret = nouveau_object_inc(engine);
-		if (ret)
-			goto fail_class;
-	}
-
-	/* if engine requires it, create a context object to insert
-	 * between the parent and its children (eg. PGRAPH context)
-	 */
-	if (engine && nv_engine(engine)->cclass) {
-		ret = nouveau_object_ctor(parent->object, engine,
-					  nv_engine(engine)->cclass,
-					  data, size, &engctx);
-		if (ret)
-			goto fail_engctx;
-	} else {
-		nouveau_object_ref(parent->object, &engctx);
-	}
-
-	/* finally, create new object and bind it to its handle */
-	ret = nouveau_object_ctor(engctx, engine, oclass, data, size, &object);
-	client->data = object;
-	if (ret)
-		goto fail_ctor;
-
-	ret = nouveau_object_inc(object);
-	if (ret)
-		goto fail_init;
-
-	ret = nouveau_handle_create(parent->object, parent->name,
-				    _handle, object, &handle);
-	if (ret)
-		goto fail_handle;
-
-	ret = nouveau_handle_init(handle);
-	handle->route = args->v0.route;
-	handle->token = args->v0.token;
-	if (ret)
-		nouveau_handle_destroy(handle);
-
-fail_handle:
-	nouveau_object_dec(object, false);
-fail_init:
-	nouveau_object_ref(NULL, &object);
-fail_ctor:
-	nouveau_object_ref(NULL, &engctx);
-fail_engctx:
-	if (engine)
-		nouveau_object_dec(engine, false);
-fail_class:
-	return ret;
-}
-
-static int
-nvkm_ioctl_del(struct nouveau_handle *handle, void *data, u32 size)
-{
-	struct nouveau_object *object = handle->object;
-	union {
-		struct nvif_ioctl_del none;
-	} *args = data;
-	int ret;
-
-	nv_ioctl(object, "delete size %d\n", size);
-	if (nvif_unvers(args->none)) {
-		nv_ioctl(object, "delete\n");
-		nouveau_handle_fini(handle, false);
-		nouveau_handle_destroy(handle);
-	}
-
-	return ret;
-}
-
-static int
-nvkm_ioctl_mthd(struct nouveau_handle *handle, void *data, u32 size)
-{
-	struct nouveau_object *object = handle->object;
-	struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs;
-	union {
-		struct nvif_ioctl_mthd_v0 v0;
-	} *args = data;
-	int ret;
-
-	nv_ioctl(object, "mthd size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, true)) {
-		nv_ioctl(object, "mthd vers %d mthd %02x\n",
-			 args->v0.version, args->v0.method);
-		if (ret = -ENODEV, ofuncs->mthd)
-			ret = ofuncs->mthd(object, args->v0.method, data, size);
-	}
-
-	return ret;
-}
-
-
-static int
-nvkm_ioctl_rd(struct nouveau_handle *handle, void *data, u32 size)
-{
-	struct nouveau_object *object = handle->object;
-	struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs;
-	union {
-		struct nvif_ioctl_rd_v0 v0;
-	} *args = data;
-	int ret;
-
-	nv_ioctl(object, "rd size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "rd vers %d size %d addr %016llx\n",
-			args->v0.version, args->v0.size, args->v0.addr);
-		switch (args->v0.size) {
-		case 1:
-			if (ret = -ENODEV, ofuncs->rd08) {
-				args->v0.data = nv_ro08(object, args->v0.addr);
-				ret = 0;
-			}
-			break;
-		case 2:
-			if (ret = -ENODEV, ofuncs->rd16) {
-				args->v0.data = nv_ro16(object, args->v0.addr);
-				ret = 0;
-			}
-			break;
-		case 4:
-			if (ret = -ENODEV, ofuncs->rd32) {
-				args->v0.data = nv_ro32(object, args->v0.addr);
-				ret = 0;
-			}
-			break;
-		default:
-			ret = -EINVAL;
-			break;
-		}
-	}
-
-	return ret;
-}
-
-static int
-nvkm_ioctl_wr(struct nouveau_handle *handle, void *data, u32 size)
-{
-	struct nouveau_object *object = handle->object;
-	struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs;
-	union {
-		struct nvif_ioctl_wr_v0 v0;
-	} *args = data;
-	int ret;
-
-	nv_ioctl(object, "wr size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "wr vers %d size %d addr %016llx data %08x\n",
-			 args->v0.version, args->v0.size, args->v0.addr,
-			 args->v0.data);
-		switch (args->v0.size) {
-		case 1:
-			if (ret = -ENODEV, ofuncs->wr08) {
-				nv_wo08(object, args->v0.addr, args->v0.data);
-				ret = 0;
-			}
-			break;
-		case 2:
-			if (ret = -ENODEV, ofuncs->wr16) {
-				nv_wo16(object, args->v0.addr, args->v0.data);
-				ret = 0;
-			}
-			break;
-		case 4:
-			if (ret = -ENODEV, ofuncs->wr32) {
-				nv_wo32(object, args->v0.addr, args->v0.data);
-				ret = 0;
-			}
-			break;
-		default:
-			ret = -EINVAL;
-			break;
-		}
-	}
-
-	return ret;
-}
-
-static int
-nvkm_ioctl_map(struct nouveau_handle *handle, void *data, u32 size)
-{
-	struct nouveau_object *object = handle->object;
-	struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs;
-	union {
-		struct nvif_ioctl_map_v0 v0;
-	} *args = data;
-	int ret;
-
-	nv_ioctl(object, "map size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "map vers %d\n", args->v0.version);
-		if (ret = -ENODEV, ofuncs->map) {
-			ret = ofuncs->map(object, &args->v0.handle,
-						  &args->v0.length);
-		}
-	}
-
-	return ret;
-}
-
-static int
-nvkm_ioctl_unmap(struct nouveau_handle *handle, void *data, u32 size)
-{
-	struct nouveau_object *object = handle->object;
-	union {
-		struct nvif_ioctl_unmap none;
-	} *args = data;
-	int ret;
-
-	nv_ioctl(object, "unmap size %d\n", size);
-	if (nvif_unvers(args->none)) {
-		nv_ioctl(object, "unmap\n");
-	}
-
-	return ret;
-}
-
-static int
-nvkm_ioctl_ntfy_new(struct nouveau_handle *handle, void *data, u32 size)
-{
-	struct nouveau_object *object = handle->object;
-	struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs;
-	union {
-		struct nvif_ioctl_ntfy_new_v0 v0;
-	} *args = data;
-	struct nvkm_event *event;
-	int ret;
-
-	nv_ioctl(object, "ntfy new size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, true)) {
-		nv_ioctl(object, "ntfy new vers %d event %02x\n",
-			 args->v0.version, args->v0.event);
-		if (ret = -ENODEV, ofuncs->ntfy)
-			ret = ofuncs->ntfy(object, args->v0.event, &event);
-		if (ret == 0) {
-			ret = nvkm_client_notify_new(object, event, data, size);
-			if (ret >= 0) {
-				args->v0.index = ret;
-				ret = 0;
-			}
-		}
-	}
-
-	return ret;
-}
-
-static int
-nvkm_ioctl_ntfy_del(struct nouveau_handle *handle, void *data, u32 size)
-{
-	struct nouveau_client *client = nouveau_client(handle->object);
-	struct nouveau_object *object = handle->object;
-	union {
-		struct nvif_ioctl_ntfy_del_v0 v0;
-	} *args = data;
-	int ret;
-
-	nv_ioctl(object, "ntfy del size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "ntfy del vers %d index %d\n",
-			 args->v0.version, args->v0.index);
-		ret = nvkm_client_notify_del(client, args->v0.index);
-	}
-
-	return ret;
-}
-
-static int
-nvkm_ioctl_ntfy_get(struct nouveau_handle *handle, void *data, u32 size)
-{
-	struct nouveau_client *client = nouveau_client(handle->object);
-	struct nouveau_object *object = handle->object;
-	union {
-		struct nvif_ioctl_ntfy_get_v0 v0;
-	} *args = data;
-	int ret;
-
-	nv_ioctl(object, "ntfy get size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "ntfy get vers %d index %d\n",
-			 args->v0.version, args->v0.index);
-		ret = nvkm_client_notify_get(client, args->v0.index);
-	}
-
-	return ret;
-}
-
-static int
-nvkm_ioctl_ntfy_put(struct nouveau_handle *handle, void *data, u32 size)
-{
-	struct nouveau_client *client = nouveau_client(handle->object);
-	struct nouveau_object *object = handle->object;
-	union {
-		struct nvif_ioctl_ntfy_put_v0 v0;
-	} *args = data;
-	int ret;
-
-	nv_ioctl(object, "ntfy put size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "ntfy put vers %d index %d\n",
-			 args->v0.version, args->v0.index);
-		ret = nvkm_client_notify_put(client, args->v0.index);
-	}
-
-	return ret;
-}
-
-static struct {
-	int version;
-	int (*func)(struct nouveau_handle *, void *, u32);
-}
-nvkm_ioctl_v0[] = {
-	{ 0x00, nvkm_ioctl_nop },
-	{ 0x00, nvkm_ioctl_sclass },
-	{ 0x00, nvkm_ioctl_new },
-	{ 0x00, nvkm_ioctl_del },
-	{ 0x00, nvkm_ioctl_mthd },
-	{ 0x00, nvkm_ioctl_rd },
-	{ 0x00, nvkm_ioctl_wr },
-	{ 0x00, nvkm_ioctl_map },
-	{ 0x00, nvkm_ioctl_unmap },
-	{ 0x00, nvkm_ioctl_ntfy_new },
-	{ 0x00, nvkm_ioctl_ntfy_del },
-	{ 0x00, nvkm_ioctl_ntfy_get },
-	{ 0x00, nvkm_ioctl_ntfy_put },
-};
-
-static int
-nvkm_ioctl_path(struct nouveau_handle *parent, u32 type, u32 nr,
-		  u32 *path, void *data, u32 size,
-		  u8 owner, u8 *route, u64 *token)
-{
-	struct nouveau_handle *handle = parent;
-	struct nouveau_namedb *namedb;
-	struct nouveau_object *object;
-	int ret;
-
-	while ((object = parent->object), nr--) {
-		nv_ioctl(object, "path 0x%08x\n", path[nr]);
-		if (!nv_iclass(object, NV_PARENT_CLASS)) {
-			nv_debug(object, "cannot have children (path)\n");
-			return -EINVAL;
-		}
-
-		if (!(namedb = (void *)nv_pclass(object, NV_NAMEDB_CLASS)) ||
-		    !(handle = nouveau_namedb_get(namedb, path[nr]))) {
-			nv_debug(object, "handle 0x%08x not found\n", path[nr]);
-			return -ENOENT;
-		}
-		nouveau_namedb_put(handle);
-		parent = handle;
-	}
-
-	if (owner != NVIF_IOCTL_V0_OWNER_ANY &&
-	    owner != handle->route) {
-		nv_ioctl(object, "object route != owner\n");
-		return -EACCES;
-	}
-	*route = handle->route;
-	*token = handle->token;
-
-	if (ret = -EINVAL, type < ARRAY_SIZE(nvkm_ioctl_v0)) {
-		if (nvkm_ioctl_v0[type].version == 0) {
-			ret = nvkm_ioctl_v0[type].func(handle, data, size);
-		}
-	}
-
-	return ret;
-}
-
-int
-nvkm_ioctl(struct nouveau_client *client, bool supervisor,
-	   void *data, u32 size, void **hack)
-{
-	union {
-		struct nvif_ioctl_v0 v0;
-	} *args = data;
-	int ret;
-
-	client->super = supervisor;
-	nv_ioctl(client, "size %d\n", size);
-
-	if (nvif_unpack(args->v0, 0, 0, true)) {
-		nv_ioctl(client, "vers %d type %02x path %d owner %02x\n",
-			 args->v0.version, args->v0.type, args->v0.path_nr,
-			 args->v0.owner);
-		ret = nvkm_ioctl_path(client->root, args->v0.type,
-				      args->v0.path_nr, args->v0.path,
-				      data, size, args->v0.owner,
-				     &args->v0.route, &args->v0.token);
-	}
-
-	nv_ioctl(client, "return %d\n", ret);
-	if (hack) {
-		*hack = client->data;
-		client->data = NULL;
-	}
-	client->super = false;
-	return ret;
-}
diff --git a/drivers/gpu/drm/nouveau/core/core/mm.c b/drivers/gpu/drm/nouveau/core/core/mm.c
deleted file mode 100644
index b4f5db66d5b5..000000000000
--- a/drivers/gpu/drm/nouveau/core/core/mm.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "core/os.h"
-#include "core/mm.h"
-
-#define node(root, dir) ((root)->nl_entry.dir == &mm->nodes) ? NULL : \
-	list_entry((root)->nl_entry.dir, struct nouveau_mm_node, nl_entry)
-
-static void
-nouveau_mm_dump(struct nouveau_mm *mm, const char *header)
-{
-	struct nouveau_mm_node *node;
-
-	printk(KERN_ERR "nouveau: %s\n", header);
-	printk(KERN_ERR "nouveau: node list:\n");
-	list_for_each_entry(node, &mm->nodes, nl_entry) {
-		printk(KERN_ERR "nouveau: \t%08x %08x %d\n",
-		       node->offset, node->length, node->type);
-	}
-	printk(KERN_ERR "nouveau: free list:\n");
-	list_for_each_entry(node, &mm->free, fl_entry) {
-		printk(KERN_ERR "nouveau: \t%08x %08x %d\n",
-		       node->offset, node->length, node->type);
-	}
-}
-
-void
-nouveau_mm_free(struct nouveau_mm *mm, struct nouveau_mm_node **pthis)
-{
-	struct nouveau_mm_node *this = *pthis;
-
-	if (this) {
-		struct nouveau_mm_node *prev = node(this, prev);
-		struct nouveau_mm_node *next = node(this, next);
-
-		if (prev && prev->type == NVKM_MM_TYPE_NONE) {
-			prev->length += this->length;
-			list_del(&this->nl_entry);
-			kfree(this); this = prev;
-		}
-
-		if (next && next->type == NVKM_MM_TYPE_NONE) {
-			next->offset  = this->offset;
-			next->length += this->length;
-			if (this->type == NVKM_MM_TYPE_NONE)
-				list_del(&this->fl_entry);
-			list_del(&this->nl_entry);
-			kfree(this); this = NULL;
-		}
-
-		if (this && this->type != NVKM_MM_TYPE_NONE) {
-			list_for_each_entry(prev, &mm->free, fl_entry) {
-				if (this->offset < prev->offset)
-					break;
-			}
-
-			list_add_tail(&this->fl_entry, &prev->fl_entry);
-			this->type = NVKM_MM_TYPE_NONE;
-		}
-	}
-
-	*pthis = NULL;
-}
-
-static struct nouveau_mm_node *
-region_head(struct nouveau_mm *mm, struct nouveau_mm_node *a, u32 size)
-{
-	struct nouveau_mm_node *b;
-
-	if (a->length == size)
-		return a;
-
-	b = kmalloc(sizeof(*b), GFP_KERNEL);
-	if (unlikely(b == NULL))
-		return NULL;
-
-	b->offset = a->offset;
-	b->length = size;
-	b->heap   = a->heap;
-	b->type   = a->type;
-	a->offset += size;
-	a->length -= size;
-	list_add_tail(&b->nl_entry, &a->nl_entry);
-	if (b->type == NVKM_MM_TYPE_NONE)
-		list_add_tail(&b->fl_entry, &a->fl_entry);
-	return b;
-}
-
-int
-nouveau_mm_head(struct nouveau_mm *mm, u8 heap, u8 type, u32 size_max,
-		u32 size_min, u32 align, struct nouveau_mm_node **pnode)
-{
-	struct nouveau_mm_node *prev, *this, *next;
-	u32 mask = align - 1;
-	u32 splitoff;
-	u32 s, e;
-
-	BUG_ON(type == NVKM_MM_TYPE_NONE || type == NVKM_MM_TYPE_HOLE);
-
-	list_for_each_entry(this, &mm->free, fl_entry) {
-		if (unlikely(heap != NVKM_MM_HEAP_ANY)) {
-			if (this->heap != heap)
-				continue;
-		}
-		e = this->offset + this->length;
-		s = this->offset;
-
-		prev = node(this, prev);
-		if (prev && prev->type != type)
-			s = roundup(s, mm->block_size);
-
-		next = node(this, next);
-		if (next && next->type != type)
-			e = rounddown(e, mm->block_size);
-
-		s  = (s + mask) & ~mask;
-		e &= ~mask;
-		if (s > e || e - s < size_min)
-			continue;
-
-		splitoff = s - this->offset;
-		if (splitoff && !region_head(mm, this, splitoff))
-			return -ENOMEM;
-
-		this = region_head(mm, this, min(size_max, e - s));
-		if (!this)
-			return -ENOMEM;
-
-		this->type = type;
-		list_del(&this->fl_entry);
-		*pnode = this;
-		return 0;
-	}
-
-	return -ENOSPC;
-}
-
-static struct nouveau_mm_node *
-region_tail(struct nouveau_mm *mm, struct nouveau_mm_node *a, u32 size)
-{
-	struct nouveau_mm_node *b;
-
-	if (a->length == size)
-		return a;
-
-	b = kmalloc(sizeof(*b), GFP_KERNEL);
-	if (unlikely(b == NULL))
-		return NULL;
-
-	a->length -= size;
-	b->offset  = a->offset + a->length;
-	b->length  = size;
-	b->heap    = a->heap;
-	b->type    = a->type;
-
-	list_add(&b->nl_entry, &a->nl_entry);
-	if (b->type == NVKM_MM_TYPE_NONE)
-		list_add(&b->fl_entry, &a->fl_entry);
-	return b;
-}
-
-int
-nouveau_mm_tail(struct nouveau_mm *mm, u8 heap, u8 type, u32 size_max,
-		u32 size_min, u32 align, struct nouveau_mm_node **pnode)
-{
-	struct nouveau_mm_node *prev, *this, *next;
-	u32 mask = align - 1;
-
-	BUG_ON(type == NVKM_MM_TYPE_NONE || type == NVKM_MM_TYPE_HOLE);
-
-	list_for_each_entry_reverse(this, &mm->free, fl_entry) {
-		u32 e = this->offset + this->length;
-		u32 s = this->offset;
-		u32 c = 0, a;
-		if (unlikely(heap != NVKM_MM_HEAP_ANY)) {
-			if (this->heap != heap)
-				continue;
-		}
-
-		prev = node(this, prev);
-		if (prev && prev->type != type)
-			s = roundup(s, mm->block_size);
-
-		next = node(this, next);
-		if (next && next->type != type) {
-			e = rounddown(e, mm->block_size);
-			c = next->offset - e;
-		}
-
-		s = (s + mask) & ~mask;
-		a = e - s;
-		if (s > e || a < size_min)
-			continue;
-
-		a  = min(a, size_max);
-		s  = (e - a) & ~mask;
-		c += (e - s) - a;
-
-		if (c && !region_tail(mm, this, c))
-			return -ENOMEM;
-
-		this = region_tail(mm, this, a);
-		if (!this)
-			return -ENOMEM;
-
-		this->type = type;
-		list_del(&this->fl_entry);
-		*pnode = this;
-		return 0;
-	}
-
-	return -ENOSPC;
-}
-
-int
-nouveau_mm_init(struct nouveau_mm *mm, u32 offset, u32 length, u32 block)
-{
-	struct nouveau_mm_node *node, *prev;
-	u32 next;
-
-	if (nouveau_mm_initialised(mm)) {
-		prev = list_last_entry(&mm->nodes, typeof(*node), nl_entry);
-		next = prev->offset + prev->length;
-		if (next != offset) {
-			BUG_ON(next > offset);
-			if (!(node = kzalloc(sizeof(*node), GFP_KERNEL)))
-				return -ENOMEM;
-			node->type   = NVKM_MM_TYPE_HOLE;
-			node->offset = next;
-			node->length = offset - next;
-			list_add_tail(&node->nl_entry, &mm->nodes);
-		}
-		BUG_ON(block != mm->block_size);
-	} else {
-		INIT_LIST_HEAD(&mm->nodes);
-		INIT_LIST_HEAD(&mm->free);
-		mm->block_size = block;
-		mm->heap_nodes = 0;
-	}
-
-	node = kzalloc(sizeof(*node), GFP_KERNEL);
-	if (!node)
-		return -ENOMEM;
-
-	if (length) {
-		node->offset  = roundup(offset, mm->block_size);
-		node->length  = rounddown(offset + length, mm->block_size);
-		node->length -= node->offset;
-	}
-
-	list_add_tail(&node->nl_entry, &mm->nodes);
-	list_add_tail(&node->fl_entry, &mm->free);
-	node->heap = ++mm->heap_nodes;
-	return 0;
-}
-
-int
-nouveau_mm_fini(struct nouveau_mm *mm)
-{
-	struct nouveau_mm_node *node, *temp;
-	int nodes = 0;
-
-	if (!nouveau_mm_initialised(mm))
-		return 0;
-
-	list_for_each_entry(node, &mm->nodes, nl_entry) {
-		if (node->type != NVKM_MM_TYPE_HOLE) {
-			if (++nodes > mm->heap_nodes) {
-				nouveau_mm_dump(mm, "mm not clean!");
-				return -EBUSY;
-			}
-		}
-	}
-
-	list_for_each_entry_safe(node, temp, &mm->nodes, nl_entry) {
-		list_del(&node->nl_entry);
-		kfree(node);
-	}
-	mm->heap_nodes = 0;
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/core/namedb.c b/drivers/gpu/drm/nouveau/core/core/namedb.c
deleted file mode 100644
index 0594a599f6fb..000000000000
--- a/drivers/gpu/drm/nouveau/core/core/namedb.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/object.h>
-#include <core/namedb.h>
-#include <core/handle.h>
-#include <core/gpuobj.h>
-
-static struct nouveau_handle *
-nouveau_namedb_lookup(struct nouveau_namedb *namedb, u32 name)
-{
-	struct nouveau_handle *handle;
-
-	list_for_each_entry(handle, &namedb->list, node) {
-		if (handle->name == name)
-			return handle;
-	}
-
-	return NULL;
-}
-
-static struct nouveau_handle *
-nouveau_namedb_lookup_class(struct nouveau_namedb *namedb, u16 oclass)
-{
-	struct nouveau_handle *handle;
-
-	list_for_each_entry(handle, &namedb->list, node) {
-		if (nv_mclass(handle->object) == oclass)
-			return handle;
-	}
-
-	return NULL;
-}
-
-static struct nouveau_handle *
-nouveau_namedb_lookup_vinst(struct nouveau_namedb *namedb, u64 vinst)
-{
-	struct nouveau_handle *handle;
-
-	list_for_each_entry(handle, &namedb->list, node) {
-		if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) {
-			if (nv_gpuobj(handle->object)->addr == vinst)
-				return handle;
-		}
-	}
-
-	return NULL;
-}
-
-static struct nouveau_handle *
-nouveau_namedb_lookup_cinst(struct nouveau_namedb *namedb, u32 cinst)
-{
-	struct nouveau_handle *handle;
-
-	list_for_each_entry(handle, &namedb->list, node) {
-		if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) {
-			if (nv_gpuobj(handle->object)->node &&
-			    nv_gpuobj(handle->object)->node->offset == cinst)
-				return handle;
-		}
-	}
-
-	return NULL;
-}
-
-int
-nouveau_namedb_insert(struct nouveau_namedb *namedb, u32 name,
-		      struct nouveau_object *object,
-		      struct nouveau_handle *handle)
-{
-	int ret = -EEXIST;
-	write_lock_irq(&namedb->lock);
-	if (!nouveau_namedb_lookup(namedb, name)) {
-		nouveau_object_ref(object, &handle->object);
-		handle->namedb = namedb;
-		list_add(&handle->node, &namedb->list);
-		ret = 0;
-	}
-	write_unlock_irq(&namedb->lock);
-	return ret;
-}
-
-void
-nouveau_namedb_remove(struct nouveau_handle *handle)
-{
-	struct nouveau_namedb *namedb = handle->namedb;
-	struct nouveau_object *object = handle->object;
-	write_lock_irq(&namedb->lock);
-	list_del(&handle->node);
-	write_unlock_irq(&namedb->lock);
-	nouveau_object_ref(NULL, &object);
-}
-
-struct nouveau_handle *
-nouveau_namedb_get(struct nouveau_namedb *namedb, u32 name)
-{
-	struct nouveau_handle *handle;
-	read_lock(&namedb->lock);
-	handle = nouveau_namedb_lookup(namedb, name);
-	if (handle == NULL)
-		read_unlock(&namedb->lock);
-	return handle;
-}
-
-struct nouveau_handle *
-nouveau_namedb_get_class(struct nouveau_namedb *namedb, u16 oclass)
-{
-	struct nouveau_handle *handle;
-	read_lock(&namedb->lock);
-	handle = nouveau_namedb_lookup_class(namedb, oclass);
-	if (handle == NULL)
-		read_unlock(&namedb->lock);
-	return handle;
-}
-
-struct nouveau_handle *
-nouveau_namedb_get_vinst(struct nouveau_namedb *namedb, u64 vinst)
-{
-	struct nouveau_handle *handle;
-	read_lock(&namedb->lock);
-	handle = nouveau_namedb_lookup_vinst(namedb, vinst);
-	if (handle == NULL)
-		read_unlock(&namedb->lock);
-	return handle;
-}
-
-struct nouveau_handle *
-nouveau_namedb_get_cinst(struct nouveau_namedb *namedb, u32 cinst)
-{
-	struct nouveau_handle *handle;
-	read_lock(&namedb->lock);
-	handle = nouveau_namedb_lookup_cinst(namedb, cinst);
-	if (handle == NULL)
-		read_unlock(&namedb->lock);
-	return handle;
-}
-
-void
-nouveau_namedb_put(struct nouveau_handle *handle)
-{
-	if (handle)
-		read_unlock(&handle->namedb->lock);
-}
-
-int
-nouveau_namedb_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, u32 pclass,
-		       struct nouveau_oclass *sclass, u64 engcls,
-		       int length, void **pobject)
-{
-	struct nouveau_namedb *namedb;
-	int ret;
-
-	ret = nouveau_parent_create_(parent, engine, oclass, pclass |
-				     NV_NAMEDB_CLASS, sclass, engcls,
-				     length, pobject);
-	namedb = *pobject;
-	if (ret)
-		return ret;
-
-	rwlock_init(&namedb->lock);
-	INIT_LIST_HEAD(&namedb->list);
-	return 0;
-}
-
-int
-_nouveau_namedb_ctor(struct nouveau_object *parent,
-		     struct nouveau_object *engine,
-		     struct nouveau_oclass *oclass, void *data, u32 size,
-		     struct nouveau_object **pobject)
-{
-	struct nouveau_namedb *object;
-	int ret;
-
-	ret = nouveau_namedb_create(parent, engine, oclass, 0, NULL, 0, &object);
-	*pobject = nv_object(object);
-	if (ret)
-		return ret;
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/core/notify.c b/drivers/gpu/drm/nouveau/core/core/notify.c
deleted file mode 100644
index 839a32577680..000000000000
--- a/drivers/gpu/drm/nouveau/core/core/notify.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include <core/client.h>
-#include <core/event.h>
-#include <core/notify.h>
-
-#include <nvif/unpack.h>
-#include <nvif/event.h>
-
-static inline void
-nvkm_notify_put_locked(struct nvkm_notify *notify)
-{
-	if (notify->block++ == 0)
-		nvkm_event_put(notify->event, notify->types, notify->index);
-}
-
-void
-nvkm_notify_put(struct nvkm_notify *notify)
-{
-	struct nvkm_event *event = notify->event;
-	unsigned long flags;
-	if (likely(event) &&
-	    test_and_clear_bit(NVKM_NOTIFY_USER, &notify->flags)) {
-		spin_lock_irqsave(&event->refs_lock, flags);
-		nvkm_notify_put_locked(notify);
-		spin_unlock_irqrestore(&event->refs_lock, flags);
-		if (test_bit(NVKM_NOTIFY_WORK, &notify->flags))
-			flush_work(&notify->work);
-	}
-}
-
-static inline void
-nvkm_notify_get_locked(struct nvkm_notify *notify)
-{
-	if (--notify->block == 0)
-		nvkm_event_get(notify->event, notify->types, notify->index);
-}
-
-void
-nvkm_notify_get(struct nvkm_notify *notify)
-{
-	struct nvkm_event *event = notify->event;
-	unsigned long flags;
-	if (likely(event) &&
-	    !test_and_set_bit(NVKM_NOTIFY_USER, &notify->flags)) {
-		spin_lock_irqsave(&event->refs_lock, flags);
-		nvkm_notify_get_locked(notify);
-		spin_unlock_irqrestore(&event->refs_lock, flags);
-	}
-}
-
-static inline void
-nvkm_notify_func(struct nvkm_notify *notify)
-{
-	struct nvkm_event *event = notify->event;
-	int ret = notify->func(notify);
-	unsigned long flags;
-	if ((ret == NVKM_NOTIFY_KEEP) ||
-	    !test_and_clear_bit(NVKM_NOTIFY_USER, &notify->flags)) {
-		spin_lock_irqsave(&event->refs_lock, flags);
-		nvkm_notify_get_locked(notify);
-		spin_unlock_irqrestore(&event->refs_lock, flags);
-	}
-}
-
-static void
-nvkm_notify_work(struct work_struct *work)
-{
-	struct nvkm_notify *notify = container_of(work, typeof(*notify), work);
-	nvkm_notify_func(notify);
-}
-
-void
-nvkm_notify_send(struct nvkm_notify *notify, void *data, u32 size)
-{
-	struct nvkm_event *event = notify->event;
-	unsigned long flags;
-
-	assert_spin_locked(&event->list_lock);
-	BUG_ON(size != notify->size);
-
-	spin_lock_irqsave(&event->refs_lock, flags);
-	if (notify->block) {
-		spin_unlock_irqrestore(&event->refs_lock, flags);
-		return;
-	}
-	nvkm_notify_put_locked(notify);
-	spin_unlock_irqrestore(&event->refs_lock, flags);
-
-	if (test_bit(NVKM_NOTIFY_WORK, &notify->flags)) {
-		memcpy((void *)notify->data, data, size);
-		schedule_work(&notify->work);
-	} else {
-		notify->data = data;
-		nvkm_notify_func(notify);
-		notify->data = NULL;
-	}
-}
-
-void
-nvkm_notify_fini(struct nvkm_notify *notify)
-{
-	unsigned long flags;
-	if (notify->event) {
-		nvkm_notify_put(notify);
-		spin_lock_irqsave(&notify->event->list_lock, flags);
-		list_del(&notify->head);
-		spin_unlock_irqrestore(&notify->event->list_lock, flags);
-		kfree((void *)notify->data);
-		notify->event = NULL;
-	}
-}
-
-int
-nvkm_notify_init(struct nouveau_object *object, struct nvkm_event *event,
-		 int (*func)(struct nvkm_notify *), bool work,
-		 void *data, u32 size, u32 reply,
-		 struct nvkm_notify *notify)
-{
-	unsigned long flags;
-	int ret = -ENODEV;
-	if ((notify->event = event), event->refs) {
-		ret = event->func->ctor(object, data, size, notify);
-		if (ret == 0 && (ret = -EINVAL, notify->size == reply)) {
-			notify->flags = 0;
-			notify->block = 1;
-			notify->func = func;
-			notify->data = NULL;
-			if (ret = 0, work) {
-				INIT_WORK(&notify->work, nvkm_notify_work);
-				set_bit(NVKM_NOTIFY_WORK, &notify->flags);
-				notify->data = kmalloc(reply, GFP_KERNEL);
-				if (!notify->data)
-					ret = -ENOMEM;
-			}
-		}
-		if (ret == 0) {
-			spin_lock_irqsave(&event->list_lock, flags);
-			list_add_tail(&notify->head, &event->list);
-			spin_unlock_irqrestore(&event->list_lock, flags);
-		}
-	}
-	if (ret)
-		notify->event = NULL;
-	return ret;
-}
diff --git a/drivers/gpu/drm/nouveau/core/core/object.c b/drivers/gpu/drm/nouveau/core/core/object.c
deleted file mode 100644
index b08630577c82..000000000000
--- a/drivers/gpu/drm/nouveau/core/core/object.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/object.h>
-#include <core/engine.h>
-
-#ifdef NOUVEAU_OBJECT_MAGIC
-static struct list_head _objlist = LIST_HEAD_INIT(_objlist);
-static DEFINE_SPINLOCK(_objlist_lock);
-#endif
-
-int
-nouveau_object_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, u32 pclass,
-		       int size, void **pobject)
-{
-	struct nouveau_object *object;
-
-	object = *pobject = kzalloc(size, GFP_KERNEL);
-	if (!object)
-		return -ENOMEM;
-
-	nouveau_object_ref(parent, &object->parent);
-	nouveau_object_ref(engine, &object->engine);
-	object->oclass = oclass;
-	object->oclass->handle |= pclass;
-	atomic_set(&object->refcount, 1);
-	atomic_set(&object->usecount, 0);
-
-#ifdef NOUVEAU_OBJECT_MAGIC
-	object->_magic = NOUVEAU_OBJECT_MAGIC;
-	spin_lock(&_objlist_lock);
-	list_add(&object->list, &_objlist);
-	spin_unlock(&_objlist_lock);
-#endif
-	return 0;
-}
-
-int
-_nouveau_object_ctor(struct nouveau_object *parent,
-		     struct nouveau_object *engine,
-		     struct nouveau_oclass *oclass, void *data, u32 size,
-		     struct nouveau_object **pobject)
-{
-	if (size != 0)
-		return -ENOSYS;
-	return nouveau_object_create(parent, engine, oclass, 0, pobject);
-}
-
-void
-nouveau_object_destroy(struct nouveau_object *object)
-{
-#ifdef NOUVEAU_OBJECT_MAGIC
-	spin_lock(&_objlist_lock);
-	list_del(&object->list);
-	spin_unlock(&_objlist_lock);
-#endif
-	nouveau_object_ref(NULL, &object->engine);
-	nouveau_object_ref(NULL, &object->parent);
-	kfree(object);
-}
-
-int
-nouveau_object_init(struct nouveau_object *object)
-{
-	return 0;
-}
-
-int
-nouveau_object_fini(struct nouveau_object *object, bool suspend)
-{
-	return 0;
-}
-
-struct nouveau_ofuncs
-nouveau_object_ofuncs = {
-	.ctor = _nouveau_object_ctor,
-	.dtor = nouveau_object_destroy,
-	.init = nouveau_object_init,
-	.fini = nouveau_object_fini,
-};
-
-int
-nouveau_object_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
-{
-	struct nouveau_ofuncs *ofuncs = oclass->ofuncs;
-	struct nouveau_object *object = NULL;
-	int ret;
-
-	ret = ofuncs->ctor(parent, engine, oclass, data, size, &object);
-	*pobject = object;
-	if (ret < 0) {
-		if (ret != -ENODEV) {
-			nv_error(parent, "failed to create 0x%08x, %d\n",
-				 oclass->handle, ret);
-		}
-
-		if (object) {
-			ofuncs->dtor(object);
-			*pobject = NULL;
-		}
-
-		return ret;
-	}
-
-	if (ret == 0) {
-		nv_trace(object, "created\n");
-		atomic_set(&object->refcount, 1);
-	}
-
-	return 0;
-}
-
-static void
-nouveau_object_dtor(struct nouveau_object *object)
-{
-	nv_trace(object, "destroying\n");
-	nv_ofuncs(object)->dtor(object);
-}
-
-void
-nouveau_object_ref(struct nouveau_object *obj, struct nouveau_object **ref)
-{
-	if (obj) {
-		atomic_inc(&obj->refcount);
-		nv_trace(obj, "inc() == %d\n", atomic_read(&obj->refcount));
-	}
-
-	if (*ref) {
-		int dead = atomic_dec_and_test(&(*ref)->refcount);
-		nv_trace(*ref, "dec() == %d\n", atomic_read(&(*ref)->refcount));
-		if (dead)
-			nouveau_object_dtor(*ref);
-	}
-
-	*ref = obj;
-}
-
-int
-nouveau_object_inc(struct nouveau_object *object)
-{
-	int ref = atomic_add_return(1, &object->usecount);
-	int ret;
-
-	nv_trace(object, "use(+1) == %d\n", atomic_read(&object->usecount));
-	if (ref != 1)
-		return 0;
-
-	nv_trace(object, "initialising...\n");
-	if (object->parent) {
-		ret = nouveau_object_inc(object->parent);
-		if (ret) {
-			nv_error(object, "parent failed, %d\n", ret);
-			goto fail_parent;
-		}
-	}
-
-	if (object->engine) {
-		mutex_lock(&nv_subdev(object->engine)->mutex);
-		ret = nouveau_object_inc(object->engine);
-		mutex_unlock(&nv_subdev(object->engine)->mutex);
-		if (ret) {
-			nv_error(object, "engine failed, %d\n", ret);
-			goto fail_engine;
-		}
-	}
-
-	ret = nv_ofuncs(object)->init(object);
-	atomic_set(&object->usecount, 1);
-	if (ret) {
-		nv_error(object, "init failed, %d\n", ret);
-		goto fail_self;
-	}
-
-	nv_trace(object, "initialised\n");
-	return 0;
-
-fail_self:
-	if (object->engine) {
-		mutex_lock(&nv_subdev(object->engine)->mutex);
-		nouveau_object_dec(object->engine, false);
-		mutex_unlock(&nv_subdev(object->engine)->mutex);
-	}
-fail_engine:
-	if (object->parent)
-		 nouveau_object_dec(object->parent, false);
-fail_parent:
-	atomic_dec(&object->usecount);
-	return ret;
-}
-
-static int
-nouveau_object_decf(struct nouveau_object *object)
-{
-	int ret;
-
-	nv_trace(object, "stopping...\n");
-
-	ret = nv_ofuncs(object)->fini(object, false);
-	atomic_set(&object->usecount, 0);
-	if (ret)
-		nv_warn(object, "failed fini, %d\n", ret);
-
-	if (object->engine) {
-		mutex_lock(&nv_subdev(object->engine)->mutex);
-		nouveau_object_dec(object->engine, false);
-		mutex_unlock(&nv_subdev(object->engine)->mutex);
-	}
-
-	if (object->parent)
-		nouveau_object_dec(object->parent, false);
-
-	nv_trace(object, "stopped\n");
-	return 0;
-}
-
-static int
-nouveau_object_decs(struct nouveau_object *object)
-{
-	int ret, rret;
-
-	nv_trace(object, "suspending...\n");
-
-	ret = nv_ofuncs(object)->fini(object, true);
-	atomic_set(&object->usecount, 0);
-	if (ret) {
-		nv_error(object, "failed suspend, %d\n", ret);
-		return ret;
-	}
-
-	if (object->engine) {
-		mutex_lock(&nv_subdev(object->engine)->mutex);
-		ret = nouveau_object_dec(object->engine, true);
-		mutex_unlock(&nv_subdev(object->engine)->mutex);
-		if (ret) {
-			nv_warn(object, "engine failed suspend, %d\n", ret);
-			goto fail_engine;
-		}
-	}
-
-	if (object->parent) {
-		ret = nouveau_object_dec(object->parent, true);
-		if (ret) {
-			nv_warn(object, "parent failed suspend, %d\n", ret);
-			goto fail_parent;
-		}
-	}
-
-	nv_trace(object, "suspended\n");
-	return 0;
-
-fail_parent:
-	if (object->engine) {
-		mutex_lock(&nv_subdev(object->engine)->mutex);
-		rret = nouveau_object_inc(object->engine);
-		mutex_unlock(&nv_subdev(object->engine)->mutex);
-		if (rret)
-			nv_fatal(object, "engine failed to reinit, %d\n", rret);
-	}
-
-fail_engine:
-	rret = nv_ofuncs(object)->init(object);
-	if (rret)
-		nv_fatal(object, "failed to reinit, %d\n", rret);
-
-	return ret;
-}
-
-int
-nouveau_object_dec(struct nouveau_object *object, bool suspend)
-{
-	int ref = atomic_add_return(-1, &object->usecount);
-	int ret;
-
-	nv_trace(object, "use(-1) == %d\n", atomic_read(&object->usecount));
-
-	if (ref == 0) {
-		if (suspend)
-			ret = nouveau_object_decs(object);
-		else
-			ret = nouveau_object_decf(object);
-
-		if (ret) {
-			atomic_inc(&object->usecount);
-			return ret;
-		}
-	}
-
-	return 0;
-}
-
-void
-nouveau_object_debug(void)
-{
-#ifdef NOUVEAU_OBJECT_MAGIC
-	struct nouveau_object *object;
-	if (!list_empty(&_objlist)) {
-		nv_fatal(NULL, "*******************************************\n");
-		nv_fatal(NULL, "* AIIIII! object(s) still exist!!!\n");
-		nv_fatal(NULL, "*******************************************\n");
-		list_for_each_entry(object, &_objlist, list) {
-			nv_fatal(object, "%p/%p/%d/%d\n",
-				 object->parent, object->engine,
-				 atomic_read(&object->refcount),
-				 atomic_read(&object->usecount));
-		}
-	}
-#endif
-}
diff --git a/drivers/gpu/drm/nouveau/core/core/option.c b/drivers/gpu/drm/nouveau/core/core/option.c
deleted file mode 100644
index 9f6fcc5f66c2..000000000000
--- a/drivers/gpu/drm/nouveau/core/core/option.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/option.h>
-#include <core/debug.h>
-
-const char *
-nouveau_stropt(const char *optstr, const char *opt, int *arglen)
-{
-	while (optstr && *optstr != '\0') {
-		int len = strcspn(optstr, ",=");
-		switch (optstr[len]) {
-		case '=':
-			if (!strncasecmpz(optstr, opt, len)) {
-				optstr += len + 1;
-				*arglen = strcspn(optstr, ",=");
-				return *arglen ? optstr : NULL;
-			}
-			optstr++;
-			break;
-		case ',':
-			optstr++;
-			break;
-		default:
-			break;
-		}
-		optstr += len;
-	}
-
-	return NULL;
-}
-
-bool
-nouveau_boolopt(const char *optstr, const char *opt, bool value)
-{
-	int arglen;
-
-	optstr = nouveau_stropt(optstr, opt, &arglen);
-	if (optstr) {
-		if (!strncasecmpz(optstr, "0", arglen) ||
-		    !strncasecmpz(optstr, "no", arglen) ||
-		    !strncasecmpz(optstr, "off", arglen) ||
-		    !strncasecmpz(optstr, "false", arglen))
-			value = false;
-		else
-		if (!strncasecmpz(optstr, "1", arglen) ||
-		    !strncasecmpz(optstr, "yes", arglen) ||
-		    !strncasecmpz(optstr, "on", arglen) ||
-		    !strncasecmpz(optstr, "true", arglen))
-			value = true;
-	}
-
-	return value;
-}
-
-int
-nouveau_dbgopt(const char *optstr, const char *sub)
-{
-	int mode = 1, level = CONFIG_NOUVEAU_DEBUG_DEFAULT;
-
-	while (optstr) {
-		int len = strcspn(optstr, ",=");
-		switch (optstr[len]) {
-		case '=':
-			if (strncasecmpz(optstr, sub, len))
-				mode = 0;
-			optstr++;
-			break;
-		default:
-			if (mode) {
-				if (!strncasecmpz(optstr, "fatal", len))
-					level = NV_DBG_FATAL;
-				else if (!strncasecmpz(optstr, "error", len))
-					level = NV_DBG_ERROR;
-				else if (!strncasecmpz(optstr, "warn", len))
-					level = NV_DBG_WARN;
-				else if (!strncasecmpz(optstr, "info", len))
-					level = NV_DBG_INFO_NORMAL;
-				else if (!strncasecmpz(optstr, "debug", len))
-					level = NV_DBG_DEBUG;
-				else if (!strncasecmpz(optstr, "trace", len))
-					level = NV_DBG_TRACE;
-				else if (!strncasecmpz(optstr, "paranoia", len))
-					level = NV_DBG_PARANOIA;
-				else if (!strncasecmpz(optstr, "spam", len))
-					level = NV_DBG_SPAM;
-			}
-
-			if (optstr[len] != '\0') {
-				optstr++;
-				mode = 1;
-				break;
-			}
-
-			return level;
-		}
-		optstr += len;
-	}
-
-	return level;
-}
diff --git a/drivers/gpu/drm/nouveau/core/core/parent.c b/drivers/gpu/drm/nouveau/core/core/parent.c
deleted file mode 100644
index 30a2911878f8..000000000000
--- a/drivers/gpu/drm/nouveau/core/core/parent.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/object.h>
-#include <core/parent.h>
-#include <core/client.h>
-
-int
-nouveau_parent_sclass(struct nouveau_object *parent, u16 handle,
-		      struct nouveau_object **pengine,
-		      struct nouveau_oclass **poclass)
-{
-	struct nouveau_sclass *sclass;
-	struct nouveau_engine *engine;
-	struct nouveau_oclass *oclass;
-	u64 mask;
-
-	sclass = nv_parent(parent)->sclass;
-	while (sclass) {
-		if ((sclass->oclass->handle & 0xffff) == handle) {
-			*pengine = parent->engine;
-			*poclass = sclass->oclass;
-			return 0;
-		}
-
-		sclass = sclass->sclass;
-	}
-
-	mask = nv_parent(parent)->engine;
-	while (mask) {
-		int i = __ffs64(mask);
-
-		if (nv_iclass(parent, NV_CLIENT_CLASS))
-			engine = nv_engine(nv_client(parent)->device);
-		else
-			engine = nouveau_engine(parent, i);
-
-		if (engine) {
-			oclass = engine->sclass;
-			while (oclass->ofuncs) {
-				if ((oclass->handle & 0xffff) == handle) {
-					*pengine = nv_object(engine);
-					*poclass = oclass;
-					return 0;
-				}
-				oclass++;
-			}
-		}
-
-		mask &= ~(1ULL << i);
-	}
-
-	return -EINVAL;
-}
-
-int
-nouveau_parent_lclass(struct nouveau_object *parent, u32 *lclass, int size)
-{
-	struct nouveau_sclass *sclass;
-	struct nouveau_engine *engine;
-	struct nouveau_oclass *oclass;
-	int nr = -1, i;
-	u64 mask;
-
-	sclass = nv_parent(parent)->sclass;
-	while (sclass) {
-		if (++nr < size)
-			lclass[nr] = sclass->oclass->handle & 0xffff;
-		sclass = sclass->sclass;
-	}
-
-	mask = nv_parent(parent)->engine;
-	while (i = __ffs64(mask), mask) {
-		engine = nouveau_engine(parent, i);
-		if (engine && (oclass = engine->sclass)) {
-			while (oclass->ofuncs) {
-				if (++nr < size)
-					lclass[nr] = oclass->handle & 0xffff;
-				oclass++;
-			}
-		}
-
-		mask &= ~(1ULL << i);
-	}
-
-	return nr + 1;
-}
-
-int
-nouveau_parent_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, u32 pclass,
-		       struct nouveau_oclass *sclass, u64 engcls,
-		       int size, void **pobject)
-{
-	struct nouveau_parent *object;
-	struct nouveau_sclass *nclass;
-	int ret;
-
-	ret = nouveau_object_create_(parent, engine, oclass, pclass |
-				     NV_PARENT_CLASS, size, pobject);
-	object = *pobject;
-	if (ret)
-		return ret;
-
-	while (sclass && sclass->ofuncs) {
-		nclass = kzalloc(sizeof(*nclass), GFP_KERNEL);
-		if (!nclass)
-			return -ENOMEM;
-
-		nclass->sclass = object->sclass;
-		object->sclass = nclass;
-		nclass->engine = engine ? nv_engine(engine) : NULL;
-		nclass->oclass = sclass;
-		sclass++;
-	}
-
-	object->engine = engcls;
-	return 0;
-}
-
-void
-nouveau_parent_destroy(struct nouveau_parent *parent)
-{
-	struct nouveau_sclass *sclass;
-
-	while ((sclass = parent->sclass)) {
-		parent->sclass = sclass->sclass;
-		kfree(sclass);
-	}
-
-	nouveau_object_destroy(&parent->base);
-}
-
-
-void
-_nouveau_parent_dtor(struct nouveau_object *object)
-{
-	nouveau_parent_destroy(nv_parent(object));
-}
diff --git a/drivers/gpu/drm/nouveau/core/core/printk.c b/drivers/gpu/drm/nouveau/core/core/printk.c
deleted file mode 100644
index 03e0060b13da..000000000000
--- a/drivers/gpu/drm/nouveau/core/core/printk.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/object.h>
-#include <core/client.h>
-#include <core/subdev.h>
-#include <core/printk.h>
-
-int nv_info_debug_level = NV_DBG_INFO_NORMAL;
-
-void
-nv_printk_(struct nouveau_object *object, int level, const char *fmt, ...)
-{
-	static const char name[] = { '!', 'E', 'W', ' ', 'D', 'T', 'P', 'S' };
-	const char *pfx;
-	char mfmt[256];
-	va_list args;
-
-	switch (level) {
-	case NV_DBG_FATAL:
-		pfx = KERN_CRIT;
-		break;
-	case NV_DBG_ERROR:
-		pfx = KERN_ERR;
-		break;
-	case NV_DBG_WARN:
-		pfx = KERN_WARNING;
-		break;
-	case NV_DBG_INFO_NORMAL:
-		pfx = KERN_INFO;
-		break;
-	case NV_DBG_DEBUG:
-	case NV_DBG_PARANOIA:
-	case NV_DBG_TRACE:
-	case NV_DBG_SPAM:
-	default:
-		pfx = KERN_DEBUG;
-		break;
-	}
-
-	if (object && !nv_iclass(object, NV_CLIENT_CLASS)) {
-		struct nouveau_object *device = object;
-		struct nouveau_object *subdev = object;
-		char obuf[64], *ofmt = "";
-
-		if (object->engine) {
-			snprintf(obuf, sizeof(obuf), "[0x%08x][%p]",
-				 nv_hclass(object), object);
-			ofmt = obuf;
-			subdev = object->engine;
-			device = object->engine;
-		}
-
-		if (subdev->parent)
-			device = subdev->parent;
-
-		if (level > nv_subdev(subdev)->debug)
-			return;
-
-		snprintf(mfmt, sizeof(mfmt), "%snouveau %c[%8s][%s]%s %s", pfx,
-			 name[level], nv_subdev(subdev)->name,
-			 nv_device(device)->name, ofmt, fmt);
-	} else
-	if (object && nv_iclass(object, NV_CLIENT_CLASS)) {
-		if (level > nv_client(object)->debug)
-			return;
-
-		snprintf(mfmt, sizeof(mfmt), "%snouveau %c[%8s] %s", pfx,
-			 name[level], nv_client(object)->name, fmt);
-	} else {
-		snprintf(mfmt, sizeof(mfmt), "%snouveau: %s", pfx, fmt);
-	}
-
-	va_start(args, fmt);
-	vprintk(mfmt, args);
-	va_end(args);
-}
diff --git a/drivers/gpu/drm/nouveau/core/core/ramht.c b/drivers/gpu/drm/nouveau/core/core/ramht.c
deleted file mode 100644
index f3b9bddc3875..000000000000
--- a/drivers/gpu/drm/nouveau/core/core/ramht.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <core/object.h>
-#include <core/ramht.h>
-
-#include <subdev/bar.h>
-
-static u32
-nouveau_ramht_hash(struct nouveau_ramht *ramht, int chid, u32 handle)
-{
-	u32 hash = 0;
-
-	while (handle) {
-		hash ^= (handle & ((1 << ramht->bits) - 1));
-		handle >>= ramht->bits;
-	}
-
-	hash ^= chid << (ramht->bits - 4);
-	hash  = hash << 3;
-	return hash;
-}
-
-int
-nouveau_ramht_insert(struct nouveau_ramht *ramht, int chid,
-		     u32 handle, u32 context)
-{
-	struct nouveau_bar *bar = nouveau_bar(ramht);
-	u32 co, ho;
-
-	co = ho = nouveau_ramht_hash(ramht, chid, handle);
-	do {
-		if (!nv_ro32(ramht, co + 4)) {
-			nv_wo32(ramht, co + 0, handle);
-			nv_wo32(ramht, co + 4, context);
-			if (bar)
-				bar->flush(bar);
-			return co;
-		}
-
-		co += 8;
-		if (co >= nv_gpuobj(ramht)->size)
-			co = 0;
-	} while (co != ho);
-
-	return -ENOMEM;
-}
-
-void
-nouveau_ramht_remove(struct nouveau_ramht *ramht, int cookie)
-{
-	struct nouveau_bar *bar = nouveau_bar(ramht);
-	nv_wo32(ramht, cookie + 0, 0x00000000);
-	nv_wo32(ramht, cookie + 4, 0x00000000);
-	if (bar)
-		bar->flush(bar);
-}
-
-static struct nouveau_oclass
-nouveau_ramht_oclass = {
-	.handle = 0x0000abcd,
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = NULL,
-		.dtor = _nouveau_gpuobj_dtor,
-		.init = _nouveau_gpuobj_init,
-		.fini = _nouveau_gpuobj_fini,
-		.rd32 = _nouveau_gpuobj_rd32,
-		.wr32 = _nouveau_gpuobj_wr32,
-	},
-};
-
-int
-nouveau_ramht_new(struct nouveau_object *parent, struct nouveau_object *pargpu,
-		  u32 size, u32 align, struct nouveau_ramht **pramht)
-{
-	struct nouveau_ramht *ramht;
-	int ret;
-
-	ret = nouveau_gpuobj_create(parent, parent->engine ?
-				    parent->engine : parent, /* <nv50 ramht */
-				    &nouveau_ramht_oclass, 0, pargpu, size,
-				    align, NVOBJ_FLAG_ZERO_ALLOC, &ramht);
-	*pramht = ramht;
-	if (ret)
-		return ret;
-
-	ramht->bits = order_base_2(nv_gpuobj(ramht)->size >> 3);
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/core/subdev.c b/drivers/gpu/drm/nouveau/core/core/subdev.c
deleted file mode 100644
index 2ea5568b6cf5..000000000000
--- a/drivers/gpu/drm/nouveau/core/core/subdev.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/object.h>
-#include <core/subdev.h>
-#include <core/device.h>
-#include <core/option.h>
-
-void
-nouveau_subdev_reset(struct nouveau_object *subdev)
-{
-	nv_trace(subdev, "resetting...\n");
-	nv_ofuncs(subdev)->fini(subdev, false);
-	nv_debug(subdev, "reset\n");
-}
-
-int
-nouveau_subdev_init(struct nouveau_subdev *subdev)
-{
-	int ret = nouveau_object_init(&subdev->base);
-	if (ret)
-		return ret;
-
-	nouveau_subdev_reset(&subdev->base);
-	return 0;
-}
-
-int
-_nouveau_subdev_init(struct nouveau_object *object)
-{
-	return nouveau_subdev_init(nv_subdev(object));
-}
-
-int
-nouveau_subdev_fini(struct nouveau_subdev *subdev, bool suspend)
-{
-	if (subdev->unit) {
-		nv_mask(subdev, 0x000200, subdev->unit, 0x00000000);
-		nv_mask(subdev, 0x000200, subdev->unit, subdev->unit);
-	}
-
-	return nouveau_object_fini(&subdev->base, suspend);
-}
-
-int
-_nouveau_subdev_fini(struct nouveau_object *object, bool suspend)
-{
-	return nouveau_subdev_fini(nv_subdev(object), suspend);
-}
-
-void
-nouveau_subdev_destroy(struct nouveau_subdev *subdev)
-{
-	int subidx = nv_hclass(subdev) & 0xff;
-	nv_device(subdev)->subdev[subidx] = NULL;
-	nouveau_object_destroy(&subdev->base);
-}
-
-void
-_nouveau_subdev_dtor(struct nouveau_object *object)
-{
-	nouveau_subdev_destroy(nv_subdev(object));
-}
-
-int
-nouveau_subdev_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, u32 pclass,
-		       const char *subname, const char *sysname,
-		       int size, void **pobject)
-{
-	struct nouveau_subdev *subdev;
-	int ret;
-
-	ret = nouveau_object_create_(parent, engine, oclass, pclass |
-				     NV_SUBDEV_CLASS, size, pobject);
-	subdev = *pobject;
-	if (ret)
-		return ret;
-
-	__mutex_init(&subdev->mutex, subname, &oclass->lock_class_key);
-	subdev->name = subname;
-
-	if (parent) {
-		struct nouveau_device *device = nv_device(parent);
-		subdev->debug = nouveau_dbgopt(device->dbgopt, subname);
-		subdev->mmio  = nv_subdev(device)->mmio;
-	}
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c
deleted file mode 100644
index 1e8e75c0684a..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs, Ilia Mirkin
- */
-
-#include <engine/xtensa.h>
-#include <engine/bsp.h>
-
-/*******************************************************************************
- * BSP object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv84_bsp_sclass[] = {
-	{ 0x74b0, &nouveau_object_ofuncs },
-	{},
-};
-
-/*******************************************************************************
- * BSP context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv84_bsp_cclass = {
-	.handle = NV_ENGCTX(BSP, 0x84),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_xtensa_engctx_ctor,
-		.dtor = _nouveau_engctx_dtor,
-		.init = _nouveau_engctx_init,
-		.fini = _nouveau_engctx_fini,
-		.rd32 = _nouveau_engctx_rd32,
-		.wr32 = _nouveau_engctx_wr32,
-	},
-};
-
-/*******************************************************************************
- * BSP engine/subdev functions
- ******************************************************************************/
-
-static int
-nv84_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 size,
-	      struct nouveau_object **pobject)
-{
-	struct nouveau_xtensa *priv;
-	int ret;
-
-	ret = nouveau_xtensa_create(parent, engine, oclass, 0x103000, true,
-				    "PBSP", "bsp", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x04008000;
-	nv_engine(priv)->cclass = &nv84_bsp_cclass;
-	nv_engine(priv)->sclass = nv84_bsp_sclass;
-	priv->fifo_val = 0x1111;
-	priv->unkd28 = 0x90044;
-	return 0;
-}
-
-struct nouveau_oclass
-nv84_bsp_oclass = {
-	.handle = NV_ENGINE(BSP, 0x84),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv84_bsp_ctor,
-		.dtor = _nouveau_xtensa_dtor,
-		.init = _nouveau_xtensa_init,
-		.fini = _nouveau_xtensa_fini,
-		.rd32 = _nouveau_xtensa_rd32,
-		.wr32 = _nouveau_xtensa_wr32,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nv98.c b/drivers/gpu/drm/nouveau/core/engine/bsp/nv98.c
deleted file mode 100644
index 6b089e022fd2..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/bsp/nv98.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
- */
-
-#include <engine/falcon.h>
-#include <engine/bsp.h>
-
-struct nv98_bsp_priv {
-	struct nouveau_falcon base;
-};
-
-/*******************************************************************************
- * BSP object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv98_bsp_sclass[] = {
-	{ 0x88b1, &nouveau_object_ofuncs },
-	{ 0x85b1, &nouveau_object_ofuncs },
-	{ 0x86b1, &nouveau_object_ofuncs },
-	{},
-};
-
-/*******************************************************************************
- * PBSP context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv98_bsp_cclass = {
-	.handle = NV_ENGCTX(BSP, 0x98),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_falcon_context_ctor,
-		.dtor = _nouveau_falcon_context_dtor,
-		.init = _nouveau_falcon_context_init,
-		.fini = _nouveau_falcon_context_fini,
-		.rd32 = _nouveau_falcon_context_rd32,
-		.wr32 = _nouveau_falcon_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PBSP engine/subdev functions
- ******************************************************************************/
-
-static int
-nv98_bsp_init(struct nouveau_object *object)
-{
-	struct nv98_bsp_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_falcon_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x084010, 0x0000ffd2);
-	nv_wr32(priv, 0x08401c, 0x0000fff2);
-	return 0;
-}
-
-static int
-nv98_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 size,
-	      struct nouveau_object **pobject)
-{
-	struct nv98_bsp_priv *priv;
-	int ret;
-
-	ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true,
-				    "PBSP", "bsp", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x04008000;
-	nv_engine(priv)->cclass = &nv98_bsp_cclass;
-	nv_engine(priv)->sclass = nv98_bsp_sclass;
-	return 0;
-}
-
-struct nouveau_oclass
-nv98_bsp_oclass = {
-	.handle = NV_ENGINE(BSP, 0x98),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv98_bsp_ctor,
-		.dtor = _nouveau_falcon_dtor,
-		.init = nv98_bsp_init,
-		.fini = _nouveau_falcon_fini,
-		.rd32 = _nouveau_falcon_rd32,
-		.wr32 = _nouveau_falcon_wr32,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/bsp/nvc0.c
deleted file mode 100644
index ce860de43e61..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/bsp/nvc0.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright 2012 Maarten Lankhorst
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Maarten Lankhorst
- */
-
-#include <engine/falcon.h>
-#include <engine/bsp.h>
-
-struct nvc0_bsp_priv {
-	struct nouveau_falcon base;
-};
-
-/*******************************************************************************
- * BSP object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nvc0_bsp_sclass[] = {
-	{ 0x90b1, &nouveau_object_ofuncs },
-	{},
-};
-
-/*******************************************************************************
- * PBSP context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nvc0_bsp_cclass = {
-	.handle = NV_ENGCTX(BSP, 0xc0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_falcon_context_ctor,
-		.dtor = _nouveau_falcon_context_dtor,
-		.init = _nouveau_falcon_context_init,
-		.fini = _nouveau_falcon_context_fini,
-		.rd32 = _nouveau_falcon_context_rd32,
-		.wr32 = _nouveau_falcon_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PBSP engine/subdev functions
- ******************************************************************************/
-
-static int
-nvc0_bsp_init(struct nouveau_object *object)
-{
-	struct nvc0_bsp_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_falcon_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x084010, 0x0000fff2);
-	nv_wr32(priv, 0x08401c, 0x0000fff2);
-	return 0;
-}
-
-static int
-nvc0_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 size,
-	      struct nouveau_object **pobject)
-{
-	struct nvc0_bsp_priv *priv;
-	int ret;
-
-	ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true,
-				    "PBSP", "bsp", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00008000;
-	nv_subdev(priv)->intr = nouveau_falcon_intr;
-	nv_engine(priv)->cclass = &nvc0_bsp_cclass;
-	nv_engine(priv)->sclass = nvc0_bsp_sclass;
-	return 0;
-}
-
-struct nouveau_oclass
-nvc0_bsp_oclass = {
-	.handle = NV_ENGINE(BSP, 0xc0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_bsp_ctor,
-		.dtor = _nouveau_falcon_dtor,
-		.init = nvc0_bsp_init,
-		.fini = _nouveau_falcon_fini,
-		.rd32 = _nouveau_falcon_rd32,
-		.wr32 = _nouveau_falcon_wr32,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nve0.c b/drivers/gpu/drm/nouveau/core/engine/bsp/nve0.c
deleted file mode 100644
index ba6aeca0285e..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/bsp/nve0.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <engine/falcon.h>
-#include <engine/bsp.h>
-
-struct nve0_bsp_priv {
-	struct nouveau_falcon base;
-};
-
-/*******************************************************************************
- * BSP object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nve0_bsp_sclass[] = {
-	{ 0x95b1, &nouveau_object_ofuncs },
-	{},
-};
-
-/*******************************************************************************
- * PBSP context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nve0_bsp_cclass = {
-	.handle = NV_ENGCTX(BSP, 0xe0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_falcon_context_ctor,
-		.dtor = _nouveau_falcon_context_dtor,
-		.init = _nouveau_falcon_context_init,
-		.fini = _nouveau_falcon_context_fini,
-		.rd32 = _nouveau_falcon_context_rd32,
-		.wr32 = _nouveau_falcon_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PBSP engine/subdev functions
- ******************************************************************************/
-
-static int
-nve0_bsp_init(struct nouveau_object *object)
-{
-	struct nve0_bsp_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_falcon_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x084010, 0x0000fff2);
-	nv_wr32(priv, 0x08401c, 0x0000fff2);
-	return 0;
-}
-
-static int
-nve0_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 size,
-	      struct nouveau_object **pobject)
-{
-	struct nve0_bsp_priv *priv;
-	int ret;
-
-	ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true,
-				    "PBSP", "bsp", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00008000;
-	nv_subdev(priv)->intr = nouveau_falcon_intr;
-	nv_engine(priv)->cclass = &nve0_bsp_cclass;
-	nv_engine(priv)->sclass = nve0_bsp_sclass;
-	return 0;
-}
-
-struct nouveau_oclass
-nve0_bsp_oclass = {
-	.handle = NV_ENGINE(BSP, 0xe0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nve0_bsp_ctor,
-		.dtor = _nouveau_falcon_dtor,
-		.init = nve0_bsp_init,
-		.fini = _nouveau_falcon_fini,
-		.rd32 = _nouveau_falcon_rd32,
-		.wr32 = _nouveau_falcon_wr32,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc b/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc
deleted file mode 100644
index 219850d53286..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc
+++ /dev/null
@@ -1,872 +0,0 @@
-/* fuc microcode for copy engine on nva3- chipsets
- *
- * Copyright 2011 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-/* To build for nva3:nvc0
- *    m4 -DNVA3 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nva3_copy.fuc.h
- *
- * To build for nvc0-
- *    m4 -DNVC0 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_copy.fuc.h
- */
-
-ifdef(`NVA3',
-.section #nva3_pcopy_data
-,
-.section #nvc0_pcopy_data
-)
-
-ctx_object:                   .b32 0
-ifdef(`NVA3',
-ctx_dma:
-ctx_dma_query:                .b32 0
-ctx_dma_src:                  .b32 0
-ctx_dma_dst:                  .b32 0
-,)
-.equ #ctx_dma_count 3
-ctx_query_address_high:       .b32 0
-ctx_query_address_low:        .b32 0
-ctx_query_counter:            .b32 0
-ctx_src_address_high:         .b32 0
-ctx_src_address_low:          .b32 0
-ctx_src_pitch:                .b32 0
-ctx_src_tile_mode:            .b32 0
-ctx_src_xsize:                .b32 0
-ctx_src_ysize:                .b32 0
-ctx_src_zsize:                .b32 0
-ctx_src_zoff:                 .b32 0
-ctx_src_xoff:                 .b32 0
-ctx_src_yoff:                 .b32 0
-ctx_src_cpp:                  .b32 0
-ctx_dst_address_high:         .b32 0
-ctx_dst_address_low:          .b32 0
-ctx_dst_pitch:                .b32 0
-ctx_dst_tile_mode:            .b32 0
-ctx_dst_xsize:                .b32 0
-ctx_dst_ysize:                .b32 0
-ctx_dst_zsize:                .b32 0
-ctx_dst_zoff:                 .b32 0
-ctx_dst_xoff:                 .b32 0
-ctx_dst_yoff:                 .b32 0
-ctx_dst_cpp:                  .b32 0
-ctx_format:                   .b32 0
-ctx_swz_const0:               .b32 0
-ctx_swz_const1:               .b32 0
-ctx_xcnt:                     .b32 0
-ctx_ycnt:                     .b32 0
-.align 256
-
-dispatch_table:
-// mthd 0x0000, NAME
-.b16 0x000 1
-.b32 #ctx_object                     ~0xffffffff
-// mthd 0x0100, NOP
-.b16 0x040 1
-.b32 0x00010000 + #cmd_nop           ~0xffffffff
-// mthd 0x0140, PM_TRIGGER
-.b16 0x050 1
-.b32 0x00010000 + #cmd_pm_trigger    ~0xffffffff
-ifdef(`NVA3', `
-// mthd 0x0180-0x018c, DMA_
-.b16 0x060 #ctx_dma_count
-dispatch_dma:
-.b32 0x00010000 + #cmd_dma           ~0xffffffff
-.b32 0x00010000 + #cmd_dma           ~0xffffffff
-.b32 0x00010000 + #cmd_dma           ~0xffffffff
-',)
-// mthd 0x0200-0x0218, SRC_TILE
-.b16 0x80 7
-.b32 #ctx_src_tile_mode              ~0x00000fff
-.b32 #ctx_src_xsize                  ~0x0007ffff
-.b32 #ctx_src_ysize                  ~0x00001fff
-.b32 #ctx_src_zsize                  ~0x000007ff
-.b32 #ctx_src_zoff                   ~0x00000fff
-.b32 #ctx_src_xoff                   ~0x0007ffff
-.b32 #ctx_src_yoff                   ~0x00001fff
-// mthd 0x0220-0x0238, DST_TILE
-.b16 0x88 7
-.b32 #ctx_dst_tile_mode              ~0x00000fff
-.b32 #ctx_dst_xsize                  ~0x0007ffff
-.b32 #ctx_dst_ysize                  ~0x00001fff
-.b32 #ctx_dst_zsize                  ~0x000007ff
-.b32 #ctx_dst_zoff                   ~0x00000fff
-.b32 #ctx_dst_xoff                   ~0x0007ffff
-.b32 #ctx_dst_yoff                   ~0x00001fff
-// mthd 0x0300-0x0304, EXEC, WRCACHE_FLUSH
-.b16 0xc0 2
-.b32 0x00010000 + #cmd_exec          ~0xffffffff
-.b32 0x00010000 + #cmd_wrcache_flush ~0xffffffff
-// mthd 0x030c-0x0340, various stuff
-.b16 0xc3 14
-.b32 #ctx_src_address_high           ~0x000000ff
-.b32 #ctx_src_address_low            ~0xffffffff
-.b32 #ctx_dst_address_high           ~0x000000ff
-.b32 #ctx_dst_address_low            ~0xffffffff
-.b32 #ctx_src_pitch                  ~0x0007ffff
-.b32 #ctx_dst_pitch                  ~0x0007ffff
-.b32 #ctx_xcnt                       ~0x0000ffff
-.b32 #ctx_ycnt                       ~0x00001fff
-.b32 #ctx_format                     ~0x0333ffff
-.b32 #ctx_swz_const0                 ~0xffffffff
-.b32 #ctx_swz_const1                 ~0xffffffff
-.b32 #ctx_query_address_high         ~0x000000ff
-.b32 #ctx_query_address_low          ~0xffffffff
-.b32 #ctx_query_counter              ~0xffffffff
-.b16 0x800 0
-
-ifdef(`NVA3',
-.section #nva3_pcopy_code
-,
-.section #nvc0_pcopy_code
-)
-
-main:
-   clear b32 $r0
-   mov $sp $r0
-
-   // setup i0 handler and route fifo and ctxswitch to it
-   mov $r1 #ih
-   mov $iv0 $r1
-   mov $r1 0x400
-   movw $r2 0xfff3
-   sethi $r2 0
-   iowr I[$r1 + 0x300] $r2
-
-   // enable interrupts
-   or $r2 0xc
-   iowr I[$r1] $r2
-   bset $flags ie0
-
-   // enable fifo access and context switching
-   mov $r1 0x1200
-   mov $r2 3
-   iowr I[$r1] $r2
-
-   // sleep forever, waking for interrupts
-   bset $flags $p0
-   spin:
-      sleep $p0
-      bra #spin
-
-// i0 handler
-ih:
-   iord $r1 I[$r0 + 0x200]
-
-   and $r2 $r1 0x00000008
-   bra e #ih_no_chsw
-      call #chsw
-   ih_no_chsw:
-   and $r2 $r1 0x00000004
-   bra e #ih_no_cmd
-      call #dispatch
-
-   ih_no_cmd:
-   and $r1 $r1 0x0000000c
-   iowr I[$r0 + 0x100] $r1
-   iret
-
-// $p1 direction (0 = unload, 1 = load)
-// $r3 channel
-swctx:
-   mov $r4 0x7700
-   mov $xtargets $r4
-ifdef(`NVA3', `
-   // target 7 hardcoded to ctx dma object
-   mov $xdbase $r0
-', ` // NVC0
-   // read SCRATCH3 to decide if we are PCOPY0 or PCOPY1
-   mov $r4 0x2100
-   iord $r4 I[$r4 + 0]
-   and $r4 1
-   shl b32 $r4 4
-   add b32 $r4 0x30
-
-   // channel is in vram
-   mov $r15 0x61c
-   shl b32 $r15 6
-   mov $r5 0x114
-   iowrs I[$r15] $r5
-
-   // read 16-byte PCOPYn info, containing context pointer, from channel
-   shl b32 $r5 $r3 4
-   add b32 $r5 2
-   mov $xdbase $r5
-   mov $r5 $sp
-   // get a chunk of stack space, aligned to 256 byte boundary
-   sub b32 $r5 0x100
-   mov $r6 0xff
-   not b32 $r6
-   and $r5 $r6
-   sethi $r5 0x00020000
-   xdld $r4 $r5
-   xdwait
-   sethi $r5 0
-
-   // set context pointer, from within channel VM
-   mov $r14 0
-   iowrs I[$r15] $r14
-   ld b32 $r4 D[$r5 + 0]
-   shr b32 $r4 8
-   ld b32 $r6 D[$r5 + 4]
-   shl b32 $r6 24
-   or $r4 $r6
-   mov $xdbase $r4
-')
-   // 256-byte context, at start of data segment
-   mov b32 $r4 $r0
-   sethi $r4 0x60000
-
-   // swap!
-   bra $p1 #swctx_load
-      xdst $r0 $r4
-      bra #swctx_done
-   swctx_load:
-      xdld $r0 $r4
-   swctx_done:
-   xdwait
-   ret
-
-chsw:
-   // read current channel
-   mov $r2 0x1400
-   iord $r3 I[$r2]
-
-   // if it's active, unload it and return
-   xbit $r15 $r3 0x1e
-   bra e #chsw_no_unload
-      bclr $flags $p1
-      call #swctx
-      bclr $r3 0x1e
-      iowr I[$r2] $r3
-      mov $r4 1
-      iowr I[$r2 + 0x200] $r4
-      ret
-
-   // read next channel
-   chsw_no_unload:
-   iord $r3 I[$r2 + 0x100]
-
-   // is there a channel waiting to be loaded?
-   xbit $r13 $r3 0x1e
-   bra e #chsw_finish_load
-      bset $flags $p1
-      call #swctx
-ifdef(`NVA3',
-      // load dma objects back into TARGET regs
-      mov $r5 #ctx_dma
-      mov $r6 #ctx_dma_count
-      chsw_load_ctx_dma:
-         ld b32 $r7 D[$r5 + $r6 * 4]
-         add b32 $r8 $r6 0x180
-         shl b32 $r8 8
-         iowr I[$r8] $r7
-         sub b32 $r6 1
-         bra nc #chsw_load_ctx_dma
-,)
-
-   chsw_finish_load:
-   mov $r3 2
-   iowr I[$r2 + 0x200] $r3
-   ret
-
-dispatch:
-   // read incoming fifo command
-   mov $r3 0x1900
-   iord $r2 I[$r3 + 0x100]
-   iord $r3 I[$r3 + 0x000]
-   and $r4 $r2 0x7ff
-   // $r2 will be used to store exception data
-   shl b32 $r2 0x10
-
-   // lookup method in the dispatch table, ILLEGAL_MTHD if not found
-   mov $r5 #dispatch_table
-   clear b32 $r6
-   clear b32 $r7
-   dispatch_loop:
-      ld b16 $r6 D[$r5 + 0]
-      ld b16 $r7 D[$r5 + 2]
-      add b32 $r5 4
-      cmpu b32 $r4 $r6
-      bra c #dispatch_illegal_mthd
-      add b32 $r7 $r6
-      cmpu b32 $r4 $r7
-      bra c #dispatch_valid_mthd
-      sub b32 $r7 $r6
-      shl b32 $r7 3
-      add b32 $r5 $r7
-      bra #dispatch_loop
-
-   // ensure no bits set in reserved fields, INVALID_BITFIELD
-   dispatch_valid_mthd:
-   sub b32 $r4 $r6
-   shl b32 $r4 3
-   add b32 $r4 $r5
-   ld b32 $r5 D[$r4 + 4]
-   and $r5 $r3
-   cmpu b32 $r5 0
-   bra ne #dispatch_invalid_bitfield
-
-   // depending on dispatch flags: execute method, or save data as state
-   ld b16 $r5 D[$r4 + 0]
-   ld b16 $r6 D[$r4 + 2]
-   cmpu b32 $r6 0
-   bra ne #dispatch_cmd
-      st b32 D[$r5] $r3
-      bra #dispatch_done
-   dispatch_cmd:
-      bclr $flags $p1
-      call $r5
-      bra $p1 #dispatch_error
-      bra #dispatch_done
-
-   dispatch_invalid_bitfield:
-   or $r2 2
-   dispatch_illegal_mthd:
-   or $r2 1
-
-   // store exception data in SCRATCH0/SCRATCH1, signal hostirq
-   dispatch_error:
-   mov $r4 0x1000
-   iowr I[$r4 + 0x000] $r2
-   iowr I[$r4 + 0x100] $r3
-   mov $r2 0x40
-   iowr I[$r0] $r2
-   hostirq_wait:
-      iord $r2 I[$r0 + 0x200]
-      and $r2 0x40
-      cmpu b32 $r2 0
-      bra ne #hostirq_wait
-
-   dispatch_done:
-   mov $r2 0x1d00
-   mov $r3 1
-   iowr I[$r2] $r3
-   ret
-
-// No-operation
-//
-// Inputs:
-//    $r1: irqh state
-//    $r2: hostirq state
-//    $r3: data
-//    $r4: dispatch table entry
-// Outputs:
-//    $r1: irqh state
-//    $p1: set on error
-//       $r2: hostirq state
-//       $r3: data
-cmd_nop:
-   ret
-
-// PM_TRIGGER
-//
-// Inputs:
-//    $r1: irqh state
-//    $r2: hostirq state
-//    $r3: data
-//    $r4: dispatch table entry
-// Outputs:
-//    $r1: irqh state
-//    $p1: set on error
-//       $r2: hostirq state
-//       $r3: data
-cmd_pm_trigger:
-   mov $r2 0x2200
-   clear b32 $r3
-   sethi $r3 0x20000
-   iowr I[$r2] $r3
-   ret
-
-ifdef(`NVA3',
-// SET_DMA_* method handler
-//
-// Inputs:
-//    $r1: irqh state
-//    $r2: hostirq state
-//    $r3: data
-//    $r4: dispatch table entry
-// Outputs:
-//    $r1: irqh state
-//    $p1: set on error
-//       $r2: hostirq state
-//       $r3: data
-cmd_dma:
-   sub b32 $r4 #dispatch_dma
-   shr b32 $r4 1
-   bset $r3 0x1e
-   st b32 D[$r4 + #ctx_dma] $r3
-   add b32 $r4 0x600
-   shl b32 $r4 6
-   iowr I[$r4] $r3
-   ret
-,)
-
-// Calculates the hw swizzle mask and adjusts the surface's xcnt to match
-//
-cmd_exec_set_format:
-   // zero out a chunk of the stack to store the swizzle into
-   add $sp -0x10
-   st b32 D[$sp + 0x00] $r0
-   st b32 D[$sp + 0x04] $r0
-   st b32 D[$sp + 0x08] $r0
-   st b32 D[$sp + 0x0c] $r0
-
-   // extract cpp, src_ncomp and dst_ncomp from FORMAT
-   ld b32 $r4 D[$r0 + #ctx_format]
-   extr $r5 $r4 16:17
-   add b32 $r5 1
-   extr $r6 $r4 20:21
-   add b32 $r6 1
-   extr $r7 $r4 24:25
-   add b32 $r7 1
-
-   // convert FORMAT swizzle mask to hw swizzle mask
-   bclr $flags $p2
-   clear b32 $r8
-   clear b32 $r9
-   ncomp_loop:
-      and $r10 $r4 0xf
-      shr b32 $r4 4
-      clear b32 $r11
-      bpc_loop:
-         cmpu b8 $r10 4
-         bra nc #cmp_c0
-            mulu $r12 $r10 $r5
-            add b32 $r12 $r11
-            bset $flags $p2
-            bra #bpc_next
-         cmp_c0:
-         bra ne #cmp_c1
-            mov $r12 0x10
-            add b32 $r12 $r11
-            bra #bpc_next
-         cmp_c1:
-         cmpu b8 $r10 6
-         bra nc #cmp_zero
-            mov $r12 0x14
-            add b32 $r12 $r11
-            bra #bpc_next
-         cmp_zero:
-            mov $r12 0x80
-         bpc_next:
-         st b8 D[$sp + $r8] $r12
-         add b32 $r8 1
-         add b32 $r11 1
-         cmpu b32 $r11 $r5
-         bra c #bpc_loop
-      add b32 $r9 1
-      cmpu b32 $r9 $r7
-      bra c #ncomp_loop
-
-   // SRC_XCNT = (xcnt * src_cpp), or 0 if no src ref in swz (hw will hang)
-   mulu $r6 $r5
-   st b32 D[$r0 + #ctx_src_cpp] $r6
-   ld b32 $r8 D[$r0 + #ctx_xcnt]
-   mulu $r6 $r8
-   bra $p2 #dst_xcnt
-   clear b32 $r6
-
-   dst_xcnt:
-   mulu $r7 $r5
-   st b32 D[$r0 + #ctx_dst_cpp] $r7
-   mulu $r7 $r8
-
-   mov $r5 0x810
-   shl b32 $r5 6
-   iowr I[$r5 + 0x000] $r6
-   iowr I[$r5 + 0x100] $r7
-   add b32 $r5 0x800
-   ld b32 $r6 D[$r0 + #ctx_dst_cpp]
-   sub b32 $r6 1
-   shl b32 $r6 8
-   ld b32 $r7 D[$r0 + #ctx_src_cpp]
-   sub b32 $r7 1
-   or $r6 $r7
-   iowr I[$r5 + 0x000] $r6
-   add b32 $r5 0x100
-   ld b32 $r6 D[$sp + 0x00]
-   iowr I[$r5 + 0x000] $r6
-   ld b32 $r6 D[$sp + 0x04]
-   iowr I[$r5 + 0x100] $r6
-   ld b32 $r6 D[$sp + 0x08]
-   iowr I[$r5 + 0x200] $r6
-   ld b32 $r6 D[$sp + 0x0c]
-   iowr I[$r5 + 0x300] $r6
-   add b32 $r5 0x400
-   ld b32 $r6 D[$r0 + #ctx_swz_const0]
-   iowr I[$r5 + 0x000] $r6
-   ld b32 $r6 D[$r0 + #ctx_swz_const1]
-   iowr I[$r5 + 0x100] $r6
-   add $sp 0x10
-   ret
-
-// Setup to handle a tiled surface
-//
-// Calculates a number of parameters the hardware requires in order
-// to correctly handle tiling.
-//
-// Offset calculation is performed as follows (Tp/Th/Td from TILE_MODE):
-//    nTx = round_up(w * cpp, 1 << Tp) >> Tp
-//    nTy = round_up(h, 1 << Th) >> Th
-//    Txo = (x * cpp) & ((1 << Tp) - 1)
-//     Tx = (x * cpp) >> Tp
-//    Tyo = y & ((1 << Th) - 1)
-//     Ty = y >> Th
-//    Tzo = z & ((1 << Td) - 1)
-//     Tz = z >> Td
-//
-//    off  = (Tzo << Tp << Th) + (Tyo << Tp) + Txo
-//    off += ((Tz * nTy * nTx)) + (Ty * nTx) + Tx) << Td << Th << Tp;
-//
-// Inputs:
-//    $r4: hw command (0x104800)
-//    $r5: ctx offset adjustment for src/dst selection
-//    $p2: set if dst surface
-//
-cmd_exec_set_surface_tiled:
-   // translate TILE_MODE into Tp, Th, Td shift values
-   ld b32 $r7 D[$r5 + #ctx_src_tile_mode]
-   extr $r9 $r7 8:11
-   extr $r8 $r7 4:7
-ifdef(`NVA3',
-   add b32 $r8 2
-,
-   add b32 $r8 3
-)
-   extr $r7 $r7 0:3
-   cmp b32 $r7 0xe
-   bra ne #xtile64
-   mov $r7 4
-   bra #xtileok
-   xtile64:
-   xbit $r7 $flags $p2
-   add b32 $r7 17
-   bset $r4 $r7
-   mov $r7 6
-   xtileok:
-
-   // Op = (x * cpp) & ((1 << Tp) - 1)
-   // Tx = (x * cpp) >> Tp
-   ld b32 $r10 D[$r5 + #ctx_src_xoff]
-   ld b32 $r11 D[$r5 + #ctx_src_cpp]
-   mulu $r10 $r11
-   mov $r11 1
-   shl b32 $r11 $r7
-   sub b32 $r11 1
-   and $r12 $r10 $r11
-   shr b32 $r10 $r7
-
-   // Tyo = y & ((1 << Th) - 1)
-   // Ty  = y >> Th
-   ld b32 $r13 D[$r5 + #ctx_src_yoff]
-   mov $r14 1
-   shl b32 $r14 $r8
-   sub b32 $r14 1
-   and $r11 $r13 $r14
-   shr b32 $r13 $r8
-
-   // YTILE = ((1 << Th) << 12) | ((1 << Th) - Tyo)
-   add b32 $r14 1
-   shl b32 $r15 $r14 12
-   sub b32 $r14 $r11
-   or $r15 $r14
-   xbit $r6 $flags $p2
-   add b32 $r6 0x208
-   shl b32 $r6 8
-   iowr I[$r6 + 0x000] $r15
-
-   // Op += Tyo << Tp
-   shl b32 $r11 $r7
-   add b32 $r12 $r11
-
-   // nTx = ((w * cpp) + ((1 << Tp) - 1) >> Tp)
-   ld b32 $r15 D[$r5 + #ctx_src_xsize]
-   ld b32 $r11 D[$r5 + #ctx_src_cpp]
-   mulu $r15 $r11
-   mov $r11 1
-   shl b32 $r11 $r7
-   sub b32 $r11 1
-   add b32 $r15 $r11
-   shr b32 $r15 $r7
-   push $r15
-
-   // nTy = (h + ((1 << Th) - 1)) >> Th
-   ld b32 $r15 D[$r5 + #ctx_src_ysize]
-   mov $r11 1
-   shl b32 $r11 $r8
-   sub b32 $r11 1
-   add b32 $r15 $r11
-   shr b32 $r15 $r8
-   push $r15
-
-   // Tys = Tp + Th
-   // CFG_YZ_TILE_SIZE = ((1 << Th) >> 2) << Td
-   add b32 $r7 $r8
-   sub b32 $r8 2
-   mov $r11 1
-   shl b32 $r11 $r8
-   shl b32 $r11 $r9
-
-   // Tzo = z & ((1 << Td) - 1)
-   // Tz  = z >> Td
-   // Op += Tzo << Tys
-   // Ts  = Tys + Td
-   ld b32 $r8 D[$r5 + #ctx_src_zoff]
-   mov $r14 1
-   shl b32 $r14 $r9
-   sub b32 $r14 1
-   and $r15 $r8 $r14
-   shl b32 $r15 $r7
-   add b32 $r12 $r15
-   add b32 $r7 $r9
-   shr b32 $r8 $r9
-
-   // Ot = ((Tz * nTy * nTx) + (Ty * nTx) + Tx) << Ts
-   pop $r15
-   pop $r9
-   mulu $r13 $r9
-   add b32 $r10 $r13
-   mulu $r8 $r9
-   mulu $r8 $r15
-   add b32 $r10 $r8
-   shl b32 $r10 $r7
-
-   // PITCH = (nTx - 1) << Ts
-   sub b32 $r9 1
-   shl b32 $r9 $r7
-   iowr I[$r6 + 0x200] $r9
-
-   // SRC_ADDRESS_LOW   = (Ot + Op) & 0xffffffff
-   // CFG_ADDRESS_HIGH |= ((Ot + Op) >> 32) << 16
-   ld b32 $r7 D[$r5 + #ctx_src_address_low]
-   ld b32 $r8 D[$r5 + #ctx_src_address_high]
-   add b32 $r10 $r12
-   add b32 $r7 $r10
-   adc b32 $r8 0
-   shl b32 $r8 16
-   or $r8 $r11
-   sub b32 $r6 0x600
-   iowr I[$r6 + 0x000] $r7
-   add b32 $r6 0x400
-   iowr I[$r6 + 0x000] $r8
-   ret
-
-// Setup to handle a linear surface
-//
-// Nothing to see here.. Sets ADDRESS and PITCH, pretty non-exciting
-//
-cmd_exec_set_surface_linear:
-   xbit $r6 $flags $p2
-   add b32 $r6 0x202
-   shl b32 $r6 8
-   ld b32 $r7 D[$r5 + #ctx_src_address_low]
-   iowr I[$r6 + 0x000] $r7
-   add b32 $r6 0x400
-   ld b32 $r7 D[$r5 + #ctx_src_address_high]
-   shl b32 $r7 16
-   iowr I[$r6 + 0x000] $r7
-   add b32 $r6 0x400
-   ld b32 $r7 D[$r5 + #ctx_src_pitch]
-   iowr I[$r6 + 0x000] $r7
-   ret
-
-// wait for regs to be available for use
-cmd_exec_wait:
-   push $r0
-   push $r1
-   mov $r0 0x800
-   shl b32 $r0 6
-   loop:
-      iord $r1 I[$r0]
-      and $r1 1
-      bra ne #loop
-   pop $r1
-   pop $r0
-   ret
-
-cmd_exec_query:
-   // if QUERY_SHORT not set, write out { -, 0, TIME_LO, TIME_HI }
-   xbit $r4 $r3 13
-   bra ne #query_counter
-      call #cmd_exec_wait
-      mov $r4 0x80c
-      shl b32 $r4 6
-      ld b32 $r5 D[$r0 + #ctx_query_address_low]
-      add b32 $r5 4
-      iowr I[$r4 + 0x000] $r5
-      iowr I[$r4 + 0x100] $r0
-      mov $r5 0xc
-      iowr I[$r4 + 0x200] $r5
-      add b32 $r4 0x400
-      ld b32 $r5 D[$r0 + #ctx_query_address_high]
-      shl b32 $r5 16
-      iowr I[$r4 + 0x000] $r5
-      add b32 $r4 0x500
-      mov $r5 0x00000b00
-      sethi $r5 0x00010000
-      iowr I[$r4 + 0x000] $r5
-      mov $r5 0x00004040
-      shl b32 $r5 1
-      sethi $r5 0x80800000
-      iowr I[$r4 + 0x100] $r5
-      mov $r5 0x00001110
-      sethi $r5 0x13120000
-      iowr I[$r4 + 0x200] $r5
-      mov $r5 0x00001514
-      sethi $r5 0x17160000
-      iowr I[$r4 + 0x300] $r5
-      mov $r5 0x00002601
-      sethi $r5 0x00010000
-      mov $r4 0x800
-      shl b32 $r4 6
-      iowr I[$r4 + 0x000] $r5
-
-   // write COUNTER
-   query_counter:
-   call #cmd_exec_wait
-   mov $r4 0x80c
-   shl b32 $r4 6
-   ld b32 $r5 D[$r0 + #ctx_query_address_low]
-   iowr I[$r4 + 0x000] $r5
-   iowr I[$r4 + 0x100] $r0
-   mov $r5 0x4
-   iowr I[$r4 + 0x200] $r5
-   add b32 $r4 0x400
-   ld b32 $r5 D[$r0 + #ctx_query_address_high]
-   shl b32 $r5 16
-   iowr I[$r4 + 0x000] $r5
-   add b32 $r4 0x500
-   mov $r5 0x00000300
-   iowr I[$r4 + 0x000] $r5
-   mov $r5 0x00001110
-   sethi $r5 0x13120000
-   iowr I[$r4 + 0x100] $r5
-   ld b32 $r5 D[$r0 + #ctx_query_counter]
-   add b32 $r4 0x500
-   iowr I[$r4 + 0x000] $r5
-   mov $r5 0x00002601
-   sethi $r5 0x00010000
-   mov $r4 0x800
-   shl b32 $r4 6
-   iowr I[$r4 + 0x000] $r5
-   ret
-
-// Execute a copy operation
-//
-// Inputs:
-//    $r1: irqh state
-//    $r2: hostirq state
-//    $r3: data
-//       000002000 QUERY_SHORT
-//       000001000 QUERY
-//       000000100 DST_LINEAR
-//       000000010 SRC_LINEAR
-//       000000001 FORMAT
-//    $r4: dispatch table entry
-// Outputs:
-//    $r1: irqh state
-//    $p1: set on error
-//       $r2: hostirq state
-//       $r3: data
-cmd_exec:
-   call #cmd_exec_wait
-
-   // if format requested, call function to calculate it, otherwise
-   // fill in cpp/xcnt for both surfaces as if (cpp == 1)
-   xbit $r15 $r3 0
-   bra e #cmd_exec_no_format
-      call #cmd_exec_set_format
-      mov $r4 0x200
-      bra #cmd_exec_init_src_surface
-   cmd_exec_no_format:
-      mov $r6 0x810
-      shl b32 $r6 6
-      mov $r7 1
-      st b32 D[$r0 + #ctx_src_cpp] $r7
-      st b32 D[$r0 + #ctx_dst_cpp] $r7
-      ld b32 $r7 D[$r0 + #ctx_xcnt]
-      iowr I[$r6 + 0x000] $r7
-      iowr I[$r6 + 0x100] $r7
-      clear b32 $r4
-
-   cmd_exec_init_src_surface:
-   bclr $flags $p2
-   clear b32 $r5
-   xbit $r15 $r3 4
-   bra e #src_tiled
-      call #cmd_exec_set_surface_linear
-      bra #cmd_exec_init_dst_surface
-   src_tiled:
-      call #cmd_exec_set_surface_tiled
-      bset $r4 7
-
-   cmd_exec_init_dst_surface:
-   bset $flags $p2
-   mov $r5 #ctx_dst_address_high - #ctx_src_address_high
-   xbit $r15 $r3 8
-   bra e #dst_tiled
-      call #cmd_exec_set_surface_linear
-      bra #cmd_exec_kick
-   dst_tiled:
-      call #cmd_exec_set_surface_tiled
-      bset $r4 8
-
-   cmd_exec_kick:
-   mov $r5 0x800
-   shl b32 $r5 6
-   ld b32 $r6 D[$r0 + #ctx_ycnt]
-   iowr I[$r5 + 0x100] $r6
-   mov $r6 0x0041
-   // SRC_TARGET = 1, DST_TARGET = 2
-   sethi $r6 0x44000000
-   or $r4 $r6
-   iowr I[$r5] $r4
-
-   // if requested, queue up a QUERY write after the copy has completed
-   xbit $r15 $r3 12
-   bra e #cmd_exec_done
-      call #cmd_exec_query
-
-   cmd_exec_done:
-   ret
-
-// Flush write cache
-//
-// Inputs:
-//    $r1: irqh state
-//    $r2: hostirq state
-//    $r3: data
-//    $r4: dispatch table entry
-// Outputs:
-//    $r1: irqh state
-//    $p1: set on error
-//       $r2: hostirq state
-//       $r3: data
-cmd_wrcache_flush:
-   mov $r2 0x2200
-   clear b32 $r3
-   sethi $r3 0x10000
-   iowr I[$r2] $r3
-   ret
-
-.align 0x100
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc.h b/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc.h
deleted file mode 100644
index 241b27201206..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc.h
+++ /dev/null
@@ -1,620 +0,0 @@
-uint32_t nva3_pcopy_data[] = {
-/* 0x0000: ctx_object */
-	0x00000000,
-/* 0x0004: ctx_dma */
-/* 0x0004: ctx_dma_query */
-	0x00000000,
-/* 0x0008: ctx_dma_src */
-	0x00000000,
-/* 0x000c: ctx_dma_dst */
-	0x00000000,
-/* 0x0010: ctx_query_address_high */
-	0x00000000,
-/* 0x0014: ctx_query_address_low */
-	0x00000000,
-/* 0x0018: ctx_query_counter */
-	0x00000000,
-/* 0x001c: ctx_src_address_high */
-	0x00000000,
-/* 0x0020: ctx_src_address_low */
-	0x00000000,
-/* 0x0024: ctx_src_pitch */
-	0x00000000,
-/* 0x0028: ctx_src_tile_mode */
-	0x00000000,
-/* 0x002c: ctx_src_xsize */
-	0x00000000,
-/* 0x0030: ctx_src_ysize */
-	0x00000000,
-/* 0x0034: ctx_src_zsize */
-	0x00000000,
-/* 0x0038: ctx_src_zoff */
-	0x00000000,
-/* 0x003c: ctx_src_xoff */
-	0x00000000,
-/* 0x0040: ctx_src_yoff */
-	0x00000000,
-/* 0x0044: ctx_src_cpp */
-	0x00000000,
-/* 0x0048: ctx_dst_address_high */
-	0x00000000,
-/* 0x004c: ctx_dst_address_low */
-	0x00000000,
-/* 0x0050: ctx_dst_pitch */
-	0x00000000,
-/* 0x0054: ctx_dst_tile_mode */
-	0x00000000,
-/* 0x0058: ctx_dst_xsize */
-	0x00000000,
-/* 0x005c: ctx_dst_ysize */
-	0x00000000,
-/* 0x0060: ctx_dst_zsize */
-	0x00000000,
-/* 0x0064: ctx_dst_zoff */
-	0x00000000,
-/* 0x0068: ctx_dst_xoff */
-	0x00000000,
-/* 0x006c: ctx_dst_yoff */
-	0x00000000,
-/* 0x0070: ctx_dst_cpp */
-	0x00000000,
-/* 0x0074: ctx_format */
-	0x00000000,
-/* 0x0078: ctx_swz_const0 */
-	0x00000000,
-/* 0x007c: ctx_swz_const1 */
-	0x00000000,
-/* 0x0080: ctx_xcnt */
-	0x00000000,
-/* 0x0084: ctx_ycnt */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0100: dispatch_table */
-	0x00010000,
-	0x00000000,
-	0x00000000,
-	0x00010040,
-	0x00010160,
-	0x00000000,
-	0x00010050,
-	0x00010162,
-	0x00000000,
-	0x00030060,
-/* 0x0128: dispatch_dma */
-	0x00010170,
-	0x00000000,
-	0x00010170,
-	0x00000000,
-	0x00010170,
-	0x00000000,
-	0x00070080,
-	0x00000028,
-	0xfffff000,
-	0x0000002c,
-	0xfff80000,
-	0x00000030,
-	0xffffe000,
-	0x00000034,
-	0xfffff800,
-	0x00000038,
-	0xfffff000,
-	0x0000003c,
-	0xfff80000,
-	0x00000040,
-	0xffffe000,
-	0x00070088,
-	0x00000054,
-	0xfffff000,
-	0x00000058,
-	0xfff80000,
-	0x0000005c,
-	0xffffe000,
-	0x00000060,
-	0xfffff800,
-	0x00000064,
-	0xfffff000,
-	0x00000068,
-	0xfff80000,
-	0x0000006c,
-	0xffffe000,
-	0x000200c0,
-	0x00010492,
-	0x00000000,
-	0x0001051b,
-	0x00000000,
-	0x000e00c3,
-	0x0000001c,
-	0xffffff00,
-	0x00000020,
-	0x00000000,
-	0x00000048,
-	0xffffff00,
-	0x0000004c,
-	0x00000000,
-	0x00000024,
-	0xfff80000,
-	0x00000050,
-	0xfff80000,
-	0x00000080,
-	0xffff0000,
-	0x00000084,
-	0xffffe000,
-	0x00000074,
-	0xfccc0000,
-	0x00000078,
-	0x00000000,
-	0x0000007c,
-	0x00000000,
-	0x00000010,
-	0xffffff00,
-	0x00000014,
-	0x00000000,
-	0x00000018,
-	0x00000000,
-	0x00000800,
-};
-
-uint32_t nva3_pcopy_code[] = {
-/* 0x0000: main */
-	0x04fe04bd,
-	0x3517f000,
-	0xf10010fe,
-	0xf1040017,
-	0xf0fff327,
-	0x12d00023,
-	0x0c25f0c0,
-	0xf40012d0,
-	0x17f11031,
-	0x27f01200,
-	0x0012d003,
-/* 0x002f: spin */
-	0xf40031f4,
-	0x0ef40028,
-/* 0x0035: ih */
-	0x8001cffd,
-	0xf40812c4,
-	0x21f4060b,
-/* 0x0041: ih_no_chsw */
-	0x0412c472,
-	0xf4060bf4,
-/* 0x004a: ih_no_cmd */
-	0x11c4c321,
-	0x4001d00c,
-/* 0x0052: swctx */
-	0x47f101f8,
-	0x4bfe7700,
-	0x0007fe00,
-	0xf00204b9,
-	0x01f40643,
-	0x0604fa09,
-/* 0x006b: swctx_load */
-	0xfa060ef4,
-/* 0x006e: swctx_done */
-	0x03f80504,
-/* 0x0072: chsw */
-	0x27f100f8,
-	0x23cf1400,
-	0x1e3fc800,
-	0xf4170bf4,
-	0x21f40132,
-	0x1e3af052,
-	0xf00023d0,
-	0x24d00147,
-/* 0x0093: chsw_no_unload */
-	0xcf00f880,
-	0x3dc84023,
-	0x220bf41e,
-	0xf40131f4,
-	0x57f05221,
-	0x0367f004,
-/* 0x00a8: chsw_load_ctx_dma */
-	0xa07856bc,
-	0xb6018068,
-	0x87d00884,
-	0x0162b600,
-/* 0x00bb: chsw_finish_load */
-	0xf0f018f4,
-	0x23d00237,
-/* 0x00c3: dispatch */
-	0xf100f880,
-	0xcf190037,
-	0x33cf4032,
-	0xff24e400,
-	0x1024b607,
-	0x010057f1,
-	0x74bd64bd,
-/* 0x00dc: dispatch_loop */
-	0x58005658,
-	0x50b60157,
-	0x0446b804,
-	0xbb4d08f4,
-	0x47b80076,
-	0x0f08f404,
-	0xb60276bb,
-	0x57bb0374,
-	0xdf0ef400,
-/* 0x0100: dispatch_valid_mthd */
-	0xb60246bb,
-	0x45bb0344,
-	0x01459800,
-	0xb00453fd,
-	0x1bf40054,
-	0x00455820,
-	0xb0014658,
-	0x1bf40064,
-	0x00538009,
-/* 0x0127: dispatch_cmd */
-	0xf4300ef4,
-	0x55f90132,
-	0xf40c01f4,
-/* 0x0132: dispatch_invalid_bitfield */
-	0x25f0250e,
-/* 0x0135: dispatch_illegal_mthd */
-	0x0125f002,
-/* 0x0138: dispatch_error */
-	0x100047f1,
-	0xd00042d0,
-	0x27f04043,
-	0x0002d040,
-/* 0x0148: hostirq_wait */
-	0xf08002cf,
-	0x24b04024,
-	0xf71bf400,
-/* 0x0154: dispatch_done */
-	0x1d0027f1,
-	0xd00137f0,
-	0x00f80023,
-/* 0x0160: cmd_nop */
-/* 0x0162: cmd_pm_trigger */
-	0x27f100f8,
-	0x34bd2200,
-	0xd00233f0,
-	0x00f80023,
-/* 0x0170: cmd_dma */
-	0x012842b7,
-	0xf00145b6,
-	0x43801e39,
-	0x0040b701,
-	0x0644b606,
-	0xf80043d0,
-/* 0x0189: cmd_exec_set_format */
-	0xf030f400,
-	0xb00001b0,
-	0x01b00101,
-	0x0301b002,
-	0xc71d0498,
-	0x50b63045,
-	0x3446c701,
-	0xc70160b6,
-	0x70b63847,
-	0x0232f401,
-	0x94bd84bd,
-/* 0x01b4: ncomp_loop */
-	0xb60f4ac4,
-	0xb4bd0445,
-/* 0x01bc: bpc_loop */
-	0xf404a430,
-	0xa5ff0f18,
-	0x00cbbbc0,
-	0xf40231f4,
-/* 0x01ce: cmp_c0 */
-	0x1bf4220e,
-	0x10c7f00c,
-	0xf400cbbb,
-/* 0x01da: cmp_c1 */
-	0xa430160e,
-	0x0c18f406,
-	0xbb14c7f0,
-	0x0ef400cb,
-/* 0x01e9: cmp_zero */
-	0x80c7f107,
-/* 0x01ed: bpc_next */
-	0x01c83800,
-	0xb60180b6,
-	0xb5b801b0,
-	0xc308f404,
-	0xb80190b6,
-	0x08f40497,
-	0x0065fdb2,
-	0x98110680,
-	0x68fd2008,
-	0x0502f400,
-/* 0x0216: dst_xcnt */
-	0x75fd64bd,
-	0x1c078000,
-	0xf10078fd,
-	0xb6081057,
-	0x56d00654,
-	0x4057d000,
-	0x080050b7,
-	0xb61c0698,
-	0x64b60162,
-	0x11079808,
-	0xfd0172b6,
-	0x56d00567,
-	0x0050b700,
-	0x0060b401,
-	0xb40056d0,
-	0x56d00160,
-	0x0260b440,
-	0xb48056d0,
-	0x56d00360,
-	0x0050b7c0,
-	0x1e069804,
-	0x980056d0,
-	0x56d01f06,
-	0x1030f440,
-/* 0x0276: cmd_exec_set_surface_tiled */
-	0x579800f8,
-	0x6879c70a,
-	0xb66478c7,
-	0x77c70280,
-	0x0e76b060,
-	0xf0091bf4,
-	0x0ef40477,
-/* 0x0291: xtile64 */
-	0x027cf00f,
-	0xfd1170b6,
-	0x77f00947,
-/* 0x029d: xtileok */
-	0x0f5a9806,
-	0xfd115b98,
-	0xb7f000ab,
-	0x04b7bb01,
-	0xff01b2b6,
-	0xa7bbc4ab,
-	0x105d9805,
-	0xbb01e7f0,
-	0xe2b604e8,
-	0xb4deff01,
-	0xb605d8bb,
-	0xef9401e0,
-	0x02ebbb0c,
-	0xf005fefd,
-	0x60b7026c,
-	0x64b60208,
-	0x006fd008,
-	0xbb04b7bb,
-	0x5f9800cb,
-	0x115b980b,
-	0xf000fbfd,
-	0xb7bb01b7,
-	0x01b2b604,
-	0xbb00fbbb,
-	0xf0f905f7,
-	0xf00c5f98,
-	0xb8bb01b7,
-	0x01b2b604,
-	0xbb00fbbb,
-	0xf0f905f8,
-	0xb60078bb,
-	0xb7f00282,
-	0x04b8bb01,
-	0x9804b9bb,
-	0xe7f00e58,
-	0x04e9bb01,
-	0xff01e2b6,
-	0xf7bbf48e,
-	0x00cfbb04,
-	0xbb0079bb,
-	0xf0fc0589,
-	0xd9fd90fc,
-	0x00adbb00,
-	0xfd0089fd,
-	0xa8bb008f,
-	0x04a7bb00,
-	0xbb0192b6,
-	0x69d00497,
-	0x08579880,
-	0xbb075898,
-	0x7abb00ac,
-	0x0081b600,
-	0xfd1084b6,
-	0x62b7058b,
-	0x67d00600,
-	0x0060b700,
-	0x0068d004,
-/* 0x0382: cmd_exec_set_surface_linear */
-	0x6cf000f8,
-	0x0260b702,
-	0x0864b602,
-	0xd0085798,
-	0x60b70067,
-	0x57980400,
-	0x1074b607,
-	0xb70067d0,
-	0x98040060,
-	0x67d00957,
-/* 0x03ab: cmd_exec_wait */
-	0xf900f800,
-	0xf110f900,
-	0xb6080007,
-/* 0x03b6: loop */
-	0x01cf0604,
-	0x0114f000,
-	0xfcfa1bf4,
-	0xf800fc10,
-/* 0x03c5: cmd_exec_query */
-	0x0d34c800,
-	0xf5701bf4,
-	0xf103ab21,
-	0xb6080c47,
-	0x05980644,
-	0x0450b605,
-	0xd00045d0,
-	0x57f04040,
-	0x8045d00c,
-	0x040040b7,
-	0xb6040598,
-	0x45d01054,
-	0x0040b700,
-	0x0057f105,
-	0x0153f00b,
-	0xf10045d0,
-	0xb6404057,
-	0x53f10154,
-	0x45d08080,
-	0x1057f140,
-	0x1253f111,
-	0x8045d013,
-	0x151457f1,
-	0x171653f1,
-	0xf1c045d0,
-	0xf0260157,
-	0x47f10153,
-	0x44b60800,
-	0x0045d006,
-/* 0x0438: query_counter */
-	0x03ab21f5,
-	0x080c47f1,
-	0x980644b6,
-	0x45d00505,
-	0x4040d000,
-	0xd00457f0,
-	0x40b78045,
-	0x05980400,
-	0x1054b604,
-	0xb70045d0,
-	0xf1050040,
-	0xd0030057,
-	0x57f10045,
-	0x53f11110,
-	0x45d01312,
-	0x06059840,
-	0x050040b7,
-	0xf10045d0,
-	0xf0260157,
-	0x47f10153,
-	0x44b60800,
-	0x0045d006,
-/* 0x0492: cmd_exec */
-	0x21f500f8,
-	0x3fc803ab,
-	0x0e0bf400,
-	0x018921f5,
-	0x020047f1,
-/* 0x04a7: cmd_exec_no_format */
-	0xf11e0ef4,
-	0xb6081067,
-	0x77f00664,
-	0x11078001,
-	0x981c0780,
-	0x67d02007,
-	0x4067d000,
-/* 0x04c2: cmd_exec_init_src_surface */
-	0x32f444bd,
-	0xc854bd02,
-	0x0bf4043f,
-	0x8221f50a,
-	0x0a0ef403,
-/* 0x04d4: src_tiled */
-	0x027621f5,
-/* 0x04db: cmd_exec_init_dst_surface */
-	0xf40749f0,
-	0x57f00231,
-	0x083fc82c,
-	0xf50a0bf4,
-	0xf4038221,
-/* 0x04ee: dst_tiled */
-	0x21f50a0e,
-	0x49f00276,
-/* 0x04f5: cmd_exec_kick */
-	0x0057f108,
-	0x0654b608,
-	0xd0210698,
-	0x67f04056,
-	0x0063f141,
-	0x0546fd44,
-	0xc80054d0,
-	0x0bf40c3f,
-	0xc521f507,
-/* 0x0519: cmd_exec_done */
-/* 0x051b: cmd_wrcache_flush */
-	0xf100f803,
-	0xbd220027,
-	0x0133f034,
-	0xf80023d0,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h
deleted file mode 100644
index 98cc4216a372..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h
+++ /dev/null
@@ -1,606 +0,0 @@
-uint32_t nvc0_pcopy_data[] = {
-/* 0x0000: ctx_object */
-	0x00000000,
-/* 0x0004: ctx_query_address_high */
-	0x00000000,
-/* 0x0008: ctx_query_address_low */
-	0x00000000,
-/* 0x000c: ctx_query_counter */
-	0x00000000,
-/* 0x0010: ctx_src_address_high */
-	0x00000000,
-/* 0x0014: ctx_src_address_low */
-	0x00000000,
-/* 0x0018: ctx_src_pitch */
-	0x00000000,
-/* 0x001c: ctx_src_tile_mode */
-	0x00000000,
-/* 0x0020: ctx_src_xsize */
-	0x00000000,
-/* 0x0024: ctx_src_ysize */
-	0x00000000,
-/* 0x0028: ctx_src_zsize */
-	0x00000000,
-/* 0x002c: ctx_src_zoff */
-	0x00000000,
-/* 0x0030: ctx_src_xoff */
-	0x00000000,
-/* 0x0034: ctx_src_yoff */
-	0x00000000,
-/* 0x0038: ctx_src_cpp */
-	0x00000000,
-/* 0x003c: ctx_dst_address_high */
-	0x00000000,
-/* 0x0040: ctx_dst_address_low */
-	0x00000000,
-/* 0x0044: ctx_dst_pitch */
-	0x00000000,
-/* 0x0048: ctx_dst_tile_mode */
-	0x00000000,
-/* 0x004c: ctx_dst_xsize */
-	0x00000000,
-/* 0x0050: ctx_dst_ysize */
-	0x00000000,
-/* 0x0054: ctx_dst_zsize */
-	0x00000000,
-/* 0x0058: ctx_dst_zoff */
-	0x00000000,
-/* 0x005c: ctx_dst_xoff */
-	0x00000000,
-/* 0x0060: ctx_dst_yoff */
-	0x00000000,
-/* 0x0064: ctx_dst_cpp */
-	0x00000000,
-/* 0x0068: ctx_format */
-	0x00000000,
-/* 0x006c: ctx_swz_const0 */
-	0x00000000,
-/* 0x0070: ctx_swz_const1 */
-	0x00000000,
-/* 0x0074: ctx_xcnt */
-	0x00000000,
-/* 0x0078: ctx_ycnt */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0100: dispatch_table */
-	0x00010000,
-	0x00000000,
-	0x00000000,
-	0x00010040,
-	0x0001019f,
-	0x00000000,
-	0x00010050,
-	0x000101a1,
-	0x00000000,
-	0x00070080,
-	0x0000001c,
-	0xfffff000,
-	0x00000020,
-	0xfff80000,
-	0x00000024,
-	0xffffe000,
-	0x00000028,
-	0xfffff800,
-	0x0000002c,
-	0xfffff000,
-	0x00000030,
-	0xfff80000,
-	0x00000034,
-	0xffffe000,
-	0x00070088,
-	0x00000048,
-	0xfffff000,
-	0x0000004c,
-	0xfff80000,
-	0x00000050,
-	0xffffe000,
-	0x00000054,
-	0xfffff800,
-	0x00000058,
-	0xfffff000,
-	0x0000005c,
-	0xfff80000,
-	0x00000060,
-	0xffffe000,
-	0x000200c0,
-	0x000104b8,
-	0x00000000,
-	0x00010541,
-	0x00000000,
-	0x000e00c3,
-	0x00000010,
-	0xffffff00,
-	0x00000014,
-	0x00000000,
-	0x0000003c,
-	0xffffff00,
-	0x00000040,
-	0x00000000,
-	0x00000018,
-	0xfff80000,
-	0x00000044,
-	0xfff80000,
-	0x00000074,
-	0xffff0000,
-	0x00000078,
-	0xffffe000,
-	0x00000068,
-	0xfccc0000,
-	0x0000006c,
-	0x00000000,
-	0x00000070,
-	0x00000000,
-	0x00000004,
-	0xffffff00,
-	0x00000008,
-	0x00000000,
-	0x0000000c,
-	0x00000000,
-	0x00000800,
-};
-
-uint32_t nvc0_pcopy_code[] = {
-/* 0x0000: main */
-	0x04fe04bd,
-	0x3517f000,
-	0xf10010fe,
-	0xf1040017,
-	0xf0fff327,
-	0x12d00023,
-	0x0c25f0c0,
-	0xf40012d0,
-	0x17f11031,
-	0x27f01200,
-	0x0012d003,
-/* 0x002f: spin */
-	0xf40031f4,
-	0x0ef40028,
-/* 0x0035: ih */
-	0x8001cffd,
-	0xf40812c4,
-	0x21f4060b,
-/* 0x0041: ih_no_chsw */
-	0x0412c4ca,
-	0xf5070bf4,
-/* 0x004b: ih_no_cmd */
-	0xc4010221,
-	0x01d00c11,
-/* 0x0053: swctx */
-	0xf101f840,
-	0xfe770047,
-	0x47f1004b,
-	0x44cf2100,
-	0x0144f000,
-	0xb60444b6,
-	0xf7f13040,
-	0xf4b6061c,
-	0x1457f106,
-	0x00f5d101,
-	0xb6043594,
-	0x57fe0250,
-	0x0145fe00,
-	0x010052b7,
-	0x00ff67f1,
-	0x56fd60bd,
-	0x0253f004,
-	0xf80545fa,
-	0x0053f003,
-	0xd100e7f0,
-	0x549800fe,
-	0x0845b600,
-	0xb6015698,
-	0x46fd1864,
-	0x0047fe05,
-	0xf00204b9,
-	0x01f40643,
-	0x0604fa09,
-/* 0x00c3: swctx_load */
-	0xfa060ef4,
-/* 0x00c6: swctx_done */
-	0x03f80504,
-/* 0x00ca: chsw */
-	0x27f100f8,
-	0x23cf1400,
-	0x1e3fc800,
-	0xf4170bf4,
-	0x21f40132,
-	0x1e3af053,
-	0xf00023d0,
-	0x24d00147,
-/* 0x00eb: chsw_no_unload */
-	0xcf00f880,
-	0x3dc84023,
-	0x090bf41e,
-	0xf40131f4,
-/* 0x00fa: chsw_finish_load */
-	0x37f05321,
-	0x8023d002,
-/* 0x0102: dispatch */
-	0x37f100f8,
-	0x32cf1900,
-	0x0033cf40,
-	0x07ff24e4,
-	0xf11024b6,
-	0xbd010057,
-/* 0x011b: dispatch_loop */
-	0x5874bd64,
-	0x57580056,
-	0x0450b601,
-	0xf40446b8,
-	0x76bb4d08,
-	0x0447b800,
-	0xbb0f08f4,
-	0x74b60276,
-	0x0057bb03,
-/* 0x013f: dispatch_valid_mthd */
-	0xbbdf0ef4,
-	0x44b60246,
-	0x0045bb03,
-	0xfd014598,
-	0x54b00453,
-	0x201bf400,
-	0x58004558,
-	0x64b00146,
-	0x091bf400,
-	0xf4005380,
-/* 0x0166: dispatch_cmd */
-	0x32f4300e,
-	0xf455f901,
-	0x0ef40c01,
-/* 0x0171: dispatch_invalid_bitfield */
-	0x0225f025,
-/* 0x0174: dispatch_illegal_mthd */
-/* 0x0177: dispatch_error */
-	0xf10125f0,
-	0xd0100047,
-	0x43d00042,
-	0x4027f040,
-/* 0x0187: hostirq_wait */
-	0xcf0002d0,
-	0x24f08002,
-	0x0024b040,
-/* 0x0193: dispatch_done */
-	0xf1f71bf4,
-	0xf01d0027,
-	0x23d00137,
-/* 0x019f: cmd_nop */
-	0xf800f800,
-/* 0x01a1: cmd_pm_trigger */
-	0x0027f100,
-	0xf034bd22,
-	0x23d00233,
-/* 0x01af: cmd_exec_set_format */
-	0xf400f800,
-	0x01b0f030,
-	0x0101b000,
-	0xb00201b0,
-	0x04980301,
-	0x3045c71a,
-	0xc70150b6,
-	0x60b63446,
-	0x3847c701,
-	0xf40170b6,
-	0x84bd0232,
-/* 0x01da: ncomp_loop */
-	0x4ac494bd,
-	0x0445b60f,
-/* 0x01e2: bpc_loop */
-	0xa430b4bd,
-	0x0f18f404,
-	0xbbc0a5ff,
-	0x31f400cb,
-	0x220ef402,
-/* 0x01f4: cmp_c0 */
-	0xf00c1bf4,
-	0xcbbb10c7,
-	0x160ef400,
-/* 0x0200: cmp_c1 */
-	0xf406a430,
-	0xc7f00c18,
-	0x00cbbb14,
-/* 0x020f: cmp_zero */
-	0xf1070ef4,
-/* 0x0213: bpc_next */
-	0x380080c7,
-	0x80b601c8,
-	0x01b0b601,
-	0xf404b5b8,
-	0x90b6c308,
-	0x0497b801,
-	0xfdb208f4,
-	0x06800065,
-	0x1d08980e,
-	0xf40068fd,
-	0x64bd0502,
-/* 0x023c: dst_xcnt */
-	0x800075fd,
-	0x78fd1907,
-	0x1057f100,
-	0x0654b608,
-	0xd00056d0,
-	0x50b74057,
-	0x06980800,
-	0x0162b619,
-	0x980864b6,
-	0x72b60e07,
-	0x0567fd01,
-	0xb70056d0,
-	0xb4010050,
-	0x56d00060,
-	0x0160b400,
-	0xb44056d0,
-	0x56d00260,
-	0x0360b480,
-	0xb7c056d0,
-	0x98040050,
-	0x56d01b06,
-	0x1c069800,
-	0xf44056d0,
-	0x00f81030,
-/* 0x029c: cmd_exec_set_surface_tiled */
-	0xc7075798,
-	0x78c76879,
-	0x0380b664,
-	0xb06077c7,
-	0x1bf40e76,
-	0x0477f009,
-/* 0x02b7: xtile64 */
-	0xf00f0ef4,
-	0x70b6027c,
-	0x0947fd11,
-/* 0x02c3: xtileok */
-	0x980677f0,
-	0x5b980c5a,
-	0x00abfd0e,
-	0xbb01b7f0,
-	0xb2b604b7,
-	0xc4abff01,
-	0x9805a7bb,
-	0xe7f00d5d,
-	0x04e8bb01,
-	0xff01e2b6,
-	0xd8bbb4de,
-	0x01e0b605,
-	0xbb0cef94,
-	0xfefd02eb,
-	0x026cf005,
-	0x020860b7,
-	0xd00864b6,
-	0xb7bb006f,
-	0x00cbbb04,
-	0x98085f98,
-	0xfbfd0e5b,
-	0x01b7f000,
-	0xb604b7bb,
-	0xfbbb01b2,
-	0x05f7bb00,
-	0x5f98f0f9,
-	0x01b7f009,
-	0xb604b8bb,
-	0xfbbb01b2,
-	0x05f8bb00,
-	0x78bbf0f9,
-	0x0282b600,
-	0xbb01b7f0,
-	0xb9bb04b8,
-	0x0b589804,
-	0xbb01e7f0,
-	0xe2b604e9,
-	0xf48eff01,
-	0xbb04f7bb,
-	0x79bb00cf,
-	0x0589bb00,
-	0x90fcf0fc,
-	0xbb00d9fd,
-	0x89fd00ad,
-	0x008ffd00,
-	0xbb00a8bb,
-	0x92b604a7,
-	0x0497bb01,
-	0x988069d0,
-	0x58980557,
-	0x00acbb04,
-	0xb6007abb,
-	0x84b60081,
-	0x058bfd10,
-	0x060062b7,
-	0xb70067d0,
-	0xd0040060,
-	0x00f80068,
-/* 0x03a8: cmd_exec_set_surface_linear */
-	0xb7026cf0,
-	0xb6020260,
-	0x57980864,
-	0x0067d005,
-	0x040060b7,
-	0xb6045798,
-	0x67d01074,
-	0x0060b700,
-	0x06579804,
-	0xf80067d0,
-/* 0x03d1: cmd_exec_wait */
-	0xf900f900,
-	0x0007f110,
-	0x0604b608,
-/* 0x03dc: loop */
-	0xf00001cf,
-	0x1bf40114,
-	0xfc10fcfa,
-/* 0x03eb: cmd_exec_query */
-	0xc800f800,
-	0x1bf40d34,
-	0xd121f570,
-	0x0c47f103,
-	0x0644b608,
-	0xb6020598,
-	0x45d00450,
-	0x4040d000,
-	0xd00c57f0,
-	0x40b78045,
-	0x05980400,
-	0x1054b601,
-	0xb70045d0,
-	0xf1050040,
-	0xf00b0057,
-	0x45d00153,
-	0x4057f100,
-	0x0154b640,
-	0x808053f1,
-	0xf14045d0,
-	0xf1111057,
-	0xd0131253,
-	0x57f18045,
-	0x53f11514,
-	0x45d01716,
-	0x0157f1c0,
-	0x0153f026,
-	0x080047f1,
-	0xd00644b6,
-/* 0x045e: query_counter */
-	0x21f50045,
-	0x47f103d1,
-	0x44b6080c,
-	0x02059806,
-	0xd00045d0,
-	0x57f04040,
-	0x8045d004,
-	0x040040b7,
-	0xb6010598,
-	0x45d01054,
-	0x0040b700,
-	0x0057f105,
-	0x0045d003,
-	0x111057f1,
-	0x131253f1,
-	0x984045d0,
-	0x40b70305,
-	0x45d00500,
-	0x0157f100,
-	0x0153f026,
-	0x080047f1,
-	0xd00644b6,
-	0x00f80045,
-/* 0x04b8: cmd_exec */
-	0x03d121f5,
-	0xf4003fc8,
-	0x21f50e0b,
-	0x47f101af,
-	0x0ef40200,
-/* 0x04cd: cmd_exec_no_format */
-	0x1067f11e,
-	0x0664b608,
-	0x800177f0,
-	0x07800e07,
-	0x1d079819,
-	0xd00067d0,
-	0x44bd4067,
-/* 0x04e8: cmd_exec_init_src_surface */
-	0xbd0232f4,
-	0x043fc854,
-	0xf50a0bf4,
-	0xf403a821,
-/* 0x04fa: src_tiled */
-	0x21f50a0e,
-	0x49f0029c,
-/* 0x0501: cmd_exec_init_dst_surface */
-	0x0231f407,
-	0xc82c57f0,
-	0x0bf4083f,
-	0xa821f50a,
-	0x0a0ef403,
-/* 0x0514: dst_tiled */
-	0x029c21f5,
-/* 0x051b: cmd_exec_kick */
-	0xf10849f0,
-	0xb6080057,
-	0x06980654,
-	0x4056d01e,
-	0xf14167f0,
-	0xfd440063,
-	0x54d00546,
-	0x0c3fc800,
-	0xf5070bf4,
-/* 0x053f: cmd_exec_done */
-	0xf803eb21,
-/* 0x0541: cmd_wrcache_flush */
-	0x0027f100,
-	0xf034bd22,
-	0x23d00133,
-	0x0000f800,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c b/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
deleted file mode 100644
index abb410ef09ea..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <engine/falcon.h>
-#include <engine/fifo.h>
-#include <engine/copy.h>
-
-#include <subdev/fb.h>
-#include <subdev/vm.h>
-
-#include <core/client.h>
-#include <core/enum.h>
-
-
-#include "fuc/nva3.fuc.h"
-
-struct nva3_copy_priv {
-	struct nouveau_falcon base;
-};
-
-/*******************************************************************************
- * Copy object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nva3_copy_sclass[] = {
-	{ 0x85b5, &nouveau_object_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * PCOPY context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nva3_copy_cclass = {
-	.handle = NV_ENGCTX(COPY0, 0xa3),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_falcon_context_ctor,
-		.dtor = _nouveau_falcon_context_dtor,
-		.init = _nouveau_falcon_context_init,
-		.fini = _nouveau_falcon_context_fini,
-		.rd32 = _nouveau_falcon_context_rd32,
-		.wr32 = _nouveau_falcon_context_wr32,
-
-	},
-};
-
-/*******************************************************************************
- * PCOPY engine/subdev functions
- ******************************************************************************/
-
-static const struct nouveau_enum nva3_copy_isr_error_name[] = {
-	{ 0x0001, "ILLEGAL_MTHD" },
-	{ 0x0002, "INVALID_ENUM" },
-	{ 0x0003, "INVALID_BITFIELD" },
-	{}
-};
-
-void
-nva3_copy_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
-	struct nouveau_engine *engine = nv_engine(subdev);
-	struct nouveau_falcon *falcon = (void *)subdev;
-	struct nouveau_object *engctx;
-	u32 dispatch = nv_ro32(falcon, 0x01c);
-	u32 stat = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16);
-	u64 inst = nv_ro32(falcon, 0x050) & 0x3fffffff;
-	u32 ssta = nv_ro32(falcon, 0x040) & 0x0000ffff;
-	u32 addr = nv_ro32(falcon, 0x040) >> 16;
-	u32 mthd = (addr & 0x07ff) << 2;
-	u32 subc = (addr & 0x3800) >> 11;
-	u32 data = nv_ro32(falcon, 0x044);
-	int chid;
-
-	engctx = nouveau_engctx_get(engine, inst);
-	chid   = pfifo->chid(pfifo, engctx);
-
-	if (stat & 0x00000040) {
-		nv_error(falcon, "DISPATCH_ERROR [");
-		nouveau_enum_print(nva3_copy_isr_error_name, ssta);
-		pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n",
-		       chid, inst << 12, nouveau_client_name(engctx), subc,
-		       mthd, data);
-		nv_wo32(falcon, 0x004, 0x00000040);
-		stat &= ~0x00000040;
-	}
-
-	if (stat) {
-		nv_error(falcon, "unhandled intr 0x%08x\n", stat);
-		nv_wo32(falcon, 0x004, stat);
-	}
-
-	nouveau_engctx_put(engctx);
-}
-
-static int
-nva3_copy_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	bool enable = (nv_device(parent)->chipset != 0xaf);
-	struct nva3_copy_priv *priv;
-	int ret;
-
-	ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, enable,
-				    "PCE0", "copy0", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00802000;
-	nv_subdev(priv)->intr = nva3_copy_intr;
-	nv_engine(priv)->cclass = &nva3_copy_cclass;
-	nv_engine(priv)->sclass = nva3_copy_sclass;
-	nv_falcon(priv)->code.data = nva3_pcopy_code;
-	nv_falcon(priv)->code.size = sizeof(nva3_pcopy_code);
-	nv_falcon(priv)->data.data = nva3_pcopy_data;
-	nv_falcon(priv)->data.size = sizeof(nva3_pcopy_data);
-	return 0;
-}
-
-struct nouveau_oclass
-nva3_copy_oclass = {
-	.handle = NV_ENGINE(COPY0, 0xa3),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nva3_copy_ctor,
-		.dtor = _nouveau_falcon_dtor,
-		.init = _nouveau_falcon_init,
-		.fini = _nouveau_falcon_fini,
-		.rd32 = _nouveau_falcon_rd32,
-		.wr32 = _nouveau_falcon_wr32,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
deleted file mode 100644
index 9261694d0d35..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <engine/falcon.h>
-#include <engine/fifo.h>
-#include <engine/copy.h>
-
-#include <core/enum.h>
-#include <core/enum.h>
-
-#include "fuc/nvc0.fuc.h"
-
-struct nvc0_copy_priv {
-	struct nouveau_falcon base;
-};
-
-/*******************************************************************************
- * Copy object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nvc0_copy0_sclass[] = {
-	{ 0x90b5, &nouveau_object_ofuncs },
-	{},
-};
-
-static struct nouveau_oclass
-nvc0_copy1_sclass[] = {
-	{ 0x90b8, &nouveau_object_ofuncs },
-	{},
-};
-
-/*******************************************************************************
- * PCOPY context
- ******************************************************************************/
-
-static struct nouveau_ofuncs
-nvc0_copy_context_ofuncs = {
-	.ctor = _nouveau_falcon_context_ctor,
-	.dtor = _nouveau_falcon_context_dtor,
-	.init = _nouveau_falcon_context_init,
-	.fini = _nouveau_falcon_context_fini,
-	.rd32 = _nouveau_falcon_context_rd32,
-	.wr32 = _nouveau_falcon_context_wr32,
-};
-
-static struct nouveau_oclass
-nvc0_copy0_cclass = {
-	.handle = NV_ENGCTX(COPY0, 0xc0),
-	.ofuncs = &nvc0_copy_context_ofuncs,
-};
-
-static struct nouveau_oclass
-nvc0_copy1_cclass = {
-	.handle = NV_ENGCTX(COPY1, 0xc0),
-	.ofuncs = &nvc0_copy_context_ofuncs,
-};
-
-/*******************************************************************************
- * PCOPY engine/subdev functions
- ******************************************************************************/
-
-static int
-nvc0_copy_init(struct nouveau_object *object)
-{
-	struct nvc0_copy_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_falcon_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wo32(priv, 0x084, nv_engidx(object) - NVDEV_ENGINE_COPY0);
-	return 0;
-}
-
-static int
-nvc0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nvc0_copy_priv *priv;
-	int ret;
-
-	ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, true,
-				    "PCE0", "copy0", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00000040;
-	nv_subdev(priv)->intr = nva3_copy_intr;
-	nv_engine(priv)->cclass = &nvc0_copy0_cclass;
-	nv_engine(priv)->sclass = nvc0_copy0_sclass;
-	nv_falcon(priv)->code.data = nvc0_pcopy_code;
-	nv_falcon(priv)->code.size = sizeof(nvc0_pcopy_code);
-	nv_falcon(priv)->data.data = nvc0_pcopy_data;
-	nv_falcon(priv)->data.size = sizeof(nvc0_pcopy_data);
-	return 0;
-}
-
-static int
-nvc0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nvc0_copy_priv *priv;
-	int ret;
-
-	ret = nouveau_falcon_create(parent, engine, oclass, 0x105000, true,
-				    "PCE1", "copy1", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00000080;
-	nv_subdev(priv)->intr = nva3_copy_intr;
-	nv_engine(priv)->cclass = &nvc0_copy1_cclass;
-	nv_engine(priv)->sclass = nvc0_copy1_sclass;
-	nv_falcon(priv)->code.data = nvc0_pcopy_code;
-	nv_falcon(priv)->code.size = sizeof(nvc0_pcopy_code);
-	nv_falcon(priv)->data.data = nvc0_pcopy_data;
-	nv_falcon(priv)->data.size = sizeof(nvc0_pcopy_data);
-	return 0;
-}
-
-struct nouveau_oclass
-nvc0_copy0_oclass = {
-	.handle = NV_ENGINE(COPY0, 0xc0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_copy0_ctor,
-		.dtor = _nouveau_falcon_dtor,
-		.init = nvc0_copy_init,
-		.fini = _nouveau_falcon_fini,
-		.rd32 = _nouveau_falcon_rd32,
-		.wr32 = _nouveau_falcon_wr32,
-	},
-};
-
-struct nouveau_oclass
-nvc0_copy1_oclass = {
-	.handle = NV_ENGINE(COPY1, 0xc0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_copy1_ctor,
-		.dtor = _nouveau_falcon_dtor,
-		.init = nvc0_copy_init,
-		.fini = _nouveau_falcon_fini,
-		.rd32 = _nouveau_falcon_rd32,
-		.wr32 = _nouveau_falcon_wr32,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
deleted file mode 100644
index c7194b354605..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/os.h>
-#include <core/enum.h>
-#include <core/engctx.h>
-
-#include <engine/copy.h>
-
-struct nve0_copy_priv {
-	struct nouveau_engine base;
-};
-
-/*******************************************************************************
- * Copy object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nve0_copy_sclass[] = {
-	{ 0xa0b5, &nouveau_object_ofuncs },
-	{},
-};
-
-/*******************************************************************************
- * PCOPY context
- ******************************************************************************/
-
-static struct nouveau_ofuncs
-nve0_copy_context_ofuncs = {
-	.ctor = _nouveau_engctx_ctor,
-	.dtor = _nouveau_engctx_dtor,
-	.init = _nouveau_engctx_init,
-	.fini = _nouveau_engctx_fini,
-	.rd32 = _nouveau_engctx_rd32,
-	.wr32 = _nouveau_engctx_wr32,
-};
-
-static struct nouveau_oclass
-nve0_copy_cclass = {
-	.handle = NV_ENGCTX(COPY0, 0xc0),
-	.ofuncs = &nve0_copy_context_ofuncs,
-};
-
-/*******************************************************************************
- * PCOPY engine/subdev functions
- ******************************************************************************/
-
-static void
-nve0_copy_intr(struct nouveau_subdev *subdev)
-{
-	const int ce = nv_subidx(nv_object(subdev)) - NVDEV_ENGINE_COPY0;
-	struct nve0_copy_priv *priv = (void *)subdev;
-	u32 stat = nv_rd32(priv, 0x104908 + (ce * 0x1000));
-
-	if (stat) {
-		nv_warn(priv, "unhandled intr 0x%08x\n", stat);
-		nv_wr32(priv, 0x104908 + (ce * 0x1000), stat);
-	}
-}
-
-static int
-nve0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nve0_copy_priv *priv;
-	int ret;
-
-	ret = nouveau_engine_create(parent, engine, oclass, true,
-				    "PCE0", "copy0", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00000040;
-	nv_subdev(priv)->intr = nve0_copy_intr;
-	nv_engine(priv)->cclass = &nve0_copy_cclass;
-	nv_engine(priv)->sclass = nve0_copy_sclass;
-	return 0;
-}
-
-static int
-nve0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nve0_copy_priv *priv;
-	int ret;
-
-	ret = nouveau_engine_create(parent, engine, oclass, true,
-				    "PCE1", "copy1", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00000080;
-	nv_subdev(priv)->intr = nve0_copy_intr;
-	nv_engine(priv)->cclass = &nve0_copy_cclass;
-	nv_engine(priv)->sclass = nve0_copy_sclass;
-	return 0;
-}
-
-static int
-nve0_copy2_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nve0_copy_priv *priv;
-	int ret;
-
-	ret = nouveau_engine_create(parent, engine, oclass, true,
-				    "PCE2", "copy2", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00200000;
-	nv_subdev(priv)->intr = nve0_copy_intr;
-	nv_engine(priv)->cclass = &nve0_copy_cclass;
-	nv_engine(priv)->sclass = nve0_copy_sclass;
-	return 0;
-}
-
-struct nouveau_oclass
-nve0_copy0_oclass = {
-	.handle = NV_ENGINE(COPY0, 0xe0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nve0_copy0_ctor,
-		.dtor = _nouveau_engine_dtor,
-		.init = _nouveau_engine_init,
-		.fini = _nouveau_engine_fini,
-	},
-};
-
-struct nouveau_oclass
-nve0_copy1_oclass = {
-	.handle = NV_ENGINE(COPY1, 0xe0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nve0_copy1_ctor,
-		.dtor = _nouveau_engine_dtor,
-		.init = _nouveau_engine_init,
-		.fini = _nouveau_engine_fini,
-	},
-};
-
-struct nouveau_oclass
-nve0_copy2_oclass = {
-	.handle = NV_ENGINE(COPY2, 0xe0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nve0_copy2_ctor,
-		.dtor = _nouveau_engine_dtor,
-		.init = _nouveau_engine_init,
-		.fini = _nouveau_engine_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc b/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc
deleted file mode 100644
index 629da02dc352..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc
+++ /dev/null
@@ -1,698 +0,0 @@
-/*
- *  fuc microcode for nv98 pcrypt engine
- *  Copyright (C) 2010  Marcin Kościelnicki
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-.section #nv98_pcrypt_data
-
-ctx_dma:
-ctx_dma_query:		.b32 0
-ctx_dma_src:		.b32 0
-ctx_dma_dst:		.b32 0
-.equ #dma_count 3
-ctx_query_address_high:	.b32 0
-ctx_query_address_low:	.b32 0
-ctx_query_counter:	.b32 0
-ctx_cond_address_high:	.b32 0
-ctx_cond_address_low:	.b32 0
-ctx_cond_off:		.b32 0
-ctx_src_address_high:	.b32 0
-ctx_src_address_low:	.b32 0
-ctx_dst_address_high:	.b32 0
-ctx_dst_address_low:	.b32 0
-ctx_mode:		.b32 0
-.align 16
-ctx_key:		.skip 16
-ctx_iv:			.skip 16
-
-.align 0x80
-swap:
-.skip 32
-
-.align 8
-common_cmd_dtable:
-.b32 #ctx_query_address_high + 0x20000 ~0xff
-.b32 #ctx_query_address_low + 0x20000 ~0xfffffff0
-.b32 #ctx_query_counter + 0x20000 ~0xffffffff
-.b32 #cmd_query_get + 0x00000 ~1
-.b32 #ctx_cond_address_high + 0x20000 ~0xff
-.b32 #ctx_cond_address_low + 0x20000 ~0xfffffff0
-.b32 #cmd_cond_mode + 0x00000 ~7
-.b32 #cmd_wrcache_flush + 0x00000 ~0
-.equ #common_cmd_max 0x88
-
-
-.align 8
-engine_cmd_dtable:
-.b32 #ctx_key + 0x0 + 0x20000 ~0xffffffff
-.b32 #ctx_key + 0x4 + 0x20000 ~0xffffffff
-.b32 #ctx_key + 0x8 + 0x20000 ~0xffffffff
-.b32 #ctx_key + 0xc + 0x20000 ~0xffffffff
-.b32 #ctx_iv + 0x0 + 0x20000 ~0xffffffff
-.b32 #ctx_iv + 0x4 + 0x20000 ~0xffffffff
-.b32 #ctx_iv + 0x8 + 0x20000 ~0xffffffff
-.b32 #ctx_iv + 0xc + 0x20000 ~0xffffffff
-.b32 #ctx_src_address_high + 0x20000 ~0xff
-.b32 #ctx_src_address_low + 0x20000 ~0xfffffff0
-.b32 #ctx_dst_address_high + 0x20000 ~0xff
-.b32 #ctx_dst_address_low + 0x20000 ~0xfffffff0
-.b32 #crypt_cmd_mode + 0x00000 ~0xf
-.b32 #crypt_cmd_length + 0x10000 ~0x0ffffff0
-.equ #engine_cmd_max 0xce
-
-.align 4
-crypt_dtable:
-.b16 #crypt_copy_prep #crypt_do_inout
-.b16 #crypt_store_prep #crypt_do_out
-.b16 #crypt_ecb_e_prep #crypt_do_inout
-.b16 #crypt_ecb_d_prep #crypt_do_inout
-.b16 #crypt_cbc_e_prep #crypt_do_inout
-.b16 #crypt_cbc_d_prep #crypt_do_inout
-.b16 #crypt_pcbc_e_prep #crypt_do_inout
-.b16 #crypt_pcbc_d_prep #crypt_do_inout
-.b16 #crypt_cfb_e_prep #crypt_do_inout
-.b16 #crypt_cfb_d_prep #crypt_do_inout
-.b16 #crypt_ofb_prep #crypt_do_inout
-.b16 #crypt_ctr_prep #crypt_do_inout
-.b16 #crypt_cbc_mac_prep #crypt_do_in
-.b16 #crypt_cmac_finish_complete_prep #crypt_do_in
-.b16 #crypt_cmac_finish_partial_prep #crypt_do_in
-
-.align 0x100
-
-.section #nv98_pcrypt_code
-
-	// $r0 is always set to 0 in our code - this allows some space savings.
-	clear b32 $r0
-
-	// set up the interrupt handler
-	mov $r1 #ih
-	mov $iv0 $r1
-
-	// init stack pointer
-	mov $sp $r0
-
-	// set interrupt dispatch - route timer, fifo, ctxswitch to i0, others to host
-	movw $r1 0xfff0
-	sethi $r1 0
-	mov $r2 0x400
-	iowr I[$r2 + 0x300] $r1
-
-	// enable the interrupts
-	or $r1 0xc
-	iowr I[$r2] $r1
-
-	// enable fifo access and context switching
-	mov $r1 3
-	mov $r2 0x1200
-	iowr I[$r2] $r1
-
-	// enable i0 delivery
-	bset $flags ie0
-
-	// sleep forver, waking only for interrupts.
-	bset $flags $p0
-	spin:
-	sleep $p0
-	bra #spin
-
-// i0 handler
-ih:
-	// see which interrupts we got
-	iord $r1 I[$r0 + 0x200]
-
-	and $r2 $r1 0x8
-	cmpu b32 $r2 0
-	bra e #noctx
-
-		// context switch... prepare the regs for xfer
-		mov $r2 0x7700
-		mov $xtargets $r2
-		mov $xdbase $r0
-		// 128-byte context.
-		mov $r2 0
-		sethi $r2 0x50000
-
-		// read current channel
-		mov $r3 0x1400
-		iord $r4 I[$r3]
-		// if bit 30 set, it's active, so we have to unload it first.
-		shl b32 $r5 $r4 1
-		cmps b32 $r5 0
-		bra nc #ctxload
-
-			// unload the current channel - save the context
-			xdst $r0 $r2
-			xdwait
-			// and clear bit 30, then write back
-			bclr $r4 0x1e
-			iowr I[$r3] $r4
-			// tell PFIFO we unloaded
-			mov $r4 1
-			iowr I[$r3 + 0x200] $r4
-
-		bra #noctx
-
-		ctxload:
-			// no channel loaded - perhaps we're requested to load one
-			iord $r4 I[$r3 + 0x100]
-			shl b32 $r15 $r4 1
-			cmps b32 $r15 0
-			// if bit 30 of next channel not set, probably PFIFO is just
-			// killing a context. do a faux load, without the active bit.
-			bra nc #dummyload
-
-				// ok, do a real context load.
-				xdld $r0 $r2
-				xdwait
-				mov $r5 #ctx_dma
-				mov $r6 #dma_count - 1
-				ctxload_dma_loop:
-					ld b32 $r7 D[$r5 + $r6 * 4]
-					add b32 $r8 $r6 0x180
-					shl b32 $r8 8
-					iowr I[$r8] $r7
-					sub b32 $r6 1
-				bra nc #ctxload_dma_loop
-
-			dummyload:
-			// tell PFIFO we're done
-			mov $r5 2
-			iowr I[$r3 + 0x200] $r5
-
-	noctx:
-	and $r2 $r1 0x4
-	cmpu b32 $r2 0
-	bra e #nocmd
-
-		// incoming fifo command.
-		mov $r3 0x1900
-		iord $r2 I[$r3 + 0x100]
-		iord $r3 I[$r3]
-		// extract the method
-		and $r4 $r2 0x7ff
-		// shift the addr to proper position if we need to interrupt later
-		shl b32 $r2 0x10
-
-		// mthd 0 and 0x100 [NAME, NOP]: ignore
-		and $r5 $r4 0x7bf
-		cmpu b32 $r5 0
-		bra e #cmddone
-
-		mov $r5 #engine_cmd_dtable - 0xc0 * 8
-		mov $r6 #engine_cmd_max
-		cmpu b32 $r4 0xc0
-		bra nc #dtable_cmd
-		mov $r5 #common_cmd_dtable - 0x80 * 8
-		mov $r6 #common_cmd_max
-		cmpu b32 $r4 0x80
-		bra nc #dtable_cmd
-		cmpu b32 $r4 0x60
-		bra nc #dma_cmd
-		cmpu b32 $r4 0x50
-		bra ne #illegal_mthd
-
-			// mthd 0x140: PM_TRIGGER
-			mov $r2 0x2200
-			clear b32 $r3
-			sethi $r3 0x20000
-			iowr I[$r2] $r3
-			bra #cmddone
-
-		dma_cmd:
-			// mthd 0x180...: DMA_*
-			cmpu b32 $r4 0x60+#dma_count
-			bra nc #illegal_mthd
-			shl b32 $r5 $r4 2
-			add b32 $r5 ((#ctx_dma - 0x60 * 4) & 0xffff)
-			bset $r3 0x1e
-			st b32 D[$r5] $r3
-			add b32 $r4 0x180 - 0x60
-			shl b32 $r4 8
-			iowr I[$r4] $r3
-			bra #cmddone
-
-		dtable_cmd:
-			cmpu b32 $r4 $r6
-			bra nc #illegal_mthd
-			shl b32 $r4 3
-			add b32 $r4 $r5
-			ld b32 $r5 D[$r4 + 4]
-			and $r5 $r3
-			cmpu b32 $r5 0
-			bra ne #invalid_bitfield
-			ld b16 $r5 D[$r4]
-			ld b16 $r6 D[$r4 + 2]
-			cmpu b32 $r6 2
-			bra e #cmd_setctx
-			ld b32 $r7 D[$r0 + #ctx_cond_off]
-			and $r6 $r7
-			cmpu b32 $r6 1
-			bra e #cmddone
-			call $r5
-			bra $p1 #dispatch_error
-			bra #cmddone
-
-		cmd_setctx:
-			st b32 D[$r5] $r3
-			bra #cmddone
-
-
-		invalid_bitfield:
-			or $r2 1
-		dispatch_error:
-		illegal_mthd:
-			mov $r4 0x1000
-			iowr I[$r4] $r2
-			iowr I[$r4 + 0x100] $r3
-			mov $r4 0x40
-			iowr I[$r0] $r4
-
-			im_loop:
-				iord $r4 I[$r0 + 0x200]
-				and $r4 0x40
-				cmpu b32 $r4 0
-			bra ne #im_loop
-
-		cmddone:
-		// remove the command from FIFO
-		mov $r3 0x1d00
-		mov $r4 1
-		iowr I[$r3] $r4
-
-	nocmd:
-	// ack the processed interrupts
-	and $r1 $r1 0xc
-	iowr I[$r0 + 0x100] $r1
-iret
-
-cmd_query_get:
-	// if bit 0 of param set, trigger interrupt afterwards.
-	setp $p1 $r3
-	or $r2 3
-
-	// read PTIMER, beware of races...
-	mov $r4 0xb00
-	ptimer_retry:
-		iord $r6 I[$r4 + 0x100]
-		iord $r5 I[$r4]
-		iord $r7 I[$r4 + 0x100]
-		cmpu b32 $r6 $r7
-	bra ne #ptimer_retry
-
-	// prepare the query structure
-	ld b32 $r4 D[$r0 + #ctx_query_counter]
-	st b32 D[$r0 + #swap + 0x0] $r4
-	st b32 D[$r0 + #swap + 0x4] $r0
-	st b32 D[$r0 + #swap + 0x8] $r5
-	st b32 D[$r0 + #swap + 0xc] $r6
-
-	// will use target 0, DMA_QUERY.
-	mov $xtargets $r0
-
-	ld b32 $r4 D[$r0 + #ctx_query_address_high]
-	shl b32 $r4 0x18
-	mov $xdbase $r4
-
-	ld b32 $r4 D[$r0 + #ctx_query_address_low]
-	mov $r5 #swap
-	sethi $r5 0x20000
-	xdst $r4 $r5
-	xdwait
-
-	ret
-
-cmd_cond_mode:
-	// if >= 5, INVALID_ENUM
-	bset $flags $p1
-	or $r2 2
-	cmpu b32 $r3 5
-	bra nc #return
-
-	// otherwise, no error.
-	bclr $flags $p1
-
-	// if < 2, no QUERY object is involved
-	cmpu b32 $r3 2
-	bra nc #cmd_cond_mode_queryful
-
-		xor $r3 1
-		st b32 D[$r0 + #ctx_cond_off] $r3
-	return:
-		ret
-
-	cmd_cond_mode_queryful:
-	// ok, will need to pull a QUERY object, prepare offsets
-	ld b32 $r4 D[$r0 + #ctx_cond_address_high]
-	ld b32 $r5 D[$r0 + #ctx_cond_address_low]
-	and $r6 $r5 0xff
-	shr b32 $r5 8
-	shl b32 $r4 0x18
-	or $r4 $r5
-	mov $xdbase $r4
-	mov $xtargets $r0
-
-	// pull the first one
-	mov $r5 #swap
-	sethi $r5 0x20000
-	xdld $r6 $r5
-
-	// if == 2, only a single QUERY is involved...
-	cmpu b32 $r3 2
-	bra ne #cmd_cond_mode_double
-
-		xdwait
-		ld b32 $r4 D[$r0 + #swap + 4]
-		cmpu b32 $r4 0
-		xbit $r4 $flags z
-		st b32 D[$r0 + #ctx_cond_off] $r4
-		ret
-
-	// ok, we'll need to pull second one too
-	cmd_cond_mode_double:
-	add b32 $r6 0x10
-	add b32 $r5 0x10
-	xdld $r6 $r5
-	xdwait
-
-	// compare COUNTERs
-	ld b32 $r5 D[$r0 + #swap + 0x00]
-	ld b32 $r6 D[$r0 + #swap + 0x10]
-	cmpu b32 $r5 $r6
-	xbit $r4 $flags z
-
-	// compare RESen
-	ld b32 $r5 D[$r0 + #swap + 0x04]
-	ld b32 $r6 D[$r0 + #swap + 0x14]
-	cmpu b32 $r5 $r6
-	xbit $r5 $flags z
-	and $r4 $r5
-
-	// and negate or not, depending on mode
-	cmpu b32 $r3 3
-	xbit $r5 $flags z
-	xor $r4 $r5
-	st b32 D[$r0 + #ctx_cond_off] $r4
-	ret
-
-cmd_wrcache_flush:
-	bclr $flags $p1
-	mov $r2 0x2200
-	clear b32 $r3
-	sethi $r3 0x10000
-	iowr I[$r2] $r3
-	ret
-
-crypt_cmd_mode:
-	// if >= 0xf, INVALID_ENUM
-	bset $flags $p1
-	or $r2 2
-	cmpu b32 $r3 0xf
-	bra nc #crypt_cmd_mode_return
-
-		bclr $flags $p1
-		st b32 D[$r0 + #ctx_mode] $r3
-
-	crypt_cmd_mode_return:
-	ret
-
-crypt_cmd_length:
-	// nop if length == 0
-	cmpu b32 $r3 0
-	bra e #crypt_cmd_mode_return
-
-	// init key, IV
-	cxset 3
-	mov $r4 #ctx_key
-	sethi $r4 0x70000
-	xdst $r0 $r4
-	mov $r4 #ctx_iv
-	sethi $r4 0x60000
-	xdst $r0 $r4
-	xdwait
-	ckeyreg $c7
-
-	// prepare the targets
-	mov $r4 0x2100
-	mov $xtargets $r4
-
-	// prepare src address
-	ld b32 $r4 D[$r0 + #ctx_src_address_high]
-	ld b32 $r5 D[$r0 + #ctx_src_address_low]
-	shr b32 $r8 $r5 8
-	shl b32 $r4 0x18
-	or $r4 $r8
-	and $r5 $r5 0xff
-
-	// prepare dst address
-	ld b32 $r6 D[$r0 + #ctx_dst_address_high]
-	ld b32 $r7 D[$r0 + #ctx_dst_address_low]
-	shr b32 $r8 $r7 8
-	shl b32 $r6 0x18
-	or $r6 $r8
-	and $r7 $r7 0xff
-
-	// find the proper prep & do functions
-	ld b32 $r8 D[$r0 + #ctx_mode]
-	shl b32 $r8 2
-
-	// run prep
-	ld b16 $r9 D[$r8 + #crypt_dtable]
-	call $r9
-
-	// do it
-	ld b16 $r9 D[$r8 + #crypt_dtable + 2]
-	call $r9
-	cxset 1
-	xdwait
-	cxset 0x61
-	xdwait
-	xdwait
-
-	// update src address
-	shr b32 $r8 $r4 0x18
-	shl b32 $r9 $r4 8
-	add b32 $r9 $r5
-	adc b32 $r8 0
-	st b32 D[$r0 + #ctx_src_address_high] $r8
-	st b32 D[$r0 + #ctx_src_address_low] $r9
-
-	// update dst address
-	shr b32 $r8 $r6 0x18
-	shl b32 $r9 $r6 8
-	add b32 $r9 $r7
-	adc b32 $r8 0
-	st b32 D[$r0 + #ctx_dst_address_high] $r8
-	st b32 D[$r0 + #ctx_dst_address_low] $r9
-
-	// pull updated IV
-	cxset 2
-	mov $r4 #ctx_iv
-	sethi $r4 0x60000
-	xdld $r0 $r4
-	xdwait
-
-	ret
-
-
-crypt_copy_prep:
-	cs0begin 2
-		cxsin $c0
-		cxsout $c0
-	ret
-
-crypt_store_prep:
-	cs0begin 1
-		cxsout $c6
-	ret
-
-crypt_ecb_e_prep:
-	cs0begin 3
-		cxsin $c0
-		cenc $c0 $c0
-		cxsout $c0
-	ret
-
-crypt_ecb_d_prep:
-	ckexp $c7 $c7
-	cs0begin 3
-		cxsin $c0
-		cdec $c0 $c0
-		cxsout $c0
-	ret
-
-crypt_cbc_e_prep:
-	cs0begin 4
-		cxsin $c0
-		cxor $c6 $c0
-		cenc $c6 $c6
-		cxsout $c6
-	ret
-
-crypt_cbc_d_prep:
-	ckexp $c7 $c7
-	cs0begin 5
-		cmov $c2 $c6
-		cxsin $c6
-		cdec $c0 $c6
-		cxor $c0 $c2
-		cxsout $c0
-	ret
-
-crypt_pcbc_e_prep:
-	cs0begin 5
-		cxsin $c0
-		cxor $c6 $c0
-		cenc $c6 $c6
-		cxsout $c6
-		cxor $c6 $c0
-	ret
-
-crypt_pcbc_d_prep:
-	ckexp $c7 $c7
-	cs0begin 5
-		cxsin $c0
-		cdec $c1 $c0
-		cxor $c6 $c1
-		cxsout $c6
-		cxor $c6 $c0
-	ret
-
-crypt_cfb_e_prep:
-	cs0begin 4
-		cenc $c6 $c6
-		cxsin $c0
-		cxor $c6 $c0
-		cxsout $c6
-	ret
-
-crypt_cfb_d_prep:
-	cs0begin 4
-		cenc $c0 $c6
-		cxsin $c6
-		cxor $c0 $c6
-		cxsout $c0
-	ret
-
-crypt_ofb_prep:
-	cs0begin 4
-		cenc $c6 $c6
-		cxsin $c0
-		cxor $c0 $c6
-		cxsout $c0
-	ret
-
-crypt_ctr_prep:
-	cs0begin 5
-		cenc $c1 $c6
-		cadd $c6 1
-		cxsin $c0
-		cxor $c0 $c1
-		cxsout $c0
-	ret
-
-crypt_cbc_mac_prep:
-	cs0begin 3
-		cxsin $c0
-		cxor $c6 $c0
-		cenc $c6 $c6
-	ret
-
-crypt_cmac_finish_complete_prep:
-	cs0begin 7
-		cxsin $c0
-		cxor $c6 $c0
-		cxor $c0 $c0
-		cenc $c0 $c0
-		cprecmac $c0 $c0
-		cxor $c6 $c0
-		cenc $c6 $c6
-	ret
-
-crypt_cmac_finish_partial_prep:
-	cs0begin 8
-		cxsin $c0
-		cxor $c6 $c0
-		cxor $c0 $c0
-		cenc $c0 $c0
-		cprecmac $c0 $c0
-		cprecmac $c0 $c0
-		cxor $c6 $c0
-		cenc $c6 $c6
-	ret
-
-// TODO
-crypt_do_in:
-	add b32 $r3 $r5
-	mov $xdbase $r4
-	mov $r9 #swap
-	sethi $r9 0x20000
-	crypt_do_in_loop:
-		xdld $r5 $r9
-		xdwait
-		cxset 0x22
-		xdst $r0 $r9
-		cs0exec 1
-		xdwait
-		add b32 $r5 0x10
-		cmpu b32 $r5 $r3
-	bra ne #crypt_do_in_loop
-	cxset 1
-	xdwait
-	ret
-
-crypt_do_out:
-	add b32 $r3 $r7
-	mov $xdbase $r6
-	mov $r9 #swap
-	sethi $r9 0x20000
-	crypt_do_out_loop:
-		cs0exec 1
-		cxset 0x61
-		xdld $r7 $r9
-		xdst $r7 $r9
-		cxset 1
-		xdwait
-		add b32 $r7 0x10
-		cmpu b32 $r7 $r3
-	bra ne #crypt_do_out_loop
-	ret
-
-crypt_do_inout:
-	add b32 $r3 $r5
-	mov $r9 #swap
-	sethi $r9 0x20000
-	crypt_do_inout_loop:
-		mov $xdbase $r4
-		xdld $r5 $r9
-		xdwait
-		cxset 0x21
-		xdst $r0 $r9
-		cs0exec 1
-		cxset 0x61
-		mov $xdbase $r6
-		xdld $r7 $r9
-		xdst $r7 $r9
-		cxset 1
-		xdwait
-		add b32 $r5 0x10
-		add b32 $r7 0x10
-		cmpu b32 $r5 $r3
-	bra ne #crypt_do_inout_loop
-	ret
-
-.align 0x100
diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc.h b/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc.h
deleted file mode 100644
index 38676c74e6e0..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc.h
+++ /dev/null
@@ -1,584 +0,0 @@
-uint32_t nv98_pcrypt_data[] = {
-/* 0x0000: ctx_dma */
-/* 0x0000: ctx_dma_query */
-	0x00000000,
-/* 0x0004: ctx_dma_src */
-	0x00000000,
-/* 0x0008: ctx_dma_dst */
-	0x00000000,
-/* 0x000c: ctx_query_address_high */
-	0x00000000,
-/* 0x0010: ctx_query_address_low */
-	0x00000000,
-/* 0x0014: ctx_query_counter */
-	0x00000000,
-/* 0x0018: ctx_cond_address_high */
-	0x00000000,
-/* 0x001c: ctx_cond_address_low */
-	0x00000000,
-/* 0x0020: ctx_cond_off */
-	0x00000000,
-/* 0x0024: ctx_src_address_high */
-	0x00000000,
-/* 0x0028: ctx_src_address_low */
-	0x00000000,
-/* 0x002c: ctx_dst_address_high */
-	0x00000000,
-/* 0x0030: ctx_dst_address_low */
-	0x00000000,
-/* 0x0034: ctx_mode */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0040: ctx_key */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0050: ctx_iv */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0080: swap */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x00a0: common_cmd_dtable */
-	0x0002000c,
-	0xffffff00,
-	0x00020010,
-	0x0000000f,
-	0x00020014,
-	0x00000000,
-	0x00000192,
-	0xfffffffe,
-	0x00020018,
-	0xffffff00,
-	0x0002001c,
-	0x0000000f,
-	0x000001d7,
-	0xfffffff8,
-	0x00000260,
-	0xffffffff,
-/* 0x00e0: engine_cmd_dtable */
-	0x00020040,
-	0x00000000,
-	0x00020044,
-	0x00000000,
-	0x00020048,
-	0x00000000,
-	0x0002004c,
-	0x00000000,
-	0x00020050,
-	0x00000000,
-	0x00020054,
-	0x00000000,
-	0x00020058,
-	0x00000000,
-	0x0002005c,
-	0x00000000,
-	0x00020024,
-	0xffffff00,
-	0x00020028,
-	0x0000000f,
-	0x0002002c,
-	0xffffff00,
-	0x00020030,
-	0x0000000f,
-	0x00000271,
-	0xfffffff0,
-	0x00010285,
-	0xf000000f,
-/* 0x0150: crypt_dtable */
-	0x04db0321,
-	0x04b1032f,
-	0x04db0339,
-	0x04db034b,
-	0x04db0361,
-	0x04db0377,
-	0x04db0395,
-	0x04db03af,
-	0x04db03cd,
-	0x04db03e3,
-	0x04db03f9,
-	0x04db040f,
-	0x04830429,
-	0x0483043b,
-	0x0483045d,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-uint32_t nv98_pcrypt_code[] = {
-	0x17f004bd,
-	0x0010fe35,
-	0xf10004fe,
-	0xf0fff017,
-	0x27f10013,
-	0x21d00400,
-	0x0c15f0c0,
-	0xf00021d0,
-	0x27f10317,
-	0x21d01200,
-	0x1031f400,
-/* 0x002f: spin */
-	0xf40031f4,
-	0x0ef40028,
-/* 0x0035: ih */
-	0x8001cffd,
-	0xb00812c4,
-	0x0bf40024,
-	0x0027f167,
-	0x002bfe77,
-	0xf00007fe,
-	0x23f00027,
-	0x0037f105,
-	0x0034cf14,
-	0xb0014594,
-	0x18f40055,
-	0x0602fa17,
-	0x4af003f8,
-	0x0034d01e,
-	0xd00147f0,
-	0x0ef48034,
-/* 0x0075: ctxload */
-	0x4034cf33,
-	0xb0014f94,
-	0x18f400f5,
-	0x0502fa21,
-	0x57f003f8,
-	0x0267f000,
-/* 0x008c: ctxload_dma_loop */
-	0xa07856bc,
-	0xb6018068,
-	0x87d00884,
-	0x0162b600,
-/* 0x009f: dummyload */
-	0xf0f018f4,
-	0x35d00257,
-/* 0x00a5: noctx */
-	0x0412c480,
-	0xf50024b0,
-	0xf100df0b,
-	0xcf190037,
-	0x33cf4032,
-	0xff24e400,
-	0x1024b607,
-	0x07bf45e4,
-	0xf50054b0,
-	0xf100b90b,
-	0xf1fae057,
-	0xb000ce67,
-	0x18f4c044,
-	0xa057f14d,
-	0x8867f1fc,
-	0x8044b000,
-	0xb03f18f4,
-	0x18f46044,
-	0x5044b019,
-	0xf1741bf4,
-	0xbd220027,
-	0x0233f034,
-	0xf50023d0,
-/* 0x0103: dma_cmd */
-	0xb000810e,
-	0x18f46344,
-	0x0245945e,
-	0xfe8050b7,
-	0x801e39f0,
-	0x40b70053,
-	0x44b60120,
-	0x0043d008,
-/* 0x0123: dtable_cmd */
-	0xb8600ef4,
-	0x18f40446,
-	0x0344b63e,
-	0x980045bb,
-	0x53fd0145,
-	0x0054b004,
-	0x58291bf4,
-	0x46580045,
-	0x0264b001,
-	0x98170bf4,
-	0x67fd0807,
-	0x0164b004,
-	0xf9300bf4,
-	0x0f01f455,
-/* 0x015b: cmd_setctx */
-	0x80280ef4,
-	0x0ef40053,
-/* 0x0161: invalid_bitfield */
-	0x0125f022,
-/* 0x0164: dispatch_error */
-/* 0x0164: illegal_mthd */
-	0x100047f1,
-	0xd00042d0,
-	0x47f04043,
-	0x0004d040,
-/* 0x0174: im_loop */
-	0xf08004cf,
-	0x44b04044,
-	0xf71bf400,
-/* 0x0180: cmddone */
-	0x1d0037f1,
-	0xd00147f0,
-/* 0x018a: nocmd */
-	0x11c40034,
-	0x4001d00c,
-/* 0x0192: cmd_query_get */
-	0x38f201f8,
-	0x0325f001,
-	0x0b0047f1,
-/* 0x019c: ptimer_retry */
-	0xcf4046cf,
-	0x47cf0045,
-	0x0467b840,
-	0x98f41bf4,
-	0x04800504,
-	0x21008020,
-	0x80220580,
-	0x0bfe2306,
-	0x03049800,
-	0xfe1844b6,
-	0x04980047,
-	0x8057f104,
-	0x0253f000,
-	0xf80645fa,
-/* 0x01d7: cmd_cond_mode */
-	0xf400f803,
-	0x25f00131,
-	0x0534b002,
-	0xf41218f4,
-	0x34b00132,
-	0x0b18f402,
-	0x800136f0,
-/* 0x01f2: return */
-	0x00f80803,
-/* 0x01f4: cmd_cond_mode_queryful */
-	0x98060498,
-	0x56c40705,
-	0x0855b6ff,
-	0xfd1844b6,
-	0x47fe0545,
-	0x000bfe00,
-	0x008057f1,
-	0xfa0253f0,
-	0x34b00565,
-	0x131bf402,
-	0x049803f8,
-	0x0044b021,
-	0x800b4cf0,
-	0x00f80804,
-/* 0x022c: cmd_cond_mode_double */
-	0xb61060b6,
-	0x65fa1050,
-	0x9803f805,
-	0x06982005,
-	0x0456b824,
-	0x980b4cf0,
-	0x06982105,
-	0x0456b825,
-	0xfd0b5cf0,
-	0x34b00445,
-	0x0b5cf003,
-	0x800645fd,
-	0x00f80804,
-/* 0x0260: cmd_wrcache_flush */
-	0xf10132f4,
-	0xbd220027,
-	0x0133f034,
-	0xf80023d0,
-/* 0x0271: crypt_cmd_mode */
-	0x0131f400,
-	0xb00225f0,
-	0x18f40f34,
-	0x0132f409,
-/* 0x0283: crypt_cmd_mode_return */
-	0xf80d0380,
-/* 0x0285: crypt_cmd_length */
-	0x0034b000,
-	0xf4fb0bf4,
-	0x47f0033c,
-	0x0743f040,
-	0xf00604fa,
-	0x43f05047,
-	0x0604fa06,
-	0x3cf503f8,
-	0x47f1c407,
-	0x4bfe2100,
-	0x09049800,
-	0x950a0598,
-	0x44b60858,
-	0x0548fd18,
-	0x98ff55c4,
-	0x07980b06,
-	0x0878950c,
-	0xfd1864b6,
-	0x77c40568,
-	0x0d0898ff,
-	0x580284b6,
-	0x95f9a889,
-	0xf9a98958,
-	0x013cf495,
-	0x3cf403f8,
-	0xf803f861,
-	0x18489503,
-	0xbb084994,
-	0x81b60095,
-	0x09088000,
-	0x950a0980,
-	0x69941868,
-	0x0097bb08,
-	0x800081b6,
-	0x09800b08,
-	0x023cf40c,
-	0xf05047f0,
-	0x04fa0643,
-	0xf803f805,
-/* 0x0321: crypt_copy_prep */
-	0x203cf500,
-	0x003cf594,
-	0x003cf588,
-/* 0x032f: crypt_store_prep */
-	0xf500f88c,
-	0xf594103c,
-	0xf88c063c,
-/* 0x0339: crypt_ecb_e_prep */
-	0x303cf500,
-	0x003cf594,
-	0x003cf588,
-	0x003cf5d0,
-/* 0x034b: crypt_ecb_d_prep */
-	0xf500f88c,
-	0xf5c8773c,
-	0xf594303c,
-	0xf588003c,
-	0xf5d4003c,
-	0xf88c003c,
-/* 0x0361: crypt_cbc_e_prep */
-	0x403cf500,
-	0x003cf594,
-	0x063cf588,
-	0x663cf5ac,
-	0x063cf5d0,
-/* 0x0377: crypt_cbc_d_prep */
-	0xf500f88c,
-	0xf5c8773c,
-	0xf594503c,
-	0xf584623c,
-	0xf588063c,
-	0xf5d4603c,
-	0xf5ac203c,
-	0xf88c003c,
-/* 0x0395: crypt_pcbc_e_prep */
-	0x503cf500,
-	0x003cf594,
-	0x063cf588,
-	0x663cf5ac,
-	0x063cf5d0,
-	0x063cf58c,
-/* 0x03af: crypt_pcbc_d_prep */
-	0xf500f8ac,
-	0xf5c8773c,
-	0xf594503c,
-	0xf588003c,
-	0xf5d4013c,
-	0xf5ac163c,
-	0xf58c063c,
-	0xf8ac063c,
-/* 0x03cd: crypt_cfb_e_prep */
-	0x403cf500,
-	0x663cf594,
-	0x003cf5d0,
-	0x063cf588,
-	0x063cf5ac,
-/* 0x03e3: crypt_cfb_d_prep */
-	0xf500f88c,
-	0xf594403c,
-	0xf5d0603c,
-	0xf588063c,
-	0xf5ac603c,
-	0xf88c003c,
-/* 0x03f9: crypt_ofb_prep */
-	0x403cf500,
-	0x663cf594,
-	0x003cf5d0,
-	0x603cf588,
-	0x003cf5ac,
-/* 0x040f: crypt_ctr_prep */
-	0xf500f88c,
-	0xf594503c,
-	0xf5d0613c,
-	0xf5b0163c,
-	0xf588003c,
-	0xf5ac103c,
-	0xf88c003c,
-/* 0x0429: crypt_cbc_mac_prep */
-	0x303cf500,
-	0x003cf594,
-	0x063cf588,
-	0x663cf5ac,
-/* 0x043b: crypt_cmac_finish_complete_prep */
-	0xf500f8d0,
-	0xf594703c,
-	0xf588003c,
-	0xf5ac063c,
-	0xf5ac003c,
-	0xf5d0003c,
-	0xf5bc003c,
-	0xf5ac063c,
-	0xf8d0663c,
-/* 0x045d: crypt_cmac_finish_partial_prep */
-	0x803cf500,
-	0x003cf594,
-	0x063cf588,
-	0x003cf5ac,
-	0x003cf5ac,
-	0x003cf5d0,
-	0x003cf5bc,
-	0x063cf5bc,
-	0x663cf5ac,
-/* 0x0483: crypt_do_in */
-	0xbb00f8d0,
-	0x47fe0035,
-	0x8097f100,
-	0x0293f000,
-/* 0x0490: crypt_do_in_loop */
-	0xf80559fa,
-	0x223cf403,
-	0xf50609fa,
-	0xf898103c,
-	0x1050b603,
-	0xf40453b8,
-	0x3cf4e91b,
-	0xf803f801,
-/* 0x04b1: crypt_do_out */
-	0x0037bb00,
-	0xf10067fe,
-	0xf0008097,
-/* 0x04be: crypt_do_out_loop */
-	0x3cf50293,
-	0x3cf49810,
-	0x0579fa61,
-	0xf40679fa,
-	0x03f8013c,
-	0xb81070b6,
-	0x1bf40473,
-/* 0x04db: crypt_do_inout */
-	0xbb00f8e8,
-	0x97f10035,
-	0x93f00080,
-/* 0x04e5: crypt_do_inout_loop */
-	0x0047fe02,
-	0xf80559fa,
-	0x213cf403,
-	0xf50609fa,
-	0xf498103c,
-	0x67fe613c,
-	0x0579fa00,
-	0xf40679fa,
-	0x03f8013c,
-	0xb61050b6,
-	0x53b81070,
-	0xd41bf404,
-	0x000000f8,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c b/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
deleted file mode 100644
index ea5c42f31791..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <core/os.h>
-#include <core/enum.h>
-#include <core/engctx.h>
-#include <core/gpuobj.h>
-
-#include <subdev/fb.h>
-
-#include <engine/fifo.h>
-#include <engine/crypt.h>
-
-struct nv84_crypt_priv {
-	struct nouveau_engine base;
-};
-
-/*******************************************************************************
- * Crypt object classes
- ******************************************************************************/
-
-static int
-nv84_crypt_object_ctor(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, void *data, u32 size,
-		       struct nouveau_object **pobject)
-{
-	struct nouveau_gpuobj *obj;
-	int ret;
-
-	ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
-				    16, 16, 0, &obj);
-	*pobject = nv_object(obj);
-	if (ret)
-		return ret;
-
-	nv_wo32(obj, 0x00, nv_mclass(obj));
-	nv_wo32(obj, 0x04, 0x00000000);
-	nv_wo32(obj, 0x08, 0x00000000);
-	nv_wo32(obj, 0x0c, 0x00000000);
-	return 0;
-}
-
-static struct nouveau_ofuncs
-nv84_crypt_ofuncs = {
-	.ctor = nv84_crypt_object_ctor,
-	.dtor = _nouveau_gpuobj_dtor,
-	.init = _nouveau_gpuobj_init,
-	.fini = _nouveau_gpuobj_fini,
-	.rd32 = _nouveau_gpuobj_rd32,
-	.wr32 = _nouveau_gpuobj_wr32,
-};
-
-static struct nouveau_oclass
-nv84_crypt_sclass[] = {
-	{ 0x74c1, &nv84_crypt_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * PCRYPT context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv84_crypt_cclass = {
-	.handle = NV_ENGCTX(CRYPT, 0x84),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_engctx_ctor,
-		.dtor = _nouveau_engctx_dtor,
-		.init = _nouveau_engctx_init,
-		.fini = _nouveau_engctx_fini,
-		.rd32 = _nouveau_engctx_rd32,
-		.wr32 = _nouveau_engctx_wr32,
-	},
-};
-
-/*******************************************************************************
- * PCRYPT engine/subdev functions
- ******************************************************************************/
-
-static const struct nouveau_bitfield nv84_crypt_intr_mask[] = {
-	{ 0x00000001, "INVALID_STATE" },
-	{ 0x00000002, "ILLEGAL_MTHD" },
-	{ 0x00000004, "ILLEGAL_CLASS" },
-	{ 0x00000080, "QUERY" },
-	{ 0x00000100, "FAULT" },
-	{}
-};
-
-static void
-nv84_crypt_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
-	struct nouveau_engine *engine = nv_engine(subdev);
-	struct nouveau_object *engctx;
-	struct nv84_crypt_priv *priv = (void *)subdev;
-	u32 stat = nv_rd32(priv, 0x102130);
-	u32 mthd = nv_rd32(priv, 0x102190);
-	u32 data = nv_rd32(priv, 0x102194);
-	u32 inst = nv_rd32(priv, 0x102188) & 0x7fffffff;
-	int chid;
-
-	engctx = nouveau_engctx_get(engine, inst);
-	chid   = pfifo->chid(pfifo, engctx);
-
-	if (stat) {
-		nv_error(priv, "%s", "");
-		nouveau_bitfield_print(nv84_crypt_intr_mask, stat);
-		pr_cont(" ch %d [0x%010llx %s] mthd 0x%04x data 0x%08x\n",
-		       chid, (u64)inst << 12, nouveau_client_name(engctx),
-		       mthd, data);
-	}
-
-	nv_wr32(priv, 0x102130, stat);
-	nv_wr32(priv, 0x10200c, 0x10);
-
-	nouveau_engctx_put(engctx);
-}
-
-static int
-nv84_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv84_crypt_priv *priv;
-	int ret;
-
-	ret = nouveau_engine_create(parent, engine, oclass, true,
-				    "PCRYPT", "crypt", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00004000;
-	nv_subdev(priv)->intr = nv84_crypt_intr;
-	nv_engine(priv)->cclass = &nv84_crypt_cclass;
-	nv_engine(priv)->sclass = nv84_crypt_sclass;
-	return 0;
-}
-
-static int
-nv84_crypt_init(struct nouveau_object *object)
-{
-	struct nv84_crypt_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_engine_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x102130, 0xffffffff);
-	nv_wr32(priv, 0x102140, 0xffffffbf);
-	nv_wr32(priv, 0x10200c, 0x00000010);
-	return 0;
-}
-
-struct nouveau_oclass
-nv84_crypt_oclass = {
-	.handle = NV_ENGINE(CRYPT, 0x84),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv84_crypt_ctor,
-		.dtor = _nouveau_engine_dtor,
-		.init = nv84_crypt_init,
-		.fini = _nouveau_engine_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c b/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
deleted file mode 100644
index 5571c09534cb..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <core/os.h>
-#include <core/enum.h>
-#include <core/engctx.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/falcon.h>
-#include <engine/fifo.h>
-#include <engine/crypt.h>
-
-#include "fuc/nv98.fuc.h"
-
-struct nv98_crypt_priv {
-	struct nouveau_falcon base;
-};
-
-/*******************************************************************************
- * Crypt object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv98_crypt_sclass[] = {
-	{ 0x88b4, &nouveau_object_ofuncs },
-	{},
-};
-
-/*******************************************************************************
- * PCRYPT context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv98_crypt_cclass = {
-	.handle = NV_ENGCTX(CRYPT, 0x98),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_falcon_context_ctor,
-		.dtor = _nouveau_falcon_context_dtor,
-		.init = _nouveau_falcon_context_init,
-		.fini = _nouveau_falcon_context_fini,
-		.rd32 = _nouveau_falcon_context_rd32,
-		.wr32 = _nouveau_falcon_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PCRYPT engine/subdev functions
- ******************************************************************************/
-
-static const struct nouveau_enum nv98_crypt_isr_error_name[] = {
-	{ 0x0000, "ILLEGAL_MTHD" },
-	{ 0x0001, "INVALID_BITFIELD" },
-	{ 0x0002, "INVALID_ENUM" },
-	{ 0x0003, "QUERY" },
-	{}
-};
-
-static void
-nv98_crypt_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
-	struct nouveau_engine *engine = nv_engine(subdev);
-	struct nouveau_object *engctx;
-	struct nv98_crypt_priv *priv = (void *)subdev;
-	u32 disp = nv_rd32(priv, 0x08701c);
-	u32 stat = nv_rd32(priv, 0x087008) & disp & ~(disp >> 16);
-	u32 inst = nv_rd32(priv, 0x087050) & 0x3fffffff;
-	u32 ssta = nv_rd32(priv, 0x087040) & 0x0000ffff;
-	u32 addr = nv_rd32(priv, 0x087040) >> 16;
-	u32 mthd = (addr & 0x07ff) << 2;
-	u32 subc = (addr & 0x3800) >> 11;
-	u32 data = nv_rd32(priv, 0x087044);
-	int chid;
-
-	engctx = nouveau_engctx_get(engine, inst);
-	chid   = pfifo->chid(pfifo, engctx);
-
-	if (stat & 0x00000040) {
-		nv_error(priv, "DISPATCH_ERROR [");
-		nouveau_enum_print(nv98_crypt_isr_error_name, ssta);
-		pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n",
-		       chid, (u64)inst << 12, nouveau_client_name(engctx),
-		       subc, mthd, data);
-		nv_wr32(priv, 0x087004, 0x00000040);
-		stat &= ~0x00000040;
-	}
-
-	if (stat) {
-		nv_error(priv, "unhandled intr 0x%08x\n", stat);
-		nv_wr32(priv, 0x087004, stat);
-	}
-
-	nouveau_engctx_put(engctx);
-}
-
-static int
-nv98_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv98_crypt_priv *priv;
-	int ret;
-
-	ret = nouveau_falcon_create(parent, engine, oclass, 0x087000, true,
-				    "PCRYPT", "crypt", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00004000;
-	nv_subdev(priv)->intr = nv98_crypt_intr;
-	nv_engine(priv)->cclass = &nv98_crypt_cclass;
-	nv_engine(priv)->sclass = nv98_crypt_sclass;
-	nv_falcon(priv)->code.data = nv98_pcrypt_code;
-	nv_falcon(priv)->code.size = sizeof(nv98_pcrypt_code);
-	nv_falcon(priv)->data.data = nv98_pcrypt_data;
-	nv_falcon(priv)->data.size = sizeof(nv98_pcrypt_data);
-	return 0;
-}
-
-struct nouveau_oclass
-nv98_crypt_oclass = {
-	.handle = NV_ENGINE(CRYPT, 0x98),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv98_crypt_ctor,
-		.dtor = _nouveau_falcon_dtor,
-		.init = _nouveau_falcon_init,
-		.fini = _nouveau_falcon_fini,
-		.rd32 = _nouveau_falcon_rd32,
-		.wr32 = _nouveau_falcon_wr32,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/acpi.c b/drivers/gpu/drm/nouveau/core/engine/device/acpi.c
deleted file mode 100644
index 4dbf0ba89e5c..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/device/acpi.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "acpi.h"
-
-#ifdef CONFIG_ACPI
-static int
-nvkm_acpi_ntfy(struct notifier_block *nb, unsigned long val, void *data)
-{
-	struct nouveau_device *device =
-		container_of(nb, typeof(*device), acpi.nb);
-	struct acpi_bus_event *info = data;
-
-	if (!strcmp(info->device_class, "ac_adapter"))
-		nvkm_event_send(&device->event, 1, 0, NULL, 0);
-
-	return NOTIFY_DONE;
-}
-#endif
-
-int
-nvkm_acpi_fini(struct nouveau_device *device, bool suspend)
-{
-#ifdef CONFIG_ACPI
-	unregister_acpi_notifier(&device->acpi.nb);
-#endif
-	return 0;
-}
-
-int
-nvkm_acpi_init(struct nouveau_device *device)
-{
-#ifdef CONFIG_ACPI
-	device->acpi.nb.notifier_call = nvkm_acpi_ntfy;
-	register_acpi_notifier(&device->acpi.nb);
-#endif
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/acpi.h b/drivers/gpu/drm/nouveau/core/engine/device/acpi.h
deleted file mode 100644
index cc49f4f568cd..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/device/acpi.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __NVKM_DEVICE_ACPI_H__
-#define __NVKM_DEVICE_ACPI_H__
-
-#include <engine/device.h>
-
-int nvkm_acpi_init(struct nouveau_device *);
-int nvkm_acpi_fini(struct nouveau_device *, bool);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c
deleted file mode 100644
index 137e0b0faeae..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/device/base.c
+++ /dev/null
@@ -1,715 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/object.h>
-#include <core/device.h>
-#include <core/client.h>
-#include <core/option.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/bios.h>
-#include <subdev/fb.h>
-#include <subdev/instmem.h>
-
-#include "priv.h"
-#include "acpi.h"
-
-static DEFINE_MUTEX(nv_devices_mutex);
-static LIST_HEAD(nv_devices);
-
-struct nouveau_device *
-nouveau_device_find(u64 name)
-{
-	struct nouveau_device *device, *match = NULL;
-	mutex_lock(&nv_devices_mutex);
-	list_for_each_entry(device, &nv_devices, head) {
-		if (device->handle == name) {
-			match = device;
-			break;
-		}
-	}
-	mutex_unlock(&nv_devices_mutex);
-	return match;
-}
-
-int
-nouveau_device_list(u64 *name, int size)
-{
-	struct nouveau_device *device;
-	int nr = 0;
-	mutex_lock(&nv_devices_mutex);
-	list_for_each_entry(device, &nv_devices, head) {
-		if (nr++ < size)
-			name[nr - 1] = device->handle;
-	}
-	mutex_unlock(&nv_devices_mutex);
-	return nr;
-}
-
-/******************************************************************************
- * nouveau_devobj (0x0080): class implementation
- *****************************************************************************/
-
-struct nouveau_devobj {
-	struct nouveau_parent base;
-	struct nouveau_object *subdev[NVDEV_SUBDEV_NR];
-};
-
-static int
-nouveau_devobj_info(struct nouveau_object *object, void *data, u32 size)
-{
-	struct nouveau_device *device = nv_device(object);
-	struct nouveau_fb *pfb = nouveau_fb(device);
-	struct nouveau_instmem *imem = nouveau_instmem(device);
-	union {
-		struct nv_device_info_v0 v0;
-	} *args = data;
-	int ret;
-
-	nv_ioctl(object, "device info size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "device info vers %d\n", args->v0.version);
-	} else
-		return ret;
-
-	switch (device->chipset) {
-	case 0x01a:
-	case 0x01f:
-	case 0x04c:
-	case 0x04e:
-	case 0x063:
-	case 0x067:
-	case 0x068:
-	case 0x0aa:
-	case 0x0ac:
-	case 0x0af:
-		args->v0.platform = NV_DEVICE_INFO_V0_IGP;
-		break;
-	default:
-		if (device->pdev) {
-			if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP))
-				args->v0.platform = NV_DEVICE_INFO_V0_AGP;
-			else
-			if (pci_is_pcie(device->pdev))
-				args->v0.platform = NV_DEVICE_INFO_V0_PCIE;
-			else
-				args->v0.platform = NV_DEVICE_INFO_V0_PCI;
-		} else {
-			args->v0.platform = NV_DEVICE_INFO_V0_SOC;
-		}
-		break;
-	}
-
-	switch (device->card_type) {
-	case NV_04: args->v0.family = NV_DEVICE_INFO_V0_TNT; break;
-	case NV_10:
-	case NV_11: args->v0.family = NV_DEVICE_INFO_V0_CELSIUS; break;
-	case NV_20: args->v0.family = NV_DEVICE_INFO_V0_KELVIN; break;
-	case NV_30: args->v0.family = NV_DEVICE_INFO_V0_RANKINE; break;
-	case NV_40: args->v0.family = NV_DEVICE_INFO_V0_CURIE; break;
-	case NV_50: args->v0.family = NV_DEVICE_INFO_V0_TESLA; break;
-	case NV_C0: args->v0.family = NV_DEVICE_INFO_V0_FERMI; break;
-	case NV_E0: args->v0.family = NV_DEVICE_INFO_V0_KEPLER; break;
-	case GM100: args->v0.family = NV_DEVICE_INFO_V0_MAXWELL; break;
-	default:
-		args->v0.family = 0;
-		break;
-	}
-
-	args->v0.chipset  = device->chipset;
-	args->v0.revision = device->chiprev;
-	if (pfb)  args->v0.ram_size = args->v0.ram_user = pfb->ram->size;
-	else      args->v0.ram_size = args->v0.ram_user = 0;
-	if (imem) args->v0.ram_user = args->v0.ram_user - imem->reserved;
-	return 0;
-}
-
-static int
-nouveau_devobj_mthd(struct nouveau_object *object, u32 mthd,
-		    void *data, u32 size)
-{
-	switch (mthd) {
-	case NV_DEVICE_V0_INFO:
-		return nouveau_devobj_info(object, data, size);
-	default:
-		break;
-	}
-	return -EINVAL;
-}
-
-static u8
-nouveau_devobj_rd08(struct nouveau_object *object, u64 addr)
-{
-	return nv_rd08(object->engine, addr);
-}
-
-static u16
-nouveau_devobj_rd16(struct nouveau_object *object, u64 addr)
-{
-	return nv_rd16(object->engine, addr);
-}
-
-static u32
-nouveau_devobj_rd32(struct nouveau_object *object, u64 addr)
-{
-	return nv_rd32(object->engine, addr);
-}
-
-static void
-nouveau_devobj_wr08(struct nouveau_object *object, u64 addr, u8 data)
-{
-	nv_wr08(object->engine, addr, data);
-}
-
-static void
-nouveau_devobj_wr16(struct nouveau_object *object, u64 addr, u16 data)
-{
-	nv_wr16(object->engine, addr, data);
-}
-
-static void
-nouveau_devobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
-{
-	nv_wr32(object->engine, addr, data);
-}
-
-static int
-nouveau_devobj_map(struct nouveau_object *object, u64 *addr, u32 *size)
-{
-	struct nouveau_device *device = nv_device(object);
-	*addr = nv_device_resource_start(device, 0);
-	*size = nv_device_resource_len(device, 0);
-	return 0;
-}
-
-static const u64 disable_map[] = {
-	[NVDEV_SUBDEV_VBIOS]	= NV_DEVICE_V0_DISABLE_VBIOS,
-	[NVDEV_SUBDEV_DEVINIT]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_SUBDEV_GPIO]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_SUBDEV_I2C]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_SUBDEV_CLOCK]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_SUBDEV_MXM]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_SUBDEV_MC]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_SUBDEV_BUS]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_SUBDEV_TIMER]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_SUBDEV_FB]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_SUBDEV_LTC]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_SUBDEV_IBUS]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_SUBDEV_INSTMEM]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_SUBDEV_VM]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_SUBDEV_BAR]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_SUBDEV_VOLT]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_SUBDEV_THERM]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_SUBDEV_PWR]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_SUBDEV_FUSE]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_ENGINE_DMAOBJ]	= NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_ENGINE_PERFMON]  = NV_DEVICE_V0_DISABLE_CORE,
-	[NVDEV_ENGINE_FIFO]	= NV_DEVICE_V0_DISABLE_FIFO,
-	[NVDEV_ENGINE_SW]	= NV_DEVICE_V0_DISABLE_FIFO,
-	[NVDEV_ENGINE_GR]	= NV_DEVICE_V0_DISABLE_GRAPH,
-	[NVDEV_ENGINE_MPEG]	= NV_DEVICE_V0_DISABLE_MPEG,
-	[NVDEV_ENGINE_ME]	= NV_DEVICE_V0_DISABLE_ME,
-	[NVDEV_ENGINE_VP]	= NV_DEVICE_V0_DISABLE_VP,
-	[NVDEV_ENGINE_CRYPT]	= NV_DEVICE_V0_DISABLE_CRYPT,
-	[NVDEV_ENGINE_BSP]	= NV_DEVICE_V0_DISABLE_BSP,
-	[NVDEV_ENGINE_PPP]	= NV_DEVICE_V0_DISABLE_PPP,
-	[NVDEV_ENGINE_COPY0]	= NV_DEVICE_V0_DISABLE_COPY0,
-	[NVDEV_ENGINE_COPY1]	= NV_DEVICE_V0_DISABLE_COPY1,
-	[NVDEV_ENGINE_COPY2]	= NV_DEVICE_V0_DISABLE_COPY1,
-	[NVDEV_ENGINE_VIC]	= NV_DEVICE_V0_DISABLE_VIC,
-	[NVDEV_ENGINE_VENC]	= NV_DEVICE_V0_DISABLE_VENC,
-	[NVDEV_ENGINE_DISP]	= NV_DEVICE_V0_DISABLE_DISP,
-	[NVDEV_SUBDEV_NR]	= 0,
-};
-
-static void
-nouveau_devobj_dtor(struct nouveau_object *object)
-{
-	struct nouveau_devobj *devobj = (void *)object;
-	int i;
-
-	for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--)
-		nouveau_object_ref(NULL, &devobj->subdev[i]);
-
-	nouveau_parent_destroy(&devobj->base);
-}
-
-static struct nouveau_oclass
-nouveau_devobj_oclass_super = {
-	.handle = NV_DEVICE,
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.dtor = nouveau_devobj_dtor,
-		.init = _nouveau_parent_init,
-		.fini = _nouveau_parent_fini,
-		.mthd = nouveau_devobj_mthd,
-		.map  = nouveau_devobj_map,
-		.rd08 = nouveau_devobj_rd08,
-		.rd16 = nouveau_devobj_rd16,
-		.rd32 = nouveau_devobj_rd32,
-		.wr08 = nouveau_devobj_wr08,
-		.wr16 = nouveau_devobj_wr16,
-		.wr32 = nouveau_devobj_wr32,
-	}
-};
-
-static int
-nouveau_devobj_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
-{
-	union {
-		struct nv_device_v0 v0;
-	} *args = data;
-	struct nouveau_client *client = nv_client(parent);
-	struct nouveau_device *device;
-	struct nouveau_devobj *devobj;
-	u32 boot0, strap;
-	u64 disable, mmio_base, mmio_size;
-	void __iomem *map;
-	int ret, i, c;
-
-	nv_ioctl(parent, "create device size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create device v%d device %016llx "
-				 "disable %016llx debug0 %016llx\n",
-			 args->v0.version, args->v0.device,
-			 args->v0.disable, args->v0.debug0);
-	} else
-		return ret;
-
-	/* give priviledged clients register access */
-	if (client->super)
-		oclass = &nouveau_devobj_oclass_super;
-
-	/* find the device subdev that matches what the client requested */
-	device = nv_device(client->device);
-	if (args->v0.device != ~0) {
-		device = nouveau_device_find(args->v0.device);
-		if (!device)
-			return -ENODEV;
-	}
-
-	ret = nouveau_parent_create(parent, nv_object(device), oclass, 0,
-				    nouveau_control_oclass,
-				    (1ULL << NVDEV_ENGINE_DMAOBJ) |
-				    (1ULL << NVDEV_ENGINE_FIFO) |
-				    (1ULL << NVDEV_ENGINE_DISP) |
-				    (1ULL << NVDEV_ENGINE_PERFMON), &devobj);
-	*pobject = nv_object(devobj);
-	if (ret)
-		return ret;
-
-	mmio_base = nv_device_resource_start(device, 0);
-	mmio_size = nv_device_resource_len(device, 0);
-
-	/* translate api disable mask into internal mapping */
-	disable = args->v0.debug0;
-	for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
-		if (args->v0.disable & disable_map[i])
-			disable |= (1ULL << i);
-	}
-
-	/* identify the chipset, and determine classes of subdev/engines */
-	if (!(args->v0.disable & NV_DEVICE_V0_DISABLE_IDENTIFY) &&
-	    !device->card_type) {
-		map = ioremap(mmio_base, 0x102000);
-		if (map == NULL)
-			return -ENOMEM;
-
-		/* switch mmio to cpu's native endianness */
-#ifndef __BIG_ENDIAN
-		if (ioread32_native(map + 0x000004) != 0x00000000)
-#else
-		if (ioread32_native(map + 0x000004) == 0x00000000)
-#endif
-			iowrite32_native(0x01000001, map + 0x000004);
-
-		/* read boot0 and strapping information */
-		boot0 = ioread32_native(map + 0x000000);
-		strap = ioread32_native(map + 0x101000);
-		iounmap(map);
-
-		/* determine chipset and derive architecture from it */
-		if ((boot0 & 0x1f000000) > 0) {
-			device->chipset = (boot0 & 0x1ff00000) >> 20;
-			device->chiprev = (boot0 & 0x000000ff);
-			switch (device->chipset & 0x1f0) {
-			case 0x010: {
-				if (0x461 & (1 << (device->chipset & 0xf)))
-					device->card_type = NV_10;
-				else
-					device->card_type = NV_11;
-				device->chiprev = 0x00;
-				break;
-			}
-			case 0x020: device->card_type = NV_20; break;
-			case 0x030: device->card_type = NV_30; break;
-			case 0x040:
-			case 0x060: device->card_type = NV_40; break;
-			case 0x050:
-			case 0x080:
-			case 0x090:
-			case 0x0a0: device->card_type = NV_50; break;
-			case 0x0c0:
-			case 0x0d0: device->card_type = NV_C0; break;
-			case 0x0e0:
-			case 0x0f0:
-			case 0x100: device->card_type = NV_E0; break;
-			case 0x110:
-			case 0x120: device->card_type = GM100; break;
-			default:
-				break;
-			}
-		} else
-		if ((boot0 & 0xff00fff0) == 0x20004000) {
-			if (boot0 & 0x00f00000)
-				device->chipset = 0x05;
-			else
-				device->chipset = 0x04;
-			device->card_type = NV_04;
-		}
-
-		switch (device->card_type) {
-		case NV_04: ret = nv04_identify(device); break;
-		case NV_10:
-		case NV_11: ret = nv10_identify(device); break;
-		case NV_20: ret = nv20_identify(device); break;
-		case NV_30: ret = nv30_identify(device); break;
-		case NV_40: ret = nv40_identify(device); break;
-		case NV_50: ret = nv50_identify(device); break;
-		case NV_C0: ret = nvc0_identify(device); break;
-		case NV_E0: ret = nve0_identify(device); break;
-		case GM100: ret = gm100_identify(device); break;
-		default:
-			ret = -EINVAL;
-			break;
-		}
-
-		if (ret) {
-			nv_error(device, "unknown chipset, 0x%08x\n", boot0);
-			return ret;
-		}
-
-		nv_info(device, "BOOT0  : 0x%08x\n", boot0);
-		nv_info(device, "Chipset: %s (NV%02X)\n",
-			device->cname, device->chipset);
-		nv_info(device, "Family : NV%02X\n", device->card_type);
-
-		/* determine frequency of timing crystal */
-		if ( device->card_type <= NV_10 || device->chipset < 0x17 ||
-		    (device->chipset >= 0x20 && device->chipset < 0x25))
-			strap &= 0x00000040;
-		else
-			strap &= 0x00400040;
-
-		switch (strap) {
-		case 0x00000000: device->crystal = 13500; break;
-		case 0x00000040: device->crystal = 14318; break;
-		case 0x00400000: device->crystal = 27000; break;
-		case 0x00400040: device->crystal = 25000; break;
-		}
-
-		nv_debug(device, "crystal freq: %dKHz\n", device->crystal);
-	} else
-	if ( (args->v0.disable & NV_DEVICE_V0_DISABLE_IDENTIFY)) {
-		device->cname = "NULL";
-		device->oclass[NVDEV_SUBDEV_VBIOS] = &nouveau_bios_oclass;
-	}
-
-	if (!(args->v0.disable & NV_DEVICE_V0_DISABLE_MMIO) &&
-	    !nv_subdev(device)->mmio) {
-		nv_subdev(device)->mmio  = ioremap(mmio_base, mmio_size);
-		if (!nv_subdev(device)->mmio) {
-			nv_error(device, "unable to map device registers\n");
-			return -ENOMEM;
-		}
-	}
-
-	/* ensure requested subsystems are available for use */
-	for (i = 1, c = 1; i < NVDEV_SUBDEV_NR; i++) {
-		if (!(oclass = device->oclass[i]) || (disable & (1ULL << i)))
-			continue;
-
-		if (device->subdev[i]) {
-			nouveau_object_ref(device->subdev[i],
-					  &devobj->subdev[i]);
-			continue;
-		}
-
-		ret = nouveau_object_ctor(nv_object(device), NULL,
-					  oclass, NULL, i,
-					  &devobj->subdev[i]);
-		if (ret == -ENODEV)
-			continue;
-		if (ret)
-			return ret;
-
-		device->subdev[i] = devobj->subdev[i];
-
-		/* note: can't init *any* subdevs until devinit has been run
-		 * due to not knowing exactly what the vbios init tables will
-		 * mess with.  devinit also can't be run until all of its
-		 * dependencies have been created.
-		 *
-		 * this code delays init of any subdev until all of devinit's
-		 * dependencies have been created, and then initialises each
-		 * subdev in turn as they're created.
-		 */
-		while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) {
-			struct nouveau_object *subdev = devobj->subdev[c++];
-			if (subdev && !nv_iclass(subdev, NV_ENGINE_CLASS)) {
-				ret = nouveau_object_inc(subdev);
-				if (ret)
-					return ret;
-				atomic_dec(&nv_object(device)->usecount);
-			} else
-			if (subdev) {
-				nouveau_subdev_reset(subdev);
-			}
-		}
-	}
-
-	return 0;
-}
-
-static struct nouveau_ofuncs
-nouveau_devobj_ofuncs = {
-	.ctor = nouveau_devobj_ctor,
-	.dtor = nouveau_devobj_dtor,
-	.init = _nouveau_parent_init,
-	.fini = _nouveau_parent_fini,
-	.mthd = nouveau_devobj_mthd,
-};
-
-/******************************************************************************
- * nouveau_device: engine functions
- *****************************************************************************/
-
-static struct nouveau_oclass
-nouveau_device_sclass[] = {
-	{ 0x0080, &nouveau_devobj_ofuncs },
-	{}
-};
-
-static int
-nouveau_device_event_ctor(struct nouveau_object *object, void *data, u32 size,
-			  struct nvkm_notify *notify)
-{
-	if (!WARN_ON(size != 0)) {
-		notify->size  = 0;
-		notify->types = 1;
-		notify->index = 0;
-		return 0;
-	}
-	return -EINVAL;
-}
-
-static const struct nvkm_event_func
-nouveau_device_event_func = {
-	.ctor = nouveau_device_event_ctor,
-};
-
-static int
-nouveau_device_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nouveau_device *device = (void *)object;
-	struct nouveau_object *subdev;
-	int ret, i;
-
-	for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) {
-		if ((subdev = device->subdev[i])) {
-			if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
-				ret = nouveau_object_dec(subdev, suspend);
-				if (ret && suspend)
-					goto fail;
-			}
-		}
-	}
-
-	ret = nvkm_acpi_fini(device, suspend);
-fail:
-	for (; ret && i < NVDEV_SUBDEV_NR; i++) {
-		if ((subdev = device->subdev[i])) {
-			if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
-				ret = nouveau_object_inc(subdev);
-				if (ret) {
-					/* XXX */
-				}
-			}
-		}
-	}
-
-	return ret;
-}
-
-static int
-nouveau_device_init(struct nouveau_object *object)
-{
-	struct nouveau_device *device = (void *)object;
-	struct nouveau_object *subdev;
-	int ret, i = 0;
-
-	ret = nvkm_acpi_init(device);
-	if (ret)
-		goto fail;
-
-	for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
-		if ((subdev = device->subdev[i])) {
-			if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
-				ret = nouveau_object_inc(subdev);
-				if (ret)
-					goto fail;
-			} else {
-				nouveau_subdev_reset(subdev);
-			}
-		}
-	}
-
-	ret = 0;
-fail:
-	for (--i; ret && i >= 0; i--) {
-		if ((subdev = device->subdev[i])) {
-			if (!nv_iclass(subdev, NV_ENGINE_CLASS))
-				nouveau_object_dec(subdev, false);
-		}
-	}
-
-	if (ret)
-		nvkm_acpi_fini(device, false);
-	return ret;
-}
-
-static void
-nouveau_device_dtor(struct nouveau_object *object)
-{
-	struct nouveau_device *device = (void *)object;
-
-	nvkm_event_fini(&device->event);
-
-	mutex_lock(&nv_devices_mutex);
-	list_del(&device->head);
-	mutex_unlock(&nv_devices_mutex);
-
-	if (nv_subdev(device)->mmio)
-		iounmap(nv_subdev(device)->mmio);
-
-	nouveau_engine_destroy(&device->base);
-}
-
-resource_size_t
-nv_device_resource_start(struct nouveau_device *device, unsigned int bar)
-{
-	if (nv_device_is_pci(device)) {
-		return pci_resource_start(device->pdev, bar);
-	} else {
-		struct resource *res;
-		res = platform_get_resource(device->platformdev,
-					    IORESOURCE_MEM, bar);
-		if (!res)
-			return 0;
-		return res->start;
-	}
-}
-
-resource_size_t
-nv_device_resource_len(struct nouveau_device *device, unsigned int bar)
-{
-	if (nv_device_is_pci(device)) {
-		return pci_resource_len(device->pdev, bar);
-	} else {
-		struct resource *res;
-		res = platform_get_resource(device->platformdev,
-					    IORESOURCE_MEM, bar);
-		if (!res)
-			return 0;
-		return resource_size(res);
-	}
-}
-
-int
-nv_device_get_irq(struct nouveau_device *device, bool stall)
-{
-	if (nv_device_is_pci(device)) {
-		return device->pdev->irq;
-	} else {
-		return platform_get_irq_byname(device->platformdev,
-					       stall ? "stall" : "nonstall");
-	}
-}
-
-static struct nouveau_oclass
-nouveau_device_oclass = {
-	.handle = NV_ENGINE(DEVICE, 0x00),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.dtor = nouveau_device_dtor,
-		.init = nouveau_device_init,
-		.fini = nouveau_device_fini,
-	},
-};
-
-int
-nouveau_device_create_(void *dev, enum nv_bus_type type, u64 name,
-		       const char *sname, const char *cfg, const char *dbg,
-		       int length, void **pobject)
-{
-	struct nouveau_device *device;
-	int ret = -EEXIST;
-
-	mutex_lock(&nv_devices_mutex);
-	list_for_each_entry(device, &nv_devices, head) {
-		if (device->handle == name)
-			goto done;
-	}
-
-	ret = nouveau_engine_create_(NULL, NULL, &nouveau_device_oclass, true,
-				     "DEVICE", "device", length, pobject);
-	device = *pobject;
-	if (ret)
-		goto done;
-
-	switch (type) {
-	case NOUVEAU_BUS_PCI:
-		device->pdev = dev;
-		break;
-	case NOUVEAU_BUS_PLATFORM:
-		device->platformdev = dev;
-		break;
-	}
-	device->handle = name;
-	device->cfgopt = cfg;
-	device->dbgopt = dbg;
-	device->name = sname;
-
-	nv_subdev(device)->debug = nouveau_dbgopt(device->dbgopt, "DEVICE");
-	nv_engine(device)->sclass = nouveau_device_sclass;
-	list_add(&device->head, &nv_devices);
-
-	ret = nvkm_event_init(&nouveau_device_event_func, 1, 1,
-			      &device->event);
-done:
-	mutex_unlock(&nv_devices_mutex);
-	return ret;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/ctrl.c b/drivers/gpu/drm/nouveau/core/engine/device/ctrl.c
deleted file mode 100644
index e34101a3490e..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/device/ctrl.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include <core/client.h>
-#include <core/object.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-#include <nvif/ioctl.h>
-
-#include <subdev/clock.h>
-
-#include "priv.h"
-
-static int
-nouveau_control_mthd_pstate_info(struct nouveau_object *object,
-				 void *data, u32 size)
-{
-	union {
-		struct nvif_control_pstate_info_v0 v0;
-	} *args = data;
-	struct nouveau_clock *clk = nouveau_clock(object);
-	int ret;
-
-	nv_ioctl(object, "control pstate info size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "control pstate info vers %d\n",
-			 args->v0.version);
-	} else
-		return ret;
-
-	if (clk) {
-		args->v0.count = clk->state_nr;
-		args->v0.ustate_ac = clk->ustate_ac;
-		args->v0.ustate_dc = clk->ustate_dc;
-		args->v0.pwrsrc = clk->pwrsrc;
-		args->v0.pstate = clk->pstate;
-	} else {
-		args->v0.count = 0;
-		args->v0.ustate_ac = NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE;
-		args->v0.ustate_dc = NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE;
-		args->v0.pwrsrc = -ENOSYS;
-		args->v0.pstate = NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN;
-	}
-
-	return 0;
-}
-
-static int
-nouveau_control_mthd_pstate_attr(struct nouveau_object *object,
-				 void *data, u32 size)
-{
-	union {
-		struct nvif_control_pstate_attr_v0 v0;
-	} *args = data;
-	struct nouveau_clock *clk = nouveau_clock(object);
-	struct nouveau_clocks *domain;
-	struct nouveau_pstate *pstate;
-	struct nouveau_cstate *cstate;
-	int i = 0, j = -1;
-	u32 lo, hi;
-	int ret;
-
-	nv_ioctl(object, "control pstate attr size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "control pstate attr vers %d state %d "
-				 "index %d\n",
-			 args->v0.version, args->v0.state, args->v0.index);
-		if (!clk)
-			return -ENODEV;
-		if (args->v0.state < NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT)
-			return -EINVAL;
-		if (args->v0.state >= clk->state_nr)
-			return -EINVAL;
-	} else
-		return ret;
-	domain = clk->domains;
-
-	while (domain->name != nv_clk_src_max) {
-		if (domain->mname && ++j == args->v0.index)
-			break;
-		domain++;
-	}
-
-	if (domain->name == nv_clk_src_max)
-		return -EINVAL;
-
-	if (args->v0.state != NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT) {
-		list_for_each_entry(pstate, &clk->states, head) {
-			if (i++ == args->v0.state)
-				break;
-		}
-
-		lo = pstate->base.domain[domain->name];
-		hi = lo;
-		list_for_each_entry(cstate, &pstate->list, head) {
-			lo = min(lo, cstate->domain[domain->name]);
-			hi = max(hi, cstate->domain[domain->name]);
-		}
-
-		args->v0.state = pstate->pstate;
-	} else {
-		lo = max(clk->read(clk, domain->name), 0);
-		hi = lo;
-	}
-
-	snprintf(args->v0.name, sizeof(args->v0.name), "%s", domain->mname);
-	snprintf(args->v0.unit, sizeof(args->v0.unit), "MHz");
-	args->v0.min = lo / domain->mdiv;
-	args->v0.max = hi / domain->mdiv;
-
-	args->v0.index = 0;
-	while ((++domain)->name != nv_clk_src_max) {
-		if (domain->mname) {
-			args->v0.index = ++j;
-			break;
-		}
-	}
-
-	return 0;
-}
-
-static int
-nouveau_control_mthd_pstate_user(struct nouveau_object *object,
-				 void *data, u32 size)
-{
-	union {
-		struct nvif_control_pstate_user_v0 v0;
-	} *args = data;
-	struct nouveau_clock *clk = nouveau_clock(object);
-	int ret;
-
-	nv_ioctl(object, "control pstate user size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "control pstate user vers %d ustate %d "
-				 "pwrsrc %d\n", args->v0.version,
-			 args->v0.ustate, args->v0.pwrsrc);
-		if (!clk)
-			return -ENODEV;
-	} else
-		return ret;
-
-	if (args->v0.pwrsrc >= 0) {
-		ret |= nouveau_clock_ustate(clk, args->v0.ustate, args->v0.pwrsrc);
-	} else {
-		ret |= nouveau_clock_ustate(clk, args->v0.ustate, 0);
-		ret |= nouveau_clock_ustate(clk, args->v0.ustate, 1);
-	}
-
-	return ret;
-}
-
-static int
-nouveau_control_mthd(struct nouveau_object *object, u32 mthd,
-		     void *data, u32 size)
-{
-	switch (mthd) {
-	case NVIF_CONTROL_PSTATE_INFO:
-		return nouveau_control_mthd_pstate_info(object, data, size);
-	case NVIF_CONTROL_PSTATE_ATTR:
-		return nouveau_control_mthd_pstate_attr(object, data, size);
-	case NVIF_CONTROL_PSTATE_USER:
-		return nouveau_control_mthd_pstate_user(object, data, size);
-	default:
-		break;
-	}
-	return -EINVAL;
-}
-
-static struct nouveau_ofuncs
-nouveau_control_ofuncs = {
-	.ctor = _nouveau_object_ctor,
-	.dtor = nouveau_object_destroy,
-	.init = nouveau_object_init,
-	.fini = nouveau_object_fini,
-	.mthd = nouveau_control_mthd,
-};
-
-struct nouveau_oclass
-nouveau_control_oclass[] = {
-	{ .handle = NVIF_IOCTL_NEW_V0_CONTROL,
-	  .ofuncs = &nouveau_control_ofuncs
-	},
-	{}
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/gm100.c b/drivers/gpu/drm/nouveau/core/engine/device/gm100.c
deleted file mode 100644
index 4e74a3376de8..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/device/gm100.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bus.h>
-#include <subdev/gpio.h>
-#include <subdev/i2c.h>
-#include <subdev/fuse.h>
-#include <subdev/clock.h>
-#include <subdev/therm.h>
-#include <subdev/mxm.h>
-#include <subdev/devinit.h>
-#include <subdev/mc.h>
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <subdev/ltc.h>
-#include <subdev/ibus.h>
-#include <subdev/instmem.h>
-#include <subdev/vm.h>
-#include <subdev/bar.h>
-#include <subdev/pwr.h>
-#include <subdev/volt.h>
-
-#include <engine/device.h>
-#include <engine/dmaobj.h>
-#include <engine/fifo.h>
-#include <engine/software.h>
-#include <engine/graph.h>
-#include <engine/disp.h>
-#include <engine/copy.h>
-#include <engine/bsp.h>
-#include <engine/vp.h>
-#include <engine/ppp.h>
-#include <engine/perfmon.h>
-
-int
-gm100_identify(struct nouveau_device *device)
-{
-	switch (device->chipset) {
-	case 0x117:
-		device->cname = "GM107";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nvd0_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gm107_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &gm107_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  gm107_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  gm107_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gm107_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nv108_pwr_oclass;
-
-#if 0
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-#endif
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gm107_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  gm107_disp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
-#if 0
-		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
-#endif
-		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
-#if 0
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
-#endif
-		break;
-	case 0x124:
-		device->cname = "GM204";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  gm204_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gm107_fuse_oclass;
-#if 0
-		/* looks to be some non-trivial changes */
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
-		/* priv ring says no to 0x10eb14 writes */
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &gm107_therm_oclass;
-#endif
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  gm204_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  gm107_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gm107_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nv108_pwr_oclass;
-#if 0
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-#endif
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
-#if 0
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gm107_graph_oclass;
-#endif
-		device->oclass[NVDEV_ENGINE_DISP   ] =  gm204_disp_oclass;
-#if 0
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &gm204_copy0_oclass;
-		device->oclass[NVDEV_ENGINE_COPY1  ] = &gm204_copy1_oclass;
-		device->oclass[NVDEV_ENGINE_COPY2  ] = &gm204_copy2_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
-#endif
-		break;
-	default:
-		nv_fatal(device, "unknown Maxwell chipset\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c b/drivers/gpu/drm/nouveau/core/engine/device/nv04.c
deleted file mode 100644
index 573b55f5c2f9..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bus.h>
-#include <subdev/i2c.h>
-#include <subdev/clock.h>
-#include <subdev/devinit.h>
-#include <subdev/mc.h>
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <subdev/instmem.h>
-#include <subdev/vm.h>
-
-#include <engine/device.h>
-#include <engine/dmaobj.h>
-#include <engine/fifo.h>
-#include <engine/software.h>
-#include <engine/graph.h>
-#include <engine/disp.h>
-
-int
-nv04_identify(struct nouveau_device *device)
-{
-	switch (device->chipset) {
-	case 0x04:
-		device->cname = "NV04";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv04_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv04_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv04_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv04_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv04_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	case 0x05:
-		device->cname = "NV05";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv05_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv04_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv04_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv04_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv04_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	default:
-		nv_fatal(device, "unknown RIVA chipset\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c b/drivers/gpu/drm/nouveau/core/engine/device/nv10.c
deleted file mode 100644
index 183a85a6204e..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bus.h>
-#include <subdev/gpio.h>
-#include <subdev/i2c.h>
-#include <subdev/clock.h>
-#include <subdev/devinit.h>
-#include <subdev/mc.h>
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <subdev/instmem.h>
-#include <subdev/vm.h>
-
-#include <engine/device.h>
-#include <engine/dmaobj.h>
-#include <engine/fifo.h>
-#include <engine/software.h>
-#include <engine/graph.h>
-#include <engine/disp.h>
-
-int
-nv10_identify(struct nouveau_device *device)
-{
-	switch (device->chipset) {
-	case 0x10:
-		device->cname = "NV10";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv10_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	case 0x15:
-		device->cname = "NV15";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv10_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	case 0x16:
-		device->cname = "NV16";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv10_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	case 0x1a:
-		device->cname = "nForce";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv1a_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	case 0x11:
-		device->cname = "NV11";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv10_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	case 0x17:
-		device->cname = "NV17";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv10_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	case 0x1f:
-		device->cname = "nForce2";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv1a_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	case 0x18:
-		device->cname = "NV18";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv10_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	default:
-		nv_fatal(device, "unknown Celsius chipset\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c b/drivers/gpu/drm/nouveau/core/engine/device/nv20.c
deleted file mode 100644
index aa564c68a920..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bus.h>
-#include <subdev/gpio.h>
-#include <subdev/i2c.h>
-#include <subdev/clock.h>
-#include <subdev/therm.h>
-#include <subdev/devinit.h>
-#include <subdev/mc.h>
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <subdev/instmem.h>
-#include <subdev/vm.h>
-
-#include <engine/device.h>
-#include <engine/dmaobj.h>
-#include <engine/fifo.h>
-#include <engine/software.h>
-#include <engine/graph.h>
-#include <engine/disp.h>
-
-int
-nv20_identify(struct nouveau_device *device)
-{
-	switch (device->chipset) {
-	case 0x20:
-		device->cname = "NV20";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv20_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv20_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	case 0x25:
-		device->cname = "NV25";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv25_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv25_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	case 0x28:
-		device->cname = "NV28";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv25_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv25_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	case 0x2a:
-		device->cname = "NV2A";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv25_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv2a_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	default:
-		nv_fatal(device, "unknown Kelvin chipset\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c b/drivers/gpu/drm/nouveau/core/engine/device/nv30.c
deleted file mode 100644
index 11bd31da82ab..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bus.h>
-#include <subdev/gpio.h>
-#include <subdev/i2c.h>
-#include <subdev/clock.h>
-#include <subdev/devinit.h>
-#include <subdev/mc.h>
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <subdev/instmem.h>
-#include <subdev/vm.h>
-
-#include <engine/device.h>
-#include <engine/dmaobj.h>
-#include <engine/fifo.h>
-#include <engine/software.h>
-#include <engine/graph.h>
-#include <engine/mpeg.h>
-#include <engine/disp.h>
-
-int
-nv30_identify(struct nouveau_device *device)
-{
-	switch (device->chipset) {
-	case 0x30:
-		device->cname = "NV30";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv30_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv30_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	case 0x35:
-		device->cname = "NV35";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv35_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv35_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	case 0x31:
-		device->cname = "NV31";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv30_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv30_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	case 0x36:
-		device->cname = "NV36";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv36_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv35_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	case 0x34:
-		device->cname = "NV34";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv10_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv34_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		break;
-	default:
-		nv_fatal(device, "unknown Rankine chipset\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c b/drivers/gpu/drm/nouveau/core/engine/device/nv40.c
deleted file mode 100644
index e96c223cb797..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c
+++ /dev/null
@@ -1,427 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bus.h>
-#include <subdev/vm.h>
-#include <subdev/gpio.h>
-#include <subdev/i2c.h>
-#include <subdev/clock.h>
-#include <subdev/therm.h>
-#include <subdev/devinit.h>
-#include <subdev/mc.h>
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <subdev/instmem.h>
-#include <subdev/vm.h>
-#include <subdev/volt.h>
-
-#include <engine/device.h>
-#include <engine/dmaobj.h>
-#include <engine/fifo.h>
-#include <engine/software.h>
-#include <engine/graph.h>
-#include <engine/mpeg.h>
-#include <engine/disp.h>
-#include <engine/perfmon.h>
-
-int
-nv40_identify(struct nouveau_device *device)
-{
-	switch (device->chipset) {
-	case 0x40:
-		device->cname = "NV40";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv40_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
-		break;
-	case 0x41:
-		device->cname = "NV41";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv41_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv41_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
-		break;
-	case 0x42:
-		device->cname = "NV42";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv41_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv41_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
-		break;
-	case 0x43:
-		device->cname = "NV43";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv41_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv41_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
-		break;
-	case 0x45:
-		device->cname = "NV45";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv40_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
-		break;
-	case 0x47:
-		device->cname = "G70";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv47_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv41_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
-		break;
-	case 0x49:
-		device->cname = "G71";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv49_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv41_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
-		break;
-	case 0x4b:
-		device->cname = "G73";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv49_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv41_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
-		break;
-	case 0x44:
-		device->cname = "NV44";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv44_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv44_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv44_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
-		break;
-	case 0x46:
-		device->cname = "G72";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv44_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv44_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
-		break;
-	case 0x4a:
-		device->cname = "NV44A";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv44_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv44_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv44_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
-		break;
-	case 0x4c:
-		device->cname = "C61";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv4c_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv44_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
-		break;
-	case 0x4e:
-		device->cname = "C51";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv4e_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv4c_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv4e_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv44_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
-		break;
-	case 0x63:
-		device->cname = "C73";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv4c_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv44_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
-		break;
-	case 0x67:
-		device->cname = "C67";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv4c_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv44_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
-		break;
-	case 0x68:
-		device->cname = "C68";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv4c_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv44_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
-		break;
-	default:
-		nv_fatal(device, "unknown Curie chipset\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
deleted file mode 100644
index 96f568d1321b..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
+++ /dev/null
@@ -1,475 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bus.h>
-#include <subdev/gpio.h>
-#include <subdev/i2c.h>
-#include <subdev/fuse.h>
-#include <subdev/clock.h>
-#include <subdev/therm.h>
-#include <subdev/mxm.h>
-#include <subdev/devinit.h>
-#include <subdev/mc.h>
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <subdev/instmem.h>
-#include <subdev/vm.h>
-#include <subdev/bar.h>
-#include <subdev/pwr.h>
-#include <subdev/volt.h>
-
-#include <engine/device.h>
-#include <engine/dmaobj.h>
-#include <engine/fifo.h>
-#include <engine/software.h>
-#include <engine/graph.h>
-#include <engine/mpeg.h>
-#include <engine/vp.h>
-#include <engine/crypt.h>
-#include <engine/bsp.h>
-#include <engine/ppp.h>
-#include <engine/copy.h>
-#include <engine/disp.h>
-#include <engine/perfmon.h>
-
-int
-nv50_identify(struct nouveau_device *device)
-{
-	switch (device->chipset) {
-	case 0x50:
-		device->cname = "G80";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv50_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv50_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv50_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv50_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv50_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv50_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv50_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv50_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv50_perfmon_oclass;
-		break;
-	case 0x84:
-		device->cname = "G84";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv50_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv84_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
-		device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv84_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
-		break;
-	case 0x86:
-		device->cname = "G86";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv50_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv84_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
-		device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv84_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
-		break;
-	case 0x92:
-		device->cname = "G92";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv50_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv84_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
-		device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv84_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
-		break;
-	case 0x94:
-		device->cname = "G94";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv84_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv94_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
-		device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv94_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
-		break;
-	case 0x96:
-		device->cname = "G96";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv84_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv94_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
-		device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv94_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
-		break;
-	case 0x98:
-		device->cname = "G98";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv98_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
-		device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv98_crypt_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv94_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
-		break;
-	case 0xa0:
-		device->cname = "G200";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv84_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
-		device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva0_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
-		break;
-	case 0xaa:
-		device->cname = "MCP77/MCP78";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nvaa_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv98_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nvaa_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
-		device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv98_crypt_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv94_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
-		break;
-	case 0xac:
-		device->cname = "MCP79/MCP7A";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nvaa_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv98_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nvaa_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
-		device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv98_crypt_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv94_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
-		break;
-	case 0xa3:
-		device->cname = "GT215";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nva3_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nva3_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nva3_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nva3_copy_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nva3_perfmon_oclass;
-		break;
-	case 0xa5:
-		device->cname = "GT216";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nva3_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nva3_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nva3_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nva3_copy_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nva3_perfmon_oclass;
-		break;
-	case 0xa8:
-		device->cname = "GT218";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nva3_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nva3_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nva3_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nva3_copy_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nva3_perfmon_oclass;
-		break;
-	case 0xaf:
-		device->cname = "MCP89";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvaf_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nvaf_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nva3_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nva3_copy_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] =  nva3_perfmon_oclass;
-		break;
-	default:
-		nv_fatal(device, "unknown Tesla chipset\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
deleted file mode 100644
index 72a40f95d048..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
+++ /dev/null
@@ -1,357 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bus.h>
-#include <subdev/gpio.h>
-#include <subdev/i2c.h>
-#include <subdev/fuse.h>
-#include <subdev/clock.h>
-#include <subdev/therm.h>
-#include <subdev/mxm.h>
-#include <subdev/devinit.h>
-#include <subdev/mc.h>
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <subdev/ltc.h>
-#include <subdev/ibus.h>
-#include <subdev/instmem.h>
-#include <subdev/vm.h>
-#include <subdev/bar.h>
-#include <subdev/pwr.h>
-#include <subdev/volt.h>
-
-#include <engine/device.h>
-#include <engine/dmaobj.h>
-#include <engine/fifo.h>
-#include <engine/software.h>
-#include <engine/graph.h>
-#include <engine/vp.h>
-#include <engine/bsp.h>
-#include <engine/ppp.h>
-#include <engine/copy.h>
-#include <engine/disp.h>
-#include <engine/perfmon.h>
-
-int
-nvc0_identify(struct nouveau_device *device)
-{
-	switch (device->chipset) {
-	case 0xc0:
-		device->cname = "GF100";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc0_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvc0_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc0_graph_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
-		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
-		break;
-	case 0xc4:
-		device->cname = "GF104";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc0_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvc0_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_graph_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
-		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
-		break;
-	case 0xc3:
-		device->cname = "GF106";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvc0_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_graph_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
-		break;
-	case 0xce:
-		device->cname = "GF114";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc0_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvc0_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_graph_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
-		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
-		break;
-	case 0xcf:
-		device->cname = "GF116";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvc0_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_graph_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
-		break;
-	case 0xc1:
-		device->cname = "GF108";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvc0_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc1_graph_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
-		break;
-	case 0xc8:
-		device->cname = "GF110";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc0_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvc0_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc8_graph_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
-		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
-		break;
-	case 0xd9:
-		device->cname = "GF119";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nvd0_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nvd0_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvd0_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvd9_graph_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nvd0_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
-		break;
-	case 0xd7:
-		device->cname = "GF117";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nvd0_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  gf117_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvd7_graph_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nvd0_disp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
-		break;
-	default:
-		nv_fatal(device, "unknown Fermi chipset\n");
-		return -EINVAL;
-	}
-
-	return 0;
-	}
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
deleted file mode 100644
index 732922690653..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bus.h>
-#include <subdev/gpio.h>
-#include <subdev/i2c.h>
-#include <subdev/fuse.h>
-#include <subdev/clock.h>
-#include <subdev/therm.h>
-#include <subdev/mxm.h>
-#include <subdev/devinit.h>
-#include <subdev/mc.h>
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <subdev/ltc.h>
-#include <subdev/ibus.h>
-#include <subdev/instmem.h>
-#include <subdev/vm.h>
-#include <subdev/bar.h>
-#include <subdev/pwr.h>
-#include <subdev/volt.h>
-
-#include <engine/device.h>
-#include <engine/dmaobj.h>
-#include <engine/fifo.h>
-#include <engine/software.h>
-#include <engine/graph.h>
-#include <engine/disp.h>
-#include <engine/copy.h>
-#include <engine/bsp.h>
-#include <engine/vp.h>
-#include <engine/ppp.h>
-#include <engine/perfmon.h>
-
-int
-nve0_identify(struct nouveau_device *device)
-{
-	switch (device->chipset) {
-	case 0xe4:
-		device->cname = "GK104";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nve0_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  gk104_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nve0_disp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
-		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
-		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
-		break;
-	case 0xe7:
-		device->cname = "GK107";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nve0_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvd0_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nve0_disp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
-		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
-		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
-		break;
-	case 0xe6:
-		device->cname = "GK106";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nve0_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  gk104_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nve0_disp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
-		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
-		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
-		break;
-	case 0xea:
-		device->cname = "GK20A";
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &gk20a_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  gk20a_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &gk20a_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &gk20a_bar_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk20a_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gk20a_graph_oclass;
-		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &gk20a_volt_oclass;
-		break;
-	case 0xf0:
-		device->cname = "GK110";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nve0_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvd0_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvf0_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
-		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
-		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass;
-		break;
-	case 0xf1:
-		device->cname = "GK110B";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nvd0_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvd0_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gk110b_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
-		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
-		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
-		device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass;
-		break;
-	case 0x106:
-		device->cname = "GK208B";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nve0_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nv108_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nv108_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
-		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
-		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
-		break;
-	case 0x108:
-		device->cname = "GK208";
-		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
-		device->oclass[NVDEV_SUBDEV_I2C    ] =  nve0_i2c_oclass;
-		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
-		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
-		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
-		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
-		device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
-		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
-		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
-		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
-		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
-		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
-		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
-		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-		device->oclass[NVDEV_SUBDEV_PWR    ] =  nv108_pwr_oclass;
-		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
-		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nv108_graph_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
-		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
-		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
-		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
-		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
-		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
-		break;
-	default:
-		nv_fatal(device, "unknown Kepler chipset\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/priv.h b/drivers/gpu/drm/nouveau/core/engine/device/priv.h
deleted file mode 100644
index 035fd5b9cfc3..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/device/priv.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __NVKM_DEVICE_PRIV_H__
-#define __NVKM_DEVICE_PRIV_H__
-
-#include <engine/device.h>
-
-extern struct nouveau_oclass nouveau_control_oclass[];
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/base.c b/drivers/gpu/drm/nouveau/core/engine/disp/base.c
deleted file mode 100644
index 64b84667f3a5..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/base.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/os.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-#include <nvif/event.h>
-
-#include "priv.h"
-#include "outp.h"
-#include "conn.h"
-
-int
-nouveau_disp_vblank_ctor(struct nouveau_object *object, void *data, u32 size,
-			 struct nvkm_notify *notify)
-{
-	struct nouveau_disp *disp =
-		container_of(notify->event, typeof(*disp), vblank);
-	union {
-		struct nvif_notify_head_req_v0 v0;
-	} *req = data;
-	int ret;
-
-	if (nvif_unpack(req->v0, 0, 0, false)) {
-		notify->size = sizeof(struct nvif_notify_head_rep_v0);
-		if (ret = -ENXIO, req->v0.head <= disp->vblank.index_nr) {
-			notify->types = 1;
-			notify->index = req->v0.head;
-			return 0;
-		}
-	}
-
-	return ret;
-}
-
-void
-nouveau_disp_vblank(struct nouveau_disp *disp, int head)
-{
-	struct nvif_notify_head_rep_v0 rep = {};
-	nvkm_event_send(&disp->vblank, 1, head, &rep, sizeof(rep));
-}
-
-static int
-nouveau_disp_hpd_ctor(struct nouveau_object *object, void *data, u32 size,
-		      struct nvkm_notify *notify)
-{
-	struct nouveau_disp *disp =
-		container_of(notify->event, typeof(*disp), hpd);
-	union {
-		struct nvif_notify_conn_req_v0 v0;
-	} *req = data;
-	struct nvkm_output *outp;
-	int ret;
-
-	if (nvif_unpack(req->v0, 0, 0, false)) {
-		notify->size = sizeof(struct nvif_notify_conn_rep_v0);
-		list_for_each_entry(outp, &disp->outp, head) {
-			if (ret = -ENXIO, outp->conn->index == req->v0.conn) {
-				if (ret = -ENODEV, outp->conn->hpd.event) {
-					notify->types = req->v0.mask;
-					notify->index = req->v0.conn;
-					ret = 0;
-				}
-				break;
-			}
-		}
-	}
-
-	return ret;
-}
-
-static const struct nvkm_event_func
-nouveau_disp_hpd_func = {
-	.ctor = nouveau_disp_hpd_ctor
-};
-
-int
-nouveau_disp_ntfy(struct nouveau_object *object, u32 type,
-		  struct nvkm_event **event)
-{
-	struct nouveau_disp *disp = (void *)object->engine;
-	switch (type) {
-	case NV04_DISP_NTFY_VBLANK:
-		*event = &disp->vblank;
-		return 0;
-	case NV04_DISP_NTFY_CONN:
-		*event = &disp->hpd;
-		return 0;
-	default:
-		break;
-	}
-	return -EINVAL;
-}
-
-int
-_nouveau_disp_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nouveau_disp *disp = (void *)object;
-	struct nvkm_output *outp;
-	int ret;
-
-	list_for_each_entry(outp, &disp->outp, head) {
-		ret = nv_ofuncs(outp)->fini(nv_object(outp), suspend);
-		if (ret && suspend)
-			goto fail_outp;
-	}
-
-	return nouveau_engine_fini(&disp->base, suspend);
-
-fail_outp:
-	list_for_each_entry_continue_reverse(outp, &disp->outp, head) {
-		nv_ofuncs(outp)->init(nv_object(outp));
-	}
-
-	return ret;
-}
-
-int
-_nouveau_disp_init(struct nouveau_object *object)
-{
-	struct nouveau_disp *disp = (void *)object;
-	struct nvkm_output *outp;
-	int ret;
-
-	ret = nouveau_engine_init(&disp->base);
-	if (ret)
-		return ret;
-
-	list_for_each_entry(outp, &disp->outp, head) {
-		ret = nv_ofuncs(outp)->init(nv_object(outp));
-		if (ret)
-			goto fail_outp;
-	}
-
-	return ret;
-
-fail_outp:
-	list_for_each_entry_continue_reverse(outp, &disp->outp, head) {
-		nv_ofuncs(outp)->fini(nv_object(outp), false);
-	}
-
-	return ret;
-}
-
-void
-_nouveau_disp_dtor(struct nouveau_object *object)
-{
-	struct nouveau_disp *disp = (void *)object;
-	struct nvkm_output *outp, *outt;
-
-	nvkm_event_fini(&disp->vblank);
-	nvkm_event_fini(&disp->hpd);
-
-	if (disp->outp.next) {
-		list_for_each_entry_safe(outp, outt, &disp->outp, head) {
-			nouveau_object_ref(NULL, (struct nouveau_object **)&outp);
-		}
-	}
-
-	nouveau_engine_destroy(&disp->base);
-}
-
-int
-nouveau_disp_create_(struct nouveau_object *parent,
-		     struct nouveau_object *engine,
-		     struct nouveau_oclass *oclass, int heads,
-		     const char *intname, const char *extname,
-		     int length, void **pobject)
-{
-	struct nouveau_disp_impl *impl = (void *)oclass;
-	struct nouveau_bios *bios = nouveau_bios(parent);
-	struct nouveau_disp *disp;
-	struct nouveau_oclass **sclass;
-	struct nouveau_object *object;
-	struct dcb_output dcbE;
-	u8  hpd = 0, ver, hdr;
-	u32 data;
-	int ret, i;
-
-	ret = nouveau_engine_create_(parent, engine, oclass, true,
-				     intname, extname, length, pobject);
-	disp = *pobject;
-	if (ret)
-		return ret;
-
-	INIT_LIST_HEAD(&disp->outp);
-
-	/* create output objects for each display path in the vbios */
-	i = -1;
-	while ((data = dcb_outp_parse(bios, ++i, &ver, &hdr, &dcbE))) {
-		if (dcbE.type == DCB_OUTPUT_UNUSED)
-			continue;
-		if (dcbE.type == DCB_OUTPUT_EOL)
-			break;
-		data = dcbE.location << 4 | dcbE.type;
-
-		oclass = nvkm_output_oclass;
-		sclass = impl->outp;
-		while (sclass && sclass[0]) {
-			if (sclass[0]->handle == data) {
-				oclass = sclass[0];
-				break;
-			}
-			sclass++;
-		}
-
-		nouveau_object_ctor(*pobject, *pobject, oclass,
-				    &dcbE, i, &object);
-		hpd = max(hpd, (u8)(dcbE.connector + 1));
-	}
-
-	ret = nvkm_event_init(&nouveau_disp_hpd_func, 3, hpd, &disp->hpd);
-	if (ret)
-		return ret;
-
-	ret = nvkm_event_init(impl->vblank, 1, heads, &disp->vblank);
-	if (ret)
-		return ret;
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/conn.c b/drivers/gpu/drm/nouveau/core/engine/disp/conn.c
deleted file mode 100644
index 1496b567dd4a..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/conn.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/os.h>
-#include <nvif/event.h>
-
-#include <subdev/gpio.h>
-
-#include "conn.h"
-#include "outp.h"
-
-static int
-nvkm_connector_hpd(struct nvkm_notify *notify)
-{
-	struct nvkm_connector *conn = container_of(notify, typeof(*conn), hpd);
-	struct nouveau_disp *disp = nouveau_disp(conn);
-	struct nouveau_gpio *gpio = nouveau_gpio(conn);
-	const struct nvkm_gpio_ntfy_rep *line = notify->data;
-	struct nvif_notify_conn_rep_v0 rep;
-	int index = conn->index;
-
-	DBG("HPD: %d\n", line->mask);
-
-	if (!gpio->get(gpio, 0, DCB_GPIO_UNUSED, conn->hpd.index))
-		rep.mask = NVIF_NOTIFY_CONN_V0_UNPLUG;
-	else
-		rep.mask = NVIF_NOTIFY_CONN_V0_PLUG;
-	rep.version = 0;
-
-	nvkm_event_send(&disp->hpd, rep.mask, index, &rep, sizeof(rep));
-	return NVKM_NOTIFY_KEEP;
-}
-
-int
-_nvkm_connector_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nvkm_connector *conn = (void *)object;
-	nvkm_notify_put(&conn->hpd);
-	return nouveau_object_fini(&conn->base, suspend);
-}
-
-int
-_nvkm_connector_init(struct nouveau_object *object)
-{
-	struct nvkm_connector *conn = (void *)object;
-	int ret = nouveau_object_init(&conn->base);
-	if (ret == 0)
-		nvkm_notify_get(&conn->hpd);
-	return ret;
-}
-
-void
-_nvkm_connector_dtor(struct nouveau_object *object)
-{
-	struct nvkm_connector *conn = (void *)object;
-	nvkm_notify_fini(&conn->hpd);
-	nouveau_object_destroy(&conn->base);
-}
-
-int
-nvkm_connector_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass,
-		       struct nvbios_connE *info, int index,
-		       int length, void **pobject)
-{
-	static const u8 hpd[] = { 0x07, 0x08, 0x51, 0x52, 0x5e, 0x5f, 0x60 };
-	struct nouveau_gpio *gpio = nouveau_gpio(parent);
-	struct nouveau_disp *disp = (void *)engine;
-	struct nvkm_connector *conn;
-	struct nvkm_output *outp;
-	struct dcb_gpio_func func;
-	int ret;
-
-	list_for_each_entry(outp, &disp->outp, head) {
-		if (outp->conn && outp->conn->index == index) {
-			atomic_inc(&nv_object(outp->conn)->refcount);
-			*pobject = outp->conn;
-			return 1;
-		}
-	}
-
-	ret = nouveau_object_create_(parent, engine, oclass, 0, length, pobject);
-	conn = *pobject;
-	if (ret)
-		return ret;
-
-	conn->info = *info;
-	conn->index = index;
-
-	DBG("type %02x loc %d hpd %02x dp %x di %x sr %x lcdid %x\n",
-	    info->type, info->location, info->hpd, info->dp,
-	    info->di, info->sr, info->lcdid);
-
-	if ((info->hpd = ffs(info->hpd))) {
-		if (--info->hpd >= ARRAY_SIZE(hpd)) {
-			ERR("hpd %02x unknown\n", info->hpd);
-			return 0;
-		}
-		info->hpd = hpd[info->hpd];
-
-		ret = gpio->find(gpio, 0, info->hpd, DCB_GPIO_UNUSED, &func);
-		if (ret) {
-			ERR("func %02x lookup failed, %d\n", info->hpd, ret);
-			return 0;
-		}
-
-		ret = nvkm_notify_init(NULL, &gpio->event, nvkm_connector_hpd,
-				       true, &(struct nvkm_gpio_ntfy_req) {
-					.mask = NVKM_GPIO_TOGGLED,
-					.line = func.line,
-				       },
-				       sizeof(struct nvkm_gpio_ntfy_req),
-				       sizeof(struct nvkm_gpio_ntfy_rep),
-				       &conn->hpd);
-		if (ret) {
-			ERR("func %02x failed, %d\n", info->hpd, ret);
-		} else {
-			DBG("func %02x (HPD)\n", info->hpd);
-		}
-	}
-
-	return 0;
-}
-
-int
-_nvkm_connector_ctor(struct nouveau_object *parent,
-		     struct nouveau_object *engine,
-		     struct nouveau_oclass *oclass, void *info, u32 index,
-		     struct nouveau_object **pobject)
-{
-	struct nvkm_connector *conn;
-	int ret;
-
-	ret = nvkm_connector_create(parent, engine, oclass, info, index, &conn);
-	*pobject = nv_object(conn);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-struct nouveau_oclass *
-nvkm_connector_oclass = &(struct nvkm_connector_impl) {
-	.base = {
-		.handle = 0,
-		.ofuncs = &(struct nouveau_ofuncs) {
-			.ctor = _nvkm_connector_ctor,
-			.dtor = _nvkm_connector_dtor,
-			.init = _nvkm_connector_init,
-			.fini = _nvkm_connector_fini,
-		},
-	},
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/conn.h b/drivers/gpu/drm/nouveau/core/engine/disp/conn.h
deleted file mode 100644
index 55e5f5c82c14..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/conn.h
+++ /dev/null
@@ -1,56 +0,0 @@
-#ifndef __NVKM_DISP_CONN_H__
-#define __NVKM_DISP_CONN_H__
-
-#include "priv.h"
-
-struct nvkm_connector {
-	struct nouveau_object base;
-	struct list_head head;
-
-	struct nvbios_connE info;
-	int index;
-
-	struct nvkm_notify hpd;
-};
-
-#define nvkm_connector_create(p,e,c,b,i,d)                                     \
-	nvkm_connector_create_((p), (e), (c), (b), (i), sizeof(**d), (void **)d)
-#define nvkm_connector_destroy(d) ({                                           \
-	struct nvkm_connector *disp = (d);                                     \
-	_nvkm_connector_dtor(nv_object(disp));                                 \
-})
-#define nvkm_connector_init(d) ({                                              \
-	struct nvkm_connector *disp = (d);                                     \
-	_nvkm_connector_init(nv_object(disp));                                 \
-})
-#define nvkm_connector_fini(d,s) ({                                            \
-	struct nvkm_connector *disp = (d);                                     \
-	_nvkm_connector_fini(nv_object(disp), (s));                            \
-})
-
-int nvkm_connector_create_(struct nouveau_object *, struct nouveau_object *,
-			   struct nouveau_oclass *, struct nvbios_connE *,
-			   int, int, void **);
-
-int  _nvkm_connector_ctor(struct nouveau_object *, struct nouveau_object *,
-			  struct nouveau_oclass *, void *, u32,
-			  struct nouveau_object **);
-void _nvkm_connector_dtor(struct nouveau_object *);
-int  _nvkm_connector_init(struct nouveau_object *);
-int  _nvkm_connector_fini(struct nouveau_object *, bool);
-
-struct nvkm_connector_impl {
-	struct nouveau_oclass base;
-};
-
-#ifndef MSG
-#define MSG(l,f,a...) do {                                                     \
-	struct nvkm_connector *_conn = (void *)conn;                           \
-	nv_##l(nv_object(conn)->engine, "%02x:%02x%02x: "f, _conn->index,      \
-	       _conn->info.location, _conn->info.type, ##a);                   \
-} while(0)
-#define DBG(f,a...) MSG(debug, f, ##a)
-#define ERR(f,a...) MSG(error, f, ##a)
-#endif
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
deleted file mode 100644
index b36addff06a9..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/timer.h>
-
-#include "nv50.h"
-
-int
-nv50_dac_power(NV50_DISP_MTHD_V1)
-{
-	const u32 doff = outp->or * 0x800;
-	union {
-		struct nv50_disp_dac_pwr_v0 v0;
-	} *args = data;
-	u32 stat;
-	int ret;
-
-	nv_ioctl(object, "disp dac pwr size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "disp dac pwr vers %d state %d data %d "
-				 "vsync %d hsync %d\n",
-			 args->v0.version, args->v0.state, args->v0.data,
-			 args->v0.vsync, args->v0.hsync);
-		stat  = 0x00000040 * !args->v0.state;
-		stat |= 0x00000010 * !args->v0.data;
-		stat |= 0x00000004 * !args->v0.vsync;
-		stat |= 0x00000001 * !args->v0.hsync;
-	} else
-		return ret;
-
-	nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
-	nv_mask(priv, 0x61a004 + doff, 0xc000007f, 0x80000000 | stat);
-	nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
-	return 0;
-}
-
-int
-nv50_dac_sense(NV50_DISP_MTHD_V1)
-{
-	union {
-		struct nv50_disp_dac_load_v0 v0;
-	} *args = data;
-	const u32 doff = outp->or * 0x800;
-	u32 loadval;
-	int ret;
-
-	nv_ioctl(object, "disp dac load size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "disp dac load vers %d data %08x\n",
-			 args->v0.version, args->v0.data);
-		if (args->v0.data & 0xfff00000)
-			return -EINVAL;
-		loadval = args->v0.data;
-	} else
-		return ret;
-
-	nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80150000);
-	nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
-
-	nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval);
-	mdelay(9);
-	udelay(500);
-	loadval = nv_mask(priv, 0x61a00c + doff, 0xffffffff, 0x00000000);
-
-	nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80550000);
-	nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
-
-	nv_debug(priv, "DAC%d sense: 0x%08x\n", outp->or, loadval);
-	if (!(loadval & 0x80000000))
-		return -ETIMEDOUT;
-
-	args->v0.load = (loadval & 0x38000000) >> 27;
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
deleted file mode 100644
index 16db08dfba6e..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
+++ /dev/null
@@ -1,402 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/dp.h>
-#include <subdev/bios/init.h>
-#include <subdev/i2c.h>
-
-#include "nv50.h"
-
-#include <nvif/class.h>
-
-#include "dport.h"
-#include "outpdp.h"
-
-/******************************************************************************
- * link training
- *****************************************************************************/
-struct dp_state {
-	struct nvkm_output_dp *outp;
-	int link_nr;
-	u32 link_bw;
-	u8  stat[6];
-	u8  conf[4];
-	bool pc2;
-	u8  pc2stat;
-	u8  pc2conf[2];
-};
-
-static int
-dp_set_link_config(struct dp_state *dp)
-{
-	struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp);
-	struct nvkm_output_dp *outp = dp->outp;
-	struct nouveau_disp *disp = nouveau_disp(outp);
-	struct nouveau_bios *bios = nouveau_bios(disp);
-	struct nvbios_init init = {
-		.subdev = nv_subdev(disp),
-		.bios = bios,
-		.offset = 0x0000,
-		.outp = &outp->base.info,
-		.crtc = -1,
-		.execute = 1,
-	};
-	u32 lnkcmp;
-	u8 sink[2];
-	int ret;
-
-	DBG("%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
-
-	/* set desired link configuration on the source */
-	if ((lnkcmp = dp->outp->info.lnkcmp)) {
-		if (outp->version < 0x30) {
-			while ((dp->link_bw / 10) < nv_ro16(bios, lnkcmp))
-				lnkcmp += 4;
-			init.offset = nv_ro16(bios, lnkcmp + 2);
-		} else {
-			while ((dp->link_bw / 27000) < nv_ro08(bios, lnkcmp))
-				lnkcmp += 3;
-			init.offset = nv_ro16(bios, lnkcmp + 1);
-		}
-
-		nvbios_exec(&init);
-	}
-
-	ret = impl->lnk_ctl(outp, dp->link_nr, dp->link_bw / 27000,
-			    outp->dpcd[DPCD_RC02] &
-				       DPCD_RC02_ENHANCED_FRAME_CAP);
-	if (ret) {
-		if (ret < 0)
-			ERR("lnk_ctl failed with %d\n", ret);
-		return ret;
-	}
-
-	impl->lnk_pwr(outp, dp->link_nr);
-
-	/* set desired link configuration on the sink */
-	sink[0] = dp->link_bw / 27000;
-	sink[1] = dp->link_nr;
-	if (outp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP)
-		sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN;
-
-	return nv_wraux(outp->base.edid, DPCD_LC00_LINK_BW_SET, sink, 2);
-}
-
-static void
-dp_set_training_pattern(struct dp_state *dp, u8 pattern)
-{
-	struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp);
-	struct nvkm_output_dp *outp = dp->outp;
-	u8 sink_tp;
-
-	DBG("training pattern %d\n", pattern);
-	impl->pattern(outp, pattern);
-
-	nv_rdaux(outp->base.edid, DPCD_LC02, &sink_tp, 1);
-	sink_tp &= ~DPCD_LC02_TRAINING_PATTERN_SET;
-	sink_tp |= pattern;
-	nv_wraux(outp->base.edid, DPCD_LC02, &sink_tp, 1);
-}
-
-static int
-dp_link_train_commit(struct dp_state *dp, bool pc)
-{
-	struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp);
-	struct nvkm_output_dp *outp = dp->outp;
-	int ret, i;
-
-	for (i = 0; i < dp->link_nr; i++) {
-		u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
-		u8 lpc2 = (dp->pc2stat >> (i * 2)) & 0x3;
-		u8 lpre = (lane & 0x0c) >> 2;
-		u8 lvsw = (lane & 0x03) >> 0;
-		u8 hivs = 3 - lpre;
-		u8 hipe = 3;
-		u8 hipc = 3;
-
-		if (lpc2 >= hipc)
-			lpc2 = hipc | DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED;
-		if (lpre >= hipe) {
-			lpre = hipe | DPCD_LC03_MAX_SWING_REACHED; /* yes. */
-			lvsw = hivs = 3 - (lpre & 3);
-		} else
-		if (lvsw >= hivs) {
-			lvsw = hivs | DPCD_LC03_MAX_SWING_REACHED;
-		}
-
-		dp->conf[i] = (lpre << 3) | lvsw;
-		dp->pc2conf[i >> 1] |= lpc2 << ((i & 1) * 4);
-
-		DBG("config lane %d %02x %02x\n", i, dp->conf[i], lpc2);
-		impl->drv_ctl(outp, i, lvsw & 3, lpre & 3, lpc2 & 3);
-	}
-
-	ret = nv_wraux(outp->base.edid, DPCD_LC03(0), dp->conf, 4);
-	if (ret)
-		return ret;
-
-	if (pc) {
-		ret = nv_wraux(outp->base.edid, DPCD_LC0F, dp->pc2conf, 2);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
-static int
-dp_link_train_update(struct dp_state *dp, bool pc, u32 delay)
-{
-	struct nvkm_output_dp *outp = dp->outp;
-	int ret;
-
-	if (outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL])
-		mdelay(outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4);
-	else
-		udelay(delay);
-
-	ret = nv_rdaux(outp->base.edid, DPCD_LS02, dp->stat, 6);
-	if (ret)
-		return ret;
-
-	if (pc) {
-		ret = nv_rdaux(outp->base.edid, DPCD_LS0C, &dp->pc2stat, 1);
-		if (ret)
-			dp->pc2stat = 0x00;
-		DBG("status %6ph pc2 %02x\n", dp->stat, dp->pc2stat);
-	} else {
-		DBG("status %6ph\n", dp->stat);
-	}
-
-	return 0;
-}
-
-static int
-dp_link_train_cr(struct dp_state *dp)
-{
-	bool cr_done = false, abort = false;
-	int voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
-	int tries = 0, i;
-
-	dp_set_training_pattern(dp, 1);
-
-	do {
-		if (dp_link_train_commit(dp, false) ||
-		    dp_link_train_update(dp, false, 100))
-			break;
-
-		cr_done = true;
-		for (i = 0; i < dp->link_nr; i++) {
-			u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
-			if (!(lane & DPCD_LS02_LANE0_CR_DONE)) {
-				cr_done = false;
-				if (dp->conf[i] & DPCD_LC03_MAX_SWING_REACHED)
-					abort = true;
-				break;
-			}
-		}
-
-		if ((dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) {
-			voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
-			tries = 0;
-		}
-	} while (!cr_done && !abort && ++tries < 5);
-
-	return cr_done ? 0 : -1;
-}
-
-static int
-dp_link_train_eq(struct dp_state *dp)
-{
-	struct nvkm_output_dp *outp = dp->outp;
-	bool eq_done = false, cr_done = true;
-	int tries = 0, i;
-
-	if (outp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED)
-		dp_set_training_pattern(dp, 3);
-	else
-		dp_set_training_pattern(dp, 2);
-
-	do {
-		if ((tries &&
-		    dp_link_train_commit(dp, dp->pc2)) ||
-		    dp_link_train_update(dp, dp->pc2, 400))
-			break;
-
-		eq_done = !!(dp->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE);
-		for (i = 0; i < dp->link_nr && eq_done; i++) {
-			u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
-			if (!(lane & DPCD_LS02_LANE0_CR_DONE))
-				cr_done = false;
-			if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) ||
-			    !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED))
-				eq_done = false;
-		}
-	} while (!eq_done && cr_done && ++tries <= 5);
-
-	return eq_done ? 0 : -1;
-}
-
-static void
-dp_link_train_init(struct dp_state *dp, bool spread)
-{
-	struct nvkm_output_dp *outp = dp->outp;
-	struct nouveau_disp *disp = nouveau_disp(outp);
-	struct nouveau_bios *bios = nouveau_bios(disp);
-	struct nvbios_init init = {
-		.subdev = nv_subdev(disp),
-		.bios = bios,
-		.outp = &outp->base.info,
-		.crtc = -1,
-		.execute = 1,
-	};
-
-	/* set desired spread */
-	if (spread)
-		init.offset = outp->info.script[2];
-	else
-		init.offset = outp->info.script[3];
-	nvbios_exec(&init);
-
-	/* pre-train script */
-	init.offset = outp->info.script[0];
-	nvbios_exec(&init);
-}
-
-static void
-dp_link_train_fini(struct dp_state *dp)
-{
-	struct nvkm_output_dp *outp = dp->outp;
-	struct nouveau_disp *disp = nouveau_disp(outp);
-	struct nouveau_bios *bios = nouveau_bios(disp);
-	struct nvbios_init init = {
-		.subdev = nv_subdev(disp),
-		.bios = bios,
-		.outp = &outp->base.info,
-		.crtc = -1,
-		.execute = 1,
-	};
-
-	/* post-train script */
-	init.offset = outp->info.script[1],
-	nvbios_exec(&init);
-}
-
-static const struct dp_rates {
-	u32 rate;
-	u8  bw;
-	u8  nr;
-} nouveau_dp_rates[] = {
-	{ 2160000, 0x14, 4 },
-	{ 1080000, 0x0a, 4 },
-	{ 1080000, 0x14, 2 },
-	{  648000, 0x06, 4 },
-	{  540000, 0x0a, 2 },
-	{  540000, 0x14, 1 },
-	{  324000, 0x06, 2 },
-	{  270000, 0x0a, 1 },
-	{  162000, 0x06, 1 },
-	{}
-};
-
-void
-nouveau_dp_train(struct work_struct *w)
-{
-	struct nvkm_output_dp *outp = container_of(w, typeof(*outp), lt.work);
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	const struct dp_rates *cfg = nouveau_dp_rates;
-	struct dp_state _dp = {
-		.outp = outp,
-	}, *dp = &_dp;
-	u32 datarate = 0;
-	int ret;
-
-	if (!outp->base.info.location && priv->sor.magic)
-		priv->sor.magic(&outp->base);
-
-	/* bring capabilities within encoder limits */
-	if (nv_mclass(priv) < GF110_DISP)
-		outp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED;
-	if ((outp->dpcd[2] & 0x1f) > outp->base.info.dpconf.link_nr) {
-		outp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT;
-		outp->dpcd[2] |= outp->base.info.dpconf.link_nr;
-	}
-	if (outp->dpcd[1] > outp->base.info.dpconf.link_bw)
-		outp->dpcd[1] = outp->base.info.dpconf.link_bw;
-	dp->pc2 = outp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED;
-
-	/* restrict link config to the lowest required rate, if requested */
-	if (datarate) {
-		datarate = (datarate / 8) * 10; /* 8B/10B coding overhead */
-		while (cfg[1].rate >= datarate)
-			cfg++;
-	}
-	cfg--;
-
-	/* disable link interrupt handling during link training */
-	nvkm_notify_put(&outp->irq);
-
-	/* enable down-spreading and execute pre-train script from vbios */
-	dp_link_train_init(dp, outp->dpcd[3] & 0x01);
-
-	while (ret = -EIO, (++cfg)->rate) {
-		/* select next configuration supported by encoder and sink */
-		while (cfg->nr > (outp->dpcd[2] & DPCD_RC02_MAX_LANE_COUNT) ||
-		       cfg->bw > (outp->dpcd[DPCD_RC01_MAX_LINK_RATE]))
-			cfg++;
-		dp->link_bw = cfg->bw * 27000;
-		dp->link_nr = cfg->nr;
-
-		/* program selected link configuration */
-		ret = dp_set_link_config(dp);
-		if (ret == 0) {
-			/* attempt to train the link at this configuration */
-			memset(dp->stat, 0x00, sizeof(dp->stat));
-			if (!dp_link_train_cr(dp) &&
-			    !dp_link_train_eq(dp))
-				break;
-		} else
-		if (ret) {
-			/* dp_set_link_config() handled training, or
-			 * we failed to communicate with the sink.
-			 */
-			break;
-		}
-	}
-
-	/* finish link training and execute post-train script from vbios */
-	dp_set_training_pattern(dp, 0);
-	if (ret < 0)
-		ERR("link training failed\n");
-
-	dp_link_train_fini(dp);
-
-	/* signal completion and enable link interrupt handling */
-	DBG("training complete\n");
-	atomic_set(&outp->lt.done, 1);
-	wake_up(&outp->lt.wait);
-	nvkm_notify_get(&outp->irq);
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.h b/drivers/gpu/drm/nouveau/core/engine/disp/dport.h
deleted file mode 100644
index 5628d2d5ec71..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/dport.h
+++ /dev/null
@@ -1,75 +0,0 @@
-#ifndef __NVKM_DISP_DPORT_H__
-#define __NVKM_DISP_DPORT_H__
-
-/* DPCD Receiver Capabilities */
-#define DPCD_RC00_DPCD_REV                                              0x00000
-#define DPCD_RC01_MAX_LINK_RATE                                         0x00001
-#define DPCD_RC02                                                       0x00002
-#define DPCD_RC02_ENHANCED_FRAME_CAP                                       0x80
-#define DPCD_RC02_TPS3_SUPPORTED                                           0x40
-#define DPCD_RC02_MAX_LANE_COUNT                                           0x1f
-#define DPCD_RC03                                                       0x00003
-#define DPCD_RC03_MAX_DOWNSPREAD                                           0x01
-#define DPCD_RC0E_AUX_RD_INTERVAL                                       0x0000e
-
-/* DPCD Link Configuration */
-#define DPCD_LC00_LINK_BW_SET                                           0x00100
-#define DPCD_LC01                                                       0x00101
-#define DPCD_LC01_ENHANCED_FRAME_EN                                        0x80
-#define DPCD_LC01_LANE_COUNT_SET                                           0x1f
-#define DPCD_LC02                                                       0x00102
-#define DPCD_LC02_TRAINING_PATTERN_SET                                     0x03
-#define DPCD_LC03(l)                                            ((l) +  0x00103)
-#define DPCD_LC03_MAX_PRE_EMPHASIS_REACHED                                 0x20
-#define DPCD_LC03_PRE_EMPHASIS_SET                                         0x18
-#define DPCD_LC03_MAX_SWING_REACHED                                        0x04
-#define DPCD_LC03_VOLTAGE_SWING_SET                                        0x03
-#define DPCD_LC0F                                                       0x0010f
-#define DPCD_LC0F_LANE1_MAX_POST_CURSOR2_REACHED                           0x40
-#define DPCD_LC0F_LANE1_POST_CURSOR2_SET                                   0x30
-#define DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED                           0x04
-#define DPCD_LC0F_LANE0_POST_CURSOR2_SET                                   0x03
-#define DPCD_LC10                                                       0x00110
-#define DPCD_LC10_LANE3_MAX_POST_CURSOR2_REACHED                           0x40
-#define DPCD_LC10_LANE3_POST_CURSOR2_SET                                   0x30
-#define DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED                           0x04
-#define DPCD_LC10_LANE2_POST_CURSOR2_SET                                   0x03
-
-/* DPCD Link/Sink Status */
-#define DPCD_LS02                                                       0x00202
-#define DPCD_LS02_LANE1_SYMBOL_LOCKED                                      0x40
-#define DPCD_LS02_LANE1_CHANNEL_EQ_DONE                                    0x20
-#define DPCD_LS02_LANE1_CR_DONE                                            0x10
-#define DPCD_LS02_LANE0_SYMBOL_LOCKED                                      0x04
-#define DPCD_LS02_LANE0_CHANNEL_EQ_DONE                                    0x02
-#define DPCD_LS02_LANE0_CR_DONE                                            0x01
-#define DPCD_LS03                                                       0x00203
-#define DPCD_LS03_LANE3_SYMBOL_LOCKED                                      0x40
-#define DPCD_LS03_LANE3_CHANNEL_EQ_DONE                                    0x20
-#define DPCD_LS03_LANE3_CR_DONE                                            0x10
-#define DPCD_LS03_LANE2_SYMBOL_LOCKED                                      0x04
-#define DPCD_LS03_LANE2_CHANNEL_EQ_DONE                                    0x02
-#define DPCD_LS03_LANE2_CR_DONE                                            0x01
-#define DPCD_LS04                                                       0x00204
-#define DPCD_LS04_LINK_STATUS_UPDATED                                      0x80
-#define DPCD_LS04_DOWNSTREAM_PORT_STATUS_CHANGED                           0x40
-#define DPCD_LS04_INTERLANE_ALIGN_DONE                                     0x01
-#define DPCD_LS06                                                       0x00206
-#define DPCD_LS06_LANE1_PRE_EMPHASIS                                       0xc0
-#define DPCD_LS06_LANE1_VOLTAGE_SWING                                      0x30
-#define DPCD_LS06_LANE0_PRE_EMPHASIS                                       0x0c
-#define DPCD_LS06_LANE0_VOLTAGE_SWING                                      0x03
-#define DPCD_LS07                                                       0x00207
-#define DPCD_LS07_LANE3_PRE_EMPHASIS                                       0xc0
-#define DPCD_LS07_LANE3_VOLTAGE_SWING                                      0x30
-#define DPCD_LS07_LANE2_PRE_EMPHASIS                                       0x0c
-#define DPCD_LS07_LANE2_VOLTAGE_SWING                                      0x03
-#define DPCD_LS0C                                                       0x0020c
-#define DPCD_LS0C_LANE3_POST_CURSOR2                                       0xc0
-#define DPCD_LS0C_LANE2_POST_CURSOR2                                       0x30
-#define DPCD_LS0C_LANE1_POST_CURSOR2                                       0x0c
-#define DPCD_LS0C_LANE0_POST_CURSOR2                                       0x03
-
-void nouveau_dp_train(struct work_struct *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
deleted file mode 100644
index e2ad0543fb31..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <engine/software.h>
-#include <engine/disp.h>
-
-#include <nvif/class.h>
-
-#include "nv50.h"
-
-/*******************************************************************************
- * Base display object
- ******************************************************************************/
-
-static struct nouveau_oclass
-gm107_disp_sclass[] = {
-	{ GM107_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
-	{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
-	{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
-	{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
-	{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
-	{}
-};
-
-static struct nouveau_oclass
-gm107_disp_main_oclass[] = {
-	{ GM107_DISP, &nvd0_disp_main_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * Display engine implementation
- ******************************************************************************/
-
-static int
-gm107_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv50_disp_priv *priv;
-	int heads = nv_rd32(parent, 0x022448);
-	int ret;
-
-	ret = nouveau_disp_create(parent, engine, oclass, heads,
-				  "PDISP", "display", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
-	if (ret)
-		return ret;
-
-	nv_engine(priv)->sclass = gm107_disp_main_oclass;
-	nv_engine(priv)->cclass = &nv50_disp_cclass;
-	nv_subdev(priv)->intr = nvd0_disp_intr;
-	INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
-	priv->sclass = gm107_disp_sclass;
-	priv->head.nr = heads;
-	priv->dac.nr = 3;
-	priv->sor.nr = 4;
-	priv->dac.power = nv50_dac_power;
-	priv->dac.sense = nv50_dac_sense;
-	priv->sor.power = nv50_sor_power;
-	priv->sor.hda_eld = nvd0_hda_eld;
-	priv->sor.hdmi = nve0_hdmi_ctrl;
-	return 0;
-}
-
-struct nouveau_oclass *
-gm107_disp_oclass = &(struct nv50_disp_impl) {
-	.base.base.handle = NV_ENGINE(DISP, 0x07),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = gm107_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
-	},
-	.base.vblank = &nvd0_disp_vblank_func,
-	.base.outp =  nvd0_disp_outp_sclass,
-	.mthd.core = &nve0_disp_core_mthd_chan,
-	.mthd.base = &nvd0_disp_base_mthd_chan,
-	.mthd.ovly = &nve0_disp_ovly_mthd_chan,
-	.mthd.prev = -0x020000,
-	.head.scanoutpos = nvd0_disp_main_scanoutpos,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/gm204.c b/drivers/gpu/drm/nouveau/core/engine/disp/gm204.c
deleted file mode 100644
index 672ded79b2a9..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/gm204.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <engine/software.h>
-#include <engine/disp.h>
-
-#include <nvif/class.h>
-
-#include "nv50.h"
-
-/*******************************************************************************
- * Base display object
- ******************************************************************************/
-
-static struct nouveau_oclass
-gm204_disp_sclass[] = {
-	{ GM204_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
-	{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
-	{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
-	{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
-	{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
-	{}
-};
-
-static struct nouveau_oclass
-gm204_disp_main_oclass[] = {
-	{ GM204_DISP, &nvd0_disp_main_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * Display engine implementation
- ******************************************************************************/
-
-static int
-gm204_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv50_disp_priv *priv;
-	int heads = nv_rd32(parent, 0x022448);
-	int ret;
-
-	ret = nouveau_disp_create(parent, engine, oclass, heads,
-				  "PDISP", "display", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
-	if (ret)
-		return ret;
-
-	nv_engine(priv)->sclass = gm204_disp_main_oclass;
-	nv_engine(priv)->cclass = &nv50_disp_cclass;
-	nv_subdev(priv)->intr = nvd0_disp_intr;
-	INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
-	priv->sclass = gm204_disp_sclass;
-	priv->head.nr = heads;
-	priv->dac.nr = 3;
-	priv->sor.nr = 4;
-	priv->dac.power = nv50_dac_power;
-	priv->dac.sense = nv50_dac_sense;
-	priv->sor.power = nv50_sor_power;
-	priv->sor.hda_eld = nvd0_hda_eld;
-	priv->sor.hdmi = nvd0_hdmi_ctrl;
-	priv->sor.magic = gm204_sor_magic;
-	return 0;
-}
-
-struct nouveau_oclass *
-gm204_disp_outp_sclass[] = {
-	&gm204_sor_dp_impl.base.base,
-	NULL
-};
-
-struct nouveau_oclass *
-gm204_disp_oclass = &(struct nv50_disp_impl) {
-	.base.base.handle = NV_ENGINE(DISP, 0x07),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = gm204_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
-	},
-	.base.vblank = &nvd0_disp_vblank_func,
-	.base.outp =  gm204_disp_outp_sclass,
-	.mthd.core = &nve0_disp_core_mthd_chan,
-	.mthd.base = &nvd0_disp_base_mthd_chan,
-	.mthd.ovly = &nve0_disp_ovly_mthd_chan,
-	.mthd.prev = -0x020000,
-	.head.scanoutpos = nvd0_disp_main_scanoutpos,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c
deleted file mode 100644
index fe9ef5894dd4..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/timer.h>
-
-#include "nv50.h"
-
-int
-nva3_hda_eld(NV50_DISP_MTHD_V1)
-{
-	union {
-		struct nv50_disp_sor_hda_eld_v0 v0;
-	} *args = data;
-	const u32 soff = outp->or * 0x800;
-	int ret, i;
-
-	nv_ioctl(object, "disp sor hda eld size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, true)) {
-		nv_ioctl(object, "disp sor hda eld vers %d\n", args->v0.version);
-		if (size > 0x60)
-			return -E2BIG;
-	} else
-		return ret;
-
-	if (size && args->v0.data[0]) {
-		if (outp->info.type == DCB_OUTPUT_DP) {
-			nv_mask(priv, 0x61c1e0 + soff, 0x8000000d, 0x80000001);
-			nv_wait(priv, 0x61c1e0 + soff, 0x80000000, 0x00000000);
-		}
-		for (i = 0; i < size; i++)
-			nv_wr32(priv, 0x61c440 + soff, (i << 8) | args->v0.data[0]);
-		for (; i < 0x60; i++)
-			nv_wr32(priv, 0x61c440 + soff, (i << 8));
-		nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000003);
-	} else {
-		if (outp->info.type == DCB_OUTPUT_DP) {
-			nv_mask(priv, 0x61c1e0 + soff, 0x80000001, 0x80000000);
-			nv_wait(priv, 0x61c1e0 + soff, 0x80000000, 0x00000000);
-		}
-		nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000000 | !!size);
-	}
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c
deleted file mode 100644
index 1d4e8432d857..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/timer.h>
-
-#include "nv50.h"
-
-int
-nvd0_hda_eld(NV50_DISP_MTHD_V1)
-{
-	union {
-		struct nv50_disp_sor_hda_eld_v0 v0;
-	} *args = data;
-	const u32 soff = outp->or * 0x030;
-	const u32 hoff = head * 0x800;
-	int ret, i;
-
-	nv_ioctl(object, "disp sor hda eld size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, true)) {
-		nv_ioctl(object, "disp sor hda eld vers %d\n", args->v0.version);
-		if (size > 0x60)
-			return -E2BIG;
-	} else
-		return ret;
-
-	if (size && args->v0.data[0]) {
-		if (outp->info.type == DCB_OUTPUT_DP) {
-			nv_mask(priv, 0x616618 + hoff, 0x8000000c, 0x80000001);
-			nv_wait(priv, 0x616618 + hoff, 0x80000000, 0x00000000);
-		}
-		nv_mask(priv, 0x616548 + hoff, 0x00000070, 0x00000000);
-		for (i = 0; i < size; i++)
-			nv_wr32(priv, 0x10ec00 + soff, (i << 8) | args->v0.data[i]);
-		for (; i < 0x60; i++)
-			nv_wr32(priv, 0x10ec00 + soff, (i << 8));
-		nv_mask(priv, 0x10ec10 + soff, 0x80000003, 0x80000003);
-	} else {
-		if (outp->info.type == DCB_OUTPUT_DP) {
-			nv_mask(priv, 0x616618 + hoff, 0x80000001, 0x80000000);
-			nv_wait(priv, 0x616618 + hoff, 0x80000000, 0x00000000);
-		}
-		nv_mask(priv, 0x10ec10 + soff, 0x80000003, 0x80000000 | !!size);
-	}
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c
deleted file mode 100644
index fa276dede9cd..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include "nv50.h"
-
-int
-nv84_hdmi_ctrl(NV50_DISP_MTHD_V1)
-{
-	const u32 hoff = (head * 0x800);
-	union {
-		struct nv50_disp_sor_hdmi_pwr_v0 v0;
-	} *args = data;
-	u32 ctrl;
-	int ret;
-
-	nv_ioctl(object, "disp sor hdmi ctrl size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "disp sor hdmi ctrl vers %d state %d "
-				 "max_ac_packet %d rekey %d\n",
-			 args->v0.version, args->v0.state,
-			 args->v0.max_ac_packet, args->v0.rekey);
-		if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f)
-			return -EINVAL;
-		ctrl  = 0x40000000 * !!args->v0.state;
-		ctrl |= args->v0.max_ac_packet << 16;
-		ctrl |= args->v0.rekey;
-		ctrl |= 0x1f000000; /* ??? */
-	} else
-		return ret;
-
-	if (!(ctrl & 0x40000000)) {
-		nv_mask(priv, 0x6165a4 + hoff, 0x40000000, 0x00000000);
-		nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000000);
-		nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000000);
-		return 0;
-	}
-
-	/* AVI InfoFrame */
-	nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000000);
-	nv_wr32(priv, 0x616528 + hoff, 0x000d0282);
-	nv_wr32(priv, 0x61652c + hoff, 0x0000006f);
-	nv_wr32(priv, 0x616530 + hoff, 0x00000000);
-	nv_wr32(priv, 0x616534 + hoff, 0x00000000);
-	nv_wr32(priv, 0x616538 + hoff, 0x00000000);
-	nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000001);
-
-	/* Audio InfoFrame */
-	nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000000);
-	nv_wr32(priv, 0x616508 + hoff, 0x000a0184);
-	nv_wr32(priv, 0x61650c + hoff, 0x00000071);
-	nv_wr32(priv, 0x616510 + hoff, 0x00000000);
-	nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000001);
-
-	nv_mask(priv, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
-	nv_mask(priv, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
-	nv_mask(priv, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
-
-	/* ??? */
-	nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
-	nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
-	nv_mask(priv, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
-
-	/* HDMI_CTRL */
-	nv_mask(priv, 0x6165a4 + hoff, 0x5f1f007f, ctrl);
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c
deleted file mode 100644
index 57eeed1d1942..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include "nv50.h"
-
-int
-nva3_hdmi_ctrl(NV50_DISP_MTHD_V1)
-{
-	const u32 soff = outp->or * 0x800;
-	union {
-		struct nv50_disp_sor_hdmi_pwr_v0 v0;
-	} *args = data;
-	u32 ctrl;
-	int ret;
-
-	nv_ioctl(object, "disp sor hdmi ctrl size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "disp sor hdmi ctrl vers %d state %d "
-				 "max_ac_packet %d rekey %d\n",
-			 args->v0.version, args->v0.state,
-			 args->v0.max_ac_packet, args->v0.rekey);
-		if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f)
-			return -EINVAL;
-		ctrl  = 0x40000000 * !!args->v0.state;
-		ctrl |= args->v0.max_ac_packet << 16;
-		ctrl |= args->v0.rekey;
-		ctrl |= 0x1f000000; /* ??? */
-	} else
-		return ret;
-
-	if (!(ctrl & 0x40000000)) {
-		nv_mask(priv, 0x61c5a4 + soff, 0x40000000, 0x00000000);
-		nv_mask(priv, 0x61c520 + soff, 0x00000001, 0x00000000);
-		nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000000);
-		return 0;
-	}
-
-	/* AVI InfoFrame */
-	nv_mask(priv, 0x61c520 + soff, 0x00000001, 0x00000000);
-	nv_wr32(priv, 0x61c528 + soff, 0x000d0282);
-	nv_wr32(priv, 0x61c52c + soff, 0x0000006f);
-	nv_wr32(priv, 0x61c530 + soff, 0x00000000);
-	nv_wr32(priv, 0x61c534 + soff, 0x00000000);
-	nv_wr32(priv, 0x61c538 + soff, 0x00000000);
-	nv_mask(priv, 0x61c520 + soff, 0x00000001, 0x00000001);
-
-	/* Audio InfoFrame */
-	nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000000);
-	nv_wr32(priv, 0x61c508 + soff, 0x000a0184);
-	nv_wr32(priv, 0x61c50c + soff, 0x00000071);
-	nv_wr32(priv, 0x61c510 + soff, 0x00000000);
-	nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000001);
-
-	nv_mask(priv, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
-	nv_mask(priv, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
-	nv_mask(priv, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
-
-	/* ??? */
-	nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
-	nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
-	nv_mask(priv, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
-
-	/* HDMI_CTRL */
-	nv_mask(priv, 0x61c5a4 + soff, 0x5f1f007f, ctrl);
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminvd0.c
deleted file mode 100644
index bac4fc4570f0..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminvd0.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include "nv50.h"
-
-int
-nvd0_hdmi_ctrl(NV50_DISP_MTHD_V1)
-{
-	const u32 hoff = (head * 0x800);
-	union {
-		struct nv50_disp_sor_hdmi_pwr_v0 v0;
-	} *args = data;
-	u32 ctrl;
-	int ret;
-
-	nv_ioctl(object, "disp sor hdmi ctrl size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "disp sor hdmi ctrl vers %d state %d "
-				 "max_ac_packet %d rekey %d\n",
-			 args->v0.version, args->v0.state,
-			 args->v0.max_ac_packet, args->v0.rekey);
-		if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f)
-			return -EINVAL;
-		ctrl  = 0x40000000 * !!args->v0.state;
-		ctrl |= args->v0.max_ac_packet << 16;
-		ctrl |= args->v0.rekey;
-	} else
-		return ret;
-
-	if (!(ctrl & 0x40000000)) {
-		nv_mask(priv, 0x616798 + hoff, 0x40000000, 0x00000000);
-		nv_mask(priv, 0x6167a4 + hoff, 0x00000001, 0x00000000);
-		nv_mask(priv, 0x616714 + hoff, 0x00000001, 0x00000000);
-		return 0;
-	}
-
-	/* AVI InfoFrame */
-	nv_mask(priv, 0x616714 + hoff, 0x00000001, 0x00000000);
-	nv_wr32(priv, 0x61671c + hoff, 0x000d0282);
-	nv_wr32(priv, 0x616720 + hoff, 0x0000006f);
-	nv_wr32(priv, 0x616724 + hoff, 0x00000000);
-	nv_wr32(priv, 0x616728 + hoff, 0x00000000);
-	nv_wr32(priv, 0x61672c + hoff, 0x00000000);
-	nv_mask(priv, 0x616714 + hoff, 0x00000001, 0x00000001);
-
-	/* ??? InfoFrame? */
-	nv_mask(priv, 0x6167a4 + hoff, 0x00000001, 0x00000000);
-	nv_wr32(priv, 0x6167ac + hoff, 0x00000010);
-	nv_mask(priv, 0x6167a4 + hoff, 0x00000001, 0x00000001);
-
-	/* HDMI_CTRL */
-	nv_mask(priv, 0x616798 + hoff, 0x401f007f, ctrl);
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminve0.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminve0.c
deleted file mode 100644
index 528d14ec2f7f..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminve0.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include "nv50.h"
-
-int
-nve0_hdmi_ctrl(NV50_DISP_MTHD_V1)
-{
-	const u32 hoff = (head * 0x800);
-	const u32 hdmi = (head * 0x400);
-	union {
-		struct nv50_disp_sor_hdmi_pwr_v0 v0;
-	} *args = data;
-	u32 ctrl;
-	int ret;
-
-	nv_ioctl(object, "disp sor hdmi ctrl size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "disp sor hdmi ctrl vers %d state %d "
-				 "max_ac_packet %d rekey %d\n",
-			 args->v0.version, args->v0.state,
-			 args->v0.max_ac_packet, args->v0.rekey);
-		if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f)
-			return -EINVAL;
-		ctrl  = 0x40000000 * !!args->v0.state;
-		ctrl |= args->v0.max_ac_packet << 16;
-		ctrl |= args->v0.rekey;
-	} else
-		return ret;
-
-	if (!(ctrl & 0x40000000)) {
-		nv_mask(priv, 0x616798 + hoff, 0x40000000, 0x00000000);
-		nv_mask(priv, 0x6900c0 + hdmi, 0x00000001, 0x00000000);
-		nv_mask(priv, 0x690000 + hdmi, 0x00000001, 0x00000000);
-		return 0;
-	}
-
-	/* AVI InfoFrame */
-	nv_mask(priv, 0x690000 + hdmi, 0x00000001, 0x00000000);
-	nv_wr32(priv, 0x690008 + hdmi, 0x000d0282);
-	nv_wr32(priv, 0x69000c + hdmi, 0x0000006f);
-	nv_wr32(priv, 0x690010 + hdmi, 0x00000000);
-	nv_wr32(priv, 0x690014 + hdmi, 0x00000000);
-	nv_wr32(priv, 0x690018 + hdmi, 0x00000000);
-	nv_mask(priv, 0x690000 + hdmi, 0x00000001, 0x00000001);
-
-	/* ??? InfoFrame? */
-	nv_mask(priv, 0x6900c0 + hdmi, 0x00000001, 0x00000000);
-	nv_wr32(priv, 0x6900cc + hdmi, 0x00000010);
-	nv_mask(priv, 0x6900c0 + hdmi, 0x00000001, 0x00000001);
-
-	/* ??? */
-	nv_wr32(priv, 0x690080 + hdmi, 0x82000000);
-
-	/* HDMI_CTRL */
-	nv_mask(priv, 0x616798 + hoff, 0x401f007f, ctrl);
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c
deleted file mode 100644
index 366f315fc9a5..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-
-#include <core/client.h>
-#include <core/event.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-struct nv04_disp_priv {
-	struct nouveau_disp base;
-};
-
-static int
-nv04_disp_scanoutpos(struct nouveau_object *object, struct nv04_disp_priv *priv,
-		     void *data, u32 size, int head)
-{
-	const u32 hoff = head * 0x2000;
-	union {
-		struct nv04_disp_scanoutpos_v0 v0;
-	} *args = data;
-	u32 line;
-	int ret;
-
-	nv_ioctl(object, "disp scanoutpos size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "disp scanoutpos vers %d\n", args->v0.version);
-		args->v0.vblanks = nv_rd32(priv, 0x680800 + hoff) & 0xffff;
-		args->v0.vtotal  = nv_rd32(priv, 0x680804 + hoff) & 0xffff;
-		args->v0.vblanke = args->v0.vtotal - 1;
-
-		args->v0.hblanks = nv_rd32(priv, 0x680820 + hoff) & 0xffff;
-		args->v0.htotal  = nv_rd32(priv, 0x680824 + hoff) & 0xffff;
-		args->v0.hblanke = args->v0.htotal - 1;
-
-		/*
-		 * If output is vga instead of digital then vtotal/htotal is
-		 * invalid so we have to give up and trigger the timestamping
-		 * fallback in the drm core.
-		 */
-		if (!args->v0.vtotal || !args->v0.htotal)
-			return -ENOTSUPP;
-
-		args->v0.time[0] = ktime_to_ns(ktime_get());
-		line = nv_rd32(priv, 0x600868 + hoff);
-		args->v0.time[1] = ktime_to_ns(ktime_get());
-		args->v0.hline = (line & 0xffff0000) >> 16;
-		args->v0.vline = (line & 0x0000ffff);
-	} else
-		return ret;
-
-	return 0;
-}
-
-static int
-nv04_disp_mthd(struct nouveau_object *object, u32 mthd, void *data, u32 size)
-{
-	union {
-		struct nv04_disp_mthd_v0 v0;
-	} *args = data;
-	struct nv04_disp_priv *priv = (void *)object->engine;
-	int head, ret;
-
-	nv_ioctl(object, "disp mthd size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, true)) {
-		nv_ioctl(object, "disp mthd vers %d mthd %02x head %d\n",
-			 args->v0.version, args->v0.method, args->v0.head);
-		mthd = args->v0.method;
-		head = args->v0.head;
-	} else
-		return ret;
-
-	if (head < 0 || head >= 2)
-		return -ENXIO;
-
-	switch (mthd) {
-	case NV04_DISP_SCANOUTPOS:
-		return nv04_disp_scanoutpos(object, priv, data, size, head);
-	default:
-		break;
-	}
-
-	return -EINVAL;
-}
-
-static struct nouveau_ofuncs
-nv04_disp_ofuncs = {
-	.ctor = _nouveau_object_ctor,
-	.dtor = nouveau_object_destroy,
-	.init = nouveau_object_init,
-	.fini = nouveau_object_fini,
-	.mthd = nv04_disp_mthd,
-	.ntfy = nouveau_disp_ntfy,
-};
-
-static struct nouveau_oclass
-nv04_disp_sclass[] = {
-	{ NV04_DISP, &nv04_disp_ofuncs },
-	{},
-};
-
-/*******************************************************************************
- * Display engine implementation
- ******************************************************************************/
-
-static void
-nv04_disp_vblank_init(struct nvkm_event *event, int type, int head)
-{
-	struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank);
-	nv_wr32(disp, 0x600140 + (head * 0x2000) , 0x00000001);
-}
-
-static void
-nv04_disp_vblank_fini(struct nvkm_event *event, int type, int head)
-{
-	struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank);
-	nv_wr32(disp, 0x600140 + (head * 0x2000) , 0x00000000);
-}
-
-static const struct nvkm_event_func
-nv04_disp_vblank_func = {
-	.ctor = nouveau_disp_vblank_ctor,
-	.init = nv04_disp_vblank_init,
-	.fini = nv04_disp_vblank_fini,
-};
-
-static void
-nv04_disp_intr(struct nouveau_subdev *subdev)
-{
-	struct nv04_disp_priv *priv = (void *)subdev;
-	u32 crtc0 = nv_rd32(priv, 0x600100);
-	u32 crtc1 = nv_rd32(priv, 0x602100);
-	u32 pvideo;
-
-	if (crtc0 & 0x00000001) {
-		nouveau_disp_vblank(&priv->base, 0);
-		nv_wr32(priv, 0x600100, 0x00000001);
-	}
-
-	if (crtc1 & 0x00000001) {
-		nouveau_disp_vblank(&priv->base, 1);
-		nv_wr32(priv, 0x602100, 0x00000001);
-	}
-
-	if (nv_device(priv)->chipset >= 0x10 &&
-	    nv_device(priv)->chipset <= 0x40) {
-		pvideo = nv_rd32(priv, 0x8100);
-		if (pvideo & ~0x11)
-			nv_info(priv, "PVIDEO intr: %08x\n", pvideo);
-		nv_wr32(priv, 0x8100, pvideo);
-	}
-}
-
-static int
-nv04_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv04_disp_priv *priv;
-	int ret;
-
-	ret = nouveau_disp_create(parent, engine, oclass, 2, "DISPLAY",
-				  "display", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_engine(priv)->sclass = nv04_disp_sclass;
-	nv_subdev(priv)->intr = nv04_disp_intr;
-	return 0;
-}
-
-struct nouveau_oclass *
-nv04_disp_oclass = &(struct nouveau_disp_impl) {
-	.base.handle = NV_ENGINE(DISP, 0x04),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
-	},
-	.vblank = &nv04_disp_vblank_func,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
deleted file mode 100644
index 44a8290aaea5..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ /dev/null
@@ -1,2017 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/object.h>
-#include <core/client.h>
-#include <core/parent.h>
-#include <core/handle.h>
-#include <core/enum.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-#include <nvif/event.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/disp.h>
-#include <subdev/bios/init.h>
-#include <subdev/bios/pll.h>
-#include <subdev/devinit.h>
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include "nv50.h"
-
-/*******************************************************************************
- * EVO channel base class
- ******************************************************************************/
-
-static int
-nv50_disp_chan_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, int head,
-		       int length, void **pobject)
-{
-	const struct nv50_disp_chan_impl *impl = (void *)oclass->ofuncs;
-	struct nv50_disp_base *base = (void *)parent;
-	struct nv50_disp_chan *chan;
-	int chid = impl->chid + head;
-	int ret;
-
-	if (base->chan & (1 << chid))
-		return -EBUSY;
-	base->chan |= (1 << chid);
-
-	ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL,
-				     (1ULL << NVDEV_ENGINE_DMAOBJ),
-				     length, pobject);
-	chan = *pobject;
-	if (ret)
-		return ret;
-	chan->chid = chid;
-
-	nv_parent(chan)->object_attach = impl->attach;
-	nv_parent(chan)->object_detach = impl->detach;
-	return 0;
-}
-
-static void
-nv50_disp_chan_destroy(struct nv50_disp_chan *chan)
-{
-	struct nv50_disp_base *base = (void *)nv_object(chan)->parent;
-	base->chan &= ~(1 << chan->chid);
-	nouveau_namedb_destroy(&chan->base);
-}
-
-static void
-nv50_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
-{
-	struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
-	nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000000 << index);
-	nv_wr32(priv, 0x610020, 0x00000001 << index);
-}
-
-static void
-nv50_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
-{
-	struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
-	nv_wr32(priv, 0x610020, 0x00000001 << index);
-	nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000001 << index);
-}
-
-void
-nv50_disp_chan_uevent_send(struct nv50_disp_priv *priv, int chid)
-{
-	struct nvif_notify_uevent_rep {
-	} rep;
-
-	nvkm_event_send(&priv->uevent, 1, chid, &rep, sizeof(rep));
-}
-
-int
-nv50_disp_chan_uevent_ctor(struct nouveau_object *object, void *data, u32 size,
-			   struct nvkm_notify *notify)
-{
-	struct nv50_disp_dmac *dmac = (void *)object;
-	union {
-		struct nvif_notify_uevent_req none;
-	} *args = data;
-	int ret;
-
-	if (nvif_unvers(args->none)) {
-		notify->size  = sizeof(struct nvif_notify_uevent_rep);
-		notify->types = 1;
-		notify->index = dmac->base.chid;
-		return 0;
-	}
-
-	return ret;
-}
-
-const struct nvkm_event_func
-nv50_disp_chan_uevent = {
-	.ctor = nv50_disp_chan_uevent_ctor,
-	.init = nv50_disp_chan_uevent_init,
-	.fini = nv50_disp_chan_uevent_fini,
-};
-
-int
-nv50_disp_chan_ntfy(struct nouveau_object *object, u32 type,
-		    struct nvkm_event **pevent)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	switch (type) {
-	case NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT:
-		*pevent = &priv->uevent;
-		return 0;
-	default:
-		break;
-	}
-	return -EINVAL;
-}
-
-int
-nv50_disp_chan_map(struct nouveau_object *object, u64 *addr, u32 *size)
-{
-	struct nv50_disp_chan *chan = (void *)object;
-	*addr = nv_device_resource_start(nv_device(object), 0) +
-		0x640000 + (chan->chid * 0x1000);
-	*size = 0x001000;
-	return 0;
-}
-
-u32
-nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nv50_disp_chan *chan = (void *)object;
-	return nv_rd32(priv, 0x640000 + (chan->chid * 0x1000) + addr);
-}
-
-void
-nv50_disp_chan_wr32(struct nouveau_object *object, u64 addr, u32 data)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nv50_disp_chan *chan = (void *)object;
-	nv_wr32(priv, 0x640000 + (chan->chid * 0x1000) + addr, data);
-}
-
-/*******************************************************************************
- * EVO DMA channel base class
- ******************************************************************************/
-
-static int
-nv50_disp_dmac_object_attach(struct nouveau_object *parent,
-			     struct nouveau_object *object, u32 name)
-{
-	struct nv50_disp_base *base = (void *)parent->parent;
-	struct nv50_disp_chan *chan = (void *)parent;
-	u32 addr = nv_gpuobj(object)->node->offset;
-	u32 chid = chan->chid;
-	u32 data = (chid << 28) | (addr << 10) | chid;
-	return nouveau_ramht_insert(base->ramht, chid, name, data);
-}
-
-static void
-nv50_disp_dmac_object_detach(struct nouveau_object *parent, int cookie)
-{
-	struct nv50_disp_base *base = (void *)parent->parent;
-	nouveau_ramht_remove(base->ramht, cookie);
-}
-
-static int
-nv50_disp_dmac_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, u32 pushbuf, int head,
-		       int length, void **pobject)
-{
-	struct nv50_disp_dmac *dmac;
-	int ret;
-
-	ret = nv50_disp_chan_create_(parent, engine, oclass, head,
-				     length, pobject);
-	dmac = *pobject;
-	if (ret)
-		return ret;
-
-	dmac->pushdma = (void *)nouveau_handle_ref(parent, pushbuf);
-	if (!dmac->pushdma)
-		return -ENOENT;
-
-	switch (nv_mclass(dmac->pushdma)) {
-	case 0x0002:
-	case 0x003d:
-		if (dmac->pushdma->limit - dmac->pushdma->start != 0xfff)
-			return -EINVAL;
-
-		switch (dmac->pushdma->target) {
-		case NV_MEM_TARGET_VRAM:
-			dmac->push = 0x00000000 | dmac->pushdma->start >> 8;
-			break;
-		case NV_MEM_TARGET_PCI_NOSNOOP:
-			dmac->push = 0x00000003 | dmac->pushdma->start >> 8;
-			break;
-		default:
-			return -EINVAL;
-		}
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-void
-nv50_disp_dmac_dtor(struct nouveau_object *object)
-{
-	struct nv50_disp_dmac *dmac = (void *)object;
-	nouveau_object_ref(NULL, (struct nouveau_object **)&dmac->pushdma);
-	nv50_disp_chan_destroy(&dmac->base);
-}
-
-static int
-nv50_disp_dmac_init(struct nouveau_object *object)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nv50_disp_dmac *dmac = (void *)object;
-	int chid = dmac->base.chid;
-	int ret;
-
-	ret = nv50_disp_chan_init(&dmac->base);
-	if (ret)
-		return ret;
-
-	/* enable error reporting */
-	nv_mask(priv, 0x610028, 0x00010000 << chid, 0x00010000 << chid);
-
-	/* initialise channel for dma command submission */
-	nv_wr32(priv, 0x610204 + (chid * 0x0010), dmac->push);
-	nv_wr32(priv, 0x610208 + (chid * 0x0010), 0x00010000);
-	nv_wr32(priv, 0x61020c + (chid * 0x0010), chid);
-	nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010);
-	nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000);
-	nv_wr32(priv, 0x610200 + (chid * 0x0010), 0x00000013);
-
-	/* wait for it to go inactive */
-	if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x80000000, 0x00000000)) {
-		nv_error(dmac, "init timeout, 0x%08x\n",
-			 nv_rd32(priv, 0x610200 + (chid * 0x10)));
-		return -EBUSY;
-	}
-
-	return 0;
-}
-
-static int
-nv50_disp_dmac_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nv50_disp_dmac *dmac = (void *)object;
-	int chid = dmac->base.chid;
-
-	/* deactivate channel */
-	nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000);
-	nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000);
-	if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x001e0000, 0x00000000)) {
-		nv_error(dmac, "fini timeout, 0x%08x\n",
-			 nv_rd32(priv, 0x610200 + (chid * 0x10)));
-		if (suspend)
-			return -EBUSY;
-	}
-
-	/* disable error reporting and completion notifications */
-	nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00000000 << chid);
-
-	return nv50_disp_chan_fini(&dmac->base, suspend);
-}
-
-/*******************************************************************************
- * EVO master channel object
- ******************************************************************************/
-
-static void
-nv50_disp_mthd_list(struct nv50_disp_priv *priv, int debug, u32 base, int c,
-		    const struct nv50_disp_mthd_list *list, int inst)
-{
-	struct nouveau_object *disp = nv_object(priv);
-	int i;
-
-	for (i = 0; list->data[i].mthd; i++) {
-		if (list->data[i].addr) {
-			u32 next = nv_rd32(priv, list->data[i].addr + base + 0);
-			u32 prev = nv_rd32(priv, list->data[i].addr + base + c);
-			u32 mthd = list->data[i].mthd + (list->mthd * inst);
-			const char *name = list->data[i].name;
-			char mods[16];
-
-			if (prev != next)
-				snprintf(mods, sizeof(mods), "-> 0x%08x", next);
-			else
-				snprintf(mods, sizeof(mods), "%13c", ' ');
-
-			nv_printk_(disp, debug, "\t0x%04x: 0x%08x %s%s%s\n",
-				   mthd, prev, mods, name ? " // " : "",
-				   name ? name : "");
-		}
-	}
-}
-
-void
-nv50_disp_mthd_chan(struct nv50_disp_priv *priv, int debug, int head,
-		    const struct nv50_disp_mthd_chan *chan)
-{
-	struct nouveau_object *disp = nv_object(priv);
-	const struct nv50_disp_impl *impl = (void *)disp->oclass;
-	const struct nv50_disp_mthd_list *list;
-	int i, j;
-
-	if (debug > nv_subdev(priv)->debug)
-		return;
-
-	for (i = 0; (list = chan->data[i].mthd) != NULL; i++) {
-		u32 base = head * chan->addr;
-		for (j = 0; j < chan->data[i].nr; j++, base += list->addr) {
-			const char *cname = chan->name;
-			const char *sname = "";
-			char cname_[16], sname_[16];
-
-			if (chan->addr) {
-				snprintf(cname_, sizeof(cname_), "%s %d",
-					 chan->name, head);
-				cname = cname_;
-			}
-
-			if (chan->data[i].nr > 1) {
-				snprintf(sname_, sizeof(sname_), " - %s %d",
-					 chan->data[i].name, j);
-				sname = sname_;
-			}
-
-			nv_printk_(disp, debug, "%s%s:\n", cname, sname);
-			nv50_disp_mthd_list(priv, debug, base, impl->mthd.prev,
-					    list, j);
-		}
-	}
-}
-
-const struct nv50_disp_mthd_list
-nv50_disp_core_mthd_base = {
-	.mthd = 0x0000,
-	.addr = 0x000000,
-	.data = {
-		{ 0x0080, 0x000000 },
-		{ 0x0084, 0x610bb8 },
-		{ 0x0088, 0x610b9c },
-		{ 0x008c, 0x000000 },
-		{}
-	}
-};
-
-static const struct nv50_disp_mthd_list
-nv50_disp_core_mthd_dac = {
-	.mthd = 0x0080,
-	.addr = 0x000008,
-	.data = {
-		{ 0x0400, 0x610b58 },
-		{ 0x0404, 0x610bdc },
-		{ 0x0420, 0x610828 },
-		{}
-	}
-};
-
-const struct nv50_disp_mthd_list
-nv50_disp_core_mthd_sor = {
-	.mthd = 0x0040,
-	.addr = 0x000008,
-	.data = {
-		{ 0x0600, 0x610b70 },
-		{}
-	}
-};
-
-const struct nv50_disp_mthd_list
-nv50_disp_core_mthd_pior = {
-	.mthd = 0x0040,
-	.addr = 0x000008,
-	.data = {
-		{ 0x0700, 0x610b80 },
-		{}
-	}
-};
-
-static const struct nv50_disp_mthd_list
-nv50_disp_core_mthd_head = {
-	.mthd = 0x0400,
-	.addr = 0x000540,
-	.data = {
-		{ 0x0800, 0x610ad8 },
-		{ 0x0804, 0x610ad0 },
-		{ 0x0808, 0x610a48 },
-		{ 0x080c, 0x610a78 },
-		{ 0x0810, 0x610ac0 },
-		{ 0x0814, 0x610af8 },
-		{ 0x0818, 0x610b00 },
-		{ 0x081c, 0x610ae8 },
-		{ 0x0820, 0x610af0 },
-		{ 0x0824, 0x610b08 },
-		{ 0x0828, 0x610b10 },
-		{ 0x082c, 0x610a68 },
-		{ 0x0830, 0x610a60 },
-		{ 0x0834, 0x000000 },
-		{ 0x0838, 0x610a40 },
-		{ 0x0840, 0x610a24 },
-		{ 0x0844, 0x610a2c },
-		{ 0x0848, 0x610aa8 },
-		{ 0x084c, 0x610ab0 },
-		{ 0x0860, 0x610a84 },
-		{ 0x0864, 0x610a90 },
-		{ 0x0868, 0x610b18 },
-		{ 0x086c, 0x610b20 },
-		{ 0x0870, 0x610ac8 },
-		{ 0x0874, 0x610a38 },
-		{ 0x0880, 0x610a58 },
-		{ 0x0884, 0x610a9c },
-		{ 0x08a0, 0x610a70 },
-		{ 0x08a4, 0x610a50 },
-		{ 0x08a8, 0x610ae0 },
-		{ 0x08c0, 0x610b28 },
-		{ 0x08c4, 0x610b30 },
-		{ 0x08c8, 0x610b40 },
-		{ 0x08d4, 0x610b38 },
-		{ 0x08d8, 0x610b48 },
-		{ 0x08dc, 0x610b50 },
-		{ 0x0900, 0x610a18 },
-		{ 0x0904, 0x610ab8 },
-		{}
-	}
-};
-
-static const struct nv50_disp_mthd_chan
-nv50_disp_core_mthd_chan = {
-	.name = "Core",
-	.addr = 0x000000,
-	.data = {
-		{ "Global", 1, &nv50_disp_core_mthd_base },
-		{    "DAC", 3, &nv50_disp_core_mthd_dac  },
-		{    "SOR", 2, &nv50_disp_core_mthd_sor  },
-		{   "PIOR", 3, &nv50_disp_core_mthd_pior },
-		{   "HEAD", 2, &nv50_disp_core_mthd_head },
-		{}
-	}
-};
-
-int
-nv50_disp_core_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
-{
-	union {
-		struct nv50_disp_core_channel_dma_v0 v0;
-	} *args = data;
-	struct nv50_disp_dmac *mast;
-	int ret;
-
-	nv_ioctl(parent, "create disp core channel dma size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create disp core channel dma vers %d "
-				 "pushbuf %08x\n",
-			 args->v0.version, args->v0.pushbuf);
-	} else
-		return ret;
-
-	ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf,
-				     0, sizeof(*mast), (void **)&mast);
-	*pobject = nv_object(mast);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-static int
-nv50_disp_core_init(struct nouveau_object *object)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nv50_disp_dmac *mast = (void *)object;
-	int ret;
-
-	ret = nv50_disp_chan_init(&mast->base);
-	if (ret)
-		return ret;
-
-	/* enable error reporting */
-	nv_mask(priv, 0x610028, 0x00010000, 0x00010000);
-
-	/* attempt to unstick channel from some unknown state */
-	if ((nv_rd32(priv, 0x610200) & 0x009f0000) == 0x00020000)
-		nv_mask(priv, 0x610200, 0x00800000, 0x00800000);
-	if ((nv_rd32(priv, 0x610200) & 0x003f0000) == 0x00030000)
-		nv_mask(priv, 0x610200, 0x00600000, 0x00600000);
-
-	/* initialise channel for dma command submission */
-	nv_wr32(priv, 0x610204, mast->push);
-	nv_wr32(priv, 0x610208, 0x00010000);
-	nv_wr32(priv, 0x61020c, 0x00000000);
-	nv_mask(priv, 0x610200, 0x00000010, 0x00000010);
-	nv_wr32(priv, 0x640000, 0x00000000);
-	nv_wr32(priv, 0x610200, 0x01000013);
-
-	/* wait for it to go inactive */
-	if (!nv_wait(priv, 0x610200, 0x80000000, 0x00000000)) {
-		nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610200));
-		return -EBUSY;
-	}
-
-	return 0;
-}
-
-static int
-nv50_disp_core_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nv50_disp_dmac *mast = (void *)object;
-
-	/* deactivate channel */
-	nv_mask(priv, 0x610200, 0x00000010, 0x00000000);
-	nv_mask(priv, 0x610200, 0x00000003, 0x00000000);
-	if (!nv_wait(priv, 0x610200, 0x001e0000, 0x00000000)) {
-		nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610200));
-		if (suspend)
-			return -EBUSY;
-	}
-
-	/* disable error reporting and completion notifications */
-	nv_mask(priv, 0x610028, 0x00010001, 0x00000000);
-
-	return nv50_disp_chan_fini(&mast->base, suspend);
-}
-
-struct nv50_disp_chan_impl
-nv50_disp_core_ofuncs = {
-	.base.ctor = nv50_disp_core_ctor,
-	.base.dtor = nv50_disp_dmac_dtor,
-	.base.init = nv50_disp_core_init,
-	.base.fini = nv50_disp_core_fini,
-	.base.map  = nv50_disp_chan_map,
-	.base.ntfy = nv50_disp_chan_ntfy,
-	.base.rd32 = nv50_disp_chan_rd32,
-	.base.wr32 = nv50_disp_chan_wr32,
-	.chid = 0,
-	.attach = nv50_disp_dmac_object_attach,
-	.detach = nv50_disp_dmac_object_detach,
-};
-
-/*******************************************************************************
- * EVO sync channel objects
- ******************************************************************************/
-
-static const struct nv50_disp_mthd_list
-nv50_disp_base_mthd_base = {
-	.mthd = 0x0000,
-	.addr = 0x000000,
-	.data = {
-		{ 0x0080, 0x000000 },
-		{ 0x0084, 0x0008c4 },
-		{ 0x0088, 0x0008d0 },
-		{ 0x008c, 0x0008dc },
-		{ 0x0090, 0x0008e4 },
-		{ 0x0094, 0x610884 },
-		{ 0x00a0, 0x6108a0 },
-		{ 0x00a4, 0x610878 },
-		{ 0x00c0, 0x61086c },
-		{ 0x00e0, 0x610858 },
-		{ 0x00e4, 0x610860 },
-		{ 0x00e8, 0x6108ac },
-		{ 0x00ec, 0x6108b4 },
-		{ 0x0100, 0x610894 },
-		{ 0x0110, 0x6108bc },
-		{ 0x0114, 0x61088c },
-		{}
-	}
-};
-
-const struct nv50_disp_mthd_list
-nv50_disp_base_mthd_image = {
-	.mthd = 0x0400,
-	.addr = 0x000000,
-	.data = {
-		{ 0x0800, 0x6108f0 },
-		{ 0x0804, 0x6108fc },
-		{ 0x0808, 0x61090c },
-		{ 0x080c, 0x610914 },
-		{ 0x0810, 0x610904 },
-		{}
-	}
-};
-
-static const struct nv50_disp_mthd_chan
-nv50_disp_base_mthd_chan = {
-	.name = "Base",
-	.addr = 0x000540,
-	.data = {
-		{ "Global", 1, &nv50_disp_base_mthd_base },
-		{  "Image", 2, &nv50_disp_base_mthd_image },
-		{}
-	}
-};
-
-int
-nv50_disp_base_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
-{
-	union {
-		struct nv50_disp_base_channel_dma_v0 v0;
-	} *args = data;
-	struct nv50_disp_priv *priv = (void *)engine;
-	struct nv50_disp_dmac *dmac;
-	int ret;
-
-	nv_ioctl(parent, "create disp base channel dma size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create disp base channel dma vers %d "
-				 "pushbuf %08x head %d\n",
-			 args->v0.version, args->v0.pushbuf, args->v0.head);
-		if (args->v0.head > priv->head.nr)
-			return -EINVAL;
-	} else
-		return ret;
-
-	ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf,
-				     args->v0.head, sizeof(*dmac),
-				     (void **)&dmac);
-	*pobject = nv_object(dmac);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-struct nv50_disp_chan_impl
-nv50_disp_base_ofuncs = {
-	.base.ctor = nv50_disp_base_ctor,
-	.base.dtor = nv50_disp_dmac_dtor,
-	.base.init = nv50_disp_dmac_init,
-	.base.fini = nv50_disp_dmac_fini,
-	.base.ntfy = nv50_disp_chan_ntfy,
-	.base.map  = nv50_disp_chan_map,
-	.base.rd32 = nv50_disp_chan_rd32,
-	.base.wr32 = nv50_disp_chan_wr32,
-	.chid = 1,
-	.attach = nv50_disp_dmac_object_attach,
-	.detach = nv50_disp_dmac_object_detach,
-};
-
-/*******************************************************************************
- * EVO overlay channel objects
- ******************************************************************************/
-
-const struct nv50_disp_mthd_list
-nv50_disp_ovly_mthd_base = {
-	.mthd = 0x0000,
-	.addr = 0x000000,
-	.data = {
-		{ 0x0080, 0x000000 },
-		{ 0x0084, 0x0009a0 },
-		{ 0x0088, 0x0009c0 },
-		{ 0x008c, 0x0009c8 },
-		{ 0x0090, 0x6109b4 },
-		{ 0x0094, 0x610970 },
-		{ 0x00a0, 0x610998 },
-		{ 0x00a4, 0x610964 },
-		{ 0x00c0, 0x610958 },
-		{ 0x00e0, 0x6109a8 },
-		{ 0x00e4, 0x6109d0 },
-		{ 0x00e8, 0x6109d8 },
-		{ 0x0100, 0x61094c },
-		{ 0x0104, 0x610984 },
-		{ 0x0108, 0x61098c },
-		{ 0x0800, 0x6109f8 },
-		{ 0x0808, 0x610a08 },
-		{ 0x080c, 0x610a10 },
-		{ 0x0810, 0x610a00 },
-		{}
-	}
-};
-
-static const struct nv50_disp_mthd_chan
-nv50_disp_ovly_mthd_chan = {
-	.name = "Overlay",
-	.addr = 0x000540,
-	.data = {
-		{ "Global", 1, &nv50_disp_ovly_mthd_base },
-		{}
-	}
-};
-
-int
-nv50_disp_ovly_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
-{
-	union {
-		struct nv50_disp_overlay_channel_dma_v0 v0;
-	} *args = data;
-	struct nv50_disp_priv *priv = (void *)engine;
-	struct nv50_disp_dmac *dmac;
-	int ret;
-
-	nv_ioctl(parent, "create disp overlay channel dma size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create disp overlay channel dma vers %d "
-				 "pushbuf %08x head %d\n",
-			 args->v0.version, args->v0.pushbuf, args->v0.head);
-		if (args->v0.head > priv->head.nr)
-			return -EINVAL;
-	} else
-		return ret;
-
-	ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf,
-				     args->v0.head, sizeof(*dmac),
-				     (void **)&dmac);
-	*pobject = nv_object(dmac);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-struct nv50_disp_chan_impl
-nv50_disp_ovly_ofuncs = {
-	.base.ctor = nv50_disp_ovly_ctor,
-	.base.dtor = nv50_disp_dmac_dtor,
-	.base.init = nv50_disp_dmac_init,
-	.base.fini = nv50_disp_dmac_fini,
-	.base.ntfy = nv50_disp_chan_ntfy,
-	.base.map  = nv50_disp_chan_map,
-	.base.rd32 = nv50_disp_chan_rd32,
-	.base.wr32 = nv50_disp_chan_wr32,
-	.chid = 3,
-	.attach = nv50_disp_dmac_object_attach,
-	.detach = nv50_disp_dmac_object_detach,
-};
-
-/*******************************************************************************
- * EVO PIO channel base class
- ******************************************************************************/
-
-static int
-nv50_disp_pioc_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, int head,
-		       int length, void **pobject)
-{
-	return nv50_disp_chan_create_(parent, engine, oclass, head,
-				      length, pobject);
-}
-
-void
-nv50_disp_pioc_dtor(struct nouveau_object *object)
-{
-	struct nv50_disp_pioc *pioc = (void *)object;
-	nv50_disp_chan_destroy(&pioc->base);
-}
-
-static int
-nv50_disp_pioc_init(struct nouveau_object *object)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nv50_disp_pioc *pioc = (void *)object;
-	int chid = pioc->base.chid;
-	int ret;
-
-	ret = nv50_disp_chan_init(&pioc->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00002000);
-	if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00000000, 0x00000000)) {
-		nv_error(pioc, "timeout0: 0x%08x\n",
-			 nv_rd32(priv, 0x610200 + (chid * 0x10)));
-		return -EBUSY;
-	}
-
-	nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00000001);
-	if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00010000)) {
-		nv_error(pioc, "timeout1: 0x%08x\n",
-			 nv_rd32(priv, 0x610200 + (chid * 0x10)));
-		return -EBUSY;
-	}
-
-	return 0;
-}
-
-static int
-nv50_disp_pioc_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nv50_disp_pioc *pioc = (void *)object;
-	int chid = pioc->base.chid;
-
-	nv_mask(priv, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000);
-	if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00000000)) {
-		nv_error(pioc, "timeout: 0x%08x\n",
-			 nv_rd32(priv, 0x610200 + (chid * 0x10)));
-		if (suspend)
-			return -EBUSY;
-	}
-
-	return nv50_disp_chan_fini(&pioc->base, suspend);
-}
-
-/*******************************************************************************
- * EVO immediate overlay channel objects
- ******************************************************************************/
-
-int
-nv50_disp_oimm_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
-{
-	union {
-		struct nv50_disp_overlay_v0 v0;
-	} *args = data;
-	struct nv50_disp_priv *priv = (void *)engine;
-	struct nv50_disp_pioc *pioc;
-	int ret;
-
-	nv_ioctl(parent, "create disp overlay size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create disp overlay vers %d head %d\n",
-			 args->v0.version, args->v0.head);
-		if (args->v0.head > priv->head.nr)
-			return -EINVAL;
-	} else
-		return ret;
-
-	ret = nv50_disp_pioc_create_(parent, engine, oclass, args->v0.head,
-				     sizeof(*pioc), (void **)&pioc);
-	*pobject = nv_object(pioc);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-struct nv50_disp_chan_impl
-nv50_disp_oimm_ofuncs = {
-	.base.ctor = nv50_disp_oimm_ctor,
-	.base.dtor = nv50_disp_pioc_dtor,
-	.base.init = nv50_disp_pioc_init,
-	.base.fini = nv50_disp_pioc_fini,
-	.base.ntfy = nv50_disp_chan_ntfy,
-	.base.map  = nv50_disp_chan_map,
-	.base.rd32 = nv50_disp_chan_rd32,
-	.base.wr32 = nv50_disp_chan_wr32,
-	.chid = 5,
-};
-
-/*******************************************************************************
- * EVO cursor channel objects
- ******************************************************************************/
-
-int
-nv50_disp_curs_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
-{
-	union {
-		struct nv50_disp_cursor_v0 v0;
-	} *args = data;
-	struct nv50_disp_priv *priv = (void *)engine;
-	struct nv50_disp_pioc *pioc;
-	int ret;
-
-	nv_ioctl(parent, "create disp cursor size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create disp cursor vers %d head %d\n",
-			 args->v0.version, args->v0.head);
-		if (args->v0.head > priv->head.nr)
-			return -EINVAL;
-	} else
-		return ret;
-
-	ret = nv50_disp_pioc_create_(parent, engine, oclass, args->v0.head,
-				     sizeof(*pioc), (void **)&pioc);
-	*pobject = nv_object(pioc);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-struct nv50_disp_chan_impl
-nv50_disp_curs_ofuncs = {
-	.base.ctor = nv50_disp_curs_ctor,
-	.base.dtor = nv50_disp_pioc_dtor,
-	.base.init = nv50_disp_pioc_init,
-	.base.fini = nv50_disp_pioc_fini,
-	.base.ntfy = nv50_disp_chan_ntfy,
-	.base.map  = nv50_disp_chan_map,
-	.base.rd32 = nv50_disp_chan_rd32,
-	.base.wr32 = nv50_disp_chan_wr32,
-	.chid = 7,
-};
-
-/*******************************************************************************
- * Base display object
- ******************************************************************************/
-
-int
-nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0)
-{
-	const u32 blanke = nv_rd32(priv, 0x610aec + (head * 0x540));
-	const u32 blanks = nv_rd32(priv, 0x610af4 + (head * 0x540));
-	const u32 total  = nv_rd32(priv, 0x610afc + (head * 0x540));
-	union {
-		struct nv04_disp_scanoutpos_v0 v0;
-	} *args = data;
-	int ret;
-
-	nv_ioctl(object, "disp scanoutpos size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "disp scanoutpos vers %d\n", args->v0.version);
-		args->v0.vblanke = (blanke & 0xffff0000) >> 16;
-		args->v0.hblanke = (blanke & 0x0000ffff);
-		args->v0.vblanks = (blanks & 0xffff0000) >> 16;
-		args->v0.hblanks = (blanks & 0x0000ffff);
-		args->v0.vtotal  = ( total & 0xffff0000) >> 16;
-		args->v0.htotal  = ( total & 0x0000ffff);
-		args->v0.time[0] = ktime_to_ns(ktime_get());
-		args->v0.vline = /* vline read locks hline */
-			nv_rd32(priv, 0x616340 + (head * 0x800)) & 0xffff;
-		args->v0.time[1] = ktime_to_ns(ktime_get());
-		args->v0.hline =
-			nv_rd32(priv, 0x616344 + (head * 0x800)) & 0xffff;
-	} else
-		return ret;
-
-	return 0;
-}
-
-int
-nv50_disp_main_mthd(struct nouveau_object *object, u32 mthd,
-		    void *data, u32 size)
-{
-	const struct nv50_disp_impl *impl = (void *)nv_oclass(object->engine);
-	union {
-		struct nv50_disp_mthd_v0 v0;
-		struct nv50_disp_mthd_v1 v1;
-	} *args = data;
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nvkm_output *outp = NULL;
-	struct nvkm_output *temp;
-	u16 type, mask = 0;
-	int head, ret;
-
-	if (mthd != NV50_DISP_MTHD)
-		return -EINVAL;
-
-	nv_ioctl(object, "disp mthd size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, true)) {
-		nv_ioctl(object, "disp mthd vers %d mthd %02x head %d\n",
-			 args->v0.version, args->v0.method, args->v0.head);
-		mthd = args->v0.method;
-		head = args->v0.head;
-	} else
-	if (nvif_unpack(args->v1, 1, 1, true)) {
-		nv_ioctl(object, "disp mthd vers %d mthd %02x "
-				 "type %04x mask %04x\n",
-			 args->v1.version, args->v1.method,
-			 args->v1.hasht, args->v1.hashm);
-		mthd = args->v1.method;
-		type = args->v1.hasht;
-		mask = args->v1.hashm;
-		head = ffs((mask >> 8) & 0x0f) - 1;
-	} else
-		return ret;
-
-	if (head < 0 || head >= priv->head.nr)
-		return -ENXIO;
-
-	if (mask) {
-		list_for_each_entry(temp, &priv->base.outp, head) {
-			if ((temp->info.hasht         == type) &&
-			    (temp->info.hashm & mask) == mask) {
-				outp = temp;
-				break;
-			}
-		}
-		if (outp == NULL)
-			return -ENXIO;
-	}
-
-	switch (mthd) {
-	case NV50_DISP_SCANOUTPOS:
-		return impl->head.scanoutpos(object, priv, data, size, head);
-	default:
-		break;
-	}
-
-	switch (mthd * !!outp) {
-	case NV50_DISP_MTHD_V1_DAC_PWR:
-		return priv->dac.power(object, priv, data, size, head, outp);
-	case NV50_DISP_MTHD_V1_DAC_LOAD:
-		return priv->dac.sense(object, priv, data, size, head, outp);
-	case NV50_DISP_MTHD_V1_SOR_PWR:
-		return priv->sor.power(object, priv, data, size, head, outp);
-	case NV50_DISP_MTHD_V1_SOR_HDA_ELD:
-		if (!priv->sor.hda_eld)
-			return -ENODEV;
-		return priv->sor.hda_eld(object, priv, data, size, head, outp);
-	case NV50_DISP_MTHD_V1_SOR_HDMI_PWR:
-		if (!priv->sor.hdmi)
-			return -ENODEV;
-		return priv->sor.hdmi(object, priv, data, size, head, outp);
-	case NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT: {
-		union {
-			struct nv50_disp_sor_lvds_script_v0 v0;
-		} *args = data;
-		nv_ioctl(object, "disp sor lvds script size %d\n", size);
-		if (nvif_unpack(args->v0, 0, 0, false)) {
-			nv_ioctl(object, "disp sor lvds script "
-					 "vers %d name %04x\n",
-				 args->v0.version, args->v0.script);
-			priv->sor.lvdsconf = args->v0.script;
-			return 0;
-		} else
-			return ret;
-	}
-		break;
-	case NV50_DISP_MTHD_V1_SOR_DP_PWR: {
-		struct nvkm_output_dp *outpdp = (void *)outp;
-		union {
-			struct nv50_disp_sor_dp_pwr_v0 v0;
-		} *args = data;
-		nv_ioctl(object, "disp sor dp pwr size %d\n", size);
-		if (nvif_unpack(args->v0, 0, 0, false)) {
-			nv_ioctl(object, "disp sor dp pwr vers %d state %d\n",
-				 args->v0.version, args->v0.state);
-			if (args->v0.state == 0) {
-				nvkm_notify_put(&outpdp->irq);
-				((struct nvkm_output_dp_impl *)nv_oclass(outp))
-					->lnk_pwr(outpdp, 0);
-				atomic_set(&outpdp->lt.done, 0);
-				return 0;
-			} else
-			if (args->v0.state != 0) {
-				nvkm_output_dp_train(&outpdp->base, 0, true);
-				return 0;
-			}
-		} else
-			return ret;
-	}
-		break;
-	case NV50_DISP_MTHD_V1_PIOR_PWR:
-		if (!priv->pior.power)
-			return -ENODEV;
-		return priv->pior.power(object, priv, data, size, head, outp);
-	default:
-		break;
-	}
-
-	return -EINVAL;
-}
-
-int
-nv50_disp_main_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
-{
-	struct nv50_disp_priv *priv = (void *)engine;
-	struct nv50_disp_base *base;
-	int ret;
-
-	ret = nouveau_parent_create(parent, engine, oclass, 0,
-				    priv->sclass, 0, &base);
-	*pobject = nv_object(base);
-	if (ret)
-		return ret;
-
-	return nouveau_ramht_new(nv_object(base), nv_object(base), 0x1000, 0,
-				&base->ramht);
-}
-
-void
-nv50_disp_main_dtor(struct nouveau_object *object)
-{
-	struct nv50_disp_base *base = (void *)object;
-	nouveau_ramht_ref(NULL, &base->ramht);
-	nouveau_parent_destroy(&base->base);
-}
-
-static int
-nv50_disp_main_init(struct nouveau_object *object)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nv50_disp_base *base = (void *)object;
-	int ret, i;
-	u32 tmp;
-
-	ret = nouveau_parent_init(&base->base);
-	if (ret)
-		return ret;
-
-	/* The below segments of code copying values from one register to
-	 * another appear to inform EVO of the display capabilities or
-	 * something similar.  NFI what the 0x614004 caps are for..
-	 */
-	tmp = nv_rd32(priv, 0x614004);
-	nv_wr32(priv, 0x610184, tmp);
-
-	/* ... CRTC caps */
-	for (i = 0; i < priv->head.nr; i++) {
-		tmp = nv_rd32(priv, 0x616100 + (i * 0x800));
-		nv_wr32(priv, 0x610190 + (i * 0x10), tmp);
-		tmp = nv_rd32(priv, 0x616104 + (i * 0x800));
-		nv_wr32(priv, 0x610194 + (i * 0x10), tmp);
-		tmp = nv_rd32(priv, 0x616108 + (i * 0x800));
-		nv_wr32(priv, 0x610198 + (i * 0x10), tmp);
-		tmp = nv_rd32(priv, 0x61610c + (i * 0x800));
-		nv_wr32(priv, 0x61019c + (i * 0x10), tmp);
-	}
-
-	/* ... DAC caps */
-	for (i = 0; i < priv->dac.nr; i++) {
-		tmp = nv_rd32(priv, 0x61a000 + (i * 0x800));
-		nv_wr32(priv, 0x6101d0 + (i * 0x04), tmp);
-	}
-
-	/* ... SOR caps */
-	for (i = 0; i < priv->sor.nr; i++) {
-		tmp = nv_rd32(priv, 0x61c000 + (i * 0x800));
-		nv_wr32(priv, 0x6101e0 + (i * 0x04), tmp);
-	}
-
-	/* ... PIOR caps */
-	for (i = 0; i < priv->pior.nr; i++) {
-		tmp = nv_rd32(priv, 0x61e000 + (i * 0x800));
-		nv_wr32(priv, 0x6101f0 + (i * 0x04), tmp);
-	}
-
-	/* steal display away from vbios, or something like that */
-	if (nv_rd32(priv, 0x610024) & 0x00000100) {
-		nv_wr32(priv, 0x610024, 0x00000100);
-		nv_mask(priv, 0x6194e8, 0x00000001, 0x00000000);
-		if (!nv_wait(priv, 0x6194e8, 0x00000002, 0x00000000)) {
-			nv_error(priv, "timeout acquiring display\n");
-			return -EBUSY;
-		}
-	}
-
-	/* point at display engine memory area (hash table, objects) */
-	nv_wr32(priv, 0x610010, (nv_gpuobj(base->ramht)->addr >> 8) | 9);
-
-	/* enable supervisor interrupts, disable everything else */
-	nv_wr32(priv, 0x61002c, 0x00000370);
-	nv_wr32(priv, 0x610028, 0x00000000);
-	return 0;
-}
-
-static int
-nv50_disp_main_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nv50_disp_base *base = (void *)object;
-
-	/* disable all interrupts */
-	nv_wr32(priv, 0x610024, 0x00000000);
-	nv_wr32(priv, 0x610020, 0x00000000);
-
-	return nouveau_parent_fini(&base->base, suspend);
-}
-
-struct nouveau_ofuncs
-nv50_disp_main_ofuncs = {
-	.ctor = nv50_disp_main_ctor,
-	.dtor = nv50_disp_main_dtor,
-	.init = nv50_disp_main_init,
-	.fini = nv50_disp_main_fini,
-	.mthd = nv50_disp_main_mthd,
-	.ntfy = nouveau_disp_ntfy,
-};
-
-static struct nouveau_oclass
-nv50_disp_main_oclass[] = {
-	{ NV50_DISP, &nv50_disp_main_ofuncs },
-	{}
-};
-
-static struct nouveau_oclass
-nv50_disp_sclass[] = {
-	{ NV50_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
-	{ NV50_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
-	{ NV50_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
-	{ NV50_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
-	{ NV50_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
-	{}
-};
-
-/*******************************************************************************
- * Display context, tracks instmem allocation and prevents more than one
- * client using the display hardware at any time.
- ******************************************************************************/
-
-static int
-nv50_disp_data_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
-{
-	struct nv50_disp_priv *priv = (void *)engine;
-	struct nouveau_engctx *ectx;
-	int ret = -EBUSY;
-
-	/* no context needed for channel objects... */
-	if (nv_mclass(parent) != NV_DEVICE) {
-		atomic_inc(&parent->refcount);
-		*pobject = parent;
-		return 1;
-	}
-
-	/* allocate display hardware to client */
-	mutex_lock(&nv_subdev(priv)->mutex);
-	if (list_empty(&nv_engine(priv)->contexts)) {
-		ret = nouveau_engctx_create(parent, engine, oclass, NULL,
-					    0x10000, 0x10000,
-					    NVOBJ_FLAG_HEAP, &ectx);
-		*pobject = nv_object(ectx);
-	}
-	mutex_unlock(&nv_subdev(priv)->mutex);
-	return ret;
-}
-
-struct nouveau_oclass
-nv50_disp_cclass = {
-	.handle = NV_ENGCTX(DISP, 0x50),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_disp_data_ctor,
-		.dtor = _nouveau_engctx_dtor,
-		.init = _nouveau_engctx_init,
-		.fini = _nouveau_engctx_fini,
-		.rd32 = _nouveau_engctx_rd32,
-		.wr32 = _nouveau_engctx_wr32,
-	},
-};
-
-/*******************************************************************************
- * Display engine implementation
- ******************************************************************************/
-
-static void
-nv50_disp_vblank_fini(struct nvkm_event *event, int type, int head)
-{
-	struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank);
-	nv_mask(disp, 0x61002c, (4 << head), 0);
-}
-
-static void
-nv50_disp_vblank_init(struct nvkm_event *event, int type, int head)
-{
-	struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank);
-	nv_mask(disp, 0x61002c, (4 << head), (4 << head));
-}
-
-const struct nvkm_event_func
-nv50_disp_vblank_func = {
-	.ctor = nouveau_disp_vblank_ctor,
-	.init = nv50_disp_vblank_init,
-	.fini = nv50_disp_vblank_fini,
-};
-
-static const struct nouveau_enum
-nv50_disp_intr_error_type[] = {
-	{ 3, "ILLEGAL_MTHD" },
-	{ 4, "INVALID_VALUE" },
-	{ 5, "INVALID_STATE" },
-	{ 7, "INVALID_HANDLE" },
-	{}
-};
-
-static const struct nouveau_enum
-nv50_disp_intr_error_code[] = {
-	{ 0x00, "" },
-	{}
-};
-
-static void
-nv50_disp_intr_error(struct nv50_disp_priv *priv, int chid)
-{
-	struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass;
-	u32 data = nv_rd32(priv, 0x610084 + (chid * 0x08));
-	u32 addr = nv_rd32(priv, 0x610080 + (chid * 0x08));
-	u32 code = (addr & 0x00ff0000) >> 16;
-	u32 type = (addr & 0x00007000) >> 12;
-	u32 mthd = (addr & 0x00000ffc);
-	const struct nouveau_enum *ec, *et;
-	char ecunk[6], etunk[6];
-
-	et = nouveau_enum_find(nv50_disp_intr_error_type, type);
-	if (!et)
-		snprintf(etunk, sizeof(etunk), "UNK%02X", type);
-
-	ec = nouveau_enum_find(nv50_disp_intr_error_code, code);
-	if (!ec)
-		snprintf(ecunk, sizeof(ecunk), "UNK%02X", code);
-
-	nv_error(priv, "%s [%s] chid %d mthd 0x%04x data 0x%08x\n",
-		 et ? et->name : etunk, ec ? ec->name : ecunk,
-		 chid, mthd, data);
-
-	if (chid == 0) {
-		switch (mthd) {
-		case 0x0080:
-			nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 0,
-					    impl->mthd.core);
-			break;
-		default:
-			break;
-		}
-	} else
-	if (chid <= 2) {
-		switch (mthd) {
-		case 0x0080:
-			nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 1,
-					    impl->mthd.base);
-			break;
-		default:
-			break;
-		}
-	} else
-	if (chid <= 4) {
-		switch (mthd) {
-		case 0x0080:
-			nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 3,
-					    impl->mthd.ovly);
-			break;
-		default:
-			break;
-		}
-	}
-
-	nv_wr32(priv, 0x610020, 0x00010000 << chid);
-	nv_wr32(priv, 0x610080 + (chid * 0x08), 0x90000000);
-}
-
-static struct nvkm_output *
-exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl,
-	    u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-	    struct nvbios_outp *info)
-{
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	struct nvkm_output *outp;
-	u16 mask, type;
-
-	if (or < 4) {
-		type = DCB_OUTPUT_ANALOG;
-		mask = 0;
-	} else
-	if (or < 8) {
-		switch (ctrl & 0x00000f00) {
-		case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break;
-		case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break;
-		case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break;
-		case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break;
-		case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break;
-		case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break;
-		default:
-			nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl);
-			return NULL;
-		}
-		or  -= 4;
-	} else {
-		or   = or - 8;
-		type = 0x0010;
-		mask = 0;
-		switch (ctrl & 0x00000f00) {
-		case 0x00000000: type |= priv->pior.type[or]; break;
-		default:
-			nv_error(priv, "unknown PIOR mc 0x%08x\n", ctrl);
-			return NULL;
-		}
-	}
-
-	mask  = 0x00c0 & (mask << 6);
-	mask |= 0x0001 << or;
-	mask |= 0x0100 << head;
-
-	list_for_each_entry(outp, &priv->base.outp, head) {
-		if ((outp->info.hasht & 0xff) == type &&
-		    (outp->info.hashm & mask) == mask) {
-			*data = nvbios_outp_match(bios, outp->info.hasht,
-							outp->info.hashm,
-						  ver, hdr, cnt, len, info);
-			if (!*data)
-				return NULL;
-			return outp;
-		}
-	}
-
-	return NULL;
-}
-
-static struct nvkm_output *
-exec_script(struct nv50_disp_priv *priv, int head, int id)
-{
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	struct nvkm_output *outp;
-	struct nvbios_outp info;
-	u8  ver, hdr, cnt, len;
-	u32 data, ctrl = 0;
-	u32 reg;
-	int i;
-
-	/* DAC */
-	for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++)
-		ctrl = nv_rd32(priv, 0x610b5c + (i * 8));
-
-	/* SOR */
-	if (!(ctrl & (1 << head))) {
-		if (nv_device(priv)->chipset  < 0x90 ||
-		    nv_device(priv)->chipset == 0x92 ||
-		    nv_device(priv)->chipset == 0xa0) {
-			reg = 0x610b74;
-		} else {
-			reg = 0x610798;
-		}
-		for (i = 0; !(ctrl & (1 << head)) && i < priv->sor.nr; i++)
-			ctrl = nv_rd32(priv, reg + (i * 8));
-		i += 4;
-	}
-
-	/* PIOR */
-	if (!(ctrl & (1 << head))) {
-		for (i = 0; !(ctrl & (1 << head)) && i < priv->pior.nr; i++)
-			ctrl = nv_rd32(priv, 0x610b84 + (i * 8));
-		i += 8;
-	}
-
-	if (!(ctrl & (1 << head)))
-		return NULL;
-	i--;
-
-	outp = exec_lookup(priv, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info);
-	if (outp) {
-		struct nvbios_init init = {
-			.subdev = nv_subdev(priv),
-			.bios = bios,
-			.offset = info.script[id],
-			.outp = &outp->info,
-			.crtc = head,
-			.execute = 1,
-		};
-
-		nvbios_exec(&init);
-	}
-
-	return outp;
-}
-
-static struct nvkm_output *
-exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf)
-{
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	struct nvkm_output *outp;
-	struct nvbios_outp info1;
-	struct nvbios_ocfg info2;
-	u8  ver, hdr, cnt, len;
-	u32 data, ctrl = 0;
-	u32 reg;
-	int i;
-
-	/* DAC */
-	for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++)
-		ctrl = nv_rd32(priv, 0x610b58 + (i * 8));
-
-	/* SOR */
-	if (!(ctrl & (1 << head))) {
-		if (nv_device(priv)->chipset  < 0x90 ||
-		    nv_device(priv)->chipset == 0x92 ||
-		    nv_device(priv)->chipset == 0xa0) {
-			reg = 0x610b70;
-		} else {
-			reg = 0x610794;
-		}
-		for (i = 0; !(ctrl & (1 << head)) && i < priv->sor.nr; i++)
-			ctrl = nv_rd32(priv, reg + (i * 8));
-		i += 4;
-	}
-
-	/* PIOR */
-	if (!(ctrl & (1 << head))) {
-		for (i = 0; !(ctrl & (1 << head)) && i < priv->pior.nr; i++)
-			ctrl = nv_rd32(priv, 0x610b80 + (i * 8));
-		i += 8;
-	}
-
-	if (!(ctrl & (1 << head)))
-		return NULL;
-	i--;
-
-	outp = exec_lookup(priv, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1);
-	if (!outp)
-		return NULL;
-
-	if (outp->info.location == 0) {
-		switch (outp->info.type) {
-		case DCB_OUTPUT_TMDS:
-			*conf = (ctrl & 0x00000f00) >> 8;
-			if (pclk >= 165000)
-				*conf |= 0x0100;
-			break;
-		case DCB_OUTPUT_LVDS:
-			*conf = priv->sor.lvdsconf;
-			break;
-		case DCB_OUTPUT_DP:
-			*conf = (ctrl & 0x00000f00) >> 8;
-			break;
-		case DCB_OUTPUT_ANALOG:
-		default:
-			*conf = 0x00ff;
-			break;
-		}
-	} else {
-		*conf = (ctrl & 0x00000f00) >> 8;
-		pclk = pclk / 2;
-	}
-
-	data = nvbios_ocfg_match(bios, data, *conf, &ver, &hdr, &cnt, &len, &info2);
-	if (data && id < 0xff) {
-		data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
-		if (data) {
-			struct nvbios_init init = {
-				.subdev = nv_subdev(priv),
-				.bios = bios,
-				.offset = data,
-				.outp = &outp->info,
-				.crtc = head,
-				.execute = 1,
-			};
-
-			nvbios_exec(&init);
-		}
-	}
-
-	return outp;
-}
-
-static void
-nv50_disp_intr_unk10_0(struct nv50_disp_priv *priv, int head)
-{
-	exec_script(priv, head, 1);
-}
-
-static void
-nv50_disp_intr_unk20_0(struct nv50_disp_priv *priv, int head)
-{
-	struct nvkm_output *outp = exec_script(priv, head, 2);
-
-	/* the binary driver does this outside of the supervisor handling
-	 * (after the third supervisor from a detach).  we (currently?)
-	 * allow both detach/attach to happen in the same set of
-	 * supervisor interrupts, so it would make sense to execute this
-	 * (full power down?) script after all the detach phases of the
-	 * supervisor handling.  like with training if needed from the
-	 * second supervisor, nvidia doesn't do this, so who knows if it's
-	 * entirely safe, but it does appear to work..
-	 *
-	 * without this script being run, on some configurations i've
-	 * seen, switching from DP to TMDS on a DP connector may result
-	 * in a blank screen (SOR_PWR off/on can restore it)
-	 */
-	if (outp && outp->info.type == DCB_OUTPUT_DP) {
-		struct nvkm_output_dp *outpdp = (void *)outp;
-		struct nvbios_init init = {
-			.subdev = nv_subdev(priv),
-			.bios = nouveau_bios(priv),
-			.outp = &outp->info,
-			.crtc = head,
-			.offset = outpdp->info.script[4],
-			.execute = 1,
-		};
-
-		nvbios_exec(&init);
-		atomic_set(&outpdp->lt.done, 0);
-	}
-}
-
-static void
-nv50_disp_intr_unk20_1(struct nv50_disp_priv *priv, int head)
-{
-	struct nouveau_devinit *devinit = nouveau_devinit(priv);
-	u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
-	if (pclk)
-		devinit->pll_set(devinit, PLL_VPLL0 + head, pclk);
-}
-
-static void
-nv50_disp_intr_unk20_2_dp(struct nv50_disp_priv *priv, int head,
-			  struct dcb_output *outp, u32 pclk)
-{
-	const int link = !(outp->sorconf.link & 1);
-	const int   or = ffs(outp->or) - 1;
-	const u32 soff = (  or * 0x800);
-	const u32 loff = (link * 0x080) + soff;
-	const u32 ctrl = nv_rd32(priv, 0x610794 + (or * 8));
-	const u32 symbol = 100000;
-	const s32 vactive = nv_rd32(priv, 0x610af8 + (head * 0x540)) & 0xffff;
-	const s32 vblanke = nv_rd32(priv, 0x610ae8 + (head * 0x540)) & 0xffff;
-	const s32 vblanks = nv_rd32(priv, 0x610af0 + (head * 0x540)) & 0xffff;
-	u32 dpctrl = nv_rd32(priv, 0x61c10c + loff);
-	u32 clksor = nv_rd32(priv, 0x614300 + soff);
-	int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
-	int TU, VTUi, VTUf, VTUa;
-	u64 link_data_rate, link_ratio, unk;
-	u32 best_diff = 64 * symbol;
-	u32 link_nr, link_bw, bits;
-	u64 value;
-
-	link_bw = (clksor & 0x000c0000) ? 270000 : 162000;
-	link_nr = hweight32(dpctrl & 0x000f0000);
-
-	/* symbols/hblank - algorithm taken from comments in tegra driver */
-	value = vblanke + vactive - vblanks - 7;
-	value = value * link_bw;
-	do_div(value, pclk);
-	value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr);
-	nv_mask(priv, 0x61c1e8 + soff, 0x0000ffff, value);
-
-	/* symbols/vblank - algorithm taken from comments in tegra driver */
-	value = vblanks - vblanke - 25;
-	value = value * link_bw;
-	do_div(value, pclk);
-	value = value - ((36 / link_nr) + 3) - 1;
-	nv_mask(priv, 0x61c1ec + soff, 0x00ffffff, value);
-
-	/* watermark / activesym */
-	if      ((ctrl & 0xf0000) == 0x60000) bits = 30;
-	else if ((ctrl & 0xf0000) == 0x50000) bits = 24;
-	else                                  bits = 18;
-
-	link_data_rate = (pclk * bits / 8) / link_nr;
-
-	/* calculate ratio of packed data rate to link symbol rate */
-	link_ratio = link_data_rate * symbol;
-	do_div(link_ratio, link_bw);
-
-	for (TU = 64; TU >= 32; TU--) {
-		/* calculate average number of valid symbols in each TU */
-		u32 tu_valid = link_ratio * TU;
-		u32 calc, diff;
-
-		/* find a hw representation for the fraction.. */
-		VTUi = tu_valid / symbol;
-		calc = VTUi * symbol;
-		diff = tu_valid - calc;
-		if (diff) {
-			if (diff >= (symbol / 2)) {
-				VTUf = symbol / (symbol - diff);
-				if (symbol - (VTUf * diff))
-					VTUf++;
-
-				if (VTUf <= 15) {
-					VTUa  = 1;
-					calc += symbol - (symbol / VTUf);
-				} else {
-					VTUa  = 0;
-					VTUf  = 1;
-					calc += symbol;
-				}
-			} else {
-				VTUa  = 0;
-				VTUf  = min((int)(symbol / diff), 15);
-				calc += symbol / VTUf;
-			}
-
-			diff = calc - tu_valid;
-		} else {
-			/* no remainder, but the hw doesn't like the fractional
-			 * part to be zero.  decrement the integer part and
-			 * have the fraction add a whole symbol back
-			 */
-			VTUa = 0;
-			VTUf = 1;
-			VTUi--;
-		}
-
-		if (diff < best_diff) {
-			best_diff = diff;
-			bestTU = TU;
-			bestVTUa = VTUa;
-			bestVTUf = VTUf;
-			bestVTUi = VTUi;
-			if (diff == 0)
-				break;
-		}
-	}
-
-	if (!bestTU) {
-		nv_error(priv, "unable to find suitable dp config\n");
-		return;
-	}
-
-	/* XXX close to vbios numbers, but not right */
-	unk  = (symbol - link_ratio) * bestTU;
-	unk *= link_ratio;
-	do_div(unk, symbol);
-	do_div(unk, symbol);
-	unk += 6;
-
-	nv_mask(priv, 0x61c10c + loff, 0x000001fc, bestTU << 2);
-	nv_mask(priv, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 |
-						   bestVTUf << 16 |
-						   bestVTUi << 8 | unk);
-}
-
-static void
-nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
-{
-	struct nvkm_output *outp;
-	u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
-	u32 hval, hreg = 0x614200 + (head * 0x800);
-	u32 oval, oreg;
-	u32 mask, conf;
-
-	outp = exec_clkcmp(priv, head, 0xff, pclk, &conf);
-	if (!outp)
-		return;
-
-	/* we allow both encoder attach and detach operations to occur
-	 * within a single supervisor (ie. modeset) sequence.  the
-	 * encoder detach scripts quite often switch off power to the
-	 * lanes, which requires the link to be re-trained.
-	 *
-	 * this is not generally an issue as the sink "must" (heh)
-	 * signal an irq when it's lost sync so the driver can
-	 * re-train.
-	 *
-	 * however, on some boards, if one does not configure at least
-	 * the gpu side of the link *before* attaching, then various
-	 * things can go horribly wrong (PDISP disappearing from mmio,
-	 * third supervisor never happens, etc).
-	 *
-	 * the solution is simply to retrain here, if necessary.  last
-	 * i checked, the binary driver userspace does not appear to
-	 * trigger this situation (it forces an UPDATE between steps).
-	 */
-	if (outp->info.type == DCB_OUTPUT_DP) {
-		u32 soff = (ffs(outp->info.or) - 1) * 0x08;
-		u32 ctrl, datarate;
-
-		if (outp->info.location == 0) {
-			ctrl = nv_rd32(priv, 0x610794 + soff);
-			soff = 1;
-		} else {
-			ctrl = nv_rd32(priv, 0x610b80 + soff);
-			soff = 2;
-		}
-
-		switch ((ctrl & 0x000f0000) >> 16) {
-		case 6: datarate = pclk * 30; break;
-		case 5: datarate = pclk * 24; break;
-		case 2:
-		default:
-			datarate = pclk * 18;
-			break;
-		}
-
-		if (nvkm_output_dp_train(outp, datarate / soff, true))
-			ERR("link not trained before attach\n");
-	}
-
-	exec_clkcmp(priv, head, 0, pclk, &conf);
-
-	if (!outp->info.location && outp->info.type == DCB_OUTPUT_ANALOG) {
-		oreg = 0x614280 + (ffs(outp->info.or) - 1) * 0x800;
-		oval = 0x00000000;
-		hval = 0x00000000;
-		mask = 0xffffffff;
-	} else
-	if (!outp->info.location) {
-		if (outp->info.type == DCB_OUTPUT_DP)
-			nv50_disp_intr_unk20_2_dp(priv, head, &outp->info, pclk);
-		oreg = 0x614300 + (ffs(outp->info.or) - 1) * 0x800;
-		oval = (conf & 0x0100) ? 0x00000101 : 0x00000000;
-		hval = 0x00000000;
-		mask = 0x00000707;
-	} else {
-		oreg = 0x614380 + (ffs(outp->info.or) - 1) * 0x800;
-		oval = 0x00000001;
-		hval = 0x00000001;
-		mask = 0x00000707;
-	}
-
-	nv_mask(priv, hreg, 0x0000000f, hval);
-	nv_mask(priv, oreg, mask, oval);
-}
-
-/* If programming a TMDS output on a SOR that can also be configured for
- * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
- *
- * It looks like the VBIOS TMDS scripts make an attempt at this, however,
- * the VBIOS scripts on at least one board I have only switch it off on
- * link 0, causing a blank display if the output has previously been
- * programmed for DisplayPort.
- */
-static void
-nv50_disp_intr_unk40_0_tmds(struct nv50_disp_priv *priv, struct dcb_output *outp)
-{
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	const int link = !(outp->sorconf.link & 1);
-	const int   or = ffs(outp->or) - 1;
-	const u32 loff = (or * 0x800) + (link * 0x80);
-	const u16 mask = (outp->sorconf.link << 6) | outp->or;
-	struct dcb_output match;
-	u8  ver, hdr;
-
-	if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, &match))
-		nv_mask(priv, 0x61c10c + loff, 0x00000001, 0x00000000);
-}
-
-static void
-nv50_disp_intr_unk40_0(struct nv50_disp_priv *priv, int head)
-{
-	struct nvkm_output *outp;
-	u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
-	u32 conf;
-
-	outp = exec_clkcmp(priv, head, 1, pclk, &conf);
-	if (!outp)
-		return;
-
-	if (outp->info.location == 0 && outp->info.type == DCB_OUTPUT_TMDS)
-		nv50_disp_intr_unk40_0_tmds(priv, &outp->info);
-}
-
-void
-nv50_disp_intr_supervisor(struct work_struct *work)
-{
-	struct nv50_disp_priv *priv =
-		container_of(work, struct nv50_disp_priv, supervisor);
-	struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass;
-	u32 super = nv_rd32(priv, 0x610030);
-	int head;
-
-	nv_debug(priv, "supervisor 0x%08x 0x%08x\n", priv->super, super);
-
-	if (priv->super & 0x00000010) {
-		nv50_disp_mthd_chan(priv, NV_DBG_DEBUG, 0, impl->mthd.core);
-		for (head = 0; head < priv->head.nr; head++) {
-			if (!(super & (0x00000020 << head)))
-				continue;
-			if (!(super & (0x00000080 << head)))
-				continue;
-			nv50_disp_intr_unk10_0(priv, head);
-		}
-	} else
-	if (priv->super & 0x00000020) {
-		for (head = 0; head < priv->head.nr; head++) {
-			if (!(super & (0x00000080 << head)))
-				continue;
-			nv50_disp_intr_unk20_0(priv, head);
-		}
-		for (head = 0; head < priv->head.nr; head++) {
-			if (!(super & (0x00000200 << head)))
-				continue;
-			nv50_disp_intr_unk20_1(priv, head);
-		}
-		for (head = 0; head < priv->head.nr; head++) {
-			if (!(super & (0x00000080 << head)))
-				continue;
-			nv50_disp_intr_unk20_2(priv, head);
-		}
-	} else
-	if (priv->super & 0x00000040) {
-		for (head = 0; head < priv->head.nr; head++) {
-			if (!(super & (0x00000080 << head)))
-				continue;
-			nv50_disp_intr_unk40_0(priv, head);
-		}
-	}
-
-	nv_wr32(priv, 0x610030, 0x80000000);
-}
-
-void
-nv50_disp_intr(struct nouveau_subdev *subdev)
-{
-	struct nv50_disp_priv *priv = (void *)subdev;
-	u32 intr0 = nv_rd32(priv, 0x610020);
-	u32 intr1 = nv_rd32(priv, 0x610024);
-
-	while (intr0 & 0x001f0000) {
-		u32 chid = __ffs(intr0 & 0x001f0000) - 16;
-		nv50_disp_intr_error(priv, chid);
-		intr0 &= ~(0x00010000 << chid);
-	}
-
-	while (intr0 & 0x0000001f) {
-		u32 chid = __ffs(intr0 & 0x0000001f);
-		nv50_disp_chan_uevent_send(priv, chid);
-		intr0 &= ~(0x00000001 << chid);
-	}
-
-	if (intr1 & 0x00000004) {
-		nouveau_disp_vblank(&priv->base, 0);
-		nv_wr32(priv, 0x610024, 0x00000004);
-		intr1 &= ~0x00000004;
-	}
-
-	if (intr1 & 0x00000008) {
-		nouveau_disp_vblank(&priv->base, 1);
-		nv_wr32(priv, 0x610024, 0x00000008);
-		intr1 &= ~0x00000008;
-	}
-
-	if (intr1 & 0x00000070) {
-		priv->super = (intr1 & 0x00000070);
-		schedule_work(&priv->supervisor);
-		nv_wr32(priv, 0x610024, priv->super);
-		intr1 &= ~0x00000070;
-	}
-}
-
-static int
-nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv50_disp_priv *priv;
-	int ret;
-
-	ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
-				  "display", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
-	if (ret)
-		return ret;
-
-	nv_engine(priv)->sclass = nv50_disp_main_oclass;
-	nv_engine(priv)->cclass = &nv50_disp_cclass;
-	nv_subdev(priv)->intr = nv50_disp_intr;
-	INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
-	priv->sclass = nv50_disp_sclass;
-	priv->head.nr = 2;
-	priv->dac.nr = 3;
-	priv->sor.nr = 2;
-	priv->pior.nr = 3;
-	priv->dac.power = nv50_dac_power;
-	priv->dac.sense = nv50_dac_sense;
-	priv->sor.power = nv50_sor_power;
-	priv->pior.power = nv50_pior_power;
-	return 0;
-}
-
-struct nouveau_oclass *
-nv50_disp_outp_sclass[] = {
-	&nv50_pior_dp_impl.base.base,
-	NULL
-};
-
-struct nouveau_oclass *
-nv50_disp_oclass = &(struct nv50_disp_impl) {
-	.base.base.handle = NV_ENGINE(DISP, 0x50),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
-	},
-	.base.vblank = &nv50_disp_vblank_func,
-	.base.outp =  nv50_disp_outp_sclass,
-	.mthd.core = &nv50_disp_core_mthd_chan,
-	.mthd.base = &nv50_disp_base_mthd_chan,
-	.mthd.ovly = &nv50_disp_ovly_mthd_chan,
-	.mthd.prev = 0x000004,
-	.head.scanoutpos = nv50_disp_main_scanoutpos,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
deleted file mode 100644
index 7f08078ee925..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
+++ /dev/null
@@ -1,252 +0,0 @@
-#ifndef __NV50_DISP_H__
-#define __NV50_DISP_H__
-
-#include <core/parent.h>
-#include <core/namedb.h>
-#include <core/engctx.h>
-#include <core/ramht.h>
-#include <core/event.h>
-
-#include <engine/dmaobj.h>
-
-#include "dport.h"
-#include "priv.h"
-#include "outp.h"
-#include "outpdp.h"
-
-#define NV50_DISP_MTHD_ struct nouveau_object *object,                         \
-	struct nv50_disp_priv *priv, void *data, u32 size
-#define NV50_DISP_MTHD_V0 NV50_DISP_MTHD_, int head
-#define NV50_DISP_MTHD_V1 NV50_DISP_MTHD_, int head, struct nvkm_output *outp
-
-struct nv50_disp_priv {
-	struct nouveau_disp base;
-	struct nouveau_oclass *sclass;
-
-	struct work_struct supervisor;
-	u32 super;
-
-	struct nvkm_event uevent;
-
-	struct {
-		int nr;
-	} head;
-	struct {
-		int nr;
-		int (*power)(NV50_DISP_MTHD_V1);
-		int (*sense)(NV50_DISP_MTHD_V1);
-	} dac;
-	struct {
-		int nr;
-		int (*power)(NV50_DISP_MTHD_V1);
-		int (*hda_eld)(NV50_DISP_MTHD_V1);
-		int (*hdmi)(NV50_DISP_MTHD_V1);
-		u32 lvdsconf;
-		void (*magic)(struct nvkm_output *);
-	} sor;
-	struct {
-		int nr;
-		int (*power)(NV50_DISP_MTHD_V1);
-		u8 type[3];
-	} pior;
-};
-
-struct nv50_disp_impl {
-	struct nouveau_disp_impl base;
-	struct {
-		const struct nv50_disp_mthd_chan *core;
-		const struct nv50_disp_mthd_chan *base;
-		const struct nv50_disp_mthd_chan *ovly;
-		int prev;
-	} mthd;
-	struct {
-		int (*scanoutpos)(NV50_DISP_MTHD_V0);
-	} head;
-};
-
-int nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0);
-int nv50_disp_main_mthd(struct nouveau_object *, u32, void *, u32);
-
-int nvd0_disp_main_scanoutpos(NV50_DISP_MTHD_V0);
-
-int nv50_dac_power(NV50_DISP_MTHD_V1);
-int nv50_dac_sense(NV50_DISP_MTHD_V1);
-
-int nva3_hda_eld(NV50_DISP_MTHD_V1);
-int nvd0_hda_eld(NV50_DISP_MTHD_V1);
-
-int nv84_hdmi_ctrl(NV50_DISP_MTHD_V1);
-int nva3_hdmi_ctrl(NV50_DISP_MTHD_V1);
-int nvd0_hdmi_ctrl(NV50_DISP_MTHD_V1);
-int nve0_hdmi_ctrl(NV50_DISP_MTHD_V1);
-
-int nv50_sor_power(NV50_DISP_MTHD_V1);
-
-int nv94_sor_dp_train_init(struct nv50_disp_priv *, int, int, int, u16, u16,
-		           u32, struct dcb_output *);
-int nv94_sor_dp_train_fini(struct nv50_disp_priv *, int, int, int, u16, u16,
-		           u32, struct dcb_output *);
-int nv94_sor_dp_train(struct nv50_disp_priv *, int, int, u16, u16, u32,
-		      struct dcb_output *);
-int nv94_sor_dp_lnkctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32,
-		       struct dcb_output *);
-int nv94_sor_dp_drvctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32,
-		       struct dcb_output *);
-
-int nvd0_sor_dp_train(struct nv50_disp_priv *, int, int, u16, u16, u32,
-		      struct dcb_output *);
-int nvd0_sor_dp_lnkctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32,
-		       struct dcb_output *);
-int nvd0_sor_dp_drvctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32,
-		       struct dcb_output *);
-
-int nv50_pior_power(NV50_DISP_MTHD_V1);
-
-struct nv50_disp_base {
-	struct nouveau_parent base;
-	struct nouveau_ramht *ramht;
-	u32 chan;
-};
-
-struct nv50_disp_chan_impl {
-	struct nouveau_ofuncs base;
-	int chid;
-	int  (*attach)(struct nouveau_object *, struct nouveau_object *, u32);
-	void (*detach)(struct nouveau_object *, int);
-};
-
-struct nv50_disp_chan {
-	struct nouveau_namedb base;
-	int chid;
-};
-
-int  nv50_disp_chan_ntfy(struct nouveau_object *, u32, struct nvkm_event **);
-int  nv50_disp_chan_map(struct nouveau_object *, u64 *, u32 *);
-u32  nv50_disp_chan_rd32(struct nouveau_object *, u64);
-void nv50_disp_chan_wr32(struct nouveau_object *, u64, u32);
-extern const struct nvkm_event_func nv50_disp_chan_uevent;
-int  nv50_disp_chan_uevent_ctor(struct nouveau_object *, void *, u32,
-				struct nvkm_notify *);
-void nv50_disp_chan_uevent_send(struct nv50_disp_priv *, int);
-
-extern const struct nvkm_event_func nvd0_disp_chan_uevent;
-
-#define nv50_disp_chan_init(a)                                                 \
-	nouveau_namedb_init(&(a)->base)
-#define nv50_disp_chan_fini(a,b)                                               \
-	nouveau_namedb_fini(&(a)->base, (b))
-
-struct nv50_disp_dmac {
-	struct nv50_disp_chan base;
-	struct nouveau_dmaobj *pushdma;
-	u32 push;
-};
-
-void nv50_disp_dmac_dtor(struct nouveau_object *);
-
-struct nv50_disp_pioc {
-	struct nv50_disp_chan base;
-};
-
-void nv50_disp_pioc_dtor(struct nouveau_object *);
-
-struct nv50_disp_mthd_list {
-	u32 mthd;
-	u32 addr;
-	struct {
-		u32 mthd;
-		u32 addr;
-		const char *name;
-	} data[];
-};
-
-struct nv50_disp_mthd_chan {
-	const char *name;
-	u32 addr;
-	struct {
-		const char *name;
-		int nr;
-		const struct nv50_disp_mthd_list *mthd;
-	} data[];
-};
-
-extern struct nv50_disp_chan_impl nv50_disp_core_ofuncs;
-int nv50_disp_core_ctor(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, void *, u32,
-			struct nouveau_object **);
-extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_base;
-extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_sor;
-extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_pior;
-extern struct nv50_disp_chan_impl nv50_disp_base_ofuncs;
-int nv50_disp_base_ctor(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, void *, u32,
-			struct nouveau_object **);
-extern const struct nv50_disp_mthd_list nv50_disp_base_mthd_image;
-extern struct nv50_disp_chan_impl nv50_disp_ovly_ofuncs;
-int nv50_disp_ovly_ctor(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, void *, u32,
-			struct nouveau_object **);
-extern const struct nv50_disp_mthd_list nv50_disp_ovly_mthd_base;
-extern struct nv50_disp_chan_impl nv50_disp_oimm_ofuncs;
-int nv50_disp_oimm_ctor(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, void *, u32,
-			struct nouveau_object **);
-extern struct nv50_disp_chan_impl nv50_disp_curs_ofuncs;
-int nv50_disp_curs_ctor(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, void *, u32,
-			struct nouveau_object **);
-extern struct nouveau_ofuncs nv50_disp_main_ofuncs;
-int  nv50_disp_main_ctor(struct nouveau_object *, struct nouveau_object *,
-			 struct nouveau_oclass *, void *, u32,
-			 struct nouveau_object **);
-void nv50_disp_main_dtor(struct nouveau_object *);
-extern struct nouveau_omthds nv50_disp_main_omthds[];
-extern struct nouveau_oclass nv50_disp_cclass;
-void nv50_disp_mthd_chan(struct nv50_disp_priv *, int debug, int head,
-			 const struct nv50_disp_mthd_chan *);
-void nv50_disp_intr_supervisor(struct work_struct *);
-void nv50_disp_intr(struct nouveau_subdev *);
-extern const struct nvkm_event_func nv50_disp_vblank_func;
-
-extern const struct nv50_disp_mthd_chan nv84_disp_core_mthd_chan;
-extern const struct nv50_disp_mthd_list nv84_disp_core_mthd_dac;
-extern const struct nv50_disp_mthd_list nv84_disp_core_mthd_head;
-extern const struct nv50_disp_mthd_chan nv84_disp_base_mthd_chan;
-extern const struct nv50_disp_mthd_chan nv84_disp_ovly_mthd_chan;
-
-extern const struct nv50_disp_mthd_chan nv94_disp_core_mthd_chan;
-
-extern struct nv50_disp_chan_impl nvd0_disp_core_ofuncs;
-extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_base;
-extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_dac;
-extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_sor;
-extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_pior;
-extern struct nv50_disp_chan_impl nvd0_disp_base_ofuncs;
-extern struct nv50_disp_chan_impl nvd0_disp_ovly_ofuncs;
-extern const struct nv50_disp_mthd_chan nvd0_disp_base_mthd_chan;
-extern struct nv50_disp_chan_impl nvd0_disp_oimm_ofuncs;
-extern struct nv50_disp_chan_impl nvd0_disp_curs_ofuncs;
-extern struct nouveau_ofuncs nvd0_disp_main_ofuncs;
-extern struct nouveau_oclass nvd0_disp_cclass;
-void nvd0_disp_intr_supervisor(struct work_struct *);
-void nvd0_disp_intr(struct nouveau_subdev *);
-extern const struct nvkm_event_func nvd0_disp_vblank_func;
-
-extern const struct nv50_disp_mthd_chan nve0_disp_core_mthd_chan;
-extern const struct nv50_disp_mthd_chan nve0_disp_ovly_mthd_chan;
-
-extern struct nvkm_output_dp_impl nv50_pior_dp_impl;
-extern struct nouveau_oclass *nv50_disp_outp_sclass[];
-
-extern struct nvkm_output_dp_impl nv94_sor_dp_impl;
-int nv94_sor_dp_lnk_pwr(struct nvkm_output_dp *, int);
-extern struct nouveau_oclass *nv94_disp_outp_sclass[];
-
-extern struct nvkm_output_dp_impl nvd0_sor_dp_impl;
-int nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *, int, int, bool);
-extern struct nouveau_oclass *nvd0_disp_outp_sclass[];
-
-void gm204_sor_magic(struct nvkm_output *outp);
-extern struct nvkm_output_dp_impl gm204_sor_dp_impl;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
deleted file mode 100644
index 13eff5e4ee51..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
+++ /dev/null
@@ -1,276 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <engine/software.h>
-#include <engine/disp.h>
-
-#include <nvif/class.h>
-
-#include "nv50.h"
-
-/*******************************************************************************
- * EVO master channel object
- ******************************************************************************/
-
-const struct nv50_disp_mthd_list
-nv84_disp_core_mthd_dac = {
-	.mthd = 0x0080,
-	.addr = 0x000008,
-	.data = {
-		{ 0x0400, 0x610b58 },
-		{ 0x0404, 0x610bdc },
-		{ 0x0420, 0x610bc4 },
-		{}
-	}
-};
-
-const struct nv50_disp_mthd_list
-nv84_disp_core_mthd_head = {
-	.mthd = 0x0400,
-	.addr = 0x000540,
-	.data = {
-		{ 0x0800, 0x610ad8 },
-		{ 0x0804, 0x610ad0 },
-		{ 0x0808, 0x610a48 },
-		{ 0x080c, 0x610a78 },
-		{ 0x0810, 0x610ac0 },
-		{ 0x0814, 0x610af8 },
-		{ 0x0818, 0x610b00 },
-		{ 0x081c, 0x610ae8 },
-		{ 0x0820, 0x610af0 },
-		{ 0x0824, 0x610b08 },
-		{ 0x0828, 0x610b10 },
-		{ 0x082c, 0x610a68 },
-		{ 0x0830, 0x610a60 },
-		{ 0x0834, 0x000000 },
-		{ 0x0838, 0x610a40 },
-		{ 0x0840, 0x610a24 },
-		{ 0x0844, 0x610a2c },
-		{ 0x0848, 0x610aa8 },
-		{ 0x084c, 0x610ab0 },
-		{ 0x085c, 0x610c5c },
-		{ 0x0860, 0x610a84 },
-		{ 0x0864, 0x610a90 },
-		{ 0x0868, 0x610b18 },
-		{ 0x086c, 0x610b20 },
-		{ 0x0870, 0x610ac8 },
-		{ 0x0874, 0x610a38 },
-		{ 0x0878, 0x610c50 },
-		{ 0x0880, 0x610a58 },
-		{ 0x0884, 0x610a9c },
-		{ 0x089c, 0x610c68 },
-		{ 0x08a0, 0x610a70 },
-		{ 0x08a4, 0x610a50 },
-		{ 0x08a8, 0x610ae0 },
-		{ 0x08c0, 0x610b28 },
-		{ 0x08c4, 0x610b30 },
-		{ 0x08c8, 0x610b40 },
-		{ 0x08d4, 0x610b38 },
-		{ 0x08d8, 0x610b48 },
-		{ 0x08dc, 0x610b50 },
-		{ 0x0900, 0x610a18 },
-		{ 0x0904, 0x610ab8 },
-		{ 0x0910, 0x610c70 },
-		{ 0x0914, 0x610c78 },
-		{}
-	}
-};
-
-const struct nv50_disp_mthd_chan
-nv84_disp_core_mthd_chan = {
-	.name = "Core",
-	.addr = 0x000000,
-	.data = {
-		{ "Global", 1, &nv50_disp_core_mthd_base },
-		{    "DAC", 3, &nv84_disp_core_mthd_dac  },
-		{    "SOR", 2, &nv50_disp_core_mthd_sor  },
-		{   "PIOR", 3, &nv50_disp_core_mthd_pior },
-		{   "HEAD", 2, &nv84_disp_core_mthd_head },
-		{}
-	}
-};
-
-/*******************************************************************************
- * EVO sync channel objects
- ******************************************************************************/
-
-static const struct nv50_disp_mthd_list
-nv84_disp_base_mthd_base = {
-	.mthd = 0x0000,
-	.addr = 0x000000,
-	.data = {
-		{ 0x0080, 0x000000 },
-		{ 0x0084, 0x0008c4 },
-		{ 0x0088, 0x0008d0 },
-		{ 0x008c, 0x0008dc },
-		{ 0x0090, 0x0008e4 },
-		{ 0x0094, 0x610884 },
-		{ 0x00a0, 0x6108a0 },
-		{ 0x00a4, 0x610878 },
-		{ 0x00c0, 0x61086c },
-		{ 0x00c4, 0x610800 },
-		{ 0x00c8, 0x61080c },
-		{ 0x00cc, 0x610818 },
-		{ 0x00e0, 0x610858 },
-		{ 0x00e4, 0x610860 },
-		{ 0x00e8, 0x6108ac },
-		{ 0x00ec, 0x6108b4 },
-		{ 0x00fc, 0x610824 },
-		{ 0x0100, 0x610894 },
-		{ 0x0104, 0x61082c },
-		{ 0x0110, 0x6108bc },
-		{ 0x0114, 0x61088c },
-		{}
-	}
-};
-
-const struct nv50_disp_mthd_chan
-nv84_disp_base_mthd_chan = {
-	.name = "Base",
-	.addr = 0x000540,
-	.data = {
-		{ "Global", 1, &nv84_disp_base_mthd_base },
-		{  "Image", 2, &nv50_disp_base_mthd_image },
-		{}
-	}
-};
-
-/*******************************************************************************
- * EVO overlay channel objects
- ******************************************************************************/
-
-static const struct nv50_disp_mthd_list
-nv84_disp_ovly_mthd_base = {
-	.mthd = 0x0000,
-	.addr = 0x000000,
-	.data = {
-		{ 0x0080, 0x000000 },
-		{ 0x0084, 0x6109a0 },
-		{ 0x0088, 0x6109c0 },
-		{ 0x008c, 0x6109c8 },
-		{ 0x0090, 0x6109b4 },
-		{ 0x0094, 0x610970 },
-		{ 0x00a0, 0x610998 },
-		{ 0x00a4, 0x610964 },
-		{ 0x00c0, 0x610958 },
-		{ 0x00e0, 0x6109a8 },
-		{ 0x00e4, 0x6109d0 },
-		{ 0x00e8, 0x6109d8 },
-		{ 0x0100, 0x61094c },
-		{ 0x0104, 0x610984 },
-		{ 0x0108, 0x61098c },
-		{ 0x0800, 0x6109f8 },
-		{ 0x0808, 0x610a08 },
-		{ 0x080c, 0x610a10 },
-		{ 0x0810, 0x610a00 },
-		{}
-	}
-};
-
-const struct nv50_disp_mthd_chan
-nv84_disp_ovly_mthd_chan = {
-	.name = "Overlay",
-	.addr = 0x000540,
-	.data = {
-		{ "Global", 1, &nv84_disp_ovly_mthd_base },
-		{}
-	}
-};
-
-/*******************************************************************************
- * Base display object
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv84_disp_sclass[] = {
-	{ G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
-	{ G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
-	{ G82_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
-	{ G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
-	{ G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
-	{}
-};
-
-static struct nouveau_oclass
-nv84_disp_main_oclass[] = {
-	{ G82_DISP, &nv50_disp_main_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * Display engine implementation
- ******************************************************************************/
-
-static int
-nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv50_disp_priv *priv;
-	int ret;
-
-	ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
-				  "display", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
-	if (ret)
-		return ret;
-
-	nv_engine(priv)->sclass = nv84_disp_main_oclass;
-	nv_engine(priv)->cclass = &nv50_disp_cclass;
-	nv_subdev(priv)->intr = nv50_disp_intr;
-	INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
-	priv->sclass = nv84_disp_sclass;
-	priv->head.nr = 2;
-	priv->dac.nr = 3;
-	priv->sor.nr = 2;
-	priv->pior.nr = 3;
-	priv->dac.power = nv50_dac_power;
-	priv->dac.sense = nv50_dac_sense;
-	priv->sor.power = nv50_sor_power;
-	priv->sor.hdmi = nv84_hdmi_ctrl;
-	priv->pior.power = nv50_pior_power;
-	return 0;
-}
-
-struct nouveau_oclass *
-nv84_disp_oclass = &(struct nv50_disp_impl) {
-	.base.base.handle = NV_ENGINE(DISP, 0x82),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv84_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
-	},
-	.base.vblank = &nv50_disp_vblank_func,
-	.base.outp =  nv50_disp_outp_sclass,
-	.mthd.core = &nv84_disp_core_mthd_chan,
-	.mthd.base = &nv84_disp_base_mthd_chan,
-	.mthd.ovly = &nv84_disp_ovly_mthd_chan,
-	.mthd.prev = 0x000004,
-	.head.scanoutpos = nv50_disp_main_scanoutpos,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
deleted file mode 100644
index 2bb7ac5cd0e6..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <engine/software.h>
-#include <engine/disp.h>
-
-#include <nvif/class.h>
-
-#include "nv50.h"
-
-/*******************************************************************************
- * EVO master channel object
- ******************************************************************************/
-
-const struct nv50_disp_mthd_list
-nv94_disp_core_mthd_sor = {
-	.mthd = 0x0040,
-	.addr = 0x000008,
-	.data = {
-		{ 0x0600, 0x610794 },
-		{}
-	}
-};
-
-const struct nv50_disp_mthd_chan
-nv94_disp_core_mthd_chan = {
-	.name = "Core",
-	.addr = 0x000000,
-	.data = {
-		{ "Global", 1, &nv50_disp_core_mthd_base },
-		{    "DAC", 3, &nv84_disp_core_mthd_dac  },
-		{    "SOR", 4, &nv94_disp_core_mthd_sor  },
-		{   "PIOR", 3, &nv50_disp_core_mthd_pior },
-		{   "HEAD", 2, &nv84_disp_core_mthd_head },
-		{}
-	}
-};
-
-/*******************************************************************************
- * Base display object
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv94_disp_sclass[] = {
-	{ GT206_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
-	{ GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
-	{ GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
-	{ G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
-	{ G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
-	{}
-};
-
-static struct nouveau_oclass
-nv94_disp_main_oclass[] = {
-	{ GT206_DISP, &nv50_disp_main_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * Display engine implementation
- ******************************************************************************/
-
-static int
-nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv50_disp_priv *priv;
-	int ret;
-
-	ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
-				  "display", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
-	if (ret)
-		return ret;
-
-	nv_engine(priv)->sclass = nv94_disp_main_oclass;
-	nv_engine(priv)->cclass = &nv50_disp_cclass;
-	nv_subdev(priv)->intr = nv50_disp_intr;
-	INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
-	priv->sclass = nv94_disp_sclass;
-	priv->head.nr = 2;
-	priv->dac.nr = 3;
-	priv->sor.nr = 4;
-	priv->pior.nr = 3;
-	priv->dac.power = nv50_dac_power;
-	priv->dac.sense = nv50_dac_sense;
-	priv->sor.power = nv50_sor_power;
-	priv->sor.hdmi = nv84_hdmi_ctrl;
-	priv->pior.power = nv50_pior_power;
-	return 0;
-}
-
-struct nouveau_oclass *
-nv94_disp_outp_sclass[] = {
-	&nv50_pior_dp_impl.base.base,
-	&nv94_sor_dp_impl.base.base,
-	NULL
-};
-
-struct nouveau_oclass *
-nv94_disp_oclass = &(struct nv50_disp_impl) {
-	.base.base.handle = NV_ENGINE(DISP, 0x88),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv94_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
-	},
-	.base.vblank = &nv50_disp_vblank_func,
-	.base.outp =  nv94_disp_outp_sclass,
-	.mthd.core = &nv94_disp_core_mthd_chan,
-	.mthd.base = &nv84_disp_base_mthd_chan,
-	.mthd.ovly = &nv84_disp_ovly_mthd_chan,
-	.mthd.prev = 0x000004,
-	.head.scanoutpos = nv50_disp_main_scanoutpos,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
deleted file mode 100644
index b32456c9494f..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <engine/software.h>
-#include <engine/disp.h>
-
-#include <nvif/class.h>
-
-#include "nv50.h"
-
-/*******************************************************************************
- * EVO overlay channel objects
- ******************************************************************************/
-
-static const struct nv50_disp_mthd_list
-nva0_disp_ovly_mthd_base = {
-	.mthd = 0x0000,
-	.addr = 0x000000,
-	.data = {
-		{ 0x0080, 0x000000 },
-		{ 0x0084, 0x6109a0 },
-		{ 0x0088, 0x6109c0 },
-		{ 0x008c, 0x6109c8 },
-		{ 0x0090, 0x6109b4 },
-		{ 0x0094, 0x610970 },
-		{ 0x00a0, 0x610998 },
-		{ 0x00a4, 0x610964 },
-		{ 0x00b0, 0x610c98 },
-		{ 0x00b4, 0x610ca4 },
-		{ 0x00b8, 0x610cac },
-		{ 0x00c0, 0x610958 },
-		{ 0x00e0, 0x6109a8 },
-		{ 0x00e4, 0x6109d0 },
-		{ 0x00e8, 0x6109d8 },
-		{ 0x0100, 0x61094c },
-		{ 0x0104, 0x610984 },
-		{ 0x0108, 0x61098c },
-		{ 0x0800, 0x6109f8 },
-		{ 0x0808, 0x610a08 },
-		{ 0x080c, 0x610a10 },
-		{ 0x0810, 0x610a00 },
-		{}
-	}
-};
-
-static const struct nv50_disp_mthd_chan
-nva0_disp_ovly_mthd_chan = {
-	.name = "Overlay",
-	.addr = 0x000540,
-	.data = {
-		{ "Global", 1, &nva0_disp_ovly_mthd_base },
-		{}
-	}
-};
-
-/*******************************************************************************
- * Base display object
- ******************************************************************************/
-
-static struct nouveau_oclass
-nva0_disp_sclass[] = {
-	{ GT200_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
-	{ GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
-	{ GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
-	{ G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
-	{ G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
-	{}
-};
-
-static struct nouveau_oclass
-nva0_disp_main_oclass[] = {
-	{ GT200_DISP, &nv50_disp_main_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * Display engine implementation
- ******************************************************************************/
-
-static int
-nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv50_disp_priv *priv;
-	int ret;
-
-	ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
-				  "display", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
-	if (ret)
-		return ret;
-
-	nv_engine(priv)->sclass = nva0_disp_main_oclass;
-	nv_engine(priv)->cclass = &nv50_disp_cclass;
-	nv_subdev(priv)->intr = nv50_disp_intr;
-	INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
-	priv->sclass = nva0_disp_sclass;
-	priv->head.nr = 2;
-	priv->dac.nr = 3;
-	priv->sor.nr = 2;
-	priv->pior.nr = 3;
-	priv->dac.power = nv50_dac_power;
-	priv->dac.sense = nv50_dac_sense;
-	priv->sor.power = nv50_sor_power;
-	priv->sor.hdmi = nv84_hdmi_ctrl;
-	priv->pior.power = nv50_pior_power;
-	return 0;
-}
-
-struct nouveau_oclass *
-nva0_disp_oclass = &(struct nv50_disp_impl) {
-	.base.base.handle = NV_ENGINE(DISP, 0x83),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nva0_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
-	},
-	.base.vblank = &nv50_disp_vblank_func,
-	.base.outp =  nv50_disp_outp_sclass,
-	.mthd.core = &nv84_disp_core_mthd_chan,
-	.mthd.base = &nv84_disp_base_mthd_chan,
-	.mthd.ovly = &nva0_disp_ovly_mthd_chan,
-	.mthd.prev = 0x000004,
-	.head.scanoutpos = nv50_disp_main_scanoutpos,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
deleted file mode 100644
index 951d79f9b781..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <engine/software.h>
-#include <engine/disp.h>
-
-#include <nvif/class.h>
-
-#include "nv50.h"
-
-/*******************************************************************************
- * Base display object
- ******************************************************************************/
-
-static struct nouveau_oclass
-nva3_disp_sclass[] = {
-	{ GT214_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
-	{ GT214_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
-	{ GT214_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
-	{ GT214_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
-	{ GT214_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
-	{}
-};
-
-static struct nouveau_oclass
-nva3_disp_main_oclass[] = {
-	{ GT214_DISP, &nv50_disp_main_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * Display engine implementation
- ******************************************************************************/
-
-static int
-nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv50_disp_priv *priv;
-	int ret;
-
-	ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
-				  "display", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
-	if (ret)
-		return ret;
-
-	nv_engine(priv)->sclass = nva3_disp_main_oclass;
-	nv_engine(priv)->cclass = &nv50_disp_cclass;
-	nv_subdev(priv)->intr = nv50_disp_intr;
-	INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
-	priv->sclass = nva3_disp_sclass;
-	priv->head.nr = 2;
-	priv->dac.nr = 3;
-	priv->sor.nr = 4;
-	priv->pior.nr = 3;
-	priv->dac.power = nv50_dac_power;
-	priv->dac.sense = nv50_dac_sense;
-	priv->sor.power = nv50_sor_power;
-	priv->sor.hda_eld = nva3_hda_eld;
-	priv->sor.hdmi = nva3_hdmi_ctrl;
-	priv->pior.power = nv50_pior_power;
-	return 0;
-}
-
-struct nouveau_oclass *
-nva3_disp_oclass = &(struct nv50_disp_impl) {
-	.base.base.handle = NV_ENGINE(DISP, 0x85),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nva3_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
-	},
-	.base.vblank = &nv50_disp_vblank_func,
-	.base.outp =  nv94_disp_outp_sclass,
-	.mthd.core = &nv94_disp_core_mthd_chan,
-	.mthd.base = &nv84_disp_base_mthd_chan,
-	.mthd.ovly = &nv84_disp_ovly_mthd_chan,
-	.mthd.prev = 0x000004,
-	.head.scanoutpos = nv50_disp_main_scanoutpos,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
deleted file mode 100644
index 181a2d57e356..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
+++ /dev/null
@@ -1,1313 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/object.h>
-#include <core/client.h>
-#include <core/parent.h>
-#include <core/handle.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <engine/disp.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/disp.h>
-#include <subdev/bios/init.h>
-#include <subdev/bios/pll.h>
-#include <subdev/devinit.h>
-#include <subdev/fb.h>
-#include <subdev/timer.h>
-
-#include "nv50.h"
-
-/*******************************************************************************
- * EVO channel base class
- ******************************************************************************/
-
-static void
-nvd0_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
-{
-	struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
-	nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000000 << index);
-	nv_wr32(priv, 0x61008c, 0x00000001 << index);
-}
-
-static void
-nvd0_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
-{
-	struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
-	nv_wr32(priv, 0x61008c, 0x00000001 << index);
-	nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000001 << index);
-}
-
-const struct nvkm_event_func
-nvd0_disp_chan_uevent = {
-	.ctor = nv50_disp_chan_uevent_ctor,
-	.init = nvd0_disp_chan_uevent_init,
-	.fini = nvd0_disp_chan_uevent_fini,
-};
-
-/*******************************************************************************
- * EVO DMA channel base class
- ******************************************************************************/
-
-static int
-nvd0_disp_dmac_object_attach(struct nouveau_object *parent,
-			     struct nouveau_object *object, u32 name)
-{
-	struct nv50_disp_base *base = (void *)parent->parent;
-	struct nv50_disp_chan *chan = (void *)parent;
-	u32 addr = nv_gpuobj(object)->node->offset;
-	u32 data = (chan->chid << 27) | (addr << 9) | 0x00000001;
-	return nouveau_ramht_insert(base->ramht, chan->chid, name, data);
-}
-
-static void
-nvd0_disp_dmac_object_detach(struct nouveau_object *parent, int cookie)
-{
-	struct nv50_disp_base *base = (void *)parent->parent;
-	nouveau_ramht_remove(base->ramht, cookie);
-}
-
-static int
-nvd0_disp_dmac_init(struct nouveau_object *object)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nv50_disp_dmac *dmac = (void *)object;
-	int chid = dmac->base.chid;
-	int ret;
-
-	ret = nv50_disp_chan_init(&dmac->base);
-	if (ret)
-		return ret;
-
-	/* enable error reporting */
-	nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid);
-
-	/* initialise channel for dma command submission */
-	nv_wr32(priv, 0x610494 + (chid * 0x0010), dmac->push);
-	nv_wr32(priv, 0x610498 + (chid * 0x0010), 0x00010000);
-	nv_wr32(priv, 0x61049c + (chid * 0x0010), 0x00000001);
-	nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00000010, 0x00000010);
-	nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000);
-	nv_wr32(priv, 0x610490 + (chid * 0x0010), 0x00000013);
-
-	/* wait for it to go inactive */
-	if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x80000000, 0x00000000)) {
-		nv_error(dmac, "init: 0x%08x\n",
-			 nv_rd32(priv, 0x610490 + (chid * 0x10)));
-		return -EBUSY;
-	}
-
-	return 0;
-}
-
-static int
-nvd0_disp_dmac_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nv50_disp_dmac *dmac = (void *)object;
-	int chid = dmac->base.chid;
-
-	/* deactivate channel */
-	nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00001010, 0x00001000);
-	nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00000003, 0x00000000);
-	if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x001e0000, 0x00000000)) {
-		nv_error(dmac, "fini: 0x%08x\n",
-			 nv_rd32(priv, 0x610490 + (chid * 0x10)));
-		if (suspend)
-			return -EBUSY;
-	}
-
-	/* disable error reporting and completion notification */
-	nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000);
-	nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000);
-
-	return nv50_disp_chan_fini(&dmac->base, suspend);
-}
-
-/*******************************************************************************
- * EVO master channel object
- ******************************************************************************/
-
-const struct nv50_disp_mthd_list
-nvd0_disp_core_mthd_base = {
-	.mthd = 0x0000,
-	.addr = 0x000000,
-	.data = {
-		{ 0x0080, 0x660080 },
-		{ 0x0084, 0x660084 },
-		{ 0x0088, 0x660088 },
-		{ 0x008c, 0x000000 },
-		{}
-	}
-};
-
-const struct nv50_disp_mthd_list
-nvd0_disp_core_mthd_dac = {
-	.mthd = 0x0020,
-	.addr = 0x000020,
-	.data = {
-		{ 0x0180, 0x660180 },
-		{ 0x0184, 0x660184 },
-		{ 0x0188, 0x660188 },
-		{ 0x0190, 0x660190 },
-		{}
-	}
-};
-
-const struct nv50_disp_mthd_list
-nvd0_disp_core_mthd_sor = {
-	.mthd = 0x0020,
-	.addr = 0x000020,
-	.data = {
-		{ 0x0200, 0x660200 },
-		{ 0x0204, 0x660204 },
-		{ 0x0208, 0x660208 },
-		{ 0x0210, 0x660210 },
-		{}
-	}
-};
-
-const struct nv50_disp_mthd_list
-nvd0_disp_core_mthd_pior = {
-	.mthd = 0x0020,
-	.addr = 0x000020,
-	.data = {
-		{ 0x0300, 0x660300 },
-		{ 0x0304, 0x660304 },
-		{ 0x0308, 0x660308 },
-		{ 0x0310, 0x660310 },
-		{}
-	}
-};
-
-static const struct nv50_disp_mthd_list
-nvd0_disp_core_mthd_head = {
-	.mthd = 0x0300,
-	.addr = 0x000300,
-	.data = {
-		{ 0x0400, 0x660400 },
-		{ 0x0404, 0x660404 },
-		{ 0x0408, 0x660408 },
-		{ 0x040c, 0x66040c },
-		{ 0x0410, 0x660410 },
-		{ 0x0414, 0x660414 },
-		{ 0x0418, 0x660418 },
-		{ 0x041c, 0x66041c },
-		{ 0x0420, 0x660420 },
-		{ 0x0424, 0x660424 },
-		{ 0x0428, 0x660428 },
-		{ 0x042c, 0x66042c },
-		{ 0x0430, 0x660430 },
-		{ 0x0434, 0x660434 },
-		{ 0x0438, 0x660438 },
-		{ 0x0440, 0x660440 },
-		{ 0x0444, 0x660444 },
-		{ 0x0448, 0x660448 },
-		{ 0x044c, 0x66044c },
-		{ 0x0450, 0x660450 },
-		{ 0x0454, 0x660454 },
-		{ 0x0458, 0x660458 },
-		{ 0x045c, 0x66045c },
-		{ 0x0460, 0x660460 },
-		{ 0x0468, 0x660468 },
-		{ 0x046c, 0x66046c },
-		{ 0x0470, 0x660470 },
-		{ 0x0474, 0x660474 },
-		{ 0x0480, 0x660480 },
-		{ 0x0484, 0x660484 },
-		{ 0x048c, 0x66048c },
-		{ 0x0490, 0x660490 },
-		{ 0x0494, 0x660494 },
-		{ 0x0498, 0x660498 },
-		{ 0x04b0, 0x6604b0 },
-		{ 0x04b8, 0x6604b8 },
-		{ 0x04bc, 0x6604bc },
-		{ 0x04c0, 0x6604c0 },
-		{ 0x04c4, 0x6604c4 },
-		{ 0x04c8, 0x6604c8 },
-		{ 0x04d0, 0x6604d0 },
-		{ 0x04d4, 0x6604d4 },
-		{ 0x04e0, 0x6604e0 },
-		{ 0x04e4, 0x6604e4 },
-		{ 0x04e8, 0x6604e8 },
-		{ 0x04ec, 0x6604ec },
-		{ 0x04f0, 0x6604f0 },
-		{ 0x04f4, 0x6604f4 },
-		{ 0x04f8, 0x6604f8 },
-		{ 0x04fc, 0x6604fc },
-		{ 0x0500, 0x660500 },
-		{ 0x0504, 0x660504 },
-		{ 0x0508, 0x660508 },
-		{ 0x050c, 0x66050c },
-		{ 0x0510, 0x660510 },
-		{ 0x0514, 0x660514 },
-		{ 0x0518, 0x660518 },
-		{ 0x051c, 0x66051c },
-		{ 0x052c, 0x66052c },
-		{ 0x0530, 0x660530 },
-		{ 0x054c, 0x66054c },
-		{ 0x0550, 0x660550 },
-		{ 0x0554, 0x660554 },
-		{ 0x0558, 0x660558 },
-		{ 0x055c, 0x66055c },
-		{}
-	}
-};
-
-static const struct nv50_disp_mthd_chan
-nvd0_disp_core_mthd_chan = {
-	.name = "Core",
-	.addr = 0x000000,
-	.data = {
-		{ "Global", 1, &nvd0_disp_core_mthd_base },
-		{    "DAC", 3, &nvd0_disp_core_mthd_dac  },
-		{    "SOR", 8, &nvd0_disp_core_mthd_sor  },
-		{   "PIOR", 4, &nvd0_disp_core_mthd_pior },
-		{   "HEAD", 4, &nvd0_disp_core_mthd_head },
-		{}
-	}
-};
-
-static int
-nvd0_disp_core_init(struct nouveau_object *object)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nv50_disp_dmac *mast = (void *)object;
-	int ret;
-
-	ret = nv50_disp_chan_init(&mast->base);
-	if (ret)
-		return ret;
-
-	/* enable error reporting */
-	nv_mask(priv, 0x6100a0, 0x00000001, 0x00000001);
-
-	/* initialise channel for dma command submission */
-	nv_wr32(priv, 0x610494, mast->push);
-	nv_wr32(priv, 0x610498, 0x00010000);
-	nv_wr32(priv, 0x61049c, 0x00000001);
-	nv_mask(priv, 0x610490, 0x00000010, 0x00000010);
-	nv_wr32(priv, 0x640000, 0x00000000);
-	nv_wr32(priv, 0x610490, 0x01000013);
-
-	/* wait for it to go inactive */
-	if (!nv_wait(priv, 0x610490, 0x80000000, 0x00000000)) {
-		nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610490));
-		return -EBUSY;
-	}
-
-	return 0;
-}
-
-static int
-nvd0_disp_core_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nv50_disp_dmac *mast = (void *)object;
-
-	/* deactivate channel */
-	nv_mask(priv, 0x610490, 0x00000010, 0x00000000);
-	nv_mask(priv, 0x610490, 0x00000003, 0x00000000);
-	if (!nv_wait(priv, 0x610490, 0x001e0000, 0x00000000)) {
-		nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610490));
-		if (suspend)
-			return -EBUSY;
-	}
-
-	/* disable error reporting and completion notification */
-	nv_mask(priv, 0x610090, 0x00000001, 0x00000000);
-	nv_mask(priv, 0x6100a0, 0x00000001, 0x00000000);
-
-	return nv50_disp_chan_fini(&mast->base, suspend);
-}
-
-struct nv50_disp_chan_impl
-nvd0_disp_core_ofuncs = {
-	.base.ctor = nv50_disp_core_ctor,
-	.base.dtor = nv50_disp_dmac_dtor,
-	.base.init = nvd0_disp_core_init,
-	.base.fini = nvd0_disp_core_fini,
-	.base.ntfy = nv50_disp_chan_ntfy,
-	.base.map  = nv50_disp_chan_map,
-	.base.rd32 = nv50_disp_chan_rd32,
-	.base.wr32 = nv50_disp_chan_wr32,
-	.chid = 0,
-	.attach = nvd0_disp_dmac_object_attach,
-	.detach = nvd0_disp_dmac_object_detach,
-};
-
-/*******************************************************************************
- * EVO sync channel objects
- ******************************************************************************/
-
-static const struct nv50_disp_mthd_list
-nvd0_disp_base_mthd_base = {
-	.mthd = 0x0000,
-	.addr = 0x000000,
-	.data = {
-		{ 0x0080, 0x661080 },
-		{ 0x0084, 0x661084 },
-		{ 0x0088, 0x661088 },
-		{ 0x008c, 0x66108c },
-		{ 0x0090, 0x661090 },
-		{ 0x0094, 0x661094 },
-		{ 0x00a0, 0x6610a0 },
-		{ 0x00a4, 0x6610a4 },
-		{ 0x00c0, 0x6610c0 },
-		{ 0x00c4, 0x6610c4 },
-		{ 0x00c8, 0x6610c8 },
-		{ 0x00cc, 0x6610cc },
-		{ 0x00e0, 0x6610e0 },
-		{ 0x00e4, 0x6610e4 },
-		{ 0x00e8, 0x6610e8 },
-		{ 0x00ec, 0x6610ec },
-		{ 0x00fc, 0x6610fc },
-		{ 0x0100, 0x661100 },
-		{ 0x0104, 0x661104 },
-		{ 0x0108, 0x661108 },
-		{ 0x010c, 0x66110c },
-		{ 0x0110, 0x661110 },
-		{ 0x0114, 0x661114 },
-		{ 0x0118, 0x661118 },
-		{ 0x011c, 0x66111c },
-		{ 0x0130, 0x661130 },
-		{ 0x0134, 0x661134 },
-		{ 0x0138, 0x661138 },
-		{ 0x013c, 0x66113c },
-		{ 0x0140, 0x661140 },
-		{ 0x0144, 0x661144 },
-		{ 0x0148, 0x661148 },
-		{ 0x014c, 0x66114c },
-		{ 0x0150, 0x661150 },
-		{ 0x0154, 0x661154 },
-		{ 0x0158, 0x661158 },
-		{ 0x015c, 0x66115c },
-		{ 0x0160, 0x661160 },
-		{ 0x0164, 0x661164 },
-		{ 0x0168, 0x661168 },
-		{ 0x016c, 0x66116c },
-		{}
-	}
-};
-
-static const struct nv50_disp_mthd_list
-nvd0_disp_base_mthd_image = {
-	.mthd = 0x0400,
-	.addr = 0x000400,
-	.data = {
-		{ 0x0400, 0x661400 },
-		{ 0x0404, 0x661404 },
-		{ 0x0408, 0x661408 },
-		{ 0x040c, 0x66140c },
-		{ 0x0410, 0x661410 },
-		{}
-	}
-};
-
-const struct nv50_disp_mthd_chan
-nvd0_disp_base_mthd_chan = {
-	.name = "Base",
-	.addr = 0x001000,
-	.data = {
-		{ "Global", 1, &nvd0_disp_base_mthd_base },
-		{  "Image", 2, &nvd0_disp_base_mthd_image },
-		{}
-	}
-};
-
-struct nv50_disp_chan_impl
-nvd0_disp_base_ofuncs = {
-	.base.ctor = nv50_disp_base_ctor,
-	.base.dtor = nv50_disp_dmac_dtor,
-	.base.init = nvd0_disp_dmac_init,
-	.base.fini = nvd0_disp_dmac_fini,
-	.base.ntfy = nv50_disp_chan_ntfy,
-	.base.map  = nv50_disp_chan_map,
-	.base.rd32 = nv50_disp_chan_rd32,
-	.base.wr32 = nv50_disp_chan_wr32,
-	.chid = 1,
-	.attach = nvd0_disp_dmac_object_attach,
-	.detach = nvd0_disp_dmac_object_detach,
-};
-
-/*******************************************************************************
- * EVO overlay channel objects
- ******************************************************************************/
-
-static const struct nv50_disp_mthd_list
-nvd0_disp_ovly_mthd_base = {
-	.mthd = 0x0000,
-	.data = {
-		{ 0x0080, 0x665080 },
-		{ 0x0084, 0x665084 },
-		{ 0x0088, 0x665088 },
-		{ 0x008c, 0x66508c },
-		{ 0x0090, 0x665090 },
-		{ 0x0094, 0x665094 },
-		{ 0x00a0, 0x6650a0 },
-		{ 0x00a4, 0x6650a4 },
-		{ 0x00b0, 0x6650b0 },
-		{ 0x00b4, 0x6650b4 },
-		{ 0x00b8, 0x6650b8 },
-		{ 0x00c0, 0x6650c0 },
-		{ 0x00e0, 0x6650e0 },
-		{ 0x00e4, 0x6650e4 },
-		{ 0x00e8, 0x6650e8 },
-		{ 0x0100, 0x665100 },
-		{ 0x0104, 0x665104 },
-		{ 0x0108, 0x665108 },
-		{ 0x010c, 0x66510c },
-		{ 0x0110, 0x665110 },
-		{ 0x0118, 0x665118 },
-		{ 0x011c, 0x66511c },
-		{ 0x0120, 0x665120 },
-		{ 0x0124, 0x665124 },
-		{ 0x0130, 0x665130 },
-		{ 0x0134, 0x665134 },
-		{ 0x0138, 0x665138 },
-		{ 0x013c, 0x66513c },
-		{ 0x0140, 0x665140 },
-		{ 0x0144, 0x665144 },
-		{ 0x0148, 0x665148 },
-		{ 0x014c, 0x66514c },
-		{ 0x0150, 0x665150 },
-		{ 0x0154, 0x665154 },
-		{ 0x0158, 0x665158 },
-		{ 0x015c, 0x66515c },
-		{ 0x0160, 0x665160 },
-		{ 0x0164, 0x665164 },
-		{ 0x0168, 0x665168 },
-		{ 0x016c, 0x66516c },
-		{ 0x0400, 0x665400 },
-		{ 0x0408, 0x665408 },
-		{ 0x040c, 0x66540c },
-		{ 0x0410, 0x665410 },
-		{}
-	}
-};
-
-static const struct nv50_disp_mthd_chan
-nvd0_disp_ovly_mthd_chan = {
-	.name = "Overlay",
-	.addr = 0x001000,
-	.data = {
-		{ "Global", 1, &nvd0_disp_ovly_mthd_base },
-		{}
-	}
-};
-
-struct nv50_disp_chan_impl
-nvd0_disp_ovly_ofuncs = {
-	.base.ctor = nv50_disp_ovly_ctor,
-	.base.dtor = nv50_disp_dmac_dtor,
-	.base.init = nvd0_disp_dmac_init,
-	.base.fini = nvd0_disp_dmac_fini,
-	.base.ntfy = nv50_disp_chan_ntfy,
-	.base.map  = nv50_disp_chan_map,
-	.base.rd32 = nv50_disp_chan_rd32,
-	.base.wr32 = nv50_disp_chan_wr32,
-	.chid = 5,
-	.attach = nvd0_disp_dmac_object_attach,
-	.detach = nvd0_disp_dmac_object_detach,
-};
-
-/*******************************************************************************
- * EVO PIO channel base class
- ******************************************************************************/
-
-static int
-nvd0_disp_pioc_init(struct nouveau_object *object)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nv50_disp_pioc *pioc = (void *)object;
-	int chid = pioc->base.chid;
-	int ret;
-
-	ret = nv50_disp_chan_init(&pioc->base);
-	if (ret)
-		return ret;
-
-	/* enable error reporting */
-	nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid);
-
-	/* activate channel */
-	nv_wr32(priv, 0x610490 + (chid * 0x10), 0x00000001);
-	if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x00030000, 0x00010000)) {
-		nv_error(pioc, "init: 0x%08x\n",
-			 nv_rd32(priv, 0x610490 + (chid * 0x10)));
-		return -EBUSY;
-	}
-
-	return 0;
-}
-
-static int
-nvd0_disp_pioc_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nv50_disp_pioc *pioc = (void *)object;
-	int chid = pioc->base.chid;
-
-	nv_mask(priv, 0x610490 + (chid * 0x10), 0x00000001, 0x00000000);
-	if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x00030000, 0x00000000)) {
-		nv_error(pioc, "timeout: 0x%08x\n",
-			 nv_rd32(priv, 0x610490 + (chid * 0x10)));
-		if (suspend)
-			return -EBUSY;
-	}
-
-	/* disable error reporting and completion notification */
-	nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000);
-	nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000);
-
-	return nv50_disp_chan_fini(&pioc->base, suspend);
-}
-
-/*******************************************************************************
- * EVO immediate overlay channel objects
- ******************************************************************************/
-
-struct nv50_disp_chan_impl
-nvd0_disp_oimm_ofuncs = {
-	.base.ctor = nv50_disp_oimm_ctor,
-	.base.dtor = nv50_disp_pioc_dtor,
-	.base.init = nvd0_disp_pioc_init,
-	.base.fini = nvd0_disp_pioc_fini,
-	.base.ntfy = nv50_disp_chan_ntfy,
-	.base.map  = nv50_disp_chan_map,
-	.base.rd32 = nv50_disp_chan_rd32,
-	.base.wr32 = nv50_disp_chan_wr32,
-	.chid = 9,
-};
-
-/*******************************************************************************
- * EVO cursor channel objects
- ******************************************************************************/
-
-struct nv50_disp_chan_impl
-nvd0_disp_curs_ofuncs = {
-	.base.ctor = nv50_disp_curs_ctor,
-	.base.dtor = nv50_disp_pioc_dtor,
-	.base.init = nvd0_disp_pioc_init,
-	.base.fini = nvd0_disp_pioc_fini,
-	.base.ntfy = nv50_disp_chan_ntfy,
-	.base.map  = nv50_disp_chan_map,
-	.base.rd32 = nv50_disp_chan_rd32,
-	.base.wr32 = nv50_disp_chan_wr32,
-	.chid = 13,
-};
-
-/*******************************************************************************
- * Base display object
- ******************************************************************************/
-
-int
-nvd0_disp_main_scanoutpos(NV50_DISP_MTHD_V0)
-{
-	const u32 total  = nv_rd32(priv, 0x640414 + (head * 0x300));
-	const u32 blanke = nv_rd32(priv, 0x64041c + (head * 0x300));
-	const u32 blanks = nv_rd32(priv, 0x640420 + (head * 0x300));
-	union {
-		struct nv04_disp_scanoutpos_v0 v0;
-	} *args = data;
-	int ret;
-
-	nv_ioctl(object, "disp scanoutpos size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "disp scanoutpos vers %d\n", args->v0.version);
-		args->v0.vblanke = (blanke & 0xffff0000) >> 16;
-		args->v0.hblanke = (blanke & 0x0000ffff);
-		args->v0.vblanks = (blanks & 0xffff0000) >> 16;
-		args->v0.hblanks = (blanks & 0x0000ffff);
-		args->v0.vtotal  = ( total & 0xffff0000) >> 16;
-		args->v0.htotal  = ( total & 0x0000ffff);
-		args->v0.time[0] = ktime_to_ns(ktime_get());
-		args->v0.vline = /* vline read locks hline */
-			nv_rd32(priv, 0x616340 + (head * 0x800)) & 0xffff;
-		args->v0.time[1] = ktime_to_ns(ktime_get());
-		args->v0.hline =
-			nv_rd32(priv, 0x616344 + (head * 0x800)) & 0xffff;
-	} else
-		return ret;
-
-	return 0;
-}
-
-static int
-nvd0_disp_main_init(struct nouveau_object *object)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nv50_disp_base *base = (void *)object;
-	int ret, i;
-	u32 tmp;
-
-	ret = nouveau_parent_init(&base->base);
-	if (ret)
-		return ret;
-
-	/* The below segments of code copying values from one register to
-	 * another appear to inform EVO of the display capabilities or
-	 * something similar.
-	 */
-
-	/* ... CRTC caps */
-	for (i = 0; i < priv->head.nr; i++) {
-		tmp = nv_rd32(priv, 0x616104 + (i * 0x800));
-		nv_wr32(priv, 0x6101b4 + (i * 0x800), tmp);
-		tmp = nv_rd32(priv, 0x616108 + (i * 0x800));
-		nv_wr32(priv, 0x6101b8 + (i * 0x800), tmp);
-		tmp = nv_rd32(priv, 0x61610c + (i * 0x800));
-		nv_wr32(priv, 0x6101bc + (i * 0x800), tmp);
-	}
-
-	/* ... DAC caps */
-	for (i = 0; i < priv->dac.nr; i++) {
-		tmp = nv_rd32(priv, 0x61a000 + (i * 0x800));
-		nv_wr32(priv, 0x6101c0 + (i * 0x800), tmp);
-	}
-
-	/* ... SOR caps */
-	for (i = 0; i < priv->sor.nr; i++) {
-		tmp = nv_rd32(priv, 0x61c000 + (i * 0x800));
-		nv_wr32(priv, 0x6301c4 + (i * 0x800), tmp);
-	}
-
-	/* steal display away from vbios, or something like that */
-	if (nv_rd32(priv, 0x6100ac) & 0x00000100) {
-		nv_wr32(priv, 0x6100ac, 0x00000100);
-		nv_mask(priv, 0x6194e8, 0x00000001, 0x00000000);
-		if (!nv_wait(priv, 0x6194e8, 0x00000002, 0x00000000)) {
-			nv_error(priv, "timeout acquiring display\n");
-			return -EBUSY;
-		}
-	}
-
-	/* point at display engine memory area (hash table, objects) */
-	nv_wr32(priv, 0x610010, (nv_gpuobj(object->parent)->addr >> 8) | 9);
-
-	/* enable supervisor interrupts, disable everything else */
-	nv_wr32(priv, 0x610090, 0x00000000);
-	nv_wr32(priv, 0x6100a0, 0x00000000);
-	nv_wr32(priv, 0x6100b0, 0x00000307);
-
-	/* disable underflow reporting, preventing an intermittent issue
-	 * on some nve4 boards where the production vbios left this
-	 * setting enabled by default.
-	 *
-	 * ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt
-	 */
-	for (i = 0; i < priv->head.nr; i++)
-		nv_mask(priv, 0x616308 + (i * 0x800), 0x00000111, 0x00000010);
-
-	return 0;
-}
-
-static int
-nvd0_disp_main_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv50_disp_priv *priv = (void *)object->engine;
-	struct nv50_disp_base *base = (void *)object;
-
-	/* disable all interrupts */
-	nv_wr32(priv, 0x6100b0, 0x00000000);
-
-	return nouveau_parent_fini(&base->base, suspend);
-}
-
-struct nouveau_ofuncs
-nvd0_disp_main_ofuncs = {
-	.ctor = nv50_disp_main_ctor,
-	.dtor = nv50_disp_main_dtor,
-	.init = nvd0_disp_main_init,
-	.fini = nvd0_disp_main_fini,
-	.mthd = nv50_disp_main_mthd,
-	.ntfy = nouveau_disp_ntfy,
-};
-
-static struct nouveau_oclass
-nvd0_disp_main_oclass[] = {
-	{ GF110_DISP, &nvd0_disp_main_ofuncs },
-	{}
-};
-
-static struct nouveau_oclass
-nvd0_disp_sclass[] = {
-	{ GF110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
-	{ GF110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
-	{ GF110_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
-	{ GF110_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
-	{ GF110_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
-	{}
-};
-
-/*******************************************************************************
- * Display engine implementation
- ******************************************************************************/
-
-static void
-nvd0_disp_vblank_init(struct nvkm_event *event, int type, int head)
-{
-	struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank);
-	nv_mask(disp, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000001);
-}
-
-static void
-nvd0_disp_vblank_fini(struct nvkm_event *event, int type, int head)
-{
-	struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank);
-	nv_mask(disp, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000000);
-}
-
-const struct nvkm_event_func
-nvd0_disp_vblank_func = {
-	.ctor = nouveau_disp_vblank_ctor,
-	.init = nvd0_disp_vblank_init,
-	.fini = nvd0_disp_vblank_fini,
-};
-
-static struct nvkm_output *
-exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl,
-	    u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-	    struct nvbios_outp *info)
-{
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	struct nvkm_output *outp;
-	u16 mask, type;
-
-	if (or < 4) {
-		type = DCB_OUTPUT_ANALOG;
-		mask = 0;
-	} else {
-		or -= 4;
-		switch (ctrl & 0x00000f00) {
-		case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break;
-		case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break;
-		case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break;
-		case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break;
-		case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break;
-		case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break;
-		default:
-			nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl);
-			return 0x0000;
-		}
-	}
-
-	mask  = 0x00c0 & (mask << 6);
-	mask |= 0x0001 << or;
-	mask |= 0x0100 << head;
-
-	list_for_each_entry(outp, &priv->base.outp, head) {
-		if ((outp->info.hasht & 0xff) == type &&
-		    (outp->info.hashm & mask) == mask) {
-			*data = nvbios_outp_match(bios, outp->info.hasht,
-							outp->info.hashm,
-						  ver, hdr, cnt, len, info);
-			if (!*data)
-				return NULL;
-			return outp;
-		}
-	}
-
-	return NULL;
-}
-
-static struct nvkm_output *
-exec_script(struct nv50_disp_priv *priv, int head, int id)
-{
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	struct nvkm_output *outp;
-	struct nvbios_outp info;
-	u8  ver, hdr, cnt, len;
-	u32 data, ctrl = 0;
-	int or;
-
-	for (or = 0; !(ctrl & (1 << head)) && or < 8; or++) {
-		ctrl = nv_rd32(priv, 0x640180 + (or * 0x20));
-		if (ctrl & (1 << head))
-			break;
-	}
-
-	if (or == 8)
-		return NULL;
-
-	outp = exec_lookup(priv, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info);
-	if (outp) {
-		struct nvbios_init init = {
-			.subdev = nv_subdev(priv),
-			.bios = bios,
-			.offset = info.script[id],
-			.outp = &outp->info,
-			.crtc = head,
-			.execute = 1,
-		};
-
-		nvbios_exec(&init);
-	}
-
-	return outp;
-}
-
-static struct nvkm_output *
-exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf)
-{
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	struct nvkm_output *outp;
-	struct nvbios_outp info1;
-	struct nvbios_ocfg info2;
-	u8  ver, hdr, cnt, len;
-	u32 data, ctrl = 0;
-	int or;
-
-	for (or = 0; !(ctrl & (1 << head)) && or < 8; or++) {
-		ctrl = nv_rd32(priv, 0x660180 + (or * 0x20));
-		if (ctrl & (1 << head))
-			break;
-	}
-
-	if (or == 8)
-		return NULL;
-
-	outp = exec_lookup(priv, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info1);
-	if (!outp)
-		return NULL;
-
-	switch (outp->info.type) {
-	case DCB_OUTPUT_TMDS:
-		*conf = (ctrl & 0x00000f00) >> 8;
-		if (pclk >= 165000)
-			*conf |= 0x0100;
-		break;
-	case DCB_OUTPUT_LVDS:
-		*conf = priv->sor.lvdsconf;
-		break;
-	case DCB_OUTPUT_DP:
-		*conf = (ctrl & 0x00000f00) >> 8;
-		break;
-	case DCB_OUTPUT_ANALOG:
-	default:
-		*conf = 0x00ff;
-		break;
-	}
-
-	data = nvbios_ocfg_match(bios, data, *conf, &ver, &hdr, &cnt, &len, &info2);
-	if (data && id < 0xff) {
-		data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
-		if (data) {
-			struct nvbios_init init = {
-				.subdev = nv_subdev(priv),
-				.bios = bios,
-				.offset = data,
-				.outp = &outp->info,
-				.crtc = head,
-				.execute = 1,
-			};
-
-			nvbios_exec(&init);
-		}
-	}
-
-	return outp;
-}
-
-static void
-nvd0_disp_intr_unk1_0(struct nv50_disp_priv *priv, int head)
-{
-	exec_script(priv, head, 1);
-}
-
-static void
-nvd0_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head)
-{
-	struct nvkm_output *outp = exec_script(priv, head, 2);
-
-	/* see note in nv50_disp_intr_unk20_0() */
-	if (outp && outp->info.type == DCB_OUTPUT_DP) {
-		struct nvkm_output_dp *outpdp = (void *)outp;
-		struct nvbios_init init = {
-			.subdev = nv_subdev(priv),
-			.bios = nouveau_bios(priv),
-			.outp = &outp->info,
-			.crtc = head,
-			.offset = outpdp->info.script[4],
-			.execute = 1,
-		};
-
-		nvbios_exec(&init);
-		atomic_set(&outpdp->lt.done, 0);
-	}
-}
-
-static void
-nvd0_disp_intr_unk2_1(struct nv50_disp_priv *priv, int head)
-{
-	struct nouveau_devinit *devinit = nouveau_devinit(priv);
-	u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
-	if (pclk)
-		devinit->pll_set(devinit, PLL_VPLL0 + head, pclk);
-	nv_wr32(priv, 0x612200 + (head * 0x800), 0x00000000);
-}
-
-static void
-nvd0_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head,
-			 struct dcb_output *outp)
-{
-	const int or = ffs(outp->or) - 1;
-	const u32 ctrl = nv_rd32(priv, 0x660200 + (or   * 0x020));
-	const u32 conf = nv_rd32(priv, 0x660404 + (head * 0x300));
-	const s32 vactive = nv_rd32(priv, 0x660414 + (head * 0x300)) & 0xffff;
-	const s32 vblanke = nv_rd32(priv, 0x66041c + (head * 0x300)) & 0xffff;
-	const s32 vblanks = nv_rd32(priv, 0x660420 + (head * 0x300)) & 0xffff;
-	const u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
-	const u32 link = ((ctrl & 0xf00) == 0x800) ? 0 : 1;
-	const u32 hoff = (head * 0x800);
-	const u32 soff = (  or * 0x800);
-	const u32 loff = (link * 0x080) + soff;
-	const u32 symbol = 100000;
-	const u32 TU = 64;
-	u32 dpctrl = nv_rd32(priv, 0x61c10c + loff);
-	u32 clksor = nv_rd32(priv, 0x612300 + soff);
-	u32 datarate, link_nr, link_bw, bits;
-	u64 ratio, value;
-
-	link_nr  = hweight32(dpctrl & 0x000f0000);
-	link_bw  = (clksor & 0x007c0000) >> 18;
-	link_bw *= 27000;
-
-	/* symbols/hblank - algorithm taken from comments in tegra driver */
-	value = vblanke + vactive - vblanks - 7;
-	value = value * link_bw;
-	do_div(value, pclk);
-	value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr);
-	nv_mask(priv, 0x616620 + hoff, 0x0000ffff, value);
-
-	/* symbols/vblank - algorithm taken from comments in tegra driver */
-	value = vblanks - vblanke - 25;
-	value = value * link_bw;
-	do_div(value, pclk);
-	value = value - ((36 / link_nr) + 3) - 1;
-	nv_mask(priv, 0x616624 + hoff, 0x00ffffff, value);
-
-	/* watermark */
-	if      ((conf & 0x3c0) == 0x180) bits = 30;
-	else if ((conf & 0x3c0) == 0x140) bits = 24;
-	else                              bits = 18;
-	datarate = (pclk * bits) / 8;
-
-	ratio  = datarate;
-	ratio *= symbol;
-	do_div(ratio, link_nr * link_bw);
-
-	value  = (symbol - ratio) * TU;
-	value *= ratio;
-	do_div(value, symbol);
-	do_div(value, symbol);
-
-	value += 5;
-	value |= 0x08000000;
-
-	nv_wr32(priv, 0x616610 + hoff, value);
-}
-
-static void
-nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head)
-{
-	struct nvkm_output *outp;
-	u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
-	u32 conf, addr, data;
-
-	outp = exec_clkcmp(priv, head, 0xff, pclk, &conf);
-	if (!outp)
-		return;
-
-	/* see note in nv50_disp_intr_unk20_2() */
-	if (outp->info.type == DCB_OUTPUT_DP) {
-		u32 sync = nv_rd32(priv, 0x660404 + (head * 0x300));
-		switch ((sync & 0x000003c0) >> 6) {
-		case 6: pclk = pclk * 30; break;
-		case 5: pclk = pclk * 24; break;
-		case 2:
-		default:
-			pclk = pclk * 18;
-			break;
-		}
-
-		if (nvkm_output_dp_train(outp, pclk, true))
-			ERR("link not trained before attach\n");
-	} else {
-		if (priv->sor.magic)
-			priv->sor.magic(outp);
-	}
-
-	exec_clkcmp(priv, head, 0, pclk, &conf);
-
-	if (outp->info.type == DCB_OUTPUT_ANALOG) {
-		addr = 0x612280 + (ffs(outp->info.or) - 1) * 0x800;
-		data = 0x00000000;
-	} else {
-		addr = 0x612300 + (ffs(outp->info.or) - 1) * 0x800;
-		data = (conf & 0x0100) ? 0x00000101 : 0x00000000;
-		switch (outp->info.type) {
-		case DCB_OUTPUT_TMDS:
-			nv_mask(priv, addr, 0x007c0000, 0x00280000);
-			break;
-		case DCB_OUTPUT_DP:
-			nvd0_disp_intr_unk2_2_tu(priv, head, &outp->info);
-			break;
-		default:
-			break;
-		}
-	}
-
-	nv_mask(priv, addr, 0x00000707, data);
-}
-
-static void
-nvd0_disp_intr_unk4_0(struct nv50_disp_priv *priv, int head)
-{
-	u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
-	u32 conf;
-
-	exec_clkcmp(priv, head, 1, pclk, &conf);
-}
-
-void
-nvd0_disp_intr_supervisor(struct work_struct *work)
-{
-	struct nv50_disp_priv *priv =
-		container_of(work, struct nv50_disp_priv, supervisor);
-	struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass;
-	u32 mask[4];
-	int head;
-
-	nv_debug(priv, "supervisor %d\n", ffs(priv->super));
-	for (head = 0; head < priv->head.nr; head++) {
-		mask[head] = nv_rd32(priv, 0x6101d4 + (head * 0x800));
-		nv_debug(priv, "head %d: 0x%08x\n", head, mask[head]);
-	}
-
-	if (priv->super & 0x00000001) {
-		nv50_disp_mthd_chan(priv, NV_DBG_DEBUG, 0, impl->mthd.core);
-		for (head = 0; head < priv->head.nr; head++) {
-			if (!(mask[head] & 0x00001000))
-				continue;
-			nv_debug(priv, "supervisor 1.0 - head %d\n", head);
-			nvd0_disp_intr_unk1_0(priv, head);
-		}
-	} else
-	if (priv->super & 0x00000002) {
-		for (head = 0; head < priv->head.nr; head++) {
-			if (!(mask[head] & 0x00001000))
-				continue;
-			nv_debug(priv, "supervisor 2.0 - head %d\n", head);
-			nvd0_disp_intr_unk2_0(priv, head);
-		}
-		for (head = 0; head < priv->head.nr; head++) {
-			if (!(mask[head] & 0x00010000))
-				continue;
-			nv_debug(priv, "supervisor 2.1 - head %d\n", head);
-			nvd0_disp_intr_unk2_1(priv, head);
-		}
-		for (head = 0; head < priv->head.nr; head++) {
-			if (!(mask[head] & 0x00001000))
-				continue;
-			nv_debug(priv, "supervisor 2.2 - head %d\n", head);
-			nvd0_disp_intr_unk2_2(priv, head);
-		}
-	} else
-	if (priv->super & 0x00000004) {
-		for (head = 0; head < priv->head.nr; head++) {
-			if (!(mask[head] & 0x00001000))
-				continue;
-			nv_debug(priv, "supervisor 3.0 - head %d\n", head);
-			nvd0_disp_intr_unk4_0(priv, head);
-		}
-	}
-
-	for (head = 0; head < priv->head.nr; head++)
-		nv_wr32(priv, 0x6101d4 + (head * 0x800), 0x00000000);
-	nv_wr32(priv, 0x6101d0, 0x80000000);
-}
-
-static void
-nvd0_disp_intr_error(struct nv50_disp_priv *priv, int chid)
-{
-	const struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass;
-	u32 mthd = nv_rd32(priv, 0x6101f0 + (chid * 12));
-	u32 data = nv_rd32(priv, 0x6101f4 + (chid * 12));
-	u32 unkn = nv_rd32(priv, 0x6101f8 + (chid * 12));
-
-	nv_error(priv, "chid %d mthd 0x%04x data 0x%08x "
-		       "0x%08x 0x%08x\n",
-		 chid, (mthd & 0x0000ffc), data, mthd, unkn);
-
-	if (chid == 0) {
-		switch (mthd & 0xffc) {
-		case 0x0080:
-			nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 0,
-					    impl->mthd.core);
-			break;
-		default:
-			break;
-		}
-	} else
-	if (chid <= 4) {
-		switch (mthd & 0xffc) {
-		case 0x0080:
-			nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 1,
-					    impl->mthd.base);
-			break;
-		default:
-			break;
-		}
-	} else
-	if (chid <= 8) {
-		switch (mthd & 0xffc) {
-		case 0x0080:
-			nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 5,
-					    impl->mthd.ovly);
-			break;
-		default:
-			break;
-		}
-	}
-
-	nv_wr32(priv, 0x61009c, (1 << chid));
-	nv_wr32(priv, 0x6101f0 + (chid * 12), 0x90000000);
-}
-
-void
-nvd0_disp_intr(struct nouveau_subdev *subdev)
-{
-	struct nv50_disp_priv *priv = (void *)subdev;
-	u32 intr = nv_rd32(priv, 0x610088);
-	int i;
-
-	if (intr & 0x00000001) {
-		u32 stat = nv_rd32(priv, 0x61008c);
-		while (stat) {
-			int chid = __ffs(stat); stat &= ~(1 << chid);
-			nv50_disp_chan_uevent_send(priv, chid);
-			nv_wr32(priv, 0x61008c, 1 << chid);
-		}
-		intr &= ~0x00000001;
-	}
-
-	if (intr & 0x00000002) {
-		u32 stat = nv_rd32(priv, 0x61009c);
-		int chid = ffs(stat) - 1;
-		if (chid >= 0)
-			nvd0_disp_intr_error(priv, chid);
-		intr &= ~0x00000002;
-	}
-
-	if (intr & 0x00100000) {
-		u32 stat = nv_rd32(priv, 0x6100ac);
-		if (stat & 0x00000007) {
-			priv->super = (stat & 0x00000007);
-			schedule_work(&priv->supervisor);
-			nv_wr32(priv, 0x6100ac, priv->super);
-			stat &= ~0x00000007;
-		}
-
-		if (stat) {
-			nv_info(priv, "unknown intr24 0x%08x\n", stat);
-			nv_wr32(priv, 0x6100ac, stat);
-		}
-
-		intr &= ~0x00100000;
-	}
-
-	for (i = 0; i < priv->head.nr; i++) {
-		u32 mask = 0x01000000 << i;
-		if (mask & intr) {
-			u32 stat = nv_rd32(priv, 0x6100bc + (i * 0x800));
-			if (stat & 0x00000001)
-				nouveau_disp_vblank(&priv->base, i);
-			nv_mask(priv, 0x6100bc + (i * 0x800), 0, 0);
-			nv_rd32(priv, 0x6100c0 + (i * 0x800));
-		}
-	}
-}
-
-static int
-nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv50_disp_priv *priv;
-	int heads = nv_rd32(parent, 0x022448);
-	int ret;
-
-	ret = nouveau_disp_create(parent, engine, oclass, heads,
-				  "PDISP", "display", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
-	if (ret)
-		return ret;
-
-	nv_engine(priv)->sclass = nvd0_disp_main_oclass;
-	nv_engine(priv)->cclass = &nv50_disp_cclass;
-	nv_subdev(priv)->intr = nvd0_disp_intr;
-	INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
-	priv->sclass = nvd0_disp_sclass;
-	priv->head.nr = heads;
-	priv->dac.nr = 3;
-	priv->sor.nr = 4;
-	priv->dac.power = nv50_dac_power;
-	priv->dac.sense = nv50_dac_sense;
-	priv->sor.power = nv50_sor_power;
-	priv->sor.hda_eld = nvd0_hda_eld;
-	priv->sor.hdmi = nvd0_hdmi_ctrl;
-	return 0;
-}
-
-struct nouveau_oclass *
-nvd0_disp_outp_sclass[] = {
-	&nvd0_sor_dp_impl.base.base,
-	NULL
-};
-
-struct nouveau_oclass *
-nvd0_disp_oclass = &(struct nv50_disp_impl) {
-	.base.base.handle = NV_ENGINE(DISP, 0x90),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvd0_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
-	},
-	.base.vblank = &nvd0_disp_vblank_func,
-	.base.outp =  nvd0_disp_outp_sclass,
-	.mthd.core = &nvd0_disp_core_mthd_chan,
-	.mthd.base = &nvd0_disp_base_mthd_chan,
-	.mthd.ovly = &nvd0_disp_ovly_mthd_chan,
-	.mthd.prev = -0x020000,
-	.head.scanoutpos = nvd0_disp_main_scanoutpos,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
deleted file mode 100644
index 55debec7e68f..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <engine/software.h>
-#include <engine/disp.h>
-
-#include <nvif/class.h>
-
-#include "nv50.h"
-
-/*******************************************************************************
- * EVO master channel object
- ******************************************************************************/
-
-static const struct nv50_disp_mthd_list
-nve0_disp_core_mthd_head = {
-	.mthd = 0x0300,
-	.addr = 0x000300,
-	.data = {
-		{ 0x0400, 0x660400 },
-		{ 0x0404, 0x660404 },
-		{ 0x0408, 0x660408 },
-		{ 0x040c, 0x66040c },
-		{ 0x0410, 0x660410 },
-		{ 0x0414, 0x660414 },
-		{ 0x0418, 0x660418 },
-		{ 0x041c, 0x66041c },
-		{ 0x0420, 0x660420 },
-		{ 0x0424, 0x660424 },
-		{ 0x0428, 0x660428 },
-		{ 0x042c, 0x66042c },
-		{ 0x0430, 0x660430 },
-		{ 0x0434, 0x660434 },
-		{ 0x0438, 0x660438 },
-		{ 0x0440, 0x660440 },
-		{ 0x0444, 0x660444 },
-		{ 0x0448, 0x660448 },
-		{ 0x044c, 0x66044c },
-		{ 0x0450, 0x660450 },
-		{ 0x0454, 0x660454 },
-		{ 0x0458, 0x660458 },
-		{ 0x045c, 0x66045c },
-		{ 0x0460, 0x660460 },
-		{ 0x0468, 0x660468 },
-		{ 0x046c, 0x66046c },
-		{ 0x0470, 0x660470 },
-		{ 0x0474, 0x660474 },
-		{ 0x047c, 0x66047c },
-		{ 0x0480, 0x660480 },
-		{ 0x0484, 0x660484 },
-		{ 0x0488, 0x660488 },
-		{ 0x048c, 0x66048c },
-		{ 0x0490, 0x660490 },
-		{ 0x0494, 0x660494 },
-		{ 0x0498, 0x660498 },
-		{ 0x04a0, 0x6604a0 },
-		{ 0x04b0, 0x6604b0 },
-		{ 0x04b8, 0x6604b8 },
-		{ 0x04bc, 0x6604bc },
-		{ 0x04c0, 0x6604c0 },
-		{ 0x04c4, 0x6604c4 },
-		{ 0x04c8, 0x6604c8 },
-		{ 0x04d0, 0x6604d0 },
-		{ 0x04d4, 0x6604d4 },
-		{ 0x04e0, 0x6604e0 },
-		{ 0x04e4, 0x6604e4 },
-		{ 0x04e8, 0x6604e8 },
-		{ 0x04ec, 0x6604ec },
-		{ 0x04f0, 0x6604f0 },
-		{ 0x04f4, 0x6604f4 },
-		{ 0x04f8, 0x6604f8 },
-		{ 0x04fc, 0x6604fc },
-		{ 0x0500, 0x660500 },
-		{ 0x0504, 0x660504 },
-		{ 0x0508, 0x660508 },
-		{ 0x050c, 0x66050c },
-		{ 0x0510, 0x660510 },
-		{ 0x0514, 0x660514 },
-		{ 0x0518, 0x660518 },
-		{ 0x051c, 0x66051c },
-		{ 0x0520, 0x660520 },
-		{ 0x0524, 0x660524 },
-		{ 0x052c, 0x66052c },
-		{ 0x0530, 0x660530 },
-		{ 0x054c, 0x66054c },
-		{ 0x0550, 0x660550 },
-		{ 0x0554, 0x660554 },
-		{ 0x0558, 0x660558 },
-		{ 0x055c, 0x66055c },
-		{}
-	}
-};
-
-const struct nv50_disp_mthd_chan
-nve0_disp_core_mthd_chan = {
-	.name = "Core",
-	.addr = 0x000000,
-	.data = {
-		{ "Global", 1, &nvd0_disp_core_mthd_base },
-		{    "DAC", 3, &nvd0_disp_core_mthd_dac  },
-		{    "SOR", 8, &nvd0_disp_core_mthd_sor  },
-		{   "PIOR", 4, &nvd0_disp_core_mthd_pior },
-		{   "HEAD", 4, &nve0_disp_core_mthd_head },
-		{}
-	}
-};
-
-/*******************************************************************************
- * EVO overlay channel objects
- ******************************************************************************/
-
-static const struct nv50_disp_mthd_list
-nve0_disp_ovly_mthd_base = {
-	.mthd = 0x0000,
-	.data = {
-		{ 0x0080, 0x665080 },
-		{ 0x0084, 0x665084 },
-		{ 0x0088, 0x665088 },
-		{ 0x008c, 0x66508c },
-		{ 0x0090, 0x665090 },
-		{ 0x0094, 0x665094 },
-		{ 0x00a0, 0x6650a0 },
-		{ 0x00a4, 0x6650a4 },
-		{ 0x00b0, 0x6650b0 },
-		{ 0x00b4, 0x6650b4 },
-		{ 0x00b8, 0x6650b8 },
-		{ 0x00c0, 0x6650c0 },
-		{ 0x00c4, 0x6650c4 },
-		{ 0x00e0, 0x6650e0 },
-		{ 0x00e4, 0x6650e4 },
-		{ 0x00e8, 0x6650e8 },
-		{ 0x0100, 0x665100 },
-		{ 0x0104, 0x665104 },
-		{ 0x0108, 0x665108 },
-		{ 0x010c, 0x66510c },
-		{ 0x0110, 0x665110 },
-		{ 0x0118, 0x665118 },
-		{ 0x011c, 0x66511c },
-		{ 0x0120, 0x665120 },
-		{ 0x0124, 0x665124 },
-		{ 0x0130, 0x665130 },
-		{ 0x0134, 0x665134 },
-		{ 0x0138, 0x665138 },
-		{ 0x013c, 0x66513c },
-		{ 0x0140, 0x665140 },
-		{ 0x0144, 0x665144 },
-		{ 0x0148, 0x665148 },
-		{ 0x014c, 0x66514c },
-		{ 0x0150, 0x665150 },
-		{ 0x0154, 0x665154 },
-		{ 0x0158, 0x665158 },
-		{ 0x015c, 0x66515c },
-		{ 0x0160, 0x665160 },
-		{ 0x0164, 0x665164 },
-		{ 0x0168, 0x665168 },
-		{ 0x016c, 0x66516c },
-		{ 0x0400, 0x665400 },
-		{ 0x0404, 0x665404 },
-		{ 0x0408, 0x665408 },
-		{ 0x040c, 0x66540c },
-		{ 0x0410, 0x665410 },
-		{}
-	}
-};
-
-const struct nv50_disp_mthd_chan
-nve0_disp_ovly_mthd_chan = {
-	.name = "Overlay",
-	.addr = 0x001000,
-	.data = {
-		{ "Global", 1, &nve0_disp_ovly_mthd_base },
-		{}
-	}
-};
-
-/*******************************************************************************
- * Base display object
- ******************************************************************************/
-
-static struct nouveau_oclass
-nve0_disp_sclass[] = {
-	{ GK104_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
-	{ GK104_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
-	{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
-	{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
-	{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
-	{}
-};
-
-static struct nouveau_oclass
-nve0_disp_main_oclass[] = {
-	{ GK104_DISP, &nvd0_disp_main_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * Display engine implementation
- ******************************************************************************/
-
-static int
-nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv50_disp_priv *priv;
-	int heads = nv_rd32(parent, 0x022448);
-	int ret;
-
-	ret = nouveau_disp_create(parent, engine, oclass, heads,
-				  "PDISP", "display", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
-	if (ret)
-		return ret;
-
-	nv_engine(priv)->sclass = nve0_disp_main_oclass;
-	nv_engine(priv)->cclass = &nv50_disp_cclass;
-	nv_subdev(priv)->intr = nvd0_disp_intr;
-	INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
-	priv->sclass = nve0_disp_sclass;
-	priv->head.nr = heads;
-	priv->dac.nr = 3;
-	priv->sor.nr = 4;
-	priv->dac.power = nv50_dac_power;
-	priv->dac.sense = nv50_dac_sense;
-	priv->sor.power = nv50_sor_power;
-	priv->sor.hda_eld = nvd0_hda_eld;
-	priv->sor.hdmi = nve0_hdmi_ctrl;
-	return 0;
-}
-
-struct nouveau_oclass *
-nve0_disp_oclass = &(struct nv50_disp_impl) {
-	.base.base.handle = NV_ENGINE(DISP, 0x91),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nve0_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
-	},
-	.base.vblank = &nvd0_disp_vblank_func,
-	.base.outp =  nvd0_disp_outp_sclass,
-	.mthd.core = &nve0_disp_core_mthd_chan,
-	.mthd.base = &nvd0_disp_base_mthd_chan,
-	.mthd.ovly = &nve0_disp_ovly_mthd_chan,
-	.mthd.prev = -0x020000,
-	.head.scanoutpos = nvd0_disp_main_scanoutpos,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
deleted file mode 100644
index 3e7e2d28744c..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <engine/software.h>
-#include <engine/disp.h>
-
-#include <nvif/class.h>
-
-#include "nv50.h"
-
-/*******************************************************************************
- * Base display object
- ******************************************************************************/
-
-static struct nouveau_oclass
-nvf0_disp_sclass[] = {
-	{ GK110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
-	{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
-	{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
-	{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
-	{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
-	{}
-};
-
-static struct nouveau_oclass
-nvf0_disp_main_oclass[] = {
-	{ GK110_DISP, &nvd0_disp_main_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * Display engine implementation
- ******************************************************************************/
-
-static int
-nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv50_disp_priv *priv;
-	int heads = nv_rd32(parent, 0x022448);
-	int ret;
-
-	ret = nouveau_disp_create(parent, engine, oclass, heads,
-				  "PDISP", "display", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
-	if (ret)
-		return ret;
-
-	nv_engine(priv)->sclass = nvf0_disp_main_oclass;
-	nv_engine(priv)->cclass = &nv50_disp_cclass;
-	nv_subdev(priv)->intr = nvd0_disp_intr;
-	INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
-	priv->sclass = nvf0_disp_sclass;
-	priv->head.nr = heads;
-	priv->dac.nr = 3;
-	priv->sor.nr = 4;
-	priv->dac.power = nv50_dac_power;
-	priv->dac.sense = nv50_dac_sense;
-	priv->sor.power = nv50_sor_power;
-	priv->sor.hda_eld = nvd0_hda_eld;
-	priv->sor.hdmi = nve0_hdmi_ctrl;
-	return 0;
-}
-
-struct nouveau_oclass *
-nvf0_disp_oclass = &(struct nv50_disp_impl) {
-	.base.base.handle = NV_ENGINE(DISP, 0x92),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvf0_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
-	},
-	.base.vblank = &nvd0_disp_vblank_func,
-	.base.outp =  nvd0_disp_outp_sclass,
-	.mthd.core = &nve0_disp_core_mthd_chan,
-	.mthd.base = &nvd0_disp_base_mthd_chan,
-	.mthd.ovly = &nve0_disp_ovly_mthd_chan,
-	.mthd.prev = -0x020000,
-	.head.scanoutpos = nvd0_disp_main_scanoutpos,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outp.c b/drivers/gpu/drm/nouveau/core/engine/disp/outp.c
deleted file mode 100644
index bbd9b6fdc90f..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/outp.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/i2c.h>
-#include <subdev/bios.h>
-#include <subdev/bios/conn.h>
-
-#include "outp.h"
-
-int
-_nvkm_output_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nvkm_output *outp = (void *)object;
-	nv_ofuncs(outp->conn)->fini(nv_object(outp->conn), suspend);
-	return nouveau_object_fini(&outp->base, suspend);
-}
-
-int
-_nvkm_output_init(struct nouveau_object *object)
-{
-	struct nvkm_output *outp = (void *)object;
-	int ret = nouveau_object_init(&outp->base);
-	if (ret == 0)
-		nv_ofuncs(outp->conn)->init(nv_object(outp->conn));
-	return 0;
-}
-
-void
-_nvkm_output_dtor(struct nouveau_object *object)
-{
-	struct nvkm_output *outp = (void *)object;
-	list_del(&outp->head);
-	nouveau_object_ref(NULL, (void *)&outp->conn);
-	nouveau_object_destroy(&outp->base);
-}
-
-int
-nvkm_output_create_(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass,
-		    struct dcb_output *dcbE, int index,
-		    int length, void **pobject)
-{
-	struct nouveau_bios *bios = nouveau_bios(engine);
-	struct nouveau_i2c *i2c = nouveau_i2c(parent);
-	struct nouveau_disp *disp = (void *)engine;
-	struct nvbios_connE connE;
-	struct nvkm_output *outp;
-	u8  ver, hdr;
-	u32 data;
-	int ret;
-
-	ret = nouveau_object_create_(parent, engine, oclass, 0, length, pobject);
-	outp = *pobject;
-	if (ret)
-		return ret;
-
-	outp->info = *dcbE;
-	outp->index = index;
-	outp->or = ffs(outp->info.or) - 1;
-
-	DBG("type %02x loc %d or %d link %d con %x edid %x bus %d head %x\n",
-	    dcbE->type, dcbE->location, dcbE->or, dcbE->type >= 2 ?
-	    dcbE->sorconf.link : 0, dcbE->connector, dcbE->i2c_index,
-	    dcbE->bus, dcbE->heads);
-
-	if (outp->info.type != DCB_OUTPUT_DP)
-		outp->port = i2c->find(i2c, NV_I2C_PORT(outp->info.i2c_index));
-	else
-		outp->port = i2c->find(i2c, NV_I2C_AUX(outp->info.i2c_index));
-	outp->edid = outp->port;
-
-	data = nvbios_connEp(bios, outp->info.connector, &ver, &hdr, &connE);
-	if (!data) {
-		DBG("vbios connector data not found\n");
-		memset(&connE, 0x00, sizeof(connE));
-		connE.type = DCB_CONNECTOR_NONE;
-	}
-
-	ret = nouveau_object_ctor(parent, engine, nvkm_connector_oclass,
-				 &connE, outp->info.connector,
-				 (struct nouveau_object **)&outp->conn);
-	if (ret < 0) {
-		ERR("error %d creating connector, disabling\n", ret);
-		return ret;
-	}
-
-	list_add_tail(&outp->head, &disp->outp);
-	return 0;
-}
-
-int
-_nvkm_output_ctor(struct nouveau_object *parent,
-		  struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *dcbE, u32 index,
-		  struct nouveau_object **pobject)
-{
-	struct nvkm_output *outp;
-	int ret;
-
-	ret = nvkm_output_create(parent, engine, oclass, dcbE, index, &outp);
-	*pobject = nv_object(outp);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-struct nouveau_oclass *
-nvkm_output_oclass = &(struct nvkm_output_impl) {
-	.base = {
-		.handle = 0,
-		.ofuncs = &(struct nouveau_ofuncs) {
-			.ctor = _nvkm_output_ctor,
-			.dtor = _nvkm_output_dtor,
-			.init = _nvkm_output_init,
-			.fini = _nvkm_output_fini,
-		},
-	},
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outp.h b/drivers/gpu/drm/nouveau/core/engine/disp/outp.h
deleted file mode 100644
index 187f435ad0e2..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/outp.h
+++ /dev/null
@@ -1,60 +0,0 @@
-#ifndef __NVKM_DISP_OUTP_H__
-#define __NVKM_DISP_OUTP_H__
-
-#include "priv.h"
-
-struct nvkm_output {
-	struct nouveau_object base;
-	struct list_head head;
-
-	struct dcb_output info;
-	int index;
-	int or;
-
-	struct nouveau_i2c_port *port;
-	struct nouveau_i2c_port *edid;
-
-	struct nvkm_connector *conn;
-};
-
-#define nvkm_output_create(p,e,c,b,i,d)                                        \
-	nvkm_output_create_((p), (e), (c), (b), (i), sizeof(**d), (void **)d)
-#define nvkm_output_destroy(d) ({                                              \
-	struct nvkm_output *_outp = (d);                                       \
-	_nvkm_output_dtor(nv_object(_outp));                                   \
-})
-#define nvkm_output_init(d) ({                                                 \
-	struct nvkm_output *_outp = (d);                                       \
-	_nvkm_output_init(nv_object(_outp));                                   \
-})
-#define nvkm_output_fini(d,s) ({                                               \
-	struct nvkm_output *_outp = (d);                                       \
-	_nvkm_output_fini(nv_object(_outp), (s));                              \
-})
-
-int nvkm_output_create_(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, struct dcb_output *,
-			int, int, void **);
-
-int  _nvkm_output_ctor(struct nouveau_object *, struct nouveau_object *,
-		       struct nouveau_oclass *, void *, u32,
-		       struct nouveau_object **);
-void _nvkm_output_dtor(struct nouveau_object *);
-int  _nvkm_output_init(struct nouveau_object *);
-int  _nvkm_output_fini(struct nouveau_object *, bool);
-
-struct nvkm_output_impl {
-	struct nouveau_oclass base;
-};
-
-#ifndef MSG
-#define MSG(l,f,a...) do {                                                     \
-	struct nvkm_output *_outp = (void *)outp;                              \
-	nv_##l(nv_object(outp)->engine, "%02x:%04x:%04x: "f, _outp->index,     \
-	       _outp->info.hasht, _outp->info.hashm, ##a);                     \
-} while(0)
-#define DBG(f,a...) MSG(debug, f, ##a)
-#define ERR(f,a...) MSG(error, f, ##a)
-#endif
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c b/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c
deleted file mode 100644
index 667a9070e006..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/os.h>
-#include <nvif/event.h>
-
-#include <subdev/i2c.h>
-
-#include "outpdp.h"
-#include "conn.h"
-#include "dport.h"
-
-int
-nvkm_output_dp_train(struct nvkm_output *base, u32 datarate, bool wait)
-{
-	struct nvkm_output_dp *outp = (void *)base;
-	bool retrain = true;
-	u8 link[2], stat[3];
-	u32 linkrate;
-	int ret, i;
-
-	/* check that the link is trained at a high enough rate */
-	ret = nv_rdaux(outp->base.edid, DPCD_LC00_LINK_BW_SET, link, 2);
-	if (ret) {
-		DBG("failed to read link config, assuming no sink\n");
-		goto done;
-	}
-
-	linkrate = link[0] * 27000 * (link[1] & DPCD_LC01_LANE_COUNT_SET);
-	linkrate = (linkrate * 8) / 10; /* 8B/10B coding overhead */
-	datarate = (datarate + 9) / 10; /* -> decakilobits */
-	if (linkrate < datarate) {
-		DBG("link not trained at sufficient rate\n");
-		goto done;
-	}
-
-	/* check that link is still trained */
-	ret = nv_rdaux(outp->base.edid, DPCD_LS02, stat, 3);
-	if (ret) {
-		DBG("failed to read link status, assuming no sink\n");
-		goto done;
-	}
-
-	if (stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE) {
-		for (i = 0; i < (link[1] & DPCD_LC01_LANE_COUNT_SET); i++) {
-			u8 lane = (stat[i >> 1] >> ((i & 1) * 4)) & 0x0f;
-			if (!(lane & DPCD_LS02_LANE0_CR_DONE) ||
-			    !(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) ||
-			    !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) {
-				DBG("lane %d not equalised\n", lane);
-				goto done;
-			}
-		}
-		retrain = false;
-	} else {
-		DBG("no inter-lane alignment\n");
-	}
-
-done:
-	if (retrain || !atomic_read(&outp->lt.done)) {
-		/* no sink, but still need to configure source */
-		if (outp->dpcd[DPCD_RC00_DPCD_REV] == 0x00) {
-			outp->dpcd[DPCD_RC01_MAX_LINK_RATE] =
-				outp->base.info.dpconf.link_bw;
-			outp->dpcd[DPCD_RC02] =
-				outp->base.info.dpconf.link_nr;
-		}
-		atomic_set(&outp->lt.done, 0);
-		schedule_work(&outp->lt.work);
-	} else {
-		nvkm_notify_get(&outp->irq);
-	}
-
-	if (wait) {
-		if (!wait_event_timeout(outp->lt.wait,
-					atomic_read(&outp->lt.done),
-					msecs_to_jiffies(2000)))
-			ret = -ETIMEDOUT;
-	}
-
-	return ret;
-}
-
-static void
-nvkm_output_dp_enable(struct nvkm_output_dp *outp, bool present)
-{
-	struct nouveau_i2c_port *port = outp->base.edid;
-	if (present) {
-		if (!outp->present) {
-			nouveau_i2c(port)->acquire_pad(port, 0);
-			DBG("aux power -> always\n");
-			outp->present = true;
-		}
-		nvkm_output_dp_train(&outp->base, 0, true);
-	} else {
-		if (outp->present) {
-			nouveau_i2c(port)->release_pad(port);
-			DBG("aux power -> demand\n");
-			outp->present = false;
-		}
-		atomic_set(&outp->lt.done, 0);
-	}
-}
-
-static void
-nvkm_output_dp_detect(struct nvkm_output_dp *outp)
-{
-	struct nouveau_i2c_port *port = outp->base.edid;
-	int ret = nouveau_i2c(port)->acquire_pad(port, 0);
-	if (ret == 0) {
-		ret = nv_rdaux(outp->base.edid, DPCD_RC00_DPCD_REV,
-			       outp->dpcd, sizeof(outp->dpcd));
-		nvkm_output_dp_enable(outp, ret == 0);
-		nouveau_i2c(port)->release_pad(port);
-	}
-}
-
-static int
-nvkm_output_dp_hpd(struct nvkm_notify *notify)
-{
-	struct nvkm_connector *conn = container_of(notify, typeof(*conn), hpd);
-	struct nvkm_output_dp *outp;
-	struct nouveau_disp *disp = nouveau_disp(conn);
-	const struct nvkm_i2c_ntfy_rep *line = notify->data;
-	struct nvif_notify_conn_rep_v0 rep = {};
-
-	list_for_each_entry(outp, &disp->outp, base.head) {
-		if (outp->base.conn == conn &&
-		    outp->info.type == DCB_OUTPUT_DP) {
-			DBG("HPD: %d\n", line->mask);
-			nvkm_output_dp_detect(outp);
-
-			if (line->mask & NVKM_I2C_UNPLUG)
-				rep.mask |= NVIF_NOTIFY_CONN_V0_UNPLUG;
-			if (line->mask & NVKM_I2C_PLUG)
-				rep.mask |= NVIF_NOTIFY_CONN_V0_PLUG;
-
-			nvkm_event_send(&disp->hpd, rep.mask, conn->index,
-					&rep, sizeof(rep));
-			return NVKM_NOTIFY_KEEP;
-		}
-	}
-
-	WARN_ON(1);
-	return NVKM_NOTIFY_DROP;
-}
-
-static int
-nvkm_output_dp_irq(struct nvkm_notify *notify)
-{
-	struct nvkm_output_dp *outp = container_of(notify, typeof(*outp), irq);
-	struct nouveau_disp *disp = nouveau_disp(outp);
-	const struct nvkm_i2c_ntfy_rep *line = notify->data;
-	struct nvif_notify_conn_rep_v0 rep = {
-		.mask = NVIF_NOTIFY_CONN_V0_IRQ,
-	};
-	int index = outp->base.info.connector;
-
-	DBG("IRQ: %d\n", line->mask);
-	nvkm_output_dp_train(&outp->base, 0, true);
-
-	nvkm_event_send(&disp->hpd, rep.mask, index, &rep, sizeof(rep));
-	return NVKM_NOTIFY_DROP;
-}
-
-int
-_nvkm_output_dp_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nvkm_output_dp *outp = (void *)object;
-	nvkm_notify_put(&outp->irq);
-	nvkm_output_dp_enable(outp, false);
-	return nvkm_output_fini(&outp->base, suspend);
-}
-
-int
-_nvkm_output_dp_init(struct nouveau_object *object)
-{
-	struct nvkm_output_dp *outp = (void *)object;
-	nvkm_output_dp_detect(outp);
-	return nvkm_output_init(&outp->base);
-}
-
-void
-_nvkm_output_dp_dtor(struct nouveau_object *object)
-{
-	struct nvkm_output_dp *outp = (void *)object;
-	nvkm_notify_fini(&outp->irq);
-	nvkm_output_destroy(&outp->base);
-}
-
-int
-nvkm_output_dp_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass,
-		       struct dcb_output *info, int index,
-		       int length, void **pobject)
-{
-	struct nouveau_bios *bios = nouveau_bios(parent);
-	struct nouveau_i2c *i2c = nouveau_i2c(parent);
-	struct nvkm_output_dp *outp;
-	u8  hdr, cnt, len;
-	u32 data;
-	int ret;
-
-	ret = nvkm_output_create_(parent, engine, oclass, info, index,
-				  length, pobject);
-	outp = *pobject;
-	if (ret)
-		return ret;
-
-	nvkm_notify_fini(&outp->base.conn->hpd);
-
-	/* access to the aux channel is not optional... */
-	if (!outp->base.edid) {
-		ERR("aux channel not found\n");
-		return -ENODEV;
-	}
-
-	/* nor is the bios data for this output... */
-	data = nvbios_dpout_match(bios, outp->base.info.hasht,
-				  outp->base.info.hashm, &outp->version,
-				  &hdr, &cnt, &len, &outp->info);
-	if (!data) {
-		ERR("no bios dp data\n");
-		return -ENODEV;
-	}
-
-	DBG("bios dp %02x %02x %02x %02x\n", outp->version, hdr, cnt, len);
-
-	/* link training */
-	INIT_WORK(&outp->lt.work, nouveau_dp_train);
-	init_waitqueue_head(&outp->lt.wait);
-	atomic_set(&outp->lt.done, 0);
-
-	/* link maintenance */
-	ret = nvkm_notify_init(NULL, &i2c->event, nvkm_output_dp_irq, true,
-			       &(struct nvkm_i2c_ntfy_req) {
-				.mask = NVKM_I2C_IRQ,
-				.port = outp->base.edid->index,
-			       },
-			       sizeof(struct nvkm_i2c_ntfy_req),
-			       sizeof(struct nvkm_i2c_ntfy_rep),
-			       &outp->irq);
-	if (ret) {
-		ERR("error monitoring aux irq event: %d\n", ret);
-		return ret;
-	}
-
-	/* hotplug detect, replaces gpio-based mechanism with aux events */
-	ret = nvkm_notify_init(NULL, &i2c->event, nvkm_output_dp_hpd, true,
-			       &(struct nvkm_i2c_ntfy_req) {
-				.mask = NVKM_I2C_PLUG | NVKM_I2C_UNPLUG,
-				.port = outp->base.edid->index,
-			       },
-			       sizeof(struct nvkm_i2c_ntfy_req),
-			       sizeof(struct nvkm_i2c_ntfy_rep),
-			       &outp->base.conn->hpd);
-	if (ret) {
-		ERR("error monitoring aux hpd events: %d\n", ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-int
-_nvkm_output_dp_ctor(struct nouveau_object *parent,
-		     struct nouveau_object *engine,
-		     struct nouveau_oclass *oclass, void *info, u32 index,
-		     struct nouveau_object **pobject)
-{
-	struct nvkm_output_dp *outp;
-	int ret;
-
-	ret = nvkm_output_dp_create(parent, engine, oclass, info, index, &outp);
-	*pobject = nv_object(outp);
-	if (ret)
-		return ret;
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.h b/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.h
deleted file mode 100644
index 1fac367cc867..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.h
+++ /dev/null
@@ -1,62 +0,0 @@
-#ifndef __NVKM_DISP_OUTP_DP_H__
-#define __NVKM_DISP_OUTP_DP_H__
-
-#include <subdev/bios.h>
-#include <subdev/bios/dp.h>
-
-#include "outp.h"
-
-struct nvkm_output_dp {
-	struct nvkm_output base;
-
-	struct nvbios_dpout info;
-	u8 version;
-
-	struct nvkm_notify irq;
-	bool present;
-	u8 dpcd[16];
-
-	struct {
-		struct work_struct work;
-		wait_queue_head_t wait;
-		atomic_t done;
-	} lt;
-};
-
-#define nvkm_output_dp_create(p,e,c,b,i,d)                                     \
-	nvkm_output_dp_create_((p), (e), (c), (b), (i), sizeof(**d), (void **)d)
-#define nvkm_output_dp_destroy(d) ({                                           \
-	struct nvkm_output_dp *_outp = (d);                                    \
-	_nvkm_output_dp_dtor(nv_object(_outp));                                \
-})
-#define nvkm_output_dp_init(d) ({                                              \
-	struct nvkm_output_dp *_outp = (d);                                    \
-	_nvkm_output_dp_init(nv_object(_outp));                                \
-})
-#define nvkm_output_dp_fini(d,s) ({                                            \
-	struct nvkm_output_dp *_outp = (d);                                    \
-	_nvkm_output_dp_fini(nv_object(_outp), (s));                           \
-})
-
-int nvkm_output_dp_create_(struct nouveau_object *, struct nouveau_object *,
-			   struct nouveau_oclass *, struct dcb_output *,
-			   int, int, void **);
-
-int  _nvkm_output_dp_ctor(struct nouveau_object *, struct nouveau_object *,
-			  struct nouveau_oclass *, void *, u32,
-			  struct nouveau_object **);
-void _nvkm_output_dp_dtor(struct nouveau_object *);
-int  _nvkm_output_dp_init(struct nouveau_object *);
-int  _nvkm_output_dp_fini(struct nouveau_object *, bool);
-
-struct nvkm_output_dp_impl {
-	struct nvkm_output_impl base;
-	int (*pattern)(struct nvkm_output_dp *, int);
-	int (*lnk_pwr)(struct nvkm_output_dp *, int nr);
-	int (*lnk_ctl)(struct nvkm_output_dp *, int nr, int bw, bool ef);
-	int (*drv_ctl)(struct nvkm_output_dp *, int ln, int vs, int pe, int pc);
-};
-
-int nvkm_output_dp_train(struct nvkm_output *, u32 rate, bool wait);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/piornv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/piornv50.c
deleted file mode 100644
index d00f89a468a7..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/piornv50.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/timer.h>
-#include <subdev/i2c.h>
-
-#include "nv50.h"
-
-/******************************************************************************
- * TMDS
- *****************************************************************************/
-
-static int
-nv50_pior_tmds_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *info, u32 index,
-		    struct nouveau_object **pobject)
-{
-	struct nouveau_i2c *i2c = nouveau_i2c(parent);
-	struct nvkm_output *outp;
-	int ret;
-
-	ret = nvkm_output_create(parent, engine, oclass, info, index, &outp);
-	*pobject = nv_object(outp);
-	if (ret)
-		return ret;
-
-	outp->edid = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(outp->info.extdev));
-	return 0;
-}
-
-struct nvkm_output_impl
-nv50_pior_tmds_impl = {
-	.base.handle = DCB_OUTPUT_TMDS | 0x0100,
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_pior_tmds_ctor,
-		.dtor = _nvkm_output_dtor,
-		.init = _nvkm_output_init,
-		.fini = _nvkm_output_fini,
-	},
-};
-
-/******************************************************************************
- * DisplayPort
- *****************************************************************************/
-
-static int
-nv50_pior_dp_pattern(struct nvkm_output_dp *outp, int pattern)
-{
-	struct nouveau_i2c_port *port = outp->base.edid;
-	if (port && port->func->pattern)
-		return port->func->pattern(port, pattern);
-	return port ? 0 : -ENODEV;
-}
-
-static int
-nv50_pior_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
-{
-	return 0;
-}
-
-static int
-nv50_pior_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
-{
-	struct nouveau_i2c_port *port = outp->base.edid;
-	if (port && port->func->lnk_ctl)
-		return port->func->lnk_ctl(port, nr, bw, ef);
-	return port ? 0 : -ENODEV;
-}
-
-static int
-nv50_pior_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
-{
-	struct nouveau_i2c_port *port = outp->base.edid;
-	if (port && port->func->drv_ctl)
-		return port->func->drv_ctl(port, ln, vs, pe);
-	return port ? 0 : -ENODEV;
-}
-
-static int
-nv50_pior_dp_ctor(struct nouveau_object *parent,
-		  struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *info, u32 index,
-		  struct nouveau_object **pobject)
-{
-	struct nouveau_i2c *i2c = nouveau_i2c(parent);
-	struct nvkm_output_dp *outp;
-	int ret;
-
-	ret = nvkm_output_dp_create(parent, engine, oclass, info, index, &outp);
-	*pobject = nv_object(outp);
-	if (ret)
-		return ret;
-
-	outp->base.edid = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(
-					 outp->base.info.extdev));
-	return 0;
-}
-
-struct nvkm_output_dp_impl
-nv50_pior_dp_impl = {
-	.base.base.handle = DCB_OUTPUT_DP | 0x0010,
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_pior_dp_ctor,
-		.dtor = _nvkm_output_dp_dtor,
-		.init = _nvkm_output_dp_init,
-		.fini = _nvkm_output_dp_fini,
-	},
-	.pattern = nv50_pior_dp_pattern,
-	.lnk_pwr = nv50_pior_dp_lnk_pwr,
-	.lnk_ctl = nv50_pior_dp_lnk_ctl,
-	.drv_ctl = nv50_pior_dp_drv_ctl,
-};
-
-/******************************************************************************
- * General PIOR handling
- *****************************************************************************/
-
-int
-nv50_pior_power(NV50_DISP_MTHD_V1)
-{
-	const u32 soff = outp->or * 0x800;
-	union {
-		struct nv50_disp_pior_pwr_v0 v0;
-	} *args = data;
-	u32 ctrl, type;
-	int ret;
-
-	nv_ioctl(object, "disp pior pwr size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "disp pior pwr vers %d state %d type %x\n",
-			 args->v0.version, args->v0.state, args->v0.type);
-		if (args->v0.type > 0x0f)
-			return -EINVAL;
-		ctrl = !!args->v0.state;
-		type = args->v0.type;
-	} else
-		return ret;
-
-	nv_wait(priv, 0x61e004 + soff, 0x80000000, 0x00000000);
-	nv_mask(priv, 0x61e004 + soff, 0x80000101, 0x80000000 | ctrl);
-	nv_wait(priv, 0x61e004 + soff, 0x80000000, 0x00000000);
-	priv->pior.type[outp->or] = type;
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/priv.h b/drivers/gpu/drm/nouveau/core/engine/disp/priv.h
deleted file mode 100644
index 6a0511d54ce6..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/priv.h
+++ /dev/null
@@ -1,48 +0,0 @@
-#ifndef __NVKM_DISP_PRIV_H__
-#define __NVKM_DISP_PRIV_H__
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/conn.h>
-
-#include <engine/disp.h>
-
-struct nouveau_disp_impl {
-	struct nouveau_oclass base;
-	struct nouveau_oclass **outp;
-	struct nouveau_oclass **conn;
-	const struct nvkm_event_func *vblank;
-};
-
-#define nouveau_disp_create(p,e,c,h,i,x,d)                                     \
-	nouveau_disp_create_((p), (e), (c), (h), (i), (x),                     \
-			     sizeof(**d), (void **)d)
-#define nouveau_disp_destroy(d) ({                                             \
-	struct nouveau_disp *disp = (d);                                       \
-	_nouveau_disp_dtor(nv_object(disp));                                   \
-})
-#define nouveau_disp_init(d) ({                                                \
-	struct nouveau_disp *disp = (d);                                       \
-	_nouveau_disp_init(nv_object(disp));                                   \
-})
-#define nouveau_disp_fini(d,s) ({                                              \
-	struct nouveau_disp *disp = (d);                                       \
-	_nouveau_disp_fini(nv_object(disp), (s));                              \
-})
-
-int  nouveau_disp_create_(struct nouveau_object *, struct nouveau_object *,
-			  struct nouveau_oclass *, int heads,
-			  const char *, const char *, int, void **);
-void _nouveau_disp_dtor(struct nouveau_object *);
-int  _nouveau_disp_init(struct nouveau_object *);
-int  _nouveau_disp_fini(struct nouveau_object *, bool);
-
-extern struct nouveau_oclass *nvkm_output_oclass;
-extern struct nouveau_oclass *nvkm_connector_oclass;
-
-int  nouveau_disp_vblank_ctor(struct nouveau_object *, void *data, u32 size,
-			      struct nvkm_notify *);
-void nouveau_disp_vblank(struct nouveau_disp *, int head);
-int  nouveau_disp_ntfy(struct nouveau_object *, u32, struct nvkm_event **);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sorgm204.c b/drivers/gpu/drm/nouveau/core/engine/disp/sorgm204.c
deleted file mode 100644
index 0b4fad39e9a6..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/sorgm204.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/os.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/dp.h>
-#include <subdev/bios/init.h>
-#include <subdev/timer.h>
-
-#include "nv50.h"
-
-static inline u32
-gm204_sor_soff(struct nvkm_output_dp *outp)
-{
-	return (ffs(outp->base.info.or) - 1) * 0x800;
-}
-
-static inline u32
-gm204_sor_loff(struct nvkm_output_dp *outp)
-{
-	return gm204_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
-}
-
-void
-gm204_sor_magic(struct nvkm_output *outp)
-{
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	const u32 soff = outp->or * 0x100;
-	const u32 data = outp->or + 1;
-	if (outp->info.sorconf.link & 1)
-		nv_mask(priv, 0x612308 + soff, 0x0000001f, 0x00000000 | data);
-	if (outp->info.sorconf.link & 2)
-		nv_mask(priv, 0x612388 + soff, 0x0000001f, 0x00000010 | data);
-}
-
-static inline u32
-gm204_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
-{
-	return lane * 0x08;
-}
-
-static int
-gm204_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
-{
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	const u32 soff = gm204_sor_soff(outp);
-	const u32 data = 0x01010101 * pattern;
-	if (outp->base.info.sorconf.link & 1)
-		nv_mask(priv, 0x61c110 + soff, 0x0f0f0f0f, data);
-	else
-		nv_mask(priv, 0x61c12c + soff, 0x0f0f0f0f, data);
-	return 0;
-}
-
-static int
-gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
-{
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	const u32 soff = gm204_sor_soff(outp);
-	const u32 loff = gm204_sor_loff(outp);
-	u32 mask = 0, i;
-
-	for (i = 0; i < nr; i++)
-		mask |= 1 << (gm204_sor_dp_lane_map(priv, i) >> 3);
-
-	nv_mask(priv, 0x61c130 + loff, 0x0000000f, mask);
-	nv_mask(priv, 0x61c034 + soff, 0x80000000, 0x80000000);
-	nv_wait(priv, 0x61c034 + soff, 0x80000000, 0x00000000);
-	return 0;
-}
-
-static int
-gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
-{
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	const u32 shift = gm204_sor_dp_lane_map(priv, ln);
-	const u32 loff = gm204_sor_loff(outp);
-	u32 addr, data[4];
-	u8  ver, hdr, cnt, len;
-	struct nvbios_dpout info;
-	struct nvbios_dpcfg ocfg;
-
-	addr = nvbios_dpout_match(bios, outp->base.info.hasht,
-					outp->base.info.hashm,
-				 &ver, &hdr, &cnt, &len, &info);
-	if (!addr)
-		return -ENODEV;
-
-	addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe,
-				 &ver, &hdr, &cnt, &len, &ocfg);
-	if (!addr)
-		return -EINVAL;
-
-	data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift);
-	data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift);
-	data[2] = nv_rd32(priv, 0x61c130 + loff);
-	if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0)
-		data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8);
-	nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
-	nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
-	nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.tx_pu << 8));
-	data[3] = nv_rd32(priv, 0x61c13c + loff) & ~(0x000000ff << shift);
-	nv_wr32(priv, 0x61c13c + loff, data[3] | (ocfg.pc << shift));
-	return 0;
-}
-
-struct nvkm_output_dp_impl
-gm204_sor_dp_impl = {
-	.base.base.handle = DCB_OUTPUT_DP,
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nvkm_output_dp_ctor,
-		.dtor = _nvkm_output_dp_dtor,
-		.init = _nvkm_output_dp_init,
-		.fini = _nvkm_output_dp_fini,
-	},
-	.pattern = gm204_sor_dp_pattern,
-	.lnk_pwr = gm204_sor_dp_lnk_pwr,
-	.lnk_ctl = nvd0_sor_dp_lnk_ctl,
-	.drv_ctl = gm204_sor_dp_drv_ctl,
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
deleted file mode 100644
index ddf1760c4400..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/timer.h>
-
-#include "nv50.h"
-
-int
-nv50_sor_power(NV50_DISP_MTHD_V1)
-{
-	union {
-		struct nv50_disp_sor_pwr_v0 v0;
-	} *args = data;
-	const u32 soff = outp->or * 0x800;
-	u32 stat;
-	int ret;
-
-	nv_ioctl(object, "disp sor pwr size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "disp sor pwr vers %d state %d\n",
-			 args->v0.version, args->v0.state);
-		stat = !!args->v0.state;
-	} else
-		return ret;
-
-	nv_wait(priv, 0x61c004 + soff, 0x80000000, 0x00000000);
-	nv_mask(priv, 0x61c004 + soff, 0x80000001, 0x80000000 | stat);
-	nv_wait(priv, 0x61c004 + soff, 0x80000000, 0x00000000);
-	nv_wait(priv, 0x61c030 + soff, 0x10000000, 0x00000000);
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c
deleted file mode 100644
index 39f85d627336..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/os.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/dp.h>
-#include <subdev/bios/init.h>
-#include <subdev/timer.h>
-
-#include "nv50.h"
-#include "outpdp.h"
-
-static inline u32
-nv94_sor_soff(struct nvkm_output_dp *outp)
-{
-	return (ffs(outp->base.info.or) - 1) * 0x800;
-}
-
-static inline u32
-nv94_sor_loff(struct nvkm_output_dp *outp)
-{
-	return nv94_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
-}
-
-static inline u32
-nv94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
-{
-	static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
-	static const u8 nv94[] = { 16, 8, 0, 24 };
-	if (nv_device(priv)->chipset == 0xaf)
-		return nvaf[lane];
-	return nv94[lane];
-}
-
-static int
-nv94_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
-{
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	const u32 loff = nv94_sor_loff(outp);
-	nv_mask(priv, 0x61c10c + loff, 0x0f000000, pattern << 24);
-	return 0;
-}
-
-int
-nv94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
-{
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	const u32 soff = nv94_sor_soff(outp);
-	const u32 loff = nv94_sor_loff(outp);
-	u32 mask = 0, i;
-
-	for (i = 0; i < nr; i++)
-		mask |= 1 << (nv94_sor_dp_lane_map(priv, i) >> 3);
-
-	nv_mask(priv, 0x61c130 + loff, 0x0000000f, mask);
-	nv_mask(priv, 0x61c034 + soff, 0x80000000, 0x80000000);
-	nv_wait(priv, 0x61c034 + soff, 0x80000000, 0x00000000);
-	return 0;
-}
-
-static int
-nv94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
-{
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	const u32 soff = nv94_sor_soff(outp);
-	const u32 loff = nv94_sor_loff(outp);
-	u32 dpctrl = 0x00000000;
-	u32 clksor = 0x00000000;
-
-	dpctrl |= ((1 << nr) - 1) << 16;
-	if (ef)
-		dpctrl |= 0x00004000;
-	if (bw > 0x06)
-		clksor |= 0x00040000;
-
-	nv_mask(priv, 0x614300 + soff, 0x000c0000, clksor);
-	nv_mask(priv, 0x61c10c + loff, 0x001f4000, dpctrl);
-	return 0;
-}
-
-static int
-nv94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
-{
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	const u32 shift = nv94_sor_dp_lane_map(priv, ln);
-	const u32 loff = nv94_sor_loff(outp);
-	u32 addr, data[3];
-	u8  ver, hdr, cnt, len;
-	struct nvbios_dpout info;
-	struct nvbios_dpcfg ocfg;
-
-	addr = nvbios_dpout_match(bios, outp->base.info.hasht,
-					outp->base.info.hashm,
-				 &ver, &hdr, &cnt, &len, &info);
-	if (!addr)
-		return -ENODEV;
-
-	addr = nvbios_dpcfg_match(bios, addr, 0, vs, pe,
-				 &ver, &hdr, &cnt, &len, &ocfg);
-	if (!addr)
-		return -EINVAL;
-
-	data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift);
-	data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift);
-	data[2] = nv_rd32(priv, 0x61c130 + loff);
-	if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0)
-		data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8);
-	nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
-	nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
-	nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.tx_pu << 8));
-	return 0;
-}
-
-struct nvkm_output_dp_impl
-nv94_sor_dp_impl = {
-	.base.base.handle = DCB_OUTPUT_DP,
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nvkm_output_dp_ctor,
-		.dtor = _nvkm_output_dp_dtor,
-		.init = _nvkm_output_dp_init,
-		.fini = _nvkm_output_dp_fini,
-	},
-	.pattern = nv94_sor_dp_pattern,
-	.lnk_pwr = nv94_sor_dp_lnk_pwr,
-	.lnk_ctl = nv94_sor_dp_lnk_ctl,
-	.drv_ctl = nv94_sor_dp_drv_ctl,
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c
deleted file mode 100644
index fdab2939070c..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/os.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/dp.h>
-#include <subdev/bios/init.h>
-#include <subdev/timer.h>
-
-#include "nv50.h"
-
-static inline u32
-nvd0_sor_soff(struct nvkm_output_dp *outp)
-{
-	return (ffs(outp->base.info.or) - 1) * 0x800;
-}
-
-static inline u32
-nvd0_sor_loff(struct nvkm_output_dp *outp)
-{
-	return nvd0_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
-}
-
-static inline u32
-nvd0_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
-{
-	static const u8 nvd0[] = { 16, 8, 0, 24 };
-	return nvd0[lane];
-}
-
-static int
-nvd0_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
-{
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	const u32 loff = nvd0_sor_loff(outp);
-	nv_mask(priv, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern);
-	return 0;
-}
-
-int
-nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
-{
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	const u32 soff = nvd0_sor_soff(outp);
-	const u32 loff = nvd0_sor_loff(outp);
-	u32 dpctrl = 0x00000000;
-	u32 clksor = 0x00000000;
-
-	clksor |= bw << 18;
-	dpctrl |= ((1 << nr) - 1) << 16;
-	if (ef)
-		dpctrl |= 0x00004000;
-
-	nv_mask(priv, 0x612300 + soff, 0x007c0000, clksor);
-	nv_mask(priv, 0x61c10c + loff, 0x001f4000, dpctrl);
-	return 0;
-}
-
-static int
-nvd0_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
-{
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	const u32 shift = nvd0_sor_dp_lane_map(priv, ln);
-	const u32 loff = nvd0_sor_loff(outp);
-	u32 addr, data[4];
-	u8  ver, hdr, cnt, len;
-	struct nvbios_dpout info;
-	struct nvbios_dpcfg ocfg;
-
-	addr = nvbios_dpout_match(bios, outp->base.info.hasht,
-					outp->base.info.hashm,
-				 &ver, &hdr, &cnt, &len, &info);
-	if (!addr)
-		return -ENODEV;
-
-	addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe,
-				 &ver, &hdr, &cnt, &len, &ocfg);
-	if (!addr)
-		return -EINVAL;
-
-	data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift);
-	data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift);
-	data[2] = nv_rd32(priv, 0x61c130 + loff);
-	if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0)
-		data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8);
-	nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
-	nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
-	nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.tx_pu << 8));
-	data[3] = nv_rd32(priv, 0x61c13c + loff) & ~(0x000000ff << shift);
-	nv_wr32(priv, 0x61c13c + loff, data[3] | (ocfg.pc << shift));
-	return 0;
-}
-
-struct nvkm_output_dp_impl
-nvd0_sor_dp_impl = {
-	.base.base.handle = DCB_OUTPUT_DP,
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nvkm_output_dp_ctor,
-		.dtor = _nvkm_output_dp_dtor,
-		.init = _nvkm_output_dp_init,
-		.fini = _nvkm_output_dp_fini,
-	},
-	.pattern = nvd0_sor_dp_pattern,
-	.lnk_pwr = nv94_sor_dp_lnk_pwr,
-	.lnk_ctl = nvd0_sor_dp_lnk_ctl,
-	.drv_ctl = nvd0_sor_dp_drv_ctl,
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/vga.c b/drivers/gpu/drm/nouveau/core/engine/disp/vga.c
deleted file mode 100644
index 8836c3cb99c3..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/disp/vga.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/subdev.h>
-#include <core/device.h>
-#include <subdev/vga.h>
-
-u8
-nv_rdport(void *obj, int head, u16 port)
-{
-	struct nouveau_device *device = nv_device(obj);
-
-	if (device->card_type >= NV_50)
-		return nv_rd08(obj, 0x601000 + port);
-
-	if (port == 0x03c0 || port == 0x03c1 ||	/* AR */
-	    port == 0x03c2 || port == 0x03da ||	/* INP0 */
-	    port == 0x03d4 || port == 0x03d5)	/* CR */
-		return nv_rd08(obj, 0x601000 + (head * 0x2000) + port);
-
-	if (port == 0x03c2 || port == 0x03cc ||	/* MISC */
-	    port == 0x03c4 || port == 0x03c5 ||	/* SR */
-	    port == 0x03ce || port == 0x03cf) {	/* GR */
-		if (device->card_type < NV_40)
-			head = 0; /* CR44 selects head */
-		return nv_rd08(obj, 0x0c0000 + (head * 0x2000) + port);
-	}
-
-	nv_error(obj, "unknown vga port 0x%04x\n", port);
-	return 0x00;
-}
-
-void
-nv_wrport(void *obj, int head, u16 port, u8 data)
-{
-	struct nouveau_device *device = nv_device(obj);
-
-	if (device->card_type >= NV_50)
-		nv_wr08(obj, 0x601000 + port, data);
-	else
-	if (port == 0x03c0 || port == 0x03c1 ||	/* AR */
-	    port == 0x03c2 || port == 0x03da ||	/* INP0 */
-	    port == 0x03d4 || port == 0x03d5)	/* CR */
-		nv_wr08(obj, 0x601000 + (head * 0x2000) + port, data);
-	else
-	if (port == 0x03c2 || port == 0x03cc ||	/* MISC */
-	    port == 0x03c4 || port == 0x03c5 ||	/* SR */
-	    port == 0x03ce || port == 0x03cf) {	/* GR */
-		if (device->card_type < NV_40)
-			head = 0; /* CR44 selects head */
-		nv_wr08(obj, 0x0c0000 + (head * 0x2000) + port, data);
-	} else
-		nv_error(obj, "unknown vga port 0x%04x\n", port);
-}
-
-u8
-nv_rdvgas(void *obj, int head, u8 index)
-{
-	nv_wrport(obj, head, 0x03c4, index);
-	return nv_rdport(obj, head, 0x03c5);
-}
-
-void
-nv_wrvgas(void *obj, int head, u8 index, u8 value)
-{
-	nv_wrport(obj, head, 0x03c4, index);
-	nv_wrport(obj, head, 0x03c5, value);
-}
-
-u8
-nv_rdvgag(void *obj, int head, u8 index)
-{
-	nv_wrport(obj, head, 0x03ce, index);
-	return nv_rdport(obj, head, 0x03cf);
-}
-
-void
-nv_wrvgag(void *obj, int head, u8 index, u8 value)
-{
-	nv_wrport(obj, head, 0x03ce, index);
-	nv_wrport(obj, head, 0x03cf, value);
-}
-
-u8
-nv_rdvgac(void *obj, int head, u8 index)
-{
-	nv_wrport(obj, head, 0x03d4, index);
-	return nv_rdport(obj, head, 0x03d5);
-}
-
-void
-nv_wrvgac(void *obj, int head, u8 index, u8 value)
-{
-	nv_wrport(obj, head, 0x03d4, index);
-	nv_wrport(obj, head, 0x03d5, value);
-}
-
-u8
-nv_rdvgai(void *obj, int head, u16 port, u8 index)
-{
-	if (port == 0x03c4) return nv_rdvgas(obj, head, index);
-	if (port == 0x03ce) return nv_rdvgag(obj, head, index);
-	if (port == 0x03d4) return nv_rdvgac(obj, head, index);
-	nv_error(obj, "unknown indexed vga port 0x%04x\n", port);
-	return 0x00;
-}
-
-void
-nv_wrvgai(void *obj, int head, u16 port, u8 index, u8 value)
-{
-	if      (port == 0x03c4) nv_wrvgas(obj, head, index, value);
-	else if (port == 0x03ce) nv_wrvgag(obj, head, index, value);
-	else if (port == 0x03d4) nv_wrvgac(obj, head, index, value);
-	else nv_error(obj, "unknown indexed vga port 0x%04x\n", port);
-}
-
-bool
-nv_lockvgac(void *obj, bool lock)
-{
-	struct nouveau_device *dev = nv_device(obj);
-
-	bool locked = !nv_rdvgac(obj, 0, 0x1f);
-	u8 data = lock ? 0x99 : 0x57;
-	if (dev->card_type < NV_50)
-		nv_wrvgac(obj, 0, 0x1f, data);
-	else
-		nv_wrvgac(obj, 0, 0x3f, data);
-	if (dev->chipset == 0x11) {
-		if (!(nv_rd32(obj, 0x001084) & 0x10000000))
-			nv_wrvgac(obj, 1, 0x1f, data);
-	}
-	return locked;
-}
-
-/* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied)
- * it affects only the 8 bit vga io regs, which we access using mmio at
- * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d*
- * in general, the set value of cr44 does not matter: reg access works as
- * expected and values can be set for the appropriate head by using a 0x2000
- * offset as required
- * however:
- * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and
- *    cr44 must be set to 0 or 3 for accessing values on the correct head
- *    through the common 0xc03c* addresses
- * b) in tied mode (4) head B is programmed to the values set on head A, and
- *    access using the head B addresses can have strange results, ergo we leave
- *    tied mode in init once we know to what cr44 should be restored on exit
- *
- * the owner parameter is slightly abused:
- * 0 and 1 are treated as head values and so the set value is (owner * 3)
- * other values are treated as literal values to set
- */
-u8
-nv_rdvgaowner(void *obj)
-{
-	if (nv_device(obj)->card_type < NV_50) {
-		if (nv_device(obj)->chipset == 0x11) {
-			u32 tied = nv_rd32(obj, 0x001084) & 0x10000000;
-			if (tied == 0) {
-				u8 slA = nv_rdvgac(obj, 0, 0x28) & 0x80;
-				u8 tvA = nv_rdvgac(obj, 0, 0x33) & 0x01;
-				u8 slB = nv_rdvgac(obj, 1, 0x28) & 0x80;
-				u8 tvB = nv_rdvgac(obj, 1, 0x33) & 0x01;
-				if (slA && !tvA) return 0x00;
-				if (slB && !tvB) return 0x03;
-				if (slA) return 0x00;
-				if (slB) return 0x03;
-				return 0x00;
-			}
-			return 0x04;
-		}
-
-		return nv_rdvgac(obj, 0, 0x44);
-	}
-
-	nv_error(obj, "rdvgaowner after nv4x\n");
-	return 0x00;
-}
-
-void
-nv_wrvgaowner(void *obj, u8 select)
-{
-	if (nv_device(obj)->card_type < NV_50) {
-		u8 owner = (select == 1) ? 3 : select;
-		if (nv_device(obj)->chipset == 0x11) {
-			/* workaround hw lockup bug */
-			nv_rdvgac(obj, 0, 0x1f);
-			nv_rdvgac(obj, 1, 0x1f);
-		}
-
-		nv_wrvgac(obj, 0, 0x44, owner);
-
-		if (nv_device(obj)->chipset == 0x11) {
-			nv_wrvgac(obj, 0, 0x2e, owner);
-			nv_wrvgac(obj, 0, 0x2e, owner);
-		}
-	} else
-		nv_error(obj, "wrvgaowner after nv4x\n");
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/base.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/base.c
deleted file mode 100644
index e1500f77a56a..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/base.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/object.h>
-#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/fb.h>
-#include <subdev/instmem.h>
-
-#include "priv.h"
-
-static int
-nvkm_dmaobj_bind(struct nouveau_dmaobj *dmaobj, struct nouveau_object *parent,
-		 struct nouveau_gpuobj **pgpuobj)
-{
-	const struct nvkm_dmaeng_impl *impl = (void *)
-		nv_oclass(nv_object(dmaobj)->engine);
-	int ret = 0;
-
-	if (nv_object(dmaobj) == parent) { /* ctor bind */
-		if (nv_mclass(parent->parent) == NV_DEVICE) {
-			/* delayed, or no, binding */
-			return 0;
-		}
-		ret = impl->bind(dmaobj, parent, pgpuobj);
-		if (ret == 0)
-			nouveau_object_ref(NULL, &parent);
-		return ret;
-	}
-
-	return impl->bind(dmaobj, parent, pgpuobj);
-}
-
-int
-nvkm_dmaobj_create_(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void **pdata, u32 *psize,
-		    int length, void **pobject)
-{
-	union {
-		struct nv_dma_v0 v0;
-	} *args = *pdata;
-	struct nouveau_instmem *instmem = nouveau_instmem(parent);
-	struct nouveau_client *client = nouveau_client(parent);
-	struct nouveau_device *device = nv_device(parent);
-	struct nouveau_fb *pfb = nouveau_fb(parent);
-	struct nouveau_dmaobj *dmaobj;
-	void *data = *pdata;
-	u32 size = *psize;
-	int ret;
-
-	ret = nouveau_object_create_(parent, engine, oclass, 0, length, pobject);
-	dmaobj = *pobject;
-	if (ret)
-		return ret;
-
-	nv_ioctl(parent, "create dma size %d\n", *psize);
-	if (nvif_unpack(args->v0, 0, 0, true)) {
-		nv_ioctl(parent, "create dma vers %d target %d access %d "
-				 "start %016llx limit %016llx\n",
-			 args->v0.version, args->v0.target, args->v0.access,
-			 args->v0.start, args->v0.limit);
-		dmaobj->target = args->v0.target;
-		dmaobj->access = args->v0.access;
-		dmaobj->start  = args->v0.start;
-		dmaobj->limit  = args->v0.limit;
-	} else
-		return ret;
-
-	*pdata = data;
-	*psize = size;
-
-	if (dmaobj->start > dmaobj->limit)
-		return -EINVAL;
-
-	switch (dmaobj->target) {
-	case NV_DMA_V0_TARGET_VM:
-		dmaobj->target = NV_MEM_TARGET_VM;
-		break;
-	case NV_DMA_V0_TARGET_VRAM:
-		if (!client->super) {
-			if (dmaobj->limit >= pfb->ram->size - instmem->reserved)
-				return -EACCES;
-			if (device->card_type >= NV_50)
-				return -EACCES;
-		}
-		dmaobj->target = NV_MEM_TARGET_VRAM;
-		break;
-	case NV_DMA_V0_TARGET_PCI:
-		if (!client->super)
-			return -EACCES;
-		dmaobj->target = NV_MEM_TARGET_PCI;
-		break;
-	case NV_DMA_V0_TARGET_PCI_US:
-	case NV_DMA_V0_TARGET_AGP:
-		if (!client->super)
-			return -EACCES;
-		dmaobj->target = NV_MEM_TARGET_PCI_NOSNOOP;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	switch (dmaobj->access) {
-	case NV_DMA_V0_ACCESS_VM:
-		dmaobj->access = NV_MEM_ACCESS_VM;
-		break;
-	case NV_DMA_V0_ACCESS_RD:
-		dmaobj->access = NV_MEM_ACCESS_RO;
-		break;
-	case NV_DMA_V0_ACCESS_WR:
-		dmaobj->access = NV_MEM_ACCESS_WO;
-		break;
-	case NV_DMA_V0_ACCESS_RDWR:
-		dmaobj->access = NV_MEM_ACCESS_RW;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	return ret;
-}
-
-int
-_nvkm_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 size,
-		  struct nouveau_object **pobject)
-{
-	const struct nvkm_dmaeng_impl *impl = (void *)oclass;
-	struct nouveau_dmaeng *dmaeng;
-	int ret;
-
-	ret = nouveau_engine_create(parent, engine, oclass, true, "DMAOBJ",
-				    "dmaobj", &dmaeng);
-	*pobject = nv_object(dmaeng);
-	if (ret)
-		return ret;
-
-	nv_engine(dmaeng)->sclass = impl->sclass;
-	dmaeng->bind = nvkm_dmaobj_bind;
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c
deleted file mode 100644
index 20c9dbfe3b2e..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/gpuobj.h>
-#include <nvif/class.h>
-
-#include <subdev/fb.h>
-#include <subdev/vm/nv04.h>
-
-#include "priv.h"
-
-struct nv04_dmaobj_priv {
-	struct nouveau_dmaobj base;
-	bool clone;
-	u32 flags0;
-	u32 flags2;
-};
-
-static int
-nv04_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
-		 struct nouveau_object *parent,
-		 struct nouveau_gpuobj **pgpuobj)
-{
-	struct nv04_dmaobj_priv *priv = (void *)dmaobj;
-	struct nouveau_gpuobj *gpuobj;
-	u64 offset = priv->base.start & 0xfffff000;
-	u64 adjust = priv->base.start & 0x00000fff;
-	u32 length = priv->base.limit - priv->base.start;
-	int ret;
-
-	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
-		switch (nv_mclass(parent->parent)) {
-		case NV03_CHANNEL_DMA:
-		case NV10_CHANNEL_DMA:
-		case NV17_CHANNEL_DMA:
-		case NV40_CHANNEL_DMA:
-			break;
-		default:
-			return -EINVAL;
-		}
-	}
-
-	if (priv->clone) {
-		struct nv04_vmmgr_priv *vmm = nv04_vmmgr(dmaobj);
-		struct nouveau_gpuobj *pgt = vmm->vm->pgt[0].obj[0];
-		if (!dmaobj->start)
-			return nouveau_gpuobj_dup(parent, pgt, pgpuobj);
-		offset  = nv_ro32(pgt, 8 + (offset >> 10));
-		offset &= 0xfffff000;
-	}
-
-	ret = nouveau_gpuobj_new(parent, parent, 16, 16, 0, &gpuobj);
-	*pgpuobj = gpuobj;
-	if (ret == 0) {
-		nv_wo32(*pgpuobj, 0x00, priv->flags0 | (adjust << 20));
-		nv_wo32(*pgpuobj, 0x04, length);
-		nv_wo32(*pgpuobj, 0x08, priv->flags2 | offset);
-		nv_wo32(*pgpuobj, 0x0c, priv->flags2 | offset);
-	}
-
-	return ret;
-}
-
-static int
-nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		 struct nouveau_oclass *oclass, void *data, u32 size,
-		 struct nouveau_object **pobject)
-{
-	struct nouveau_dmaeng *dmaeng = (void *)engine;
-	struct nv04_vmmgr_priv *vmm = nv04_vmmgr(engine);
-	struct nv04_dmaobj_priv *priv;
-	int ret;
-
-	ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
-	*pobject = nv_object(priv);
-	if (ret || (ret = -ENOSYS, size))
-		return ret;
-
-	if (priv->base.target == NV_MEM_TARGET_VM) {
-		if (nv_object(vmm)->oclass == &nv04_vmmgr_oclass)
-			priv->clone = true;
-		priv->base.target = NV_MEM_TARGET_PCI;
-		priv->base.access = NV_MEM_ACCESS_RW;
-	}
-
-	priv->flags0 = nv_mclass(priv);
-	switch (priv->base.target) {
-	case NV_MEM_TARGET_VRAM:
-		priv->flags0 |= 0x00003000;
-		break;
-	case NV_MEM_TARGET_PCI:
-		priv->flags0 |= 0x00023000;
-		break;
-	case NV_MEM_TARGET_PCI_NOSNOOP:
-		priv->flags0 |= 0x00033000;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	switch (priv->base.access) {
-	case NV_MEM_ACCESS_RO:
-		priv->flags0 |= 0x00004000;
-		break;
-	case NV_MEM_ACCESS_WO:
-		priv->flags0 |= 0x00008000;
-	case NV_MEM_ACCESS_RW:
-		priv->flags2 |= 0x00000002;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
-}
-
-static struct nouveau_ofuncs
-nv04_dmaobj_ofuncs = {
-	.ctor =  nv04_dmaobj_ctor,
-	.dtor = _nvkm_dmaobj_dtor,
-	.init = _nvkm_dmaobj_init,
-	.fini = _nvkm_dmaobj_fini,
-};
-
-static struct nouveau_oclass
-nv04_dmaeng_sclass[] = {
-	{ NV_DMA_FROM_MEMORY, &nv04_dmaobj_ofuncs },
-	{ NV_DMA_TO_MEMORY, &nv04_dmaobj_ofuncs },
-	{ NV_DMA_IN_MEMORY, &nv04_dmaobj_ofuncs },
-	{}
-};
-
-struct nouveau_oclass *
-nv04_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
-	.base.handle = NV_ENGINE(DMAOBJ, 0x04),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nvkm_dmaeng_ctor,
-		.dtor = _nvkm_dmaeng_dtor,
-		.init = _nvkm_dmaeng_init,
-		.fini = _nvkm_dmaeng_fini,
-	},
-	.sclass = nv04_dmaeng_sclass,
-	.bind = nv04_dmaobj_bind,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c
deleted file mode 100644
index a740ddba2ee2..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <core/gpuobj.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/fb.h>
-
-#include "priv.h"
-
-struct nv50_dmaobj_priv {
-	struct nouveau_dmaobj base;
-	u32 flags0;
-	u32 flags5;
-};
-
-static int
-nv50_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
-		 struct nouveau_object *parent,
-		 struct nouveau_gpuobj **pgpuobj)
-{
-	struct nv50_dmaobj_priv *priv = (void *)dmaobj;
-	int ret;
-
-	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
-		switch (nv_mclass(parent->parent)) {
-		case NV40_CHANNEL_DMA:
-		case NV50_CHANNEL_GPFIFO:
-		case G82_CHANNEL_GPFIFO:
-		case NV50_DISP_CORE_CHANNEL_DMA:
-		case G82_DISP_CORE_CHANNEL_DMA:
-		case GT206_DISP_CORE_CHANNEL_DMA:
-		case GT200_DISP_CORE_CHANNEL_DMA:
-		case GT214_DISP_CORE_CHANNEL_DMA:
-		case NV50_DISP_BASE_CHANNEL_DMA:
-		case G82_DISP_BASE_CHANNEL_DMA:
-		case GT200_DISP_BASE_CHANNEL_DMA:
-		case GT214_DISP_BASE_CHANNEL_DMA:
-		case NV50_DISP_OVERLAY_CHANNEL_DMA:
-		case G82_DISP_OVERLAY_CHANNEL_DMA:
-		case GT200_DISP_OVERLAY_CHANNEL_DMA:
-		case GT214_DISP_OVERLAY_CHANNEL_DMA:
-			break;
-		default:
-			return -EINVAL;
-		}
-	}
-
-	ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
-	if (ret == 0) {
-		nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj));
-		nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit));
-		nv_wo32(*pgpuobj, 0x08, lower_32_bits(priv->base.start));
-		nv_wo32(*pgpuobj, 0x0c, upper_32_bits(priv->base.limit) << 24 |
-					upper_32_bits(priv->base.start));
-		nv_wo32(*pgpuobj, 0x10, 0x00000000);
-		nv_wo32(*pgpuobj, 0x14, priv->flags5);
-	}
-
-	return ret;
-}
-
-static int
-nv50_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		 struct nouveau_oclass *oclass, void *data, u32 size,
-		 struct nouveau_object **pobject)
-{
-	struct nouveau_dmaeng *dmaeng = (void *)engine;
-	union {
-		struct nv50_dma_v0 v0;
-	} *args;
-	struct nv50_dmaobj_priv *priv;
-	u32 user, part, comp, kind;
-	int ret;
-
-	ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-	args = data;
-
-	nv_ioctl(parent, "create nv50 dma size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create nv50 dma vers %d priv %d part %d "
-				 "comp %d kind %02x\n", args->v0.version,
-			 args->v0.priv, args->v0.part, args->v0.comp,
-			 args->v0.kind);
-		user = args->v0.priv;
-		part = args->v0.part;
-		comp = args->v0.comp;
-		kind = args->v0.kind;
-	} else
-	if (size == 0) {
-		if (priv->base.target != NV_MEM_TARGET_VM) {
-			user = NV50_DMA_V0_PRIV_US;
-			part = NV50_DMA_V0_PART_256;
-			comp = NV50_DMA_V0_COMP_NONE;
-			kind = NV50_DMA_V0_KIND_PITCH;
-		} else {
-			user = NV50_DMA_V0_PRIV_VM;
-			part = NV50_DMA_V0_PART_VM;
-			comp = NV50_DMA_V0_COMP_VM;
-			kind = NV50_DMA_V0_KIND_VM;
-		}
-	} else
-		return ret;
-
-	if (user > 2 || part > 2 || comp > 3 || kind > 0x7f)
-		return -EINVAL;
-	priv->flags0 = (comp << 29) | (kind << 22) | (user << 20);
-	priv->flags5 = (part << 16);
-
-	switch (priv->base.target) {
-	case NV_MEM_TARGET_VM:
-		priv->flags0 |= 0x00000000;
-		break;
-	case NV_MEM_TARGET_VRAM:
-		priv->flags0 |= 0x00010000;
-		break;
-	case NV_MEM_TARGET_PCI:
-		priv->flags0 |= 0x00020000;
-		break;
-	case NV_MEM_TARGET_PCI_NOSNOOP:
-		priv->flags0 |= 0x00030000;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	switch (priv->base.access) {
-	case NV_MEM_ACCESS_VM:
-		break;
-	case NV_MEM_ACCESS_RO:
-		priv->flags0 |= 0x00040000;
-		break;
-	case NV_MEM_ACCESS_WO:
-	case NV_MEM_ACCESS_RW:
-		priv->flags0 |= 0x00080000;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
-}
-
-static struct nouveau_ofuncs
-nv50_dmaobj_ofuncs = {
-	.ctor =  nv50_dmaobj_ctor,
-	.dtor = _nvkm_dmaobj_dtor,
-	.init = _nvkm_dmaobj_init,
-	.fini = _nvkm_dmaobj_fini,
-};
-
-static struct nouveau_oclass
-nv50_dmaeng_sclass[] = {
-	{ NV_DMA_FROM_MEMORY, &nv50_dmaobj_ofuncs },
-	{ NV_DMA_TO_MEMORY, &nv50_dmaobj_ofuncs },
-	{ NV_DMA_IN_MEMORY, &nv50_dmaobj_ofuncs },
-	{}
-};
-
-struct nouveau_oclass *
-nv50_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
-	.base.handle = NV_ENGINE(DMAOBJ, 0x50),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nvkm_dmaeng_ctor,
-		.dtor = _nvkm_dmaeng_dtor,
-		.init = _nvkm_dmaeng_init,
-		.fini = _nvkm_dmaeng_fini,
-	},
-	.sclass = nv50_dmaeng_sclass,
-	.bind = nv50_dmaobj_bind,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c
deleted file mode 100644
index 88ec33b20048..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <core/device.h>
-#include <core/gpuobj.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/fb.h>
-
-#include "priv.h"
-
-struct nvc0_dmaobj_priv {
-	struct nouveau_dmaobj base;
-	u32 flags0;
-	u32 flags5;
-};
-
-static int
-nvc0_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
-		 struct nouveau_object *parent,
-		 struct nouveau_gpuobj **pgpuobj)
-{
-	struct nvc0_dmaobj_priv *priv = (void *)dmaobj;
-	int ret;
-
-	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
-		switch (nv_mclass(parent->parent)) {
-		case GT214_DISP_CORE_CHANNEL_DMA:
-		case GT214_DISP_BASE_CHANNEL_DMA:
-		case GT214_DISP_OVERLAY_CHANNEL_DMA:
-			break;
-		default:
-			return -EINVAL;
-		}
-	} else
-		return 0;
-
-	ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
-	if (ret == 0) {
-		nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj));
-		nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit));
-		nv_wo32(*pgpuobj, 0x08, lower_32_bits(priv->base.start));
-		nv_wo32(*pgpuobj, 0x0c, upper_32_bits(priv->base.limit) << 24 |
-					upper_32_bits(priv->base.start));
-		nv_wo32(*pgpuobj, 0x10, 0x00000000);
-		nv_wo32(*pgpuobj, 0x14, priv->flags5);
-	}
-
-	return ret;
-}
-
-static int
-nvc0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		 struct nouveau_oclass *oclass, void *data, u32 size,
-		 struct nouveau_object **pobject)
-{
-	struct nouveau_dmaeng *dmaeng = (void *)engine;
-	union {
-		struct gf100_dma_v0 v0;
-	} *args;
-	struct nvc0_dmaobj_priv *priv;
-	u32 kind, user, unkn;
-	int ret;
-
-	ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-	args = data;
-
-	nv_ioctl(parent, "create gf100 dma size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create gf100 dma vers %d priv %d kind %02x\n",
-			 args->v0.version, args->v0.priv, args->v0.kind);
-		kind = args->v0.kind;
-		user = args->v0.priv;
-		unkn = 0;
-	} else
-	if (size == 0) {
-		if (priv->base.target != NV_MEM_TARGET_VM) {
-			kind = GF100_DMA_V0_KIND_PITCH;
-			user = GF100_DMA_V0_PRIV_US;
-			unkn = 2;
-		} else {
-			kind = GF100_DMA_V0_KIND_VM;
-			user = GF100_DMA_V0_PRIV_VM;
-			unkn = 0;
-		}
-	} else
-		return ret;
-
-	if (user > 2)
-		return -EINVAL;
-	priv->flags0 |= (kind << 22) | (user << 20);
-	priv->flags5 |= (unkn << 16);
-
-	switch (priv->base.target) {
-	case NV_MEM_TARGET_VM:
-		priv->flags0 |= 0x00000000;
-		break;
-	case NV_MEM_TARGET_VRAM:
-		priv->flags0 |= 0x00010000;
-		break;
-	case NV_MEM_TARGET_PCI:
-		priv->flags0 |= 0x00020000;
-		break;
-	case NV_MEM_TARGET_PCI_NOSNOOP:
-		priv->flags0 |= 0x00030000;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	switch (priv->base.access) {
-	case NV_MEM_ACCESS_VM:
-		break;
-	case NV_MEM_ACCESS_RO:
-		priv->flags0 |= 0x00040000;
-		break;
-	case NV_MEM_ACCESS_WO:
-	case NV_MEM_ACCESS_RW:
-		priv->flags0 |= 0x00080000;
-		break;
-	}
-
-	return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
-}
-
-static struct nouveau_ofuncs
-nvc0_dmaobj_ofuncs = {
-	.ctor =  nvc0_dmaobj_ctor,
-	.dtor = _nvkm_dmaobj_dtor,
-	.init = _nvkm_dmaobj_init,
-	.fini = _nvkm_dmaobj_fini,
-};
-
-static struct nouveau_oclass
-nvc0_dmaeng_sclass[] = {
-	{ NV_DMA_FROM_MEMORY, &nvc0_dmaobj_ofuncs },
-	{ NV_DMA_TO_MEMORY, &nvc0_dmaobj_ofuncs },
-	{ NV_DMA_IN_MEMORY, &nvc0_dmaobj_ofuncs },
-	{}
-};
-
-struct nouveau_oclass *
-nvc0_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
-	.base.handle = NV_ENGINE(DMAOBJ, 0xc0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nvkm_dmaeng_ctor,
-		.dtor = _nvkm_dmaeng_dtor,
-		.init = _nvkm_dmaeng_init,
-		.fini = _nvkm_dmaeng_fini,
-	},
-	.sclass = nvc0_dmaeng_sclass,
-	.bind = nvc0_dmaobj_bind,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c
deleted file mode 100644
index 19f5f6522962..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <core/device.h>
-#include <core/gpuobj.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/fb.h>
-
-#include "priv.h"
-
-struct nvd0_dmaobj_priv {
-	struct nouveau_dmaobj base;
-	u32 flags0;
-};
-
-static int
-nvd0_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
-		 struct nouveau_object *parent,
-		 struct nouveau_gpuobj **pgpuobj)
-{
-	struct nvd0_dmaobj_priv *priv = (void *)dmaobj;
-	int ret;
-
-	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
-		switch (nv_mclass(parent->parent)) {
-		case GF110_DISP_CORE_CHANNEL_DMA:
-		case GK104_DISP_CORE_CHANNEL_DMA:
-		case GK110_DISP_CORE_CHANNEL_DMA:
-		case GM107_DISP_CORE_CHANNEL_DMA:
-		case GM204_DISP_CORE_CHANNEL_DMA:
-		case GF110_DISP_BASE_CHANNEL_DMA:
-		case GK104_DISP_BASE_CHANNEL_DMA:
-		case GK110_DISP_BASE_CHANNEL_DMA:
-		case GF110_DISP_OVERLAY_CONTROL_DMA:
-		case GK104_DISP_OVERLAY_CONTROL_DMA:
-			break;
-		default:
-			return -EINVAL;
-		}
-	} else
-		return 0;
-
-	ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
-	if (ret == 0) {
-		nv_wo32(*pgpuobj, 0x00, priv->flags0);
-		nv_wo32(*pgpuobj, 0x04, priv->base.start >> 8);
-		nv_wo32(*pgpuobj, 0x08, priv->base.limit >> 8);
-		nv_wo32(*pgpuobj, 0x0c, 0x00000000);
-		nv_wo32(*pgpuobj, 0x10, 0x00000000);
-		nv_wo32(*pgpuobj, 0x14, 0x00000000);
-	}
-
-	return ret;
-}
-
-static int
-nvd0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		 struct nouveau_oclass *oclass, void *data, u32 size,
-		 struct nouveau_object **pobject)
-{
-	struct nouveau_dmaeng *dmaeng = (void *)engine;
-	union {
-		struct gf110_dma_v0 v0;
-	} *args;
-	struct nvd0_dmaobj_priv *priv;
-	u32 kind, page;
-	int ret;
-
-	ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-	args = data;
-
-	nv_ioctl(parent, "create gf110 dma size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create gf100 dma vers %d page %d kind %02x\n",
-			 args->v0.version, args->v0.page, args->v0.kind);
-		kind = args->v0.kind;
-		page = args->v0.page;
-	} else
-	if (size == 0) {
-		if (priv->base.target != NV_MEM_TARGET_VM) {
-			kind = GF110_DMA_V0_KIND_PITCH;
-			page = GF110_DMA_V0_PAGE_SP;
-		} else {
-			kind = GF110_DMA_V0_KIND_VM;
-			page = GF110_DMA_V0_PAGE_LP;
-		}
-	} else
-		return ret;
-
-	if (page > 1)
-		return -EINVAL;
-	priv->flags0 = (kind << 20) | (page << 6);
-
-	switch (priv->base.target) {
-	case NV_MEM_TARGET_VRAM:
-		priv->flags0 |= 0x00000009;
-		break;
-	case NV_MEM_TARGET_VM:
-	case NV_MEM_TARGET_PCI:
-	case NV_MEM_TARGET_PCI_NOSNOOP:
-		/* XXX: don't currently know how to construct a real one
-		 *      of these.  we only use them to represent pushbufs
-		 *      on these chipsets, and the classes that use them
-		 *      deal with the target themselves.
-		 */
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
-}
-
-static struct nouveau_ofuncs
-nvd0_dmaobj_ofuncs = {
-	.ctor =  nvd0_dmaobj_ctor,
-	.dtor = _nvkm_dmaobj_dtor,
-	.init = _nvkm_dmaobj_init,
-	.fini = _nvkm_dmaobj_fini,
-};
-
-static struct nouveau_oclass
-nvd0_dmaeng_sclass[] = {
-	{ NV_DMA_FROM_MEMORY, &nvd0_dmaobj_ofuncs },
-	{ NV_DMA_TO_MEMORY, &nvd0_dmaobj_ofuncs },
-	{ NV_DMA_IN_MEMORY, &nvd0_dmaobj_ofuncs },
-	{}
-};
-
-struct nouveau_oclass *
-nvd0_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
-	.base.handle = NV_ENGINE(DMAOBJ, 0xd0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nvkm_dmaeng_ctor,
-		.dtor = _nvkm_dmaeng_dtor,
-		.init = _nvkm_dmaeng_init,
-		.fini = _nvkm_dmaeng_fini,
-	},
-	.sclass = nvd0_dmaeng_sclass,
-	.bind = nvd0_dmaobj_bind,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/priv.h b/drivers/gpu/drm/nouveau/core/engine/dmaobj/priv.h
deleted file mode 100644
index 36f743866937..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/priv.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef __NVKM_DMAOBJ_PRIV_H__
-#define __NVKM_DMAOBJ_PRIV_H__
-
-#include <engine/dmaobj.h>
-
-#define nvkm_dmaobj_create(p,e,c,pa,sa,d)                                      \
-	nvkm_dmaobj_create_((p), (e), (c), (pa), (sa), sizeof(**d), (void **)d)
-
-int nvkm_dmaobj_create_(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, void **, u32 *,
-			int, void **);
-#define _nvkm_dmaobj_dtor nouveau_object_destroy
-#define _nvkm_dmaobj_init nouveau_object_init
-#define _nvkm_dmaobj_fini nouveau_object_fini
-
-int _nvkm_dmaeng_ctor(struct nouveau_object *, struct nouveau_object *,
-		      struct nouveau_oclass *, void *, u32,
-		      struct nouveau_object **);
-#define _nvkm_dmaeng_dtor _nouveau_engine_dtor
-#define _nvkm_dmaeng_init _nouveau_engine_init
-#define _nvkm_dmaeng_fini _nouveau_engine_fini
-
-struct nvkm_dmaeng_impl {
-	struct nouveau_oclass base;
-	struct nouveau_oclass *sclass;
-	int (*bind)(struct nouveau_dmaobj *, struct nouveau_object *,
-		    struct nouveau_gpuobj **);
-};
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/falcon.c b/drivers/gpu/drm/nouveau/core/engine/falcon.c
deleted file mode 100644
index 2914646c8709..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/falcon.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <engine/falcon.h>
-#include <subdev/timer.h>
-
-void
-nouveau_falcon_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_falcon *falcon = (void *)subdev;
-	u32 dispatch = nv_ro32(falcon, 0x01c);
-	u32 intr = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16);
-
-	if (intr & 0x00000010) {
-		nv_debug(falcon, "ucode halted\n");
-		nv_wo32(falcon, 0x004, 0x00000010);
-		intr &= ~0x00000010;
-	}
-
-	if (intr)  {
-		nv_error(falcon, "unhandled intr 0x%08x\n", intr);
-		nv_wo32(falcon, 0x004, intr);
-	}
-}
-
-u32
-_nouveau_falcon_rd32(struct nouveau_object *object, u64 addr)
-{
-	struct nouveau_falcon *falcon = (void *)object;
-	return nv_rd32(falcon, falcon->addr + addr);
-}
-
-void
-_nouveau_falcon_wr32(struct nouveau_object *object, u64 addr, u32 data)
-{
-	struct nouveau_falcon *falcon = (void *)object;
-	nv_wr32(falcon, falcon->addr + addr, data);
-}
-
-static void *
-vmemdup(const void *src, size_t len)
-{
-	void *p = vmalloc(len);
-
-	if (p)
-		memcpy(p, src, len);
-	return p;
-}
-
-int
-_nouveau_falcon_init(struct nouveau_object *object)
-{
-	struct nouveau_device *device = nv_device(object);
-	struct nouveau_falcon *falcon = (void *)object;
-	const struct firmware *fw;
-	char name[32] = "internal";
-	int ret, i;
-	u32 caps;
-
-	/* enable engine, and determine its capabilities */
-	ret = nouveau_engine_init(&falcon->base);
-	if (ret)
-		return ret;
-
-	if (device->chipset <  0xa3 ||
-	    device->chipset == 0xaa || device->chipset == 0xac) {
-		falcon->version = 0;
-		falcon->secret  = (falcon->addr == 0x087000) ? 1 : 0;
-	} else {
-		caps = nv_ro32(falcon, 0x12c);
-		falcon->version = (caps & 0x0000000f);
-		falcon->secret  = (caps & 0x00000030) >> 4;
-	}
-
-	caps = nv_ro32(falcon, 0x108);
-	falcon->code.limit = (caps & 0x000001ff) << 8;
-	falcon->data.limit = (caps & 0x0003fe00) >> 1;
-
-	nv_debug(falcon, "falcon version: %d\n", falcon->version);
-	nv_debug(falcon, "secret level: %d\n", falcon->secret);
-	nv_debug(falcon, "code limit: %d\n", falcon->code.limit);
-	nv_debug(falcon, "data limit: %d\n", falcon->data.limit);
-
-	/* wait for 'uc halted' to be signalled before continuing */
-	if (falcon->secret && falcon->version < 4) {
-		if (!falcon->version)
-			nv_wait(falcon, 0x008, 0x00000010, 0x00000010);
-		else
-			nv_wait(falcon, 0x180, 0x80000000, 0);
-		nv_wo32(falcon, 0x004, 0x00000010);
-	}
-
-	/* disable all interrupts */
-	nv_wo32(falcon, 0x014, 0xffffffff);
-
-	/* no default ucode provided by the engine implementation, try and
-	 * locate a "self-bootstrapping" firmware image for the engine
-	 */
-	if (!falcon->code.data) {
-		snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03x",
-			 device->chipset, falcon->addr >> 12);
-
-		ret = request_firmware(&fw, name, nv_device_base(device));
-		if (ret == 0) {
-			falcon->code.data = vmemdup(fw->data, fw->size);
-			falcon->code.size = fw->size;
-			falcon->data.data = NULL;
-			falcon->data.size = 0;
-			release_firmware(fw);
-		}
-
-		falcon->external = true;
-	}
-
-	/* next step is to try and load "static code/data segment" firmware
-	 * images for the engine
-	 */
-	if (!falcon->code.data) {
-		snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xd",
-			 device->chipset, falcon->addr >> 12);
-
-		ret = request_firmware(&fw, name, nv_device_base(device));
-		if (ret) {
-			nv_error(falcon, "unable to load firmware data\n");
-			return ret;
-		}
-
-		falcon->data.data = vmemdup(fw->data, fw->size);
-		falcon->data.size = fw->size;
-		release_firmware(fw);
-		if (!falcon->data.data)
-			return -ENOMEM;
-
-		snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xc",
-			 device->chipset, falcon->addr >> 12);
-
-		ret = request_firmware(&fw, name, nv_device_base(device));
-		if (ret) {
-			nv_error(falcon, "unable to load firmware code\n");
-			return ret;
-		}
-
-		falcon->code.data = vmemdup(fw->data, fw->size);
-		falcon->code.size = fw->size;
-		release_firmware(fw);
-		if (!falcon->code.data)
-			return -ENOMEM;
-	}
-
-	nv_debug(falcon, "firmware: %s (%s)\n", name, falcon->data.data ?
-		 "static code/data segments" : "self-bootstrapping");
-
-	/* ensure any "self-bootstrapping" firmware image is in vram */
-	if (!falcon->data.data && !falcon->core) {
-		ret = nouveau_gpuobj_new(object->parent, NULL,
-					 falcon->code.size, 256, 0,
-					&falcon->core);
-		if (ret) {
-			nv_error(falcon, "core allocation failed, %d\n", ret);
-			return ret;
-		}
-
-		for (i = 0; i < falcon->code.size; i += 4)
-			nv_wo32(falcon->core, i, falcon->code.data[i / 4]);
-	}
-
-	/* upload firmware bootloader (or the full code segments) */
-	if (falcon->core) {
-		if (device->card_type < NV_C0)
-			nv_wo32(falcon, 0x618, 0x04000000);
-		else
-			nv_wo32(falcon, 0x618, 0x00000114);
-		nv_wo32(falcon, 0x11c, 0);
-		nv_wo32(falcon, 0x110, falcon->core->addr >> 8);
-		nv_wo32(falcon, 0x114, 0);
-		nv_wo32(falcon, 0x118, 0x00006610);
-	} else {
-		if (falcon->code.size > falcon->code.limit ||
-		    falcon->data.size > falcon->data.limit) {
-			nv_error(falcon, "ucode exceeds falcon limit(s)\n");
-			return -EINVAL;
-		}
-
-		if (falcon->version < 3) {
-			nv_wo32(falcon, 0xff8, 0x00100000);
-			for (i = 0; i < falcon->code.size / 4; i++)
-				nv_wo32(falcon, 0xff4, falcon->code.data[i]);
-		} else {
-			nv_wo32(falcon, 0x180, 0x01000000);
-			for (i = 0; i < falcon->code.size / 4; i++) {
-				if ((i & 0x3f) == 0)
-					nv_wo32(falcon, 0x188, i >> 6);
-				nv_wo32(falcon, 0x184, falcon->code.data[i]);
-			}
-		}
-	}
-
-	/* upload data segment (if necessary), zeroing the remainder */
-	if (falcon->version < 3) {
-		nv_wo32(falcon, 0xff8, 0x00000000);
-		for (i = 0; !falcon->core && i < falcon->data.size / 4; i++)
-			nv_wo32(falcon, 0xff4, falcon->data.data[i]);
-		for (; i < falcon->data.limit; i += 4)
-			nv_wo32(falcon, 0xff4, 0x00000000);
-	} else {
-		nv_wo32(falcon, 0x1c0, 0x01000000);
-		for (i = 0; !falcon->core && i < falcon->data.size / 4; i++)
-			nv_wo32(falcon, 0x1c4, falcon->data.data[i]);
-		for (; i < falcon->data.limit / 4; i++)
-			nv_wo32(falcon, 0x1c4, 0x00000000);
-	}
-
-	/* start it running */
-	nv_wo32(falcon, 0x10c, 0x00000001); /* BLOCK_ON_FIFO */
-	nv_wo32(falcon, 0x104, 0x00000000); /* ENTRY */
-	nv_wo32(falcon, 0x100, 0x00000002); /* TRIGGER */
-	nv_wo32(falcon, 0x048, 0x00000003); /* FIFO | CHSW */
-	return 0;
-}
-
-int
-_nouveau_falcon_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nouveau_falcon *falcon = (void *)object;
-
-	if (!suspend) {
-		nouveau_gpuobj_ref(NULL, &falcon->core);
-		if (falcon->external) {
-			vfree(falcon->data.data);
-			vfree(falcon->code.data);
-			falcon->code.data = NULL;
-		}
-	}
-
-	nv_mo32(falcon, 0x048, 0x00000003, 0x00000000);
-	nv_wo32(falcon, 0x014, 0xffffffff);
-
-	return nouveau_engine_fini(&falcon->base, suspend);
-}
-
-int
-nouveau_falcon_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, u32 addr, bool enable,
-		       const char *iname, const char *fname,
-		       int length, void **pobject)
-{
-	struct nouveau_falcon *falcon;
-	int ret;
-
-	ret = nouveau_engine_create_(parent, engine, oclass, enable, iname,
-				     fname, length, pobject);
-	falcon = *pobject;
-	if (ret)
-		return ret;
-
-	falcon->addr = addr;
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/base.c b/drivers/gpu/drm/nouveau/core/engine/fifo/base.c
deleted file mode 100644
index ac8375cf4eef..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/base.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <core/object.h>
-#include <core/handle.h>
-#include <core/event.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-#include <nvif/event.h>
-
-#include <engine/dmaobj.h>
-#include <engine/fifo.h>
-
-static int
-nouveau_fifo_event_ctor(struct nouveau_object *object, void *data, u32 size,
-			struct nvkm_notify *notify)
-{
-	if (size == 0) {
-		notify->size  = 0;
-		notify->types = 1;
-		notify->index = 0;
-		return 0;
-	}
-	return -ENOSYS;
-}
-
-static const struct nvkm_event_func
-nouveau_fifo_event_func = {
-	.ctor = nouveau_fifo_event_ctor,
-};
-
-int
-nouveau_fifo_channel_create_(struct nouveau_object *parent,
-			     struct nouveau_object *engine,
-			     struct nouveau_oclass *oclass,
-			     int bar, u32 addr, u32 size, u32 pushbuf,
-			     u64 engmask, int len, void **ptr)
-{
-	struct nouveau_device *device = nv_device(engine);
-	struct nouveau_fifo *priv = (void *)engine;
-	struct nouveau_fifo_chan *chan;
-	struct nouveau_dmaeng *dmaeng;
-	unsigned long flags;
-	int ret;
-
-	/* create base object class */
-	ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL,
-				     engmask, len, ptr);
-	chan = *ptr;
-	if (ret)
-		return ret;
-
-	/* validate dma object representing push buffer */
-	chan->pushdma = (void *)nouveau_handle_ref(parent, pushbuf);
-	if (!chan->pushdma)
-		return -ENOENT;
-
-	dmaeng = (void *)chan->pushdma->base.engine;
-	switch (chan->pushdma->base.oclass->handle) {
-	case NV_DMA_FROM_MEMORY:
-	case NV_DMA_IN_MEMORY:
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	ret = dmaeng->bind(chan->pushdma, parent, &chan->pushgpu);
-	if (ret)
-		return ret;
-
-	/* find a free fifo channel */
-	spin_lock_irqsave(&priv->lock, flags);
-	for (chan->chid = priv->min; chan->chid < priv->max; chan->chid++) {
-		if (!priv->channel[chan->chid]) {
-			priv->channel[chan->chid] = nv_object(chan);
-			break;
-		}
-	}
-	spin_unlock_irqrestore(&priv->lock, flags);
-
-	if (chan->chid == priv->max) {
-		nv_error(priv, "no free channels\n");
-		return -ENOSPC;
-	}
-
-	chan->addr = nv_device_resource_start(device, bar) +
-		     addr + size * chan->chid;
-	chan->size = size;
-	nvkm_event_send(&priv->cevent, 1, 0, NULL, 0);
-	return 0;
-}
-
-void
-nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *chan)
-{
-	struct nouveau_fifo *priv = (void *)nv_object(chan)->engine;
-	unsigned long flags;
-
-	if (chan->user)
-		iounmap(chan->user);
-
-	spin_lock_irqsave(&priv->lock, flags);
-	priv->channel[chan->chid] = NULL;
-	spin_unlock_irqrestore(&priv->lock, flags);
-
-	nouveau_gpuobj_ref(NULL, &chan->pushgpu);
-	nouveau_object_ref(NULL, (struct nouveau_object **)&chan->pushdma);
-	nouveau_namedb_destroy(&chan->base);
-}
-
-void
-_nouveau_fifo_channel_dtor(struct nouveau_object *object)
-{
-	struct nouveau_fifo_chan *chan = (void *)object;
-	nouveau_fifo_channel_destroy(chan);
-}
-
-int
-_nouveau_fifo_channel_map(struct nouveau_object *object, u64 *addr, u32 *size)
-{
-	struct nouveau_fifo_chan *chan = (void *)object;
-	*addr = chan->addr;
-	*size = chan->size;
-	return 0;
-}
-
-u32
-_nouveau_fifo_channel_rd32(struct nouveau_object *object, u64 addr)
-{
-	struct nouveau_fifo_chan *chan = (void *)object;
-	if (unlikely(!chan->user)) {
-		chan->user = ioremap(chan->addr, chan->size);
-		if (WARN_ON_ONCE(chan->user == NULL))
-			return 0;
-	}
-	return ioread32_native(chan->user + addr);
-}
-
-void
-_nouveau_fifo_channel_wr32(struct nouveau_object *object, u64 addr, u32 data)
-{
-	struct nouveau_fifo_chan *chan = (void *)object;
-	if (unlikely(!chan->user)) {
-		chan->user = ioremap(chan->addr, chan->size);
-		if (WARN_ON_ONCE(chan->user == NULL))
-			return;
-	}
-	iowrite32_native(data, chan->user + addr);
-}
-
-int
-nouveau_fifo_uevent_ctor(struct nouveau_object *object, void *data, u32 size,
-			 struct nvkm_notify *notify)
-{
-	union {
-		struct nvif_notify_uevent_req none;
-	} *req = data;
-	int ret;
-
-	if (nvif_unvers(req->none)) {
-		notify->size  = sizeof(struct nvif_notify_uevent_rep);
-		notify->types = 1;
-		notify->index = 0;
-	}
-
-	return ret;
-}
-
-void
-nouveau_fifo_uevent(struct nouveau_fifo *fifo)
-{
-	struct nvif_notify_uevent_rep rep = {
-	};
-	nvkm_event_send(&fifo->uevent, 1, 0, &rep, sizeof(rep));
-}
-
-int
-_nouveau_fifo_channel_ntfy(struct nouveau_object *object, u32 type,
-			   struct nvkm_event **event)
-{
-	struct nouveau_fifo *fifo = (void *)object->engine;
-	switch (type) {
-	case G82_CHANNEL_DMA_V0_NTFY_UEVENT:
-		if (nv_mclass(object) >= G82_CHANNEL_DMA) {
-			*event = &fifo->uevent;
-			return 0;
-		}
-		break;
-	default:
-		break;
-	}
-	return -EINVAL;
-}
-
-static int
-nouveau_fifo_chid(struct nouveau_fifo *priv, struct nouveau_object *object)
-{
-	int engidx = nv_hclass(priv) & 0xff;
-
-	while (object && object->parent) {
-		if ( nv_iclass(object->parent, NV_ENGCTX_CLASS) &&
-		    (nv_hclass(object->parent) & 0xff) == engidx)
-			return nouveau_fifo_chan(object)->chid;
-		object = object->parent;
-	}
-
-	return -1;
-}
-
-const char *
-nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid)
-{
-	struct nouveau_fifo_chan *chan = NULL;
-	unsigned long flags;
-
-	spin_lock_irqsave(&fifo->lock, flags);
-	if (chid >= fifo->min && chid <= fifo->max)
-		chan = (void *)fifo->channel[chid];
-	spin_unlock_irqrestore(&fifo->lock, flags);
-
-	return nouveau_client_name(chan);
-}
-
-void
-nouveau_fifo_destroy(struct nouveau_fifo *priv)
-{
-	kfree(priv->channel);
-	nvkm_event_fini(&priv->uevent);
-	nvkm_event_fini(&priv->cevent);
-	nouveau_engine_destroy(&priv->base);
-}
-
-int
-nouveau_fifo_create_(struct nouveau_object *parent,
-		     struct nouveau_object *engine,
-		     struct nouveau_oclass *oclass,
-		     int min, int max, int length, void **pobject)
-{
-	struct nouveau_fifo *priv;
-	int ret;
-
-	ret = nouveau_engine_create_(parent, engine, oclass, true, "PFIFO",
-				     "fifo", length, pobject);
-	priv = *pobject;
-	if (ret)
-		return ret;
-
-	priv->min = min;
-	priv->max = max;
-	priv->channel = kzalloc(sizeof(*priv->channel) * (max + 1), GFP_KERNEL);
-	if (!priv->channel)
-		return -ENOMEM;
-
-	ret = nvkm_event_init(&nouveau_fifo_event_func, 1, 1, &priv->cevent);
-	if (ret)
-		return ret;
-
-	priv->chid = nouveau_fifo_chid;
-	spin_lock_init(&priv->lock);
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c b/drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c
deleted file mode 100644
index 327456eae963..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include "nve0.h"
-
-struct nouveau_oclass *
-gk20a_fifo_oclass = &(struct nve0_fifo_impl) {
-	.base.handle = NV_ENGINE(FIFO, 0xea),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nve0_fifo_ctor,
-		.dtor = nve0_fifo_dtor,
-		.init = nve0_fifo_init,
-		.fini = nve0_fifo_fini,
-	},
-	.channels = 128,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
deleted file mode 100644
index 1931057f9962..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
+++ /dev/null
@@ -1,656 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-#include <core/engctx.h>
-#include <core/namedb.h>
-#include <core/handle.h>
-#include <core/ramht.h>
-#include <core/event.h>
-
-#include <subdev/instmem.h>
-#include <subdev/instmem/nv04.h>
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/fifo.h>
-
-#include "nv04.h"
-
-static struct ramfc_desc
-nv04_ramfc[] = {
-	{ 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
-	{ 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
-	{ 16,  0, 0x08,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
-	{ 16, 16, 0x08,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
-	{ 32,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_STATE },
-	{ 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
-	{ 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_ENGINE },
-	{ 32,  0, 0x18,  0, NV04_PFIFO_CACHE1_PULL1 },
-	{}
-};
-
-/*******************************************************************************
- * FIFO channel objects
- ******************************************************************************/
-
-int
-nv04_fifo_object_attach(struct nouveau_object *parent,
-			struct nouveau_object *object, u32 handle)
-{
-	struct nv04_fifo_priv *priv = (void *)parent->engine;
-	struct nv04_fifo_chan *chan = (void *)parent;
-	u32 context, chid = chan->base.chid;
-	int ret;
-
-	if (nv_iclass(object, NV_GPUOBJ_CLASS))
-		context = nv_gpuobj(object)->addr >> 4;
-	else
-		context = 0x00000004; /* just non-zero */
-
-	switch (nv_engidx(object->engine)) {
-	case NVDEV_ENGINE_DMAOBJ:
-	case NVDEV_ENGINE_SW:
-		context |= 0x00000000;
-		break;
-	case NVDEV_ENGINE_GR:
-		context |= 0x00010000;
-		break;
-	case NVDEV_ENGINE_MPEG:
-		context |= 0x00020000;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	context |= 0x80000000; /* valid */
-	context |= chid << 24;
-
-	mutex_lock(&nv_subdev(priv)->mutex);
-	ret = nouveau_ramht_insert(priv->ramht, chid, handle, context);
-	mutex_unlock(&nv_subdev(priv)->mutex);
-	return ret;
-}
-
-void
-nv04_fifo_object_detach(struct nouveau_object *parent, int cookie)
-{
-	struct nv04_fifo_priv *priv = (void *)parent->engine;
-	mutex_lock(&nv_subdev(priv)->mutex);
-	nouveau_ramht_remove(priv->ramht, cookie);
-	mutex_unlock(&nv_subdev(priv)->mutex);
-}
-
-int
-nv04_fifo_context_attach(struct nouveau_object *parent,
-			 struct nouveau_object *object)
-{
-	nv_engctx(object)->addr = nouveau_fifo_chan(parent)->chid;
-	return 0;
-}
-
-static int
-nv04_fifo_chan_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
-{
-	union {
-		struct nv03_channel_dma_v0 v0;
-	} *args = data;
-	struct nv04_fifo_priv *priv = (void *)engine;
-	struct nv04_fifo_chan *chan;
-	int ret;
-
-	nv_ioctl(parent, "create channel dma size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create channel dma vers %d pushbuf %08x "
-				 "offset %016llx\n", args->v0.version,
-			 args->v0.pushbuf, args->v0.offset);
-	} else
-		return ret;
-
-	ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
-					  0x10000, args->v0.pushbuf,
-					  (1ULL << NVDEV_ENGINE_DMAOBJ) |
-					  (1ULL << NVDEV_ENGINE_SW) |
-					  (1ULL << NVDEV_ENGINE_GR), &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	args->v0.chid = chan->base.chid;
-
-	nv_parent(chan)->object_attach = nv04_fifo_object_attach;
-	nv_parent(chan)->object_detach = nv04_fifo_object_detach;
-	nv_parent(chan)->context_attach = nv04_fifo_context_attach;
-	chan->ramfc = chan->base.chid * 32;
-
-	nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset);
-	nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset);
-	nv_wo32(priv->ramfc, chan->ramfc + 0x08, chan->base.pushgpu->addr >> 4);
-	nv_wo32(priv->ramfc, chan->ramfc + 0x10,
-			     NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
-			     NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
-#ifdef __BIG_ENDIAN
-			     NV_PFIFO_CACHE1_BIG_ENDIAN |
-#endif
-			     NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
-	return 0;
-}
-
-void
-nv04_fifo_chan_dtor(struct nouveau_object *object)
-{
-	struct nv04_fifo_priv *priv = (void *)object->engine;
-	struct nv04_fifo_chan *chan = (void *)object;
-	struct ramfc_desc *c = priv->ramfc_desc;
-
-	do {
-		nv_wo32(priv->ramfc, chan->ramfc + c->ctxp, 0x00000000);
-	} while ((++c)->bits);
-
-	nouveau_fifo_channel_destroy(&chan->base);
-}
-
-int
-nv04_fifo_chan_init(struct nouveau_object *object)
-{
-	struct nv04_fifo_priv *priv = (void *)object->engine;
-	struct nv04_fifo_chan *chan = (void *)object;
-	u32 mask = 1 << chan->base.chid;
-	unsigned long flags;
-	int ret;
-
-	ret = nouveau_fifo_channel_init(&chan->base);
-	if (ret)
-		return ret;
-
-	spin_lock_irqsave(&priv->base.lock, flags);
-	nv_mask(priv, NV04_PFIFO_MODE, mask, mask);
-	spin_unlock_irqrestore(&priv->base.lock, flags);
-	return 0;
-}
-
-int
-nv04_fifo_chan_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv04_fifo_priv *priv = (void *)object->engine;
-	struct nv04_fifo_chan *chan = (void *)object;
-	struct nouveau_gpuobj *fctx = priv->ramfc;
-	struct ramfc_desc *c;
-	unsigned long flags;
-	u32 data = chan->ramfc;
-	u32 chid;
-
-	/* prevent fifo context switches */
-	spin_lock_irqsave(&priv->base.lock, flags);
-	nv_wr32(priv, NV03_PFIFO_CACHES, 0);
-
-	/* if this channel is active, replace it with a null context */
-	chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max;
-	if (chid == chan->base.chid) {
-		nv_mask(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0);
-		nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 0);
-		nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0);
-
-		c = priv->ramfc_desc;
-		do {
-			u32 rm = ((1ULL << c->bits) - 1) << c->regs;
-			u32 cm = ((1ULL << c->bits) - 1) << c->ctxs;
-			u32 rv = (nv_rd32(priv, c->regp) &  rm) >> c->regs;
-			u32 cv = (nv_ro32(fctx, c->ctxp + data) & ~cm);
-			nv_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs));
-		} while ((++c)->bits);
-
-		c = priv->ramfc_desc;
-		do {
-			nv_wr32(priv, c->regp, 0x00000000);
-		} while ((++c)->bits);
-
-		nv_wr32(priv, NV03_PFIFO_CACHE1_GET, 0);
-		nv_wr32(priv, NV03_PFIFO_CACHE1_PUT, 0);
-		nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max);
-		nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1);
-		nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
-	}
-
-	/* restore normal operation, after disabling dma mode */
-	nv_mask(priv, NV04_PFIFO_MODE, 1 << chan->base.chid, 0);
-	nv_wr32(priv, NV03_PFIFO_CACHES, 1);
-	spin_unlock_irqrestore(&priv->base.lock, flags);
-
-	return nouveau_fifo_channel_fini(&chan->base, suspend);
-}
-
-static struct nouveau_ofuncs
-nv04_fifo_ofuncs = {
-	.ctor = nv04_fifo_chan_ctor,
-	.dtor = nv04_fifo_chan_dtor,
-	.init = nv04_fifo_chan_init,
-	.fini = nv04_fifo_chan_fini,
-	.map  = _nouveau_fifo_channel_map,
-	.rd32 = _nouveau_fifo_channel_rd32,
-	.wr32 = _nouveau_fifo_channel_wr32,
-	.ntfy = _nouveau_fifo_channel_ntfy
-};
-
-static struct nouveau_oclass
-nv04_fifo_sclass[] = {
-	{ NV03_CHANNEL_DMA, &nv04_fifo_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * FIFO context - basically just the instmem reserved for the channel
- ******************************************************************************/
-
-int
-nv04_fifo_context_ctor(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, void *data, u32 size,
-		       struct nouveau_object **pobject)
-{
-	struct nv04_fifo_base *base;
-	int ret;
-
-	ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
-				          0x1000, NVOBJ_FLAG_HEAP, &base);
-	*pobject = nv_object(base);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-static struct nouveau_oclass
-nv04_fifo_cclass = {
-	.handle = NV_ENGCTX(FIFO, 0x04),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fifo_context_ctor,
-		.dtor = _nouveau_fifo_context_dtor,
-		.init = _nouveau_fifo_context_init,
-		.fini = _nouveau_fifo_context_fini,
-		.rd32 = _nouveau_fifo_context_rd32,
-		.wr32 = _nouveau_fifo_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PFIFO engine
- ******************************************************************************/
-
-void
-nv04_fifo_pause(struct nouveau_fifo *pfifo, unsigned long *pflags)
-__acquires(priv->base.lock)
-{
-	struct nv04_fifo_priv *priv = (void *)pfifo;
-	unsigned long flags;
-
-	spin_lock_irqsave(&priv->base.lock, flags);
-	*pflags = flags;
-
-	nv_wr32(priv, NV03_PFIFO_CACHES, 0x00000000);
-	nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000);
-
-	/* in some cases the puller may be left in an inconsistent state
-	 * if you try to stop it while it's busy translating handles.
-	 * sometimes you get a CACHE_ERROR, sometimes it just fails
-	 * silently; sending incorrect instance offsets to PGRAPH after
-	 * it's started up again.
-	 *
-	 * to avoid this, we invalidate the most recently calculated
-	 * instance.
-	 */
-	if (!nv_wait(priv, NV04_PFIFO_CACHE1_PULL0,
-			   NV04_PFIFO_CACHE1_PULL0_HASH_BUSY, 0x00000000))
-		nv_warn(priv, "timeout idling puller\n");
-
-	if (nv_rd32(priv, NV04_PFIFO_CACHE1_PULL0) &
-			  NV04_PFIFO_CACHE1_PULL0_HASH_FAILED)
-		nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
-
-	nv_wr32(priv, NV04_PFIFO_CACHE1_HASH, 0x00000000);
-}
-
-void
-nv04_fifo_start(struct nouveau_fifo *pfifo, unsigned long *pflags)
-__releases(priv->base.lock)
-{
-	struct nv04_fifo_priv *priv = (void *)pfifo;
-	unsigned long flags = *pflags;
-
-	nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001);
-	nv_wr32(priv, NV03_PFIFO_CACHES, 0x00000001);
-
-	spin_unlock_irqrestore(&priv->base.lock, flags);
-}
-
-static const char *
-nv_dma_state_err(u32 state)
-{
-	static const char * const desc[] = {
-		"NONE", "CALL_SUBR_ACTIVE", "INVALID_MTHD", "RET_SUBR_INACTIVE",
-		"INVALID_CMD", "IB_EMPTY"/* NV50+ */, "MEM_FAULT", "UNK"
-	};
-	return desc[(state >> 29) & 0x7];
-}
-
-static bool
-nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data)
-{
-	struct nv04_fifo_chan *chan = NULL;
-	struct nouveau_handle *bind;
-	const int subc = (addr >> 13) & 0x7;
-	const int mthd = addr & 0x1ffc;
-	bool handled = false;
-	unsigned long flags;
-	u32 engine;
-
-	spin_lock_irqsave(&priv->base.lock, flags);
-	if (likely(chid >= priv->base.min && chid <= priv->base.max))
-		chan = (void *)priv->base.channel[chid];
-	if (unlikely(!chan))
-		goto out;
-
-	switch (mthd) {
-	case 0x0000:
-		bind = nouveau_namedb_get(nv_namedb(chan), data);
-		if (unlikely(!bind))
-			break;
-
-		if (nv_engidx(bind->object->engine) == NVDEV_ENGINE_SW) {
-			engine = 0x0000000f << (subc * 4);
-			chan->subc[subc] = data;
-			handled = true;
-
-			nv_mask(priv, NV04_PFIFO_CACHE1_ENGINE, engine, 0);
-		}
-
-		nouveau_namedb_put(bind);
-		break;
-	default:
-		engine = nv_rd32(priv, NV04_PFIFO_CACHE1_ENGINE);
-		if (unlikely(((engine >> (subc * 4)) & 0xf) != 0))
-			break;
-
-		bind = nouveau_namedb_get(nv_namedb(chan), chan->subc[subc]);
-		if (likely(bind)) {
-			if (!nv_call(bind->object, mthd, data))
-				handled = true;
-			nouveau_namedb_put(bind);
-		}
-		break;
-	}
-
-out:
-	spin_unlock_irqrestore(&priv->base.lock, flags);
-	return handled;
-}
-
-static void
-nv04_fifo_cache_error(struct nouveau_device *device,
-		struct nv04_fifo_priv *priv, u32 chid, u32 get)
-{
-	u32 mthd, data;
-	int ptr;
-
-	/* NV_PFIFO_CACHE1_GET actually goes to 0xffc before wrapping on my
-	 * G80 chips, but CACHE1 isn't big enough for this much data.. Tests
-	 * show that it wraps around to the start at GET=0x800.. No clue as to
-	 * why..
-	 */
-	ptr = (get & 0x7ff) >> 2;
-
-	if (device->card_type < NV_40) {
-		mthd = nv_rd32(priv, NV04_PFIFO_CACHE1_METHOD(ptr));
-		data = nv_rd32(priv, NV04_PFIFO_CACHE1_DATA(ptr));
-	} else {
-		mthd = nv_rd32(priv, NV40_PFIFO_CACHE1_METHOD(ptr));
-		data = nv_rd32(priv, NV40_PFIFO_CACHE1_DATA(ptr));
-	}
-
-	if (!nv04_fifo_swmthd(priv, chid, mthd, data)) {
-		const char *client_name =
-			nouveau_client_name_for_fifo_chid(&priv->base, chid);
-		nv_error(priv,
-			 "CACHE_ERROR - ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
-			 chid, client_name, (mthd >> 13) & 7, mthd & 0x1ffc,
-			 data);
-	}
-
-	nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
-	nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
-
-	nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0,
-		nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) & ~1);
-	nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4);
-	nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0,
-		nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) | 1);
-	nv_wr32(priv, NV04_PFIFO_CACHE1_HASH, 0);
-
-	nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH,
-		nv_rd32(priv, NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
-	nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
-}
-
-static void
-nv04_fifo_dma_pusher(struct nouveau_device *device, struct nv04_fifo_priv *priv,
-		u32 chid)
-{
-	const char *client_name;
-	u32 dma_get = nv_rd32(priv, 0x003244);
-	u32 dma_put = nv_rd32(priv, 0x003240);
-	u32 push = nv_rd32(priv, 0x003220);
-	u32 state = nv_rd32(priv, 0x003228);
-
-	client_name = nouveau_client_name_for_fifo_chid(&priv->base, chid);
-
-	if (device->card_type == NV_50) {
-		u32 ho_get = nv_rd32(priv, 0x003328);
-		u32 ho_put = nv_rd32(priv, 0x003320);
-		u32 ib_get = nv_rd32(priv, 0x003334);
-		u32 ib_put = nv_rd32(priv, 0x003330);
-
-		nv_error(priv,
-			 "DMA_PUSHER - ch %d [%s] get 0x%02x%08x put 0x%02x%08x ib_get 0x%08x ib_put 0x%08x state 0x%08x (err: %s) push 0x%08x\n",
-			 chid, client_name, ho_get, dma_get, ho_put, dma_put,
-			 ib_get, ib_put, state, nv_dma_state_err(state), push);
-
-		/* METHOD_COUNT, in DMA_STATE on earlier chipsets */
-		nv_wr32(priv, 0x003364, 0x00000000);
-		if (dma_get != dma_put || ho_get != ho_put) {
-			nv_wr32(priv, 0x003244, dma_put);
-			nv_wr32(priv, 0x003328, ho_put);
-		} else
-		if (ib_get != ib_put)
-			nv_wr32(priv, 0x003334, ib_put);
-	} else {
-		nv_error(priv,
-			 "DMA_PUSHER - ch %d [%s] get 0x%08x put 0x%08x state 0x%08x (err: %s) push 0x%08x\n",
-			 chid, client_name, dma_get, dma_put, state,
-			 nv_dma_state_err(state), push);
-
-		if (dma_get != dma_put)
-			nv_wr32(priv, 0x003244, dma_put);
-	}
-
-	nv_wr32(priv, 0x003228, 0x00000000);
-	nv_wr32(priv, 0x003220, 0x00000001);
-	nv_wr32(priv, 0x002100, NV_PFIFO_INTR_DMA_PUSHER);
-}
-
-void
-nv04_fifo_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_device *device = nv_device(subdev);
-	struct nv04_fifo_priv *priv = (void *)subdev;
-	uint32_t status, reassign;
-	int cnt = 0;
-
-	reassign = nv_rd32(priv, NV03_PFIFO_CACHES) & 1;
-	while ((status = nv_rd32(priv, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) {
-		uint32_t chid, get;
-
-		nv_wr32(priv, NV03_PFIFO_CACHES, 0);
-
-		chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max;
-		get  = nv_rd32(priv, NV03_PFIFO_CACHE1_GET);
-
-		if (status & NV_PFIFO_INTR_CACHE_ERROR) {
-			nv04_fifo_cache_error(device, priv, chid, get);
-			status &= ~NV_PFIFO_INTR_CACHE_ERROR;
-		}
-
-		if (status & NV_PFIFO_INTR_DMA_PUSHER) {
-			nv04_fifo_dma_pusher(device, priv, chid);
-			status &= ~NV_PFIFO_INTR_DMA_PUSHER;
-		}
-
-		if (status & NV_PFIFO_INTR_SEMAPHORE) {
-			uint32_t sem;
-
-			status &= ~NV_PFIFO_INTR_SEMAPHORE;
-			nv_wr32(priv, NV03_PFIFO_INTR_0,
-				NV_PFIFO_INTR_SEMAPHORE);
-
-			sem = nv_rd32(priv, NV10_PFIFO_CACHE1_SEMAPHORE);
-			nv_wr32(priv, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);
-
-			nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4);
-			nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
-		}
-
-		if (device->card_type == NV_50) {
-			if (status & 0x00000010) {
-				status &= ~0x00000010;
-				nv_wr32(priv, 0x002100, 0x00000010);
-			}
-
-			if (status & 0x40000000) {
-				nv_wr32(priv, 0x002100, 0x40000000);
-				nouveau_fifo_uevent(&priv->base);
-				status &= ~0x40000000;
-			}
-		}
-
-		if (status) {
-			nv_warn(priv, "unknown intr 0x%08x, ch %d\n",
-				status, chid);
-			nv_wr32(priv, NV03_PFIFO_INTR_0, status);
-			status = 0;
-		}
-
-		nv_wr32(priv, NV03_PFIFO_CACHES, reassign);
-	}
-
-	if (status) {
-		nv_error(priv, "still angry after %d spins, halt\n", cnt);
-		nv_wr32(priv, 0x002140, 0);
-		nv_wr32(priv, 0x000140, 0);
-	}
-
-	nv_wr32(priv, 0x000100, 0x00000100);
-}
-
-static int
-nv04_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv04_instmem_priv *imem = nv04_instmem(parent);
-	struct nv04_fifo_priv *priv;
-	int ret;
-
-	ret = nouveau_fifo_create(parent, engine, oclass, 0, 15, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nouveau_ramht_ref(imem->ramht, &priv->ramht);
-	nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
-	nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
-
-	nv_subdev(priv)->unit = 0x00000100;
-	nv_subdev(priv)->intr = nv04_fifo_intr;
-	nv_engine(priv)->cclass = &nv04_fifo_cclass;
-	nv_engine(priv)->sclass = nv04_fifo_sclass;
-	priv->base.pause = nv04_fifo_pause;
-	priv->base.start = nv04_fifo_start;
-	priv->ramfc_desc = nv04_ramfc;
-	return 0;
-}
-
-void
-nv04_fifo_dtor(struct nouveau_object *object)
-{
-	struct nv04_fifo_priv *priv = (void *)object;
-	nouveau_gpuobj_ref(NULL, &priv->ramfc);
-	nouveau_gpuobj_ref(NULL, &priv->ramro);
-	nouveau_ramht_ref(NULL, &priv->ramht);
-	nouveau_fifo_destroy(&priv->base);
-}
-
-int
-nv04_fifo_init(struct nouveau_object *object)
-{
-	struct nv04_fifo_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_fifo_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, NV04_PFIFO_DELAY_0, 0x000000ff);
-	nv_wr32(priv, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);
-
-	nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
-				       ((priv->ramht->bits - 9) << 16) |
-				        (priv->ramht->base.addr >> 8));
-	nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8);
-	nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8);
-
-	nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max);
-
-	nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff);
-	nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff);
-
-	nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1);
-	nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
-	nv_wr32(priv, NV03_PFIFO_CACHES, 1);
-	return 0;
-}
-
-struct nouveau_oclass *
-nv04_fifo_oclass = &(struct nouveau_oclass) {
-	.handle = NV_ENGINE(FIFO, 0x04),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fifo_ctor,
-		.dtor = nv04_fifo_dtor,
-		.init = nv04_fifo_init,
-		.fini = _nouveau_fifo_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.h b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.h
deleted file mode 100644
index 496a4b4fdfaf..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.h
+++ /dev/null
@@ -1,178 +0,0 @@
-#ifndef __NV04_FIFO_H__
-#define __NV04_FIFO_H__
-
-#include <engine/fifo.h>
-
-#define NV04_PFIFO_DELAY_0                                 0x00002040
-#define NV04_PFIFO_DMA_TIMESLICE                           0x00002044
-#define NV04_PFIFO_NEXT_CHANNEL                            0x00002050
-#define NV03_PFIFO_INTR_0                                  0x00002100
-#define NV03_PFIFO_INTR_EN_0                               0x00002140
-#    define NV_PFIFO_INTR_CACHE_ERROR                          (1<<0)
-#    define NV_PFIFO_INTR_RUNOUT                               (1<<4)
-#    define NV_PFIFO_INTR_RUNOUT_OVERFLOW                      (1<<8)
-#    define NV_PFIFO_INTR_DMA_PUSHER                          (1<<12)
-#    define NV_PFIFO_INTR_DMA_PT                              (1<<16)
-#    define NV_PFIFO_INTR_SEMAPHORE                           (1<<20)
-#    define NV_PFIFO_INTR_ACQUIRE_TIMEOUT                     (1<<24)
-#define NV03_PFIFO_RAMHT                                   0x00002210
-#define NV03_PFIFO_RAMFC                                   0x00002214
-#define NV03_PFIFO_RAMRO                                   0x00002218
-#define NV40_PFIFO_RAMFC                                   0x00002220
-#define NV03_PFIFO_CACHES                                  0x00002500
-#define NV04_PFIFO_MODE                                    0x00002504
-#define NV04_PFIFO_DMA                                     0x00002508
-#define NV04_PFIFO_SIZE                                    0x0000250c
-#define NV50_PFIFO_CTX_TABLE(c)                        (0x2600+(c)*4)
-#define NV50_PFIFO_CTX_TABLE__SIZE                                128
-#define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED                  (1<<31)
-#define NV50_PFIFO_CTX_TABLE_UNK30_BAD                        (1<<30)
-#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80             0x0FFFFFFF
-#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84             0x00FFFFFF
-#define NV03_PFIFO_CACHE0_PUSH0                            0x00003000
-#define NV03_PFIFO_CACHE0_PULL0                            0x00003040
-#define NV04_PFIFO_CACHE0_PULL0                            0x00003050
-#define NV04_PFIFO_CACHE0_PULL1                            0x00003054
-#define NV03_PFIFO_CACHE1_PUSH0                            0x00003200
-#define NV03_PFIFO_CACHE1_PUSH1                            0x00003204
-#define NV03_PFIFO_CACHE1_PUSH1_DMA                            (1<<8)
-#define NV40_PFIFO_CACHE1_PUSH1_DMA                           (1<<16)
-#define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK                  0x0000000f
-#define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK                  0x0000001f
-#define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK                  0x0000007f
-#define NV03_PFIFO_CACHE1_PUT                              0x00003210
-#define NV04_PFIFO_CACHE1_DMA_PUSH                         0x00003220
-#define NV04_PFIFO_CACHE1_DMA_FETCH                        0x00003224
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES         0x00000000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES        0x00000008
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES        0x00000010
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES        0x00000018
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES        0x00000020
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES        0x00000028
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES        0x00000030
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES        0x00000038
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES        0x00000040
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES        0x00000048
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES        0x00000050
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES        0x00000058
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES       0x00000060
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES       0x00000068
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES       0x00000070
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES       0x00000078
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES       0x00000080
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES       0x00000088
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES       0x00000090
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES       0x00000098
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES       0x000000A0
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES       0x000000A8
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES       0x000000B0
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES       0x000000B8
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES       0x000000C0
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES       0x000000C8
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES       0x000000D0
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES       0x000000D8
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES       0x000000E0
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES       0x000000E8
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES       0x000000F0
-#    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES       0x000000F8
-#    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE                 0x0000E000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES        0x00000000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES        0x00002000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES        0x00004000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES       0x00006000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES       0x00008000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES       0x0000A000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES       0x0000C000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES       0x0000E000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS             0x001F0000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0           0x00000000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1           0x00010000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2           0x00020000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3           0x00030000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4           0x00040000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5           0x00050000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6           0x00060000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7           0x00070000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8           0x00080000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9           0x00090000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10          0x000A0000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11          0x000B0000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12          0x000C0000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13          0x000D0000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14          0x000E0000
-#    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15          0x000F0000
-#    define NV_PFIFO_CACHE1_ENDIAN                         0x80000000
-#    define NV_PFIFO_CACHE1_LITTLE_ENDIAN                  0x7FFFFFFF
-#    define NV_PFIFO_CACHE1_BIG_ENDIAN                     0x80000000
-#define NV04_PFIFO_CACHE1_DMA_STATE                        0x00003228
-#define NV04_PFIFO_CACHE1_DMA_INSTANCE                     0x0000322c
-#define NV04_PFIFO_CACHE1_DMA_CTL                          0x00003230
-#define NV04_PFIFO_CACHE1_DMA_PUT                          0x00003240
-#define NV04_PFIFO_CACHE1_DMA_GET                          0x00003244
-#define NV10_PFIFO_CACHE1_REF_CNT                          0x00003248
-#define NV10_PFIFO_CACHE1_DMA_SUBROUTINE                   0x0000324C
-#define NV03_PFIFO_CACHE1_PULL0                            0x00003240
-#define NV04_PFIFO_CACHE1_PULL0                            0x00003250
-#    define NV04_PFIFO_CACHE1_PULL0_HASH_FAILED            0x00000010
-#    define NV04_PFIFO_CACHE1_PULL0_HASH_BUSY              0x00001000
-#define NV03_PFIFO_CACHE1_PULL1                            0x00003250
-#define NV04_PFIFO_CACHE1_PULL1                            0x00003254
-#define NV04_PFIFO_CACHE1_HASH                             0x00003258
-#define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT                  0x00003260
-#define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP                0x00003264
-#define NV10_PFIFO_CACHE1_ACQUIRE_VALUE                    0x00003268
-#define NV10_PFIFO_CACHE1_SEMAPHORE                        0x0000326C
-#define NV03_PFIFO_CACHE1_GET                              0x00003270
-#define NV04_PFIFO_CACHE1_ENGINE                           0x00003280
-#define NV04_PFIFO_CACHE1_DMA_DCOUNT                       0x000032A0
-#define NV40_PFIFO_GRCTX_INSTANCE                          0x000032E0
-#define NV40_PFIFO_UNK32E4                                 0x000032E4
-#define NV04_PFIFO_CACHE1_METHOD(i)                (0x00003800+(i*8))
-#define NV04_PFIFO_CACHE1_DATA(i)                  (0x00003804+(i*8))
-#define NV40_PFIFO_CACHE1_METHOD(i)                (0x00090000+(i*8))
-#define NV40_PFIFO_CACHE1_DATA(i)                  (0x00090004+(i*8))
-
-struct ramfc_desc {
-	unsigned bits:6;
-	unsigned ctxs:5;
-	unsigned ctxp:8;
-	unsigned regs:5;
-	unsigned regp;
-};
-
-struct nv04_fifo_priv {
-	struct nouveau_fifo base;
-	struct ramfc_desc *ramfc_desc;
-	struct nouveau_ramht  *ramht;
-	struct nouveau_gpuobj *ramro;
-	struct nouveau_gpuobj *ramfc;
-};
-
-struct nv04_fifo_base {
-	struct nouveau_fifo_base base;
-};
-
-struct nv04_fifo_chan {
-	struct nouveau_fifo_chan base;
-	u32 subc[8];
-	u32 ramfc;
-};
-
-int  nv04_fifo_object_attach(struct nouveau_object *,
-			     struct nouveau_object *, u32);
-void nv04_fifo_object_detach(struct nouveau_object *, int);
-
-void nv04_fifo_chan_dtor(struct nouveau_object *);
-int  nv04_fifo_chan_init(struct nouveau_object *);
-int  nv04_fifo_chan_fini(struct nouveau_object *, bool suspend);
-
-int  nv04_fifo_context_ctor(struct nouveau_object *, struct nouveau_object *,
-			    struct nouveau_oclass *, void *, u32,
-			    struct nouveau_object **);
-
-void nv04_fifo_dtor(struct nouveau_object *);
-int  nv04_fifo_init(struct nouveau_object *);
-void nv04_fifo_pause(struct nouveau_fifo *, unsigned long *);
-void nv04_fifo_start(struct nouveau_fifo *, unsigned long *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c
deleted file mode 100644
index 2a32add51c81..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-#include <core/engctx.h>
-#include <core/ramht.h>
-
-#include <subdev/instmem.h>
-#include <subdev/instmem/nv04.h>
-#include <subdev/fb.h>
-
-#include <engine/fifo.h>
-
-#include "nv04.h"
-
-static struct ramfc_desc
-nv10_ramfc[] = {
-	{ 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
-	{ 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
-	{ 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
-	{ 16,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
-	{ 16, 16, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
-	{ 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_STATE },
-	{ 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
-	{ 32,  0, 0x18,  0, NV04_PFIFO_CACHE1_ENGINE },
-	{ 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_PULL1 },
-	{}
-};
-
-/*******************************************************************************
- * FIFO channel objects
- ******************************************************************************/
-
-static int
-nv10_fifo_chan_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
-{
-	union {
-		struct nv03_channel_dma_v0 v0;
-	} *args = data;
-	struct nv04_fifo_priv *priv = (void *)engine;
-	struct nv04_fifo_chan *chan;
-	int ret;
-
-	nv_ioctl(parent, "create channel dma size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create channel dma vers %d pushbuf %08x "
-				 "offset %016llx\n", args->v0.version,
-			 args->v0.pushbuf, args->v0.offset);
-	} else
-		return ret;
-
-	ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
-					  0x10000, args->v0.pushbuf,
-					  (1ULL << NVDEV_ENGINE_DMAOBJ) |
-					  (1ULL << NVDEV_ENGINE_SW) |
-					  (1ULL << NVDEV_ENGINE_GR), &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	args->v0.chid = chan->base.chid;
-
-	nv_parent(chan)->object_attach = nv04_fifo_object_attach;
-	nv_parent(chan)->object_detach = nv04_fifo_object_detach;
-	nv_parent(chan)->context_attach = nv04_fifo_context_attach;
-	chan->ramfc = chan->base.chid * 32;
-
-	nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset);
-	nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset);
-	nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4);
-	nv_wo32(priv->ramfc, chan->ramfc + 0x14,
-			     NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
-			     NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
-#ifdef __BIG_ENDIAN
-			     NV_PFIFO_CACHE1_BIG_ENDIAN |
-#endif
-			     NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
-	return 0;
-}
-
-static struct nouveau_ofuncs
-nv10_fifo_ofuncs = {
-	.ctor = nv10_fifo_chan_ctor,
-	.dtor = nv04_fifo_chan_dtor,
-	.init = nv04_fifo_chan_init,
-	.fini = nv04_fifo_chan_fini,
-	.map  = _nouveau_fifo_channel_map,
-	.rd32 = _nouveau_fifo_channel_rd32,
-	.wr32 = _nouveau_fifo_channel_wr32,
-	.ntfy = _nouveau_fifo_channel_ntfy
-};
-
-static struct nouveau_oclass
-nv10_fifo_sclass[] = {
-	{ NV10_CHANNEL_DMA, &nv10_fifo_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * FIFO context - basically just the instmem reserved for the channel
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv10_fifo_cclass = {
-	.handle = NV_ENGCTX(FIFO, 0x10),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fifo_context_ctor,
-		.dtor = _nouveau_fifo_context_dtor,
-		.init = _nouveau_fifo_context_init,
-		.fini = _nouveau_fifo_context_fini,
-		.rd32 = _nouveau_fifo_context_rd32,
-		.wr32 = _nouveau_fifo_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PFIFO engine
- ******************************************************************************/
-
-static int
-nv10_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv04_instmem_priv *imem = nv04_instmem(parent);
-	struct nv04_fifo_priv *priv;
-	int ret;
-
-	ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nouveau_ramht_ref(imem->ramht, &priv->ramht);
-	nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
-	nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
-
-	nv_subdev(priv)->unit = 0x00000100;
-	nv_subdev(priv)->intr = nv04_fifo_intr;
-	nv_engine(priv)->cclass = &nv10_fifo_cclass;
-	nv_engine(priv)->sclass = nv10_fifo_sclass;
-	priv->base.pause = nv04_fifo_pause;
-	priv->base.start = nv04_fifo_start;
-	priv->ramfc_desc = nv10_ramfc;
-	return 0;
-}
-
-struct nouveau_oclass *
-nv10_fifo_oclass = &(struct nouveau_oclass) {
-	.handle = NV_ENGINE(FIFO, 0x10),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv10_fifo_ctor,
-		.dtor = nv04_fifo_dtor,
-		.init = nv04_fifo_init,
-		.fini = _nouveau_fifo_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv108.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv108.c
deleted file mode 100644
index 09362a51ba57..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv108.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nve0.h"
-
-struct nouveau_oclass *
-nv108_fifo_oclass = &(struct nve0_fifo_impl) {
-	.base.handle = NV_ENGINE(FIFO, 0x08),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nve0_fifo_ctor,
-		.dtor = nve0_fifo_dtor,
-		.init = nve0_fifo_init,
-		.fini = _nouveau_fifo_fini,
-	},
-	.channels = 1024,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
deleted file mode 100644
index 12d76c8adb23..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-#include <core/engctx.h>
-#include <core/ramht.h>
-
-#include <subdev/instmem.h>
-#include <subdev/instmem/nv04.h>
-#include <subdev/fb.h>
-
-#include <engine/fifo.h>
-
-#include "nv04.h"
-
-static struct ramfc_desc
-nv17_ramfc[] = {
-	{ 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
-	{ 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
-	{ 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
-	{ 16,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
-	{ 16, 16, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
-	{ 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_STATE },
-	{ 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
-	{ 32,  0, 0x18,  0, NV04_PFIFO_CACHE1_ENGINE },
-	{ 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_PULL1 },
-	{ 32,  0, 0x20,  0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
-	{ 32,  0, 0x24,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
-	{ 32,  0, 0x28,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
-	{ 32,  0, 0x2c,  0, NV10_PFIFO_CACHE1_SEMAPHORE },
-	{ 32,  0, 0x30,  0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
-	{}
-};
-
-/*******************************************************************************
- * FIFO channel objects
- ******************************************************************************/
-
-static int
-nv17_fifo_chan_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
-{
-	union {
-		struct nv03_channel_dma_v0 v0;
-	} *args = data;
-	struct nv04_fifo_priv *priv = (void *)engine;
-	struct nv04_fifo_chan *chan;
-	int ret;
-
-	nv_ioctl(parent, "create channel dma size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create channel dma vers %d pushbuf %08x "
-				 "offset %016llx\n", args->v0.version,
-			 args->v0.pushbuf, args->v0.offset);
-	} else
-		return ret;
-
-	ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
-					  0x10000, args->v0.pushbuf,
-					  (1ULL << NVDEV_ENGINE_DMAOBJ) |
-					  (1ULL << NVDEV_ENGINE_SW) |
-					  (1ULL << NVDEV_ENGINE_GR) |
-					  (1ULL << NVDEV_ENGINE_MPEG), /* NV31- */
-					  &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	args->v0.chid = chan->base.chid;
-
-	nv_parent(chan)->object_attach = nv04_fifo_object_attach;
-	nv_parent(chan)->object_detach = nv04_fifo_object_detach;
-	nv_parent(chan)->context_attach = nv04_fifo_context_attach;
-	chan->ramfc = chan->base.chid * 64;
-
-	nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset);
-	nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset);
-	nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4);
-	nv_wo32(priv->ramfc, chan->ramfc + 0x14,
-			     NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
-			     NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
-#ifdef __BIG_ENDIAN
-			     NV_PFIFO_CACHE1_BIG_ENDIAN |
-#endif
-			     NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
-	return 0;
-}
-
-static struct nouveau_ofuncs
-nv17_fifo_ofuncs = {
-	.ctor = nv17_fifo_chan_ctor,
-	.dtor = nv04_fifo_chan_dtor,
-	.init = nv04_fifo_chan_init,
-	.fini = nv04_fifo_chan_fini,
-	.map  = _nouveau_fifo_channel_map,
-	.rd32 = _nouveau_fifo_channel_rd32,
-	.wr32 = _nouveau_fifo_channel_wr32,
-	.ntfy = _nouveau_fifo_channel_ntfy
-};
-
-static struct nouveau_oclass
-nv17_fifo_sclass[] = {
-	{ NV17_CHANNEL_DMA, &nv17_fifo_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * FIFO context - basically just the instmem reserved for the channel
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv17_fifo_cclass = {
-	.handle = NV_ENGCTX(FIFO, 0x17),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fifo_context_ctor,
-		.dtor = _nouveau_fifo_context_dtor,
-		.init = _nouveau_fifo_context_init,
-		.fini = _nouveau_fifo_context_fini,
-		.rd32 = _nouveau_fifo_context_rd32,
-		.wr32 = _nouveau_fifo_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PFIFO engine
- ******************************************************************************/
-
-static int
-nv17_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv04_instmem_priv *imem = nv04_instmem(parent);
-	struct nv04_fifo_priv *priv;
-	int ret;
-
-	ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nouveau_ramht_ref(imem->ramht, &priv->ramht);
-	nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
-	nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
-
-	nv_subdev(priv)->unit = 0x00000100;
-	nv_subdev(priv)->intr = nv04_fifo_intr;
-	nv_engine(priv)->cclass = &nv17_fifo_cclass;
-	nv_engine(priv)->sclass = nv17_fifo_sclass;
-	priv->base.pause = nv04_fifo_pause;
-	priv->base.start = nv04_fifo_start;
-	priv->ramfc_desc = nv17_ramfc;
-	return 0;
-}
-
-static int
-nv17_fifo_init(struct nouveau_object *object)
-{
-	struct nv04_fifo_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_fifo_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, NV04_PFIFO_DELAY_0, 0x000000ff);
-	nv_wr32(priv, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);
-
-	nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
-				       ((priv->ramht->bits - 9) << 16) |
-				        (priv->ramht->base.addr >> 8));
-	nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8);
-	nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8 | 0x00010000);
-
-	nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max);
-
-	nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff);
-	nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff);
-
-	nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1);
-	nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
-	nv_wr32(priv, NV03_PFIFO_CACHES, 1);
-	return 0;
-}
-
-struct nouveau_oclass *
-nv17_fifo_oclass = &(struct nouveau_oclass) {
-	.handle = NV_ENGINE(FIFO, 0x17),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv17_fifo_ctor,
-		.dtor = nv04_fifo_dtor,
-		.init = nv17_fifo_init,
-		.fini = _nouveau_fifo_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
deleted file mode 100644
index 9f49c3a24dc6..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
+++ /dev/null
@@ -1,361 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-#include <core/engctx.h>
-#include <core/ramht.h>
-
-#include <subdev/instmem.h>
-#include <subdev/instmem/nv04.h>
-#include <subdev/fb.h>
-
-#include <engine/fifo.h>
-
-#include "nv04.h"
-
-static struct ramfc_desc
-nv40_ramfc[] = {
-	{ 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
-	{ 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
-	{ 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
-	{ 32,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
-	{ 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
-	{ 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_STATE },
-	{ 28,  0, 0x18,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
-	{  2, 28, 0x18, 28, 0x002058 },
-	{ 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_ENGINE },
-	{ 32,  0, 0x20,  0, NV04_PFIFO_CACHE1_PULL1 },
-	{ 32,  0, 0x24,  0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
-	{ 32,  0, 0x28,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
-	{ 32,  0, 0x2c,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
-	{ 32,  0, 0x30,  0, NV10_PFIFO_CACHE1_SEMAPHORE },
-	{ 32,  0, 0x34,  0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
-	{ 32,  0, 0x38,  0, NV40_PFIFO_GRCTX_INSTANCE },
-	{ 17,  0, 0x3c,  0, NV04_PFIFO_DMA_TIMESLICE },
-	{ 32,  0, 0x40,  0, 0x0032e4 },
-	{ 32,  0, 0x44,  0, 0x0032e8 },
-	{ 32,  0, 0x4c,  0, 0x002088 },
-	{ 32,  0, 0x50,  0, 0x003300 },
-	{ 32,  0, 0x54,  0, 0x00330c },
-	{}
-};
-
-/*******************************************************************************
- * FIFO channel objects
- ******************************************************************************/
-
-static int
-nv40_fifo_object_attach(struct nouveau_object *parent,
-			struct nouveau_object *object, u32 handle)
-{
-	struct nv04_fifo_priv *priv = (void *)parent->engine;
-	struct nv04_fifo_chan *chan = (void *)parent;
-	u32 context, chid = chan->base.chid;
-	int ret;
-
-	if (nv_iclass(object, NV_GPUOBJ_CLASS))
-		context = nv_gpuobj(object)->addr >> 4;
-	else
-		context = 0x00000004; /* just non-zero */
-
-	switch (nv_engidx(object->engine)) {
-	case NVDEV_ENGINE_DMAOBJ:
-	case NVDEV_ENGINE_SW:
-		context |= 0x00000000;
-		break;
-	case NVDEV_ENGINE_GR:
-		context |= 0x00100000;
-		break;
-	case NVDEV_ENGINE_MPEG:
-		context |= 0x00200000;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	context |= chid << 23;
-
-	mutex_lock(&nv_subdev(priv)->mutex);
-	ret = nouveau_ramht_insert(priv->ramht, chid, handle, context);
-	mutex_unlock(&nv_subdev(priv)->mutex);
-	return ret;
-}
-
-static int
-nv40_fifo_context_attach(struct nouveau_object *parent,
-			 struct nouveau_object *engctx)
-{
-	struct nv04_fifo_priv *priv = (void *)parent->engine;
-	struct nv04_fifo_chan *chan = (void *)parent;
-	unsigned long flags;
-	u32 reg, ctx;
-
-	switch (nv_engidx(engctx->engine)) {
-	case NVDEV_ENGINE_SW:
-		return 0;
-	case NVDEV_ENGINE_GR:
-		reg = 0x32e0;
-		ctx = 0x38;
-		break;
-	case NVDEV_ENGINE_MPEG:
-		reg = 0x330c;
-		ctx = 0x54;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	spin_lock_irqsave(&priv->base.lock, flags);
-	nv_engctx(engctx)->addr = nv_gpuobj(engctx)->addr >> 4;
-	nv_mask(priv, 0x002500, 0x00000001, 0x00000000);
-
-	if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid)
-		nv_wr32(priv, reg, nv_engctx(engctx)->addr);
-	nv_wo32(priv->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr);
-
-	nv_mask(priv, 0x002500, 0x00000001, 0x00000001);
-	spin_unlock_irqrestore(&priv->base.lock, flags);
-	return 0;
-}
-
-static int
-nv40_fifo_context_detach(struct nouveau_object *parent, bool suspend,
-			 struct nouveau_object *engctx)
-{
-	struct nv04_fifo_priv *priv = (void *)parent->engine;
-	struct nv04_fifo_chan *chan = (void *)parent;
-	unsigned long flags;
-	u32 reg, ctx;
-
-	switch (nv_engidx(engctx->engine)) {
-	case NVDEV_ENGINE_SW:
-		return 0;
-	case NVDEV_ENGINE_GR:
-		reg = 0x32e0;
-		ctx = 0x38;
-		break;
-	case NVDEV_ENGINE_MPEG:
-		reg = 0x330c;
-		ctx = 0x54;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	spin_lock_irqsave(&priv->base.lock, flags);
-	nv_mask(priv, 0x002500, 0x00000001, 0x00000000);
-
-	if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid)
-		nv_wr32(priv, reg, 0x00000000);
-	nv_wo32(priv->ramfc, chan->ramfc + ctx, 0x00000000);
-
-	nv_mask(priv, 0x002500, 0x00000001, 0x00000001);
-	spin_unlock_irqrestore(&priv->base.lock, flags);
-	return 0;
-}
-
-static int
-nv40_fifo_chan_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
-{
-	union {
-		struct nv03_channel_dma_v0 v0;
-	} *args = data;
-	struct nv04_fifo_priv *priv = (void *)engine;
-	struct nv04_fifo_chan *chan;
-	int ret;
-
-	nv_ioctl(parent, "create channel dma size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create channel dma vers %d pushbuf %08x "
-				 "offset %016llx\n", args->v0.version,
-			 args->v0.pushbuf, args->v0.offset);
-	} else
-		return ret;
-
-	ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
-					  0x1000, args->v0.pushbuf,
-					  (1ULL << NVDEV_ENGINE_DMAOBJ) |
-					  (1ULL << NVDEV_ENGINE_SW) |
-					  (1ULL << NVDEV_ENGINE_GR) |
-					  (1ULL << NVDEV_ENGINE_MPEG), &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	args->v0.chid = chan->base.chid;
-
-	nv_parent(chan)->context_attach = nv40_fifo_context_attach;
-	nv_parent(chan)->context_detach = nv40_fifo_context_detach;
-	nv_parent(chan)->object_attach = nv40_fifo_object_attach;
-	nv_parent(chan)->object_detach = nv04_fifo_object_detach;
-	chan->ramfc = chan->base.chid * 128;
-
-	nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset);
-	nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset);
-	nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4);
-	nv_wo32(priv->ramfc, chan->ramfc + 0x18, 0x30000000 |
-			     NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
-			     NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
-#ifdef __BIG_ENDIAN
-			     NV_PFIFO_CACHE1_BIG_ENDIAN |
-#endif
-			     NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
-	nv_wo32(priv->ramfc, chan->ramfc + 0x3c, 0x0001ffff);
-	return 0;
-}
-
-static struct nouveau_ofuncs
-nv40_fifo_ofuncs = {
-	.ctor = nv40_fifo_chan_ctor,
-	.dtor = nv04_fifo_chan_dtor,
-	.init = nv04_fifo_chan_init,
-	.fini = nv04_fifo_chan_fini,
-	.map  = _nouveau_fifo_channel_map,
-	.rd32 = _nouveau_fifo_channel_rd32,
-	.wr32 = _nouveau_fifo_channel_wr32,
-	.ntfy = _nouveau_fifo_channel_ntfy
-};
-
-static struct nouveau_oclass
-nv40_fifo_sclass[] = {
-	{ NV40_CHANNEL_DMA, &nv40_fifo_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * FIFO context - basically just the instmem reserved for the channel
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv40_fifo_cclass = {
-	.handle = NV_ENGCTX(FIFO, 0x40),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fifo_context_ctor,
-		.dtor = _nouveau_fifo_context_dtor,
-		.init = _nouveau_fifo_context_init,
-		.fini = _nouveau_fifo_context_fini,
-		.rd32 = _nouveau_fifo_context_rd32,
-		.wr32 = _nouveau_fifo_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PFIFO engine
- ******************************************************************************/
-
-static int
-nv40_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv04_instmem_priv *imem = nv04_instmem(parent);
-	struct nv04_fifo_priv *priv;
-	int ret;
-
-	ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nouveau_ramht_ref(imem->ramht, &priv->ramht);
-	nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
-	nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
-
-	nv_subdev(priv)->unit = 0x00000100;
-	nv_subdev(priv)->intr = nv04_fifo_intr;
-	nv_engine(priv)->cclass = &nv40_fifo_cclass;
-	nv_engine(priv)->sclass = nv40_fifo_sclass;
-	priv->base.pause = nv04_fifo_pause;
-	priv->base.start = nv04_fifo_start;
-	priv->ramfc_desc = nv40_ramfc;
-	return 0;
-}
-
-static int
-nv40_fifo_init(struct nouveau_object *object)
-{
-	struct nv04_fifo_priv *priv = (void *)object;
-	struct nouveau_fb *pfb = nouveau_fb(object);
-	int ret;
-
-	ret = nouveau_fifo_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x002040, 0x000000ff);
-	nv_wr32(priv, 0x002044, 0x2101ffff);
-	nv_wr32(priv, 0x002058, 0x00000001);
-
-	nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
-				       ((priv->ramht->bits - 9) << 16) |
-				        (priv->ramht->base.addr >> 8));
-	nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8);
-
-	switch (nv_device(priv)->chipset) {
-	case 0x47:
-	case 0x49:
-	case 0x4b:
-		nv_wr32(priv, 0x002230, 0x00000001);
-	case 0x40:
-	case 0x41:
-	case 0x42:
-	case 0x43:
-	case 0x45:
-	case 0x48:
-		nv_wr32(priv, 0x002220, 0x00030002);
-		break;
-	default:
-		nv_wr32(priv, 0x002230, 0x00000000);
-		nv_wr32(priv, 0x002220, ((pfb->ram->size - 512 * 1024 +
-					 priv->ramfc->addr) >> 16) |
-					0x00030000);
-		break;
-	}
-
-	nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max);
-
-	nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff);
-	nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff);
-
-	nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1);
-	nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
-	nv_wr32(priv, NV03_PFIFO_CACHES, 1);
-	return 0;
-}
-
-struct nouveau_oclass *
-nv40_fifo_oclass = &(struct nouveau_oclass) {
-	.handle = NV_ENGINE(FIFO, 0x40),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv40_fifo_ctor,
-		.dtor = nv04_fifo_dtor,
-		.init = nv40_fifo_init,
-		.fini = _nouveau_fifo_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
deleted file mode 100644
index 5d1e86bc244c..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
+++ /dev/null
@@ -1,541 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <core/engctx.h>
-#include <core/ramht.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/timer.h>
-#include <subdev/bar.h>
-
-#include <engine/dmaobj.h>
-#include <engine/fifo.h>
-
-#include "nv04.h"
-#include "nv50.h"
-
-/*******************************************************************************
- * FIFO channel objects
- ******************************************************************************/
-
-static void
-nv50_fifo_playlist_update_locked(struct nv50_fifo_priv *priv)
-{
-	struct nouveau_bar *bar = nouveau_bar(priv);
-	struct nouveau_gpuobj *cur;
-	int i, p;
-
-	cur = priv->playlist[priv->cur_playlist];
-	priv->cur_playlist = !priv->cur_playlist;
-
-	for (i = priv->base.min, p = 0; i < priv->base.max; i++) {
-		if (nv_rd32(priv, 0x002600 + (i * 4)) & 0x80000000)
-			nv_wo32(cur, p++ * 4, i);
-	}
-
-	bar->flush(bar);
-
-	nv_wr32(priv, 0x0032f4, cur->addr >> 12);
-	nv_wr32(priv, 0x0032ec, p);
-	nv_wr32(priv, 0x002500, 0x00000101);
-}
-
-void
-nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
-{
-	mutex_lock(&nv_subdev(priv)->mutex);
-	nv50_fifo_playlist_update_locked(priv);
-	mutex_unlock(&nv_subdev(priv)->mutex);
-}
-
-static int
-nv50_fifo_context_attach(struct nouveau_object *parent,
-			 struct nouveau_object *object)
-{
-	struct nouveau_bar *bar = nouveau_bar(parent);
-	struct nv50_fifo_base *base = (void *)parent->parent;
-	struct nouveau_gpuobj *ectx = (void *)object;
-	u64 limit = ectx->addr + ectx->size - 1;
-	u64 start = ectx->addr;
-	u32 addr;
-
-	switch (nv_engidx(object->engine)) {
-	case NVDEV_ENGINE_SW   : return 0;
-	case NVDEV_ENGINE_GR   : addr = 0x0000; break;
-	case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
-	default:
-		return -EINVAL;
-	}
-
-	nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
-	nv_wo32(base->eng, addr + 0x00, 0x00190000);
-	nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
-	nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
-	nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 |
-					upper_32_bits(start));
-	nv_wo32(base->eng, addr + 0x10, 0x00000000);
-	nv_wo32(base->eng, addr + 0x14, 0x00000000);
-	bar->flush(bar);
-	return 0;
-}
-
-static int
-nv50_fifo_context_detach(struct nouveau_object *parent, bool suspend,
-			 struct nouveau_object *object)
-{
-	struct nouveau_bar *bar = nouveau_bar(parent);
-	struct nv50_fifo_priv *priv = (void *)parent->engine;
-	struct nv50_fifo_base *base = (void *)parent->parent;
-	struct nv50_fifo_chan *chan = (void *)parent;
-	u32 addr, me;
-	int ret = 0;
-
-	switch (nv_engidx(object->engine)) {
-	case NVDEV_ENGINE_SW   : return 0;
-	case NVDEV_ENGINE_GR   : addr = 0x0000; break;
-	case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
-	default:
-		return -EINVAL;
-	}
-
-	/* HW bug workaround:
-	 *
-	 * PFIFO will hang forever if the connected engines don't report
-	 * that they've processed the context switch request.
-	 *
-	 * In order for the kickoff to work, we need to ensure all the
-	 * connected engines are in a state where they can answer.
-	 *
-	 * Newer chipsets don't seem to suffer from this issue, and well,
-	 * there's also a "ignore these engines" bitmask reg we can use
-	 * if we hit the issue there..
-	 */
-	me = nv_mask(priv, 0x00b860, 0x00000001, 0x00000001);
-
-	/* do the kickoff... */
-	nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
-	if (!nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff)) {
-		nv_error(priv, "channel %d [%s] unload timeout\n",
-			 chan->base.chid, nouveau_client_name(chan));
-		if (suspend)
-			ret = -EBUSY;
-	}
-	nv_wr32(priv, 0x00b860, me);
-
-	if (ret == 0) {
-		nv_wo32(base->eng, addr + 0x00, 0x00000000);
-		nv_wo32(base->eng, addr + 0x04, 0x00000000);
-		nv_wo32(base->eng, addr + 0x08, 0x00000000);
-		nv_wo32(base->eng, addr + 0x0c, 0x00000000);
-		nv_wo32(base->eng, addr + 0x10, 0x00000000);
-		nv_wo32(base->eng, addr + 0x14, 0x00000000);
-		bar->flush(bar);
-	}
-
-	return ret;
-}
-
-static int
-nv50_fifo_object_attach(struct nouveau_object *parent,
-			struct nouveau_object *object, u32 handle)
-{
-	struct nv50_fifo_chan *chan = (void *)parent;
-	u32 context;
-
-	if (nv_iclass(object, NV_GPUOBJ_CLASS))
-		context = nv_gpuobj(object)->node->offset >> 4;
-	else
-		context = 0x00000004; /* just non-zero */
-
-	switch (nv_engidx(object->engine)) {
-	case NVDEV_ENGINE_DMAOBJ:
-	case NVDEV_ENGINE_SW    : context |= 0x00000000; break;
-	case NVDEV_ENGINE_GR    : context |= 0x00100000; break;
-	case NVDEV_ENGINE_MPEG  : context |= 0x00200000; break;
-	default:
-		return -EINVAL;
-	}
-
-	return nouveau_ramht_insert(chan->ramht, 0, handle, context);
-}
-
-void
-nv50_fifo_object_detach(struct nouveau_object *parent, int cookie)
-{
-	struct nv50_fifo_chan *chan = (void *)parent;
-	nouveau_ramht_remove(chan->ramht, cookie);
-}
-
-static int
-nv50_fifo_chan_ctor_dma(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass, void *data, u32 size,
-			struct nouveau_object **pobject)
-{
-	union {
-		struct nv03_channel_dma_v0 v0;
-	} *args = data;
-	struct nouveau_bar *bar = nouveau_bar(parent);
-	struct nv50_fifo_base *base = (void *)parent;
-	struct nv50_fifo_chan *chan;
-	int ret;
-
-	nv_ioctl(parent, "create channel dma size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create channel dma vers %d pushbuf %08x "
-				 "offset %016llx\n", args->v0.version,
-			 args->v0.pushbuf, args->v0.offset);
-	} else
-		return ret;
-
-	ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
-					  0x2000, args->v0.pushbuf,
-					  (1ULL << NVDEV_ENGINE_DMAOBJ) |
-					  (1ULL << NVDEV_ENGINE_SW) |
-					  (1ULL << NVDEV_ENGINE_GR) |
-					  (1ULL << NVDEV_ENGINE_MPEG), &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	args->v0.chid = chan->base.chid;
-
-	nv_parent(chan)->context_attach = nv50_fifo_context_attach;
-	nv_parent(chan)->context_detach = nv50_fifo_context_detach;
-	nv_parent(chan)->object_attach = nv50_fifo_object_attach;
-	nv_parent(chan)->object_detach = nv50_fifo_object_detach;
-
-	ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
-				&chan->ramht);
-	if (ret)
-		return ret;
-
-	nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset));
-	nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset));
-	nv_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset));
-	nv_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset));
-	nv_wo32(base->ramfc, 0x3c, 0x003f6078);
-	nv_wo32(base->ramfc, 0x44, 0x01003fff);
-	nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
-	nv_wo32(base->ramfc, 0x4c, 0xffffffff);
-	nv_wo32(base->ramfc, 0x60, 0x7fffffff);
-	nv_wo32(base->ramfc, 0x78, 0x00000000);
-	nv_wo32(base->ramfc, 0x7c, 0x30000001);
-	nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
-				   (4 << 24) /* SEARCH_FULL */ |
-				   (chan->ramht->base.node->offset >> 4));
-	bar->flush(bar);
-	return 0;
-}
-
-static int
-nv50_fifo_chan_ctor_ind(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass, void *data, u32 size,
-			struct nouveau_object **pobject)
-{
-	union {
-		struct nv50_channel_gpfifo_v0 v0;
-	} *args = data;
-	struct nouveau_bar *bar = nouveau_bar(parent);
-	struct nv50_fifo_base *base = (void *)parent;
-	struct nv50_fifo_chan *chan;
-	u64 ioffset, ilength;
-	int ret;
-
-	nv_ioctl(parent, "create channel gpfifo size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x "
-				 "ioffset %016llx ilength %08x\n",
-			 args->v0.version, args->v0.pushbuf, args->v0.ioffset,
-			 args->v0.ilength);
-	} else
-		return ret;
-
-	ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
-					  0x2000, args->v0.pushbuf,
-					  (1ULL << NVDEV_ENGINE_DMAOBJ) |
-					  (1ULL << NVDEV_ENGINE_SW) |
-					  (1ULL << NVDEV_ENGINE_GR) |
-					  (1ULL << NVDEV_ENGINE_MPEG), &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	args->v0.chid = chan->base.chid;
-
-	nv_parent(chan)->context_attach = nv50_fifo_context_attach;
-	nv_parent(chan)->context_detach = nv50_fifo_context_detach;
-	nv_parent(chan)->object_attach = nv50_fifo_object_attach;
-	nv_parent(chan)->object_detach = nv50_fifo_object_detach;
-
-	ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
-			       &chan->ramht);
-	if (ret)
-		return ret;
-
-	ioffset = args->v0.ioffset;
-	ilength = order_base_2(args->v0.ilength / 8);
-
-	nv_wo32(base->ramfc, 0x3c, 0x403f6078);
-	nv_wo32(base->ramfc, 0x44, 0x01003fff);
-	nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
-	nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));
-	nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
-	nv_wo32(base->ramfc, 0x60, 0x7fffffff);
-	nv_wo32(base->ramfc, 0x78, 0x00000000);
-	nv_wo32(base->ramfc, 0x7c, 0x30000001);
-	nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
-				   (4 << 24) /* SEARCH_FULL */ |
-				   (chan->ramht->base.node->offset >> 4));
-	bar->flush(bar);
-	return 0;
-}
-
-void
-nv50_fifo_chan_dtor(struct nouveau_object *object)
-{
-	struct nv50_fifo_chan *chan = (void *)object;
-	nouveau_ramht_ref(NULL, &chan->ramht);
-	nouveau_fifo_channel_destroy(&chan->base);
-}
-
-static int
-nv50_fifo_chan_init(struct nouveau_object *object)
-{
-	struct nv50_fifo_priv *priv = (void *)object->engine;
-	struct nv50_fifo_base *base = (void *)object->parent;
-	struct nv50_fifo_chan *chan = (void *)object;
-	struct nouveau_gpuobj *ramfc = base->ramfc;
-	u32 chid = chan->base.chid;
-	int ret;
-
-	ret = nouveau_fifo_channel_init(&chan->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 12);
-	nv50_fifo_playlist_update(priv);
-	return 0;
-}
-
-int
-nv50_fifo_chan_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv50_fifo_priv *priv = (void *)object->engine;
-	struct nv50_fifo_chan *chan = (void *)object;
-	u32 chid = chan->base.chid;
-
-	/* remove channel from playlist, fifo will unload context */
-	nv_mask(priv, 0x002600 + (chid * 4), 0x80000000, 0x00000000);
-	nv50_fifo_playlist_update(priv);
-	nv_wr32(priv, 0x002600 + (chid * 4), 0x00000000);
-
-	return nouveau_fifo_channel_fini(&chan->base, suspend);
-}
-
-static struct nouveau_ofuncs
-nv50_fifo_ofuncs_dma = {
-	.ctor = nv50_fifo_chan_ctor_dma,
-	.dtor = nv50_fifo_chan_dtor,
-	.init = nv50_fifo_chan_init,
-	.fini = nv50_fifo_chan_fini,
-	.map  = _nouveau_fifo_channel_map,
-	.rd32 = _nouveau_fifo_channel_rd32,
-	.wr32 = _nouveau_fifo_channel_wr32,
-	.ntfy = _nouveau_fifo_channel_ntfy
-};
-
-static struct nouveau_ofuncs
-nv50_fifo_ofuncs_ind = {
-	.ctor = nv50_fifo_chan_ctor_ind,
-	.dtor = nv50_fifo_chan_dtor,
-	.init = nv50_fifo_chan_init,
-	.fini = nv50_fifo_chan_fini,
-	.map  = _nouveau_fifo_channel_map,
-	.rd32 = _nouveau_fifo_channel_rd32,
-	.wr32 = _nouveau_fifo_channel_wr32,
-	.ntfy = _nouveau_fifo_channel_ntfy
-};
-
-static struct nouveau_oclass
-nv50_fifo_sclass[] = {
-	{ NV50_CHANNEL_DMA, &nv50_fifo_ofuncs_dma },
-	{ NV50_CHANNEL_GPFIFO, &nv50_fifo_ofuncs_ind },
-	{}
-};
-
-/*******************************************************************************
- * FIFO context - basically just the instmem reserved for the channel
- ******************************************************************************/
-
-static int
-nv50_fifo_context_ctor(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, void *data, u32 size,
-		       struct nouveau_object **pobject)
-{
-	struct nv50_fifo_base *base;
-	int ret;
-
-	ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
-				          0x1000, NVOBJ_FLAG_HEAP, &base);
-	*pobject = nv_object(base);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0200,
-				 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x1200, 0,
-				 NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, 0,
-				&base->pgd);
-	if (ret)
-		return ret;
-
-	ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-void
-nv50_fifo_context_dtor(struct nouveau_object *object)
-{
-	struct nv50_fifo_base *base = (void *)object;
-	nouveau_vm_ref(NULL, &base->vm, base->pgd);
-	nouveau_gpuobj_ref(NULL, &base->pgd);
-	nouveau_gpuobj_ref(NULL, &base->eng);
-	nouveau_gpuobj_ref(NULL, &base->ramfc);
-	nouveau_gpuobj_ref(NULL, &base->cache);
-	nouveau_fifo_context_destroy(&base->base);
-}
-
-static struct nouveau_oclass
-nv50_fifo_cclass = {
-	.handle = NV_ENGCTX(FIFO, 0x50),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_fifo_context_ctor,
-		.dtor = nv50_fifo_context_dtor,
-		.init = _nouveau_fifo_context_init,
-		.fini = _nouveau_fifo_context_fini,
-		.rd32 = _nouveau_fifo_context_rd32,
-		.wr32 = _nouveau_fifo_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PFIFO engine
- ******************************************************************************/
-
-static int
-nv50_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv50_fifo_priv *priv;
-	int ret;
-
-	ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
-				&priv->playlist[0]);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
-				&priv->playlist[1]);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00000100;
-	nv_subdev(priv)->intr = nv04_fifo_intr;
-	nv_engine(priv)->cclass = &nv50_fifo_cclass;
-	nv_engine(priv)->sclass = nv50_fifo_sclass;
-	priv->base.pause = nv04_fifo_pause;
-	priv->base.start = nv04_fifo_start;
-	return 0;
-}
-
-void
-nv50_fifo_dtor(struct nouveau_object *object)
-{
-	struct nv50_fifo_priv *priv = (void *)object;
-
-	nouveau_gpuobj_ref(NULL, &priv->playlist[1]);
-	nouveau_gpuobj_ref(NULL, &priv->playlist[0]);
-
-	nouveau_fifo_destroy(&priv->base);
-}
-
-int
-nv50_fifo_init(struct nouveau_object *object)
-{
-	struct nv50_fifo_priv *priv = (void *)object;
-	int ret, i;
-
-	ret = nouveau_fifo_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
-	nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
-	nv_wr32(priv, 0x00250c, 0x6f3cfc34);
-	nv_wr32(priv, 0x002044, 0x01003fff);
-
-	nv_wr32(priv, 0x002100, 0xffffffff);
-	nv_wr32(priv, 0x002140, 0xbfffffff);
-
-	for (i = 0; i < 128; i++)
-		nv_wr32(priv, 0x002600 + (i * 4), 0x00000000);
-	nv50_fifo_playlist_update_locked(priv);
-
-	nv_wr32(priv, 0x003200, 0x00000001);
-	nv_wr32(priv, 0x003250, 0x00000001);
-	nv_wr32(priv, 0x002500, 0x00000001);
-	return 0;
-}
-
-struct nouveau_oclass *
-nv50_fifo_oclass = &(struct nouveau_oclass) {
-	.handle = NV_ENGINE(FIFO, 0x50),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_fifo_ctor,
-		.dtor = nv50_fifo_dtor,
-		.init = nv50_fifo_init,
-		.fini = _nouveau_fifo_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.h b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.h
deleted file mode 100644
index 3a9ceb315c20..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef __NV50_FIFO_H__
-#define __NV50_FIFO_H__
-
-struct nv50_fifo_priv {
-	struct nouveau_fifo base;
-	struct nouveau_gpuobj *playlist[2];
-	int cur_playlist;
-};
-
-struct nv50_fifo_base {
-	struct nouveau_fifo_base base;
-	struct nouveau_gpuobj *ramfc;
-	struct nouveau_gpuobj *cache;
-	struct nouveau_gpuobj *eng;
-	struct nouveau_gpuobj *pgd;
-	struct nouveau_vm *vm;
-};
-
-struct nv50_fifo_chan {
-	struct nouveau_fifo_chan base;
-	u32 subc[8];
-	struct nouveau_ramht *ramht;
-};
-
-void nv50_fifo_playlist_update(struct nv50_fifo_priv *);
-
-void nv50_fifo_object_detach(struct nouveau_object *, int);
-void nv50_fifo_chan_dtor(struct nouveau_object *);
-int  nv50_fifo_chan_fini(struct nouveau_object *, bool);
-
-void nv50_fifo_context_dtor(struct nouveau_object *);
-
-void nv50_fifo_dtor(struct nouveau_object *);
-int  nv50_fifo_init(struct nouveau_object *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
deleted file mode 100644
index 1f42996b354a..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
+++ /dev/null
@@ -1,481 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/os.h>
-#include <core/client.h>
-#include <core/engctx.h>
-#include <core/ramht.h>
-#include <core/event.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/timer.h>
-#include <subdev/bar.h>
-
-#include <engine/dmaobj.h>
-#include <engine/fifo.h>
-
-#include "nv04.h"
-#include "nv50.h"
-
-/*******************************************************************************
- * FIFO channel objects
- ******************************************************************************/
-
-static int
-nv84_fifo_context_attach(struct nouveau_object *parent,
-			 struct nouveau_object *object)
-{
-	struct nouveau_bar *bar = nouveau_bar(parent);
-	struct nv50_fifo_base *base = (void *)parent->parent;
-	struct nouveau_gpuobj *ectx = (void *)object;
-	u64 limit = ectx->addr + ectx->size - 1;
-	u64 start = ectx->addr;
-	u32 addr;
-
-	switch (nv_engidx(object->engine)) {
-	case NVDEV_ENGINE_SW   : return 0;
-	case NVDEV_ENGINE_GR   : addr = 0x0020; break;
-	case NVDEV_ENGINE_VP   : addr = 0x0040; break;
-	case NVDEV_ENGINE_PPP  :
-	case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
-	case NVDEV_ENGINE_BSP  : addr = 0x0080; break;
-	case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
-	case NVDEV_ENGINE_COPY0: addr = 0x00c0; break;
-	default:
-		return -EINVAL;
-	}
-
-	nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
-	nv_wo32(base->eng, addr + 0x00, 0x00190000);
-	nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
-	nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
-	nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 |
-					upper_32_bits(start));
-	nv_wo32(base->eng, addr + 0x10, 0x00000000);
-	nv_wo32(base->eng, addr + 0x14, 0x00000000);
-	bar->flush(bar);
-	return 0;
-}
-
-static int
-nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
-			 struct nouveau_object *object)
-{
-	struct nouveau_bar *bar = nouveau_bar(parent);
-	struct nv50_fifo_priv *priv = (void *)parent->engine;
-	struct nv50_fifo_base *base = (void *)parent->parent;
-	struct nv50_fifo_chan *chan = (void *)parent;
-	u32 addr, save, engn;
-	bool done;
-
-	switch (nv_engidx(object->engine)) {
-	case NVDEV_ENGINE_SW   : return 0;
-	case NVDEV_ENGINE_GR   : engn = 0; addr = 0x0020; break;
-	case NVDEV_ENGINE_VP   : engn = 3; addr = 0x0040; break;
-	case NVDEV_ENGINE_PPP  :
-	case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
-	case NVDEV_ENGINE_BSP  : engn = 5; addr = 0x0080; break;
-	case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;
-	case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break;
-	default:
-		return -EINVAL;
-	}
-
-	save = nv_mask(priv, 0x002520, 0x0000003f, 1 << engn);
-	nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
-	done = nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff);
-	nv_wr32(priv, 0x002520, save);
-	if (!done) {
-		nv_error(priv, "channel %d [%s] unload timeout\n",
-			 chan->base.chid, nouveau_client_name(chan));
-		if (suspend)
-			return -EBUSY;
-	}
-
-	nv_wo32(base->eng, addr + 0x00, 0x00000000);
-	nv_wo32(base->eng, addr + 0x04, 0x00000000);
-	nv_wo32(base->eng, addr + 0x08, 0x00000000);
-	nv_wo32(base->eng, addr + 0x0c, 0x00000000);
-	nv_wo32(base->eng, addr + 0x10, 0x00000000);
-	nv_wo32(base->eng, addr + 0x14, 0x00000000);
-	bar->flush(bar);
-	return 0;
-}
-
-static int
-nv84_fifo_object_attach(struct nouveau_object *parent,
-			struct nouveau_object *object, u32 handle)
-{
-	struct nv50_fifo_chan *chan = (void *)parent;
-	u32 context;
-
-	if (nv_iclass(object, NV_GPUOBJ_CLASS))
-		context = nv_gpuobj(object)->node->offset >> 4;
-	else
-		context = 0x00000004; /* just non-zero */
-
-	switch (nv_engidx(object->engine)) {
-	case NVDEV_ENGINE_DMAOBJ:
-	case NVDEV_ENGINE_SW    : context |= 0x00000000; break;
-	case NVDEV_ENGINE_GR    : context |= 0x00100000; break;
-	case NVDEV_ENGINE_MPEG  :
-	case NVDEV_ENGINE_PPP   : context |= 0x00200000; break;
-	case NVDEV_ENGINE_ME    :
-	case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break;
-	case NVDEV_ENGINE_VP    : context |= 0x00400000; break;
-	case NVDEV_ENGINE_CRYPT :
-	case NVDEV_ENGINE_VIC   : context |= 0x00500000; break;
-	case NVDEV_ENGINE_BSP   : context |= 0x00600000; break;
-	default:
-		return -EINVAL;
-	}
-
-	return nouveau_ramht_insert(chan->ramht, 0, handle, context);
-}
-
-static int
-nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass, void *data, u32 size,
-			struct nouveau_object **pobject)
-{
-	union {
-		struct nv03_channel_dma_v0 v0;
-	} *args = data;
-	struct nouveau_bar *bar = nouveau_bar(parent);
-	struct nv50_fifo_base *base = (void *)parent;
-	struct nv50_fifo_chan *chan;
-	int ret;
-
-	nv_ioctl(parent, "create channel dma size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create channel dma vers %d pushbuf %08x "
-				 "offset %016llx\n", args->v0.version,
-			 args->v0.pushbuf, args->v0.offset);
-	} else
-		return ret;
-
-	ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
-					  0x2000, args->v0.pushbuf,
-					  (1ULL << NVDEV_ENGINE_DMAOBJ) |
-					  (1ULL << NVDEV_ENGINE_SW) |
-					  (1ULL << NVDEV_ENGINE_GR) |
-					  (1ULL << NVDEV_ENGINE_MPEG) |
-					  (1ULL << NVDEV_ENGINE_ME) |
-					  (1ULL << NVDEV_ENGINE_VP) |
-					  (1ULL << NVDEV_ENGINE_CRYPT) |
-					  (1ULL << NVDEV_ENGINE_BSP) |
-					  (1ULL << NVDEV_ENGINE_PPP) |
-					  (1ULL << NVDEV_ENGINE_COPY0) |
-					  (1ULL << NVDEV_ENGINE_VIC), &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	args->v0.chid = chan->base.chid;
-
-	ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
-			       &chan->ramht);
-	if (ret)
-		return ret;
-
-	nv_parent(chan)->context_attach = nv84_fifo_context_attach;
-	nv_parent(chan)->context_detach = nv84_fifo_context_detach;
-	nv_parent(chan)->object_attach = nv84_fifo_object_attach;
-	nv_parent(chan)->object_detach = nv50_fifo_object_detach;
-
-	nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset));
-	nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset));
-	nv_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset));
-	nv_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset));
-	nv_wo32(base->ramfc, 0x3c, 0x003f6078);
-	nv_wo32(base->ramfc, 0x44, 0x01003fff);
-	nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
-	nv_wo32(base->ramfc, 0x4c, 0xffffffff);
-	nv_wo32(base->ramfc, 0x60, 0x7fffffff);
-	nv_wo32(base->ramfc, 0x78, 0x00000000);
-	nv_wo32(base->ramfc, 0x7c, 0x30000001);
-	nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
-				   (4 << 24) /* SEARCH_FULL */ |
-				   (chan->ramht->base.node->offset >> 4));
-	nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
-	nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
-	bar->flush(bar);
-	return 0;
-}
-
-static int
-nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass, void *data, u32 size,
-			struct nouveau_object **pobject)
-{
-	union {
-		struct nv50_channel_gpfifo_v0 v0;
-	} *args = data;
-	struct nouveau_bar *bar = nouveau_bar(parent);
-	struct nv50_fifo_base *base = (void *)parent;
-	struct nv50_fifo_chan *chan;
-	u64 ioffset, ilength;
-	int ret;
-
-	nv_ioctl(parent, "create channel gpfifo size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x "
-				 "ioffset %016llx ilength %08x\n",
-			 args->v0.version, args->v0.pushbuf, args->v0.ioffset,
-			 args->v0.ilength);
-	} else
-		return ret;
-
-	ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
-					  0x2000, args->v0.pushbuf,
-					  (1ULL << NVDEV_ENGINE_DMAOBJ) |
-					  (1ULL << NVDEV_ENGINE_SW) |
-					  (1ULL << NVDEV_ENGINE_GR) |
-					  (1ULL << NVDEV_ENGINE_MPEG) |
-					  (1ULL << NVDEV_ENGINE_ME) |
-					  (1ULL << NVDEV_ENGINE_VP) |
-					  (1ULL << NVDEV_ENGINE_CRYPT) |
-					  (1ULL << NVDEV_ENGINE_BSP) |
-					  (1ULL << NVDEV_ENGINE_PPP) |
-					  (1ULL << NVDEV_ENGINE_COPY0) |
-					  (1ULL << NVDEV_ENGINE_VIC), &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	args->v0.chid = chan->base.chid;
-
-	ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
-			       &chan->ramht);
-	if (ret)
-		return ret;
-
-	nv_parent(chan)->context_attach = nv84_fifo_context_attach;
-	nv_parent(chan)->context_detach = nv84_fifo_context_detach;
-	nv_parent(chan)->object_attach = nv84_fifo_object_attach;
-	nv_parent(chan)->object_detach = nv50_fifo_object_detach;
-
-	ioffset = args->v0.ioffset;
-	ilength = order_base_2(args->v0.ilength / 8);
-
-	nv_wo32(base->ramfc, 0x3c, 0x403f6078);
-	nv_wo32(base->ramfc, 0x44, 0x01003fff);
-	nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
-	nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));
-	nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
-	nv_wo32(base->ramfc, 0x60, 0x7fffffff);
-	nv_wo32(base->ramfc, 0x78, 0x00000000);
-	nv_wo32(base->ramfc, 0x7c, 0x30000001);
-	nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
-				   (4 << 24) /* SEARCH_FULL */ |
-				   (chan->ramht->base.node->offset >> 4));
-	nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
-	nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
-	bar->flush(bar);
-	return 0;
-}
-
-static int
-nv84_fifo_chan_init(struct nouveau_object *object)
-{
-	struct nv50_fifo_priv *priv = (void *)object->engine;
-	struct nv50_fifo_base *base = (void *)object->parent;
-	struct nv50_fifo_chan *chan = (void *)object;
-	struct nouveau_gpuobj *ramfc = base->ramfc;
-	u32 chid = chan->base.chid;
-	int ret;
-
-	ret = nouveau_fifo_channel_init(&chan->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8);
-	nv50_fifo_playlist_update(priv);
-	return 0;
-}
-
-static struct nouveau_ofuncs
-nv84_fifo_ofuncs_dma = {
-	.ctor = nv84_fifo_chan_ctor_dma,
-	.dtor = nv50_fifo_chan_dtor,
-	.init = nv84_fifo_chan_init,
-	.fini = nv50_fifo_chan_fini,
-	.map  = _nouveau_fifo_channel_map,
-	.rd32 = _nouveau_fifo_channel_rd32,
-	.wr32 = _nouveau_fifo_channel_wr32,
-	.ntfy = _nouveau_fifo_channel_ntfy
-};
-
-static struct nouveau_ofuncs
-nv84_fifo_ofuncs_ind = {
-	.ctor = nv84_fifo_chan_ctor_ind,
-	.dtor = nv50_fifo_chan_dtor,
-	.init = nv84_fifo_chan_init,
-	.fini = nv50_fifo_chan_fini,
-	.map  = _nouveau_fifo_channel_map,
-	.rd32 = _nouveau_fifo_channel_rd32,
-	.wr32 = _nouveau_fifo_channel_wr32,
-	.ntfy = _nouveau_fifo_channel_ntfy
-};
-
-static struct nouveau_oclass
-nv84_fifo_sclass[] = {
-	{ G82_CHANNEL_DMA, &nv84_fifo_ofuncs_dma },
-	{ G82_CHANNEL_GPFIFO, &nv84_fifo_ofuncs_ind },
-	{}
-};
-
-/*******************************************************************************
- * FIFO context - basically just the instmem reserved for the channel
- ******************************************************************************/
-
-static int
-nv84_fifo_context_ctor(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, void *data, u32 size,
-		       struct nouveau_object **pobject)
-{
-	struct nv50_fifo_base *base;
-	int ret;
-
-	ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
-				          0x1000, NVOBJ_FLAG_HEAP, &base);
-	*pobject = nv_object(base);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0200, 0,
-				 NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0,
-				 0, &base->pgd);
-	if (ret)
-		return ret;
-
-	ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x1000,
-				 0x400, NVOBJ_FLAG_ZERO_ALLOC, &base->cache);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0100,
-				 0x100, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-static struct nouveau_oclass
-nv84_fifo_cclass = {
-	.handle = NV_ENGCTX(FIFO, 0x84),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv84_fifo_context_ctor,
-		.dtor = nv50_fifo_context_dtor,
-		.init = _nouveau_fifo_context_init,
-		.fini = _nouveau_fifo_context_fini,
-		.rd32 = _nouveau_fifo_context_rd32,
-		.wr32 = _nouveau_fifo_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PFIFO engine
- ******************************************************************************/
-
-static void
-nv84_fifo_uevent_init(struct nvkm_event *event, int type, int index)
-{
-	struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent);
-	nv_mask(fifo, 0x002140, 0x40000000, 0x40000000);
-}
-
-static void
-nv84_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
-{
-	struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent);
-	nv_mask(fifo, 0x002140, 0x40000000, 0x00000000);
-}
-
-static const struct nvkm_event_func
-nv84_fifo_uevent_func = {
-	.ctor = nouveau_fifo_uevent_ctor,
-	.init = nv84_fifo_uevent_init,
-	.fini = nv84_fifo_uevent_fini,
-};
-
-static int
-nv84_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv50_fifo_priv *priv;
-	int ret;
-
-	ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
-				&priv->playlist[0]);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
-				&priv->playlist[1]);
-	if (ret)
-		return ret;
-
-	ret = nvkm_event_init(&nv84_fifo_uevent_func, 1, 1, &priv->base.uevent);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00000100;
-	nv_subdev(priv)->intr = nv04_fifo_intr;
-	nv_engine(priv)->cclass = &nv84_fifo_cclass;
-	nv_engine(priv)->sclass = nv84_fifo_sclass;
-	priv->base.pause = nv04_fifo_pause;
-	priv->base.start = nv04_fifo_start;
-	return 0;
-}
-
-struct nouveau_oclass *
-nv84_fifo_oclass = &(struct nouveau_oclass) {
-	.handle = NV_ENGINE(FIFO, 0x84),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv84_fifo_ctor,
-		.dtor = nv50_fifo_dtor,
-		.init = nv50_fifo_init,
-		.fini = _nouveau_fifo_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
deleted file mode 100644
index 074d434c3077..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
+++ /dev/null
@@ -1,975 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <core/handle.h>
-#include <core/namedb.h>
-#include <core/gpuobj.h>
-#include <core/engctx.h>
-#include <core/event.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/bar.h>
-#include <subdev/fb.h>
-#include <subdev/vm.h>
-
-#include <engine/dmaobj.h>
-#include <engine/fifo.h>
-
-struct nvc0_fifo_priv {
-	struct nouveau_fifo base;
-
-	struct work_struct fault;
-	u64 mask;
-
-	struct {
-		struct nouveau_gpuobj *mem[2];
-		int active;
-		wait_queue_head_t wait;
-	} runlist;
-
-	struct {
-		struct nouveau_gpuobj *mem;
-		struct nouveau_vma bar;
-	} user;
-	int spoon_nr;
-};
-
-struct nvc0_fifo_base {
-	struct nouveau_fifo_base base;
-	struct nouveau_gpuobj *pgd;
-	struct nouveau_vm *vm;
-};
-
-struct nvc0_fifo_chan {
-	struct nouveau_fifo_chan base;
-	enum {
-		STOPPED,
-		RUNNING,
-		KILLED
-	} state;
-};
-
-/*******************************************************************************
- * FIFO channel objects
- ******************************************************************************/
-
-static void
-nvc0_fifo_runlist_update(struct nvc0_fifo_priv *priv)
-{
-	struct nouveau_bar *bar = nouveau_bar(priv);
-	struct nouveau_gpuobj *cur;
-	int i, p;
-
-	mutex_lock(&nv_subdev(priv)->mutex);
-	cur = priv->runlist.mem[priv->runlist.active];
-	priv->runlist.active = !priv->runlist.active;
-
-	for (i = 0, p = 0; i < 128; i++) {
-		struct nvc0_fifo_chan *chan = (void *)priv->base.channel[i];
-		if (chan && chan->state == RUNNING) {
-			nv_wo32(cur, p + 0, i);
-			nv_wo32(cur, p + 4, 0x00000004);
-			p += 8;
-		}
-	}
-	bar->flush(bar);
-
-	nv_wr32(priv, 0x002270, cur->addr >> 12);
-	nv_wr32(priv, 0x002274, 0x01f00000 | (p >> 3));
-
-	if (wait_event_timeout(priv->runlist.wait,
-			       !(nv_rd32(priv, 0x00227c) & 0x00100000),
-			       msecs_to_jiffies(2000)) == 0)
-		nv_error(priv, "runlist update timeout\n");
-	mutex_unlock(&nv_subdev(priv)->mutex);
-}
-
-static int
-nvc0_fifo_context_attach(struct nouveau_object *parent,
-			 struct nouveau_object *object)
-{
-	struct nouveau_bar *bar = nouveau_bar(parent);
-	struct nvc0_fifo_base *base = (void *)parent->parent;
-	struct nouveau_engctx *ectx = (void *)object;
-	u32 addr;
-	int ret;
-
-	switch (nv_engidx(object->engine)) {
-	case NVDEV_ENGINE_SW   : return 0;
-	case NVDEV_ENGINE_GR   : addr = 0x0210; break;
-	case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
-	case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
-	case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
-	case NVDEV_ENGINE_VP   : addr = 0x0250; break;
-	case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
-	default:
-		return -EINVAL;
-	}
-
-	if (!ectx->vma.node) {
-		ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
-					    NV_MEM_ACCESS_RW, &ectx->vma);
-		if (ret)
-			return ret;
-
-		nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
-	}
-
-	nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
-	nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));
-	bar->flush(bar);
-	return 0;
-}
-
-static int
-nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
-			 struct nouveau_object *object)
-{
-	struct nouveau_bar *bar = nouveau_bar(parent);
-	struct nvc0_fifo_priv *priv = (void *)parent->engine;
-	struct nvc0_fifo_base *base = (void *)parent->parent;
-	struct nvc0_fifo_chan *chan = (void *)parent;
-	u32 addr;
-
-	switch (nv_engidx(object->engine)) {
-	case NVDEV_ENGINE_SW   : return 0;
-	case NVDEV_ENGINE_GR   : addr = 0x0210; break;
-	case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
-	case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
-	case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
-	case NVDEV_ENGINE_VP   : addr = 0x0250; break;
-	case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
-	default:
-		return -EINVAL;
-	}
-
-	nv_wr32(priv, 0x002634, chan->base.chid);
-	if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
-		nv_error(priv, "channel %d [%s] kick timeout\n",
-			 chan->base.chid, nouveau_client_name(chan));
-		if (suspend)
-			return -EBUSY;
-	}
-
-	nv_wo32(base, addr + 0x00, 0x00000000);
-	nv_wo32(base, addr + 0x04, 0x00000000);
-	bar->flush(bar);
-	return 0;
-}
-
-static int
-nvc0_fifo_chan_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
-{
-	union {
-		struct nv50_channel_gpfifo_v0 v0;
-	} *args = data;
-	struct nouveau_bar *bar = nouveau_bar(parent);
-	struct nvc0_fifo_priv *priv = (void *)engine;
-	struct nvc0_fifo_base *base = (void *)parent;
-	struct nvc0_fifo_chan *chan;
-	u64 usermem, ioffset, ilength;
-	int ret, i;
-
-	nv_ioctl(parent, "create channel gpfifo size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x "
-				 "ioffset %016llx ilength %08x\n",
-			 args->v0.version, args->v0.pushbuf, args->v0.ioffset,
-			 args->v0.ilength);
-	} else
-		return ret;
-
-	ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
-					  priv->user.bar.offset, 0x1000,
-					  args->v0.pushbuf,
-					  (1ULL << NVDEV_ENGINE_SW) |
-					  (1ULL << NVDEV_ENGINE_GR) |
-					  (1ULL << NVDEV_ENGINE_COPY0) |
-					  (1ULL << NVDEV_ENGINE_COPY1) |
-					  (1ULL << NVDEV_ENGINE_BSP) |
-					  (1ULL << NVDEV_ENGINE_VP) |
-					  (1ULL << NVDEV_ENGINE_PPP), &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	args->v0.chid = chan->base.chid;
-
-	nv_parent(chan)->context_attach = nvc0_fifo_context_attach;
-	nv_parent(chan)->context_detach = nvc0_fifo_context_detach;
-
-	usermem = chan->base.chid * 0x1000;
-	ioffset = args->v0.ioffset;
-	ilength = order_base_2(args->v0.ilength / 8);
-
-	for (i = 0; i < 0x1000; i += 4)
-		nv_wo32(priv->user.mem, usermem + i, 0x00000000);
-
-	nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem));
-	nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem));
-	nv_wo32(base, 0x10, 0x0000face);
-	nv_wo32(base, 0x30, 0xfffff902);
-	nv_wo32(base, 0x48, lower_32_bits(ioffset));
-	nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
-	nv_wo32(base, 0x54, 0x00000002);
-	nv_wo32(base, 0x84, 0x20400000);
-	nv_wo32(base, 0x94, 0x30000001);
-	nv_wo32(base, 0x9c, 0x00000100);
-	nv_wo32(base, 0xa4, 0x1f1f1f1f);
-	nv_wo32(base, 0xa8, 0x1f1f1f1f);
-	nv_wo32(base, 0xac, 0x0000001f);
-	nv_wo32(base, 0xb8, 0xf8000000);
-	nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */
-	nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */
-	bar->flush(bar);
-	return 0;
-}
-
-static int
-nvc0_fifo_chan_init(struct nouveau_object *object)
-{
-	struct nouveau_gpuobj *base = nv_gpuobj(object->parent);
-	struct nvc0_fifo_priv *priv = (void *)object->engine;
-	struct nvc0_fifo_chan *chan = (void *)object;
-	u32 chid = chan->base.chid;
-	int ret;
-
-	ret = nouveau_fifo_channel_init(&chan->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12);
-
-	if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) {
-		nv_wr32(priv, 0x003004 + (chid * 8), 0x001f0001);
-		nvc0_fifo_runlist_update(priv);
-	}
-
-	return 0;
-}
-
-static void nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv);
-
-static int
-nvc0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nvc0_fifo_priv *priv = (void *)object->engine;
-	struct nvc0_fifo_chan *chan = (void *)object;
-	u32 chid = chan->base.chid;
-
-	if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) {
-		nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000);
-		nvc0_fifo_runlist_update(priv);
-	}
-
-	nvc0_fifo_intr_engine(priv);
-
-	nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000);
-	return nouveau_fifo_channel_fini(&chan->base, suspend);
-}
-
-static struct nouveau_ofuncs
-nvc0_fifo_ofuncs = {
-	.ctor = nvc0_fifo_chan_ctor,
-	.dtor = _nouveau_fifo_channel_dtor,
-	.init = nvc0_fifo_chan_init,
-	.fini = nvc0_fifo_chan_fini,
-	.map  = _nouveau_fifo_channel_map,
-	.rd32 = _nouveau_fifo_channel_rd32,
-	.wr32 = _nouveau_fifo_channel_wr32,
-	.ntfy = _nouveau_fifo_channel_ntfy
-};
-
-static struct nouveau_oclass
-nvc0_fifo_sclass[] = {
-	{ FERMI_CHANNEL_GPFIFO, &nvc0_fifo_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * FIFO context - instmem heap and vm setup
- ******************************************************************************/
-
-static int
-nvc0_fifo_context_ctor(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, void *data, u32 size,
-		       struct nouveau_object **pobject)
-{
-	struct nvc0_fifo_base *base;
-	int ret;
-
-	ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
-				          0x1000, NVOBJ_FLAG_ZERO_ALLOC |
-					  NVOBJ_FLAG_HEAP, &base);
-	*pobject = nv_object(base);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
-				&base->pgd);
-	if (ret)
-		return ret;
-
-	nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
-	nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
-	nv_wo32(base, 0x0208, 0xffffffff);
-	nv_wo32(base, 0x020c, 0x000000ff);
-
-	ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-static void
-nvc0_fifo_context_dtor(struct nouveau_object *object)
-{
-	struct nvc0_fifo_base *base = (void *)object;
-	nouveau_vm_ref(NULL, &base->vm, base->pgd);
-	nouveau_gpuobj_ref(NULL, &base->pgd);
-	nouveau_fifo_context_destroy(&base->base);
-}
-
-static struct nouveau_oclass
-nvc0_fifo_cclass = {
-	.handle = NV_ENGCTX(FIFO, 0xc0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_fifo_context_ctor,
-		.dtor = nvc0_fifo_context_dtor,
-		.init = _nouveau_fifo_context_init,
-		.fini = _nouveau_fifo_context_fini,
-		.rd32 = _nouveau_fifo_context_rd32,
-		.wr32 = _nouveau_fifo_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PFIFO engine
- ******************************************************************************/
-
-static inline int
-nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn)
-{
-	switch (engn) {
-	case NVDEV_ENGINE_GR   : engn = 0; break;
-	case NVDEV_ENGINE_BSP  : engn = 1; break;
-	case NVDEV_ENGINE_PPP  : engn = 2; break;
-	case NVDEV_ENGINE_VP   : engn = 3; break;
-	case NVDEV_ENGINE_COPY0: engn = 4; break;
-	case NVDEV_ENGINE_COPY1: engn = 5; break;
-	default:
-		return -1;
-	}
-
-	return engn;
-}
-
-static inline struct nouveau_engine *
-nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn)
-{
-	switch (engn) {
-	case 0: engn = NVDEV_ENGINE_GR; break;
-	case 1: engn = NVDEV_ENGINE_BSP; break;
-	case 2: engn = NVDEV_ENGINE_PPP; break;
-	case 3: engn = NVDEV_ENGINE_VP; break;
-	case 4: engn = NVDEV_ENGINE_COPY0; break;
-	case 5: engn = NVDEV_ENGINE_COPY1; break;
-	default:
-		return NULL;
-	}
-
-	return nouveau_engine(priv, engn);
-}
-
-static void
-nvc0_fifo_recover_work(struct work_struct *work)
-{
-	struct nvc0_fifo_priv *priv = container_of(work, typeof(*priv), fault);
-	struct nouveau_object *engine;
-	unsigned long flags;
-	u32 engn, engm = 0;
-	u64 mask, todo;
-
-	spin_lock_irqsave(&priv->base.lock, flags);
-	mask = priv->mask;
-	priv->mask = 0ULL;
-	spin_unlock_irqrestore(&priv->base.lock, flags);
-
-	for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn))
-		engm |= 1 << nvc0_fifo_engidx(priv, engn);
-	nv_mask(priv, 0x002630, engm, engm);
-
-	for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) {
-		if ((engine = (void *)nouveau_engine(priv, engn))) {
-			nv_ofuncs(engine)->fini(engine, false);
-			WARN_ON(nv_ofuncs(engine)->init(engine));
-		}
-	}
-
-	nvc0_fifo_runlist_update(priv);
-	nv_wr32(priv, 0x00262c, engm);
-	nv_mask(priv, 0x002630, engm, 0x00000000);
-}
-
-static void
-nvc0_fifo_recover(struct nvc0_fifo_priv *priv, struct nouveau_engine *engine,
-		  struct nvc0_fifo_chan *chan)
-{
-	struct nouveau_object *engobj = nv_object(engine);
-	u32 chid = chan->base.chid;
-	unsigned long flags;
-
-	nv_error(priv, "%s engine fault on channel %d, recovering...\n",
-		       nv_subdev(engine)->name, chid);
-
-	nv_mask(priv, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000);
-	chan->state = KILLED;
-
-	spin_lock_irqsave(&priv->base.lock, flags);
-	priv->mask |= 1ULL << nv_engidx(engobj);
-	spin_unlock_irqrestore(&priv->base.lock, flags);
-	schedule_work(&priv->fault);
-}
-
-static int
-nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
-{
-	struct nvc0_fifo_chan *chan = NULL;
-	struct nouveau_handle *bind;
-	unsigned long flags;
-	int ret = -EINVAL;
-
-	spin_lock_irqsave(&priv->base.lock, flags);
-	if (likely(chid >= priv->base.min && chid <= priv->base.max))
-		chan = (void *)priv->base.channel[chid];
-	if (unlikely(!chan))
-		goto out;
-
-	bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e);
-	if (likely(bind)) {
-		if (!mthd || !nv_call(bind->object, mthd, data))
-			ret = 0;
-		nouveau_namedb_put(bind);
-	}
-
-out:
-	spin_unlock_irqrestore(&priv->base.lock, flags);
-	return ret;
-}
-
-static const struct nouveau_enum
-nvc0_fifo_sched_reason[] = {
-	{ 0x0a, "CTXSW_TIMEOUT" },
-	{}
-};
-
-static void
-nvc0_fifo_intr_sched_ctxsw(struct nvc0_fifo_priv *priv)
-{
-	struct nouveau_engine *engine;
-	struct nvc0_fifo_chan *chan;
-	u32 engn;
-
-	for (engn = 0; engn < 6; engn++) {
-		u32 stat = nv_rd32(priv, 0x002640 + (engn * 0x04));
-		u32 busy = (stat & 0x80000000);
-		u32 save = (stat & 0x00100000); /* maybe? */
-		u32 unk0 = (stat & 0x00040000);
-		u32 unk1 = (stat & 0x00001000);
-		u32 chid = (stat & 0x0000007f);
-		(void)save;
-
-		if (busy && unk0 && unk1) {
-			if (!(chan = (void *)priv->base.channel[chid]))
-				continue;
-			if (!(engine = nvc0_fifo_engine(priv, engn)))
-				continue;
-			nvc0_fifo_recover(priv, engine, chan);
-		}
-	}
-}
-
-static void
-nvc0_fifo_intr_sched(struct nvc0_fifo_priv *priv)
-{
-	u32 intr = nv_rd32(priv, 0x00254c);
-	u32 code = intr & 0x000000ff;
-	const struct nouveau_enum *en;
-	char enunk[6] = "";
-
-	en = nouveau_enum_find(nvc0_fifo_sched_reason, code);
-	if (!en)
-		snprintf(enunk, sizeof(enunk), "UNK%02x", code);
-
-	nv_error(priv, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk);
-
-	switch (code) {
-	case 0x0a:
-		nvc0_fifo_intr_sched_ctxsw(priv);
-		break;
-	default:
-		break;
-	}
-}
-
-static const struct nouveau_enum
-nvc0_fifo_fault_engine[] = {
-	{ 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR },
-	{ 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB },
-	{ 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
-	{ 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
-	{ 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
-	{ 0x10, "PBSP", NULL, NVDEV_ENGINE_BSP },
-	{ 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP },
-	{ 0x13, "PCOUNTER" },
-	{ 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
-	{ 0x15, "PCOPY0", NULL, NVDEV_ENGINE_COPY0 },
-	{ 0x16, "PCOPY1", NULL, NVDEV_ENGINE_COPY1 },
-	{ 0x17, "PDAEMON" },
-	{}
-};
-
-static const struct nouveau_enum
-nvc0_fifo_fault_reason[] = {
-	{ 0x00, "PT_NOT_PRESENT" },
-	{ 0x01, "PT_TOO_SHORT" },
-	{ 0x02, "PAGE_NOT_PRESENT" },
-	{ 0x03, "VM_LIMIT_EXCEEDED" },
-	{ 0x04, "NO_CHANNEL" },
-	{ 0x05, "PAGE_SYSTEM_ONLY" },
-	{ 0x06, "PAGE_READ_ONLY" },
-	{ 0x0a, "COMPRESSED_SYSRAM" },
-	{ 0x0c, "INVALID_STORAGE_TYPE" },
-	{}
-};
-
-static const struct nouveau_enum
-nvc0_fifo_fault_hubclient[] = {
-	{ 0x01, "PCOPY0" },
-	{ 0x02, "PCOPY1" },
-	{ 0x04, "DISPATCH" },
-	{ 0x05, "CTXCTL" },
-	{ 0x06, "PFIFO" },
-	{ 0x07, "BAR_READ" },
-	{ 0x08, "BAR_WRITE" },
-	{ 0x0b, "PVP" },
-	{ 0x0c, "PPPP" },
-	{ 0x0d, "PBSP" },
-	{ 0x11, "PCOUNTER" },
-	{ 0x12, "PDAEMON" },
-	{ 0x14, "CCACHE" },
-	{ 0x15, "CCACHE_POST" },
-	{}
-};
-
-static const struct nouveau_enum
-nvc0_fifo_fault_gpcclient[] = {
-	{ 0x01, "TEX" },
-	{ 0x0c, "ESETUP" },
-	{ 0x0e, "CTXCTL" },
-	{ 0x0f, "PROP" },
-	{}
-};
-
-static void
-nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit)
-{
-	u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10));
-	u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10));
-	u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10));
-	u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10));
-	u32 gpc    = (stat & 0x1f000000) >> 24;
-	u32 client = (stat & 0x00001f00) >> 8;
-	u32 write  = (stat & 0x00000080);
-	u32 hub    = (stat & 0x00000040);
-	u32 reason = (stat & 0x0000000f);
-	struct nouveau_object *engctx = NULL, *object;
-	struct nouveau_engine *engine = NULL;
-	const struct nouveau_enum *er, *eu, *ec;
-	char erunk[6] = "";
-	char euunk[6] = "";
-	char ecunk[6] = "";
-	char gpcid[3] = "";
-
-	er = nouveau_enum_find(nvc0_fifo_fault_reason, reason);
-	if (!er)
-		snprintf(erunk, sizeof(erunk), "UNK%02X", reason);
-
-	eu = nouveau_enum_find(nvc0_fifo_fault_engine, unit);
-	if (eu) {
-		switch (eu->data2) {
-		case NVDEV_SUBDEV_BAR:
-			nv_mask(priv, 0x001704, 0x00000000, 0x00000000);
-			break;
-		case NVDEV_SUBDEV_INSTMEM:
-			nv_mask(priv, 0x001714, 0x00000000, 0x00000000);
-			break;
-		case NVDEV_ENGINE_IFB:
-			nv_mask(priv, 0x001718, 0x00000000, 0x00000000);
-			break;
-		default:
-			engine = nouveau_engine(priv, eu->data2);
-			if (engine)
-				engctx = nouveau_engctx_get(engine, inst);
-			break;
-		}
-	} else {
-		snprintf(euunk, sizeof(euunk), "UNK%02x", unit);
-	}
-
-	if (hub) {
-		ec = nouveau_enum_find(nvc0_fifo_fault_hubclient, client);
-	} else {
-		ec = nouveau_enum_find(nvc0_fifo_fault_gpcclient, client);
-		snprintf(gpcid, sizeof(gpcid), "%d", gpc);
-	}
-
-	if (!ec)
-		snprintf(ecunk, sizeof(ecunk), "UNK%02x", client);
-
-	nv_error(priv, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on "
-		       "channel 0x%010llx [%s]\n", write ? "write" : "read",
-		 (u64)vahi << 32 | valo, er ? er->name : erunk,
-		 eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/",
-		 ec ? ec->name : ecunk, (u64)inst << 12,
-		 nouveau_client_name(engctx));
-
-	object = engctx;
-	while (object) {
-		switch (nv_mclass(object)) {
-		case FERMI_CHANNEL_GPFIFO:
-			nvc0_fifo_recover(priv, engine, (void *)object);
-			break;
-		}
-		object = object->parent;
-	}
-
-	nouveau_engctx_put(engctx);
-}
-
-static const struct nouveau_bitfield
-nvc0_fifo_pbdma_intr[] = {
-/*	{ 0x00008000, "" }	seen with null ib push */
-	{ 0x00200000, "ILLEGAL_MTHD" },
-	{ 0x00800000, "EMPTY_SUBC" },
-	{}
-};
-
-static void
-nvc0_fifo_intr_pbdma(struct nvc0_fifo_priv *priv, int unit)
-{
-	u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000));
-	u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000));
-	u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000));
-	u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0x7f;
-	u32 subc = (addr & 0x00070000) >> 16;
-	u32 mthd = (addr & 0x00003ffc);
-	u32 show = stat;
-
-	if (stat & 0x00800000) {
-		if (!nvc0_fifo_swmthd(priv, chid, mthd, data))
-			show &= ~0x00800000;
-	}
-
-	if (show) {
-		nv_error(priv, "PBDMA%d:", unit);
-		nouveau_bitfield_print(nvc0_fifo_pbdma_intr, show);
-		pr_cont("\n");
-		nv_error(priv,
-			 "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
-			 unit, chid,
-			 nouveau_client_name_for_fifo_chid(&priv->base, chid),
-			 subc, mthd, data);
-	}
-
-	nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);
-	nv_wr32(priv, 0x040108 + (unit * 0x2000), stat);
-}
-
-static void
-nvc0_fifo_intr_runlist(struct nvc0_fifo_priv *priv)
-{
-	u32 intr = nv_rd32(priv, 0x002a00);
-
-	if (intr & 0x10000000) {
-		wake_up(&priv->runlist.wait);
-		nv_wr32(priv, 0x002a00, 0x10000000);
-		intr &= ~0x10000000;
-	}
-
-	if (intr) {
-		nv_error(priv, "RUNLIST 0x%08x\n", intr);
-		nv_wr32(priv, 0x002a00, intr);
-	}
-}
-
-static void
-nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn)
-{
-	u32 intr = nv_rd32(priv, 0x0025a8 + (engn * 0x04));
-	u32 inte = nv_rd32(priv, 0x002628);
-	u32 unkn;
-
-	nv_wr32(priv, 0x0025a8 + (engn * 0x04), intr);
-
-	for (unkn = 0; unkn < 8; unkn++) {
-		u32 ints = (intr >> (unkn * 0x04)) & inte;
-		if (ints & 0x1) {
-			nouveau_fifo_uevent(&priv->base);
-			ints &= ~1;
-		}
-		if (ints) {
-			nv_error(priv, "ENGINE %d %d %01x", engn, unkn, ints);
-			nv_mask(priv, 0x002628, ints, 0);
-		}
-	}
-}
-
-static void
-nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv)
-{
-	u32 mask = nv_rd32(priv, 0x0025a4);
-	while (mask) {
-		u32 unit = __ffs(mask);
-		nvc0_fifo_intr_engine_unit(priv, unit);
-		mask &= ~(1 << unit);
-	}
-}
-
-static void
-nvc0_fifo_intr(struct nouveau_subdev *subdev)
-{
-	struct nvc0_fifo_priv *priv = (void *)subdev;
-	u32 mask = nv_rd32(priv, 0x002140);
-	u32 stat = nv_rd32(priv, 0x002100) & mask;
-
-	if (stat & 0x00000001) {
-		u32 intr = nv_rd32(priv, 0x00252c);
-		nv_warn(priv, "INTR 0x00000001: 0x%08x\n", intr);
-		nv_wr32(priv, 0x002100, 0x00000001);
-		stat &= ~0x00000001;
-	}
-
-	if (stat & 0x00000100) {
-		nvc0_fifo_intr_sched(priv);
-		nv_wr32(priv, 0x002100, 0x00000100);
-		stat &= ~0x00000100;
-	}
-
-	if (stat & 0x00010000) {
-		u32 intr = nv_rd32(priv, 0x00256c);
-		nv_warn(priv, "INTR 0x00010000: 0x%08x\n", intr);
-		nv_wr32(priv, 0x002100, 0x00010000);
-		stat &= ~0x00010000;
-	}
-
-	if (stat & 0x01000000) {
-		u32 intr = nv_rd32(priv, 0x00258c);
-		nv_warn(priv, "INTR 0x01000000: 0x%08x\n", intr);
-		nv_wr32(priv, 0x002100, 0x01000000);
-		stat &= ~0x01000000;
-	}
-
-	if (stat & 0x10000000) {
-		u32 mask = nv_rd32(priv, 0x00259c);
-		while (mask) {
-			u32 unit = __ffs(mask);
-			nvc0_fifo_intr_fault(priv, unit);
-			nv_wr32(priv, 0x00259c, (1 << unit));
-			mask &= ~(1 << unit);
-		}
-		stat &= ~0x10000000;
-	}
-
-	if (stat & 0x20000000) {
-		u32 mask = nv_rd32(priv, 0x0025a0);
-		while (mask) {
-			u32 unit = __ffs(mask);
-			nvc0_fifo_intr_pbdma(priv, unit);
-			nv_wr32(priv, 0x0025a0, (1 << unit));
-			mask &= ~(1 << unit);
-		}
-		stat &= ~0x20000000;
-	}
-
-	if (stat & 0x40000000) {
-		nvc0_fifo_intr_runlist(priv);
-		stat &= ~0x40000000;
-	}
-
-	if (stat & 0x80000000) {
-		nvc0_fifo_intr_engine(priv);
-		stat &= ~0x80000000;
-	}
-
-	if (stat) {
-		nv_error(priv, "INTR 0x%08x\n", stat);
-		nv_mask(priv, 0x002140, stat, 0x00000000);
-		nv_wr32(priv, 0x002100, stat);
-	}
-}
-
-static void
-nvc0_fifo_uevent_init(struct nvkm_event *event, int type, int index)
-{
-	struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent);
-	nv_mask(fifo, 0x002140, 0x80000000, 0x80000000);
-}
-
-static void
-nvc0_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
-{
-	struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent);
-	nv_mask(fifo, 0x002140, 0x80000000, 0x00000000);
-}
-
-static const struct nvkm_event_func
-nvc0_fifo_uevent_func = {
-	.ctor = nouveau_fifo_uevent_ctor,
-	.init = nvc0_fifo_uevent_init,
-	.fini = nvc0_fifo_uevent_fini,
-};
-
-static int
-nvc0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nvc0_fifo_priv *priv;
-	int ret;
-
-	ret = nouveau_fifo_create(parent, engine, oclass, 0, 127, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	INIT_WORK(&priv->fault, nvc0_fifo_recover_work);
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0,
-				&priv->runlist.mem[0]);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0,
-				&priv->runlist.mem[1]);
-	if (ret)
-		return ret;
-
-	init_waitqueue_head(&priv->runlist.wait);
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 0x1000, 0x1000, 0,
-				&priv->user.mem);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
-				&priv->user.bar);
-	if (ret)
-		return ret;
-
-	ret = nvkm_event_init(&nvc0_fifo_uevent_func, 1, 1, &priv->base.uevent);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00000100;
-	nv_subdev(priv)->intr = nvc0_fifo_intr;
-	nv_engine(priv)->cclass = &nvc0_fifo_cclass;
-	nv_engine(priv)->sclass = nvc0_fifo_sclass;
-	return 0;
-}
-
-static void
-nvc0_fifo_dtor(struct nouveau_object *object)
-{
-	struct nvc0_fifo_priv *priv = (void *)object;
-
-	nouveau_gpuobj_unmap(&priv->user.bar);
-	nouveau_gpuobj_ref(NULL, &priv->user.mem);
-	nouveau_gpuobj_ref(NULL, &priv->runlist.mem[0]);
-	nouveau_gpuobj_ref(NULL, &priv->runlist.mem[1]);
-
-	nouveau_fifo_destroy(&priv->base);
-}
-
-static int
-nvc0_fifo_init(struct nouveau_object *object)
-{
-	struct nvc0_fifo_priv *priv = (void *)object;
-	int ret, i;
-
-	ret = nouveau_fifo_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x000204, 0xffffffff);
-	nv_wr32(priv, 0x002204, 0xffffffff);
-
-	priv->spoon_nr = hweight32(nv_rd32(priv, 0x002204));
-	nv_debug(priv, "%d PBDMA unit(s)\n", priv->spoon_nr);
-
-	/* assign engines to PBDMAs */
-	if (priv->spoon_nr >= 3) {
-		nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */
-		nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */
-		nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */
-		nv_wr32(priv, 0x002214, ~(1 << 1)); /* PBSP */
-		nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */
-		nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */
-	}
-
-	/* PBDMA[n] */
-	for (i = 0; i < priv->spoon_nr; i++) {
-		nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
-		nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
-		nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
-	}
-
-	nv_mask(priv, 0x002200, 0x00000001, 0x00000001);
-	nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
-
-	nv_wr32(priv, 0x002100, 0xffffffff);
-	nv_wr32(priv, 0x002140, 0x7fffffff);
-	nv_wr32(priv, 0x002628, 0x00000001); /* ENGINE_INTR_EN */
-	return 0;
-}
-
-struct nouveau_oclass *
-nvc0_fifo_oclass = &(struct nouveau_oclass) {
-	.handle = NV_ENGINE(FIFO, 0xc0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_fifo_ctor,
-		.dtor = nvc0_fifo_dtor,
-		.init = nvc0_fifo_init,
-		.fini = _nouveau_fifo_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
deleted file mode 100644
index 6a8db7c80bd1..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
+++ /dev/null
@@ -1,1147 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <core/handle.h>
-#include <core/namedb.h>
-#include <core/gpuobj.h>
-#include <core/engctx.h>
-#include <core/event.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/bar.h>
-#include <subdev/fb.h>
-#include <subdev/vm.h>
-
-#include <engine/dmaobj.h>
-
-#include "nve0.h"
-
-#define _(a,b) { (a), ((1ULL << (a)) | (b)) }
-static const struct {
-	u64 subdev;
-	u64 mask;
-} fifo_engine[] = {
-	_(NVDEV_ENGINE_GR      , (1ULL << NVDEV_ENGINE_SW) |
-				 (1ULL << NVDEV_ENGINE_COPY2)),
-	_(NVDEV_ENGINE_VP      , 0),
-	_(NVDEV_ENGINE_PPP     , 0),
-	_(NVDEV_ENGINE_BSP     , 0),
-	_(NVDEV_ENGINE_COPY0   , 0),
-	_(NVDEV_ENGINE_COPY1   , 0),
-	_(NVDEV_ENGINE_VENC    , 0),
-};
-#undef _
-#define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine)
-
-struct nve0_fifo_engn {
-	struct nouveau_gpuobj *runlist[2];
-	int cur_runlist;
-	wait_queue_head_t wait;
-};
-
-struct nve0_fifo_priv {
-	struct nouveau_fifo base;
-
-	struct work_struct fault;
-	u64 mask;
-
-	struct nve0_fifo_engn engine[FIFO_ENGINE_NR];
-	struct {
-		struct nouveau_gpuobj *mem;
-		struct nouveau_vma bar;
-	} user;
-	int spoon_nr;
-};
-
-struct nve0_fifo_base {
-	struct nouveau_fifo_base base;
-	struct nouveau_gpuobj *pgd;
-	struct nouveau_vm *vm;
-};
-
-struct nve0_fifo_chan {
-	struct nouveau_fifo_chan base;
-	u32 engine;
-	enum {
-		STOPPED,
-		RUNNING,
-		KILLED
-	} state;
-};
-
-/*******************************************************************************
- * FIFO channel objects
- ******************************************************************************/
-
-static void
-nve0_fifo_runlist_update(struct nve0_fifo_priv *priv, u32 engine)
-{
-	struct nouveau_bar *bar = nouveau_bar(priv);
-	struct nve0_fifo_engn *engn = &priv->engine[engine];
-	struct nouveau_gpuobj *cur;
-	int i, p;
-
-	mutex_lock(&nv_subdev(priv)->mutex);
-	cur = engn->runlist[engn->cur_runlist];
-	engn->cur_runlist = !engn->cur_runlist;
-
-	for (i = 0, p = 0; i < priv->base.max; i++) {
-		struct nve0_fifo_chan *chan = (void *)priv->base.channel[i];
-		if (chan && chan->state == RUNNING && chan->engine == engine) {
-			nv_wo32(cur, p + 0, i);
-			nv_wo32(cur, p + 4, 0x00000000);
-			p += 8;
-		}
-	}
-	bar->flush(bar);
-
-	nv_wr32(priv, 0x002270, cur->addr >> 12);
-	nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3));
-
-	if (wait_event_timeout(engn->wait, !(nv_rd32(priv, 0x002284 +
-			       (engine * 0x08)) & 0x00100000),
-				msecs_to_jiffies(2000)) == 0)
-		nv_error(priv, "runlist %d update timeout\n", engine);
-	mutex_unlock(&nv_subdev(priv)->mutex);
-}
-
-static int
-nve0_fifo_context_attach(struct nouveau_object *parent,
-			 struct nouveau_object *object)
-{
-	struct nouveau_bar *bar = nouveau_bar(parent);
-	struct nve0_fifo_base *base = (void *)parent->parent;
-	struct nouveau_engctx *ectx = (void *)object;
-	u32 addr;
-	int ret;
-
-	switch (nv_engidx(object->engine)) {
-	case NVDEV_ENGINE_SW   :
-		return 0;
-	case NVDEV_ENGINE_COPY0:
-	case NVDEV_ENGINE_COPY1:
-	case NVDEV_ENGINE_COPY2:
-		nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
-		return 0;
-	case NVDEV_ENGINE_GR   : addr = 0x0210; break;
-	case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
-	case NVDEV_ENGINE_VP   : addr = 0x0250; break;
-	case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
-	default:
-		return -EINVAL;
-	}
-
-	if (!ectx->vma.node) {
-		ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
-					    NV_MEM_ACCESS_RW, &ectx->vma);
-		if (ret)
-			return ret;
-
-		nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
-	}
-
-	nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
-	nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));
-	bar->flush(bar);
-	return 0;
-}
-
-static int
-nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
-			 struct nouveau_object *object)
-{
-	struct nouveau_bar *bar = nouveau_bar(parent);
-	struct nve0_fifo_priv *priv = (void *)parent->engine;
-	struct nve0_fifo_base *base = (void *)parent->parent;
-	struct nve0_fifo_chan *chan = (void *)parent;
-	u32 addr;
-
-	switch (nv_engidx(object->engine)) {
-	case NVDEV_ENGINE_SW   : return 0;
-	case NVDEV_ENGINE_COPY0:
-	case NVDEV_ENGINE_COPY1:
-	case NVDEV_ENGINE_COPY2: addr = 0x0000; break;
-	case NVDEV_ENGINE_GR   : addr = 0x0210; break;
-	case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
-	case NVDEV_ENGINE_VP   : addr = 0x0250; break;
-	case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
-	default:
-		return -EINVAL;
-	}
-
-	nv_wr32(priv, 0x002634, chan->base.chid);
-	if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
-		nv_error(priv, "channel %d [%s] kick timeout\n",
-			 chan->base.chid, nouveau_client_name(chan));
-		if (suspend)
-			return -EBUSY;
-	}
-
-	if (addr) {
-		nv_wo32(base, addr + 0x00, 0x00000000);
-		nv_wo32(base, addr + 0x04, 0x00000000);
-		bar->flush(bar);
-	}
-
-	return 0;
-}
-
-static int
-nve0_fifo_chan_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
-{
-	union {
-		struct kepler_channel_gpfifo_a_v0 v0;
-	} *args = data;
-	struct nouveau_bar *bar = nouveau_bar(parent);
-	struct nve0_fifo_priv *priv = (void *)engine;
-	struct nve0_fifo_base *base = (void *)parent;
-	struct nve0_fifo_chan *chan;
-	u64 usermem, ioffset, ilength;
-	int ret, i;
-
-	nv_ioctl(parent, "create channel gpfifo size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x "
-				 "ioffset %016llx ilength %08x engine %08x\n",
-			 args->v0.version, args->v0.pushbuf, args->v0.ioffset,
-			 args->v0.ilength, args->v0.engine);
-	} else
-		return ret;
-
-	for (i = 0; i < FIFO_ENGINE_NR; i++) {
-		if (args->v0.engine & (1 << i)) {
-			if (nouveau_engine(parent, fifo_engine[i].subdev)) {
-				args->v0.engine = (1 << i);
-				break;
-			}
-		}
-	}
-
-	if (i == FIFO_ENGINE_NR) {
-		nv_error(priv, "unsupported engines 0x%08x\n", args->v0.engine);
-		return -ENODEV;
-	}
-
-	ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
-					  priv->user.bar.offset, 0x200,
-					  args->v0.pushbuf,
-					  fifo_engine[i].mask, &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	args->v0.chid = chan->base.chid;
-
-	nv_parent(chan)->context_attach = nve0_fifo_context_attach;
-	nv_parent(chan)->context_detach = nve0_fifo_context_detach;
-	chan->engine = i;
-
-	usermem = chan->base.chid * 0x200;
-	ioffset = args->v0.ioffset;
-	ilength = order_base_2(args->v0.ilength / 8);
-
-	for (i = 0; i < 0x200; i += 4)
-		nv_wo32(priv->user.mem, usermem + i, 0x00000000);
-
-	nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem));
-	nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem));
-	nv_wo32(base, 0x10, 0x0000face);
-	nv_wo32(base, 0x30, 0xfffff902);
-	nv_wo32(base, 0x48, lower_32_bits(ioffset));
-	nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
-	nv_wo32(base, 0x84, 0x20400000);
-	nv_wo32(base, 0x94, 0x30000001);
-	nv_wo32(base, 0x9c, 0x00000100);
-	nv_wo32(base, 0xac, 0x0000001f);
-	nv_wo32(base, 0xe8, chan->base.chid);
-	nv_wo32(base, 0xb8, 0xf8000000);
-	nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */
-	nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */
-	bar->flush(bar);
-	return 0;
-}
-
-static int
-nve0_fifo_chan_init(struct nouveau_object *object)
-{
-	struct nouveau_gpuobj *base = nv_gpuobj(object->parent);
-	struct nve0_fifo_priv *priv = (void *)object->engine;
-	struct nve0_fifo_chan *chan = (void *)object;
-	u32 chid = chan->base.chid;
-	int ret;
-
-	ret = nouveau_fifo_channel_init(&chan->base);
-	if (ret)
-		return ret;
-
-	nv_mask(priv, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16);
-	nv_wr32(priv, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12);
-
-	if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) {
-		nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400);
-		nve0_fifo_runlist_update(priv, chan->engine);
-		nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400);
-	}
-
-	return 0;
-}
-
-static int
-nve0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nve0_fifo_priv *priv = (void *)object->engine;
-	struct nve0_fifo_chan *chan = (void *)object;
-	u32 chid = chan->base.chid;
-
-	if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) {
-		nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800);
-		nve0_fifo_runlist_update(priv, chan->engine);
-	}
-
-	nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000);
-	return nouveau_fifo_channel_fini(&chan->base, suspend);
-}
-
-static struct nouveau_ofuncs
-nve0_fifo_ofuncs = {
-	.ctor = nve0_fifo_chan_ctor,
-	.dtor = _nouveau_fifo_channel_dtor,
-	.init = nve0_fifo_chan_init,
-	.fini = nve0_fifo_chan_fini,
-	.map  = _nouveau_fifo_channel_map,
-	.rd32 = _nouveau_fifo_channel_rd32,
-	.wr32 = _nouveau_fifo_channel_wr32,
-	.ntfy = _nouveau_fifo_channel_ntfy
-};
-
-static struct nouveau_oclass
-nve0_fifo_sclass[] = {
-	{ KEPLER_CHANNEL_GPFIFO_A, &nve0_fifo_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * FIFO context - instmem heap and vm setup
- ******************************************************************************/
-
-static int
-nve0_fifo_context_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
-{
-	struct nve0_fifo_base *base;
-	int ret;
-
-	ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
-				          0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base);
-	*pobject = nv_object(base);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
-				&base->pgd);
-	if (ret)
-		return ret;
-
-	nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
-	nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
-	nv_wo32(base, 0x0208, 0xffffffff);
-	nv_wo32(base, 0x020c, 0x000000ff);
-
-	ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-static void
-nve0_fifo_context_dtor(struct nouveau_object *object)
-{
-	struct nve0_fifo_base *base = (void *)object;
-	nouveau_vm_ref(NULL, &base->vm, base->pgd);
-	nouveau_gpuobj_ref(NULL, &base->pgd);
-	nouveau_fifo_context_destroy(&base->base);
-}
-
-static struct nouveau_oclass
-nve0_fifo_cclass = {
-	.handle = NV_ENGCTX(FIFO, 0xe0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nve0_fifo_context_ctor,
-		.dtor = nve0_fifo_context_dtor,
-		.init = _nouveau_fifo_context_init,
-		.fini = _nouveau_fifo_context_fini,
-		.rd32 = _nouveau_fifo_context_rd32,
-		.wr32 = _nouveau_fifo_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PFIFO engine
- ******************************************************************************/
-
-static inline int
-nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn)
-{
-	switch (engn) {
-	case NVDEV_ENGINE_GR   :
-	case NVDEV_ENGINE_COPY2: engn = 0; break;
-	case NVDEV_ENGINE_BSP  : engn = 1; break;
-	case NVDEV_ENGINE_PPP  : engn = 2; break;
-	case NVDEV_ENGINE_VP   : engn = 3; break;
-	case NVDEV_ENGINE_COPY0: engn = 4; break;
-	case NVDEV_ENGINE_COPY1: engn = 5; break;
-	case NVDEV_ENGINE_VENC : engn = 6; break;
-	default:
-		return -1;
-	}
-
-	return engn;
-}
-
-static inline struct nouveau_engine *
-nve0_fifo_engine(struct nve0_fifo_priv *priv, u32 engn)
-{
-	if (engn >= ARRAY_SIZE(fifo_engine))
-		return NULL;
-	return nouveau_engine(priv, fifo_engine[engn].subdev);
-}
-
-static void
-nve0_fifo_recover_work(struct work_struct *work)
-{
-	struct nve0_fifo_priv *priv = container_of(work, typeof(*priv), fault);
-	struct nouveau_object *engine;
-	unsigned long flags;
-	u32 engn, engm = 0;
-	u64 mask, todo;
-
-	spin_lock_irqsave(&priv->base.lock, flags);
-	mask = priv->mask;
-	priv->mask = 0ULL;
-	spin_unlock_irqrestore(&priv->base.lock, flags);
-
-	for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn))
-		engm |= 1 << nve0_fifo_engidx(priv, engn);
-	nv_mask(priv, 0x002630, engm, engm);
-
-	for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) {
-		if ((engine = (void *)nouveau_engine(priv, engn))) {
-			nv_ofuncs(engine)->fini(engine, false);
-			WARN_ON(nv_ofuncs(engine)->init(engine));
-		}
-		nve0_fifo_runlist_update(priv, nve0_fifo_engidx(priv, engn));
-	}
-
-	nv_wr32(priv, 0x00262c, engm);
-	nv_mask(priv, 0x002630, engm, 0x00000000);
-}
-
-static void
-nve0_fifo_recover(struct nve0_fifo_priv *priv, struct nouveau_engine *engine,
-		  struct nve0_fifo_chan *chan)
-{
-	struct nouveau_object *engobj = nv_object(engine);
-	u32 chid = chan->base.chid;
-	unsigned long flags;
-
-	nv_error(priv, "%s engine fault on channel %d, recovering...\n",
-		       nv_subdev(engine)->name, chid);
-
-	nv_mask(priv, 0x800004 + (chid * 0x08), 0x00000800, 0x00000800);
-	chan->state = KILLED;
-
-	spin_lock_irqsave(&priv->base.lock, flags);
-	priv->mask |= 1ULL << nv_engidx(engobj);
-	spin_unlock_irqrestore(&priv->base.lock, flags);
-	schedule_work(&priv->fault);
-}
-
-static int
-nve0_fifo_swmthd(struct nve0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
-{
-	struct nve0_fifo_chan *chan = NULL;
-	struct nouveau_handle *bind;
-	unsigned long flags;
-	int ret = -EINVAL;
-
-	spin_lock_irqsave(&priv->base.lock, flags);
-	if (likely(chid >= priv->base.min && chid <= priv->base.max))
-		chan = (void *)priv->base.channel[chid];
-	if (unlikely(!chan))
-		goto out;
-
-	bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e);
-	if (likely(bind)) {
-		if (!mthd || !nv_call(bind->object, mthd, data))
-			ret = 0;
-		nouveau_namedb_put(bind);
-	}
-
-out:
-	spin_unlock_irqrestore(&priv->base.lock, flags);
-	return ret;
-}
-
-static const struct nouveau_enum
-nve0_fifo_bind_reason[] = {
-	{ 0x01, "BIND_NOT_UNBOUND" },
-	{ 0x02, "SNOOP_WITHOUT_BAR1" },
-	{ 0x03, "UNBIND_WHILE_RUNNING" },
-	{ 0x05, "INVALID_RUNLIST" },
-	{ 0x06, "INVALID_CTX_TGT" },
-	{ 0x0b, "UNBIND_WHILE_PARKED" },
-	{}
-};
-
-static void
-nve0_fifo_intr_bind(struct nve0_fifo_priv *priv)
-{
-	u32 intr = nv_rd32(priv, 0x00252c);
-	u32 code = intr & 0x000000ff;
-	const struct nouveau_enum *en;
-	char enunk[6] = "";
-
-	en = nouveau_enum_find(nve0_fifo_bind_reason, code);
-	if (!en)
-		snprintf(enunk, sizeof(enunk), "UNK%02x", code);
-
-	nv_error(priv, "BIND_ERROR [ %s ]\n", en ? en->name : enunk);
-}
-
-static const struct nouveau_enum
-nve0_fifo_sched_reason[] = {
-	{ 0x0a, "CTXSW_TIMEOUT" },
-	{}
-};
-
-static void
-nve0_fifo_intr_sched_ctxsw(struct nve0_fifo_priv *priv)
-{
-	struct nouveau_engine *engine;
-	struct nve0_fifo_chan *chan;
-	u32 engn;
-
-	for (engn = 0; engn < ARRAY_SIZE(fifo_engine); engn++) {
-		u32 stat = nv_rd32(priv, 0x002640 + (engn * 0x04));
-		u32 busy = (stat & 0x80000000);
-		u32 next = (stat & 0x07ff0000) >> 16;
-		u32 chsw = (stat & 0x00008000);
-		u32 save = (stat & 0x00004000);
-		u32 load = (stat & 0x00002000);
-		u32 prev = (stat & 0x000007ff);
-		u32 chid = load ? next : prev;
-		(void)save;
-
-		if (busy && chsw) {
-			if (!(chan = (void *)priv->base.channel[chid]))
-				continue;
-			if (!(engine = nve0_fifo_engine(priv, engn)))
-				continue;
-			nve0_fifo_recover(priv, engine, chan);
-		}
-	}
-}
-
-static void
-nve0_fifo_intr_sched(struct nve0_fifo_priv *priv)
-{
-	u32 intr = nv_rd32(priv, 0x00254c);
-	u32 code = intr & 0x000000ff;
-	const struct nouveau_enum *en;
-	char enunk[6] = "";
-
-	en = nouveau_enum_find(nve0_fifo_sched_reason, code);
-	if (!en)
-		snprintf(enunk, sizeof(enunk), "UNK%02x", code);
-
-	nv_error(priv, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk);
-
-	switch (code) {
-	case 0x0a:
-		nve0_fifo_intr_sched_ctxsw(priv);
-		break;
-	default:
-		break;
-	}
-}
-
-static void
-nve0_fifo_intr_chsw(struct nve0_fifo_priv *priv)
-{
-	u32 stat = nv_rd32(priv, 0x00256c);
-	nv_error(priv, "CHSW_ERROR 0x%08x\n", stat);
-	nv_wr32(priv, 0x00256c, stat);
-}
-
-static void
-nve0_fifo_intr_dropped_fault(struct nve0_fifo_priv *priv)
-{
-	u32 stat = nv_rd32(priv, 0x00259c);
-	nv_error(priv, "DROPPED_MMU_FAULT 0x%08x\n", stat);
-}
-
-static const struct nouveau_enum
-nve0_fifo_fault_engine[] = {
-	{ 0x00, "GR", NULL, NVDEV_ENGINE_GR },
-	{ 0x03, "IFB", NULL, NVDEV_ENGINE_IFB },
-	{ 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
-	{ 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
-	{ 0x07, "PBDMA0", NULL, NVDEV_ENGINE_FIFO },
-	{ 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO },
-	{ 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO },
-	{ 0x10, "MSVLD", NULL, NVDEV_ENGINE_BSP },
-	{ 0x11, "MSPPP", NULL, NVDEV_ENGINE_PPP },
-	{ 0x13, "PERF" },
-	{ 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP },
-	{ 0x15, "CE0", NULL, NVDEV_ENGINE_COPY0 },
-	{ 0x16, "CE1", NULL, NVDEV_ENGINE_COPY1 },
-	{ 0x17, "PMU" },
-	{ 0x19, "MSENC", NULL, NVDEV_ENGINE_VENC },
-	{ 0x1b, "CE2", NULL, NVDEV_ENGINE_COPY2 },
-	{}
-};
-
-static const struct nouveau_enum
-nve0_fifo_fault_reason[] = {
-	{ 0x00, "PDE" },
-	{ 0x01, "PDE_SIZE" },
-	{ 0x02, "PTE" },
-	{ 0x03, "VA_LIMIT_VIOLATION" },
-	{ 0x04, "UNBOUND_INST_BLOCK" },
-	{ 0x05, "PRIV_VIOLATION" },
-	{ 0x06, "RO_VIOLATION" },
-	{ 0x07, "WO_VIOLATION" },
-	{ 0x08, "PITCH_MASK_VIOLATION" },
-	{ 0x09, "WORK_CREATION" },
-	{ 0x0a, "UNSUPPORTED_APERTURE" },
-	{ 0x0b, "COMPRESSION_FAILURE" },
-	{ 0x0c, "UNSUPPORTED_KIND" },
-	{ 0x0d, "REGION_VIOLATION" },
-	{ 0x0e, "BOTH_PTES_VALID" },
-	{ 0x0f, "INFO_TYPE_POISONED" },
-	{}
-};
-
-static const struct nouveau_enum
-nve0_fifo_fault_hubclient[] = {
-	{ 0x00, "VIP" },
-	{ 0x01, "CE0" },
-	{ 0x02, "CE1" },
-	{ 0x03, "DNISO" },
-	{ 0x04, "FE" },
-	{ 0x05, "FECS" },
-	{ 0x06, "HOST" },
-	{ 0x07, "HOST_CPU" },
-	{ 0x08, "HOST_CPU_NB" },
-	{ 0x09, "ISO" },
-	{ 0x0a, "MMU" },
-	{ 0x0b, "MSPDEC" },
-	{ 0x0c, "MSPPP" },
-	{ 0x0d, "MSVLD" },
-	{ 0x0e, "NISO" },
-	{ 0x0f, "P2P" },
-	{ 0x10, "PD" },
-	{ 0x11, "PERF" },
-	{ 0x12, "PMU" },
-	{ 0x13, "RASTERTWOD" },
-	{ 0x14, "SCC" },
-	{ 0x15, "SCC_NB" },
-	{ 0x16, "SEC" },
-	{ 0x17, "SSYNC" },
-	{ 0x18, "GR_COPY" },
-	{ 0x19, "CE2" },
-	{ 0x1a, "XV" },
-	{ 0x1b, "MMU_NB" },
-	{ 0x1c, "MSENC" },
-	{ 0x1d, "DFALCON" },
-	{ 0x1e, "SKED" },
-	{ 0x1f, "AFALCON" },
-	{}
-};
-
-static const struct nouveau_enum
-nve0_fifo_fault_gpcclient[] = {
-	{ 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" },
-	{ 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" },
-	{ 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" },
-	{ 0x09, "L1_3" }, { 0x0a, "T1_3" }, { 0x0b, "PE_3" },
-	{ 0x0c, "RAST" },
-	{ 0x0d, "GCC" },
-	{ 0x0e, "GPCCS" },
-	{ 0x0f, "PROP_0" },
-	{ 0x10, "PROP_1" },
-	{ 0x11, "PROP_2" },
-	{ 0x12, "PROP_3" },
-	{ 0x13, "L1_4" }, { 0x14, "T1_4" }, { 0x15, "PE_4" },
-	{ 0x16, "L1_5" }, { 0x17, "T1_5" }, { 0x18, "PE_5" },
-	{ 0x19, "L1_6" }, { 0x1a, "T1_6" }, { 0x1b, "PE_6" },
-	{ 0x1c, "L1_7" }, { 0x1d, "T1_7" }, { 0x1e, "PE_7" },
-	{ 0x1f, "GPM" },
-	{ 0x20, "LTP_UTLB_0" },
-	{ 0x21, "LTP_UTLB_1" },
-	{ 0x22, "LTP_UTLB_2" },
-	{ 0x23, "LTP_UTLB_3" },
-	{ 0x24, "GPC_RGG_UTLB" },
-	{}
-};
-
-static void
-nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit)
-{
-	u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10));
-	u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10));
-	u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10));
-	u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10));
-	u32 gpc    = (stat & 0x1f000000) >> 24;
-	u32 client = (stat & 0x00001f00) >> 8;
-	u32 write  = (stat & 0x00000080);
-	u32 hub    = (stat & 0x00000040);
-	u32 reason = (stat & 0x0000000f);
-	struct nouveau_object *engctx = NULL, *object;
-	struct nouveau_engine *engine = NULL;
-	const struct nouveau_enum *er, *eu, *ec;
-	char erunk[6] = "";
-	char euunk[6] = "";
-	char ecunk[6] = "";
-	char gpcid[3] = "";
-
-	er = nouveau_enum_find(nve0_fifo_fault_reason, reason);
-	if (!er)
-		snprintf(erunk, sizeof(erunk), "UNK%02X", reason);
-
-	eu = nouveau_enum_find(nve0_fifo_fault_engine, unit);
-	if (eu) {
-		switch (eu->data2) {
-		case NVDEV_SUBDEV_BAR:
-			nv_mask(priv, 0x001704, 0x00000000, 0x00000000);
-			break;
-		case NVDEV_SUBDEV_INSTMEM:
-			nv_mask(priv, 0x001714, 0x00000000, 0x00000000);
-			break;
-		case NVDEV_ENGINE_IFB:
-			nv_mask(priv, 0x001718, 0x00000000, 0x00000000);
-			break;
-		default:
-			engine = nouveau_engine(priv, eu->data2);
-			if (engine)
-				engctx = nouveau_engctx_get(engine, inst);
-			break;
-		}
-	} else {
-		snprintf(euunk, sizeof(euunk), "UNK%02x", unit);
-	}
-
-	if (hub) {
-		ec = nouveau_enum_find(nve0_fifo_fault_hubclient, client);
-	} else {
-		ec = nouveau_enum_find(nve0_fifo_fault_gpcclient, client);
-		snprintf(gpcid, sizeof(gpcid), "%d", gpc);
-	}
-
-	if (!ec)
-		snprintf(ecunk, sizeof(ecunk), "UNK%02x", client);
-
-	nv_error(priv, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on "
-		       "channel 0x%010llx [%s]\n", write ? "write" : "read",
-		 (u64)vahi << 32 | valo, er ? er->name : erunk,
-		 eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/",
-		 ec ? ec->name : ecunk, (u64)inst << 12,
-		 nouveau_client_name(engctx));
-
-	object = engctx;
-	while (object) {
-		switch (nv_mclass(object)) {
-		case KEPLER_CHANNEL_GPFIFO_A:
-			nve0_fifo_recover(priv, engine, (void *)object);
-			break;
-		}
-		object = object->parent;
-	}
-
-	nouveau_engctx_put(engctx);
-}
-
-static const struct nouveau_bitfield nve0_fifo_pbdma_intr_0[] = {
-	{ 0x00000001, "MEMREQ" },
-	{ 0x00000002, "MEMACK_TIMEOUT" },
-	{ 0x00000004, "MEMACK_EXTRA" },
-	{ 0x00000008, "MEMDAT_TIMEOUT" },
-	{ 0x00000010, "MEMDAT_EXTRA" },
-	{ 0x00000020, "MEMFLUSH" },
-	{ 0x00000040, "MEMOP" },
-	{ 0x00000080, "LBCONNECT" },
-	{ 0x00000100, "LBREQ" },
-	{ 0x00000200, "LBACK_TIMEOUT" },
-	{ 0x00000400, "LBACK_EXTRA" },
-	{ 0x00000800, "LBDAT_TIMEOUT" },
-	{ 0x00001000, "LBDAT_EXTRA" },
-	{ 0x00002000, "GPFIFO" },
-	{ 0x00004000, "GPPTR" },
-	{ 0x00008000, "GPENTRY" },
-	{ 0x00010000, "GPCRC" },
-	{ 0x00020000, "PBPTR" },
-	{ 0x00040000, "PBENTRY" },
-	{ 0x00080000, "PBCRC" },
-	{ 0x00100000, "XBARCONNECT" },
-	{ 0x00200000, "METHOD" },
-	{ 0x00400000, "METHODCRC" },
-	{ 0x00800000, "DEVICE" },
-	{ 0x02000000, "SEMAPHORE" },
-	{ 0x04000000, "ACQUIRE" },
-	{ 0x08000000, "PRI" },
-	{ 0x20000000, "NO_CTXSW_SEG" },
-	{ 0x40000000, "PBSEG" },
-	{ 0x80000000, "SIGNATURE" },
-	{}
-};
-
-static void
-nve0_fifo_intr_pbdma_0(struct nve0_fifo_priv *priv, int unit)
-{
-	u32 mask = nv_rd32(priv, 0x04010c + (unit * 0x2000));
-	u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)) & mask;
-	u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000));
-	u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000));
-	u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0xfff;
-	u32 subc = (addr & 0x00070000) >> 16;
-	u32 mthd = (addr & 0x00003ffc);
-	u32 show = stat;
-
-	if (stat & 0x00800000) {
-		if (!nve0_fifo_swmthd(priv, chid, mthd, data))
-			show &= ~0x00800000;
-		nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);
-	}
-
-	if (show) {
-		nv_error(priv, "PBDMA%d:", unit);
-		nouveau_bitfield_print(nve0_fifo_pbdma_intr_0, show);
-		pr_cont("\n");
-		nv_error(priv,
-			 "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
-			 unit, chid,
-			 nouveau_client_name_for_fifo_chid(&priv->base, chid),
-			 subc, mthd, data);
-	}
-
-	nv_wr32(priv, 0x040108 + (unit * 0x2000), stat);
-}
-
-static const struct nouveau_bitfield nve0_fifo_pbdma_intr_1[] = {
-	{ 0x00000001, "HCE_RE_ILLEGAL_OP" },
-	{ 0x00000002, "HCE_RE_ALIGNB" },
-	{ 0x00000004, "HCE_PRIV" },
-	{ 0x00000008, "HCE_ILLEGAL_MTHD" },
-	{ 0x00000010, "HCE_ILLEGAL_CLASS" },
-	{}
-};
-
-static void
-nve0_fifo_intr_pbdma_1(struct nve0_fifo_priv *priv, int unit)
-{
-	u32 mask = nv_rd32(priv, 0x04014c + (unit * 0x2000));
-	u32 stat = nv_rd32(priv, 0x040148 + (unit * 0x2000)) & mask;
-	u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0xfff;
-
-	if (stat) {
-		nv_error(priv, "PBDMA%d:", unit);
-		nouveau_bitfield_print(nve0_fifo_pbdma_intr_1, stat);
-		pr_cont("\n");
-		nv_error(priv, "PBDMA%d: ch %d %08x %08x\n", unit, chid,
-			 nv_rd32(priv, 0x040150 + (unit * 0x2000)),
-			 nv_rd32(priv, 0x040154 + (unit * 0x2000)));
-	}
-
-	nv_wr32(priv, 0x040148 + (unit * 0x2000), stat);
-}
-
-static void
-nve0_fifo_intr_runlist(struct nve0_fifo_priv *priv)
-{
-	u32 mask = nv_rd32(priv, 0x002a00);
-	while (mask) {
-		u32 engn = __ffs(mask);
-		wake_up(&priv->engine[engn].wait);
-		nv_wr32(priv, 0x002a00, 1 << engn);
-		mask &= ~(1 << engn);
-	}
-}
-
-static void
-nve0_fifo_intr_engine(struct nve0_fifo_priv *priv)
-{
-	nouveau_fifo_uevent(&priv->base);
-}
-
-static void
-nve0_fifo_intr(struct nouveau_subdev *subdev)
-{
-	struct nve0_fifo_priv *priv = (void *)subdev;
-	u32 mask = nv_rd32(priv, 0x002140);
-	u32 stat = nv_rd32(priv, 0x002100) & mask;
-
-	if (stat & 0x00000001) {
-		nve0_fifo_intr_bind(priv);
-		nv_wr32(priv, 0x002100, 0x00000001);
-		stat &= ~0x00000001;
-	}
-
-	if (stat & 0x00000010) {
-		nv_error(priv, "PIO_ERROR\n");
-		nv_wr32(priv, 0x002100, 0x00000010);
-		stat &= ~0x00000010;
-	}
-
-	if (stat & 0x00000100) {
-		nve0_fifo_intr_sched(priv);
-		nv_wr32(priv, 0x002100, 0x00000100);
-		stat &= ~0x00000100;
-	}
-
-	if (stat & 0x00010000) {
-		nve0_fifo_intr_chsw(priv);
-		nv_wr32(priv, 0x002100, 0x00010000);
-		stat &= ~0x00010000;
-	}
-
-	if (stat & 0x00800000) {
-		nv_error(priv, "FB_FLUSH_TIMEOUT\n");
-		nv_wr32(priv, 0x002100, 0x00800000);
-		stat &= ~0x00800000;
-	}
-
-	if (stat & 0x01000000) {
-		nv_error(priv, "LB_ERROR\n");
-		nv_wr32(priv, 0x002100, 0x01000000);
-		stat &= ~0x01000000;
-	}
-
-	if (stat & 0x08000000) {
-		nve0_fifo_intr_dropped_fault(priv);
-		nv_wr32(priv, 0x002100, 0x08000000);
-		stat &= ~0x08000000;
-	}
-
-	if (stat & 0x10000000) {
-		u32 mask = nv_rd32(priv, 0x00259c);
-		while (mask) {
-			u32 unit = __ffs(mask);
-			nve0_fifo_intr_fault(priv, unit);
-			nv_wr32(priv, 0x00259c, (1 << unit));
-			mask &= ~(1 << unit);
-		}
-		stat &= ~0x10000000;
-	}
-
-	if (stat & 0x20000000) {
-		u32 mask = nv_rd32(priv, 0x0025a0);
-		while (mask) {
-			u32 unit = __ffs(mask);
-			nve0_fifo_intr_pbdma_0(priv, unit);
-			nve0_fifo_intr_pbdma_1(priv, unit);
-			nv_wr32(priv, 0x0025a0, (1 << unit));
-			mask &= ~(1 << unit);
-		}
-		stat &= ~0x20000000;
-	}
-
-	if (stat & 0x40000000) {
-		nve0_fifo_intr_runlist(priv);
-		stat &= ~0x40000000;
-	}
-
-	if (stat & 0x80000000) {
-		nv_wr32(priv, 0x002100, 0x80000000);
-		nve0_fifo_intr_engine(priv);
-		stat &= ~0x80000000;
-	}
-
-	if (stat) {
-		nv_error(priv, "INTR 0x%08x\n", stat);
-		nv_mask(priv, 0x002140, stat, 0x00000000);
-		nv_wr32(priv, 0x002100, stat);
-	}
-}
-
-static void
-nve0_fifo_uevent_init(struct nvkm_event *event, int type, int index)
-{
-	struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent);
-	nv_mask(fifo, 0x002140, 0x80000000, 0x80000000);
-}
-
-static void
-nve0_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
-{
-	struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent);
-	nv_mask(fifo, 0x002140, 0x80000000, 0x00000000);
-}
-
-static const struct nvkm_event_func
-nve0_fifo_uevent_func = {
-	.ctor = nouveau_fifo_uevent_ctor,
-	.init = nve0_fifo_uevent_init,
-	.fini = nve0_fifo_uevent_fini,
-};
-
-int
-nve0_fifo_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nve0_fifo_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_fifo_fini(&priv->base, suspend);
-	if (ret)
-		return ret;
-
-	/* allow mmu fault interrupts, even when we're not using fifo */
-	nv_mask(priv, 0x002140, 0x10000000, 0x10000000);
-	return 0;
-}
-
-int
-nve0_fifo_init(struct nouveau_object *object)
-{
-	struct nve0_fifo_priv *priv = (void *)object;
-	int ret, i;
-
-	ret = nouveau_fifo_init(&priv->base);
-	if (ret)
-		return ret;
-
-	/* enable all available PBDMA units */
-	nv_wr32(priv, 0x000204, 0xffffffff);
-	priv->spoon_nr = hweight32(nv_rd32(priv, 0x000204));
-	nv_debug(priv, "%d PBDMA unit(s)\n", priv->spoon_nr);
-
-	/* PBDMA[n] */
-	for (i = 0; i < priv->spoon_nr; i++) {
-		nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
-		nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
-		nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
-	}
-
-	/* PBDMA[n].HCE */
-	for (i = 0; i < priv->spoon_nr; i++) {
-		nv_wr32(priv, 0x040148 + (i * 0x2000), 0xffffffff); /* INTR */
-		nv_wr32(priv, 0x04014c + (i * 0x2000), 0xffffffff); /* INTREN */
-	}
-
-	nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
-
-	nv_wr32(priv, 0x002100, 0xffffffff);
-	nv_wr32(priv, 0x002140, 0x7fffffff);
-	return 0;
-}
-
-void
-nve0_fifo_dtor(struct nouveau_object *object)
-{
-	struct nve0_fifo_priv *priv = (void *)object;
-	int i;
-
-	nouveau_gpuobj_unmap(&priv->user.bar);
-	nouveau_gpuobj_ref(NULL, &priv->user.mem);
-
-	for (i = 0; i < FIFO_ENGINE_NR; i++) {
-		nouveau_gpuobj_ref(NULL, &priv->engine[i].runlist[1]);
-		nouveau_gpuobj_ref(NULL, &priv->engine[i].runlist[0]);
-	}
-
-	nouveau_fifo_destroy(&priv->base);
-}
-
-int
-nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nve0_fifo_impl *impl = (void *)oclass;
-	struct nve0_fifo_priv *priv;
-	int ret, i;
-
-	ret = nouveau_fifo_create(parent, engine, oclass, 0,
-				  impl->channels - 1, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	INIT_WORK(&priv->fault, nve0_fifo_recover_work);
-
-	for (i = 0; i < FIFO_ENGINE_NR; i++) {
-		ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000,
-					 0, &priv->engine[i].runlist[0]);
-		if (ret)
-			return ret;
-
-		ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000,
-					 0, &priv->engine[i].runlist[1]);
-		if (ret)
-			return ret;
-
-		init_waitqueue_head(&priv->engine[i].wait);
-	}
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, impl->channels * 0x200,
-				0x1000, NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
-				&priv->user.bar);
-	if (ret)
-		return ret;
-
-	ret = nvkm_event_init(&nve0_fifo_uevent_func, 1, 1, &priv->base.uevent);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00000100;
-	nv_subdev(priv)->intr = nve0_fifo_intr;
-	nv_engine(priv)->cclass = &nve0_fifo_cclass;
-	nv_engine(priv)->sclass = nve0_fifo_sclass;
-	return 0;
-}
-
-struct nouveau_oclass *
-nve0_fifo_oclass = &(struct nve0_fifo_impl) {
-	.base.handle = NV_ENGINE(FIFO, 0xe0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nve0_fifo_ctor,
-		.dtor = nve0_fifo_dtor,
-		.init = nve0_fifo_init,
-		.fini = nve0_fifo_fini,
-	},
-	.channels = 4096,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h
deleted file mode 100644
index e96b32bb1bbc..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef __NVKM_FIFO_NVE0_H__
-#define __NVKM_FIFO_NVE0_H__
-
-#include <engine/fifo.h>
-
-int  nve0_fifo_ctor(struct nouveau_object *, struct nouveau_object *,
-		    struct nouveau_oclass *, void *, u32,
-		    struct nouveau_object **);
-void nve0_fifo_dtor(struct nouveau_object *);
-int  nve0_fifo_init(struct nouveau_object *);
-int  nve0_fifo_fini(struct nouveau_object *, bool);
-
-struct nve0_fifo_impl {
-	struct nouveau_oclass base;
-	u32 channels;
-};
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctx.h b/drivers/gpu/drm/nouveau/core/engine/graph/ctx.h
deleted file mode 100644
index e1947013d3bc..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctx.h
+++ /dev/null
@@ -1,129 +0,0 @@
-#ifndef __NOUVEAU_GRCTX_H__
-#define __NOUVEAU_GRCTX_H__
-
-struct nouveau_grctx {
-	struct nouveau_device *device;
-
-	enum {
-		NOUVEAU_GRCTX_PROG,
-		NOUVEAU_GRCTX_VALS
-	} mode;
-	void *data;
-
-	u32 ctxprog_max;
-	u32 ctxprog_len;
-	u32 ctxprog_reg;
-	int ctxprog_label[32];
-	u32 ctxvals_pos;
-	u32 ctxvals_base;
-};
-
-static inline void
-cp_out(struct nouveau_grctx *ctx, u32 inst)
-{
-	u32 *ctxprog = ctx->data;
-
-	if (ctx->mode != NOUVEAU_GRCTX_PROG)
-		return;
-
-	BUG_ON(ctx->ctxprog_len == ctx->ctxprog_max);
-	ctxprog[ctx->ctxprog_len++] = inst;
-}
-
-static inline void
-cp_lsr(struct nouveau_grctx *ctx, u32 val)
-{
-	cp_out(ctx, CP_LOAD_SR | val);
-}
-
-static inline void
-cp_ctx(struct nouveau_grctx *ctx, u32 reg, u32 length)
-{
-	ctx->ctxprog_reg = (reg - 0x00400000) >> 2;
-
-	ctx->ctxvals_base = ctx->ctxvals_pos;
-	ctx->ctxvals_pos = ctx->ctxvals_base + length;
-
-	if (length > (CP_CTX_COUNT >> CP_CTX_COUNT_SHIFT)) {
-		cp_lsr(ctx, length);
-		length = 0;
-	}
-
-	cp_out(ctx, CP_CTX | (length << CP_CTX_COUNT_SHIFT) | ctx->ctxprog_reg);
-}
-
-static inline void
-cp_name(struct nouveau_grctx *ctx, int name)
-{
-	u32 *ctxprog = ctx->data;
-	int i;
-
-	if (ctx->mode != NOUVEAU_GRCTX_PROG)
-		return;
-
-	ctx->ctxprog_label[name] = ctx->ctxprog_len;
-	for (i = 0; i < ctx->ctxprog_len; i++) {
-		if ((ctxprog[i] & 0xfff00000) != 0xff400000)
-			continue;
-		if ((ctxprog[i] & CP_BRA_IP) != ((name) << CP_BRA_IP_SHIFT))
-			continue;
-		ctxprog[i] = (ctxprog[i] & 0x00ff00ff) |
-			     (ctx->ctxprog_len << CP_BRA_IP_SHIFT);
-	}
-}
-
-static inline void
-_cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name)
-{
-	int ip = 0;
-
-	if (mod != 2) {
-		ip = ctx->ctxprog_label[name] << CP_BRA_IP_SHIFT;
-		if (ip == 0)
-			ip = 0xff000000 | (name << CP_BRA_IP_SHIFT);
-	}
-
-	cp_out(ctx, CP_BRA | (mod << 18) | ip | flag |
-		    (state ? 0 : CP_BRA_IF_CLEAR));
-}
-#define cp_bra(c, f, s, n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
-#define cp_cal(c, f, s, n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
-#define cp_ret(c, f, s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0)
-
-static inline void
-_cp_wait(struct nouveau_grctx *ctx, int flag, int state)
-{
-	cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0));
-}
-#define cp_wait(c, f, s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
-
-static inline void
-_cp_set(struct nouveau_grctx *ctx, int flag, int state)
-{
-	cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0));
-}
-#define cp_set(c, f, s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
-
-static inline void
-cp_pos(struct nouveau_grctx *ctx, int offset)
-{
-	ctx->ctxvals_pos = offset;
-	ctx->ctxvals_base = ctx->ctxvals_pos;
-
-	cp_lsr(ctx, ctx->ctxvals_pos);
-	cp_out(ctx, CP_SET_CONTEXT_POINTER);
-}
-
-static inline void
-gr_def(struct nouveau_grctx *ctx, u32 reg, u32 val)
-{
-	if (ctx->mode != NOUVEAU_GRCTX_VALS)
-		return;
-
-	reg = (reg - 0x00400000) / 4;
-	reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base;
-
-	nv_wo32(ctx->data, reg * 4, val);
-}
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgk110b.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxgk110b.c
deleted file mode 100644
index 3adb7fe91772..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgk110b.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * PGRAPH context register lists
- ******************************************************************************/
-
-static const struct nvc0_graph_init
-gk110b_grctx_init_sm_0[] = {
-	{ 0x419e04,   1, 0x04, 0x00000000 },
-	{ 0x419e08,   1, 0x04, 0x0000001d },
-	{ 0x419e0c,   1, 0x04, 0x00000000 },
-	{ 0x419e10,   1, 0x04, 0x00001c02 },
-	{ 0x419e44,   1, 0x04, 0x0013eff2 },
-	{ 0x419e48,   1, 0x04, 0x00000000 },
-	{ 0x419e4c,   1, 0x04, 0x0000007f },
-	{ 0x419e50,   2, 0x04, 0x00000000 },
-	{ 0x419e58,   1, 0x04, 0x00000001 },
-	{ 0x419e5c,   3, 0x04, 0x00000000 },
-	{ 0x419e68,   1, 0x04, 0x00000002 },
-	{ 0x419e6c,  12, 0x04, 0x00000000 },
-	{ 0x419eac,   1, 0x04, 0x00001f8f },
-	{ 0x419eb0,   1, 0x04, 0x0db00d2f },
-	{ 0x419eb8,   1, 0x04, 0x00000000 },
-	{ 0x419ec8,   1, 0x04, 0x0001304f },
-	{ 0x419f30,   4, 0x04, 0x00000000 },
-	{ 0x419f40,   1, 0x04, 0x00000018 },
-	{ 0x419f44,   3, 0x04, 0x00000000 },
-	{ 0x419f58,   1, 0x04, 0x00000000 },
-	{ 0x419f70,   1, 0x04, 0x00006300 },
-	{ 0x419f78,   1, 0x04, 0x000000eb },
-	{ 0x419f7c,   1, 0x04, 0x00000404 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-gk110b_grctx_pack_tpc[] = {
-	{ nvd7_grctx_init_pe_0 },
-	{ nvf0_grctx_init_tex_0 },
-	{ nvf0_grctx_init_mpc_0 },
-	{ nvf0_grctx_init_l1c_0 },
-	{ gk110b_grctx_init_sm_0 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH context implementation
- ******************************************************************************/
-
-struct nouveau_oclass *
-gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) {
-	.base.handle = NV_ENGCTX(GR, 0xf1),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-	.main  = nve4_grctx_generate_main,
-	.unkn  = nve4_grctx_generate_unkn,
-	.hub   = nvf0_grctx_pack_hub,
-	.gpc   = nvf0_grctx_pack_gpc,
-	.zcull = nvc0_grctx_pack_zcull,
-	.tpc   = gk110b_grctx_pack_tpc,
-	.ppc   = nvf0_grctx_pack_ppc,
-	.icmd  = nvf0_grctx_pack_icmd,
-	.mthd  = nvf0_grctx_pack_mthd,
-	.bundle = nve4_grctx_generate_bundle,
-	.bundle_size = 0x3000,
-	.bundle_min_gpm_fifo_depth = 0x180,
-	.bundle_token_limit = 0x600,
-	.pagepool = nve4_grctx_generate_pagepool,
-	.pagepool_size = 0x8000,
-	.attrib = nvd7_grctx_generate_attrib,
-	.attrib_nr_max = 0x324,
-	.attrib_nr = 0x218,
-	.alpha_nr_max = 0x7ff,
-	.alpha_nr = 0x648,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgk20a.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxgk20a.c
deleted file mode 100644
index 36fc9831cc93..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgk20a.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include "ctxnvc0.h"
-
-static const struct nvc0_graph_pack
-gk20a_grctx_pack_mthd[] = {
-	{ nve4_grctx_init_a097_0, 0xa297 },
-	{ nvc0_grctx_init_902d_0, 0x902d },
-	{}
-};
-
-struct nouveau_oclass *
-gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) {
-	.base.handle = NV_ENGCTX(GR, 0xea),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-	.main  = nve4_grctx_generate_main,
-	.unkn  = nve4_grctx_generate_unkn,
-	.hub   = nve4_grctx_pack_hub,
-	.gpc   = nve4_grctx_pack_gpc,
-	.zcull = nvc0_grctx_pack_zcull,
-	.tpc   = nve4_grctx_pack_tpc,
-	.ppc   = nve4_grctx_pack_ppc,
-	.icmd  = nve4_grctx_pack_icmd,
-	.mthd  = gk20a_grctx_pack_mthd,
-	.bundle = nve4_grctx_generate_bundle,
-	.bundle_size = 0x1800,
-	.bundle_min_gpm_fifo_depth = 0x62,
-	.bundle_token_limit = 0x100,
-	.pagepool = nve4_grctx_generate_pagepool,
-	.pagepool_size = 0x8000,
-	.attrib = nvd7_grctx_generate_attrib,
-	.attrib_nr_max = 0x240,
-	.attrib_nr = 0x240,
-	.alpha_nr_max = 0x648 + (0x648 / 2),
-	.alpha_nr = 0x648,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c
deleted file mode 100644
index 62e918b9fa81..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c
+++ /dev/null
@@ -1,1032 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * PGRAPH context register lists
- ******************************************************************************/
-
-static const struct nvc0_graph_init
-gm107_grctx_init_icmd_0[] = {
-	{ 0x001000,   1, 0x01, 0x00000004 },
-	{ 0x000039,   3, 0x01, 0x00000000 },
-	{ 0x0000a9,   1, 0x01, 0x0000ffff },
-	{ 0x000038,   1, 0x01, 0x0fac6881 },
-	{ 0x00003d,   1, 0x01, 0x00000001 },
-	{ 0x0000e8,   8, 0x01, 0x00000400 },
-	{ 0x000078,   8, 0x01, 0x00000300 },
-	{ 0x000050,   1, 0x01, 0x00000011 },
-	{ 0x000058,   8, 0x01, 0x00000008 },
-	{ 0x000208,   8, 0x01, 0x00000001 },
-	{ 0x000081,   1, 0x01, 0x00000001 },
-	{ 0x000085,   1, 0x01, 0x00000004 },
-	{ 0x000088,   1, 0x01, 0x00000400 },
-	{ 0x000090,   1, 0x01, 0x00000300 },
-	{ 0x000098,   1, 0x01, 0x00001001 },
-	{ 0x0000e3,   1, 0x01, 0x00000001 },
-	{ 0x0000da,   1, 0x01, 0x00000001 },
-	{ 0x0000f8,   1, 0x01, 0x00000003 },
-	{ 0x0000fa,   1, 0x01, 0x00000001 },
-	{ 0x0000b1,   2, 0x01, 0x00000001 },
-	{ 0x00009f,   4, 0x01, 0x0000ffff },
-	{ 0x0000a8,   1, 0x01, 0x0000ffff },
-	{ 0x0000ad,   1, 0x01, 0x0000013e },
-	{ 0x0000e1,   1, 0x01, 0x00000010 },
-	{ 0x000290,  16, 0x01, 0x00000000 },
-	{ 0x0003b0,  16, 0x01, 0x00000000 },
-	{ 0x0002a0,  16, 0x01, 0x00000000 },
-	{ 0x000420,  16, 0x01, 0x00000000 },
-	{ 0x0002b0,  16, 0x01, 0x00000000 },
-	{ 0x000430,  16, 0x01, 0x00000000 },
-	{ 0x0002c0,  16, 0x01, 0x00000000 },
-	{ 0x0004d0,  16, 0x01, 0x00000000 },
-	{ 0x000720,  16, 0x01, 0x00000000 },
-	{ 0x0008c0,  16, 0x01, 0x00000000 },
-	{ 0x000890,  16, 0x01, 0x00000000 },
-	{ 0x0008e0,  16, 0x01, 0x00000000 },
-	{ 0x0008a0,  16, 0x01, 0x00000000 },
-	{ 0x0008f0,  16, 0x01, 0x00000000 },
-	{ 0x00094c,   1, 0x01, 0x000000ff },
-	{ 0x00094d,   1, 0x01, 0xffffffff },
-	{ 0x00094e,   1, 0x01, 0x00000002 },
-	{ 0x0002f2,   2, 0x01, 0x00000001 },
-	{ 0x0002f5,   1, 0x01, 0x00000001 },
-	{ 0x0002f7,   1, 0x01, 0x00000001 },
-	{ 0x000303,   1, 0x01, 0x00000001 },
-	{ 0x0002e6,   1, 0x01, 0x00000001 },
-	{ 0x000466,   1, 0x01, 0x00000052 },
-	{ 0x000301,   1, 0x01, 0x3f800000 },
-	{ 0x000304,   1, 0x01, 0x30201000 },
-	{ 0x000305,   1, 0x01, 0x70605040 },
-	{ 0x000306,   1, 0x01, 0xb8a89888 },
-	{ 0x000307,   1, 0x01, 0xf8e8d8c8 },
-	{ 0x00030a,   1, 0x01, 0x00ffff00 },
-	{ 0x0000de,   1, 0x01, 0x00000001 },
-	{ 0x00030b,   1, 0x01, 0x0000001a },
-	{ 0x00030c,   1, 0x01, 0x00000001 },
-	{ 0x000318,   1, 0x01, 0x00000001 },
-	{ 0x000340,   1, 0x01, 0x00000000 },
-	{ 0x00037d,   1, 0x01, 0x00000006 },
-	{ 0x0003a0,   1, 0x01, 0x00000002 },
-	{ 0x0003aa,   1, 0x01, 0x00000001 },
-	{ 0x0003a9,   1, 0x01, 0x00000001 },
-	{ 0x000380,   1, 0x01, 0x00000001 },
-	{ 0x000383,   1, 0x01, 0x00000011 },
-	{ 0x000360,   1, 0x01, 0x00000040 },
-	{ 0x000366,   2, 0x01, 0x00000000 },
-	{ 0x000368,   1, 0x01, 0x00000fff },
-	{ 0x000370,   2, 0x01, 0x00000000 },
-	{ 0x000372,   1, 0x01, 0x000fffff },
-	{ 0x00037a,   1, 0x01, 0x00000012 },
-	{ 0x000619,   1, 0x01, 0x00000003 },
-	{ 0x000811,   1, 0x01, 0x00000003 },
-	{ 0x000812,   1, 0x01, 0x00000004 },
-	{ 0x000813,   1, 0x01, 0x00000006 },
-	{ 0x000814,   1, 0x01, 0x00000008 },
-	{ 0x000815,   1, 0x01, 0x0000000b },
-	{ 0x000800,   6, 0x01, 0x00000001 },
-	{ 0x000632,   1, 0x01, 0x00000001 },
-	{ 0x000633,   1, 0x01, 0x00000002 },
-	{ 0x000634,   1, 0x01, 0x00000003 },
-	{ 0x000635,   1, 0x01, 0x00000004 },
-	{ 0x000654,   1, 0x01, 0x3f800000 },
-	{ 0x000657,   1, 0x01, 0x3f800000 },
-	{ 0x000655,   2, 0x01, 0x3f800000 },
-	{ 0x0006cd,   1, 0x01, 0x3f800000 },
-	{ 0x0007f5,   1, 0x01, 0x3f800000 },
-	{ 0x0007dc,   1, 0x01, 0x39291909 },
-	{ 0x0007dd,   1, 0x01, 0x79695949 },
-	{ 0x0007de,   1, 0x01, 0xb9a99989 },
-	{ 0x0007df,   1, 0x01, 0xf9e9d9c9 },
-	{ 0x0007e8,   1, 0x01, 0x00003210 },
-	{ 0x0007e9,   1, 0x01, 0x00007654 },
-	{ 0x0007ea,   1, 0x01, 0x00000098 },
-	{ 0x0007ec,   1, 0x01, 0x39291909 },
-	{ 0x0007ed,   1, 0x01, 0x79695949 },
-	{ 0x0007ee,   1, 0x01, 0xb9a99989 },
-	{ 0x0007ef,   1, 0x01, 0xf9e9d9c9 },
-	{ 0x0007f0,   1, 0x01, 0x00003210 },
-	{ 0x0007f1,   1, 0x01, 0x00007654 },
-	{ 0x0007f2,   1, 0x01, 0x00000098 },
-	{ 0x0005a5,   1, 0x01, 0x00000001 },
-	{ 0x0005d0,   1, 0x01, 0x20181008 },
-	{ 0x0005d1,   1, 0x01, 0x40383028 },
-	{ 0x0005d2,   1, 0x01, 0x60585048 },
-	{ 0x0005d3,   1, 0x01, 0x80787068 },
-	{ 0x000980, 128, 0x01, 0x00000000 },
-	{ 0x000468,   1, 0x01, 0x00000004 },
-	{ 0x00046c,   1, 0x01, 0x00000001 },
-	{ 0x000470,  96, 0x01, 0x00000000 },
-	{ 0x000510,  16, 0x01, 0x3f800000 },
-	{ 0x000520,   1, 0x01, 0x000002b6 },
-	{ 0x000529,   1, 0x01, 0x00000001 },
-	{ 0x000530,  16, 0x01, 0xffff0000 },
-	{ 0x000550,  32, 0x01, 0xffff0000 },
-	{ 0x000585,   1, 0x01, 0x0000003f },
-	{ 0x000576,   1, 0x01, 0x00000003 },
-	{ 0x00057b,   1, 0x01, 0x00000059 },
-	{ 0x000586,   1, 0x01, 0x00000040 },
-	{ 0x000582,   2, 0x01, 0x00000080 },
-	{ 0x000595,   1, 0x01, 0x00400040 },
-	{ 0x000596,   1, 0x01, 0x00000492 },
-	{ 0x000597,   1, 0x01, 0x08080203 },
-	{ 0x0005ad,   1, 0x01, 0x00000008 },
-	{ 0x000598,   1, 0x01, 0x00020001 },
-	{ 0x0005c2,   1, 0x01, 0x00000001 },
-	{ 0x000638,   2, 0x01, 0x00000001 },
-	{ 0x00063a,   1, 0x01, 0x00000002 },
-	{ 0x00063b,   2, 0x01, 0x00000001 },
-	{ 0x00063d,   1, 0x01, 0x00000002 },
-	{ 0x00063e,   1, 0x01, 0x00000001 },
-	{ 0x0008b8,   8, 0x01, 0x00000001 },
-	{ 0x000900,   8, 0x01, 0x00000001 },
-	{ 0x000908,   8, 0x01, 0x00000002 },
-	{ 0x000910,  16, 0x01, 0x00000001 },
-	{ 0x000920,   8, 0x01, 0x00000002 },
-	{ 0x000928,   8, 0x01, 0x00000001 },
-	{ 0x000662,   1, 0x01, 0x00000001 },
-	{ 0x000648,   9, 0x01, 0x00000001 },
-	{ 0x000658,   1, 0x01, 0x0000000f },
-	{ 0x0007ff,   1, 0x01, 0x0000000a },
-	{ 0x00066a,   1, 0x01, 0x40000000 },
-	{ 0x00066b,   1, 0x01, 0x10000000 },
-	{ 0x00066c,   2, 0x01, 0xffff0000 },
-	{ 0x0007af,   2, 0x01, 0x00000008 },
-	{ 0x0007f6,   1, 0x01, 0x00000001 },
-	{ 0x0006b2,   1, 0x01, 0x00000055 },
-	{ 0x0007ad,   1, 0x01, 0x00000003 },
-	{ 0x000971,   1, 0x01, 0x00000008 },
-	{ 0x000972,   1, 0x01, 0x00000040 },
-	{ 0x000973,   1, 0x01, 0x0000012c },
-	{ 0x00097c,   1, 0x01, 0x00000040 },
-	{ 0x000975,   1, 0x01, 0x00000020 },
-	{ 0x000976,   1, 0x01, 0x00000001 },
-	{ 0x000977,   1, 0x01, 0x00000020 },
-	{ 0x000978,   1, 0x01, 0x00000001 },
-	{ 0x000957,   1, 0x01, 0x00000003 },
-	{ 0x00095e,   1, 0x01, 0x20164010 },
-	{ 0x00095f,   1, 0x01, 0x00000020 },
-	{ 0x000a0d,   1, 0x01, 0x00000006 },
-	{ 0x00097d,   1, 0x01, 0x0000000c },
-	{ 0x000683,   1, 0x01, 0x00000006 },
-	{ 0x000687,   1, 0x01, 0x003fffff },
-	{ 0x0006a0,   1, 0x01, 0x00000005 },
-	{ 0x000840,   1, 0x01, 0x00400008 },
-	{ 0x000841,   1, 0x01, 0x08000080 },
-	{ 0x000842,   1, 0x01, 0x00400008 },
-	{ 0x000843,   1, 0x01, 0x08000080 },
-	{ 0x000818,   8, 0x01, 0x00000000 },
-	{ 0x000848,  16, 0x01, 0x00000000 },
-	{ 0x000738,   1, 0x01, 0x00000000 },
-	{ 0x0006aa,   1, 0x01, 0x00000001 },
-	{ 0x0006ab,   1, 0x01, 0x00000002 },
-	{ 0x0006ac,   1, 0x01, 0x00000080 },
-	{ 0x0006ad,   2, 0x01, 0x00000100 },
-	{ 0x0006b1,   1, 0x01, 0x00000011 },
-	{ 0x0006bb,   1, 0x01, 0x000000cf },
-	{ 0x0006ce,   1, 0x01, 0x2a712488 },
-	{ 0x000739,   1, 0x01, 0x4085c000 },
-	{ 0x00073a,   1, 0x01, 0x00000080 },
-	{ 0x000786,   1, 0x01, 0x80000100 },
-	{ 0x00073c,   1, 0x01, 0x00010100 },
-	{ 0x00073d,   1, 0x01, 0x02800000 },
-	{ 0x000787,   1, 0x01, 0x000000cf },
-	{ 0x00078c,   1, 0x01, 0x00000008 },
-	{ 0x000792,   1, 0x01, 0x00000001 },
-	{ 0x000794,   3, 0x01, 0x00000001 },
-	{ 0x000797,   1, 0x01, 0x000000cf },
-	{ 0x000836,   1, 0x01, 0x00000001 },
-	{ 0x00079a,   1, 0x01, 0x00000002 },
-	{ 0x000833,   1, 0x01, 0x04444480 },
-	{ 0x0007a1,   1, 0x01, 0x00000001 },
-	{ 0x0007a3,   3, 0x01, 0x00000001 },
-	{ 0x000831,   1, 0x01, 0x00000004 },
-	{ 0x000b07,   1, 0x01, 0x00000002 },
-	{ 0x000b08,   2, 0x01, 0x00000100 },
-	{ 0x000b0a,   1, 0x01, 0x00000001 },
-	{ 0x000a04,   1, 0x01, 0x000000ff },
-	{ 0x000a0b,   1, 0x01, 0x00000040 },
-	{ 0x00097f,   1, 0x01, 0x00000100 },
-	{ 0x000a02,   1, 0x01, 0x00000001 },
-	{ 0x000809,   1, 0x01, 0x00000007 },
-	{ 0x00c221,   1, 0x01, 0x00000040 },
-	{ 0x00c1b0,   8, 0x01, 0x0000000f },
-	{ 0x00c1b8,   1, 0x01, 0x0fac6881 },
-	{ 0x00c1b9,   1, 0x01, 0x00fac688 },
-	{ 0x00c401,   1, 0x01, 0x00000001 },
-	{ 0x00c402,   1, 0x01, 0x00010001 },
-	{ 0x00c403,   2, 0x01, 0x00000001 },
-	{ 0x00c40e,   1, 0x01, 0x00000020 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000002 },
-	{ 0x0006aa,   1, 0x01, 0x00000001 },
-	{ 0x0006ad,   2, 0x01, 0x00000100 },
-	{ 0x0006b1,   1, 0x01, 0x00000011 },
-	{ 0x00078c,   1, 0x01, 0x00000008 },
-	{ 0x000792,   1, 0x01, 0x00000001 },
-	{ 0x000794,   3, 0x01, 0x00000001 },
-	{ 0x000797,   1, 0x01, 0x000000cf },
-	{ 0x00079a,   1, 0x01, 0x00000002 },
-	{ 0x0007a1,   1, 0x01, 0x00000001 },
-	{ 0x0007a3,   3, 0x01, 0x00000001 },
-	{ 0x000831,   1, 0x01, 0x00000004 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000008 },
-	{ 0x000039,   3, 0x01, 0x00000000 },
-	{ 0x000380,   1, 0x01, 0x00000001 },
-	{ 0x000366,   2, 0x01, 0x00000000 },
-	{ 0x000368,   1, 0x01, 0x00000fff },
-	{ 0x000370,   2, 0x01, 0x00000000 },
-	{ 0x000372,   1, 0x01, 0x000fffff },
-	{ 0x000813,   1, 0x01, 0x00000006 },
-	{ 0x000814,   1, 0x01, 0x00000008 },
-	{ 0x000818,   8, 0x01, 0x00000000 },
-	{ 0x000848,  16, 0x01, 0x00000000 },
-	{ 0x000738,   1, 0x01, 0x00000000 },
-	{ 0x000b07,   1, 0x01, 0x00000002 },
-	{ 0x000b08,   2, 0x01, 0x00000100 },
-	{ 0x000b0a,   1, 0x01, 0x00000001 },
-	{ 0x000a04,   1, 0x01, 0x000000ff },
-	{ 0x000a0b,   1, 0x01, 0x00000040 },
-	{ 0x00097f,   1, 0x01, 0x00000100 },
-	{ 0x000a02,   1, 0x01, 0x00000001 },
-	{ 0x000809,   1, 0x01, 0x00000007 },
-	{ 0x00c221,   1, 0x01, 0x00000040 },
-	{ 0x00c401,   1, 0x01, 0x00000001 },
-	{ 0x00c402,   1, 0x01, 0x00010001 },
-	{ 0x00c403,   2, 0x01, 0x00000001 },
-	{ 0x00c40e,   1, 0x01, 0x00000020 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000001 },
-	{ 0x000b07,   1, 0x01, 0x00000002 },
-	{ 0x000b08,   2, 0x01, 0x00000100 },
-	{ 0x000b0a,   1, 0x01, 0x00000001 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-gm107_grctx_pack_icmd[] = {
-	{ gm107_grctx_init_icmd_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_grctx_init_b097_0[] = {
-	{ 0x000800,   8, 0x40, 0x00000000 },
-	{ 0x000804,   8, 0x40, 0x00000000 },
-	{ 0x000808,   8, 0x40, 0x00000400 },
-	{ 0x00080c,   8, 0x40, 0x00000300 },
-	{ 0x000810,   1, 0x04, 0x000000cf },
-	{ 0x000850,   7, 0x40, 0x00000000 },
-	{ 0x000814,   8, 0x40, 0x00000040 },
-	{ 0x000818,   8, 0x40, 0x00000001 },
-	{ 0x00081c,   8, 0x40, 0x00000000 },
-	{ 0x000820,   8, 0x40, 0x00000000 },
-	{ 0x001c00,  16, 0x10, 0x00000000 },
-	{ 0x001c04,  16, 0x10, 0x00000000 },
-	{ 0x001c08,  16, 0x10, 0x00000000 },
-	{ 0x001c0c,  16, 0x10, 0x00000000 },
-	{ 0x001d00,  16, 0x10, 0x00000000 },
-	{ 0x001d04,  16, 0x10, 0x00000000 },
-	{ 0x001d08,  16, 0x10, 0x00000000 },
-	{ 0x001d0c,  16, 0x10, 0x00000000 },
-	{ 0x001f00,  16, 0x08, 0x00000000 },
-	{ 0x001f04,  16, 0x08, 0x00000000 },
-	{ 0x001f80,  16, 0x08, 0x00000000 },
-	{ 0x001f84,  16, 0x08, 0x00000000 },
-	{ 0x002000,   1, 0x04, 0x00000000 },
-	{ 0x002040,   1, 0x04, 0x00000011 },
-	{ 0x002080,   1, 0x04, 0x00000020 },
-	{ 0x0020c0,   1, 0x04, 0x00000030 },
-	{ 0x002100,   1, 0x04, 0x00000040 },
-	{ 0x002140,   1, 0x04, 0x00000051 },
-	{ 0x00200c,   6, 0x40, 0x00000001 },
-	{ 0x002010,   1, 0x04, 0x00000000 },
-	{ 0x002050,   1, 0x04, 0x00000000 },
-	{ 0x002090,   1, 0x04, 0x00000001 },
-	{ 0x0020d0,   1, 0x04, 0x00000002 },
-	{ 0x002110,   1, 0x04, 0x00000003 },
-	{ 0x002150,   1, 0x04, 0x00000004 },
-	{ 0x000380,   4, 0x20, 0x00000000 },
-	{ 0x000384,   4, 0x20, 0x00000000 },
-	{ 0x000388,   4, 0x20, 0x00000000 },
-	{ 0x00038c,   4, 0x20, 0x00000000 },
-	{ 0x000700,   4, 0x10, 0x00000000 },
-	{ 0x000704,   4, 0x10, 0x00000000 },
-	{ 0x000708,   4, 0x10, 0x00000000 },
-	{ 0x002800, 128, 0x04, 0x00000000 },
-	{ 0x000a00,  16, 0x20, 0x00000000 },
-	{ 0x000a04,  16, 0x20, 0x00000000 },
-	{ 0x000a08,  16, 0x20, 0x00000000 },
-	{ 0x000a0c,  16, 0x20, 0x00000000 },
-	{ 0x000a10,  16, 0x20, 0x00000000 },
-	{ 0x000a14,  16, 0x20, 0x00000000 },
-	{ 0x000c00,  16, 0x10, 0x00000000 },
-	{ 0x000c04,  16, 0x10, 0x00000000 },
-	{ 0x000c08,  16, 0x10, 0x00000000 },
-	{ 0x000c0c,  16, 0x10, 0x3f800000 },
-	{ 0x000d00,   8, 0x08, 0xffff0000 },
-	{ 0x000d04,   8, 0x08, 0xffff0000 },
-	{ 0x000e00,  16, 0x10, 0x00000000 },
-	{ 0x000e04,  16, 0x10, 0xffff0000 },
-	{ 0x000e08,  16, 0x10, 0xffff0000 },
-	{ 0x000d40,   4, 0x08, 0x00000000 },
-	{ 0x000d44,   4, 0x08, 0x00000000 },
-	{ 0x001e00,   8, 0x20, 0x00000001 },
-	{ 0x001e04,   8, 0x20, 0x00000001 },
-	{ 0x001e08,   8, 0x20, 0x00000002 },
-	{ 0x001e0c,   8, 0x20, 0x00000001 },
-	{ 0x001e10,   8, 0x20, 0x00000001 },
-	{ 0x001e14,   8, 0x20, 0x00000002 },
-	{ 0x001e18,   8, 0x20, 0x00000001 },
-	{ 0x001480,   8, 0x10, 0x00000000 },
-	{ 0x001484,   8, 0x10, 0x00000000 },
-	{ 0x001488,   8, 0x10, 0x00000000 },
-	{ 0x003400, 128, 0x04, 0x00000000 },
-	{ 0x00030c,   1, 0x04, 0x00000001 },
-	{ 0x001944,   1, 0x04, 0x00000000 },
-	{ 0x001514,   1, 0x04, 0x00000000 },
-	{ 0x000d68,   1, 0x04, 0x0000ffff },
-	{ 0x00121c,   1, 0x04, 0x0fac6881 },
-	{ 0x000fac,   1, 0x04, 0x00000001 },
-	{ 0x001538,   1, 0x04, 0x00000001 },
-	{ 0x000fe0,   2, 0x04, 0x00000000 },
-	{ 0x000fe8,   1, 0x04, 0x00000014 },
-	{ 0x000fec,   1, 0x04, 0x00000040 },
-	{ 0x000ff0,   1, 0x04, 0x00000000 },
-	{ 0x00179c,   1, 0x04, 0x00000000 },
-	{ 0x001228,   1, 0x04, 0x00000400 },
-	{ 0x00122c,   1, 0x04, 0x00000300 },
-	{ 0x001230,   1, 0x04, 0x00010001 },
-	{ 0x0007f8,   1, 0x04, 0x00000000 },
-	{ 0x0015b4,   1, 0x04, 0x00000001 },
-	{ 0x0015cc,   1, 0x04, 0x00000000 },
-	{ 0x001534,   1, 0x04, 0x00000000 },
-	{ 0x000754,   1, 0x04, 0x00000001 },
-	{ 0x000fb0,   1, 0x04, 0x00000000 },
-	{ 0x0015d0,   1, 0x04, 0x00000000 },
-	{ 0x00153c,   1, 0x04, 0x00000000 },
-	{ 0x0016b4,   1, 0x04, 0x00000003 },
-	{ 0x000fbc,   4, 0x04, 0x0000ffff },
-	{ 0x000df8,   2, 0x04, 0x00000000 },
-	{ 0x001948,   1, 0x04, 0x00000000 },
-	{ 0x001970,   1, 0x04, 0x00000001 },
-	{ 0x00161c,   1, 0x04, 0x000009f0 },
-	{ 0x000dcc,   1, 0x04, 0x00000010 },
-	{ 0x0015e4,   1, 0x04, 0x00000000 },
-	{ 0x001160,  32, 0x04, 0x25e00040 },
-	{ 0x001880,  32, 0x04, 0x00000000 },
-	{ 0x000f84,   2, 0x04, 0x00000000 },
-	{ 0x0017c8,   2, 0x04, 0x00000000 },
-	{ 0x0017d0,   1, 0x04, 0x000000ff },
-	{ 0x0017d4,   1, 0x04, 0xffffffff },
-	{ 0x0017d8,   1, 0x04, 0x00000002 },
-	{ 0x0017dc,   1, 0x04, 0x00000000 },
-	{ 0x0015f4,   2, 0x04, 0x00000000 },
-	{ 0x001434,   2, 0x04, 0x00000000 },
-	{ 0x000d74,   1, 0x04, 0x00000000 },
-	{ 0x0013a4,   1, 0x04, 0x00000000 },
-	{ 0x001318,   1, 0x04, 0x00000001 },
-	{ 0x001080,   2, 0x04, 0x00000000 },
-	{ 0x001088,   2, 0x04, 0x00000001 },
-	{ 0x001090,   1, 0x04, 0x00000000 },
-	{ 0x001094,   1, 0x04, 0x00000001 },
-	{ 0x001098,   1, 0x04, 0x00000000 },
-	{ 0x00109c,   1, 0x04, 0x00000001 },
-	{ 0x0010a0,   2, 0x04, 0x00000000 },
-	{ 0x001644,   1, 0x04, 0x00000000 },
-	{ 0x000748,   1, 0x04, 0x00000000 },
-	{ 0x000de8,   1, 0x04, 0x00000000 },
-	{ 0x001648,   1, 0x04, 0x00000000 },
-	{ 0x0012a4,   1, 0x04, 0x00000000 },
-	{ 0x001120,   4, 0x04, 0x00000000 },
-	{ 0x001118,   1, 0x04, 0x00000000 },
-	{ 0x00164c,   1, 0x04, 0x00000000 },
-	{ 0x001658,   1, 0x04, 0x00000000 },
-	{ 0x001910,   1, 0x04, 0x00000290 },
-	{ 0x001518,   1, 0x04, 0x00000000 },
-	{ 0x00165c,   1, 0x04, 0x00000001 },
-	{ 0x001520,   1, 0x04, 0x00000000 },
-	{ 0x001604,   1, 0x04, 0x00000000 },
-	{ 0x001570,   1, 0x04, 0x00000000 },
-	{ 0x0013b0,   2, 0x04, 0x3f800000 },
-	{ 0x00020c,   1, 0x04, 0x00000000 },
-	{ 0x001670,   1, 0x04, 0x30201000 },
-	{ 0x001674,   1, 0x04, 0x70605040 },
-	{ 0x001678,   1, 0x04, 0xb8a89888 },
-	{ 0x00167c,   1, 0x04, 0xf8e8d8c8 },
-	{ 0x00166c,   1, 0x04, 0x00000000 },
-	{ 0x001680,   1, 0x04, 0x00ffff00 },
-	{ 0x0012d0,   1, 0x04, 0x00000003 },
-	{ 0x0012d4,   1, 0x04, 0x00000002 },
-	{ 0x001684,   2, 0x04, 0x00000000 },
-	{ 0x000dac,   2, 0x04, 0x00001b02 },
-	{ 0x000db4,   1, 0x04, 0x00000000 },
-	{ 0x00168c,   1, 0x04, 0x00000000 },
-	{ 0x0015bc,   1, 0x04, 0x00000000 },
-	{ 0x00156c,   1, 0x04, 0x00000000 },
-	{ 0x00187c,   1, 0x04, 0x00000000 },
-	{ 0x001110,   1, 0x04, 0x00000001 },
-	{ 0x000dc0,   3, 0x04, 0x00000000 },
-	{ 0x000f40,   5, 0x04, 0x00000000 },
-	{ 0x001234,   1, 0x04, 0x00000000 },
-	{ 0x001690,   1, 0x04, 0x00000000 },
-	{ 0x000790,   5, 0x04, 0x00000000 },
-	{ 0x00077c,   1, 0x04, 0x00000000 },
-	{ 0x001000,   1, 0x04, 0x00000010 },
-	{ 0x0010fc,   1, 0x04, 0x00000000 },
-	{ 0x001290,   1, 0x04, 0x00000000 },
-	{ 0x000218,   1, 0x04, 0x00000010 },
-	{ 0x0012d8,   1, 0x04, 0x00000000 },
-	{ 0x0012dc,   1, 0x04, 0x00000010 },
-	{ 0x000d94,   1, 0x04, 0x00000001 },
-	{ 0x00155c,   2, 0x04, 0x00000000 },
-	{ 0x001564,   1, 0x04, 0x00000fff },
-	{ 0x001574,   2, 0x04, 0x00000000 },
-	{ 0x00157c,   1, 0x04, 0x000fffff },
-	{ 0x001354,   1, 0x04, 0x00000000 },
-	{ 0x001610,   1, 0x04, 0x00000012 },
-	{ 0x001608,   2, 0x04, 0x00000000 },
-	{ 0x00260c,   1, 0x04, 0x00000000 },
-	{ 0x0007ac,   1, 0x04, 0x00000000 },
-	{ 0x00162c,   1, 0x04, 0x00000003 },
-	{ 0x000210,   1, 0x04, 0x00000000 },
-	{ 0x000320,   1, 0x04, 0x00000000 },
-	{ 0x000324,   6, 0x04, 0x3f800000 },
-	{ 0x000750,   1, 0x04, 0x00000000 },
-	{ 0x000760,   1, 0x04, 0x39291909 },
-	{ 0x000764,   1, 0x04, 0x79695949 },
-	{ 0x000768,   1, 0x04, 0xb9a99989 },
-	{ 0x00076c,   1, 0x04, 0xf9e9d9c9 },
-	{ 0x000770,   1, 0x04, 0x30201000 },
-	{ 0x000774,   1, 0x04, 0x70605040 },
-	{ 0x000778,   1, 0x04, 0x00009080 },
-	{ 0x000780,   1, 0x04, 0x39291909 },
-	{ 0x000784,   1, 0x04, 0x79695949 },
-	{ 0x000788,   1, 0x04, 0xb9a99989 },
-	{ 0x00078c,   1, 0x04, 0xf9e9d9c9 },
-	{ 0x0007d0,   1, 0x04, 0x30201000 },
-	{ 0x0007d4,   1, 0x04, 0x70605040 },
-	{ 0x0007d8,   1, 0x04, 0x00009080 },
-	{ 0x00037c,   1, 0x04, 0x00000001 },
-	{ 0x000740,   2, 0x04, 0x00000000 },
-	{ 0x002600,   1, 0x04, 0x00000000 },
-	{ 0x001918,   1, 0x04, 0x00000000 },
-	{ 0x00191c,   1, 0x04, 0x00000900 },
-	{ 0x001920,   1, 0x04, 0x00000405 },
-	{ 0x001308,   1, 0x04, 0x00000001 },
-	{ 0x001924,   1, 0x04, 0x00000000 },
-	{ 0x0013ac,   1, 0x04, 0x00000000 },
-	{ 0x00192c,   1, 0x04, 0x00000001 },
-	{ 0x00193c,   1, 0x04, 0x00002c1c },
-	{ 0x000d7c,   1, 0x04, 0x00000000 },
-	{ 0x000f8c,   1, 0x04, 0x00000000 },
-	{ 0x0002c0,   1, 0x04, 0x00000001 },
-	{ 0x001510,   1, 0x04, 0x00000000 },
-	{ 0x001940,   1, 0x04, 0x00000000 },
-	{ 0x000ff4,   2, 0x04, 0x00000000 },
-	{ 0x00194c,   2, 0x04, 0x00000000 },
-	{ 0x001968,   1, 0x04, 0x00000000 },
-	{ 0x001590,   1, 0x04, 0x0000003f },
-	{ 0x0007e8,   4, 0x04, 0x00000000 },
-	{ 0x00196c,   1, 0x04, 0x00000011 },
-	{ 0x0002e4,   1, 0x04, 0x0000b001 },
-	{ 0x00036c,   2, 0x04, 0x00000000 },
-	{ 0x00197c,   1, 0x04, 0x00000000 },
-	{ 0x000fcc,   2, 0x04, 0x00000000 },
-	{ 0x0002d8,   1, 0x04, 0x00000040 },
-	{ 0x001980,   1, 0x04, 0x00000080 },
-	{ 0x001504,   1, 0x04, 0x00000080 },
-	{ 0x001984,   1, 0x04, 0x00000000 },
-	{ 0x000f60,   1, 0x04, 0x00000000 },
-	{ 0x000f64,   1, 0x04, 0x00400040 },
-	{ 0x000f68,   1, 0x04, 0x00002212 },
-	{ 0x000f6c,   1, 0x04, 0x08080203 },
-	{ 0x001108,   1, 0x04, 0x00000008 },
-	{ 0x000f70,   1, 0x04, 0x00080001 },
-	{ 0x000ffc,   1, 0x04, 0x00000000 },
-	{ 0x000300,   1, 0x04, 0x00000001 },
-	{ 0x0013a8,   1, 0x04, 0x00000000 },
-	{ 0x0012ec,   1, 0x04, 0x00000000 },
-	{ 0x001310,   1, 0x04, 0x00000000 },
-	{ 0x001314,   1, 0x04, 0x00000001 },
-	{ 0x001380,   1, 0x04, 0x00000000 },
-	{ 0x001384,   4, 0x04, 0x00000001 },
-	{ 0x001394,   1, 0x04, 0x00000000 },
-	{ 0x00139c,   1, 0x04, 0x00000000 },
-	{ 0x001398,   1, 0x04, 0x00000000 },
-	{ 0x001594,   1, 0x04, 0x00000000 },
-	{ 0x001598,   4, 0x04, 0x00000001 },
-	{ 0x000f54,   3, 0x04, 0x00000000 },
-	{ 0x0019bc,   1, 0x04, 0x00000000 },
-	{ 0x000f9c,   2, 0x04, 0x00000000 },
-	{ 0x0012cc,   1, 0x04, 0x00000000 },
-	{ 0x0012e8,   1, 0x04, 0x00000000 },
-	{ 0x00130c,   1, 0x04, 0x00000001 },
-	{ 0x001360,   8, 0x04, 0x00000000 },
-	{ 0x00133c,   2, 0x04, 0x00000001 },
-	{ 0x001344,   1, 0x04, 0x00000002 },
-	{ 0x001348,   2, 0x04, 0x00000001 },
-	{ 0x001350,   1, 0x04, 0x00000002 },
-	{ 0x001358,   1, 0x04, 0x00000001 },
-	{ 0x0012e4,   1, 0x04, 0x00000000 },
-	{ 0x00131c,   4, 0x04, 0x00000000 },
-	{ 0x0019c0,   1, 0x04, 0x00000000 },
-	{ 0x001140,   1, 0x04, 0x00000000 },
-	{ 0x000dd0,   1, 0x04, 0x00000000 },
-	{ 0x000dd4,   1, 0x04, 0x00000001 },
-	{ 0x0002f4,   1, 0x04, 0x00000000 },
-	{ 0x0019c4,   1, 0x04, 0x00000000 },
-	{ 0x0019c8,   1, 0x04, 0x00001500 },
-	{ 0x00135c,   1, 0x04, 0x00000000 },
-	{ 0x000f90,   1, 0x04, 0x00000000 },
-	{ 0x0019e0,   8, 0x04, 0x00000001 },
-	{ 0x0019cc,   1, 0x04, 0x00000001 },
-	{ 0x0015b8,   1, 0x04, 0x00000000 },
-	{ 0x001a00,   1, 0x04, 0x00001111 },
-	{ 0x001a04,   7, 0x04, 0x00000000 },
-	{ 0x000d6c,   2, 0x04, 0xffff0000 },
-	{ 0x0010f8,   1, 0x04, 0x00001010 },
-	{ 0x000d80,   5, 0x04, 0x00000000 },
-	{ 0x000da0,   1, 0x04, 0x00000000 },
-	{ 0x0007a4,   2, 0x04, 0x00000000 },
-	{ 0x001508,   1, 0x04, 0x80000000 },
-	{ 0x00150c,   1, 0x04, 0x40000000 },
-	{ 0x001668,   1, 0x04, 0x00000000 },
-	{ 0x000318,   2, 0x04, 0x00000008 },
-	{ 0x000d9c,   1, 0x04, 0x00000001 },
-	{ 0x000f14,   1, 0x04, 0x00000000 },
-	{ 0x000374,   1, 0x04, 0x00000000 },
-	{ 0x000378,   1, 0x04, 0x0000000c },
-	{ 0x0007dc,   1, 0x04, 0x00000000 },
-	{ 0x00074c,   1, 0x04, 0x00000055 },
-	{ 0x001420,   1, 0x04, 0x00000003 },
-	{ 0x001008,   1, 0x04, 0x00000008 },
-	{ 0x00100c,   1, 0x04, 0x00000040 },
-	{ 0x001010,   1, 0x04, 0x0000012c },
-	{ 0x000d60,   1, 0x04, 0x00000040 },
-	{ 0x001018,   1, 0x04, 0x00000020 },
-	{ 0x00101c,   1, 0x04, 0x00000001 },
-	{ 0x001020,   1, 0x04, 0x00000020 },
-	{ 0x001024,   1, 0x04, 0x00000001 },
-	{ 0x001444,   3, 0x04, 0x00000000 },
-	{ 0x000360,   1, 0x04, 0x20164010 },
-	{ 0x000364,   1, 0x04, 0x00000020 },
-	{ 0x000368,   1, 0x04, 0x00000000 },
-	{ 0x000da8,   1, 0x04, 0x00000030 },
-	{ 0x000de4,   1, 0x04, 0x00000000 },
-	{ 0x000204,   1, 0x04, 0x00000006 },
-	{ 0x0002d0,   1, 0x04, 0x003fffff },
-	{ 0x001220,   1, 0x04, 0x00000005 },
-	{ 0x000fdc,   1, 0x04, 0x00000000 },
-	{ 0x000f98,   1, 0x04, 0x00400008 },
-	{ 0x001284,   1, 0x04, 0x08000080 },
-	{ 0x001450,   1, 0x04, 0x00400008 },
-	{ 0x001454,   1, 0x04, 0x08000080 },
-	{ 0x000214,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-gm107_grctx_pack_mthd[] = {
-	{ gm107_grctx_init_b097_0, 0xb097 },
-	{ nvc0_grctx_init_902d_0, 0x902d },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_grctx_init_fe_0[] = {
-	{ 0x404004,   8, 0x04, 0x00000000 },
-	{ 0x404024,   1, 0x04, 0x0000e000 },
-	{ 0x404028,   8, 0x04, 0x00000000 },
-	{ 0x4040a8,   8, 0x04, 0x00000000 },
-	{ 0x4040c8,   1, 0x04, 0xf800008f },
-	{ 0x4040d0,   6, 0x04, 0x00000000 },
-	{ 0x4040f8,   1, 0x04, 0x00000000 },
-	{ 0x404100,  10, 0x04, 0x00000000 },
-	{ 0x404130,   2, 0x04, 0x00000000 },
-	{ 0x404150,   1, 0x04, 0x0000002e },
-	{ 0x404154,   1, 0x04, 0x00000400 },
-	{ 0x404158,   1, 0x04, 0x00000200 },
-	{ 0x404164,   1, 0x04, 0x00000045 },
-	{ 0x40417c,   2, 0x04, 0x00000000 },
-	{ 0x404194,   1, 0x04, 0x01000700 },
-	{ 0x4041a0,   4, 0x04, 0x00000000 },
-	{ 0x404200,   4, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_grctx_init_ds_0[] = {
-	{ 0x405800,   1, 0x04, 0x0f8001bf },
-	{ 0x405830,   1, 0x04, 0x0aa01000 },
-	{ 0x405834,   1, 0x04, 0x08000000 },
-	{ 0x405838,   1, 0x04, 0x00000000 },
-	{ 0x405854,   1, 0x04, 0x00000000 },
-	{ 0x405870,   4, 0x04, 0x00000001 },
-	{ 0x405a00,   2, 0x04, 0x00000000 },
-	{ 0x405a18,   1, 0x04, 0x00000000 },
-	{ 0x405a1c,   1, 0x04, 0x000000ff },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_grctx_init_pd_0[] = {
-	{ 0x406020,   1, 0x04, 0x07410001 },
-	{ 0x406028,   4, 0x04, 0x00000001 },
-	{ 0x4064a8,   1, 0x04, 0x00000000 },
-	{ 0x4064ac,   1, 0x04, 0x00003fff },
-	{ 0x4064b0,   3, 0x04, 0x00000000 },
-	{ 0x4064c0,   1, 0x04, 0x80400280 },
-	{ 0x4064c4,   1, 0x04, 0x0400ffff },
-	{ 0x4064c8,   1, 0x04, 0x018001ff },
-	{ 0x4064cc,   9, 0x04, 0x00000000 },
-	{ 0x4064fc,   1, 0x04, 0x0000022a },
-	{ 0x406500,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_grctx_init_be_0[] = {
-	{ 0x408800,   1, 0x04, 0x32802a3c },
-	{ 0x408804,   1, 0x04, 0x00000040 },
-	{ 0x408808,   1, 0x04, 0x1003e005 },
-	{ 0x408840,   1, 0x04, 0x0000000b },
-	{ 0x408900,   1, 0x04, 0xb080b801 },
-	{ 0x408904,   1, 0x04, 0x63038001 },
-	{ 0x408908,   1, 0x04, 0x02c8102f },
-	{ 0x408980,   1, 0x04, 0x0000011d },
-	{}
-};
-
-static const struct nvc0_graph_pack
-gm107_grctx_pack_hub[] = {
-	{ nvc0_grctx_init_main_0 },
-	{ gm107_grctx_init_fe_0 },
-	{ nvf0_grctx_init_pri_0 },
-	{ nve4_grctx_init_memfmt_0 },
-	{ gm107_grctx_init_ds_0 },
-	{ nvf0_grctx_init_cwd_0 },
-	{ gm107_grctx_init_pd_0 },
-	{ nv108_grctx_init_rstr2d_0 },
-	{ nve4_grctx_init_scc_0 },
-	{ gm107_grctx_init_be_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_grctx_init_gpc_unk_0[] = {
-	{ 0x418380,   1, 0x04, 0x00000056 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_grctx_init_gpc_unk_1[] = {
-	{ 0x418600,   1, 0x04, 0x0000007f },
-	{ 0x418684,   1, 0x04, 0x0000001f },
-	{ 0x418700,   1, 0x04, 0x00000002 },
-	{ 0x418704,   1, 0x04, 0x00000080 },
-	{ 0x418708,   1, 0x04, 0x40000000 },
-	{ 0x41870c,   2, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_grctx_init_setup_0[] = {
-	{ 0x418800,   1, 0x04, 0x7006863a },
-	{ 0x418810,   1, 0x04, 0x00000000 },
-	{ 0x418828,   1, 0x04, 0x00000044 },
-	{ 0x418830,   1, 0x04, 0x10000001 },
-	{ 0x4188d8,   1, 0x04, 0x00000008 },
-	{ 0x4188e0,   1, 0x04, 0x01000000 },
-	{ 0x4188e8,   5, 0x04, 0x00000000 },
-	{ 0x4188fc,   1, 0x04, 0x20100058 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_grctx_init_gpc_unk_2[] = {
-	{ 0x418d24,   1, 0x04, 0x00000000 },
-	{ 0x418e00,   1, 0x04, 0x90000000 },
-	{ 0x418e24,   1, 0x04, 0x00000000 },
-	{ 0x418e28,   1, 0x04, 0x00000030 },
-	{ 0x418e30,   1, 0x04, 0x00000000 },
-	{ 0x418e34,   1, 0x04, 0x00010000 },
-	{ 0x418e38,   1, 0x04, 0x00000000 },
-	{ 0x418e40,  22, 0x04, 0x00000000 },
-	{ 0x418ea0,   2, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-gm107_grctx_pack_gpc[] = {
-	{ gm107_grctx_init_gpc_unk_0 },
-	{ nv108_grctx_init_prop_0 },
-	{ gm107_grctx_init_gpc_unk_1 },
-	{ gm107_grctx_init_setup_0 },
-	{ nvc0_grctx_init_zcull_0 },
-	{ nv108_grctx_init_crstr_0 },
-	{ nve4_grctx_init_gpm_0 },
-	{ gm107_grctx_init_gpc_unk_2 },
-	{ nvc0_grctx_init_gcc_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_grctx_init_tex_0[] = {
-	{ 0x419a00,   1, 0x04, 0x000300f0 },
-	{ 0x419a04,   1, 0x04, 0x00000005 },
-	{ 0x419a08,   1, 0x04, 0x00000421 },
-	{ 0x419a0c,   1, 0x04, 0x00120000 },
-	{ 0x419a10,   1, 0x04, 0x00000000 },
-	{ 0x419a14,   1, 0x04, 0x00002200 },
-	{ 0x419a1c,   1, 0x04, 0x0000c000 },
-	{ 0x419a20,   1, 0x04, 0x20008a00 },
-	{ 0x419a30,   1, 0x04, 0x00000001 },
-	{ 0x419a3c,   1, 0x04, 0x00000002 },
-	{ 0x419ac4,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_grctx_init_mpc_0[] = {
-	{ 0x419c00,   1, 0x04, 0x0000001a },
-	{ 0x419c04,   1, 0x04, 0x80000006 },
-	{ 0x419c08,   1, 0x04, 0x00000002 },
-	{ 0x419c20,   1, 0x04, 0x00000000 },
-	{ 0x419c24,   1, 0x04, 0x00084210 },
-	{ 0x419c28,   1, 0x04, 0x3efbefbe },
-	{ 0x419c2c,   1, 0x04, 0x00000000 },
-	{ 0x419c34,   1, 0x04, 0x01ff1ff3 },
-	{ 0x419c3c,   1, 0x04, 0x00001919 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_grctx_init_l1c_0[] = {
-	{ 0x419c84,   1, 0x04, 0x00000020 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_grctx_init_sm_0[] = {
-	{ 0x419e04,   3, 0x04, 0x00000000 },
-	{ 0x419e10,   1, 0x04, 0x00001c02 },
-	{ 0x419e44,   1, 0x04, 0x00d3eff2 },
-	{ 0x419e48,   1, 0x04, 0x00000000 },
-	{ 0x419e4c,   1, 0x04, 0x0000007f },
-	{ 0x419e50,   1, 0x04, 0x00000000 },
-	{ 0x419e60,   4, 0x04, 0x00000000 },
-	{ 0x419e74,  10, 0x04, 0x00000000 },
-	{ 0x419eac,   1, 0x04, 0x0001cf8b },
-	{ 0x419eb0,   1, 0x04, 0x00030300 },
-	{ 0x419eb8,   1, 0x04, 0x00000000 },
-	{ 0x419ef0,  24, 0x04, 0x00000000 },
-	{ 0x419f68,   2, 0x04, 0x00000000 },
-	{ 0x419f70,   1, 0x04, 0x00000020 },
-	{ 0x419f78,   1, 0x04, 0x000003eb },
-	{ 0x419f7c,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-gm107_grctx_pack_tpc[] = {
-	{ nvd7_grctx_init_pe_0 },
-	{ gm107_grctx_init_tex_0 },
-	{ gm107_grctx_init_mpc_0 },
-	{ gm107_grctx_init_l1c_0 },
-	{ gm107_grctx_init_sm_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_grctx_init_cbm_0[] = {
-	{ 0x41bec0,   1, 0x04, 0x00000000 },
-	{ 0x41bec4,   1, 0x04, 0x01050000 },
-	{ 0x41bee4,   1, 0x04, 0x00000000 },
-	{ 0x41bef0,   1, 0x04, 0x000003ff },
-	{ 0x41bef4,   2, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_grctx_init_wwdx_0[] = {
-	{ 0x41bf00,   1, 0x04, 0x0a418820 },
-	{ 0x41bf04,   1, 0x04, 0x062080e6 },
-	{ 0x41bf08,   1, 0x04, 0x020398a4 },
-	{ 0x41bf0c,   1, 0x04, 0x0e629062 },
-	{ 0x41bf10,   1, 0x04, 0x0a418820 },
-	{ 0x41bf14,   1, 0x04, 0x000000e6 },
-	{ 0x41bfd0,   1, 0x04, 0x00900103 },
-	{ 0x41bfe0,   1, 0x04, 0x80000000 },
-	{ 0x41bfe4,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-gm107_grctx_pack_ppc[] = {
-	{ nve4_grctx_init_pes_0 },
-	{ gm107_grctx_init_cbm_0 },
-	{ gm107_grctx_init_wwdx_0 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH context implementation
- ******************************************************************************/
-
-static void
-gm107_grctx_generate_bundle(struct nvc0_grctx *info)
-{
-	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
-	const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth,
-				    impl->bundle_size / 0x20);
-	const u32 token_limit = impl->bundle_token_limit;
-	const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
-	const int s = 8;
-	const int b = mmio_vram(info, impl->bundle_size, (1 << s), access);
-	mmio_refn(info, 0x408004, 0x00000000, s, b);
-	mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b);
-	mmio_refn(info, 0x418e24, 0x00000000, s, b);
-	mmio_refn(info, 0x418e28, 0x80000000 | (impl->bundle_size >> s), 0, b);
-	mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit);
-}
-
-static void
-gm107_grctx_generate_pagepool(struct nvc0_grctx *info)
-{
-	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
-	const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
-	const int s = 8;
-	const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
-	mmio_refn(info, 0x40800c, 0x00000000, s, b);
-	mmio_wr32(info, 0x408010, 0x80000000);
-	mmio_refn(info, 0x419004, 0x00000000, s, b);
-	mmio_wr32(info, 0x419008, 0x00000000);
-	mmio_wr32(info, 0x4064cc, 0x80000000);
-	mmio_wr32(info, 0x418e30, 0x80000000); /* guess at it being related */
-}
-
-static void
-gm107_grctx_generate_attrib(struct nvc0_grctx *info)
-{
-	struct nvc0_graph_priv *priv = info->priv;
-	const struct nvc0_grctx_oclass *impl = (void *)nvc0_grctx_impl(priv);
-	const u32  alpha = impl->alpha_nr;
-	const u32 attrib = impl->attrib_nr;
-	const u32   size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
-	const u32 access = NV_MEM_ACCESS_RW;
-	const int s = 12;
-	const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access);
-	const int max_batches = 0xffff;
-	u32 bo = 0;
-	u32 ao = bo + impl->attrib_nr_max * priv->tpc_total;
-	int gpc, ppc, n = 0;
-
-	mmio_refn(info, 0x418810, 0x80000000, s, b);
-	mmio_refn(info, 0x419848, 0x10000000, s, b);
-	mmio_refn(info, 0x419c2c, 0x10000000, s, b);
-	mmio_wr32(info, 0x405830, (attrib << 16) | alpha);
-	mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
-
-	for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-		for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++, n++) {
-			const u32 as =  alpha * priv->ppc_tpc_nr[gpc][ppc];
-			const u32 bs = attrib * priv->ppc_tpc_nr[gpc][ppc];
-			const u32 u = 0x418ea0 + (n * 0x04);
-			const u32 o = PPC_UNIT(gpc, ppc, 0);
-			mmio_wr32(info, o + 0xc0, bs);
-			mmio_wr32(info, o + 0xf4, bo);
-			bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc];
-			mmio_wr32(info, o + 0xe4, as);
-			mmio_wr32(info, o + 0xf8, ao);
-			ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc];
-			mmio_wr32(info, u, (0x715 /*XXX*/ << 16) | bs);
-		}
-	}
-}
-
-static void
-gm107_grctx_generate_tpcid(struct nvc0_graph_priv *priv)
-{
-	int gpc, tpc, id;
-
-	for (tpc = 0, id = 0; tpc < 4; tpc++) {
-		for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-			if (tpc < priv->tpc_nr[gpc]) {
-				nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id);
-				nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
-				nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id);
-				id++;
-			}
-
-			nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]);
-			nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]);
-		}
-	}
-}
-
-static void
-gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
-{
-	struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
-	int i;
-
-	nvc0_graph_mmio(priv, oclass->hub);
-	nvc0_graph_mmio(priv, oclass->gpc);
-	nvc0_graph_mmio(priv, oclass->zcull);
-	nvc0_graph_mmio(priv, oclass->tpc);
-	nvc0_graph_mmio(priv, oclass->ppc);
-
-	nv_wr32(priv, 0x404154, 0x00000000);
-
-	oclass->bundle(info);
-	oclass->pagepool(info);
-	oclass->attrib(info);
-	oclass->unkn(priv);
-
-	gm107_grctx_generate_tpcid(priv);
-	nvc0_grctx_generate_r406028(priv);
-	nve4_grctx_generate_r418bb8(priv);
-	nvc0_grctx_generate_r406800(priv);
-
-	nv_wr32(priv, 0x4064d0, 0x00000001);
-	for (i = 1; i < 8; i++)
-		nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
-	nv_wr32(priv, 0x406500, 0x00000001);
-
-	nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
-
-	if (priv->gpc_nr == 1) {
-		nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]);
-		nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]);
-	} else {
-		nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr);
-		nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
-	}
-
-	nvc0_graph_icmd(priv, oclass->icmd);
-	nv_wr32(priv, 0x404154, 0x00000400);
-	nvc0_graph_mthd(priv, oclass->mthd);
-
-	nv_mask(priv, 0x419e00, 0x00808080, 0x00808080);
-	nv_mask(priv, 0x419ccc, 0x80000000, 0x80000000);
-	nv_mask(priv, 0x419f80, 0x80000000, 0x80000000);
-	nv_mask(priv, 0x419f88, 0x80000000, 0x80000000);
-}
-
-struct nouveau_oclass *
-gm107_grctx_oclass = &(struct nvc0_grctx_oclass) {
-	.base.handle = NV_ENGCTX(GR, 0x08),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-	.main  = gm107_grctx_generate_main,
-	.unkn  = nve4_grctx_generate_unkn,
-	.hub   = gm107_grctx_pack_hub,
-	.gpc   = gm107_grctx_pack_gpc,
-	.zcull = nvc0_grctx_pack_zcull,
-	.tpc   = gm107_grctx_pack_tpc,
-	.ppc   = gm107_grctx_pack_ppc,
-	.icmd  = gm107_grctx_pack_icmd,
-	.mthd  = gm107_grctx_pack_mthd,
-	.bundle = gm107_grctx_generate_bundle,
-	.bundle_size = 0x3000,
-	.bundle_min_gpm_fifo_depth = 0x180,
-	.bundle_token_limit = 0x2c0,
-	.pagepool = gm107_grctx_generate_pagepool,
-	.pagepool_size = 0x8000,
-	.attrib = gm107_grctx_generate_attrib,
-	.attrib_nr_max = 0xff0,
-	.attrib_nr = 0xaa0,
-	.alpha_nr_max = 0x1800,
-	.alpha_nr = 0x1000,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c
deleted file mode 100644
index ce252adbef81..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c
+++ /dev/null
@@ -1,565 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * PGRAPH context register lists
- ******************************************************************************/
-
-static const struct nvc0_graph_init
-nv108_grctx_init_icmd_0[] = {
-	{ 0x001000,   1, 0x01, 0x00000004 },
-	{ 0x000039,   3, 0x01, 0x00000000 },
-	{ 0x0000a9,   1, 0x01, 0x0000ffff },
-	{ 0x000038,   1, 0x01, 0x0fac6881 },
-	{ 0x00003d,   1, 0x01, 0x00000001 },
-	{ 0x0000e8,   8, 0x01, 0x00000400 },
-	{ 0x000078,   8, 0x01, 0x00000300 },
-	{ 0x000050,   1, 0x01, 0x00000011 },
-	{ 0x000058,   8, 0x01, 0x00000008 },
-	{ 0x000208,   8, 0x01, 0x00000001 },
-	{ 0x000081,   1, 0x01, 0x00000001 },
-	{ 0x000085,   1, 0x01, 0x00000004 },
-	{ 0x000088,   1, 0x01, 0x00000400 },
-	{ 0x000090,   1, 0x01, 0x00000300 },
-	{ 0x000098,   1, 0x01, 0x00001001 },
-	{ 0x0000e3,   1, 0x01, 0x00000001 },
-	{ 0x0000da,   1, 0x01, 0x00000001 },
-	{ 0x0000f8,   1, 0x01, 0x00000003 },
-	{ 0x0000fa,   1, 0x01, 0x00000001 },
-	{ 0x00009f,   4, 0x01, 0x0000ffff },
-	{ 0x0000b1,   1, 0x01, 0x00000001 },
-	{ 0x0000ad,   1, 0x01, 0x0000013e },
-	{ 0x0000e1,   1, 0x01, 0x00000010 },
-	{ 0x000290,  16, 0x01, 0x00000000 },
-	{ 0x0003b0,  16, 0x01, 0x00000000 },
-	{ 0x0002a0,  16, 0x01, 0x00000000 },
-	{ 0x000420,  16, 0x01, 0x00000000 },
-	{ 0x0002b0,  16, 0x01, 0x00000000 },
-	{ 0x000430,  16, 0x01, 0x00000000 },
-	{ 0x0002c0,  16, 0x01, 0x00000000 },
-	{ 0x0004d0,  16, 0x01, 0x00000000 },
-	{ 0x000720,  16, 0x01, 0x00000000 },
-	{ 0x0008c0,  16, 0x01, 0x00000000 },
-	{ 0x000890,  16, 0x01, 0x00000000 },
-	{ 0x0008e0,  16, 0x01, 0x00000000 },
-	{ 0x0008a0,  16, 0x01, 0x00000000 },
-	{ 0x0008f0,  16, 0x01, 0x00000000 },
-	{ 0x00094c,   1, 0x01, 0x000000ff },
-	{ 0x00094d,   1, 0x01, 0xffffffff },
-	{ 0x00094e,   1, 0x01, 0x00000002 },
-	{ 0x0002ec,   1, 0x01, 0x00000001 },
-	{ 0x0002f2,   2, 0x01, 0x00000001 },
-	{ 0x0002f5,   1, 0x01, 0x00000001 },
-	{ 0x0002f7,   1, 0x01, 0x00000001 },
-	{ 0x000303,   1, 0x01, 0x00000001 },
-	{ 0x0002e6,   1, 0x01, 0x00000001 },
-	{ 0x000466,   1, 0x01, 0x00000052 },
-	{ 0x000301,   1, 0x01, 0x3f800000 },
-	{ 0x000304,   1, 0x01, 0x30201000 },
-	{ 0x000305,   1, 0x01, 0x70605040 },
-	{ 0x000306,   1, 0x01, 0xb8a89888 },
-	{ 0x000307,   1, 0x01, 0xf8e8d8c8 },
-	{ 0x00030a,   1, 0x01, 0x00ffff00 },
-	{ 0x00030b,   1, 0x01, 0x0000001a },
-	{ 0x00030c,   1, 0x01, 0x00000001 },
-	{ 0x000318,   1, 0x01, 0x00000001 },
-	{ 0x000340,   1, 0x01, 0x00000000 },
-	{ 0x000375,   1, 0x01, 0x00000001 },
-	{ 0x00037d,   1, 0x01, 0x00000006 },
-	{ 0x0003a0,   1, 0x01, 0x00000002 },
-	{ 0x0003aa,   1, 0x01, 0x00000001 },
-	{ 0x0003a9,   1, 0x01, 0x00000001 },
-	{ 0x000380,   1, 0x01, 0x00000001 },
-	{ 0x000383,   1, 0x01, 0x00000011 },
-	{ 0x000360,   1, 0x01, 0x00000040 },
-	{ 0x000366,   2, 0x01, 0x00000000 },
-	{ 0x000368,   1, 0x01, 0x00000fff },
-	{ 0x000370,   2, 0x01, 0x00000000 },
-	{ 0x000372,   1, 0x01, 0x000fffff },
-	{ 0x00037a,   1, 0x01, 0x00000012 },
-	{ 0x000619,   1, 0x01, 0x00000003 },
-	{ 0x000811,   1, 0x01, 0x00000003 },
-	{ 0x000812,   1, 0x01, 0x00000004 },
-	{ 0x000813,   1, 0x01, 0x00000006 },
-	{ 0x000814,   1, 0x01, 0x00000008 },
-	{ 0x000815,   1, 0x01, 0x0000000b },
-	{ 0x000800,   6, 0x01, 0x00000001 },
-	{ 0x000632,   1, 0x01, 0x00000001 },
-	{ 0x000633,   1, 0x01, 0x00000002 },
-	{ 0x000634,   1, 0x01, 0x00000003 },
-	{ 0x000635,   1, 0x01, 0x00000004 },
-	{ 0x000654,   1, 0x01, 0x3f800000 },
-	{ 0x000657,   1, 0x01, 0x3f800000 },
-	{ 0x000655,   2, 0x01, 0x3f800000 },
-	{ 0x0006cd,   1, 0x01, 0x3f800000 },
-	{ 0x0007f5,   1, 0x01, 0x3f800000 },
-	{ 0x0007dc,   1, 0x01, 0x39291909 },
-	{ 0x0007dd,   1, 0x01, 0x79695949 },
-	{ 0x0007de,   1, 0x01, 0xb9a99989 },
-	{ 0x0007df,   1, 0x01, 0xf9e9d9c9 },
-	{ 0x0007e8,   1, 0x01, 0x00003210 },
-	{ 0x0007e9,   1, 0x01, 0x00007654 },
-	{ 0x0007ea,   1, 0x01, 0x00000098 },
-	{ 0x0007ec,   1, 0x01, 0x39291909 },
-	{ 0x0007ed,   1, 0x01, 0x79695949 },
-	{ 0x0007ee,   1, 0x01, 0xb9a99989 },
-	{ 0x0007ef,   1, 0x01, 0xf9e9d9c9 },
-	{ 0x0007f0,   1, 0x01, 0x00003210 },
-	{ 0x0007f1,   1, 0x01, 0x00007654 },
-	{ 0x0007f2,   1, 0x01, 0x00000098 },
-	{ 0x0005a5,   1, 0x01, 0x00000001 },
-	{ 0x000980, 128, 0x01, 0x00000000 },
-	{ 0x000468,   1, 0x01, 0x00000004 },
-	{ 0x00046c,   1, 0x01, 0x00000001 },
-	{ 0x000470,  96, 0x01, 0x00000000 },
-	{ 0x000510,  16, 0x01, 0x3f800000 },
-	{ 0x000520,   1, 0x01, 0x000002b6 },
-	{ 0x000529,   1, 0x01, 0x00000001 },
-	{ 0x000530,  16, 0x01, 0xffff0000 },
-	{ 0x000585,   1, 0x01, 0x0000003f },
-	{ 0x000576,   1, 0x01, 0x00000003 },
-	{ 0x00057b,   1, 0x01, 0x00000059 },
-	{ 0x000586,   1, 0x01, 0x00000040 },
-	{ 0x000582,   2, 0x01, 0x00000080 },
-	{ 0x0005c2,   1, 0x01, 0x00000001 },
-	{ 0x000638,   2, 0x01, 0x00000001 },
-	{ 0x00063a,   1, 0x01, 0x00000002 },
-	{ 0x00063b,   2, 0x01, 0x00000001 },
-	{ 0x00063d,   1, 0x01, 0x00000002 },
-	{ 0x00063e,   1, 0x01, 0x00000001 },
-	{ 0x0008b8,   8, 0x01, 0x00000001 },
-	{ 0x000900,   8, 0x01, 0x00000001 },
-	{ 0x000908,   8, 0x01, 0x00000002 },
-	{ 0x000910,  16, 0x01, 0x00000001 },
-	{ 0x000920,   8, 0x01, 0x00000002 },
-	{ 0x000928,   8, 0x01, 0x00000001 },
-	{ 0x000662,   1, 0x01, 0x00000001 },
-	{ 0x000648,   9, 0x01, 0x00000001 },
-	{ 0x000658,   1, 0x01, 0x0000000f },
-	{ 0x0007ff,   1, 0x01, 0x0000000a },
-	{ 0x00066a,   1, 0x01, 0x40000000 },
-	{ 0x00066b,   1, 0x01, 0x10000000 },
-	{ 0x00066c,   2, 0x01, 0xffff0000 },
-	{ 0x0007af,   2, 0x01, 0x00000008 },
-	{ 0x0007f6,   1, 0x01, 0x00000001 },
-	{ 0x00080b,   1, 0x01, 0x00000002 },
-	{ 0x0006b2,   1, 0x01, 0x00000055 },
-	{ 0x0007ad,   1, 0x01, 0x00000003 },
-	{ 0x000937,   1, 0x01, 0x00000001 },
-	{ 0x000971,   1, 0x01, 0x00000008 },
-	{ 0x000972,   1, 0x01, 0x00000040 },
-	{ 0x000973,   1, 0x01, 0x0000012c },
-	{ 0x00097c,   1, 0x01, 0x00000040 },
-	{ 0x000979,   1, 0x01, 0x00000003 },
-	{ 0x000975,   1, 0x01, 0x00000020 },
-	{ 0x000976,   1, 0x01, 0x00000001 },
-	{ 0x000977,   1, 0x01, 0x00000020 },
-	{ 0x000978,   1, 0x01, 0x00000001 },
-	{ 0x000957,   1, 0x01, 0x00000003 },
-	{ 0x00095e,   1, 0x01, 0x20164010 },
-	{ 0x00095f,   1, 0x01, 0x00000020 },
-	{ 0x000a0d,   1, 0x01, 0x00000006 },
-	{ 0x00097d,   1, 0x01, 0x00000020 },
-	{ 0x000683,   1, 0x01, 0x00000006 },
-	{ 0x000685,   1, 0x01, 0x003fffff },
-	{ 0x000687,   1, 0x01, 0x003fffff },
-	{ 0x0006a0,   1, 0x01, 0x00000005 },
-	{ 0x000840,   1, 0x01, 0x00400008 },
-	{ 0x000841,   1, 0x01, 0x08000080 },
-	{ 0x000842,   1, 0x01, 0x00400008 },
-	{ 0x000843,   1, 0x01, 0x08000080 },
-	{ 0x0006aa,   1, 0x01, 0x00000001 },
-	{ 0x0006ab,   1, 0x01, 0x00000002 },
-	{ 0x0006ac,   1, 0x01, 0x00000080 },
-	{ 0x0006ad,   2, 0x01, 0x00000100 },
-	{ 0x0006b1,   1, 0x01, 0x00000011 },
-	{ 0x0006bb,   1, 0x01, 0x000000cf },
-	{ 0x0006ce,   1, 0x01, 0x2a712488 },
-	{ 0x000739,   1, 0x01, 0x4085c000 },
-	{ 0x00073a,   1, 0x01, 0x00000080 },
-	{ 0x000786,   1, 0x01, 0x80000100 },
-	{ 0x00073c,   1, 0x01, 0x00010100 },
-	{ 0x00073d,   1, 0x01, 0x02800000 },
-	{ 0x000787,   1, 0x01, 0x000000cf },
-	{ 0x00078c,   1, 0x01, 0x00000008 },
-	{ 0x000792,   1, 0x01, 0x00000001 },
-	{ 0x000794,   3, 0x01, 0x00000001 },
-	{ 0x000797,   1, 0x01, 0x000000cf },
-	{ 0x000836,   1, 0x01, 0x00000001 },
-	{ 0x00079a,   1, 0x01, 0x00000002 },
-	{ 0x000833,   1, 0x01, 0x04444480 },
-	{ 0x0007a1,   1, 0x01, 0x00000001 },
-	{ 0x0007a3,   3, 0x01, 0x00000001 },
-	{ 0x000831,   1, 0x01, 0x00000004 },
-	{ 0x000b07,   1, 0x01, 0x00000002 },
-	{ 0x000b08,   2, 0x01, 0x00000100 },
-	{ 0x000b0a,   1, 0x01, 0x00000001 },
-	{ 0x000a04,   1, 0x01, 0x000000ff },
-	{ 0x000a0b,   1, 0x01, 0x00000040 },
-	{ 0x00097f,   1, 0x01, 0x00000100 },
-	{ 0x000a02,   1, 0x01, 0x00000001 },
-	{ 0x000809,   1, 0x01, 0x00000007 },
-	{ 0x00c221,   1, 0x01, 0x00000040 },
-	{ 0x00c1b0,   8, 0x01, 0x0000000f },
-	{ 0x00c1b8,   1, 0x01, 0x0fac6881 },
-	{ 0x00c1b9,   1, 0x01, 0x00fac688 },
-	{ 0x00c401,   1, 0x01, 0x00000001 },
-	{ 0x00c402,   1, 0x01, 0x00010001 },
-	{ 0x00c403,   2, 0x01, 0x00000001 },
-	{ 0x00c40e,   1, 0x01, 0x00000020 },
-	{ 0x00c500,   1, 0x01, 0x00000003 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000002 },
-	{ 0x0006aa,   1, 0x01, 0x00000001 },
-	{ 0x0006ad,   2, 0x01, 0x00000100 },
-	{ 0x0006b1,   1, 0x01, 0x00000011 },
-	{ 0x00078c,   1, 0x01, 0x00000008 },
-	{ 0x000792,   1, 0x01, 0x00000001 },
-	{ 0x000794,   3, 0x01, 0x00000001 },
-	{ 0x000797,   1, 0x01, 0x000000cf },
-	{ 0x00079a,   1, 0x01, 0x00000002 },
-	{ 0x0007a1,   1, 0x01, 0x00000001 },
-	{ 0x0007a3,   3, 0x01, 0x00000001 },
-	{ 0x000831,   1, 0x01, 0x00000004 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000008 },
-	{ 0x000039,   3, 0x01, 0x00000000 },
-	{ 0x000380,   1, 0x01, 0x00000001 },
-	{ 0x000366,   2, 0x01, 0x00000000 },
-	{ 0x000368,   1, 0x01, 0x00000fff },
-	{ 0x000370,   2, 0x01, 0x00000000 },
-	{ 0x000372,   1, 0x01, 0x000fffff },
-	{ 0x000813,   1, 0x01, 0x00000006 },
-	{ 0x000814,   1, 0x01, 0x00000008 },
-	{ 0x000957,   1, 0x01, 0x00000003 },
-	{ 0x000b07,   1, 0x01, 0x00000002 },
-	{ 0x000b08,   2, 0x01, 0x00000100 },
-	{ 0x000b0a,   1, 0x01, 0x00000001 },
-	{ 0x000a04,   1, 0x01, 0x000000ff },
-	{ 0x000a0b,   1, 0x01, 0x00000040 },
-	{ 0x00097f,   1, 0x01, 0x00000100 },
-	{ 0x000a02,   1, 0x01, 0x00000001 },
-	{ 0x000809,   1, 0x01, 0x00000007 },
-	{ 0x00c221,   1, 0x01, 0x00000040 },
-	{ 0x00c401,   1, 0x01, 0x00000001 },
-	{ 0x00c402,   1, 0x01, 0x00010001 },
-	{ 0x00c403,   2, 0x01, 0x00000001 },
-	{ 0x00c40e,   1, 0x01, 0x00000020 },
-	{ 0x00c500,   1, 0x01, 0x00000003 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000001 },
-	{ 0x000b07,   1, 0x01, 0x00000002 },
-	{ 0x000b08,   2, 0x01, 0x00000100 },
-	{ 0x000b0a,   1, 0x01, 0x00000001 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nv108_grctx_pack_icmd[] = {
-	{ nv108_grctx_init_icmd_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nv108_grctx_init_fe_0[] = {
-	{ 0x404004,   8, 0x04, 0x00000000 },
-	{ 0x404024,   1, 0x04, 0x0000e000 },
-	{ 0x404028,   8, 0x04, 0x00000000 },
-	{ 0x4040a8,   8, 0x04, 0x00000000 },
-	{ 0x4040c8,   1, 0x04, 0xf800008f },
-	{ 0x4040d0,   6, 0x04, 0x00000000 },
-	{ 0x4040e8,   1, 0x04, 0x00001000 },
-	{ 0x4040f8,   1, 0x04, 0x00000000 },
-	{ 0x404100,  10, 0x04, 0x00000000 },
-	{ 0x404130,   2, 0x04, 0x00000000 },
-	{ 0x404138,   1, 0x04, 0x20000040 },
-	{ 0x404150,   1, 0x04, 0x0000002e },
-	{ 0x404154,   1, 0x04, 0x00000400 },
-	{ 0x404158,   1, 0x04, 0x00000200 },
-	{ 0x404164,   1, 0x04, 0x00000055 },
-	{ 0x40417c,   2, 0x04, 0x00000000 },
-	{ 0x404194,   1, 0x04, 0x01000700 },
-	{ 0x4041a0,   4, 0x04, 0x00000000 },
-	{ 0x404200,   1, 0x04, 0x0000a197 },
-	{ 0x404204,   1, 0x04, 0x0000a1c0 },
-	{ 0x404208,   1, 0x04, 0x0000a140 },
-	{ 0x40420c,   1, 0x04, 0x0000902d },
-	{}
-};
-
-static const struct nvc0_graph_init
-nv108_grctx_init_ds_0[] = {
-	{ 0x405800,   1, 0x04, 0x0f8000bf },
-	{ 0x405830,   1, 0x04, 0x02180648 },
-	{ 0x405834,   1, 0x04, 0x08000000 },
-	{ 0x405838,   1, 0x04, 0x00000000 },
-	{ 0x405854,   1, 0x04, 0x00000000 },
-	{ 0x405870,   4, 0x04, 0x00000001 },
-	{ 0x405a00,   2, 0x04, 0x00000000 },
-	{ 0x405a18,   1, 0x04, 0x00000000 },
-	{ 0x405a1c,   1, 0x04, 0x000000ff },
-	{}
-};
-
-static const struct nvc0_graph_init
-nv108_grctx_init_pd_0[] = {
-	{ 0x406020,   1, 0x04, 0x034103c1 },
-	{ 0x406028,   4, 0x04, 0x00000001 },
-	{ 0x4064a8,   1, 0x04, 0x00000000 },
-	{ 0x4064ac,   1, 0x04, 0x00003fff },
-	{ 0x4064b0,   3, 0x04, 0x00000000 },
-	{ 0x4064c0,   1, 0x04, 0x802000f0 },
-	{ 0x4064c4,   1, 0x04, 0x0192ffff },
-	{ 0x4064c8,   1, 0x04, 0x00c20200 },
-	{ 0x4064cc,   9, 0x04, 0x00000000 },
-	{ 0x4064fc,   1, 0x04, 0x0000022a },
-	{}
-};
-
-const struct nvc0_graph_init
-nv108_grctx_init_rstr2d_0[] = {
-	{ 0x407804,   1, 0x04, 0x00000063 },
-	{ 0x40780c,   1, 0x04, 0x0a418820 },
-	{ 0x407810,   1, 0x04, 0x062080e6 },
-	{ 0x407814,   1, 0x04, 0x020398a4 },
-	{ 0x407818,   1, 0x04, 0x0e629062 },
-	{ 0x40781c,   1, 0x04, 0x0a418820 },
-	{ 0x407820,   1, 0x04, 0x000000e6 },
-	{ 0x4078bc,   1, 0x04, 0x00000103 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nv108_grctx_init_be_0[] = {
-	{ 0x408800,   1, 0x04, 0x32802a3c },
-	{ 0x408804,   1, 0x04, 0x00000040 },
-	{ 0x408808,   1, 0x04, 0x1003e005 },
-	{ 0x408840,   1, 0x04, 0x0000000b },
-	{ 0x408900,   1, 0x04, 0xb080b801 },
-	{ 0x408904,   1, 0x04, 0x62000001 },
-	{ 0x408908,   1, 0x04, 0x02c8102f },
-	{ 0x408980,   1, 0x04, 0x0000011d },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nv108_grctx_pack_hub[] = {
-	{ nvc0_grctx_init_main_0 },
-	{ nv108_grctx_init_fe_0 },
-	{ nvf0_grctx_init_pri_0 },
-	{ nve4_grctx_init_memfmt_0 },
-	{ nv108_grctx_init_ds_0 },
-	{ nvf0_grctx_init_cwd_0 },
-	{ nv108_grctx_init_pd_0 },
-	{ nv108_grctx_init_rstr2d_0 },
-	{ nve4_grctx_init_scc_0 },
-	{ nv108_grctx_init_be_0 },
-	{}
-};
-
-const struct nvc0_graph_init
-nv108_grctx_init_prop_0[] = {
-	{ 0x418400,   1, 0x04, 0x38005e00 },
-	{ 0x418404,   1, 0x04, 0x71e0ffff },
-	{ 0x41840c,   1, 0x04, 0x00001008 },
-	{ 0x418410,   1, 0x04, 0x0fff0fff },
-	{ 0x418414,   1, 0x04, 0x02200fff },
-	{ 0x418450,   6, 0x04, 0x00000000 },
-	{ 0x418468,   1, 0x04, 0x00000001 },
-	{ 0x41846c,   2, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nv108_grctx_init_gpc_unk_1[] = {
-	{ 0x418600,   1, 0x04, 0x0000007f },
-	{ 0x418684,   1, 0x04, 0x0000001f },
-	{ 0x418700,   1, 0x04, 0x00000002 },
-	{ 0x418704,   2, 0x04, 0x00000080 },
-	{ 0x41870c,   2, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nv108_grctx_init_setup_0[] = {
-	{ 0x418800,   1, 0x04, 0x7006863a },
-	{ 0x418808,   1, 0x04, 0x00000000 },
-	{ 0x41880c,   1, 0x04, 0x00000030 },
-	{ 0x418810,   1, 0x04, 0x00000000 },
-	{ 0x418828,   1, 0x04, 0x00000044 },
-	{ 0x418830,   1, 0x04, 0x10000001 },
-	{ 0x4188d8,   1, 0x04, 0x00000008 },
-	{ 0x4188e0,   1, 0x04, 0x01000000 },
-	{ 0x4188e8,   5, 0x04, 0x00000000 },
-	{ 0x4188fc,   1, 0x04, 0x20100058 },
-	{}
-};
-
-const struct nvc0_graph_init
-nv108_grctx_init_crstr_0[] = {
-	{ 0x418b00,   1, 0x04, 0x0000001e },
-	{ 0x418b08,   1, 0x04, 0x0a418820 },
-	{ 0x418b0c,   1, 0x04, 0x062080e6 },
-	{ 0x418b10,   1, 0x04, 0x020398a4 },
-	{ 0x418b14,   1, 0x04, 0x0e629062 },
-	{ 0x418b18,   1, 0x04, 0x0a418820 },
-	{ 0x418b1c,   1, 0x04, 0x000000e6 },
-	{ 0x418bb8,   1, 0x04, 0x00000103 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nv108_grctx_init_gpm_0[] = {
-	{ 0x418c08,   1, 0x04, 0x00000001 },
-	{ 0x418c10,   8, 0x04, 0x00000000 },
-	{ 0x418c40,   1, 0x04, 0xffffffff },
-	{ 0x418c6c,   1, 0x04, 0x00000001 },
-	{ 0x418c80,   1, 0x04, 0x2020000c },
-	{ 0x418c8c,   1, 0x04, 0x00000001 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nv108_grctx_pack_gpc[] = {
-	{ nvc0_grctx_init_gpc_unk_0 },
-	{ nv108_grctx_init_prop_0 },
-	{ nv108_grctx_init_gpc_unk_1 },
-	{ nv108_grctx_init_setup_0 },
-	{ nvc0_grctx_init_zcull_0 },
-	{ nv108_grctx_init_crstr_0 },
-	{ nv108_grctx_init_gpm_0 },
-	{ nvf0_grctx_init_gpc_unk_2 },
-	{ nvc0_grctx_init_gcc_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nv108_grctx_init_tex_0[] = {
-	{ 0x419a00,   1, 0x04, 0x000100f0 },
-	{ 0x419a04,   1, 0x04, 0x00000001 },
-	{ 0x419a08,   1, 0x04, 0x00000421 },
-	{ 0x419a0c,   1, 0x04, 0x00120000 },
-	{ 0x419a10,   1, 0x04, 0x00000000 },
-	{ 0x419a14,   1, 0x04, 0x00000200 },
-	{ 0x419a1c,   1, 0x04, 0x0000c000 },
-	{ 0x419a20,   1, 0x04, 0x00000800 },
-	{ 0x419a30,   1, 0x04, 0x00000001 },
-	{ 0x419ac4,   1, 0x04, 0x0037f440 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nv108_grctx_init_sm_0[] = {
-	{ 0x419e04,   1, 0x04, 0x00000000 },
-	{ 0x419e08,   1, 0x04, 0x0000001d },
-	{ 0x419e0c,   1, 0x04, 0x00000000 },
-	{ 0x419e10,   1, 0x04, 0x00001c02 },
-	{ 0x419e44,   1, 0x04, 0x0013eff2 },
-	{ 0x419e48,   1, 0x04, 0x00000000 },
-	{ 0x419e4c,   1, 0x04, 0x0000007f },
-	{ 0x419e50,   2, 0x04, 0x00000000 },
-	{ 0x419e58,   1, 0x04, 0x00000001 },
-	{ 0x419e5c,   3, 0x04, 0x00000000 },
-	{ 0x419e68,   1, 0x04, 0x00000002 },
-	{ 0x419e6c,  12, 0x04, 0x00000000 },
-	{ 0x419eac,   1, 0x04, 0x00001f8f },
-	{ 0x419eb0,   1, 0x04, 0x0db00d2f },
-	{ 0x419eb8,   1, 0x04, 0x00000000 },
-	{ 0x419ec8,   1, 0x04, 0x0001304f },
-	{ 0x419f30,   4, 0x04, 0x00000000 },
-	{ 0x419f40,   1, 0x04, 0x00000018 },
-	{ 0x419f44,   3, 0x04, 0x00000000 },
-	{ 0x419f58,   1, 0x04, 0x00000020 },
-	{ 0x419f70,   1, 0x04, 0x00000000 },
-	{ 0x419f78,   1, 0x04, 0x000001eb },
-	{ 0x419f7c,   1, 0x04, 0x00000404 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nv108_grctx_pack_tpc[] = {
-	{ nvd7_grctx_init_pe_0 },
-	{ nv108_grctx_init_tex_0 },
-	{ nvf0_grctx_init_mpc_0 },
-	{ nvf0_grctx_init_l1c_0 },
-	{ nv108_grctx_init_sm_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nv108_grctx_init_cbm_0[] = {
-	{ 0x41bec0,   1, 0x04, 0x10000000 },
-	{ 0x41bec4,   1, 0x04, 0x00037f7f },
-	{ 0x41bee4,   1, 0x04, 0x00000000 },
-	{ 0x41bef0,   1, 0x04, 0x000003ff },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nv108_grctx_pack_ppc[] = {
-	{ nve4_grctx_init_pes_0 },
-	{ nv108_grctx_init_cbm_0 },
-	{ nvd7_grctx_init_wwdx_0 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH context implementation
- ******************************************************************************/
-
-struct nouveau_oclass *
-nv108_grctx_oclass = &(struct nvc0_grctx_oclass) {
-	.base.handle = NV_ENGCTX(GR, 0x08),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-	.main  = nve4_grctx_generate_main,
-	.unkn  = nve4_grctx_generate_unkn,
-	.hub   = nv108_grctx_pack_hub,
-	.gpc   = nv108_grctx_pack_gpc,
-	.zcull = nvc0_grctx_pack_zcull,
-	.tpc   = nv108_grctx_pack_tpc,
-	.ppc   = nv108_grctx_pack_ppc,
-	.icmd  = nv108_grctx_pack_icmd,
-	.mthd  = nvf0_grctx_pack_mthd,
-	.bundle = nve4_grctx_generate_bundle,
-	.bundle_size = 0x3000,
-	.bundle_min_gpm_fifo_depth = 0xc2,
-	.bundle_token_limit = 0x200,
-	.pagepool = nve4_grctx_generate_pagepool,
-	.pagepool_size = 0x8000,
-	.attrib = nvd7_grctx_generate_attrib,
-	.attrib_nr_max = 0x324,
-	.attrib_nr = 0x218,
-	.alpha_nr_max = 0x7ff,
-	.alpha_nr = 0x648,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c
deleted file mode 100644
index 7bbb1e1b7a8d..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c
+++ /dev/null
@@ -1,695 +0,0 @@
-/*
- * Copyright 2009 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/gpuobj.h>
-
-/* NVIDIA context programs handle a number of other conditions which are
- * not implemented in our versions.  It's not clear why NVIDIA context
- * programs have this code, nor whether it's strictly necessary for
- * correct operation.  We'll implement additional handling if/when we
- * discover it's necessary.
- *
- * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state"
- *   flag is set, this gets saved into the context.
- * - On context save, the context program for all cards load nsource
- *   into a flag register and check for ILLEGAL_MTHD.  If it's set,
- *   opcode 0x60000d is called before resuming normal operation.
- * - Some context programs check more conditions than the above.  NV44
- *   checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001))
- *   and calls 0x60000d before resuming normal operation.
- * - At the very beginning of NVIDIA's context programs, flag 9 is checked
- *   and if true 0x800001 is called with count=0, pos=0, the flag is cleared
- *   and then the ctxprog is aborted.  It looks like a complicated NOP,
- *   its purpose is unknown.
- * - In the section of code that loads the per-vs state, NVIDIA check
- *   flag 10.  If it's set, they only transfer the small 0x300 byte block
- *   of state + the state for a single vs as opposed to the state for
- *   all vs units.  It doesn't seem likely that it'll occur in normal
- *   operation, especially seeing as it appears NVIDIA may have screwed
- *   up the ctxprogs for some cards and have an invalid instruction
- *   rather than a cp_lsr(ctx, dwords_for_1_vs_unit) instruction.
- * - There's a number of places where context offset 0 (where we place
- *   the PRAMIN offset of the context) is loaded into either 0x408000,
- *   0x408004 or 0x408008.  Not sure what's up there either.
- * - The ctxprogs for some cards save 0x400a00 again during the cleanup
- *   path for auto-loadctx.
- */
-
-#define CP_FLAG_CLEAR                 0
-#define CP_FLAG_SET                   1
-#define CP_FLAG_SWAP_DIRECTION        ((0 * 32) + 0)
-#define CP_FLAG_SWAP_DIRECTION_LOAD   0
-#define CP_FLAG_SWAP_DIRECTION_SAVE   1
-#define CP_FLAG_USER_SAVE             ((0 * 32) + 5)
-#define CP_FLAG_USER_SAVE_NOT_PENDING 0
-#define CP_FLAG_USER_SAVE_PENDING     1
-#define CP_FLAG_USER_LOAD             ((0 * 32) + 6)
-#define CP_FLAG_USER_LOAD_NOT_PENDING 0
-#define CP_FLAG_USER_LOAD_PENDING     1
-#define CP_FLAG_STATUS                ((3 * 32) + 0)
-#define CP_FLAG_STATUS_IDLE           0
-#define CP_FLAG_STATUS_BUSY           1
-#define CP_FLAG_AUTO_SAVE             ((3 * 32) + 4)
-#define CP_FLAG_AUTO_SAVE_NOT_PENDING 0
-#define CP_FLAG_AUTO_SAVE_PENDING     1
-#define CP_FLAG_AUTO_LOAD             ((3 * 32) + 5)
-#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0
-#define CP_FLAG_AUTO_LOAD_PENDING     1
-#define CP_FLAG_UNK54                 ((3 * 32) + 6)
-#define CP_FLAG_UNK54_CLEAR           0
-#define CP_FLAG_UNK54_SET             1
-#define CP_FLAG_ALWAYS                ((3 * 32) + 8)
-#define CP_FLAG_ALWAYS_FALSE          0
-#define CP_FLAG_ALWAYS_TRUE           1
-#define CP_FLAG_UNK57                 ((3 * 32) + 9)
-#define CP_FLAG_UNK57_CLEAR           0
-#define CP_FLAG_UNK57_SET             1
-
-#define CP_CTX                   0x00100000
-#define CP_CTX_COUNT             0x000fc000
-#define CP_CTX_COUNT_SHIFT               14
-#define CP_CTX_REG               0x00003fff
-#define CP_LOAD_SR               0x00200000
-#define CP_LOAD_SR_VALUE         0x000fffff
-#define CP_BRA                   0x00400000
-#define CP_BRA_IP                0x0000ff00
-#define CP_BRA_IP_SHIFT                   8
-#define CP_BRA_IF_CLEAR          0x00000080
-#define CP_BRA_FLAG              0x0000007f
-#define CP_WAIT                  0x00500000
-#define CP_WAIT_SET              0x00000080
-#define CP_WAIT_FLAG             0x0000007f
-#define CP_SET                   0x00700000
-#define CP_SET_1                 0x00000080
-#define CP_SET_FLAG              0x0000007f
-#define CP_NEXT_TO_SWAP          0x00600007
-#define CP_NEXT_TO_CURRENT       0x00600009
-#define CP_SET_CONTEXT_POINTER   0x0060000a
-#define CP_END                   0x0060000e
-#define CP_LOAD_MAGIC_UNK01      0x00800001 /* unknown */
-#define CP_LOAD_MAGIC_NV44TCL    0x00800029 /* per-vs state (0x4497) */
-#define CP_LOAD_MAGIC_NV40TCL    0x00800041 /* per-vs state (0x4097) */
-
-#include "nv40.h"
-#include "ctx.h"
-
-/* TODO:
- *  - get vs count from 0x1540
- */
-
-static int
-nv40_graph_vs_count(struct nouveau_device *device)
-{
-
-	switch (device->chipset) {
-	case 0x47:
-	case 0x49:
-	case 0x4b:
-		return 8;
-	case 0x40:
-		return 6;
-	case 0x41:
-	case 0x42:
-		return 5;
-	case 0x43:
-	case 0x44:
-	case 0x46:
-	case 0x4a:
-		return 3;
-	case 0x4c:
-	case 0x4e:
-	case 0x67:
-	default:
-		return 1;
-	}
-}
-
-
-enum cp_label {
-	cp_check_load = 1,
-	cp_setup_auto_load,
-	cp_setup_load,
-	cp_setup_save,
-	cp_swap_state,
-	cp_swap_state3d_3_is_save,
-	cp_prepare_exit,
-	cp_exit,
-};
-
-static void
-nv40_graph_construct_general(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	int i;
-
-	cp_ctx(ctx, 0x4000a4, 1);
-	gr_def(ctx, 0x4000a4, 0x00000008);
-	cp_ctx(ctx, 0x400144, 58);
-	gr_def(ctx, 0x400144, 0x00000001);
-	cp_ctx(ctx, 0x400314, 1);
-	gr_def(ctx, 0x400314, 0x00000000);
-	cp_ctx(ctx, 0x400400, 10);
-	cp_ctx(ctx, 0x400480, 10);
-	cp_ctx(ctx, 0x400500, 19);
-	gr_def(ctx, 0x400514, 0x00040000);
-	gr_def(ctx, 0x400524, 0x55555555);
-	gr_def(ctx, 0x400528, 0x55555555);
-	gr_def(ctx, 0x40052c, 0x55555555);
-	gr_def(ctx, 0x400530, 0x55555555);
-	cp_ctx(ctx, 0x400560, 6);
-	gr_def(ctx, 0x400568, 0x0000ffff);
-	gr_def(ctx, 0x40056c, 0x0000ffff);
-	cp_ctx(ctx, 0x40057c, 5);
-	cp_ctx(ctx, 0x400710, 3);
-	gr_def(ctx, 0x400710, 0x20010001);
-	gr_def(ctx, 0x400714, 0x0f73ef00);
-	cp_ctx(ctx, 0x400724, 1);
-	gr_def(ctx, 0x400724, 0x02008821);
-	cp_ctx(ctx, 0x400770, 3);
-	if (device->chipset == 0x40) {
-		cp_ctx(ctx, 0x400814, 4);
-		cp_ctx(ctx, 0x400828, 5);
-		cp_ctx(ctx, 0x400840, 5);
-		gr_def(ctx, 0x400850, 0x00000040);
-		cp_ctx(ctx, 0x400858, 4);
-		gr_def(ctx, 0x400858, 0x00000040);
-		gr_def(ctx, 0x40085c, 0x00000040);
-		gr_def(ctx, 0x400864, 0x80000000);
-		cp_ctx(ctx, 0x40086c, 9);
-		gr_def(ctx, 0x40086c, 0x80000000);
-		gr_def(ctx, 0x400870, 0x80000000);
-		gr_def(ctx, 0x400874, 0x80000000);
-		gr_def(ctx, 0x400878, 0x80000000);
-		gr_def(ctx, 0x400888, 0x00000040);
-		gr_def(ctx, 0x40088c, 0x80000000);
-		cp_ctx(ctx, 0x4009c0, 8);
-		gr_def(ctx, 0x4009cc, 0x80000000);
-		gr_def(ctx, 0x4009dc, 0x80000000);
-	} else {
-		cp_ctx(ctx, 0x400840, 20);
-		if (nv44_graph_class(ctx->device)) {
-			for (i = 0; i < 8; i++)
-				gr_def(ctx, 0x400860 + (i * 4), 0x00000001);
-		}
-		gr_def(ctx, 0x400880, 0x00000040);
-		gr_def(ctx, 0x400884, 0x00000040);
-		gr_def(ctx, 0x400888, 0x00000040);
-		cp_ctx(ctx, 0x400894, 11);
-		gr_def(ctx, 0x400894, 0x00000040);
-		if (!nv44_graph_class(ctx->device)) {
-			for (i = 0; i < 8; i++)
-				gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000);
-		}
-		cp_ctx(ctx, 0x4008e0, 2);
-		cp_ctx(ctx, 0x4008f8, 2);
-		if (device->chipset == 0x4c ||
-		    (device->chipset & 0xf0) == 0x60)
-			cp_ctx(ctx, 0x4009f8, 1);
-	}
-	cp_ctx(ctx, 0x400a00, 73);
-	gr_def(ctx, 0x400b0c, 0x0b0b0b0c);
-	cp_ctx(ctx, 0x401000, 4);
-	cp_ctx(ctx, 0x405004, 1);
-	switch (device->chipset) {
-	case 0x47:
-	case 0x49:
-	case 0x4b:
-		cp_ctx(ctx, 0x403448, 1);
-		gr_def(ctx, 0x403448, 0x00001010);
-		break;
-	default:
-		cp_ctx(ctx, 0x403440, 1);
-		switch (device->chipset) {
-		case 0x40:
-			gr_def(ctx, 0x403440, 0x00000010);
-			break;
-		case 0x44:
-		case 0x46:
-		case 0x4a:
-			gr_def(ctx, 0x403440, 0x00003010);
-			break;
-		case 0x41:
-		case 0x42:
-		case 0x43:
-		case 0x4c:
-		case 0x4e:
-		case 0x67:
-		default:
-			gr_def(ctx, 0x403440, 0x00001010);
-			break;
-		}
-		break;
-	}
-}
-
-static void
-nv40_graph_construct_state3d(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	int i;
-
-	if (device->chipset == 0x40) {
-		cp_ctx(ctx, 0x401880, 51);
-		gr_def(ctx, 0x401940, 0x00000100);
-	} else
-	if (device->chipset == 0x46 || device->chipset == 0x47 ||
-	    device->chipset == 0x49 || device->chipset == 0x4b) {
-		cp_ctx(ctx, 0x401880, 32);
-		for (i = 0; i < 16; i++)
-			gr_def(ctx, 0x401880 + (i * 4), 0x00000111);
-		if (device->chipset == 0x46)
-			cp_ctx(ctx, 0x401900, 16);
-		cp_ctx(ctx, 0x401940, 3);
-	}
-	cp_ctx(ctx, 0x40194c, 18);
-	gr_def(ctx, 0x401954, 0x00000111);
-	gr_def(ctx, 0x401958, 0x00080060);
-	gr_def(ctx, 0x401974, 0x00000080);
-	gr_def(ctx, 0x401978, 0xffff0000);
-	gr_def(ctx, 0x40197c, 0x00000001);
-	gr_def(ctx, 0x401990, 0x46400000);
-	if (device->chipset == 0x40) {
-		cp_ctx(ctx, 0x4019a0, 2);
-		cp_ctx(ctx, 0x4019ac, 5);
-	} else {
-		cp_ctx(ctx, 0x4019a0, 1);
-		cp_ctx(ctx, 0x4019b4, 3);
-	}
-	gr_def(ctx, 0x4019bc, 0xffff0000);
-	switch (device->chipset) {
-	case 0x46:
-	case 0x47:
-	case 0x49:
-	case 0x4b:
-		cp_ctx(ctx, 0x4019c0, 18);
-		for (i = 0; i < 16; i++)
-			gr_def(ctx, 0x4019c0 + (i * 4), 0x88888888);
-		break;
-	}
-	cp_ctx(ctx, 0x401a08, 8);
-	gr_def(ctx, 0x401a10, 0x0fff0000);
-	gr_def(ctx, 0x401a14, 0x0fff0000);
-	gr_def(ctx, 0x401a1c, 0x00011100);
-	cp_ctx(ctx, 0x401a2c, 4);
-	cp_ctx(ctx, 0x401a44, 26);
-	for (i = 0; i < 16; i++)
-		gr_def(ctx, 0x401a44 + (i * 4), 0x07ff0000);
-	gr_def(ctx, 0x401a8c, 0x4b7fffff);
-	if (device->chipset == 0x40) {
-		cp_ctx(ctx, 0x401ab8, 3);
-	} else {
-		cp_ctx(ctx, 0x401ab8, 1);
-		cp_ctx(ctx, 0x401ac0, 1);
-	}
-	cp_ctx(ctx, 0x401ad0, 8);
-	gr_def(ctx, 0x401ad0, 0x30201000);
-	gr_def(ctx, 0x401ad4, 0x70605040);
-	gr_def(ctx, 0x401ad8, 0xb8a89888);
-	gr_def(ctx, 0x401adc, 0xf8e8d8c8);
-	cp_ctx(ctx, 0x401b10, device->chipset == 0x40 ? 2 : 1);
-	gr_def(ctx, 0x401b10, 0x40100000);
-	cp_ctx(ctx, 0x401b18, device->chipset == 0x40 ? 6 : 5);
-	gr_def(ctx, 0x401b28, device->chipset == 0x40 ?
-			      0x00000004 : 0x00000000);
-	cp_ctx(ctx, 0x401b30, 25);
-	gr_def(ctx, 0x401b34, 0x0000ffff);
-	gr_def(ctx, 0x401b68, 0x435185d6);
-	gr_def(ctx, 0x401b6c, 0x2155b699);
-	gr_def(ctx, 0x401b70, 0xfedcba98);
-	gr_def(ctx, 0x401b74, 0x00000098);
-	gr_def(ctx, 0x401b84, 0xffffffff);
-	gr_def(ctx, 0x401b88, 0x00ff7000);
-	gr_def(ctx, 0x401b8c, 0x0000ffff);
-	if (device->chipset != 0x44 && device->chipset != 0x4a &&
-	    device->chipset != 0x4e)
-		cp_ctx(ctx, 0x401b94, 1);
-	cp_ctx(ctx, 0x401b98, 8);
-	gr_def(ctx, 0x401b9c, 0x00ff0000);
-	cp_ctx(ctx, 0x401bc0, 9);
-	gr_def(ctx, 0x401be0, 0x00ffff00);
-	cp_ctx(ctx, 0x401c00, 192);
-	for (i = 0; i < 16; i++) { /* fragment texture units */
-		gr_def(ctx, 0x401c40 + (i * 4), 0x00018488);
-		gr_def(ctx, 0x401c80 + (i * 4), 0x00028202);
-		gr_def(ctx, 0x401d00 + (i * 4), 0x0000aae4);
-		gr_def(ctx, 0x401d40 + (i * 4), 0x01012000);
-		gr_def(ctx, 0x401d80 + (i * 4), 0x00080008);
-		gr_def(ctx, 0x401e00 + (i * 4), 0x00100008);
-	}
-	for (i = 0; i < 4; i++) { /* vertex texture units */
-		gr_def(ctx, 0x401e90 + (i * 4), 0x0001bc80);
-		gr_def(ctx, 0x401ea0 + (i * 4), 0x00000202);
-		gr_def(ctx, 0x401ec0 + (i * 4), 0x00000008);
-		gr_def(ctx, 0x401ee0 + (i * 4), 0x00080008);
-	}
-	cp_ctx(ctx, 0x400f5c, 3);
-	gr_def(ctx, 0x400f5c, 0x00000002);
-	cp_ctx(ctx, 0x400f84, 1);
-}
-
-static void
-nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	int i;
-
-	cp_ctx(ctx, 0x402000, 1);
-	cp_ctx(ctx, 0x402404, device->chipset == 0x40 ? 1 : 2);
-	switch (device->chipset) {
-	case 0x40:
-		gr_def(ctx, 0x402404, 0x00000001);
-		break;
-	case 0x4c:
-	case 0x4e:
-	case 0x67:
-		gr_def(ctx, 0x402404, 0x00000020);
-		break;
-	case 0x46:
-	case 0x49:
-	case 0x4b:
-		gr_def(ctx, 0x402404, 0x00000421);
-		break;
-	default:
-		gr_def(ctx, 0x402404, 0x00000021);
-	}
-	if (device->chipset != 0x40)
-		gr_def(ctx, 0x402408, 0x030c30c3);
-	switch (device->chipset) {
-	case 0x44:
-	case 0x46:
-	case 0x4a:
-	case 0x4c:
-	case 0x4e:
-	case 0x67:
-		cp_ctx(ctx, 0x402440, 1);
-		gr_def(ctx, 0x402440, 0x00011001);
-		break;
-	default:
-		break;
-	}
-	cp_ctx(ctx, 0x402480, device->chipset == 0x40 ? 8 : 9);
-	gr_def(ctx, 0x402488, 0x3e020200);
-	gr_def(ctx, 0x40248c, 0x00ffffff);
-	switch (device->chipset) {
-	case 0x40:
-		gr_def(ctx, 0x402490, 0x60103f00);
-		break;
-	case 0x47:
-		gr_def(ctx, 0x402490, 0x40103f00);
-		break;
-	case 0x41:
-	case 0x42:
-	case 0x49:
-	case 0x4b:
-		gr_def(ctx, 0x402490, 0x20103f00);
-		break;
-	default:
-		gr_def(ctx, 0x402490, 0x0c103f00);
-		break;
-	}
-	gr_def(ctx, 0x40249c, device->chipset <= 0x43 ?
-			      0x00020000 : 0x00040000);
-	cp_ctx(ctx, 0x402500, 31);
-	gr_def(ctx, 0x402530, 0x00008100);
-	if (device->chipset == 0x40)
-		cp_ctx(ctx, 0x40257c, 6);
-	cp_ctx(ctx, 0x402594, 16);
-	cp_ctx(ctx, 0x402800, 17);
-	gr_def(ctx, 0x402800, 0x00000001);
-	switch (device->chipset) {
-	case 0x47:
-	case 0x49:
-	case 0x4b:
-		cp_ctx(ctx, 0x402864, 1);
-		gr_def(ctx, 0x402864, 0x00001001);
-		cp_ctx(ctx, 0x402870, 3);
-		gr_def(ctx, 0x402878, 0x00000003);
-		if (device->chipset != 0x47) { /* belong at end!! */
-			cp_ctx(ctx, 0x402900, 1);
-			cp_ctx(ctx, 0x402940, 1);
-			cp_ctx(ctx, 0x402980, 1);
-			cp_ctx(ctx, 0x4029c0, 1);
-			cp_ctx(ctx, 0x402a00, 1);
-			cp_ctx(ctx, 0x402a40, 1);
-			cp_ctx(ctx, 0x402a80, 1);
-			cp_ctx(ctx, 0x402ac0, 1);
-		}
-		break;
-	case 0x40:
-		cp_ctx(ctx, 0x402844, 1);
-		gr_def(ctx, 0x402844, 0x00000001);
-		cp_ctx(ctx, 0x402850, 1);
-		break;
-	default:
-		cp_ctx(ctx, 0x402844, 1);
-		gr_def(ctx, 0x402844, 0x00001001);
-		cp_ctx(ctx, 0x402850, 2);
-		gr_def(ctx, 0x402854, 0x00000003);
-		break;
-	}
-
-	cp_ctx(ctx, 0x402c00, 4);
-	gr_def(ctx, 0x402c00, device->chipset == 0x40 ?
-			      0x80800001 : 0x00888001);
-	switch (device->chipset) {
-	case 0x47:
-	case 0x49:
-	case 0x4b:
-		cp_ctx(ctx, 0x402c20, 40);
-		for (i = 0; i < 32; i++)
-			gr_def(ctx, 0x402c40 + (i * 4), 0xffffffff);
-		cp_ctx(ctx, 0x4030b8, 13);
-		gr_def(ctx, 0x4030dc, 0x00000005);
-		gr_def(ctx, 0x4030e8, 0x0000ffff);
-		break;
-	default:
-		cp_ctx(ctx, 0x402c10, 4);
-		if (device->chipset == 0x40)
-			cp_ctx(ctx, 0x402c20, 36);
-		else
-		if (device->chipset <= 0x42)
-			cp_ctx(ctx, 0x402c20, 24);
-		else
-		if (device->chipset <= 0x4a)
-			cp_ctx(ctx, 0x402c20, 16);
-		else
-			cp_ctx(ctx, 0x402c20, 8);
-		cp_ctx(ctx, 0x402cb0, device->chipset == 0x40 ? 12 : 13);
-		gr_def(ctx, 0x402cd4, 0x00000005);
-		if (device->chipset != 0x40)
-			gr_def(ctx, 0x402ce0, 0x0000ffff);
-		break;
-	}
-
-	cp_ctx(ctx, 0x403400, device->chipset == 0x40 ? 4 : 3);
-	cp_ctx(ctx, 0x403410, device->chipset == 0x40 ? 4 : 3);
-	cp_ctx(ctx, 0x403420, nv40_graph_vs_count(ctx->device));
-	for (i = 0; i < nv40_graph_vs_count(ctx->device); i++)
-		gr_def(ctx, 0x403420 + (i * 4), 0x00005555);
-
-	if (device->chipset != 0x40) {
-		cp_ctx(ctx, 0x403600, 1);
-		gr_def(ctx, 0x403600, 0x00000001);
-	}
-	cp_ctx(ctx, 0x403800, 1);
-
-	cp_ctx(ctx, 0x403c18, 1);
-	gr_def(ctx, 0x403c18, 0x00000001);
-	switch (device->chipset) {
-	case 0x46:
-	case 0x47:
-	case 0x49:
-	case 0x4b:
-		cp_ctx(ctx, 0x405018, 1);
-		gr_def(ctx, 0x405018, 0x08e00001);
-		cp_ctx(ctx, 0x405c24, 1);
-		gr_def(ctx, 0x405c24, 0x000e3000);
-		break;
-	}
-	if (device->chipset != 0x4e)
-		cp_ctx(ctx, 0x405800, 11);
-	cp_ctx(ctx, 0x407000, 1);
-}
-
-static void
-nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx)
-{
-	int len = nv44_graph_class(ctx->device) ? 0x0084 : 0x0684;
-
-	cp_out (ctx, 0x300000);
-	cp_lsr (ctx, len - 4);
-	cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_swap_state3d_3_is_save);
-	cp_lsr (ctx, len);
-	cp_name(ctx, cp_swap_state3d_3_is_save);
-	cp_out (ctx, 0x800001);
-
-	ctx->ctxvals_pos += len;
-}
-
-static void
-nv40_graph_construct_shader(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	struct nouveau_gpuobj *obj = ctx->data;
-	int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset;
-	int offset, i;
-
-	vs_nr    = nv40_graph_vs_count(ctx->device);
-	vs_nr_b0 = 363;
-	vs_nr_b1 = device->chipset == 0x40 ? 128 : 64;
-	if (device->chipset == 0x40) {
-		b0_offset = 0x2200/4; /* 33a0 */
-		b1_offset = 0x55a0/4; /* 1500 */
-		vs_len = 0x6aa0/4;
-	} else
-	if (device->chipset == 0x41 || device->chipset == 0x42) {
-		b0_offset = 0x2200/4; /* 2200 */
-		b1_offset = 0x4400/4; /* 0b00 */
-		vs_len = 0x4f00/4;
-	} else {
-		b0_offset = 0x1d40/4; /* 2200 */
-		b1_offset = 0x3f40/4; /* 0b00 : 0a40 */
-		vs_len = nv44_graph_class(device) ? 0x4980/4 : 0x4a40/4;
-	}
-
-	cp_lsr(ctx, vs_len * vs_nr + 0x300/4);
-	cp_out(ctx, nv44_graph_class(device) ? 0x800029 : 0x800041);
-
-	offset = ctx->ctxvals_pos;
-	ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len));
-
-	if (ctx->mode != NOUVEAU_GRCTX_VALS)
-		return;
-
-	offset += 0x0280/4;
-	for (i = 0; i < 16; i++, offset += 2)
-		nv_wo32(obj, offset * 4, 0x3f800000);
-
-	for (vs = 0; vs < vs_nr; vs++, offset += vs_len) {
-		for (i = 0; i < vs_nr_b0 * 6; i += 6)
-			nv_wo32(obj, (offset + b0_offset + i) * 4, 0x00000001);
-		for (i = 0; i < vs_nr_b1 * 4; i += 4)
-			nv_wo32(obj, (offset + b1_offset + i) * 4, 0x3f800000);
-	}
-}
-
-static void
-nv40_grctx_generate(struct nouveau_grctx *ctx)
-{
-	/* decide whether we're loading/unloading the context */
-	cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);
-	cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save);
-
-	cp_name(ctx, cp_check_load);
-	cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load);
-	cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load);
-	cp_bra (ctx, ALWAYS, TRUE, cp_exit);
-
-	/* setup for context load */
-	cp_name(ctx, cp_setup_auto_load);
-	cp_wait(ctx, STATUS, IDLE);
-	cp_out (ctx, CP_NEXT_TO_SWAP);
-	cp_name(ctx, cp_setup_load);
-	cp_wait(ctx, STATUS, IDLE);
-	cp_set (ctx, SWAP_DIRECTION, LOAD);
-	cp_out (ctx, 0x00910880); /* ?? */
-	cp_out (ctx, 0x00901ffe); /* ?? */
-	cp_out (ctx, 0x01940000); /* ?? */
-	cp_lsr (ctx, 0x20);
-	cp_out (ctx, 0x0060000b); /* ?? */
-	cp_wait(ctx, UNK57, CLEAR);
-	cp_out (ctx, 0x0060000c); /* ?? */
-	cp_bra (ctx, ALWAYS, TRUE, cp_swap_state);
-
-	/* setup for context save */
-	cp_name(ctx, cp_setup_save);
-	cp_set (ctx, SWAP_DIRECTION, SAVE);
-
-	/* general PGRAPH state */
-	cp_name(ctx, cp_swap_state);
-	cp_pos (ctx, 0x00020/4);
-	nv40_graph_construct_general(ctx);
-	cp_wait(ctx, STATUS, IDLE);
-
-	/* 3D state, block 1 */
-	cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit);
-	nv40_graph_construct_state3d(ctx);
-	cp_wait(ctx, STATUS, IDLE);
-
-	/* 3D state, block 2 */
-	nv40_graph_construct_state3d_2(ctx);
-
-	/* Some other block of "random" state */
-	nv40_graph_construct_state3d_3(ctx);
-
-	/* Per-vertex shader state */
-	cp_pos (ctx, ctx->ctxvals_pos);
-	nv40_graph_construct_shader(ctx);
-
-	/* pre-exit state updates */
-	cp_name(ctx, cp_prepare_exit);
-	cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load);
-	cp_bra (ctx, USER_SAVE, PENDING, cp_exit);
-	cp_out (ctx, CP_NEXT_TO_CURRENT);
-
-	cp_name(ctx, cp_exit);
-	cp_set (ctx, USER_SAVE, NOT_PENDING);
-	cp_set (ctx, USER_LOAD, NOT_PENDING);
-	cp_out (ctx, CP_END);
-}
-
-void
-nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem)
-{
-	nv40_grctx_generate(&(struct nouveau_grctx) {
-			     .device = device,
-			     .mode = NOUVEAU_GRCTX_VALS,
-			     .data = mem,
-			   });
-}
-
-int
-nv40_grctx_init(struct nouveau_device *device, u32 *size)
-{
-	u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i;
-	struct nouveau_grctx ctx = {
-		.device = device,
-		.mode = NOUVEAU_GRCTX_PROG,
-		.data = ctxprog,
-		.ctxprog_max = 256,
-	};
-
-	if (!ctxprog)
-		return -ENOMEM;
-
-	nv40_grctx_generate(&ctx);
-
-	nv_wr32(device, 0x400324, 0);
-	for (i = 0; i < ctx.ctxprog_len; i++)
-		nv_wr32(device, 0x400328, ctxprog[i]);
-	*size = ctx.ctxvals_pos * 4;
-
-	kfree(ctxprog);
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv50.c
deleted file mode 100644
index 1d0e33fb5f61..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv50.c
+++ /dev/null
@@ -1,3347 +0,0 @@
-/*
- * Copyright 2009 Marcin Kościelnicki
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <core/gpuobj.h>
-
-#define CP_FLAG_CLEAR                 0
-#define CP_FLAG_SET                   1
-#define CP_FLAG_SWAP_DIRECTION        ((0 * 32) + 0)
-#define CP_FLAG_SWAP_DIRECTION_LOAD   0
-#define CP_FLAG_SWAP_DIRECTION_SAVE   1
-#define CP_FLAG_UNK01                 ((0 * 32) + 1)
-#define CP_FLAG_UNK01_CLEAR           0
-#define CP_FLAG_UNK01_SET             1
-#define CP_FLAG_UNK03                 ((0 * 32) + 3)
-#define CP_FLAG_UNK03_CLEAR           0
-#define CP_FLAG_UNK03_SET             1
-#define CP_FLAG_USER_SAVE             ((0 * 32) + 5)
-#define CP_FLAG_USER_SAVE_NOT_PENDING 0
-#define CP_FLAG_USER_SAVE_PENDING     1
-#define CP_FLAG_USER_LOAD             ((0 * 32) + 6)
-#define CP_FLAG_USER_LOAD_NOT_PENDING 0
-#define CP_FLAG_USER_LOAD_PENDING     1
-#define CP_FLAG_UNK0B                 ((0 * 32) + 0xb)
-#define CP_FLAG_UNK0B_CLEAR           0
-#define CP_FLAG_UNK0B_SET             1
-#define CP_FLAG_XFER_SWITCH           ((0 * 32) + 0xe)
-#define CP_FLAG_XFER_SWITCH_DISABLE   0
-#define CP_FLAG_XFER_SWITCH_ENABLE    1
-#define CP_FLAG_STATE                 ((0 * 32) + 0x1c)
-#define CP_FLAG_STATE_STOPPED         0
-#define CP_FLAG_STATE_RUNNING         1
-#define CP_FLAG_UNK1D                 ((0 * 32) + 0x1d)
-#define CP_FLAG_UNK1D_CLEAR           0
-#define CP_FLAG_UNK1D_SET             1
-#define CP_FLAG_UNK20                 ((1 * 32) + 0)
-#define CP_FLAG_UNK20_CLEAR           0
-#define CP_FLAG_UNK20_SET             1
-#define CP_FLAG_STATUS                ((2 * 32) + 0)
-#define CP_FLAG_STATUS_BUSY           0
-#define CP_FLAG_STATUS_IDLE           1
-#define CP_FLAG_AUTO_SAVE             ((2 * 32) + 4)
-#define CP_FLAG_AUTO_SAVE_NOT_PENDING 0
-#define CP_FLAG_AUTO_SAVE_PENDING     1
-#define CP_FLAG_AUTO_LOAD             ((2 * 32) + 5)
-#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0
-#define CP_FLAG_AUTO_LOAD_PENDING     1
-#define CP_FLAG_NEWCTX                ((2 * 32) + 10)
-#define CP_FLAG_NEWCTX_BUSY           0
-#define CP_FLAG_NEWCTX_DONE           1
-#define CP_FLAG_XFER                  ((2 * 32) + 11)
-#define CP_FLAG_XFER_IDLE             0
-#define CP_FLAG_XFER_BUSY             1
-#define CP_FLAG_ALWAYS                ((2 * 32) + 13)
-#define CP_FLAG_ALWAYS_FALSE          0
-#define CP_FLAG_ALWAYS_TRUE           1
-#define CP_FLAG_INTR                  ((2 * 32) + 15)
-#define CP_FLAG_INTR_NOT_PENDING      0
-#define CP_FLAG_INTR_PENDING          1
-
-#define CP_CTX                   0x00100000
-#define CP_CTX_COUNT             0x000f0000
-#define CP_CTX_COUNT_SHIFT               16
-#define CP_CTX_REG               0x00003fff
-#define CP_LOAD_SR               0x00200000
-#define CP_LOAD_SR_VALUE         0x000fffff
-#define CP_BRA                   0x00400000
-#define CP_BRA_IP                0x0001ff00
-#define CP_BRA_IP_SHIFT                   8
-#define CP_BRA_IF_CLEAR          0x00000080
-#define CP_BRA_FLAG              0x0000007f
-#define CP_WAIT                  0x00500000
-#define CP_WAIT_SET              0x00000080
-#define CP_WAIT_FLAG             0x0000007f
-#define CP_SET                   0x00700000
-#define CP_SET_1                 0x00000080
-#define CP_SET_FLAG              0x0000007f
-#define CP_NEWCTX                0x00600004
-#define CP_NEXT_TO_SWAP          0x00600005
-#define CP_SET_CONTEXT_POINTER   0x00600006
-#define CP_SET_XFER_POINTER      0x00600007
-#define CP_ENABLE                0x00600009
-#define CP_END                   0x0060000c
-#define CP_NEXT_TO_CURRENT       0x0060000d
-#define CP_DISABLE1              0x0090ffff
-#define CP_DISABLE2              0x0091ffff
-#define CP_XFER_1      0x008000ff
-#define CP_XFER_2      0x008800ff
-#define CP_SEEK_1      0x00c000ff
-#define CP_SEEK_2      0x00c800ff
-
-#include "nv50.h"
-#include "ctx.h"
-
-#define IS_NVA3F(x) (((x) > 0xa0 && (x) < 0xaa) || (x) == 0xaf)
-#define IS_NVAAF(x) ((x) >= 0xaa && (x) <= 0xac)
-
-#include <subdev/fb.h>
-
-/*
- * This code deals with PGRAPH contexts on NV50 family cards. Like NV40, it's
- * the GPU itself that does context-switching, but it needs a special
- * microcode to do it. And it's the driver's task to supply this microcode,
- * further known as ctxprog, as well as the initial context values, known
- * as ctxvals.
- *
- * Without ctxprog, you cannot switch contexts. Not even in software, since
- * the majority of context [xfer strands] isn't accessible directly. You're
- * stuck with a single channel, and you also suffer all the problems resulting
- * from missing ctxvals, since you cannot load them.
- *
- * Without ctxvals, you're stuck with PGRAPH's default context. It's enough to
- * run 2d operations, but trying to utilise 3d or CUDA will just lock you up,
- * since you don't have... some sort of needed setup.
- *
- * Nouveau will just disable acceleration if not given ctxprog + ctxvals, since
- * it's too much hassle to handle no-ctxprog as a special case.
- */
-
-/*
- * How ctxprogs work.
- *
- * The ctxprog is written in its own kind of microcode, with very small and
- * crappy set of available commands. You upload it to a small [512 insns]
- * area of memory on PGRAPH, and it'll be run when PFIFO wants PGRAPH to
- * switch channel. or when the driver explicitely requests it. Stuff visible
- * to ctxprog consists of: PGRAPH MMIO registers, PGRAPH context strands,
- * the per-channel context save area in VRAM [known as ctxvals or grctx],
- * 4 flags registers, a scratch register, two grctx pointers, plus many
- * random poorly-understood details.
- *
- * When ctxprog runs, it's supposed to check what operations are asked of it,
- * save old context if requested, optionally reset PGRAPH and switch to the
- * new channel, and load the new context. Context consists of three major
- * parts: subset of MMIO registers and two "xfer areas".
- */
-
-/* TODO:
- *  - document unimplemented bits compared to nvidia
- *  - NVAx: make a TP subroutine, use it.
- *  - use 0x4008fc instead of 0x1540?
- */
-
-enum cp_label {
-	cp_check_load = 1,
-	cp_setup_auto_load,
-	cp_setup_load,
-	cp_setup_save,
-	cp_swap_state,
-	cp_prepare_exit,
-	cp_exit,
-};
-
-static void nv50_graph_construct_mmio(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_xfer1(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_xfer2(struct nouveau_grctx *ctx);
-
-/* Main function: construct the ctxprog skeleton, call the other functions. */
-
-static int
-nv50_grctx_generate(struct nouveau_grctx *ctx)
-{
-	cp_set (ctx, STATE, RUNNING);
-	cp_set (ctx, XFER_SWITCH, ENABLE);
-	/* decide whether we're loading/unloading the context */
-	cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);
-	cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save);
-
-	cp_name(ctx, cp_check_load);
-	cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load);
-	cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load);
-	cp_bra (ctx, ALWAYS, TRUE, cp_prepare_exit);
-
-	/* setup for context load */
-	cp_name(ctx, cp_setup_auto_load);
-	cp_out (ctx, CP_DISABLE1);
-	cp_out (ctx, CP_DISABLE2);
-	cp_out (ctx, CP_ENABLE);
-	cp_out (ctx, CP_NEXT_TO_SWAP);
-	cp_set (ctx, UNK01, SET);
-	cp_name(ctx, cp_setup_load);
-	cp_out (ctx, CP_NEWCTX);
-	cp_wait(ctx, NEWCTX, BUSY);
-	cp_set (ctx, UNK1D, CLEAR);
-	cp_set (ctx, SWAP_DIRECTION, LOAD);
-	cp_bra (ctx, UNK0B, SET, cp_prepare_exit);
-	cp_bra (ctx, ALWAYS, TRUE, cp_swap_state);
-
-	/* setup for context save */
-	cp_name(ctx, cp_setup_save);
-	cp_set (ctx, UNK1D, SET);
-	cp_wait(ctx, STATUS, BUSY);
-	cp_wait(ctx, INTR, PENDING);
-	cp_bra (ctx, STATUS, BUSY, cp_setup_save);
-	cp_set (ctx, UNK01, SET);
-	cp_set (ctx, SWAP_DIRECTION, SAVE);
-
-	/* general PGRAPH state */
-	cp_name(ctx, cp_swap_state);
-	cp_set (ctx, UNK03, SET);
-	cp_pos (ctx, 0x00004/4);
-	cp_ctx (ctx, 0x400828, 1); /* needed. otherwise, flickering happens. */
-	cp_pos (ctx, 0x00100/4);
-	nv50_graph_construct_mmio(ctx);
-	nv50_graph_construct_xfer1(ctx);
-	nv50_graph_construct_xfer2(ctx);
-
-	cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load);
-
-	cp_set (ctx, UNK20, SET);
-	cp_set (ctx, SWAP_DIRECTION, SAVE); /* no idea why this is needed, but fixes at least one lockup. */
-	cp_lsr (ctx, ctx->ctxvals_base);
-	cp_out (ctx, CP_SET_XFER_POINTER);
-	cp_lsr (ctx, 4);
-	cp_out (ctx, CP_SEEK_1);
-	cp_out (ctx, CP_XFER_1);
-	cp_wait(ctx, XFER, BUSY);
-
-	/* pre-exit state updates */
-	cp_name(ctx, cp_prepare_exit);
-	cp_set (ctx, UNK01, CLEAR);
-	cp_set (ctx, UNK03, CLEAR);
-	cp_set (ctx, UNK1D, CLEAR);
-
-	cp_bra (ctx, USER_SAVE, PENDING, cp_exit);
-	cp_out (ctx, CP_NEXT_TO_CURRENT);
-
-	cp_name(ctx, cp_exit);
-	cp_set (ctx, USER_SAVE, NOT_PENDING);
-	cp_set (ctx, USER_LOAD, NOT_PENDING);
-	cp_set (ctx, XFER_SWITCH, DISABLE);
-	cp_set (ctx, STATE, STOPPED);
-	cp_out (ctx, CP_END);
-	ctx->ctxvals_pos += 0x400; /* padding... no idea why you need it */
-
-	return 0;
-}
-
-void
-nv50_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem)
-{
-	nv50_grctx_generate(&(struct nouveau_grctx) {
-			     .device = device,
-			     .mode = NOUVEAU_GRCTX_VALS,
-			     .data = mem,
-			   });
-}
-
-int
-nv50_grctx_init(struct nouveau_device *device, u32 *size)
-{
-	u32 *ctxprog = kmalloc(512 * 4, GFP_KERNEL), i;
-	struct nouveau_grctx ctx = {
-		.device = device,
-		.mode = NOUVEAU_GRCTX_PROG,
-		.data = ctxprog,
-		.ctxprog_max = 512,
-	};
-
-	if (!ctxprog)
-		return -ENOMEM;
-	nv50_grctx_generate(&ctx);
-
-	nv_wr32(device, 0x400324, 0);
-	for (i = 0; i < ctx.ctxprog_len; i++)
-		nv_wr32(device, 0x400328, ctxprog[i]);
-	*size = ctx.ctxvals_pos * 4;
-	kfree(ctxprog);
-	return 0;
-}
-
-/*
- * Constructs MMIO part of ctxprog and ctxvals. Just a matter of knowing which
- * registers to save/restore and the default values for them.
- */
-
-static void
-nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx);
-
-static void
-nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	int i, j;
-	int offset, base;
-	u32 units = nv_rd32 (ctx->device, 0x1540);
-
-	/* 0800: DISPATCH */
-	cp_ctx(ctx, 0x400808, 7);
-	gr_def(ctx, 0x400814, 0x00000030);
-	cp_ctx(ctx, 0x400834, 0x32);
-	if (device->chipset == 0x50) {
-		gr_def(ctx, 0x400834, 0xff400040);
-		gr_def(ctx, 0x400838, 0xfff00080);
-		gr_def(ctx, 0x40083c, 0xfff70090);
-		gr_def(ctx, 0x400840, 0xffe806a8);
-	}
-	gr_def(ctx, 0x400844, 0x00000002);
-	if (IS_NVA3F(device->chipset))
-		gr_def(ctx, 0x400894, 0x00001000);
-	gr_def(ctx, 0x4008e8, 0x00000003);
-	gr_def(ctx, 0x4008ec, 0x00001000);
-	if (device->chipset == 0x50)
-		cp_ctx(ctx, 0x400908, 0xb);
-	else if (device->chipset < 0xa0)
-		cp_ctx(ctx, 0x400908, 0xc);
-	else
-		cp_ctx(ctx, 0x400908, 0xe);
-
-	if (device->chipset >= 0xa0)
-		cp_ctx(ctx, 0x400b00, 0x1);
-	if (IS_NVA3F(device->chipset)) {
-		cp_ctx(ctx, 0x400b10, 0x1);
-		gr_def(ctx, 0x400b10, 0x0001629d);
-		cp_ctx(ctx, 0x400b20, 0x1);
-		gr_def(ctx, 0x400b20, 0x0001629d);
-	}
-
-	nv50_graph_construct_mmio_ddata(ctx);
-
-	/* 0C00: VFETCH */
-	cp_ctx(ctx, 0x400c08, 0x2);
-	gr_def(ctx, 0x400c08, 0x0000fe0c);
-
-	/* 1000 */
-	if (device->chipset < 0xa0) {
-		cp_ctx(ctx, 0x401008, 0x4);
-		gr_def(ctx, 0x401014, 0x00001000);
-	} else if (!IS_NVA3F(device->chipset)) {
-		cp_ctx(ctx, 0x401008, 0x5);
-		gr_def(ctx, 0x401018, 0x00001000);
-	} else {
-		cp_ctx(ctx, 0x401008, 0x5);
-		gr_def(ctx, 0x401018, 0x00004000);
-	}
-
-	/* 1400 */
-	cp_ctx(ctx, 0x401400, 0x8);
-	cp_ctx(ctx, 0x401424, 0x3);
-	if (device->chipset == 0x50)
-		gr_def(ctx, 0x40142c, 0x0001fd87);
-	else
-		gr_def(ctx, 0x40142c, 0x00000187);
-	cp_ctx(ctx, 0x401540, 0x5);
-	gr_def(ctx, 0x401550, 0x00001018);
-
-	/* 1800: STREAMOUT */
-	cp_ctx(ctx, 0x401814, 0x1);
-	gr_def(ctx, 0x401814, 0x000000ff);
-	if (device->chipset == 0x50) {
-		cp_ctx(ctx, 0x40181c, 0xe);
-		gr_def(ctx, 0x401850, 0x00000004);
-	} else if (device->chipset < 0xa0) {
-		cp_ctx(ctx, 0x40181c, 0xf);
-		gr_def(ctx, 0x401854, 0x00000004);
-	} else {
-		cp_ctx(ctx, 0x40181c, 0x13);
-		gr_def(ctx, 0x401864, 0x00000004);
-	}
-
-	/* 1C00 */
-	cp_ctx(ctx, 0x401c00, 0x1);
-	switch (device->chipset) {
-	case 0x50:
-		gr_def(ctx, 0x401c00, 0x0001005f);
-		break;
-	case 0x84:
-	case 0x86:
-	case 0x94:
-		gr_def(ctx, 0x401c00, 0x044d00df);
-		break;
-	case 0x92:
-	case 0x96:
-	case 0x98:
-	case 0xa0:
-	case 0xaa:
-	case 0xac:
-		gr_def(ctx, 0x401c00, 0x042500df);
-		break;
-	case 0xa3:
-	case 0xa5:
-	case 0xa8:
-	case 0xaf:
-		gr_def(ctx, 0x401c00, 0x142500df);
-		break;
-	}
-
-	/* 2000 */
-
-	/* 2400 */
-	cp_ctx(ctx, 0x402400, 0x1);
-	if (device->chipset == 0x50)
-		cp_ctx(ctx, 0x402408, 0x1);
-	else
-		cp_ctx(ctx, 0x402408, 0x2);
-	gr_def(ctx, 0x402408, 0x00000600);
-
-	/* 2800: CSCHED */
-	cp_ctx(ctx, 0x402800, 0x1);
-	if (device->chipset == 0x50)
-		gr_def(ctx, 0x402800, 0x00000006);
-
-	/* 2C00: ZCULL */
-	cp_ctx(ctx, 0x402c08, 0x6);
-	if (device->chipset != 0x50)
-		gr_def(ctx, 0x402c14, 0x01000000);
-	gr_def(ctx, 0x402c18, 0x000000ff);
-	if (device->chipset == 0x50)
-		cp_ctx(ctx, 0x402ca0, 0x1);
-	else
-		cp_ctx(ctx, 0x402ca0, 0x2);
-	if (device->chipset < 0xa0)
-		gr_def(ctx, 0x402ca0, 0x00000400);
-	else if (!IS_NVA3F(device->chipset))
-		gr_def(ctx, 0x402ca0, 0x00000800);
-	else
-		gr_def(ctx, 0x402ca0, 0x00000400);
-	cp_ctx(ctx, 0x402cac, 0x4);
-
-	/* 3000: ENG2D */
-	cp_ctx(ctx, 0x403004, 0x1);
-	gr_def(ctx, 0x403004, 0x00000001);
-
-	/* 3400 */
-	if (device->chipset >= 0xa0) {
-		cp_ctx(ctx, 0x403404, 0x1);
-		gr_def(ctx, 0x403404, 0x00000001);
-	}
-
-	/* 5000: CCACHE */
-	cp_ctx(ctx, 0x405000, 0x1);
-	switch (device->chipset) {
-	case 0x50:
-		gr_def(ctx, 0x405000, 0x00300080);
-		break;
-	case 0x84:
-	case 0xa0:
-	case 0xa3:
-	case 0xa5:
-	case 0xa8:
-	case 0xaa:
-	case 0xac:
-	case 0xaf:
-		gr_def(ctx, 0x405000, 0x000e0080);
-		break;
-	case 0x86:
-	case 0x92:
-	case 0x94:
-	case 0x96:
-	case 0x98:
-		gr_def(ctx, 0x405000, 0x00000080);
-		break;
-	}
-	cp_ctx(ctx, 0x405014, 0x1);
-	gr_def(ctx, 0x405014, 0x00000004);
-	cp_ctx(ctx, 0x40501c, 0x1);
-	cp_ctx(ctx, 0x405024, 0x1);
-	cp_ctx(ctx, 0x40502c, 0x1);
-
-	/* 6000? */
-	if (device->chipset == 0x50)
-		cp_ctx(ctx, 0x4063e0, 0x1);
-
-	/* 6800: M2MF */
-	if (device->chipset < 0x90) {
-		cp_ctx(ctx, 0x406814, 0x2b);
-		gr_def(ctx, 0x406818, 0x00000f80);
-		gr_def(ctx, 0x406860, 0x007f0080);
-		gr_def(ctx, 0x40689c, 0x007f0080);
-	} else {
-		cp_ctx(ctx, 0x406814, 0x4);
-		if (device->chipset == 0x98)
-			gr_def(ctx, 0x406818, 0x00000f80);
-		else
-			gr_def(ctx, 0x406818, 0x00001f80);
-		if (IS_NVA3F(device->chipset))
-			gr_def(ctx, 0x40681c, 0x00000030);
-		cp_ctx(ctx, 0x406830, 0x3);
-	}
-
-	/* 7000: per-ROP group state */
-	for (i = 0; i < 8; i++) {
-		if (units & (1<<(i+16))) {
-			cp_ctx(ctx, 0x407000 + (i<<8), 3);
-			if (device->chipset == 0x50)
-				gr_def(ctx, 0x407000 + (i<<8), 0x1b74f820);
-			else if (device->chipset != 0xa5)
-				gr_def(ctx, 0x407000 + (i<<8), 0x3b74f821);
-			else
-				gr_def(ctx, 0x407000 + (i<<8), 0x7b74f821);
-			gr_def(ctx, 0x407004 + (i<<8), 0x89058001);
-
-			if (device->chipset == 0x50) {
-				cp_ctx(ctx, 0x407010 + (i<<8), 1);
-			} else if (device->chipset < 0xa0) {
-				cp_ctx(ctx, 0x407010 + (i<<8), 2);
-				gr_def(ctx, 0x407010 + (i<<8), 0x00001000);
-				gr_def(ctx, 0x407014 + (i<<8), 0x0000001f);
-			} else {
-				cp_ctx(ctx, 0x407010 + (i<<8), 3);
-				gr_def(ctx, 0x407010 + (i<<8), 0x00001000);
-				if (device->chipset != 0xa5)
-					gr_def(ctx, 0x407014 + (i<<8), 0x000000ff);
-				else
-					gr_def(ctx, 0x407014 + (i<<8), 0x000001ff);
-			}
-
-			cp_ctx(ctx, 0x407080 + (i<<8), 4);
-			if (device->chipset != 0xa5)
-				gr_def(ctx, 0x407080 + (i<<8), 0x027c10fa);
-			else
-				gr_def(ctx, 0x407080 + (i<<8), 0x827c10fa);
-			if (device->chipset == 0x50)
-				gr_def(ctx, 0x407084 + (i<<8), 0x000000c0);
-			else
-				gr_def(ctx, 0x407084 + (i<<8), 0x400000c0);
-			gr_def(ctx, 0x407088 + (i<<8), 0xb7892080);
-
-			if (device->chipset < 0xa0)
-				cp_ctx(ctx, 0x407094 + (i<<8), 1);
-			else if (!IS_NVA3F(device->chipset))
-				cp_ctx(ctx, 0x407094 + (i<<8), 3);
-			else {
-				cp_ctx(ctx, 0x407094 + (i<<8), 4);
-				gr_def(ctx, 0x4070a0 + (i<<8), 1);
-			}
-		}
-	}
-
-	cp_ctx(ctx, 0x407c00, 0x3);
-	if (device->chipset < 0x90)
-		gr_def(ctx, 0x407c00, 0x00010040);
-	else if (device->chipset < 0xa0)
-		gr_def(ctx, 0x407c00, 0x00390040);
-	else
-		gr_def(ctx, 0x407c00, 0x003d0040);
-	gr_def(ctx, 0x407c08, 0x00000022);
-	if (device->chipset >= 0xa0) {
-		cp_ctx(ctx, 0x407c10, 0x3);
-		cp_ctx(ctx, 0x407c20, 0x1);
-		cp_ctx(ctx, 0x407c2c, 0x1);
-	}
-
-	if (device->chipset < 0xa0) {
-		cp_ctx(ctx, 0x407d00, 0x9);
-	} else {
-		cp_ctx(ctx, 0x407d00, 0x15);
-	}
-	if (device->chipset == 0x98)
-		gr_def(ctx, 0x407d08, 0x00380040);
-	else {
-		if (device->chipset < 0x90)
-			gr_def(ctx, 0x407d08, 0x00010040);
-		else if (device->chipset < 0xa0)
-			gr_def(ctx, 0x407d08, 0x00390040);
-		else {
-			if (nouveau_fb(device)->ram->type != NV_MEM_TYPE_GDDR5)
-				gr_def(ctx, 0x407d08, 0x003d0040);
-			else
-				gr_def(ctx, 0x407d08, 0x003c0040);
-		}
-		gr_def(ctx, 0x407d0c, 0x00000022);
-	}
-
-	/* 8000+: per-TP state */
-	for (i = 0; i < 10; i++) {
-		if (units & (1<<i)) {
-			if (device->chipset < 0xa0)
-				base = 0x408000 + (i<<12);
-			else
-				base = 0x408000 + (i<<11);
-			if (device->chipset < 0xa0)
-				offset = base + 0xc00;
-			else
-				offset = base + 0x80;
-			cp_ctx(ctx, offset + 0x00, 1);
-			gr_def(ctx, offset + 0x00, 0x0000ff0a);
-			cp_ctx(ctx, offset + 0x08, 1);
-
-			/* per-MP state */
-			for (j = 0; j < (device->chipset < 0xa0 ? 2 : 4); j++) {
-				if (!(units & (1 << (j+24)))) continue;
-				if (device->chipset < 0xa0)
-					offset = base + 0x200 + (j<<7);
-				else
-					offset = base + 0x100 + (j<<7);
-				cp_ctx(ctx, offset, 0x20);
-				gr_def(ctx, offset + 0x00, 0x01800000);
-				gr_def(ctx, offset + 0x04, 0x00160000);
-				gr_def(ctx, offset + 0x08, 0x01800000);
-				gr_def(ctx, offset + 0x18, 0x0003ffff);
-				switch (device->chipset) {
-				case 0x50:
-					gr_def(ctx, offset + 0x1c, 0x00080000);
-					break;
-				case 0x84:
-					gr_def(ctx, offset + 0x1c, 0x00880000);
-					break;
-				case 0x86:
-					gr_def(ctx, offset + 0x1c, 0x018c0000);
-					break;
-				case 0x92:
-				case 0x96:
-				case 0x98:
-					gr_def(ctx, offset + 0x1c, 0x118c0000);
-					break;
-				case 0x94:
-					gr_def(ctx, offset + 0x1c, 0x10880000);
-					break;
-				case 0xa0:
-				case 0xa5:
-					gr_def(ctx, offset + 0x1c, 0x310c0000);
-					break;
-				case 0xa3:
-				case 0xa8:
-				case 0xaa:
-				case 0xac:
-				case 0xaf:
-					gr_def(ctx, offset + 0x1c, 0x300c0000);
-					break;
-				}
-				gr_def(ctx, offset + 0x40, 0x00010401);
-				if (device->chipset == 0x50)
-					gr_def(ctx, offset + 0x48, 0x00000040);
-				else
-					gr_def(ctx, offset + 0x48, 0x00000078);
-				gr_def(ctx, offset + 0x50, 0x000000bf);
-				gr_def(ctx, offset + 0x58, 0x00001210);
-				if (device->chipset == 0x50)
-					gr_def(ctx, offset + 0x5c, 0x00000080);
-				else
-					gr_def(ctx, offset + 0x5c, 0x08000080);
-				if (device->chipset >= 0xa0)
-					gr_def(ctx, offset + 0x68, 0x0000003e);
-			}
-
-			if (device->chipset < 0xa0)
-				cp_ctx(ctx, base + 0x300, 0x4);
-			else
-				cp_ctx(ctx, base + 0x300, 0x5);
-			if (device->chipset == 0x50)
-				gr_def(ctx, base + 0x304, 0x00007070);
-			else if (device->chipset < 0xa0)
-				gr_def(ctx, base + 0x304, 0x00027070);
-			else if (!IS_NVA3F(device->chipset))
-				gr_def(ctx, base + 0x304, 0x01127070);
-			else
-				gr_def(ctx, base + 0x304, 0x05127070);
-
-			if (device->chipset < 0xa0)
-				cp_ctx(ctx, base + 0x318, 1);
-			else
-				cp_ctx(ctx, base + 0x320, 1);
-			if (device->chipset == 0x50)
-				gr_def(ctx, base + 0x318, 0x0003ffff);
-			else if (device->chipset < 0xa0)
-				gr_def(ctx, base + 0x318, 0x03ffffff);
-			else
-				gr_def(ctx, base + 0x320, 0x07ffffff);
-
-			if (device->chipset < 0xa0)
-				cp_ctx(ctx, base + 0x324, 5);
-			else
-				cp_ctx(ctx, base + 0x328, 4);
-
-			if (device->chipset < 0xa0) {
-				cp_ctx(ctx, base + 0x340, 9);
-				offset = base + 0x340;
-			} else if (!IS_NVA3F(device->chipset)) {
-				cp_ctx(ctx, base + 0x33c, 0xb);
-				offset = base + 0x344;
-			} else {
-				cp_ctx(ctx, base + 0x33c, 0xd);
-				offset = base + 0x344;
-			}
-			gr_def(ctx, offset + 0x0, 0x00120407);
-			gr_def(ctx, offset + 0x4, 0x05091507);
-			if (device->chipset == 0x84)
-				gr_def(ctx, offset + 0x8, 0x05100202);
-			else
-				gr_def(ctx, offset + 0x8, 0x05010202);
-			gr_def(ctx, offset + 0xc, 0x00030201);
-			if (device->chipset == 0xa3)
-				cp_ctx(ctx, base + 0x36c, 1);
-
-			cp_ctx(ctx, base + 0x400, 2);
-			gr_def(ctx, base + 0x404, 0x00000040);
-			cp_ctx(ctx, base + 0x40c, 2);
-			gr_def(ctx, base + 0x40c, 0x0d0c0b0a);
-			gr_def(ctx, base + 0x410, 0x00141210);
-
-			if (device->chipset < 0xa0)
-				offset = base + 0x800;
-			else
-				offset = base + 0x500;
-			cp_ctx(ctx, offset, 6);
-			gr_def(ctx, offset + 0x0, 0x000001f0);
-			gr_def(ctx, offset + 0x4, 0x00000001);
-			gr_def(ctx, offset + 0x8, 0x00000003);
-			if (device->chipset == 0x50 || IS_NVAAF(device->chipset))
-				gr_def(ctx, offset + 0xc, 0x00008000);
-			gr_def(ctx, offset + 0x14, 0x00039e00);
-			cp_ctx(ctx, offset + 0x1c, 2);
-			if (device->chipset == 0x50)
-				gr_def(ctx, offset + 0x1c, 0x00000040);
-			else
-				gr_def(ctx, offset + 0x1c, 0x00000100);
-			gr_def(ctx, offset + 0x20, 0x00003800);
-
-			if (device->chipset >= 0xa0) {
-				cp_ctx(ctx, base + 0x54c, 2);
-				if (!IS_NVA3F(device->chipset))
-					gr_def(ctx, base + 0x54c, 0x003fe006);
-				else
-					gr_def(ctx, base + 0x54c, 0x003fe007);
-				gr_def(ctx, base + 0x550, 0x003fe000);
-			}
-
-			if (device->chipset < 0xa0)
-				offset = base + 0xa00;
-			else
-				offset = base + 0x680;
-			cp_ctx(ctx, offset, 1);
-			gr_def(ctx, offset, 0x00404040);
-
-			if (device->chipset < 0xa0)
-				offset = base + 0xe00;
-			else
-				offset = base + 0x700;
-			cp_ctx(ctx, offset, 2);
-			if (device->chipset < 0xa0)
-				gr_def(ctx, offset, 0x0077f005);
-			else if (device->chipset == 0xa5)
-				gr_def(ctx, offset, 0x6cf7f007);
-			else if (device->chipset == 0xa8)
-				gr_def(ctx, offset, 0x6cfff007);
-			else if (device->chipset == 0xac)
-				gr_def(ctx, offset, 0x0cfff007);
-			else
-				gr_def(ctx, offset, 0x0cf7f007);
-			if (device->chipset == 0x50)
-				gr_def(ctx, offset + 0x4, 0x00007fff);
-			else if (device->chipset < 0xa0)
-				gr_def(ctx, offset + 0x4, 0x003f7fff);
-			else
-				gr_def(ctx, offset + 0x4, 0x02bf7fff);
-			cp_ctx(ctx, offset + 0x2c, 1);
-			if (device->chipset == 0x50) {
-				cp_ctx(ctx, offset + 0x50, 9);
-				gr_def(ctx, offset + 0x54, 0x000003ff);
-				gr_def(ctx, offset + 0x58, 0x00000003);
-				gr_def(ctx, offset + 0x5c, 0x00000003);
-				gr_def(ctx, offset + 0x60, 0x000001ff);
-				gr_def(ctx, offset + 0x64, 0x0000001f);
-				gr_def(ctx, offset + 0x68, 0x0000000f);
-				gr_def(ctx, offset + 0x6c, 0x0000000f);
-			} else if (device->chipset < 0xa0) {
-				cp_ctx(ctx, offset + 0x50, 1);
-				cp_ctx(ctx, offset + 0x70, 1);
-			} else {
-				cp_ctx(ctx, offset + 0x50, 1);
-				cp_ctx(ctx, offset + 0x60, 5);
-			}
-		}
-	}
-}
-
-static void
-dd_emit(struct nouveau_grctx *ctx, int num, u32 val) {
-	int i;
-	if (val && ctx->mode == NOUVEAU_GRCTX_VALS)
-		for (i = 0; i < num; i++)
-			nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val);
-	ctx->ctxvals_pos += num;
-}
-
-static void
-nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	int base, num;
-	base = ctx->ctxvals_pos;
-
-	/* tesla state */
-	dd_emit(ctx, 1, 0);	/* 00000001 UNK0F90 */
-	dd_emit(ctx, 1, 0);	/* 00000001 UNK135C */
-
-	/* SRC_TIC state */
-	dd_emit(ctx, 1, 0);	/* 00000007 SRC_TILE_MODE_Z */
-	dd_emit(ctx, 1, 2);	/* 00000007 SRC_TILE_MODE_Y */
-	dd_emit(ctx, 1, 1);	/* 00000001 SRC_LINEAR #1 */
-	dd_emit(ctx, 1, 0);	/* 000000ff SRC_ADDRESS_HIGH */
-	dd_emit(ctx, 1, 0);	/* 00000001 SRC_SRGB */
-	if (device->chipset >= 0x94)
-		dd_emit(ctx, 1, 0);	/* 00000003 eng2d UNK0258 */
-	dd_emit(ctx, 1, 1);	/* 00000fff SRC_DEPTH */
-	dd_emit(ctx, 1, 0x100);	/* 0000ffff SRC_HEIGHT */
-
-	/* turing state */
-	dd_emit(ctx, 1, 0);		/* 0000000f TEXTURES_LOG2 */
-	dd_emit(ctx, 1, 0);		/* 0000000f SAMPLERS_LOG2 */
-	dd_emit(ctx, 1, 0);		/* 000000ff CB_DEF_ADDRESS_HIGH */
-	dd_emit(ctx, 1, 0);		/* ffffffff CB_DEF_ADDRESS_LOW */
-	dd_emit(ctx, 1, 0);		/* ffffffff SHARED_SIZE */
-	dd_emit(ctx, 1, 2);		/* ffffffff REG_MODE */
-	dd_emit(ctx, 1, 1);		/* 0000ffff BLOCK_ALLOC_THREADS */
-	dd_emit(ctx, 1, 1);		/* 00000001 LANES32 */
-	dd_emit(ctx, 1, 0);		/* 000000ff UNK370 */
-	dd_emit(ctx, 1, 0);		/* 000000ff USER_PARAM_UNK */
-	dd_emit(ctx, 1, 0);		/* 000000ff USER_PARAM_COUNT */
-	dd_emit(ctx, 1, 1);		/* 000000ff UNK384 bits 8-15 */
-	dd_emit(ctx, 1, 0x3fffff);	/* 003fffff TIC_LIMIT */
-	dd_emit(ctx, 1, 0x1fff);	/* 000fffff TSC_LIMIT */
-	dd_emit(ctx, 1, 0);		/* 0000ffff CB_ADDR_INDEX */
-	dd_emit(ctx, 1, 1);		/* 000007ff BLOCKDIM_X */
-	dd_emit(ctx, 1, 1);		/* 000007ff BLOCKDIM_XMY */
-	dd_emit(ctx, 1, 0);		/* 00000001 BLOCKDIM_XMY_OVERFLOW */
-	dd_emit(ctx, 1, 1);		/* 0003ffff BLOCKDIM_XMYMZ */
-	dd_emit(ctx, 1, 1);		/* 000007ff BLOCKDIM_Y */
-	dd_emit(ctx, 1, 1);		/* 0000007f BLOCKDIM_Z */
-	dd_emit(ctx, 1, 4);		/* 000000ff CP_REG_ALLOC_TEMP */
-	dd_emit(ctx, 1, 1);		/* 00000001 BLOCKDIM_DIRTY */
-	if (IS_NVA3F(device->chipset))
-		dd_emit(ctx, 1, 0);	/* 00000003 UNK03E8 */
-	dd_emit(ctx, 1, 1);		/* 0000007f BLOCK_ALLOC_HALFWARPS */
-	dd_emit(ctx, 1, 1);		/* 00000007 LOCAL_WARPS_NO_CLAMP */
-	dd_emit(ctx, 1, 7);		/* 00000007 LOCAL_WARPS_LOG_ALLOC */
-	dd_emit(ctx, 1, 1);		/* 00000007 STACK_WARPS_NO_CLAMP */
-	dd_emit(ctx, 1, 7);		/* 00000007 STACK_WARPS_LOG_ALLOC */
-	dd_emit(ctx, 1, 1);		/* 00001fff BLOCK_ALLOC_REGSLOTS_PACKED */
-	dd_emit(ctx, 1, 1);		/* 00001fff BLOCK_ALLOC_REGSLOTS_STRIDED */
-	dd_emit(ctx, 1, 1);		/* 000007ff BLOCK_ALLOC_THREADS */
-
-	/* compat 2d state */
-	if (device->chipset == 0x50) {
-		dd_emit(ctx, 4, 0);		/* 0000ffff clip X, Y, W, H */
-
-		dd_emit(ctx, 1, 1);		/* ffffffff chroma COLOR_FORMAT */
-
-		dd_emit(ctx, 1, 1);		/* ffffffff pattern COLOR_FORMAT */
-		dd_emit(ctx, 1, 0);		/* ffffffff pattern SHAPE */
-		dd_emit(ctx, 1, 1);		/* ffffffff pattern PATTERN_SELECT */
-
-		dd_emit(ctx, 1, 0xa);		/* ffffffff surf2d SRC_FORMAT */
-		dd_emit(ctx, 1, 0);		/* ffffffff surf2d DMA_SRC */
-		dd_emit(ctx, 1, 0);		/* 000000ff surf2d SRC_ADDRESS_HIGH */
-		dd_emit(ctx, 1, 0);		/* ffffffff surf2d SRC_ADDRESS_LOW */
-		dd_emit(ctx, 1, 0x40);		/* 0000ffff surf2d SRC_PITCH */
-		dd_emit(ctx, 1, 0);		/* 0000000f surf2d SRC_TILE_MODE_Z */
-		dd_emit(ctx, 1, 2);		/* 0000000f surf2d SRC_TILE_MODE_Y */
-		dd_emit(ctx, 1, 0x100);		/* ffffffff surf2d SRC_HEIGHT */
-		dd_emit(ctx, 1, 1);		/* 00000001 surf2d SRC_LINEAR */
-		dd_emit(ctx, 1, 0x100);		/* ffffffff surf2d SRC_WIDTH */
-
-		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect CLIP_B_X */
-		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect CLIP_B_Y */
-		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect CLIP_C_X */
-		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect CLIP_C_Y */
-		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect CLIP_D_X */
-		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect CLIP_D_Y */
-		dd_emit(ctx, 1, 1);		/* ffffffff gdirect COLOR_FORMAT */
-		dd_emit(ctx, 1, 0);		/* ffffffff gdirect OPERATION */
-		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect POINT_X */
-		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect POINT_Y */
-
-		dd_emit(ctx, 1, 0);		/* 0000ffff blit SRC_Y */
-		dd_emit(ctx, 1, 0);		/* ffffffff blit OPERATION */
-
-		dd_emit(ctx, 1, 0);		/* ffffffff ifc OPERATION */
-
-		dd_emit(ctx, 1, 0);		/* ffffffff iifc INDEX_FORMAT */
-		dd_emit(ctx, 1, 0);		/* ffffffff iifc LUT_OFFSET */
-		dd_emit(ctx, 1, 4);		/* ffffffff iifc COLOR_FORMAT */
-		dd_emit(ctx, 1, 0);		/* ffffffff iifc OPERATION */
-	}
-
-	/* m2mf state */
-	dd_emit(ctx, 1, 0);		/* ffffffff m2mf LINE_COUNT */
-	dd_emit(ctx, 1, 0);		/* ffffffff m2mf LINE_LENGTH_IN */
-	dd_emit(ctx, 2, 0);		/* ffffffff m2mf OFFSET_IN, OFFSET_OUT */
-	dd_emit(ctx, 1, 1);		/* ffffffff m2mf TILING_DEPTH_OUT */
-	dd_emit(ctx, 1, 0x100);		/* ffffffff m2mf TILING_HEIGHT_OUT */
-	dd_emit(ctx, 1, 0);		/* ffffffff m2mf TILING_POSITION_OUT_Z */
-	dd_emit(ctx, 1, 1);		/* 00000001 m2mf LINEAR_OUT */
-	dd_emit(ctx, 2, 0);		/* 0000ffff m2mf TILING_POSITION_OUT_X, Y */
-	dd_emit(ctx, 1, 0x100);		/* ffffffff m2mf TILING_PITCH_OUT */
-	dd_emit(ctx, 1, 1);		/* ffffffff m2mf TILING_DEPTH_IN */
-	dd_emit(ctx, 1, 0x100);		/* ffffffff m2mf TILING_HEIGHT_IN */
-	dd_emit(ctx, 1, 0);		/* ffffffff m2mf TILING_POSITION_IN_Z */
-	dd_emit(ctx, 1, 1);		/* 00000001 m2mf LINEAR_IN */
-	dd_emit(ctx, 2, 0);		/* 0000ffff m2mf TILING_POSITION_IN_X, Y */
-	dd_emit(ctx, 1, 0x100);		/* ffffffff m2mf TILING_PITCH_IN */
-
-	/* more compat 2d state */
-	if (device->chipset == 0x50) {
-		dd_emit(ctx, 1, 1);		/* ffffffff line COLOR_FORMAT */
-		dd_emit(ctx, 1, 0);		/* ffffffff line OPERATION */
-
-		dd_emit(ctx, 1, 1);		/* ffffffff triangle COLOR_FORMAT */
-		dd_emit(ctx, 1, 0);		/* ffffffff triangle OPERATION */
-
-		dd_emit(ctx, 1, 0);		/* 0000000f sifm TILE_MODE_Z */
-		dd_emit(ctx, 1, 2);		/* 0000000f sifm TILE_MODE_Y */
-		dd_emit(ctx, 1, 0);		/* 000000ff sifm FORMAT_FILTER */
-		dd_emit(ctx, 1, 1);		/* 000000ff sifm FORMAT_ORIGIN */
-		dd_emit(ctx, 1, 0);		/* 0000ffff sifm SRC_PITCH */
-		dd_emit(ctx, 1, 1);		/* 00000001 sifm SRC_LINEAR */
-		dd_emit(ctx, 1, 0);		/* 000000ff sifm SRC_OFFSET_HIGH */
-		dd_emit(ctx, 1, 0);		/* ffffffff sifm SRC_OFFSET */
-		dd_emit(ctx, 1, 0);		/* 0000ffff sifm SRC_HEIGHT */
-		dd_emit(ctx, 1, 0);		/* 0000ffff sifm SRC_WIDTH */
-		dd_emit(ctx, 1, 3);		/* ffffffff sifm COLOR_FORMAT */
-		dd_emit(ctx, 1, 0);		/* ffffffff sifm OPERATION */
-
-		dd_emit(ctx, 1, 0);		/* ffffffff sifc OPERATION */
-	}
-
-	/* tesla state */
-	dd_emit(ctx, 1, 0);		/* 0000000f GP_TEXTURES_LOG2 */
-	dd_emit(ctx, 1, 0);		/* 0000000f GP_SAMPLERS_LOG2 */
-	dd_emit(ctx, 1, 0);		/* 000000ff */
-	dd_emit(ctx, 1, 0);		/* ffffffff */
-	dd_emit(ctx, 1, 4);		/* 000000ff UNK12B0_0 */
-	dd_emit(ctx, 1, 0x70);		/* 000000ff UNK12B0_1 */
-	dd_emit(ctx, 1, 0x80);		/* 000000ff UNK12B0_3 */
-	dd_emit(ctx, 1, 0);		/* 000000ff UNK12B0_2 */
-	dd_emit(ctx, 1, 0);		/* 0000000f FP_TEXTURES_LOG2 */
-	dd_emit(ctx, 1, 0);		/* 0000000f FP_SAMPLERS_LOG2 */
-	if (IS_NVA3F(device->chipset)) {
-		dd_emit(ctx, 1, 0);	/* ffffffff */
-		dd_emit(ctx, 1, 0);	/* 0000007f MULTISAMPLE_SAMPLES_LOG2 */
-	} else {
-		dd_emit(ctx, 1, 0);	/* 0000000f MULTISAMPLE_SAMPLES_LOG2 */
-	}
-	dd_emit(ctx, 1, 0xc);		/* 000000ff SEMANTIC_COLOR.BFC0_ID */
-	if (device->chipset != 0x50)
-		dd_emit(ctx, 1, 0);	/* 00000001 SEMANTIC_COLOR.CLMP_EN */
-	dd_emit(ctx, 1, 8);		/* 000000ff SEMANTIC_COLOR.COLR_NR */
-	dd_emit(ctx, 1, 0x14);		/* 000000ff SEMANTIC_COLOR.FFC0_ID */
-	if (device->chipset == 0x50) {
-		dd_emit(ctx, 1, 0);	/* 000000ff SEMANTIC_LAYER */
-		dd_emit(ctx, 1, 0);	/* 00000001 */
-	} else {
-		dd_emit(ctx, 1, 0);	/* 00000001 SEMANTIC_PTSZ.ENABLE */
-		dd_emit(ctx, 1, 0x29);	/* 000000ff SEMANTIC_PTSZ.PTSZ_ID */
-		dd_emit(ctx, 1, 0x27);	/* 000000ff SEMANTIC_PRIM */
-		dd_emit(ctx, 1, 0x26);	/* 000000ff SEMANTIC_LAYER */
-		dd_emit(ctx, 1, 8);	/* 0000000f SMENATIC_CLIP.CLIP_HIGH */
-		dd_emit(ctx, 1, 4);	/* 000000ff SEMANTIC_CLIP.CLIP_LO */
-		dd_emit(ctx, 1, 0x27);	/* 000000ff UNK0FD4 */
-		dd_emit(ctx, 1, 0);	/* 00000001 UNK1900 */
-	}
-	dd_emit(ctx, 1, 0);		/* 00000007 RT_CONTROL_MAP0 */
-	dd_emit(ctx, 1, 1);		/* 00000007 RT_CONTROL_MAP1 */
-	dd_emit(ctx, 1, 2);		/* 00000007 RT_CONTROL_MAP2 */
-	dd_emit(ctx, 1, 3);		/* 00000007 RT_CONTROL_MAP3 */
-	dd_emit(ctx, 1, 4);		/* 00000007 RT_CONTROL_MAP4 */
-	dd_emit(ctx, 1, 5);		/* 00000007 RT_CONTROL_MAP5 */
-	dd_emit(ctx, 1, 6);		/* 00000007 RT_CONTROL_MAP6 */
-	dd_emit(ctx, 1, 7);		/* 00000007 RT_CONTROL_MAP7 */
-	dd_emit(ctx, 1, 1);		/* 0000000f RT_CONTROL_COUNT */
-	dd_emit(ctx, 8, 0);		/* 00000001 RT_HORIZ_UNK */
-	dd_emit(ctx, 8, 0);		/* ffffffff RT_ADDRESS_LOW */
-	dd_emit(ctx, 1, 0xcf);		/* 000000ff RT_FORMAT */
-	dd_emit(ctx, 7, 0);		/* 000000ff RT_FORMAT */
-	if (device->chipset != 0x50)
-		dd_emit(ctx, 3, 0);	/* 1, 1, 1 */
-	else
-		dd_emit(ctx, 2, 0);	/* 1, 1 */
-	dd_emit(ctx, 1, 0);		/* ffffffff GP_ENABLE */
-	dd_emit(ctx, 1, 0x80);		/* 0000ffff GP_VERTEX_OUTPUT_COUNT*/
-	dd_emit(ctx, 1, 4);		/* 000000ff GP_REG_ALLOC_RESULT */
-	dd_emit(ctx, 1, 4);		/* 000000ff GP_RESULT_MAP_SIZE */
-	if (IS_NVA3F(device->chipset)) {
-		dd_emit(ctx, 1, 3);	/* 00000003 */
-		dd_emit(ctx, 1, 0);	/* 00000001 UNK1418. Alone. */
-	}
-	if (device->chipset != 0x50)
-		dd_emit(ctx, 1, 3);	/* 00000003 UNK15AC */
-	dd_emit(ctx, 1, 1);		/* ffffffff RASTERIZE_ENABLE */
-	dd_emit(ctx, 1, 0);		/* 00000001 FP_CONTROL.EXPORTS_Z */
-	if (device->chipset != 0x50)
-		dd_emit(ctx, 1, 0);	/* 00000001 FP_CONTROL.MULTIPLE_RESULTS */
-	dd_emit(ctx, 1, 0x12);		/* 000000ff FP_INTERPOLANT_CTRL.COUNT */
-	dd_emit(ctx, 1, 0x10);		/* 000000ff FP_INTERPOLANT_CTRL.COUNT_NONFLAT */
-	dd_emit(ctx, 1, 0xc);		/* 000000ff FP_INTERPOLANT_CTRL.OFFSET */
-	dd_emit(ctx, 1, 1);		/* 00000001 FP_INTERPOLANT_CTRL.UMASK.W */
-	dd_emit(ctx, 1, 0);		/* 00000001 FP_INTERPOLANT_CTRL.UMASK.X */
-	dd_emit(ctx, 1, 0);		/* 00000001 FP_INTERPOLANT_CTRL.UMASK.Y */
-	dd_emit(ctx, 1, 0);		/* 00000001 FP_INTERPOLANT_CTRL.UMASK.Z */
-	dd_emit(ctx, 1, 4);		/* 000000ff FP_RESULT_COUNT */
-	dd_emit(ctx, 1, 2);		/* ffffffff REG_MODE */
-	dd_emit(ctx, 1, 4);		/* 000000ff FP_REG_ALLOC_TEMP */
-	if (device->chipset >= 0xa0)
-		dd_emit(ctx, 1, 0);	/* ffffffff */
-	dd_emit(ctx, 1, 0);		/* 00000001 GP_BUILTIN_RESULT_EN.LAYER_IDX */
-	dd_emit(ctx, 1, 0);		/* ffffffff STRMOUT_ENABLE */
-	dd_emit(ctx, 1, 0x3fffff);	/* 003fffff TIC_LIMIT */
-	dd_emit(ctx, 1, 0x1fff);	/* 000fffff TSC_LIMIT */
-	dd_emit(ctx, 1, 0);		/* 00000001 VERTEX_TWO_SIDE_ENABLE*/
-	if (device->chipset != 0x50)
-		dd_emit(ctx, 8, 0);	/* 00000001 */
-	if (device->chipset >= 0xa0) {
-		dd_emit(ctx, 1, 1);	/* 00000007 VTX_ATTR_DEFINE.COMP */
-		dd_emit(ctx, 1, 1);	/* 00000007 VTX_ATTR_DEFINE.SIZE */
-		dd_emit(ctx, 1, 2);	/* 00000007 VTX_ATTR_DEFINE.TYPE */
-		dd_emit(ctx, 1, 0);	/* 000000ff VTX_ATTR_DEFINE.ATTR */
-	}
-	dd_emit(ctx, 1, 4);		/* 0000007f VP_RESULT_MAP_SIZE */
-	dd_emit(ctx, 1, 0x14);		/* 0000001f ZETA_FORMAT */
-	dd_emit(ctx, 1, 1);		/* 00000001 ZETA_ENABLE */
-	dd_emit(ctx, 1, 0);		/* 0000000f VP_TEXTURES_LOG2 */
-	dd_emit(ctx, 1, 0);		/* 0000000f VP_SAMPLERS_LOG2 */
-	if (IS_NVA3F(device->chipset))
-		dd_emit(ctx, 1, 0);	/* 00000001 */
-	dd_emit(ctx, 1, 2);		/* 00000003 POLYGON_MODE_BACK */
-	if (device->chipset >= 0xa0)
-		dd_emit(ctx, 1, 0);	/* 00000003 VTX_ATTR_DEFINE.SIZE - 1 */
-	dd_emit(ctx, 1, 0);		/* 0000ffff CB_ADDR_INDEX */
-	if (device->chipset >= 0xa0)
-		dd_emit(ctx, 1, 0);	/* 00000003 */
-	dd_emit(ctx, 1, 0);		/* 00000001 CULL_FACE_ENABLE */
-	dd_emit(ctx, 1, 1);		/* 00000003 CULL_FACE */
-	dd_emit(ctx, 1, 0);		/* 00000001 FRONT_FACE */
-	dd_emit(ctx, 1, 2);		/* 00000003 POLYGON_MODE_FRONT */
-	dd_emit(ctx, 1, 0x1000);	/* 00007fff UNK141C */
-	if (device->chipset != 0x50) {
-		dd_emit(ctx, 1, 0xe00);		/* 7fff */
-		dd_emit(ctx, 1, 0x1000);	/* 7fff */
-		dd_emit(ctx, 1, 0x1e00);	/* 7fff */
-	}
-	dd_emit(ctx, 1, 0);		/* 00000001 BEGIN_END_ACTIVE */
-	dd_emit(ctx, 1, 1);		/* 00000001 POLYGON_MODE_??? */
-	dd_emit(ctx, 1, 1);		/* 000000ff GP_REG_ALLOC_TEMP / 4 rounded up */
-	dd_emit(ctx, 1, 1);		/* 000000ff FP_REG_ALLOC_TEMP... without /4? */
-	dd_emit(ctx, 1, 1);		/* 000000ff VP_REG_ALLOC_TEMP / 4 rounded up */
-	dd_emit(ctx, 1, 1);		/* 00000001 */
-	dd_emit(ctx, 1, 0);		/* 00000001 */
-	dd_emit(ctx, 1, 0);		/* 00000001 VTX_ATTR_MASK_UNK0 nonempty */
-	dd_emit(ctx, 1, 0);		/* 00000001 VTX_ATTR_MASK_UNK1 nonempty */
-	dd_emit(ctx, 1, 0x200);		/* 0003ffff GP_VERTEX_OUTPUT_COUNT*GP_REG_ALLOC_RESULT */
-	if (IS_NVA3F(device->chipset))
-		dd_emit(ctx, 1, 0x200);
-	dd_emit(ctx, 1, 0);		/* 00000001 */
-	if (device->chipset < 0xa0) {
-		dd_emit(ctx, 1, 1);	/* 00000001 */
-		dd_emit(ctx, 1, 0x70);	/* 000000ff */
-		dd_emit(ctx, 1, 0x80);	/* 000000ff */
-		dd_emit(ctx, 1, 0);	/* 000000ff */
-		dd_emit(ctx, 1, 0);	/* 00000001 */
-		dd_emit(ctx, 1, 1);	/* 00000001 */
-		dd_emit(ctx, 1, 0x70);	/* 000000ff */
-		dd_emit(ctx, 1, 0x80);	/* 000000ff */
-		dd_emit(ctx, 1, 0);	/* 000000ff */
-	} else {
-		dd_emit(ctx, 1, 1);	/* 00000001 */
-		dd_emit(ctx, 1, 0xf0);	/* 000000ff */
-		dd_emit(ctx, 1, 0xff);	/* 000000ff */
-		dd_emit(ctx, 1, 0);	/* 000000ff */
-		dd_emit(ctx, 1, 0);	/* 00000001 */
-		dd_emit(ctx, 1, 1);	/* 00000001 */
-		dd_emit(ctx, 1, 0xf0);	/* 000000ff */
-		dd_emit(ctx, 1, 0xff);	/* 000000ff */
-		dd_emit(ctx, 1, 0);	/* 000000ff */
-		dd_emit(ctx, 1, 9);	/* 0000003f UNK114C.COMP,SIZE */
-	}
-
-	/* eng2d state */
-	dd_emit(ctx, 1, 0);		/* 00000001 eng2d COLOR_KEY_ENABLE */
-	dd_emit(ctx, 1, 0);		/* 00000007 eng2d COLOR_KEY_FORMAT */
-	dd_emit(ctx, 1, 1);		/* ffffffff eng2d DST_DEPTH */
-	dd_emit(ctx, 1, 0xcf);		/* 000000ff eng2d DST_FORMAT */
-	dd_emit(ctx, 1, 0);		/* ffffffff eng2d DST_LAYER */
-	dd_emit(ctx, 1, 1);		/* 00000001 eng2d DST_LINEAR */
-	dd_emit(ctx, 1, 0);		/* 00000007 eng2d PATTERN_COLOR_FORMAT */
-	dd_emit(ctx, 1, 0);		/* 00000007 eng2d OPERATION */
-	dd_emit(ctx, 1, 0);		/* 00000003 eng2d PATTERN_SELECT */
-	dd_emit(ctx, 1, 0xcf);		/* 000000ff eng2d SIFC_FORMAT */
-	dd_emit(ctx, 1, 0);		/* 00000001 eng2d SIFC_BITMAP_ENABLE */
-	dd_emit(ctx, 1, 2);		/* 00000003 eng2d SIFC_BITMAP_UNK808 */
-	dd_emit(ctx, 1, 0);		/* ffffffff eng2d BLIT_DU_DX_FRACT */
-	dd_emit(ctx, 1, 1);		/* ffffffff eng2d BLIT_DU_DX_INT */
-	dd_emit(ctx, 1, 0);		/* ffffffff eng2d BLIT_DV_DY_FRACT */
-	dd_emit(ctx, 1, 1);		/* ffffffff eng2d BLIT_DV_DY_INT */
-	dd_emit(ctx, 1, 0);		/* 00000001 eng2d BLIT_CONTROL_FILTER */
-	dd_emit(ctx, 1, 0xcf);		/* 000000ff eng2d DRAW_COLOR_FORMAT */
-	dd_emit(ctx, 1, 0xcf);		/* 000000ff eng2d SRC_FORMAT */
-	dd_emit(ctx, 1, 1);		/* 00000001 eng2d SRC_LINEAR #2 */
-
-	num = ctx->ctxvals_pos - base;
-	ctx->ctxvals_pos = base;
-	if (IS_NVA3F(device->chipset))
-		cp_ctx(ctx, 0x404800, num);
-	else
-		cp_ctx(ctx, 0x405400, num);
-}
-
-/*
- * xfer areas. These are a pain.
- *
- * There are 2 xfer areas: the first one is big and contains all sorts of
- * stuff, the second is small and contains some per-TP context.
- *
- * Each area is split into 8 "strands". The areas, when saved to grctx,
- * are made of 8-word blocks. Each block contains a single word from
- * each strand. The strands are independent of each other, their
- * addresses are unrelated to each other, and data in them is closely
- * packed together. The strand layout varies a bit between cards: here
- * and there, a single word is thrown out in the middle and the whole
- * strand is offset by a bit from corresponding one on another chipset.
- * For this reason, addresses of stuff in strands are almost useless.
- * Knowing sequence of stuff and size of gaps between them is much more
- * useful, and that's how we build the strands in our generator.
- *
- * NVA0 takes this mess to a whole new level by cutting the old strands
- * into a few dozen pieces [known as genes], rearranging them randomly,
- * and putting them back together to make new strands. Hopefully these
- * genes correspond more or less directly to the same PGRAPH subunits
- * as in 400040 register.
- *
- * The most common value in default context is 0, and when the genes
- * are separated by 0's, gene bounduaries are quite speculative...
- * some of them can be clearly deduced, others can be guessed, and yet
- * others won't be resolved without figuring out the real meaning of
- * given ctxval. For the same reason, ending point of each strand
- * is unknown. Except for strand 0, which is the longest strand and
- * its end corresponds to end of the whole xfer.
- *
- * An unsolved mystery is the seek instruction: it takes an argument
- * in bits 8-18, and that argument is clearly the place in strands to
- * seek to... but the offsets don't seem to correspond to offsets as
- * seen in grctx. Perhaps there's another, real, not randomly-changing
- * addressing in strands, and the xfer insn just happens to skip over
- * the unused bits? NV10-NV30 PIPE comes to mind...
- *
- * As far as I know, there's no way to access the xfer areas directly
- * without the help of ctxprog.
- */
-
-static void
-xf_emit(struct nouveau_grctx *ctx, int num, u32 val) {
-	int i;
-	if (val && ctx->mode == NOUVEAU_GRCTX_VALS)
-		for (i = 0; i < num; i++)
-			nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val);
-	ctx->ctxvals_pos += num << 3;
-}
-
-/* Gene declarations... */
-
-static void nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx);
-
-static void
-nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	int i;
-	int offset;
-	int size = 0;
-	u32 units = nv_rd32 (ctx->device, 0x1540);
-
-	offset = (ctx->ctxvals_pos+0x3f)&~0x3f;
-	ctx->ctxvals_base = offset;
-
-	if (device->chipset < 0xa0) {
-		/* Strand 0 */
-		ctx->ctxvals_pos = offset;
-		nv50_graph_construct_gene_dispatch(ctx);
-		nv50_graph_construct_gene_m2mf(ctx);
-		nv50_graph_construct_gene_unk24xx(ctx);
-		nv50_graph_construct_gene_clipid(ctx);
-		nv50_graph_construct_gene_zcull(ctx);
-		if ((ctx->ctxvals_pos-offset)/8 > size)
-			size = (ctx->ctxvals_pos-offset)/8;
-
-		/* Strand 1 */
-		ctx->ctxvals_pos = offset + 0x1;
-		nv50_graph_construct_gene_vfetch(ctx);
-		nv50_graph_construct_gene_eng2d(ctx);
-		nv50_graph_construct_gene_csched(ctx);
-		nv50_graph_construct_gene_ropm1(ctx);
-		nv50_graph_construct_gene_ropm2(ctx);
-		if ((ctx->ctxvals_pos-offset)/8 > size)
-			size = (ctx->ctxvals_pos-offset)/8;
-
-		/* Strand 2 */
-		ctx->ctxvals_pos = offset + 0x2;
-		nv50_graph_construct_gene_ccache(ctx);
-		nv50_graph_construct_gene_unk1cxx(ctx);
-		nv50_graph_construct_gene_strmout(ctx);
-		nv50_graph_construct_gene_unk14xx(ctx);
-		nv50_graph_construct_gene_unk10xx(ctx);
-		nv50_graph_construct_gene_unk34xx(ctx);
-		if ((ctx->ctxvals_pos-offset)/8 > size)
-			size = (ctx->ctxvals_pos-offset)/8;
-
-		/* Strand 3: per-ROP group state */
-		ctx->ctxvals_pos = offset + 3;
-		for (i = 0; i < 6; i++)
-			if (units & (1 << (i + 16)))
-				nv50_graph_construct_gene_ropc(ctx);
-		if ((ctx->ctxvals_pos-offset)/8 > size)
-			size = (ctx->ctxvals_pos-offset)/8;
-
-		/* Strands 4-7: per-TP state */
-		for (i = 0; i < 4; i++) {
-			ctx->ctxvals_pos = offset + 4 + i;
-			if (units & (1 << (2 * i)))
-				nv50_graph_construct_xfer_tp(ctx);
-			if (units & (1 << (2 * i + 1)))
-				nv50_graph_construct_xfer_tp(ctx);
-			if ((ctx->ctxvals_pos-offset)/8 > size)
-				size = (ctx->ctxvals_pos-offset)/8;
-		}
-	} else {
-		/* Strand 0 */
-		ctx->ctxvals_pos = offset;
-		nv50_graph_construct_gene_dispatch(ctx);
-		nv50_graph_construct_gene_m2mf(ctx);
-		nv50_graph_construct_gene_unk34xx(ctx);
-		nv50_graph_construct_gene_csched(ctx);
-		nv50_graph_construct_gene_unk1cxx(ctx);
-		nv50_graph_construct_gene_strmout(ctx);
-		if ((ctx->ctxvals_pos-offset)/8 > size)
-			size = (ctx->ctxvals_pos-offset)/8;
-
-		/* Strand 1 */
-		ctx->ctxvals_pos = offset + 1;
-		nv50_graph_construct_gene_unk10xx(ctx);
-		if ((ctx->ctxvals_pos-offset)/8 > size)
-			size = (ctx->ctxvals_pos-offset)/8;
-
-		/* Strand 2 */
-		ctx->ctxvals_pos = offset + 2;
-		if (device->chipset == 0xa0)
-			nv50_graph_construct_gene_unk14xx(ctx);
-		nv50_graph_construct_gene_unk24xx(ctx);
-		if ((ctx->ctxvals_pos-offset)/8 > size)
-			size = (ctx->ctxvals_pos-offset)/8;
-
-		/* Strand 3 */
-		ctx->ctxvals_pos = offset + 3;
-		nv50_graph_construct_gene_vfetch(ctx);
-		if ((ctx->ctxvals_pos-offset)/8 > size)
-			size = (ctx->ctxvals_pos-offset)/8;
-
-		/* Strand 4 */
-		ctx->ctxvals_pos = offset + 4;
-		nv50_graph_construct_gene_ccache(ctx);
-		if ((ctx->ctxvals_pos-offset)/8 > size)
-			size = (ctx->ctxvals_pos-offset)/8;
-
-		/* Strand 5 */
-		ctx->ctxvals_pos = offset + 5;
-		nv50_graph_construct_gene_ropm2(ctx);
-		nv50_graph_construct_gene_ropm1(ctx);
-		/* per-ROP context */
-		for (i = 0; i < 8; i++)
-			if (units & (1<<(i+16)))
-				nv50_graph_construct_gene_ropc(ctx);
-		if ((ctx->ctxvals_pos-offset)/8 > size)
-			size = (ctx->ctxvals_pos-offset)/8;
-
-		/* Strand 6 */
-		ctx->ctxvals_pos = offset + 6;
-		nv50_graph_construct_gene_zcull(ctx);
-		nv50_graph_construct_gene_clipid(ctx);
-		nv50_graph_construct_gene_eng2d(ctx);
-		if (units & (1 << 0))
-			nv50_graph_construct_xfer_tp(ctx);
-		if (units & (1 << 1))
-			nv50_graph_construct_xfer_tp(ctx);
-		if (units & (1 << 2))
-			nv50_graph_construct_xfer_tp(ctx);
-		if (units & (1 << 3))
-			nv50_graph_construct_xfer_tp(ctx);
-		if ((ctx->ctxvals_pos-offset)/8 > size)
-			size = (ctx->ctxvals_pos-offset)/8;
-
-		/* Strand 7 */
-		ctx->ctxvals_pos = offset + 7;
-		if (device->chipset == 0xa0) {
-			if (units & (1 << 4))
-				nv50_graph_construct_xfer_tp(ctx);
-			if (units & (1 << 5))
-				nv50_graph_construct_xfer_tp(ctx);
-			if (units & (1 << 6))
-				nv50_graph_construct_xfer_tp(ctx);
-			if (units & (1 << 7))
-				nv50_graph_construct_xfer_tp(ctx);
-			if (units & (1 << 8))
-				nv50_graph_construct_xfer_tp(ctx);
-			if (units & (1 << 9))
-				nv50_graph_construct_xfer_tp(ctx);
-		} else {
-			nv50_graph_construct_gene_unk14xx(ctx);
-		}
-		if ((ctx->ctxvals_pos-offset)/8 > size)
-			size = (ctx->ctxvals_pos-offset)/8;
-	}
-
-	ctx->ctxvals_pos = offset + size * 8;
-	ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f;
-	cp_lsr (ctx, offset);
-	cp_out (ctx, CP_SET_XFER_POINTER);
-	cp_lsr (ctx, size);
-	cp_out (ctx, CP_SEEK_1);
-	cp_out (ctx, CP_XFER_1);
-	cp_wait(ctx, XFER, BUSY);
-}
-
-/*
- * non-trivial demagiced parts of ctx init go here
- */
-
-static void
-nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx)
-{
-	/* start of strand 0 */
-	struct nouveau_device *device = ctx->device;
-	/* SEEK */
-	if (device->chipset == 0x50)
-		xf_emit(ctx, 5, 0);
-	else if (!IS_NVA3F(device->chipset))
-		xf_emit(ctx, 6, 0);
-	else
-		xf_emit(ctx, 4, 0);
-	/* SEEK */
-	/* the PGRAPH's internal FIFO */
-	if (device->chipset == 0x50)
-		xf_emit(ctx, 8*3, 0);
-	else
-		xf_emit(ctx, 0x100*3, 0);
-	/* and another bonus slot?!? */
-	xf_emit(ctx, 3, 0);
-	/* and YET ANOTHER bonus slot? */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 3, 0);
-	/* SEEK */
-	/* CTX_SWITCH: caches of gr objects bound to subchannels. 8 values, last used index */
-	xf_emit(ctx, 9, 0);
-	/* SEEK */
-	xf_emit(ctx, 9, 0);
-	/* SEEK */
-	xf_emit(ctx, 9, 0);
-	/* SEEK */
-	xf_emit(ctx, 9, 0);
-	/* SEEK */
-	if (device->chipset < 0x90)
-		xf_emit(ctx, 4, 0);
-	/* SEEK */
-	xf_emit(ctx, 2, 0);
-	/* SEEK */
-	xf_emit(ctx, 6*2, 0);
-	xf_emit(ctx, 2, 0);
-	/* SEEK */
-	xf_emit(ctx, 2, 0);
-	/* SEEK */
-	xf_emit(ctx, 6*2, 0);
-	xf_emit(ctx, 2, 0);
-	/* SEEK */
-	if (device->chipset == 0x50)
-		xf_emit(ctx, 0x1c, 0);
-	else if (device->chipset < 0xa0)
-		xf_emit(ctx, 0x1e, 0);
-	else
-		xf_emit(ctx, 0x22, 0);
-	/* SEEK */
-	xf_emit(ctx, 0x15, 0);
-}
-
-static void
-nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx)
-{
-	/* Strand 0, right after dispatch */
-	struct nouveau_device *device = ctx->device;
-	int smallm2mf = 0;
-	if (device->chipset < 0x92 || device->chipset == 0x98)
-		smallm2mf = 1;
-	/* SEEK */
-	xf_emit (ctx, 1, 0);		/* DMA_NOTIFY instance >> 4 */
-	xf_emit (ctx, 1, 0);		/* DMA_BUFFER_IN instance >> 4 */
-	xf_emit (ctx, 1, 0);		/* DMA_BUFFER_OUT instance >> 4 */
-	xf_emit (ctx, 1, 0);		/* OFFSET_IN */
-	xf_emit (ctx, 1, 0);		/* OFFSET_OUT */
-	xf_emit (ctx, 1, 0);		/* PITCH_IN */
-	xf_emit (ctx, 1, 0);		/* PITCH_OUT */
-	xf_emit (ctx, 1, 0);		/* LINE_LENGTH */
-	xf_emit (ctx, 1, 0);		/* LINE_COUNT */
-	xf_emit (ctx, 1, 0x21);		/* FORMAT: bits 0-4 INPUT_INC, bits 5-9 OUTPUT_INC */
-	xf_emit (ctx, 1, 1);		/* LINEAR_IN */
-	xf_emit (ctx, 1, 0x2);		/* TILING_MODE_IN: bits 0-2 y tiling, bits 3-5 z tiling */
-	xf_emit (ctx, 1, 0x100);	/* TILING_PITCH_IN */
-	xf_emit (ctx, 1, 0x100);	/* TILING_HEIGHT_IN */
-	xf_emit (ctx, 1, 1);		/* TILING_DEPTH_IN */
-	xf_emit (ctx, 1, 0);		/* TILING_POSITION_IN_Z */
-	xf_emit (ctx, 1, 0);		/* TILING_POSITION_IN */
-	xf_emit (ctx, 1, 1);		/* LINEAR_OUT */
-	xf_emit (ctx, 1, 0x2);		/* TILING_MODE_OUT: bits 0-2 y tiling, bits 3-5 z tiling */
-	xf_emit (ctx, 1, 0x100);	/* TILING_PITCH_OUT */
-	xf_emit (ctx, 1, 0x100);	/* TILING_HEIGHT_OUT */
-	xf_emit (ctx, 1, 1);		/* TILING_DEPTH_OUT */
-	xf_emit (ctx, 1, 0);		/* TILING_POSITION_OUT_Z */
-	xf_emit (ctx, 1, 0);		/* TILING_POSITION_OUT */
-	xf_emit (ctx, 1, 0);		/* OFFSET_IN_HIGH */
-	xf_emit (ctx, 1, 0);		/* OFFSET_OUT_HIGH */
-	/* SEEK */
-	if (smallm2mf)
-		xf_emit(ctx, 0x40, 0);	/* 20 * ffffffff, 3ffff */
-	else
-		xf_emit(ctx, 0x100, 0);	/* 80 * ffffffff, 3ffff */
-	xf_emit(ctx, 4, 0);		/* 1f/7f, 0, 1f/7f, 0 [1f for smallm2mf, 7f otherwise] */
-	/* SEEK */
-	if (smallm2mf)
-		xf_emit(ctx, 0x400, 0);	/* ffffffff */
-	else
-		xf_emit(ctx, 0x800, 0);	/* ffffffff */
-	xf_emit(ctx, 4, 0);		/* ff/1ff, 0, 0, 0 [ff for smallm2mf, 1ff otherwise] */
-	/* SEEK */
-	xf_emit(ctx, 0x40, 0);		/* 20 * bits ffffffff, 3ffff */
-	xf_emit(ctx, 0x6, 0);		/* 1f, 0, 1f, 0, 1f, 0 */
-}
-
-static void
-nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	xf_emit(ctx, 2, 0);		/* RO */
-	xf_emit(ctx, 0x800, 0);		/* ffffffff */
-	switch (device->chipset) {
-	case 0x50:
-	case 0x92:
-	case 0xa0:
-		xf_emit(ctx, 0x2b, 0);
-		break;
-	case 0x84:
-		xf_emit(ctx, 0x29, 0);
-		break;
-	case 0x94:
-	case 0x96:
-	case 0xa3:
-		xf_emit(ctx, 0x27, 0);
-		break;
-	case 0x86:
-	case 0x98:
-	case 0xa5:
-	case 0xa8:
-	case 0xaa:
-	case 0xac:
-	case 0xaf:
-		xf_emit(ctx, 0x25, 0);
-		break;
-	}
-	/* CB bindings, 0x80 of them. first word is address >> 8, second is
-	 * size >> 4 | valid << 24 */
-	xf_emit(ctx, 0x100, 0);		/* ffffffff CB_DEF */
-	xf_emit(ctx, 1, 0);		/* 0000007f CB_ADDR_BUFFER */
-	xf_emit(ctx, 1, 0);		/* 0 */
-	xf_emit(ctx, 0x30, 0);		/* ff SET_PROGRAM_CB */
-	xf_emit(ctx, 1, 0);		/* 3f last SET_PROGRAM_CB */
-	xf_emit(ctx, 4, 0);		/* RO */
-	xf_emit(ctx, 0x100, 0);		/* ffffffff */
-	xf_emit(ctx, 8, 0);		/* 1f, 0, 0, ... */
-	xf_emit(ctx, 8, 0);		/* ffffffff */
-	xf_emit(ctx, 4, 0);		/* ffffffff */
-	xf_emit(ctx, 1, 0);		/* 3 */
-	xf_emit(ctx, 1, 0);		/* ffffffff */
-	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_CODE_CB */
-	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_TIC */
-	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_TSC */
-	xf_emit(ctx, 1, 0);		/* 00000001 LINKED_TSC */
-	xf_emit(ctx, 1, 0);		/* 000000ff TIC_ADDRESS_HIGH */
-	xf_emit(ctx, 1, 0);		/* ffffffff TIC_ADDRESS_LOW */
-	xf_emit(ctx, 1, 0x3fffff);	/* 003fffff TIC_LIMIT */
-	xf_emit(ctx, 1, 0);		/* 000000ff TSC_ADDRESS_HIGH */
-	xf_emit(ctx, 1, 0);		/* ffffffff TSC_ADDRESS_LOW */
-	xf_emit(ctx, 1, 0x1fff);	/* 000fffff TSC_LIMIT */
-	xf_emit(ctx, 1, 0);		/* 000000ff VP_ADDRESS_HIGH */
-	xf_emit(ctx, 1, 0);		/* ffffffff VP_ADDRESS_LOW */
-	xf_emit(ctx, 1, 0);		/* 00ffffff VP_START_ID */
-	xf_emit(ctx, 1, 0);		/* 000000ff CB_DEF_ADDRESS_HIGH */
-	xf_emit(ctx, 1, 0);		/* ffffffff CB_DEF_ADDRESS_LOW */
-	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 000000ff GP_ADDRESS_HIGH */
-	xf_emit(ctx, 1, 0);		/* ffffffff GP_ADDRESS_LOW */
-	xf_emit(ctx, 1, 0);		/* 00ffffff GP_START_ID */
-	xf_emit(ctx, 1, 0);		/* 000000ff FP_ADDRESS_HIGH */
-	xf_emit(ctx, 1, 0);		/* ffffffff FP_ADDRESS_LOW */
-	xf_emit(ctx, 1, 0);		/* 00ffffff FP_START_ID */
-}
-
-static void
-nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	int i;
-	/* end of area 2 on pre-NVA0, area 1 on NVAx */
-	xf_emit(ctx, 1, 4);		/* 000000ff GP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 4);		/* 0000007f VP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 0x80);		/* 0000ffff GP_VERTEX_OUTPUT_COUNT */
-	xf_emit(ctx, 1, 4);		/* 000000ff GP_REG_ALLOC_RESULT */
-	xf_emit(ctx, 1, 0x80c14);	/* 01ffffff SEMANTIC_COLOR */
-	xf_emit(ctx, 1, 0);		/* 00000001 VERTEX_TWO_SIDE_ENABLE */
-	if (device->chipset == 0x50)
-		xf_emit(ctx, 1, 0x3ff);
-	else
-		xf_emit(ctx, 1, 0x7ff);	/* 000007ff */
-	xf_emit(ctx, 1, 0);		/* 111/113 */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */
-	for (i = 0; i < 8; i++) {
-		switch (device->chipset) {
-		case 0x50:
-		case 0x86:
-		case 0x98:
-		case 0xaa:
-		case 0xac:
-			xf_emit(ctx, 0xa0, 0);	/* ffffffff */
-			break;
-		case 0x84:
-		case 0x92:
-		case 0x94:
-		case 0x96:
-			xf_emit(ctx, 0x120, 0);
-			break;
-		case 0xa5:
-		case 0xa8:
-			xf_emit(ctx, 0x100, 0);	/* ffffffff */
-			break;
-		case 0xa0:
-		case 0xa3:
-		case 0xaf:
-			xf_emit(ctx, 0x400, 0);	/* ffffffff */
-			break;
-		}
-		xf_emit(ctx, 4, 0);	/* 3f, 0, 0, 0 */
-		xf_emit(ctx, 4, 0);	/* ffffffff */
-	}
-	xf_emit(ctx, 1, 4);		/* 000000ff GP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 4);		/* 0000007f VP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 0x80);		/* 0000ffff GP_VERTEX_OUTPUT_COUNT */
-	xf_emit(ctx, 1, 4);		/* 000000ff GP_REG_ALLOC_TEMP */
-	xf_emit(ctx, 1, 1);		/* 00000001 RASTERIZE_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1900 */
-	xf_emit(ctx, 1, 0x27);		/* 000000ff UNK0FD4 */
-	xf_emit(ctx, 1, 0);		/* 0001ffff GP_BUILTIN_RESULT_EN */
-	xf_emit(ctx, 1, 0x26);		/* 000000ff SEMANTIC_LAYER */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */
-}
-
-static void
-nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	/* end of area 2 on pre-NVA0, area 1 on NVAx */
-	xf_emit(ctx, 1, 0);		/* 00000001 VIEWPORT_CLIP_RECTS_EN */
-	xf_emit(ctx, 1, 0);		/* 00000003 VIEWPORT_CLIP_MODE */
-	xf_emit(ctx, 0x10, 0x04000000);	/* 07ffffff VIEWPORT_CLIP_HORIZ*8, VIEWPORT_CLIP_VERT*8 */
-	xf_emit(ctx, 1, 0);		/* 00000001 POLYGON_STIPPLE_ENABLE */
-	xf_emit(ctx, 0x20, 0);		/* ffffffff POLYGON_STIPPLE */
-	xf_emit(ctx, 2, 0);		/* 00007fff WINDOW_OFFSET_XY */
-	xf_emit(ctx, 1, 0);		/* ffff0ff3 */
-	xf_emit(ctx, 1, 0x04e3bfdf);	/* ffffffff UNK0D64 */
-	xf_emit(ctx, 1, 0x04e3bfdf);	/* ffffffff UNK0DF4 */
-	xf_emit(ctx, 1, 0);		/* 00000003 WINDOW_ORIGIN */
-	xf_emit(ctx, 1, 0);		/* 00000007 */
-	xf_emit(ctx, 1, 0x1fe21);	/* 0001ffff tesla UNK0FAC */
-	if (device->chipset >= 0xa0)
-		xf_emit(ctx, 1, 0x0fac6881);
-	if (IS_NVA3F(device->chipset)) {
-		xf_emit(ctx, 1, 1);
-		xf_emit(ctx, 3, 0);
-	}
-}
-
-static void
-nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	/* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */
-	if (device->chipset != 0x50) {
-		xf_emit(ctx, 5, 0);		/* ffffffff */
-		xf_emit(ctx, 1, 0x80c14);	/* 01ffffff SEMANTIC_COLOR */
-		xf_emit(ctx, 1, 0);		/* 00000001 */
-		xf_emit(ctx, 1, 0);		/* 000003ff */
-		xf_emit(ctx, 1, 0x804);		/* 00000fff SEMANTIC_CLIP */
-		xf_emit(ctx, 1, 0);		/* 00000001 */
-		xf_emit(ctx, 2, 4);		/* 7f, ff */
-		xf_emit(ctx, 1, 0x8100c12);	/* 1fffffff FP_INTERPOLANT_CTRL */
-	}
-	xf_emit(ctx, 1, 0);			/* ffffffff tesla UNK1A30 */
-	xf_emit(ctx, 1, 4);			/* 0000007f VP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 4);			/* 000000ff GP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 0);			/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 0x10);			/* 7f/ff VIEW_VOLUME_CLIP_CTRL */
-	xf_emit(ctx, 1, 0);			/* 000000ff VP_CLIP_DISTANCE_ENABLE */
-	if (device->chipset != 0x50)
-		xf_emit(ctx, 1, 0);		/* 3ff */
-	xf_emit(ctx, 1, 0);			/* 000000ff tesla UNK1940 */
-	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK0D7C */
-	xf_emit(ctx, 1, 0x804);			/* 00000fff SEMANTIC_CLIP */
-	xf_emit(ctx, 1, 1);			/* 00000001 VIEWPORT_TRANSFORM_EN */
-	xf_emit(ctx, 1, 0x1a);			/* 0000001f POLYGON_MODE */
-	if (device->chipset != 0x50)
-		xf_emit(ctx, 1, 0x7f);		/* 000000ff tesla UNK0FFC */
-	xf_emit(ctx, 1, 0);			/* ffffffff tesla UNK1A30 */
-	xf_emit(ctx, 1, 1);			/* 00000001 SHADE_MODEL */
-	xf_emit(ctx, 1, 0x80c14);		/* 01ffffff SEMANTIC_COLOR */
-	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK1900 */
-	xf_emit(ctx, 1, 0x8100c12);		/* 1fffffff FP_INTERPOLANT_CTRL */
-	xf_emit(ctx, 1, 4);			/* 0000007f VP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 4);			/* 000000ff GP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 0);			/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 0x10);			/* 7f/ff VIEW_VOLUME_CLIP_CTRL */
-	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK0D7C */
-	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK0F8C */
-	xf_emit(ctx, 1, 0);			/* ffffffff tesla UNK1A30 */
-	xf_emit(ctx, 1, 1);			/* 00000001 VIEWPORT_TRANSFORM_EN */
-	xf_emit(ctx, 1, 0x8100c12);		/* 1fffffff FP_INTERPOLANT_CTRL */
-	xf_emit(ctx, 4, 0);			/* ffffffff NOPERSPECTIVE_BITMAP */
-	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK1900 */
-	xf_emit(ctx, 1, 0);			/* 0000000f */
-	if (device->chipset == 0x50)
-		xf_emit(ctx, 1, 0x3ff);		/* 000003ff tesla UNK0D68 */
-	else
-		xf_emit(ctx, 1, 0x7ff);		/* 000007ff tesla UNK0D68 */
-	xf_emit(ctx, 1, 0x80c14);		/* 01ffffff SEMANTIC_COLOR */
-	xf_emit(ctx, 1, 0);			/* 00000001 VERTEX_TWO_SIDE_ENABLE */
-	xf_emit(ctx, 0x30, 0);			/* ffffffff VIEWPORT_SCALE: X0, Y0, Z0, X1, Y1, ... */
-	xf_emit(ctx, 3, 0);			/* f, 0, 0 */
-	xf_emit(ctx, 3, 0);			/* ffffffff last VIEWPORT_SCALE? */
-	xf_emit(ctx, 1, 0);			/* ffffffff tesla UNK1A30 */
-	xf_emit(ctx, 1, 1);			/* 00000001 VIEWPORT_TRANSFORM_EN */
-	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK1900 */
-	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK1924 */
-	xf_emit(ctx, 1, 0x10);			/* 000000ff VIEW_VOLUME_CLIP_CTRL */
-	xf_emit(ctx, 1, 0);			/* 00000001 */
-	xf_emit(ctx, 0x30, 0);			/* ffffffff VIEWPORT_TRANSLATE */
-	xf_emit(ctx, 3, 0);			/* f, 0, 0 */
-	xf_emit(ctx, 3, 0);			/* ffffffff */
-	xf_emit(ctx, 1, 0);			/* ffffffff tesla UNK1A30 */
-	xf_emit(ctx, 2, 0x88);			/* 000001ff tesla UNK19D8 */
-	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK1924 */
-	xf_emit(ctx, 1, 0);			/* ffffffff tesla UNK1A30 */
-	xf_emit(ctx, 1, 4);			/* 0000000f CULL_MODE */
-	xf_emit(ctx, 2, 0);			/* 07ffffff SCREEN_SCISSOR */
-	xf_emit(ctx, 2, 0);			/* 00007fff WINDOW_OFFSET_XY */
-	xf_emit(ctx, 1, 0);			/* 00000003 WINDOW_ORIGIN */
-	xf_emit(ctx, 0x10, 0);			/* 00000001 SCISSOR_ENABLE */
-	xf_emit(ctx, 1, 0);			/* 0001ffff GP_BUILTIN_RESULT_EN */
-	xf_emit(ctx, 1, 0x26);			/* 000000ff SEMANTIC_LAYER */
-	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK1900 */
-	xf_emit(ctx, 1, 0);			/* 0000000f */
-	xf_emit(ctx, 1, 0x3f800000);		/* ffffffff LINE_WIDTH */
-	xf_emit(ctx, 1, 0);			/* 00000001 LINE_STIPPLE_ENABLE */
-	xf_emit(ctx, 1, 0);			/* 00000001 LINE_SMOOTH_ENABLE */
-	xf_emit(ctx, 1, 0);			/* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 1, 0);		/* 00000001 */
-	xf_emit(ctx, 1, 0x1a);			/* 0000001f POLYGON_MODE */
-	xf_emit(ctx, 1, 0x10);			/* 000000ff VIEW_VOLUME_CLIP_CTRL */
-	if (device->chipset != 0x50) {
-		xf_emit(ctx, 1, 0);		/* ffffffff */
-		xf_emit(ctx, 1, 0);		/* 00000001 */
-		xf_emit(ctx, 1, 0);		/* 000003ff */
-	}
-	xf_emit(ctx, 0x20, 0);			/* 10xbits ffffffff, 3fffff. SCISSOR_* */
-	xf_emit(ctx, 1, 0);			/* f */
-	xf_emit(ctx, 1, 0);			/* 0? */
-	xf_emit(ctx, 1, 0);			/* ffffffff */
-	xf_emit(ctx, 1, 0);			/* 003fffff */
-	xf_emit(ctx, 1, 0);			/* ffffffff tesla UNK1A30 */
-	xf_emit(ctx, 1, 0x52);			/* 000001ff SEMANTIC_PTSZ */
-	xf_emit(ctx, 1, 0);			/* 0001ffff GP_BUILTIN_RESULT_EN */
-	xf_emit(ctx, 1, 0x26);			/* 000000ff SEMANTIC_LAYER */
-	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK1900 */
-	xf_emit(ctx, 1, 4);			/* 0000007f VP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 4);			/* 000000ff GP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 0);			/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 0x1a);			/* 0000001f POLYGON_MODE */
-	xf_emit(ctx, 1, 0);			/* 00000001 LINE_SMOOTH_ENABLE */
-	xf_emit(ctx, 1, 0);			/* 00000001 LINE_STIPPLE_ENABLE */
-	xf_emit(ctx, 1, 0x00ffff00);		/* 00ffffff LINE_STIPPLE_PATTERN */
-	xf_emit(ctx, 1, 0);			/* 0000000f */
-}
-
-static void
-nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	/* end of strand 0 on pre-NVA0, beginning of strand 6 on NVAx */
-	/* SEEK */
-	xf_emit(ctx, 1, 0x3f);		/* 0000003f UNK1590 */
-	xf_emit(ctx, 1, 0);		/* 00000001 ALPHA_TEST_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */
-	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_BACK_FUNC_FUNC */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_FUNC_MASK */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_FUNC_REF */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_MASK */
-	xf_emit(ctx, 3, 0);		/* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */
-	xf_emit(ctx, 1, 2);		/* 00000003 tesla UNK143C */
-	xf_emit(ctx, 2, 0x04000000);	/* 07ffffff tesla UNK0D6C */
-	xf_emit(ctx, 1, 0);		/* ffff0ff3 */
-	xf_emit(ctx, 1, 0);		/* 00000001 CLIPID_ENABLE */
-	xf_emit(ctx, 2, 0);		/* ffffffff DEPTH_BOUNDS */
-	xf_emit(ctx, 1, 0);		/* 00000001 */
-	xf_emit(ctx, 1, 0);		/* 00000007 DEPTH_TEST_FUNC */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */
-	xf_emit(ctx, 1, 4);		/* 0000000f CULL_MODE */
-	xf_emit(ctx, 1, 0);		/* 0000ffff */
-	xf_emit(ctx, 1, 0);		/* 00000001 UNK0FB0 */
-	xf_emit(ctx, 1, 0);		/* 00000001 POLYGON_STIPPLE_ENABLE */
-	xf_emit(ctx, 1, 4);		/* 00000007 FP_CONTROL */
-	xf_emit(ctx, 1, 0);		/* ffffffff */
-	xf_emit(ctx, 1, 0);		/* 0001ffff GP_BUILTIN_RESULT_EN */
-	xf_emit(ctx, 1, 0);		/* 000000ff CLEAR_STENCIL */
-	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_FRONT_FUNC_FUNC */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_FUNC_MASK */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_FUNC_REF */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_MASK */
-	xf_emit(ctx, 3, 0);		/* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */
-	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_BACK_ENABLE */
-	xf_emit(ctx, 1, 0);		/* ffffffff CLEAR_DEPTH */
-	xf_emit(ctx, 1, 0);		/* 00000007 */
-	if (device->chipset != 0x50)
-		xf_emit(ctx, 1, 0);	/* 00000003 tesla UNK1108 */
-	xf_emit(ctx, 1, 0);		/* 00000001 SAMPLECNT_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */
-	xf_emit(ctx, 1, 1);		/* 00000001 ZETA_ENABLE */
-	xf_emit(ctx, 1, 0x1001);	/* 00001fff ZETA_ARRAY_MODE */
-	/* SEEK */
-	xf_emit(ctx, 4, 0xffff);	/* 0000ffff MSAA_MASK */
-	xf_emit(ctx, 0x10, 0);		/* 00000001 SCISSOR_ENABLE */
-	xf_emit(ctx, 0x10, 0);		/* ffffffff DEPTH_RANGE_NEAR */
-	xf_emit(ctx, 0x10, 0x3f800000);	/* ffffffff DEPTH_RANGE_FAR */
-	xf_emit(ctx, 1, 0x10);		/* 7f/ff/3ff VIEW_VOLUME_CLIP_CTRL */
-	xf_emit(ctx, 1, 0);		/* 00000001 VIEWPORT_CLIP_RECTS_EN */
-	xf_emit(ctx, 1, 3);		/* 00000003 FP_CTRL_UNK196C */
-	xf_emit(ctx, 1, 0);		/* 00000003 tesla UNK1968 */
-	if (device->chipset != 0x50)
-		xf_emit(ctx, 1, 0);	/* 0fffffff tesla UNK1104 */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK151C */
-}
-
-static void
-nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx)
-{
-	/* middle of strand 0 on pre-NVA0 [after 24xx], middle of area 6 on NVAx */
-	/* SEEK */
-	xf_emit(ctx, 1, 0);		/* 00000007 UNK0FB4 */
-	/* SEEK */
-	xf_emit(ctx, 4, 0);		/* 07ffffff CLIPID_REGION_HORIZ */
-	xf_emit(ctx, 4, 0);		/* 07ffffff CLIPID_REGION_VERT */
-	xf_emit(ctx, 2, 0);		/* 07ffffff SCREEN_SCISSOR */
-	xf_emit(ctx, 2, 0x04000000);	/* 07ffffff UNK1508 */
-	xf_emit(ctx, 1, 0);		/* 00000001 CLIPID_ENABLE */
-	xf_emit(ctx, 1, 0x80);		/* 00003fff CLIPID_WIDTH */
-	xf_emit(ctx, 1, 0);		/* 000000ff CLIPID_ID */
-	xf_emit(ctx, 1, 0);		/* 000000ff CLIPID_ADDRESS_HIGH */
-	xf_emit(ctx, 1, 0);		/* ffffffff CLIPID_ADDRESS_LOW */
-	xf_emit(ctx, 1, 0x80);		/* 00003fff CLIPID_HEIGHT */
-	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_CLIPID */
-}
-
-static void
-nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	int i;
-	/* middle of strand 0 on pre-NVA0 [after m2mf], end of strand 2 on NVAx */
-	/* SEEK */
-	xf_emit(ctx, 0x33, 0);
-	/* SEEK */
-	xf_emit(ctx, 2, 0);
-	/* SEEK */
-	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 4);		/* 0000007f VP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 4);		/* 000000ff GP_RESULT_MAP_SIZE */
-	/* SEEK */
-	if (IS_NVA3F(device->chipset)) {
-		xf_emit(ctx, 4, 0);	/* RO */
-		xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */
-		xf_emit(ctx, 1, 0);	/* 1ff */
-		xf_emit(ctx, 8, 0);	/* 0? */
-		xf_emit(ctx, 9, 0);	/* ffffffff, 7ff */
-
-		xf_emit(ctx, 4, 0);	/* RO */
-		xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */
-		xf_emit(ctx, 1, 0);	/* 1ff */
-		xf_emit(ctx, 8, 0);	/* 0? */
-		xf_emit(ctx, 9, 0);	/* ffffffff, 7ff */
-	} else {
-		xf_emit(ctx, 0xc, 0);	/* RO */
-		/* SEEK */
-		xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */
-		xf_emit(ctx, 1, 0);	/* 1ff */
-		xf_emit(ctx, 8, 0);	/* 0? */
-
-		/* SEEK */
-		xf_emit(ctx, 0xc, 0);	/* RO */
-		/* SEEK */
-		xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */
-		xf_emit(ctx, 1, 0);	/* 1ff */
-		xf_emit(ctx, 8, 0);	/* 0? */
-	}
-	/* SEEK */
-	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 4);		/* 000000ff GP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 4);		/* 0000007f VP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 0x8100c12);	/* 1fffffff FP_INTERPOLANT_CTRL */
-	if (device->chipset != 0x50)
-		xf_emit(ctx, 1, 3);	/* 00000003 tesla UNK1100 */
-	/* SEEK */
-	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 0x8100c12);	/* 1fffffff FP_INTERPOLANT_CTRL */
-	xf_emit(ctx, 1, 0);		/* 0000000f VP_GP_BUILTIN_ATTR_EN */
-	xf_emit(ctx, 1, 0x80c14);	/* 01ffffff SEMANTIC_COLOR */
-	xf_emit(ctx, 1, 1);		/* 00000001 */
-	/* SEEK */
-	if (device->chipset >= 0xa0)
-		xf_emit(ctx, 2, 4);	/* 000000ff */
-	xf_emit(ctx, 1, 0x80c14);	/* 01ffffff SEMANTIC_COLOR */
-	xf_emit(ctx, 1, 0);		/* 00000001 VERTEX_TWO_SIDE_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 POINT_SPRITE_ENABLE */
-	xf_emit(ctx, 1, 0x8100c12);	/* 1fffffff FP_INTERPOLANT_CTRL */
-	xf_emit(ctx, 1, 0x27);		/* 000000ff SEMANTIC_PRIM_ID */
-	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 0000000f */
-	xf_emit(ctx, 1, 1);		/* 00000001 */
-	for (i = 0; i < 10; i++) {
-		/* SEEK */
-		xf_emit(ctx, 0x40, 0);		/* ffffffff */
-		xf_emit(ctx, 0x10, 0);		/* 3, 0, 0.... */
-		xf_emit(ctx, 0x10, 0);		/* ffffffff */
-	}
-	/* SEEK */
-	xf_emit(ctx, 1, 0);		/* 00000001 POINT_SPRITE_CTRL */
-	xf_emit(ctx, 1, 1);		/* 00000001 */
-	xf_emit(ctx, 1, 0);		/* ffffffff */
-	xf_emit(ctx, 4, 0);		/* ffffffff NOPERSPECTIVE_BITMAP */
-	xf_emit(ctx, 0x10, 0);		/* 00ffffff POINT_COORD_REPLACE_MAP */
-	xf_emit(ctx, 1, 0);		/* 00000003 WINDOW_ORIGIN */
-	xf_emit(ctx, 1, 0x8100c12);	/* 1fffffff FP_INTERPOLANT_CTRL */
-	if (device->chipset != 0x50)
-		xf_emit(ctx, 1, 0);	/* 000003ff */
-}
-
-static void
-nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	int acnt = 0x10, rep, i;
-	/* beginning of strand 1 on pre-NVA0, strand 3 on NVAx */
-	if (IS_NVA3F(device->chipset))
-		acnt = 0x20;
-	/* SEEK */
-	if (device->chipset >= 0xa0) {
-		xf_emit(ctx, 1, 0);	/* ffffffff tesla UNK13A4 */
-		xf_emit(ctx, 1, 1);	/* 00000fff tesla UNK1318 */
-	}
-	xf_emit(ctx, 1, 0);		/* ffffffff VERTEX_BUFFER_FIRST */
-	xf_emit(ctx, 1, 0);		/* 00000001 PRIMITIVE_RESTART_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 UNK0DE8 */
-	xf_emit(ctx, 1, 0);		/* ffffffff PRIMITIVE_RESTART_INDEX */
-	xf_emit(ctx, 1, 0xf);		/* ffffffff VP_ATTR_EN */
-	xf_emit(ctx, (acnt/8)-1, 0);	/* ffffffff VP_ATTR_EN */
-	xf_emit(ctx, acnt/8, 0);	/* ffffffff VTX_ATR_MASK_UNK0DD0 */
-	xf_emit(ctx, 1, 0);		/* 0000000f VP_GP_BUILTIN_ATTR_EN */
-	xf_emit(ctx, 1, 0x20);		/* 0000ffff tesla UNK129C */
-	xf_emit(ctx, 1, 0);		/* 000000ff turing UNK370??? */
-	xf_emit(ctx, 1, 0);		/* 0000ffff turing USER_PARAM_COUNT */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */
-	/* SEEK */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 0xb, 0);	/* RO */
-	else if (device->chipset >= 0xa0)
-		xf_emit(ctx, 0x9, 0);	/* RO */
-	else
-		xf_emit(ctx, 0x8, 0);	/* RO */
-	/* SEEK */
-	xf_emit(ctx, 1, 0);		/* 00000001 EDGE_FLAG */
-	xf_emit(ctx, 1, 0);		/* 00000001 PROVOKING_VERTEX_LAST */
-	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 0x1a);		/* 0000001f POLYGON_MODE */
-	/* SEEK */
-	xf_emit(ctx, 0xc, 0);		/* RO */
-	/* SEEK */
-	xf_emit(ctx, 1, 0);		/* 7f/ff */
-	xf_emit(ctx, 1, 4);		/* 7f/ff VP_REG_ALLOC_RESULT */
-	xf_emit(ctx, 1, 4);		/* 7f/ff VP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 0);		/* 0000000f VP_GP_BUILTIN_ATTR_EN */
-	xf_emit(ctx, 1, 4);		/* 000001ff UNK1A28 */
-	xf_emit(ctx, 1, 8);		/* 000001ff UNK0DF0 */
-	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-	if (device->chipset == 0x50)
-		xf_emit(ctx, 1, 0x3ff);	/* 3ff tesla UNK0D68 */
-	else
-		xf_emit(ctx, 1, 0x7ff);	/* 7ff tesla UNK0D68 */
-	if (device->chipset == 0xa8)
-		xf_emit(ctx, 1, 0x1e00);	/* 7fff */
-	/* SEEK */
-	xf_emit(ctx, 0xc, 0);		/* RO or close */
-	/* SEEK */
-	xf_emit(ctx, 1, 0xf);		/* ffffffff VP_ATTR_EN */
-	xf_emit(ctx, (acnt/8)-1, 0);	/* ffffffff VP_ATTR_EN */
-	xf_emit(ctx, 1, 0);		/* 0000000f VP_GP_BUILTIN_ATTR_EN */
-	if (device->chipset > 0x50 && device->chipset < 0xa0)
-		xf_emit(ctx, 2, 0);	/* ffffffff */
-	else
-		xf_emit(ctx, 1, 0);	/* ffffffff */
-	xf_emit(ctx, 1, 0);		/* 00000003 tesla UNK0FD8 */
-	/* SEEK */
-	if (IS_NVA3F(device->chipset)) {
-		xf_emit(ctx, 0x10, 0);	/* 0? */
-		xf_emit(ctx, 2, 0);	/* weird... */
-		xf_emit(ctx, 2, 0);	/* RO */
-	} else {
-		xf_emit(ctx, 8, 0);	/* 0? */
-		xf_emit(ctx, 1, 0);	/* weird... */
-		xf_emit(ctx, 2, 0);	/* RO */
-	}
-	/* SEEK */
-	xf_emit(ctx, 1, 0);		/* ffffffff VB_ELEMENT_BASE */
-	xf_emit(ctx, 1, 0);		/* ffffffff UNK1438 */
-	xf_emit(ctx, acnt, 0);		/* 1 tesla UNK1000 */
-	if (device->chipset >= 0xa0)
-		xf_emit(ctx, 1, 0);	/* ffffffff tesla UNK1118? */
-	/* SEEK */
-	xf_emit(ctx, acnt, 0);		/* ffffffff VERTEX_ARRAY_UNK90C */
-	xf_emit(ctx, 1, 0);		/* f/1f */
-	/* SEEK */
-	xf_emit(ctx, acnt, 0);		/* ffffffff VERTEX_ARRAY_UNK90C */
-	xf_emit(ctx, 1, 0);		/* f/1f */
-	/* SEEK */
-	xf_emit(ctx, acnt, 0);		/* RO */
-	xf_emit(ctx, 2, 0);		/* RO */
-	/* SEEK */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK111C? */
-	xf_emit(ctx, 1, 0);		/* RO */
-	/* SEEK */
-	xf_emit(ctx, 1, 0);		/* 000000ff UNK15F4_ADDRESS_HIGH */
-	xf_emit(ctx, 1, 0);		/* ffffffff UNK15F4_ADDRESS_LOW */
-	xf_emit(ctx, 1, 0);		/* 000000ff UNK0F84_ADDRESS_HIGH */
-	xf_emit(ctx, 1, 0);		/* ffffffff UNK0F84_ADDRESS_LOW */
-	/* SEEK */
-	xf_emit(ctx, acnt, 0);		/* 00003fff VERTEX_ARRAY_ATTRIB_OFFSET */
-	xf_emit(ctx, 3, 0);		/* f/1f */
-	/* SEEK */
-	xf_emit(ctx, acnt, 0);		/* 00000fff VERTEX_ARRAY_STRIDE */
-	xf_emit(ctx, 3, 0);		/* f/1f */
-	/* SEEK */
-	xf_emit(ctx, acnt, 0);		/* ffffffff VERTEX_ARRAY_LOW */
-	xf_emit(ctx, 3, 0);		/* f/1f */
-	/* SEEK */
-	xf_emit(ctx, acnt, 0);		/* 000000ff VERTEX_ARRAY_HIGH */
-	xf_emit(ctx, 3, 0);		/* f/1f */
-	/* SEEK */
-	xf_emit(ctx, acnt, 0);		/* ffffffff VERTEX_LIMIT_LOW */
-	xf_emit(ctx, 3, 0);		/* f/1f */
-	/* SEEK */
-	xf_emit(ctx, acnt, 0);		/* 000000ff VERTEX_LIMIT_HIGH */
-	xf_emit(ctx, 3, 0);		/* f/1f */
-	/* SEEK */
-	if (IS_NVA3F(device->chipset)) {
-		xf_emit(ctx, acnt, 0);		/* f */
-		xf_emit(ctx, 3, 0);		/* f/1f */
-	}
-	/* SEEK */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 2, 0);	/* RO */
-	else
-		xf_emit(ctx, 5, 0);	/* RO */
-	/* SEEK */
-	xf_emit(ctx, 1, 0);		/* ffff DMA_VTXBUF */
-	/* SEEK */
-	if (device->chipset < 0xa0) {
-		xf_emit(ctx, 0x41, 0);	/* RO */
-		/* SEEK */
-		xf_emit(ctx, 0x11, 0);	/* RO */
-	} else if (!IS_NVA3F(device->chipset))
-		xf_emit(ctx, 0x50, 0);	/* RO */
-	else
-		xf_emit(ctx, 0x58, 0);	/* RO */
-	/* SEEK */
-	xf_emit(ctx, 1, 0xf);		/* ffffffff VP_ATTR_EN */
-	xf_emit(ctx, (acnt/8)-1, 0);	/* ffffffff VP_ATTR_EN */
-	xf_emit(ctx, 1, 1);		/* 1 UNK0DEC */
-	/* SEEK */
-	xf_emit(ctx, acnt*4, 0);	/* ffffffff VTX_ATTR */
-	xf_emit(ctx, 4, 0);		/* f/1f, 0, 0, 0 */
-	/* SEEK */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 0x1d, 0);	/* RO */
-	else
-		xf_emit(ctx, 0x16, 0);	/* RO */
-	/* SEEK */
-	xf_emit(ctx, 1, 0xf);		/* ffffffff VP_ATTR_EN */
-	xf_emit(ctx, (acnt/8)-1, 0);	/* ffffffff VP_ATTR_EN */
-	/* SEEK */
-	if (device->chipset < 0xa0)
-		xf_emit(ctx, 8, 0);	/* RO */
-	else if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 0xc, 0);	/* RO */
-	else
-		xf_emit(ctx, 7, 0);	/* RO */
-	/* SEEK */
-	xf_emit(ctx, 0xa, 0);		/* RO */
-	if (device->chipset == 0xa0)
-		rep = 0xc;
-	else
-		rep = 4;
-	for (i = 0; i < rep; i++) {
-		/* SEEK */
-		if (IS_NVA3F(device->chipset))
-			xf_emit(ctx, 0x20, 0);	/* ffffffff */
-		xf_emit(ctx, 0x200, 0);	/* ffffffff */
-		xf_emit(ctx, 4, 0);	/* 7f/ff, 0, 0, 0 */
-		xf_emit(ctx, 4, 0);	/* ffffffff */
-	}
-	/* SEEK */
-	xf_emit(ctx, 1, 0);		/* 113/111 */
-	xf_emit(ctx, 1, 0xf);		/* ffffffff VP_ATTR_EN */
-	xf_emit(ctx, (acnt/8)-1, 0);	/* ffffffff VP_ATTR_EN */
-	xf_emit(ctx, acnt/8, 0);	/* ffffffff VTX_ATTR_MASK_UNK0DD0 */
-	xf_emit(ctx, 1, 0);		/* 0000000f VP_GP_BUILTIN_ATTR_EN */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */
-	/* SEEK */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 7, 0);	/* weird... */
-	else
-		xf_emit(ctx, 5, 0);	/* weird... */
-}
-
-static void
-nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	/* middle of strand 1 on pre-NVA0 [after vfetch], middle of strand 6 on NVAx */
-	/* SEEK */
-	xf_emit(ctx, 2, 0);		/* 0001ffff CLIP_X, CLIP_Y */
-	xf_emit(ctx, 2, 0);		/* 0000ffff CLIP_W, CLIP_H */
-	xf_emit(ctx, 1, 0);		/* 00000001 CLIP_ENABLE */
-	if (device->chipset < 0xa0) {
-		/* this is useless on everything but the original NV50,
-		 * guess they forgot to nuke it. Or just didn't bother. */
-		xf_emit(ctx, 2, 0);	/* 0000ffff IFC_CLIP_X, Y */
-		xf_emit(ctx, 2, 1);	/* 0000ffff IFC_CLIP_W, H */
-		xf_emit(ctx, 1, 0);	/* 00000001 IFC_CLIP_ENABLE */
-	}
-	xf_emit(ctx, 1, 1);		/* 00000001 DST_LINEAR */
-	xf_emit(ctx, 1, 0x100);		/* 0001ffff DST_WIDTH */
-	xf_emit(ctx, 1, 0x100);		/* 0001ffff DST_HEIGHT */
-	xf_emit(ctx, 1, 0x11);		/* 3f[NV50]/7f[NV84+] DST_FORMAT */
-	xf_emit(ctx, 1, 0);		/* 0001ffff DRAW_POINT_X */
-	xf_emit(ctx, 1, 8);		/* 0000000f DRAW_UNK58C */
-	xf_emit(ctx, 1, 0);		/* 000fffff SIFC_DST_X_FRACT */
-	xf_emit(ctx, 1, 0);		/* 0001ffff SIFC_DST_X_INT */
-	xf_emit(ctx, 1, 0);		/* 000fffff SIFC_DST_Y_FRACT */
-	xf_emit(ctx, 1, 0);		/* 0001ffff SIFC_DST_Y_INT */
-	xf_emit(ctx, 1, 0);		/* 000fffff SIFC_DX_DU_FRACT */
-	xf_emit(ctx, 1, 1);		/* 0001ffff SIFC_DX_DU_INT */
-	xf_emit(ctx, 1, 0);		/* 000fffff SIFC_DY_DV_FRACT */
-	xf_emit(ctx, 1, 1);		/* 0001ffff SIFC_DY_DV_INT */
-	xf_emit(ctx, 1, 1);		/* 0000ffff SIFC_WIDTH */
-	xf_emit(ctx, 1, 1);		/* 0000ffff SIFC_HEIGHT */
-	xf_emit(ctx, 1, 0xcf);		/* 000000ff SIFC_FORMAT */
-	xf_emit(ctx, 1, 2);		/* 00000003 SIFC_BITMAP_UNK808 */
-	xf_emit(ctx, 1, 0);		/* 00000003 SIFC_BITMAP_LINE_PACK_MODE */
-	xf_emit(ctx, 1, 0);		/* 00000001 SIFC_BITMAP_LSB_FIRST */
-	xf_emit(ctx, 1, 0);		/* 00000001 SIFC_BITMAP_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 0000ffff BLIT_DST_X */
-	xf_emit(ctx, 1, 0);		/* 0000ffff BLIT_DST_Y */
-	xf_emit(ctx, 1, 0);		/* 000fffff BLIT_DU_DX_FRACT */
-	xf_emit(ctx, 1, 1);		/* 0001ffff BLIT_DU_DX_INT */
-	xf_emit(ctx, 1, 0);		/* 000fffff BLIT_DV_DY_FRACT */
-	xf_emit(ctx, 1, 1);		/* 0001ffff BLIT_DV_DY_INT */
-	xf_emit(ctx, 1, 1);		/* 0000ffff BLIT_DST_W */
-	xf_emit(ctx, 1, 1);		/* 0000ffff BLIT_DST_H */
-	xf_emit(ctx, 1, 0);		/* 000fffff BLIT_SRC_X_FRACT */
-	xf_emit(ctx, 1, 0);		/* 0001ffff BLIT_SRC_X_INT */
-	xf_emit(ctx, 1, 0);		/* 000fffff BLIT_SRC_Y_FRACT */
-	xf_emit(ctx, 1, 0);		/* 00000001 UNK888 */
-	xf_emit(ctx, 1, 4);		/* 0000003f UNK884 */
-	xf_emit(ctx, 1, 0);		/* 00000007 UNK880 */
-	xf_emit(ctx, 1, 1);		/* 0000001f tesla UNK0FB8 */
-	xf_emit(ctx, 1, 0x15);		/* 000000ff tesla UNK128C */
-	xf_emit(ctx, 2, 0);		/* 00000007, ffff0ff3 */
-	xf_emit(ctx, 1, 0);		/* 00000001 UNK260 */
-	xf_emit(ctx, 1, 0x4444480);	/* 1fffffff UNK870 */
-	/* SEEK */
-	xf_emit(ctx, 0x10, 0);
-	/* SEEK */
-	xf_emit(ctx, 0x27, 0);
-}
-
-static void
-nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	/* middle of strand 1 on pre-NVA0 [after eng2d], middle of strand 0 on NVAx */
-	/* SEEK */
-	xf_emit(ctx, 2, 0);		/* 00007fff WINDOW_OFFSET_XY... what is it doing here??? */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1924 */
-	xf_emit(ctx, 1, 0);		/* 00000003 WINDOW_ORIGIN */
-	xf_emit(ctx, 1, 0x8100c12);	/* 1fffffff FP_INTERPOLANT_CTRL */
-	xf_emit(ctx, 1, 0);		/* 000003ff */
-	/* SEEK */
-	xf_emit(ctx, 1, 0);		/* ffffffff turing UNK364 */
-	xf_emit(ctx, 1, 0);		/* 0000000f turing UNK36C */
-	xf_emit(ctx, 1, 0);		/* 0000ffff USER_PARAM_COUNT */
-	xf_emit(ctx, 1, 0x100);		/* 00ffffff turing UNK384 */
-	xf_emit(ctx, 1, 0);		/* 0000000f turing UNK2A0 */
-	xf_emit(ctx, 1, 0);		/* 0000ffff GRIDID */
-	xf_emit(ctx, 1, 0x10001);	/* ffffffff GRIDDIM_XY */
-	xf_emit(ctx, 1, 0);		/* ffffffff */
-	xf_emit(ctx, 1, 0x10001);	/* ffffffff BLOCKDIM_XY */
-	xf_emit(ctx, 1, 1);		/* 0000ffff BLOCKDIM_Z */
-	xf_emit(ctx, 1, 0x10001);	/* 00ffffff BLOCK_ALLOC */
-	xf_emit(ctx, 1, 1);		/* 00000001 LANES32 */
-	xf_emit(ctx, 1, 4);		/* 000000ff FP_REG_ALLOC_TEMP */
-	xf_emit(ctx, 1, 2);		/* 00000003 REG_MODE */
-	/* SEEK */
-	xf_emit(ctx, 0x40, 0);		/* ffffffff USER_PARAM */
-	switch (device->chipset) {
-	case 0x50:
-	case 0x92:
-		xf_emit(ctx, 8, 0);	/* 7, 0, 0, 0, ... */
-		xf_emit(ctx, 0x80, 0);	/* fff */
-		xf_emit(ctx, 2, 0);	/* ff, fff */
-		xf_emit(ctx, 0x10*2, 0);	/* ffffffff, 1f */
-		break;
-	case 0x84:
-		xf_emit(ctx, 8, 0);	/* 7, 0, 0, 0, ... */
-		xf_emit(ctx, 0x60, 0);	/* fff */
-		xf_emit(ctx, 2, 0);	/* ff, fff */
-		xf_emit(ctx, 0xc*2, 0);	/* ffffffff, 1f */
-		break;
-	case 0x94:
-	case 0x96:
-		xf_emit(ctx, 8, 0);	/* 7, 0, 0, 0, ... */
-		xf_emit(ctx, 0x40, 0);	/* fff */
-		xf_emit(ctx, 2, 0);	/* ff, fff */
-		xf_emit(ctx, 8*2, 0);	/* ffffffff, 1f */
-		break;
-	case 0x86:
-	case 0x98:
-		xf_emit(ctx, 4, 0);	/* f, 0, 0, 0 */
-		xf_emit(ctx, 0x10, 0);	/* fff */
-		xf_emit(ctx, 2, 0);	/* ff, fff */
-		xf_emit(ctx, 2*2, 0);	/* ffffffff, 1f */
-		break;
-	case 0xa0:
-		xf_emit(ctx, 8, 0);	/* 7, 0, 0, 0, ... */
-		xf_emit(ctx, 0xf0, 0);	/* fff */
-		xf_emit(ctx, 2, 0);	/* ff, fff */
-		xf_emit(ctx, 0x1e*2, 0);	/* ffffffff, 1f */
-		break;
-	case 0xa3:
-		xf_emit(ctx, 8, 0);	/* 7, 0, 0, 0, ... */
-		xf_emit(ctx, 0x60, 0);	/* fff */
-		xf_emit(ctx, 2, 0);	/* ff, fff */
-		xf_emit(ctx, 0xc*2, 0);	/* ffffffff, 1f */
-		break;
-	case 0xa5:
-	case 0xaf:
-		xf_emit(ctx, 8, 0);	/* 7, 0, 0, 0, ... */
-		xf_emit(ctx, 0x30, 0);	/* fff */
-		xf_emit(ctx, 2, 0);	/* ff, fff */
-		xf_emit(ctx, 6*2, 0);	/* ffffffff, 1f */
-		break;
-	case 0xaa:
-		xf_emit(ctx, 0x12, 0);
-		break;
-	case 0xa8:
-	case 0xac:
-		xf_emit(ctx, 4, 0);	/* f, 0, 0, 0 */
-		xf_emit(ctx, 0x10, 0);	/* fff */
-		xf_emit(ctx, 2, 0);	/* ff, fff */
-		xf_emit(ctx, 2*2, 0);	/* ffffffff, 1f */
-		break;
-	}
-	xf_emit(ctx, 1, 0);		/* 0000000f */
-	xf_emit(ctx, 1, 0);		/* 00000000 */
-	xf_emit(ctx, 1, 0);		/* ffffffff */
-	xf_emit(ctx, 1, 0);		/* 0000001f */
-	xf_emit(ctx, 4, 0);		/* ffffffff */
-	xf_emit(ctx, 1, 0);		/* 00000003 turing UNK35C */
-	xf_emit(ctx, 1, 0);		/* ffffffff */
-	xf_emit(ctx, 4, 0);		/* ffffffff */
-	xf_emit(ctx, 1, 0);		/* 00000003 turing UNK35C */
-	xf_emit(ctx, 1, 0);		/* ffffffff */
-	xf_emit(ctx, 1, 0);		/* 000000ff */
-}
-
-static void
-nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	xf_emit(ctx, 2, 0);		/* 00007fff WINDOW_OFFSET_XY */
-	xf_emit(ctx, 1, 0x3f800000);	/* ffffffff LINE_WIDTH */
-	xf_emit(ctx, 1, 0);		/* 00000001 LINE_SMOOTH_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1658 */
-	xf_emit(ctx, 1, 0);		/* 00000001 POLYGON_SMOOTH_ENABLE */
-	xf_emit(ctx, 3, 0);		/* 00000001 POLYGON_OFFSET_*_ENABLE */
-	xf_emit(ctx, 1, 4);		/* 0000000f CULL_MODE */
-	xf_emit(ctx, 1, 0x1a);		/* 0000001f POLYGON_MODE */
-	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */
-	xf_emit(ctx, 1, 0);		/* 00000001 POINT_SPRITE_ENABLE */
-	xf_emit(ctx, 1, 1);		/* 00000001 tesla UNK165C */
-	xf_emit(ctx, 0x10, 0);		/* 00000001 SCISSOR_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */
-	xf_emit(ctx, 1, 0);		/* 00000001 LINE_STIPPLE_ENABLE */
-	xf_emit(ctx, 1, 0x00ffff00);	/* 00ffffff LINE_STIPPLE_PATTERN */
-	xf_emit(ctx, 1, 0);		/* ffffffff POLYGON_OFFSET_UNITS */
-	xf_emit(ctx, 1, 0);		/* ffffffff POLYGON_OFFSET_FACTOR */
-	xf_emit(ctx, 1, 0);		/* 00000003 tesla UNK1668 */
-	xf_emit(ctx, 2, 0);		/* 07ffffff SCREEN_SCISSOR */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1900 */
-	xf_emit(ctx, 1, 0xf);		/* 0000000f COLOR_MASK */
-	xf_emit(ctx, 7, 0);		/* 0000000f COLOR_MASK */
-	xf_emit(ctx, 1, 0x0fac6881);	/* 0fffffff RT_CONTROL */
-	xf_emit(ctx, 1, 0x11);		/* 0000007f RT_FORMAT */
-	xf_emit(ctx, 7, 0);		/* 0000007f RT_FORMAT */
-	xf_emit(ctx, 8, 0);		/* 00000001 RT_HORIZ_LINEAR */
-	xf_emit(ctx, 1, 4);		/* 00000007 FP_CONTROL */
-	xf_emit(ctx, 1, 0);		/* 00000001 ALPHA_TEST_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000007 ALPHA_TEST_FUNC */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 1, 3);	/* 00000003 UNK16B4 */
-	else if (device->chipset >= 0xa0)
-		xf_emit(ctx, 1, 1);	/* 00000001 UNK16B4 */
-	xf_emit(ctx, 1, 0);		/* 00000003 MULTISAMPLE_CTRL */
-	xf_emit(ctx, 1, 0);		/* 00000003 tesla UNK0F90 */
-	xf_emit(ctx, 1, 2);		/* 00000003 tesla UNK143C */
-	xf_emit(ctx, 2, 0x04000000);	/* 07ffffff tesla UNK0D6C */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_MASK */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 SAMPLECNT_ENABLE */
-	xf_emit(ctx, 1, 5);		/* 0000000f UNK1408 */
-	xf_emit(ctx, 1, 0x52);		/* 000001ff SEMANTIC_PTSZ */
-	xf_emit(ctx, 1, 0);		/* ffffffff POINT_SIZE */
-	xf_emit(ctx, 1, 0);		/* 00000001 */
-	xf_emit(ctx, 1, 0);		/* 00000007 tesla UNK0FB4 */
-	if (device->chipset != 0x50) {
-		xf_emit(ctx, 1, 0);	/* 3ff */
-		xf_emit(ctx, 1, 1);	/* 00000001 tesla UNK1110 */
-	}
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 1, 0);	/* 00000003 tesla UNK1928 */
-	xf_emit(ctx, 0x10, 0);		/* ffffffff DEPTH_RANGE_NEAR */
-	xf_emit(ctx, 0x10, 0x3f800000);	/* ffffffff DEPTH_RANGE_FAR */
-	xf_emit(ctx, 1, 0x10);		/* 000000ff VIEW_VOLUME_CLIP_CTRL */
-	xf_emit(ctx, 0x20, 0);		/* 07ffffff VIEWPORT_HORIZ, then VIEWPORT_VERT. (W&0x3fff)<<13 | (X&0x1fff). */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK187C */
-	xf_emit(ctx, 1, 0);		/* 00000003 WINDOW_ORIGIN */
-	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_BACK_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_MASK */
-	xf_emit(ctx, 1, 0x8100c12);	/* 1fffffff FP_INTERPOLANT_CTRL */
-	xf_emit(ctx, 1, 5);		/* 0000000f tesla UNK1220 */
-	xf_emit(ctx, 1, 0);		/* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
-	xf_emit(ctx, 1, 0);		/* 000000ff tesla UNK1A20 */
-	xf_emit(ctx, 1, 1);		/* 00000001 ZETA_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 VERTEX_TWO_SIDE_ENABLE */
-	xf_emit(ctx, 4, 0xffff);	/* 0000ffff MSAA_MASK */
-	if (device->chipset != 0x50)
-		xf_emit(ctx, 1, 3);	/* 00000003 tesla UNK1100 */
-	if (device->chipset < 0xa0)
-		xf_emit(ctx, 0x1c, 0);	/* RO */
-	else if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 0x9, 0);
-	xf_emit(ctx, 1, 0);		/* 00000001 UNK1534 */
-	xf_emit(ctx, 1, 0);		/* 00000001 LINE_SMOOTH_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 LINE_STIPPLE_ENABLE */
-	xf_emit(ctx, 1, 0x00ffff00);	/* 00ffffff LINE_STIPPLE_PATTERN */
-	xf_emit(ctx, 1, 0x1a);		/* 0000001f POLYGON_MODE */
-	xf_emit(ctx, 1, 0);		/* 00000003 WINDOW_ORIGIN */
-	if (device->chipset != 0x50) {
-		xf_emit(ctx, 1, 3);	/* 00000003 tesla UNK1100 */
-		xf_emit(ctx, 1, 0);	/* 3ff */
-	}
-	/* XXX: the following block could belong either to unk1cxx, or
-	 * to STRMOUT. Rather hard to tell. */
-	if (device->chipset < 0xa0)
-		xf_emit(ctx, 0x25, 0);
-	else
-		xf_emit(ctx, 0x3b, 0);
-}
-
-static void
-nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	xf_emit(ctx, 1, 0x102);		/* 0000ffff STRMOUT_BUFFER_CTRL */
-	xf_emit(ctx, 1, 0);		/* ffffffff STRMOUT_PRIMITIVE_COUNT */
-	xf_emit(ctx, 4, 4);		/* 000000ff STRMOUT_NUM_ATTRIBS */
-	if (device->chipset >= 0xa0) {
-		xf_emit(ctx, 4, 0);	/* ffffffff UNK1A8C */
-		xf_emit(ctx, 4, 0);	/* ffffffff UNK1780 */
-	}
-	xf_emit(ctx, 1, 4);		/* 000000ff GP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 4);		/* 0000007f VP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-	if (device->chipset == 0x50)
-		xf_emit(ctx, 1, 0x3ff);	/* 000003ff tesla UNK0D68 */
-	else
-		xf_emit(ctx, 1, 0x7ff);	/* 000007ff tesla UNK0D68 */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */
-	/* SEEK */
-	xf_emit(ctx, 1, 0x102);		/* 0000ffff STRMOUT_BUFFER_CTRL */
-	xf_emit(ctx, 1, 0);		/* ffffffff STRMOUT_PRIMITIVE_COUNT */
-	xf_emit(ctx, 4, 0);		/* 000000ff STRMOUT_ADDRESS_HIGH */
-	xf_emit(ctx, 4, 0);		/* ffffffff STRMOUT_ADDRESS_LOW */
-	xf_emit(ctx, 4, 4);		/* 000000ff STRMOUT_NUM_ATTRIBS */
-	if (device->chipset >= 0xa0) {
-		xf_emit(ctx, 4, 0);	/* ffffffff UNK1A8C */
-		xf_emit(ctx, 4, 0);	/* ffffffff UNK1780 */
-	}
-	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_STRMOUT */
-	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_QUERY */
-	xf_emit(ctx, 1, 0);		/* 000000ff QUERY_ADDRESS_HIGH */
-	xf_emit(ctx, 2, 0);		/* ffffffff QUERY_ADDRESS_LOW QUERY_COUNTER */
-	xf_emit(ctx, 2, 0);		/* ffffffff */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */
-	/* SEEK */
-	xf_emit(ctx, 0x20, 0);		/* ffffffff STRMOUT_MAP */
-	xf_emit(ctx, 1, 0);		/* 0000000f */
-	xf_emit(ctx, 1, 0);		/* 00000000? */
-	xf_emit(ctx, 2, 0);		/* ffffffff */
-}
-
-static void
-nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	xf_emit(ctx, 1, 0x4e3bfdf);	/* ffffffff UNK0D64 */
-	xf_emit(ctx, 1, 0x4e3bfdf);	/* ffffffff UNK0DF4 */
-	xf_emit(ctx, 1, 0);		/* 00000007 */
-	xf_emit(ctx, 1, 0);		/* 000003ff */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 1, 0x11);	/* 000000ff tesla UNK1968 */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */
-}
-
-static void
-nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	/* SEEK */
-	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_QUERY */
-	xf_emit(ctx, 1, 0x0fac6881);	/* 0fffffff RT_CONTROL */
-	xf_emit(ctx, 2, 0);		/* ffffffff */
-	xf_emit(ctx, 1, 0);		/* 000000ff QUERY_ADDRESS_HIGH */
-	xf_emit(ctx, 2, 0);		/* ffffffff QUERY_ADDRESS_LOW, COUNTER */
-	xf_emit(ctx, 1, 0);		/* 00000001 SAMPLECNT_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 7 */
-	/* SEEK */
-	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_QUERY */
-	xf_emit(ctx, 1, 0);		/* 000000ff QUERY_ADDRESS_HIGH */
-	xf_emit(ctx, 2, 0);		/* ffffffff QUERY_ADDRESS_LOW, COUNTER */
-	xf_emit(ctx, 1, 0x4e3bfdf);	/* ffffffff UNK0D64 */
-	xf_emit(ctx, 1, 0x4e3bfdf);	/* ffffffff UNK0DF4 */
-	xf_emit(ctx, 1, 0);		/* 00000001 eng2d UNK260 */
-	xf_emit(ctx, 1, 0);		/* ff/3ff */
-	xf_emit(ctx, 1, 0);		/* 00000007 */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 1, 0x11);	/* 000000ff tesla UNK1968 */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */
-}
-
-static void
-nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	int magic2;
-	if (device->chipset == 0x50) {
-		magic2 = 0x00003e60;
-	} else if (!IS_NVA3F(device->chipset)) {
-		magic2 = 0x001ffe67;
-	} else {
-		magic2 = 0x00087e67;
-	}
-	xf_emit(ctx, 1, 0);		/* f/7 MUTISAMPLE_SAMPLES_LOG2 */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */
-	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_BACK_FUNC_FUNC */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_FUNC_MASK */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_MASK */
-	xf_emit(ctx, 3, 0);		/* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */
-	xf_emit(ctx, 1, 2);		/* 00000003 tesla UNK143C */
-	xf_emit(ctx, 1, 0);		/* ffff0ff3 */
-	xf_emit(ctx, 1, magic2);	/* 001fffff tesla UNK0F78 */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_BOUNDS_EN */
-	xf_emit(ctx, 1, 0);		/* 00000007 DEPTH_TEST_FUNC */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 1, 1);	/* 0000001f tesla UNK169C */
-	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_FRONT_FUNC_FUNC */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_FUNC_MASK */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_MASK */
-	xf_emit(ctx, 3, 0);		/* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */
-	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */
-	if (device->chipset >= 0xa0 && !IS_NVAAF(device->chipset))
-		xf_emit(ctx, 1, 0x15);	/* 000000ff */
-	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_BACK_ENABLE */
-	xf_emit(ctx, 1, 1);		/* 00000001 tesla UNK15B4 */
-	xf_emit(ctx, 1, 0x10);		/* 3ff/ff VIEW_VOLUME_CLIP_CTRL */
-	xf_emit(ctx, 1, 0);		/* ffffffff CLEAR_DEPTH */
-	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */
-	xf_emit(ctx, 1, 1);		/* 00000001 ZETA_ENABLE */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */
-	if (device->chipset == 0x86 || device->chipset == 0x92 || device->chipset == 0x98 || device->chipset >= 0xa0) {
-		xf_emit(ctx, 3, 0);	/* ff, ffffffff, ffffffff */
-		xf_emit(ctx, 1, 4);	/* 7 */
-		xf_emit(ctx, 1, 0x400);	/* fffffff */
-		xf_emit(ctx, 1, 0x300);	/* ffff */
-		xf_emit(ctx, 1, 0x1001);	/* 1fff */
-		if (device->chipset != 0xa0) {
-			if (IS_NVA3F(device->chipset))
-				xf_emit(ctx, 1, 0);	/* 0000000f UNK15C8 */
-			else
-				xf_emit(ctx, 1, 0x15);	/* ff */
-		}
-	}
-	xf_emit(ctx, 1, 0);		/* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */
-	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_BACK_FUNC_FUNC */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_FUNC_MASK */
-	xf_emit(ctx, 1, 0);		/* ffff0ff3 */
-	xf_emit(ctx, 1, 2);		/* 00000003 tesla UNK143C */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_BOUNDS_EN */
-	xf_emit(ctx, 1, 0);		/* 00000007 DEPTH_TEST_FUNC */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_FRONT_FUNC_FUNC */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_FUNC_MASK */
-	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_BACK_ENABLE */
-	xf_emit(ctx, 1, 1);		/* 00000001 tesla UNK15B4 */
-	xf_emit(ctx, 1, 0x10);		/* 7f/ff VIEW_VOLUME_CLIP_CTRL */
-	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */
-	xf_emit(ctx, 1, 1);		/* 00000001 ZETA_ENABLE */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1900 */
-	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_BACK_FUNC_FUNC */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_FUNC_MASK */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_FUNC_REF */
-	xf_emit(ctx, 2, 0);		/* ffffffff DEPTH_BOUNDS */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_BOUNDS_EN */
-	xf_emit(ctx, 1, 0);		/* 00000007 DEPTH_TEST_FUNC */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 0000000f */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK0FB0 */
-	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_FRONT_FUNC_FUNC */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_FUNC_MASK */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_FUNC_REF */
-	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_BACK_ENABLE */
-	xf_emit(ctx, 1, 0x10);		/* 7f/ff VIEW_VOLUME_CLIP_CTRL */
-	xf_emit(ctx, 0x10, 0);		/* ffffffff DEPTH_RANGE_NEAR */
-	xf_emit(ctx, 0x10, 0x3f800000);	/* ffffffff DEPTH_RANGE_FAR */
-	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */
-	xf_emit(ctx, 1, 0);		/* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
-	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_BACK_FUNC_FUNC */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_FUNC_MASK */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_FUNC_REF */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_MASK */
-	xf_emit(ctx, 3, 0);		/* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */
-	xf_emit(ctx, 2, 0);		/* ffffffff DEPTH_BOUNDS */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_BOUNDS_EN */
-	xf_emit(ctx, 1, 0);		/* 00000007 DEPTH_TEST_FUNC */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 000000ff CLEAR_STENCIL */
-	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_FRONT_FUNC_FUNC */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_FUNC_MASK */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_FUNC_REF */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_MASK */
-	xf_emit(ctx, 3, 0);		/* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */
-	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_BACK_ENABLE */
-	xf_emit(ctx, 1, 0x10);		/* 7f/ff VIEW_VOLUME_CLIP_CTRL */
-	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */
-	xf_emit(ctx, 1, 0x3f);		/* 0000003f UNK1590 */
-	xf_emit(ctx, 1, 0);		/* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */
-	xf_emit(ctx, 2, 0);		/* ffff0ff3, ffff */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK0FB0 */
-	xf_emit(ctx, 1, 0);		/* 0001ffff GP_BUILTIN_RESULT_EN */
-	xf_emit(ctx, 1, 1);		/* 00000001 tesla UNK15B4 */
-	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */
-	xf_emit(ctx, 1, 1);		/* 00000001 ZETA_ENABLE */
-	xf_emit(ctx, 1, 0);		/* ffffffff CLEAR_DEPTH */
-	xf_emit(ctx, 1, 1);		/* 00000001 tesla UNK19CC */
-	if (device->chipset >= 0xa0) {
-		xf_emit(ctx, 2, 0);
-		xf_emit(ctx, 1, 0x1001);
-		xf_emit(ctx, 0xb, 0);
-	} else {
-		xf_emit(ctx, 1, 0);	/* 00000007 */
-		xf_emit(ctx, 1, 0);	/* 00000001 tesla UNK1534 */
-		xf_emit(ctx, 1, 0);	/* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
-		xf_emit(ctx, 8, 0);	/* 00000001 BLEND_ENABLE */
-		xf_emit(ctx, 1, 0);	/* ffff0ff3 */
-	}
-	xf_emit(ctx, 1, 0x11);		/* 3f/7f RT_FORMAT */
-	xf_emit(ctx, 7, 0);		/* 3f/7f RT_FORMAT */
-	xf_emit(ctx, 1, 0xf);		/* 0000000f COLOR_MASK */
-	xf_emit(ctx, 7, 0);		/* 0000000f COLOR_MASK */
-	xf_emit(ctx, 1, 0x11);		/* 3f/7f */
-	xf_emit(ctx, 1, 0);		/* 00000001 LOGIC_OP_ENABLE */
-	if (device->chipset != 0x50) {
-		xf_emit(ctx, 1, 0);	/* 0000000f LOGIC_OP */
-		xf_emit(ctx, 1, 0);	/* 000000ff */
-	}
-	xf_emit(ctx, 1, 0);		/* 00000007 OPERATION */
-	xf_emit(ctx, 1, 0);		/* ff/3ff */
-	xf_emit(ctx, 1, 0);		/* 00000003 UNK0F90 */
-	xf_emit(ctx, 2, 1);		/* 00000007 BLEND_EQUATION_RGB, ALPHA */
-	xf_emit(ctx, 1, 1);		/* 00000001 UNK133C */
-	xf_emit(ctx, 1, 2);		/* 0000001f BLEND_FUNC_SRC_RGB */
-	xf_emit(ctx, 1, 1);		/* 0000001f BLEND_FUNC_DST_RGB */
-	xf_emit(ctx, 1, 2);		/* 0000001f BLEND_FUNC_SRC_ALPHA */
-	xf_emit(ctx, 1, 1);		/* 0000001f BLEND_FUNC_DST_ALPHA */
-	xf_emit(ctx, 1, 0);		/* 00000001 */
-	xf_emit(ctx, 1, magic2);	/* 001fffff tesla UNK0F78 */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */
-	xf_emit(ctx, 1, 0x0fac6881);	/* 0fffffff RT_CONTROL */
-	if (IS_NVA3F(device->chipset)) {
-		xf_emit(ctx, 1, 0);	/* 00000001 tesla UNK12E4 */
-		xf_emit(ctx, 8, 1);	/* 00000007 IBLEND_EQUATION_RGB */
-		xf_emit(ctx, 8, 1);	/* 00000007 IBLEND_EQUATION_ALPHA */
-		xf_emit(ctx, 8, 1);	/* 00000001 IBLEND_UNK00 */
-		xf_emit(ctx, 8, 2);	/* 0000001f IBLEND_FUNC_SRC_RGB */
-		xf_emit(ctx, 8, 1);	/* 0000001f IBLEND_FUNC_DST_RGB */
-		xf_emit(ctx, 8, 2);	/* 0000001f IBLEND_FUNC_SRC_ALPHA */
-		xf_emit(ctx, 8, 1);	/* 0000001f IBLEND_FUNC_DST_ALPHA */
-		xf_emit(ctx, 1, 0);	/* 00000001 tesla UNK1140 */
-		xf_emit(ctx, 2, 0);	/* 00000001 */
-		xf_emit(ctx, 1, 1);	/* 0000001f tesla UNK169C */
-		xf_emit(ctx, 1, 0);	/* 0000000f */
-		xf_emit(ctx, 1, 0);	/* 00000003 */
-		xf_emit(ctx, 1, 0);	/* ffffffff */
-		xf_emit(ctx, 2, 0);	/* 00000001 */
-		xf_emit(ctx, 1, 1);	/* 0000001f tesla UNK169C */
-		xf_emit(ctx, 1, 0);	/* 00000001 */
-		xf_emit(ctx, 1, 0);	/* 000003ff */
-	} else if (device->chipset >= 0xa0) {
-		xf_emit(ctx, 2, 0);	/* 00000001 */
-		xf_emit(ctx, 1, 0);	/* 00000007 */
-		xf_emit(ctx, 1, 0);	/* 00000003 */
-		xf_emit(ctx, 1, 0);	/* ffffffff */
-		xf_emit(ctx, 2, 0);	/* 00000001 */
-	} else {
-		xf_emit(ctx, 1, 0);	/* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
-		xf_emit(ctx, 1, 0);	/* 00000003 tesla UNK1430 */
-		xf_emit(ctx, 1, 0);	/* ffffffff tesla UNK1A3C */
-	}
-	xf_emit(ctx, 4, 0);		/* ffffffff CLEAR_COLOR */
-	xf_emit(ctx, 4, 0);		/* ffffffff BLEND_COLOR A R G B */
-	xf_emit(ctx, 1, 0);		/* 00000fff eng2d UNK2B0 */
-	if (device->chipset >= 0xa0)
-		xf_emit(ctx, 2, 0);	/* 00000001 */
-	xf_emit(ctx, 1, 0);		/* 000003ff */
-	xf_emit(ctx, 8, 0);		/* 00000001 BLEND_ENABLE */
-	xf_emit(ctx, 1, 1);		/* 00000001 UNK133C */
-	xf_emit(ctx, 1, 2);		/* 0000001f BLEND_FUNC_SRC_RGB */
-	xf_emit(ctx, 1, 1);		/* 0000001f BLEND_FUNC_DST_RGB */
-	xf_emit(ctx, 1, 1);		/* 00000007 BLEND_EQUATION_RGB */
-	xf_emit(ctx, 1, 2);		/* 0000001f BLEND_FUNC_SRC_ALPHA */
-	xf_emit(ctx, 1, 1);		/* 0000001f BLEND_FUNC_DST_ALPHA */
-	xf_emit(ctx, 1, 1);		/* 00000007 BLEND_EQUATION_ALPHA */
-	xf_emit(ctx, 1, 0);		/* 00000001 UNK19C0 */
-	xf_emit(ctx, 1, 0);		/* 00000001 LOGIC_OP_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 0000000f LOGIC_OP */
-	if (device->chipset >= 0xa0)
-		xf_emit(ctx, 1, 0);	/* 00000001 UNK12E4? NVA3+ only? */
-	if (IS_NVA3F(device->chipset)) {
-		xf_emit(ctx, 8, 1);	/* 00000001 IBLEND_UNK00 */
-		xf_emit(ctx, 8, 1);	/* 00000007 IBLEND_EQUATION_RGB */
-		xf_emit(ctx, 8, 2);	/* 0000001f IBLEND_FUNC_SRC_RGB */
-		xf_emit(ctx, 8, 1);	/* 0000001f IBLEND_FUNC_DST_RGB */
-		xf_emit(ctx, 8, 1);	/* 00000007 IBLEND_EQUATION_ALPHA */
-		xf_emit(ctx, 8, 2);	/* 0000001f IBLEND_FUNC_SRC_ALPHA */
-		xf_emit(ctx, 8, 1);	/* 0000001f IBLEND_FUNC_DST_ALPHA */
-		xf_emit(ctx, 1, 0);	/* 00000001 tesla UNK15C4 */
-		xf_emit(ctx, 1, 0);	/* 00000001 */
-		xf_emit(ctx, 1, 0);	/* 00000001 tesla UNK1140 */
-	}
-	xf_emit(ctx, 1, 0x11);		/* 3f/7f DST_FORMAT */
-	xf_emit(ctx, 1, 1);		/* 00000001 DST_LINEAR */
-	xf_emit(ctx, 1, 0);		/* 00000007 PATTERN_COLOR_FORMAT */
-	xf_emit(ctx, 2, 0);		/* ffffffff PATTERN_MONO_COLOR */
-	xf_emit(ctx, 1, 0);		/* 00000001 PATTERN_MONO_FORMAT */
-	xf_emit(ctx, 2, 0);		/* ffffffff PATTERN_MONO_BITMAP */
-	xf_emit(ctx, 1, 0);		/* 00000003 PATTERN_SELECT */
-	xf_emit(ctx, 1, 0);		/* 000000ff ROP */
-	xf_emit(ctx, 1, 0);		/* ffffffff BETA1 */
-	xf_emit(ctx, 1, 0);		/* ffffffff BETA4 */
-	xf_emit(ctx, 1, 0);		/* 00000007 OPERATION */
-	xf_emit(ctx, 0x50, 0);		/* 10x ffffff, ffffff, ffffff, ffffff, 3 PATTERN */
-}
-
-static void
-nv50_graph_construct_xfer_unk84xx(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	int magic3;
-	switch (device->chipset) {
-	case 0x50:
-		magic3 = 0x1000;
-		break;
-	case 0x86:
-	case 0x98:
-	case 0xa8:
-	case 0xaa:
-	case 0xac:
-	case 0xaf:
-		magic3 = 0x1e00;
-		break;
-	default:
-		magic3 = 0;
-	}
-	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 4);		/* 7f/ff[NVA0+] VP_REG_ALLOC_RESULT */
-	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */
-	xf_emit(ctx, 1, 0);		/* 111/113[NVA0+] */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 0x1f, 0);	/* ffffffff */
-	else if (device->chipset >= 0xa0)
-		xf_emit(ctx, 0x0f, 0);	/* ffffffff */
-	else
-		xf_emit(ctx, 0x10, 0);	/* fffffff VP_RESULT_MAP_1 up */
-	xf_emit(ctx, 2, 0);		/* f/1f[NVA3], fffffff/ffffffff[NVA0+] */
-	xf_emit(ctx, 1, 4);		/* 7f/ff VP_REG_ALLOC_RESULT */
-	xf_emit(ctx, 1, 4);		/* 7f/ff VP_RESULT_MAP_SIZE */
-	if (device->chipset >= 0xa0)
-		xf_emit(ctx, 1, 0x03020100);	/* ffffffff */
-	else
-		xf_emit(ctx, 1, 0x00608080);	/* fffffff VP_RESULT_MAP_0 */
-	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */
-	xf_emit(ctx, 2, 0);		/* 111/113, 7f/ff */
-	xf_emit(ctx, 1, 4);		/* 7f/ff VP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */
-	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 4);		/* 000000ff GP_REG_ALLOC_RESULT */
-	xf_emit(ctx, 1, 4);		/* 000000ff GP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 0x80);		/* 0000ffff GP_VERTEX_OUTPUT_COUNT */
-	if (magic3)
-		xf_emit(ctx, 1, magic3);	/* 00007fff tesla UNK141C */
-	xf_emit(ctx, 1, 4);		/* 7f/ff VP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */
-	xf_emit(ctx, 1, 0);		/* 111/113 */
-	xf_emit(ctx, 0x1f, 0);		/* ffffffff GP_RESULT_MAP_1 up */
-	xf_emit(ctx, 1, 0);		/* 0000001f */
-	xf_emit(ctx, 1, 0);		/* ffffffff */
-	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 4);		/* 000000ff GP_REG_ALLOC_RESULT */
-	xf_emit(ctx, 1, 0x80);		/* 0000ffff GP_VERTEX_OUTPUT_COUNT */
-	xf_emit(ctx, 1, 4);		/* 000000ff GP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 0x03020100);	/* ffffffff GP_RESULT_MAP_0 */
-	xf_emit(ctx, 1, 3);		/* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */
-	if (magic3)
-		xf_emit(ctx, 1, magic3);	/* 7fff tesla UNK141C */
-	xf_emit(ctx, 1, 4);		/* 7f/ff VP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 0);		/* 00000001 PROVOKING_VERTEX_LAST */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */
-	xf_emit(ctx, 1, 0);		/* 111/113 */
-	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 4);		/* 000000ff GP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 3);		/* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */
-	xf_emit(ctx, 1, 0);		/* 00000001 PROVOKING_VERTEX_LAST */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */
-	xf_emit(ctx, 1, 0);		/* 00000003 tesla UNK13A0 */
-	xf_emit(ctx, 1, 4);		/* 7f/ff VP_REG_ALLOC_RESULT */
-	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */
-	xf_emit(ctx, 1, 0);		/* 111/113 */
-	if (device->chipset == 0x94 || device->chipset == 0x96)
-		xf_emit(ctx, 0x1020, 0);	/* 4 x (0x400 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */
-	else if (device->chipset < 0xa0)
-		xf_emit(ctx, 0xa20, 0);	/* 4 x (0x280 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */
-	else if (!IS_NVA3F(device->chipset))
-		xf_emit(ctx, 0x210, 0);	/* ffffffff */
-	else
-		xf_emit(ctx, 0x410, 0);	/* ffffffff */
-	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-	xf_emit(ctx, 1, 4);		/* 000000ff GP_RESULT_MAP_SIZE */
-	xf_emit(ctx, 1, 3);		/* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */
-	xf_emit(ctx, 1, 0);		/* 00000001 PROVOKING_VERTEX_LAST */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */
-}
-
-static void
-nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	int magic1, magic2;
-	if (device->chipset == 0x50) {
-		magic1 = 0x3ff;
-		magic2 = 0x00003e60;
-	} else if (!IS_NVA3F(device->chipset)) {
-		magic1 = 0x7ff;
-		magic2 = 0x001ffe67;
-	} else {
-		magic1 = 0x7ff;
-		magic2 = 0x00087e67;
-	}
-	xf_emit(ctx, 1, 0);		/* 00000007 ALPHA_TEST_FUNC */
-	xf_emit(ctx, 1, 0);		/* ffffffff ALPHA_TEST_REF */
-	xf_emit(ctx, 1, 0);		/* 00000001 ALPHA_TEST_ENABLE */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 1, 1);	/* 0000000f UNK16A0 */
-	xf_emit(ctx, 1, 0);		/* 7/f MULTISAMPLE_SAMPLES_LOG2 */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_MASK */
-	xf_emit(ctx, 3, 0);		/* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */
-	xf_emit(ctx, 4, 0);		/* ffffffff BLEND_COLOR */
-	xf_emit(ctx, 1, 0);		/* 00000001 UNK19C0 */
-	xf_emit(ctx, 1, 0);		/* 00000001 UNK0FDC */
-	xf_emit(ctx, 1, 0xf);		/* 0000000f COLOR_MASK */
-	xf_emit(ctx, 7, 0);		/* 0000000f COLOR_MASK */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 LOGIC_OP_ENABLE */
-	xf_emit(ctx, 1, 0);		/* ff[NV50]/3ff[NV84+] */
-	xf_emit(ctx, 1, 4);		/* 00000007 FP_CONTROL */
-	xf_emit(ctx, 4, 0xffff);	/* 0000ffff MSAA_MASK */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_MASK */
-	xf_emit(ctx, 3, 0);		/* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */
-	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_BACK_ENABLE */
-	xf_emit(ctx, 2, 0);		/* 00007fff WINDOW_OFFSET_XY */
-	xf_emit(ctx, 1, 1);		/* 00000001 tesla UNK19CC */
-	xf_emit(ctx, 1, 0);		/* 7 */
-	xf_emit(ctx, 1, 0);		/* 00000001 SAMPLECNT_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */
-	xf_emit(ctx, 1, 1);		/* 00000001 ZETA_ENABLE */
-	xf_emit(ctx, 1, 0);		/* ffffffff COLOR_KEY */
-	xf_emit(ctx, 1, 0);		/* 00000001 COLOR_KEY_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000007 COLOR_KEY_FORMAT */
-	xf_emit(ctx, 2, 0);		/* ffffffff SIFC_BITMAP_COLOR */
-	xf_emit(ctx, 1, 1);		/* 00000001 SIFC_BITMAP_WRITE_BIT0_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000007 ALPHA_TEST_FUNC */
-	xf_emit(ctx, 1, 0);		/* 00000001 ALPHA_TEST_ENABLE */
-	if (IS_NVA3F(device->chipset)) {
-		xf_emit(ctx, 1, 3);	/* 00000003 tesla UNK16B4 */
-		xf_emit(ctx, 1, 0);	/* 00000003 */
-		xf_emit(ctx, 1, 0);	/* 00000003 tesla UNK1298 */
-	} else if (device->chipset >= 0xa0) {
-		xf_emit(ctx, 1, 1);	/* 00000001 tesla UNK16B4 */
-		xf_emit(ctx, 1, 0);	/* 00000003 */
-	} else {
-		xf_emit(ctx, 1, 0);	/* 00000003 MULTISAMPLE_CTRL */
-	}
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */
-	xf_emit(ctx, 8, 0);		/* 00000001 BLEND_ENABLE */
-	xf_emit(ctx, 1, 1);		/* 0000001f BLEND_FUNC_DST_ALPHA */
-	xf_emit(ctx, 1, 1);		/* 00000007 BLEND_EQUATION_ALPHA */
-	xf_emit(ctx, 1, 2);		/* 0000001f BLEND_FUNC_SRC_ALPHA */
-	xf_emit(ctx, 1, 1);		/* 0000001f BLEND_FUNC_DST_RGB */
-	xf_emit(ctx, 1, 1);		/* 00000007 BLEND_EQUATION_RGB */
-	xf_emit(ctx, 1, 2);		/* 0000001f BLEND_FUNC_SRC_RGB */
-	if (IS_NVA3F(device->chipset)) {
-		xf_emit(ctx, 1, 0);	/* 00000001 UNK12E4 */
-		xf_emit(ctx, 8, 1);	/* 00000007 IBLEND_EQUATION_RGB */
-		xf_emit(ctx, 8, 1);	/* 00000007 IBLEND_EQUATION_ALPHA */
-		xf_emit(ctx, 8, 1);	/* 00000001 IBLEND_UNK00 */
-		xf_emit(ctx, 8, 2);	/* 0000001f IBLEND_SRC_RGB */
-		xf_emit(ctx, 8, 1);	/* 0000001f IBLEND_DST_RGB */
-		xf_emit(ctx, 8, 2);	/* 0000001f IBLEND_SRC_ALPHA */
-		xf_emit(ctx, 8, 1);	/* 0000001f IBLEND_DST_ALPHA */
-		xf_emit(ctx, 1, 0);	/* 00000001 UNK1140 */
-	}
-	xf_emit(ctx, 1, 1);		/* 00000001 UNK133C */
-	xf_emit(ctx, 1, 0);		/* ffff0ff3 */
-	xf_emit(ctx, 1, 0x11);		/* 3f/7f RT_FORMAT */
-	xf_emit(ctx, 7, 0);		/* 3f/7f RT_FORMAT */
-	xf_emit(ctx, 1, 0x0fac6881);	/* 0fffffff RT_CONTROL */
-	xf_emit(ctx, 1, 0);		/* 00000001 LOGIC_OP_ENABLE */
-	xf_emit(ctx, 1, 0);		/* ff/3ff */
-	xf_emit(ctx, 1, 4);		/* 00000007 FP_CONTROL */
-	xf_emit(ctx, 1, 0);		/* 00000003 UNK0F90 */
-	xf_emit(ctx, 1, 0);		/* 00000001 FRAMEBUFFER_SRGB */
-	xf_emit(ctx, 1, 0);		/* 7 */
-	xf_emit(ctx, 1, 0x11);		/* 3f/7f DST_FORMAT */
-	xf_emit(ctx, 1, 1);		/* 00000001 DST_LINEAR */
-	xf_emit(ctx, 1, 0);		/* 00000007 OPERATION */
-	xf_emit(ctx, 1, 0xcf);		/* 000000ff SIFC_FORMAT */
-	xf_emit(ctx, 1, 0xcf);		/* 000000ff DRAW_COLOR_FORMAT */
-	xf_emit(ctx, 1, 0xcf);		/* 000000ff SRC_FORMAT */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 1, 1);	/* 0000001f tesla UNK169C */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */
-	xf_emit(ctx, 1, 0);		/* 7/f[NVA3] MULTISAMPLE_SAMPLES_LOG2 */
-	xf_emit(ctx, 8, 0);		/* 00000001 BLEND_ENABLE */
-	xf_emit(ctx, 1, 1);		/* 0000001f BLEND_FUNC_DST_ALPHA */
-	xf_emit(ctx, 1, 1);		/* 00000007 BLEND_EQUATION_ALPHA */
-	xf_emit(ctx, 1, 2);		/* 0000001f BLEND_FUNC_SRC_ALPHA */
-	xf_emit(ctx, 1, 1);		/* 0000001f BLEND_FUNC_DST_RGB */
-	xf_emit(ctx, 1, 1);		/* 00000007 BLEND_EQUATION_RGB */
-	xf_emit(ctx, 1, 2);		/* 0000001f BLEND_FUNC_SRC_RGB */
-	xf_emit(ctx, 1, 1);		/* 00000001 UNK133C */
-	xf_emit(ctx, 1, 0);		/* ffff0ff3 */
-	xf_emit(ctx, 8, 1);		/* 00000001 UNK19E0 */
-	xf_emit(ctx, 1, 0x11);		/* 3f/7f RT_FORMAT */
-	xf_emit(ctx, 7, 0);		/* 3f/7f RT_FORMAT */
-	xf_emit(ctx, 1, 0x0fac6881);	/* 0fffffff RT_CONTROL */
-	xf_emit(ctx, 1, 0xf);		/* 0000000f COLOR_MASK */
-	xf_emit(ctx, 7, 0);		/* 0000000f COLOR_MASK */
-	xf_emit(ctx, 1, magic2);	/* 001fffff tesla UNK0F78 */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_BOUNDS_EN */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */
-	xf_emit(ctx, 1, 0x11);		/* 3f/7f DST_FORMAT */
-	xf_emit(ctx, 1, 1);		/* 00000001 DST_LINEAR */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 1, 1);	/* 0000001f tesla UNK169C */
-	if (device->chipset == 0x50)
-		xf_emit(ctx, 1, 0);	/* ff */
-	else
-		xf_emit(ctx, 3, 0);	/* 1, 7, 3ff */
-	xf_emit(ctx, 1, 4);		/* 00000007 FP_CONTROL */
-	xf_emit(ctx, 1, 0);		/* 00000003 UNK0F90 */
-	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000007 */
-	xf_emit(ctx, 1, 0);		/* 00000001 SAMPLECNT_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */
-	xf_emit(ctx, 1, 1);		/* 00000001 ZETA_ENABLE */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */
-	xf_emit(ctx, 1, 0);		/* 7/f MULTISAMPLE_SAMPLES_LOG2 */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */
-	xf_emit(ctx, 1, 0);		/* ffff0ff3 */
-	xf_emit(ctx, 1, 0x11);		/* 3f/7f RT_FORMAT */
-	xf_emit(ctx, 7, 0);		/* 3f/7f RT_FORMAT */
-	xf_emit(ctx, 1, 0x0fac6881);	/* 0fffffff RT_CONTROL */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_BOUNDS_EN */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */
-	xf_emit(ctx, 1, 0x11);		/* 3f/7f DST_FORMAT */
-	xf_emit(ctx, 1, 1);		/* 00000001 DST_LINEAR */
-	xf_emit(ctx, 1, 0);		/* 000fffff BLIT_DU_DX_FRACT */
-	xf_emit(ctx, 1, 1);		/* 0001ffff BLIT_DU_DX_INT */
-	xf_emit(ctx, 1, 0);		/* 000fffff BLIT_DV_DY_FRACT */
-	xf_emit(ctx, 1, 1);		/* 0001ffff BLIT_DV_DY_INT */
-	xf_emit(ctx, 1, 0);		/* ff/3ff */
-	xf_emit(ctx, 1, magic1);	/* 3ff/7ff tesla UNK0D68 */
-	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */
-	xf_emit(ctx, 1, 1);		/* 00000001 tesla UNK15B4 */
-	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */
-	xf_emit(ctx, 1, 1);		/* 00000001 ZETA_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000007 */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 1, 1);	/* 0000001f tesla UNK169C */
-	xf_emit(ctx, 8, 0);		/* 0000ffff DMA_COLOR */
-	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_GLOBAL */
-	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_LOCAL */
-	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_STACK */
-	xf_emit(ctx, 1, 0);		/* ff/3ff */
-	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_DST */
-	xf_emit(ctx, 1, 0);		/* 7 */
-	xf_emit(ctx, 1, 0);		/* 7/f MULTISAMPLE_SAMPLES_LOG2 */
-	xf_emit(ctx, 1, 0);		/* ffff0ff3 */
-	xf_emit(ctx, 8, 0);		/* 000000ff RT_ADDRESS_HIGH */
-	xf_emit(ctx, 8, 0);		/* ffffffff RT_LAYER_STRIDE */
-	xf_emit(ctx, 8, 0);		/* ffffffff RT_ADDRESS_LOW */
-	xf_emit(ctx, 8, 8);		/* 0000007f RT_TILE_MODE */
-	xf_emit(ctx, 1, 0x11);		/* 3f/7f RT_FORMAT */
-	xf_emit(ctx, 7, 0);		/* 3f/7f RT_FORMAT */
-	xf_emit(ctx, 1, 0x0fac6881);	/* 0fffffff RT_CONTROL */
-	xf_emit(ctx, 8, 0x400);		/* 0fffffff RT_HORIZ */
-	xf_emit(ctx, 8, 0x300);		/* 0000ffff RT_VERT */
-	xf_emit(ctx, 1, 1);		/* 00001fff RT_ARRAY_MODE */
-	xf_emit(ctx, 1, 0xf);		/* 0000000f COLOR_MASK */
-	xf_emit(ctx, 7, 0);		/* 0000000f COLOR_MASK */
-	xf_emit(ctx, 1, 0x20);		/* 00000fff DST_TILE_MODE */
-	xf_emit(ctx, 1, 0x11);		/* 3f/7f DST_FORMAT */
-	xf_emit(ctx, 1, 0x100);		/* 0001ffff DST_HEIGHT */
-	xf_emit(ctx, 1, 0);		/* 000007ff DST_LAYER */
-	xf_emit(ctx, 1, 1);		/* 00000001 DST_LINEAR */
-	xf_emit(ctx, 1, 0);		/* ffffffff DST_ADDRESS_LOW */
-	xf_emit(ctx, 1, 0);		/* 000000ff DST_ADDRESS_HIGH */
-	xf_emit(ctx, 1, 0x40);		/* 0007ffff DST_PITCH */
-	xf_emit(ctx, 1, 0x100);		/* 0001ffff DST_WIDTH */
-	xf_emit(ctx, 1, 0);		/* 0000ffff */
-	xf_emit(ctx, 1, 3);		/* 00000003 tesla UNK15AC */
-	xf_emit(ctx, 1, 0);		/* ff/3ff */
-	xf_emit(ctx, 1, 0);		/* 0001ffff GP_BUILTIN_RESULT_EN */
-	xf_emit(ctx, 1, 0);		/* 00000003 UNK0F90 */
-	xf_emit(ctx, 1, 0);		/* 00000007 */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 1, 1);	/* 0000001f tesla UNK169C */
-	xf_emit(ctx, 1, magic2);	/* 001fffff tesla UNK0F78 */
-	xf_emit(ctx, 1, 0);		/* 7/f MULTISAMPLE_SAMPLES_LOG2 */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */
-	xf_emit(ctx, 1, 0);		/* ffff0ff3 */
-	xf_emit(ctx, 1, 2);		/* 00000003 tesla UNK143C */
-	xf_emit(ctx, 1, 0x0fac6881);	/* 0fffffff RT_CONTROL */
-	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_ZETA */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_BOUNDS_EN */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */
-	xf_emit(ctx, 2, 0);		/* ffff, ff/3ff */
-	xf_emit(ctx, 1, 0);		/* 0001ffff GP_BUILTIN_RESULT_EN */
-	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_MASK */
-	xf_emit(ctx, 1, 1);		/* 00000001 tesla UNK15B4 */
-	xf_emit(ctx, 1, 0);		/* 00000007 */
-	xf_emit(ctx, 1, 0);		/* ffffffff ZETA_LAYER_STRIDE */
-	xf_emit(ctx, 1, 0);		/* 000000ff ZETA_ADDRESS_HIGH */
-	xf_emit(ctx, 1, 0);		/* ffffffff ZETA_ADDRESS_LOW */
-	xf_emit(ctx, 1, 4);		/* 00000007 ZETA_TILE_MODE */
-	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */
-	xf_emit(ctx, 1, 1);		/* 00000001 ZETA_ENABLE */
-	xf_emit(ctx, 1, 0x400);		/* 0fffffff ZETA_HORIZ */
-	xf_emit(ctx, 1, 0x300);		/* 0000ffff ZETA_VERT */
-	xf_emit(ctx, 1, 0x1001);	/* 00001fff ZETA_ARRAY_MODE */
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */
-	xf_emit(ctx, 1, 0);		/* 7/f MULTISAMPLE_SAMPLES_LOG2 */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 1, 0);	/* 00000001 */
-	xf_emit(ctx, 1, 0);		/* ffff0ff3 */
-	xf_emit(ctx, 1, 0x11);		/* 3f/7f RT_FORMAT */
-	xf_emit(ctx, 7, 0);		/* 3f/7f RT_FORMAT */
-	xf_emit(ctx, 1, 0x0fac6881);	/* 0fffffff RT_CONTROL */
-	xf_emit(ctx, 1, 0xf);		/* 0000000f COLOR_MASK */
-	xf_emit(ctx, 7, 0);		/* 0000000f COLOR_MASK */
-	xf_emit(ctx, 1, 0);		/* ff/3ff */
-	xf_emit(ctx, 8, 0);		/* 00000001 BLEND_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000003 UNK0F90 */
-	xf_emit(ctx, 1, 0);		/* 00000001 FRAMEBUFFER_SRGB */
-	xf_emit(ctx, 1, 0);		/* 7 */
-	xf_emit(ctx, 1, 0);		/* 00000001 LOGIC_OP_ENABLE */
-	if (IS_NVA3F(device->chipset)) {
-		xf_emit(ctx, 1, 0);	/* 00000001 UNK1140 */
-		xf_emit(ctx, 1, 1);	/* 0000001f tesla UNK169C */
-	}
-	xf_emit(ctx, 1, 0);		/* 7/f MULTISAMPLE_SAMPLES_LOG2 */
-	xf_emit(ctx, 1, 0);		/* 00000001 UNK1534 */
-	xf_emit(ctx, 1, 0);		/* ffff0ff3 */
-	if (device->chipset >= 0xa0)
-		xf_emit(ctx, 1, 0x0fac6881);	/* fffffff */
-	xf_emit(ctx, 1, magic2);	/* 001fffff tesla UNK0F78 */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_BOUNDS_EN */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */
-	xf_emit(ctx, 1, 0x11);		/* 3f/7f DST_FORMAT */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK0FB0 */
-	xf_emit(ctx, 1, 0);		/* ff/3ff */
-	xf_emit(ctx, 1, 4);		/* 00000007 FP_CONTROL */
-	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */
-	xf_emit(ctx, 1, 1);		/* 00000001 tesla UNK15B4 */
-	xf_emit(ctx, 1, 1);		/* 00000001 tesla UNK19CC */
-	xf_emit(ctx, 1, 0);		/* 00000007 */
-	xf_emit(ctx, 1, 0);		/* 00000001 SAMPLECNT_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */
-	xf_emit(ctx, 1, 1);		/* 00000001 ZETA_ENABLE */
-	if (IS_NVA3F(device->chipset)) {
-		xf_emit(ctx, 1, 1);	/* 0000001f tesla UNK169C */
-		xf_emit(ctx, 1, 0);	/* 0000000f tesla UNK15C8 */
-	}
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */
-	if (device->chipset >= 0xa0) {
-		xf_emit(ctx, 3, 0);		/* 7/f, 1, ffff0ff3 */
-		xf_emit(ctx, 1, 0xfac6881);	/* fffffff */
-		xf_emit(ctx, 4, 0);		/* 1, 1, 1, 3ff */
-		xf_emit(ctx, 1, 4);		/* 7 */
-		xf_emit(ctx, 1, 0);		/* 1 */
-		xf_emit(ctx, 2, 1);		/* 1 */
-		xf_emit(ctx, 2, 0);		/* 7, f */
-		xf_emit(ctx, 1, 1);		/* 1 */
-		xf_emit(ctx, 1, 0);		/* 7/f */
-		if (IS_NVA3F(device->chipset))
-			xf_emit(ctx, 0x9, 0);	/* 1 */
-		else
-			xf_emit(ctx, 0x8, 0);	/* 1 */
-		xf_emit(ctx, 1, 0);		/* ffff0ff3 */
-		xf_emit(ctx, 8, 1);		/* 1 */
-		xf_emit(ctx, 1, 0x11);		/* 7f */
-		xf_emit(ctx, 7, 0);		/* 7f */
-		xf_emit(ctx, 1, 0xfac6881);	/* fffffff */
-		xf_emit(ctx, 1, 0xf);		/* f */
-		xf_emit(ctx, 7, 0);		/* f */
-		xf_emit(ctx, 1, 0x11);		/* 7f */
-		xf_emit(ctx, 1, 1);		/* 1 */
-		xf_emit(ctx, 5, 0);		/* 1, 7, 3ff, 3, 7 */
-		if (IS_NVA3F(device->chipset)) {
-			xf_emit(ctx, 1, 0);	/* 00000001 UNK1140 */
-			xf_emit(ctx, 1, 1);	/* 0000001f tesla UNK169C */
-		}
-	}
-}
-
-static void
-nv50_graph_construct_xfer_tex(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	xf_emit(ctx, 2, 0);		/* 1 LINKED_TSC. yes, 2. */
-	if (device->chipset != 0x50)
-		xf_emit(ctx, 1, 0);	/* 3 */
-	xf_emit(ctx, 1, 1);		/* 1ffff BLIT_DU_DX_INT */
-	xf_emit(ctx, 1, 0);		/* fffff BLIT_DU_DX_FRACT */
-	xf_emit(ctx, 1, 1);		/* 1ffff BLIT_DV_DY_INT */
-	xf_emit(ctx, 1, 0);		/* fffff BLIT_DV_DY_FRACT */
-	if (device->chipset == 0x50)
-		xf_emit(ctx, 1, 0);	/* 3 BLIT_CONTROL */
-	else
-		xf_emit(ctx, 2, 0);	/* 3ff, 1 */
-	xf_emit(ctx, 1, 0x2a712488);	/* ffffffff SRC_TIC_0 */
-	xf_emit(ctx, 1, 0);		/* ffffffff SRC_TIC_1 */
-	xf_emit(ctx, 1, 0x4085c000);	/* ffffffff SRC_TIC_2 */
-	xf_emit(ctx, 1, 0x40);		/* ffffffff SRC_TIC_3 */
-	xf_emit(ctx, 1, 0x100);		/* ffffffff SRC_TIC_4 */
-	xf_emit(ctx, 1, 0x10100);	/* ffffffff SRC_TIC_5 */
-	xf_emit(ctx, 1, 0x02800000);	/* ffffffff SRC_TIC_6 */
-	xf_emit(ctx, 1, 0);		/* ffffffff SRC_TIC_7 */
-	if (device->chipset == 0x50) {
-		xf_emit(ctx, 1, 0);	/* 00000001 turing UNK358 */
-		xf_emit(ctx, 1, 0);	/* ffffffff tesla UNK1A34? */
-		xf_emit(ctx, 1, 0);	/* 00000003 turing UNK37C tesla UNK1690 */
-		xf_emit(ctx, 1, 0);	/* 00000003 BLIT_CONTROL */
-		xf_emit(ctx, 1, 0);	/* 00000001 turing UNK32C tesla UNK0F94 */
-	} else if (!IS_NVAAF(device->chipset)) {
-		xf_emit(ctx, 1, 0);	/* ffffffff tesla UNK1A34? */
-		xf_emit(ctx, 1, 0);	/* 00000003 */
-		xf_emit(ctx, 1, 0);	/* 000003ff */
-		xf_emit(ctx, 1, 0);	/* 00000003 */
-		xf_emit(ctx, 1, 0);	/* 000003ff */
-		xf_emit(ctx, 1, 0);	/* 00000003 tesla UNK1664 / turing UNK03E8 */
-		xf_emit(ctx, 1, 0);	/* 00000003 */
-		xf_emit(ctx, 1, 0);	/* 000003ff */
-	} else {
-		xf_emit(ctx, 0x6, 0);
-	}
-	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A34 */
-	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_TEXTURE */
-	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_SRC */
-}
-
-static void
-nv50_graph_construct_xfer_unk8cxx(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	xf_emit(ctx, 1, 0);		/* 00000001 UNK1534 */
-	xf_emit(ctx, 1, 0);		/* 7/f MULTISAMPLE_SAMPLES_LOG2 */
-	xf_emit(ctx, 2, 0);		/* 7, ffff0ff3 */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE */
-	xf_emit(ctx, 1, 0x04e3bfdf);	/* ffffffff UNK0D64 */
-	xf_emit(ctx, 1, 0x04e3bfdf);	/* ffffffff UNK0DF4 */
-	xf_emit(ctx, 1, 1);		/* 00000001 UNK15B4 */
-	xf_emit(ctx, 1, 0);		/* 00000001 LINE_STIPPLE_ENABLE */
-	xf_emit(ctx, 1, 0x00ffff00);	/* 00ffffff LINE_STIPPLE_PATTERN */
-	xf_emit(ctx, 1, 1);		/* 00000001 tesla UNK0F98 */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 1, 1);	/* 0000001f tesla UNK169C */
-	xf_emit(ctx, 1, 0);		/* 00000003 tesla UNK1668 */
-	xf_emit(ctx, 1, 0);		/* 00000001 LINE_STIPPLE_ENABLE */
-	xf_emit(ctx, 1, 0x00ffff00);	/* 00ffffff LINE_STIPPLE_PATTERN */
-	xf_emit(ctx, 1, 0);		/* 00000001 POLYGON_SMOOTH_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 UNK1534 */
-	xf_emit(ctx, 1, 0);		/* 7/f MULTISAMPLE_SAMPLES_LOG2 */
-	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1658 */
-	xf_emit(ctx, 1, 0);		/* 00000001 LINE_SMOOTH_ENABLE */
-	xf_emit(ctx, 1, 0);		/* ffff0ff3 */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */
-	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE */
-	xf_emit(ctx, 1, 1);		/* 00000001 UNK15B4 */
-	xf_emit(ctx, 1, 0);		/* 00000001 POINT_SPRITE_ENABLE */
-	xf_emit(ctx, 1, 1);		/* 00000001 tesla UNK165C */
-	xf_emit(ctx, 1, 0x30201000);	/* ffffffff tesla UNK1670 */
-	xf_emit(ctx, 1, 0x70605040);	/* ffffffff tesla UNK1670 */
-	xf_emit(ctx, 1, 0xb8a89888);	/* ffffffff tesla UNK1670 */
-	xf_emit(ctx, 1, 0xf8e8d8c8);	/* ffffffff tesla UNK1670 */
-	xf_emit(ctx, 1, 0);		/* 00000001 VERTEX_TWO_SIDE_ENABLE */
-	xf_emit(ctx, 1, 0x1a);		/* 0000001f POLYGON_MODE */
-}
-
-static void
-nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	if (device->chipset < 0xa0) {
-		nv50_graph_construct_xfer_unk84xx(ctx);
-		nv50_graph_construct_xfer_tprop(ctx);
-		nv50_graph_construct_xfer_tex(ctx);
-		nv50_graph_construct_xfer_unk8cxx(ctx);
-	} else {
-		nv50_graph_construct_xfer_tex(ctx);
-		nv50_graph_construct_xfer_tprop(ctx);
-		nv50_graph_construct_xfer_unk8cxx(ctx);
-		nv50_graph_construct_xfer_unk84xx(ctx);
-	}
-}
-
-static void
-nv50_graph_construct_xfer_mpc(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	int i, mpcnt = 2;
-	switch (device->chipset) {
-		case 0x98:
-		case 0xaa:
-			mpcnt = 1;
-			break;
-		case 0x50:
-		case 0x84:
-		case 0x86:
-		case 0x92:
-		case 0x94:
-		case 0x96:
-		case 0xa8:
-		case 0xac:
-			mpcnt = 2;
-			break;
-		case 0xa0:
-		case 0xa3:
-		case 0xa5:
-		case 0xaf:
-			mpcnt = 3;
-			break;
-	}
-	for (i = 0; i < mpcnt; i++) {
-		xf_emit(ctx, 1, 0);		/* ff */
-		xf_emit(ctx, 1, 0x80);		/* ffffffff tesla UNK1404 */
-		xf_emit(ctx, 1, 0x80007004);	/* ffffffff tesla UNK12B0 */
-		xf_emit(ctx, 1, 0x04000400);	/* ffffffff */
-		if (device->chipset >= 0xa0)
-			xf_emit(ctx, 1, 0xc0);	/* 00007fff tesla UNK152C */
-		xf_emit(ctx, 1, 0x1000);	/* 0000ffff tesla UNK0D60 */
-		xf_emit(ctx, 1, 0);		/* ff/3ff */
-		xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */
-		if (device->chipset == 0x86 || device->chipset == 0x98 || device->chipset == 0xa8 || IS_NVAAF(device->chipset)) {
-			xf_emit(ctx, 1, 0xe00);		/* 7fff */
-			xf_emit(ctx, 1, 0x1e00);	/* 7fff */
-		}
-		xf_emit(ctx, 1, 1);		/* 000000ff VP_REG_ALLOC_TEMP */
-		xf_emit(ctx, 1, 0);		/* 00000001 LINKED_TSC */
-		xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-		if (device->chipset == 0x50)
-			xf_emit(ctx, 2, 0x1000);	/* 7fff tesla UNK141C */
-		xf_emit(ctx, 1, 1);		/* 000000ff GP_REG_ALLOC_TEMP */
-		xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */
-		xf_emit(ctx, 1, 4);		/* 000000ff FP_REG_ALLOC_TEMP */
-		xf_emit(ctx, 1, 2);		/* 00000003 REG_MODE */
-		if (IS_NVAAF(device->chipset))
-			xf_emit(ctx, 0xb, 0);	/* RO */
-		else if (device->chipset >= 0xa0)
-			xf_emit(ctx, 0xc, 0);	/* RO */
-		else
-			xf_emit(ctx, 0xa, 0);	/* RO */
-	}
-	xf_emit(ctx, 1, 0x08100c12);		/* 1fffffff FP_INTERPOLANT_CTRL */
-	xf_emit(ctx, 1, 0);			/* ff/3ff */
-	if (device->chipset >= 0xa0) {
-		xf_emit(ctx, 1, 0x1fe21);	/* 0003ffff tesla UNK0FAC */
-	}
-	xf_emit(ctx, 3, 0);			/* 7fff, 0, 0 */
-	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK1534 */
-	xf_emit(ctx, 1, 0);			/* 7/f MULTISAMPLE_SAMPLES_LOG2 */
-	xf_emit(ctx, 4, 0xffff);		/* 0000ffff MSAA_MASK */
-	xf_emit(ctx, 1, 1);			/* 00000001 LANES32 */
-	xf_emit(ctx, 1, 0x10001);		/* 00ffffff BLOCK_ALLOC */
-	xf_emit(ctx, 1, 0x10001);		/* ffffffff BLOCKDIM_XY */
-	xf_emit(ctx, 1, 1);			/* 0000ffff BLOCKDIM_Z */
-	xf_emit(ctx, 1, 0);			/* ffffffff SHARED_SIZE */
-	xf_emit(ctx, 1, 0x1fe21);		/* 1ffff/3ffff[NVA0+] tesla UNk0FAC */
-	xf_emit(ctx, 1, 0);			/* ffffffff tesla UNK1A34 */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 1, 1);		/* 0000001f tesla UNK169C */
-	xf_emit(ctx, 1, 0);			/* ff/3ff */
-	xf_emit(ctx, 1, 0);			/* 1 LINKED_TSC */
-	xf_emit(ctx, 1, 0);			/* ff FP_ADDRESS_HIGH */
-	xf_emit(ctx, 1, 0);			/* ffffffff FP_ADDRESS_LOW */
-	xf_emit(ctx, 1, 0x08100c12);		/* 1fffffff FP_INTERPOLANT_CTRL */
-	xf_emit(ctx, 1, 4);			/* 00000007 FP_CONTROL */
-	xf_emit(ctx, 1, 0);			/* 000000ff FRAG_COLOR_CLAMP_EN */
-	xf_emit(ctx, 1, 2);			/* 00000003 REG_MODE */
-	xf_emit(ctx, 1, 0x11);			/* 0000007f RT_FORMAT */
-	xf_emit(ctx, 7, 0);			/* 0000007f RT_FORMAT */
-	xf_emit(ctx, 1, 0);			/* 00000007 */
-	xf_emit(ctx, 1, 0xfac6881);		/* 0fffffff RT_CONTROL */
-	xf_emit(ctx, 1, 0);			/* 00000003 MULTISAMPLE_CTRL */
-	if (IS_NVA3F(device->chipset))
-		xf_emit(ctx, 1, 3);		/* 00000003 tesla UNK16B4 */
-	xf_emit(ctx, 1, 0);			/* 00000001 ALPHA_TEST_ENABLE */
-	xf_emit(ctx, 1, 0);			/* 00000007 ALPHA_TEST_FUNC */
-	xf_emit(ctx, 1, 0);			/* 00000001 FRAMEBUFFER_SRGB */
-	xf_emit(ctx, 1, 4);			/* ffffffff tesla UNK1400 */
-	xf_emit(ctx, 8, 0);			/* 00000001 BLEND_ENABLE */
-	xf_emit(ctx, 1, 0);			/* 00000001 LOGIC_OP_ENABLE */
-	xf_emit(ctx, 1, 2);			/* 0000001f BLEND_FUNC_SRC_RGB */
-	xf_emit(ctx, 1, 1);			/* 0000001f BLEND_FUNC_DST_RGB */
-	xf_emit(ctx, 1, 1);			/* 00000007 BLEND_EQUATION_RGB */
-	xf_emit(ctx, 1, 2);			/* 0000001f BLEND_FUNC_SRC_ALPHA */
-	xf_emit(ctx, 1, 1);			/* 0000001f BLEND_FUNC_DST_ALPHA */
-	xf_emit(ctx, 1, 1);			/* 00000007 BLEND_EQUATION_ALPHA */
-	xf_emit(ctx, 1, 1);			/* 00000001 UNK133C */
-	if (IS_NVA3F(device->chipset)) {
-		xf_emit(ctx, 1, 0);		/* 00000001 UNK12E4 */
-		xf_emit(ctx, 8, 2);		/* 0000001f IBLEND_FUNC_SRC_RGB */
-		xf_emit(ctx, 8, 1);		/* 0000001f IBLEND_FUNC_DST_RGB */
-		xf_emit(ctx, 8, 1);		/* 00000007 IBLEND_EQUATION_RGB */
-		xf_emit(ctx, 8, 2);		/* 0000001f IBLEND_FUNC_SRC_ALPHA */
-		xf_emit(ctx, 8, 1);		/* 0000001f IBLEND_FUNC_DST_ALPHA */
-		xf_emit(ctx, 8, 1);		/* 00000007 IBLEND_EQUATION_ALPHA */
-		xf_emit(ctx, 8, 1);		/* 00000001 IBLEND_UNK00 */
-		xf_emit(ctx, 1, 0);		/* 00000003 tesla UNK1928 */
-		xf_emit(ctx, 1, 0);		/* 00000001 UNK1140 */
-	}
-	xf_emit(ctx, 1, 0);			/* 00000003 tesla UNK0F90 */
-	xf_emit(ctx, 1, 4);			/* 000000ff FP_RESULT_COUNT */
-	/* XXX: demagic this part some day */
-	if (device->chipset == 0x50)
-		xf_emit(ctx, 0x3a0, 0);
-	else if (device->chipset < 0x94)
-		xf_emit(ctx, 0x3a2, 0);
-	else if (device->chipset == 0x98 || device->chipset == 0xaa)
-		xf_emit(ctx, 0x39f, 0);
-	else
-		xf_emit(ctx, 0x3a3, 0);
-	xf_emit(ctx, 1, 0x11);			/* 3f/7f DST_FORMAT */
-	xf_emit(ctx, 1, 0);			/* 7 OPERATION */
-	xf_emit(ctx, 1, 1);			/* 1 DST_LINEAR */
-	xf_emit(ctx, 0x2d, 0);
-}
-
-static void
-nv50_graph_construct_xfer2(struct nouveau_grctx *ctx)
-{
-	struct nouveau_device *device = ctx->device;
-	int i;
-	u32 offset;
-	u32 units = nv_rd32 (ctx->device, 0x1540);
-	int size = 0;
-
-	offset = (ctx->ctxvals_pos+0x3f)&~0x3f;
-
-	if (device->chipset < 0xa0) {
-		for (i = 0; i < 8; i++) {
-			ctx->ctxvals_pos = offset + i;
-			/* that little bugger belongs to csched. No idea
-			 * what it's doing here. */
-			if (i == 0)
-				xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */
-			if (units & (1 << i))
-				nv50_graph_construct_xfer_mpc(ctx);
-			if ((ctx->ctxvals_pos-offset)/8 > size)
-				size = (ctx->ctxvals_pos-offset)/8;
-		}
-	} else {
-		/* Strand 0: TPs 0, 1 */
-		ctx->ctxvals_pos = offset;
-		/* that little bugger belongs to csched. No idea
-		 * what it's doing here. */
-		xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */
-		if (units & (1 << 0))
-			nv50_graph_construct_xfer_mpc(ctx);
-		if (units & (1 << 1))
-			nv50_graph_construct_xfer_mpc(ctx);
-		if ((ctx->ctxvals_pos-offset)/8 > size)
-			size = (ctx->ctxvals_pos-offset)/8;
-
-		/* Strand 1: TPs 2, 3 */
-		ctx->ctxvals_pos = offset + 1;
-		if (units & (1 << 2))
-			nv50_graph_construct_xfer_mpc(ctx);
-		if (units & (1 << 3))
-			nv50_graph_construct_xfer_mpc(ctx);
-		if ((ctx->ctxvals_pos-offset)/8 > size)
-			size = (ctx->ctxvals_pos-offset)/8;
-
-		/* Strand 2: TPs 4, 5, 6 */
-		ctx->ctxvals_pos = offset + 2;
-		if (units & (1 << 4))
-			nv50_graph_construct_xfer_mpc(ctx);
-		if (units & (1 << 5))
-			nv50_graph_construct_xfer_mpc(ctx);
-		if (units & (1 << 6))
-			nv50_graph_construct_xfer_mpc(ctx);
-		if ((ctx->ctxvals_pos-offset)/8 > size)
-			size = (ctx->ctxvals_pos-offset)/8;
-
-		/* Strand 3: TPs 7, 8, 9 */
-		ctx->ctxvals_pos = offset + 3;
-		if (units & (1 << 7))
-			nv50_graph_construct_xfer_mpc(ctx);
-		if (units & (1 << 8))
-			nv50_graph_construct_xfer_mpc(ctx);
-		if (units & (1 << 9))
-			nv50_graph_construct_xfer_mpc(ctx);
-		if ((ctx->ctxvals_pos-offset)/8 > size)
-			size = (ctx->ctxvals_pos-offset)/8;
-	}
-	ctx->ctxvals_pos = offset + size * 8;
-	ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f;
-	cp_lsr (ctx, offset);
-	cp_out (ctx, CP_SET_XFER_POINTER);
-	cp_lsr (ctx, size);
-	cp_out (ctx, CP_SEEK_2);
-	cp_out (ctx, CP_XFER_2);
-	cp_wait(ctx, XFER, BUSY);
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
deleted file mode 100644
index b8e5fe60a1eb..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
+++ /dev/null
@@ -1,1386 +0,0 @@
-/*
- * Copyright 2010 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * PGRAPH context register lists
- ******************************************************************************/
-
-static const struct nvc0_graph_init
-nvc0_grctx_init_icmd_0[] = {
-	{ 0x001000,   1, 0x01, 0x00000004 },
-	{ 0x0000a9,   1, 0x01, 0x0000ffff },
-	{ 0x000038,   1, 0x01, 0x0fac6881 },
-	{ 0x00003d,   1, 0x01, 0x00000001 },
-	{ 0x0000e8,   8, 0x01, 0x00000400 },
-	{ 0x000078,   8, 0x01, 0x00000300 },
-	{ 0x000050,   1, 0x01, 0x00000011 },
-	{ 0x000058,   8, 0x01, 0x00000008 },
-	{ 0x000208,   8, 0x01, 0x00000001 },
-	{ 0x000081,   1, 0x01, 0x00000001 },
-	{ 0x000085,   1, 0x01, 0x00000004 },
-	{ 0x000088,   1, 0x01, 0x00000400 },
-	{ 0x000090,   1, 0x01, 0x00000300 },
-	{ 0x000098,   1, 0x01, 0x00001001 },
-	{ 0x0000e3,   1, 0x01, 0x00000001 },
-	{ 0x0000da,   1, 0x01, 0x00000001 },
-	{ 0x0000f8,   1, 0x01, 0x00000003 },
-	{ 0x0000fa,   1, 0x01, 0x00000001 },
-	{ 0x00009f,   4, 0x01, 0x0000ffff },
-	{ 0x0000b1,   1, 0x01, 0x00000001 },
-	{ 0x0000b2,  40, 0x01, 0x00000000 },
-	{ 0x000210,   8, 0x01, 0x00000040 },
-	{ 0x000218,   8, 0x01, 0x0000c080 },
-	{ 0x0000ad,   1, 0x01, 0x0000013e },
-	{ 0x0000e1,   1, 0x01, 0x00000010 },
-	{ 0x000290,  16, 0x01, 0x00000000 },
-	{ 0x0003b0,  16, 0x01, 0x00000000 },
-	{ 0x0002a0,  16, 0x01, 0x00000000 },
-	{ 0x000420,  16, 0x01, 0x00000000 },
-	{ 0x0002b0,  16, 0x01, 0x00000000 },
-	{ 0x000430,  16, 0x01, 0x00000000 },
-	{ 0x0002c0,  16, 0x01, 0x00000000 },
-	{ 0x0004d0,  16, 0x01, 0x00000000 },
-	{ 0x000720,  16, 0x01, 0x00000000 },
-	{ 0x0008c0,  16, 0x01, 0x00000000 },
-	{ 0x000890,  16, 0x01, 0x00000000 },
-	{ 0x0008e0,  16, 0x01, 0x00000000 },
-	{ 0x0008a0,  16, 0x01, 0x00000000 },
-	{ 0x0008f0,  16, 0x01, 0x00000000 },
-	{ 0x00094c,   1, 0x01, 0x000000ff },
-	{ 0x00094d,   1, 0x01, 0xffffffff },
-	{ 0x00094e,   1, 0x01, 0x00000002 },
-	{ 0x0002ec,   1, 0x01, 0x00000001 },
-	{ 0x000303,   1, 0x01, 0x00000001 },
-	{ 0x0002e6,   1, 0x01, 0x00000001 },
-	{ 0x000466,   1, 0x01, 0x00000052 },
-	{ 0x000301,   1, 0x01, 0x3f800000 },
-	{ 0x000304,   1, 0x01, 0x30201000 },
-	{ 0x000305,   1, 0x01, 0x70605040 },
-	{ 0x000306,   1, 0x01, 0xb8a89888 },
-	{ 0x000307,   1, 0x01, 0xf8e8d8c8 },
-	{ 0x00030a,   1, 0x01, 0x00ffff00 },
-	{ 0x00030b,   1, 0x01, 0x0000001a },
-	{ 0x00030c,   1, 0x01, 0x00000001 },
-	{ 0x000318,   1, 0x01, 0x00000001 },
-	{ 0x000340,   1, 0x01, 0x00000000 },
-	{ 0x000375,   1, 0x01, 0x00000001 },
-	{ 0x000351,   1, 0x01, 0x00000100 },
-	{ 0x00037d,   1, 0x01, 0x00000006 },
-	{ 0x0003a0,   1, 0x01, 0x00000002 },
-	{ 0x0003aa,   1, 0x01, 0x00000001 },
-	{ 0x0003a9,   1, 0x01, 0x00000001 },
-	{ 0x000380,   1, 0x01, 0x00000001 },
-	{ 0x000360,   1, 0x01, 0x00000040 },
-	{ 0x000366,   2, 0x01, 0x00000000 },
-	{ 0x000368,   1, 0x01, 0x00001fff },
-	{ 0x000370,   2, 0x01, 0x00000000 },
-	{ 0x000372,   1, 0x01, 0x003fffff },
-	{ 0x00037a,   1, 0x01, 0x00000012 },
-	{ 0x0005e0,   5, 0x01, 0x00000022 },
-	{ 0x000619,   1, 0x01, 0x00000003 },
-	{ 0x000811,   1, 0x01, 0x00000003 },
-	{ 0x000812,   1, 0x01, 0x00000004 },
-	{ 0x000813,   1, 0x01, 0x00000006 },
-	{ 0x000814,   1, 0x01, 0x00000008 },
-	{ 0x000815,   1, 0x01, 0x0000000b },
-	{ 0x000800,   6, 0x01, 0x00000001 },
-	{ 0x000632,   1, 0x01, 0x00000001 },
-	{ 0x000633,   1, 0x01, 0x00000002 },
-	{ 0x000634,   1, 0x01, 0x00000003 },
-	{ 0x000635,   1, 0x01, 0x00000004 },
-	{ 0x000654,   1, 0x01, 0x3f800000 },
-	{ 0x000657,   1, 0x01, 0x3f800000 },
-	{ 0x000655,   2, 0x01, 0x3f800000 },
-	{ 0x0006cd,   1, 0x01, 0x3f800000 },
-	{ 0x0007f5,   1, 0x01, 0x3f800000 },
-	{ 0x0007dc,   1, 0x01, 0x39291909 },
-	{ 0x0007dd,   1, 0x01, 0x79695949 },
-	{ 0x0007de,   1, 0x01, 0xb9a99989 },
-	{ 0x0007df,   1, 0x01, 0xf9e9d9c9 },
-	{ 0x0007e8,   1, 0x01, 0x00003210 },
-	{ 0x0007e9,   1, 0x01, 0x00007654 },
-	{ 0x0007ea,   1, 0x01, 0x00000098 },
-	{ 0x0007ec,   1, 0x01, 0x39291909 },
-	{ 0x0007ed,   1, 0x01, 0x79695949 },
-	{ 0x0007ee,   1, 0x01, 0xb9a99989 },
-	{ 0x0007ef,   1, 0x01, 0xf9e9d9c9 },
-	{ 0x0007f0,   1, 0x01, 0x00003210 },
-	{ 0x0007f1,   1, 0x01, 0x00007654 },
-	{ 0x0007f2,   1, 0x01, 0x00000098 },
-	{ 0x0005a5,   1, 0x01, 0x00000001 },
-	{ 0x000980, 128, 0x01, 0x00000000 },
-	{ 0x000468,   1, 0x01, 0x00000004 },
-	{ 0x00046c,   1, 0x01, 0x00000001 },
-	{ 0x000470,  96, 0x01, 0x00000000 },
-	{ 0x000510,  16, 0x01, 0x3f800000 },
-	{ 0x000520,   1, 0x01, 0x000002b6 },
-	{ 0x000529,   1, 0x01, 0x00000001 },
-	{ 0x000530,  16, 0x01, 0xffff0000 },
-	{ 0x000585,   1, 0x01, 0x0000003f },
-	{ 0x000576,   1, 0x01, 0x00000003 },
-	{ 0x000586,   1, 0x01, 0x00000040 },
-	{ 0x000582,   2, 0x01, 0x00000080 },
-	{ 0x0005c2,   1, 0x01, 0x00000001 },
-	{ 0x000638,   2, 0x01, 0x00000001 },
-	{ 0x00063a,   1, 0x01, 0x00000002 },
-	{ 0x00063b,   2, 0x01, 0x00000001 },
-	{ 0x00063d,   1, 0x01, 0x00000002 },
-	{ 0x00063e,   1, 0x01, 0x00000001 },
-	{ 0x0008b8,   8, 0x01, 0x00000001 },
-	{ 0x000900,   8, 0x01, 0x00000001 },
-	{ 0x000908,   8, 0x01, 0x00000002 },
-	{ 0x000910,  16, 0x01, 0x00000001 },
-	{ 0x000920,   8, 0x01, 0x00000002 },
-	{ 0x000928,   8, 0x01, 0x00000001 },
-	{ 0x000648,   9, 0x01, 0x00000001 },
-	{ 0x000658,   1, 0x01, 0x0000000f },
-	{ 0x0007ff,   1, 0x01, 0x0000000a },
-	{ 0x00066a,   1, 0x01, 0x40000000 },
-	{ 0x00066b,   1, 0x01, 0x10000000 },
-	{ 0x00066c,   2, 0x01, 0xffff0000 },
-	{ 0x0007af,   2, 0x01, 0x00000008 },
-	{ 0x0007f6,   1, 0x01, 0x00000001 },
-	{ 0x0006b2,   1, 0x01, 0x00000055 },
-	{ 0x0007ad,   1, 0x01, 0x00000003 },
-	{ 0x000937,   1, 0x01, 0x00000001 },
-	{ 0x000971,   1, 0x01, 0x00000008 },
-	{ 0x000972,   1, 0x01, 0x00000040 },
-	{ 0x000973,   1, 0x01, 0x0000012c },
-	{ 0x00097c,   1, 0x01, 0x00000040 },
-	{ 0x000979,   1, 0x01, 0x00000003 },
-	{ 0x000975,   1, 0x01, 0x00000020 },
-	{ 0x000976,   1, 0x01, 0x00000001 },
-	{ 0x000977,   1, 0x01, 0x00000020 },
-	{ 0x000978,   1, 0x01, 0x00000001 },
-	{ 0x000957,   1, 0x01, 0x00000003 },
-	{ 0x00095e,   1, 0x01, 0x20164010 },
-	{ 0x00095f,   1, 0x01, 0x00000020 },
-	{ 0x000683,   1, 0x01, 0x00000006 },
-	{ 0x000685,   1, 0x01, 0x003fffff },
-	{ 0x000687,   1, 0x01, 0x00000c48 },
-	{ 0x0006a0,   1, 0x01, 0x00000005 },
-	{ 0x000840,   1, 0x01, 0x00300008 },
-	{ 0x000841,   1, 0x01, 0x04000080 },
-	{ 0x000842,   1, 0x01, 0x00300008 },
-	{ 0x000843,   1, 0x01, 0x04000080 },
-	{ 0x000818,   8, 0x01, 0x00000000 },
-	{ 0x000848,  16, 0x01, 0x00000000 },
-	{ 0x000738,   1, 0x01, 0x00000000 },
-	{ 0x0006aa,   1, 0x01, 0x00000001 },
-	{ 0x0006ab,   1, 0x01, 0x00000002 },
-	{ 0x0006ac,   1, 0x01, 0x00000080 },
-	{ 0x0006ad,   2, 0x01, 0x00000100 },
-	{ 0x0006b1,   1, 0x01, 0x00000011 },
-	{ 0x0006bb,   1, 0x01, 0x000000cf },
-	{ 0x0006ce,   1, 0x01, 0x2a712488 },
-	{ 0x000739,   1, 0x01, 0x4085c000 },
-	{ 0x00073a,   1, 0x01, 0x00000080 },
-	{ 0x000786,   1, 0x01, 0x80000100 },
-	{ 0x00073c,   1, 0x01, 0x00010100 },
-	{ 0x00073d,   1, 0x01, 0x02800000 },
-	{ 0x000787,   1, 0x01, 0x000000cf },
-	{ 0x00078c,   1, 0x01, 0x00000008 },
-	{ 0x000792,   1, 0x01, 0x00000001 },
-	{ 0x000794,   3, 0x01, 0x00000001 },
-	{ 0x000797,   1, 0x01, 0x000000cf },
-	{ 0x000836,   1, 0x01, 0x00000001 },
-	{ 0x00079a,   1, 0x01, 0x00000002 },
-	{ 0x000833,   1, 0x01, 0x04444480 },
-	{ 0x0007a1,   1, 0x01, 0x00000001 },
-	{ 0x0007a3,   3, 0x01, 0x00000001 },
-	{ 0x000831,   1, 0x01, 0x00000004 },
-	{ 0x00080c,   1, 0x01, 0x00000002 },
-	{ 0x00080d,   2, 0x01, 0x00000100 },
-	{ 0x00080f,   1, 0x01, 0x00000001 },
-	{ 0x000823,   1, 0x01, 0x00000002 },
-	{ 0x000824,   2, 0x01, 0x00000100 },
-	{ 0x000826,   1, 0x01, 0x00000001 },
-	{ 0x00095d,   1, 0x01, 0x00000001 },
-	{ 0x00082b,   1, 0x01, 0x00000004 },
-	{ 0x000942,   1, 0x01, 0x00010001 },
-	{ 0x000943,   1, 0x01, 0x00000001 },
-	{ 0x000944,   1, 0x01, 0x00000022 },
-	{ 0x0007c5,   1, 0x01, 0x00010001 },
-	{ 0x000834,   1, 0x01, 0x00000001 },
-	{ 0x0007c7,   1, 0x01, 0x00000001 },
-	{ 0x00c1b0,   8, 0x01, 0x0000000f },
-	{ 0x00c1b8,   1, 0x01, 0x0fac6881 },
-	{ 0x00c1b9,   1, 0x01, 0x00fac688 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000002 },
-	{ 0x0006aa,   1, 0x01, 0x00000001 },
-	{ 0x0006ad,   2, 0x01, 0x00000100 },
-	{ 0x0006b1,   1, 0x01, 0x00000011 },
-	{ 0x00078c,   1, 0x01, 0x00000008 },
-	{ 0x000792,   1, 0x01, 0x00000001 },
-	{ 0x000794,   3, 0x01, 0x00000001 },
-	{ 0x000797,   1, 0x01, 0x000000cf },
-	{ 0x00079a,   1, 0x01, 0x00000002 },
-	{ 0x000833,   1, 0x01, 0x04444480 },
-	{ 0x0007a1,   1, 0x01, 0x00000001 },
-	{ 0x0007a3,   3, 0x01, 0x00000001 },
-	{ 0x000831,   1, 0x01, 0x00000004 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000014 },
-	{ 0x000351,   1, 0x01, 0x00000100 },
-	{ 0x000957,   1, 0x01, 0x00000003 },
-	{ 0x00095d,   1, 0x01, 0x00000001 },
-	{ 0x00082b,   1, 0x01, 0x00000004 },
-	{ 0x000942,   1, 0x01, 0x00010001 },
-	{ 0x000943,   1, 0x01, 0x00000001 },
-	{ 0x0007c5,   1, 0x01, 0x00010001 },
-	{ 0x000834,   1, 0x01, 0x00000001 },
-	{ 0x0007c7,   1, 0x01, 0x00000001 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000001 },
-	{ 0x00080c,   1, 0x01, 0x00000002 },
-	{ 0x00080d,   2, 0x01, 0x00000100 },
-	{ 0x00080f,   1, 0x01, 0x00000001 },
-	{ 0x000823,   1, 0x01, 0x00000002 },
-	{ 0x000824,   2, 0x01, 0x00000100 },
-	{ 0x000826,   1, 0x01, 0x00000001 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{}
-};
-
-const struct nvc0_graph_pack
-nvc0_grctx_pack_icmd[] = {
-	{ nvc0_grctx_init_icmd_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc0_grctx_init_9097_0[] = {
-	{ 0x000800,   8, 0x40, 0x00000000 },
-	{ 0x000804,   8, 0x40, 0x00000000 },
-	{ 0x000808,   8, 0x40, 0x00000400 },
-	{ 0x00080c,   8, 0x40, 0x00000300 },
-	{ 0x000810,   1, 0x04, 0x000000cf },
-	{ 0x000850,   7, 0x40, 0x00000000 },
-	{ 0x000814,   8, 0x40, 0x00000040 },
-	{ 0x000818,   8, 0x40, 0x00000001 },
-	{ 0x00081c,   8, 0x40, 0x00000000 },
-	{ 0x000820,   8, 0x40, 0x00000000 },
-	{ 0x002700,   8, 0x20, 0x00000000 },
-	{ 0x002704,   8, 0x20, 0x00000000 },
-	{ 0x002708,   8, 0x20, 0x00000000 },
-	{ 0x00270c,   8, 0x20, 0x00000000 },
-	{ 0x002710,   8, 0x20, 0x00014000 },
-	{ 0x002714,   8, 0x20, 0x00000040 },
-	{ 0x001c00,  16, 0x10, 0x00000000 },
-	{ 0x001c04,  16, 0x10, 0x00000000 },
-	{ 0x001c08,  16, 0x10, 0x00000000 },
-	{ 0x001c0c,  16, 0x10, 0x00000000 },
-	{ 0x001d00,  16, 0x10, 0x00000000 },
-	{ 0x001d04,  16, 0x10, 0x00000000 },
-	{ 0x001d08,  16, 0x10, 0x00000000 },
-	{ 0x001d0c,  16, 0x10, 0x00000000 },
-	{ 0x001f00,  16, 0x08, 0x00000000 },
-	{ 0x001f04,  16, 0x08, 0x00000000 },
-	{ 0x001f80,  16, 0x08, 0x00000000 },
-	{ 0x001f84,  16, 0x08, 0x00000000 },
-	{ 0x002200,   5, 0x10, 0x00000022 },
-	{ 0x002000,   1, 0x04, 0x00000000 },
-	{ 0x002040,   1, 0x04, 0x00000011 },
-	{ 0x002080,   1, 0x04, 0x00000020 },
-	{ 0x0020c0,   1, 0x04, 0x00000030 },
-	{ 0x002100,   1, 0x04, 0x00000040 },
-	{ 0x002140,   1, 0x04, 0x00000051 },
-	{ 0x00200c,   6, 0x40, 0x00000001 },
-	{ 0x002010,   1, 0x04, 0x00000000 },
-	{ 0x002050,   1, 0x04, 0x00000000 },
-	{ 0x002090,   1, 0x04, 0x00000001 },
-	{ 0x0020d0,   1, 0x04, 0x00000002 },
-	{ 0x002110,   1, 0x04, 0x00000003 },
-	{ 0x002150,   1, 0x04, 0x00000004 },
-	{ 0x000380,   4, 0x20, 0x00000000 },
-	{ 0x000384,   4, 0x20, 0x00000000 },
-	{ 0x000388,   4, 0x20, 0x00000000 },
-	{ 0x00038c,   4, 0x20, 0x00000000 },
-	{ 0x000700,   4, 0x10, 0x00000000 },
-	{ 0x000704,   4, 0x10, 0x00000000 },
-	{ 0x000708,   4, 0x10, 0x00000000 },
-	{ 0x002800, 128, 0x04, 0x00000000 },
-	{ 0x000a00,  16, 0x20, 0x00000000 },
-	{ 0x000a04,  16, 0x20, 0x00000000 },
-	{ 0x000a08,  16, 0x20, 0x00000000 },
-	{ 0x000a0c,  16, 0x20, 0x00000000 },
-	{ 0x000a10,  16, 0x20, 0x00000000 },
-	{ 0x000a14,  16, 0x20, 0x00000000 },
-	{ 0x000c00,  16, 0x10, 0x00000000 },
-	{ 0x000c04,  16, 0x10, 0x00000000 },
-	{ 0x000c08,  16, 0x10, 0x00000000 },
-	{ 0x000c0c,  16, 0x10, 0x3f800000 },
-	{ 0x000d00,   8, 0x08, 0xffff0000 },
-	{ 0x000d04,   8, 0x08, 0xffff0000 },
-	{ 0x000e00,  16, 0x10, 0x00000000 },
-	{ 0x000e04,  16, 0x10, 0xffff0000 },
-	{ 0x000e08,  16, 0x10, 0xffff0000 },
-	{ 0x000d40,   4, 0x08, 0x00000000 },
-	{ 0x000d44,   4, 0x08, 0x00000000 },
-	{ 0x001e00,   8, 0x20, 0x00000001 },
-	{ 0x001e04,   8, 0x20, 0x00000001 },
-	{ 0x001e08,   8, 0x20, 0x00000002 },
-	{ 0x001e0c,   8, 0x20, 0x00000001 },
-	{ 0x001e10,   8, 0x20, 0x00000001 },
-	{ 0x001e14,   8, 0x20, 0x00000002 },
-	{ 0x001e18,   8, 0x20, 0x00000001 },
-	{ 0x003400, 128, 0x04, 0x00000000 },
-	{ 0x00030c,   1, 0x04, 0x00000001 },
-	{ 0x001944,   1, 0x04, 0x00000000 },
-	{ 0x001514,   1, 0x04, 0x00000000 },
-	{ 0x000d68,   1, 0x04, 0x0000ffff },
-	{ 0x00121c,   1, 0x04, 0x0fac6881 },
-	{ 0x000fac,   1, 0x04, 0x00000001 },
-	{ 0x001538,   1, 0x04, 0x00000001 },
-	{ 0x000fe0,   2, 0x04, 0x00000000 },
-	{ 0x000fe8,   1, 0x04, 0x00000014 },
-	{ 0x000fec,   1, 0x04, 0x00000040 },
-	{ 0x000ff0,   1, 0x04, 0x00000000 },
-	{ 0x00179c,   1, 0x04, 0x00000000 },
-	{ 0x001228,   1, 0x04, 0x00000400 },
-	{ 0x00122c,   1, 0x04, 0x00000300 },
-	{ 0x001230,   1, 0x04, 0x00010001 },
-	{ 0x0007f8,   1, 0x04, 0x00000000 },
-	{ 0x0015b4,   1, 0x04, 0x00000001 },
-	{ 0x0015cc,   1, 0x04, 0x00000000 },
-	{ 0x001534,   1, 0x04, 0x00000000 },
-	{ 0x000fb0,   1, 0x04, 0x00000000 },
-	{ 0x0015d0,   1, 0x04, 0x00000000 },
-	{ 0x00153c,   1, 0x04, 0x00000000 },
-	{ 0x0016b4,   1, 0x04, 0x00000003 },
-	{ 0x000fbc,   4, 0x04, 0x0000ffff },
-	{ 0x000df8,   2, 0x04, 0x00000000 },
-	{ 0x001948,   1, 0x04, 0x00000000 },
-	{ 0x001970,   1, 0x04, 0x00000001 },
-	{ 0x00161c,   1, 0x04, 0x000009f0 },
-	{ 0x000dcc,   1, 0x04, 0x00000010 },
-	{ 0x00163c,   1, 0x04, 0x00000000 },
-	{ 0x0015e4,   1, 0x04, 0x00000000 },
-	{ 0x001160,  32, 0x04, 0x25e00040 },
-	{ 0x001880,  32, 0x04, 0x00000000 },
-	{ 0x000f84,   2, 0x04, 0x00000000 },
-	{ 0x0017c8,   2, 0x04, 0x00000000 },
-	{ 0x0017d0,   1, 0x04, 0x000000ff },
-	{ 0x0017d4,   1, 0x04, 0xffffffff },
-	{ 0x0017d8,   1, 0x04, 0x00000002 },
-	{ 0x0017dc,   1, 0x04, 0x00000000 },
-	{ 0x0015f4,   2, 0x04, 0x00000000 },
-	{ 0x001434,   2, 0x04, 0x00000000 },
-	{ 0x000d74,   1, 0x04, 0x00000000 },
-	{ 0x000dec,   1, 0x04, 0x00000001 },
-	{ 0x0013a4,   1, 0x04, 0x00000000 },
-	{ 0x001318,   1, 0x04, 0x00000001 },
-	{ 0x001644,   1, 0x04, 0x00000000 },
-	{ 0x000748,   1, 0x04, 0x00000000 },
-	{ 0x000de8,   1, 0x04, 0x00000000 },
-	{ 0x001648,   1, 0x04, 0x00000000 },
-	{ 0x0012a4,   1, 0x04, 0x00000000 },
-	{ 0x001120,   4, 0x04, 0x00000000 },
-	{ 0x001118,   1, 0x04, 0x00000000 },
-	{ 0x00164c,   1, 0x04, 0x00000000 },
-	{ 0x001658,   1, 0x04, 0x00000000 },
-	{ 0x001910,   1, 0x04, 0x00000290 },
-	{ 0x001518,   1, 0x04, 0x00000000 },
-	{ 0x00165c,   1, 0x04, 0x00000001 },
-	{ 0x001520,   1, 0x04, 0x00000000 },
-	{ 0x001604,   1, 0x04, 0x00000000 },
-	{ 0x001570,   1, 0x04, 0x00000000 },
-	{ 0x0013b0,   2, 0x04, 0x3f800000 },
-	{ 0x00020c,   1, 0x04, 0x00000000 },
-	{ 0x001670,   1, 0x04, 0x30201000 },
-	{ 0x001674,   1, 0x04, 0x70605040 },
-	{ 0x001678,   1, 0x04, 0xb8a89888 },
-	{ 0x00167c,   1, 0x04, 0xf8e8d8c8 },
-	{ 0x00166c,   1, 0x04, 0x00000000 },
-	{ 0x001680,   1, 0x04, 0x00ffff00 },
-	{ 0x0012d0,   1, 0x04, 0x00000003 },
-	{ 0x0012d4,   1, 0x04, 0x00000002 },
-	{ 0x001684,   2, 0x04, 0x00000000 },
-	{ 0x000dac,   2, 0x04, 0x00001b02 },
-	{ 0x000db4,   1, 0x04, 0x00000000 },
-	{ 0x00168c,   1, 0x04, 0x00000000 },
-	{ 0x0015bc,   1, 0x04, 0x00000000 },
-	{ 0x00156c,   1, 0x04, 0x00000000 },
-	{ 0x00187c,   1, 0x04, 0x00000000 },
-	{ 0x001110,   1, 0x04, 0x00000001 },
-	{ 0x000dc0,   3, 0x04, 0x00000000 },
-	{ 0x001234,   1, 0x04, 0x00000000 },
-	{ 0x001690,   1, 0x04, 0x00000000 },
-	{ 0x0012ac,   1, 0x04, 0x00000001 },
-	{ 0x0002c4,   1, 0x04, 0x00000000 },
-	{ 0x000790,   5, 0x04, 0x00000000 },
-	{ 0x00077c,   1, 0x04, 0x00000000 },
-	{ 0x001000,   1, 0x04, 0x00000010 },
-	{ 0x0010fc,   1, 0x04, 0x00000000 },
-	{ 0x001290,   1, 0x04, 0x00000000 },
-	{ 0x000218,   1, 0x04, 0x00000010 },
-	{ 0x0012d8,   1, 0x04, 0x00000000 },
-	{ 0x0012dc,   1, 0x04, 0x00000010 },
-	{ 0x000d94,   1, 0x04, 0x00000001 },
-	{ 0x00155c,   2, 0x04, 0x00000000 },
-	{ 0x001564,   1, 0x04, 0x00001fff },
-	{ 0x001574,   2, 0x04, 0x00000000 },
-	{ 0x00157c,   1, 0x04, 0x003fffff },
-	{ 0x001354,   1, 0x04, 0x00000000 },
-	{ 0x001664,   1, 0x04, 0x00000000 },
-	{ 0x001610,   1, 0x04, 0x00000012 },
-	{ 0x001608,   2, 0x04, 0x00000000 },
-	{ 0x00162c,   1, 0x04, 0x00000003 },
-	{ 0x000210,   1, 0x04, 0x00000000 },
-	{ 0x000320,   1, 0x04, 0x00000000 },
-	{ 0x000324,   6, 0x04, 0x3f800000 },
-	{ 0x000750,   1, 0x04, 0x00000000 },
-	{ 0x000760,   1, 0x04, 0x39291909 },
-	{ 0x000764,   1, 0x04, 0x79695949 },
-	{ 0x000768,   1, 0x04, 0xb9a99989 },
-	{ 0x00076c,   1, 0x04, 0xf9e9d9c9 },
-	{ 0x000770,   1, 0x04, 0x30201000 },
-	{ 0x000774,   1, 0x04, 0x70605040 },
-	{ 0x000778,   1, 0x04, 0x00009080 },
-	{ 0x000780,   1, 0x04, 0x39291909 },
-	{ 0x000784,   1, 0x04, 0x79695949 },
-	{ 0x000788,   1, 0x04, 0xb9a99989 },
-	{ 0x00078c,   1, 0x04, 0xf9e9d9c9 },
-	{ 0x0007d0,   1, 0x04, 0x30201000 },
-	{ 0x0007d4,   1, 0x04, 0x70605040 },
-	{ 0x0007d8,   1, 0x04, 0x00009080 },
-	{ 0x00037c,   1, 0x04, 0x00000001 },
-	{ 0x000740,   2, 0x04, 0x00000000 },
-	{ 0x002600,   1, 0x04, 0x00000000 },
-	{ 0x001918,   1, 0x04, 0x00000000 },
-	{ 0x00191c,   1, 0x04, 0x00000900 },
-	{ 0x001920,   1, 0x04, 0x00000405 },
-	{ 0x001308,   1, 0x04, 0x00000001 },
-	{ 0x001924,   1, 0x04, 0x00000000 },
-	{ 0x0013ac,   1, 0x04, 0x00000000 },
-	{ 0x00192c,   1, 0x04, 0x00000001 },
-	{ 0x00193c,   1, 0x04, 0x00002c1c },
-	{ 0x000d7c,   1, 0x04, 0x00000000 },
-	{ 0x000f8c,   1, 0x04, 0x00000000 },
-	{ 0x0002c0,   1, 0x04, 0x00000001 },
-	{ 0x001510,   1, 0x04, 0x00000000 },
-	{ 0x001940,   1, 0x04, 0x00000000 },
-	{ 0x000ff4,   2, 0x04, 0x00000000 },
-	{ 0x00194c,   2, 0x04, 0x00000000 },
-	{ 0x001968,   1, 0x04, 0x00000000 },
-	{ 0x001590,   1, 0x04, 0x0000003f },
-	{ 0x0007e8,   4, 0x04, 0x00000000 },
-	{ 0x00196c,   1, 0x04, 0x00000011 },
-	{ 0x00197c,   1, 0x04, 0x00000000 },
-	{ 0x000fcc,   2, 0x04, 0x00000000 },
-	{ 0x0002d8,   1, 0x04, 0x00000040 },
-	{ 0x001980,   1, 0x04, 0x00000080 },
-	{ 0x001504,   1, 0x04, 0x00000080 },
-	{ 0x001984,   1, 0x04, 0x00000000 },
-	{ 0x000300,   1, 0x04, 0x00000001 },
-	{ 0x0013a8,   1, 0x04, 0x00000000 },
-	{ 0x0012ec,   1, 0x04, 0x00000000 },
-	{ 0x001310,   1, 0x04, 0x00000000 },
-	{ 0x001314,   1, 0x04, 0x00000001 },
-	{ 0x001380,   1, 0x04, 0x00000000 },
-	{ 0x001384,   4, 0x04, 0x00000001 },
-	{ 0x001394,   1, 0x04, 0x00000000 },
-	{ 0x00139c,   1, 0x04, 0x00000000 },
-	{ 0x001398,   1, 0x04, 0x00000000 },
-	{ 0x001594,   1, 0x04, 0x00000000 },
-	{ 0x001598,   4, 0x04, 0x00000001 },
-	{ 0x000f54,   3, 0x04, 0x00000000 },
-	{ 0x0019bc,   1, 0x04, 0x00000000 },
-	{ 0x000f9c,   2, 0x04, 0x00000000 },
-	{ 0x0012cc,   1, 0x04, 0x00000000 },
-	{ 0x0012e8,   1, 0x04, 0x00000000 },
-	{ 0x00130c,   1, 0x04, 0x00000001 },
-	{ 0x001360,   8, 0x04, 0x00000000 },
-	{ 0x00133c,   2, 0x04, 0x00000001 },
-	{ 0x001344,   1, 0x04, 0x00000002 },
-	{ 0x001348,   2, 0x04, 0x00000001 },
-	{ 0x001350,   1, 0x04, 0x00000002 },
-	{ 0x001358,   1, 0x04, 0x00000001 },
-	{ 0x0012e4,   1, 0x04, 0x00000000 },
-	{ 0x00131c,   4, 0x04, 0x00000000 },
-	{ 0x0019c0,   1, 0x04, 0x00000000 },
-	{ 0x001140,   1, 0x04, 0x00000000 },
-	{ 0x0019c4,   1, 0x04, 0x00000000 },
-	{ 0x0019c8,   1, 0x04, 0x00001500 },
-	{ 0x00135c,   1, 0x04, 0x00000000 },
-	{ 0x000f90,   1, 0x04, 0x00000000 },
-	{ 0x0019e0,   8, 0x04, 0x00000001 },
-	{ 0x0019cc,   1, 0x04, 0x00000001 },
-	{ 0x0015b8,   1, 0x04, 0x00000000 },
-	{ 0x001a00,   1, 0x04, 0x00001111 },
-	{ 0x001a04,   7, 0x04, 0x00000000 },
-	{ 0x000d6c,   2, 0x04, 0xffff0000 },
-	{ 0x0010f8,   1, 0x04, 0x00001010 },
-	{ 0x000d80,   5, 0x04, 0x00000000 },
-	{ 0x000da0,   1, 0x04, 0x00000000 },
-	{ 0x001508,   1, 0x04, 0x80000000 },
-	{ 0x00150c,   1, 0x04, 0x40000000 },
-	{ 0x001668,   1, 0x04, 0x00000000 },
-	{ 0x000318,   2, 0x04, 0x00000008 },
-	{ 0x000d9c,   1, 0x04, 0x00000001 },
-	{ 0x0007dc,   1, 0x04, 0x00000000 },
-	{ 0x00074c,   1, 0x04, 0x00000055 },
-	{ 0x001420,   1, 0x04, 0x00000003 },
-	{ 0x0017bc,   2, 0x04, 0x00000000 },
-	{ 0x0017c4,   1, 0x04, 0x00000001 },
-	{ 0x001008,   1, 0x04, 0x00000008 },
-	{ 0x00100c,   1, 0x04, 0x00000040 },
-	{ 0x001010,   1, 0x04, 0x0000012c },
-	{ 0x000d60,   1, 0x04, 0x00000040 },
-	{ 0x00075c,   1, 0x04, 0x00000003 },
-	{ 0x001018,   1, 0x04, 0x00000020 },
-	{ 0x00101c,   1, 0x04, 0x00000001 },
-	{ 0x001020,   1, 0x04, 0x00000020 },
-	{ 0x001024,   1, 0x04, 0x00000001 },
-	{ 0x001444,   3, 0x04, 0x00000000 },
-	{ 0x000360,   1, 0x04, 0x20164010 },
-	{ 0x000364,   1, 0x04, 0x00000020 },
-	{ 0x000368,   1, 0x04, 0x00000000 },
-	{ 0x000de4,   1, 0x04, 0x00000000 },
-	{ 0x000204,   1, 0x04, 0x00000006 },
-	{ 0x000208,   1, 0x04, 0x00000000 },
-	{ 0x0002cc,   1, 0x04, 0x003fffff },
-	{ 0x0002d0,   1, 0x04, 0x00000c48 },
-	{ 0x001220,   1, 0x04, 0x00000005 },
-	{ 0x000fdc,   1, 0x04, 0x00000000 },
-	{ 0x000f98,   1, 0x04, 0x00300008 },
-	{ 0x001284,   1, 0x04, 0x04000080 },
-	{ 0x001450,   1, 0x04, 0x00300008 },
-	{ 0x001454,   1, 0x04, 0x04000080 },
-	{ 0x000214,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_902d_0[] = {
-	{ 0x000200,   1, 0x04, 0x000000cf },
-	{ 0x000204,   1, 0x04, 0x00000001 },
-	{ 0x000208,   1, 0x04, 0x00000020 },
-	{ 0x00020c,   1, 0x04, 0x00000001 },
-	{ 0x000210,   1, 0x04, 0x00000000 },
-	{ 0x000214,   1, 0x04, 0x00000080 },
-	{ 0x000218,   2, 0x04, 0x00000100 },
-	{ 0x000220,   2, 0x04, 0x00000000 },
-	{ 0x000230,   1, 0x04, 0x000000cf },
-	{ 0x000234,   1, 0x04, 0x00000001 },
-	{ 0x000238,   1, 0x04, 0x00000020 },
-	{ 0x00023c,   1, 0x04, 0x00000001 },
-	{ 0x000244,   1, 0x04, 0x00000080 },
-	{ 0x000248,   2, 0x04, 0x00000100 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_9039_0[] = {
-	{ 0x00030c,   3, 0x04, 0x00000000 },
-	{ 0x000320,   1, 0x04, 0x00000000 },
-	{ 0x000238,   2, 0x04, 0x00000000 },
-	{ 0x000318,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_90c0_0[] = {
-	{ 0x00270c,   8, 0x20, 0x00000000 },
-	{ 0x00030c,   1, 0x04, 0x00000001 },
-	{ 0x001944,   1, 0x04, 0x00000000 },
-	{ 0x000758,   1, 0x04, 0x00000100 },
-	{ 0x0002c4,   1, 0x04, 0x00000000 },
-	{ 0x000790,   5, 0x04, 0x00000000 },
-	{ 0x00077c,   1, 0x04, 0x00000000 },
-	{ 0x000204,   3, 0x04, 0x00000000 },
-	{ 0x000214,   1, 0x04, 0x00000000 },
-	{ 0x00024c,   1, 0x04, 0x00000000 },
-	{ 0x000d94,   1, 0x04, 0x00000001 },
-	{ 0x001608,   2, 0x04, 0x00000000 },
-	{ 0x001664,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_pack
-nvc0_grctx_pack_mthd[] = {
-	{ nvc0_grctx_init_9097_0, 0x9097 },
-	{ nvc0_grctx_init_902d_0, 0x902d },
-	{ nvc0_grctx_init_9039_0, 0x9039 },
-	{ nvc0_grctx_init_90c0_0, 0x90c0 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_main_0[] = {
-	{ 0x400204,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_fe_0[] = {
-	{ 0x404004,  11, 0x04, 0x00000000 },
-	{ 0x404044,   1, 0x04, 0x00000000 },
-	{ 0x404094,  13, 0x04, 0x00000000 },
-	{ 0x4040c8,   1, 0x04, 0xf0000087 },
-	{ 0x4040d0,   6, 0x04, 0x00000000 },
-	{ 0x4040e8,   1, 0x04, 0x00001000 },
-	{ 0x4040f8,   1, 0x04, 0x00000000 },
-	{ 0x404130,   2, 0x04, 0x00000000 },
-	{ 0x404138,   1, 0x04, 0x20000040 },
-	{ 0x404150,   1, 0x04, 0x0000002e },
-	{ 0x404154,   1, 0x04, 0x00000400 },
-	{ 0x404158,   1, 0x04, 0x00000200 },
-	{ 0x404164,   1, 0x04, 0x00000055 },
-	{ 0x404168,   1, 0x04, 0x00000000 },
-	{ 0x404174,   3, 0x04, 0x00000000 },
-	{ 0x404200,   8, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_pri_0[] = {
-	{ 0x404404,  14, 0x04, 0x00000000 },
-	{ 0x404460,   2, 0x04, 0x00000000 },
-	{ 0x404468,   1, 0x04, 0x00ffffff },
-	{ 0x40446c,   1, 0x04, 0x00000000 },
-	{ 0x404480,   1, 0x04, 0x00000001 },
-	{ 0x404498,   1, 0x04, 0x00000001 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_memfmt_0[] = {
-	{ 0x404604,   1, 0x04, 0x00000015 },
-	{ 0x404608,   1, 0x04, 0x00000000 },
-	{ 0x40460c,   1, 0x04, 0x00002e00 },
-	{ 0x404610,   1, 0x04, 0x00000100 },
-	{ 0x404618,   8, 0x04, 0x00000000 },
-	{ 0x404638,   1, 0x04, 0x00000004 },
-	{ 0x40463c,   8, 0x04, 0x00000000 },
-	{ 0x40465c,   1, 0x04, 0x007f0100 },
-	{ 0x404660,   7, 0x04, 0x00000000 },
-	{ 0x40467c,   1, 0x04, 0x00000002 },
-	{ 0x404680,   8, 0x04, 0x00000000 },
-	{ 0x4046a0,   1, 0x04, 0x007f0080 },
-	{ 0x4046a4,  18, 0x04, 0x00000000 },
-	{ 0x4046f0,   2, 0x04, 0x00000000 },
-	{ 0x404700,  13, 0x04, 0x00000000 },
-	{ 0x404734,   1, 0x04, 0x00000100 },
-	{ 0x404738,   8, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc0_grctx_init_ds_0[] = {
-	{ 0x405800,   1, 0x04, 0x078000bf },
-	{ 0x405830,   1, 0x04, 0x02180000 },
-	{ 0x405834,   2, 0x04, 0x00000000 },
-	{ 0x405854,   1, 0x04, 0x00000000 },
-	{ 0x405870,   4, 0x04, 0x00000001 },
-	{ 0x405a00,   2, 0x04, 0x00000000 },
-	{ 0x405a18,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc0_grctx_init_pd_0[] = {
-	{ 0x406020,   1, 0x04, 0x000103c1 },
-	{ 0x406028,   4, 0x04, 0x00000001 },
-	{ 0x4064a8,   1, 0x04, 0x00000000 },
-	{ 0x4064ac,   1, 0x04, 0x00003fff },
-	{ 0x4064b4,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_rstr2d_0[] = {
-	{ 0x407804,   1, 0x04, 0x00000023 },
-	{ 0x40780c,   1, 0x04, 0x0a418820 },
-	{ 0x407810,   1, 0x04, 0x062080e6 },
-	{ 0x407814,   1, 0x04, 0x020398a4 },
-	{ 0x407818,   1, 0x04, 0x0e629062 },
-	{ 0x40781c,   1, 0x04, 0x0a418820 },
-	{ 0x407820,   1, 0x04, 0x000000e6 },
-	{ 0x4078bc,   1, 0x04, 0x00000103 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_scc_0[] = {
-	{ 0x408000,   2, 0x04, 0x00000000 },
-	{ 0x408008,   1, 0x04, 0x00000018 },
-	{ 0x40800c,   2, 0x04, 0x00000000 },
-	{ 0x408014,   1, 0x04, 0x00000069 },
-	{ 0x408018,   1, 0x04, 0xe100e100 },
-	{ 0x408064,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc0_grctx_init_be_0[] = {
-	{ 0x408800,   1, 0x04, 0x02802a3c },
-	{ 0x408804,   1, 0x04, 0x00000040 },
-	{ 0x408808,   1, 0x04, 0x0003e00d },
-	{ 0x408900,   1, 0x04, 0x3080b801 },
-	{ 0x408904,   1, 0x04, 0x02000001 },
-	{ 0x408908,   1, 0x04, 0x00c80929 },
-	{ 0x408980,   1, 0x04, 0x0000011d },
-	{}
-};
-
-const struct nvc0_graph_pack
-nvc0_grctx_pack_hub[] = {
-	{ nvc0_grctx_init_main_0 },
-	{ nvc0_grctx_init_fe_0 },
-	{ nvc0_grctx_init_pri_0 },
-	{ nvc0_grctx_init_memfmt_0 },
-	{ nvc0_grctx_init_ds_0 },
-	{ nvc0_grctx_init_pd_0 },
-	{ nvc0_grctx_init_rstr2d_0 },
-	{ nvc0_grctx_init_scc_0 },
-	{ nvc0_grctx_init_be_0 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_gpc_unk_0[] = {
-	{ 0x418380,   1, 0x04, 0x00000016 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_prop_0[] = {
-	{ 0x418400,   1, 0x04, 0x38004e00 },
-	{ 0x418404,   1, 0x04, 0x71e0ffff },
-	{ 0x418408,   1, 0x04, 0x00000000 },
-	{ 0x41840c,   1, 0x04, 0x00001008 },
-	{ 0x418410,   1, 0x04, 0x0fff0fff },
-	{ 0x418414,   1, 0x04, 0x00200fff },
-	{ 0x418450,   6, 0x04, 0x00000000 },
-	{ 0x418468,   1, 0x04, 0x00000001 },
-	{ 0x41846c,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_gpc_unk_1[] = {
-	{ 0x418600,   1, 0x04, 0x0000001f },
-	{ 0x418684,   1, 0x04, 0x0000000f },
-	{ 0x418700,   1, 0x04, 0x00000002 },
-	{ 0x418704,   1, 0x04, 0x00000080 },
-	{ 0x418708,   1, 0x04, 0x00000000 },
-	{ 0x41870c,   1, 0x04, 0x07c80000 },
-	{ 0x418710,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc0_grctx_init_setup_0[] = {
-	{ 0x418800,   1, 0x04, 0x0006860a },
-	{ 0x418808,   3, 0x04, 0x00000000 },
-	{ 0x418828,   1, 0x04, 0x00008442 },
-	{ 0x418830,   1, 0x04, 0x00000001 },
-	{ 0x4188d8,   1, 0x04, 0x00000008 },
-	{ 0x4188e0,   1, 0x04, 0x01000000 },
-	{ 0x4188e8,   5, 0x04, 0x00000000 },
-	{ 0x4188fc,   1, 0x04, 0x00100000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_zcull_0[] = {
-	{ 0x41891c,   1, 0x04, 0x00ff00ff },
-	{ 0x418924,   1, 0x04, 0x00000000 },
-	{ 0x418928,   1, 0x04, 0x00ffff00 },
-	{ 0x41892c,   1, 0x04, 0x0000ff00 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_crstr_0[] = {
-	{ 0x418b00,   1, 0x04, 0x00000000 },
-	{ 0x418b08,   1, 0x04, 0x0a418820 },
-	{ 0x418b0c,   1, 0x04, 0x062080e6 },
-	{ 0x418b10,   1, 0x04, 0x020398a4 },
-	{ 0x418b14,   1, 0x04, 0x0e629062 },
-	{ 0x418b18,   1, 0x04, 0x0a418820 },
-	{ 0x418b1c,   1, 0x04, 0x000000e6 },
-	{ 0x418bb8,   1, 0x04, 0x00000103 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_gpm_0[] = {
-	{ 0x418c08,   1, 0x04, 0x00000001 },
-	{ 0x418c10,   8, 0x04, 0x00000000 },
-	{ 0x418c80,   1, 0x04, 0x20200004 },
-	{ 0x418c8c,   1, 0x04, 0x00000001 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_gcc_0[] = {
-	{ 0x419000,   1, 0x04, 0x00000780 },
-	{ 0x419004,   2, 0x04, 0x00000000 },
-	{ 0x419014,   1, 0x04, 0x00000004 },
-	{}
-};
-
-const struct nvc0_graph_pack
-nvc0_grctx_pack_gpc[] = {
-	{ nvc0_grctx_init_gpc_unk_0 },
-	{ nvc0_grctx_init_prop_0 },
-	{ nvc0_grctx_init_gpc_unk_1 },
-	{ nvc0_grctx_init_setup_0 },
-	{ nvc0_grctx_init_zcull_0 },
-	{ nvc0_grctx_init_crstr_0 },
-	{ nvc0_grctx_init_gpm_0 },
-	{ nvc0_grctx_init_gcc_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc0_grctx_init_zcullr_0[] = {
-	{ 0x418a00,   3, 0x04, 0x00000000 },
-	{ 0x418a0c,   1, 0x04, 0x00010000 },
-	{ 0x418a10,   3, 0x04, 0x00000000 },
-	{ 0x418a20,   3, 0x04, 0x00000000 },
-	{ 0x418a2c,   1, 0x04, 0x00010000 },
-	{ 0x418a30,   3, 0x04, 0x00000000 },
-	{ 0x418a40,   3, 0x04, 0x00000000 },
-	{ 0x418a4c,   1, 0x04, 0x00010000 },
-	{ 0x418a50,   3, 0x04, 0x00000000 },
-	{ 0x418a60,   3, 0x04, 0x00000000 },
-	{ 0x418a6c,   1, 0x04, 0x00010000 },
-	{ 0x418a70,   3, 0x04, 0x00000000 },
-	{ 0x418a80,   3, 0x04, 0x00000000 },
-	{ 0x418a8c,   1, 0x04, 0x00010000 },
-	{ 0x418a90,   3, 0x04, 0x00000000 },
-	{ 0x418aa0,   3, 0x04, 0x00000000 },
-	{ 0x418aac,   1, 0x04, 0x00010000 },
-	{ 0x418ab0,   3, 0x04, 0x00000000 },
-	{ 0x418ac0,   3, 0x04, 0x00000000 },
-	{ 0x418acc,   1, 0x04, 0x00010000 },
-	{ 0x418ad0,   3, 0x04, 0x00000000 },
-	{ 0x418ae0,   3, 0x04, 0x00000000 },
-	{ 0x418aec,   1, 0x04, 0x00010000 },
-	{ 0x418af0,   3, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_pack
-nvc0_grctx_pack_zcull[] = {
-	{ nvc0_grctx_init_zcullr_0 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_pe_0[] = {
-	{ 0x419818,   1, 0x04, 0x00000000 },
-	{ 0x41983c,   1, 0x04, 0x00038bc7 },
-	{ 0x419848,   1, 0x04, 0x00000000 },
-	{ 0x419864,   1, 0x04, 0x0000012a },
-	{ 0x419888,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc0_grctx_init_tex_0[] = {
-	{ 0x419a00,   1, 0x04, 0x000001f0 },
-	{ 0x419a04,   1, 0x04, 0x00000001 },
-	{ 0x419a08,   1, 0x04, 0x00000023 },
-	{ 0x419a0c,   1, 0x04, 0x00020000 },
-	{ 0x419a10,   1, 0x04, 0x00000000 },
-	{ 0x419a14,   1, 0x04, 0x00000200 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_wwdx_0[] = {
-	{ 0x419b00,   1, 0x04, 0x0a418820 },
-	{ 0x419b04,   1, 0x04, 0x062080e6 },
-	{ 0x419b08,   1, 0x04, 0x020398a4 },
-	{ 0x419b0c,   1, 0x04, 0x0e629062 },
-	{ 0x419b10,   1, 0x04, 0x0a418820 },
-	{ 0x419b14,   1, 0x04, 0x000000e6 },
-	{ 0x419bd0,   1, 0x04, 0x00900103 },
-	{ 0x419be0,   1, 0x04, 0x00000001 },
-	{ 0x419be4,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_mpc_0[] = {
-	{ 0x419c00,   1, 0x04, 0x00000002 },
-	{ 0x419c04,   1, 0x04, 0x00000006 },
-	{ 0x419c08,   1, 0x04, 0x00000002 },
-	{ 0x419c20,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc0_grctx_init_l1c_0[] = {
-	{ 0x419cb0,   1, 0x04, 0x00060048 },
-	{ 0x419ce8,   1, 0x04, 0x00000000 },
-	{ 0x419cf4,   1, 0x04, 0x00000183 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_grctx_init_tpccs_0[] = {
-	{ 0x419d20,   1, 0x04, 0x02180000 },
-	{ 0x419d24,   1, 0x04, 0x00001fff },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc0_grctx_init_sm_0[] = {
-	{ 0x419e04,   3, 0x04, 0x00000000 },
-	{ 0x419e10,   1, 0x04, 0x00000002 },
-	{ 0x419e44,   1, 0x04, 0x001beff2 },
-	{ 0x419e48,   1, 0x04, 0x00000000 },
-	{ 0x419e4c,   1, 0x04, 0x0000000f },
-	{ 0x419e50,  17, 0x04, 0x00000000 },
-	{ 0x419e98,   1, 0x04, 0x00000000 },
-	{ 0x419f50,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_pack
-nvc0_grctx_pack_tpc[] = {
-	{ nvc0_grctx_init_pe_0 },
-	{ nvc0_grctx_init_tex_0 },
-	{ nvc0_grctx_init_wwdx_0 },
-	{ nvc0_grctx_init_mpc_0 },
-	{ nvc0_grctx_init_l1c_0 },
-	{ nvc0_grctx_init_tpccs_0 },
-	{ nvc0_grctx_init_sm_0 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH context implementation
- ******************************************************************************/
-
-int
-nvc0_grctx_mmio_data(struct nvc0_grctx *info, u32 size, u32 align, u32 access)
-{
-	if (info->data) {
-		info->buffer[info->buffer_nr] = round_up(info->addr, align);
-		info->addr = info->buffer[info->buffer_nr] + size;
-		info->data->size = size;
-		info->data->align = align;
-		info->data->access = access;
-		info->data++;
-		return info->buffer_nr++;
-	}
-	return -1;
-}
-
-void
-nvc0_grctx_mmio_item(struct nvc0_grctx *info, u32 addr, u32 data,
-		     int shift, int buffer)
-{
-	if (info->data) {
-		if (shift >= 0) {
-			info->mmio->addr = addr;
-			info->mmio->data = data;
-			info->mmio->shift = shift;
-			info->mmio->buffer = buffer;
-			if (buffer >= 0)
-				data |= info->buffer[buffer] >> shift;
-			info->mmio++;
-		} else
-			return;
-	} else {
-		if (buffer >= 0)
-			return;
-	}
-
-	nv_wr32(info->priv, addr, data);
-}
-
-void
-nvc0_grctx_generate_bundle(struct nvc0_grctx *info)
-{
-	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
-	const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
-	const int s = 8;
-	const int b = mmio_vram(info, impl->bundle_size, (1 << s), access);
-	mmio_refn(info, 0x408004, 0x00000000, s, b);
-	mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b);
-	mmio_refn(info, 0x418808, 0x00000000, s, b);
-	mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b);
-}
-
-void
-nvc0_grctx_generate_pagepool(struct nvc0_grctx *info)
-{
-	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
-	const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
-	const int s = 8;
-	const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
-	mmio_refn(info, 0x40800c, 0x00000000, s, b);
-	mmio_wr32(info, 0x408010, 0x80000000);
-	mmio_refn(info, 0x419004, 0x00000000, s, b);
-	mmio_wr32(info, 0x419008, 0x00000000);
-}
-
-void
-nvc0_grctx_generate_attrib(struct nvc0_grctx *info)
-{
-	struct nvc0_graph_priv *priv = info->priv;
-	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
-	const u32 attrib = impl->attrib_nr;
-	const u32   size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
-	const u32 access = NV_MEM_ACCESS_RW;
-	const int s = 12;
-	const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access);
-	int gpc, tpc;
-	u32 bo = 0;
-
-	mmio_refn(info, 0x418810, 0x80000000, s, b);
-	mmio_refn(info, 0x419848, 0x10000000, s, b);
-	mmio_wr32(info, 0x405830, (attrib << 16));
-
-	for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-		for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
-			const u32 o = TPC_UNIT(gpc, tpc, 0x0520);
-			mmio_skip(info, o, (attrib << 16) | ++bo);
-			mmio_wr32(info, o, (attrib << 16) | --bo);
-			bo += impl->attrib_nr_max;
-		}
-	}
-}
-
-void
-nvc0_grctx_generate_unkn(struct nvc0_graph_priv *priv)
-{
-}
-
-void
-nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *priv)
-{
-	int gpc, tpc, id;
-
-	for (tpc = 0, id = 0; tpc < 4; tpc++) {
-		for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-			if (tpc < priv->tpc_nr[gpc]) {
-				nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id);
-				nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x4e8), id);
-				nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
-				nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id);
-				id++;
-			}
-
-			nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]);
-			nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]);
-		}
-	}
-}
-
-void
-nvc0_grctx_generate_r406028(struct nvc0_graph_priv *priv)
-{
-	u32 tmp[GPC_MAX / 8] = {}, i = 0;
-	for (i = 0; i < priv->gpc_nr; i++)
-		tmp[i / 8] |= priv->tpc_nr[i] << ((i % 8) * 4);
-	for (i = 0; i < 4; i++) {
-		nv_wr32(priv, 0x406028 + (i * 4), tmp[i]);
-		nv_wr32(priv, 0x405870 + (i * 4), tmp[i]);
-	}
-}
-
-void
-nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *priv)
-{
-	u8  tpcnr[GPC_MAX], data[TPC_MAX];
-	int gpc, tpc, i;
-
-	memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
-	memset(data, 0x1f, sizeof(data));
-
-	gpc = -1;
-	for (tpc = 0; tpc < priv->tpc_total; tpc++) {
-		do {
-			gpc = (gpc + 1) % priv->gpc_nr;
-		} while (!tpcnr[gpc]);
-		tpcnr[gpc]--;
-		data[tpc] = gpc;
-	}
-
-	for (i = 0; i < 4; i++)
-		nv_wr32(priv, 0x4060a8 + (i * 4), ((u32 *)data)[i]);
-}
-
-void
-nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *priv)
-{
-	u32 data[6] = {}, data2[2] = {};
-	u8  tpcnr[GPC_MAX];
-	u8  shift, ntpcv;
-	int gpc, tpc, i;
-
-	/* calculate first set of magics */
-	memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
-
-	gpc = -1;
-	for (tpc = 0; tpc < priv->tpc_total; tpc++) {
-		do {
-			gpc = (gpc + 1) % priv->gpc_nr;
-		} while (!tpcnr[gpc]);
-		tpcnr[gpc]--;
-
-		data[tpc / 6] |= gpc << ((tpc % 6) * 5);
-	}
-
-	for (; tpc < 32; tpc++)
-		data[tpc / 6] |= 7 << ((tpc % 6) * 5);
-
-	/* and the second... */
-	shift = 0;
-	ntpcv = priv->tpc_total;
-	while (!(ntpcv & (1 << 4))) {
-		ntpcv <<= 1;
-		shift++;
-	}
-
-	data2[0]  = (ntpcv << 16);
-	data2[0] |= (shift << 21);
-	data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24);
-	for (i = 1; i < 7; i++)
-		data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
-
-	/* GPC_BROADCAST */
-	nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) |
-				 priv->magic_not_rop_nr);
-	for (i = 0; i < 6; i++)
-		nv_wr32(priv, 0x418b08 + (i * 4), data[i]);
-
-	/* GPC_BROADCAST.TP_BROADCAST */
-	nv_wr32(priv, 0x419bd0, (priv->tpc_total << 8) |
-				 priv->magic_not_rop_nr | data2[0]);
-	nv_wr32(priv, 0x419be4, data2[1]);
-	for (i = 0; i < 6; i++)
-		nv_wr32(priv, 0x419b00 + (i * 4), data[i]);
-
-	/* UNK78xx */
-	nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) |
-				 priv->magic_not_rop_nr);
-	for (i = 0; i < 6; i++)
-		nv_wr32(priv, 0x40780c + (i * 4), data[i]);
-}
-
-void
-nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
-{
-	u64 tpc_mask = 0, tpc_set = 0;
-	u8  tpcnr[GPC_MAX];
-	int gpc, tpc;
-	int i, a, b;
-
-	memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
-	for (gpc = 0; gpc < priv->gpc_nr; gpc++)
-		tpc_mask |= ((1ULL << priv->tpc_nr[gpc]) - 1) << (gpc * 8);
-
-	for (i = 0, gpc = -1, b = -1; i < 32; i++) {
-		a = (i * (priv->tpc_total - 1)) / 32;
-		if (a != b) {
-			b = a;
-			do {
-				gpc = (gpc + 1) % priv->gpc_nr;
-			} while (!tpcnr[gpc]);
-			tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
-
-			tpc_set |= 1ULL << ((gpc * 8) + tpc);
-		}
-
-		nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));
-		nv_wr32(priv, 0x406c00 + (i * 0x20), lower_32_bits(tpc_set ^ tpc_mask));
-		if (priv->gpc_nr > 4) {
-			nv_wr32(priv, 0x406804 + (i * 0x20), upper_32_bits(tpc_set));
-			nv_wr32(priv, 0x406c04 + (i * 0x20), upper_32_bits(tpc_set ^ tpc_mask));
-		}
-	}
-}
-
-void
-nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
-{
-	struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
-
-	nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
-
-	nvc0_graph_mmio(priv, oclass->hub);
-	nvc0_graph_mmio(priv, oclass->gpc);
-	nvc0_graph_mmio(priv, oclass->zcull);
-	nvc0_graph_mmio(priv, oclass->tpc);
-	nvc0_graph_mmio(priv, oclass->ppc);
-
-	nv_wr32(priv, 0x404154, 0x00000000);
-
-	oclass->bundle(info);
-	oclass->pagepool(info);
-	oclass->attrib(info);
-	oclass->unkn(priv);
-
-	nvc0_grctx_generate_tpcid(priv);
-	nvc0_grctx_generate_r406028(priv);
-	nvc0_grctx_generate_r4060a8(priv);
-	nvc0_grctx_generate_r418bb8(priv);
-	nvc0_grctx_generate_r406800(priv);
-
-	nvc0_graph_icmd(priv, oclass->icmd);
-	nv_wr32(priv, 0x404154, 0x00000400);
-	nvc0_graph_mthd(priv, oclass->mthd);
-	nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
-}
-
-int
-nvc0_grctx_generate(struct nvc0_graph_priv *priv)
-{
-	struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
-	struct nouveau_bar *bar = nouveau_bar(priv);
-	struct nouveau_gpuobj *chan;
-	struct nvc0_grctx info;
-	int ret, i;
-
-	/* allocate memory to for a "channel", which we'll use to generate
-	 * the default context values
-	 */
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x80000 + priv->size,
-				 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan);
-	if (ret) {
-		nv_error(priv, "failed to allocate channel memory, %d\n", ret);
-		return ret;
-	}
-
-	/* PGD pointer */
-	nv_wo32(chan, 0x0200, lower_32_bits(chan->addr + 0x1000));
-	nv_wo32(chan, 0x0204, upper_32_bits(chan->addr + 0x1000));
-	nv_wo32(chan, 0x0208, 0xffffffff);
-	nv_wo32(chan, 0x020c, 0x000000ff);
-
-	/* PGT[0] pointer */
-	nv_wo32(chan, 0x1000, 0x00000000);
-	nv_wo32(chan, 0x1004, 0x00000001 | (chan->addr + 0x2000) >> 8);
-
-	/* identity-map the whole "channel" into its own vm */
-	for (i = 0; i < chan->size / 4096; i++) {
-		u64 addr = ((chan->addr + (i * 4096)) >> 8) | 1;
-		nv_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr));
-		nv_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr));
-	}
-
-	/* context pointer (virt) */
-	nv_wo32(chan, 0x0210, 0x00080004);
-	nv_wo32(chan, 0x0214, 0x00000000);
-
-	bar->flush(bar);
-
-	nv_wr32(priv, 0x100cb8, (chan->addr + 0x1000) >> 8);
-	nv_wr32(priv, 0x100cbc, 0x80000001);
-	nv_wait(priv, 0x100c80, 0x00008000, 0x00008000);
-
-	/* setup default state for mmio list construction */
-	info.priv = priv;
-	info.data = priv->mmio_data;
-	info.mmio = priv->mmio_list;
-	info.addr = 0x2000 + (i * 8);
-	info.buffer_nr = 0;
-
-	/* make channel current */
-	if (priv->firmware) {
-		nv_wr32(priv, 0x409840, 0x00000030);
-		nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12);
-		nv_wr32(priv, 0x409504, 0x00000003);
-		if (!nv_wait(priv, 0x409800, 0x00000010, 0x00000010))
-			nv_error(priv, "load_ctx timeout\n");
-
-		nv_wo32(chan, 0x8001c, 1);
-		nv_wo32(chan, 0x80020, 0);
-		nv_wo32(chan, 0x80028, 0);
-		nv_wo32(chan, 0x8002c, 0);
-		bar->flush(bar);
-	} else {
-		nv_wr32(priv, 0x409840, 0x80000000);
-		nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12);
-		nv_wr32(priv, 0x409504, 0x00000001);
-		if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000))
-			nv_error(priv, "HUB_SET_CHAN timeout\n");
-	}
-
-	oclass->main(priv, &info);
-
-	/* trigger a context unload by unsetting the "next channel valid" bit
-	 * and faking a context switch interrupt
-	 */
-	nv_mask(priv, 0x409b04, 0x80000000, 0x00000000);
-	nv_wr32(priv, 0x409000, 0x00000100);
-	if (!nv_wait(priv, 0x409b00, 0x80000000, 0x00000000)) {
-		nv_error(priv, "grctx template channel unload timeout\n");
-		ret = -EBUSY;
-		goto done;
-	}
-
-	priv->data = kmalloc(priv->size, GFP_KERNEL);
-	if (priv->data) {
-		for (i = 0; i < priv->size; i += 4)
-			priv->data[i / 4] = nv_ro32(chan, 0x80000 + i);
-		ret = 0;
-	} else {
-		ret = -ENOMEM;
-	}
-
-done:
-	nouveau_gpuobj_ref(NULL, &chan);
-	return ret;
-}
-
-struct nouveau_oclass *
-nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) {
-	.base.handle = NV_ENGCTX(GR, 0xc0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-	.main  = nvc0_grctx_generate_main,
-	.unkn  = nvc0_grctx_generate_unkn,
-	.hub   = nvc0_grctx_pack_hub,
-	.gpc   = nvc0_grctx_pack_gpc,
-	.zcull = nvc0_grctx_pack_zcull,
-	.tpc   = nvc0_grctx_pack_tpc,
-	.icmd  = nvc0_grctx_pack_icmd,
-	.mthd  = nvc0_grctx_pack_mthd,
-	.bundle = nvc0_grctx_generate_bundle,
-	.bundle_size = 0x1800,
-	.pagepool = nvc0_grctx_generate_pagepool,
-	.pagepool_size = 0x8000,
-	.attrib = nvc0_grctx_generate_attrib,
-	.attrib_nr_max = 0x324,
-	.attrib_nr = 0x218,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h
deleted file mode 100644
index c776cd715e33..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h
+++ /dev/null
@@ -1,202 +0,0 @@
-#ifndef __NVKM_GRCTX_NVC0_H__
-#define __NVKM_GRCTX_NVC0_H__
-
-#include "nvc0.h"
-
-struct nvc0_grctx {
-	struct nvc0_graph_priv *priv;
-	struct nvc0_graph_data *data;
-	struct nvc0_graph_mmio *mmio;
-	int buffer_nr;
-	u64 buffer[4];
-	u64 addr;
-};
-
-int  nvc0_grctx_mmio_data(struct nvc0_grctx *, u32 size, u32 align, u32 access);
-void nvc0_grctx_mmio_item(struct nvc0_grctx *, u32 addr, u32 data, int s, int);
-
-#define mmio_vram(a,b,c,d) nvc0_grctx_mmio_data((a), (b), (c), (d))
-#define mmio_refn(a,b,c,d,e) nvc0_grctx_mmio_item((a), (b), (c), (d), (e))
-#define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1)
-#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c),  0, -1)
-
-struct nvc0_grctx_oclass {
-	struct nouveau_oclass base;
-	/* main context generation function */
-	void  (*main)(struct nvc0_graph_priv *, struct nvc0_grctx *);
-	/* context-specific modify-on-first-load list generation function */
-	void  (*unkn)(struct nvc0_graph_priv *);
-	/* mmio context data */
-	const struct nvc0_graph_pack *hub;
-	const struct nvc0_graph_pack *gpc;
-	const struct nvc0_graph_pack *zcull;
-	const struct nvc0_graph_pack *tpc;
-	const struct nvc0_graph_pack *ppc;
-	/* indirect context data, generated with icmds/mthds */
-	const struct nvc0_graph_pack *icmd;
-	const struct nvc0_graph_pack *mthd;
-	/* bundle circular buffer */
-	void (*bundle)(struct nvc0_grctx *);
-	u32 bundle_size;
-	u32 bundle_min_gpm_fifo_depth;
-	u32 bundle_token_limit;
-	/* pagepool */
-	void (*pagepool)(struct nvc0_grctx *);
-	u32 pagepool_size;
-	/* attribute(/alpha) circular buffer */
-	void (*attrib)(struct nvc0_grctx *);
-	u32 attrib_nr_max;
-	u32 attrib_nr;
-	u32 alpha_nr_max;
-	u32 alpha_nr;
-};
-
-static inline const struct nvc0_grctx_oclass *
-nvc0_grctx_impl(struct nvc0_graph_priv *priv)
-{
-	return (void *)nv_engine(priv)->cclass;
-}
-
-extern struct nouveau_oclass *nvc0_grctx_oclass;
-int  nvc0_grctx_generate(struct nvc0_graph_priv *);
-void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
-void nvc0_grctx_generate_bundle(struct nvc0_grctx *);
-void nvc0_grctx_generate_pagepool(struct nvc0_grctx *);
-void nvc0_grctx_generate_attrib(struct nvc0_grctx *);
-void nvc0_grctx_generate_unkn(struct nvc0_graph_priv *);
-void nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *);
-void nvc0_grctx_generate_r406028(struct nvc0_graph_priv *);
-void nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *);
-void nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *);
-void nvc0_grctx_generate_r406800(struct nvc0_graph_priv *);
-
-extern struct nouveau_oclass *nvc1_grctx_oclass;
-void nvc1_grctx_generate_attrib(struct nvc0_grctx *);
-void nvc1_grctx_generate_unkn(struct nvc0_graph_priv *);
-
-extern struct nouveau_oclass *nvc4_grctx_oclass;
-extern struct nouveau_oclass *nvc8_grctx_oclass;
-
-extern struct nouveau_oclass *nvd7_grctx_oclass;
-void nvd7_grctx_generate_attrib(struct nvc0_grctx *);
-
-extern struct nouveau_oclass *nvd9_grctx_oclass;
-
-extern struct nouveau_oclass *nve4_grctx_oclass;
-extern struct nouveau_oclass *gk20a_grctx_oclass;
-void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
-void nve4_grctx_generate_bundle(struct nvc0_grctx *);
-void nve4_grctx_generate_pagepool(struct nvc0_grctx *);
-void nve4_grctx_generate_unkn(struct nvc0_graph_priv *);
-void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *);
-
-extern struct nouveau_oclass *nvf0_grctx_oclass;
-extern struct nouveau_oclass *gk110b_grctx_oclass;
-extern struct nouveau_oclass *nv108_grctx_oclass;
-extern struct nouveau_oclass *gm107_grctx_oclass;
-
-/* context init value lists */
-
-extern const struct nvc0_graph_pack nvc0_grctx_pack_icmd[];
-
-extern const struct nvc0_graph_pack nvc0_grctx_pack_mthd[];
-extern const struct nvc0_graph_init nvc0_grctx_init_902d_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_9039_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_90c0_0[];
-
-extern const struct nvc0_graph_pack nvc0_grctx_pack_hub[];
-extern const struct nvc0_graph_init nvc0_grctx_init_main_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_fe_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_pri_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_memfmt_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_rstr2d_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_scc_0[];
-
-extern const struct nvc0_graph_pack nvc0_grctx_pack_gpc[];
-extern const struct nvc0_graph_init nvc0_grctx_init_gpc_unk_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_prop_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_gpc_unk_1[];
-extern const struct nvc0_graph_init nvc0_grctx_init_zcull_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_crstr_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_gpm_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_gcc_0[];
-
-extern const struct nvc0_graph_pack nvc0_grctx_pack_zcull[];
-
-extern const struct nvc0_graph_pack nvc0_grctx_pack_tpc[];
-extern const struct nvc0_graph_init nvc0_grctx_init_pe_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_wwdx_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_mpc_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_tpccs_0[];
-
-extern const struct nvc0_graph_init nvc4_grctx_init_tex_0[];
-extern const struct nvc0_graph_init nvc4_grctx_init_l1c_0[];
-extern const struct nvc0_graph_init nvc4_grctx_init_sm_0[];
-
-extern const struct nvc0_graph_init nvc1_grctx_init_9097_0[];
-
-extern const struct nvc0_graph_init nvc1_grctx_init_gpm_0[];
-
-extern const struct nvc0_graph_init nvc1_grctx_init_pe_0[];
-extern const struct nvc0_graph_init nvc1_grctx_init_wwdx_0[];
-extern const struct nvc0_graph_init nvc1_grctx_init_tpccs_0[];
-
-extern const struct nvc0_graph_init nvc8_grctx_init_9197_0[];
-extern const struct nvc0_graph_init nvc8_grctx_init_9297_0[];
-
-extern const struct nvc0_graph_pack nvd9_grctx_pack_icmd[];
-
-extern const struct nvc0_graph_pack nvd9_grctx_pack_mthd[];
-
-extern const struct nvc0_graph_init nvd9_grctx_init_fe_0[];
-extern const struct nvc0_graph_init nvd9_grctx_init_be_0[];
-
-extern const struct nvc0_graph_init nvd9_grctx_init_prop_0[];
-extern const struct nvc0_graph_init nvd9_grctx_init_gpc_unk_1[];
-extern const struct nvc0_graph_init nvd9_grctx_init_crstr_0[];
-
-extern const struct nvc0_graph_init nvd9_grctx_init_sm_0[];
-
-extern const struct nvc0_graph_init nvd7_grctx_init_pe_0[];
-
-extern const struct nvc0_graph_init nvd7_grctx_init_wwdx_0[];
-
-extern const struct nvc0_graph_init nve4_grctx_init_memfmt_0[];
-extern const struct nvc0_graph_init nve4_grctx_init_ds_0[];
-extern const struct nvc0_graph_init nve4_grctx_init_scc_0[];
-
-extern const struct nvc0_graph_init nve4_grctx_init_gpm_0[];
-
-extern const struct nvc0_graph_init nve4_grctx_init_pes_0[];
-
-extern const struct nvc0_graph_pack nve4_grctx_pack_hub[];
-extern const struct nvc0_graph_pack nve4_grctx_pack_gpc[];
-extern const struct nvc0_graph_pack nve4_grctx_pack_tpc[];
-extern const struct nvc0_graph_pack nve4_grctx_pack_ppc[];
-extern const struct nvc0_graph_pack nve4_grctx_pack_icmd[];
-extern const struct nvc0_graph_init nve4_grctx_init_a097_0[];
-
-extern const struct nvc0_graph_pack nvf0_grctx_pack_icmd[];
-
-extern const struct nvc0_graph_pack nvf0_grctx_pack_mthd[];
-
-extern const struct nvc0_graph_pack nvf0_grctx_pack_hub[];
-extern const struct nvc0_graph_init nvf0_grctx_init_pri_0[];
-extern const struct nvc0_graph_init nvf0_grctx_init_cwd_0[];
-
-extern const struct nvc0_graph_pack nvf0_grctx_pack_gpc[];
-extern const struct nvc0_graph_init nvf0_grctx_init_gpc_unk_2[];
-
-extern const struct nvc0_graph_init nvf0_grctx_init_tex_0[];
-extern const struct nvc0_graph_init nvf0_grctx_init_mpc_0[];
-extern const struct nvc0_graph_init nvf0_grctx_init_l1c_0[];
-
-extern const struct nvc0_graph_pack nvf0_grctx_pack_ppc[];
-
-extern const struct nvc0_graph_init nv108_grctx_init_rstr2d_0[];
-
-extern const struct nvc0_graph_init nv108_grctx_init_prop_0[];
-extern const struct nvc0_graph_init nv108_grctx_init_crstr_0[];
-
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
deleted file mode 100644
index c6ba8fed18f1..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
+++ /dev/null
@@ -1,805 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * PGRAPH context register lists
- ******************************************************************************/
-
-static const struct nvc0_graph_init
-nvc1_grctx_init_icmd_0[] = {
-	{ 0x001000,   1, 0x01, 0x00000004 },
-	{ 0x0000a9,   1, 0x01, 0x0000ffff },
-	{ 0x000038,   1, 0x01, 0x0fac6881 },
-	{ 0x00003d,   1, 0x01, 0x00000001 },
-	{ 0x0000e8,   8, 0x01, 0x00000400 },
-	{ 0x000078,   8, 0x01, 0x00000300 },
-	{ 0x000050,   1, 0x01, 0x00000011 },
-	{ 0x000058,   8, 0x01, 0x00000008 },
-	{ 0x000208,   8, 0x01, 0x00000001 },
-	{ 0x000081,   1, 0x01, 0x00000001 },
-	{ 0x000085,   1, 0x01, 0x00000004 },
-	{ 0x000088,   1, 0x01, 0x00000400 },
-	{ 0x000090,   1, 0x01, 0x00000300 },
-	{ 0x000098,   1, 0x01, 0x00001001 },
-	{ 0x0000e3,   1, 0x01, 0x00000001 },
-	{ 0x0000da,   1, 0x01, 0x00000001 },
-	{ 0x0000f8,   1, 0x01, 0x00000003 },
-	{ 0x0000fa,   1, 0x01, 0x00000001 },
-	{ 0x00009f,   4, 0x01, 0x0000ffff },
-	{ 0x0000b1,   1, 0x01, 0x00000001 },
-	{ 0x0000b2,  40, 0x01, 0x00000000 },
-	{ 0x000210,   8, 0x01, 0x00000040 },
-	{ 0x000218,   8, 0x01, 0x0000c080 },
-	{ 0x0000ad,   1, 0x01, 0x0000013e },
-	{ 0x0000e1,   1, 0x01, 0x00000010 },
-	{ 0x000290,  16, 0x01, 0x00000000 },
-	{ 0x0003b0,  16, 0x01, 0x00000000 },
-	{ 0x0002a0,  16, 0x01, 0x00000000 },
-	{ 0x000420,  16, 0x01, 0x00000000 },
-	{ 0x0002b0,  16, 0x01, 0x00000000 },
-	{ 0x000430,  16, 0x01, 0x00000000 },
-	{ 0x0002c0,  16, 0x01, 0x00000000 },
-	{ 0x0004d0,  16, 0x01, 0x00000000 },
-	{ 0x000720,  16, 0x01, 0x00000000 },
-	{ 0x0008c0,  16, 0x01, 0x00000000 },
-	{ 0x000890,  16, 0x01, 0x00000000 },
-	{ 0x0008e0,  16, 0x01, 0x00000000 },
-	{ 0x0008a0,  16, 0x01, 0x00000000 },
-	{ 0x0008f0,  16, 0x01, 0x00000000 },
-	{ 0x00094c,   1, 0x01, 0x000000ff },
-	{ 0x00094d,   1, 0x01, 0xffffffff },
-	{ 0x00094e,   1, 0x01, 0x00000002 },
-	{ 0x0002ec,   1, 0x01, 0x00000001 },
-	{ 0x000303,   1, 0x01, 0x00000001 },
-	{ 0x0002e6,   1, 0x01, 0x00000001 },
-	{ 0x000466,   1, 0x01, 0x00000052 },
-	{ 0x000301,   1, 0x01, 0x3f800000 },
-	{ 0x000304,   1, 0x01, 0x30201000 },
-	{ 0x000305,   1, 0x01, 0x70605040 },
-	{ 0x000306,   1, 0x01, 0xb8a89888 },
-	{ 0x000307,   1, 0x01, 0xf8e8d8c8 },
-	{ 0x00030a,   1, 0x01, 0x00ffff00 },
-	{ 0x00030b,   1, 0x01, 0x0000001a },
-	{ 0x00030c,   1, 0x01, 0x00000001 },
-	{ 0x000318,   1, 0x01, 0x00000001 },
-	{ 0x000340,   1, 0x01, 0x00000000 },
-	{ 0x000375,   1, 0x01, 0x00000001 },
-	{ 0x000351,   1, 0x01, 0x00000100 },
-	{ 0x00037d,   1, 0x01, 0x00000006 },
-	{ 0x0003a0,   1, 0x01, 0x00000002 },
-	{ 0x0003aa,   1, 0x01, 0x00000001 },
-	{ 0x0003a9,   1, 0x01, 0x00000001 },
-	{ 0x000380,   1, 0x01, 0x00000001 },
-	{ 0x000360,   1, 0x01, 0x00000040 },
-	{ 0x000366,   2, 0x01, 0x00000000 },
-	{ 0x000368,   1, 0x01, 0x00001fff },
-	{ 0x000370,   2, 0x01, 0x00000000 },
-	{ 0x000372,   1, 0x01, 0x003fffff },
-	{ 0x00037a,   1, 0x01, 0x00000012 },
-	{ 0x0005e0,   5, 0x01, 0x00000022 },
-	{ 0x000619,   1, 0x01, 0x00000003 },
-	{ 0x000811,   1, 0x01, 0x00000003 },
-	{ 0x000812,   1, 0x01, 0x00000004 },
-	{ 0x000813,   1, 0x01, 0x00000006 },
-	{ 0x000814,   1, 0x01, 0x00000008 },
-	{ 0x000815,   1, 0x01, 0x0000000b },
-	{ 0x000800,   6, 0x01, 0x00000001 },
-	{ 0x000632,   1, 0x01, 0x00000001 },
-	{ 0x000633,   1, 0x01, 0x00000002 },
-	{ 0x000634,   1, 0x01, 0x00000003 },
-	{ 0x000635,   1, 0x01, 0x00000004 },
-	{ 0x000654,   1, 0x01, 0x3f800000 },
-	{ 0x000657,   1, 0x01, 0x3f800000 },
-	{ 0x000655,   2, 0x01, 0x3f800000 },
-	{ 0x0006cd,   1, 0x01, 0x3f800000 },
-	{ 0x0007f5,   1, 0x01, 0x3f800000 },
-	{ 0x0007dc,   1, 0x01, 0x39291909 },
-	{ 0x0007dd,   1, 0x01, 0x79695949 },
-	{ 0x0007de,   1, 0x01, 0xb9a99989 },
-	{ 0x0007df,   1, 0x01, 0xf9e9d9c9 },
-	{ 0x0007e8,   1, 0x01, 0x00003210 },
-	{ 0x0007e9,   1, 0x01, 0x00007654 },
-	{ 0x0007ea,   1, 0x01, 0x00000098 },
-	{ 0x0007ec,   1, 0x01, 0x39291909 },
-	{ 0x0007ed,   1, 0x01, 0x79695949 },
-	{ 0x0007ee,   1, 0x01, 0xb9a99989 },
-	{ 0x0007ef,   1, 0x01, 0xf9e9d9c9 },
-	{ 0x0007f0,   1, 0x01, 0x00003210 },
-	{ 0x0007f1,   1, 0x01, 0x00007654 },
-	{ 0x0007f2,   1, 0x01, 0x00000098 },
-	{ 0x0005a5,   1, 0x01, 0x00000001 },
-	{ 0x000980, 128, 0x01, 0x00000000 },
-	{ 0x000468,   1, 0x01, 0x00000004 },
-	{ 0x00046c,   1, 0x01, 0x00000001 },
-	{ 0x000470,  96, 0x01, 0x00000000 },
-	{ 0x000510,  16, 0x01, 0x3f800000 },
-	{ 0x000520,   1, 0x01, 0x000002b6 },
-	{ 0x000529,   1, 0x01, 0x00000001 },
-	{ 0x000530,  16, 0x01, 0xffff0000 },
-	{ 0x000585,   1, 0x01, 0x0000003f },
-	{ 0x000576,   1, 0x01, 0x00000003 },
-	{ 0x00057b,   1, 0x01, 0x00000059 },
-	{ 0x000586,   1, 0x01, 0x00000040 },
-	{ 0x000582,   2, 0x01, 0x00000080 },
-	{ 0x0005c2,   1, 0x01, 0x00000001 },
-	{ 0x000638,   2, 0x01, 0x00000001 },
-	{ 0x00063a,   1, 0x01, 0x00000002 },
-	{ 0x00063b,   2, 0x01, 0x00000001 },
-	{ 0x00063d,   1, 0x01, 0x00000002 },
-	{ 0x00063e,   1, 0x01, 0x00000001 },
-	{ 0x0008b8,   8, 0x01, 0x00000001 },
-	{ 0x000900,   8, 0x01, 0x00000001 },
-	{ 0x000908,   8, 0x01, 0x00000002 },
-	{ 0x000910,  16, 0x01, 0x00000001 },
-	{ 0x000920,   8, 0x01, 0x00000002 },
-	{ 0x000928,   8, 0x01, 0x00000001 },
-	{ 0x000648,   9, 0x01, 0x00000001 },
-	{ 0x000658,   1, 0x01, 0x0000000f },
-	{ 0x0007ff,   1, 0x01, 0x0000000a },
-	{ 0x00066a,   1, 0x01, 0x40000000 },
-	{ 0x00066b,   1, 0x01, 0x10000000 },
-	{ 0x00066c,   2, 0x01, 0xffff0000 },
-	{ 0x0007af,   2, 0x01, 0x00000008 },
-	{ 0x0007f6,   1, 0x01, 0x00000001 },
-	{ 0x0006b2,   1, 0x01, 0x00000055 },
-	{ 0x0007ad,   1, 0x01, 0x00000003 },
-	{ 0x000937,   1, 0x01, 0x00000001 },
-	{ 0x000971,   1, 0x01, 0x00000008 },
-	{ 0x000972,   1, 0x01, 0x00000040 },
-	{ 0x000973,   1, 0x01, 0x0000012c },
-	{ 0x00097c,   1, 0x01, 0x00000040 },
-	{ 0x000979,   1, 0x01, 0x00000003 },
-	{ 0x000975,   1, 0x01, 0x00000020 },
-	{ 0x000976,   1, 0x01, 0x00000001 },
-	{ 0x000977,   1, 0x01, 0x00000020 },
-	{ 0x000978,   1, 0x01, 0x00000001 },
-	{ 0x000957,   1, 0x01, 0x00000003 },
-	{ 0x00095e,   1, 0x01, 0x20164010 },
-	{ 0x00095f,   1, 0x01, 0x00000020 },
-	{ 0x000683,   1, 0x01, 0x00000006 },
-	{ 0x000685,   1, 0x01, 0x003fffff },
-	{ 0x000687,   1, 0x01, 0x00000c48 },
-	{ 0x0006a0,   1, 0x01, 0x00000005 },
-	{ 0x000840,   1, 0x01, 0x00300008 },
-	{ 0x000841,   1, 0x01, 0x04000080 },
-	{ 0x000842,   1, 0x01, 0x00300008 },
-	{ 0x000843,   1, 0x01, 0x04000080 },
-	{ 0x000818,   8, 0x01, 0x00000000 },
-	{ 0x000848,  16, 0x01, 0x00000000 },
-	{ 0x000738,   1, 0x01, 0x00000000 },
-	{ 0x0006aa,   1, 0x01, 0x00000001 },
-	{ 0x0006ab,   1, 0x01, 0x00000002 },
-	{ 0x0006ac,   1, 0x01, 0x00000080 },
-	{ 0x0006ad,   2, 0x01, 0x00000100 },
-	{ 0x0006b1,   1, 0x01, 0x00000011 },
-	{ 0x0006bb,   1, 0x01, 0x000000cf },
-	{ 0x0006ce,   1, 0x01, 0x2a712488 },
-	{ 0x000739,   1, 0x01, 0x4085c000 },
-	{ 0x00073a,   1, 0x01, 0x00000080 },
-	{ 0x000786,   1, 0x01, 0x80000100 },
-	{ 0x00073c,   1, 0x01, 0x00010100 },
-	{ 0x00073d,   1, 0x01, 0x02800000 },
-	{ 0x000787,   1, 0x01, 0x000000cf },
-	{ 0x00078c,   1, 0x01, 0x00000008 },
-	{ 0x000792,   1, 0x01, 0x00000001 },
-	{ 0x000794,   3, 0x01, 0x00000001 },
-	{ 0x000797,   1, 0x01, 0x000000cf },
-	{ 0x000836,   1, 0x01, 0x00000001 },
-	{ 0x00079a,   1, 0x01, 0x00000002 },
-	{ 0x000833,   1, 0x01, 0x04444480 },
-	{ 0x0007a1,   1, 0x01, 0x00000001 },
-	{ 0x0007a3,   3, 0x01, 0x00000001 },
-	{ 0x000831,   1, 0x01, 0x00000004 },
-	{ 0x00080c,   1, 0x01, 0x00000002 },
-	{ 0x00080d,   2, 0x01, 0x00000100 },
-	{ 0x00080f,   1, 0x01, 0x00000001 },
-	{ 0x000823,   1, 0x01, 0x00000002 },
-	{ 0x000824,   2, 0x01, 0x00000100 },
-	{ 0x000826,   1, 0x01, 0x00000001 },
-	{ 0x00095d,   1, 0x01, 0x00000001 },
-	{ 0x00082b,   1, 0x01, 0x00000004 },
-	{ 0x000942,   1, 0x01, 0x00010001 },
-	{ 0x000943,   1, 0x01, 0x00000001 },
-	{ 0x000944,   1, 0x01, 0x00000022 },
-	{ 0x0007c5,   1, 0x01, 0x00010001 },
-	{ 0x000834,   1, 0x01, 0x00000001 },
-	{ 0x0007c7,   1, 0x01, 0x00000001 },
-	{ 0x00c1b0,   8, 0x01, 0x0000000f },
-	{ 0x00c1b8,   1, 0x01, 0x0fac6881 },
-	{ 0x00c1b9,   1, 0x01, 0x00fac688 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000002 },
-	{ 0x0006aa,   1, 0x01, 0x00000001 },
-	{ 0x0006ad,   2, 0x01, 0x00000100 },
-	{ 0x0006b1,   1, 0x01, 0x00000011 },
-	{ 0x00078c,   1, 0x01, 0x00000008 },
-	{ 0x000792,   1, 0x01, 0x00000001 },
-	{ 0x000794,   3, 0x01, 0x00000001 },
-	{ 0x000797,   1, 0x01, 0x000000cf },
-	{ 0x00079a,   1, 0x01, 0x00000002 },
-	{ 0x000833,   1, 0x01, 0x04444480 },
-	{ 0x0007a1,   1, 0x01, 0x00000001 },
-	{ 0x0007a3,   3, 0x01, 0x00000001 },
-	{ 0x000831,   1, 0x01, 0x00000004 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000014 },
-	{ 0x000351,   1, 0x01, 0x00000100 },
-	{ 0x000957,   1, 0x01, 0x00000003 },
-	{ 0x00095d,   1, 0x01, 0x00000001 },
-	{ 0x00082b,   1, 0x01, 0x00000004 },
-	{ 0x000942,   1, 0x01, 0x00010001 },
-	{ 0x000943,   1, 0x01, 0x00000001 },
-	{ 0x0007c5,   1, 0x01, 0x00010001 },
-	{ 0x000834,   1, 0x01, 0x00000001 },
-	{ 0x0007c7,   1, 0x01, 0x00000001 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000001 },
-	{ 0x00080c,   1, 0x01, 0x00000002 },
-	{ 0x00080d,   2, 0x01, 0x00000100 },
-	{ 0x00080f,   1, 0x01, 0x00000001 },
-	{ 0x000823,   1, 0x01, 0x00000002 },
-	{ 0x000824,   2, 0x01, 0x00000100 },
-	{ 0x000826,   1, 0x01, 0x00000001 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvc1_grctx_pack_icmd[] = {
-	{ nvc1_grctx_init_icmd_0 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc1_grctx_init_9097_0[] = {
-	{ 0x000800,   8, 0x40, 0x00000000 },
-	{ 0x000804,   8, 0x40, 0x00000000 },
-	{ 0x000808,   8, 0x40, 0x00000400 },
-	{ 0x00080c,   8, 0x40, 0x00000300 },
-	{ 0x000810,   1, 0x04, 0x000000cf },
-	{ 0x000850,   7, 0x40, 0x00000000 },
-	{ 0x000814,   8, 0x40, 0x00000040 },
-	{ 0x000818,   8, 0x40, 0x00000001 },
-	{ 0x00081c,   8, 0x40, 0x00000000 },
-	{ 0x000820,   8, 0x40, 0x00000000 },
-	{ 0x002700,   8, 0x20, 0x00000000 },
-	{ 0x002704,   8, 0x20, 0x00000000 },
-	{ 0x002708,   8, 0x20, 0x00000000 },
-	{ 0x00270c,   8, 0x20, 0x00000000 },
-	{ 0x002710,   8, 0x20, 0x00014000 },
-	{ 0x002714,   8, 0x20, 0x00000040 },
-	{ 0x001c00,  16, 0x10, 0x00000000 },
-	{ 0x001c04,  16, 0x10, 0x00000000 },
-	{ 0x001c08,  16, 0x10, 0x00000000 },
-	{ 0x001c0c,  16, 0x10, 0x00000000 },
-	{ 0x001d00,  16, 0x10, 0x00000000 },
-	{ 0x001d04,  16, 0x10, 0x00000000 },
-	{ 0x001d08,  16, 0x10, 0x00000000 },
-	{ 0x001d0c,  16, 0x10, 0x00000000 },
-	{ 0x001f00,  16, 0x08, 0x00000000 },
-	{ 0x001f04,  16, 0x08, 0x00000000 },
-	{ 0x001f80,  16, 0x08, 0x00000000 },
-	{ 0x001f84,  16, 0x08, 0x00000000 },
-	{ 0x002200,   5, 0x10, 0x00000022 },
-	{ 0x002000,   1, 0x04, 0x00000000 },
-	{ 0x002040,   1, 0x04, 0x00000011 },
-	{ 0x002080,   1, 0x04, 0x00000020 },
-	{ 0x0020c0,   1, 0x04, 0x00000030 },
-	{ 0x002100,   1, 0x04, 0x00000040 },
-	{ 0x002140,   1, 0x04, 0x00000051 },
-	{ 0x00200c,   6, 0x40, 0x00000001 },
-	{ 0x002010,   1, 0x04, 0x00000000 },
-	{ 0x002050,   1, 0x04, 0x00000000 },
-	{ 0x002090,   1, 0x04, 0x00000001 },
-	{ 0x0020d0,   1, 0x04, 0x00000002 },
-	{ 0x002110,   1, 0x04, 0x00000003 },
-	{ 0x002150,   1, 0x04, 0x00000004 },
-	{ 0x000380,   4, 0x20, 0x00000000 },
-	{ 0x000384,   4, 0x20, 0x00000000 },
-	{ 0x000388,   4, 0x20, 0x00000000 },
-	{ 0x00038c,   4, 0x20, 0x00000000 },
-	{ 0x000700,   4, 0x10, 0x00000000 },
-	{ 0x000704,   4, 0x10, 0x00000000 },
-	{ 0x000708,   4, 0x10, 0x00000000 },
-	{ 0x002800, 128, 0x04, 0x00000000 },
-	{ 0x000a00,  16, 0x20, 0x00000000 },
-	{ 0x000a04,  16, 0x20, 0x00000000 },
-	{ 0x000a08,  16, 0x20, 0x00000000 },
-	{ 0x000a0c,  16, 0x20, 0x00000000 },
-	{ 0x000a10,  16, 0x20, 0x00000000 },
-	{ 0x000a14,  16, 0x20, 0x00000000 },
-	{ 0x000c00,  16, 0x10, 0x00000000 },
-	{ 0x000c04,  16, 0x10, 0x00000000 },
-	{ 0x000c08,  16, 0x10, 0x00000000 },
-	{ 0x000c0c,  16, 0x10, 0x3f800000 },
-	{ 0x000d00,   8, 0x08, 0xffff0000 },
-	{ 0x000d04,   8, 0x08, 0xffff0000 },
-	{ 0x000e00,  16, 0x10, 0x00000000 },
-	{ 0x000e04,  16, 0x10, 0xffff0000 },
-	{ 0x000e08,  16, 0x10, 0xffff0000 },
-	{ 0x000d40,   4, 0x08, 0x00000000 },
-	{ 0x000d44,   4, 0x08, 0x00000000 },
-	{ 0x001e00,   8, 0x20, 0x00000001 },
-	{ 0x001e04,   8, 0x20, 0x00000001 },
-	{ 0x001e08,   8, 0x20, 0x00000002 },
-	{ 0x001e0c,   8, 0x20, 0x00000001 },
-	{ 0x001e10,   8, 0x20, 0x00000001 },
-	{ 0x001e14,   8, 0x20, 0x00000002 },
-	{ 0x001e18,   8, 0x20, 0x00000001 },
-	{ 0x00030c,   1, 0x04, 0x00000001 },
-	{ 0x001944,   1, 0x04, 0x00000000 },
-	{ 0x001514,   1, 0x04, 0x00000000 },
-	{ 0x000d68,   1, 0x04, 0x0000ffff },
-	{ 0x00121c,   1, 0x04, 0x0fac6881 },
-	{ 0x000fac,   1, 0x04, 0x00000001 },
-	{ 0x001538,   1, 0x04, 0x00000001 },
-	{ 0x000fe0,   2, 0x04, 0x00000000 },
-	{ 0x000fe8,   1, 0x04, 0x00000014 },
-	{ 0x000fec,   1, 0x04, 0x00000040 },
-	{ 0x000ff0,   1, 0x04, 0x00000000 },
-	{ 0x00179c,   1, 0x04, 0x00000000 },
-	{ 0x001228,   1, 0x04, 0x00000400 },
-	{ 0x00122c,   1, 0x04, 0x00000300 },
-	{ 0x001230,   1, 0x04, 0x00010001 },
-	{ 0x0007f8,   1, 0x04, 0x00000000 },
-	{ 0x0015b4,   1, 0x04, 0x00000001 },
-	{ 0x0015cc,   1, 0x04, 0x00000000 },
-	{ 0x001534,   1, 0x04, 0x00000000 },
-	{ 0x000fb0,   1, 0x04, 0x00000000 },
-	{ 0x0015d0,   1, 0x04, 0x00000000 },
-	{ 0x00153c,   1, 0x04, 0x00000000 },
-	{ 0x0016b4,   1, 0x04, 0x00000003 },
-	{ 0x000fbc,   4, 0x04, 0x0000ffff },
-	{ 0x000df8,   2, 0x04, 0x00000000 },
-	{ 0x001948,   1, 0x04, 0x00000000 },
-	{ 0x001970,   1, 0x04, 0x00000001 },
-	{ 0x00161c,   1, 0x04, 0x000009f0 },
-	{ 0x000dcc,   1, 0x04, 0x00000010 },
-	{ 0x00163c,   1, 0x04, 0x00000000 },
-	{ 0x0015e4,   1, 0x04, 0x00000000 },
-	{ 0x001160,  32, 0x04, 0x25e00040 },
-	{ 0x001880,  32, 0x04, 0x00000000 },
-	{ 0x000f84,   2, 0x04, 0x00000000 },
-	{ 0x0017c8,   2, 0x04, 0x00000000 },
-	{ 0x0017d0,   1, 0x04, 0x000000ff },
-	{ 0x0017d4,   1, 0x04, 0xffffffff },
-	{ 0x0017d8,   1, 0x04, 0x00000002 },
-	{ 0x0017dc,   1, 0x04, 0x00000000 },
-	{ 0x0015f4,   2, 0x04, 0x00000000 },
-	{ 0x001434,   2, 0x04, 0x00000000 },
-	{ 0x000d74,   1, 0x04, 0x00000000 },
-	{ 0x000dec,   1, 0x04, 0x00000001 },
-	{ 0x0013a4,   1, 0x04, 0x00000000 },
-	{ 0x001318,   1, 0x04, 0x00000001 },
-	{ 0x001644,   1, 0x04, 0x00000000 },
-	{ 0x000748,   1, 0x04, 0x00000000 },
-	{ 0x000de8,   1, 0x04, 0x00000000 },
-	{ 0x001648,   1, 0x04, 0x00000000 },
-	{ 0x0012a4,   1, 0x04, 0x00000000 },
-	{ 0x001120,   4, 0x04, 0x00000000 },
-	{ 0x001118,   1, 0x04, 0x00000000 },
-	{ 0x00164c,   1, 0x04, 0x00000000 },
-	{ 0x001658,   1, 0x04, 0x00000000 },
-	{ 0x001910,   1, 0x04, 0x00000290 },
-	{ 0x001518,   1, 0x04, 0x00000000 },
-	{ 0x00165c,   1, 0x04, 0x00000001 },
-	{ 0x001520,   1, 0x04, 0x00000000 },
-	{ 0x001604,   1, 0x04, 0x00000000 },
-	{ 0x001570,   1, 0x04, 0x00000000 },
-	{ 0x0013b0,   2, 0x04, 0x3f800000 },
-	{ 0x00020c,   1, 0x04, 0x00000000 },
-	{ 0x001670,   1, 0x04, 0x30201000 },
-	{ 0x001674,   1, 0x04, 0x70605040 },
-	{ 0x001678,   1, 0x04, 0xb8a89888 },
-	{ 0x00167c,   1, 0x04, 0xf8e8d8c8 },
-	{ 0x00166c,   1, 0x04, 0x00000000 },
-	{ 0x001680,   1, 0x04, 0x00ffff00 },
-	{ 0x0012d0,   1, 0x04, 0x00000003 },
-	{ 0x0012d4,   1, 0x04, 0x00000002 },
-	{ 0x001684,   2, 0x04, 0x00000000 },
-	{ 0x000dac,   2, 0x04, 0x00001b02 },
-	{ 0x000db4,   1, 0x04, 0x00000000 },
-	{ 0x00168c,   1, 0x04, 0x00000000 },
-	{ 0x0015bc,   1, 0x04, 0x00000000 },
-	{ 0x00156c,   1, 0x04, 0x00000000 },
-	{ 0x00187c,   1, 0x04, 0x00000000 },
-	{ 0x001110,   1, 0x04, 0x00000001 },
-	{ 0x000dc0,   3, 0x04, 0x00000000 },
-	{ 0x001234,   1, 0x04, 0x00000000 },
-	{ 0x001690,   1, 0x04, 0x00000000 },
-	{ 0x0012ac,   1, 0x04, 0x00000001 },
-	{ 0x0002c4,   1, 0x04, 0x00000000 },
-	{ 0x000790,   5, 0x04, 0x00000000 },
-	{ 0x00077c,   1, 0x04, 0x00000000 },
-	{ 0x001000,   1, 0x04, 0x00000010 },
-	{ 0x0010fc,   1, 0x04, 0x00000000 },
-	{ 0x001290,   1, 0x04, 0x00000000 },
-	{ 0x000218,   1, 0x04, 0x00000010 },
-	{ 0x0012d8,   1, 0x04, 0x00000000 },
-	{ 0x0012dc,   1, 0x04, 0x00000010 },
-	{ 0x000d94,   1, 0x04, 0x00000001 },
-	{ 0x00155c,   2, 0x04, 0x00000000 },
-	{ 0x001564,   1, 0x04, 0x00001fff },
-	{ 0x001574,   2, 0x04, 0x00000000 },
-	{ 0x00157c,   1, 0x04, 0x003fffff },
-	{ 0x001354,   1, 0x04, 0x00000000 },
-	{ 0x001664,   1, 0x04, 0x00000000 },
-	{ 0x001610,   1, 0x04, 0x00000012 },
-	{ 0x001608,   2, 0x04, 0x00000000 },
-	{ 0x00162c,   1, 0x04, 0x00000003 },
-	{ 0x000210,   1, 0x04, 0x00000000 },
-	{ 0x000320,   1, 0x04, 0x00000000 },
-	{ 0x000324,   6, 0x04, 0x3f800000 },
-	{ 0x000750,   1, 0x04, 0x00000000 },
-	{ 0x000760,   1, 0x04, 0x39291909 },
-	{ 0x000764,   1, 0x04, 0x79695949 },
-	{ 0x000768,   1, 0x04, 0xb9a99989 },
-	{ 0x00076c,   1, 0x04, 0xf9e9d9c9 },
-	{ 0x000770,   1, 0x04, 0x30201000 },
-	{ 0x000774,   1, 0x04, 0x70605040 },
-	{ 0x000778,   1, 0x04, 0x00009080 },
-	{ 0x000780,   1, 0x04, 0x39291909 },
-	{ 0x000784,   1, 0x04, 0x79695949 },
-	{ 0x000788,   1, 0x04, 0xb9a99989 },
-	{ 0x00078c,   1, 0x04, 0xf9e9d9c9 },
-	{ 0x0007d0,   1, 0x04, 0x30201000 },
-	{ 0x0007d4,   1, 0x04, 0x70605040 },
-	{ 0x0007d8,   1, 0x04, 0x00009080 },
-	{ 0x00037c,   1, 0x04, 0x00000001 },
-	{ 0x000740,   2, 0x04, 0x00000000 },
-	{ 0x002600,   1, 0x04, 0x00000000 },
-	{ 0x001918,   1, 0x04, 0x00000000 },
-	{ 0x00191c,   1, 0x04, 0x00000900 },
-	{ 0x001920,   1, 0x04, 0x00000405 },
-	{ 0x001308,   1, 0x04, 0x00000001 },
-	{ 0x001924,   1, 0x04, 0x00000000 },
-	{ 0x0013ac,   1, 0x04, 0x00000000 },
-	{ 0x00192c,   1, 0x04, 0x00000001 },
-	{ 0x00193c,   1, 0x04, 0x00002c1c },
-	{ 0x000d7c,   1, 0x04, 0x00000000 },
-	{ 0x000f8c,   1, 0x04, 0x00000000 },
-	{ 0x0002c0,   1, 0x04, 0x00000001 },
-	{ 0x001510,   1, 0x04, 0x00000000 },
-	{ 0x001940,   1, 0x04, 0x00000000 },
-	{ 0x000ff4,   2, 0x04, 0x00000000 },
-	{ 0x00194c,   2, 0x04, 0x00000000 },
-	{ 0x001968,   1, 0x04, 0x00000000 },
-	{ 0x001590,   1, 0x04, 0x0000003f },
-	{ 0x0007e8,   4, 0x04, 0x00000000 },
-	{ 0x00196c,   1, 0x04, 0x00000011 },
-	{ 0x00197c,   1, 0x04, 0x00000000 },
-	{ 0x000fcc,   2, 0x04, 0x00000000 },
-	{ 0x0002d8,   1, 0x04, 0x00000040 },
-	{ 0x001980,   1, 0x04, 0x00000080 },
-	{ 0x001504,   1, 0x04, 0x00000080 },
-	{ 0x001984,   1, 0x04, 0x00000000 },
-	{ 0x000300,   1, 0x04, 0x00000001 },
-	{ 0x0013a8,   1, 0x04, 0x00000000 },
-	{ 0x0012ec,   1, 0x04, 0x00000000 },
-	{ 0x001310,   1, 0x04, 0x00000000 },
-	{ 0x001314,   1, 0x04, 0x00000001 },
-	{ 0x001380,   1, 0x04, 0x00000000 },
-	{ 0x001384,   4, 0x04, 0x00000001 },
-	{ 0x001394,   1, 0x04, 0x00000000 },
-	{ 0x00139c,   1, 0x04, 0x00000000 },
-	{ 0x001398,   1, 0x04, 0x00000000 },
-	{ 0x001594,   1, 0x04, 0x00000000 },
-	{ 0x001598,   4, 0x04, 0x00000001 },
-	{ 0x000f54,   3, 0x04, 0x00000000 },
-	{ 0x0019bc,   1, 0x04, 0x00000000 },
-	{ 0x000f9c,   2, 0x04, 0x00000000 },
-	{ 0x0012cc,   1, 0x04, 0x00000000 },
-	{ 0x0012e8,   1, 0x04, 0x00000000 },
-	{ 0x00130c,   1, 0x04, 0x00000001 },
-	{ 0x001360,   8, 0x04, 0x00000000 },
-	{ 0x00133c,   2, 0x04, 0x00000001 },
-	{ 0x001344,   1, 0x04, 0x00000002 },
-	{ 0x001348,   2, 0x04, 0x00000001 },
-	{ 0x001350,   1, 0x04, 0x00000002 },
-	{ 0x001358,   1, 0x04, 0x00000001 },
-	{ 0x0012e4,   1, 0x04, 0x00000000 },
-	{ 0x00131c,   4, 0x04, 0x00000000 },
-	{ 0x0019c0,   1, 0x04, 0x00000000 },
-	{ 0x001140,   1, 0x04, 0x00000000 },
-	{ 0x0019c4,   1, 0x04, 0x00000000 },
-	{ 0x0019c8,   1, 0x04, 0x00001500 },
-	{ 0x00135c,   1, 0x04, 0x00000000 },
-	{ 0x000f90,   1, 0x04, 0x00000000 },
-	{ 0x0019e0,   8, 0x04, 0x00000001 },
-	{ 0x0019cc,   1, 0x04, 0x00000001 },
-	{ 0x0015b8,   1, 0x04, 0x00000000 },
-	{ 0x001a00,   1, 0x04, 0x00001111 },
-	{ 0x001a04,   7, 0x04, 0x00000000 },
-	{ 0x000d6c,   2, 0x04, 0xffff0000 },
-	{ 0x0010f8,   1, 0x04, 0x00001010 },
-	{ 0x000d80,   5, 0x04, 0x00000000 },
-	{ 0x000da0,   1, 0x04, 0x00000000 },
-	{ 0x001508,   1, 0x04, 0x80000000 },
-	{ 0x00150c,   1, 0x04, 0x40000000 },
-	{ 0x001668,   1, 0x04, 0x00000000 },
-	{ 0x000318,   2, 0x04, 0x00000008 },
-	{ 0x000d9c,   1, 0x04, 0x00000001 },
-	{ 0x0007dc,   1, 0x04, 0x00000000 },
-	{ 0x00074c,   1, 0x04, 0x00000055 },
-	{ 0x001420,   1, 0x04, 0x00000003 },
-	{ 0x0017bc,   2, 0x04, 0x00000000 },
-	{ 0x0017c4,   1, 0x04, 0x00000001 },
-	{ 0x001008,   1, 0x04, 0x00000008 },
-	{ 0x00100c,   1, 0x04, 0x00000040 },
-	{ 0x001010,   1, 0x04, 0x0000012c },
-	{ 0x000d60,   1, 0x04, 0x00000040 },
-	{ 0x00075c,   1, 0x04, 0x00000003 },
-	{ 0x001018,   1, 0x04, 0x00000020 },
-	{ 0x00101c,   1, 0x04, 0x00000001 },
-	{ 0x001020,   1, 0x04, 0x00000020 },
-	{ 0x001024,   1, 0x04, 0x00000001 },
-	{ 0x001444,   3, 0x04, 0x00000000 },
-	{ 0x000360,   1, 0x04, 0x20164010 },
-	{ 0x000364,   1, 0x04, 0x00000020 },
-	{ 0x000368,   1, 0x04, 0x00000000 },
-	{ 0x000de4,   1, 0x04, 0x00000000 },
-	{ 0x000204,   1, 0x04, 0x00000006 },
-	{ 0x000208,   1, 0x04, 0x00000000 },
-	{ 0x0002cc,   1, 0x04, 0x003fffff },
-	{ 0x0002d0,   1, 0x04, 0x00000c48 },
-	{ 0x001220,   1, 0x04, 0x00000005 },
-	{ 0x000fdc,   1, 0x04, 0x00000000 },
-	{ 0x000f98,   1, 0x04, 0x00300008 },
-	{ 0x001284,   1, 0x04, 0x04000080 },
-	{ 0x001450,   1, 0x04, 0x00300008 },
-	{ 0x001454,   1, 0x04, 0x04000080 },
-	{ 0x000214,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc1_grctx_init_9197_0[] = {
-	{ 0x003400, 128, 0x04, 0x00000000 },
-	{ 0x0002e4,   1, 0x04, 0x0000b001 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvc1_grctx_pack_mthd[] = {
-	{ nvc1_grctx_init_9097_0, 0x9097 },
-	{ nvc1_grctx_init_9197_0, 0x9197 },
-	{ nvc0_grctx_init_902d_0, 0x902d },
-	{ nvc0_grctx_init_9039_0, 0x9039 },
-	{ nvc0_grctx_init_90c0_0, 0x90c0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc1_grctx_init_ds_0[] = {
-	{ 0x405800,   1, 0x04, 0x0f8000bf },
-	{ 0x405830,   1, 0x04, 0x02180218 },
-	{ 0x405834,   2, 0x04, 0x00000000 },
-	{ 0x405854,   1, 0x04, 0x00000000 },
-	{ 0x405870,   4, 0x04, 0x00000001 },
-	{ 0x405a00,   2, 0x04, 0x00000000 },
-	{ 0x405a18,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc1_grctx_init_pd_0[] = {
-	{ 0x406020,   1, 0x04, 0x000103c1 },
-	{ 0x406028,   4, 0x04, 0x00000001 },
-	{ 0x4064a8,   1, 0x04, 0x00000000 },
-	{ 0x4064ac,   1, 0x04, 0x00003fff },
-	{ 0x4064b4,   2, 0x04, 0x00000000 },
-	{ 0x4064c0,   1, 0x04, 0x80140078 },
-	{ 0x4064c4,   1, 0x04, 0x0086ffff },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc1_grctx_init_be_0[] = {
-	{ 0x408800,   1, 0x04, 0x02802a3c },
-	{ 0x408804,   1, 0x04, 0x00000040 },
-	{ 0x408808,   1, 0x04, 0x1003e005 },
-	{ 0x408900,   1, 0x04, 0x3080b801 },
-	{ 0x408904,   1, 0x04, 0x62000001 },
-	{ 0x408908,   1, 0x04, 0x00c80929 },
-	{ 0x408980,   1, 0x04, 0x0000011d },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvc1_grctx_pack_hub[] = {
-	{ nvc0_grctx_init_main_0 },
-	{ nvc0_grctx_init_fe_0 },
-	{ nvc0_grctx_init_pri_0 },
-	{ nvc0_grctx_init_memfmt_0 },
-	{ nvc1_grctx_init_ds_0 },
-	{ nvc1_grctx_init_pd_0 },
-	{ nvc0_grctx_init_rstr2d_0 },
-	{ nvc0_grctx_init_scc_0 },
-	{ nvc1_grctx_init_be_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc1_grctx_init_setup_0[] = {
-	{ 0x418800,   1, 0x04, 0x0006860a },
-	{ 0x418808,   3, 0x04, 0x00000000 },
-	{ 0x418828,   1, 0x04, 0x00008442 },
-	{ 0x418830,   1, 0x04, 0x10000001 },
-	{ 0x4188d8,   1, 0x04, 0x00000008 },
-	{ 0x4188e0,   1, 0x04, 0x01000000 },
-	{ 0x4188e8,   5, 0x04, 0x00000000 },
-	{ 0x4188fc,   1, 0x04, 0x00100018 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc1_grctx_init_gpm_0[] = {
-	{ 0x418c08,   1, 0x04, 0x00000001 },
-	{ 0x418c10,   8, 0x04, 0x00000000 },
-	{ 0x418c6c,   1, 0x04, 0x00000001 },
-	{ 0x418c80,   1, 0x04, 0x20200004 },
-	{ 0x418c8c,   1, 0x04, 0x00000001 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvc1_grctx_pack_gpc[] = {
-	{ nvc0_grctx_init_gpc_unk_0 },
-	{ nvc0_grctx_init_prop_0 },
-	{ nvc0_grctx_init_gpc_unk_1 },
-	{ nvc1_grctx_init_setup_0 },
-	{ nvc0_grctx_init_zcull_0 },
-	{ nvc0_grctx_init_crstr_0 },
-	{ nvc1_grctx_init_gpm_0 },
-	{ nvc0_grctx_init_gcc_0 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc1_grctx_init_pe_0[] = {
-	{ 0x419818,   1, 0x04, 0x00000000 },
-	{ 0x41983c,   1, 0x04, 0x00038bc7 },
-	{ 0x419848,   1, 0x04, 0x00000000 },
-	{ 0x419864,   1, 0x04, 0x00000129 },
-	{ 0x419888,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc1_grctx_init_wwdx_0[] = {
-	{ 0x419b00,   1, 0x04, 0x0a418820 },
-	{ 0x419b04,   1, 0x04, 0x062080e6 },
-	{ 0x419b08,   1, 0x04, 0x020398a4 },
-	{ 0x419b0c,   1, 0x04, 0x0e629062 },
-	{ 0x419b10,   1, 0x04, 0x0a418820 },
-	{ 0x419b14,   1, 0x04, 0x000000e6 },
-	{ 0x419bd0,   1, 0x04, 0x00900103 },
-	{ 0x419be0,   1, 0x04, 0x00400001 },
-	{ 0x419be4,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc1_grctx_init_tpccs_0[] = {
-	{ 0x419d20,   1, 0x04, 0x12180000 },
-	{ 0x419d24,   1, 0x04, 0x00001fff },
-	{ 0x419d44,   1, 0x04, 0x02180218 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvc1_grctx_pack_tpc[] = {
-	{ nvc1_grctx_init_pe_0 },
-	{ nvc4_grctx_init_tex_0 },
-	{ nvc1_grctx_init_wwdx_0 },
-	{ nvc0_grctx_init_mpc_0 },
-	{ nvc4_grctx_init_l1c_0 },
-	{ nvc1_grctx_init_tpccs_0 },
-	{ nvc4_grctx_init_sm_0 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH context implementation
- ******************************************************************************/
-
-void
-nvc1_grctx_generate_attrib(struct nvc0_grctx *info)
-{
-	struct nvc0_graph_priv *priv = info->priv;
-	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
-	const u32  alpha = impl->alpha_nr;
-	const u32   beta = impl->attrib_nr;
-	const u32   size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
-	const u32 access = NV_MEM_ACCESS_RW;
-	const int s = 12;
-	const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access);
-	const int timeslice_mode = 1;
-	const int max_batches = 0xffff;
-	u32 bo = 0;
-	u32 ao = bo + impl->attrib_nr_max * priv->tpc_total;
-	int gpc, tpc;
-
-	mmio_refn(info, 0x418810, 0x80000000, s, b);
-	mmio_refn(info, 0x419848, 0x10000000, s, b);
-	mmio_wr32(info, 0x405830, (beta << 16) | alpha);
-	mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
-
-	for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-		for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
-			const u32 a = alpha;
-			const u32 b =  beta;
-			const u32 t = timeslice_mode;
-			const u32 o = TPC_UNIT(gpc, tpc, 0x500);
-			mmio_skip(info, o + 0x20, (t << 28) | (b << 16) | ++bo);
-			mmio_wr32(info, o + 0x20, (t << 28) | (b << 16) | --bo);
-			bo += impl->attrib_nr_max;
-			mmio_wr32(info, o + 0x44, (a << 16) | ao);
-			ao += impl->alpha_nr_max;
-		}
-	}
-}
-
-void
-nvc1_grctx_generate_unkn(struct nvc0_graph_priv *priv)
-{
-	nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
-	nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
-	nv_mask(priv, 0x419814, 0x00000004, 0x00000004);
-	nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000);
-	nv_mask(priv, 0x405800, 0x08000000, 0x08000000);
-	nv_mask(priv, 0x419c00, 0x00000008, 0x00000008);
-}
-
-struct nouveau_oclass *
-nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) {
-	.base.handle = NV_ENGCTX(GR, 0xc1),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-	.main  = nvc0_grctx_generate_main,
-	.unkn  = nvc1_grctx_generate_unkn,
-	.hub   = nvc1_grctx_pack_hub,
-	.gpc   = nvc1_grctx_pack_gpc,
-	.zcull = nvc0_grctx_pack_zcull,
-	.tpc   = nvc1_grctx_pack_tpc,
-	.icmd  = nvc1_grctx_pack_icmd,
-	.mthd  = nvc1_grctx_pack_mthd,
-	.bundle = nvc0_grctx_generate_bundle,
-	.bundle_size = 0x1800,
-	.pagepool = nvc0_grctx_generate_pagepool,
-	.pagepool_size = 0x8000,
-	.attrib = nvc1_grctx_generate_attrib,
-	.attrib_nr_max = 0x324,
-	.attrib_nr = 0x218,
-	.alpha_nr_max = 0x324,
-	.alpha_nr = 0x218,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c
deleted file mode 100644
index 41705c60cc47..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * PGRAPH context register lists
- ******************************************************************************/
-
-const struct nvc0_graph_init
-nvc4_grctx_init_tex_0[] = {
-	{ 0x419a00,   1, 0x04, 0x000001f0 },
-	{ 0x419a04,   1, 0x04, 0x00000001 },
-	{ 0x419a08,   1, 0x04, 0x00000023 },
-	{ 0x419a0c,   1, 0x04, 0x00020000 },
-	{ 0x419a10,   1, 0x04, 0x00000000 },
-	{ 0x419a14,   1, 0x04, 0x00000200 },
-	{ 0x419a1c,   1, 0x04, 0x00000000 },
-	{ 0x419a20,   1, 0x04, 0x00000800 },
-	{ 0x419ac4,   1, 0x04, 0x0007f440 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc4_grctx_init_l1c_0[] = {
-	{ 0x419cb0,   1, 0x04, 0x00020048 },
-	{ 0x419ce8,   1, 0x04, 0x00000000 },
-	{ 0x419cf4,   1, 0x04, 0x00000183 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc4_grctx_init_sm_0[] = {
-	{ 0x419e04,   3, 0x04, 0x00000000 },
-	{ 0x419e10,   1, 0x04, 0x00000002 },
-	{ 0x419e44,   1, 0x04, 0x001beff2 },
-	{ 0x419e48,   1, 0x04, 0x00000000 },
-	{ 0x419e4c,   1, 0x04, 0x0000000f },
-	{ 0x419e50,  17, 0x04, 0x00000000 },
-	{ 0x419e98,   1, 0x04, 0x00000000 },
-	{ 0x419ee0,   1, 0x04, 0x00011110 },
-	{ 0x419f30,  11, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvc4_grctx_pack_tpc[] = {
-	{ nvc0_grctx_init_pe_0 },
-	{ nvc4_grctx_init_tex_0 },
-	{ nvc0_grctx_init_wwdx_0 },
-	{ nvc0_grctx_init_mpc_0 },
-	{ nvc4_grctx_init_l1c_0 },
-	{ nvc0_grctx_init_tpccs_0 },
-	{ nvc4_grctx_init_sm_0 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH context implementation
- ******************************************************************************/
-
-struct nouveau_oclass *
-nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) {
-	.base.handle = NV_ENGCTX(GR, 0xc3),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-	.main  = nvc0_grctx_generate_main,
-	.unkn  = nvc0_grctx_generate_unkn,
-	.hub   = nvc0_grctx_pack_hub,
-	.gpc   = nvc0_grctx_pack_gpc,
-	.zcull = nvc0_grctx_pack_zcull,
-	.tpc   = nvc4_grctx_pack_tpc,
-	.icmd  = nvc0_grctx_pack_icmd,
-	.mthd  = nvc0_grctx_pack_mthd,
-	.bundle = nvc0_grctx_generate_bundle,
-	.bundle_size = 0x1800,
-	.pagepool = nvc0_grctx_generate_pagepool,
-	.pagepool_size = 0x8000,
-	.attrib = nvc0_grctx_generate_attrib,
-	.attrib_nr_max = 0x324,
-	.attrib_nr = 0x218,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c
deleted file mode 100644
index 8f804cd8f9c7..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c
+++ /dev/null
@@ -1,360 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * PGRAPH context register lists
- ******************************************************************************/
-
-static const struct nvc0_graph_init
-nvc8_grctx_init_icmd_0[] = {
-	{ 0x001000,   1, 0x01, 0x00000004 },
-	{ 0x0000a9,   1, 0x01, 0x0000ffff },
-	{ 0x000038,   1, 0x01, 0x0fac6881 },
-	{ 0x00003d,   1, 0x01, 0x00000001 },
-	{ 0x0000e8,   8, 0x01, 0x00000400 },
-	{ 0x000078,   8, 0x01, 0x00000300 },
-	{ 0x000050,   1, 0x01, 0x00000011 },
-	{ 0x000058,   8, 0x01, 0x00000008 },
-	{ 0x000208,   8, 0x01, 0x00000001 },
-	{ 0x000081,   1, 0x01, 0x00000001 },
-	{ 0x000085,   1, 0x01, 0x00000004 },
-	{ 0x000088,   1, 0x01, 0x00000400 },
-	{ 0x000090,   1, 0x01, 0x00000300 },
-	{ 0x000098,   1, 0x01, 0x00001001 },
-	{ 0x0000e3,   1, 0x01, 0x00000001 },
-	{ 0x0000da,   1, 0x01, 0x00000001 },
-	{ 0x0000f8,   1, 0x01, 0x00000003 },
-	{ 0x0000fa,   1, 0x01, 0x00000001 },
-	{ 0x00009f,   4, 0x01, 0x0000ffff },
-	{ 0x0000b1,   1, 0x01, 0x00000001 },
-	{ 0x0000b2,  40, 0x01, 0x00000000 },
-	{ 0x000210,   8, 0x01, 0x00000040 },
-	{ 0x000218,   8, 0x01, 0x0000c080 },
-	{ 0x0000ad,   1, 0x01, 0x0000013e },
-	{ 0x0000e1,   1, 0x01, 0x00000010 },
-	{ 0x000290,  16, 0x01, 0x00000000 },
-	{ 0x0003b0,  16, 0x01, 0x00000000 },
-	{ 0x0002a0,  16, 0x01, 0x00000000 },
-	{ 0x000420,  16, 0x01, 0x00000000 },
-	{ 0x0002b0,  16, 0x01, 0x00000000 },
-	{ 0x000430,  16, 0x01, 0x00000000 },
-	{ 0x0002c0,  16, 0x01, 0x00000000 },
-	{ 0x0004d0,  16, 0x01, 0x00000000 },
-	{ 0x000720,  16, 0x01, 0x00000000 },
-	{ 0x0008c0,  16, 0x01, 0x00000000 },
-	{ 0x000890,  16, 0x01, 0x00000000 },
-	{ 0x0008e0,  16, 0x01, 0x00000000 },
-	{ 0x0008a0,  16, 0x01, 0x00000000 },
-	{ 0x0008f0,  16, 0x01, 0x00000000 },
-	{ 0x00094c,   1, 0x01, 0x000000ff },
-	{ 0x00094d,   1, 0x01, 0xffffffff },
-	{ 0x00094e,   1, 0x01, 0x00000002 },
-	{ 0x0002ec,   1, 0x01, 0x00000001 },
-	{ 0x000303,   1, 0x01, 0x00000001 },
-	{ 0x0002e6,   1, 0x01, 0x00000001 },
-	{ 0x000466,   1, 0x01, 0x00000052 },
-	{ 0x000301,   1, 0x01, 0x3f800000 },
-	{ 0x000304,   1, 0x01, 0x30201000 },
-	{ 0x000305,   1, 0x01, 0x70605040 },
-	{ 0x000306,   1, 0x01, 0xb8a89888 },
-	{ 0x000307,   1, 0x01, 0xf8e8d8c8 },
-	{ 0x00030a,   1, 0x01, 0x00ffff00 },
-	{ 0x00030b,   1, 0x01, 0x0000001a },
-	{ 0x00030c,   1, 0x01, 0x00000001 },
-	{ 0x000318,   1, 0x01, 0x00000001 },
-	{ 0x000340,   1, 0x01, 0x00000000 },
-	{ 0x000375,   1, 0x01, 0x00000001 },
-	{ 0x000351,   1, 0x01, 0x00000100 },
-	{ 0x00037d,   1, 0x01, 0x00000006 },
-	{ 0x0003a0,   1, 0x01, 0x00000002 },
-	{ 0x0003aa,   1, 0x01, 0x00000001 },
-	{ 0x0003a9,   1, 0x01, 0x00000001 },
-	{ 0x000380,   1, 0x01, 0x00000001 },
-	{ 0x000360,   1, 0x01, 0x00000040 },
-	{ 0x000366,   2, 0x01, 0x00000000 },
-	{ 0x000368,   1, 0x01, 0x00001fff },
-	{ 0x000370,   2, 0x01, 0x00000000 },
-	{ 0x000372,   1, 0x01, 0x003fffff },
-	{ 0x00037a,   1, 0x01, 0x00000012 },
-	{ 0x0005e0,   5, 0x01, 0x00000022 },
-	{ 0x000619,   1, 0x01, 0x00000003 },
-	{ 0x000811,   1, 0x01, 0x00000003 },
-	{ 0x000812,   1, 0x01, 0x00000004 },
-	{ 0x000813,   1, 0x01, 0x00000006 },
-	{ 0x000814,   1, 0x01, 0x00000008 },
-	{ 0x000815,   1, 0x01, 0x0000000b },
-	{ 0x000800,   6, 0x01, 0x00000001 },
-	{ 0x000632,   1, 0x01, 0x00000001 },
-	{ 0x000633,   1, 0x01, 0x00000002 },
-	{ 0x000634,   1, 0x01, 0x00000003 },
-	{ 0x000635,   1, 0x01, 0x00000004 },
-	{ 0x000654,   1, 0x01, 0x3f800000 },
-	{ 0x000657,   1, 0x01, 0x3f800000 },
-	{ 0x000655,   2, 0x01, 0x3f800000 },
-	{ 0x0006cd,   1, 0x01, 0x3f800000 },
-	{ 0x0007f5,   1, 0x01, 0x3f800000 },
-	{ 0x0007dc,   1, 0x01, 0x39291909 },
-	{ 0x0007dd,   1, 0x01, 0x79695949 },
-	{ 0x0007de,   1, 0x01, 0xb9a99989 },
-	{ 0x0007df,   1, 0x01, 0xf9e9d9c9 },
-	{ 0x0007e8,   1, 0x01, 0x00003210 },
-	{ 0x0007e9,   1, 0x01, 0x00007654 },
-	{ 0x0007ea,   1, 0x01, 0x00000098 },
-	{ 0x0007ec,   1, 0x01, 0x39291909 },
-	{ 0x0007ed,   1, 0x01, 0x79695949 },
-	{ 0x0007ee,   1, 0x01, 0xb9a99989 },
-	{ 0x0007ef,   1, 0x01, 0xf9e9d9c9 },
-	{ 0x0007f0,   1, 0x01, 0x00003210 },
-	{ 0x0007f1,   1, 0x01, 0x00007654 },
-	{ 0x0007f2,   1, 0x01, 0x00000098 },
-	{ 0x0005a5,   1, 0x01, 0x00000001 },
-	{ 0x000980, 128, 0x01, 0x00000000 },
-	{ 0x000468,   1, 0x01, 0x00000004 },
-	{ 0x00046c,   1, 0x01, 0x00000001 },
-	{ 0x000470,  96, 0x01, 0x00000000 },
-	{ 0x000510,  16, 0x01, 0x3f800000 },
-	{ 0x000520,   1, 0x01, 0x000002b6 },
-	{ 0x000529,   1, 0x01, 0x00000001 },
-	{ 0x000530,  16, 0x01, 0xffff0000 },
-	{ 0x000585,   1, 0x01, 0x0000003f },
-	{ 0x000576,   1, 0x01, 0x00000003 },
-	{ 0x00057b,   1, 0x01, 0x00000059 },
-	{ 0x000586,   1, 0x01, 0x00000040 },
-	{ 0x000582,   2, 0x01, 0x00000080 },
-	{ 0x0005c2,   1, 0x01, 0x00000001 },
-	{ 0x000638,   2, 0x01, 0x00000001 },
-	{ 0x00063a,   1, 0x01, 0x00000002 },
-	{ 0x00063b,   2, 0x01, 0x00000001 },
-	{ 0x00063d,   1, 0x01, 0x00000002 },
-	{ 0x00063e,   1, 0x01, 0x00000001 },
-	{ 0x0008b8,   8, 0x01, 0x00000001 },
-	{ 0x000900,   8, 0x01, 0x00000001 },
-	{ 0x000908,   8, 0x01, 0x00000002 },
-	{ 0x000910,  16, 0x01, 0x00000001 },
-	{ 0x000920,   8, 0x01, 0x00000002 },
-	{ 0x000928,   8, 0x01, 0x00000001 },
-	{ 0x000648,   9, 0x01, 0x00000001 },
-	{ 0x000658,   1, 0x01, 0x0000000f },
-	{ 0x0007ff,   1, 0x01, 0x0000000a },
-	{ 0x00066a,   1, 0x01, 0x40000000 },
-	{ 0x00066b,   1, 0x01, 0x10000000 },
-	{ 0x00066c,   2, 0x01, 0xffff0000 },
-	{ 0x0007af,   2, 0x01, 0x00000008 },
-	{ 0x0007f6,   1, 0x01, 0x00000001 },
-	{ 0x0006b2,   1, 0x01, 0x00000055 },
-	{ 0x0007ad,   1, 0x01, 0x00000003 },
-	{ 0x000937,   1, 0x01, 0x00000001 },
-	{ 0x000971,   1, 0x01, 0x00000008 },
-	{ 0x000972,   1, 0x01, 0x00000040 },
-	{ 0x000973,   1, 0x01, 0x0000012c },
-	{ 0x00097c,   1, 0x01, 0x00000040 },
-	{ 0x000979,   1, 0x01, 0x00000003 },
-	{ 0x000975,   1, 0x01, 0x00000020 },
-	{ 0x000976,   1, 0x01, 0x00000001 },
-	{ 0x000977,   1, 0x01, 0x00000020 },
-	{ 0x000978,   1, 0x01, 0x00000001 },
-	{ 0x000957,   1, 0x01, 0x00000003 },
-	{ 0x00095e,   1, 0x01, 0x20164010 },
-	{ 0x00095f,   1, 0x01, 0x00000020 },
-	{ 0x00097d,   1, 0x01, 0x00000020 },
-	{ 0x000683,   1, 0x01, 0x00000006 },
-	{ 0x000685,   1, 0x01, 0x003fffff },
-	{ 0x000687,   1, 0x01, 0x00000c48 },
-	{ 0x0006a0,   1, 0x01, 0x00000005 },
-	{ 0x000840,   1, 0x01, 0x00300008 },
-	{ 0x000841,   1, 0x01, 0x04000080 },
-	{ 0x000842,   1, 0x01, 0x00300008 },
-	{ 0x000843,   1, 0x01, 0x04000080 },
-	{ 0x000818,   8, 0x01, 0x00000000 },
-	{ 0x000848,  16, 0x01, 0x00000000 },
-	{ 0x000738,   1, 0x01, 0x00000000 },
-	{ 0x0006aa,   1, 0x01, 0x00000001 },
-	{ 0x0006ab,   1, 0x01, 0x00000002 },
-	{ 0x0006ac,   1, 0x01, 0x00000080 },
-	{ 0x0006ad,   2, 0x01, 0x00000100 },
-	{ 0x0006b1,   1, 0x01, 0x00000011 },
-	{ 0x0006bb,   1, 0x01, 0x000000cf },
-	{ 0x0006ce,   1, 0x01, 0x2a712488 },
-	{ 0x000739,   1, 0x01, 0x4085c000 },
-	{ 0x00073a,   1, 0x01, 0x00000080 },
-	{ 0x000786,   1, 0x01, 0x80000100 },
-	{ 0x00073c,   1, 0x01, 0x00010100 },
-	{ 0x00073d,   1, 0x01, 0x02800000 },
-	{ 0x000787,   1, 0x01, 0x000000cf },
-	{ 0x00078c,   1, 0x01, 0x00000008 },
-	{ 0x000792,   1, 0x01, 0x00000001 },
-	{ 0x000794,   3, 0x01, 0x00000001 },
-	{ 0x000797,   1, 0x01, 0x000000cf },
-	{ 0x000836,   1, 0x01, 0x00000001 },
-	{ 0x00079a,   1, 0x01, 0x00000002 },
-	{ 0x000833,   1, 0x01, 0x04444480 },
-	{ 0x0007a1,   1, 0x01, 0x00000001 },
-	{ 0x0007a3,   3, 0x01, 0x00000001 },
-	{ 0x000831,   1, 0x01, 0x00000004 },
-	{ 0x00080c,   1, 0x01, 0x00000002 },
-	{ 0x00080d,   2, 0x01, 0x00000100 },
-	{ 0x00080f,   1, 0x01, 0x00000001 },
-	{ 0x000823,   1, 0x01, 0x00000002 },
-	{ 0x000824,   2, 0x01, 0x00000100 },
-	{ 0x000826,   1, 0x01, 0x00000001 },
-	{ 0x00095d,   1, 0x01, 0x00000001 },
-	{ 0x00082b,   1, 0x01, 0x00000004 },
-	{ 0x000942,   1, 0x01, 0x00010001 },
-	{ 0x000943,   1, 0x01, 0x00000001 },
-	{ 0x000944,   1, 0x01, 0x00000022 },
-	{ 0x0007c5,   1, 0x01, 0x00010001 },
-	{ 0x000834,   1, 0x01, 0x00000001 },
-	{ 0x0007c7,   1, 0x01, 0x00000001 },
-	{ 0x00c1b0,   8, 0x01, 0x0000000f },
-	{ 0x00c1b8,   1, 0x01, 0x0fac6881 },
-	{ 0x00c1b9,   1, 0x01, 0x00fac688 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000002 },
-	{ 0x0006aa,   1, 0x01, 0x00000001 },
-	{ 0x0006ad,   2, 0x01, 0x00000100 },
-	{ 0x0006b1,   1, 0x01, 0x00000011 },
-	{ 0x00078c,   1, 0x01, 0x00000008 },
-	{ 0x000792,   1, 0x01, 0x00000001 },
-	{ 0x000794,   3, 0x01, 0x00000001 },
-	{ 0x000797,   1, 0x01, 0x000000cf },
-	{ 0x00079a,   1, 0x01, 0x00000002 },
-	{ 0x000833,   1, 0x01, 0x04444480 },
-	{ 0x0007a1,   1, 0x01, 0x00000001 },
-	{ 0x0007a3,   3, 0x01, 0x00000001 },
-	{ 0x000831,   1, 0x01, 0x00000004 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000014 },
-	{ 0x000351,   1, 0x01, 0x00000100 },
-	{ 0x000957,   1, 0x01, 0x00000003 },
-	{ 0x00095d,   1, 0x01, 0x00000001 },
-	{ 0x00082b,   1, 0x01, 0x00000004 },
-	{ 0x000942,   1, 0x01, 0x00010001 },
-	{ 0x000943,   1, 0x01, 0x00000001 },
-	{ 0x0007c5,   1, 0x01, 0x00010001 },
-	{ 0x000834,   1, 0x01, 0x00000001 },
-	{ 0x0007c7,   1, 0x01, 0x00000001 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000001 },
-	{ 0x00080c,   1, 0x01, 0x00000002 },
-	{ 0x00080d,   2, 0x01, 0x00000100 },
-	{ 0x00080f,   1, 0x01, 0x00000001 },
-	{ 0x000823,   1, 0x01, 0x00000002 },
-	{ 0x000824,   2, 0x01, 0x00000100 },
-	{ 0x000826,   1, 0x01, 0x00000001 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvc8_grctx_pack_icmd[] = {
-	{ nvc8_grctx_init_icmd_0 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc8_grctx_init_9197_0[] = {
-	{ 0x0002e4,   1, 0x04, 0x0000b001 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc8_grctx_init_9297_0[] = {
-	{ 0x003400, 128, 0x04, 0x00000000 },
-	{ 0x00036c,   2, 0x04, 0x00000000 },
-	{ 0x0007a4,   2, 0x04, 0x00000000 },
-	{ 0x000374,   1, 0x04, 0x00000000 },
-	{ 0x000378,   1, 0x04, 0x00000020 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvc8_grctx_pack_mthd[] = {
-	{ nvc1_grctx_init_9097_0, 0x9097 },
-	{ nvc8_grctx_init_9197_0, 0x9197 },
-	{ nvc8_grctx_init_9297_0, 0x9297 },
-	{ nvc0_grctx_init_902d_0, 0x902d },
-	{ nvc0_grctx_init_9039_0, 0x9039 },
-	{ nvc0_grctx_init_90c0_0, 0x90c0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc8_grctx_init_setup_0[] = {
-	{ 0x418800,   1, 0x04, 0x0006860a },
-	{ 0x418808,   3, 0x04, 0x00000000 },
-	{ 0x418828,   1, 0x04, 0x00008442 },
-	{ 0x418830,   1, 0x04, 0x00000001 },
-	{ 0x4188d8,   1, 0x04, 0x00000008 },
-	{ 0x4188e0,   1, 0x04, 0x01000000 },
-	{ 0x4188e8,   5, 0x04, 0x00000000 },
-	{ 0x4188fc,   1, 0x04, 0x20100000 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvc8_grctx_pack_gpc[] = {
-	{ nvc0_grctx_init_gpc_unk_0 },
-	{ nvc0_grctx_init_prop_0 },
-	{ nvc0_grctx_init_gpc_unk_1 },
-	{ nvc8_grctx_init_setup_0 },
-	{ nvc0_grctx_init_zcull_0 },
-	{ nvc0_grctx_init_crstr_0 },
-	{ nvc0_grctx_init_gpm_0 },
-	{ nvc0_grctx_init_gcc_0 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH context implementation
- ******************************************************************************/
-
-struct nouveau_oclass *
-nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) {
-	.base.handle = NV_ENGCTX(GR, 0xc8),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-	.main  = nvc0_grctx_generate_main,
-	.unkn  = nvc0_grctx_generate_unkn,
-	.hub   = nvc0_grctx_pack_hub,
-	.gpc   = nvc8_grctx_pack_gpc,
-	.zcull = nvc0_grctx_pack_zcull,
-	.tpc   = nvc0_grctx_pack_tpc,
-	.icmd  = nvc8_grctx_pack_icmd,
-	.mthd  = nvc8_grctx_pack_mthd,
-	.bundle = nvc0_grctx_generate_bundle,
-	.bundle_size = 0x1800,
-	.pagepool = nvc0_grctx_generate_pagepool,
-	.pagepool_size = 0x8000,
-	.attrib = nvc0_grctx_generate_attrib,
-	.attrib_nr_max = 0x324,
-	.attrib_nr = 0x218,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
deleted file mode 100644
index fcf534fd9e65..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * PGRAPH context register lists
- ******************************************************************************/
-
-static const struct nvc0_graph_init
-nvd7_grctx_init_ds_0[] = {
-	{ 0x405800,   1, 0x04, 0x0f8000bf },
-	{ 0x405830,   1, 0x04, 0x02180324 },
-	{ 0x405834,   1, 0x04, 0x08000000 },
-	{ 0x405838,   1, 0x04, 0x00000000 },
-	{ 0x405854,   1, 0x04, 0x00000000 },
-	{ 0x405870,   4, 0x04, 0x00000001 },
-	{ 0x405a00,   2, 0x04, 0x00000000 },
-	{ 0x405a18,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvd7_grctx_init_pd_0[] = {
-	{ 0x406020,   1, 0x04, 0x000103c1 },
-	{ 0x406028,   4, 0x04, 0x00000001 },
-	{ 0x4064a8,   1, 0x04, 0x00000000 },
-	{ 0x4064ac,   1, 0x04, 0x00003fff },
-	{ 0x4064b4,   3, 0x04, 0x00000000 },
-	{ 0x4064c0,   1, 0x04, 0x801a0078 },
-	{ 0x4064c4,   1, 0x04, 0x00c9ffff },
-	{ 0x4064d0,   8, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvd7_grctx_pack_hub[] = {
-	{ nvc0_grctx_init_main_0 },
-	{ nvd9_grctx_init_fe_0 },
-	{ nvc0_grctx_init_pri_0 },
-	{ nvc0_grctx_init_memfmt_0 },
-	{ nvd7_grctx_init_ds_0 },
-	{ nvd7_grctx_init_pd_0 },
-	{ nvc0_grctx_init_rstr2d_0 },
-	{ nvc0_grctx_init_scc_0 },
-	{ nvd9_grctx_init_be_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvd7_grctx_init_setup_0[] = {
-	{ 0x418800,   1, 0x04, 0x7006860a },
-	{ 0x418808,   3, 0x04, 0x00000000 },
-	{ 0x418828,   1, 0x04, 0x00008442 },
-	{ 0x418830,   1, 0x04, 0x10000001 },
-	{ 0x4188d8,   1, 0x04, 0x00000008 },
-	{ 0x4188e0,   1, 0x04, 0x01000000 },
-	{ 0x4188e8,   5, 0x04, 0x00000000 },
-	{ 0x4188fc,   1, 0x04, 0x20100018 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvd7_grctx_pack_gpc[] = {
-	{ nvc0_grctx_init_gpc_unk_0 },
-	{ nvd9_grctx_init_prop_0 },
-	{ nvd9_grctx_init_gpc_unk_1 },
-	{ nvd7_grctx_init_setup_0 },
-	{ nvc0_grctx_init_zcull_0 },
-	{ nvd9_grctx_init_crstr_0 },
-	{ nvc1_grctx_init_gpm_0 },
-	{ nvc0_grctx_init_gcc_0 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvd7_grctx_init_pe_0[] = {
-	{ 0x419848,   1, 0x04, 0x00000000 },
-	{ 0x419864,   1, 0x04, 0x00000129 },
-	{ 0x419888,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvd7_grctx_init_tex_0[] = {
-	{ 0x419a00,   1, 0x04, 0x000001f0 },
-	{ 0x419a04,   1, 0x04, 0x00000001 },
-	{ 0x419a08,   1, 0x04, 0x00000023 },
-	{ 0x419a0c,   1, 0x04, 0x00020000 },
-	{ 0x419a10,   1, 0x04, 0x00000000 },
-	{ 0x419a14,   1, 0x04, 0x00000200 },
-	{ 0x419a1c,   1, 0x04, 0x00008000 },
-	{ 0x419a20,   1, 0x04, 0x00000800 },
-	{ 0x419ac4,   1, 0x04, 0x0017f440 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvd7_grctx_init_mpc_0[] = {
-	{ 0x419c00,   1, 0x04, 0x0000000a },
-	{ 0x419c04,   1, 0x04, 0x00000006 },
-	{ 0x419c08,   1, 0x04, 0x00000002 },
-	{ 0x419c20,   1, 0x04, 0x00000000 },
-	{ 0x419c24,   1, 0x04, 0x00084210 },
-	{ 0x419c28,   1, 0x04, 0x3efbefbe },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvd7_grctx_pack_tpc[] = {
-	{ nvd7_grctx_init_pe_0 },
-	{ nvd7_grctx_init_tex_0 },
-	{ nvd7_grctx_init_mpc_0 },
-	{ nvc4_grctx_init_l1c_0 },
-	{ nvd9_grctx_init_sm_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvd7_grctx_init_pes_0[] = {
-	{ 0x41be24,   1, 0x04, 0x00000002 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvd7_grctx_init_cbm_0[] = {
-	{ 0x41bec0,   1, 0x04, 0x12180000 },
-	{ 0x41bec4,   1, 0x04, 0x00003fff },
-	{ 0x41bee4,   1, 0x04, 0x03240218 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvd7_grctx_init_wwdx_0[] = {
-	{ 0x41bf00,   1, 0x04, 0x0a418820 },
-	{ 0x41bf04,   1, 0x04, 0x062080e6 },
-	{ 0x41bf08,   1, 0x04, 0x020398a4 },
-	{ 0x41bf0c,   1, 0x04, 0x0e629062 },
-	{ 0x41bf10,   1, 0x04, 0x0a418820 },
-	{ 0x41bf14,   1, 0x04, 0x000000e6 },
-	{ 0x41bfd0,   1, 0x04, 0x00900103 },
-	{ 0x41bfe0,   1, 0x04, 0x00400001 },
-	{ 0x41bfe4,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvd7_grctx_pack_ppc[] = {
-	{ nvd7_grctx_init_pes_0 },
-	{ nvd7_grctx_init_cbm_0 },
-	{ nvd7_grctx_init_wwdx_0 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH context implementation
- ******************************************************************************/
-
-void
-nvd7_grctx_generate_attrib(struct nvc0_grctx *info)
-{
-	struct nvc0_graph_priv *priv = info->priv;
-	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
-	const u32  alpha = impl->alpha_nr;
-	const u32   beta = impl->attrib_nr;
-	const u32   size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
-	const u32 access = NV_MEM_ACCESS_RW;
-	const int s = 12;
-	const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access);
-	const int timeslice_mode = 1;
-	const int max_batches = 0xffff;
-	u32 bo = 0;
-	u32 ao = bo + impl->attrib_nr_max * priv->tpc_total;
-	int gpc, ppc;
-
-	mmio_refn(info, 0x418810, 0x80000000, s, b);
-	mmio_refn(info, 0x419848, 0x10000000, s, b);
-	mmio_wr32(info, 0x405830, (beta << 16) | alpha);
-	mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
-
-	for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-		for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++) {
-			const u32 a = alpha * priv->ppc_tpc_nr[gpc][ppc];
-			const u32 b =  beta * priv->ppc_tpc_nr[gpc][ppc];
-			const u32 t = timeslice_mode;
-			const u32 o = PPC_UNIT(gpc, ppc, 0);
-			mmio_skip(info, o + 0xc0, (t << 28) | (b << 16) | ++bo);
-			mmio_wr32(info, o + 0xc0, (t << 28) | (b << 16) | --bo);
-			bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc];
-			mmio_wr32(info, o + 0xe4, (a << 16) | ao);
-			ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc];
-		}
-	}
-}
-
-void
-nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
-{
-	struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
-	int i;
-
-	nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
-
-	nvc0_graph_mmio(priv, oclass->hub);
-	nvc0_graph_mmio(priv, oclass->gpc);
-	nvc0_graph_mmio(priv, oclass->zcull);
-	nvc0_graph_mmio(priv, oclass->tpc);
-	nvc0_graph_mmio(priv, oclass->ppc);
-
-	nv_wr32(priv, 0x404154, 0x00000000);
-
-	oclass->bundle(info);
-	oclass->pagepool(info);
-	oclass->attrib(info);
-	oclass->unkn(priv);
-
-	nvc0_grctx_generate_tpcid(priv);
-	nvc0_grctx_generate_r406028(priv);
-	nvc0_grctx_generate_r4060a8(priv);
-	nve4_grctx_generate_r418bb8(priv);
-	nvc0_grctx_generate_r406800(priv);
-
-	for (i = 0; i < 8; i++)
-		nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
-
-	nvc0_graph_icmd(priv, oclass->icmd);
-	nv_wr32(priv, 0x404154, 0x00000400);
-	nvc0_graph_mthd(priv, oclass->mthd);
-	nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
-}
-
-struct nouveau_oclass *
-nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
-	.base.handle = NV_ENGCTX(GR, 0xd7),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-	.main  = nvd7_grctx_generate_main,
-	.unkn  = nve4_grctx_generate_unkn,
-	.hub   = nvd7_grctx_pack_hub,
-	.gpc   = nvd7_grctx_pack_gpc,
-	.zcull = nvc0_grctx_pack_zcull,
-	.tpc   = nvd7_grctx_pack_tpc,
-	.ppc   = nvd7_grctx_pack_ppc,
-	.icmd  = nvd9_grctx_pack_icmd,
-	.mthd  = nvd9_grctx_pack_mthd,
-	.bundle = nvc0_grctx_generate_bundle,
-	.bundle_size = 0x1800,
-	.pagepool = nvc0_grctx_generate_pagepool,
-	.pagepool_size = 0x8000,
-	.attrib = nvd7_grctx_generate_attrib,
-	.attrib_nr_max = 0x324,
-	.attrib_nr = 0x218,
-	.alpha_nr_max = 0x7ff,
-	.alpha_nr = 0x324,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
deleted file mode 100644
index b9a301b6fd9f..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
+++ /dev/null
@@ -1,530 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * PGRAPH context register lists
- ******************************************************************************/
-
-static const struct nvc0_graph_init
-nvd9_grctx_init_icmd_0[] = {
-	{ 0x001000,   1, 0x01, 0x00000004 },
-	{ 0x0000a9,   1, 0x01, 0x0000ffff },
-	{ 0x000038,   1, 0x01, 0x0fac6881 },
-	{ 0x00003d,   1, 0x01, 0x00000001 },
-	{ 0x0000e8,   8, 0x01, 0x00000400 },
-	{ 0x000078,   8, 0x01, 0x00000300 },
-	{ 0x000050,   1, 0x01, 0x00000011 },
-	{ 0x000058,   8, 0x01, 0x00000008 },
-	{ 0x000208,   8, 0x01, 0x00000001 },
-	{ 0x000081,   1, 0x01, 0x00000001 },
-	{ 0x000085,   1, 0x01, 0x00000004 },
-	{ 0x000088,   1, 0x01, 0x00000400 },
-	{ 0x000090,   1, 0x01, 0x00000300 },
-	{ 0x000098,   1, 0x01, 0x00001001 },
-	{ 0x0000e3,   1, 0x01, 0x00000001 },
-	{ 0x0000da,   1, 0x01, 0x00000001 },
-	{ 0x0000f8,   1, 0x01, 0x00000003 },
-	{ 0x0000fa,   1, 0x01, 0x00000001 },
-	{ 0x00009f,   4, 0x01, 0x0000ffff },
-	{ 0x0000b1,   1, 0x01, 0x00000001 },
-	{ 0x0000b2,  40, 0x01, 0x00000000 },
-	{ 0x000210,   8, 0x01, 0x00000040 },
-	{ 0x000400,  24, 0x01, 0x00000040 },
-	{ 0x000218,   8, 0x01, 0x0000c080 },
-	{ 0x000440,  24, 0x01, 0x0000c080 },
-	{ 0x0000ad,   1, 0x01, 0x0000013e },
-	{ 0x0000e1,   1, 0x01, 0x00000010 },
-	{ 0x000290,  16, 0x01, 0x00000000 },
-	{ 0x0003b0,  16, 0x01, 0x00000000 },
-	{ 0x0002a0,  16, 0x01, 0x00000000 },
-	{ 0x000420,  16, 0x01, 0x00000000 },
-	{ 0x0002b0,  16, 0x01, 0x00000000 },
-	{ 0x000430,  16, 0x01, 0x00000000 },
-	{ 0x0002c0,  16, 0x01, 0x00000000 },
-	{ 0x0004d0,  16, 0x01, 0x00000000 },
-	{ 0x000720,  16, 0x01, 0x00000000 },
-	{ 0x0008c0,  16, 0x01, 0x00000000 },
-	{ 0x000890,  16, 0x01, 0x00000000 },
-	{ 0x0008e0,  16, 0x01, 0x00000000 },
-	{ 0x0008a0,  16, 0x01, 0x00000000 },
-	{ 0x0008f0,  16, 0x01, 0x00000000 },
-	{ 0x00094c,   1, 0x01, 0x000000ff },
-	{ 0x00094d,   1, 0x01, 0xffffffff },
-	{ 0x00094e,   1, 0x01, 0x00000002 },
-	{ 0x0002ec,   1, 0x01, 0x00000001 },
-	{ 0x000303,   1, 0x01, 0x00000001 },
-	{ 0x0002e6,   1, 0x01, 0x00000001 },
-	{ 0x000466,   1, 0x01, 0x00000052 },
-	{ 0x000301,   1, 0x01, 0x3f800000 },
-	{ 0x000304,   1, 0x01, 0x30201000 },
-	{ 0x000305,   1, 0x01, 0x70605040 },
-	{ 0x000306,   1, 0x01, 0xb8a89888 },
-	{ 0x000307,   1, 0x01, 0xf8e8d8c8 },
-	{ 0x00030a,   1, 0x01, 0x00ffff00 },
-	{ 0x00030b,   1, 0x01, 0x0000001a },
-	{ 0x00030c,   1, 0x01, 0x00000001 },
-	{ 0x000318,   1, 0x01, 0x00000001 },
-	{ 0x000340,   1, 0x01, 0x00000000 },
-	{ 0x000375,   1, 0x01, 0x00000001 },
-	{ 0x000351,   1, 0x01, 0x00000100 },
-	{ 0x00037d,   1, 0x01, 0x00000006 },
-	{ 0x0003a0,   1, 0x01, 0x00000002 },
-	{ 0x0003aa,   1, 0x01, 0x00000001 },
-	{ 0x0003a9,   1, 0x01, 0x00000001 },
-	{ 0x000380,   1, 0x01, 0x00000001 },
-	{ 0x000360,   1, 0x01, 0x00000040 },
-	{ 0x000366,   2, 0x01, 0x00000000 },
-	{ 0x000368,   1, 0x01, 0x00001fff },
-	{ 0x000370,   2, 0x01, 0x00000000 },
-	{ 0x000372,   1, 0x01, 0x003fffff },
-	{ 0x00037a,   1, 0x01, 0x00000012 },
-	{ 0x0005e0,   5, 0x01, 0x00000022 },
-	{ 0x000619,   1, 0x01, 0x00000003 },
-	{ 0x000811,   1, 0x01, 0x00000003 },
-	{ 0x000812,   1, 0x01, 0x00000004 },
-	{ 0x000813,   1, 0x01, 0x00000006 },
-	{ 0x000814,   1, 0x01, 0x00000008 },
-	{ 0x000815,   1, 0x01, 0x0000000b },
-	{ 0x000800,   6, 0x01, 0x00000001 },
-	{ 0x000632,   1, 0x01, 0x00000001 },
-	{ 0x000633,   1, 0x01, 0x00000002 },
-	{ 0x000634,   1, 0x01, 0x00000003 },
-	{ 0x000635,   1, 0x01, 0x00000004 },
-	{ 0x000654,   1, 0x01, 0x3f800000 },
-	{ 0x000657,   1, 0x01, 0x3f800000 },
-	{ 0x000655,   2, 0x01, 0x3f800000 },
-	{ 0x0006cd,   1, 0x01, 0x3f800000 },
-	{ 0x0007f5,   1, 0x01, 0x3f800000 },
-	{ 0x0007dc,   1, 0x01, 0x39291909 },
-	{ 0x0007dd,   1, 0x01, 0x79695949 },
-	{ 0x0007de,   1, 0x01, 0xb9a99989 },
-	{ 0x0007df,   1, 0x01, 0xf9e9d9c9 },
-	{ 0x0007e8,   1, 0x01, 0x00003210 },
-	{ 0x0007e9,   1, 0x01, 0x00007654 },
-	{ 0x0007ea,   1, 0x01, 0x00000098 },
-	{ 0x0007ec,   1, 0x01, 0x39291909 },
-	{ 0x0007ed,   1, 0x01, 0x79695949 },
-	{ 0x0007ee,   1, 0x01, 0xb9a99989 },
-	{ 0x0007ef,   1, 0x01, 0xf9e9d9c9 },
-	{ 0x0007f0,   1, 0x01, 0x00003210 },
-	{ 0x0007f1,   1, 0x01, 0x00007654 },
-	{ 0x0007f2,   1, 0x01, 0x00000098 },
-	{ 0x0005a5,   1, 0x01, 0x00000001 },
-	{ 0x000980, 128, 0x01, 0x00000000 },
-	{ 0x000468,   1, 0x01, 0x00000004 },
-	{ 0x00046c,   1, 0x01, 0x00000001 },
-	{ 0x000470,  96, 0x01, 0x00000000 },
-	{ 0x000510,  16, 0x01, 0x3f800000 },
-	{ 0x000520,   1, 0x01, 0x000002b6 },
-	{ 0x000529,   1, 0x01, 0x00000001 },
-	{ 0x000530,  16, 0x01, 0xffff0000 },
-	{ 0x000585,   1, 0x01, 0x0000003f },
-	{ 0x000576,   1, 0x01, 0x00000003 },
-	{ 0x00057b,   1, 0x01, 0x00000059 },
-	{ 0x000586,   1, 0x01, 0x00000040 },
-	{ 0x000582,   2, 0x01, 0x00000080 },
-	{ 0x0005c2,   1, 0x01, 0x00000001 },
-	{ 0x000638,   2, 0x01, 0x00000001 },
-	{ 0x00063a,   1, 0x01, 0x00000002 },
-	{ 0x00063b,   2, 0x01, 0x00000001 },
-	{ 0x00063d,   1, 0x01, 0x00000002 },
-	{ 0x00063e,   1, 0x01, 0x00000001 },
-	{ 0x0008b8,   8, 0x01, 0x00000001 },
-	{ 0x000900,   8, 0x01, 0x00000001 },
-	{ 0x000908,   8, 0x01, 0x00000002 },
-	{ 0x000910,  16, 0x01, 0x00000001 },
-	{ 0x000920,   8, 0x01, 0x00000002 },
-	{ 0x000928,   8, 0x01, 0x00000001 },
-	{ 0x000648,   9, 0x01, 0x00000001 },
-	{ 0x000658,   1, 0x01, 0x0000000f },
-	{ 0x0007ff,   1, 0x01, 0x0000000a },
-	{ 0x00066a,   1, 0x01, 0x40000000 },
-	{ 0x00066b,   1, 0x01, 0x10000000 },
-	{ 0x00066c,   2, 0x01, 0xffff0000 },
-	{ 0x0007af,   2, 0x01, 0x00000008 },
-	{ 0x0007f6,   1, 0x01, 0x00000001 },
-	{ 0x0006b2,   1, 0x01, 0x00000055 },
-	{ 0x0007ad,   1, 0x01, 0x00000003 },
-	{ 0x000937,   1, 0x01, 0x00000001 },
-	{ 0x000971,   1, 0x01, 0x00000008 },
-	{ 0x000972,   1, 0x01, 0x00000040 },
-	{ 0x000973,   1, 0x01, 0x0000012c },
-	{ 0x00097c,   1, 0x01, 0x00000040 },
-	{ 0x000979,   1, 0x01, 0x00000003 },
-	{ 0x000975,   1, 0x01, 0x00000020 },
-	{ 0x000976,   1, 0x01, 0x00000001 },
-	{ 0x000977,   1, 0x01, 0x00000020 },
-	{ 0x000978,   1, 0x01, 0x00000001 },
-	{ 0x000957,   1, 0x01, 0x00000003 },
-	{ 0x00095e,   1, 0x01, 0x20164010 },
-	{ 0x00095f,   1, 0x01, 0x00000020 },
-	{ 0x00097d,   1, 0x01, 0x00000020 },
-	{ 0x000683,   1, 0x01, 0x00000006 },
-	{ 0x000685,   1, 0x01, 0x003fffff },
-	{ 0x000687,   1, 0x01, 0x00000c48 },
-	{ 0x0006a0,   1, 0x01, 0x00000005 },
-	{ 0x000840,   1, 0x01, 0x00300008 },
-	{ 0x000841,   1, 0x01, 0x04000080 },
-	{ 0x000842,   1, 0x01, 0x00300008 },
-	{ 0x000843,   1, 0x01, 0x04000080 },
-	{ 0x000818,   8, 0x01, 0x00000000 },
-	{ 0x000848,  16, 0x01, 0x00000000 },
-	{ 0x000738,   1, 0x01, 0x00000000 },
-	{ 0x0006aa,   1, 0x01, 0x00000001 },
-	{ 0x0006ab,   1, 0x01, 0x00000002 },
-	{ 0x0006ac,   1, 0x01, 0x00000080 },
-	{ 0x0006ad,   2, 0x01, 0x00000100 },
-	{ 0x0006b1,   1, 0x01, 0x00000011 },
-	{ 0x0006bb,   1, 0x01, 0x000000cf },
-	{ 0x0006ce,   1, 0x01, 0x2a712488 },
-	{ 0x000739,   1, 0x01, 0x4085c000 },
-	{ 0x00073a,   1, 0x01, 0x00000080 },
-	{ 0x000786,   1, 0x01, 0x80000100 },
-	{ 0x00073c,   1, 0x01, 0x00010100 },
-	{ 0x00073d,   1, 0x01, 0x02800000 },
-	{ 0x000787,   1, 0x01, 0x000000cf },
-	{ 0x00078c,   1, 0x01, 0x00000008 },
-	{ 0x000792,   1, 0x01, 0x00000001 },
-	{ 0x000794,   3, 0x01, 0x00000001 },
-	{ 0x000797,   1, 0x01, 0x000000cf },
-	{ 0x000836,   1, 0x01, 0x00000001 },
-	{ 0x00079a,   1, 0x01, 0x00000002 },
-	{ 0x000833,   1, 0x01, 0x04444480 },
-	{ 0x0007a1,   1, 0x01, 0x00000001 },
-	{ 0x0007a3,   3, 0x01, 0x00000001 },
-	{ 0x000831,   1, 0x01, 0x00000004 },
-	{ 0x00080c,   1, 0x01, 0x00000002 },
-	{ 0x00080d,   2, 0x01, 0x00000100 },
-	{ 0x00080f,   1, 0x01, 0x00000001 },
-	{ 0x000823,   1, 0x01, 0x00000002 },
-	{ 0x000824,   2, 0x01, 0x00000100 },
-	{ 0x000826,   1, 0x01, 0x00000001 },
-	{ 0x00095d,   1, 0x01, 0x00000001 },
-	{ 0x00082b,   1, 0x01, 0x00000004 },
-	{ 0x000942,   1, 0x01, 0x00010001 },
-	{ 0x000943,   1, 0x01, 0x00000001 },
-	{ 0x000944,   1, 0x01, 0x00000022 },
-	{ 0x0007c5,   1, 0x01, 0x00010001 },
-	{ 0x000834,   1, 0x01, 0x00000001 },
-	{ 0x0007c7,   1, 0x01, 0x00000001 },
-	{ 0x00c1b0,   8, 0x01, 0x0000000f },
-	{ 0x00c1b8,   1, 0x01, 0x0fac6881 },
-	{ 0x00c1b9,   1, 0x01, 0x00fac688 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000002 },
-	{ 0x0006aa,   1, 0x01, 0x00000001 },
-	{ 0x0006ad,   2, 0x01, 0x00000100 },
-	{ 0x0006b1,   1, 0x01, 0x00000011 },
-	{ 0x00078c,   1, 0x01, 0x00000008 },
-	{ 0x000792,   1, 0x01, 0x00000001 },
-	{ 0x000794,   3, 0x01, 0x00000001 },
-	{ 0x000797,   1, 0x01, 0x000000cf },
-	{ 0x00079a,   1, 0x01, 0x00000002 },
-	{ 0x000833,   1, 0x01, 0x04444480 },
-	{ 0x0007a1,   1, 0x01, 0x00000001 },
-	{ 0x0007a3,   3, 0x01, 0x00000001 },
-	{ 0x000831,   1, 0x01, 0x00000004 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000014 },
-	{ 0x000351,   1, 0x01, 0x00000100 },
-	{ 0x000957,   1, 0x01, 0x00000003 },
-	{ 0x00095d,   1, 0x01, 0x00000001 },
-	{ 0x00082b,   1, 0x01, 0x00000004 },
-	{ 0x000942,   1, 0x01, 0x00010001 },
-	{ 0x000943,   1, 0x01, 0x00000001 },
-	{ 0x0007c5,   1, 0x01, 0x00010001 },
-	{ 0x000834,   1, 0x01, 0x00000001 },
-	{ 0x0007c7,   1, 0x01, 0x00000001 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000001 },
-	{ 0x00080c,   1, 0x01, 0x00000002 },
-	{ 0x00080d,   2, 0x01, 0x00000100 },
-	{ 0x00080f,   1, 0x01, 0x00000001 },
-	{ 0x000823,   1, 0x01, 0x00000002 },
-	{ 0x000824,   2, 0x01, 0x00000100 },
-	{ 0x000826,   1, 0x01, 0x00000001 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{}
-};
-
-const struct nvc0_graph_pack
-nvd9_grctx_pack_icmd[] = {
-	{ nvd9_grctx_init_icmd_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvd9_grctx_init_90c0_0[] = {
-	{ 0x002700,   8, 0x20, 0x00000000 },
-	{ 0x002704,   8, 0x20, 0x00000000 },
-	{ 0x002708,   8, 0x20, 0x00000000 },
-	{ 0x00270c,   8, 0x20, 0x00000000 },
-	{ 0x002710,   8, 0x20, 0x00014000 },
-	{ 0x002714,   8, 0x20, 0x00000040 },
-	{ 0x00030c,   1, 0x04, 0x00000001 },
-	{ 0x001944,   1, 0x04, 0x00000000 },
-	{ 0x000758,   1, 0x04, 0x00000100 },
-	{ 0x0002c4,   1, 0x04, 0x00000000 },
-	{ 0x000790,   5, 0x04, 0x00000000 },
-	{ 0x00077c,   1, 0x04, 0x00000000 },
-	{ 0x000204,   3, 0x04, 0x00000000 },
-	{ 0x000214,   1, 0x04, 0x00000000 },
-	{ 0x00024c,   1, 0x04, 0x00000000 },
-	{ 0x000d94,   1, 0x04, 0x00000001 },
-	{ 0x001608,   2, 0x04, 0x00000000 },
-	{ 0x001664,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_pack
-nvd9_grctx_pack_mthd[] = {
-	{ nvc1_grctx_init_9097_0, 0x9097 },
-	{ nvc8_grctx_init_9197_0, 0x9197 },
-	{ nvc8_grctx_init_9297_0, 0x9297 },
-	{ nvc0_grctx_init_902d_0, 0x902d },
-	{ nvc0_grctx_init_9039_0, 0x9039 },
-	{ nvd9_grctx_init_90c0_0, 0x90c0 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvd9_grctx_init_fe_0[] = {
-	{ 0x404004,  10, 0x04, 0x00000000 },
-	{ 0x404044,   1, 0x04, 0x00000000 },
-	{ 0x404094,  13, 0x04, 0x00000000 },
-	{ 0x4040c8,   1, 0x04, 0xf0000087 },
-	{ 0x4040d0,   6, 0x04, 0x00000000 },
-	{ 0x4040e8,   1, 0x04, 0x00001000 },
-	{ 0x4040f8,   1, 0x04, 0x00000000 },
-	{ 0x404130,   2, 0x04, 0x00000000 },
-	{ 0x404138,   1, 0x04, 0x20000040 },
-	{ 0x404150,   1, 0x04, 0x0000002e },
-	{ 0x404154,   1, 0x04, 0x00000400 },
-	{ 0x404158,   1, 0x04, 0x00000200 },
-	{ 0x404164,   1, 0x04, 0x00000055 },
-	{ 0x404168,   1, 0x04, 0x00000000 },
-	{ 0x404178,   2, 0x04, 0x00000000 },
-	{ 0x404200,   8, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvd9_grctx_init_ds_0[] = {
-	{ 0x405800,   1, 0x04, 0x0f8000bf },
-	{ 0x405830,   1, 0x04, 0x02180218 },
-	{ 0x405834,   1, 0x04, 0x08000000 },
-	{ 0x405838,   1, 0x04, 0x00000000 },
-	{ 0x405854,   1, 0x04, 0x00000000 },
-	{ 0x405870,   4, 0x04, 0x00000001 },
-	{ 0x405a00,   2, 0x04, 0x00000000 },
-	{ 0x405a18,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvd9_grctx_init_pd_0[] = {
-	{ 0x406020,   1, 0x04, 0x000103c1 },
-	{ 0x406028,   4, 0x04, 0x00000001 },
-	{ 0x4064a8,   1, 0x04, 0x00000000 },
-	{ 0x4064ac,   1, 0x04, 0x00003fff },
-	{ 0x4064b4,   3, 0x04, 0x00000000 },
-	{ 0x4064c0,   1, 0x04, 0x80140078 },
-	{ 0x4064c4,   1, 0x04, 0x0086ffff },
-	{}
-};
-
-const struct nvc0_graph_init
-nvd9_grctx_init_be_0[] = {
-	{ 0x408800,   1, 0x04, 0x02802a3c },
-	{ 0x408804,   1, 0x04, 0x00000040 },
-	{ 0x408808,   1, 0x04, 0x1043e005 },
-	{ 0x408900,   1, 0x04, 0x3080b801 },
-	{ 0x408904,   1, 0x04, 0x62000001 },
-	{ 0x408908,   1, 0x04, 0x00c8102f },
-	{ 0x408980,   1, 0x04, 0x0000011d },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvd9_grctx_pack_hub[] = {
-	{ nvc0_grctx_init_main_0 },
-	{ nvd9_grctx_init_fe_0 },
-	{ nvc0_grctx_init_pri_0 },
-	{ nvc0_grctx_init_memfmt_0 },
-	{ nvd9_grctx_init_ds_0 },
-	{ nvd9_grctx_init_pd_0 },
-	{ nvc0_grctx_init_rstr2d_0 },
-	{ nvc0_grctx_init_scc_0 },
-	{ nvd9_grctx_init_be_0 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvd9_grctx_init_prop_0[] = {
-	{ 0x418400,   1, 0x04, 0x38004e00 },
-	{ 0x418404,   1, 0x04, 0x71e0ffff },
-	{ 0x41840c,   1, 0x04, 0x00001008 },
-	{ 0x418410,   1, 0x04, 0x0fff0fff },
-	{ 0x418414,   1, 0x04, 0x02200fff },
-	{ 0x418450,   6, 0x04, 0x00000000 },
-	{ 0x418468,   1, 0x04, 0x00000001 },
-	{ 0x41846c,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvd9_grctx_init_gpc_unk_1[] = {
-	{ 0x418600,   1, 0x04, 0x0000001f },
-	{ 0x418684,   1, 0x04, 0x0000000f },
-	{ 0x418700,   1, 0x04, 0x00000002 },
-	{ 0x418704,   1, 0x04, 0x00000080 },
-	{ 0x418708,   3, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvd9_grctx_init_setup_0[] = {
-	{ 0x418800,   1, 0x04, 0x7006860a },
-	{ 0x418808,   3, 0x04, 0x00000000 },
-	{ 0x418828,   1, 0x04, 0x00008442 },
-	{ 0x418830,   1, 0x04, 0x10000001 },
-	{ 0x4188d8,   1, 0x04, 0x00000008 },
-	{ 0x4188e0,   1, 0x04, 0x01000000 },
-	{ 0x4188e8,   5, 0x04, 0x00000000 },
-	{ 0x4188fc,   1, 0x04, 0x20100008 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvd9_grctx_init_crstr_0[] = {
-	{ 0x418b00,   1, 0x04, 0x00000006 },
-	{ 0x418b08,   1, 0x04, 0x0a418820 },
-	{ 0x418b0c,   1, 0x04, 0x062080e6 },
-	{ 0x418b10,   1, 0x04, 0x020398a4 },
-	{ 0x418b14,   1, 0x04, 0x0e629062 },
-	{ 0x418b18,   1, 0x04, 0x0a418820 },
-	{ 0x418b1c,   1, 0x04, 0x000000e6 },
-	{ 0x418bb8,   1, 0x04, 0x00000103 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvd9_grctx_pack_gpc[] = {
-	{ nvc0_grctx_init_gpc_unk_0 },
-	{ nvd9_grctx_init_prop_0 },
-	{ nvd9_grctx_init_gpc_unk_1 },
-	{ nvd9_grctx_init_setup_0 },
-	{ nvc0_grctx_init_zcull_0 },
-	{ nvd9_grctx_init_crstr_0 },
-	{ nvc1_grctx_init_gpm_0 },
-	{ nvc0_grctx_init_gcc_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvd9_grctx_init_tex_0[] = {
-	{ 0x419a00,   1, 0x04, 0x000001f0 },
-	{ 0x419a04,   1, 0x04, 0x00000001 },
-	{ 0x419a08,   1, 0x04, 0x00000023 },
-	{ 0x419a0c,   1, 0x04, 0x00020000 },
-	{ 0x419a10,   1, 0x04, 0x00000000 },
-	{ 0x419a14,   1, 0x04, 0x00000200 },
-	{ 0x419a1c,   1, 0x04, 0x00000000 },
-	{ 0x419a20,   1, 0x04, 0x00000800 },
-	{ 0x419ac4,   1, 0x04, 0x0017f440 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvd9_grctx_init_mpc_0[] = {
-	{ 0x419c00,   1, 0x04, 0x0000000a },
-	{ 0x419c04,   1, 0x04, 0x00000006 },
-	{ 0x419c08,   1, 0x04, 0x00000002 },
-	{ 0x419c20,   1, 0x04, 0x00000000 },
-	{ 0x419c24,   1, 0x04, 0x00084210 },
-	{ 0x419c28,   1, 0x04, 0x3cf3cf3c },
-	{}
-};
-
-const struct nvc0_graph_init
-nvd9_grctx_init_sm_0[] = {
-	{ 0x419e04,   3, 0x04, 0x00000000 },
-	{ 0x419e10,   1, 0x04, 0x00000002 },
-	{ 0x419e44,   1, 0x04, 0x001beff2 },
-	{ 0x419e48,   1, 0x04, 0x00000000 },
-	{ 0x419e4c,   1, 0x04, 0x0000000f },
-	{ 0x419e50,  17, 0x04, 0x00000000 },
-	{ 0x419e98,   1, 0x04, 0x00000000 },
-	{ 0x419ee0,   1, 0x04, 0x00010110 },
-	{ 0x419f30,  11, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvd9_grctx_pack_tpc[] = {
-	{ nvc1_grctx_init_pe_0 },
-	{ nvd9_grctx_init_tex_0 },
-	{ nvc1_grctx_init_wwdx_0 },
-	{ nvd9_grctx_init_mpc_0 },
-	{ nvc4_grctx_init_l1c_0 },
-	{ nvc1_grctx_init_tpccs_0 },
-	{ nvd9_grctx_init_sm_0 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH context implementation
- ******************************************************************************/
-
-struct nouveau_oclass *
-nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) {
-	.base.handle = NV_ENGCTX(GR, 0xd9),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-	.main  = nvc0_grctx_generate_main,
-	.unkn  = nvc1_grctx_generate_unkn,
-	.hub   = nvd9_grctx_pack_hub,
-	.gpc   = nvd9_grctx_pack_gpc,
-	.zcull = nvc0_grctx_pack_zcull,
-	.tpc   = nvd9_grctx_pack_tpc,
-	.icmd  = nvd9_grctx_pack_icmd,
-	.mthd  = nvd9_grctx_pack_mthd,
-	.bundle = nvc0_grctx_generate_bundle,
-	.bundle_size = 0x1800,
-	.pagepool = nvc0_grctx_generate_pagepool,
-	.pagepool_size = 0x8000,
-	.attrib = nvc1_grctx_generate_attrib,
-	.attrib_nr_max = 0x324,
-	.attrib_nr = 0x218,
-	.alpha_nr_max = 0x324,
-	.alpha_nr = 0x218,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
deleted file mode 100644
index ccac2ee1a1cb..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
+++ /dev/null
@@ -1,1020 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * PGRAPH context register lists
- ******************************************************************************/
-
-static const struct nvc0_graph_init
-nve4_grctx_init_icmd_0[] = {
-	{ 0x001000,   1, 0x01, 0x00000004 },
-	{ 0x000039,   3, 0x01, 0x00000000 },
-	{ 0x0000a9,   1, 0x01, 0x0000ffff },
-	{ 0x000038,   1, 0x01, 0x0fac6881 },
-	{ 0x00003d,   1, 0x01, 0x00000001 },
-	{ 0x0000e8,   8, 0x01, 0x00000400 },
-	{ 0x000078,   8, 0x01, 0x00000300 },
-	{ 0x000050,   1, 0x01, 0x00000011 },
-	{ 0x000058,   8, 0x01, 0x00000008 },
-	{ 0x000208,   8, 0x01, 0x00000001 },
-	{ 0x000081,   1, 0x01, 0x00000001 },
-	{ 0x000085,   1, 0x01, 0x00000004 },
-	{ 0x000088,   1, 0x01, 0x00000400 },
-	{ 0x000090,   1, 0x01, 0x00000300 },
-	{ 0x000098,   1, 0x01, 0x00001001 },
-	{ 0x0000e3,   1, 0x01, 0x00000001 },
-	{ 0x0000da,   1, 0x01, 0x00000001 },
-	{ 0x0000f8,   1, 0x01, 0x00000003 },
-	{ 0x0000fa,   1, 0x01, 0x00000001 },
-	{ 0x00009f,   4, 0x01, 0x0000ffff },
-	{ 0x0000b1,   1, 0x01, 0x00000001 },
-	{ 0x0000ad,   1, 0x01, 0x0000013e },
-	{ 0x0000e1,   1, 0x01, 0x00000010 },
-	{ 0x000290,  16, 0x01, 0x00000000 },
-	{ 0x0003b0,  16, 0x01, 0x00000000 },
-	{ 0x0002a0,  16, 0x01, 0x00000000 },
-	{ 0x000420,  16, 0x01, 0x00000000 },
-	{ 0x0002b0,  16, 0x01, 0x00000000 },
-	{ 0x000430,  16, 0x01, 0x00000000 },
-	{ 0x0002c0,  16, 0x01, 0x00000000 },
-	{ 0x0004d0,  16, 0x01, 0x00000000 },
-	{ 0x000720,  16, 0x01, 0x00000000 },
-	{ 0x0008c0,  16, 0x01, 0x00000000 },
-	{ 0x000890,  16, 0x01, 0x00000000 },
-	{ 0x0008e0,  16, 0x01, 0x00000000 },
-	{ 0x0008a0,  16, 0x01, 0x00000000 },
-	{ 0x0008f0,  16, 0x01, 0x00000000 },
-	{ 0x00094c,   1, 0x01, 0x000000ff },
-	{ 0x00094d,   1, 0x01, 0xffffffff },
-	{ 0x00094e,   1, 0x01, 0x00000002 },
-	{ 0x0002ec,   1, 0x01, 0x00000001 },
-	{ 0x000303,   1, 0x01, 0x00000001 },
-	{ 0x0002e6,   1, 0x01, 0x00000001 },
-	{ 0x000466,   1, 0x01, 0x00000052 },
-	{ 0x000301,   1, 0x01, 0x3f800000 },
-	{ 0x000304,   1, 0x01, 0x30201000 },
-	{ 0x000305,   1, 0x01, 0x70605040 },
-	{ 0x000306,   1, 0x01, 0xb8a89888 },
-	{ 0x000307,   1, 0x01, 0xf8e8d8c8 },
-	{ 0x00030a,   1, 0x01, 0x00ffff00 },
-	{ 0x00030b,   1, 0x01, 0x0000001a },
-	{ 0x00030c,   1, 0x01, 0x00000001 },
-	{ 0x000318,   1, 0x01, 0x00000001 },
-	{ 0x000340,   1, 0x01, 0x00000000 },
-	{ 0x000375,   1, 0x01, 0x00000001 },
-	{ 0x00037d,   1, 0x01, 0x00000006 },
-	{ 0x0003a0,   1, 0x01, 0x00000002 },
-	{ 0x0003aa,   1, 0x01, 0x00000001 },
-	{ 0x0003a9,   1, 0x01, 0x00000001 },
-	{ 0x000380,   1, 0x01, 0x00000001 },
-	{ 0x000383,   1, 0x01, 0x00000011 },
-	{ 0x000360,   1, 0x01, 0x00000040 },
-	{ 0x000366,   2, 0x01, 0x00000000 },
-	{ 0x000368,   1, 0x01, 0x00000fff },
-	{ 0x000370,   2, 0x01, 0x00000000 },
-	{ 0x000372,   1, 0x01, 0x000fffff },
-	{ 0x00037a,   1, 0x01, 0x00000012 },
-	{ 0x000619,   1, 0x01, 0x00000003 },
-	{ 0x000811,   1, 0x01, 0x00000003 },
-	{ 0x000812,   1, 0x01, 0x00000004 },
-	{ 0x000813,   1, 0x01, 0x00000006 },
-	{ 0x000814,   1, 0x01, 0x00000008 },
-	{ 0x000815,   1, 0x01, 0x0000000b },
-	{ 0x000800,   6, 0x01, 0x00000001 },
-	{ 0x000632,   1, 0x01, 0x00000001 },
-	{ 0x000633,   1, 0x01, 0x00000002 },
-	{ 0x000634,   1, 0x01, 0x00000003 },
-	{ 0x000635,   1, 0x01, 0x00000004 },
-	{ 0x000654,   1, 0x01, 0x3f800000 },
-	{ 0x000657,   1, 0x01, 0x3f800000 },
-	{ 0x000655,   2, 0x01, 0x3f800000 },
-	{ 0x0006cd,   1, 0x01, 0x3f800000 },
-	{ 0x0007f5,   1, 0x01, 0x3f800000 },
-	{ 0x0007dc,   1, 0x01, 0x39291909 },
-	{ 0x0007dd,   1, 0x01, 0x79695949 },
-	{ 0x0007de,   1, 0x01, 0xb9a99989 },
-	{ 0x0007df,   1, 0x01, 0xf9e9d9c9 },
-	{ 0x0007e8,   1, 0x01, 0x00003210 },
-	{ 0x0007e9,   1, 0x01, 0x00007654 },
-	{ 0x0007ea,   1, 0x01, 0x00000098 },
-	{ 0x0007ec,   1, 0x01, 0x39291909 },
-	{ 0x0007ed,   1, 0x01, 0x79695949 },
-	{ 0x0007ee,   1, 0x01, 0xb9a99989 },
-	{ 0x0007ef,   1, 0x01, 0xf9e9d9c9 },
-	{ 0x0007f0,   1, 0x01, 0x00003210 },
-	{ 0x0007f1,   1, 0x01, 0x00007654 },
-	{ 0x0007f2,   1, 0x01, 0x00000098 },
-	{ 0x0005a5,   1, 0x01, 0x00000001 },
-	{ 0x000980, 128, 0x01, 0x00000000 },
-	{ 0x000468,   1, 0x01, 0x00000004 },
-	{ 0x00046c,   1, 0x01, 0x00000001 },
-	{ 0x000470,  96, 0x01, 0x00000000 },
-	{ 0x000510,  16, 0x01, 0x3f800000 },
-	{ 0x000520,   1, 0x01, 0x000002b6 },
-	{ 0x000529,   1, 0x01, 0x00000001 },
-	{ 0x000530,  16, 0x01, 0xffff0000 },
-	{ 0x000585,   1, 0x01, 0x0000003f },
-	{ 0x000576,   1, 0x01, 0x00000003 },
-	{ 0x00057b,   1, 0x01, 0x00000059 },
-	{ 0x000586,   1, 0x01, 0x00000040 },
-	{ 0x000582,   2, 0x01, 0x00000080 },
-	{ 0x0005c2,   1, 0x01, 0x00000001 },
-	{ 0x000638,   2, 0x01, 0x00000001 },
-	{ 0x00063a,   1, 0x01, 0x00000002 },
-	{ 0x00063b,   2, 0x01, 0x00000001 },
-	{ 0x00063d,   1, 0x01, 0x00000002 },
-	{ 0x00063e,   1, 0x01, 0x00000001 },
-	{ 0x0008b8,   8, 0x01, 0x00000001 },
-	{ 0x000900,   8, 0x01, 0x00000001 },
-	{ 0x000908,   8, 0x01, 0x00000002 },
-	{ 0x000910,  16, 0x01, 0x00000001 },
-	{ 0x000920,   8, 0x01, 0x00000002 },
-	{ 0x000928,   8, 0x01, 0x00000001 },
-	{ 0x000648,   9, 0x01, 0x00000001 },
-	{ 0x000658,   1, 0x01, 0x0000000f },
-	{ 0x0007ff,   1, 0x01, 0x0000000a },
-	{ 0x00066a,   1, 0x01, 0x40000000 },
-	{ 0x00066b,   1, 0x01, 0x10000000 },
-	{ 0x00066c,   2, 0x01, 0xffff0000 },
-	{ 0x0007af,   2, 0x01, 0x00000008 },
-	{ 0x0007f6,   1, 0x01, 0x00000001 },
-	{ 0x0006b2,   1, 0x01, 0x00000055 },
-	{ 0x0007ad,   1, 0x01, 0x00000003 },
-	{ 0x000937,   1, 0x01, 0x00000001 },
-	{ 0x000971,   1, 0x01, 0x00000008 },
-	{ 0x000972,   1, 0x01, 0x00000040 },
-	{ 0x000973,   1, 0x01, 0x0000012c },
-	{ 0x00097c,   1, 0x01, 0x00000040 },
-	{ 0x000979,   1, 0x01, 0x00000003 },
-	{ 0x000975,   1, 0x01, 0x00000020 },
-	{ 0x000976,   1, 0x01, 0x00000001 },
-	{ 0x000977,   1, 0x01, 0x00000020 },
-	{ 0x000978,   1, 0x01, 0x00000001 },
-	{ 0x000957,   1, 0x01, 0x00000003 },
-	{ 0x00095e,   1, 0x01, 0x20164010 },
-	{ 0x00095f,   1, 0x01, 0x00000020 },
-	{ 0x00097d,   1, 0x01, 0x00000020 },
-	{ 0x000683,   1, 0x01, 0x00000006 },
-	{ 0x000685,   1, 0x01, 0x003fffff },
-	{ 0x000687,   1, 0x01, 0x003fffff },
-	{ 0x0006a0,   1, 0x01, 0x00000005 },
-	{ 0x000840,   1, 0x01, 0x00400008 },
-	{ 0x000841,   1, 0x01, 0x08000080 },
-	{ 0x000842,   1, 0x01, 0x00400008 },
-	{ 0x000843,   1, 0x01, 0x08000080 },
-	{ 0x0006aa,   1, 0x01, 0x00000001 },
-	{ 0x0006ab,   1, 0x01, 0x00000002 },
-	{ 0x0006ac,   1, 0x01, 0x00000080 },
-	{ 0x0006ad,   2, 0x01, 0x00000100 },
-	{ 0x0006b1,   1, 0x01, 0x00000011 },
-	{ 0x0006bb,   1, 0x01, 0x000000cf },
-	{ 0x0006ce,   1, 0x01, 0x2a712488 },
-	{ 0x000739,   1, 0x01, 0x4085c000 },
-	{ 0x00073a,   1, 0x01, 0x00000080 },
-	{ 0x000786,   1, 0x01, 0x80000100 },
-	{ 0x00073c,   1, 0x01, 0x00010100 },
-	{ 0x00073d,   1, 0x01, 0x02800000 },
-	{ 0x000787,   1, 0x01, 0x000000cf },
-	{ 0x00078c,   1, 0x01, 0x00000008 },
-	{ 0x000792,   1, 0x01, 0x00000001 },
-	{ 0x000794,   3, 0x01, 0x00000001 },
-	{ 0x000797,   1, 0x01, 0x000000cf },
-	{ 0x000836,   1, 0x01, 0x00000001 },
-	{ 0x00079a,   1, 0x01, 0x00000002 },
-	{ 0x000833,   1, 0x01, 0x04444480 },
-	{ 0x0007a1,   1, 0x01, 0x00000001 },
-	{ 0x0007a3,   3, 0x01, 0x00000001 },
-	{ 0x000831,   1, 0x01, 0x00000004 },
-	{ 0x000b07,   1, 0x01, 0x00000002 },
-	{ 0x000b08,   2, 0x01, 0x00000100 },
-	{ 0x000b0a,   1, 0x01, 0x00000001 },
-	{ 0x000a04,   1, 0x01, 0x000000ff },
-	{ 0x000a0b,   1, 0x01, 0x00000040 },
-	{ 0x00097f,   1, 0x01, 0x00000100 },
-	{ 0x000a02,   1, 0x01, 0x00000001 },
-	{ 0x000809,   1, 0x01, 0x00000007 },
-	{ 0x00c221,   1, 0x01, 0x00000040 },
-	{ 0x00c1b0,   8, 0x01, 0x0000000f },
-	{ 0x00c1b8,   1, 0x01, 0x0fac6881 },
-	{ 0x00c1b9,   1, 0x01, 0x00fac688 },
-	{ 0x00c401,   1, 0x01, 0x00000001 },
-	{ 0x00c402,   1, 0x01, 0x00010001 },
-	{ 0x00c403,   2, 0x01, 0x00000001 },
-	{ 0x00c40e,   1, 0x01, 0x00000020 },
-	{ 0x00c500,   1, 0x01, 0x00000003 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000002 },
-	{ 0x0006aa,   1, 0x01, 0x00000001 },
-	{ 0x0006ad,   2, 0x01, 0x00000100 },
-	{ 0x0006b1,   1, 0x01, 0x00000011 },
-	{ 0x00078c,   1, 0x01, 0x00000008 },
-	{ 0x000792,   1, 0x01, 0x00000001 },
-	{ 0x000794,   3, 0x01, 0x00000001 },
-	{ 0x000797,   1, 0x01, 0x000000cf },
-	{ 0x00079a,   1, 0x01, 0x00000002 },
-	{ 0x000833,   1, 0x01, 0x04444480 },
-	{ 0x0007a1,   1, 0x01, 0x00000001 },
-	{ 0x0007a3,   3, 0x01, 0x00000001 },
-	{ 0x000831,   1, 0x01, 0x00000004 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000008 },
-	{ 0x000039,   3, 0x01, 0x00000000 },
-	{ 0x000380,   1, 0x01, 0x00000001 },
-	{ 0x000366,   2, 0x01, 0x00000000 },
-	{ 0x000368,   1, 0x01, 0x00000fff },
-	{ 0x000370,   2, 0x01, 0x00000000 },
-	{ 0x000372,   1, 0x01, 0x000fffff },
-	{ 0x000813,   1, 0x01, 0x00000006 },
-	{ 0x000814,   1, 0x01, 0x00000008 },
-	{ 0x000957,   1, 0x01, 0x00000003 },
-	{ 0x000b07,   1, 0x01, 0x00000002 },
-	{ 0x000b08,   2, 0x01, 0x00000100 },
-	{ 0x000b0a,   1, 0x01, 0x00000001 },
-	{ 0x000a04,   1, 0x01, 0x000000ff },
-	{ 0x00097f,   1, 0x01, 0x00000100 },
-	{ 0x000a02,   1, 0x01, 0x00000001 },
-	{ 0x000809,   1, 0x01, 0x00000007 },
-	{ 0x00c221,   1, 0x01, 0x00000040 },
-	{ 0x00c401,   1, 0x01, 0x00000001 },
-	{ 0x00c402,   1, 0x01, 0x00010001 },
-	{ 0x00c403,   2, 0x01, 0x00000001 },
-	{ 0x00c40e,   1, 0x01, 0x00000020 },
-	{ 0x00c500,   1, 0x01, 0x00000003 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000001 },
-	{ 0x000b07,   1, 0x01, 0x00000002 },
-	{ 0x000b08,   2, 0x01, 0x00000100 },
-	{ 0x000b0a,   1, 0x01, 0x00000001 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{}
-};
-
-const struct nvc0_graph_pack
-nve4_grctx_pack_icmd[] = {
-	{ nve4_grctx_init_icmd_0 },
-	{}
-};
-
-const struct nvc0_graph_init
-nve4_grctx_init_a097_0[] = {
-	{ 0x000800,   8, 0x40, 0x00000000 },
-	{ 0x000804,   8, 0x40, 0x00000000 },
-	{ 0x000808,   8, 0x40, 0x00000400 },
-	{ 0x00080c,   8, 0x40, 0x00000300 },
-	{ 0x000810,   1, 0x04, 0x000000cf },
-	{ 0x000850,   7, 0x40, 0x00000000 },
-	{ 0x000814,   8, 0x40, 0x00000040 },
-	{ 0x000818,   8, 0x40, 0x00000001 },
-	{ 0x00081c,   8, 0x40, 0x00000000 },
-	{ 0x000820,   8, 0x40, 0x00000000 },
-	{ 0x001c00,  16, 0x10, 0x00000000 },
-	{ 0x001c04,  16, 0x10, 0x00000000 },
-	{ 0x001c08,  16, 0x10, 0x00000000 },
-	{ 0x001c0c,  16, 0x10, 0x00000000 },
-	{ 0x001d00,  16, 0x10, 0x00000000 },
-	{ 0x001d04,  16, 0x10, 0x00000000 },
-	{ 0x001d08,  16, 0x10, 0x00000000 },
-	{ 0x001d0c,  16, 0x10, 0x00000000 },
-	{ 0x001f00,  16, 0x08, 0x00000000 },
-	{ 0x001f04,  16, 0x08, 0x00000000 },
-	{ 0x001f80,  16, 0x08, 0x00000000 },
-	{ 0x001f84,  16, 0x08, 0x00000000 },
-	{ 0x002000,   1, 0x04, 0x00000000 },
-	{ 0x002040,   1, 0x04, 0x00000011 },
-	{ 0x002080,   1, 0x04, 0x00000020 },
-	{ 0x0020c0,   1, 0x04, 0x00000030 },
-	{ 0x002100,   1, 0x04, 0x00000040 },
-	{ 0x002140,   1, 0x04, 0x00000051 },
-	{ 0x00200c,   6, 0x40, 0x00000001 },
-	{ 0x002010,   1, 0x04, 0x00000000 },
-	{ 0x002050,   1, 0x04, 0x00000000 },
-	{ 0x002090,   1, 0x04, 0x00000001 },
-	{ 0x0020d0,   1, 0x04, 0x00000002 },
-	{ 0x002110,   1, 0x04, 0x00000003 },
-	{ 0x002150,   1, 0x04, 0x00000004 },
-	{ 0x000380,   4, 0x20, 0x00000000 },
-	{ 0x000384,   4, 0x20, 0x00000000 },
-	{ 0x000388,   4, 0x20, 0x00000000 },
-	{ 0x00038c,   4, 0x20, 0x00000000 },
-	{ 0x000700,   4, 0x10, 0x00000000 },
-	{ 0x000704,   4, 0x10, 0x00000000 },
-	{ 0x000708,   4, 0x10, 0x00000000 },
-	{ 0x002800, 128, 0x04, 0x00000000 },
-	{ 0x000a00,  16, 0x20, 0x00000000 },
-	{ 0x000a04,  16, 0x20, 0x00000000 },
-	{ 0x000a08,  16, 0x20, 0x00000000 },
-	{ 0x000a0c,  16, 0x20, 0x00000000 },
-	{ 0x000a10,  16, 0x20, 0x00000000 },
-	{ 0x000a14,  16, 0x20, 0x00000000 },
-	{ 0x000c00,  16, 0x10, 0x00000000 },
-	{ 0x000c04,  16, 0x10, 0x00000000 },
-	{ 0x000c08,  16, 0x10, 0x00000000 },
-	{ 0x000c0c,  16, 0x10, 0x3f800000 },
-	{ 0x000d00,   8, 0x08, 0xffff0000 },
-	{ 0x000d04,   8, 0x08, 0xffff0000 },
-	{ 0x000e00,  16, 0x10, 0x00000000 },
-	{ 0x000e04,  16, 0x10, 0xffff0000 },
-	{ 0x000e08,  16, 0x10, 0xffff0000 },
-	{ 0x000d40,   4, 0x08, 0x00000000 },
-	{ 0x000d44,   4, 0x08, 0x00000000 },
-	{ 0x001e00,   8, 0x20, 0x00000001 },
-	{ 0x001e04,   8, 0x20, 0x00000001 },
-	{ 0x001e08,   8, 0x20, 0x00000002 },
-	{ 0x001e0c,   8, 0x20, 0x00000001 },
-	{ 0x001e10,   8, 0x20, 0x00000001 },
-	{ 0x001e14,   8, 0x20, 0x00000002 },
-	{ 0x001e18,   8, 0x20, 0x00000001 },
-	{ 0x003400, 128, 0x04, 0x00000000 },
-	{ 0x00030c,   1, 0x04, 0x00000001 },
-	{ 0x001944,   1, 0x04, 0x00000000 },
-	{ 0x001514,   1, 0x04, 0x00000000 },
-	{ 0x000d68,   1, 0x04, 0x0000ffff },
-	{ 0x00121c,   1, 0x04, 0x0fac6881 },
-	{ 0x000fac,   1, 0x04, 0x00000001 },
-	{ 0x001538,   1, 0x04, 0x00000001 },
-	{ 0x000fe0,   2, 0x04, 0x00000000 },
-	{ 0x000fe8,   1, 0x04, 0x00000014 },
-	{ 0x000fec,   1, 0x04, 0x00000040 },
-	{ 0x000ff0,   1, 0x04, 0x00000000 },
-	{ 0x00179c,   1, 0x04, 0x00000000 },
-	{ 0x001228,   1, 0x04, 0x00000400 },
-	{ 0x00122c,   1, 0x04, 0x00000300 },
-	{ 0x001230,   1, 0x04, 0x00010001 },
-	{ 0x0007f8,   1, 0x04, 0x00000000 },
-	{ 0x0015b4,   1, 0x04, 0x00000001 },
-	{ 0x0015cc,   1, 0x04, 0x00000000 },
-	{ 0x001534,   1, 0x04, 0x00000000 },
-	{ 0x000fb0,   1, 0x04, 0x00000000 },
-	{ 0x0015d0,   1, 0x04, 0x00000000 },
-	{ 0x00153c,   1, 0x04, 0x00000000 },
-	{ 0x0016b4,   1, 0x04, 0x00000003 },
-	{ 0x000fbc,   4, 0x04, 0x0000ffff },
-	{ 0x000df8,   2, 0x04, 0x00000000 },
-	{ 0x001948,   1, 0x04, 0x00000000 },
-	{ 0x001970,   1, 0x04, 0x00000001 },
-	{ 0x00161c,   1, 0x04, 0x000009f0 },
-	{ 0x000dcc,   1, 0x04, 0x00000010 },
-	{ 0x00163c,   1, 0x04, 0x00000000 },
-	{ 0x0015e4,   1, 0x04, 0x00000000 },
-	{ 0x001160,  32, 0x04, 0x25e00040 },
-	{ 0x001880,  32, 0x04, 0x00000000 },
-	{ 0x000f84,   2, 0x04, 0x00000000 },
-	{ 0x0017c8,   2, 0x04, 0x00000000 },
-	{ 0x0017d0,   1, 0x04, 0x000000ff },
-	{ 0x0017d4,   1, 0x04, 0xffffffff },
-	{ 0x0017d8,   1, 0x04, 0x00000002 },
-	{ 0x0017dc,   1, 0x04, 0x00000000 },
-	{ 0x0015f4,   2, 0x04, 0x00000000 },
-	{ 0x001434,   2, 0x04, 0x00000000 },
-	{ 0x000d74,   1, 0x04, 0x00000000 },
-	{ 0x000dec,   1, 0x04, 0x00000001 },
-	{ 0x0013a4,   1, 0x04, 0x00000000 },
-	{ 0x001318,   1, 0x04, 0x00000001 },
-	{ 0x001644,   1, 0x04, 0x00000000 },
-	{ 0x000748,   1, 0x04, 0x00000000 },
-	{ 0x000de8,   1, 0x04, 0x00000000 },
-	{ 0x001648,   1, 0x04, 0x00000000 },
-	{ 0x0012a4,   1, 0x04, 0x00000000 },
-	{ 0x001120,   4, 0x04, 0x00000000 },
-	{ 0x001118,   1, 0x04, 0x00000000 },
-	{ 0x00164c,   1, 0x04, 0x00000000 },
-	{ 0x001658,   1, 0x04, 0x00000000 },
-	{ 0x001910,   1, 0x04, 0x00000290 },
-	{ 0x001518,   1, 0x04, 0x00000000 },
-	{ 0x00165c,   1, 0x04, 0x00000001 },
-	{ 0x001520,   1, 0x04, 0x00000000 },
-	{ 0x001604,   1, 0x04, 0x00000000 },
-	{ 0x001570,   1, 0x04, 0x00000000 },
-	{ 0x0013b0,   2, 0x04, 0x3f800000 },
-	{ 0x00020c,   1, 0x04, 0x00000000 },
-	{ 0x001670,   1, 0x04, 0x30201000 },
-	{ 0x001674,   1, 0x04, 0x70605040 },
-	{ 0x001678,   1, 0x04, 0xb8a89888 },
-	{ 0x00167c,   1, 0x04, 0xf8e8d8c8 },
-	{ 0x00166c,   1, 0x04, 0x00000000 },
-	{ 0x001680,   1, 0x04, 0x00ffff00 },
-	{ 0x0012d0,   1, 0x04, 0x00000003 },
-	{ 0x0012d4,   1, 0x04, 0x00000002 },
-	{ 0x001684,   2, 0x04, 0x00000000 },
-	{ 0x000dac,   2, 0x04, 0x00001b02 },
-	{ 0x000db4,   1, 0x04, 0x00000000 },
-	{ 0x00168c,   1, 0x04, 0x00000000 },
-	{ 0x0015bc,   1, 0x04, 0x00000000 },
-	{ 0x00156c,   1, 0x04, 0x00000000 },
-	{ 0x00187c,   1, 0x04, 0x00000000 },
-	{ 0x001110,   1, 0x04, 0x00000001 },
-	{ 0x000dc0,   3, 0x04, 0x00000000 },
-	{ 0x001234,   1, 0x04, 0x00000000 },
-	{ 0x001690,   1, 0x04, 0x00000000 },
-	{ 0x0012ac,   1, 0x04, 0x00000001 },
-	{ 0x000790,   5, 0x04, 0x00000000 },
-	{ 0x00077c,   1, 0x04, 0x00000000 },
-	{ 0x001000,   1, 0x04, 0x00000010 },
-	{ 0x0010fc,   1, 0x04, 0x00000000 },
-	{ 0x001290,   1, 0x04, 0x00000000 },
-	{ 0x000218,   1, 0x04, 0x00000010 },
-	{ 0x0012d8,   1, 0x04, 0x00000000 },
-	{ 0x0012dc,   1, 0x04, 0x00000010 },
-	{ 0x000d94,   1, 0x04, 0x00000001 },
-	{ 0x00155c,   2, 0x04, 0x00000000 },
-	{ 0x001564,   1, 0x04, 0x00000fff },
-	{ 0x001574,   2, 0x04, 0x00000000 },
-	{ 0x00157c,   1, 0x04, 0x000fffff },
-	{ 0x001354,   1, 0x04, 0x00000000 },
-	{ 0x001610,   1, 0x04, 0x00000012 },
-	{ 0x001608,   2, 0x04, 0x00000000 },
-	{ 0x00260c,   1, 0x04, 0x00000000 },
-	{ 0x0007ac,   1, 0x04, 0x00000000 },
-	{ 0x00162c,   1, 0x04, 0x00000003 },
-	{ 0x000210,   1, 0x04, 0x00000000 },
-	{ 0x000320,   1, 0x04, 0x00000000 },
-	{ 0x000324,   6, 0x04, 0x3f800000 },
-	{ 0x000750,   1, 0x04, 0x00000000 },
-	{ 0x000760,   1, 0x04, 0x39291909 },
-	{ 0x000764,   1, 0x04, 0x79695949 },
-	{ 0x000768,   1, 0x04, 0xb9a99989 },
-	{ 0x00076c,   1, 0x04, 0xf9e9d9c9 },
-	{ 0x000770,   1, 0x04, 0x30201000 },
-	{ 0x000774,   1, 0x04, 0x70605040 },
-	{ 0x000778,   1, 0x04, 0x00009080 },
-	{ 0x000780,   1, 0x04, 0x39291909 },
-	{ 0x000784,   1, 0x04, 0x79695949 },
-	{ 0x000788,   1, 0x04, 0xb9a99989 },
-	{ 0x00078c,   1, 0x04, 0xf9e9d9c9 },
-	{ 0x0007d0,   1, 0x04, 0x30201000 },
-	{ 0x0007d4,   1, 0x04, 0x70605040 },
-	{ 0x0007d8,   1, 0x04, 0x00009080 },
-	{ 0x00037c,   1, 0x04, 0x00000001 },
-	{ 0x000740,   2, 0x04, 0x00000000 },
-	{ 0x002600,   1, 0x04, 0x00000000 },
-	{ 0x001918,   1, 0x04, 0x00000000 },
-	{ 0x00191c,   1, 0x04, 0x00000900 },
-	{ 0x001920,   1, 0x04, 0x00000405 },
-	{ 0x001308,   1, 0x04, 0x00000001 },
-	{ 0x001924,   1, 0x04, 0x00000000 },
-	{ 0x0013ac,   1, 0x04, 0x00000000 },
-	{ 0x00192c,   1, 0x04, 0x00000001 },
-	{ 0x00193c,   1, 0x04, 0x00002c1c },
-	{ 0x000d7c,   1, 0x04, 0x00000000 },
-	{ 0x000f8c,   1, 0x04, 0x00000000 },
-	{ 0x0002c0,   1, 0x04, 0x00000001 },
-	{ 0x001510,   1, 0x04, 0x00000000 },
-	{ 0x001940,   1, 0x04, 0x00000000 },
-	{ 0x000ff4,   2, 0x04, 0x00000000 },
-	{ 0x00194c,   2, 0x04, 0x00000000 },
-	{ 0x001968,   1, 0x04, 0x00000000 },
-	{ 0x001590,   1, 0x04, 0x0000003f },
-	{ 0x0007e8,   4, 0x04, 0x00000000 },
-	{ 0x00196c,   1, 0x04, 0x00000011 },
-	{ 0x0002e4,   1, 0x04, 0x0000b001 },
-	{ 0x00036c,   2, 0x04, 0x00000000 },
-	{ 0x00197c,   1, 0x04, 0x00000000 },
-	{ 0x000fcc,   2, 0x04, 0x00000000 },
-	{ 0x0002d8,   1, 0x04, 0x00000040 },
-	{ 0x001980,   1, 0x04, 0x00000080 },
-	{ 0x001504,   1, 0x04, 0x00000080 },
-	{ 0x001984,   1, 0x04, 0x00000000 },
-	{ 0x000300,   1, 0x04, 0x00000001 },
-	{ 0x0013a8,   1, 0x04, 0x00000000 },
-	{ 0x0012ec,   1, 0x04, 0x00000000 },
-	{ 0x001310,   1, 0x04, 0x00000000 },
-	{ 0x001314,   1, 0x04, 0x00000001 },
-	{ 0x001380,   1, 0x04, 0x00000000 },
-	{ 0x001384,   4, 0x04, 0x00000001 },
-	{ 0x001394,   1, 0x04, 0x00000000 },
-	{ 0x00139c,   1, 0x04, 0x00000000 },
-	{ 0x001398,   1, 0x04, 0x00000000 },
-	{ 0x001594,   1, 0x04, 0x00000000 },
-	{ 0x001598,   4, 0x04, 0x00000001 },
-	{ 0x000f54,   3, 0x04, 0x00000000 },
-	{ 0x0019bc,   1, 0x04, 0x00000000 },
-	{ 0x000f9c,   2, 0x04, 0x00000000 },
-	{ 0x0012cc,   1, 0x04, 0x00000000 },
-	{ 0x0012e8,   1, 0x04, 0x00000000 },
-	{ 0x00130c,   1, 0x04, 0x00000001 },
-	{ 0x001360,   8, 0x04, 0x00000000 },
-	{ 0x00133c,   2, 0x04, 0x00000001 },
-	{ 0x001344,   1, 0x04, 0x00000002 },
-	{ 0x001348,   2, 0x04, 0x00000001 },
-	{ 0x001350,   1, 0x04, 0x00000002 },
-	{ 0x001358,   1, 0x04, 0x00000001 },
-	{ 0x0012e4,   1, 0x04, 0x00000000 },
-	{ 0x00131c,   4, 0x04, 0x00000000 },
-	{ 0x0019c0,   1, 0x04, 0x00000000 },
-	{ 0x001140,   1, 0x04, 0x00000000 },
-	{ 0x0019c4,   1, 0x04, 0x00000000 },
-	{ 0x0019c8,   1, 0x04, 0x00001500 },
-	{ 0x00135c,   1, 0x04, 0x00000000 },
-	{ 0x000f90,   1, 0x04, 0x00000000 },
-	{ 0x0019e0,   8, 0x04, 0x00000001 },
-	{ 0x0019cc,   1, 0x04, 0x00000001 },
-	{ 0x0015b8,   1, 0x04, 0x00000000 },
-	{ 0x001a00,   1, 0x04, 0x00001111 },
-	{ 0x001a04,   7, 0x04, 0x00000000 },
-	{ 0x000d6c,   2, 0x04, 0xffff0000 },
-	{ 0x0010f8,   1, 0x04, 0x00001010 },
-	{ 0x000d80,   5, 0x04, 0x00000000 },
-	{ 0x000da0,   1, 0x04, 0x00000000 },
-	{ 0x0007a4,   2, 0x04, 0x00000000 },
-	{ 0x001508,   1, 0x04, 0x80000000 },
-	{ 0x00150c,   1, 0x04, 0x40000000 },
-	{ 0x001668,   1, 0x04, 0x00000000 },
-	{ 0x000318,   2, 0x04, 0x00000008 },
-	{ 0x000d9c,   1, 0x04, 0x00000001 },
-	{ 0x000374,   1, 0x04, 0x00000000 },
-	{ 0x000378,   1, 0x04, 0x00000020 },
-	{ 0x0007dc,   1, 0x04, 0x00000000 },
-	{ 0x00074c,   1, 0x04, 0x00000055 },
-	{ 0x001420,   1, 0x04, 0x00000003 },
-	{ 0x0017bc,   2, 0x04, 0x00000000 },
-	{ 0x0017c4,   1, 0x04, 0x00000001 },
-	{ 0x001008,   1, 0x04, 0x00000008 },
-	{ 0x00100c,   1, 0x04, 0x00000040 },
-	{ 0x001010,   1, 0x04, 0x0000012c },
-	{ 0x000d60,   1, 0x04, 0x00000040 },
-	{ 0x00075c,   1, 0x04, 0x00000003 },
-	{ 0x001018,   1, 0x04, 0x00000020 },
-	{ 0x00101c,   1, 0x04, 0x00000001 },
-	{ 0x001020,   1, 0x04, 0x00000020 },
-	{ 0x001024,   1, 0x04, 0x00000001 },
-	{ 0x001444,   3, 0x04, 0x00000000 },
-	{ 0x000360,   1, 0x04, 0x20164010 },
-	{ 0x000364,   1, 0x04, 0x00000020 },
-	{ 0x000368,   1, 0x04, 0x00000000 },
-	{ 0x000de4,   1, 0x04, 0x00000000 },
-	{ 0x000204,   1, 0x04, 0x00000006 },
-	{ 0x000208,   1, 0x04, 0x00000000 },
-	{ 0x0002cc,   2, 0x04, 0x003fffff },
-	{ 0x001220,   1, 0x04, 0x00000005 },
-	{ 0x000fdc,   1, 0x04, 0x00000000 },
-	{ 0x000f98,   1, 0x04, 0x00400008 },
-	{ 0x001284,   1, 0x04, 0x08000080 },
-	{ 0x001450,   1, 0x04, 0x00400008 },
-	{ 0x001454,   1, 0x04, 0x08000080 },
-	{ 0x000214,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nve4_grctx_pack_mthd[] = {
-	{ nve4_grctx_init_a097_0, 0xa097 },
-	{ nvc0_grctx_init_902d_0, 0x902d },
-	{}
-};
-
-static const struct nvc0_graph_init
-nve4_grctx_init_fe_0[] = {
-	{ 0x404010,   5, 0x04, 0x00000000 },
-	{ 0x404024,   1, 0x04, 0x0000e000 },
-	{ 0x404028,   1, 0x04, 0x00000000 },
-	{ 0x4040a8,   8, 0x04, 0x00000000 },
-	{ 0x4040c8,   1, 0x04, 0xf800008f },
-	{ 0x4040d0,   6, 0x04, 0x00000000 },
-	{ 0x4040e8,   1, 0x04, 0x00001000 },
-	{ 0x4040f8,   1, 0x04, 0x00000000 },
-	{ 0x404130,   2, 0x04, 0x00000000 },
-	{ 0x404138,   1, 0x04, 0x20000040 },
-	{ 0x404150,   1, 0x04, 0x0000002e },
-	{ 0x404154,   1, 0x04, 0x00000400 },
-	{ 0x404158,   1, 0x04, 0x00000200 },
-	{ 0x404164,   1, 0x04, 0x00000055 },
-	{ 0x4041a0,   4, 0x04, 0x00000000 },
-	{ 0x404200,   4, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nve4_grctx_init_memfmt_0[] = {
-	{ 0x404604,   1, 0x04, 0x00000014 },
-	{ 0x404608,   1, 0x04, 0x00000000 },
-	{ 0x40460c,   1, 0x04, 0x00003fff },
-	{ 0x404610,   1, 0x04, 0x00000100 },
-	{ 0x404618,   4, 0x04, 0x00000000 },
-	{ 0x40462c,   2, 0x04, 0x00000000 },
-	{ 0x404640,   1, 0x04, 0x00000000 },
-	{ 0x404654,   1, 0x04, 0x00000000 },
-	{ 0x404660,   1, 0x04, 0x00000000 },
-	{ 0x404678,   1, 0x04, 0x00000000 },
-	{ 0x40467c,   1, 0x04, 0x00000002 },
-	{ 0x404680,   8, 0x04, 0x00000000 },
-	{ 0x4046a0,   1, 0x04, 0x007f0080 },
-	{ 0x4046a4,   8, 0x04, 0x00000000 },
-	{ 0x4046c8,   3, 0x04, 0x00000000 },
-	{ 0x404700,   3, 0x04, 0x00000000 },
-	{ 0x404718,   7, 0x04, 0x00000000 },
-	{ 0x404734,   1, 0x04, 0x00000100 },
-	{ 0x404738,   2, 0x04, 0x00000000 },
-	{ 0x404744,   2, 0x04, 0x00000000 },
-	{ 0x404754,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nve4_grctx_init_ds_0[] = {
-	{ 0x405800,   1, 0x04, 0x0f8000bf },
-	{ 0x405830,   1, 0x04, 0x02180648 },
-	{ 0x405834,   1, 0x04, 0x08000000 },
-	{ 0x405838,   1, 0x04, 0x00000000 },
-	{ 0x405854,   1, 0x04, 0x00000000 },
-	{ 0x405870,   4, 0x04, 0x00000001 },
-	{ 0x405a00,   2, 0x04, 0x00000000 },
-	{ 0x405a18,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nve4_grctx_init_cwd_0[] = {
-	{ 0x405b00,   1, 0x04, 0x00000000 },
-	{ 0x405b10,   1, 0x04, 0x00001000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nve4_grctx_init_pd_0[] = {
-	{ 0x406020,   1, 0x04, 0x004103c1 },
-	{ 0x406028,   4, 0x04, 0x00000001 },
-	{ 0x4064a8,   1, 0x04, 0x00000000 },
-	{ 0x4064ac,   1, 0x04, 0x00003fff },
-	{ 0x4064b4,   2, 0x04, 0x00000000 },
-	{ 0x4064c0,   1, 0x04, 0x801a00f0 },
-	{ 0x4064c4,   1, 0x04, 0x0192ffff },
-	{ 0x4064c8,   1, 0x04, 0x01800600 },
-	{ 0x4064cc,   9, 0x04, 0x00000000 },
-	{ 0x4064fc,   1, 0x04, 0x0000022a },
-	{}
-};
-
-static const struct nvc0_graph_init
-nve4_grctx_init_sked_0[] = {
-	{ 0x407040,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nve4_grctx_init_scc_0[] = {
-	{ 0x408000,   2, 0x04, 0x00000000 },
-	{ 0x408008,   1, 0x04, 0x00000030 },
-	{ 0x40800c,   2, 0x04, 0x00000000 },
-	{ 0x408014,   1, 0x04, 0x00000069 },
-	{ 0x408018,   1, 0x04, 0xe100e100 },
-	{ 0x408064,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nve4_grctx_init_be_0[] = {
-	{ 0x408800,   1, 0x04, 0x02802a3c },
-	{ 0x408804,   1, 0x04, 0x00000040 },
-	{ 0x408808,   1, 0x04, 0x1043e005 },
-	{ 0x408840,   1, 0x04, 0x0000000b },
-	{ 0x408900,   1, 0x04, 0x3080b801 },
-	{ 0x408904,   1, 0x04, 0x62000001 },
-	{ 0x408908,   1, 0x04, 0x00c8102f },
-	{ 0x408980,   1, 0x04, 0x0000011d },
-	{}
-};
-
-const struct nvc0_graph_pack
-nve4_grctx_pack_hub[] = {
-	{ nvc0_grctx_init_main_0 },
-	{ nve4_grctx_init_fe_0 },
-	{ nvc0_grctx_init_pri_0 },
-	{ nve4_grctx_init_memfmt_0 },
-	{ nve4_grctx_init_ds_0 },
-	{ nve4_grctx_init_cwd_0 },
-	{ nve4_grctx_init_pd_0 },
-	{ nve4_grctx_init_sked_0 },
-	{ nvc0_grctx_init_rstr2d_0 },
-	{ nve4_grctx_init_scc_0 },
-	{ nve4_grctx_init_be_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nve4_grctx_init_setup_0[] = {
-	{ 0x418800,   1, 0x04, 0x7006860a },
-	{ 0x418808,   3, 0x04, 0x00000000 },
-	{ 0x418828,   1, 0x04, 0x00000044 },
-	{ 0x418830,   1, 0x04, 0x10000001 },
-	{ 0x4188d8,   1, 0x04, 0x00000008 },
-	{ 0x4188e0,   1, 0x04, 0x01000000 },
-	{ 0x4188e8,   5, 0x04, 0x00000000 },
-	{ 0x4188fc,   1, 0x04, 0x20100018 },
-	{}
-};
-
-const struct nvc0_graph_init
-nve4_grctx_init_gpm_0[] = {
-	{ 0x418c08,   1, 0x04, 0x00000001 },
-	{ 0x418c10,   8, 0x04, 0x00000000 },
-	{ 0x418c40,   1, 0x04, 0xffffffff },
-	{ 0x418c6c,   1, 0x04, 0x00000001 },
-	{ 0x418c80,   1, 0x04, 0x20200004 },
-	{ 0x418c8c,   1, 0x04, 0x00000001 },
-	{}
-};
-
-const struct nvc0_graph_pack
-nve4_grctx_pack_gpc[] = {
-	{ nvc0_grctx_init_gpc_unk_0 },
-	{ nvd9_grctx_init_prop_0 },
-	{ nvd9_grctx_init_gpc_unk_1 },
-	{ nve4_grctx_init_setup_0 },
-	{ nvc0_grctx_init_zcull_0 },
-	{ nvd9_grctx_init_crstr_0 },
-	{ nve4_grctx_init_gpm_0 },
-	{ nvc0_grctx_init_gcc_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nve4_grctx_init_tex_0[] = {
-	{ 0x419a00,   1, 0x04, 0x000000f0 },
-	{ 0x419a04,   1, 0x04, 0x00000001 },
-	{ 0x419a08,   1, 0x04, 0x00000021 },
-	{ 0x419a0c,   1, 0x04, 0x00020000 },
-	{ 0x419a10,   1, 0x04, 0x00000000 },
-	{ 0x419a14,   1, 0x04, 0x00000200 },
-	{ 0x419a1c,   1, 0x04, 0x0000c000 },
-	{ 0x419a20,   1, 0x04, 0x00000800 },
-	{ 0x419a30,   1, 0x04, 0x00000001 },
-	{ 0x419ac4,   1, 0x04, 0x0037f440 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nve4_grctx_init_mpc_0[] = {
-	{ 0x419c00,   1, 0x04, 0x0000000a },
-	{ 0x419c04,   1, 0x04, 0x80000006 },
-	{ 0x419c08,   1, 0x04, 0x00000002 },
-	{ 0x419c20,   1, 0x04, 0x00000000 },
-	{ 0x419c24,   1, 0x04, 0x00084210 },
-	{ 0x419c28,   1, 0x04, 0x3efbefbe },
-	{}
-};
-
-static const struct nvc0_graph_init
-nve4_grctx_init_l1c_0[] = {
-	{ 0x419ce8,   1, 0x04, 0x00000000 },
-	{ 0x419cf4,   1, 0x04, 0x00003203 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nve4_grctx_init_sm_0[] = {
-	{ 0x419e04,   3, 0x04, 0x00000000 },
-	{ 0x419e10,   1, 0x04, 0x00000402 },
-	{ 0x419e44,   1, 0x04, 0x0013eff2 },
-	{ 0x419e48,   1, 0x04, 0x00000000 },
-	{ 0x419e4c,   1, 0x04, 0x0000007f },
-	{ 0x419e50,  19, 0x04, 0x00000000 },
-	{ 0x419eac,   1, 0x04, 0x00001f8f },
-	{ 0x419eb0,   1, 0x04, 0x00000d3f },
-	{ 0x419ec8,   1, 0x04, 0x0001304f },
-	{ 0x419f30,   8, 0x04, 0x00000000 },
-	{ 0x419f58,   1, 0x04, 0x00000000 },
-	{ 0x419f70,   1, 0x04, 0x00000000 },
-	{ 0x419f78,   1, 0x04, 0x0000000b },
-	{ 0x419f7c,   1, 0x04, 0x0000027c },
-	{}
-};
-
-const struct nvc0_graph_pack
-nve4_grctx_pack_tpc[] = {
-	{ nvd7_grctx_init_pe_0 },
-	{ nve4_grctx_init_tex_0 },
-	{ nve4_grctx_init_mpc_0 },
-	{ nve4_grctx_init_l1c_0 },
-	{ nve4_grctx_init_sm_0 },
-	{}
-};
-
-const struct nvc0_graph_init
-nve4_grctx_init_pes_0[] = {
-	{ 0x41be24,   1, 0x04, 0x00000006 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nve4_grctx_init_cbm_0[] = {
-	{ 0x41bec0,   1, 0x04, 0x12180000 },
-	{ 0x41bec4,   1, 0x04, 0x00037f7f },
-	{ 0x41bee4,   1, 0x04, 0x06480430 },
-	{}
-};
-
-const struct nvc0_graph_pack
-nve4_grctx_pack_ppc[] = {
-	{ nve4_grctx_init_pes_0 },
-	{ nve4_grctx_init_cbm_0 },
-	{ nvd7_grctx_init_wwdx_0 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH context implementation
- ******************************************************************************/
-
-void
-nve4_grctx_generate_bundle(struct nvc0_grctx *info)
-{
-	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
-	const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth,
-				    impl->bundle_size / 0x20);
-	const u32 token_limit = impl->bundle_token_limit;
-	const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
-	const int s = 8;
-	const int b = mmio_vram(info, impl->bundle_size, (1 << s), access);
-	mmio_refn(info, 0x408004, 0x00000000, s, b);
-	mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b);
-	mmio_refn(info, 0x418808, 0x00000000, s, b);
-	mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b);
-	mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit);
-}
-
-void
-nve4_grctx_generate_pagepool(struct nvc0_grctx *info)
-{
-	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
-	const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
-	const int s = 8;
-	const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
-	mmio_refn(info, 0x40800c, 0x00000000, s, b);
-	mmio_wr32(info, 0x408010, 0x80000000);
-	mmio_refn(info, 0x419004, 0x00000000, s, b);
-	mmio_wr32(info, 0x419008, 0x00000000);
-	mmio_wr32(info, 0x4064cc, 0x80000000);
-}
-
-void
-nve4_grctx_generate_unkn(struct nvc0_graph_priv *priv)
-{
-	nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
-	nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
-	nv_mask(priv, 0x41be08, 0x00000004, 0x00000004);
-	nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000);
-	nv_mask(priv, 0x405800, 0x08000000, 0x08000000);
-	nv_mask(priv, 0x419c00, 0x00000008, 0x00000008);
-}
-
-void
-nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *priv)
-{
-	u32 data[6] = {}, data2[2] = {};
-	u8  tpcnr[GPC_MAX];
-	u8  shift, ntpcv;
-	int gpc, tpc, i;
-
-	/* calculate first set of magics */
-	memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
-
-	gpc = -1;
-	for (tpc = 0; tpc < priv->tpc_total; tpc++) {
-		do {
-			gpc = (gpc + 1) % priv->gpc_nr;
-		} while (!tpcnr[gpc]);
-		tpcnr[gpc]--;
-
-		data[tpc / 6] |= gpc << ((tpc % 6) * 5);
-	}
-
-	for (; tpc < 32; tpc++)
-		data[tpc / 6] |= 7 << ((tpc % 6) * 5);
-
-	/* and the second... */
-	shift = 0;
-	ntpcv = priv->tpc_total;
-	while (!(ntpcv & (1 << 4))) {
-		ntpcv <<= 1;
-		shift++;
-	}
-
-	data2[0]  = (ntpcv << 16);
-	data2[0] |= (shift << 21);
-	data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24);
-	for (i = 1; i < 7; i++)
-		data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
-
-	/* GPC_BROADCAST */
-	nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) |
-				 priv->magic_not_rop_nr);
-	for (i = 0; i < 6; i++)
-		nv_wr32(priv, 0x418b08 + (i * 4), data[i]);
-
-	/* GPC_BROADCAST.TP_BROADCAST */
-	nv_wr32(priv, 0x41bfd0, (priv->tpc_total << 8) |
-				 priv->magic_not_rop_nr | data2[0]);
-	nv_wr32(priv, 0x41bfe4, data2[1]);
-	for (i = 0; i < 6; i++)
-		nv_wr32(priv, 0x41bf00 + (i * 4), data[i]);
-
-	/* UNK78xx */
-	nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) |
-				 priv->magic_not_rop_nr);
-	for (i = 0; i < 6; i++)
-		nv_wr32(priv, 0x40780c + (i * 4), data[i]);
-}
-
-void
-nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
-{
-	struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
-	int i;
-
-	nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
-
-	nvc0_graph_mmio(priv, oclass->hub);
-	nvc0_graph_mmio(priv, oclass->gpc);
-	nvc0_graph_mmio(priv, oclass->zcull);
-	nvc0_graph_mmio(priv, oclass->tpc);
-	nvc0_graph_mmio(priv, oclass->ppc);
-
-	nv_wr32(priv, 0x404154, 0x00000000);
-
-	oclass->bundle(info);
-	oclass->pagepool(info);
-	oclass->attrib(info);
-	oclass->unkn(priv);
-
-	nvc0_grctx_generate_tpcid(priv);
-	nvc0_grctx_generate_r406028(priv);
-	nve4_grctx_generate_r418bb8(priv);
-	nvc0_grctx_generate_r406800(priv);
-
-	for (i = 0; i < 8; i++)
-		nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
-
-	nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
-	if (priv->gpc_nr == 1) {
-		nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]);
-		nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]);
-	} else {
-		nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr);
-		nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
-	}
-	nv_mask(priv, 0x419f78, 0x00000001, 0x00000000);
-
-	nvc0_graph_icmd(priv, oclass->icmd);
-	nv_wr32(priv, 0x404154, 0x00000400);
-	nvc0_graph_mthd(priv, oclass->mthd);
-	nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
-
-	nv_mask(priv, 0x418800, 0x00200000, 0x00200000);
-	nv_mask(priv, 0x41be10, 0x00800000, 0x00800000);
-}
-
-struct nouveau_oclass *
-nve4_grctx_oclass = &(struct nvc0_grctx_oclass) {
-	.base.handle = NV_ENGCTX(GR, 0xe4),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-	.main  = nve4_grctx_generate_main,
-	.unkn  = nve4_grctx_generate_unkn,
-	.hub   = nve4_grctx_pack_hub,
-	.gpc   = nve4_grctx_pack_gpc,
-	.zcull = nvc0_grctx_pack_zcull,
-	.tpc   = nve4_grctx_pack_tpc,
-	.ppc   = nve4_grctx_pack_ppc,
-	.icmd  = nve4_grctx_pack_icmd,
-	.mthd  = nve4_grctx_pack_mthd,
-	.bundle = nve4_grctx_generate_bundle,
-	.bundle_size = 0x3000,
-	.bundle_min_gpm_fifo_depth = 0x180,
-	.bundle_token_limit = 0x600,
-	.pagepool = nve4_grctx_generate_pagepool,
-	.pagepool_size = 0x8000,
-	.attrib = nvd7_grctx_generate_attrib,
-	.attrib_nr_max = 0x324,
-	.attrib_nr = 0x218,
-	.alpha_nr_max = 0x7ff,
-	.alpha_nr = 0x648,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
deleted file mode 100644
index e9b0dcf95a49..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
+++ /dev/null
@@ -1,843 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * PGRAPH context register lists
- ******************************************************************************/
-
-static const struct nvc0_graph_init
-nvf0_grctx_init_icmd_0[] = {
-	{ 0x001000,   1, 0x01, 0x00000004 },
-	{ 0x000039,   3, 0x01, 0x00000000 },
-	{ 0x0000a9,   1, 0x01, 0x0000ffff },
-	{ 0x000038,   1, 0x01, 0x0fac6881 },
-	{ 0x00003d,   1, 0x01, 0x00000001 },
-	{ 0x0000e8,   8, 0x01, 0x00000400 },
-	{ 0x000078,   8, 0x01, 0x00000300 },
-	{ 0x000050,   1, 0x01, 0x00000011 },
-	{ 0x000058,   8, 0x01, 0x00000008 },
-	{ 0x000208,   8, 0x01, 0x00000001 },
-	{ 0x000081,   1, 0x01, 0x00000001 },
-	{ 0x000085,   1, 0x01, 0x00000004 },
-	{ 0x000088,   1, 0x01, 0x00000400 },
-	{ 0x000090,   1, 0x01, 0x00000300 },
-	{ 0x000098,   1, 0x01, 0x00001001 },
-	{ 0x0000e3,   1, 0x01, 0x00000001 },
-	{ 0x0000da,   1, 0x01, 0x00000001 },
-	{ 0x0000f8,   1, 0x01, 0x00000003 },
-	{ 0x0000fa,   1, 0x01, 0x00000001 },
-	{ 0x00009f,   4, 0x01, 0x0000ffff },
-	{ 0x0000b1,   1, 0x01, 0x00000001 },
-	{ 0x0000ad,   1, 0x01, 0x0000013e },
-	{ 0x0000e1,   1, 0x01, 0x00000010 },
-	{ 0x000290,  16, 0x01, 0x00000000 },
-	{ 0x0003b0,  16, 0x01, 0x00000000 },
-	{ 0x0002a0,  16, 0x01, 0x00000000 },
-	{ 0x000420,  16, 0x01, 0x00000000 },
-	{ 0x0002b0,  16, 0x01, 0x00000000 },
-	{ 0x000430,  16, 0x01, 0x00000000 },
-	{ 0x0002c0,  16, 0x01, 0x00000000 },
-	{ 0x0004d0,  16, 0x01, 0x00000000 },
-	{ 0x000720,  16, 0x01, 0x00000000 },
-	{ 0x0008c0,  16, 0x01, 0x00000000 },
-	{ 0x000890,  16, 0x01, 0x00000000 },
-	{ 0x0008e0,  16, 0x01, 0x00000000 },
-	{ 0x0008a0,  16, 0x01, 0x00000000 },
-	{ 0x0008f0,  16, 0x01, 0x00000000 },
-	{ 0x00094c,   1, 0x01, 0x000000ff },
-	{ 0x00094d,   1, 0x01, 0xffffffff },
-	{ 0x00094e,   1, 0x01, 0x00000002 },
-	{ 0x0002ec,   1, 0x01, 0x00000001 },
-	{ 0x0002f2,   2, 0x01, 0x00000001 },
-	{ 0x0002f5,   1, 0x01, 0x00000001 },
-	{ 0x0002f7,   1, 0x01, 0x00000001 },
-	{ 0x000303,   1, 0x01, 0x00000001 },
-	{ 0x0002e6,   1, 0x01, 0x00000001 },
-	{ 0x000466,   1, 0x01, 0x00000052 },
-	{ 0x000301,   1, 0x01, 0x3f800000 },
-	{ 0x000304,   1, 0x01, 0x30201000 },
-	{ 0x000305,   1, 0x01, 0x70605040 },
-	{ 0x000306,   1, 0x01, 0xb8a89888 },
-	{ 0x000307,   1, 0x01, 0xf8e8d8c8 },
-	{ 0x00030a,   1, 0x01, 0x00ffff00 },
-	{ 0x00030b,   1, 0x01, 0x0000001a },
-	{ 0x00030c,   1, 0x01, 0x00000001 },
-	{ 0x000318,   1, 0x01, 0x00000001 },
-	{ 0x000340,   1, 0x01, 0x00000000 },
-	{ 0x000375,   1, 0x01, 0x00000001 },
-	{ 0x00037d,   1, 0x01, 0x00000006 },
-	{ 0x0003a0,   1, 0x01, 0x00000002 },
-	{ 0x0003aa,   1, 0x01, 0x00000001 },
-	{ 0x0003a9,   1, 0x01, 0x00000001 },
-	{ 0x000380,   1, 0x01, 0x00000001 },
-	{ 0x000383,   1, 0x01, 0x00000011 },
-	{ 0x000360,   1, 0x01, 0x00000040 },
-	{ 0x000366,   2, 0x01, 0x00000000 },
-	{ 0x000368,   1, 0x01, 0x00000fff },
-	{ 0x000370,   2, 0x01, 0x00000000 },
-	{ 0x000372,   1, 0x01, 0x000fffff },
-	{ 0x00037a,   1, 0x01, 0x00000012 },
-	{ 0x000619,   1, 0x01, 0x00000003 },
-	{ 0x000811,   1, 0x01, 0x00000003 },
-	{ 0x000812,   1, 0x01, 0x00000004 },
-	{ 0x000813,   1, 0x01, 0x00000006 },
-	{ 0x000814,   1, 0x01, 0x00000008 },
-	{ 0x000815,   1, 0x01, 0x0000000b },
-	{ 0x000800,   6, 0x01, 0x00000001 },
-	{ 0x000632,   1, 0x01, 0x00000001 },
-	{ 0x000633,   1, 0x01, 0x00000002 },
-	{ 0x000634,   1, 0x01, 0x00000003 },
-	{ 0x000635,   1, 0x01, 0x00000004 },
-	{ 0x000654,   1, 0x01, 0x3f800000 },
-	{ 0x000657,   1, 0x01, 0x3f800000 },
-	{ 0x000655,   2, 0x01, 0x3f800000 },
-	{ 0x0006cd,   1, 0x01, 0x3f800000 },
-	{ 0x0007f5,   1, 0x01, 0x3f800000 },
-	{ 0x0007dc,   1, 0x01, 0x39291909 },
-	{ 0x0007dd,   1, 0x01, 0x79695949 },
-	{ 0x0007de,   1, 0x01, 0xb9a99989 },
-	{ 0x0007df,   1, 0x01, 0xf9e9d9c9 },
-	{ 0x0007e8,   1, 0x01, 0x00003210 },
-	{ 0x0007e9,   1, 0x01, 0x00007654 },
-	{ 0x0007ea,   1, 0x01, 0x00000098 },
-	{ 0x0007ec,   1, 0x01, 0x39291909 },
-	{ 0x0007ed,   1, 0x01, 0x79695949 },
-	{ 0x0007ee,   1, 0x01, 0xb9a99989 },
-	{ 0x0007ef,   1, 0x01, 0xf9e9d9c9 },
-	{ 0x0007f0,   1, 0x01, 0x00003210 },
-	{ 0x0007f1,   1, 0x01, 0x00007654 },
-	{ 0x0007f2,   1, 0x01, 0x00000098 },
-	{ 0x0005a5,   1, 0x01, 0x00000001 },
-	{ 0x000980, 128, 0x01, 0x00000000 },
-	{ 0x000468,   1, 0x01, 0x00000004 },
-	{ 0x00046c,   1, 0x01, 0x00000001 },
-	{ 0x000470,  96, 0x01, 0x00000000 },
-	{ 0x000510,  16, 0x01, 0x3f800000 },
-	{ 0x000520,   1, 0x01, 0x000002b6 },
-	{ 0x000529,   1, 0x01, 0x00000001 },
-	{ 0x000530,  16, 0x01, 0xffff0000 },
-	{ 0x000585,   1, 0x01, 0x0000003f },
-	{ 0x000576,   1, 0x01, 0x00000003 },
-	{ 0x00057b,   1, 0x01, 0x00000059 },
-	{ 0x000586,   1, 0x01, 0x00000040 },
-	{ 0x000582,   2, 0x01, 0x00000080 },
-	{ 0x0005c2,   1, 0x01, 0x00000001 },
-	{ 0x000638,   2, 0x01, 0x00000001 },
-	{ 0x00063a,   1, 0x01, 0x00000002 },
-	{ 0x00063b,   2, 0x01, 0x00000001 },
-	{ 0x00063d,   1, 0x01, 0x00000002 },
-	{ 0x00063e,   1, 0x01, 0x00000001 },
-	{ 0x0008b8,   8, 0x01, 0x00000001 },
-	{ 0x000900,   8, 0x01, 0x00000001 },
-	{ 0x000908,   8, 0x01, 0x00000002 },
-	{ 0x000910,  16, 0x01, 0x00000001 },
-	{ 0x000920,   8, 0x01, 0x00000002 },
-	{ 0x000928,   8, 0x01, 0x00000001 },
-	{ 0x000662,   1, 0x01, 0x00000001 },
-	{ 0x000648,   9, 0x01, 0x00000001 },
-	{ 0x000658,   1, 0x01, 0x0000000f },
-	{ 0x0007ff,   1, 0x01, 0x0000000a },
-	{ 0x00066a,   1, 0x01, 0x40000000 },
-	{ 0x00066b,   1, 0x01, 0x10000000 },
-	{ 0x00066c,   2, 0x01, 0xffff0000 },
-	{ 0x0007af,   2, 0x01, 0x00000008 },
-	{ 0x0007f6,   1, 0x01, 0x00000001 },
-	{ 0x00080b,   1, 0x01, 0x00000002 },
-	{ 0x0006b2,   1, 0x01, 0x00000055 },
-	{ 0x0007ad,   1, 0x01, 0x00000003 },
-	{ 0x000937,   1, 0x01, 0x00000001 },
-	{ 0x000971,   1, 0x01, 0x00000008 },
-	{ 0x000972,   1, 0x01, 0x00000040 },
-	{ 0x000973,   1, 0x01, 0x0000012c },
-	{ 0x00097c,   1, 0x01, 0x00000040 },
-	{ 0x000979,   1, 0x01, 0x00000003 },
-	{ 0x000975,   1, 0x01, 0x00000020 },
-	{ 0x000976,   1, 0x01, 0x00000001 },
-	{ 0x000977,   1, 0x01, 0x00000020 },
-	{ 0x000978,   1, 0x01, 0x00000001 },
-	{ 0x000957,   1, 0x01, 0x00000003 },
-	{ 0x00095e,   1, 0x01, 0x20164010 },
-	{ 0x00095f,   1, 0x01, 0x00000020 },
-	{ 0x000a0d,   1, 0x01, 0x00000006 },
-	{ 0x00097d,   1, 0x01, 0x00000020 },
-	{ 0x000683,   1, 0x01, 0x00000006 },
-	{ 0x000685,   1, 0x01, 0x003fffff },
-	{ 0x000687,   1, 0x01, 0x003fffff },
-	{ 0x0006a0,   1, 0x01, 0x00000005 },
-	{ 0x000840,   1, 0x01, 0x00400008 },
-	{ 0x000841,   1, 0x01, 0x08000080 },
-	{ 0x000842,   1, 0x01, 0x00400008 },
-	{ 0x000843,   1, 0x01, 0x08000080 },
-	{ 0x0006aa,   1, 0x01, 0x00000001 },
-	{ 0x0006ab,   1, 0x01, 0x00000002 },
-	{ 0x0006ac,   1, 0x01, 0x00000080 },
-	{ 0x0006ad,   2, 0x01, 0x00000100 },
-	{ 0x0006b1,   1, 0x01, 0x00000011 },
-	{ 0x0006bb,   1, 0x01, 0x000000cf },
-	{ 0x0006ce,   1, 0x01, 0x2a712488 },
-	{ 0x000739,   1, 0x01, 0x4085c000 },
-	{ 0x00073a,   1, 0x01, 0x00000080 },
-	{ 0x000786,   1, 0x01, 0x80000100 },
-	{ 0x00073c,   1, 0x01, 0x00010100 },
-	{ 0x00073d,   1, 0x01, 0x02800000 },
-	{ 0x000787,   1, 0x01, 0x000000cf },
-	{ 0x00078c,   1, 0x01, 0x00000008 },
-	{ 0x000792,   1, 0x01, 0x00000001 },
-	{ 0x000794,   3, 0x01, 0x00000001 },
-	{ 0x000797,   1, 0x01, 0x000000cf },
-	{ 0x000836,   1, 0x01, 0x00000001 },
-	{ 0x00079a,   1, 0x01, 0x00000002 },
-	{ 0x000833,   1, 0x01, 0x04444480 },
-	{ 0x0007a1,   1, 0x01, 0x00000001 },
-	{ 0x0007a3,   3, 0x01, 0x00000001 },
-	{ 0x000831,   1, 0x01, 0x00000004 },
-	{ 0x000b07,   1, 0x01, 0x00000002 },
-	{ 0x000b08,   2, 0x01, 0x00000100 },
-	{ 0x000b0a,   1, 0x01, 0x00000001 },
-	{ 0x000a04,   1, 0x01, 0x000000ff },
-	{ 0x000a0b,   1, 0x01, 0x00000040 },
-	{ 0x00097f,   1, 0x01, 0x00000100 },
-	{ 0x000a02,   1, 0x01, 0x00000001 },
-	{ 0x000809,   1, 0x01, 0x00000007 },
-	{ 0x00c221,   1, 0x01, 0x00000040 },
-	{ 0x00c1b0,   8, 0x01, 0x0000000f },
-	{ 0x00c1b8,   1, 0x01, 0x0fac6881 },
-	{ 0x00c1b9,   1, 0x01, 0x00fac688 },
-	{ 0x00c401,   1, 0x01, 0x00000001 },
-	{ 0x00c402,   1, 0x01, 0x00010001 },
-	{ 0x00c403,   2, 0x01, 0x00000001 },
-	{ 0x00c40e,   1, 0x01, 0x00000020 },
-	{ 0x00c500,   1, 0x01, 0x00000003 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000002 },
-	{ 0x0006aa,   1, 0x01, 0x00000001 },
-	{ 0x0006ad,   2, 0x01, 0x00000100 },
-	{ 0x0006b1,   1, 0x01, 0x00000011 },
-	{ 0x00078c,   1, 0x01, 0x00000008 },
-	{ 0x000792,   1, 0x01, 0x00000001 },
-	{ 0x000794,   3, 0x01, 0x00000001 },
-	{ 0x000797,   1, 0x01, 0x000000cf },
-	{ 0x00079a,   1, 0x01, 0x00000002 },
-	{ 0x000833,   1, 0x01, 0x04444480 },
-	{ 0x0007a1,   1, 0x01, 0x00000001 },
-	{ 0x0007a3,   3, 0x01, 0x00000001 },
-	{ 0x000831,   1, 0x01, 0x00000004 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000008 },
-	{ 0x000039,   3, 0x01, 0x00000000 },
-	{ 0x000380,   1, 0x01, 0x00000001 },
-	{ 0x000366,   2, 0x01, 0x00000000 },
-	{ 0x000368,   1, 0x01, 0x00000fff },
-	{ 0x000370,   2, 0x01, 0x00000000 },
-	{ 0x000372,   1, 0x01, 0x000fffff },
-	{ 0x000813,   1, 0x01, 0x00000006 },
-	{ 0x000814,   1, 0x01, 0x00000008 },
-	{ 0x000957,   1, 0x01, 0x00000003 },
-	{ 0x000b07,   1, 0x01, 0x00000002 },
-	{ 0x000b08,   2, 0x01, 0x00000100 },
-	{ 0x000b0a,   1, 0x01, 0x00000001 },
-	{ 0x000a04,   1, 0x01, 0x000000ff },
-	{ 0x000a0b,   1, 0x01, 0x00000040 },
-	{ 0x00097f,   1, 0x01, 0x00000100 },
-	{ 0x000a02,   1, 0x01, 0x00000001 },
-	{ 0x000809,   1, 0x01, 0x00000007 },
-	{ 0x00c221,   1, 0x01, 0x00000040 },
-	{ 0x00c401,   1, 0x01, 0x00000001 },
-	{ 0x00c402,   1, 0x01, 0x00010001 },
-	{ 0x00c403,   2, 0x01, 0x00000001 },
-	{ 0x00c40e,   1, 0x01, 0x00000020 },
-	{ 0x00c500,   1, 0x01, 0x00000003 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{ 0x001000,   1, 0x01, 0x00000001 },
-	{ 0x000b07,   1, 0x01, 0x00000002 },
-	{ 0x000b08,   2, 0x01, 0x00000100 },
-	{ 0x000b0a,   1, 0x01, 0x00000001 },
-	{ 0x01e100,   1, 0x01, 0x00000001 },
-	{}
-};
-
-const struct nvc0_graph_pack
-nvf0_grctx_pack_icmd[] = {
-	{ nvf0_grctx_init_icmd_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvf0_grctx_init_a197_0[] = {
-	{ 0x000800,   8, 0x40, 0x00000000 },
-	{ 0x000804,   8, 0x40, 0x00000000 },
-	{ 0x000808,   8, 0x40, 0x00000400 },
-	{ 0x00080c,   8, 0x40, 0x00000300 },
-	{ 0x000810,   1, 0x04, 0x000000cf },
-	{ 0x000850,   7, 0x40, 0x00000000 },
-	{ 0x000814,   8, 0x40, 0x00000040 },
-	{ 0x000818,   8, 0x40, 0x00000001 },
-	{ 0x00081c,   8, 0x40, 0x00000000 },
-	{ 0x000820,   8, 0x40, 0x00000000 },
-	{ 0x001c00,  16, 0x10, 0x00000000 },
-	{ 0x001c04,  16, 0x10, 0x00000000 },
-	{ 0x001c08,  16, 0x10, 0x00000000 },
-	{ 0x001c0c,  16, 0x10, 0x00000000 },
-	{ 0x001d00,  16, 0x10, 0x00000000 },
-	{ 0x001d04,  16, 0x10, 0x00000000 },
-	{ 0x001d08,  16, 0x10, 0x00000000 },
-	{ 0x001d0c,  16, 0x10, 0x00000000 },
-	{ 0x001f00,  16, 0x08, 0x00000000 },
-	{ 0x001f04,  16, 0x08, 0x00000000 },
-	{ 0x001f80,  16, 0x08, 0x00000000 },
-	{ 0x001f84,  16, 0x08, 0x00000000 },
-	{ 0x002000,   1, 0x04, 0x00000000 },
-	{ 0x002040,   1, 0x04, 0x00000011 },
-	{ 0x002080,   1, 0x04, 0x00000020 },
-	{ 0x0020c0,   1, 0x04, 0x00000030 },
-	{ 0x002100,   1, 0x04, 0x00000040 },
-	{ 0x002140,   1, 0x04, 0x00000051 },
-	{ 0x00200c,   6, 0x40, 0x00000001 },
-	{ 0x002010,   1, 0x04, 0x00000000 },
-	{ 0x002050,   1, 0x04, 0x00000000 },
-	{ 0x002090,   1, 0x04, 0x00000001 },
-	{ 0x0020d0,   1, 0x04, 0x00000002 },
-	{ 0x002110,   1, 0x04, 0x00000003 },
-	{ 0x002150,   1, 0x04, 0x00000004 },
-	{ 0x000380,   4, 0x20, 0x00000000 },
-	{ 0x000384,   4, 0x20, 0x00000000 },
-	{ 0x000388,   4, 0x20, 0x00000000 },
-	{ 0x00038c,   4, 0x20, 0x00000000 },
-	{ 0x000700,   4, 0x10, 0x00000000 },
-	{ 0x000704,   4, 0x10, 0x00000000 },
-	{ 0x000708,   4, 0x10, 0x00000000 },
-	{ 0x002800, 128, 0x04, 0x00000000 },
-	{ 0x000a00,  16, 0x20, 0x00000000 },
-	{ 0x000a04,  16, 0x20, 0x00000000 },
-	{ 0x000a08,  16, 0x20, 0x00000000 },
-	{ 0x000a0c,  16, 0x20, 0x00000000 },
-	{ 0x000a10,  16, 0x20, 0x00000000 },
-	{ 0x000a14,  16, 0x20, 0x00000000 },
-	{ 0x000c00,  16, 0x10, 0x00000000 },
-	{ 0x000c04,  16, 0x10, 0x00000000 },
-	{ 0x000c08,  16, 0x10, 0x00000000 },
-	{ 0x000c0c,  16, 0x10, 0x3f800000 },
-	{ 0x000d00,   8, 0x08, 0xffff0000 },
-	{ 0x000d04,   8, 0x08, 0xffff0000 },
-	{ 0x000e00,  16, 0x10, 0x00000000 },
-	{ 0x000e04,  16, 0x10, 0xffff0000 },
-	{ 0x000e08,  16, 0x10, 0xffff0000 },
-	{ 0x000d40,   4, 0x08, 0x00000000 },
-	{ 0x000d44,   4, 0x08, 0x00000000 },
-	{ 0x001e00,   8, 0x20, 0x00000001 },
-	{ 0x001e04,   8, 0x20, 0x00000001 },
-	{ 0x001e08,   8, 0x20, 0x00000002 },
-	{ 0x001e0c,   8, 0x20, 0x00000001 },
-	{ 0x001e10,   8, 0x20, 0x00000001 },
-	{ 0x001e14,   8, 0x20, 0x00000002 },
-	{ 0x001e18,   8, 0x20, 0x00000001 },
-	{ 0x003400, 128, 0x04, 0x00000000 },
-	{ 0x00030c,   1, 0x04, 0x00000001 },
-	{ 0x001944,   1, 0x04, 0x00000000 },
-	{ 0x001514,   1, 0x04, 0x00000000 },
-	{ 0x000d68,   1, 0x04, 0x0000ffff },
-	{ 0x00121c,   1, 0x04, 0x0fac6881 },
-	{ 0x000fac,   1, 0x04, 0x00000001 },
-	{ 0x001538,   1, 0x04, 0x00000001 },
-	{ 0x000fe0,   2, 0x04, 0x00000000 },
-	{ 0x000fe8,   1, 0x04, 0x00000014 },
-	{ 0x000fec,   1, 0x04, 0x00000040 },
-	{ 0x000ff0,   1, 0x04, 0x00000000 },
-	{ 0x00179c,   1, 0x04, 0x00000000 },
-	{ 0x001228,   1, 0x04, 0x00000400 },
-	{ 0x00122c,   1, 0x04, 0x00000300 },
-	{ 0x001230,   1, 0x04, 0x00010001 },
-	{ 0x0007f8,   1, 0x04, 0x00000000 },
-	{ 0x0015b4,   1, 0x04, 0x00000001 },
-	{ 0x0015cc,   1, 0x04, 0x00000000 },
-	{ 0x001534,   1, 0x04, 0x00000000 },
-	{ 0x000fb0,   1, 0x04, 0x00000000 },
-	{ 0x0015d0,   1, 0x04, 0x00000000 },
-	{ 0x00153c,   1, 0x04, 0x00000000 },
-	{ 0x0016b4,   1, 0x04, 0x00000003 },
-	{ 0x000fbc,   4, 0x04, 0x0000ffff },
-	{ 0x000df8,   2, 0x04, 0x00000000 },
-	{ 0x001948,   1, 0x04, 0x00000000 },
-	{ 0x001970,   1, 0x04, 0x00000001 },
-	{ 0x00161c,   1, 0x04, 0x000009f0 },
-	{ 0x000dcc,   1, 0x04, 0x00000010 },
-	{ 0x00163c,   1, 0x04, 0x00000000 },
-	{ 0x0015e4,   1, 0x04, 0x00000000 },
-	{ 0x001160,  32, 0x04, 0x25e00040 },
-	{ 0x001880,  32, 0x04, 0x00000000 },
-	{ 0x000f84,   2, 0x04, 0x00000000 },
-	{ 0x0017c8,   2, 0x04, 0x00000000 },
-	{ 0x0017d0,   1, 0x04, 0x000000ff },
-	{ 0x0017d4,   1, 0x04, 0xffffffff },
-	{ 0x0017d8,   1, 0x04, 0x00000002 },
-	{ 0x0017dc,   1, 0x04, 0x00000000 },
-	{ 0x0015f4,   2, 0x04, 0x00000000 },
-	{ 0x001434,   2, 0x04, 0x00000000 },
-	{ 0x000d74,   1, 0x04, 0x00000000 },
-	{ 0x000dec,   1, 0x04, 0x00000001 },
-	{ 0x0013a4,   1, 0x04, 0x00000000 },
-	{ 0x001318,   1, 0x04, 0x00000001 },
-	{ 0x001644,   1, 0x04, 0x00000000 },
-	{ 0x000748,   1, 0x04, 0x00000000 },
-	{ 0x000de8,   1, 0x04, 0x00000000 },
-	{ 0x001648,   1, 0x04, 0x00000000 },
-	{ 0x0012a4,   1, 0x04, 0x00000000 },
-	{ 0x001120,   4, 0x04, 0x00000000 },
-	{ 0x001118,   1, 0x04, 0x00000000 },
-	{ 0x00164c,   1, 0x04, 0x00000000 },
-	{ 0x001658,   1, 0x04, 0x00000000 },
-	{ 0x001910,   1, 0x04, 0x00000290 },
-	{ 0x001518,   1, 0x04, 0x00000000 },
-	{ 0x00165c,   1, 0x04, 0x00000001 },
-	{ 0x001520,   1, 0x04, 0x00000000 },
-	{ 0x001604,   1, 0x04, 0x00000000 },
-	{ 0x001570,   1, 0x04, 0x00000000 },
-	{ 0x0013b0,   2, 0x04, 0x3f800000 },
-	{ 0x00020c,   1, 0x04, 0x00000000 },
-	{ 0x001670,   1, 0x04, 0x30201000 },
-	{ 0x001674,   1, 0x04, 0x70605040 },
-	{ 0x001678,   1, 0x04, 0xb8a89888 },
-	{ 0x00167c,   1, 0x04, 0xf8e8d8c8 },
-	{ 0x00166c,   1, 0x04, 0x00000000 },
-	{ 0x001680,   1, 0x04, 0x00ffff00 },
-	{ 0x0012d0,   1, 0x04, 0x00000003 },
-	{ 0x0012d4,   1, 0x04, 0x00000002 },
-	{ 0x001684,   2, 0x04, 0x00000000 },
-	{ 0x000dac,   2, 0x04, 0x00001b02 },
-	{ 0x000db4,   1, 0x04, 0x00000000 },
-	{ 0x00168c,   1, 0x04, 0x00000000 },
-	{ 0x0015bc,   1, 0x04, 0x00000000 },
-	{ 0x00156c,   1, 0x04, 0x00000000 },
-	{ 0x00187c,   1, 0x04, 0x00000000 },
-	{ 0x001110,   1, 0x04, 0x00000001 },
-	{ 0x000dc0,   3, 0x04, 0x00000000 },
-	{ 0x001234,   1, 0x04, 0x00000000 },
-	{ 0x001690,   1, 0x04, 0x00000000 },
-	{ 0x0012ac,   1, 0x04, 0x00000001 },
-	{ 0x0002c4,   1, 0x04, 0x00000000 },
-	{ 0x000790,   5, 0x04, 0x00000000 },
-	{ 0x00077c,   1, 0x04, 0x00000000 },
-	{ 0x001000,   1, 0x04, 0x00000010 },
-	{ 0x0010fc,   1, 0x04, 0x00000000 },
-	{ 0x001290,   1, 0x04, 0x00000000 },
-	{ 0x000218,   1, 0x04, 0x00000010 },
-	{ 0x0012d8,   1, 0x04, 0x00000000 },
-	{ 0x0012dc,   1, 0x04, 0x00000010 },
-	{ 0x000d94,   1, 0x04, 0x00000001 },
-	{ 0x00155c,   2, 0x04, 0x00000000 },
-	{ 0x001564,   1, 0x04, 0x00000fff },
-	{ 0x001574,   2, 0x04, 0x00000000 },
-	{ 0x00157c,   1, 0x04, 0x000fffff },
-	{ 0x001354,   1, 0x04, 0x00000000 },
-	{ 0x001610,   1, 0x04, 0x00000012 },
-	{ 0x001608,   2, 0x04, 0x00000000 },
-	{ 0x00260c,   1, 0x04, 0x00000000 },
-	{ 0x0007ac,   1, 0x04, 0x00000000 },
-	{ 0x00162c,   1, 0x04, 0x00000003 },
-	{ 0x000210,   1, 0x04, 0x00000000 },
-	{ 0x000320,   1, 0x04, 0x00000000 },
-	{ 0x000324,   6, 0x04, 0x3f800000 },
-	{ 0x000750,   1, 0x04, 0x00000000 },
-	{ 0x000760,   1, 0x04, 0x39291909 },
-	{ 0x000764,   1, 0x04, 0x79695949 },
-	{ 0x000768,   1, 0x04, 0xb9a99989 },
-	{ 0x00076c,   1, 0x04, 0xf9e9d9c9 },
-	{ 0x000770,   1, 0x04, 0x30201000 },
-	{ 0x000774,   1, 0x04, 0x70605040 },
-	{ 0x000778,   1, 0x04, 0x00009080 },
-	{ 0x000780,   1, 0x04, 0x39291909 },
-	{ 0x000784,   1, 0x04, 0x79695949 },
-	{ 0x000788,   1, 0x04, 0xb9a99989 },
-	{ 0x00078c,   1, 0x04, 0xf9e9d9c9 },
-	{ 0x0007d0,   1, 0x04, 0x30201000 },
-	{ 0x0007d4,   1, 0x04, 0x70605040 },
-	{ 0x0007d8,   1, 0x04, 0x00009080 },
-	{ 0x00037c,   1, 0x04, 0x00000001 },
-	{ 0x000740,   2, 0x04, 0x00000000 },
-	{ 0x002600,   1, 0x04, 0x00000000 },
-	{ 0x001918,   1, 0x04, 0x00000000 },
-	{ 0x00191c,   1, 0x04, 0x00000900 },
-	{ 0x001920,   1, 0x04, 0x00000405 },
-	{ 0x001308,   1, 0x04, 0x00000001 },
-	{ 0x001924,   1, 0x04, 0x00000000 },
-	{ 0x0013ac,   1, 0x04, 0x00000000 },
-	{ 0x00192c,   1, 0x04, 0x00000001 },
-	{ 0x00193c,   1, 0x04, 0x00002c1c },
-	{ 0x000d7c,   1, 0x04, 0x00000000 },
-	{ 0x000f8c,   1, 0x04, 0x00000000 },
-	{ 0x0002c0,   1, 0x04, 0x00000001 },
-	{ 0x001510,   1, 0x04, 0x00000000 },
-	{ 0x001940,   1, 0x04, 0x00000000 },
-	{ 0x000ff4,   2, 0x04, 0x00000000 },
-	{ 0x00194c,   2, 0x04, 0x00000000 },
-	{ 0x001968,   1, 0x04, 0x00000000 },
-	{ 0x001590,   1, 0x04, 0x0000003f },
-	{ 0x0007e8,   4, 0x04, 0x00000000 },
-	{ 0x00196c,   1, 0x04, 0x00000011 },
-	{ 0x0002e4,   1, 0x04, 0x0000b001 },
-	{ 0x00036c,   2, 0x04, 0x00000000 },
-	{ 0x00197c,   1, 0x04, 0x00000000 },
-	{ 0x000fcc,   2, 0x04, 0x00000000 },
-	{ 0x0002d8,   1, 0x04, 0x00000040 },
-	{ 0x001980,   1, 0x04, 0x00000080 },
-	{ 0x001504,   1, 0x04, 0x00000080 },
-	{ 0x001984,   1, 0x04, 0x00000000 },
-	{ 0x000300,   1, 0x04, 0x00000001 },
-	{ 0x0013a8,   1, 0x04, 0x00000000 },
-	{ 0x0012ec,   1, 0x04, 0x00000000 },
-	{ 0x001310,   1, 0x04, 0x00000000 },
-	{ 0x001314,   1, 0x04, 0x00000001 },
-	{ 0x001380,   1, 0x04, 0x00000000 },
-	{ 0x001384,   4, 0x04, 0x00000001 },
-	{ 0x001394,   1, 0x04, 0x00000000 },
-	{ 0x00139c,   1, 0x04, 0x00000000 },
-	{ 0x001398,   1, 0x04, 0x00000000 },
-	{ 0x001594,   1, 0x04, 0x00000000 },
-	{ 0x001598,   4, 0x04, 0x00000001 },
-	{ 0x000f54,   3, 0x04, 0x00000000 },
-	{ 0x0019bc,   1, 0x04, 0x00000000 },
-	{ 0x000f9c,   2, 0x04, 0x00000000 },
-	{ 0x0012cc,   1, 0x04, 0x00000000 },
-	{ 0x0012e8,   1, 0x04, 0x00000000 },
-	{ 0x00130c,   1, 0x04, 0x00000001 },
-	{ 0x001360,   8, 0x04, 0x00000000 },
-	{ 0x00133c,   2, 0x04, 0x00000001 },
-	{ 0x001344,   1, 0x04, 0x00000002 },
-	{ 0x001348,   2, 0x04, 0x00000001 },
-	{ 0x001350,   1, 0x04, 0x00000002 },
-	{ 0x001358,   1, 0x04, 0x00000001 },
-	{ 0x0012e4,   1, 0x04, 0x00000000 },
-	{ 0x00131c,   4, 0x04, 0x00000000 },
-	{ 0x0019c0,   1, 0x04, 0x00000000 },
-	{ 0x001140,   1, 0x04, 0x00000000 },
-	{ 0x0019c4,   1, 0x04, 0x00000000 },
-	{ 0x0019c8,   1, 0x04, 0x00001500 },
-	{ 0x00135c,   1, 0x04, 0x00000000 },
-	{ 0x000f90,   1, 0x04, 0x00000000 },
-	{ 0x0019e0,   8, 0x04, 0x00000001 },
-	{ 0x0019cc,   1, 0x04, 0x00000001 },
-	{ 0x0015b8,   1, 0x04, 0x00000000 },
-	{ 0x001a00,   1, 0x04, 0x00001111 },
-	{ 0x001a04,   7, 0x04, 0x00000000 },
-	{ 0x000d6c,   2, 0x04, 0xffff0000 },
-	{ 0x0010f8,   1, 0x04, 0x00001010 },
-	{ 0x000d80,   5, 0x04, 0x00000000 },
-	{ 0x000da0,   1, 0x04, 0x00000000 },
-	{ 0x0007a4,   2, 0x04, 0x00000000 },
-	{ 0x001508,   1, 0x04, 0x80000000 },
-	{ 0x00150c,   1, 0x04, 0x40000000 },
-	{ 0x001668,   1, 0x04, 0x00000000 },
-	{ 0x000318,   2, 0x04, 0x00000008 },
-	{ 0x000d9c,   1, 0x04, 0x00000001 },
-	{ 0x000ddc,   1, 0x04, 0x00000002 },
-	{ 0x000374,   1, 0x04, 0x00000000 },
-	{ 0x000378,   1, 0x04, 0x00000020 },
-	{ 0x0007dc,   1, 0x04, 0x00000000 },
-	{ 0x00074c,   1, 0x04, 0x00000055 },
-	{ 0x001420,   1, 0x04, 0x00000003 },
-	{ 0x0017bc,   2, 0x04, 0x00000000 },
-	{ 0x0017c4,   1, 0x04, 0x00000001 },
-	{ 0x001008,   1, 0x04, 0x00000008 },
-	{ 0x00100c,   1, 0x04, 0x00000040 },
-	{ 0x001010,   1, 0x04, 0x0000012c },
-	{ 0x000d60,   1, 0x04, 0x00000040 },
-	{ 0x00075c,   1, 0x04, 0x00000003 },
-	{ 0x001018,   1, 0x04, 0x00000020 },
-	{ 0x00101c,   1, 0x04, 0x00000001 },
-	{ 0x001020,   1, 0x04, 0x00000020 },
-	{ 0x001024,   1, 0x04, 0x00000001 },
-	{ 0x001444,   3, 0x04, 0x00000000 },
-	{ 0x000360,   1, 0x04, 0x20164010 },
-	{ 0x000364,   1, 0x04, 0x00000020 },
-	{ 0x000368,   1, 0x04, 0x00000000 },
-	{ 0x000de4,   1, 0x04, 0x00000000 },
-	{ 0x000204,   1, 0x04, 0x00000006 },
-	{ 0x000208,   1, 0x04, 0x00000000 },
-	{ 0x0002cc,   2, 0x04, 0x003fffff },
-	{ 0x001220,   1, 0x04, 0x00000005 },
-	{ 0x000fdc,   1, 0x04, 0x00000000 },
-	{ 0x000f98,   1, 0x04, 0x00400008 },
-	{ 0x001284,   1, 0x04, 0x08000080 },
-	{ 0x001450,   1, 0x04, 0x00400008 },
-	{ 0x001454,   1, 0x04, 0x08000080 },
-	{ 0x000214,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_pack
-nvf0_grctx_pack_mthd[] = {
-	{ nvf0_grctx_init_a197_0, 0xa197 },
-	{ nvc0_grctx_init_902d_0, 0x902d },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvf0_grctx_init_fe_0[] = {
-	{ 0x404004,   8, 0x04, 0x00000000 },
-	{ 0x404024,   1, 0x04, 0x0000e000 },
-	{ 0x404028,   8, 0x04, 0x00000000 },
-	{ 0x4040a8,   8, 0x04, 0x00000000 },
-	{ 0x4040c8,   1, 0x04, 0xf800008f },
-	{ 0x4040d0,   6, 0x04, 0x00000000 },
-	{ 0x4040e8,   1, 0x04, 0x00001000 },
-	{ 0x4040f8,   1, 0x04, 0x00000000 },
-	{ 0x404100,  10, 0x04, 0x00000000 },
-	{ 0x404130,   2, 0x04, 0x00000000 },
-	{ 0x404138,   1, 0x04, 0x20000040 },
-	{ 0x404150,   1, 0x04, 0x0000002e },
-	{ 0x404154,   1, 0x04, 0x00000400 },
-	{ 0x404158,   1, 0x04, 0x00000200 },
-	{ 0x404164,   1, 0x04, 0x00000055 },
-	{ 0x40417c,   2, 0x04, 0x00000000 },
-	{ 0x4041a0,   4, 0x04, 0x00000000 },
-	{ 0x404200,   1, 0x04, 0x0000a197 },
-	{ 0x404204,   1, 0x04, 0x0000a1c0 },
-	{ 0x404208,   1, 0x04, 0x0000a140 },
-	{ 0x40420c,   1, 0x04, 0x0000902d },
-	{}
-};
-
-const struct nvc0_graph_init
-nvf0_grctx_init_pri_0[] = {
-	{ 0x404404,  12, 0x04, 0x00000000 },
-	{ 0x404438,   1, 0x04, 0x00000000 },
-	{ 0x404460,   2, 0x04, 0x00000000 },
-	{ 0x404468,   1, 0x04, 0x00ffffff },
-	{ 0x40446c,   1, 0x04, 0x00000000 },
-	{ 0x404480,   1, 0x04, 0x00000001 },
-	{ 0x404498,   1, 0x04, 0x00000001 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvf0_grctx_init_cwd_0[] = {
-	{ 0x405b00,   1, 0x04, 0x00000000 },
-	{ 0x405b10,   1, 0x04, 0x00001000 },
-	{ 0x405b20,   1, 0x04, 0x04000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvf0_grctx_init_pd_0[] = {
-	{ 0x406020,   1, 0x04, 0x034103c1 },
-	{ 0x406028,   4, 0x04, 0x00000001 },
-	{ 0x4064a8,   1, 0x04, 0x00000000 },
-	{ 0x4064ac,   1, 0x04, 0x00003fff },
-	{ 0x4064b0,   3, 0x04, 0x00000000 },
-	{ 0x4064c0,   1, 0x04, 0x802000f0 },
-	{ 0x4064c4,   1, 0x04, 0x0192ffff },
-	{ 0x4064c8,   1, 0x04, 0x018007c0 },
-	{ 0x4064cc,   9, 0x04, 0x00000000 },
-	{ 0x4064fc,   1, 0x04, 0x0000022a },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvf0_grctx_init_be_0[] = {
-	{ 0x408800,   1, 0x04, 0x12802a3c },
-	{ 0x408804,   1, 0x04, 0x00000040 },
-	{ 0x408808,   1, 0x04, 0x1003e005 },
-	{ 0x408840,   1, 0x04, 0x0000000b },
-	{ 0x408900,   1, 0x04, 0x3080b801 },
-	{ 0x408904,   1, 0x04, 0x62000001 },
-	{ 0x408908,   1, 0x04, 0x00c8102f },
-	{ 0x408980,   1, 0x04, 0x0000011d },
-	{}
-};
-
-const struct nvc0_graph_pack
-nvf0_grctx_pack_hub[] = {
-	{ nvc0_grctx_init_main_0 },
-	{ nvf0_grctx_init_fe_0 },
-	{ nvf0_grctx_init_pri_0 },
-	{ nve4_grctx_init_memfmt_0 },
-	{ nve4_grctx_init_ds_0 },
-	{ nvf0_grctx_init_cwd_0 },
-	{ nvf0_grctx_init_pd_0 },
-	{ nvc0_grctx_init_rstr2d_0 },
-	{ nve4_grctx_init_scc_0 },
-	{ nvf0_grctx_init_be_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvf0_grctx_init_setup_0[] = {
-	{ 0x418800,   1, 0x04, 0x7006860a },
-	{ 0x418808,   1, 0x04, 0x00000000 },
-	{ 0x41880c,   1, 0x04, 0x00000030 },
-	{ 0x418810,   1, 0x04, 0x00000000 },
-	{ 0x418828,   1, 0x04, 0x00000044 },
-	{ 0x418830,   1, 0x04, 0x10000001 },
-	{ 0x4188d8,   1, 0x04, 0x00000008 },
-	{ 0x4188e0,   1, 0x04, 0x01000000 },
-	{ 0x4188e8,   5, 0x04, 0x00000000 },
-	{ 0x4188fc,   1, 0x04, 0x20100018 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvf0_grctx_init_gpc_unk_2[] = {
-	{ 0x418d24,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_pack
-nvf0_grctx_pack_gpc[] = {
-	{ nvc0_grctx_init_gpc_unk_0 },
-	{ nvd9_grctx_init_prop_0 },
-	{ nvd9_grctx_init_gpc_unk_1 },
-	{ nvf0_grctx_init_setup_0 },
-	{ nvc0_grctx_init_zcull_0 },
-	{ nvd9_grctx_init_crstr_0 },
-	{ nve4_grctx_init_gpm_0 },
-	{ nvf0_grctx_init_gpc_unk_2 },
-	{ nvc0_grctx_init_gcc_0 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvf0_grctx_init_tex_0[] = {
-	{ 0x419a00,   1, 0x04, 0x000000f0 },
-	{ 0x419a04,   1, 0x04, 0x00000001 },
-	{ 0x419a08,   1, 0x04, 0x00000021 },
-	{ 0x419a0c,   1, 0x04, 0x00020000 },
-	{ 0x419a10,   1, 0x04, 0x00000000 },
-	{ 0x419a14,   1, 0x04, 0x00000200 },
-	{ 0x419a1c,   1, 0x04, 0x0000c000 },
-	{ 0x419a20,   1, 0x04, 0x00020800 },
-	{ 0x419a30,   1, 0x04, 0x00000001 },
-	{ 0x419ac4,   1, 0x04, 0x0037f440 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvf0_grctx_init_mpc_0[] = {
-	{ 0x419c00,   1, 0x04, 0x0000001a },
-	{ 0x419c04,   1, 0x04, 0x80000006 },
-	{ 0x419c08,   1, 0x04, 0x00000002 },
-	{ 0x419c20,   1, 0x04, 0x00000000 },
-	{ 0x419c24,   1, 0x04, 0x00084210 },
-	{ 0x419c28,   1, 0x04, 0x3efbefbe },
-	{}
-};
-
-const struct nvc0_graph_init
-nvf0_grctx_init_l1c_0[] = {
-	{ 0x419ce8,   1, 0x04, 0x00000000 },
-	{ 0x419cf4,   1, 0x04, 0x00000203 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvf0_grctx_init_sm_0[] = {
-	{ 0x419e04,   1, 0x04, 0x00000000 },
-	{ 0x419e08,   1, 0x04, 0x0000001d },
-	{ 0x419e0c,   1, 0x04, 0x00000000 },
-	{ 0x419e10,   1, 0x04, 0x00001c02 },
-	{ 0x419e44,   1, 0x04, 0x0013eff2 },
-	{ 0x419e48,   1, 0x04, 0x00000000 },
-	{ 0x419e4c,   1, 0x04, 0x0000007f },
-	{ 0x419e50,   2, 0x04, 0x00000000 },
-	{ 0x419e58,   1, 0x04, 0x00000001 },
-	{ 0x419e5c,   3, 0x04, 0x00000000 },
-	{ 0x419e68,   1, 0x04, 0x00000002 },
-	{ 0x419e6c,  12, 0x04, 0x00000000 },
-	{ 0x419eac,   1, 0x04, 0x00001f8f },
-	{ 0x419eb0,   1, 0x04, 0x0db00d2f },
-	{ 0x419eb8,   1, 0x04, 0x00000000 },
-	{ 0x419ec8,   1, 0x04, 0x0001304f },
-	{ 0x419f30,   4, 0x04, 0x00000000 },
-	{ 0x419f40,   1, 0x04, 0x00000018 },
-	{ 0x419f44,   3, 0x04, 0x00000000 },
-	{ 0x419f58,   1, 0x04, 0x00000000 },
-	{ 0x419f70,   1, 0x04, 0x00007300 },
-	{ 0x419f78,   1, 0x04, 0x000000eb },
-	{ 0x419f7c,   1, 0x04, 0x00000404 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvf0_grctx_pack_tpc[] = {
-	{ nvd7_grctx_init_pe_0 },
-	{ nvf0_grctx_init_tex_0 },
-	{ nvf0_grctx_init_mpc_0 },
-	{ nvf0_grctx_init_l1c_0 },
-	{ nvf0_grctx_init_sm_0 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvf0_grctx_init_cbm_0[] = {
-	{ 0x41bec0,   1, 0x04, 0x10000000 },
-	{ 0x41bec4,   1, 0x04, 0x00037f7f },
-	{ 0x41bee4,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_pack
-nvf0_grctx_pack_ppc[] = {
-	{ nve4_grctx_init_pes_0 },
-	{ nvf0_grctx_init_cbm_0 },
-	{ nvd7_grctx_init_wwdx_0 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH context implementation
- ******************************************************************************/
-
-struct nouveau_oclass *
-nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) {
-	.base.handle = NV_ENGCTX(GR, 0xf0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-	.main  = nve4_grctx_generate_main,
-	.unkn  = nve4_grctx_generate_unkn,
-	.hub   = nvf0_grctx_pack_hub,
-	.gpc   = nvf0_grctx_pack_gpc,
-	.zcull = nvc0_grctx_pack_zcull,
-	.tpc   = nvf0_grctx_pack_tpc,
-	.ppc   = nvf0_grctx_pack_ppc,
-	.icmd  = nvf0_grctx_pack_icmd,
-	.mthd  = nvf0_grctx_pack_mthd,
-	.bundle = nve4_grctx_generate_bundle,
-	.bundle_size = 0x3000,
-	.bundle_min_gpm_fifo_depth = 0x180,
-	.bundle_token_limit = 0x7c0,
-	.pagepool = nve4_grctx_generate_pagepool,
-	.pagepool_size = 0x8000,
-	.attrib = nvd7_grctx_generate_attrib,
-	.attrib_nr_max = 0x324,
-	.attrib_nr = 0x218,
-	.alpha_nr_max = 0x7ff,
-	.alpha_nr = 0x648,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc
deleted file mode 100644
index e37d8106ae1a..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc
+++ /dev/null
@@ -1,335 +0,0 @@
-/* fuc microcode util functions for nvc0 PGRAPH
- *
- * Copyright 2011 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#ifdef INCLUDE_CODE
-// queue_put - add request to queue
-//
-// In : $r13 queue pointer
-//	$r14 command
-//	$r15 data
-//
-queue_put:
-	// make sure we have space..
-	ld b32 $r8 D[$r13 + 0x0]	// GET
-	ld b32 $r9 D[$r13 + 0x4]	// PUT
-	xor $r8 8
-	cmpu b32 $r8 $r9
-	bra ne #queue_put_next
-		mov $r15 E_CMD_OVERFLOW
-		call(error)
-		ret
-
-	// store cmd/data on queue
-	queue_put_next:
-	and $r8 $r9 7
-	shl b32 $r8 3
-	add b32 $r8 $r13
-	add b32 $r8 8
-	st b32 D[$r8 + 0x0] $r14
-	st b32 D[$r8 + 0x4] $r15
-
-	// update PUT
-	add b32 $r9 1
-	and $r9 0xf
-	st b32 D[$r13 + 0x4] $r9
-	ret
-
-// queue_get - fetch request from queue
-//
-// In : $r13 queue pointer
-//
-// Out:	$p1  clear on success (data available)
-//	$r14 command
-// 	$r15 data
-//
-queue_get:
-	bset $flags $p1
-	ld b32 $r8 D[$r13 + 0x0]	// GET
-	ld b32 $r9 D[$r13 + 0x4]	// PUT
-	cmpu b32 $r8 $r9
-	bra e #queue_get_done
-		// fetch first cmd/data pair
-		and $r9 $r8 7
-		shl b32 $r9 3
-		add b32 $r9 $r13
-		add b32 $r9 8
-		ld b32 $r14 D[$r9 + 0x0]
-		ld b32 $r15 D[$r9 + 0x4]
-
-		// update GET
-		add b32 $r8 1
-		and $r8 0xf
-		st b32 D[$r13 + 0x0] $r8
-		bclr $flags $p1
-queue_get_done:
-	ret
-
-// nv_rd32 - read 32-bit value from nv register
-//
-// In : $r14 register
-// Out: $r15 value
-//
-nv_rd32:
-	mov b32 $r12 $r14
-	bset $r12 31			// MMIO_CTRL_PENDING
-	nv_iowr(NV_PGRAPH_FECS_MMIO_CTRL, 0, $r12)
-	nv_rd32_wait:
-		nv_iord($r12, NV_PGRAPH_FECS_MMIO_CTRL, 0)
-		xbit $r12 $r12 31
-		bra ne #nv_rd32_wait
-	mov $r10 6			// DONE_MMIO_RD
-	call(wait_doneo)
-	nv_iord($r15, NV_PGRAPH_FECS_MMIO_RDVAL, 0)
-	ret
-
-// nv_wr32 - write 32-bit value to nv register
-//
-// In : $r14 register
-//      $r15 value
-//
-nv_wr32:
-	nv_iowr(NV_PGRAPH_FECS_MMIO_WRVAL, 0, $r15)
-	mov b32 $r12 $r14
-	bset $r12 31			// MMIO_CTRL_PENDING
-	bset $r12 30			// MMIO_CTRL_WRITE
-	nv_iowr(NV_PGRAPH_FECS_MMIO_CTRL, 0, $r12)
-	nv_wr32_wait:
-		nv_iord($r12, NV_PGRAPH_FECS_MMIO_CTRL, 0)
-		xbit $r12 $r12 31
-		bra ne #nv_wr32_wait
-	ret
-
-// wait_donez - wait on FUC_DONE bit to become clear
-//
-// In : $r10 bit to wait on
-//
-wait_donez:
-	trace_set(T_WAIT);
-	nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(6), 0, $r10)
-	wait_donez_ne:
-		nv_iord($r8, NV_PGRAPH_FECS_SIGNAL, 0)
-		xbit $r8 $r8 $r10
-		bra ne #wait_donez_ne
-	trace_clr(T_WAIT)
-	ret
-
-// wait_doneo - wait on FUC_DONE bit to become set
-//
-// In : $r10 bit to wait on
-//
-wait_doneo:
-	trace_set(T_WAIT);
-	nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(6), 0, $r10)
-	wait_doneo_e:
-		nv_iord($r8, NV_PGRAPH_FECS_SIGNAL, 0)
-		xbit $r8 $r8 $r10
-		bra e #wait_doneo_e
-	trace_clr(T_WAIT)
-	ret
-
-// mmctx_size - determine size of a mmio list transfer
-//
-// In : $r14 mmio list head
-//      $r15 mmio list tail
-// Out: $r15 transfer size (in bytes)
-//
-mmctx_size:
-	clear b32 $r9
-	nv_mmctx_size_loop:
-		ld b32 $r8 D[$r14]
-		shr b32 $r8 26
-		add b32 $r8 1
-		shl b32 $r8 2
-		add b32 $r9 $r8
-		add b32 $r14 4
-		cmpu b32 $r14 $r15
-		bra ne #nv_mmctx_size_loop
-	mov b32 $r15 $r9
-	ret
-
-// mmctx_xfer - execute a list of mmio transfers
-//
-// In : $r10 flags
-//		bit 0: direction (0 = save, 1 = load)
-//		bit 1: set if first transfer
-//		bit 2: set if last transfer
-//	$r11 base
-//	$r12 mmio list head
-//	$r13 mmio list tail
-//	$r14 multi_stride
-//	$r15 multi_mask
-//
-mmctx_xfer:
-	trace_set(T_MMCTX)
-	clear b32 $r9
-	or $r11 $r11
-	bra e #mmctx_base_disabled
-		nv_iowr(NV_PGRAPH_FECS_MMCTX_BASE, 0, $r11)
-		bset $r9 0			// BASE_EN
-	mmctx_base_disabled:
-	or $r14 $r14
-	bra e #mmctx_multi_disabled
-		nv_iowr(NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE, 0, $r14)
-		nv_iowr(NV_PGRAPH_FECS_MMCTX_MULTI_MASK, 0, $r15)
-		bset $r9 1			// MULTI_EN
-	mmctx_multi_disabled:
-
-	xbit $r11 $r10 0
-	shl b32 $r11 16			// DIR
-	bset $r11 12			// QLIMIT = 0x10
-	xbit $r14 $r10 1
-	shl b32 $r14 17
-	or $r11 $r14			// START_TRIGGER
-	nv_iowr(NV_PGRAPH_FECS_MMCTX_CTRL, 0, $r11)
-
-	// loop over the mmio list, and send requests to the hw
-	mmctx_exec_loop:
-		// wait for space in mmctx queue
-		mmctx_wait_free:
-			nv_iord($r14, NV_PGRAPH_FECS_MMCTX_CTRL, 0)
-			and $r14 0x1f
-			bra e #mmctx_wait_free
-
-		// queue up an entry
-		ld b32 $r14 D[$r12]
-		or $r14 $r9
-		nv_iowr(NV_PGRAPH_FECS_MMCTX_QUEUE, 0, $r14)
-		add b32 $r12 4
-		cmpu b32 $r12 $r13
-		bra ne #mmctx_exec_loop
-
-	xbit $r11 $r10 2
-	bra ne #mmctx_stop
-		// wait for queue to empty
-		mmctx_fini_wait:
-			nv_iord($r11, NV_PGRAPH_FECS_MMCTX_CTRL, 0)
-			and $r11 0x1f
-			cmpu b32 $r11 0x10
-			bra ne #mmctx_fini_wait
-		mov $r10 5			// DONE_MMCTX
-		call(wait_donez)
-		bra #mmctx_done
-	mmctx_stop:
-		xbit $r11 $r10 0
-		shl b32 $r11 16			// DIR
-		bset $r11 12			// QLIMIT = 0x10
-		bset $r11 18			// STOP_TRIGGER
-		nv_iowr(NV_PGRAPH_FECS_MMCTX_CTRL, 0, $r11)
-		mmctx_stop_wait:
-			// wait for STOP_TRIGGER to clear
-			nv_iord($r11, NV_PGRAPH_FECS_MMCTX_CTRL, 0)
-			xbit $r11 $r11 18
-			bra ne #mmctx_stop_wait
-	mmctx_done:
-	trace_clr(T_MMCTX)
-	ret
-
-// Wait for DONE_STRAND
-//
-strand_wait:
-	push $r10
-	mov $r10 2
-	call(wait_donez)
-	pop $r10
-	ret
-
-// unknown - call before issuing strand commands
-//
-strand_pre:
-	mov $r9 NV_PGRAPH_FECS_STRAND_CMD_ENABLE
-	nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r9)
-	call(strand_wait)
-	ret
-
-// unknown - call after issuing strand commands
-//
-strand_post:
-	mov $r9 NV_PGRAPH_FECS_STRAND_CMD_DISABLE
-	nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r9)
-	call(strand_wait)
-	ret
-
-// Selects strand set?!
-//
-// In: $r14 id
-//
-strand_set:
-	mov $r12 0xf
-	nv_iowr(NV_PGRAPH_FECS_STRAND_FILTER, 0x3f, $r12)
-	mov $r12 NV_PGRAPH_FECS_STRAND_CMD_DEACTIVATE_FILTER
-	nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12)
-	nv_iowr(NV_PGRAPH_FECS_STRAND_FILTER, 0x3f, $r14)
-	mov $r12 NV_PGRAPH_FECS_STRAND_CMD_ACTIVATE_FILTER
-	nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12)
-	call(strand_wait)
-	ret
-
-// Initialise strand context data
-//
-// In : $r15 context base
-// Out: $r15 context size (in bytes)
-//
-// Strandset(?) 3 hardcoded currently
-//
-strand_ctx_init:
-	trace_set(T_STRINIT)
-	call(strand_pre)
-	mov $r14 3
-	call(strand_set)
-
-	clear b32 $r12
-	nv_iowr(NV_PGRAPH_FECS_STRAND_SELECT, 0x3f, $r12)
-	mov $r12 NV_PGRAPH_FECS_STRAND_CMD_SEEK
-	nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12)
-	call(strand_wait)
-	sub b32 $r12 $r0 1
-	nv_iowr(NV_PGRAPH_FECS_STRAND_DATA, 0x3f, $r12)
-	mov $r12 NV_PGRAPH_FECS_STRAND_CMD_GET_INFO
-	nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12)
-	call(strand_wait)
-	call(strand_post)
-
-	// read the size of each strand, poke the context offset of
-	// each into STRAND_{SAVE,LOAD}_SWBASE now, no need to worry
-	// about it later then.
-	nv_mkio($r8, NV_PGRAPH_FECS_STRAND_SAVE_SWBASE, 0x00)
-	nv_iord($r9, NV_PGRAPH_FECS_STRANDS_CNT, 0x00)
-	shr b32 $r14 $r15 8
-	ctx_init_strand_loop:
-		iowr I[$r8 + 0x000] $r14	// STRAND_SAVE_SWBASE
-		iowr I[$r8 + 0x100] $r14	// STRAND_LOAD_SWBASE
-		iord $r10 I[$r8 + 0x200]	// STRAND_SIZE
-		shr b32 $r10 6
-		add b32 $r10 1
-		add b32 $r14 $r10
-		add b32 $r8 4
-		sub b32 $r9 1
-		bra ne #ctx_init_strand_loop
-
-	shl b32 $r14 8
-	sub b32 $r15 $r14 $r15
-	trace_clr(T_STRINIT)
-	ret
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
deleted file mode 100644
index 7445f12b1d9e..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
+++ /dev/null
@@ -1,378 +0,0 @@
-/* fuc microcode for nvc0 PGRAPH/GPC
- *
- * Copyright 2011 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-/* TODO
- * - bracket certain functions with scratch writes, useful for debugging
- * - watchdog timer around ctx operations
- */
-
-#ifdef INCLUDE_DATA
-gpc_mmio_list_head:	.b32 #mmio_list_base
-gpc_mmio_list_tail:
-tpc_mmio_list_head:	.b32 #mmio_list_base
-tpc_mmio_list_tail:
-unk_mmio_list_head:	.b32 #mmio_list_base
-unk_mmio_list_tail:	.b32 #mmio_list_base
-
-gpc_id:			.b32 0
-
-tpc_count:		.b32 0
-tpc_mask:		.b32 0
-
-#if NV_PGRAPH_GPCX_UNK__SIZE > 0
-unk_count:		.b32 0
-unk_mask:		.b32 0
-#endif
-
-cmd_queue:		queue_init
-
-mmio_list_base:
-#endif
-
-#ifdef INCLUDE_CODE
-// reports an exception to the host
-//
-// In: $r15 error code (see os.h)
-//
-error:
-	push $r14
-	nv_wr32(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), $r15)
-	mov $r15 1
-	nv_wr32(NV_PGRAPH_FECS_INTR_UP_SET, $r15)
-	pop $r14
-	ret
-
-// GPC fuc initialisation, executed by triggering ucode start, will
-// fall through to main loop after completion.
-//
-// Input:
-//   CC_SCRATCH[1]: context base
-//
-// Output:
-//   CC_SCRATCH[0]:
-//	     31:31: set to signal completion
-//   CC_SCRATCH[1]:
-//	      31:0: GPC context size
-//
-init:
-	clear b32 $r0
-
-	// setup stack
-	nv_iord($r1, NV_PGRAPH_GPCX_GPCCS_CAPS, 0)
-	extr $r1 $r1 9:17
-	shl b32 $r1 8
-	mov $sp $r1
-
-	// enable fifo access
-	mov $r2 NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO
-	nv_iowr(NV_PGRAPH_GPCX_GPCCS_ACCESS, 0, $r2)
-
-	// setup i0 handler, and route all interrupts to it
-	mov $r1 #ih
-	mov $iv0 $r1
-	nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE, 0, $r0)
-
-	// enable fifo interrupt
-	mov $r2 NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO
-	nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET, 0, $r2)
-
-	// enable interrupts
-	bset $flags ie0
-
-	// figure out which GPC we are, and how many TPCs we have
-	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_UNITS, 0)
-	mov $r3 1
-	and $r2 0x1f
-	shl b32 $r3 $r2
-	sub b32 $r3 1
-	st b32 D[$r0 + #tpc_count] $r2
-	st b32 D[$r0 + #tpc_mask] $r3
-	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_MYINDEX, 0)
-	st b32 D[$r0 + #gpc_id] $r2
-
-#if NV_PGRAPH_GPCX_UNK__SIZE > 0
-	// figure out which, and how many, UNKs are actually present
-	imm32($r14, 0x500c30)
-	clear b32 $r2
-	clear b32 $r3
-	clear b32 $r4
-	init_unk_loop:
-		call(nv_rd32)
-		cmp b32 $r15 0
-		bra z #init_unk_next
-			mov $r15 1
-			shl b32 $r15 $r2
-			or $r4 $r15
-			add b32 $r3 1
-		init_unk_next:
-		add b32 $r2 1
-		add b32 $r14 4
-		cmp b32 $r2 NV_PGRAPH_GPCX_UNK__SIZE
-		bra ne #init_unk_loop
-	init_unk_done:
-	st b32 D[$r0 + #unk_count] $r3
-	st b32 D[$r0 + #unk_mask] $r4
-#endif
-
-	// initialise context base, and size tracking
-	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0)
-	clear b32 $r3		// track GPC context size here
-
-	// set mmctx base addresses now so we don't have to do it later,
-	// they don't currently ever change
-	shr b32 $r5 $r2 8
-	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE, 0, $r5)
-	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE, 0, $r5)
-
-	// calculate GPC mmio context size
-	ld b32 $r14 D[$r0 + #gpc_mmio_list_head]
-	ld b32 $r15 D[$r0 + #gpc_mmio_list_tail]
-	call(mmctx_size)
-	add b32 $r2 $r15
-	add b32 $r3 $r15
-
-	// calculate per-TPC mmio context size
-	ld b32 $r14 D[$r0 + #tpc_mmio_list_head]
-	ld b32 $r15 D[$r0 + #tpc_mmio_list_tail]
-	call(mmctx_size)
-	ld b32 $r14 D[$r0 + #tpc_count]
-	mulu $r14 $r15
-	add b32 $r2 $r14
-	add b32 $r3 $r14
-
-#if NV_PGRAPH_GPCX_UNK__SIZE > 0
-	// calculate per-UNK mmio context size
-	ld b32 $r14 D[$r0 + #unk_mmio_list_head]
-	ld b32 $r15 D[$r0 + #unk_mmio_list_tail]
-	call(mmctx_size)
-	ld b32 $r14 D[$r0 + #unk_count]
-	mulu $r14 $r15
-	add b32 $r2 $r14
-	add b32 $r3 $r14
-#endif
-
-	// round up base/size to 256 byte boundary (for strand SWBASE)
-	shr b32 $r3 2
-	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT, 0, $r3) // wtf for?!
-	shr b32 $r2 8
-	shr b32 $r3 6
-	add b32 $r2 1
-	add b32 $r3 1
-	shl b32 $r2 8
-	shl b32 $r3 8
-
-	// calculate size of strand context data
-	mov b32 $r15 $r2
-	call(strand_ctx_init)
-	add b32 $r3 $r15
-
-	// save context size, and tell HUB we're done
-	nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0, $r3)
-	clear b32 $r2
-	bset $r2 31
-	nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(0), 0, $r2)
-
-// Main program loop, very simple, sleeps until woken up by the interrupt
-// handler, pulls a command from the queue and executes its handler
-//
-main:
-	bset $flags $p0
-	sleep $p0
-	mov $r13 #cmd_queue
-	call(queue_get)
-	bra $p1 #main
-
-	// 0x0000-0x0003 are all context transfers
-	cmpu b32 $r14 0x04
-	bra nc #main_not_ctx_xfer
-		// fetch $flags and mask off $p1/$p2
-		mov $r1 $flags
-		mov $r2 0x0006
-		not b32 $r2
-		and $r1 $r2
-		// set $p1/$p2 according to transfer type
-		shl b32 $r14 1
-		or $r1 $r14
-		mov $flags $r1
-		// transfer context data
-		call(ctx_xfer)
-		bra #main
-
-	main_not_ctx_xfer:
-	shl b32 $r15 $r14 16
-	or $r15 E_BAD_COMMAND
-	call(error)
-	bra #main
-
-// interrupt handler
-ih:
-	push $r8
-	mov $r8 $flags
-	push $r8
-	push $r9
-	push $r10
-	push $r11
-	push $r13
-	push $r14
-	push $r15
-	clear b32 $r0
-
-	// incoming fifo command?
-	nv_iord($r10, NV_PGRAPH_GPCX_GPCCS_INTR, 0)
-	and $r11 $r10 NV_PGRAPH_GPCX_GPCCS_INTR_FIFO
-	bra e #ih_no_fifo
-		// queue incoming fifo command for later processing
-		mov $r13 #cmd_queue
-		nv_iord($r14, NV_PGRAPH_GPCX_GPCCS_FIFO_CMD, 0)
-		nv_iord($r15, NV_PGRAPH_GPCX_GPCCS_FIFO_DATA, 0)
-		call(queue_put)
-		mov $r14 1
-		nv_iowr(NV_PGRAPH_GPCX_GPCCS_FIFO_ACK, 0, $r14)
-
-	// ack, and wake up main()
-	ih_no_fifo:
-	nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ACK, 0, $r10)
-
-	pop $r15
-	pop $r14
-	pop $r13
-	pop $r11
-	pop $r10
-	pop $r9
-	pop $r8
-	mov $flags $r8
-	pop $r8
-	bclr $flags $p0
-	iret
-
-// Set this GPC's bit in HUB_BAR, used to signal completion of various
-// activities to the HUB fuc
-//
-hub_barrier_done:
-	mov $r15 1
-	ld b32 $r14 D[$r0 + #gpc_id]
-	shl b32 $r15 $r14
-	nv_wr32(0x409418, $r15)	// 0x409418 - HUB_BAR_SET
-	ret
-
-// Disables various things, waits a bit, and re-enables them..
-//
-// Not sure how exactly this helps, perhaps "ENABLE" is not such a
-// good description for the bits we turn off?  Anyways, without this,
-// funny things happen.
-//
-ctx_redswitch:
-	mov $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER
-	nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15)
-	mov $r14 8
-	ctx_redswitch_delay:
-		sub b32 $r14 1
-		bra ne #ctx_redswitch_delay
-	or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11
-	or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE
-	nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15)
-	ret
-
-// Transfer GPC context data between GPU and storage area
-//
-// In: $r15 context base address
-//     $p1 clear on save, set on load
-//     $p2 set if opposite direction done/will be done, so:
-//		on save it means: "a load will follow this save"
-//		on load it means: "a save preceeded this load"
-//
-ctx_xfer:
-	// set context base address
-	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MEM_BASE, 0, $r15)
-	bra not $p1 #ctx_xfer_not_load
-		call(ctx_redswitch)
-	ctx_xfer_not_load:
-
-	// strands
-	call(strand_pre)
-	clear b32 $r2
-	nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT, 0x3f, $r2)
-	xbit $r2 $flags $p1	// SAVE/LOAD
-	add b32 $r2 NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE
-	nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_CMD, 0x3f, $r2)
-
-	// mmio context
-	xbit $r10 $flags $p1	// direction
-	or $r10 2		// first
-	imm32($r11,0x500000)
-	ld b32 $r12 D[$r0 + #gpc_id]
-	shl b32 $r12 15
-	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn
-	ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
-	ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
-	mov $r14 0		// not multi
-	call(mmctx_xfer)
-
-	// per-TPC mmio context
-	xbit $r10 $flags $p1	// direction
-#if !NV_PGRAPH_GPCX_UNK__SIZE
-	or $r10 4		// last
-#endif
-	imm32($r11, 0x504000)
-	ld b32 $r12 D[$r0 + #gpc_id]
-	shl b32 $r12 15
-	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn_TPC0
-	ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
-	ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
-	ld b32 $r15 D[$r0 + #tpc_mask]
-	mov $r14 0x800		// stride = 0x800
-	call(mmctx_xfer)
-
-#if NV_PGRAPH_GPCX_UNK__SIZE > 0
-	// per-UNK mmio context
-	xbit $r10 $flags $p1	// direction
-	or $r10 4		// last
-	imm32($r11, 0x503000)
-	ld b32 $r12 D[$r0 + #gpc_id]
-	shl b32 $r12 15
-	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn_UNK0
-	ld b32 $r12 D[$r0 + #unk_mmio_list_head]
-	ld b32 $r13 D[$r0 + #unk_mmio_list_tail]
-	ld b32 $r15 D[$r0 + #unk_mask]
-	mov $r14 0x200		// stride = 0x200
-	call(mmctx_xfer)
-#endif
-
-	// wait for strands to finish
-	call(strand_wait)
-
-	// if load, or a save without a load following, do some
-	// unknown stuff that's done after finishing a block of
-	// strand commands
-	bra $p1 #ctx_xfer_post
-	bra not $p2 #ctx_xfer_done
-	ctx_xfer_post:
-		call(strand_post)
-
-	// mark completion in HUB's barrier
-	ctx_xfer_done:
-	call(hub_barrier_done)
-	ret
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5 b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5
deleted file mode 100644
index e730603891d7..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#define NV_PGRAPH_GPCX_UNK__SIZE                                     0x00000002
-
-#define CHIPSET GK208
-#include "macros.fuc"
-
-.section #gm107_grgpc_data
-#define INCLUDE_DATA
-#include "com.fuc"
-#include "gpc.fuc"
-#undef INCLUDE_DATA
-
-.section #gm107_grgpc_code
-#define INCLUDE_CODE
-bra #init
-#include "com.fuc"
-#include "gpc.fuc"
-.align 256
-#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5.h
deleted file mode 100644
index 6d53b67dd3c4..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5.h
+++ /dev/null
@@ -1,473 +0,0 @@
-uint32_t gm107_grgpc_data[] = {
-/* 0x0000: gpc_mmio_list_head */
-	0x0000006c,
-/* 0x0004: gpc_mmio_list_tail */
-/* 0x0004: tpc_mmio_list_head */
-	0x0000006c,
-/* 0x0008: tpc_mmio_list_tail */
-/* 0x0008: unk_mmio_list_head */
-	0x0000006c,
-/* 0x000c: unk_mmio_list_tail */
-	0x0000006c,
-/* 0x0010: gpc_id */
-	0x00000000,
-/* 0x0014: tpc_count */
-	0x00000000,
-/* 0x0018: tpc_mask */
-	0x00000000,
-/* 0x001c: unk_count */
-	0x00000000,
-/* 0x0020: unk_mask */
-	0x00000000,
-/* 0x0024: cmd_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-uint32_t gm107_grgpc_code[] = {
-	0x03140ef5,
-/* 0x0004: queue_put */
-	0x9800d898,
-	0x86f001d9,
-	0xf489a408,
-	0x020f0b1b,
-	0x0002f87e,
-/* 0x001a: queue_put_next */
-	0x98c400f8,
-	0x0384b607,
-	0xb6008dbb,
-	0x8eb50880,
-	0x018fb500,
-	0xf00190b6,
-	0xd9b50f94,
-/* 0x0037: queue_get */
-	0xf400f801,
-	0xd8980131,
-	0x01d99800,
-	0x0bf489a4,
-	0x0789c421,
-	0xbb0394b6,
-	0x90b6009d,
-	0x009e9808,
-	0xb6019f98,
-	0x84f00180,
-	0x00d8b50f,
-/* 0x0063: queue_get_done */
-	0xf80132f4,
-/* 0x0065: nv_rd32 */
-	0xf0ecb200,
-	0x00801fc9,
-	0x0cf601ca,
-/* 0x0073: nv_rd32_wait */
-	0x8c04bd00,
-	0xcf01ca00,
-	0xccc800cc,
-	0xf61bf41f,
-	0xec7e060a,
-	0x008f0000,
-	0xffcf01cb,
-/* 0x008f: nv_wr32 */
-	0x8000f800,
-	0xf601cc00,
-	0x04bd000f,
-	0xc9f0ecb2,
-	0x1ec9f01f,
-	0x01ca0080,
-	0xbd000cf6,
-/* 0x00a9: nv_wr32_wait */
-	0xca008c04,
-	0x00cccf01,
-	0xf41fccc8,
-	0x00f8f61b,
-/* 0x00b8: wait_donez */
-	0x99f094bd,
-	0x37008000,
-	0x0009f602,
-	0x008004bd,
-	0x0af60206,
-/* 0x00cf: wait_donez_ne */
-	0x8804bd00,
-	0xcf010000,
-	0x8aff0088,
-	0xf61bf488,
-	0x99f094bd,
-	0x17008000,
-	0x0009f602,
-	0x00f804bd,
-/* 0x00ec: wait_doneo */
-	0x99f094bd,
-	0x37008000,
-	0x0009f602,
-	0x008004bd,
-	0x0af60206,
-/* 0x0103: wait_doneo_e */
-	0x8804bd00,
-	0xcf010000,
-	0x8aff0088,
-	0xf60bf488,
-	0x99f094bd,
-	0x17008000,
-	0x0009f602,
-	0x00f804bd,
-/* 0x0120: mmctx_size */
-/* 0x0122: nv_mmctx_size_loop */
-	0xe89894bd,
-	0x1a85b600,
-	0xb60180b6,
-	0x98bb0284,
-	0x04e0b600,
-	0x1bf4efa4,
-	0xf89fb2ec,
-/* 0x013d: mmctx_xfer */
-	0xf094bd00,
-	0x00800199,
-	0x09f60237,
-	0xbd04bd00,
-	0x05bbfd94,
-	0x800f0bf4,
-	0xf601c400,
-	0x04bd000b,
-/* 0x015f: mmctx_base_disabled */
-	0xfd0099f0,
-	0x0bf405ee,
-	0xc6008018,
-	0x000ef601,
-	0x008004bd,
-	0x0ff601c7,
-	0xf004bd00,
-/* 0x017a: mmctx_multi_disabled */
-	0xabc80199,
-	0x10b4b600,
-	0xc80cb9f0,
-	0xe4b601ae,
-	0x05befd11,
-	0x01c50080,
-	0xbd000bf6,
-/* 0x0195: mmctx_exec_loop */
-/* 0x0195: mmctx_wait_free */
-	0xc5008e04,
-	0x00eecf01,
-	0xf41fe4f0,
-	0xce98f60b,
-	0x05e9fd00,
-	0x01c80080,
-	0xbd000ef6,
-	0x04c0b604,
-	0x1bf4cda4,
-	0x02abc8df,
-/* 0x01bf: mmctx_fini_wait */
-	0x8b1c1bf4,
-	0xcf01c500,
-	0xb4f000bb,
-	0x10b4b01f,
-	0x0af31bf4,
-	0x00b87e05,
-	0x250ef400,
-/* 0x01d8: mmctx_stop */
-	0xb600abc8,
-	0xb9f010b4,
-	0x12b9f00c,
-	0x01c50080,
-	0xbd000bf6,
-/* 0x01ed: mmctx_stop_wait */
-	0xc5008b04,
-	0x00bbcf01,
-	0xf412bbc8,
-/* 0x01fa: mmctx_done */
-	0x94bdf61b,
-	0x800199f0,
-	0xf6021700,
-	0x04bd0009,
-/* 0x020a: strand_wait */
-	0xa0f900f8,
-	0xb87e020a,
-	0xa0fc0000,
-/* 0x0216: strand_pre */
-	0x0c0900f8,
-	0x024afc80,
-	0xbd0009f6,
-	0x020a7e04,
-/* 0x0227: strand_post */
-	0x0900f800,
-	0x4afc800d,
-	0x0009f602,
-	0x0a7e04bd,
-	0x00f80002,
-/* 0x0238: strand_set */
-	0xfc800f0c,
-	0x0cf6024f,
-	0x0c04bd00,
-	0x4afc800b,
-	0x000cf602,
-	0xfc8004bd,
-	0x0ef6024f,
-	0x0c04bd00,
-	0x4afc800a,
-	0x000cf602,
-	0x0a7e04bd,
-	0x00f80002,
-/* 0x0268: strand_ctx_init */
-	0x99f094bd,
-	0x37008003,
-	0x0009f602,
-	0x167e04bd,
-	0x030e0002,
-	0x0002387e,
-	0xfc80c4bd,
-	0x0cf60247,
-	0x0c04bd00,
-	0x4afc8001,
-	0x000cf602,
-	0x0a7e04bd,
-	0x0c920002,
-	0x46fc8001,
-	0x000cf602,
-	0x020c04bd,
-	0x024afc80,
-	0xbd000cf6,
-	0x020a7e04,
-	0x02277e00,
-	0x42008800,
-	0x20008902,
-	0x0099cf02,
-/* 0x02c7: ctx_init_strand_loop */
-	0xf608fe95,
-	0x8ef6008e,
-	0x808acf40,
-	0xb606a5b6,
-	0xeabb01a0,
-	0x0480b600,
-	0xf40192b6,
-	0xe4b6e81b,
-	0xf2efbc08,
-	0x99f094bd,
-	0x17008003,
-	0x0009f602,
-	0x00f804bd,
-/* 0x02f8: error */
-	0xffb2e0f9,
-	0x4098148e,
-	0x00008f7e,
-	0xffb2010f,
-	0x409c1c8e,
-	0x00008f7e,
-	0x00f8e0fc,
-/* 0x0314: init */
-	0x004104bd,
-	0x0011cf42,
-	0x010911e7,
-	0xfe0814b6,
-	0x02020014,
-	0xf6120040,
-	0x04bd0002,
-	0xfe047241,
-	0x00400010,
-	0x0000f607,
-	0x040204bd,
-	0xf6040040,
-	0x04bd0002,
-	0x821031f4,
-	0xcf018200,
-	0x01030022,
-	0xbb1f24f0,
-	0x32b60432,
-	0x0502b501,
-	0x820603b5,
-	0xcf018600,
-	0x02b50022,
-	0x0c308e04,
-	0xbd24bd50,
-/* 0x0377: init_unk_loop */
-	0x7e44bd34,
-	0xb0000065,
-	0x0bf400f6,
-	0xbb010f0e,
-	0x4ffd04f2,
-	0x0130b605,
-/* 0x038c: init_unk_next */
-	0xb60120b6,
-	0x26b004e0,
-	0xe21bf402,
-/* 0x0398: init_unk_done */
-	0xb50703b5,
-	0x00820804,
-	0x22cf0201,
-	0x9534bd00,
-	0x00800825,
-	0x05f601c0,
-	0x8004bd00,
-	0xf601c100,
-	0x04bd0005,
-	0x98000e98,
-	0x207e010f,
-	0x2fbb0001,
-	0x003fbb00,
-	0x98010e98,
-	0x207e020f,
-	0x0e980001,
-	0x00effd05,
-	0xbb002ebb,
-	0x0e98003e,
-	0x030f9802,
-	0x0001207e,
-	0xfd070e98,
-	0x2ebb00ef,
-	0x003ebb00,
-	0x800235b6,
-	0xf601d300,
-	0x04bd0003,
-	0xb60825b6,
-	0x20b60635,
-	0x0130b601,
-	0xb60824b6,
-	0x2fb20834,
-	0x0002687e,
-	0x80003fbb,
-	0xf6020100,
-	0x04bd0003,
-	0x29f024bd,
-	0x3000801f,
-	0x0002f602,
-/* 0x0436: main */
-	0x31f404bd,
-	0x0028f400,
-	0x377e240d,
-	0x01f40000,
-	0x04e4b0f4,
-	0xfe1d18f4,
-	0x06020181,
-	0x12fd20bd,
-	0x01e4b604,
-	0xfe051efd,
-	0x097e0018,
-	0x0ef40005,
-/* 0x0465: main_not_ctx_xfer */
-	0x10ef94d4,
-	0x7e01f5f0,
-	0xf40002f8,
-/* 0x0472: ih */
-	0x80f9c70e,
-	0xf90188fe,
-	0xf990f980,
-	0xf9b0f9a0,
-	0xf9e0f9d0,
-	0x4a04bdf0,
-	0xaacf0200,
-	0x04abc400,
-	0x0d1f0bf4,
-	0x1a004e24,
-	0x4f00eecf,
-	0xffcf1900,
-	0x00047e00,
-	0x40010e00,
-	0x0ef61d00,
-/* 0x04af: ih_no_fifo */
-	0x4004bd00,
-	0x0af60100,
-	0xfc04bd00,
-	0xfce0fcf0,
-	0xfcb0fcd0,
-	0xfc90fca0,
-	0x0088fe80,
-	0x32f480fc,
-/* 0x04cf: hub_barrier_done */
-	0x0f01f800,
-	0x040e9801,
-	0xb204febb,
-	0x94188eff,
-	0x008f7e40,
-/* 0x04e3: ctx_redswitch */
-	0x0f00f800,
-	0x85008020,
-	0x000ff601,
-	0x080e04bd,
-/* 0x04f0: ctx_redswitch_delay */
-	0xf401e2b6,
-	0xf5f1fd1b,
-	0xf5f10800,
-	0x00800200,
-	0x0ff60185,
-	0xf804bd00,
-/* 0x0509: ctx_xfer */
-	0x81008000,
-	0x000ff602,
-	0x11f404bd,
-	0x04e37e07,
-/* 0x0519: ctx_xfer_not_load */
-	0x02167e00,
-	0x8024bd00,
-	0xf60247fc,
-	0x04bd0002,
-	0xb6012cf0,
-	0xfc800320,
-	0x02f6024a,
-	0xf004bd00,
-	0xa5f001ac,
-	0x00008b02,
-	0x040c9850,
-	0xbb0fc4b6,
-	0x0c9800bc,
-	0x010d9800,
-	0x3d7e000e,
-	0xacf00001,
-	0x40008b01,
-	0x040c9850,
-	0xbb0fc4b6,
-	0x0c9800bc,
-	0x020d9801,
-	0x4e060f98,
-	0x3d7e0800,
-	0xacf00001,
-	0x04a5f001,
-	0x5030008b,
-	0xb6040c98,
-	0xbcbb0fc4,
-	0x020c9800,
-	0x98030d98,
-	0x004e080f,
-	0x013d7e02,
-	0x020a7e00,
-	0x0601f400,
-/* 0x05a3: ctx_xfer_post */
-	0x7e0712f4,
-/* 0x05a7: ctx_xfer_done */
-	0x7e000227,
-	0xf80004cf,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5 b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5
deleted file mode 100644
index bd30262d635b..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#define NV_PGRAPH_GPCX_UNK__SIZE                                     0x00000001
-
-#define CHIPSET GK208
-#include "macros.fuc"
-
-.section #nv108_grgpc_data
-#define INCLUDE_DATA
-#include "com.fuc"
-#include "gpc.fuc"
-#undef INCLUDE_DATA
-
-.section #nv108_grgpc_code
-#define INCLUDE_CODE
-bra #init
-#include "com.fuc"
-#include "gpc.fuc"
-.align 256
-#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5.h
deleted file mode 100644
index 31922707794f..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5.h
+++ /dev/null
@@ -1,473 +0,0 @@
-uint32_t nv108_grgpc_data[] = {
-/* 0x0000: gpc_mmio_list_head */
-	0x0000006c,
-/* 0x0004: gpc_mmio_list_tail */
-/* 0x0004: tpc_mmio_list_head */
-	0x0000006c,
-/* 0x0008: tpc_mmio_list_tail */
-/* 0x0008: unk_mmio_list_head */
-	0x0000006c,
-/* 0x000c: unk_mmio_list_tail */
-	0x0000006c,
-/* 0x0010: gpc_id */
-	0x00000000,
-/* 0x0014: tpc_count */
-	0x00000000,
-/* 0x0018: tpc_mask */
-	0x00000000,
-/* 0x001c: unk_count */
-	0x00000000,
-/* 0x0020: unk_mask */
-	0x00000000,
-/* 0x0024: cmd_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-uint32_t nv108_grgpc_code[] = {
-	0x03140ef5,
-/* 0x0004: queue_put */
-	0x9800d898,
-	0x86f001d9,
-	0xf489a408,
-	0x020f0b1b,
-	0x0002f87e,
-/* 0x001a: queue_put_next */
-	0x98c400f8,
-	0x0384b607,
-	0xb6008dbb,
-	0x8eb50880,
-	0x018fb500,
-	0xf00190b6,
-	0xd9b50f94,
-/* 0x0037: queue_get */
-	0xf400f801,
-	0xd8980131,
-	0x01d99800,
-	0x0bf489a4,
-	0x0789c421,
-	0xbb0394b6,
-	0x90b6009d,
-	0x009e9808,
-	0xb6019f98,
-	0x84f00180,
-	0x00d8b50f,
-/* 0x0063: queue_get_done */
-	0xf80132f4,
-/* 0x0065: nv_rd32 */
-	0xf0ecb200,
-	0x00801fc9,
-	0x0cf601ca,
-/* 0x0073: nv_rd32_wait */
-	0x8c04bd00,
-	0xcf01ca00,
-	0xccc800cc,
-	0xf61bf41f,
-	0xec7e060a,
-	0x008f0000,
-	0xffcf01cb,
-/* 0x008f: nv_wr32 */
-	0x8000f800,
-	0xf601cc00,
-	0x04bd000f,
-	0xc9f0ecb2,
-	0x1ec9f01f,
-	0x01ca0080,
-	0xbd000cf6,
-/* 0x00a9: nv_wr32_wait */
-	0xca008c04,
-	0x00cccf01,
-	0xf41fccc8,
-	0x00f8f61b,
-/* 0x00b8: wait_donez */
-	0x99f094bd,
-	0x37008000,
-	0x0009f602,
-	0x008004bd,
-	0x0af60206,
-/* 0x00cf: wait_donez_ne */
-	0x8804bd00,
-	0xcf010000,
-	0x8aff0088,
-	0xf61bf488,
-	0x99f094bd,
-	0x17008000,
-	0x0009f602,
-	0x00f804bd,
-/* 0x00ec: wait_doneo */
-	0x99f094bd,
-	0x37008000,
-	0x0009f602,
-	0x008004bd,
-	0x0af60206,
-/* 0x0103: wait_doneo_e */
-	0x8804bd00,
-	0xcf010000,
-	0x8aff0088,
-	0xf60bf488,
-	0x99f094bd,
-	0x17008000,
-	0x0009f602,
-	0x00f804bd,
-/* 0x0120: mmctx_size */
-/* 0x0122: nv_mmctx_size_loop */
-	0xe89894bd,
-	0x1a85b600,
-	0xb60180b6,
-	0x98bb0284,
-	0x04e0b600,
-	0x1bf4efa4,
-	0xf89fb2ec,
-/* 0x013d: mmctx_xfer */
-	0xf094bd00,
-	0x00800199,
-	0x09f60237,
-	0xbd04bd00,
-	0x05bbfd94,
-	0x800f0bf4,
-	0xf601c400,
-	0x04bd000b,
-/* 0x015f: mmctx_base_disabled */
-	0xfd0099f0,
-	0x0bf405ee,
-	0xc6008018,
-	0x000ef601,
-	0x008004bd,
-	0x0ff601c7,
-	0xf004bd00,
-/* 0x017a: mmctx_multi_disabled */
-	0xabc80199,
-	0x10b4b600,
-	0xc80cb9f0,
-	0xe4b601ae,
-	0x05befd11,
-	0x01c50080,
-	0xbd000bf6,
-/* 0x0195: mmctx_exec_loop */
-/* 0x0195: mmctx_wait_free */
-	0xc5008e04,
-	0x00eecf01,
-	0xf41fe4f0,
-	0xce98f60b,
-	0x05e9fd00,
-	0x01c80080,
-	0xbd000ef6,
-	0x04c0b604,
-	0x1bf4cda4,
-	0x02abc8df,
-/* 0x01bf: mmctx_fini_wait */
-	0x8b1c1bf4,
-	0xcf01c500,
-	0xb4f000bb,
-	0x10b4b01f,
-	0x0af31bf4,
-	0x00b87e05,
-	0x250ef400,
-/* 0x01d8: mmctx_stop */
-	0xb600abc8,
-	0xb9f010b4,
-	0x12b9f00c,
-	0x01c50080,
-	0xbd000bf6,
-/* 0x01ed: mmctx_stop_wait */
-	0xc5008b04,
-	0x00bbcf01,
-	0xf412bbc8,
-/* 0x01fa: mmctx_done */
-	0x94bdf61b,
-	0x800199f0,
-	0xf6021700,
-	0x04bd0009,
-/* 0x020a: strand_wait */
-	0xa0f900f8,
-	0xb87e020a,
-	0xa0fc0000,
-/* 0x0216: strand_pre */
-	0x0c0900f8,
-	0x024afc80,
-	0xbd0009f6,
-	0x020a7e04,
-/* 0x0227: strand_post */
-	0x0900f800,
-	0x4afc800d,
-	0x0009f602,
-	0x0a7e04bd,
-	0x00f80002,
-/* 0x0238: strand_set */
-	0xfc800f0c,
-	0x0cf6024f,
-	0x0c04bd00,
-	0x4afc800b,
-	0x000cf602,
-	0xfc8004bd,
-	0x0ef6024f,
-	0x0c04bd00,
-	0x4afc800a,
-	0x000cf602,
-	0x0a7e04bd,
-	0x00f80002,
-/* 0x0268: strand_ctx_init */
-	0x99f094bd,
-	0x37008003,
-	0x0009f602,
-	0x167e04bd,
-	0x030e0002,
-	0x0002387e,
-	0xfc80c4bd,
-	0x0cf60247,
-	0x0c04bd00,
-	0x4afc8001,
-	0x000cf602,
-	0x0a7e04bd,
-	0x0c920002,
-	0x46fc8001,
-	0x000cf602,
-	0x020c04bd,
-	0x024afc80,
-	0xbd000cf6,
-	0x020a7e04,
-	0x02277e00,
-	0x42008800,
-	0x20008902,
-	0x0099cf02,
-/* 0x02c7: ctx_init_strand_loop */
-	0xf608fe95,
-	0x8ef6008e,
-	0x808acf40,
-	0xb606a5b6,
-	0xeabb01a0,
-	0x0480b600,
-	0xf40192b6,
-	0xe4b6e81b,
-	0xf2efbc08,
-	0x99f094bd,
-	0x17008003,
-	0x0009f602,
-	0x00f804bd,
-/* 0x02f8: error */
-	0xffb2e0f9,
-	0x4098148e,
-	0x00008f7e,
-	0xffb2010f,
-	0x409c1c8e,
-	0x00008f7e,
-	0x00f8e0fc,
-/* 0x0314: init */
-	0x004104bd,
-	0x0011cf42,
-	0x010911e7,
-	0xfe0814b6,
-	0x02020014,
-	0xf6120040,
-	0x04bd0002,
-	0xfe047241,
-	0x00400010,
-	0x0000f607,
-	0x040204bd,
-	0xf6040040,
-	0x04bd0002,
-	0x821031f4,
-	0xcf018200,
-	0x01030022,
-	0xbb1f24f0,
-	0x32b60432,
-	0x0502b501,
-	0x820603b5,
-	0xcf018600,
-	0x02b50022,
-	0x0c308e04,
-	0xbd24bd50,
-/* 0x0377: init_unk_loop */
-	0x7e44bd34,
-	0xb0000065,
-	0x0bf400f6,
-	0xbb010f0e,
-	0x4ffd04f2,
-	0x0130b605,
-/* 0x038c: init_unk_next */
-	0xb60120b6,
-	0x26b004e0,
-	0xe21bf401,
-/* 0x0398: init_unk_done */
-	0xb50703b5,
-	0x00820804,
-	0x22cf0201,
-	0x9534bd00,
-	0x00800825,
-	0x05f601c0,
-	0x8004bd00,
-	0xf601c100,
-	0x04bd0005,
-	0x98000e98,
-	0x207e010f,
-	0x2fbb0001,
-	0x003fbb00,
-	0x98010e98,
-	0x207e020f,
-	0x0e980001,
-	0x00effd05,
-	0xbb002ebb,
-	0x0e98003e,
-	0x030f9802,
-	0x0001207e,
-	0xfd070e98,
-	0x2ebb00ef,
-	0x003ebb00,
-	0x800235b6,
-	0xf601d300,
-	0x04bd0003,
-	0xb60825b6,
-	0x20b60635,
-	0x0130b601,
-	0xb60824b6,
-	0x2fb20834,
-	0x0002687e,
-	0x80003fbb,
-	0xf6020100,
-	0x04bd0003,
-	0x29f024bd,
-	0x3000801f,
-	0x0002f602,
-/* 0x0436: main */
-	0x31f404bd,
-	0x0028f400,
-	0x377e240d,
-	0x01f40000,
-	0x04e4b0f4,
-	0xfe1d18f4,
-	0x06020181,
-	0x12fd20bd,
-	0x01e4b604,
-	0xfe051efd,
-	0x097e0018,
-	0x0ef40005,
-/* 0x0465: main_not_ctx_xfer */
-	0x10ef94d4,
-	0x7e01f5f0,
-	0xf40002f8,
-/* 0x0472: ih */
-	0x80f9c70e,
-	0xf90188fe,
-	0xf990f980,
-	0xf9b0f9a0,
-	0xf9e0f9d0,
-	0x4a04bdf0,
-	0xaacf0200,
-	0x04abc400,
-	0x0d1f0bf4,
-	0x1a004e24,
-	0x4f00eecf,
-	0xffcf1900,
-	0x00047e00,
-	0x40010e00,
-	0x0ef61d00,
-/* 0x04af: ih_no_fifo */
-	0x4004bd00,
-	0x0af60100,
-	0xfc04bd00,
-	0xfce0fcf0,
-	0xfcb0fcd0,
-	0xfc90fca0,
-	0x0088fe80,
-	0x32f480fc,
-/* 0x04cf: hub_barrier_done */
-	0x0f01f800,
-	0x040e9801,
-	0xb204febb,
-	0x94188eff,
-	0x008f7e40,
-/* 0x04e3: ctx_redswitch */
-	0x0f00f800,
-	0x85008020,
-	0x000ff601,
-	0x080e04bd,
-/* 0x04f0: ctx_redswitch_delay */
-	0xf401e2b6,
-	0xf5f1fd1b,
-	0xf5f10800,
-	0x00800200,
-	0x0ff60185,
-	0xf804bd00,
-/* 0x0509: ctx_xfer */
-	0x81008000,
-	0x000ff602,
-	0x11f404bd,
-	0x04e37e07,
-/* 0x0519: ctx_xfer_not_load */
-	0x02167e00,
-	0x8024bd00,
-	0xf60247fc,
-	0x04bd0002,
-	0xb6012cf0,
-	0xfc800320,
-	0x02f6024a,
-	0xf004bd00,
-	0xa5f001ac,
-	0x00008b02,
-	0x040c9850,
-	0xbb0fc4b6,
-	0x0c9800bc,
-	0x010d9800,
-	0x3d7e000e,
-	0xacf00001,
-	0x40008b01,
-	0x040c9850,
-	0xbb0fc4b6,
-	0x0c9800bc,
-	0x020d9801,
-	0x4e060f98,
-	0x3d7e0800,
-	0xacf00001,
-	0x04a5f001,
-	0x5030008b,
-	0xb6040c98,
-	0xbcbb0fc4,
-	0x020c9800,
-	0x98030d98,
-	0x004e080f,
-	0x013d7e02,
-	0x020a7e00,
-	0x0601f400,
-/* 0x05a3: ctx_xfer_post */
-	0x7e0712f4,
-/* 0x05a7: ctx_xfer_done */
-	0x7e000227,
-	0xf80004cf,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
deleted file mode 100644
index 5ae06a2d64c9..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#define NV_PGRAPH_GPCX_UNK__SIZE                                     0x00000000
-
-#define CHIPSET GF100
-#include "macros.fuc"
-
-.section #nvc0_grgpc_data
-#define INCLUDE_DATA
-#include "com.fuc"
-#include "gpc.fuc"
-#undef INCLUDE_DATA
-
-.section #nvc0_grgpc_code
-#define INCLUDE_CODE
-bra #init
-#include "com.fuc"
-#include "gpc.fuc"
-.align 256
-#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
deleted file mode 100644
index 325cc7b7b2fb..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
+++ /dev/null
@@ -1,530 +0,0 @@
-uint32_t nvc0_grgpc_data[] = {
-/* 0x0000: gpc_mmio_list_head */
-	0x00000064,
-/* 0x0004: gpc_mmio_list_tail */
-/* 0x0004: tpc_mmio_list_head */
-	0x00000064,
-/* 0x0008: tpc_mmio_list_tail */
-/* 0x0008: unk_mmio_list_head */
-	0x00000064,
-/* 0x000c: unk_mmio_list_tail */
-	0x00000064,
-/* 0x0010: gpc_id */
-	0x00000000,
-/* 0x0014: tpc_count */
-	0x00000000,
-/* 0x0018: tpc_mask */
-	0x00000000,
-/* 0x001c: cmd_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-uint32_t nvc0_grgpc_code[] = {
-	0x03a10ef5,
-/* 0x0004: queue_put */
-	0x9800d898,
-	0x86f001d9,
-	0x0489b808,
-	0xf00c1bf4,
-	0x21f502f7,
-	0x00f8037e,
-/* 0x001c: queue_put_next */
-	0xb60798c4,
-	0x8dbb0384,
-	0x0880b600,
-	0x80008e80,
-	0x90b6018f,
-	0x0f94f001,
-	0xf801d980,
-/* 0x0039: queue_get */
-	0x0131f400,
-	0x9800d898,
-	0x89b801d9,
-	0x210bf404,
-	0xb60789c4,
-	0x9dbb0394,
-	0x0890b600,
-	0x98009e98,
-	0x80b6019f,
-	0x0f84f001,
-	0xf400d880,
-/* 0x0066: queue_get_done */
-	0x00f80132,
-/* 0x0068: nv_rd32 */
-	0xf002ecb9,
-	0x07f11fc9,
-	0x03f0ca00,
-	0x000cd001,
-/* 0x007a: nv_rd32_wait */
-	0xc7f104bd,
-	0xc3f0ca00,
-	0x00cccf01,
-	0xf41fccc8,
-	0xa7f0f31b,
-	0x1021f506,
-	0x00f7f101,
-	0x01f3f0cb,
-	0xf800ffcf,
-/* 0x009d: nv_wr32 */
-	0x0007f100,
-	0x0103f0cc,
-	0xbd000fd0,
-	0x02ecb904,
-	0xf01fc9f0,
-	0x07f11ec9,
-	0x03f0ca00,
-	0x000cd001,
-/* 0x00be: nv_wr32_wait */
-	0xc7f104bd,
-	0xc3f0ca00,
-	0x00cccf01,
-	0xf41fccc8,
-	0x00f8f31b,
-/* 0x00d0: wait_donez */
-	0x99f094bd,
-	0x0007f100,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f006,
-	0xbd000ad0,
-/* 0x00ed: wait_donez_ne */
-	0x0087f104,
-	0x0183f000,
-	0xff0088cf,
-	0x1bf4888a,
-	0xf094bdf3,
-	0x07f10099,
-	0x03f01700,
-	0x0009d002,
-	0x00f804bd,
-/* 0x0110: wait_doneo */
-	0x99f094bd,
-	0x0007f100,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f006,
-	0xbd000ad0,
-/* 0x012d: wait_doneo_e */
-	0x0087f104,
-	0x0183f000,
-	0xff0088cf,
-	0x0bf4888a,
-	0xf094bdf3,
-	0x07f10099,
-	0x03f01700,
-	0x0009d002,
-	0x00f804bd,
-/* 0x0150: mmctx_size */
-/* 0x0152: nv_mmctx_size_loop */
-	0xe89894bd,
-	0x1a85b600,
-	0xb60180b6,
-	0x98bb0284,
-	0x04e0b600,
-	0xf404efb8,
-	0x9fb9eb1b,
-/* 0x016f: mmctx_xfer */
-	0xbd00f802,
-	0x0199f094,
-	0x0f0007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0xbbfd94bd,
-	0x120bf405,
-	0xc40007f1,
-	0xd00103f0,
-	0x04bd000b,
-/* 0x0197: mmctx_base_disabled */
-	0xfd0099f0,
-	0x0bf405ee,
-	0x0007f11e,
-	0x0103f0c6,
-	0xbd000ed0,
-	0x0007f104,
-	0x0103f0c7,
-	0xbd000fd0,
-	0x0199f004,
-/* 0x01b8: mmctx_multi_disabled */
-	0xb600abc8,
-	0xb9f010b4,
-	0x01aec80c,
-	0xfd11e4b6,
-	0x07f105be,
-	0x03f0c500,
-	0x000bd001,
-/* 0x01d6: mmctx_exec_loop */
-/* 0x01d6: mmctx_wait_free */
-	0xe7f104bd,
-	0xe3f0c500,
-	0x00eecf01,
-	0xf41fe4f0,
-	0xce98f30b,
-	0x05e9fd00,
-	0xc80007f1,
-	0xd00103f0,
-	0x04bd000e,
-	0xb804c0b6,
-	0x1bf404cd,
-	0x02abc8d8,
-/* 0x0207: mmctx_fini_wait */
-	0xf11f1bf4,
-	0xf0c500b7,
-	0xbbcf01b3,
-	0x1fb4f000,
-	0xf410b4b0,
-	0xa7f0f01b,
-	0xd021f405,
-/* 0x0223: mmctx_stop */
-	0xc82b0ef4,
-	0xb4b600ab,
-	0x0cb9f010,
-	0xf112b9f0,
-	0xf0c50007,
-	0x0bd00103,
-/* 0x023b: mmctx_stop_wait */
-	0xf104bd00,
-	0xf0c500b7,
-	0xbbcf01b3,
-	0x12bbc800,
-/* 0x024b: mmctx_done */
-	0xbdf31bf4,
-	0x0199f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-/* 0x025e: strand_wait */
-	0xa0f900f8,
-	0xf402a7f0,
-	0xa0fcd021,
-/* 0x026a: strand_pre */
-	0x97f000f8,
-	0xfc07f10c,
-	0x0203f04a,
-	0xbd0009d0,
-	0x5e21f504,
-/* 0x027f: strand_post */
-	0xf000f802,
-	0x07f10d97,
-	0x03f04afc,
-	0x0009d002,
-	0x21f504bd,
-	0x00f8025e,
-/* 0x0294: strand_set */
-	0xf10fc7f0,
-	0xf04ffc07,
-	0x0cd00203,
-	0xf004bd00,
-	0x07f10bc7,
-	0x03f04afc,
-	0x000cd002,
-	0x07f104bd,
-	0x03f04ffc,
-	0x000ed002,
-	0xc7f004bd,
-	0xfc07f10a,
-	0x0203f04a,
-	0xbd000cd0,
-	0x5e21f504,
-/* 0x02d3: strand_ctx_init */
-	0xbd00f802,
-	0x0399f094,
-	0x0f0007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0x026a21f5,
-	0xf503e7f0,
-	0xbd029421,
-	0xfc07f1c4,
-	0x0203f047,
-	0xbd000cd0,
-	0x01c7f004,
-	0x4afc07f1,
-	0xd00203f0,
-	0x04bd000c,
-	0x025e21f5,
-	0xf1010c92,
-	0xf046fc07,
-	0x0cd00203,
-	0xf004bd00,
-	0x07f102c7,
-	0x03f04afc,
-	0x000cd002,
-	0x21f504bd,
-	0x21f5025e,
-	0x87f1027f,
-	0x83f04200,
-	0x0097f102,
-	0x0293f020,
-	0x950099cf,
-/* 0x034a: ctx_init_strand_loop */
-	0x8ed008fe,
-	0x408ed000,
-	0xb6808acf,
-	0xa0b606a5,
-	0x00eabb01,
-	0xb60480b6,
-	0x1bf40192,
-	0x08e4b6e8,
-	0xbdf2efbc,
-	0x0399f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-/* 0x037e: error */
-	0xe0f900f8,
-	0xf102ffb9,
-	0xf09814e7,
-	0x21f440e3,
-	0x01f7f09d,
-	0xf102ffb9,
-	0xf09c1ce7,
-	0x21f440e3,
-	0xf8e0fc9d,
-/* 0x03a1: init */
-	0xf104bd00,
-	0xf0420017,
-	0x11cf0013,
-	0x0911e700,
-	0x0814b601,
-	0xf00014fe,
-	0x07f10227,
-	0x03f01200,
-	0x0002d000,
-	0x17f104bd,
-	0x10fe04e6,
-	0x0007f100,
-	0x0003f007,
-	0xbd0000d0,
-	0x0427f004,
-	0x040007f1,
-	0xd00003f0,
-	0x04bd0002,
-	0xf11031f4,
-	0xf0820027,
-	0x22cf0123,
-	0x0137f000,
-	0xbb1f24f0,
-	0x32b60432,
-	0x05028001,
-	0xf1060380,
-	0xf0860027,
-	0x22cf0123,
-	0x04028000,
-	0x010027f1,
-	0xcf0223f0,
-	0x34bd0022,
-	0xf1082595,
-	0xf0c00007,
-	0x05d00103,
-	0xf104bd00,
-	0xf0c10007,
-	0x05d00103,
-	0x9804bd00,
-	0x0f98000e,
-	0x5021f501,
-	0x002fbb01,
-	0x98003fbb,
-	0x0f98010e,
-	0x5021f502,
-	0x050e9801,
-	0xbb00effd,
-	0x3ebb002e,
-	0x0235b600,
-	0xd30007f1,
-	0xd00103f0,
-	0x04bd0003,
-	0xb60825b6,
-	0x20b60635,
-	0x0130b601,
-	0xb60824b6,
-	0x2fb90834,
-	0xd321f502,
-	0x003fbb02,
-	0x010007f1,
-	0xd00203f0,
-	0x04bd0003,
-	0x29f024bd,
-	0x0007f11f,
-	0x0203f008,
-	0xbd0002d0,
-/* 0x04a9: main */
-	0x0031f404,
-	0xf00028f4,
-	0x21f41cd7,
-	0xf401f439,
-	0xf404e4b0,
-	0x81fe1e18,
-	0x0627f001,
-	0x12fd20bd,
-	0x01e4b604,
-	0xfe051efd,
-	0x21f50018,
-	0x0ef4059e,
-/* 0x04d9: main_not_ctx_xfer */
-	0x10ef94d3,
-	0xf501f5f0,
-	0xf4037e21,
-/* 0x04e6: ih */
-	0x80f9c60e,
-	0xf90188fe,
-	0xf990f980,
-	0xf9b0f9a0,
-	0xf9e0f9d0,
-	0xf104bdf0,
-	0xf00200a7,
-	0xaacf00a3,
-	0x04abc400,
-	0xf02c0bf4,
-	0xe7f11cd7,
-	0xe3f01a00,
-	0x00eecf00,
-	0x1900f7f1,
-	0xcf00f3f0,
-	0x21f400ff,
-	0x01e7f004,
-	0x1d0007f1,
-	0xd00003f0,
-	0x04bd000e,
-/* 0x0534: ih_no_fifo */
-	0x010007f1,
-	0xd00003f0,
-	0x04bd000a,
-	0xe0fcf0fc,
-	0xb0fcd0fc,
-	0x90fca0fc,
-	0x88fe80fc,
-	0xf480fc00,
-	0x01f80032,
-/* 0x0558: hub_barrier_done */
-	0x9801f7f0,
-	0xfebb040e,
-	0x02ffb904,
-	0x9418e7f1,
-	0xf440e3f0,
-	0x00f89d21,
-/* 0x0570: ctx_redswitch */
-	0xf120f7f0,
-	0xf0850007,
-	0x0fd00103,
-	0xf004bd00,
-/* 0x0582: ctx_redswitch_delay */
-	0xe2b608e7,
-	0xfd1bf401,
-	0x0800f5f1,
-	0x0200f5f1,
-	0x850007f1,
-	0xd00103f0,
-	0x04bd000f,
-/* 0x059e: ctx_xfer */
-	0x07f100f8,
-	0x03f08100,
-	0x000fd002,
-	0x11f404bd,
-	0x7021f507,
-/* 0x05b1: ctx_xfer_not_load */
-	0x6a21f505,
-	0xf124bd02,
-	0xf047fc07,
-	0x02d00203,
-	0xf004bd00,
-	0x20b6012c,
-	0xfc07f103,
-	0x0203f04a,
-	0xbd0002d0,
-	0x01acf004,
-	0xf102a5f0,
-	0xf00000b7,
-	0x0c9850b3,
-	0x0fc4b604,
-	0x9800bcbb,
-	0x0d98000c,
-	0x00e7f001,
-	0x016f21f5,
-	0xf001acf0,
-	0xb7f104a5,
-	0xb3f04000,
-	0x040c9850,
-	0xbb0fc4b6,
-	0x0c9800bc,
-	0x020d9801,
-	0xf1060f98,
-	0xf50800e7,
-	0xf5016f21,
-	0xf4025e21,
-	0x12f40601,
-/* 0x0629: ctx_xfer_post */
-	0x7f21f507,
-/* 0x062d: ctx_xfer_done */
-	0x5821f502,
-	0x0000f805,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc
deleted file mode 100644
index c2f754edbd7d..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#define NV_PGRAPH_GPCX_UNK__SIZE                                     0x00000001
-
-#define CHIPSET GF117
-#include "macros.fuc"
-
-.section #nvd7_grgpc_data
-#define INCLUDE_DATA
-#include "com.fuc"
-#include "gpc.fuc"
-#undef INCLUDE_DATA
-
-.section #nvd7_grgpc_code
-#define INCLUDE_CODE
-bra #init
-#include "com.fuc"
-#include "gpc.fuc"
-.align 256
-#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h
deleted file mode 100644
index d1504a4059c6..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h
+++ /dev/null
@@ -1,537 +0,0 @@
-uint32_t nvd7_grgpc_data[] = {
-/* 0x0000: gpc_mmio_list_head */
-	0x0000006c,
-/* 0x0004: gpc_mmio_list_tail */
-/* 0x0004: tpc_mmio_list_head */
-	0x0000006c,
-/* 0x0008: tpc_mmio_list_tail */
-/* 0x0008: unk_mmio_list_head */
-	0x0000006c,
-/* 0x000c: unk_mmio_list_tail */
-	0x0000006c,
-/* 0x0010: gpc_id */
-	0x00000000,
-/* 0x0014: tpc_count */
-	0x00000000,
-/* 0x0018: tpc_mask */
-	0x00000000,
-/* 0x001c: unk_count */
-	0x00000000,
-/* 0x0020: unk_mask */
-	0x00000000,
-/* 0x0024: cmd_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-uint32_t nvd7_grgpc_code[] = {
-	0x03a10ef5,
-/* 0x0004: queue_put */
-	0x9800d898,
-	0x86f001d9,
-	0x0489b808,
-	0xf00c1bf4,
-	0x21f502f7,
-	0x00f8037e,
-/* 0x001c: queue_put_next */
-	0xb60798c4,
-	0x8dbb0384,
-	0x0880b600,
-	0x80008e80,
-	0x90b6018f,
-	0x0f94f001,
-	0xf801d980,
-/* 0x0039: queue_get */
-	0x0131f400,
-	0x9800d898,
-	0x89b801d9,
-	0x210bf404,
-	0xb60789c4,
-	0x9dbb0394,
-	0x0890b600,
-	0x98009e98,
-	0x80b6019f,
-	0x0f84f001,
-	0xf400d880,
-/* 0x0066: queue_get_done */
-	0x00f80132,
-/* 0x0068: nv_rd32 */
-	0xf002ecb9,
-	0x07f11fc9,
-	0x03f0ca00,
-	0x000cd001,
-/* 0x007a: nv_rd32_wait */
-	0xc7f104bd,
-	0xc3f0ca00,
-	0x00cccf01,
-	0xf41fccc8,
-	0xa7f0f31b,
-	0x1021f506,
-	0x00f7f101,
-	0x01f3f0cb,
-	0xf800ffcf,
-/* 0x009d: nv_wr32 */
-	0x0007f100,
-	0x0103f0cc,
-	0xbd000fd0,
-	0x02ecb904,
-	0xf01fc9f0,
-	0x07f11ec9,
-	0x03f0ca00,
-	0x000cd001,
-/* 0x00be: nv_wr32_wait */
-	0xc7f104bd,
-	0xc3f0ca00,
-	0x00cccf01,
-	0xf41fccc8,
-	0x00f8f31b,
-/* 0x00d0: wait_donez */
-	0x99f094bd,
-	0x0007f100,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f006,
-	0xbd000ad0,
-/* 0x00ed: wait_donez_ne */
-	0x0087f104,
-	0x0183f000,
-	0xff0088cf,
-	0x1bf4888a,
-	0xf094bdf3,
-	0x07f10099,
-	0x03f01700,
-	0x0009d002,
-	0x00f804bd,
-/* 0x0110: wait_doneo */
-	0x99f094bd,
-	0x0007f100,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f006,
-	0xbd000ad0,
-/* 0x012d: wait_doneo_e */
-	0x0087f104,
-	0x0183f000,
-	0xff0088cf,
-	0x0bf4888a,
-	0xf094bdf3,
-	0x07f10099,
-	0x03f01700,
-	0x0009d002,
-	0x00f804bd,
-/* 0x0150: mmctx_size */
-/* 0x0152: nv_mmctx_size_loop */
-	0xe89894bd,
-	0x1a85b600,
-	0xb60180b6,
-	0x98bb0284,
-	0x04e0b600,
-	0xf404efb8,
-	0x9fb9eb1b,
-/* 0x016f: mmctx_xfer */
-	0xbd00f802,
-	0x0199f094,
-	0x0f0007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0xbbfd94bd,
-	0x120bf405,
-	0xc40007f1,
-	0xd00103f0,
-	0x04bd000b,
-/* 0x0197: mmctx_base_disabled */
-	0xfd0099f0,
-	0x0bf405ee,
-	0x0007f11e,
-	0x0103f0c6,
-	0xbd000ed0,
-	0x0007f104,
-	0x0103f0c7,
-	0xbd000fd0,
-	0x0199f004,
-/* 0x01b8: mmctx_multi_disabled */
-	0xb600abc8,
-	0xb9f010b4,
-	0x01aec80c,
-	0xfd11e4b6,
-	0x07f105be,
-	0x03f0c500,
-	0x000bd001,
-/* 0x01d6: mmctx_exec_loop */
-/* 0x01d6: mmctx_wait_free */
-	0xe7f104bd,
-	0xe3f0c500,
-	0x00eecf01,
-	0xf41fe4f0,
-	0xce98f30b,
-	0x05e9fd00,
-	0xc80007f1,
-	0xd00103f0,
-	0x04bd000e,
-	0xb804c0b6,
-	0x1bf404cd,
-	0x02abc8d8,
-/* 0x0207: mmctx_fini_wait */
-	0xf11f1bf4,
-	0xf0c500b7,
-	0xbbcf01b3,
-	0x1fb4f000,
-	0xf410b4b0,
-	0xa7f0f01b,
-	0xd021f405,
-/* 0x0223: mmctx_stop */
-	0xc82b0ef4,
-	0xb4b600ab,
-	0x0cb9f010,
-	0xf112b9f0,
-	0xf0c50007,
-	0x0bd00103,
-/* 0x023b: mmctx_stop_wait */
-	0xf104bd00,
-	0xf0c500b7,
-	0xbbcf01b3,
-	0x12bbc800,
-/* 0x024b: mmctx_done */
-	0xbdf31bf4,
-	0x0199f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-/* 0x025e: strand_wait */
-	0xa0f900f8,
-	0xf402a7f0,
-	0xa0fcd021,
-/* 0x026a: strand_pre */
-	0x97f000f8,
-	0xfc07f10c,
-	0x0203f04a,
-	0xbd0009d0,
-	0x5e21f504,
-/* 0x027f: strand_post */
-	0xf000f802,
-	0x07f10d97,
-	0x03f04afc,
-	0x0009d002,
-	0x21f504bd,
-	0x00f8025e,
-/* 0x0294: strand_set */
-	0xf10fc7f0,
-	0xf04ffc07,
-	0x0cd00203,
-	0xf004bd00,
-	0x07f10bc7,
-	0x03f04afc,
-	0x000cd002,
-	0x07f104bd,
-	0x03f04ffc,
-	0x000ed002,
-	0xc7f004bd,
-	0xfc07f10a,
-	0x0203f04a,
-	0xbd000cd0,
-	0x5e21f504,
-/* 0x02d3: strand_ctx_init */
-	0xbd00f802,
-	0x0399f094,
-	0x0f0007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0x026a21f5,
-	0xf503e7f0,
-	0xbd029421,
-	0xfc07f1c4,
-	0x0203f047,
-	0xbd000cd0,
-	0x01c7f004,
-	0x4afc07f1,
-	0xd00203f0,
-	0x04bd000c,
-	0x025e21f5,
-	0xf1010c92,
-	0xf046fc07,
-	0x0cd00203,
-	0xf004bd00,
-	0x07f102c7,
-	0x03f04afc,
-	0x000cd002,
-	0x21f504bd,
-	0x21f5025e,
-	0x87f1027f,
-	0x83f04200,
-	0x0097f102,
-	0x0293f020,
-	0x950099cf,
-/* 0x034a: ctx_init_strand_loop */
-	0x8ed008fe,
-	0x408ed000,
-	0xb6808acf,
-	0xa0b606a5,
-	0x00eabb01,
-	0xb60480b6,
-	0x1bf40192,
-	0x08e4b6e8,
-	0xbdf2efbc,
-	0x0399f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-/* 0x037e: error */
-	0xe0f900f8,
-	0xf102ffb9,
-	0xf09814e7,
-	0x21f440e3,
-	0x01f7f09d,
-	0xf102ffb9,
-	0xf09c1ce7,
-	0x21f440e3,
-	0xf8e0fc9d,
-/* 0x03a1: init */
-	0xf104bd00,
-	0xf0420017,
-	0x11cf0013,
-	0x0911e700,
-	0x0814b601,
-	0xf00014fe,
-	0x07f10227,
-	0x03f01200,
-	0x0002d000,
-	0x17f104bd,
-	0x10fe0530,
-	0x0007f100,
-	0x0003f007,
-	0xbd0000d0,
-	0x0427f004,
-	0x040007f1,
-	0xd00003f0,
-	0x04bd0002,
-	0xf11031f4,
-	0xf0820027,
-	0x22cf0123,
-	0x0137f000,
-	0xbb1f24f0,
-	0x32b60432,
-	0x05028001,
-	0xf1060380,
-	0xf0860027,
-	0x22cf0123,
-	0x04028000,
-	0x0c30e7f1,
-	0xbd50e3f0,
-	0xbd34bd24,
-/* 0x0421: init_unk_loop */
-	0x6821f444,
-	0xf400f6b0,
-	0xf7f00f0b,
-	0x04f2bb01,
-	0xb6054ffd,
-/* 0x0436: init_unk_next */
-	0x20b60130,
-	0x04e0b601,
-	0xf40126b0,
-/* 0x0442: init_unk_done */
-	0x0380e21b,
-	0x08048007,
-	0x010027f1,
-	0xcf0223f0,
-	0x34bd0022,
-	0xf1082595,
-	0xf0c00007,
-	0x05d00103,
-	0xf104bd00,
-	0xf0c10007,
-	0x05d00103,
-	0x9804bd00,
-	0x0f98000e,
-	0x5021f501,
-	0x002fbb01,
-	0x98003fbb,
-	0x0f98010e,
-	0x5021f502,
-	0x050e9801,
-	0xbb00effd,
-	0x3ebb002e,
-	0x020e9800,
-	0xf5030f98,
-	0x98015021,
-	0xeffd070e,
-	0x002ebb00,
-	0xb6003ebb,
-	0x07f10235,
-	0x03f0d300,
-	0x0003d001,
-	0x25b604bd,
-	0x0635b608,
-	0xb60120b6,
-	0x24b60130,
-	0x0834b608,
-	0xf5022fb9,
-	0xbb02d321,
-	0x07f1003f,
-	0x03f00100,
-	0x0003d002,
-	0x24bd04bd,
-	0xf11f29f0,
-	0xf0080007,
-	0x02d00203,
-/* 0x04f3: main */
-	0xf404bd00,
-	0x28f40031,
-	0x24d7f000,
-	0xf43921f4,
-	0xe4b0f401,
-	0x1e18f404,
-	0xf00181fe,
-	0x20bd0627,
-	0xb60412fd,
-	0x1efd01e4,
-	0x0018fe05,
-	0x05e821f5,
-/* 0x0523: main_not_ctx_xfer */
-	0x94d30ef4,
-	0xf5f010ef,
-	0x7e21f501,
-	0xc60ef403,
-/* 0x0530: ih */
-	0x88fe80f9,
-	0xf980f901,
-	0xf9a0f990,
-	0xf9d0f9b0,
-	0xbdf0f9e0,
-	0x00a7f104,
-	0x00a3f002,
-	0xc400aacf,
-	0x0bf404ab,
-	0x24d7f02c,
-	0x1a00e7f1,
-	0xcf00e3f0,
-	0xf7f100ee,
-	0xf3f01900,
-	0x00ffcf00,
-	0xf00421f4,
-	0x07f101e7,
-	0x03f01d00,
-	0x000ed000,
-/* 0x057e: ih_no_fifo */
-	0x07f104bd,
-	0x03f00100,
-	0x000ad000,
-	0xf0fc04bd,
-	0xd0fce0fc,
-	0xa0fcb0fc,
-	0x80fc90fc,
-	0xfc0088fe,
-	0x0032f480,
-/* 0x05a2: hub_barrier_done */
-	0xf7f001f8,
-	0x040e9801,
-	0xb904febb,
-	0xe7f102ff,
-	0xe3f09418,
-	0x9d21f440,
-/* 0x05ba: ctx_redswitch */
-	0xf7f000f8,
-	0x0007f120,
-	0x0103f085,
-	0xbd000fd0,
-	0x08e7f004,
-/* 0x05cc: ctx_redswitch_delay */
-	0xf401e2b6,
-	0xf5f1fd1b,
-	0xf5f10800,
-	0x07f10200,
-	0x03f08500,
-	0x000fd001,
-	0x00f804bd,
-/* 0x05e8: ctx_xfer */
-	0x810007f1,
-	0xd00203f0,
-	0x04bd000f,
-	0xf50711f4,
-/* 0x05fb: ctx_xfer_not_load */
-	0xf505ba21,
-	0xbd026a21,
-	0xfc07f124,
-	0x0203f047,
-	0xbd0002d0,
-	0x012cf004,
-	0xf10320b6,
-	0xf04afc07,
-	0x02d00203,
-	0xf004bd00,
-	0xa5f001ac,
-	0x00b7f102,
-	0x50b3f000,
-	0xb6040c98,
-	0xbcbb0fc4,
-	0x000c9800,
-	0xf0010d98,
-	0x21f500e7,
-	0xacf0016f,
-	0x00b7f101,
-	0x50b3f040,
-	0xb6040c98,
-	0xbcbb0fc4,
-	0x010c9800,
-	0x98020d98,
-	0xe7f1060f,
-	0x21f50800,
-	0xacf0016f,
-	0x04a5f001,
-	0x3000b7f1,
-	0x9850b3f0,
-	0xc4b6040c,
-	0x00bcbb0f,
-	0x98020c98,
-	0x0f98030d,
-	0x00e7f108,
-	0x6f21f502,
-	0x5e21f501,
-	0x0601f402,
-/* 0x0697: ctx_xfer_post */
-	0xf50712f4,
-/* 0x069b: ctx_xfer_done */
-	0xf5027f21,
-	0xf805a221,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
deleted file mode 100644
index 6b906cd2a31f..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#define NV_PGRAPH_GPCX_UNK__SIZE                                     0x00000001
-
-#define CHIPSET GK100
-#include "macros.fuc"
-
-.section #nve0_grgpc_data
-#define INCLUDE_DATA
-#include "com.fuc"
-#include "gpc.fuc"
-#undef INCLUDE_DATA
-
-.section #nve0_grgpc_code
-#define INCLUDE_CODE
-bra #init
-#include "com.fuc"
-#include "gpc.fuc"
-.align 256
-#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
deleted file mode 100644
index 855b220378f9..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
+++ /dev/null
@@ -1,537 +0,0 @@
-uint32_t nve0_grgpc_data[] = {
-/* 0x0000: gpc_mmio_list_head */
-	0x0000006c,
-/* 0x0004: gpc_mmio_list_tail */
-/* 0x0004: tpc_mmio_list_head */
-	0x0000006c,
-/* 0x0008: tpc_mmio_list_tail */
-/* 0x0008: unk_mmio_list_head */
-	0x0000006c,
-/* 0x000c: unk_mmio_list_tail */
-	0x0000006c,
-/* 0x0010: gpc_id */
-	0x00000000,
-/* 0x0014: tpc_count */
-	0x00000000,
-/* 0x0018: tpc_mask */
-	0x00000000,
-/* 0x001c: unk_count */
-	0x00000000,
-/* 0x0020: unk_mask */
-	0x00000000,
-/* 0x0024: cmd_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-uint32_t nve0_grgpc_code[] = {
-	0x03a10ef5,
-/* 0x0004: queue_put */
-	0x9800d898,
-	0x86f001d9,
-	0x0489b808,
-	0xf00c1bf4,
-	0x21f502f7,
-	0x00f8037e,
-/* 0x001c: queue_put_next */
-	0xb60798c4,
-	0x8dbb0384,
-	0x0880b600,
-	0x80008e80,
-	0x90b6018f,
-	0x0f94f001,
-	0xf801d980,
-/* 0x0039: queue_get */
-	0x0131f400,
-	0x9800d898,
-	0x89b801d9,
-	0x210bf404,
-	0xb60789c4,
-	0x9dbb0394,
-	0x0890b600,
-	0x98009e98,
-	0x80b6019f,
-	0x0f84f001,
-	0xf400d880,
-/* 0x0066: queue_get_done */
-	0x00f80132,
-/* 0x0068: nv_rd32 */
-	0xf002ecb9,
-	0x07f11fc9,
-	0x03f0ca00,
-	0x000cd001,
-/* 0x007a: nv_rd32_wait */
-	0xc7f104bd,
-	0xc3f0ca00,
-	0x00cccf01,
-	0xf41fccc8,
-	0xa7f0f31b,
-	0x1021f506,
-	0x00f7f101,
-	0x01f3f0cb,
-	0xf800ffcf,
-/* 0x009d: nv_wr32 */
-	0x0007f100,
-	0x0103f0cc,
-	0xbd000fd0,
-	0x02ecb904,
-	0xf01fc9f0,
-	0x07f11ec9,
-	0x03f0ca00,
-	0x000cd001,
-/* 0x00be: nv_wr32_wait */
-	0xc7f104bd,
-	0xc3f0ca00,
-	0x00cccf01,
-	0xf41fccc8,
-	0x00f8f31b,
-/* 0x00d0: wait_donez */
-	0x99f094bd,
-	0x0007f100,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f006,
-	0xbd000ad0,
-/* 0x00ed: wait_donez_ne */
-	0x0087f104,
-	0x0183f000,
-	0xff0088cf,
-	0x1bf4888a,
-	0xf094bdf3,
-	0x07f10099,
-	0x03f01700,
-	0x0009d002,
-	0x00f804bd,
-/* 0x0110: wait_doneo */
-	0x99f094bd,
-	0x0007f100,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f006,
-	0xbd000ad0,
-/* 0x012d: wait_doneo_e */
-	0x0087f104,
-	0x0183f000,
-	0xff0088cf,
-	0x0bf4888a,
-	0xf094bdf3,
-	0x07f10099,
-	0x03f01700,
-	0x0009d002,
-	0x00f804bd,
-/* 0x0150: mmctx_size */
-/* 0x0152: nv_mmctx_size_loop */
-	0xe89894bd,
-	0x1a85b600,
-	0xb60180b6,
-	0x98bb0284,
-	0x04e0b600,
-	0xf404efb8,
-	0x9fb9eb1b,
-/* 0x016f: mmctx_xfer */
-	0xbd00f802,
-	0x0199f094,
-	0x0f0007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0xbbfd94bd,
-	0x120bf405,
-	0xc40007f1,
-	0xd00103f0,
-	0x04bd000b,
-/* 0x0197: mmctx_base_disabled */
-	0xfd0099f0,
-	0x0bf405ee,
-	0x0007f11e,
-	0x0103f0c6,
-	0xbd000ed0,
-	0x0007f104,
-	0x0103f0c7,
-	0xbd000fd0,
-	0x0199f004,
-/* 0x01b8: mmctx_multi_disabled */
-	0xb600abc8,
-	0xb9f010b4,
-	0x01aec80c,
-	0xfd11e4b6,
-	0x07f105be,
-	0x03f0c500,
-	0x000bd001,
-/* 0x01d6: mmctx_exec_loop */
-/* 0x01d6: mmctx_wait_free */
-	0xe7f104bd,
-	0xe3f0c500,
-	0x00eecf01,
-	0xf41fe4f0,
-	0xce98f30b,
-	0x05e9fd00,
-	0xc80007f1,
-	0xd00103f0,
-	0x04bd000e,
-	0xb804c0b6,
-	0x1bf404cd,
-	0x02abc8d8,
-/* 0x0207: mmctx_fini_wait */
-	0xf11f1bf4,
-	0xf0c500b7,
-	0xbbcf01b3,
-	0x1fb4f000,
-	0xf410b4b0,
-	0xa7f0f01b,
-	0xd021f405,
-/* 0x0223: mmctx_stop */
-	0xc82b0ef4,
-	0xb4b600ab,
-	0x0cb9f010,
-	0xf112b9f0,
-	0xf0c50007,
-	0x0bd00103,
-/* 0x023b: mmctx_stop_wait */
-	0xf104bd00,
-	0xf0c500b7,
-	0xbbcf01b3,
-	0x12bbc800,
-/* 0x024b: mmctx_done */
-	0xbdf31bf4,
-	0x0199f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-/* 0x025e: strand_wait */
-	0xa0f900f8,
-	0xf402a7f0,
-	0xa0fcd021,
-/* 0x026a: strand_pre */
-	0x97f000f8,
-	0xfc07f10c,
-	0x0203f04a,
-	0xbd0009d0,
-	0x5e21f504,
-/* 0x027f: strand_post */
-	0xf000f802,
-	0x07f10d97,
-	0x03f04afc,
-	0x0009d002,
-	0x21f504bd,
-	0x00f8025e,
-/* 0x0294: strand_set */
-	0xf10fc7f0,
-	0xf04ffc07,
-	0x0cd00203,
-	0xf004bd00,
-	0x07f10bc7,
-	0x03f04afc,
-	0x000cd002,
-	0x07f104bd,
-	0x03f04ffc,
-	0x000ed002,
-	0xc7f004bd,
-	0xfc07f10a,
-	0x0203f04a,
-	0xbd000cd0,
-	0x5e21f504,
-/* 0x02d3: strand_ctx_init */
-	0xbd00f802,
-	0x0399f094,
-	0x0f0007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0x026a21f5,
-	0xf503e7f0,
-	0xbd029421,
-	0xfc07f1c4,
-	0x0203f047,
-	0xbd000cd0,
-	0x01c7f004,
-	0x4afc07f1,
-	0xd00203f0,
-	0x04bd000c,
-	0x025e21f5,
-	0xf1010c92,
-	0xf046fc07,
-	0x0cd00203,
-	0xf004bd00,
-	0x07f102c7,
-	0x03f04afc,
-	0x000cd002,
-	0x21f504bd,
-	0x21f5025e,
-	0x87f1027f,
-	0x83f04200,
-	0x0097f102,
-	0x0293f020,
-	0x950099cf,
-/* 0x034a: ctx_init_strand_loop */
-	0x8ed008fe,
-	0x408ed000,
-	0xb6808acf,
-	0xa0b606a5,
-	0x00eabb01,
-	0xb60480b6,
-	0x1bf40192,
-	0x08e4b6e8,
-	0xbdf2efbc,
-	0x0399f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-/* 0x037e: error */
-	0xe0f900f8,
-	0xf102ffb9,
-	0xf09814e7,
-	0x21f440e3,
-	0x01f7f09d,
-	0xf102ffb9,
-	0xf09c1ce7,
-	0x21f440e3,
-	0xf8e0fc9d,
-/* 0x03a1: init */
-	0xf104bd00,
-	0xf0420017,
-	0x11cf0013,
-	0x0911e700,
-	0x0814b601,
-	0xf00014fe,
-	0x07f10227,
-	0x03f01200,
-	0x0002d000,
-	0x17f104bd,
-	0x10fe0530,
-	0x0007f100,
-	0x0003f007,
-	0xbd0000d0,
-	0x0427f004,
-	0x040007f1,
-	0xd00003f0,
-	0x04bd0002,
-	0xf11031f4,
-	0xf0820027,
-	0x22cf0123,
-	0x0137f000,
-	0xbb1f24f0,
-	0x32b60432,
-	0x05028001,
-	0xf1060380,
-	0xf0860027,
-	0x22cf0123,
-	0x04028000,
-	0x0c30e7f1,
-	0xbd50e3f0,
-	0xbd34bd24,
-/* 0x0421: init_unk_loop */
-	0x6821f444,
-	0xf400f6b0,
-	0xf7f00f0b,
-	0x04f2bb01,
-	0xb6054ffd,
-/* 0x0436: init_unk_next */
-	0x20b60130,
-	0x04e0b601,
-	0xf40126b0,
-/* 0x0442: init_unk_done */
-	0x0380e21b,
-	0x08048007,
-	0x010027f1,
-	0xcf0223f0,
-	0x34bd0022,
-	0xf1082595,
-	0xf0c00007,
-	0x05d00103,
-	0xf104bd00,
-	0xf0c10007,
-	0x05d00103,
-	0x9804bd00,
-	0x0f98000e,
-	0x5021f501,
-	0x002fbb01,
-	0x98003fbb,
-	0x0f98010e,
-	0x5021f502,
-	0x050e9801,
-	0xbb00effd,
-	0x3ebb002e,
-	0x020e9800,
-	0xf5030f98,
-	0x98015021,
-	0xeffd070e,
-	0x002ebb00,
-	0xb6003ebb,
-	0x07f10235,
-	0x03f0d300,
-	0x0003d001,
-	0x25b604bd,
-	0x0635b608,
-	0xb60120b6,
-	0x24b60130,
-	0x0834b608,
-	0xf5022fb9,
-	0xbb02d321,
-	0x07f1003f,
-	0x03f00100,
-	0x0003d002,
-	0x24bd04bd,
-	0xf11f29f0,
-	0xf0080007,
-	0x02d00203,
-/* 0x04f3: main */
-	0xf404bd00,
-	0x28f40031,
-	0x24d7f000,
-	0xf43921f4,
-	0xe4b0f401,
-	0x1e18f404,
-	0xf00181fe,
-	0x20bd0627,
-	0xb60412fd,
-	0x1efd01e4,
-	0x0018fe05,
-	0x05e821f5,
-/* 0x0523: main_not_ctx_xfer */
-	0x94d30ef4,
-	0xf5f010ef,
-	0x7e21f501,
-	0xc60ef403,
-/* 0x0530: ih */
-	0x88fe80f9,
-	0xf980f901,
-	0xf9a0f990,
-	0xf9d0f9b0,
-	0xbdf0f9e0,
-	0x00a7f104,
-	0x00a3f002,
-	0xc400aacf,
-	0x0bf404ab,
-	0x24d7f02c,
-	0x1a00e7f1,
-	0xcf00e3f0,
-	0xf7f100ee,
-	0xf3f01900,
-	0x00ffcf00,
-	0xf00421f4,
-	0x07f101e7,
-	0x03f01d00,
-	0x000ed000,
-/* 0x057e: ih_no_fifo */
-	0x07f104bd,
-	0x03f00100,
-	0x000ad000,
-	0xf0fc04bd,
-	0xd0fce0fc,
-	0xa0fcb0fc,
-	0x80fc90fc,
-	0xfc0088fe,
-	0x0032f480,
-/* 0x05a2: hub_barrier_done */
-	0xf7f001f8,
-	0x040e9801,
-	0xb904febb,
-	0xe7f102ff,
-	0xe3f09418,
-	0x9d21f440,
-/* 0x05ba: ctx_redswitch */
-	0xf7f000f8,
-	0x0007f120,
-	0x0103f085,
-	0xbd000fd0,
-	0x08e7f004,
-/* 0x05cc: ctx_redswitch_delay */
-	0xf401e2b6,
-	0xf5f1fd1b,
-	0xf5f10800,
-	0x07f10200,
-	0x03f08500,
-	0x000fd001,
-	0x00f804bd,
-/* 0x05e8: ctx_xfer */
-	0x810007f1,
-	0xd00203f0,
-	0x04bd000f,
-	0xf50711f4,
-/* 0x05fb: ctx_xfer_not_load */
-	0xf505ba21,
-	0xbd026a21,
-	0xfc07f124,
-	0x0203f047,
-	0xbd0002d0,
-	0x012cf004,
-	0xf10320b6,
-	0xf04afc07,
-	0x02d00203,
-	0xf004bd00,
-	0xa5f001ac,
-	0x00b7f102,
-	0x50b3f000,
-	0xb6040c98,
-	0xbcbb0fc4,
-	0x000c9800,
-	0xf0010d98,
-	0x21f500e7,
-	0xacf0016f,
-	0x00b7f101,
-	0x50b3f040,
-	0xb6040c98,
-	0xbcbb0fc4,
-	0x010c9800,
-	0x98020d98,
-	0xe7f1060f,
-	0x21f50800,
-	0xacf0016f,
-	0x04a5f001,
-	0x3000b7f1,
-	0x9850b3f0,
-	0xc4b6040c,
-	0x00bcbb0f,
-	0x98020c98,
-	0x0f98030d,
-	0x00e7f108,
-	0x6f21f502,
-	0x5e21f501,
-	0x0601f402,
-/* 0x0697: ctx_xfer_post */
-	0xf50712f4,
-/* 0x069b: ctx_xfer_done */
-	0xf5027f21,
-	0xf805a221,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc
deleted file mode 100644
index 90bbe525b626..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#define NV_PGRAPH_GPCX_UNK__SIZE                                     0x00000002
-
-#define CHIPSET GK110
-#include "macros.fuc"
-
-.section #nvf0_grgpc_data
-#define INCLUDE_DATA
-#include "com.fuc"
-#include "gpc.fuc"
-#undef INCLUDE_DATA
-
-.section #nvf0_grgpc_code
-#define INCLUDE_CODE
-bra #init
-#include "com.fuc"
-#include "gpc.fuc"
-.align 256
-#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h
deleted file mode 100644
index 1b803197d28b..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h
+++ /dev/null
@@ -1,537 +0,0 @@
-uint32_t nvf0_grgpc_data[] = {
-/* 0x0000: gpc_mmio_list_head */
-	0x0000006c,
-/* 0x0004: gpc_mmio_list_tail */
-/* 0x0004: tpc_mmio_list_head */
-	0x0000006c,
-/* 0x0008: tpc_mmio_list_tail */
-/* 0x0008: unk_mmio_list_head */
-	0x0000006c,
-/* 0x000c: unk_mmio_list_tail */
-	0x0000006c,
-/* 0x0010: gpc_id */
-	0x00000000,
-/* 0x0014: tpc_count */
-	0x00000000,
-/* 0x0018: tpc_mask */
-	0x00000000,
-/* 0x001c: unk_count */
-	0x00000000,
-/* 0x0020: unk_mask */
-	0x00000000,
-/* 0x0024: cmd_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-uint32_t nvf0_grgpc_code[] = {
-	0x03a10ef5,
-/* 0x0004: queue_put */
-	0x9800d898,
-	0x86f001d9,
-	0x0489b808,
-	0xf00c1bf4,
-	0x21f502f7,
-	0x00f8037e,
-/* 0x001c: queue_put_next */
-	0xb60798c4,
-	0x8dbb0384,
-	0x0880b600,
-	0x80008e80,
-	0x90b6018f,
-	0x0f94f001,
-	0xf801d980,
-/* 0x0039: queue_get */
-	0x0131f400,
-	0x9800d898,
-	0x89b801d9,
-	0x210bf404,
-	0xb60789c4,
-	0x9dbb0394,
-	0x0890b600,
-	0x98009e98,
-	0x80b6019f,
-	0x0f84f001,
-	0xf400d880,
-/* 0x0066: queue_get_done */
-	0x00f80132,
-/* 0x0068: nv_rd32 */
-	0xf002ecb9,
-	0x07f11fc9,
-	0x03f0ca00,
-	0x000cd001,
-/* 0x007a: nv_rd32_wait */
-	0xc7f104bd,
-	0xc3f0ca00,
-	0x00cccf01,
-	0xf41fccc8,
-	0xa7f0f31b,
-	0x1021f506,
-	0x00f7f101,
-	0x01f3f0cb,
-	0xf800ffcf,
-/* 0x009d: nv_wr32 */
-	0x0007f100,
-	0x0103f0cc,
-	0xbd000fd0,
-	0x02ecb904,
-	0xf01fc9f0,
-	0x07f11ec9,
-	0x03f0ca00,
-	0x000cd001,
-/* 0x00be: nv_wr32_wait */
-	0xc7f104bd,
-	0xc3f0ca00,
-	0x00cccf01,
-	0xf41fccc8,
-	0x00f8f31b,
-/* 0x00d0: wait_donez */
-	0x99f094bd,
-	0x0007f100,
-	0x0203f037,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f006,
-	0xbd000ad0,
-/* 0x00ed: wait_donez_ne */
-	0x0087f104,
-	0x0183f000,
-	0xff0088cf,
-	0x1bf4888a,
-	0xf094bdf3,
-	0x07f10099,
-	0x03f01700,
-	0x0009d002,
-	0x00f804bd,
-/* 0x0110: wait_doneo */
-	0x99f094bd,
-	0x0007f100,
-	0x0203f037,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f006,
-	0xbd000ad0,
-/* 0x012d: wait_doneo_e */
-	0x0087f104,
-	0x0183f000,
-	0xff0088cf,
-	0x0bf4888a,
-	0xf094bdf3,
-	0x07f10099,
-	0x03f01700,
-	0x0009d002,
-	0x00f804bd,
-/* 0x0150: mmctx_size */
-/* 0x0152: nv_mmctx_size_loop */
-	0xe89894bd,
-	0x1a85b600,
-	0xb60180b6,
-	0x98bb0284,
-	0x04e0b600,
-	0xf404efb8,
-	0x9fb9eb1b,
-/* 0x016f: mmctx_xfer */
-	0xbd00f802,
-	0x0199f094,
-	0x370007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0xbbfd94bd,
-	0x120bf405,
-	0xc40007f1,
-	0xd00103f0,
-	0x04bd000b,
-/* 0x0197: mmctx_base_disabled */
-	0xfd0099f0,
-	0x0bf405ee,
-	0x0007f11e,
-	0x0103f0c6,
-	0xbd000ed0,
-	0x0007f104,
-	0x0103f0c7,
-	0xbd000fd0,
-	0x0199f004,
-/* 0x01b8: mmctx_multi_disabled */
-	0xb600abc8,
-	0xb9f010b4,
-	0x01aec80c,
-	0xfd11e4b6,
-	0x07f105be,
-	0x03f0c500,
-	0x000bd001,
-/* 0x01d6: mmctx_exec_loop */
-/* 0x01d6: mmctx_wait_free */
-	0xe7f104bd,
-	0xe3f0c500,
-	0x00eecf01,
-	0xf41fe4f0,
-	0xce98f30b,
-	0x05e9fd00,
-	0xc80007f1,
-	0xd00103f0,
-	0x04bd000e,
-	0xb804c0b6,
-	0x1bf404cd,
-	0x02abc8d8,
-/* 0x0207: mmctx_fini_wait */
-	0xf11f1bf4,
-	0xf0c500b7,
-	0xbbcf01b3,
-	0x1fb4f000,
-	0xf410b4b0,
-	0xa7f0f01b,
-	0xd021f405,
-/* 0x0223: mmctx_stop */
-	0xc82b0ef4,
-	0xb4b600ab,
-	0x0cb9f010,
-	0xf112b9f0,
-	0xf0c50007,
-	0x0bd00103,
-/* 0x023b: mmctx_stop_wait */
-	0xf104bd00,
-	0xf0c500b7,
-	0xbbcf01b3,
-	0x12bbc800,
-/* 0x024b: mmctx_done */
-	0xbdf31bf4,
-	0x0199f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-/* 0x025e: strand_wait */
-	0xa0f900f8,
-	0xf402a7f0,
-	0xa0fcd021,
-/* 0x026a: strand_pre */
-	0x97f000f8,
-	0xfc07f10c,
-	0x0203f04a,
-	0xbd0009d0,
-	0x5e21f504,
-/* 0x027f: strand_post */
-	0xf000f802,
-	0x07f10d97,
-	0x03f04afc,
-	0x0009d002,
-	0x21f504bd,
-	0x00f8025e,
-/* 0x0294: strand_set */
-	0xf10fc7f0,
-	0xf04ffc07,
-	0x0cd00203,
-	0xf004bd00,
-	0x07f10bc7,
-	0x03f04afc,
-	0x000cd002,
-	0x07f104bd,
-	0x03f04ffc,
-	0x000ed002,
-	0xc7f004bd,
-	0xfc07f10a,
-	0x0203f04a,
-	0xbd000cd0,
-	0x5e21f504,
-/* 0x02d3: strand_ctx_init */
-	0xbd00f802,
-	0x0399f094,
-	0x370007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0x026a21f5,
-	0xf503e7f0,
-	0xbd029421,
-	0xfc07f1c4,
-	0x0203f047,
-	0xbd000cd0,
-	0x01c7f004,
-	0x4afc07f1,
-	0xd00203f0,
-	0x04bd000c,
-	0x025e21f5,
-	0xf1010c92,
-	0xf046fc07,
-	0x0cd00203,
-	0xf004bd00,
-	0x07f102c7,
-	0x03f04afc,
-	0x000cd002,
-	0x21f504bd,
-	0x21f5025e,
-	0x87f1027f,
-	0x83f04200,
-	0x0097f102,
-	0x0293f020,
-	0x950099cf,
-/* 0x034a: ctx_init_strand_loop */
-	0x8ed008fe,
-	0x408ed000,
-	0xb6808acf,
-	0xa0b606a5,
-	0x00eabb01,
-	0xb60480b6,
-	0x1bf40192,
-	0x08e4b6e8,
-	0xbdf2efbc,
-	0x0399f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-/* 0x037e: error */
-	0xe0f900f8,
-	0xf102ffb9,
-	0xf09814e7,
-	0x21f440e3,
-	0x01f7f09d,
-	0xf102ffb9,
-	0xf09c1ce7,
-	0x21f440e3,
-	0xf8e0fc9d,
-/* 0x03a1: init */
-	0xf104bd00,
-	0xf0420017,
-	0x11cf0013,
-	0x0911e700,
-	0x0814b601,
-	0xf00014fe,
-	0x07f10227,
-	0x03f01200,
-	0x0002d000,
-	0x17f104bd,
-	0x10fe0530,
-	0x0007f100,
-	0x0003f007,
-	0xbd0000d0,
-	0x0427f004,
-	0x040007f1,
-	0xd00003f0,
-	0x04bd0002,
-	0xf11031f4,
-	0xf0820027,
-	0x22cf0123,
-	0x0137f000,
-	0xbb1f24f0,
-	0x32b60432,
-	0x05028001,
-	0xf1060380,
-	0xf0860027,
-	0x22cf0123,
-	0x04028000,
-	0x0c30e7f1,
-	0xbd50e3f0,
-	0xbd34bd24,
-/* 0x0421: init_unk_loop */
-	0x6821f444,
-	0xf400f6b0,
-	0xf7f00f0b,
-	0x04f2bb01,
-	0xb6054ffd,
-/* 0x0436: init_unk_next */
-	0x20b60130,
-	0x04e0b601,
-	0xf40226b0,
-/* 0x0442: init_unk_done */
-	0x0380e21b,
-	0x08048007,
-	0x010027f1,
-	0xcf0223f0,
-	0x34bd0022,
-	0xf1082595,
-	0xf0c00007,
-	0x05d00103,
-	0xf104bd00,
-	0xf0c10007,
-	0x05d00103,
-	0x9804bd00,
-	0x0f98000e,
-	0x5021f501,
-	0x002fbb01,
-	0x98003fbb,
-	0x0f98010e,
-	0x5021f502,
-	0x050e9801,
-	0xbb00effd,
-	0x3ebb002e,
-	0x020e9800,
-	0xf5030f98,
-	0x98015021,
-	0xeffd070e,
-	0x002ebb00,
-	0xb6003ebb,
-	0x07f10235,
-	0x03f0d300,
-	0x0003d001,
-	0x25b604bd,
-	0x0635b608,
-	0xb60120b6,
-	0x24b60130,
-	0x0834b608,
-	0xf5022fb9,
-	0xbb02d321,
-	0x07f1003f,
-	0x03f00100,
-	0x0003d002,
-	0x24bd04bd,
-	0xf11f29f0,
-	0xf0300007,
-	0x02d00203,
-/* 0x04f3: main */
-	0xf404bd00,
-	0x28f40031,
-	0x24d7f000,
-	0xf43921f4,
-	0xe4b0f401,
-	0x1e18f404,
-	0xf00181fe,
-	0x20bd0627,
-	0xb60412fd,
-	0x1efd01e4,
-	0x0018fe05,
-	0x05e821f5,
-/* 0x0523: main_not_ctx_xfer */
-	0x94d30ef4,
-	0xf5f010ef,
-	0x7e21f501,
-	0xc60ef403,
-/* 0x0530: ih */
-	0x88fe80f9,
-	0xf980f901,
-	0xf9a0f990,
-	0xf9d0f9b0,
-	0xbdf0f9e0,
-	0x00a7f104,
-	0x00a3f002,
-	0xc400aacf,
-	0x0bf404ab,
-	0x24d7f02c,
-	0x1a00e7f1,
-	0xcf00e3f0,
-	0xf7f100ee,
-	0xf3f01900,
-	0x00ffcf00,
-	0xf00421f4,
-	0x07f101e7,
-	0x03f01d00,
-	0x000ed000,
-/* 0x057e: ih_no_fifo */
-	0x07f104bd,
-	0x03f00100,
-	0x000ad000,
-	0xf0fc04bd,
-	0xd0fce0fc,
-	0xa0fcb0fc,
-	0x80fc90fc,
-	0xfc0088fe,
-	0x0032f480,
-/* 0x05a2: hub_barrier_done */
-	0xf7f001f8,
-	0x040e9801,
-	0xb904febb,
-	0xe7f102ff,
-	0xe3f09418,
-	0x9d21f440,
-/* 0x05ba: ctx_redswitch */
-	0xf7f000f8,
-	0x0007f120,
-	0x0103f085,
-	0xbd000fd0,
-	0x08e7f004,
-/* 0x05cc: ctx_redswitch_delay */
-	0xf401e2b6,
-	0xf5f1fd1b,
-	0xf5f10800,
-	0x07f10200,
-	0x03f08500,
-	0x000fd001,
-	0x00f804bd,
-/* 0x05e8: ctx_xfer */
-	0x810007f1,
-	0xd00203f0,
-	0x04bd000f,
-	0xf50711f4,
-/* 0x05fb: ctx_xfer_not_load */
-	0xf505ba21,
-	0xbd026a21,
-	0xfc07f124,
-	0x0203f047,
-	0xbd0002d0,
-	0x012cf004,
-	0xf10320b6,
-	0xf04afc07,
-	0x02d00203,
-	0xf004bd00,
-	0xa5f001ac,
-	0x00b7f102,
-	0x50b3f000,
-	0xb6040c98,
-	0xbcbb0fc4,
-	0x000c9800,
-	0xf0010d98,
-	0x21f500e7,
-	0xacf0016f,
-	0x00b7f101,
-	0x50b3f040,
-	0xb6040c98,
-	0xbcbb0fc4,
-	0x010c9800,
-	0x98020d98,
-	0xe7f1060f,
-	0x21f50800,
-	0xacf0016f,
-	0x04a5f001,
-	0x3000b7f1,
-	0x9850b3f0,
-	0xc4b6040c,
-	0x00bcbb0f,
-	0x98020c98,
-	0x0f98030d,
-	0x00e7f108,
-	0x6f21f502,
-	0x5e21f501,
-	0x0601f402,
-/* 0x0697: ctx_xfer_post */
-	0xf50712f4,
-/* 0x069b: ctx_xfer_done */
-	0xf5027f21,
-	0xf805a221,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
deleted file mode 100644
index b4ad18bf5a26..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
+++ /dev/null
@@ -1,696 +0,0 @@
-/* fuc microcode for nvc0 PGRAPH/HUB
- *
- * Copyright 2011 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#ifdef INCLUDE_DATA
-hub_mmio_list_head:	.b32 #hub_mmio_list_base
-hub_mmio_list_tail:	.b32 #hub_mmio_list_next
-
-gpc_count:		.b32 0
-rop_count:		.b32 0
-cmd_queue:		queue_init
-
-ctx_current:		.b32 0
-
-.align 256
-chan_data:
-chan_mmio_count:	.b32 0
-chan_mmio_address:	.b32 0
-
-.align 256
-xfer_data: 		.skip 256
-
-hub_mmio_list_base:
-.b32 0x0417e91c // 0x17e91c, 2
-hub_mmio_list_next:
-#endif
-
-#ifdef INCLUDE_CODE
-// reports an exception to the host
-//
-// In: $r15 error code (see os.h)
-//
-error:
-	nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15)
-	mov $r15 1
-	nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r15)
-	ret
-
-// HUB fuc initialisation, executed by triggering ucode start, will
-// fall through to main loop after completion.
-//
-// Output:
-//   CC_SCRATCH[0]:
-//	     31:31: set to signal completion
-//   CC_SCRATCH[1]:
-//	      31:0: total PGRAPH context size
-//
-init:
-	clear b32 $r0
-	mov $xdbase $r0
-
-	// setup stack
-	nv_iord($r1, NV_PGRAPH_FECS_CAPS, 0)
-	extr $r1 $r1 9:17
-	shl b32 $r1 8
-	mov $sp $r1
-
-	// enable fifo access
-	mov $r2 NV_PGRAPH_FECS_ACCESS_FIFO
-	nv_iowr(NV_PGRAPH_FECS_ACCESS, 0, $r2)
-
-	// setup i0 handler, and route all interrupts to it
-	mov $r1 #ih
-	mov $iv0 $r1
-
-	clear b32 $r2
-	nv_iowr(NV_PGRAPH_FECS_INTR_ROUTE, 0, $r2)
-
-	// route HUB_CHSW_PULSE to fuc interrupt 8
-	mov $r2 0x2003		// { HUB_CHSW_PULSE, ZERO } -> intr 8
-	nv_iowr(NV_PGRAPH_FECS_IROUTE, 0, $r2)
-
-	// not sure what these are, route them because NVIDIA does, and
-	// the IRQ handler will signal the host if we ever get one.. we
-	// may find out if/why we need to handle these if so..
-	//
-	mov $r2 0x2004		// { 0x04, ZERO } -> intr 9
-	nv_iowr(NV_PGRAPH_FECS_IROUTE, 1, $r2)
-	mov $r2 0x200b		// { HUB_FIRMWARE_MTHD, ZERO } -> intr 10
-	nv_iowr(NV_PGRAPH_FECS_IROUTE, 2, $r2)
-	mov $r2 0x200c		// { 0x0c, ZERO } -> intr 15
-	nv_iowr(NV_PGRAPH_FECS_IROUTE, 7, $r2)
-
-	// enable all INTR_UP interrupts
-	sub b32 $r3 $r0 1
-	nv_iowr(NV_PGRAPH_FECS_INTR_UP_EN, 0, $r3)
-
-	// enable fifo, ctxsw, 9, fwmthd, 15 interrupts
-	imm32($r2, 0x8704)
-	nv_iowr(NV_PGRAPH_FECS_INTR_EN_SET, 0, $r2)
-
-	// fifo level triggered, rest edge
-	mov $r2 NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL
-	nv_iowr(NV_PGRAPH_FECS_INTR_MODE, 0, $r2)
-
-	// enable interrupts
-	bset $flags ie0
-
-	// fetch enabled GPC/ROP counts
-	nv_rd32($r14, 0x409604)
-	extr $r1 $r15 16:20
-	st b32 D[$r0 + #rop_count] $r1
-	and $r15 0x1f
-	st b32 D[$r0 + #gpc_count] $r15
-
-	// set BAR_REQMASK to GPC mask
-	mov $r1 1
-	shl b32 $r1 $r15
-	sub b32 $r1 1
-	nv_iowr(NV_PGRAPH_FECS_BAR_MASK0, 0, $r1)
-	nv_iowr(NV_PGRAPH_FECS_BAR_MASK1, 0, $r1)
-
-	// context size calculation, reserve first 256 bytes for use by fuc
-	mov $r1 256
-
-	//
-	mov $r15 2
-	call(ctx_4170s)
-	call(ctx_4170w)
-	mov $r15 0x10
-	call(ctx_86c)
-
-	// calculate size of mmio context data
-	ld b32 $r14 D[$r0 + #hub_mmio_list_head]
-	ld b32 $r15 D[$r0 + #hub_mmio_list_tail]
-	call(mmctx_size)
-
-	// set mmctx base addresses now so we don't have to do it later,
-	// they don't (currently) ever change
-	shr b32 $r4 $r1 8
-	nv_iowr(NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE, 0, $r4)
-	nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE, 0, $r4)
-	add b32 $r3 0x1300
-	add b32 $r1 $r15
-	shr b32 $r15 2
-	nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_COUNT, 0, $r15) // wtf??
-
-	// strands, base offset needs to be aligned to 256 bytes
-	shr b32 $r1 8
-	add b32 $r1 1
-	shl b32 $r1 8
-	mov b32 $r15 $r1
-	call(strand_ctx_init)
-	add b32 $r1 $r15
-
-	// initialise each GPC in sequence by passing in the offset of its
-	// context data in GPCn_CC_SCRATCH[1], and starting its FUC (which
-	// has previously been uploaded by the host) running.
-	//
-	// the GPC fuc init sequence will set GPCn_CC_SCRATCH[0] bit 31
-	// when it has completed, and return the size of its context data
-	// in GPCn_CC_SCRATCH[1]
-	//
-	ld b32 $r3 D[$r0 + #gpc_count]
-	imm32($r4, 0x502000)
-	init_gpc:
-		// setup, and start GPC ucode running
-		add b32 $r14 $r4 0x804
-		mov b32 $r15 $r1
-		call(nv_wr32)			// CC_SCRATCH[1] = ctx offset
-		add b32 $r14 $r4 0x10c
-		clear b32 $r15
-		call(nv_wr32)
-		add b32 $r14 $r4 0x104
-		call(nv_wr32)			// ENTRY
-		add b32 $r14 $r4 0x100
-		mov $r15 2			// CTRL_START_TRIGGER
-		call(nv_wr32)			// CTRL
-
-		// wait for it to complete, and adjust context size
-		add b32 $r14 $r4 0x800
-		init_gpc_wait:
-			call(nv_rd32)
-			xbit $r15 $r15 31
-			bra e #init_gpc_wait
-		add b32 $r14 $r4 0x804
-		call(nv_rd32)
-		add b32 $r1 $r15
-
-		// next!
-		add b32 $r4 0x8000
-		sub b32 $r3 1
-		bra ne #init_gpc
-
-	//
-	mov $r15 0
-	call(ctx_86c)
-	mov $r15 0
-	call(ctx_4170s)
-
-	// save context size, and tell host we're ready
-	nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(1), 0, $r1)
-	clear b32 $r1
-	bset $r1 31
-	nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r1)
-
-// Main program loop, very simple, sleeps until woken up by the interrupt
-// handler, pulls a command from the queue and executes its handler
-//
-main:
-	// sleep until we have something to do
-	bset $flags $p0
-	sleep $p0
-	mov $r13 #cmd_queue
-	call(queue_get)
-	bra $p1 #main
-
-	// context switch, requested by GPU?
-	cmpu b32 $r14 0x4001
-	bra ne #main_not_ctx_switch
-		trace_set(T_AUTO)
-		nv_iord($r1, NV_PGRAPH_FECS_CHAN_ADDR, 0)
-		nv_iord($r2, NV_PGRAPH_FECS_CHAN_NEXT, 0)
-
-		xbit $r3 $r1 31
-		bra e #chsw_no_prev
-			xbit $r3 $r2 31
-			bra e #chsw_prev_no_next
-				push $r2
-				mov b32 $r2 $r1
-				trace_set(T_SAVE)
-				bclr $flags $p1
-				bset $flags $p2
-				call(ctx_xfer)
-				trace_clr(T_SAVE);
-				pop $r2
-				trace_set(T_LOAD);
-				bset $flags $p1
-				call(ctx_xfer)
-				trace_clr(T_LOAD);
-				bra #chsw_done
-			chsw_prev_no_next:
-				push $r2
-				mov b32 $r2 $r1
-				bclr $flags $p1
-				bclr $flags $p2
-				call(ctx_xfer)
-				pop $r2
-				nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2)
-				bra #chsw_done
-		chsw_no_prev:
-			xbit $r3 $r2 31
-			bra e #chsw_done
-				bset $flags $p1
-				bclr $flags $p2
-				call(ctx_xfer)
-
-		// ack the context switch request
-		chsw_done:
-		mov $r2 NV_PGRAPH_FECS_CHSW_ACK
-		nv_iowr(NV_PGRAPH_FECS_CHSW, 0, $r2)
-		trace_clr(T_AUTO)
-		bra #main
-
-	// request to set current channel? (*not* a context switch)
-	main_not_ctx_switch:
-	cmpu b32 $r14 0x0001
-	bra ne #main_not_ctx_chan
-		mov b32 $r2 $r15
-		call(ctx_chan)
-		bra #main_done
-
-	// request to store current channel context?
-	main_not_ctx_chan:
-	cmpu b32 $r14 0x0002
-	bra ne #main_not_ctx_save
-		trace_set(T_SAVE)
-		bclr $flags $p1
-		bclr $flags $p2
-		call(ctx_xfer)
-		trace_clr(T_SAVE)
-		bra #main_done
-
-	main_not_ctx_save:
-		shl b32 $r15 $r14 16
-		or $r15 E_BAD_COMMAND
-		call(error)
-		bra #main
-
-	main_done:
-	clear b32 $r2
-	bset $r2 31
-	nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r2)
-	bra #main
-
-// interrupt handler
-ih:
-	push $r8
-	mov $r8 $flags
-	push $r8
-	push $r9
-	push $r10
-	push $r11
-	push $r13
-	push $r14
-	push $r15
-	clear b32 $r0
-
-	// incoming fifo command?
-	nv_iord($r10, NV_PGRAPH_FECS_INTR, 0)
-	and $r11 $r10 NV_PGRAPH_FECS_INTR_FIFO
-	bra e #ih_no_fifo
-		// queue incoming fifo command for later processing
-		mov $r13 #cmd_queue
-		nv_iord($r14, NV_PGRAPH_FECS_FIFO_CMD, 0)
-		nv_iord($r15, NV_PGRAPH_FECS_FIFO_DATA, 0)
-		call(queue_put)
-		add b32 $r11 0x400
-		mov $r14 1
-		nv_iowr(NV_PGRAPH_FECS_FIFO_ACK, 0, $r14)
-
-	// context switch request?
-	ih_no_fifo:
-	and $r11 $r10 NV_PGRAPH_FECS_INTR_CHSW
-	bra e #ih_no_ctxsw
-		// enqueue a context switch for later processing
-		mov $r13 #cmd_queue
-		mov $r14 0x4001
-		call(queue_put)
-
-	// firmware method?
-	ih_no_ctxsw:
-	and $r11 $r10 NV_PGRAPH_FECS_INTR_FWMTHD
-	bra e #ih_no_fwmthd
-		// none we handle; report to host and ack
-		nv_rd32($r15, NV_PGRAPH_TRAPPED_DATA_LO)
-		nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(4), 0, $r15)
-		nv_rd32($r15, NV_PGRAPH_TRAPPED_ADDR)
-		nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(3), 0, $r15)
-		extr $r14 $r15 16:18
-		shl b32 $r14 $r14 2
-		imm32($r15, NV_PGRAPH_FE_OBJECT_TABLE(0))
-		add b32 $r14 $r15
-		call(nv_rd32)
-		nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(2), 0, $r15)
-		mov $r15 E_BAD_FWMTHD
-		call(error)
-		mov $r11 0x100
-		nv_wr32(0x400144, $r11)
-
-	// anything we didn't handle, bring it to the host's attention
-	ih_no_fwmthd:
-	mov $r11 0x504 // FIFO | CHSW | FWMTHD
-	not b32 $r11
-	and $r11 $r10 $r11
-	bra e #ih_no_other
-		nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r11)
-
-	// ack, and wake up main()
-	ih_no_other:
-	nv_iowr(NV_PGRAPH_FECS_INTR_ACK, 0, $r10)
-
-	pop $r15
-	pop $r14
-	pop $r13
-	pop $r11
-	pop $r10
-	pop $r9
-	pop $r8
-	mov $flags $r8
-	pop $r8
-	bclr $flags $p0
-	iret
-
-#if CHIPSET < GK100
-// Not real sure, but, MEM_CMD 7 will hang forever if this isn't done
-ctx_4160s:
-	mov $r15 1
-	nv_wr32(0x404160, $r15)
-	ctx_4160s_wait:
-		nv_rd32($r15, 0x404160)
-		xbit $r15 $r15 4
-		bra e #ctx_4160s_wait
-	ret
-
-// Without clearing again at end of xfer, some things cause PGRAPH
-// to hang with STATUS=0x00000007 until it's cleared.. fbcon can
-// still function with it set however...
-ctx_4160c:
-	clear b32 $r15
-	nv_wr32(0x404160, $r15)
-	ret
-#endif
-
-// Again, not real sure
-//
-// In: $r15 value to set 0x404170 to
-//
-ctx_4170s:
-	or $r15 0x10
-	nv_wr32(0x404170, $r15)
-	ret
-
-// Waits for a ctx_4170s() call to complete
-//
-ctx_4170w:
-	nv_rd32($r15, 0x404170)
-	and $r15 0x10
-	bra ne #ctx_4170w
-	ret
-
-// Disables various things, waits a bit, and re-enables them..
-//
-// Not sure how exactly this helps, perhaps "ENABLE" is not such a
-// good description for the bits we turn off?  Anyways, without this,
-// funny things happen.
-//
-ctx_redswitch:
-	mov $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC
-	or  $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP
-	or  $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC
-	or  $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN
-	nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14)
-	mov $r15 8
-	ctx_redswitch_delay:
-		sub b32 $r15 1
-		bra ne #ctx_redswitch_delay
-	or  $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP
-	or  $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN
-	nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14)
-	ret
-
-// Not a clue what this is for, except that unless the value is 0x10, the
-// strand context is saved (and presumably restored) incorrectly..
-//
-// In: $r15 value to set to (0x00/0x10 are used)
-//
-ctx_86c:
-	nv_iowr(NV_PGRAPH_FECS_UNK86C, 0, $r15)
-	nv_wr32(0x408a14, $r15)
-	nv_wr32(NV_PGRAPH_GPCX_GPCCS_UNK86C, $r15)
-	ret
-
-// In: $r15 NV_PGRAPH_FECS_MEM_CMD_*
-ctx_mem:
-	nv_iowr(NV_PGRAPH_FECS_MEM_CMD, 0, $r15)
-	ctx_mem_wait:
-		nv_iord($r15, NV_PGRAPH_FECS_MEM_CMD, 0)
-		or $r15 $r15
-		bra ne #ctx_mem_wait
-	ret
-
-// ctx_load - load's a channel's ctxctl data, and selects its vm
-//
-// In: $r2 channel address
-//
-ctx_load:
-	trace_set(T_CHAN)
-
-	// switch to channel, somewhat magic in parts..
-	mov $r10 12		// DONE_UNK12
-	call(wait_donez)
-	clear b32 $r15
-	nv_iowr(0x409a24, 0, $r15)
-	nv_iowr(NV_PGRAPH_FECS_CHAN_NEXT, 0, $r2)
-	nv_iowr(NV_PGRAPH_FECS_MEM_CHAN, 0, $r2)
-	mov $r15 NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN
-	call(ctx_mem)
-	nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2)
-
-	// load channel header, fetch PGRAPH context pointer
-	mov $xtargets $r0
-	bclr $r2 31
-	shl b32 $r2 4
-	add b32 $r2 2
-
-	trace_set(T_LCHAN)
-	nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r2)
-	imm32($r2, NV_PGRAPH_FECS_MEM_TARGET_UNK31)
-	or  $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM
-	nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2)
-	mov $r1 0x10			// chan + 0x0210
-	mov $r2 #xfer_data
-	sethi $r2 0x00020000		// 16 bytes
-	xdld $r1 $r2
-	xdwait
-	trace_clr(T_LCHAN)
-
-	// update current context
-	ld b32 $r1 D[$r0 + #xfer_data + 4]
-	shl b32 $r1 24
-	ld b32 $r2 D[$r0 + #xfer_data + 0]
-	shr b32 $r2 8
-	or $r1 $r2
-	st b32 D[$r0 + #ctx_current] $r1
-
-	// set transfer base to start of context, and fetch context header
-	trace_set(T_LCTXH)
-	nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r1)
-	mov $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VM
-	nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2)
-	mov $r1 #chan_data
-	sethi $r1 0x00060000		// 256 bytes
-	xdld $r0 $r1
-	xdwait
-	trace_clr(T_LCTXH)
-
-	trace_clr(T_CHAN)
-	ret
-
-// ctx_chan - handler for HUB_SET_CHAN command, will set a channel as
-//            the active channel for ctxctl, but not actually transfer
-//            any context data.  intended for use only during initial
-//            context construction.
-//
-// In: $r2 channel address
-//
-ctx_chan:
-#if CHIPSET < GK100
-	call(ctx_4160s)
-#endif
-	call(ctx_load)
-	mov $r10 12			// DONE_UNK12
-	call(wait_donez)
-	mov $r15 5 // MEM_CMD 5 ???
-	call(ctx_mem)
-#if CHIPSET < GK100
-	call(ctx_4160c)
-#endif
-	ret
-
-// Execute per-context state overrides list
-//
-// Only executed on the first load of a channel.  Might want to look into
-// removing this and having the host directly modify the channel's context
-// to change this state...  The nouveau DRM already builds this list as
-// it's definitely needed for NVIDIA's, so we may as well use it for now
-//
-// Input: $r1 mmio list length
-//
-ctx_mmio_exec:
-	// set transfer base to be the mmio list
-	ld b32 $r3 D[$r0 + #chan_mmio_address]
-	nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3)
-
-	clear b32 $r3
-	ctx_mmio_loop:
-		// fetch next 256 bytes of mmio list if necessary
-		and $r4 $r3 0xff
-		bra ne #ctx_mmio_pull
-			mov $r5 #xfer_data
-			sethi $r5 0x00060000	// 256 bytes
-			xdld $r3 $r5
-			xdwait
-
-		// execute a single list entry
-		ctx_mmio_pull:
-		ld b32 $r14 D[$r4 + #xfer_data + 0x00]
-		ld b32 $r15 D[$r4 + #xfer_data + 0x04]
-		call(nv_wr32)
-
-		// next!
-		add b32 $r3 8
-		sub b32 $r1 1
-		bra ne #ctx_mmio_loop
-
-	// set transfer base back to the current context
-	ctx_mmio_done:
-	ld b32 $r3 D[$r0 + #ctx_current]
-	nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3)
-
-	// disable the mmio list now, we don't need/want to execute it again
-	st b32 D[$r0 + #chan_mmio_count] $r0
-	mov $r1 #chan_data
-	sethi $r1 0x00060000		// 256 bytes
-	xdst $r0 $r1
-	xdwait
-	ret
-
-// Transfer HUB context data between GPU and storage area
-//
-// In: $r2 channel address
-//     $p1 clear on save, set on load
-//     $p2 set if opposite direction done/will be done, so:
-//		on save it means: "a load will follow this save"
-//		on load it means: "a save preceeded this load"
-//
-ctx_xfer:
-	// according to mwk, some kind of wait for idle
-	mov $r14 4
-	nv_iowr(0x409c08, 0, $r14)
-	ctx_xfer_idle:
-		nv_iord($r14, 0x409c00, 0)
-		and $r14 0x2000
-		bra ne #ctx_xfer_idle
-
-	bra not $p1 #ctx_xfer_pre
-	bra $p2 #ctx_xfer_pre_load
-	ctx_xfer_pre:
-		mov $r15 0x10
-		call(ctx_86c)
-#if CHIPSET < GK100
-		call(ctx_4160s)
-#endif
-		bra not $p1 #ctx_xfer_exec
-
-	ctx_xfer_pre_load:
-		mov $r15 2
-		call(ctx_4170s)
-		call(ctx_4170w)
-		call(ctx_redswitch)
-		clear b32 $r15
-		call(ctx_4170s)
-		call(ctx_load)
-
-	// fetch context pointer, and initiate xfer on all GPCs
-	ctx_xfer_exec:
-	ld b32 $r1 D[$r0 + #ctx_current]
-
-	clear b32 $r2
-	nv_iowr(NV_PGRAPH_FECS_BAR, 0, $r2)
-
-	nv_wr32(0x41a500, $r1)	// GPC_BCAST_WRCMD_DATA = ctx pointer
-	xbit $r15 $flags $p1
-	xbit $r2 $flags $p2
-	shl b32 $r2 1
-	or $r15 $r2
-	nv_wr32(0x41a504, $r15)	// GPC_BCAST_WRCMD_CMD = GPC_XFER(type)
-
-	// strands
-	call(strand_pre)
-	clear b32 $r2
-	nv_iowr(NV_PGRAPH_FECS_STRAND_SELECT, 0x3f, $r2)
-	xbit $r2 $flags $p1	// SAVE/LOAD
-	add b32 $r2 NV_PGRAPH_FECS_STRAND_CMD_SAVE
-	nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r2)
-
-	// mmio context
-	xbit $r10 $flags $p1	// direction
-	or $r10 6		// first, last
-	mov $r11 0		// base = 0
-	ld b32 $r12 D[$r0 + #hub_mmio_list_head]
-	ld b32 $r13 D[$r0 + #hub_mmio_list_tail]
-	mov $r14 0		// not multi
-	call(mmctx_xfer)
-
-	// wait for GPCs to all complete
-	mov $r10 8		// DONE_BAR
-	call(wait_doneo)
-
-	// wait for strand xfer to complete
-	call(strand_wait)
-
-	// post-op
-	bra $p1 #ctx_xfer_post
-		mov $r10 12		// DONE_UNK12
-		call(wait_donez)
-		mov $r15 5 // MEM_CMD 5 ???
-		call(ctx_mem)
-
-	bra $p2 #ctx_xfer_done
-	ctx_xfer_post:
-		mov $r15 2
-		call(ctx_4170s)
-		clear b32 $r15
-		call(ctx_86c)
-		call(strand_post)
-		call(ctx_4170w)
-		clear b32 $r15
-		call(ctx_4170s)
-
-		bra not $p1 #ctx_xfer_no_post_mmio
-		ld b32 $r1 D[$r0 + #chan_mmio_count]
-		or $r1 $r1
-		bra e #ctx_xfer_no_post_mmio
-			call(ctx_mmio_exec)
-
-		ctx_xfer_no_post_mmio:
-#if CHIPSET < GK100
-		call(ctx_4160c)
-#endif
-
-	ctx_xfer_done:
-	ret
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5 b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5
deleted file mode 100644
index 27591b3086a5..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#define CHIPSET GK208
-#include "macros.fuc"
-
-.section #gm107_grhub_data
-#define INCLUDE_DATA
-#include "com.fuc"
-#include "hub.fuc"
-#undef INCLUDE_DATA
-
-.section #gm107_grhub_code
-#define INCLUDE_CODE
-bra #init
-#include "com.fuc"
-#include "hub.fuc"
-.align 256
-#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h
deleted file mode 100644
index 5f953c5c20b7..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h
+++ /dev/null
@@ -1,916 +0,0 @@
-uint32_t gm107_grhub_data[] = {
-/* 0x0000: hub_mmio_list_head */
-	0x00000300,
-/* 0x0004: hub_mmio_list_tail */
-	0x00000304,
-/* 0x0008: gpc_count */
-	0x00000000,
-/* 0x000c: rop_count */
-	0x00000000,
-/* 0x0010: cmd_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0058: ctx_current */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0100: chan_data */
-/* 0x0100: chan_mmio_count */
-	0x00000000,
-/* 0x0104: chan_mmio_address */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0200: xfer_data */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0300: hub_mmio_list_base */
-	0x0417e91c,
-};
-
-uint32_t gm107_grhub_code[] = {
-	0x030e0ef5,
-/* 0x0004: queue_put */
-	0x9800d898,
-	0x86f001d9,
-	0xf489a408,
-	0x020f0b1b,
-	0x0002f87e,
-/* 0x001a: queue_put_next */
-	0x98c400f8,
-	0x0384b607,
-	0xb6008dbb,
-	0x8eb50880,
-	0x018fb500,
-	0xf00190b6,
-	0xd9b50f94,
-/* 0x0037: queue_get */
-	0xf400f801,
-	0xd8980131,
-	0x01d99800,
-	0x0bf489a4,
-	0x0789c421,
-	0xbb0394b6,
-	0x90b6009d,
-	0x009e9808,
-	0xb6019f98,
-	0x84f00180,
-	0x00d8b50f,
-/* 0x0063: queue_get_done */
-	0xf80132f4,
-/* 0x0065: nv_rd32 */
-	0xf0ecb200,
-	0x00801fc9,
-	0x0cf601ca,
-/* 0x0073: nv_rd32_wait */
-	0x8c04bd00,
-	0xcf01ca00,
-	0xccc800cc,
-	0xf61bf41f,
-	0xec7e060a,
-	0x008f0000,
-	0xffcf01cb,
-/* 0x008f: nv_wr32 */
-	0x8000f800,
-	0xf601cc00,
-	0x04bd000f,
-	0xc9f0ecb2,
-	0x1ec9f01f,
-	0x01ca0080,
-	0xbd000cf6,
-/* 0x00a9: nv_wr32_wait */
-	0xca008c04,
-	0x00cccf01,
-	0xf41fccc8,
-	0x00f8f61b,
-/* 0x00b8: wait_donez */
-	0x99f094bd,
-	0x37008000,
-	0x0009f602,
-	0x008004bd,
-	0x0af60206,
-/* 0x00cf: wait_donez_ne */
-	0x8804bd00,
-	0xcf010000,
-	0x8aff0088,
-	0xf61bf488,
-	0x99f094bd,
-	0x17008000,
-	0x0009f602,
-	0x00f804bd,
-/* 0x00ec: wait_doneo */
-	0x99f094bd,
-	0x37008000,
-	0x0009f602,
-	0x008004bd,
-	0x0af60206,
-/* 0x0103: wait_doneo_e */
-	0x8804bd00,
-	0xcf010000,
-	0x8aff0088,
-	0xf60bf488,
-	0x99f094bd,
-	0x17008000,
-	0x0009f602,
-	0x00f804bd,
-/* 0x0120: mmctx_size */
-/* 0x0122: nv_mmctx_size_loop */
-	0xe89894bd,
-	0x1a85b600,
-	0xb60180b6,
-	0x98bb0284,
-	0x04e0b600,
-	0x1bf4efa4,
-	0xf89fb2ec,
-/* 0x013d: mmctx_xfer */
-	0xf094bd00,
-	0x00800199,
-	0x09f60237,
-	0xbd04bd00,
-	0x05bbfd94,
-	0x800f0bf4,
-	0xf601c400,
-	0x04bd000b,
-/* 0x015f: mmctx_base_disabled */
-	0xfd0099f0,
-	0x0bf405ee,
-	0xc6008018,
-	0x000ef601,
-	0x008004bd,
-	0x0ff601c7,
-	0xf004bd00,
-/* 0x017a: mmctx_multi_disabled */
-	0xabc80199,
-	0x10b4b600,
-	0xc80cb9f0,
-	0xe4b601ae,
-	0x05befd11,
-	0x01c50080,
-	0xbd000bf6,
-/* 0x0195: mmctx_exec_loop */
-/* 0x0195: mmctx_wait_free */
-	0xc5008e04,
-	0x00eecf01,
-	0xf41fe4f0,
-	0xce98f60b,
-	0x05e9fd00,
-	0x01c80080,
-	0xbd000ef6,
-	0x04c0b604,
-	0x1bf4cda4,
-	0x02abc8df,
-/* 0x01bf: mmctx_fini_wait */
-	0x8b1c1bf4,
-	0xcf01c500,
-	0xb4f000bb,
-	0x10b4b01f,
-	0x0af31bf4,
-	0x00b87e05,
-	0x250ef400,
-/* 0x01d8: mmctx_stop */
-	0xb600abc8,
-	0xb9f010b4,
-	0x12b9f00c,
-	0x01c50080,
-	0xbd000bf6,
-/* 0x01ed: mmctx_stop_wait */
-	0xc5008b04,
-	0x00bbcf01,
-	0xf412bbc8,
-/* 0x01fa: mmctx_done */
-	0x94bdf61b,
-	0x800199f0,
-	0xf6021700,
-	0x04bd0009,
-/* 0x020a: strand_wait */
-	0xa0f900f8,
-	0xb87e020a,
-	0xa0fc0000,
-/* 0x0216: strand_pre */
-	0x0c0900f8,
-	0x024afc80,
-	0xbd0009f6,
-	0x020a7e04,
-/* 0x0227: strand_post */
-	0x0900f800,
-	0x4afc800d,
-	0x0009f602,
-	0x0a7e04bd,
-	0x00f80002,
-/* 0x0238: strand_set */
-	0xfc800f0c,
-	0x0cf6024f,
-	0x0c04bd00,
-	0x4afc800b,
-	0x000cf602,
-	0xfc8004bd,
-	0x0ef6024f,
-	0x0c04bd00,
-	0x4afc800a,
-	0x000cf602,
-	0x0a7e04bd,
-	0x00f80002,
-/* 0x0268: strand_ctx_init */
-	0x99f094bd,
-	0x37008003,
-	0x0009f602,
-	0x167e04bd,
-	0x030e0002,
-	0x0002387e,
-	0xfc80c4bd,
-	0x0cf60247,
-	0x0c04bd00,
-	0x4afc8001,
-	0x000cf602,
-	0x0a7e04bd,
-	0x0c920002,
-	0x46fc8001,
-	0x000cf602,
-	0x020c04bd,
-	0x024afc80,
-	0xbd000cf6,
-	0x020a7e04,
-	0x02277e00,
-	0x42008800,
-	0x20008902,
-	0x0099cf02,
-/* 0x02c7: ctx_init_strand_loop */
-	0xf608fe95,
-	0x8ef6008e,
-	0x808acf40,
-	0xb606a5b6,
-	0xeabb01a0,
-	0x0480b600,
-	0xf40192b6,
-	0xe4b6e81b,
-	0xf2efbc08,
-	0x99f094bd,
-	0x17008003,
-	0x0009f602,
-	0x00f804bd,
-/* 0x02f8: error */
-	0x02050080,
-	0xbd000ff6,
-	0x80010f04,
-	0xf6030700,
-	0x04bd000f,
-/* 0x030e: init */
-	0x04bd00f8,
-	0x410007fe,
-	0x11cf4200,
-	0x0911e700,
-	0x0814b601,
-	0x020014fe,
-	0x12004002,
-	0xbd0002f6,
-	0x05c94104,
-	0xbd0010fe,
-	0x07004024,
-	0xbd0002f6,
-	0x20034204,
-	0x01010080,
-	0xbd0002f6,
-	0x20044204,
-	0x01010480,
-	0xbd0002f6,
-	0x200b4204,
-	0x01010880,
-	0xbd0002f6,
-	0x200c4204,
-	0x01011c80,
-	0xbd0002f6,
-	0x01039204,
-	0x03090080,
-	0xbd0003f6,
-	0x87044204,
-	0xf6040040,
-	0x04bd0002,
-	0x00400402,
-	0x0002f603,
-	0x31f404bd,
-	0x96048e10,
-	0x00657e40,
-	0xc7feb200,
-	0x01b590f1,
-	0x1ff4f003,
-	0x01020fb5,
-	0x041fbb01,
-	0x800112b6,
-	0xf6010300,
-	0x04bd0001,
-	0x01040080,
-	0xbd0001f6,
-	0x01004104,
-	0xa87e020f,
-	0xb77e0006,
-	0x100f0006,
-	0x0006f97e,
-	0x98000e98,
-	0x207e010f,
-	0x14950001,
-	0xc0008008,
-	0x0004f601,
-	0x008004bd,
-	0x04f601c1,
-	0xb704bd00,
-	0xbb130030,
-	0xf5b6001f,
-	0xd3008002,
-	0x000ff601,
-	0x15b604bd,
-	0x0110b608,
-	0xb20814b6,
-	0x02687e1f,
-	0x001fbb00,
-	0x84020398,
-/* 0x041f: init_gpc */
-	0xb8502000,
-	0x0008044e,
-	0x8f7e1fb2,
-	0x4eb80000,
-	0xbd00010c,
-	0x008f7ef4,
-	0x044eb800,
-	0x8f7e0001,
-	0x4eb80000,
-	0x0f000100,
-	0x008f7e02,
-	0x004eb800,
-/* 0x044e: init_gpc_wait */
-	0x657e0008,
-	0xffc80000,
-	0xf90bf41f,
-	0x08044eb8,
-	0x00657e00,
-	0x001fbb00,
-	0x800040b7,
-	0xf40132b6,
-	0x000fb41b,
-	0x0006f97e,
-	0xa87e000f,
-	0x00800006,
-	0x01f60201,
-	0xbd04bd00,
-	0x1f19f014,
-	0x02300080,
-	0xbd0001f6,
-/* 0x0491: main */
-	0x0031f404,
-	0x0d0028f4,
-	0x00377e10,
-	0xf401f400,
-	0x4001e4b1,
-	0x00c71bf5,
-	0x99f094bd,
-	0x37008004,
-	0x0009f602,
-	0x008104bd,
-	0x11cf02c0,
-	0xc1008200,
-	0x0022cf02,
-	0xf41f13c8,
-	0x23c8770b,
-	0x550bf41f,
-	0x12b220f9,
-	0x99f094bd,
-	0x37008007,
-	0x0009f602,
-	0x32f404bd,
-	0x0231f401,
-	0x00087c7e,
-	0x99f094bd,
-	0x17008007,
-	0x0009f602,
-	0x20fc04bd,
-	0x99f094bd,
-	0x37008006,
-	0x0009f602,
-	0x31f404bd,
-	0x087c7e01,
-	0xf094bd00,
-	0x00800699,
-	0x09f60217,
-	0xf404bd00,
-/* 0x0522: chsw_prev_no_next */
-	0x20f92f0e,
-	0x32f412b2,
-	0x0232f401,
-	0x00087c7e,
-	0x008020fc,
-	0x02f602c0,
-	0xf404bd00,
-/* 0x053e: chsw_no_prev */
-	0x23c8130e,
-	0x0d0bf41f,
-	0xf40131f4,
-	0x7c7e0232,
-/* 0x054e: chsw_done */
-	0x01020008,
-	0x02c30080,
-	0xbd0002f6,
-	0xf094bd04,
-	0x00800499,
-	0x09f60217,
-	0xf504bd00,
-/* 0x056b: main_not_ctx_switch */
-	0xb0ff2a0e,
-	0x1bf401e4,
-	0x7ef2b20c,
-	0xf400081c,
-/* 0x057a: main_not_ctx_chan */
-	0xe4b0400e,
-	0x2c1bf402,
-	0x99f094bd,
-	0x37008007,
-	0x0009f602,
-	0x32f404bd,
-	0x0232f401,
-	0x00087c7e,
-	0x99f094bd,
-	0x17008007,
-	0x0009f602,
-	0x0ef404bd,
-/* 0x05a9: main_not_ctx_save */
-	0x10ef9411,
-	0x7e01f5f0,
-	0xf50002f8,
-/* 0x05b7: main_done */
-	0xbdfede0e,
-	0x1f29f024,
-	0x02300080,
-	0xbd0002f6,
-	0xcc0ef504,
-/* 0x05c9: ih */
-	0xfe80f9fe,
-	0x80f90188,
-	0xa0f990f9,
-	0xd0f9b0f9,
-	0xf0f9e0f9,
-	0x004a04bd,
-	0x00aacf02,
-	0xf404abc4,
-	0x100d230b,
-	0xcf1a004e,
-	0x004f00ee,
-	0x00ffcf19,
-	0x0000047e,
-	0x0400b0b7,
-	0x0040010e,
-	0x000ef61d,
-/* 0x060a: ih_no_fifo */
-	0xabe404bd,
-	0x0bf40100,
-	0x4e100d0c,
-	0x047e4001,
-/* 0x061a: ih_no_ctxsw */
-	0xabe40000,
-	0x0bf40400,
-	0x07088e56,
-	0x00657e40,
-	0x80ffb200,
-	0xf6020400,
-	0x04bd000f,
-	0x4007048e,
-	0x0000657e,
-	0x0080ffb2,
-	0x0ff60203,
-	0xc704bd00,
-	0xee9450fe,
-	0x07008f02,
-	0x00efbb40,
-	0x0000657e,
-	0x02020080,
-	0xbd000ff6,
-	0x7e030f04,
-	0x4b0002f8,
-	0xbfb20100,
-	0x4001448e,
-	0x00008f7e,
-/* 0x0674: ih_no_fwmthd */
-	0xbd05044b,
-	0xb4abffb0,
-	0x800c0bf4,
-	0xf6030700,
-	0x04bd000b,
-/* 0x0688: ih_no_other */
-	0xf6010040,
-	0x04bd000a,
-	0xe0fcf0fc,
-	0xb0fcd0fc,
-	0x90fca0fc,
-	0x88fe80fc,
-	0xf480fc00,
-	0x01f80032,
-/* 0x06a8: ctx_4170s */
-	0xb210f5f0,
-	0x41708eff,
-	0x008f7e40,
-/* 0x06b7: ctx_4170w */
-	0x8e00f800,
-	0x7e404170,
-	0xb2000065,
-	0x10f4f0ff,
-	0xf8f31bf4,
-/* 0x06c9: ctx_redswitch */
-	0x02004e00,
-	0xf040e5f0,
-	0xe5f020e5,
-	0x85008010,
-	0x000ef601,
-	0x080f04bd,
-/* 0x06e0: ctx_redswitch_delay */
-	0xf401f2b6,
-	0xe5f1fd1b,
-	0xe5f10400,
-	0x00800100,
-	0x0ef60185,
-	0xf804bd00,
-/* 0x06f9: ctx_86c */
-	0x23008000,
-	0x000ff602,
-	0xffb204bd,
-	0x408a148e,
-	0x00008f7e,
-	0x8c8effb2,
-	0x8f7e41a8,
-	0x00f80000,
-/* 0x0718: ctx_mem */
-	0x02840080,
-	0xbd000ff6,
-/* 0x0721: ctx_mem_wait */
-	0x84008f04,
-	0x00ffcf02,
-	0xf405fffd,
-	0x00f8f61b,
-/* 0x0730: ctx_load */
-	0x99f094bd,
-	0x37008005,
-	0x0009f602,
-	0x0c0a04bd,
-	0x0000b87e,
-	0x0080f4bd,
-	0x0ff60289,
-	0x8004bd00,
-	0xf602c100,
-	0x04bd0002,
-	0x02830080,
-	0xbd0002f6,
-	0x7e070f04,
-	0x80000718,
-	0xf602c000,
-	0x04bd0002,
-	0xf0000bfe,
-	0x24b61f2a,
-	0x0220b604,
-	0x99f094bd,
-	0x37008008,
-	0x0009f602,
-	0x008004bd,
-	0x02f60281,
-	0xd204bd00,
-	0x80000000,
-	0x800225f0,
-	0xf6028800,
-	0x04bd0002,
-	0x00421001,
-	0x0223f002,
-	0xf80512fa,
-	0xf094bd03,
-	0x00800899,
-	0x09f60217,
-	0x9804bd00,
-	0x14b68101,
-	0x80029818,
-	0xfd0825b6,
-	0x01b50512,
-	0xf094bd16,
-	0x00800999,
-	0x09f60237,
-	0x8004bd00,
-	0xf6028100,
-	0x04bd0001,
-	0x00800102,
-	0x02f60288,
-	0x4104bd00,
-	0x13f00100,
-	0x0501fa06,
-	0x94bd03f8,
-	0x800999f0,
-	0xf6021700,
-	0x04bd0009,
-	0x99f094bd,
-	0x17008005,
-	0x0009f602,
-	0x00f804bd,
-/* 0x081c: ctx_chan */
-	0x0007307e,
-	0xb87e0c0a,
-	0x050f0000,
-	0x0007187e,
-/* 0x082e: ctx_mmio_exec */
-	0x039800f8,
-	0x81008041,
-	0x0003f602,
-	0x34bd04bd,
-/* 0x083c: ctx_mmio_loop */
-	0xf4ff34c4,
-	0x00450e1b,
-	0x0653f002,
-	0xf80535fa,
-/* 0x084d: ctx_mmio_pull */
-	0x804e9803,
-	0x7e814f98,
-	0xb600008f,
-	0x12b60830,
-	0xdf1bf401,
-/* 0x0860: ctx_mmio_done */
-	0x80160398,
-	0xf6028100,
-	0x04bd0003,
-	0x414000b5,
-	0x13f00100,
-	0x0601fa06,
-	0x00f803f8,
-/* 0x087c: ctx_xfer */
-	0x0080040e,
-	0x0ef60302,
-/* 0x0887: ctx_xfer_idle */
-	0x8e04bd00,
-	0xcf030000,
-	0xe4f100ee,
-	0x1bf42000,
-	0x0611f4f5,
-/* 0x089b: ctx_xfer_pre */
-	0x0f0c02f4,
-	0x06f97e10,
-	0x1b11f400,
-/* 0x08a4: ctx_xfer_pre_load */
-	0xa87e020f,
-	0xb77e0006,
-	0xc97e0006,
-	0xf4bd0006,
-	0x0006a87e,
-	0x0007307e,
-/* 0x08bc: ctx_xfer_exec */
-	0xbd160198,
-	0x05008024,
-	0x0002f601,
-	0x1fb204bd,
-	0x41a5008e,
-	0x00008f7e,
-	0xf001fcf0,
-	0x24b6022c,
-	0x05f2fd01,
-	0x048effb2,
-	0x8f7e41a5,
-	0x167e0000,
-	0x24bd0002,
-	0x0247fc80,
-	0xbd0002f6,
-	0x012cf004,
-	0x800320b6,
-	0xf6024afc,
-	0x04bd0002,
-	0xf001acf0,
-	0x000b06a5,
-	0x98000c98,
-	0x000e010d,
-	0x00013d7e,
-	0xec7e080a,
-	0x0a7e0000,
-	0x01f40002,
-	0x7e0c0a12,
-	0x0f0000b8,
-	0x07187e05,
-	0x2d02f400,
-/* 0x0938: ctx_xfer_post */
-	0xa87e020f,
-	0xf4bd0006,
-	0x0006f97e,
-	0x0002277e,
-	0x0006b77e,
-	0xa87ef4bd,
-	0x11f40006,
-	0x40019810,
-	0xf40511fd,
-	0x2e7e070b,
-/* 0x0962: ctx_xfer_no_post_mmio */
-/* 0x0962: ctx_xfer_done */
-	0x00f80008,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5 b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5
deleted file mode 100644
index 7c5d25630fa8..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#define CHIPSET GK208
-#include "macros.fuc"
-
-.section #nv108_grhub_data
-#define INCLUDE_DATA
-#include "com.fuc"
-#include "hub.fuc"
-#undef INCLUDE_DATA
-
-.section #nv108_grhub_code
-#define INCLUDE_CODE
-bra #init
-#include "com.fuc"
-#include "hub.fuc"
-.align 256
-#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h
deleted file mode 100644
index e49b5a877ae4..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h
+++ /dev/null
@@ -1,916 +0,0 @@
-uint32_t nv108_grhub_data[] = {
-/* 0x0000: hub_mmio_list_head */
-	0x00000300,
-/* 0x0004: hub_mmio_list_tail */
-	0x00000304,
-/* 0x0008: gpc_count */
-	0x00000000,
-/* 0x000c: rop_count */
-	0x00000000,
-/* 0x0010: cmd_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0058: ctx_current */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0100: chan_data */
-/* 0x0100: chan_mmio_count */
-	0x00000000,
-/* 0x0104: chan_mmio_address */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0200: xfer_data */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0300: hub_mmio_list_base */
-	0x0417e91c,
-};
-
-uint32_t nv108_grhub_code[] = {
-	0x030e0ef5,
-/* 0x0004: queue_put */
-	0x9800d898,
-	0x86f001d9,
-	0xf489a408,
-	0x020f0b1b,
-	0x0002f87e,
-/* 0x001a: queue_put_next */
-	0x98c400f8,
-	0x0384b607,
-	0xb6008dbb,
-	0x8eb50880,
-	0x018fb500,
-	0xf00190b6,
-	0xd9b50f94,
-/* 0x0037: queue_get */
-	0xf400f801,
-	0xd8980131,
-	0x01d99800,
-	0x0bf489a4,
-	0x0789c421,
-	0xbb0394b6,
-	0x90b6009d,
-	0x009e9808,
-	0xb6019f98,
-	0x84f00180,
-	0x00d8b50f,
-/* 0x0063: queue_get_done */
-	0xf80132f4,
-/* 0x0065: nv_rd32 */
-	0xf0ecb200,
-	0x00801fc9,
-	0x0cf601ca,
-/* 0x0073: nv_rd32_wait */
-	0x8c04bd00,
-	0xcf01ca00,
-	0xccc800cc,
-	0xf61bf41f,
-	0xec7e060a,
-	0x008f0000,
-	0xffcf01cb,
-/* 0x008f: nv_wr32 */
-	0x8000f800,
-	0xf601cc00,
-	0x04bd000f,
-	0xc9f0ecb2,
-	0x1ec9f01f,
-	0x01ca0080,
-	0xbd000cf6,
-/* 0x00a9: nv_wr32_wait */
-	0xca008c04,
-	0x00cccf01,
-	0xf41fccc8,
-	0x00f8f61b,
-/* 0x00b8: wait_donez */
-	0x99f094bd,
-	0x37008000,
-	0x0009f602,
-	0x008004bd,
-	0x0af60206,
-/* 0x00cf: wait_donez_ne */
-	0x8804bd00,
-	0xcf010000,
-	0x8aff0088,
-	0xf61bf488,
-	0x99f094bd,
-	0x17008000,
-	0x0009f602,
-	0x00f804bd,
-/* 0x00ec: wait_doneo */
-	0x99f094bd,
-	0x37008000,
-	0x0009f602,
-	0x008004bd,
-	0x0af60206,
-/* 0x0103: wait_doneo_e */
-	0x8804bd00,
-	0xcf010000,
-	0x8aff0088,
-	0xf60bf488,
-	0x99f094bd,
-	0x17008000,
-	0x0009f602,
-	0x00f804bd,
-/* 0x0120: mmctx_size */
-/* 0x0122: nv_mmctx_size_loop */
-	0xe89894bd,
-	0x1a85b600,
-	0xb60180b6,
-	0x98bb0284,
-	0x04e0b600,
-	0x1bf4efa4,
-	0xf89fb2ec,
-/* 0x013d: mmctx_xfer */
-	0xf094bd00,
-	0x00800199,
-	0x09f60237,
-	0xbd04bd00,
-	0x05bbfd94,
-	0x800f0bf4,
-	0xf601c400,
-	0x04bd000b,
-/* 0x015f: mmctx_base_disabled */
-	0xfd0099f0,
-	0x0bf405ee,
-	0xc6008018,
-	0x000ef601,
-	0x008004bd,
-	0x0ff601c7,
-	0xf004bd00,
-/* 0x017a: mmctx_multi_disabled */
-	0xabc80199,
-	0x10b4b600,
-	0xc80cb9f0,
-	0xe4b601ae,
-	0x05befd11,
-	0x01c50080,
-	0xbd000bf6,
-/* 0x0195: mmctx_exec_loop */
-/* 0x0195: mmctx_wait_free */
-	0xc5008e04,
-	0x00eecf01,
-	0xf41fe4f0,
-	0xce98f60b,
-	0x05e9fd00,
-	0x01c80080,
-	0xbd000ef6,
-	0x04c0b604,
-	0x1bf4cda4,
-	0x02abc8df,
-/* 0x01bf: mmctx_fini_wait */
-	0x8b1c1bf4,
-	0xcf01c500,
-	0xb4f000bb,
-	0x10b4b01f,
-	0x0af31bf4,
-	0x00b87e05,
-	0x250ef400,
-/* 0x01d8: mmctx_stop */
-	0xb600abc8,
-	0xb9f010b4,
-	0x12b9f00c,
-	0x01c50080,
-	0xbd000bf6,
-/* 0x01ed: mmctx_stop_wait */
-	0xc5008b04,
-	0x00bbcf01,
-	0xf412bbc8,
-/* 0x01fa: mmctx_done */
-	0x94bdf61b,
-	0x800199f0,
-	0xf6021700,
-	0x04bd0009,
-/* 0x020a: strand_wait */
-	0xa0f900f8,
-	0xb87e020a,
-	0xa0fc0000,
-/* 0x0216: strand_pre */
-	0x0c0900f8,
-	0x024afc80,
-	0xbd0009f6,
-	0x020a7e04,
-/* 0x0227: strand_post */
-	0x0900f800,
-	0x4afc800d,
-	0x0009f602,
-	0x0a7e04bd,
-	0x00f80002,
-/* 0x0238: strand_set */
-	0xfc800f0c,
-	0x0cf6024f,
-	0x0c04bd00,
-	0x4afc800b,
-	0x000cf602,
-	0xfc8004bd,
-	0x0ef6024f,
-	0x0c04bd00,
-	0x4afc800a,
-	0x000cf602,
-	0x0a7e04bd,
-	0x00f80002,
-/* 0x0268: strand_ctx_init */
-	0x99f094bd,
-	0x37008003,
-	0x0009f602,
-	0x167e04bd,
-	0x030e0002,
-	0x0002387e,
-	0xfc80c4bd,
-	0x0cf60247,
-	0x0c04bd00,
-	0x4afc8001,
-	0x000cf602,
-	0x0a7e04bd,
-	0x0c920002,
-	0x46fc8001,
-	0x000cf602,
-	0x020c04bd,
-	0x024afc80,
-	0xbd000cf6,
-	0x020a7e04,
-	0x02277e00,
-	0x42008800,
-	0x20008902,
-	0x0099cf02,
-/* 0x02c7: ctx_init_strand_loop */
-	0xf608fe95,
-	0x8ef6008e,
-	0x808acf40,
-	0xb606a5b6,
-	0xeabb01a0,
-	0x0480b600,
-	0xf40192b6,
-	0xe4b6e81b,
-	0xf2efbc08,
-	0x99f094bd,
-	0x17008003,
-	0x0009f602,
-	0x00f804bd,
-/* 0x02f8: error */
-	0x02050080,
-	0xbd000ff6,
-	0x80010f04,
-	0xf6030700,
-	0x04bd000f,
-/* 0x030e: init */
-	0x04bd00f8,
-	0x410007fe,
-	0x11cf4200,
-	0x0911e700,
-	0x0814b601,
-	0x020014fe,
-	0x12004002,
-	0xbd0002f6,
-	0x05c94104,
-	0xbd0010fe,
-	0x07004024,
-	0xbd0002f6,
-	0x20034204,
-	0x01010080,
-	0xbd0002f6,
-	0x20044204,
-	0x01010480,
-	0xbd0002f6,
-	0x200b4204,
-	0x01010880,
-	0xbd0002f6,
-	0x200c4204,
-	0x01011c80,
-	0xbd0002f6,
-	0x01039204,
-	0x03090080,
-	0xbd0003f6,
-	0x87044204,
-	0xf6040040,
-	0x04bd0002,
-	0x00400402,
-	0x0002f603,
-	0x31f404bd,
-	0x96048e10,
-	0x00657e40,
-	0xc7feb200,
-	0x01b590f1,
-	0x1ff4f003,
-	0x01020fb5,
-	0x041fbb01,
-	0x800112b6,
-	0xf6010300,
-	0x04bd0001,
-	0x01040080,
-	0xbd0001f6,
-	0x01004104,
-	0xa87e020f,
-	0xb77e0006,
-	0x100f0006,
-	0x0006f97e,
-	0x98000e98,
-	0x207e010f,
-	0x14950001,
-	0xc0008008,
-	0x0004f601,
-	0x008004bd,
-	0x04f601c1,
-	0xb704bd00,
-	0xbb130030,
-	0xf5b6001f,
-	0xd3008002,
-	0x000ff601,
-	0x15b604bd,
-	0x0110b608,
-	0xb20814b6,
-	0x02687e1f,
-	0x001fbb00,
-	0x84020398,
-/* 0x041f: init_gpc */
-	0xb8502000,
-	0x0008044e,
-	0x8f7e1fb2,
-	0x4eb80000,
-	0xbd00010c,
-	0x008f7ef4,
-	0x044eb800,
-	0x8f7e0001,
-	0x4eb80000,
-	0x0f000100,
-	0x008f7e02,
-	0x004eb800,
-/* 0x044e: init_gpc_wait */
-	0x657e0008,
-	0xffc80000,
-	0xf90bf41f,
-	0x08044eb8,
-	0x00657e00,
-	0x001fbb00,
-	0x800040b7,
-	0xf40132b6,
-	0x000fb41b,
-	0x0006f97e,
-	0xa87e000f,
-	0x00800006,
-	0x01f60201,
-	0xbd04bd00,
-	0x1f19f014,
-	0x02300080,
-	0xbd0001f6,
-/* 0x0491: main */
-	0x0031f404,
-	0x0d0028f4,
-	0x00377e10,
-	0xf401f400,
-	0x4001e4b1,
-	0x00c71bf5,
-	0x99f094bd,
-	0x37008004,
-	0x0009f602,
-	0x008104bd,
-	0x11cf02c0,
-	0xc1008200,
-	0x0022cf02,
-	0xf41f13c8,
-	0x23c8770b,
-	0x550bf41f,
-	0x12b220f9,
-	0x99f094bd,
-	0x37008007,
-	0x0009f602,
-	0x32f404bd,
-	0x0231f401,
-	0x00087c7e,
-	0x99f094bd,
-	0x17008007,
-	0x0009f602,
-	0x20fc04bd,
-	0x99f094bd,
-	0x37008006,
-	0x0009f602,
-	0x31f404bd,
-	0x087c7e01,
-	0xf094bd00,
-	0x00800699,
-	0x09f60217,
-	0xf404bd00,
-/* 0x0522: chsw_prev_no_next */
-	0x20f92f0e,
-	0x32f412b2,
-	0x0232f401,
-	0x00087c7e,
-	0x008020fc,
-	0x02f602c0,
-	0xf404bd00,
-/* 0x053e: chsw_no_prev */
-	0x23c8130e,
-	0x0d0bf41f,
-	0xf40131f4,
-	0x7c7e0232,
-/* 0x054e: chsw_done */
-	0x01020008,
-	0x02c30080,
-	0xbd0002f6,
-	0xf094bd04,
-	0x00800499,
-	0x09f60217,
-	0xf504bd00,
-/* 0x056b: main_not_ctx_switch */
-	0xb0ff2a0e,
-	0x1bf401e4,
-	0x7ef2b20c,
-	0xf400081c,
-/* 0x057a: main_not_ctx_chan */
-	0xe4b0400e,
-	0x2c1bf402,
-	0x99f094bd,
-	0x37008007,
-	0x0009f602,
-	0x32f404bd,
-	0x0232f401,
-	0x00087c7e,
-	0x99f094bd,
-	0x17008007,
-	0x0009f602,
-	0x0ef404bd,
-/* 0x05a9: main_not_ctx_save */
-	0x10ef9411,
-	0x7e01f5f0,
-	0xf50002f8,
-/* 0x05b7: main_done */
-	0xbdfede0e,
-	0x1f29f024,
-	0x02300080,
-	0xbd0002f6,
-	0xcc0ef504,
-/* 0x05c9: ih */
-	0xfe80f9fe,
-	0x80f90188,
-	0xa0f990f9,
-	0xd0f9b0f9,
-	0xf0f9e0f9,
-	0x004a04bd,
-	0x00aacf02,
-	0xf404abc4,
-	0x100d230b,
-	0xcf1a004e,
-	0x004f00ee,
-	0x00ffcf19,
-	0x0000047e,
-	0x0400b0b7,
-	0x0040010e,
-	0x000ef61d,
-/* 0x060a: ih_no_fifo */
-	0xabe404bd,
-	0x0bf40100,
-	0x4e100d0c,
-	0x047e4001,
-/* 0x061a: ih_no_ctxsw */
-	0xabe40000,
-	0x0bf40400,
-	0x07088e56,
-	0x00657e40,
-	0x80ffb200,
-	0xf6020400,
-	0x04bd000f,
-	0x4007048e,
-	0x0000657e,
-	0x0080ffb2,
-	0x0ff60203,
-	0xc704bd00,
-	0xee9450fe,
-	0x07008f02,
-	0x00efbb40,
-	0x0000657e,
-	0x02020080,
-	0xbd000ff6,
-	0x7e030f04,
-	0x4b0002f8,
-	0xbfb20100,
-	0x4001448e,
-	0x00008f7e,
-/* 0x0674: ih_no_fwmthd */
-	0xbd05044b,
-	0xb4abffb0,
-	0x800c0bf4,
-	0xf6030700,
-	0x04bd000b,
-/* 0x0688: ih_no_other */
-	0xf6010040,
-	0x04bd000a,
-	0xe0fcf0fc,
-	0xb0fcd0fc,
-	0x90fca0fc,
-	0x88fe80fc,
-	0xf480fc00,
-	0x01f80032,
-/* 0x06a8: ctx_4170s */
-	0xb210f5f0,
-	0x41708eff,
-	0x008f7e40,
-/* 0x06b7: ctx_4170w */
-	0x8e00f800,
-	0x7e404170,
-	0xb2000065,
-	0x10f4f0ff,
-	0xf8f31bf4,
-/* 0x06c9: ctx_redswitch */
-	0x02004e00,
-	0xf040e5f0,
-	0xe5f020e5,
-	0x85008010,
-	0x000ef601,
-	0x080f04bd,
-/* 0x06e0: ctx_redswitch_delay */
-	0xf401f2b6,
-	0xe5f1fd1b,
-	0xe5f10400,
-	0x00800100,
-	0x0ef60185,
-	0xf804bd00,
-/* 0x06f9: ctx_86c */
-	0x23008000,
-	0x000ff602,
-	0xffb204bd,
-	0x408a148e,
-	0x00008f7e,
-	0x8c8effb2,
-	0x8f7e41a8,
-	0x00f80000,
-/* 0x0718: ctx_mem */
-	0x02840080,
-	0xbd000ff6,
-/* 0x0721: ctx_mem_wait */
-	0x84008f04,
-	0x00ffcf02,
-	0xf405fffd,
-	0x00f8f61b,
-/* 0x0730: ctx_load */
-	0x99f094bd,
-	0x37008005,
-	0x0009f602,
-	0x0c0a04bd,
-	0x0000b87e,
-	0x0080f4bd,
-	0x0ff60289,
-	0x8004bd00,
-	0xf602c100,
-	0x04bd0002,
-	0x02830080,
-	0xbd0002f6,
-	0x7e070f04,
-	0x80000718,
-	0xf602c000,
-	0x04bd0002,
-	0xf0000bfe,
-	0x24b61f2a,
-	0x0220b604,
-	0x99f094bd,
-	0x37008008,
-	0x0009f602,
-	0x008004bd,
-	0x02f60281,
-	0xd204bd00,
-	0x80000000,
-	0x800225f0,
-	0xf6028800,
-	0x04bd0002,
-	0x00421001,
-	0x0223f002,
-	0xf80512fa,
-	0xf094bd03,
-	0x00800899,
-	0x09f60217,
-	0x9804bd00,
-	0x14b68101,
-	0x80029818,
-	0xfd0825b6,
-	0x01b50512,
-	0xf094bd16,
-	0x00800999,
-	0x09f60237,
-	0x8004bd00,
-	0xf6028100,
-	0x04bd0001,
-	0x00800102,
-	0x02f60288,
-	0x4104bd00,
-	0x13f00100,
-	0x0501fa06,
-	0x94bd03f8,
-	0x800999f0,
-	0xf6021700,
-	0x04bd0009,
-	0x99f094bd,
-	0x17008005,
-	0x0009f602,
-	0x00f804bd,
-/* 0x081c: ctx_chan */
-	0x0007307e,
-	0xb87e0c0a,
-	0x050f0000,
-	0x0007187e,
-/* 0x082e: ctx_mmio_exec */
-	0x039800f8,
-	0x81008041,
-	0x0003f602,
-	0x34bd04bd,
-/* 0x083c: ctx_mmio_loop */
-	0xf4ff34c4,
-	0x00450e1b,
-	0x0653f002,
-	0xf80535fa,
-/* 0x084d: ctx_mmio_pull */
-	0x804e9803,
-	0x7e814f98,
-	0xb600008f,
-	0x12b60830,
-	0xdf1bf401,
-/* 0x0860: ctx_mmio_done */
-	0x80160398,
-	0xf6028100,
-	0x04bd0003,
-	0x414000b5,
-	0x13f00100,
-	0x0601fa06,
-	0x00f803f8,
-/* 0x087c: ctx_xfer */
-	0x0080040e,
-	0x0ef60302,
-/* 0x0887: ctx_xfer_idle */
-	0x8e04bd00,
-	0xcf030000,
-	0xe4f100ee,
-	0x1bf42000,
-	0x0611f4f5,
-/* 0x089b: ctx_xfer_pre */
-	0x0f0c02f4,
-	0x06f97e10,
-	0x1b11f400,
-/* 0x08a4: ctx_xfer_pre_load */
-	0xa87e020f,
-	0xb77e0006,
-	0xc97e0006,
-	0xf4bd0006,
-	0x0006a87e,
-	0x0007307e,
-/* 0x08bc: ctx_xfer_exec */
-	0xbd160198,
-	0x05008024,
-	0x0002f601,
-	0x1fb204bd,
-	0x41a5008e,
-	0x00008f7e,
-	0xf001fcf0,
-	0x24b6022c,
-	0x05f2fd01,
-	0x048effb2,
-	0x8f7e41a5,
-	0x167e0000,
-	0x24bd0002,
-	0x0247fc80,
-	0xbd0002f6,
-	0x012cf004,
-	0x800320b6,
-	0xf6024afc,
-	0x04bd0002,
-	0xf001acf0,
-	0x000b06a5,
-	0x98000c98,
-	0x000e010d,
-	0x00013d7e,
-	0xec7e080a,
-	0x0a7e0000,
-	0x01f40002,
-	0x7e0c0a12,
-	0x0f0000b8,
-	0x07187e05,
-	0x2d02f400,
-/* 0x0938: ctx_xfer_post */
-	0xa87e020f,
-	0xf4bd0006,
-	0x0006f97e,
-	0x0002277e,
-	0x0006b77e,
-	0xa87ef4bd,
-	0x11f40006,
-	0x40019810,
-	0xf40511fd,
-	0x2e7e070b,
-/* 0x0962: ctx_xfer_no_post_mmio */
-/* 0x0962: ctx_xfer_done */
-	0x00f80008,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
deleted file mode 100644
index 3ff52badf932..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#define CHIPSET GF100
-#include "macros.fuc"
-
-.section #nvc0_grhub_data
-#define INCLUDE_DATA
-#include "com.fuc"
-#include "hub.fuc"
-#undef INCLUDE_DATA
-
-.section #nvc0_grhub_code
-#define INCLUDE_CODE
-bra #init
-#include "com.fuc"
-#include "hub.fuc"
-.align 256
-#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
deleted file mode 100644
index 92dfe6a4ac87..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
+++ /dev/null
@@ -1,1047 +0,0 @@
-uint32_t nvc0_grhub_data[] = {
-/* 0x0000: hub_mmio_list_head */
-	0x00000300,
-/* 0x0004: hub_mmio_list_tail */
-	0x00000304,
-/* 0x0008: gpc_count */
-	0x00000000,
-/* 0x000c: rop_count */
-	0x00000000,
-/* 0x0010: cmd_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0058: ctx_current */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0100: chan_data */
-/* 0x0100: chan_mmio_count */
-	0x00000000,
-/* 0x0104: chan_mmio_address */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0200: xfer_data */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0300: hub_mmio_list_base */
-	0x0417e91c,
-};
-
-uint32_t nvc0_grhub_code[] = {
-	0x039b0ef5,
-/* 0x0004: queue_put */
-	0x9800d898,
-	0x86f001d9,
-	0x0489b808,
-	0xf00c1bf4,
-	0x21f502f7,
-	0x00f8037e,
-/* 0x001c: queue_put_next */
-	0xb60798c4,
-	0x8dbb0384,
-	0x0880b600,
-	0x80008e80,
-	0x90b6018f,
-	0x0f94f001,
-	0xf801d980,
-/* 0x0039: queue_get */
-	0x0131f400,
-	0x9800d898,
-	0x89b801d9,
-	0x210bf404,
-	0xb60789c4,
-	0x9dbb0394,
-	0x0890b600,
-	0x98009e98,
-	0x80b6019f,
-	0x0f84f001,
-	0xf400d880,
-/* 0x0066: queue_get_done */
-	0x00f80132,
-/* 0x0068: nv_rd32 */
-	0xf002ecb9,
-	0x07f11fc9,
-	0x03f0ca00,
-	0x000cd001,
-/* 0x007a: nv_rd32_wait */
-	0xc7f104bd,
-	0xc3f0ca00,
-	0x00cccf01,
-	0xf41fccc8,
-	0xa7f0f31b,
-	0x1021f506,
-	0x00f7f101,
-	0x01f3f0cb,
-	0xf800ffcf,
-/* 0x009d: nv_wr32 */
-	0x0007f100,
-	0x0103f0cc,
-	0xbd000fd0,
-	0x02ecb904,
-	0xf01fc9f0,
-	0x07f11ec9,
-	0x03f0ca00,
-	0x000cd001,
-/* 0x00be: nv_wr32_wait */
-	0xc7f104bd,
-	0xc3f0ca00,
-	0x00cccf01,
-	0xf41fccc8,
-	0x00f8f31b,
-/* 0x00d0: wait_donez */
-	0x99f094bd,
-	0x0007f100,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f006,
-	0xbd000ad0,
-/* 0x00ed: wait_donez_ne */
-	0x0087f104,
-	0x0183f000,
-	0xff0088cf,
-	0x1bf4888a,
-	0xf094bdf3,
-	0x07f10099,
-	0x03f01700,
-	0x0009d002,
-	0x00f804bd,
-/* 0x0110: wait_doneo */
-	0x99f094bd,
-	0x0007f100,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f006,
-	0xbd000ad0,
-/* 0x012d: wait_doneo_e */
-	0x0087f104,
-	0x0183f000,
-	0xff0088cf,
-	0x0bf4888a,
-	0xf094bdf3,
-	0x07f10099,
-	0x03f01700,
-	0x0009d002,
-	0x00f804bd,
-/* 0x0150: mmctx_size */
-/* 0x0152: nv_mmctx_size_loop */
-	0xe89894bd,
-	0x1a85b600,
-	0xb60180b6,
-	0x98bb0284,
-	0x04e0b600,
-	0xf404efb8,
-	0x9fb9eb1b,
-/* 0x016f: mmctx_xfer */
-	0xbd00f802,
-	0x0199f094,
-	0x0f0007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0xbbfd94bd,
-	0x120bf405,
-	0xc40007f1,
-	0xd00103f0,
-	0x04bd000b,
-/* 0x0197: mmctx_base_disabled */
-	0xfd0099f0,
-	0x0bf405ee,
-	0x0007f11e,
-	0x0103f0c6,
-	0xbd000ed0,
-	0x0007f104,
-	0x0103f0c7,
-	0xbd000fd0,
-	0x0199f004,
-/* 0x01b8: mmctx_multi_disabled */
-	0xb600abc8,
-	0xb9f010b4,
-	0x01aec80c,
-	0xfd11e4b6,
-	0x07f105be,
-	0x03f0c500,
-	0x000bd001,
-/* 0x01d6: mmctx_exec_loop */
-/* 0x01d6: mmctx_wait_free */
-	0xe7f104bd,
-	0xe3f0c500,
-	0x00eecf01,
-	0xf41fe4f0,
-	0xce98f30b,
-	0x05e9fd00,
-	0xc80007f1,
-	0xd00103f0,
-	0x04bd000e,
-	0xb804c0b6,
-	0x1bf404cd,
-	0x02abc8d8,
-/* 0x0207: mmctx_fini_wait */
-	0xf11f1bf4,
-	0xf0c500b7,
-	0xbbcf01b3,
-	0x1fb4f000,
-	0xf410b4b0,
-	0xa7f0f01b,
-	0xd021f405,
-/* 0x0223: mmctx_stop */
-	0xc82b0ef4,
-	0xb4b600ab,
-	0x0cb9f010,
-	0xf112b9f0,
-	0xf0c50007,
-	0x0bd00103,
-/* 0x023b: mmctx_stop_wait */
-	0xf104bd00,
-	0xf0c500b7,
-	0xbbcf01b3,
-	0x12bbc800,
-/* 0x024b: mmctx_done */
-	0xbdf31bf4,
-	0x0199f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-/* 0x025e: strand_wait */
-	0xa0f900f8,
-	0xf402a7f0,
-	0xa0fcd021,
-/* 0x026a: strand_pre */
-	0x97f000f8,
-	0xfc07f10c,
-	0x0203f04a,
-	0xbd0009d0,
-	0x5e21f504,
-/* 0x027f: strand_post */
-	0xf000f802,
-	0x07f10d97,
-	0x03f04afc,
-	0x0009d002,
-	0x21f504bd,
-	0x00f8025e,
-/* 0x0294: strand_set */
-	0xf10fc7f0,
-	0xf04ffc07,
-	0x0cd00203,
-	0xf004bd00,
-	0x07f10bc7,
-	0x03f04afc,
-	0x000cd002,
-	0x07f104bd,
-	0x03f04ffc,
-	0x000ed002,
-	0xc7f004bd,
-	0xfc07f10a,
-	0x0203f04a,
-	0xbd000cd0,
-	0x5e21f504,
-/* 0x02d3: strand_ctx_init */
-	0xbd00f802,
-	0x0399f094,
-	0x0f0007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0x026a21f5,
-	0xf503e7f0,
-	0xbd029421,
-	0xfc07f1c4,
-	0x0203f047,
-	0xbd000cd0,
-	0x01c7f004,
-	0x4afc07f1,
-	0xd00203f0,
-	0x04bd000c,
-	0x025e21f5,
-	0xf1010c92,
-	0xf046fc07,
-	0x0cd00203,
-	0xf004bd00,
-	0x07f102c7,
-	0x03f04afc,
-	0x000cd002,
-	0x21f504bd,
-	0x21f5025e,
-	0x87f1027f,
-	0x83f04200,
-	0x0097f102,
-	0x0293f020,
-	0x950099cf,
-/* 0x034a: ctx_init_strand_loop */
-	0x8ed008fe,
-	0x408ed000,
-	0xb6808acf,
-	0xa0b606a5,
-	0x00eabb01,
-	0xb60480b6,
-	0x1bf40192,
-	0x08e4b6e8,
-	0xbdf2efbc,
-	0x0399f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-/* 0x037e: error */
-	0x07f100f8,
-	0x03f00500,
-	0x000fd002,
-	0xf7f004bd,
-	0x0007f101,
-	0x0303f007,
-	0xbd000fd0,
-/* 0x039b: init */
-	0xbd00f804,
-	0x0007fe04,
-	0x420017f1,
-	0xcf0013f0,
-	0x11e70011,
-	0x14b60109,
-	0x0014fe08,
-	0xf10227f0,
-	0xf0120007,
-	0x02d00003,
-	0xf104bd00,
-	0xfe06c817,
-	0x24bd0010,
-	0x070007f1,
-	0xd00003f0,
-	0x04bd0002,
-	0x200327f1,
-	0x010007f1,
-	0xd00103f0,
-	0x04bd0002,
-	0x200427f1,
-	0x010407f1,
-	0xd00103f0,
-	0x04bd0002,
-	0x200b27f1,
-	0x010807f1,
-	0xd00103f0,
-	0x04bd0002,
-	0x200c27f1,
-	0x011c07f1,
-	0xd00103f0,
-	0x04bd0002,
-	0xf1010392,
-	0xf0090007,
-	0x03d00303,
-	0xf104bd00,
-	0xf0870427,
-	0x07f10023,
-	0x03f00400,
-	0x0002d000,
-	0x27f004bd,
-	0x0007f104,
-	0x0003f003,
-	0xbd0002d0,
-	0x1031f404,
-	0x9604e7f1,
-	0xf440e3f0,
-	0xfeb96821,
-	0x90f1c702,
-	0xf0030180,
-	0x0f801ff4,
-	0x0117f002,
-	0xb6041fbb,
-	0x07f10112,
-	0x03f00300,
-	0x0001d001,
-	0x07f104bd,
-	0x03f00400,
-	0x0001d001,
-	0x17f104bd,
-	0xf7f00100,
-	0x0d21f502,
-	0x1f21f508,
-	0x10f7f008,
-	0x086c21f5,
-	0x98000e98,
-	0x21f5010f,
-	0x14950150,
-	0x0007f108,
-	0x0103f0c0,
-	0xbd0004d0,
-	0x0007f104,
-	0x0103f0c1,
-	0xbd0004d0,
-	0x0030b704,
-	0x001fbb13,
-	0xf102f5b6,
-	0xf0d30007,
-	0x0fd00103,
-	0xb604bd00,
-	0x10b60815,
-	0x0814b601,
-	0xf5021fb9,
-	0xbb02d321,
-	0x0398001f,
-	0x0047f102,
-	0x5043f020,
-/* 0x04f4: init_gpc */
-	0x08044ea0,
-	0xf4021fb9,
-	0x4ea09d21,
-	0xf4bd010c,
-	0xa09d21f4,
-	0xf401044e,
-	0x4ea09d21,
-	0xf7f00100,
-	0x9d21f402,
-	0x08004ea0,
-/* 0x051c: init_gpc_wait */
-	0xc86821f4,
-	0x0bf41fff,
-	0x044ea0fa,
-	0x6821f408,
-	0xb7001fbb,
-	0xb6800040,
-	0x1bf40132,
-	0x00f7f0be,
-	0x086c21f5,
-	0xf500f7f0,
-	0xf1080d21,
-	0xf0010007,
-	0x01d00203,
-	0xbd04bd00,
-	0x1f19f014,
-	0x080007f1,
-	0xd00203f0,
-	0x04bd0001,
-/* 0x0564: main */
-	0xf40031f4,
-	0xd7f00028,
-	0x3921f410,
-	0xb1f401f4,
-	0xf54001e4,
-	0xbd00e91b,
-	0x0499f094,
-	0x0f0007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0xc00017f1,
-	0xcf0213f0,
-	0x27f10011,
-	0x23f0c100,
-	0x0022cf02,
-	0xf51f13c8,
-	0xc800890b,
-	0x0bf41f23,
-	0xb920f962,
-	0x94bd0212,
-	0xf10799f0,
-	0xf00f0007,
-	0x09d00203,
-	0xf404bd00,
-	0x31f40132,
-	0x4021f502,
-	0xf094bd0a,
-	0x07f10799,
-	0x03f01700,
-	0x0009d002,
-	0x20fc04bd,
-	0x99f094bd,
-	0x0007f106,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0131f404,
-	0x0a4021f5,
-	0x99f094bd,
-	0x0007f106,
-	0x0203f017,
-	0xbd0009d0,
-	0x330ef404,
-/* 0x060c: chsw_prev_no_next */
-	0x12b920f9,
-	0x0132f402,
-	0xf50232f4,
-	0xfc0a4021,
-	0x0007f120,
-	0x0203f0c0,
-	0xbd0002d0,
-	0x130ef404,
-/* 0x062c: chsw_no_prev */
-	0xf41f23c8,
-	0x31f40d0b,
-	0x0232f401,
-	0x0a4021f5,
-/* 0x063c: chsw_done */
-	0xf10127f0,
-	0xf0c30007,
-	0x02d00203,
-	0xbd04bd00,
-	0x0499f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0xff080ef5,
-/* 0x0660: main_not_ctx_switch */
-	0xf401e4b0,
-	0xf2b90d1b,
-	0xd021f502,
-	0x460ef409,
-/* 0x0670: main_not_ctx_chan */
-	0xf402e4b0,
-	0x94bd321b,
-	0xf10799f0,
-	0xf00f0007,
-	0x09d00203,
-	0xf404bd00,
-	0x32f40132,
-	0x4021f502,
-	0xf094bd0a,
-	0x07f10799,
-	0x03f01700,
-	0x0009d002,
-	0x0ef404bd,
-/* 0x06a5: main_not_ctx_save */
-	0x10ef9411,
-	0xf501f5f0,
-	0xf5037e21,
-/* 0x06b3: main_done */
-	0xbdfeb50e,
-	0x1f29f024,
-	0x080007f1,
-	0xd00203f0,
-	0x04bd0002,
-	0xfea00ef5,
-/* 0x06c8: ih */
-	0x88fe80f9,
-	0xf980f901,
-	0xf9a0f990,
-	0xf9d0f9b0,
-	0xbdf0f9e0,
-	0x00a7f104,
-	0x00a3f002,
-	0xc400aacf,
-	0x0bf404ab,
-	0x10d7f030,
-	0x1a00e7f1,
-	0xcf00e3f0,
-	0xf7f100ee,
-	0xf3f01900,
-	0x00ffcf00,
-	0xb70421f4,
-	0xf00400b0,
-	0x07f101e7,
-	0x03f01d00,
-	0x000ed000,
-/* 0x071a: ih_no_fifo */
-	0xabe404bd,
-	0x0bf40100,
-	0x10d7f00d,
-	0x4001e7f1,
-/* 0x072b: ih_no_ctxsw */
-	0xe40421f4,
-	0xf40400ab,
-	0xe7f16c0b,
-	0xe3f00708,
-	0x6821f440,
-	0xf102ffb9,
-	0xf0040007,
-	0x0fd00203,
-	0xf104bd00,
-	0xf00704e7,
-	0x21f440e3,
-	0x02ffb968,
-	0x030007f1,
-	0xd00203f0,
-	0x04bd000f,
-	0x9450fec7,
-	0xf7f102ee,
-	0xf3f00700,
-	0x00efbb40,
-	0xf16821f4,
-	0xf0020007,
-	0x0fd00203,
-	0xf004bd00,
-	0x21f503f7,
-	0xb7f1037e,
-	0xbfb90100,
-	0x44e7f102,
-	0x40e3f001,
-/* 0x079b: ih_no_fwmthd */
-	0xf19d21f4,
-	0xbd0504b7,
-	0xb4abffb0,
-	0xf10f0bf4,
-	0xf0070007,
-	0x0bd00303,
-/* 0x07b3: ih_no_other */
-	0xf104bd00,
-	0xf0010007,
-	0x0ad00003,
-	0xfc04bd00,
-	0xfce0fcf0,
-	0xfcb0fcd0,
-	0xfc90fca0,
-	0x0088fe80,
-	0x32f480fc,
-/* 0x07d7: ctx_4160s */
-	0xf001f800,
-	0xffb901f7,
-	0x60e7f102,
-	0x40e3f041,
-/* 0x07e7: ctx_4160s_wait */
-	0xf19d21f4,
-	0xf04160e7,
-	0x21f440e3,
-	0x02ffb968,
-	0xf404ffc8,
-	0x00f8f00b,
-/* 0x07fc: ctx_4160c */
-	0xffb9f4bd,
-	0x60e7f102,
-	0x40e3f041,
-	0xf89d21f4,
-/* 0x080d: ctx_4170s */
-	0x10f5f000,
-	0xf102ffb9,
-	0xf04170e7,
-	0x21f440e3,
-/* 0x081f: ctx_4170w */
-	0xf100f89d,
-	0xf04170e7,
-	0x21f440e3,
-	0x02ffb968,
-	0xf410f4f0,
-	0x00f8f01b,
-/* 0x0834: ctx_redswitch */
-	0x0200e7f1,
-	0xf040e5f0,
-	0xe5f020e5,
-	0x0007f110,
-	0x0103f085,
-	0xbd000ed0,
-	0x08f7f004,
-/* 0x0850: ctx_redswitch_delay */
-	0xf401f2b6,
-	0xe5f1fd1b,
-	0xe5f10400,
-	0x07f10100,
-	0x03f08500,
-	0x000ed001,
-	0x00f804bd,
-/* 0x086c: ctx_86c */
-	0x1b0007f1,
-	0xd00203f0,
-	0x04bd000f,
-	0xf102ffb9,
-	0xf08a14e7,
-	0x21f440e3,
-	0x02ffb99d,
-	0xa86ce7f1,
-	0xf441e3f0,
-	0x00f89d21,
-/* 0x0894: ctx_mem */
-	0x840007f1,
-	0xd00203f0,
-	0x04bd000f,
-/* 0x08a0: ctx_mem_wait */
-	0x8400f7f1,
-	0xcf02f3f0,
-	0xfffd00ff,
-	0xf31bf405,
-/* 0x08b2: ctx_load */
-	0x94bd00f8,
-	0xf10599f0,
-	0xf00f0007,
-	0x09d00203,
-	0xf004bd00,
-	0x21f40ca7,
-	0xf1f4bdd0,
-	0xf0890007,
-	0x0fd00203,
-	0xf104bd00,
-	0xf0c10007,
-	0x02d00203,
-	0xf104bd00,
-	0xf0830007,
-	0x02d00203,
-	0xf004bd00,
-	0x21f507f7,
-	0x07f10894,
-	0x03f0c000,
-	0x0002d002,
-	0x0bfe04bd,
-	0x1f2af000,
-	0xb60424b6,
-	0x94bd0220,
-	0xf10899f0,
-	0xf00f0007,
-	0x09d00203,
-	0xf104bd00,
-	0xf0810007,
-	0x02d00203,
-	0xf104bd00,
-	0xf1000027,
-	0xf0800023,
-	0x07f10225,
-	0x03f08800,
-	0x0002d002,
-	0x17f004bd,
-	0x0027f110,
-	0x0223f002,
-	0xf80512fa,
-	0xf094bd03,
-	0x07f10899,
-	0x03f01700,
-	0x0009d002,
-	0x019804bd,
-	0x1814b681,
-	0xb6800298,
-	0x12fd0825,
-	0x16018005,
-	0x99f094bd,
-	0x0007f109,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f081,
-	0xbd0001d0,
-	0x0127f004,
-	0x880007f1,
-	0xd00203f0,
-	0x04bd0002,
-	0x010017f1,
-	0xfa0613f0,
-	0x03f80501,
-	0x99f094bd,
-	0x0007f109,
-	0x0203f017,
-	0xbd0009d0,
-	0xf094bd04,
-	0x07f10599,
-	0x03f01700,
-	0x0009d002,
-	0x00f804bd,
-/* 0x09d0: ctx_chan */
-	0x07d721f5,
-	0x08b221f5,
-	0xf40ca7f0,
-	0xf7f0d021,
-	0x9421f505,
-	0xfc21f508,
-/* 0x09eb: ctx_mmio_exec */
-	0x9800f807,
-	0x07f14103,
-	0x03f08100,
-	0x0003d002,
-	0x34bd04bd,
-/* 0x09fc: ctx_mmio_loop */
-	0xf4ff34c4,
-	0x57f10f1b,
-	0x53f00200,
-	0x0535fa06,
-/* 0x0a0e: ctx_mmio_pull */
-	0x4e9803f8,
-	0x814f9880,
-	0xb69d21f4,
-	0x12b60830,
-	0xdf1bf401,
-/* 0x0a20: ctx_mmio_done */
-	0xf1160398,
-	0xf0810007,
-	0x03d00203,
-	0x8004bd00,
-	0x17f14000,
-	0x13f00100,
-	0x0601fa06,
-	0x00f803f8,
-/* 0x0a40: ctx_xfer */
-	0xf104e7f0,
-	0xf0020007,
-	0x0ed00303,
-/* 0x0a4f: ctx_xfer_idle */
-	0xf104bd00,
-	0xf00000e7,
-	0xeecf03e3,
-	0x00e4f100,
-	0xf21bf420,
-	0xf40611f4,
-/* 0x0a66: ctx_xfer_pre */
-	0xf7f01102,
-	0x6c21f510,
-	0xd721f508,
-	0x1c11f407,
-/* 0x0a74: ctx_xfer_pre_load */
-	0xf502f7f0,
-	0xf5080d21,
-	0xf5081f21,
-	0xbd083421,
-	0x0d21f5f4,
-	0xb221f508,
-/* 0x0a8d: ctx_xfer_exec */
-	0x16019808,
-	0x07f124bd,
-	0x03f00500,
-	0x0002d001,
-	0x1fb904bd,
-	0x00e7f102,
-	0x41e3f0a5,
-	0xf09d21f4,
-	0x2cf001fc,
-	0x0124b602,
-	0xb905f2fd,
-	0xe7f102ff,
-	0xe3f0a504,
-	0x9d21f441,
-	0x026a21f5,
-	0x07f124bd,
-	0x03f047fc,
-	0x0002d002,
-	0x2cf004bd,
-	0x0320b601,
-	0x4afc07f1,
-	0xd00203f0,
-	0x04bd0002,
-	0xf001acf0,
-	0xb7f006a5,
-	0x000c9800,
-	0xf0010d98,
-	0x21f500e7,
-	0xa7f0016f,
-	0x1021f508,
-	0x5e21f501,
-	0x1301f402,
-	0xf40ca7f0,
-	0xf7f0d021,
-	0x9421f505,
-	0x3202f408,
-/* 0x0b1c: ctx_xfer_post */
-	0xf502f7f0,
-	0xbd080d21,
-	0x6c21f5f4,
-	0x7f21f508,
-	0x1f21f502,
-	0xf5f4bd08,
-	0xf4080d21,
-	0x01981011,
-	0x0511fd40,
-	0xf5070bf4,
-/* 0x0b47: ctx_xfer_no_post_mmio */
-	0xf509eb21,
-/* 0x0b4b: ctx_xfer_done */
-	0xf807fc21,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc
deleted file mode 100644
index afbe03ac9077..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#define CHIPSET GF117
-#include "macros.fuc"
-
-.section #nvd7_grhub_data
-#define INCLUDE_DATA
-#include "com.fuc"
-#include "hub.fuc"
-#undef INCLUDE_DATA
-
-.section #nvd7_grhub_code
-#define INCLUDE_CODE
-bra #init
-#include "com.fuc"
-#include "hub.fuc"
-.align 256
-#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h
deleted file mode 100644
index 62b0c7601d8b..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h
+++ /dev/null
@@ -1,1047 +0,0 @@
-uint32_t nvd7_grhub_data[] = {
-/* 0x0000: hub_mmio_list_head */
-	0x00000300,
-/* 0x0004: hub_mmio_list_tail */
-	0x00000304,
-/* 0x0008: gpc_count */
-	0x00000000,
-/* 0x000c: rop_count */
-	0x00000000,
-/* 0x0010: cmd_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0058: ctx_current */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0100: chan_data */
-/* 0x0100: chan_mmio_count */
-	0x00000000,
-/* 0x0104: chan_mmio_address */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0200: xfer_data */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0300: hub_mmio_list_base */
-	0x0417e91c,
-};
-
-uint32_t nvd7_grhub_code[] = {
-	0x039b0ef5,
-/* 0x0004: queue_put */
-	0x9800d898,
-	0x86f001d9,
-	0x0489b808,
-	0xf00c1bf4,
-	0x21f502f7,
-	0x00f8037e,
-/* 0x001c: queue_put_next */
-	0xb60798c4,
-	0x8dbb0384,
-	0x0880b600,
-	0x80008e80,
-	0x90b6018f,
-	0x0f94f001,
-	0xf801d980,
-/* 0x0039: queue_get */
-	0x0131f400,
-	0x9800d898,
-	0x89b801d9,
-	0x210bf404,
-	0xb60789c4,
-	0x9dbb0394,
-	0x0890b600,
-	0x98009e98,
-	0x80b6019f,
-	0x0f84f001,
-	0xf400d880,
-/* 0x0066: queue_get_done */
-	0x00f80132,
-/* 0x0068: nv_rd32 */
-	0xf002ecb9,
-	0x07f11fc9,
-	0x03f0ca00,
-	0x000cd001,
-/* 0x007a: nv_rd32_wait */
-	0xc7f104bd,
-	0xc3f0ca00,
-	0x00cccf01,
-	0xf41fccc8,
-	0xa7f0f31b,
-	0x1021f506,
-	0x00f7f101,
-	0x01f3f0cb,
-	0xf800ffcf,
-/* 0x009d: nv_wr32 */
-	0x0007f100,
-	0x0103f0cc,
-	0xbd000fd0,
-	0x02ecb904,
-	0xf01fc9f0,
-	0x07f11ec9,
-	0x03f0ca00,
-	0x000cd001,
-/* 0x00be: nv_wr32_wait */
-	0xc7f104bd,
-	0xc3f0ca00,
-	0x00cccf01,
-	0xf41fccc8,
-	0x00f8f31b,
-/* 0x00d0: wait_donez */
-	0x99f094bd,
-	0x0007f100,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f006,
-	0xbd000ad0,
-/* 0x00ed: wait_donez_ne */
-	0x0087f104,
-	0x0183f000,
-	0xff0088cf,
-	0x1bf4888a,
-	0xf094bdf3,
-	0x07f10099,
-	0x03f01700,
-	0x0009d002,
-	0x00f804bd,
-/* 0x0110: wait_doneo */
-	0x99f094bd,
-	0x0007f100,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f006,
-	0xbd000ad0,
-/* 0x012d: wait_doneo_e */
-	0x0087f104,
-	0x0183f000,
-	0xff0088cf,
-	0x0bf4888a,
-	0xf094bdf3,
-	0x07f10099,
-	0x03f01700,
-	0x0009d002,
-	0x00f804bd,
-/* 0x0150: mmctx_size */
-/* 0x0152: nv_mmctx_size_loop */
-	0xe89894bd,
-	0x1a85b600,
-	0xb60180b6,
-	0x98bb0284,
-	0x04e0b600,
-	0xf404efb8,
-	0x9fb9eb1b,
-/* 0x016f: mmctx_xfer */
-	0xbd00f802,
-	0x0199f094,
-	0x0f0007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0xbbfd94bd,
-	0x120bf405,
-	0xc40007f1,
-	0xd00103f0,
-	0x04bd000b,
-/* 0x0197: mmctx_base_disabled */
-	0xfd0099f0,
-	0x0bf405ee,
-	0x0007f11e,
-	0x0103f0c6,
-	0xbd000ed0,
-	0x0007f104,
-	0x0103f0c7,
-	0xbd000fd0,
-	0x0199f004,
-/* 0x01b8: mmctx_multi_disabled */
-	0xb600abc8,
-	0xb9f010b4,
-	0x01aec80c,
-	0xfd11e4b6,
-	0x07f105be,
-	0x03f0c500,
-	0x000bd001,
-/* 0x01d6: mmctx_exec_loop */
-/* 0x01d6: mmctx_wait_free */
-	0xe7f104bd,
-	0xe3f0c500,
-	0x00eecf01,
-	0xf41fe4f0,
-	0xce98f30b,
-	0x05e9fd00,
-	0xc80007f1,
-	0xd00103f0,
-	0x04bd000e,
-	0xb804c0b6,
-	0x1bf404cd,
-	0x02abc8d8,
-/* 0x0207: mmctx_fini_wait */
-	0xf11f1bf4,
-	0xf0c500b7,
-	0xbbcf01b3,
-	0x1fb4f000,
-	0xf410b4b0,
-	0xa7f0f01b,
-	0xd021f405,
-/* 0x0223: mmctx_stop */
-	0xc82b0ef4,
-	0xb4b600ab,
-	0x0cb9f010,
-	0xf112b9f0,
-	0xf0c50007,
-	0x0bd00103,
-/* 0x023b: mmctx_stop_wait */
-	0xf104bd00,
-	0xf0c500b7,
-	0xbbcf01b3,
-	0x12bbc800,
-/* 0x024b: mmctx_done */
-	0xbdf31bf4,
-	0x0199f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-/* 0x025e: strand_wait */
-	0xa0f900f8,
-	0xf402a7f0,
-	0xa0fcd021,
-/* 0x026a: strand_pre */
-	0x97f000f8,
-	0xfc07f10c,
-	0x0203f04a,
-	0xbd0009d0,
-	0x5e21f504,
-/* 0x027f: strand_post */
-	0xf000f802,
-	0x07f10d97,
-	0x03f04afc,
-	0x0009d002,
-	0x21f504bd,
-	0x00f8025e,
-/* 0x0294: strand_set */
-	0xf10fc7f0,
-	0xf04ffc07,
-	0x0cd00203,
-	0xf004bd00,
-	0x07f10bc7,
-	0x03f04afc,
-	0x000cd002,
-	0x07f104bd,
-	0x03f04ffc,
-	0x000ed002,
-	0xc7f004bd,
-	0xfc07f10a,
-	0x0203f04a,
-	0xbd000cd0,
-	0x5e21f504,
-/* 0x02d3: strand_ctx_init */
-	0xbd00f802,
-	0x0399f094,
-	0x0f0007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0x026a21f5,
-	0xf503e7f0,
-	0xbd029421,
-	0xfc07f1c4,
-	0x0203f047,
-	0xbd000cd0,
-	0x01c7f004,
-	0x4afc07f1,
-	0xd00203f0,
-	0x04bd000c,
-	0x025e21f5,
-	0xf1010c92,
-	0xf046fc07,
-	0x0cd00203,
-	0xf004bd00,
-	0x07f102c7,
-	0x03f04afc,
-	0x000cd002,
-	0x21f504bd,
-	0x21f5025e,
-	0x87f1027f,
-	0x83f04200,
-	0x0097f102,
-	0x0293f020,
-	0x950099cf,
-/* 0x034a: ctx_init_strand_loop */
-	0x8ed008fe,
-	0x408ed000,
-	0xb6808acf,
-	0xa0b606a5,
-	0x00eabb01,
-	0xb60480b6,
-	0x1bf40192,
-	0x08e4b6e8,
-	0xbdf2efbc,
-	0x0399f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-/* 0x037e: error */
-	0x07f100f8,
-	0x03f00500,
-	0x000fd002,
-	0xf7f004bd,
-	0x0007f101,
-	0x0303f007,
-	0xbd000fd0,
-/* 0x039b: init */
-	0xbd00f804,
-	0x0007fe04,
-	0x420017f1,
-	0xcf0013f0,
-	0x11e70011,
-	0x14b60109,
-	0x0014fe08,
-	0xf10227f0,
-	0xf0120007,
-	0x02d00003,
-	0xf104bd00,
-	0xfe06c817,
-	0x24bd0010,
-	0x070007f1,
-	0xd00003f0,
-	0x04bd0002,
-	0x200327f1,
-	0x010007f1,
-	0xd00103f0,
-	0x04bd0002,
-	0x200427f1,
-	0x010407f1,
-	0xd00103f0,
-	0x04bd0002,
-	0x200b27f1,
-	0x010807f1,
-	0xd00103f0,
-	0x04bd0002,
-	0x200c27f1,
-	0x011c07f1,
-	0xd00103f0,
-	0x04bd0002,
-	0xf1010392,
-	0xf0090007,
-	0x03d00303,
-	0xf104bd00,
-	0xf0870427,
-	0x07f10023,
-	0x03f00400,
-	0x0002d000,
-	0x27f004bd,
-	0x0007f104,
-	0x0003f003,
-	0xbd0002d0,
-	0x1031f404,
-	0x9604e7f1,
-	0xf440e3f0,
-	0xfeb96821,
-	0x90f1c702,
-	0xf0030180,
-	0x0f801ff4,
-	0x0117f002,
-	0xb6041fbb,
-	0x07f10112,
-	0x03f00300,
-	0x0001d001,
-	0x07f104bd,
-	0x03f00400,
-	0x0001d001,
-	0x17f104bd,
-	0xf7f00100,
-	0x0d21f502,
-	0x1f21f508,
-	0x10f7f008,
-	0x086c21f5,
-	0x98000e98,
-	0x21f5010f,
-	0x14950150,
-	0x0007f108,
-	0x0103f0c0,
-	0xbd0004d0,
-	0x0007f104,
-	0x0103f0c1,
-	0xbd0004d0,
-	0x0030b704,
-	0x001fbb13,
-	0xf102f5b6,
-	0xf0d30007,
-	0x0fd00103,
-	0xb604bd00,
-	0x10b60815,
-	0x0814b601,
-	0xf5021fb9,
-	0xbb02d321,
-	0x0398001f,
-	0x0047f102,
-	0x5043f020,
-/* 0x04f4: init_gpc */
-	0x08044ea0,
-	0xf4021fb9,
-	0x4ea09d21,
-	0xf4bd010c,
-	0xa09d21f4,
-	0xf401044e,
-	0x4ea09d21,
-	0xf7f00100,
-	0x9d21f402,
-	0x08004ea0,
-/* 0x051c: init_gpc_wait */
-	0xc86821f4,
-	0x0bf41fff,
-	0x044ea0fa,
-	0x6821f408,
-	0xb7001fbb,
-	0xb6800040,
-	0x1bf40132,
-	0x00f7f0be,
-	0x086c21f5,
-	0xf500f7f0,
-	0xf1080d21,
-	0xf0010007,
-	0x01d00203,
-	0xbd04bd00,
-	0x1f19f014,
-	0x080007f1,
-	0xd00203f0,
-	0x04bd0001,
-/* 0x0564: main */
-	0xf40031f4,
-	0xd7f00028,
-	0x3921f410,
-	0xb1f401f4,
-	0xf54001e4,
-	0xbd00e91b,
-	0x0499f094,
-	0x0f0007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0xc00017f1,
-	0xcf0213f0,
-	0x27f10011,
-	0x23f0c100,
-	0x0022cf02,
-	0xf51f13c8,
-	0xc800890b,
-	0x0bf41f23,
-	0xb920f962,
-	0x94bd0212,
-	0xf10799f0,
-	0xf00f0007,
-	0x09d00203,
-	0xf404bd00,
-	0x31f40132,
-	0x4021f502,
-	0xf094bd0a,
-	0x07f10799,
-	0x03f01700,
-	0x0009d002,
-	0x20fc04bd,
-	0x99f094bd,
-	0x0007f106,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0131f404,
-	0x0a4021f5,
-	0x99f094bd,
-	0x0007f106,
-	0x0203f017,
-	0xbd0009d0,
-	0x330ef404,
-/* 0x060c: chsw_prev_no_next */
-	0x12b920f9,
-	0x0132f402,
-	0xf50232f4,
-	0xfc0a4021,
-	0x0007f120,
-	0x0203f0c0,
-	0xbd0002d0,
-	0x130ef404,
-/* 0x062c: chsw_no_prev */
-	0xf41f23c8,
-	0x31f40d0b,
-	0x0232f401,
-	0x0a4021f5,
-/* 0x063c: chsw_done */
-	0xf10127f0,
-	0xf0c30007,
-	0x02d00203,
-	0xbd04bd00,
-	0x0499f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0xff080ef5,
-/* 0x0660: main_not_ctx_switch */
-	0xf401e4b0,
-	0xf2b90d1b,
-	0xd021f502,
-	0x460ef409,
-/* 0x0670: main_not_ctx_chan */
-	0xf402e4b0,
-	0x94bd321b,
-	0xf10799f0,
-	0xf00f0007,
-	0x09d00203,
-	0xf404bd00,
-	0x32f40132,
-	0x4021f502,
-	0xf094bd0a,
-	0x07f10799,
-	0x03f01700,
-	0x0009d002,
-	0x0ef404bd,
-/* 0x06a5: main_not_ctx_save */
-	0x10ef9411,
-	0xf501f5f0,
-	0xf5037e21,
-/* 0x06b3: main_done */
-	0xbdfeb50e,
-	0x1f29f024,
-	0x080007f1,
-	0xd00203f0,
-	0x04bd0002,
-	0xfea00ef5,
-/* 0x06c8: ih */
-	0x88fe80f9,
-	0xf980f901,
-	0xf9a0f990,
-	0xf9d0f9b0,
-	0xbdf0f9e0,
-	0x00a7f104,
-	0x00a3f002,
-	0xc400aacf,
-	0x0bf404ab,
-	0x10d7f030,
-	0x1a00e7f1,
-	0xcf00e3f0,
-	0xf7f100ee,
-	0xf3f01900,
-	0x00ffcf00,
-	0xb70421f4,
-	0xf00400b0,
-	0x07f101e7,
-	0x03f01d00,
-	0x000ed000,
-/* 0x071a: ih_no_fifo */
-	0xabe404bd,
-	0x0bf40100,
-	0x10d7f00d,
-	0x4001e7f1,
-/* 0x072b: ih_no_ctxsw */
-	0xe40421f4,
-	0xf40400ab,
-	0xe7f16c0b,
-	0xe3f00708,
-	0x6821f440,
-	0xf102ffb9,
-	0xf0040007,
-	0x0fd00203,
-	0xf104bd00,
-	0xf00704e7,
-	0x21f440e3,
-	0x02ffb968,
-	0x030007f1,
-	0xd00203f0,
-	0x04bd000f,
-	0x9450fec7,
-	0xf7f102ee,
-	0xf3f00700,
-	0x00efbb40,
-	0xf16821f4,
-	0xf0020007,
-	0x0fd00203,
-	0xf004bd00,
-	0x21f503f7,
-	0xb7f1037e,
-	0xbfb90100,
-	0x44e7f102,
-	0x40e3f001,
-/* 0x079b: ih_no_fwmthd */
-	0xf19d21f4,
-	0xbd0504b7,
-	0xb4abffb0,
-	0xf10f0bf4,
-	0xf0070007,
-	0x0bd00303,
-/* 0x07b3: ih_no_other */
-	0xf104bd00,
-	0xf0010007,
-	0x0ad00003,
-	0xfc04bd00,
-	0xfce0fcf0,
-	0xfcb0fcd0,
-	0xfc90fca0,
-	0x0088fe80,
-	0x32f480fc,
-/* 0x07d7: ctx_4160s */
-	0xf001f800,
-	0xffb901f7,
-	0x60e7f102,
-	0x40e3f041,
-/* 0x07e7: ctx_4160s_wait */
-	0xf19d21f4,
-	0xf04160e7,
-	0x21f440e3,
-	0x02ffb968,
-	0xf404ffc8,
-	0x00f8f00b,
-/* 0x07fc: ctx_4160c */
-	0xffb9f4bd,
-	0x60e7f102,
-	0x40e3f041,
-	0xf89d21f4,
-/* 0x080d: ctx_4170s */
-	0x10f5f000,
-	0xf102ffb9,
-	0xf04170e7,
-	0x21f440e3,
-/* 0x081f: ctx_4170w */
-	0xf100f89d,
-	0xf04170e7,
-	0x21f440e3,
-	0x02ffb968,
-	0xf410f4f0,
-	0x00f8f01b,
-/* 0x0834: ctx_redswitch */
-	0x0200e7f1,
-	0xf040e5f0,
-	0xe5f020e5,
-	0x0007f110,
-	0x0103f085,
-	0xbd000ed0,
-	0x08f7f004,
-/* 0x0850: ctx_redswitch_delay */
-	0xf401f2b6,
-	0xe5f1fd1b,
-	0xe5f10400,
-	0x07f10100,
-	0x03f08500,
-	0x000ed001,
-	0x00f804bd,
-/* 0x086c: ctx_86c */
-	0x1b0007f1,
-	0xd00203f0,
-	0x04bd000f,
-	0xf102ffb9,
-	0xf08a14e7,
-	0x21f440e3,
-	0x02ffb99d,
-	0xa86ce7f1,
-	0xf441e3f0,
-	0x00f89d21,
-/* 0x0894: ctx_mem */
-	0x840007f1,
-	0xd00203f0,
-	0x04bd000f,
-/* 0x08a0: ctx_mem_wait */
-	0x8400f7f1,
-	0xcf02f3f0,
-	0xfffd00ff,
-	0xf31bf405,
-/* 0x08b2: ctx_load */
-	0x94bd00f8,
-	0xf10599f0,
-	0xf00f0007,
-	0x09d00203,
-	0xf004bd00,
-	0x21f40ca7,
-	0xf1f4bdd0,
-	0xf0890007,
-	0x0fd00203,
-	0xf104bd00,
-	0xf0c10007,
-	0x02d00203,
-	0xf104bd00,
-	0xf0830007,
-	0x02d00203,
-	0xf004bd00,
-	0x21f507f7,
-	0x07f10894,
-	0x03f0c000,
-	0x0002d002,
-	0x0bfe04bd,
-	0x1f2af000,
-	0xb60424b6,
-	0x94bd0220,
-	0xf10899f0,
-	0xf00f0007,
-	0x09d00203,
-	0xf104bd00,
-	0xf0810007,
-	0x02d00203,
-	0xf104bd00,
-	0xf1000027,
-	0xf0800023,
-	0x07f10225,
-	0x03f08800,
-	0x0002d002,
-	0x17f004bd,
-	0x0027f110,
-	0x0223f002,
-	0xf80512fa,
-	0xf094bd03,
-	0x07f10899,
-	0x03f01700,
-	0x0009d002,
-	0x019804bd,
-	0x1814b681,
-	0xb6800298,
-	0x12fd0825,
-	0x16018005,
-	0x99f094bd,
-	0x0007f109,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f081,
-	0xbd0001d0,
-	0x0127f004,
-	0x880007f1,
-	0xd00203f0,
-	0x04bd0002,
-	0x010017f1,
-	0xfa0613f0,
-	0x03f80501,
-	0x99f094bd,
-	0x0007f109,
-	0x0203f017,
-	0xbd0009d0,
-	0xf094bd04,
-	0x07f10599,
-	0x03f01700,
-	0x0009d002,
-	0x00f804bd,
-/* 0x09d0: ctx_chan */
-	0x07d721f5,
-	0x08b221f5,
-	0xf40ca7f0,
-	0xf7f0d021,
-	0x9421f505,
-	0xfc21f508,
-/* 0x09eb: ctx_mmio_exec */
-	0x9800f807,
-	0x07f14103,
-	0x03f08100,
-	0x0003d002,
-	0x34bd04bd,
-/* 0x09fc: ctx_mmio_loop */
-	0xf4ff34c4,
-	0x57f10f1b,
-	0x53f00200,
-	0x0535fa06,
-/* 0x0a0e: ctx_mmio_pull */
-	0x4e9803f8,
-	0x814f9880,
-	0xb69d21f4,
-	0x12b60830,
-	0xdf1bf401,
-/* 0x0a20: ctx_mmio_done */
-	0xf1160398,
-	0xf0810007,
-	0x03d00203,
-	0x8004bd00,
-	0x17f14000,
-	0x13f00100,
-	0x0601fa06,
-	0x00f803f8,
-/* 0x0a40: ctx_xfer */
-	0xf104e7f0,
-	0xf0020007,
-	0x0ed00303,
-/* 0x0a4f: ctx_xfer_idle */
-	0xf104bd00,
-	0xf00000e7,
-	0xeecf03e3,
-	0x00e4f100,
-	0xf21bf420,
-	0xf40611f4,
-/* 0x0a66: ctx_xfer_pre */
-	0xf7f01102,
-	0x6c21f510,
-	0xd721f508,
-	0x1c11f407,
-/* 0x0a74: ctx_xfer_pre_load */
-	0xf502f7f0,
-	0xf5080d21,
-	0xf5081f21,
-	0xbd083421,
-	0x0d21f5f4,
-	0xb221f508,
-/* 0x0a8d: ctx_xfer_exec */
-	0x16019808,
-	0x07f124bd,
-	0x03f00500,
-	0x0002d001,
-	0x1fb904bd,
-	0x00e7f102,
-	0x41e3f0a5,
-	0xf09d21f4,
-	0x2cf001fc,
-	0x0124b602,
-	0xb905f2fd,
-	0xe7f102ff,
-	0xe3f0a504,
-	0x9d21f441,
-	0x026a21f5,
-	0x07f124bd,
-	0x03f047fc,
-	0x0002d002,
-	0x2cf004bd,
-	0x0320b601,
-	0x4afc07f1,
-	0xd00203f0,
-	0x04bd0002,
-	0xf001acf0,
-	0xb7f006a5,
-	0x000c9800,
-	0xf0010d98,
-	0x21f500e7,
-	0xa7f0016f,
-	0x1021f508,
-	0x5e21f501,
-	0x1301f402,
-	0xf40ca7f0,
-	0xf7f0d021,
-	0x9421f505,
-	0x3202f408,
-/* 0x0b1c: ctx_xfer_post */
-	0xf502f7f0,
-	0xbd080d21,
-	0x6c21f5f4,
-	0x7f21f508,
-	0x1f21f502,
-	0xf5f4bd08,
-	0xf4080d21,
-	0x01981011,
-	0x0511fd40,
-	0xf5070bf4,
-/* 0x0b47: ctx_xfer_no_post_mmio */
-	0xf509eb21,
-/* 0x0b4b: ctx_xfer_done */
-	0xf807fc21,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
deleted file mode 100644
index d4840f1879fd..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#define CHIPSET GK100
-#include "macros.fuc"
-
-.section #nve0_grhub_data
-#define INCLUDE_DATA
-#include "com.fuc"
-#include "hub.fuc"
-#undef INCLUDE_DATA
-
-.section #nve0_grhub_code
-#define INCLUDE_CODE
-bra #init
-#include "com.fuc"
-#include "hub.fuc"
-.align 256
-#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
deleted file mode 100644
index 51c3797d8537..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
+++ /dev/null
@@ -1,1044 +0,0 @@
-uint32_t nve0_grhub_data[] = {
-/* 0x0000: hub_mmio_list_head */
-	0x00000300,
-/* 0x0004: hub_mmio_list_tail */
-	0x00000304,
-/* 0x0008: gpc_count */
-	0x00000000,
-/* 0x000c: rop_count */
-	0x00000000,
-/* 0x0010: cmd_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0058: ctx_current */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0100: chan_data */
-/* 0x0100: chan_mmio_count */
-	0x00000000,
-/* 0x0104: chan_mmio_address */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0200: xfer_data */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0300: hub_mmio_list_base */
-	0x0417e91c,
-};
-
-uint32_t nve0_grhub_code[] = {
-	0x039b0ef5,
-/* 0x0004: queue_put */
-	0x9800d898,
-	0x86f001d9,
-	0x0489b808,
-	0xf00c1bf4,
-	0x21f502f7,
-	0x00f8037e,
-/* 0x001c: queue_put_next */
-	0xb60798c4,
-	0x8dbb0384,
-	0x0880b600,
-	0x80008e80,
-	0x90b6018f,
-	0x0f94f001,
-	0xf801d980,
-/* 0x0039: queue_get */
-	0x0131f400,
-	0x9800d898,
-	0x89b801d9,
-	0x210bf404,
-	0xb60789c4,
-	0x9dbb0394,
-	0x0890b600,
-	0x98009e98,
-	0x80b6019f,
-	0x0f84f001,
-	0xf400d880,
-/* 0x0066: queue_get_done */
-	0x00f80132,
-/* 0x0068: nv_rd32 */
-	0xf002ecb9,
-	0x07f11fc9,
-	0x03f0ca00,
-	0x000cd001,
-/* 0x007a: nv_rd32_wait */
-	0xc7f104bd,
-	0xc3f0ca00,
-	0x00cccf01,
-	0xf41fccc8,
-	0xa7f0f31b,
-	0x1021f506,
-	0x00f7f101,
-	0x01f3f0cb,
-	0xf800ffcf,
-/* 0x009d: nv_wr32 */
-	0x0007f100,
-	0x0103f0cc,
-	0xbd000fd0,
-	0x02ecb904,
-	0xf01fc9f0,
-	0x07f11ec9,
-	0x03f0ca00,
-	0x000cd001,
-/* 0x00be: nv_wr32_wait */
-	0xc7f104bd,
-	0xc3f0ca00,
-	0x00cccf01,
-	0xf41fccc8,
-	0x00f8f31b,
-/* 0x00d0: wait_donez */
-	0x99f094bd,
-	0x0007f100,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f006,
-	0xbd000ad0,
-/* 0x00ed: wait_donez_ne */
-	0x0087f104,
-	0x0183f000,
-	0xff0088cf,
-	0x1bf4888a,
-	0xf094bdf3,
-	0x07f10099,
-	0x03f01700,
-	0x0009d002,
-	0x00f804bd,
-/* 0x0110: wait_doneo */
-	0x99f094bd,
-	0x0007f100,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f006,
-	0xbd000ad0,
-/* 0x012d: wait_doneo_e */
-	0x0087f104,
-	0x0183f000,
-	0xff0088cf,
-	0x0bf4888a,
-	0xf094bdf3,
-	0x07f10099,
-	0x03f01700,
-	0x0009d002,
-	0x00f804bd,
-/* 0x0150: mmctx_size */
-/* 0x0152: nv_mmctx_size_loop */
-	0xe89894bd,
-	0x1a85b600,
-	0xb60180b6,
-	0x98bb0284,
-	0x04e0b600,
-	0xf404efb8,
-	0x9fb9eb1b,
-/* 0x016f: mmctx_xfer */
-	0xbd00f802,
-	0x0199f094,
-	0x0f0007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0xbbfd94bd,
-	0x120bf405,
-	0xc40007f1,
-	0xd00103f0,
-	0x04bd000b,
-/* 0x0197: mmctx_base_disabled */
-	0xfd0099f0,
-	0x0bf405ee,
-	0x0007f11e,
-	0x0103f0c6,
-	0xbd000ed0,
-	0x0007f104,
-	0x0103f0c7,
-	0xbd000fd0,
-	0x0199f004,
-/* 0x01b8: mmctx_multi_disabled */
-	0xb600abc8,
-	0xb9f010b4,
-	0x01aec80c,
-	0xfd11e4b6,
-	0x07f105be,
-	0x03f0c500,
-	0x000bd001,
-/* 0x01d6: mmctx_exec_loop */
-/* 0x01d6: mmctx_wait_free */
-	0xe7f104bd,
-	0xe3f0c500,
-	0x00eecf01,
-	0xf41fe4f0,
-	0xce98f30b,
-	0x05e9fd00,
-	0xc80007f1,
-	0xd00103f0,
-	0x04bd000e,
-	0xb804c0b6,
-	0x1bf404cd,
-	0x02abc8d8,
-/* 0x0207: mmctx_fini_wait */
-	0xf11f1bf4,
-	0xf0c500b7,
-	0xbbcf01b3,
-	0x1fb4f000,
-	0xf410b4b0,
-	0xa7f0f01b,
-	0xd021f405,
-/* 0x0223: mmctx_stop */
-	0xc82b0ef4,
-	0xb4b600ab,
-	0x0cb9f010,
-	0xf112b9f0,
-	0xf0c50007,
-	0x0bd00103,
-/* 0x023b: mmctx_stop_wait */
-	0xf104bd00,
-	0xf0c500b7,
-	0xbbcf01b3,
-	0x12bbc800,
-/* 0x024b: mmctx_done */
-	0xbdf31bf4,
-	0x0199f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-/* 0x025e: strand_wait */
-	0xa0f900f8,
-	0xf402a7f0,
-	0xa0fcd021,
-/* 0x026a: strand_pre */
-	0x97f000f8,
-	0xfc07f10c,
-	0x0203f04a,
-	0xbd0009d0,
-	0x5e21f504,
-/* 0x027f: strand_post */
-	0xf000f802,
-	0x07f10d97,
-	0x03f04afc,
-	0x0009d002,
-	0x21f504bd,
-	0x00f8025e,
-/* 0x0294: strand_set */
-	0xf10fc7f0,
-	0xf04ffc07,
-	0x0cd00203,
-	0xf004bd00,
-	0x07f10bc7,
-	0x03f04afc,
-	0x000cd002,
-	0x07f104bd,
-	0x03f04ffc,
-	0x000ed002,
-	0xc7f004bd,
-	0xfc07f10a,
-	0x0203f04a,
-	0xbd000cd0,
-	0x5e21f504,
-/* 0x02d3: strand_ctx_init */
-	0xbd00f802,
-	0x0399f094,
-	0x0f0007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0x026a21f5,
-	0xf503e7f0,
-	0xbd029421,
-	0xfc07f1c4,
-	0x0203f047,
-	0xbd000cd0,
-	0x01c7f004,
-	0x4afc07f1,
-	0xd00203f0,
-	0x04bd000c,
-	0x025e21f5,
-	0xf1010c92,
-	0xf046fc07,
-	0x0cd00203,
-	0xf004bd00,
-	0x07f102c7,
-	0x03f04afc,
-	0x000cd002,
-	0x21f504bd,
-	0x21f5025e,
-	0x87f1027f,
-	0x83f04200,
-	0x0097f102,
-	0x0293f020,
-	0x950099cf,
-/* 0x034a: ctx_init_strand_loop */
-	0x8ed008fe,
-	0x408ed000,
-	0xb6808acf,
-	0xa0b606a5,
-	0x00eabb01,
-	0xb60480b6,
-	0x1bf40192,
-	0x08e4b6e8,
-	0xbdf2efbc,
-	0x0399f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-/* 0x037e: error */
-	0x07f100f8,
-	0x03f00500,
-	0x000fd002,
-	0xf7f004bd,
-	0x0007f101,
-	0x0303f007,
-	0xbd000fd0,
-/* 0x039b: init */
-	0xbd00f804,
-	0x0007fe04,
-	0x420017f1,
-	0xcf0013f0,
-	0x11e70011,
-	0x14b60109,
-	0x0014fe08,
-	0xf10227f0,
-	0xf0120007,
-	0x02d00003,
-	0xf104bd00,
-	0xfe06c817,
-	0x24bd0010,
-	0x070007f1,
-	0xd00003f0,
-	0x04bd0002,
-	0x200327f1,
-	0x010007f1,
-	0xd00103f0,
-	0x04bd0002,
-	0x200427f1,
-	0x010407f1,
-	0xd00103f0,
-	0x04bd0002,
-	0x200b27f1,
-	0x010807f1,
-	0xd00103f0,
-	0x04bd0002,
-	0x200c27f1,
-	0x011c07f1,
-	0xd00103f0,
-	0x04bd0002,
-	0xf1010392,
-	0xf0090007,
-	0x03d00303,
-	0xf104bd00,
-	0xf0870427,
-	0x07f10023,
-	0x03f00400,
-	0x0002d000,
-	0x27f004bd,
-	0x0007f104,
-	0x0003f003,
-	0xbd0002d0,
-	0x1031f404,
-	0x9604e7f1,
-	0xf440e3f0,
-	0xfeb96821,
-	0x90f1c702,
-	0xf0030180,
-	0x0f801ff4,
-	0x0117f002,
-	0xb6041fbb,
-	0x07f10112,
-	0x03f00300,
-	0x0001d001,
-	0x07f104bd,
-	0x03f00400,
-	0x0001d001,
-	0x17f104bd,
-	0xf7f00100,
-	0xd721f502,
-	0xe921f507,
-	0x10f7f007,
-	0x083621f5,
-	0x98000e98,
-	0x21f5010f,
-	0x14950150,
-	0x0007f108,
-	0x0103f0c0,
-	0xbd0004d0,
-	0x0007f104,
-	0x0103f0c1,
-	0xbd0004d0,
-	0x0030b704,
-	0x001fbb13,
-	0xf102f5b6,
-	0xf0d30007,
-	0x0fd00103,
-	0xb604bd00,
-	0x10b60815,
-	0x0814b601,
-	0xf5021fb9,
-	0xbb02d321,
-	0x0398001f,
-	0x0047f102,
-	0x5043f020,
-/* 0x04f4: init_gpc */
-	0x08044ea0,
-	0xf4021fb9,
-	0x4ea09d21,
-	0xf4bd010c,
-	0xa09d21f4,
-	0xf401044e,
-	0x4ea09d21,
-	0xf7f00100,
-	0x9d21f402,
-	0x08004ea0,
-/* 0x051c: init_gpc_wait */
-	0xc86821f4,
-	0x0bf41fff,
-	0x044ea0fa,
-	0x6821f408,
-	0xb7001fbb,
-	0xb6800040,
-	0x1bf40132,
-	0x00f7f0be,
-	0x083621f5,
-	0xf500f7f0,
-	0xf107d721,
-	0xf0010007,
-	0x01d00203,
-	0xbd04bd00,
-	0x1f19f014,
-	0x080007f1,
-	0xd00203f0,
-	0x04bd0001,
-/* 0x0564: main */
-	0xf40031f4,
-	0xd7f00028,
-	0x3921f410,
-	0xb1f401f4,
-	0xf54001e4,
-	0xbd00e91b,
-	0x0499f094,
-	0x0f0007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0xc00017f1,
-	0xcf0213f0,
-	0x27f10011,
-	0x23f0c100,
-	0x0022cf02,
-	0xf51f13c8,
-	0xc800890b,
-	0x0bf41f23,
-	0xb920f962,
-	0x94bd0212,
-	0xf10799f0,
-	0xf00f0007,
-	0x09d00203,
-	0xf404bd00,
-	0x31f40132,
-	0x0221f502,
-	0xf094bd0a,
-	0x07f10799,
-	0x03f01700,
-	0x0009d002,
-	0x20fc04bd,
-	0x99f094bd,
-	0x0007f106,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0131f404,
-	0x0a0221f5,
-	0x99f094bd,
-	0x0007f106,
-	0x0203f017,
-	0xbd0009d0,
-	0x330ef404,
-/* 0x060c: chsw_prev_no_next */
-	0x12b920f9,
-	0x0132f402,
-	0xf50232f4,
-	0xfc0a0221,
-	0x0007f120,
-	0x0203f0c0,
-	0xbd0002d0,
-	0x130ef404,
-/* 0x062c: chsw_no_prev */
-	0xf41f23c8,
-	0x31f40d0b,
-	0x0232f401,
-	0x0a0221f5,
-/* 0x063c: chsw_done */
-	0xf10127f0,
-	0xf0c30007,
-	0x02d00203,
-	0xbd04bd00,
-	0x0499f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0xff080ef5,
-/* 0x0660: main_not_ctx_switch */
-	0xf401e4b0,
-	0xf2b90d1b,
-	0x9a21f502,
-	0x460ef409,
-/* 0x0670: main_not_ctx_chan */
-	0xf402e4b0,
-	0x94bd321b,
-	0xf10799f0,
-	0xf00f0007,
-	0x09d00203,
-	0xf404bd00,
-	0x32f40132,
-	0x0221f502,
-	0xf094bd0a,
-	0x07f10799,
-	0x03f01700,
-	0x0009d002,
-	0x0ef404bd,
-/* 0x06a5: main_not_ctx_save */
-	0x10ef9411,
-	0xf501f5f0,
-	0xf5037e21,
-/* 0x06b3: main_done */
-	0xbdfeb50e,
-	0x1f29f024,
-	0x080007f1,
-	0xd00203f0,
-	0x04bd0002,
-	0xfea00ef5,
-/* 0x06c8: ih */
-	0x88fe80f9,
-	0xf980f901,
-	0xf9a0f990,
-	0xf9d0f9b0,
-	0xbdf0f9e0,
-	0x00a7f104,
-	0x00a3f002,
-	0xc400aacf,
-	0x0bf404ab,
-	0x10d7f030,
-	0x1a00e7f1,
-	0xcf00e3f0,
-	0xf7f100ee,
-	0xf3f01900,
-	0x00ffcf00,
-	0xb70421f4,
-	0xf00400b0,
-	0x07f101e7,
-	0x03f01d00,
-	0x000ed000,
-/* 0x071a: ih_no_fifo */
-	0xabe404bd,
-	0x0bf40100,
-	0x10d7f00d,
-	0x4001e7f1,
-/* 0x072b: ih_no_ctxsw */
-	0xe40421f4,
-	0xf40400ab,
-	0xe7f16c0b,
-	0xe3f00708,
-	0x6821f440,
-	0xf102ffb9,
-	0xf0040007,
-	0x0fd00203,
-	0xf104bd00,
-	0xf00704e7,
-	0x21f440e3,
-	0x02ffb968,
-	0x030007f1,
-	0xd00203f0,
-	0x04bd000f,
-	0x9450fec7,
-	0xf7f102ee,
-	0xf3f00700,
-	0x00efbb40,
-	0xf16821f4,
-	0xf0020007,
-	0x0fd00203,
-	0xf004bd00,
-	0x21f503f7,
-	0xb7f1037e,
-	0xbfb90100,
-	0x44e7f102,
-	0x40e3f001,
-/* 0x079b: ih_no_fwmthd */
-	0xf19d21f4,
-	0xbd0504b7,
-	0xb4abffb0,
-	0xf10f0bf4,
-	0xf0070007,
-	0x0bd00303,
-/* 0x07b3: ih_no_other */
-	0xf104bd00,
-	0xf0010007,
-	0x0ad00003,
-	0xfc04bd00,
-	0xfce0fcf0,
-	0xfcb0fcd0,
-	0xfc90fca0,
-	0x0088fe80,
-	0x32f480fc,
-/* 0x07d7: ctx_4170s */
-	0xf001f800,
-	0xffb910f5,
-	0x70e7f102,
-	0x40e3f041,
-	0xf89d21f4,
-/* 0x07e9: ctx_4170w */
-	0x70e7f100,
-	0x40e3f041,
-	0xb96821f4,
-	0xf4f002ff,
-	0xf01bf410,
-/* 0x07fe: ctx_redswitch */
-	0xe7f100f8,
-	0xe5f00200,
-	0x20e5f040,
-	0xf110e5f0,
-	0xf0850007,
-	0x0ed00103,
-	0xf004bd00,
-/* 0x081a: ctx_redswitch_delay */
-	0xf2b608f7,
-	0xfd1bf401,
-	0x0400e5f1,
-	0x0100e5f1,
-	0x850007f1,
-	0xd00103f0,
-	0x04bd000e,
-/* 0x0836: ctx_86c */
-	0x07f100f8,
-	0x03f01b00,
-	0x000fd002,
-	0xffb904bd,
-	0x14e7f102,
-	0x40e3f08a,
-	0xb99d21f4,
-	0xe7f102ff,
-	0xe3f0a86c,
-	0x9d21f441,
-/* 0x085e: ctx_mem */
-	0x07f100f8,
-	0x03f08400,
-	0x000fd002,
-/* 0x086a: ctx_mem_wait */
-	0xf7f104bd,
-	0xf3f08400,
-	0x00ffcf02,
-	0xf405fffd,
-	0x00f8f31b,
-/* 0x087c: ctx_load */
-	0x99f094bd,
-	0x0007f105,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0ca7f004,
-	0xbdd021f4,
-	0x0007f1f4,
-	0x0203f089,
-	0xbd000fd0,
-	0x0007f104,
-	0x0203f0c1,
-	0xbd0002d0,
-	0x0007f104,
-	0x0203f083,
-	0xbd0002d0,
-	0x07f7f004,
-	0x085e21f5,
-	0xc00007f1,
-	0xd00203f0,
-	0x04bd0002,
-	0xf0000bfe,
-	0x24b61f2a,
-	0x0220b604,
-	0x99f094bd,
-	0x0007f108,
-	0x0203f00f,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f081,
-	0xbd0002d0,
-	0x0027f104,
-	0x0023f100,
-	0x0225f080,
-	0x880007f1,
-	0xd00203f0,
-	0x04bd0002,
-	0xf11017f0,
-	0xf0020027,
-	0x12fa0223,
-	0xbd03f805,
-	0x0899f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0xb6810198,
-	0x02981814,
-	0x0825b680,
-	0x800512fd,
-	0x94bd1601,
-	0xf10999f0,
-	0xf00f0007,
-	0x09d00203,
-	0xf104bd00,
-	0xf0810007,
-	0x01d00203,
-	0xf004bd00,
-	0x07f10127,
-	0x03f08800,
-	0x0002d002,
-	0x17f104bd,
-	0x13f00100,
-	0x0501fa06,
-	0x94bd03f8,
-	0xf10999f0,
-	0xf0170007,
-	0x09d00203,
-	0xbd04bd00,
-	0x0599f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-/* 0x099a: ctx_chan */
-	0x21f500f8,
-	0xa7f0087c,
-	0xd021f40c,
-	0xf505f7f0,
-	0xf8085e21,
-/* 0x09ad: ctx_mmio_exec */
-	0x41039800,
-	0x810007f1,
-	0xd00203f0,
-	0x04bd0003,
-/* 0x09be: ctx_mmio_loop */
-	0x34c434bd,
-	0x0f1bf4ff,
-	0x020057f1,
-	0xfa0653f0,
-	0x03f80535,
-/* 0x09d0: ctx_mmio_pull */
-	0x98804e98,
-	0x21f4814f,
-	0x0830b69d,
-	0xf40112b6,
-/* 0x09e2: ctx_mmio_done */
-	0x0398df1b,
-	0x0007f116,
-	0x0203f081,
-	0xbd0003d0,
-	0x40008004,
-	0x010017f1,
-	0xfa0613f0,
-	0x03f80601,
-/* 0x0a02: ctx_xfer */
-	0xe7f000f8,
-	0x0007f104,
-	0x0303f002,
-	0xbd000ed0,
-/* 0x0a11: ctx_xfer_idle */
-	0x00e7f104,
-	0x03e3f000,
-	0xf100eecf,
-	0xf42000e4,
-	0x11f4f21b,
-	0x0d02f406,
-/* 0x0a28: ctx_xfer_pre */
-	0xf510f7f0,
-	0xf4083621,
-/* 0x0a32: ctx_xfer_pre_load */
-	0xf7f01c11,
-	0xd721f502,
-	0xe921f507,
-	0xfe21f507,
-	0xf5f4bd07,
-	0xf507d721,
-/* 0x0a4b: ctx_xfer_exec */
-	0x98087c21,
-	0x24bd1601,
-	0x050007f1,
-	0xd00103f0,
-	0x04bd0002,
-	0xf1021fb9,
-	0xf0a500e7,
-	0x21f441e3,
-	0x01fcf09d,
-	0xb6022cf0,
-	0xf2fd0124,
-	0x02ffb905,
-	0xa504e7f1,
-	0xf441e3f0,
-	0x21f59d21,
-	0x24bd026a,
-	0x47fc07f1,
-	0xd00203f0,
-	0x04bd0002,
-	0xb6012cf0,
-	0x07f10320,
-	0x03f04afc,
-	0x0002d002,
-	0xacf004bd,
-	0x06a5f001,
-	0x9800b7f0,
-	0x0d98000c,
-	0x00e7f001,
-	0x016f21f5,
-	0xf508a7f0,
-	0xf5011021,
-	0xf4025e21,
-	0xa7f01301,
-	0xd021f40c,
-	0xf505f7f0,
-	0xf4085e21,
-/* 0x0ada: ctx_xfer_post */
-	0xf7f02e02,
-	0xd721f502,
-	0xf5f4bd07,
-	0xf5083621,
-	0xf5027f21,
-	0xbd07e921,
-	0xd721f5f4,
-	0x1011f407,
-	0xfd400198,
-	0x0bf40511,
-	0xad21f507,
-/* 0x0b05: ctx_xfer_no_post_mmio */
-/* 0x0b05: ctx_xfer_done */
-	0x0000f809,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc
deleted file mode 100644
index ec42ed29b50d..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#define CHIPSET GK110
-#include "macros.fuc"
-
-.section #nvf0_grhub_data
-#define INCLUDE_DATA
-#include "com.fuc"
-#include "hub.fuc"
-#undef INCLUDE_DATA
-
-.section #nvf0_grhub_code
-#define INCLUDE_CODE
-bra #init
-#include "com.fuc"
-#include "hub.fuc"
-.align 256
-#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h
deleted file mode 100644
index a0af4b703a8e..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h
+++ /dev/null
@@ -1,1044 +0,0 @@
-uint32_t nvf0_grhub_data[] = {
-/* 0x0000: hub_mmio_list_head */
-	0x00000300,
-/* 0x0004: hub_mmio_list_tail */
-	0x00000304,
-/* 0x0008: gpc_count */
-	0x00000000,
-/* 0x000c: rop_count */
-	0x00000000,
-/* 0x0010: cmd_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0058: ctx_current */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0100: chan_data */
-/* 0x0100: chan_mmio_count */
-	0x00000000,
-/* 0x0104: chan_mmio_address */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0200: xfer_data */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0300: hub_mmio_list_base */
-	0x0417e91c,
-};
-
-uint32_t nvf0_grhub_code[] = {
-	0x039b0ef5,
-/* 0x0004: queue_put */
-	0x9800d898,
-	0x86f001d9,
-	0x0489b808,
-	0xf00c1bf4,
-	0x21f502f7,
-	0x00f8037e,
-/* 0x001c: queue_put_next */
-	0xb60798c4,
-	0x8dbb0384,
-	0x0880b600,
-	0x80008e80,
-	0x90b6018f,
-	0x0f94f001,
-	0xf801d980,
-/* 0x0039: queue_get */
-	0x0131f400,
-	0x9800d898,
-	0x89b801d9,
-	0x210bf404,
-	0xb60789c4,
-	0x9dbb0394,
-	0x0890b600,
-	0x98009e98,
-	0x80b6019f,
-	0x0f84f001,
-	0xf400d880,
-/* 0x0066: queue_get_done */
-	0x00f80132,
-/* 0x0068: nv_rd32 */
-	0xf002ecb9,
-	0x07f11fc9,
-	0x03f0ca00,
-	0x000cd001,
-/* 0x007a: nv_rd32_wait */
-	0xc7f104bd,
-	0xc3f0ca00,
-	0x00cccf01,
-	0xf41fccc8,
-	0xa7f0f31b,
-	0x1021f506,
-	0x00f7f101,
-	0x01f3f0cb,
-	0xf800ffcf,
-/* 0x009d: nv_wr32 */
-	0x0007f100,
-	0x0103f0cc,
-	0xbd000fd0,
-	0x02ecb904,
-	0xf01fc9f0,
-	0x07f11ec9,
-	0x03f0ca00,
-	0x000cd001,
-/* 0x00be: nv_wr32_wait */
-	0xc7f104bd,
-	0xc3f0ca00,
-	0x00cccf01,
-	0xf41fccc8,
-	0x00f8f31b,
-/* 0x00d0: wait_donez */
-	0x99f094bd,
-	0x0007f100,
-	0x0203f037,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f006,
-	0xbd000ad0,
-/* 0x00ed: wait_donez_ne */
-	0x0087f104,
-	0x0183f000,
-	0xff0088cf,
-	0x1bf4888a,
-	0xf094bdf3,
-	0x07f10099,
-	0x03f01700,
-	0x0009d002,
-	0x00f804bd,
-/* 0x0110: wait_doneo */
-	0x99f094bd,
-	0x0007f100,
-	0x0203f037,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f006,
-	0xbd000ad0,
-/* 0x012d: wait_doneo_e */
-	0x0087f104,
-	0x0183f000,
-	0xff0088cf,
-	0x0bf4888a,
-	0xf094bdf3,
-	0x07f10099,
-	0x03f01700,
-	0x0009d002,
-	0x00f804bd,
-/* 0x0150: mmctx_size */
-/* 0x0152: nv_mmctx_size_loop */
-	0xe89894bd,
-	0x1a85b600,
-	0xb60180b6,
-	0x98bb0284,
-	0x04e0b600,
-	0xf404efb8,
-	0x9fb9eb1b,
-/* 0x016f: mmctx_xfer */
-	0xbd00f802,
-	0x0199f094,
-	0x370007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0xbbfd94bd,
-	0x120bf405,
-	0xc40007f1,
-	0xd00103f0,
-	0x04bd000b,
-/* 0x0197: mmctx_base_disabled */
-	0xfd0099f0,
-	0x0bf405ee,
-	0x0007f11e,
-	0x0103f0c6,
-	0xbd000ed0,
-	0x0007f104,
-	0x0103f0c7,
-	0xbd000fd0,
-	0x0199f004,
-/* 0x01b8: mmctx_multi_disabled */
-	0xb600abc8,
-	0xb9f010b4,
-	0x01aec80c,
-	0xfd11e4b6,
-	0x07f105be,
-	0x03f0c500,
-	0x000bd001,
-/* 0x01d6: mmctx_exec_loop */
-/* 0x01d6: mmctx_wait_free */
-	0xe7f104bd,
-	0xe3f0c500,
-	0x00eecf01,
-	0xf41fe4f0,
-	0xce98f30b,
-	0x05e9fd00,
-	0xc80007f1,
-	0xd00103f0,
-	0x04bd000e,
-	0xb804c0b6,
-	0x1bf404cd,
-	0x02abc8d8,
-/* 0x0207: mmctx_fini_wait */
-	0xf11f1bf4,
-	0xf0c500b7,
-	0xbbcf01b3,
-	0x1fb4f000,
-	0xf410b4b0,
-	0xa7f0f01b,
-	0xd021f405,
-/* 0x0223: mmctx_stop */
-	0xc82b0ef4,
-	0xb4b600ab,
-	0x0cb9f010,
-	0xf112b9f0,
-	0xf0c50007,
-	0x0bd00103,
-/* 0x023b: mmctx_stop_wait */
-	0xf104bd00,
-	0xf0c500b7,
-	0xbbcf01b3,
-	0x12bbc800,
-/* 0x024b: mmctx_done */
-	0xbdf31bf4,
-	0x0199f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-/* 0x025e: strand_wait */
-	0xa0f900f8,
-	0xf402a7f0,
-	0xa0fcd021,
-/* 0x026a: strand_pre */
-	0x97f000f8,
-	0xfc07f10c,
-	0x0203f04a,
-	0xbd0009d0,
-	0x5e21f504,
-/* 0x027f: strand_post */
-	0xf000f802,
-	0x07f10d97,
-	0x03f04afc,
-	0x0009d002,
-	0x21f504bd,
-	0x00f8025e,
-/* 0x0294: strand_set */
-	0xf10fc7f0,
-	0xf04ffc07,
-	0x0cd00203,
-	0xf004bd00,
-	0x07f10bc7,
-	0x03f04afc,
-	0x000cd002,
-	0x07f104bd,
-	0x03f04ffc,
-	0x000ed002,
-	0xc7f004bd,
-	0xfc07f10a,
-	0x0203f04a,
-	0xbd000cd0,
-	0x5e21f504,
-/* 0x02d3: strand_ctx_init */
-	0xbd00f802,
-	0x0399f094,
-	0x370007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0x026a21f5,
-	0xf503e7f0,
-	0xbd029421,
-	0xfc07f1c4,
-	0x0203f047,
-	0xbd000cd0,
-	0x01c7f004,
-	0x4afc07f1,
-	0xd00203f0,
-	0x04bd000c,
-	0x025e21f5,
-	0xf1010c92,
-	0xf046fc07,
-	0x0cd00203,
-	0xf004bd00,
-	0x07f102c7,
-	0x03f04afc,
-	0x000cd002,
-	0x21f504bd,
-	0x21f5025e,
-	0x87f1027f,
-	0x83f04200,
-	0x0097f102,
-	0x0293f020,
-	0x950099cf,
-/* 0x034a: ctx_init_strand_loop */
-	0x8ed008fe,
-	0x408ed000,
-	0xb6808acf,
-	0xa0b606a5,
-	0x00eabb01,
-	0xb60480b6,
-	0x1bf40192,
-	0x08e4b6e8,
-	0xbdf2efbc,
-	0x0399f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-/* 0x037e: error */
-	0x07f100f8,
-	0x03f00500,
-	0x000fd002,
-	0xf7f004bd,
-	0x0007f101,
-	0x0303f007,
-	0xbd000fd0,
-/* 0x039b: init */
-	0xbd00f804,
-	0x0007fe04,
-	0x420017f1,
-	0xcf0013f0,
-	0x11e70011,
-	0x14b60109,
-	0x0014fe08,
-	0xf10227f0,
-	0xf0120007,
-	0x02d00003,
-	0xf104bd00,
-	0xfe06c817,
-	0x24bd0010,
-	0x070007f1,
-	0xd00003f0,
-	0x04bd0002,
-	0x200327f1,
-	0x010007f1,
-	0xd00103f0,
-	0x04bd0002,
-	0x200427f1,
-	0x010407f1,
-	0xd00103f0,
-	0x04bd0002,
-	0x200b27f1,
-	0x010807f1,
-	0xd00103f0,
-	0x04bd0002,
-	0x200c27f1,
-	0x011c07f1,
-	0xd00103f0,
-	0x04bd0002,
-	0xf1010392,
-	0xf0090007,
-	0x03d00303,
-	0xf104bd00,
-	0xf0870427,
-	0x07f10023,
-	0x03f00400,
-	0x0002d000,
-	0x27f004bd,
-	0x0007f104,
-	0x0003f003,
-	0xbd0002d0,
-	0x1031f404,
-	0x9604e7f1,
-	0xf440e3f0,
-	0xfeb96821,
-	0x90f1c702,
-	0xf0030180,
-	0x0f801ff4,
-	0x0117f002,
-	0xb6041fbb,
-	0x07f10112,
-	0x03f00300,
-	0x0001d001,
-	0x07f104bd,
-	0x03f00400,
-	0x0001d001,
-	0x17f104bd,
-	0xf7f00100,
-	0xd721f502,
-	0xe921f507,
-	0x10f7f007,
-	0x083621f5,
-	0x98000e98,
-	0x21f5010f,
-	0x14950150,
-	0x0007f108,
-	0x0103f0c0,
-	0xbd0004d0,
-	0x0007f104,
-	0x0103f0c1,
-	0xbd0004d0,
-	0x0030b704,
-	0x001fbb13,
-	0xf102f5b6,
-	0xf0d30007,
-	0x0fd00103,
-	0xb604bd00,
-	0x10b60815,
-	0x0814b601,
-	0xf5021fb9,
-	0xbb02d321,
-	0x0398001f,
-	0x0047f102,
-	0x5043f020,
-/* 0x04f4: init_gpc */
-	0x08044ea0,
-	0xf4021fb9,
-	0x4ea09d21,
-	0xf4bd010c,
-	0xa09d21f4,
-	0xf401044e,
-	0x4ea09d21,
-	0xf7f00100,
-	0x9d21f402,
-	0x08004ea0,
-/* 0x051c: init_gpc_wait */
-	0xc86821f4,
-	0x0bf41fff,
-	0x044ea0fa,
-	0x6821f408,
-	0xb7001fbb,
-	0xb6800040,
-	0x1bf40132,
-	0x00f7f0be,
-	0x083621f5,
-	0xf500f7f0,
-	0xf107d721,
-	0xf0010007,
-	0x01d00203,
-	0xbd04bd00,
-	0x1f19f014,
-	0x300007f1,
-	0xd00203f0,
-	0x04bd0001,
-/* 0x0564: main */
-	0xf40031f4,
-	0xd7f00028,
-	0x3921f410,
-	0xb1f401f4,
-	0xf54001e4,
-	0xbd00e91b,
-	0x0499f094,
-	0x370007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0xc00017f1,
-	0xcf0213f0,
-	0x27f10011,
-	0x23f0c100,
-	0x0022cf02,
-	0xf51f13c8,
-	0xc800890b,
-	0x0bf41f23,
-	0xb920f962,
-	0x94bd0212,
-	0xf10799f0,
-	0xf0370007,
-	0x09d00203,
-	0xf404bd00,
-	0x31f40132,
-	0x0221f502,
-	0xf094bd0a,
-	0x07f10799,
-	0x03f01700,
-	0x0009d002,
-	0x20fc04bd,
-	0x99f094bd,
-	0x0007f106,
-	0x0203f037,
-	0xbd0009d0,
-	0x0131f404,
-	0x0a0221f5,
-	0x99f094bd,
-	0x0007f106,
-	0x0203f017,
-	0xbd0009d0,
-	0x330ef404,
-/* 0x060c: chsw_prev_no_next */
-	0x12b920f9,
-	0x0132f402,
-	0xf50232f4,
-	0xfc0a0221,
-	0x0007f120,
-	0x0203f0c0,
-	0xbd0002d0,
-	0x130ef404,
-/* 0x062c: chsw_no_prev */
-	0xf41f23c8,
-	0x31f40d0b,
-	0x0232f401,
-	0x0a0221f5,
-/* 0x063c: chsw_done */
-	0xf10127f0,
-	0xf0c30007,
-	0x02d00203,
-	0xbd04bd00,
-	0x0499f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0xff080ef5,
-/* 0x0660: main_not_ctx_switch */
-	0xf401e4b0,
-	0xf2b90d1b,
-	0x9a21f502,
-	0x460ef409,
-/* 0x0670: main_not_ctx_chan */
-	0xf402e4b0,
-	0x94bd321b,
-	0xf10799f0,
-	0xf0370007,
-	0x09d00203,
-	0xf404bd00,
-	0x32f40132,
-	0x0221f502,
-	0xf094bd0a,
-	0x07f10799,
-	0x03f01700,
-	0x0009d002,
-	0x0ef404bd,
-/* 0x06a5: main_not_ctx_save */
-	0x10ef9411,
-	0xf501f5f0,
-	0xf5037e21,
-/* 0x06b3: main_done */
-	0xbdfeb50e,
-	0x1f29f024,
-	0x300007f1,
-	0xd00203f0,
-	0x04bd0002,
-	0xfea00ef5,
-/* 0x06c8: ih */
-	0x88fe80f9,
-	0xf980f901,
-	0xf9a0f990,
-	0xf9d0f9b0,
-	0xbdf0f9e0,
-	0x00a7f104,
-	0x00a3f002,
-	0xc400aacf,
-	0x0bf404ab,
-	0x10d7f030,
-	0x1a00e7f1,
-	0xcf00e3f0,
-	0xf7f100ee,
-	0xf3f01900,
-	0x00ffcf00,
-	0xb70421f4,
-	0xf00400b0,
-	0x07f101e7,
-	0x03f01d00,
-	0x000ed000,
-/* 0x071a: ih_no_fifo */
-	0xabe404bd,
-	0x0bf40100,
-	0x10d7f00d,
-	0x4001e7f1,
-/* 0x072b: ih_no_ctxsw */
-	0xe40421f4,
-	0xf40400ab,
-	0xe7f16c0b,
-	0xe3f00708,
-	0x6821f440,
-	0xf102ffb9,
-	0xf0040007,
-	0x0fd00203,
-	0xf104bd00,
-	0xf00704e7,
-	0x21f440e3,
-	0x02ffb968,
-	0x030007f1,
-	0xd00203f0,
-	0x04bd000f,
-	0x9450fec7,
-	0xf7f102ee,
-	0xf3f00700,
-	0x00efbb40,
-	0xf16821f4,
-	0xf0020007,
-	0x0fd00203,
-	0xf004bd00,
-	0x21f503f7,
-	0xb7f1037e,
-	0xbfb90100,
-	0x44e7f102,
-	0x40e3f001,
-/* 0x079b: ih_no_fwmthd */
-	0xf19d21f4,
-	0xbd0504b7,
-	0xb4abffb0,
-	0xf10f0bf4,
-	0xf0070007,
-	0x0bd00303,
-/* 0x07b3: ih_no_other */
-	0xf104bd00,
-	0xf0010007,
-	0x0ad00003,
-	0xfc04bd00,
-	0xfce0fcf0,
-	0xfcb0fcd0,
-	0xfc90fca0,
-	0x0088fe80,
-	0x32f480fc,
-/* 0x07d7: ctx_4170s */
-	0xf001f800,
-	0xffb910f5,
-	0x70e7f102,
-	0x40e3f041,
-	0xf89d21f4,
-/* 0x07e9: ctx_4170w */
-	0x70e7f100,
-	0x40e3f041,
-	0xb96821f4,
-	0xf4f002ff,
-	0xf01bf410,
-/* 0x07fe: ctx_redswitch */
-	0xe7f100f8,
-	0xe5f00200,
-	0x20e5f040,
-	0xf110e5f0,
-	0xf0850007,
-	0x0ed00103,
-	0xf004bd00,
-/* 0x081a: ctx_redswitch_delay */
-	0xf2b608f7,
-	0xfd1bf401,
-	0x0400e5f1,
-	0x0100e5f1,
-	0x850007f1,
-	0xd00103f0,
-	0x04bd000e,
-/* 0x0836: ctx_86c */
-	0x07f100f8,
-	0x03f02300,
-	0x000fd002,
-	0xffb904bd,
-	0x14e7f102,
-	0x40e3f08a,
-	0xb99d21f4,
-	0xe7f102ff,
-	0xe3f0a88c,
-	0x9d21f441,
-/* 0x085e: ctx_mem */
-	0x07f100f8,
-	0x03f08400,
-	0x000fd002,
-/* 0x086a: ctx_mem_wait */
-	0xf7f104bd,
-	0xf3f08400,
-	0x00ffcf02,
-	0xf405fffd,
-	0x00f8f31b,
-/* 0x087c: ctx_load */
-	0x99f094bd,
-	0x0007f105,
-	0x0203f037,
-	0xbd0009d0,
-	0x0ca7f004,
-	0xbdd021f4,
-	0x0007f1f4,
-	0x0203f089,
-	0xbd000fd0,
-	0x0007f104,
-	0x0203f0c1,
-	0xbd0002d0,
-	0x0007f104,
-	0x0203f083,
-	0xbd0002d0,
-	0x07f7f004,
-	0x085e21f5,
-	0xc00007f1,
-	0xd00203f0,
-	0x04bd0002,
-	0xf0000bfe,
-	0x24b61f2a,
-	0x0220b604,
-	0x99f094bd,
-	0x0007f108,
-	0x0203f037,
-	0xbd0009d0,
-	0x0007f104,
-	0x0203f081,
-	0xbd0002d0,
-	0x0027f104,
-	0x0023f100,
-	0x0225f080,
-	0x880007f1,
-	0xd00203f0,
-	0x04bd0002,
-	0xf11017f0,
-	0xf0020027,
-	0x12fa0223,
-	0xbd03f805,
-	0x0899f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-	0xb6810198,
-	0x02981814,
-	0x0825b680,
-	0x800512fd,
-	0x94bd1601,
-	0xf10999f0,
-	0xf0370007,
-	0x09d00203,
-	0xf104bd00,
-	0xf0810007,
-	0x01d00203,
-	0xf004bd00,
-	0x07f10127,
-	0x03f08800,
-	0x0002d002,
-	0x17f104bd,
-	0x13f00100,
-	0x0501fa06,
-	0x94bd03f8,
-	0xf10999f0,
-	0xf0170007,
-	0x09d00203,
-	0xbd04bd00,
-	0x0599f094,
-	0x170007f1,
-	0xd00203f0,
-	0x04bd0009,
-/* 0x099a: ctx_chan */
-	0x21f500f8,
-	0xa7f0087c,
-	0xd021f40c,
-	0xf505f7f0,
-	0xf8085e21,
-/* 0x09ad: ctx_mmio_exec */
-	0x41039800,
-	0x810007f1,
-	0xd00203f0,
-	0x04bd0003,
-/* 0x09be: ctx_mmio_loop */
-	0x34c434bd,
-	0x0f1bf4ff,
-	0x020057f1,
-	0xfa0653f0,
-	0x03f80535,
-/* 0x09d0: ctx_mmio_pull */
-	0x98804e98,
-	0x21f4814f,
-	0x0830b69d,
-	0xf40112b6,
-/* 0x09e2: ctx_mmio_done */
-	0x0398df1b,
-	0x0007f116,
-	0x0203f081,
-	0xbd0003d0,
-	0x40008004,
-	0x010017f1,
-	0xfa0613f0,
-	0x03f80601,
-/* 0x0a02: ctx_xfer */
-	0xe7f000f8,
-	0x0007f104,
-	0x0303f002,
-	0xbd000ed0,
-/* 0x0a11: ctx_xfer_idle */
-	0x00e7f104,
-	0x03e3f000,
-	0xf100eecf,
-	0xf42000e4,
-	0x11f4f21b,
-	0x0d02f406,
-/* 0x0a28: ctx_xfer_pre */
-	0xf510f7f0,
-	0xf4083621,
-/* 0x0a32: ctx_xfer_pre_load */
-	0xf7f01c11,
-	0xd721f502,
-	0xe921f507,
-	0xfe21f507,
-	0xf5f4bd07,
-	0xf507d721,
-/* 0x0a4b: ctx_xfer_exec */
-	0x98087c21,
-	0x24bd1601,
-	0x050007f1,
-	0xd00103f0,
-	0x04bd0002,
-	0xf1021fb9,
-	0xf0a500e7,
-	0x21f441e3,
-	0x01fcf09d,
-	0xb6022cf0,
-	0xf2fd0124,
-	0x02ffb905,
-	0xa504e7f1,
-	0xf441e3f0,
-	0x21f59d21,
-	0x24bd026a,
-	0x47fc07f1,
-	0xd00203f0,
-	0x04bd0002,
-	0xb6012cf0,
-	0x07f10320,
-	0x03f04afc,
-	0x0002d002,
-	0xacf004bd,
-	0x06a5f001,
-	0x9800b7f0,
-	0x0d98000c,
-	0x00e7f001,
-	0x016f21f5,
-	0xf508a7f0,
-	0xf5011021,
-	0xf4025e21,
-	0xa7f01301,
-	0xd021f40c,
-	0xf505f7f0,
-	0xf4085e21,
-/* 0x0ada: ctx_xfer_post */
-	0xf7f02e02,
-	0xd721f502,
-	0xf5f4bd07,
-	0xf5083621,
-	0xf5027f21,
-	0xbd07e921,
-	0xd721f5f4,
-	0x1011f407,
-	0xfd400198,
-	0x0bf40511,
-	0xad21f507,
-/* 0x0b05: ctx_xfer_no_post_mmio */
-/* 0x0b05: ctx_xfer_done */
-	0x0000f809,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc
deleted file mode 100644
index 2a0b0f844299..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "os.h"
-
-#define GF100 0xc0
-#define GF117 0xd7
-#define GK100 0xe0
-#define GK110 0xf0
-#define GK208 0x108
-
-#define NV_PGRAPH_TRAPPED_ADDR                                         0x400704
-#define NV_PGRAPH_TRAPPED_DATA_LO                                      0x400708
-#define NV_PGRAPH_TRAPPED_DATA_HI                                      0x40070c
-
-#define NV_PGRAPH_FE_OBJECT_TABLE(n)                        ((n) * 4 + 0x400700)
-
-#define NV_PGRAPH_FECS_INTR_ACK                                        0x409004
-#define NV_PGRAPH_FECS_INTR                                            0x409008
-#define NV_PGRAPH_FECS_INTR_FWMTHD                                   0x00000400
-#define NV_PGRAPH_FECS_INTR_CHSW                                     0x00000100
-#define NV_PGRAPH_FECS_INTR_FIFO                                     0x00000004
-#define NV_PGRAPH_FECS_INTR_MODE                                       0x40900c
-#define NV_PGRAPH_FECS_INTR_MODE_FIFO                                0x00000004
-#define NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL                          0x00000004
-#define NV_PGRAPH_FECS_INTR_MODE_FIFO_EDGE                           0x00000000
-#define NV_PGRAPH_FECS_INTR_EN_SET                                     0x409010
-#define NV_PGRAPH_FECS_INTR_EN_SET_FIFO                              0x00000004
-#define NV_PGRAPH_FECS_INTR_ROUTE                                      0x40901c
-#define NV_PGRAPH_FECS_ACCESS                                          0x409048
-#define NV_PGRAPH_FECS_ACCESS_FIFO                                   0x00000002
-#define NV_PGRAPH_FECS_FIFO_DATA                                       0x409064
-#define NV_PGRAPH_FECS_FIFO_CMD                                        0x409068
-#define NV_PGRAPH_FECS_FIFO_ACK                                        0x409074
-#define NV_PGRAPH_FECS_CAPS                                            0x409108
-#define NV_PGRAPH_FECS_SIGNAL                                          0x409400
-#define NV_PGRAPH_FECS_IROUTE                                          0x409404
-#define NV_PGRAPH_FECS_BAR_MASK0                                       0x40940c
-#define NV_PGRAPH_FECS_BAR_MASK1                                       0x409410
-#define NV_PGRAPH_FECS_BAR                                             0x409414
-#define NV_PGRAPH_FECS_BAR_SET                                         0x409418
-#define NV_PGRAPH_FECS_RED_SWITCH                                      0x409614
-#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP                         0x00000400
-#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC                         0x00000200
-#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN                        0x00000100
-#define NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP                          0x00000040
-#define NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC                          0x00000020
-#define NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN                         0x00000010
-#define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_GPC                          0x00000002
-#define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_MAIN                         0x00000001
-#define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE                               0x409700
-#define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE                               0x409704
-#define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT                                0x40974c
-#define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE                               0x409700
-#define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE                               0x409704
-#define NV_PGRAPH_FECS_MMCTX_BASE                                      0x409710
-#define NV_PGRAPH_FECS_MMCTX_CTRL                                      0x409714
-#define NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE                              0x409718
-#define NV_PGRAPH_FECS_MMCTX_MULTI_MASK                                0x40971c
-#define NV_PGRAPH_FECS_MMCTX_QUEUE                                     0x409720
-#define NV_PGRAPH_FECS_MMIO_CTRL                                       0x409728
-#define NV_PGRAPH_FECS_MMIO_RDVAL                                      0x40972c
-#define NV_PGRAPH_FECS_MMIO_WRVAL                                      0x409730
-#define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT                                0x40974c
-#if CHIPSET < GK110
-#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n)                    ((n) * 4 + 0x409800)
-#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n)                    ((n) * 4 + 0x409820)
-#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n)                    ((n) * 4 + 0x409840)
-#define NV_PGRAPH_FECS_UNK86C                                          0x40986c
-#else
-#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n)                    ((n) * 4 + 0x409800)
-#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n)                    ((n) * 4 + 0x409840)
-#define NV_PGRAPH_FECS_UNK86C                                          0x40988c
-#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n)                    ((n) * 4 + 0x4098c0)
-#endif
-#define NV_PGRAPH_FECS_STRANDS_CNT                                     0x409880
-#define NV_PGRAPH_FECS_STRAND_SAVE_SWBASE                              0x409908
-#define NV_PGRAPH_FECS_STRAND_LOAD_SWBASE                              0x40990c
-#define NV_PGRAPH_FECS_STRAND_WORDS                                    0x409910
-#define NV_PGRAPH_FECS_STRAND_DATA                                     0x409918
-#define NV_PGRAPH_FECS_STRAND_SELECT                                   0x40991c
-#define NV_PGRAPH_FECS_STRAND_CMD                                      0x409928
-#define NV_PGRAPH_FECS_STRAND_CMD_SEEK                               0x00000001
-#define NV_PGRAPH_FECS_STRAND_CMD_GET_INFO                           0x00000002
-#define NV_PGRAPH_FECS_STRAND_CMD_SAVE                               0x00000003
-#define NV_PGRAPH_FECS_STRAND_CMD_LOAD                               0x00000004
-#define NV_PGRAPH_FECS_STRAND_CMD_ACTIVATE_FILTER                    0x0000000a
-#define NV_PGRAPH_FECS_STRAND_CMD_DEACTIVATE_FILTER                  0x0000000b
-#define NV_PGRAPH_FECS_STRAND_CMD_ENABLE                             0x0000000c
-#define NV_PGRAPH_FECS_STRAND_CMD_DISABLE                            0x0000000d
-#define NV_PGRAPH_FECS_STRAND_FILTER                                   0x40993c
-#define NV_PGRAPH_FECS_MEM_BASE                                        0x409a04
-#define NV_PGRAPH_FECS_MEM_CHAN                                        0x409a0c
-#define NV_PGRAPH_FECS_MEM_CMD                                         0x409a10
-#define NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN                             0x00000007
-#define NV_PGRAPH_FECS_MEM_TARGET                                      0x409a20
-#define NV_PGRAPH_FECS_MEM_TARGET_UNK31                              0x80000000
-#define NV_PGRAPH_FECS_MEM_TARGET_AS                                 0x0000001f
-#define NV_PGRAPH_FECS_MEM_TARGET_AS_VM                              0x00000001
-#define NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM                            0x00000002
-#define NV_PGRAPH_FECS_CHAN_ADDR                                       0x409b00
-#define NV_PGRAPH_FECS_CHAN_NEXT                                       0x409b04
-#define NV_PGRAPH_FECS_CHSW                                            0x409b0c
-#define NV_PGRAPH_FECS_CHSW_ACK                                      0x00000001
-#define NV_PGRAPH_FECS_INTR_UP_SET                                     0x409c1c
-#define NV_PGRAPH_FECS_INTR_UP_EN                                      0x409c24
-
-#define NV_PGRAPH_GPCX_GPCCS_INTR_ACK                                  0x41a004
-#define NV_PGRAPH_GPCX_GPCCS_INTR                                      0x41a008
-#define NV_PGRAPH_GPCX_GPCCS_INTR_FIFO                               0x00000004
-#define NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET                               0x41a010
-#define NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO                        0x00000004
-#define NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE                                0x41a01c
-#define NV_PGRAPH_GPCX_GPCCS_ACCESS                                    0x41a048
-#define NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO                             0x00000002
-#define NV_PGRAPH_GPCX_GPCCS_FIFO_DATA                                 0x41a064
-#define NV_PGRAPH_GPCX_GPCCS_FIFO_CMD                                  0x41a068
-#define NV_PGRAPH_GPCX_GPCCS_FIFO_ACK                                  0x41a074
-#define NV_PGRAPH_GPCX_GPCCS_UNITS                                     0x41a608
-#define NV_PGRAPH_GPCX_GPCCS_CAPS                                      0x41a108
-#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH                                0x41a614
-#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11                        0x00000800
-#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE                       0x00000200
-#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER                        0x00000020
-#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_PAUSE                        0x00000002
-#define NV_PGRAPH_GPCX_GPCCS_MYINDEX                                   0x41a618
-#define NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE                         0x41a700
-#define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE                         0x41a704
-#define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT                          0x41a74c
-#if CHIPSET < GK110
-#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n)              ((n) * 4 + 0x41a800)
-#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n)              ((n) * 4 + 0x41a820)
-#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n)              ((n) * 4 + 0x41a840)
-#define NV_PGRAPH_GPCX_GPCCS_UNK86C                                    0x41a86c
-#else
-#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n)              ((n) * 4 + 0x41a800)
-#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n)              ((n) * 4 + 0x41a840)
-#define NV_PGRAPH_GPCX_GPCCS_UNK86C                                    0x41a88c
-#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n)              ((n) * 4 + 0x41a8c0)
-#endif
-#define NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT                             0x41a91c
-#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD                                0x41a928
-#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE                         0x00000003
-#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_LOAD                         0x00000004
-#define NV_PGRAPH_GPCX_GPCCS_MEM_BASE                                  0x41aa04
-
-#define mmctx_data(r,c) .b32 (((c - 1) << 26) | r)
-#define queue_init      .skip 72 // (2 * 4) + ((8 * 4) * 2)
-
-#define T_WAIT    0
-#define T_MMCTX   1
-#define T_STRWAIT 2
-#define T_STRINIT 3
-#define T_AUTO    4
-#define T_CHAN    5
-#define T_LOAD    6
-#define T_SAVE    7
-#define T_LCHAN   8
-#define T_LCTXH   9
-
-#if CHIPSET < GK208
-#define imm32(reg,val) /*
-*/	movw reg  ((val) & 0x0000ffff) /*
-*/	sethi reg ((val) & 0xffff0000)
-#else
-#define imm32(reg,val) /*
-*/	mov reg (val)
-#endif
-
-#define nv_mkio(rv,r,i) /*
-*/	imm32(rv, (((r) & 0xffc) << 6) | ((i) << 2))
-
-#define hash #
-#define fn(a) a
-#if CHIPSET < GK208
-#define call(a) call fn(hash)a
-#else
-#define call(a) lcall fn(hash)a
-#endif
-
-#define nv_iord(rv,r,i) /*
-*/	nv_mkio(rv,r,i) /*
-*/	iord rv I[rv]
-
-#define nv_iowr(r,i,rv) /*
-*/	nv_mkio($r0,r,i) /*
-*/	iowr I[$r0] rv /*
-*/	clear b32 $r0
-
-#define nv_rd32(reg,addr) /*
-*/	imm32($r14, addr) /*
-*/	call(nv_rd32) /*
-*/	mov b32 reg $r15
-
-#define nv_wr32(addr,reg) /*
-*/	mov b32 $r15 reg /*
-*/	imm32($r14, addr) /*
-*/	call(nv_wr32)
-
-#define trace_set(bit) /*
-*/	clear b32 $r9 /*
-*/	bset $r9 bit /*
-*/	nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(7), 0, $r9)
-
-#define trace_clr(bit) /*
-*/	clear b32 $r9 /*
-*/	bset $r9 bit /*
-*/	nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_CLR(7), 0, $r9)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h
deleted file mode 100644
index 1718ae4e8224..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __NVKM_GRAPH_OS_H__
-#define __NVKM_GRAPH_OS_H__
-
-#define E_BAD_COMMAND  0x00000001
-#define E_CMD_OVERFLOW 0x00000002
-#define E_BAD_FWMTHD   0x00000003
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/gk110b.c b/drivers/gpu/drm/nouveau/core/engine/graph/gk110b.c
deleted file mode 100644
index d07b19dc168d..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/gk110b.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * PGRAPH register lists
- ******************************************************************************/
-
-static const struct nvc0_graph_init
-gk110b_graph_init_l1c_0[] = {
-	{ 0x419c98,   1, 0x04, 0x00000000 },
-	{ 0x419ca8,   1, 0x04, 0x00000000 },
-	{ 0x419cb0,   1, 0x04, 0x09000000 },
-	{ 0x419cb4,   1, 0x04, 0x00000000 },
-	{ 0x419cb8,   1, 0x04, 0x00b08bea },
-	{ 0x419c84,   1, 0x04, 0x00010384 },
-	{ 0x419cbc,   1, 0x04, 0x281b3646 },
-	{ 0x419cc0,   2, 0x04, 0x00000000 },
-	{ 0x419c80,   1, 0x04, 0x00020230 },
-	{ 0x419ccc,   2, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gk110b_graph_init_sm_0[] = {
-	{ 0x419e00,   1, 0x04, 0x00000080 },
-	{ 0x419ea0,   1, 0x04, 0x00000000 },
-	{ 0x419ee4,   1, 0x04, 0x00000000 },
-	{ 0x419ea4,   1, 0x04, 0x00000100 },
-	{ 0x419ea8,   1, 0x04, 0x00000000 },
-	{ 0x419eb4,   1, 0x04, 0x00000000 },
-	{ 0x419ebc,   2, 0x04, 0x00000000 },
-	{ 0x419edc,   1, 0x04, 0x00000000 },
-	{ 0x419f00,   1, 0x04, 0x00000000 },
-	{ 0x419ed0,   1, 0x04, 0x00002616 },
-	{ 0x419f74,   1, 0x04, 0x00015555 },
-	{ 0x419f80,   4, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-gk110b_graph_pack_mmio[] = {
-	{ nve4_graph_init_main_0 },
-	{ nvf0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvd9_graph_init_pd_0 },
-	{ nvf0_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvf0_graph_init_sked_0 },
-	{ nvf0_graph_init_cwd_0 },
-	{ nvd9_graph_init_prop_0 },
-	{ nvc1_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc1_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvd9_graph_init_gpm_0 },
-	{ nvf0_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nve4_graph_init_tpccs_0 },
-	{ nvf0_graph_init_tex_0 },
-	{ nve4_graph_init_pe_0 },
-	{ gk110b_graph_init_l1c_0 },
-	{ nvc0_graph_init_mpc_0 },
-	{ gk110b_graph_init_sm_0 },
-	{ nvd7_graph_init_pes_0 },
-	{ nvd7_graph_init_wwdx_0 },
-	{ nvd7_graph_init_cbm_0 },
-	{ nve4_graph_init_be_0 },
-	{ nvc0_graph_init_fe_1 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-struct nouveau_oclass *
-gk110b_graph_oclass = &(struct nvc0_graph_oclass) {
-	.base.handle = NV_ENGINE(GR, 0xf1),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nve4_graph_init,
-		.fini = nvf0_graph_fini,
-	},
-	.cclass = &gk110b_grctx_oclass,
-	.sclass =  nvf0_graph_sclass,
-	.mmio = gk110b_graph_pack_mmio,
-	.fecs.ucode = &nvf0_graph_fecs_ucode,
-	.gpccs.ucode = &nvf0_graph_gpccs_ucode,
-	.ppc_nr = 2,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/gk20a.c b/drivers/gpu/drm/nouveau/core/engine/graph/gk20a.c
deleted file mode 100644
index 7d0abe9f3fe7..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/gk20a.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
-
-static struct nouveau_oclass
-gk20a_graph_sclass[] = {
-	{ 0x902d, &nouveau_object_ofuncs },
-	{ 0xa040, &nouveau_object_ofuncs },
-	{ KEPLER_C, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
-	{}
-};
-
-struct nouveau_oclass *
-gk20a_graph_oclass = &(struct nvc0_graph_oclass) {
-	.base.handle = NV_ENGINE(GR, 0xea),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nve4_graph_init,
-		.fini = _nouveau_graph_fini,
-	},
-	.cclass = &gk20a_grctx_oclass,
-	.sclass = gk20a_graph_sclass,
-	.mmio = nve4_graph_pack_mmio,
-	.ppc_nr = 1,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/gm107.c b/drivers/gpu/drm/nouveau/core/engine/graph/gm107.c
deleted file mode 100644
index 4bdbdab2fd9a..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/gm107.c
+++ /dev/null
@@ -1,469 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/P0260.h>
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-gm107_graph_sclass[] = {
-	{ 0x902d, &nouveau_object_ofuncs },
-	{ 0xa140, &nouveau_object_ofuncs },
-	{ MAXWELL_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ MAXWELL_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH register lists
- ******************************************************************************/
-
-static const struct nvc0_graph_init
-gm107_graph_init_main_0[] = {
-	{ 0x400080,   1, 0x04, 0x003003c2 },
-	{ 0x400088,   1, 0x04, 0x0001bfe7 },
-	{ 0x40008c,   1, 0x04, 0x00060000 },
-	{ 0x400090,   1, 0x04, 0x00000030 },
-	{ 0x40013c,   1, 0x04, 0x003901f3 },
-	{ 0x400140,   1, 0x04, 0x00000100 },
-	{ 0x400144,   1, 0x04, 0x00000000 },
-	{ 0x400148,   1, 0x04, 0x00000110 },
-	{ 0x400138,   1, 0x04, 0x00000000 },
-	{ 0x400130,   2, 0x04, 0x00000000 },
-	{ 0x400124,   1, 0x04, 0x00000002 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_graph_init_ds_0[] = {
-	{ 0x405844,   1, 0x04, 0x00ffffff },
-	{ 0x405850,   1, 0x04, 0x00000000 },
-	{ 0x405900,   1, 0x04, 0x00000000 },
-	{ 0x405908,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_graph_init_scc_0[] = {
-	{ 0x40803c,   1, 0x04, 0x00000010 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_graph_init_sked_0[] = {
-	{ 0x407010,   1, 0x04, 0x00000000 },
-	{ 0x407040,   1, 0x04, 0x40440424 },
-	{ 0x407048,   1, 0x04, 0x0000000a },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_graph_init_prop_0[] = {
-	{ 0x418408,   1, 0x04, 0x00000000 },
-	{ 0x4184a0,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_graph_init_setup_1[] = {
-	{ 0x4188c8,   2, 0x04, 0x00000000 },
-	{ 0x4188d0,   1, 0x04, 0x00010000 },
-	{ 0x4188d4,   1, 0x04, 0x00010201 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_graph_init_zcull_0[] = {
-	{ 0x418910,   1, 0x04, 0x00010001 },
-	{ 0x418914,   1, 0x04, 0x00000301 },
-	{ 0x418918,   1, 0x04, 0x00800000 },
-	{ 0x418930,   2, 0x04, 0x00000000 },
-	{ 0x418980,   1, 0x04, 0x77777770 },
-	{ 0x418984,   3, 0x04, 0x77777777 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_graph_init_gpc_unk_1[] = {
-	{ 0x418d00,   1, 0x04, 0x00000000 },
-	{ 0x418f00,   1, 0x04, 0x00000400 },
-	{ 0x418f08,   1, 0x04, 0x00000000 },
-	{ 0x418e08,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_graph_init_tpccs_0[] = {
-	{ 0x419dc4,   1, 0x04, 0x00000000 },
-	{ 0x419dc8,   1, 0x04, 0x00000501 },
-	{ 0x419dd0,   1, 0x04, 0x00000000 },
-	{ 0x419dd4,   1, 0x04, 0x00000100 },
-	{ 0x419dd8,   1, 0x04, 0x00000001 },
-	{ 0x419ddc,   1, 0x04, 0x00000002 },
-	{ 0x419de0,   1, 0x04, 0x00000001 },
-	{ 0x419d0c,   1, 0x04, 0x00000000 },
-	{ 0x419d10,   1, 0x04, 0x00000014 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_graph_init_tex_0[] = {
-	{ 0x419ab0,   1, 0x04, 0x00000000 },
-	{ 0x419ab8,   1, 0x04, 0x000000e7 },
-	{ 0x419abc,   1, 0x04, 0x00000000 },
-	{ 0x419acc,   1, 0x04, 0x000000ff },
-	{ 0x419ac0,   1, 0x04, 0x00000000 },
-	{ 0x419aa8,   2, 0x04, 0x00000000 },
-	{ 0x419ad0,   2, 0x04, 0x00000000 },
-	{ 0x419ae0,   2, 0x04, 0x00000000 },
-	{ 0x419af0,   4, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_graph_init_pe_0[] = {
-	{ 0x419900,   1, 0x04, 0x000000ff },
-	{ 0x41980c,   1, 0x04, 0x00000010 },
-	{ 0x419844,   1, 0x04, 0x00000000 },
-	{ 0x419838,   1, 0x04, 0x000000ff },
-	{ 0x419850,   1, 0x04, 0x00000004 },
-	{ 0x419854,   2, 0x04, 0x00000000 },
-	{ 0x419894,   3, 0x04, 0x00100401 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_graph_init_l1c_0[] = {
-	{ 0x419c98,   1, 0x04, 0x00000000 },
-	{ 0x419cc0,   2, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_graph_init_sm_0[] = {
-	{ 0x419e30,   1, 0x04, 0x000000ff },
-	{ 0x419e00,   1, 0x04, 0x00000000 },
-	{ 0x419ea0,   1, 0x04, 0x00000000 },
-	{ 0x419ee4,   1, 0x04, 0x00000000 },
-	{ 0x419ea4,   1, 0x04, 0x00000100 },
-	{ 0x419ea8,   1, 0x04, 0x01000000 },
-	{ 0x419ee8,   1, 0x04, 0x00000091 },
-	{ 0x419eb4,   1, 0x04, 0x00000000 },
-	{ 0x419ebc,   2, 0x04, 0x00000000 },
-	{ 0x419edc,   1, 0x04, 0x000c1810 },
-	{ 0x419ed8,   1, 0x04, 0x00000000 },
-	{ 0x419ee0,   1, 0x04, 0x00000000 },
-	{ 0x419f74,   1, 0x04, 0x00005155 },
-	{ 0x419f80,   4, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_graph_init_l1c_1[] = {
-	{ 0x419ccc,   2, 0x04, 0x00000000 },
-	{ 0x419c80,   1, 0x04, 0x3f006022 },
-	{ 0x419c88,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_graph_init_pes_0[] = {
-	{ 0x41be50,   1, 0x04, 0x000000ff },
-	{ 0x41be04,   1, 0x04, 0x00000000 },
-	{ 0x41be08,   1, 0x04, 0x00000004 },
-	{ 0x41be0c,   1, 0x04, 0x00000008 },
-	{ 0x41be10,   1, 0x04, 0x0e3b8bc7 },
-	{ 0x41be14,   2, 0x04, 0x00000000 },
-	{ 0x41be3c,   5, 0x04, 0x00100401 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_graph_init_wwdx_0[] = {
-	{ 0x41bfd4,   1, 0x04, 0x00800000 },
-	{ 0x41bfdc,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_graph_init_cbm_0[] = {
-	{ 0x41becc,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_graph_init_be_0[] = {
-	{ 0x408890,   1, 0x04, 0x000000ff },
-	{ 0x40880c,   1, 0x04, 0x00000000 },
-	{ 0x408850,   1, 0x04, 0x00000004 },
-	{ 0x408878,   1, 0x04, 0x00c81603 },
-	{ 0x40887c,   1, 0x04, 0x80543432 },
-	{ 0x408880,   1, 0x04, 0x0010581e },
-	{ 0x408884,   1, 0x04, 0x00001205 },
-	{ 0x408974,   1, 0x04, 0x000000ff },
-	{ 0x408910,   9, 0x04, 0x00000000 },
-	{ 0x408950,   1, 0x04, 0x00000000 },
-	{ 0x408954,   1, 0x04, 0x0000ffff },
-	{ 0x408958,   1, 0x04, 0x00000034 },
-	{ 0x40895c,   1, 0x04, 0x8531a003 },
-	{ 0x408960,   1, 0x04, 0x0561985a },
-	{ 0x408964,   1, 0x04, 0x04e15c4f },
-	{ 0x408968,   1, 0x04, 0x02808833 },
-	{ 0x40896c,   1, 0x04, 0x01f02438 },
-	{ 0x408970,   1, 0x04, 0x00012c00 },
-	{ 0x408984,   1, 0x04, 0x00000000 },
-	{ 0x408988,   1, 0x04, 0x08040201 },
-	{ 0x40898c,   1, 0x04, 0x80402010 },
-	{}
-};
-
-static const struct nvc0_graph_init
-gm107_graph_init_sm_1[] = {
-	{ 0x419e5c,   1, 0x04, 0x00000000 },
-	{ 0x419e58,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-gm107_graph_pack_mmio[] = {
-	{ gm107_graph_init_main_0 },
-	{ nvf0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvc0_graph_init_pd_0 },
-	{ gm107_graph_init_ds_0 },
-	{ gm107_graph_init_scc_0 },
-	{ gm107_graph_init_sked_0 },
-	{ nvf0_graph_init_cwd_0 },
-	{ gm107_graph_init_prop_0 },
-	{ nv108_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ gm107_graph_init_setup_1 },
-	{ gm107_graph_init_zcull_0 },
-	{ nvc0_graph_init_gpm_0 },
-	{ gm107_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ gm107_graph_init_tpccs_0 },
-	{ gm107_graph_init_tex_0 },
-	{ gm107_graph_init_pe_0 },
-	{ gm107_graph_init_l1c_0 },
-	{ nvc0_graph_init_mpc_0 },
-	{ gm107_graph_init_sm_0 },
-	{ gm107_graph_init_l1c_1 },
-	{ gm107_graph_init_pes_0 },
-	{ gm107_graph_init_wwdx_0 },
-	{ gm107_graph_init_cbm_0 },
-	{ gm107_graph_init_be_0 },
-	{ gm107_graph_init_sm_1 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-static void
-gm107_graph_init_bios(struct nvc0_graph_priv *priv)
-{
-	static const struct {
-		u32 ctrl;
-		u32 data;
-	} regs[] = {
-		{ 0x419ed8, 0x419ee0 },
-		{ 0x419ad0, 0x419ad4 },
-		{ 0x419ae0, 0x419ae4 },
-		{ 0x419af0, 0x419af4 },
-		{ 0x419af8, 0x419afc },
-	};
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	struct nvbios_P0260E infoE;
-	struct nvbios_P0260X infoX;
-	int E = -1, X;
-	u8 ver, hdr;
-
-	while (nvbios_P0260Ep(bios, ++E, &ver, &hdr, &infoE)) {
-		if (X = -1, E < ARRAY_SIZE(regs)) {
-			nv_wr32(priv, regs[E].ctrl, infoE.data);
-			while (nvbios_P0260Xp(bios, ++X, &ver, &hdr, &infoX))
-				nv_wr32(priv, regs[E].data, infoX.data);
-		}
-	}
-}
-
-int
-gm107_graph_init(struct nouveau_object *object)
-{
-	struct nvc0_graph_oclass *oclass = (void *)object->oclass;
-	struct nvc0_graph_priv *priv = (void *)object;
-	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
-	u32 data[TPC_MAX / 8] = {};
-	u8  tpcnr[GPC_MAX];
-	int gpc, tpc, ppc, rop;
-	int ret, i;
-
-	ret = nouveau_graph_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
-	nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000);
-	nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000);
-	nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
-	nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
-
-	nvc0_graph_mmio(priv, oclass->mmio);
-
-	gm107_graph_init_bios(priv);
-
-	nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
-
-	memset(data, 0x00, sizeof(data));
-	memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
-	for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
-		do {
-			gpc = (gpc + 1) % priv->gpc_nr;
-		} while (!tpcnr[gpc]);
-		tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
-
-		data[i / 8] |= tpc << ((i % 8) * 4);
-	}
-
-	nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
-	nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
-	nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
-	nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
-
-	for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
-			priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
-			priv->tpc_total);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
-	}
-
-	nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
-	nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
-
-	nv_wr32(priv, 0x400500, 0x00010001);
-
-	nv_wr32(priv, 0x400100, 0xffffffff);
-	nv_wr32(priv, 0x40013c, 0xffffffff);
-	nv_wr32(priv, 0x400124, 0x00000002);
-	nv_wr32(priv, 0x409c24, 0x000e0000);
-
-	nv_wr32(priv, 0x404000, 0xc0000000);
-	nv_wr32(priv, 0x404600, 0xc0000000);
-	nv_wr32(priv, 0x408030, 0xc0000000);
-	nv_wr32(priv, 0x404490, 0xc0000000);
-	nv_wr32(priv, 0x406018, 0xc0000000);
-	nv_wr32(priv, 0x407020, 0x40000000);
-	nv_wr32(priv, 0x405840, 0xc0000000);
-	nv_wr32(priv, 0x405844, 0x00ffffff);
-	nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
-
-	for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-		for (ppc = 0; ppc < 2 /* priv->ppc_nr[gpc] */; ppc++)
-			nv_wr32(priv, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
-		for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005);
-		}
-		nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
-	}
-
-	for (rop = 0; rop < priv->rop_nr; rop++) {
-		nv_wr32(priv, ROP_UNIT(rop, 0x144), 0x40000000);
-		nv_wr32(priv, ROP_UNIT(rop, 0x070), 0x40000000);
-		nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
-		nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
-	}
-
-	nv_wr32(priv, 0x400108, 0xffffffff);
-	nv_wr32(priv, 0x400138, 0xffffffff);
-	nv_wr32(priv, 0x400118, 0xffffffff);
-	nv_wr32(priv, 0x400130, 0xffffffff);
-	nv_wr32(priv, 0x40011c, 0xffffffff);
-	nv_wr32(priv, 0x400134, 0xffffffff);
-
-	nv_wr32(priv, 0x400054, 0x2c350f63);
-
-	nvc0_graph_zbc_init(priv);
-
-	return nvc0_graph_init_ctxctl(priv);
-}
-
-#include "fuc/hubgm107.fuc5.h"
-
-static struct nvc0_graph_ucode
-gm107_graph_fecs_ucode = {
-	.code.data = gm107_grhub_code,
-	.code.size = sizeof(gm107_grhub_code),
-	.data.data = gm107_grhub_data,
-	.data.size = sizeof(gm107_grhub_data),
-};
-
-#include "fuc/gpcgm107.fuc5.h"
-
-static struct nvc0_graph_ucode
-gm107_graph_gpccs_ucode = {
-	.code.data = gm107_grgpc_code,
-	.code.size = sizeof(gm107_grgpc_code),
-	.data.data = gm107_grgpc_data,
-	.data.size = sizeof(gm107_grgpc_data),
-};
-
-struct nouveau_oclass *
-gm107_graph_oclass = &(struct nvc0_graph_oclass) {
-	.base.handle = NV_ENGINE(GR, 0x07),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = gm107_graph_init,
-		.fini = _nouveau_graph_fini,
-	},
-	.cclass = &gm107_grctx_oclass,
-	.sclass =  gm107_graph_sclass,
-	.mmio = gm107_graph_pack_mmio,
-	.fecs.ucode = 0 ? &gm107_graph_fecs_ucode : NULL,
-	.gpccs.ucode = &gm107_graph_gpccs_ucode,
-	.ppc_nr = 2,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c
deleted file mode 100644
index f70e2f67a4dd..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c
+++ /dev/null
@@ -1,1388 +0,0 @@
-/*
- * Copyright 2007 Stephane Marchesin
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include <core/client.h>
-#include <core/os.h>
-#include <core/handle.h>
-#include <core/namedb.h>
-
-#include <subdev/fb.h>
-#include <subdev/instmem.h>
-#include <subdev/timer.h>
-
-#include <engine/fifo.h>
-#include <engine/graph.h>
-
-#include "regs.h"
-
-static u32
-nv04_graph_ctx_regs[] = {
-	0x0040053c,
-	0x00400544,
-	0x00400540,
-	0x00400548,
-	NV04_PGRAPH_CTX_SWITCH1,
-	NV04_PGRAPH_CTX_SWITCH2,
-	NV04_PGRAPH_CTX_SWITCH3,
-	NV04_PGRAPH_CTX_SWITCH4,
-	NV04_PGRAPH_CTX_CACHE1,
-	NV04_PGRAPH_CTX_CACHE2,
-	NV04_PGRAPH_CTX_CACHE3,
-	NV04_PGRAPH_CTX_CACHE4,
-	0x00400184,
-	0x004001a4,
-	0x004001c4,
-	0x004001e4,
-	0x00400188,
-	0x004001a8,
-	0x004001c8,
-	0x004001e8,
-	0x0040018c,
-	0x004001ac,
-	0x004001cc,
-	0x004001ec,
-	0x00400190,
-	0x004001b0,
-	0x004001d0,
-	0x004001f0,
-	0x00400194,
-	0x004001b4,
-	0x004001d4,
-	0x004001f4,
-	0x00400198,
-	0x004001b8,
-	0x004001d8,
-	0x004001f8,
-	0x0040019c,
-	0x004001bc,
-	0x004001dc,
-	0x004001fc,
-	0x00400174,
-	NV04_PGRAPH_DMA_START_0,
-	NV04_PGRAPH_DMA_START_1,
-	NV04_PGRAPH_DMA_LENGTH,
-	NV04_PGRAPH_DMA_MISC,
-	NV04_PGRAPH_DMA_PITCH,
-	NV04_PGRAPH_BOFFSET0,
-	NV04_PGRAPH_BBASE0,
-	NV04_PGRAPH_BLIMIT0,
-	NV04_PGRAPH_BOFFSET1,
-	NV04_PGRAPH_BBASE1,
-	NV04_PGRAPH_BLIMIT1,
-	NV04_PGRAPH_BOFFSET2,
-	NV04_PGRAPH_BBASE2,
-	NV04_PGRAPH_BLIMIT2,
-	NV04_PGRAPH_BOFFSET3,
-	NV04_PGRAPH_BBASE3,
-	NV04_PGRAPH_BLIMIT3,
-	NV04_PGRAPH_BOFFSET4,
-	NV04_PGRAPH_BBASE4,
-	NV04_PGRAPH_BLIMIT4,
-	NV04_PGRAPH_BOFFSET5,
-	NV04_PGRAPH_BBASE5,
-	NV04_PGRAPH_BLIMIT5,
-	NV04_PGRAPH_BPITCH0,
-	NV04_PGRAPH_BPITCH1,
-	NV04_PGRAPH_BPITCH2,
-	NV04_PGRAPH_BPITCH3,
-	NV04_PGRAPH_BPITCH4,
-	NV04_PGRAPH_SURFACE,
-	NV04_PGRAPH_STATE,
-	NV04_PGRAPH_BSWIZZLE2,
-	NV04_PGRAPH_BSWIZZLE5,
-	NV04_PGRAPH_BPIXEL,
-	NV04_PGRAPH_NOTIFY,
-	NV04_PGRAPH_PATT_COLOR0,
-	NV04_PGRAPH_PATT_COLOR1,
-	NV04_PGRAPH_PATT_COLORRAM+0x00,
-	NV04_PGRAPH_PATT_COLORRAM+0x04,
-	NV04_PGRAPH_PATT_COLORRAM+0x08,
-	NV04_PGRAPH_PATT_COLORRAM+0x0c,
-	NV04_PGRAPH_PATT_COLORRAM+0x10,
-	NV04_PGRAPH_PATT_COLORRAM+0x14,
-	NV04_PGRAPH_PATT_COLORRAM+0x18,
-	NV04_PGRAPH_PATT_COLORRAM+0x1c,
-	NV04_PGRAPH_PATT_COLORRAM+0x20,
-	NV04_PGRAPH_PATT_COLORRAM+0x24,
-	NV04_PGRAPH_PATT_COLORRAM+0x28,
-	NV04_PGRAPH_PATT_COLORRAM+0x2c,
-	NV04_PGRAPH_PATT_COLORRAM+0x30,
-	NV04_PGRAPH_PATT_COLORRAM+0x34,
-	NV04_PGRAPH_PATT_COLORRAM+0x38,
-	NV04_PGRAPH_PATT_COLORRAM+0x3c,
-	NV04_PGRAPH_PATT_COLORRAM+0x40,
-	NV04_PGRAPH_PATT_COLORRAM+0x44,
-	NV04_PGRAPH_PATT_COLORRAM+0x48,
-	NV04_PGRAPH_PATT_COLORRAM+0x4c,
-	NV04_PGRAPH_PATT_COLORRAM+0x50,
-	NV04_PGRAPH_PATT_COLORRAM+0x54,
-	NV04_PGRAPH_PATT_COLORRAM+0x58,
-	NV04_PGRAPH_PATT_COLORRAM+0x5c,
-	NV04_PGRAPH_PATT_COLORRAM+0x60,
-	NV04_PGRAPH_PATT_COLORRAM+0x64,
-	NV04_PGRAPH_PATT_COLORRAM+0x68,
-	NV04_PGRAPH_PATT_COLORRAM+0x6c,
-	NV04_PGRAPH_PATT_COLORRAM+0x70,
-	NV04_PGRAPH_PATT_COLORRAM+0x74,
-	NV04_PGRAPH_PATT_COLORRAM+0x78,
-	NV04_PGRAPH_PATT_COLORRAM+0x7c,
-	NV04_PGRAPH_PATT_COLORRAM+0x80,
-	NV04_PGRAPH_PATT_COLORRAM+0x84,
-	NV04_PGRAPH_PATT_COLORRAM+0x88,
-	NV04_PGRAPH_PATT_COLORRAM+0x8c,
-	NV04_PGRAPH_PATT_COLORRAM+0x90,
-	NV04_PGRAPH_PATT_COLORRAM+0x94,
-	NV04_PGRAPH_PATT_COLORRAM+0x98,
-	NV04_PGRAPH_PATT_COLORRAM+0x9c,
-	NV04_PGRAPH_PATT_COLORRAM+0xa0,
-	NV04_PGRAPH_PATT_COLORRAM+0xa4,
-	NV04_PGRAPH_PATT_COLORRAM+0xa8,
-	NV04_PGRAPH_PATT_COLORRAM+0xac,
-	NV04_PGRAPH_PATT_COLORRAM+0xb0,
-	NV04_PGRAPH_PATT_COLORRAM+0xb4,
-	NV04_PGRAPH_PATT_COLORRAM+0xb8,
-	NV04_PGRAPH_PATT_COLORRAM+0xbc,
-	NV04_PGRAPH_PATT_COLORRAM+0xc0,
-	NV04_PGRAPH_PATT_COLORRAM+0xc4,
-	NV04_PGRAPH_PATT_COLORRAM+0xc8,
-	NV04_PGRAPH_PATT_COLORRAM+0xcc,
-	NV04_PGRAPH_PATT_COLORRAM+0xd0,
-	NV04_PGRAPH_PATT_COLORRAM+0xd4,
-	NV04_PGRAPH_PATT_COLORRAM+0xd8,
-	NV04_PGRAPH_PATT_COLORRAM+0xdc,
-	NV04_PGRAPH_PATT_COLORRAM+0xe0,
-	NV04_PGRAPH_PATT_COLORRAM+0xe4,
-	NV04_PGRAPH_PATT_COLORRAM+0xe8,
-	NV04_PGRAPH_PATT_COLORRAM+0xec,
-	NV04_PGRAPH_PATT_COLORRAM+0xf0,
-	NV04_PGRAPH_PATT_COLORRAM+0xf4,
-	NV04_PGRAPH_PATT_COLORRAM+0xf8,
-	NV04_PGRAPH_PATT_COLORRAM+0xfc,
-	NV04_PGRAPH_PATTERN,
-	0x0040080c,
-	NV04_PGRAPH_PATTERN_SHAPE,
-	0x00400600,
-	NV04_PGRAPH_ROP3,
-	NV04_PGRAPH_CHROMA,
-	NV04_PGRAPH_BETA_AND,
-	NV04_PGRAPH_BETA_PREMULT,
-	NV04_PGRAPH_CONTROL0,
-	NV04_PGRAPH_CONTROL1,
-	NV04_PGRAPH_CONTROL2,
-	NV04_PGRAPH_BLEND,
-	NV04_PGRAPH_STORED_FMT,
-	NV04_PGRAPH_SOURCE_COLOR,
-	0x00400560,
-	0x00400568,
-	0x00400564,
-	0x0040056c,
-	0x00400400,
-	0x00400480,
-	0x00400404,
-	0x00400484,
-	0x00400408,
-	0x00400488,
-	0x0040040c,
-	0x0040048c,
-	0x00400410,
-	0x00400490,
-	0x00400414,
-	0x00400494,
-	0x00400418,
-	0x00400498,
-	0x0040041c,
-	0x0040049c,
-	0x00400420,
-	0x004004a0,
-	0x00400424,
-	0x004004a4,
-	0x00400428,
-	0x004004a8,
-	0x0040042c,
-	0x004004ac,
-	0x00400430,
-	0x004004b0,
-	0x00400434,
-	0x004004b4,
-	0x00400438,
-	0x004004b8,
-	0x0040043c,
-	0x004004bc,
-	0x00400440,
-	0x004004c0,
-	0x00400444,
-	0x004004c4,
-	0x00400448,
-	0x004004c8,
-	0x0040044c,
-	0x004004cc,
-	0x00400450,
-	0x004004d0,
-	0x00400454,
-	0x004004d4,
-	0x00400458,
-	0x004004d8,
-	0x0040045c,
-	0x004004dc,
-	0x00400460,
-	0x004004e0,
-	0x00400464,
-	0x004004e4,
-	0x00400468,
-	0x004004e8,
-	0x0040046c,
-	0x004004ec,
-	0x00400470,
-	0x004004f0,
-	0x00400474,
-	0x004004f4,
-	0x00400478,
-	0x004004f8,
-	0x0040047c,
-	0x004004fc,
-	0x00400534,
-	0x00400538,
-	0x00400514,
-	0x00400518,
-	0x0040051c,
-	0x00400520,
-	0x00400524,
-	0x00400528,
-	0x0040052c,
-	0x00400530,
-	0x00400d00,
-	0x00400d40,
-	0x00400d80,
-	0x00400d04,
-	0x00400d44,
-	0x00400d84,
-	0x00400d08,
-	0x00400d48,
-	0x00400d88,
-	0x00400d0c,
-	0x00400d4c,
-	0x00400d8c,
-	0x00400d10,
-	0x00400d50,
-	0x00400d90,
-	0x00400d14,
-	0x00400d54,
-	0x00400d94,
-	0x00400d18,
-	0x00400d58,
-	0x00400d98,
-	0x00400d1c,
-	0x00400d5c,
-	0x00400d9c,
-	0x00400d20,
-	0x00400d60,
-	0x00400da0,
-	0x00400d24,
-	0x00400d64,
-	0x00400da4,
-	0x00400d28,
-	0x00400d68,
-	0x00400da8,
-	0x00400d2c,
-	0x00400d6c,
-	0x00400dac,
-	0x00400d30,
-	0x00400d70,
-	0x00400db0,
-	0x00400d34,
-	0x00400d74,
-	0x00400db4,
-	0x00400d38,
-	0x00400d78,
-	0x00400db8,
-	0x00400d3c,
-	0x00400d7c,
-	0x00400dbc,
-	0x00400590,
-	0x00400594,
-	0x00400598,
-	0x0040059c,
-	0x004005a8,
-	0x004005ac,
-	0x004005b0,
-	0x004005b4,
-	0x004005c0,
-	0x004005c4,
-	0x004005c8,
-	0x004005cc,
-	0x004005d0,
-	0x004005d4,
-	0x004005d8,
-	0x004005dc,
-	0x004005e0,
-	NV04_PGRAPH_PASSTHRU_0,
-	NV04_PGRAPH_PASSTHRU_1,
-	NV04_PGRAPH_PASSTHRU_2,
-	NV04_PGRAPH_DVD_COLORFMT,
-	NV04_PGRAPH_SCALED_FORMAT,
-	NV04_PGRAPH_MISC24_0,
-	NV04_PGRAPH_MISC24_1,
-	NV04_PGRAPH_MISC24_2,
-	0x00400500,
-	0x00400504,
-	NV04_PGRAPH_VALID1,
-	NV04_PGRAPH_VALID2,
-	NV04_PGRAPH_DEBUG_3
-};
-
-struct nv04_graph_priv {
-	struct nouveau_graph base;
-	struct nv04_graph_chan *chan[16];
-	spinlock_t lock;
-};
-
-struct nv04_graph_chan {
-	struct nouveau_object base;
-	int chid;
-	u32 nv04[ARRAY_SIZE(nv04_graph_ctx_regs)];
-};
-
-
-static inline struct nv04_graph_priv *
-nv04_graph_priv(struct nv04_graph_chan *chan)
-{
-	return (void *)nv_object(chan)->engine;
-}
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-/*
- * Software methods, why they are needed, and how they all work:
- *
- * NV04 and NV05 keep most of the state in PGRAPH context itself, but some
- * 2d engine settings are kept inside the grobjs themselves. The grobjs are
- * 3 words long on both. grobj format on NV04 is:
- *
- * word 0:
- *  - bits 0-7: class
- *  - bit 12: color key active
- *  - bit 13: clip rect active
- *  - bit 14: if set, destination surface is swizzled and taken from buffer 5
- *            [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken
- *            from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or
- *            NV03_CONTEXT_SURFACE_DST].
- *  - bits 15-17: 2d operation [aka patch config]
- *  - bit 24: patch valid [enables rendering using this object]
- *  - bit 25: surf3d valid [for tex_tri and multitex_tri only]
- * word 1:
- *  - bits 0-1: mono format
- *  - bits 8-13: color format
- *  - bits 16-31: DMA_NOTIFY instance
- * word 2:
- *  - bits 0-15: DMA_A instance
- *  - bits 16-31: DMA_B instance
- *
- * On NV05 it's:
- *
- * word 0:
- *  - bits 0-7: class
- *  - bit 12: color key active
- *  - bit 13: clip rect active
- *  - bit 14: if set, destination surface is swizzled and taken from buffer 5
- *            [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken
- *            from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or
- *            NV03_CONTEXT_SURFACE_DST].
- *  - bits 15-17: 2d operation [aka patch config]
- *  - bits 20-22: dither mode
- *  - bit 24: patch valid [enables rendering using this object]
- *  - bit 25: surface_dst/surface_color/surf2d/surf3d valid
- *  - bit 26: surface_src/surface_zeta valid
- *  - bit 27: pattern valid
- *  - bit 28: rop valid
- *  - bit 29: beta1 valid
- *  - bit 30: beta4 valid
- * word 1:
- *  - bits 0-1: mono format
- *  - bits 8-13: color format
- *  - bits 16-31: DMA_NOTIFY instance
- * word 2:
- *  - bits 0-15: DMA_A instance
- *  - bits 16-31: DMA_B instance
- *
- * NV05 will set/unset the relevant valid bits when you poke the relevant
- * object-binding methods with object of the proper type, or with the NULL
- * type. It'll only allow rendering using the grobj if all needed objects
- * are bound. The needed set of objects depends on selected operation: for
- * example rop object is needed by ROP_AND, but not by SRCCOPY_AND.
- *
- * NV04 doesn't have these methods implemented at all, and doesn't have the
- * relevant bits in grobj. Instead, it'll allow rendering whenever bit 24
- * is set. So we have to emulate them in software, internally keeping the
- * same bits as NV05 does. Since grobjs are aligned to 16 bytes on nv04,
- * but the last word isn't actually used for anything, we abuse it for this
- * purpose.
- *
- * Actually, NV05 can optionally check bit 24 too, but we disable this since
- * there's no use for it.
- *
- * For unknown reasons, NV04 implements surf3d binding in hardware as an
- * exception. Also for unknown reasons, NV04 doesn't implement the clipping
- * methods on the surf3d object, so we have to emulate them too.
- */
-
-static void
-nv04_graph_set_ctx1(struct nouveau_object *object, u32 mask, u32 value)
-{
-	struct nv04_graph_priv *priv = (void *)object->engine;
-	int subc = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
-	u32 tmp;
-
-	tmp  = nv_ro32(object, 0x00);
-	tmp &= ~mask;
-	tmp |= value;
-	nv_wo32(object, 0x00, tmp);
-
-	nv_wr32(priv, NV04_PGRAPH_CTX_SWITCH1, tmp);
-	nv_wr32(priv, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp);
-}
-
-static void
-nv04_graph_set_ctx_val(struct nouveau_object *object, u32 mask, u32 value)
-{
-	int class, op, valid = 1;
-	u32 tmp, ctx1;
-
-	ctx1 = nv_ro32(object, 0x00);
-	class = ctx1 & 0xff;
-	op = (ctx1 >> 15) & 7;
-
-	tmp = nv_ro32(object, 0x0c);
-	tmp &= ~mask;
-	tmp |= value;
-	nv_wo32(object, 0x0c, tmp);
-
-	/* check for valid surf2d/surf_dst/surf_color */
-	if (!(tmp & 0x02000000))
-		valid = 0;
-	/* check for valid surf_src/surf_zeta */
-	if ((class == 0x1f || class == 0x48) && !(tmp & 0x04000000))
-		valid = 0;
-
-	switch (op) {
-	/* SRCCOPY_AND, SRCCOPY: no extra objects required */
-	case 0:
-	case 3:
-		break;
-	/* ROP_AND: requires pattern and rop */
-	case 1:
-		if (!(tmp & 0x18000000))
-			valid = 0;
-		break;
-	/* BLEND_AND: requires beta1 */
-	case 2:
-		if (!(tmp & 0x20000000))
-			valid = 0;
-		break;
-	/* SRCCOPY_PREMULT, BLEND_PREMULT: beta4 required */
-	case 4:
-	case 5:
-		if (!(tmp & 0x40000000))
-			valid = 0;
-		break;
-	}
-
-	nv04_graph_set_ctx1(object, 0x01000000, valid << 24);
-}
-
-static int
-nv04_graph_mthd_set_operation(struct nouveau_object *object, u32 mthd,
-			      void *args, u32 size)
-{
-	u32 class = nv_ro32(object, 0) & 0xff;
-	u32 data = *(u32 *)args;
-	if (data > 5)
-		return 1;
-	/* Old versions of the objects only accept first three operations. */
-	if (data > 2 && class < 0x40)
-		return 1;
-	nv04_graph_set_ctx1(object, 0x00038000, data << 15);
-	/* changing operation changes set of objects needed for validation */
-	nv04_graph_set_ctx_val(object, 0, 0);
-	return 0;
-}
-
-static int
-nv04_graph_mthd_surf3d_clip_h(struct nouveau_object *object, u32 mthd,
-			      void *args, u32 size)
-{
-	struct nv04_graph_priv *priv = (void *)object->engine;
-	u32 data = *(u32 *)args;
-	u32 min = data & 0xffff, max;
-	u32 w = data >> 16;
-	if (min & 0x8000)
-		/* too large */
-		return 1;
-	if (w & 0x8000)
-		/* yes, it accepts negative for some reason. */
-		w |= 0xffff0000;
-	max = min + w;
-	max &= 0x3ffff;
-	nv_wr32(priv, 0x40053c, min);
-	nv_wr32(priv, 0x400544, max);
-	return 0;
-}
-
-static int
-nv04_graph_mthd_surf3d_clip_v(struct nouveau_object *object, u32 mthd,
-			      void *args, u32 size)
-{
-	struct nv04_graph_priv *priv = (void *)object->engine;
-	u32 data = *(u32 *)args;
-	u32 min = data & 0xffff, max;
-	u32 w = data >> 16;
-	if (min & 0x8000)
-		/* too large */
-		return 1;
-	if (w & 0x8000)
-		/* yes, it accepts negative for some reason. */
-		w |= 0xffff0000;
-	max = min + w;
-	max &= 0x3ffff;
-	nv_wr32(priv, 0x400540, min);
-	nv_wr32(priv, 0x400548, max);
-	return 0;
-}
-
-static u16
-nv04_graph_mthd_bind_class(struct nouveau_object *object, u32 *args, u32 size)
-{
-	struct nouveau_instmem *imem = nouveau_instmem(object);
-	u32 inst = *(u32 *)args << 4;
-	return nv_ro32(imem, inst);
-}
-
-static int
-nv04_graph_mthd_bind_surf2d(struct nouveau_object *object, u32 mthd,
-			    void *args, u32 size)
-{
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
-	case 0x30:
-		nv04_graph_set_ctx1(object, 0x00004000, 0);
-		nv04_graph_set_ctx_val(object, 0x02000000, 0);
-		return 0;
-	case 0x42:
-		nv04_graph_set_ctx1(object, 0x00004000, 0);
-		nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000);
-		return 0;
-	}
-	return 1;
-}
-
-static int
-nv04_graph_mthd_bind_surf2d_swzsurf(struct nouveau_object *object, u32 mthd,
-				    void *args, u32 size)
-{
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
-	case 0x30:
-		nv04_graph_set_ctx1(object, 0x00004000, 0);
-		nv04_graph_set_ctx_val(object, 0x02000000, 0);
-		return 0;
-	case 0x42:
-		nv04_graph_set_ctx1(object, 0x00004000, 0);
-		nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000);
-		return 0;
-	case 0x52:
-		nv04_graph_set_ctx1(object, 0x00004000, 0x00004000);
-		nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000);
-		return 0;
-	}
-	return 1;
-}
-
-static int
-nv01_graph_mthd_bind_patt(struct nouveau_object *object, u32 mthd,
-			  void *args, u32 size)
-{
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
-	case 0x30:
-		nv04_graph_set_ctx_val(object, 0x08000000, 0);
-		return 0;
-	case 0x18:
-		nv04_graph_set_ctx_val(object, 0x08000000, 0x08000000);
-		return 0;
-	}
-	return 1;
-}
-
-static int
-nv04_graph_mthd_bind_patt(struct nouveau_object *object, u32 mthd,
-			  void *args, u32 size)
-{
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
-	case 0x30:
-		nv04_graph_set_ctx_val(object, 0x08000000, 0);
-		return 0;
-	case 0x44:
-		nv04_graph_set_ctx_val(object, 0x08000000, 0x08000000);
-		return 0;
-	}
-	return 1;
-}
-
-static int
-nv04_graph_mthd_bind_rop(struct nouveau_object *object, u32 mthd,
-			 void *args, u32 size)
-{
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
-	case 0x30:
-		nv04_graph_set_ctx_val(object, 0x10000000, 0);
-		return 0;
-	case 0x43:
-		nv04_graph_set_ctx_val(object, 0x10000000, 0x10000000);
-		return 0;
-	}
-	return 1;
-}
-
-static int
-nv04_graph_mthd_bind_beta1(struct nouveau_object *object, u32 mthd,
-			   void *args, u32 size)
-{
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
-	case 0x30:
-		nv04_graph_set_ctx_val(object, 0x20000000, 0);
-		return 0;
-	case 0x12:
-		nv04_graph_set_ctx_val(object, 0x20000000, 0x20000000);
-		return 0;
-	}
-	return 1;
-}
-
-static int
-nv04_graph_mthd_bind_beta4(struct nouveau_object *object, u32 mthd,
-			   void *args, u32 size)
-{
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
-	case 0x30:
-		nv04_graph_set_ctx_val(object, 0x40000000, 0);
-		return 0;
-	case 0x72:
-		nv04_graph_set_ctx_val(object, 0x40000000, 0x40000000);
-		return 0;
-	}
-	return 1;
-}
-
-static int
-nv04_graph_mthd_bind_surf_dst(struct nouveau_object *object, u32 mthd,
-			      void *args, u32 size)
-{
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
-	case 0x30:
-		nv04_graph_set_ctx_val(object, 0x02000000, 0);
-		return 0;
-	case 0x58:
-		nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000);
-		return 0;
-	}
-	return 1;
-}
-
-static int
-nv04_graph_mthd_bind_surf_src(struct nouveau_object *object, u32 mthd,
-			      void *args, u32 size)
-{
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
-	case 0x30:
-		nv04_graph_set_ctx_val(object, 0x04000000, 0);
-		return 0;
-	case 0x59:
-		nv04_graph_set_ctx_val(object, 0x04000000, 0x04000000);
-		return 0;
-	}
-	return 1;
-}
-
-static int
-nv04_graph_mthd_bind_surf_color(struct nouveau_object *object, u32 mthd,
-				void *args, u32 size)
-{
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
-	case 0x30:
-		nv04_graph_set_ctx_val(object, 0x02000000, 0);
-		return 0;
-	case 0x5a:
-		nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000);
-		return 0;
-	}
-	return 1;
-}
-
-static int
-nv04_graph_mthd_bind_surf_zeta(struct nouveau_object *object, u32 mthd,
-			       void *args, u32 size)
-{
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
-	case 0x30:
-		nv04_graph_set_ctx_val(object, 0x04000000, 0);
-		return 0;
-	case 0x5b:
-		nv04_graph_set_ctx_val(object, 0x04000000, 0x04000000);
-		return 0;
-	}
-	return 1;
-}
-
-static int
-nv01_graph_mthd_bind_clip(struct nouveau_object *object, u32 mthd,
-			  void *args, u32 size)
-{
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
-	case 0x30:
-		nv04_graph_set_ctx1(object, 0x2000, 0);
-		return 0;
-	case 0x19:
-		nv04_graph_set_ctx1(object, 0x2000, 0x2000);
-		return 0;
-	}
-	return 1;
-}
-
-static int
-nv01_graph_mthd_bind_chroma(struct nouveau_object *object, u32 mthd,
-			    void *args, u32 size)
-{
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
-	case 0x30:
-		nv04_graph_set_ctx1(object, 0x1000, 0);
-		return 0;
-	/* Yes, for some reason even the old versions of objects
-	 * accept 0x57 and not 0x17. Consistency be damned.
-	 */
-	case 0x57:
-		nv04_graph_set_ctx1(object, 0x1000, 0x1000);
-		return 0;
-	}
-	return 1;
-}
-
-static struct nouveau_omthds
-nv03_graph_gdi_omthds[] = {
-	{ 0x0184, 0x0184, nv01_graph_mthd_bind_patt },
-	{ 0x0188, 0x0188, nv04_graph_mthd_bind_rop },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_beta1 },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_surf_dst },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
-	{}
-};
-
-static struct nouveau_omthds
-nv04_graph_gdi_omthds[] = {
-	{ 0x0188, 0x0188, nv04_graph_mthd_bind_patt },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 },
-	{ 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
-	{}
-};
-
-static struct nouveau_omthds
-nv01_graph_blit_omthds[] = {
-	{ 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
-	{ 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
-	{ 0x018c, 0x018c, nv01_graph_mthd_bind_patt },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_rop },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 },
-	{ 0x0198, 0x0198, nv04_graph_mthd_bind_surf_dst },
-	{ 0x019c, 0x019c, nv04_graph_mthd_bind_surf_src },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
-	{}
-};
-
-static struct nouveau_omthds
-nv04_graph_blit_omthds[] = {
-	{ 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
-	{ 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_patt },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_rop },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 },
-	{ 0x0198, 0x0198, nv04_graph_mthd_bind_beta4 },
-	{ 0x019c, 0x019c, nv04_graph_mthd_bind_surf2d },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
-	{}
-};
-
-static struct nouveau_omthds
-nv04_graph_iifc_omthds[] = {
-	{ 0x0188, 0x0188, nv01_graph_mthd_bind_chroma },
-	{ 0x018c, 0x018c, nv01_graph_mthd_bind_clip },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_patt },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_rop },
-	{ 0x0198, 0x0198, nv04_graph_mthd_bind_beta1 },
-	{ 0x019c, 0x019c, nv04_graph_mthd_bind_beta4 },
-	{ 0x01a0, 0x01a0, nv04_graph_mthd_bind_surf2d_swzsurf },
-	{ 0x03e4, 0x03e4, nv04_graph_mthd_set_operation },
-	{}
-};
-
-static struct nouveau_omthds
-nv01_graph_ifc_omthds[] = {
-	{ 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
-	{ 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
-	{ 0x018c, 0x018c, nv01_graph_mthd_bind_patt },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_rop },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 },
-	{ 0x0198, 0x0198, nv04_graph_mthd_bind_surf_dst },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
-	{}
-};
-
-static struct nouveau_omthds
-nv04_graph_ifc_omthds[] = {
-	{ 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
-	{ 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_patt },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_rop },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 },
-	{ 0x0198, 0x0198, nv04_graph_mthd_bind_beta4 },
-	{ 0x019c, 0x019c, nv04_graph_mthd_bind_surf2d },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
-	{}
-};
-
-static struct nouveau_omthds
-nv03_graph_sifc_omthds[] = {
-	{ 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
-	{ 0x0188, 0x0188, nv01_graph_mthd_bind_patt },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
-	{}
-};
-
-static struct nouveau_omthds
-nv04_graph_sifc_omthds[] = {
-	{ 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
-	{ 0x0188, 0x0188, nv04_graph_mthd_bind_patt },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 },
-	{ 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
-	{}
-};
-
-static struct nouveau_omthds
-nv03_graph_sifm_omthds[] = {
-	{ 0x0188, 0x0188, nv01_graph_mthd_bind_patt },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst },
-	{ 0x0304, 0x0304, nv04_graph_mthd_set_operation },
-	{}
-};
-
-static struct nouveau_omthds
-nv04_graph_sifm_omthds[] = {
-	{ 0x0188, 0x0188, nv04_graph_mthd_bind_patt },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 },
-	{ 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d },
-	{ 0x0304, 0x0304, nv04_graph_mthd_set_operation },
-	{}
-};
-
-static struct nouveau_omthds
-nv04_graph_surf3d_omthds[] = {
-	{ 0x02f8, 0x02f8, nv04_graph_mthd_surf3d_clip_h },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_surf3d_clip_v },
-	{}
-};
-
-static struct nouveau_omthds
-nv03_graph_ttri_omthds[] = {
-	{ 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_surf_color },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_surf_zeta },
-	{}
-};
-
-static struct nouveau_omthds
-nv01_graph_prim_omthds[] = {
-	{ 0x0184, 0x0184, nv01_graph_mthd_bind_clip },
-	{ 0x0188, 0x0188, nv01_graph_mthd_bind_patt },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
-	{}
-};
-
-static struct nouveau_omthds
-nv04_graph_prim_omthds[] = {
-	{ 0x0184, 0x0184, nv01_graph_mthd_bind_clip },
-	{ 0x0188, 0x0188, nv04_graph_mthd_bind_patt },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 },
-	{ 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
-	{}
-};
-
-static int
-nv04_graph_object_ctor(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, void *data, u32 size,
-		       struct nouveau_object **pobject)
-{
-	struct nouveau_gpuobj *obj;
-	int ret;
-
-	ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
-				    16, 16, 0, &obj);
-	*pobject = nv_object(obj);
-	if (ret)
-		return ret;
-
-	nv_wo32(obj, 0x00, nv_mclass(obj));
-#ifdef __BIG_ENDIAN
-	nv_mo32(obj, 0x00, 0x00080000, 0x00080000);
-#endif
-	nv_wo32(obj, 0x04, 0x00000000);
-	nv_wo32(obj, 0x08, 0x00000000);
-	nv_wo32(obj, 0x0c, 0x00000000);
-	return 0;
-}
-
-struct nouveau_ofuncs
-nv04_graph_ofuncs = {
-	.ctor = nv04_graph_object_ctor,
-	.dtor = _nouveau_gpuobj_dtor,
-	.init = _nouveau_gpuobj_init,
-	.fini = _nouveau_gpuobj_fini,
-	.rd32 = _nouveau_gpuobj_rd32,
-	.wr32 = _nouveau_gpuobj_wr32,
-};
-
-static struct nouveau_oclass
-nv04_graph_sclass[] = {
-	{ 0x0012, &nv04_graph_ofuncs }, /* beta1 */
-	{ 0x0017, &nv04_graph_ofuncs }, /* chroma */
-	{ 0x0018, &nv04_graph_ofuncs }, /* pattern (nv01) */
-	{ 0x0019, &nv04_graph_ofuncs }, /* clip */
-	{ 0x001c, &nv04_graph_ofuncs, nv01_graph_prim_omthds }, /* line */
-	{ 0x001d, &nv04_graph_ofuncs, nv01_graph_prim_omthds }, /* tri */
-	{ 0x001e, &nv04_graph_ofuncs, nv01_graph_prim_omthds }, /* rect */
-	{ 0x001f, &nv04_graph_ofuncs, nv01_graph_blit_omthds },
-	{ 0x0021, &nv04_graph_ofuncs, nv01_graph_ifc_omthds },
-	{ 0x0030, &nv04_graph_ofuncs }, /* null */
-	{ 0x0036, &nv04_graph_ofuncs, nv03_graph_sifc_omthds },
-	{ 0x0037, &nv04_graph_ofuncs, nv03_graph_sifm_omthds },
-	{ 0x0038, &nv04_graph_ofuncs }, /* dvd subpicture */
-	{ 0x0039, &nv04_graph_ofuncs }, /* m2mf */
-	{ 0x0042, &nv04_graph_ofuncs }, /* surf2d */
-	{ 0x0043, &nv04_graph_ofuncs }, /* rop */
-	{ 0x0044, &nv04_graph_ofuncs }, /* pattern */
-	{ 0x0048, &nv04_graph_ofuncs, nv03_graph_ttri_omthds },
-	{ 0x004a, &nv04_graph_ofuncs, nv04_graph_gdi_omthds },
-	{ 0x004b, &nv04_graph_ofuncs, nv03_graph_gdi_omthds },
-	{ 0x0052, &nv04_graph_ofuncs }, /* swzsurf */
-	{ 0x0053, &nv04_graph_ofuncs, nv04_graph_surf3d_omthds },
-	{ 0x0054, &nv04_graph_ofuncs }, /* ttri */
-	{ 0x0055, &nv04_graph_ofuncs }, /* mtri */
-	{ 0x0057, &nv04_graph_ofuncs }, /* chroma */
-	{ 0x0058, &nv04_graph_ofuncs }, /* surf_dst */
-	{ 0x0059, &nv04_graph_ofuncs }, /* surf_src */
-	{ 0x005a, &nv04_graph_ofuncs }, /* surf_color */
-	{ 0x005b, &nv04_graph_ofuncs }, /* surf_zeta */
-	{ 0x005c, &nv04_graph_ofuncs, nv04_graph_prim_omthds }, /* line */
-	{ 0x005d, &nv04_graph_ofuncs, nv04_graph_prim_omthds }, /* tri */
-	{ 0x005e, &nv04_graph_ofuncs, nv04_graph_prim_omthds }, /* rect */
-	{ 0x005f, &nv04_graph_ofuncs, nv04_graph_blit_omthds },
-	{ 0x0060, &nv04_graph_ofuncs, nv04_graph_iifc_omthds },
-	{ 0x0061, &nv04_graph_ofuncs, nv04_graph_ifc_omthds },
-	{ 0x0064, &nv04_graph_ofuncs }, /* iifc (nv05) */
-	{ 0x0065, &nv04_graph_ofuncs }, /* ifc (nv05) */
-	{ 0x0066, &nv04_graph_ofuncs }, /* sifc (nv05) */
-	{ 0x0072, &nv04_graph_ofuncs }, /* beta4 */
-	{ 0x0076, &nv04_graph_ofuncs, nv04_graph_sifc_omthds },
-	{ 0x0077, &nv04_graph_ofuncs, nv04_graph_sifm_omthds },
-	{},
-};
-
-/*******************************************************************************
- * PGRAPH context
- ******************************************************************************/
-
-static struct nv04_graph_chan *
-nv04_graph_channel(struct nv04_graph_priv *priv)
-{
-	struct nv04_graph_chan *chan = NULL;
-	if (nv_rd32(priv, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) {
-		int chid = nv_rd32(priv, NV04_PGRAPH_CTX_USER) >> 24;
-		if (chid < ARRAY_SIZE(priv->chan))
-			chan = priv->chan[chid];
-	}
-	return chan;
-}
-
-static int
-nv04_graph_load_context(struct nv04_graph_chan *chan, int chid)
-{
-	struct nv04_graph_priv *priv = nv04_graph_priv(chan);
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
-		nv_wr32(priv, nv04_graph_ctx_regs[i], chan->nv04[i]);
-
-	nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10010100);
-	nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24);
-	nv_mask(priv, NV04_PGRAPH_FFINTFC_ST2, 0xfff00000, 0x00000000);
-	return 0;
-}
-
-static int
-nv04_graph_unload_context(struct nv04_graph_chan *chan)
-{
-	struct nv04_graph_priv *priv = nv04_graph_priv(chan);
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
-		chan->nv04[i] = nv_rd32(priv, nv04_graph_ctx_regs[i]);
-
-	nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10000000);
-	nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000);
-	return 0;
-}
-
-static void
-nv04_graph_context_switch(struct nv04_graph_priv *priv)
-{
-	struct nv04_graph_chan *prev = NULL;
-	struct nv04_graph_chan *next = NULL;
-	unsigned long flags;
-	int chid;
-
-	spin_lock_irqsave(&priv->lock, flags);
-	nv04_graph_idle(priv);
-
-	/* If previous context is valid, we need to save it */
-	prev = nv04_graph_channel(priv);
-	if (prev)
-		nv04_graph_unload_context(prev);
-
-	/* load context for next channel */
-	chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f;
-	next = priv->chan[chid];
-	if (next)
-		nv04_graph_load_context(next, chid);
-
-	spin_unlock_irqrestore(&priv->lock, flags);
-}
-
-static u32 *ctx_reg(struct nv04_graph_chan *chan, u32 reg)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) {
-		if (nv04_graph_ctx_regs[i] == reg)
-			return &chan->nv04[i];
-	}
-
-	return NULL;
-}
-
-static int
-nv04_graph_context_ctor(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass, void *data, u32 size,
-			struct nouveau_object **pobject)
-{
-	struct nouveau_fifo_chan *fifo = (void *)parent;
-	struct nv04_graph_priv *priv = (void *)engine;
-	struct nv04_graph_chan *chan;
-	unsigned long flags;
-	int ret;
-
-	ret = nouveau_object_create(parent, engine, oclass, 0, &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	spin_lock_irqsave(&priv->lock, flags);
-	if (priv->chan[fifo->chid]) {
-		*pobject = nv_object(priv->chan[fifo->chid]);
-		atomic_inc(&(*pobject)->refcount);
-		spin_unlock_irqrestore(&priv->lock, flags);
-		nouveau_object_destroy(&chan->base);
-		return 1;
-	}
-
-	*ctx_reg(chan, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31;
-
-	priv->chan[fifo->chid] = chan;
-	chan->chid = fifo->chid;
-	spin_unlock_irqrestore(&priv->lock, flags);
-	return 0;
-}
-
-static void
-nv04_graph_context_dtor(struct nouveau_object *object)
-{
-	struct nv04_graph_priv *priv = (void *)object->engine;
-	struct nv04_graph_chan *chan = (void *)object;
-	unsigned long flags;
-
-	spin_lock_irqsave(&priv->lock, flags);
-	priv->chan[chan->chid] = NULL;
-	spin_unlock_irqrestore(&priv->lock, flags);
-
-	nouveau_object_destroy(&chan->base);
-}
-
-static int
-nv04_graph_context_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv04_graph_priv *priv = (void *)object->engine;
-	struct nv04_graph_chan *chan = (void *)object;
-	unsigned long flags;
-
-	spin_lock_irqsave(&priv->lock, flags);
-	nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
-	if (nv04_graph_channel(priv) == chan)
-		nv04_graph_unload_context(chan);
-	nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
-	spin_unlock_irqrestore(&priv->lock, flags);
-
-	return nouveau_object_fini(&chan->base, suspend);
-}
-
-static struct nouveau_oclass
-nv04_graph_cclass = {
-	.handle = NV_ENGCTX(GR, 0x04),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_graph_context_ctor,
-		.dtor = nv04_graph_context_dtor,
-		.init = nouveau_object_init,
-		.fini = nv04_graph_context_fini,
-	},
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-bool
-nv04_graph_idle(void *obj)
-{
-	struct nouveau_graph *graph = nouveau_graph(obj);
-	u32 mask = 0xffffffff;
-
-	if (nv_device(obj)->card_type == NV_40)
-		mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
-
-	if (!nv_wait(graph, NV04_PGRAPH_STATUS, mask, 0)) {
-		nv_error(graph, "idle timed out with status 0x%08x\n",
-			 nv_rd32(graph, NV04_PGRAPH_STATUS));
-		return false;
-	}
-
-	return true;
-}
-
-static const struct nouveau_bitfield
-nv04_graph_intr_name[] = {
-	{ NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
-	{}
-};
-
-static const struct nouveau_bitfield
-nv04_graph_nstatus[] = {
-	{ NV04_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
-	{ NV04_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
-	{ NV04_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
-	{ NV04_PGRAPH_NSTATUS_PROTECTION_FAULT,   "PROTECTION_FAULT" },
-	{}
-};
-
-const struct nouveau_bitfield
-nv04_graph_nsource[] = {
-	{ NV03_PGRAPH_NSOURCE_NOTIFICATION,       "NOTIFICATION" },
-	{ NV03_PGRAPH_NSOURCE_DATA_ERROR,         "DATA_ERROR" },
-	{ NV03_PGRAPH_NSOURCE_PROTECTION_ERROR,   "PROTECTION_ERROR" },
-	{ NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION,    "RANGE_EXCEPTION" },
-	{ NV03_PGRAPH_NSOURCE_LIMIT_COLOR,        "LIMIT_COLOR" },
-	{ NV03_PGRAPH_NSOURCE_LIMIT_ZETA,         "LIMIT_ZETA" },
-	{ NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD,       "ILLEGAL_MTHD" },
-	{ NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION,   "DMA_R_PROTECTION" },
-	{ NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION,   "DMA_W_PROTECTION" },
-	{ NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION,   "FORMAT_EXCEPTION" },
-	{ NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION,    "PATCH_EXCEPTION" },
-	{ NV03_PGRAPH_NSOURCE_STATE_INVALID,      "STATE_INVALID" },
-	{ NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY,      "DOUBLE_NOTIFY" },
-	{ NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE,      "NOTIFY_IN_USE" },
-	{ NV03_PGRAPH_NSOURCE_METHOD_CNT,         "METHOD_CNT" },
-	{ NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION,   "BFR_NOTIFICATION" },
-	{ NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
-	{ NV03_PGRAPH_NSOURCE_DMA_WIDTH_A,        "DMA_WIDTH_A" },
-	{ NV03_PGRAPH_NSOURCE_DMA_WIDTH_B,        "DMA_WIDTH_B" },
-	{}
-};
-
-static void
-nv04_graph_intr(struct nouveau_subdev *subdev)
-{
-	struct nv04_graph_priv *priv = (void *)subdev;
-	struct nv04_graph_chan *chan = NULL;
-	struct nouveau_namedb *namedb = NULL;
-	struct nouveau_handle *handle = NULL;
-	u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
-	u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
-	u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
-	u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
-	u32 chid = (addr & 0x0f000000) >> 24;
-	u32 subc = (addr & 0x0000e000) >> 13;
-	u32 mthd = (addr & 0x00001ffc);
-	u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
-	u32 class = nv_rd32(priv, 0x400180 + subc * 4) & 0xff;
-	u32 inst = (nv_rd32(priv, 0x40016c) & 0xffff) << 4;
-	u32 show = stat;
-	unsigned long flags;
-
-	spin_lock_irqsave(&priv->lock, flags);
-	chan = priv->chan[chid];
-	if (chan)
-		namedb = (void *)nv_pclass(nv_object(chan), NV_NAMEDB_CLASS);
-	spin_unlock_irqrestore(&priv->lock, flags);
-
-	if (stat & NV_PGRAPH_INTR_NOTIFY) {
-		if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) {
-			handle = nouveau_namedb_get_vinst(namedb, inst);
-			if (handle && !nv_call(handle->object, mthd, data))
-				show &= ~NV_PGRAPH_INTR_NOTIFY;
-		}
-	}
-
-	if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
-		nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
-		stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
-		show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
-		nv04_graph_context_switch(priv);
-	}
-
-	nv_wr32(priv, NV03_PGRAPH_INTR, stat);
-	nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
-
-	if (show) {
-		nv_error(priv, "%s", "");
-		nouveau_bitfield_print(nv04_graph_intr_name, show);
-		pr_cont(" nsource:");
-		nouveau_bitfield_print(nv04_graph_nsource, nsource);
-		pr_cont(" nstatus:");
-		nouveau_bitfield_print(nv04_graph_nstatus, nstatus);
-		pr_cont("\n");
-		nv_error(priv,
-			 "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
-			 chid, nouveau_client_name(chan), subc, class, mthd,
-			 data);
-	}
-
-	nouveau_namedb_put(handle);
-}
-
-static int
-nv04_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nv04_graph_priv *priv;
-	int ret;
-
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv04_graph_intr;
-	nv_engine(priv)->cclass = &nv04_graph_cclass;
-	nv_engine(priv)->sclass = nv04_graph_sclass;
-	spin_lock_init(&priv->lock);
-	return 0;
-}
-
-static int
-nv04_graph_init(struct nouveau_object *object)
-{
-	struct nouveau_engine *engine = nv_engine(object);
-	struct nv04_graph_priv *priv = (void *)engine;
-	int ret;
-
-	ret = nouveau_graph_init(&priv->base);
-	if (ret)
-		return ret;
-
-	/* Enable PGRAPH interrupts */
-	nv_wr32(priv, NV03_PGRAPH_INTR, 0xFFFFFFFF);
-	nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
-
-	nv_wr32(priv, NV04_PGRAPH_VALID1, 0);
-	nv_wr32(priv, NV04_PGRAPH_VALID2, 0);
-	/*nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x000001FF);
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x1231c000);
-	/*1231C000 blob, 001 haiku*/
-	/*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x72111100);
-	/*0x72111100 blob , 01 haiku*/
-	/*nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x11d5f071);
-	/*haiku same*/
-
-	/*nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31);
-	/*haiku and blob 10d4*/
-
-	nv_wr32(priv, NV04_PGRAPH_STATE        , 0xFFFFFFFF);
-	nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL  , 0x10000100);
-	nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000);
-
-	/* These don't belong here, they're part of a per-channel context */
-	nv_wr32(priv, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
-	nv_wr32(priv, NV04_PGRAPH_BETA_AND     , 0xFFFFFFFF);
-	return 0;
-}
-
-struct nouveau_oclass
-nv04_graph_oclass = {
-	.handle = NV_ENGINE(GR, 0x04),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_graph_ctor,
-		.dtor = _nouveau_graph_dtor,
-		.init = nv04_graph_init,
-		.fini = _nouveau_graph_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c
deleted file mode 100644
index 2b12b09683c8..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c
+++ /dev/null
@@ -1,1319 +0,0 @@
-/*
- * Copyright 2007 Matthieu CASTET <castet.matthieu@free.fr>
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include <core/client.h>
-#include <core/os.h>
-#include <core/handle.h>
-
-#include <subdev/fb.h>
-
-#include <engine/fifo.h>
-#include <engine/graph.h>
-
-#include "regs.h"
-
-struct pipe_state {
-	u32 pipe_0x0000[0x040/4];
-	u32 pipe_0x0040[0x010/4];
-	u32 pipe_0x0200[0x0c0/4];
-	u32 pipe_0x4400[0x080/4];
-	u32 pipe_0x6400[0x3b0/4];
-	u32 pipe_0x6800[0x2f0/4];
-	u32 pipe_0x6c00[0x030/4];
-	u32 pipe_0x7000[0x130/4];
-	u32 pipe_0x7400[0x0c0/4];
-	u32 pipe_0x7800[0x0c0/4];
-};
-
-static int nv10_graph_ctx_regs[] = {
-	NV10_PGRAPH_CTX_SWITCH(0),
-	NV10_PGRAPH_CTX_SWITCH(1),
-	NV10_PGRAPH_CTX_SWITCH(2),
-	NV10_PGRAPH_CTX_SWITCH(3),
-	NV10_PGRAPH_CTX_SWITCH(4),
-	NV10_PGRAPH_CTX_CACHE(0, 0),
-	NV10_PGRAPH_CTX_CACHE(0, 1),
-	NV10_PGRAPH_CTX_CACHE(0, 2),
-	NV10_PGRAPH_CTX_CACHE(0, 3),
-	NV10_PGRAPH_CTX_CACHE(0, 4),
-	NV10_PGRAPH_CTX_CACHE(1, 0),
-	NV10_PGRAPH_CTX_CACHE(1, 1),
-	NV10_PGRAPH_CTX_CACHE(1, 2),
-	NV10_PGRAPH_CTX_CACHE(1, 3),
-	NV10_PGRAPH_CTX_CACHE(1, 4),
-	NV10_PGRAPH_CTX_CACHE(2, 0),
-	NV10_PGRAPH_CTX_CACHE(2, 1),
-	NV10_PGRAPH_CTX_CACHE(2, 2),
-	NV10_PGRAPH_CTX_CACHE(2, 3),
-	NV10_PGRAPH_CTX_CACHE(2, 4),
-	NV10_PGRAPH_CTX_CACHE(3, 0),
-	NV10_PGRAPH_CTX_CACHE(3, 1),
-	NV10_PGRAPH_CTX_CACHE(3, 2),
-	NV10_PGRAPH_CTX_CACHE(3, 3),
-	NV10_PGRAPH_CTX_CACHE(3, 4),
-	NV10_PGRAPH_CTX_CACHE(4, 0),
-	NV10_PGRAPH_CTX_CACHE(4, 1),
-	NV10_PGRAPH_CTX_CACHE(4, 2),
-	NV10_PGRAPH_CTX_CACHE(4, 3),
-	NV10_PGRAPH_CTX_CACHE(4, 4),
-	NV10_PGRAPH_CTX_CACHE(5, 0),
-	NV10_PGRAPH_CTX_CACHE(5, 1),
-	NV10_PGRAPH_CTX_CACHE(5, 2),
-	NV10_PGRAPH_CTX_CACHE(5, 3),
-	NV10_PGRAPH_CTX_CACHE(5, 4),
-	NV10_PGRAPH_CTX_CACHE(6, 0),
-	NV10_PGRAPH_CTX_CACHE(6, 1),
-	NV10_PGRAPH_CTX_CACHE(6, 2),
-	NV10_PGRAPH_CTX_CACHE(6, 3),
-	NV10_PGRAPH_CTX_CACHE(6, 4),
-	NV10_PGRAPH_CTX_CACHE(7, 0),
-	NV10_PGRAPH_CTX_CACHE(7, 1),
-	NV10_PGRAPH_CTX_CACHE(7, 2),
-	NV10_PGRAPH_CTX_CACHE(7, 3),
-	NV10_PGRAPH_CTX_CACHE(7, 4),
-	NV10_PGRAPH_CTX_USER,
-	NV04_PGRAPH_DMA_START_0,
-	NV04_PGRAPH_DMA_START_1,
-	NV04_PGRAPH_DMA_LENGTH,
-	NV04_PGRAPH_DMA_MISC,
-	NV10_PGRAPH_DMA_PITCH,
-	NV04_PGRAPH_BOFFSET0,
-	NV04_PGRAPH_BBASE0,
-	NV04_PGRAPH_BLIMIT0,
-	NV04_PGRAPH_BOFFSET1,
-	NV04_PGRAPH_BBASE1,
-	NV04_PGRAPH_BLIMIT1,
-	NV04_PGRAPH_BOFFSET2,
-	NV04_PGRAPH_BBASE2,
-	NV04_PGRAPH_BLIMIT2,
-	NV04_PGRAPH_BOFFSET3,
-	NV04_PGRAPH_BBASE3,
-	NV04_PGRAPH_BLIMIT3,
-	NV04_PGRAPH_BOFFSET4,
-	NV04_PGRAPH_BBASE4,
-	NV04_PGRAPH_BLIMIT4,
-	NV04_PGRAPH_BOFFSET5,
-	NV04_PGRAPH_BBASE5,
-	NV04_PGRAPH_BLIMIT5,
-	NV04_PGRAPH_BPITCH0,
-	NV04_PGRAPH_BPITCH1,
-	NV04_PGRAPH_BPITCH2,
-	NV04_PGRAPH_BPITCH3,
-	NV04_PGRAPH_BPITCH4,
-	NV10_PGRAPH_SURFACE,
-	NV10_PGRAPH_STATE,
-	NV04_PGRAPH_BSWIZZLE2,
-	NV04_PGRAPH_BSWIZZLE5,
-	NV04_PGRAPH_BPIXEL,
-	NV10_PGRAPH_NOTIFY,
-	NV04_PGRAPH_PATT_COLOR0,
-	NV04_PGRAPH_PATT_COLOR1,
-	NV04_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */
-	0x00400904,
-	0x00400908,
-	0x0040090c,
-	0x00400910,
-	0x00400914,
-	0x00400918,
-	0x0040091c,
-	0x00400920,
-	0x00400924,
-	0x00400928,
-	0x0040092c,
-	0x00400930,
-	0x00400934,
-	0x00400938,
-	0x0040093c,
-	0x00400940,
-	0x00400944,
-	0x00400948,
-	0x0040094c,
-	0x00400950,
-	0x00400954,
-	0x00400958,
-	0x0040095c,
-	0x00400960,
-	0x00400964,
-	0x00400968,
-	0x0040096c,
-	0x00400970,
-	0x00400974,
-	0x00400978,
-	0x0040097c,
-	0x00400980,
-	0x00400984,
-	0x00400988,
-	0x0040098c,
-	0x00400990,
-	0x00400994,
-	0x00400998,
-	0x0040099c,
-	0x004009a0,
-	0x004009a4,
-	0x004009a8,
-	0x004009ac,
-	0x004009b0,
-	0x004009b4,
-	0x004009b8,
-	0x004009bc,
-	0x004009c0,
-	0x004009c4,
-	0x004009c8,
-	0x004009cc,
-	0x004009d0,
-	0x004009d4,
-	0x004009d8,
-	0x004009dc,
-	0x004009e0,
-	0x004009e4,
-	0x004009e8,
-	0x004009ec,
-	0x004009f0,
-	0x004009f4,
-	0x004009f8,
-	0x004009fc,
-	NV04_PGRAPH_PATTERN,	/* 2 values from 0x400808 to 0x40080c */
-	0x0040080c,
-	NV04_PGRAPH_PATTERN_SHAPE,
-	NV03_PGRAPH_MONO_COLOR0,
-	NV04_PGRAPH_ROP3,
-	NV04_PGRAPH_CHROMA,
-	NV04_PGRAPH_BETA_AND,
-	NV04_PGRAPH_BETA_PREMULT,
-	0x00400e70,
-	0x00400e74,
-	0x00400e78,
-	0x00400e7c,
-	0x00400e80,
-	0x00400e84,
-	0x00400e88,
-	0x00400e8c,
-	0x00400ea0,
-	0x00400ea4,
-	0x00400ea8,
-	0x00400e90,
-	0x00400e94,
-	0x00400e98,
-	0x00400e9c,
-	NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00-0x400f1c */
-	NV10_PGRAPH_WINDOWCLIP_VERTICAL,   /* 8 values from 0x400f20-0x400f3c */
-	0x00400f04,
-	0x00400f24,
-	0x00400f08,
-	0x00400f28,
-	0x00400f0c,
-	0x00400f2c,
-	0x00400f10,
-	0x00400f30,
-	0x00400f14,
-	0x00400f34,
-	0x00400f18,
-	0x00400f38,
-	0x00400f1c,
-	0x00400f3c,
-	NV10_PGRAPH_XFMODE0,
-	NV10_PGRAPH_XFMODE1,
-	NV10_PGRAPH_GLOBALSTATE0,
-	NV10_PGRAPH_GLOBALSTATE1,
-	NV04_PGRAPH_STORED_FMT,
-	NV04_PGRAPH_SOURCE_COLOR,
-	NV03_PGRAPH_ABS_X_RAM,	/* 32 values from 0x400400 to 0x40047c */
-	NV03_PGRAPH_ABS_Y_RAM,	/* 32 values from 0x400480 to 0x4004fc */
-	0x00400404,
-	0x00400484,
-	0x00400408,
-	0x00400488,
-	0x0040040c,
-	0x0040048c,
-	0x00400410,
-	0x00400490,
-	0x00400414,
-	0x00400494,
-	0x00400418,
-	0x00400498,
-	0x0040041c,
-	0x0040049c,
-	0x00400420,
-	0x004004a0,
-	0x00400424,
-	0x004004a4,
-	0x00400428,
-	0x004004a8,
-	0x0040042c,
-	0x004004ac,
-	0x00400430,
-	0x004004b0,
-	0x00400434,
-	0x004004b4,
-	0x00400438,
-	0x004004b8,
-	0x0040043c,
-	0x004004bc,
-	0x00400440,
-	0x004004c0,
-	0x00400444,
-	0x004004c4,
-	0x00400448,
-	0x004004c8,
-	0x0040044c,
-	0x004004cc,
-	0x00400450,
-	0x004004d0,
-	0x00400454,
-	0x004004d4,
-	0x00400458,
-	0x004004d8,
-	0x0040045c,
-	0x004004dc,
-	0x00400460,
-	0x004004e0,
-	0x00400464,
-	0x004004e4,
-	0x00400468,
-	0x004004e8,
-	0x0040046c,
-	0x004004ec,
-	0x00400470,
-	0x004004f0,
-	0x00400474,
-	0x004004f4,
-	0x00400478,
-	0x004004f8,
-	0x0040047c,
-	0x004004fc,
-	NV03_PGRAPH_ABS_UCLIP_XMIN,
-	NV03_PGRAPH_ABS_UCLIP_XMAX,
-	NV03_PGRAPH_ABS_UCLIP_YMIN,
-	NV03_PGRAPH_ABS_UCLIP_YMAX,
-	0x00400550,
-	0x00400558,
-	0x00400554,
-	0x0040055c,
-	NV03_PGRAPH_ABS_UCLIPA_XMIN,
-	NV03_PGRAPH_ABS_UCLIPA_XMAX,
-	NV03_PGRAPH_ABS_UCLIPA_YMIN,
-	NV03_PGRAPH_ABS_UCLIPA_YMAX,
-	NV03_PGRAPH_ABS_ICLIP_XMAX,
-	NV03_PGRAPH_ABS_ICLIP_YMAX,
-	NV03_PGRAPH_XY_LOGIC_MISC0,
-	NV03_PGRAPH_XY_LOGIC_MISC1,
-	NV03_PGRAPH_XY_LOGIC_MISC2,
-	NV03_PGRAPH_XY_LOGIC_MISC3,
-	NV03_PGRAPH_CLIPX_0,
-	NV03_PGRAPH_CLIPX_1,
-	NV03_PGRAPH_CLIPY_0,
-	NV03_PGRAPH_CLIPY_1,
-	NV10_PGRAPH_COMBINER0_IN_ALPHA,
-	NV10_PGRAPH_COMBINER1_IN_ALPHA,
-	NV10_PGRAPH_COMBINER0_IN_RGB,
-	NV10_PGRAPH_COMBINER1_IN_RGB,
-	NV10_PGRAPH_COMBINER_COLOR0,
-	NV10_PGRAPH_COMBINER_COLOR1,
-	NV10_PGRAPH_COMBINER0_OUT_ALPHA,
-	NV10_PGRAPH_COMBINER1_OUT_ALPHA,
-	NV10_PGRAPH_COMBINER0_OUT_RGB,
-	NV10_PGRAPH_COMBINER1_OUT_RGB,
-	NV10_PGRAPH_COMBINER_FINAL0,
-	NV10_PGRAPH_COMBINER_FINAL1,
-	0x00400e00,
-	0x00400e04,
-	0x00400e08,
-	0x00400e0c,
-	0x00400e10,
-	0x00400e14,
-	0x00400e18,
-	0x00400e1c,
-	0x00400e20,
-	0x00400e24,
-	0x00400e28,
-	0x00400e2c,
-	0x00400e30,
-	0x00400e34,
-	0x00400e38,
-	0x00400e3c,
-	NV04_PGRAPH_PASSTHRU_0,
-	NV04_PGRAPH_PASSTHRU_1,
-	NV04_PGRAPH_PASSTHRU_2,
-	NV10_PGRAPH_DIMX_TEXTURE,
-	NV10_PGRAPH_WDIMX_TEXTURE,
-	NV10_PGRAPH_DVD_COLORFMT,
-	NV10_PGRAPH_SCALED_FORMAT,
-	NV04_PGRAPH_MISC24_0,
-	NV04_PGRAPH_MISC24_1,
-	NV04_PGRAPH_MISC24_2,
-	NV03_PGRAPH_X_MISC,
-	NV03_PGRAPH_Y_MISC,
-	NV04_PGRAPH_VALID1,
-	NV04_PGRAPH_VALID2,
-};
-
-static int nv17_graph_ctx_regs[] = {
-	NV10_PGRAPH_DEBUG_4,
-	0x004006b0,
-	0x00400eac,
-	0x00400eb0,
-	0x00400eb4,
-	0x00400eb8,
-	0x00400ebc,
-	0x00400ec0,
-	0x00400ec4,
-	0x00400ec8,
-	0x00400ecc,
-	0x00400ed0,
-	0x00400ed4,
-	0x00400ed8,
-	0x00400edc,
-	0x00400ee0,
-	0x00400a00,
-	0x00400a04,
-};
-
-struct nv10_graph_priv {
-	struct nouveau_graph base;
-	struct nv10_graph_chan *chan[32];
-	spinlock_t lock;
-};
-
-struct nv10_graph_chan {
-	struct nouveau_object base;
-	int chid;
-	int nv10[ARRAY_SIZE(nv10_graph_ctx_regs)];
-	int nv17[ARRAY_SIZE(nv17_graph_ctx_regs)];
-	struct pipe_state pipe_state;
-	u32 lma_window[4];
-};
-
-
-static inline struct nv10_graph_priv *
-nv10_graph_priv(struct nv10_graph_chan *chan)
-{
-	return (void *)nv_object(chan)->engine;
-}
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-#define PIPE_SAVE(priv, state, addr)					\
-	do {								\
-		int __i;						\
-		nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, addr);		\
-		for (__i = 0; __i < ARRAY_SIZE(state); __i++)		\
-			state[__i] = nv_rd32(priv, NV10_PGRAPH_PIPE_DATA); \
-	} while (0)
-
-#define PIPE_RESTORE(priv, state, addr)					\
-	do {								\
-		int __i;						\
-		nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, addr);		\
-		for (__i = 0; __i < ARRAY_SIZE(state); __i++)		\
-			nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, state[__i]); \
-	} while (0)
-
-static struct nouveau_oclass
-nv10_graph_sclass[] = {
-	{ 0x0012, &nv04_graph_ofuncs }, /* beta1 */
-	{ 0x0019, &nv04_graph_ofuncs }, /* clip */
-	{ 0x0030, &nv04_graph_ofuncs }, /* null */
-	{ 0x0039, &nv04_graph_ofuncs }, /* m2mf */
-	{ 0x0043, &nv04_graph_ofuncs }, /* rop */
-	{ 0x0044, &nv04_graph_ofuncs }, /* pattern */
-	{ 0x004a, &nv04_graph_ofuncs }, /* gdi */
-	{ 0x0052, &nv04_graph_ofuncs }, /* swzsurf */
-	{ 0x005f, &nv04_graph_ofuncs }, /* blit */
-	{ 0x0062, &nv04_graph_ofuncs }, /* surf2d */
-	{ 0x0072, &nv04_graph_ofuncs }, /* beta4 */
-	{ 0x0089, &nv04_graph_ofuncs }, /* sifm */
-	{ 0x008a, &nv04_graph_ofuncs }, /* ifc */
-	{ 0x009f, &nv04_graph_ofuncs }, /* blit */
-	{ 0x0093, &nv04_graph_ofuncs }, /* surf3d */
-	{ 0x0094, &nv04_graph_ofuncs }, /* ttri */
-	{ 0x0095, &nv04_graph_ofuncs }, /* mtri */
-	{ 0x0056, &nv04_graph_ofuncs }, /* celcius */
-	{},
-};
-
-static struct nouveau_oclass
-nv15_graph_sclass[] = {
-	{ 0x0012, &nv04_graph_ofuncs }, /* beta1 */
-	{ 0x0019, &nv04_graph_ofuncs }, /* clip */
-	{ 0x0030, &nv04_graph_ofuncs }, /* null */
-	{ 0x0039, &nv04_graph_ofuncs }, /* m2mf */
-	{ 0x0043, &nv04_graph_ofuncs }, /* rop */
-	{ 0x0044, &nv04_graph_ofuncs }, /* pattern */
-	{ 0x004a, &nv04_graph_ofuncs }, /* gdi */
-	{ 0x0052, &nv04_graph_ofuncs }, /* swzsurf */
-	{ 0x005f, &nv04_graph_ofuncs }, /* blit */
-	{ 0x0062, &nv04_graph_ofuncs }, /* surf2d */
-	{ 0x0072, &nv04_graph_ofuncs }, /* beta4 */
-	{ 0x0089, &nv04_graph_ofuncs }, /* sifm */
-	{ 0x008a, &nv04_graph_ofuncs }, /* ifc */
-	{ 0x009f, &nv04_graph_ofuncs }, /* blit */
-	{ 0x0093, &nv04_graph_ofuncs }, /* surf3d */
-	{ 0x0094, &nv04_graph_ofuncs }, /* ttri */
-	{ 0x0095, &nv04_graph_ofuncs }, /* mtri */
-	{ 0x0096, &nv04_graph_ofuncs }, /* celcius */
-	{},
-};
-
-static int
-nv17_graph_mthd_lma_window(struct nouveau_object *object, u32 mthd,
-			   void *args, u32 size)
-{
-	struct nv10_graph_chan *chan = (void *)object->parent;
-	struct nv10_graph_priv *priv = nv10_graph_priv(chan);
-	struct pipe_state *pipe = &chan->pipe_state;
-	u32 pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3];
-	u32 xfmode0, xfmode1;
-	u32 data = *(u32 *)args;
-	int i;
-
-	chan->lma_window[(mthd - 0x1638) / 4] = data;
-
-	if (mthd != 0x1644)
-		return 0;
-
-	nv04_graph_idle(priv);
-
-	PIPE_SAVE(priv, pipe_0x0040, 0x0040);
-	PIPE_SAVE(priv, pipe->pipe_0x0200, 0x0200);
-
-	PIPE_RESTORE(priv, chan->lma_window, 0x6790);
-
-	nv04_graph_idle(priv);
-
-	xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0);
-	xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1);
-
-	PIPE_SAVE(priv, pipe->pipe_0x4400, 0x4400);
-	PIPE_SAVE(priv, pipe_0x64c0, 0x64c0);
-	PIPE_SAVE(priv, pipe_0x6ab0, 0x6ab0);
-	PIPE_SAVE(priv, pipe_0x6a80, 0x6a80);
-
-	nv04_graph_idle(priv);
-
-	nv_wr32(priv, NV10_PGRAPH_XFMODE0, 0x10000000);
-	nv_wr32(priv, NV10_PGRAPH_XFMODE1, 0x00000000);
-	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
-	for (i = 0; i < 4; i++)
-		nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
-	for (i = 0; i < 4; i++)
-		nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000);
-
-	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
-	for (i = 0; i < 3; i++)
-		nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
-
-	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
-	for (i = 0; i < 3; i++)
-		nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000);
-
-	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
-	nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000008);
-
-	PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200);
-
-	nv04_graph_idle(priv);
-
-	PIPE_RESTORE(priv, pipe_0x0040, 0x0040);
-
-	nv_wr32(priv, NV10_PGRAPH_XFMODE0, xfmode0);
-	nv_wr32(priv, NV10_PGRAPH_XFMODE1, xfmode1);
-
-	PIPE_RESTORE(priv, pipe_0x64c0, 0x64c0);
-	PIPE_RESTORE(priv, pipe_0x6ab0, 0x6ab0);
-	PIPE_RESTORE(priv, pipe_0x6a80, 0x6a80);
-	PIPE_RESTORE(priv, pipe->pipe_0x4400, 0x4400);
-
-	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0);
-	nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000);
-
-	nv04_graph_idle(priv);
-
-	return 0;
-}
-
-static int
-nv17_graph_mthd_lma_enable(struct nouveau_object *object, u32 mthd,
-			   void *args, u32 size)
-{
-	struct nv10_graph_chan *chan = (void *)object->parent;
-	struct nv10_graph_priv *priv = nv10_graph_priv(chan);
-
-	nv04_graph_idle(priv);
-
-	nv_mask(priv, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100);
-	nv_mask(priv, 0x4006b0, 0x08000000, 0x08000000);
-	return 0;
-}
-
-static struct nouveau_omthds
-nv17_celcius_omthds[] = {
-	{ 0x1638, 0x1638, nv17_graph_mthd_lma_window },
-	{ 0x163c, 0x163c, nv17_graph_mthd_lma_window },
-	{ 0x1640, 0x1640, nv17_graph_mthd_lma_window },
-	{ 0x1644, 0x1644, nv17_graph_mthd_lma_window },
-	{ 0x1658, 0x1658, nv17_graph_mthd_lma_enable },
-	{}
-};
-
-static struct nouveau_oclass
-nv17_graph_sclass[] = {
-	{ 0x0012, &nv04_graph_ofuncs }, /* beta1 */
-	{ 0x0019, &nv04_graph_ofuncs }, /* clip */
-	{ 0x0030, &nv04_graph_ofuncs }, /* null */
-	{ 0x0039, &nv04_graph_ofuncs }, /* m2mf */
-	{ 0x0043, &nv04_graph_ofuncs }, /* rop */
-	{ 0x0044, &nv04_graph_ofuncs }, /* pattern */
-	{ 0x004a, &nv04_graph_ofuncs }, /* gdi */
-	{ 0x0052, &nv04_graph_ofuncs }, /* swzsurf */
-	{ 0x005f, &nv04_graph_ofuncs }, /* blit */
-	{ 0x0062, &nv04_graph_ofuncs }, /* surf2d */
-	{ 0x0072, &nv04_graph_ofuncs }, /* beta4 */
-	{ 0x0089, &nv04_graph_ofuncs }, /* sifm */
-	{ 0x008a, &nv04_graph_ofuncs }, /* ifc */
-	{ 0x009f, &nv04_graph_ofuncs }, /* blit */
-	{ 0x0093, &nv04_graph_ofuncs }, /* surf3d */
-	{ 0x0094, &nv04_graph_ofuncs }, /* ttri */
-	{ 0x0095, &nv04_graph_ofuncs }, /* mtri */
-	{ 0x0099, &nv04_graph_ofuncs, nv17_celcius_omthds },
-	{},
-};
-
-/*******************************************************************************
- * PGRAPH context
- ******************************************************************************/
-
-static struct nv10_graph_chan *
-nv10_graph_channel(struct nv10_graph_priv *priv)
-{
-	struct nv10_graph_chan *chan = NULL;
-	if (nv_rd32(priv, 0x400144) & 0x00010000) {
-		int chid = nv_rd32(priv, 0x400148) >> 24;
-		if (chid < ARRAY_SIZE(priv->chan))
-			chan = priv->chan[chid];
-	}
-	return chan;
-}
-
-static void
-nv10_graph_save_pipe(struct nv10_graph_chan *chan)
-{
-	struct nv10_graph_priv *priv = nv10_graph_priv(chan);
-	struct pipe_state *pipe = &chan->pipe_state;
-
-	PIPE_SAVE(priv, pipe->pipe_0x4400, 0x4400);
-	PIPE_SAVE(priv, pipe->pipe_0x0200, 0x0200);
-	PIPE_SAVE(priv, pipe->pipe_0x6400, 0x6400);
-	PIPE_SAVE(priv, pipe->pipe_0x6800, 0x6800);
-	PIPE_SAVE(priv, pipe->pipe_0x6c00, 0x6c00);
-	PIPE_SAVE(priv, pipe->pipe_0x7000, 0x7000);
-	PIPE_SAVE(priv, pipe->pipe_0x7400, 0x7400);
-	PIPE_SAVE(priv, pipe->pipe_0x7800, 0x7800);
-	PIPE_SAVE(priv, pipe->pipe_0x0040, 0x0040);
-	PIPE_SAVE(priv, pipe->pipe_0x0000, 0x0000);
-}
-
-static void
-nv10_graph_load_pipe(struct nv10_graph_chan *chan)
-{
-	struct nv10_graph_priv *priv = nv10_graph_priv(chan);
-	struct pipe_state *pipe = &chan->pipe_state;
-	u32 xfmode0, xfmode1;
-	int i;
-
-	nv04_graph_idle(priv);
-	/* XXX check haiku comments */
-	xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0);
-	xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1);
-	nv_wr32(priv, NV10_PGRAPH_XFMODE0, 0x10000000);
-	nv_wr32(priv, NV10_PGRAPH_XFMODE1, 0x00000000);
-	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
-	for (i = 0; i < 4; i++)
-		nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
-	for (i = 0; i < 4; i++)
-		nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000);
-
-	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
-	for (i = 0; i < 3; i++)
-		nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
-
-	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
-	for (i = 0; i < 3; i++)
-		nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000);
-
-	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
-	nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000008);
-
-
-	PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200);
-	nv04_graph_idle(priv);
-
-	/* restore XFMODE */
-	nv_wr32(priv, NV10_PGRAPH_XFMODE0, xfmode0);
-	nv_wr32(priv, NV10_PGRAPH_XFMODE1, xfmode1);
-	PIPE_RESTORE(priv, pipe->pipe_0x6400, 0x6400);
-	PIPE_RESTORE(priv, pipe->pipe_0x6800, 0x6800);
-	PIPE_RESTORE(priv, pipe->pipe_0x6c00, 0x6c00);
-	PIPE_RESTORE(priv, pipe->pipe_0x7000, 0x7000);
-	PIPE_RESTORE(priv, pipe->pipe_0x7400, 0x7400);
-	PIPE_RESTORE(priv, pipe->pipe_0x7800, 0x7800);
-	PIPE_RESTORE(priv, pipe->pipe_0x4400, 0x4400);
-	PIPE_RESTORE(priv, pipe->pipe_0x0000, 0x0000);
-	PIPE_RESTORE(priv, pipe->pipe_0x0040, 0x0040);
-	nv04_graph_idle(priv);
-}
-
-static void
-nv10_graph_create_pipe(struct nv10_graph_chan *chan)
-{
-	struct nv10_graph_priv *priv = nv10_graph_priv(chan);
-	struct pipe_state *pipe_state = &chan->pipe_state;
-	u32 *pipe_state_addr;
-	int i;
-#define PIPE_INIT(addr) \
-	do { \
-		pipe_state_addr = pipe_state->pipe_##addr; \
-	} while (0)
-#define PIPE_INIT_END(addr) \
-	do { \
-		u32 *__end_addr = pipe_state->pipe_##addr + \
-				ARRAY_SIZE(pipe_state->pipe_##addr); \
-		if (pipe_state_addr != __end_addr) \
-			nv_error(priv, "incomplete pipe init for 0x%x :  %p/%p\n", \
-				addr, pipe_state_addr, __end_addr); \
-	} while (0)
-#define NV_WRITE_PIPE_INIT(value) *(pipe_state_addr++) = value
-
-	PIPE_INIT(0x0200);
-	for (i = 0; i < 48; i++)
-		NV_WRITE_PIPE_INIT(0x00000000);
-	PIPE_INIT_END(0x0200);
-
-	PIPE_INIT(0x6400);
-	for (i = 0; i < 211; i++)
-		NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x3f800000);
-	NV_WRITE_PIPE_INIT(0x40000000);
-	NV_WRITE_PIPE_INIT(0x40000000);
-	NV_WRITE_PIPE_INIT(0x40000000);
-	NV_WRITE_PIPE_INIT(0x40000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x3f800000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x3f000000);
-	NV_WRITE_PIPE_INIT(0x3f000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x3f800000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x3f800000);
-	NV_WRITE_PIPE_INIT(0x3f800000);
-	NV_WRITE_PIPE_INIT(0x3f800000);
-	NV_WRITE_PIPE_INIT(0x3f800000);
-	PIPE_INIT_END(0x6400);
-
-	PIPE_INIT(0x6800);
-	for (i = 0; i < 162; i++)
-		NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x3f800000);
-	for (i = 0; i < 25; i++)
-		NV_WRITE_PIPE_INIT(0x00000000);
-	PIPE_INIT_END(0x6800);
-
-	PIPE_INIT(0x6c00);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0xbf800000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	PIPE_INIT_END(0x6c00);
-
-	PIPE_INIT(0x7000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x7149f2ca);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x7149f2ca);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x7149f2ca);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x7149f2ca);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x7149f2ca);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x7149f2ca);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x7149f2ca);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x00000000);
-	NV_WRITE_PIPE_INIT(0x7149f2ca);
-	for (i = 0; i < 35; i++)
-		NV_WRITE_PIPE_INIT(0x00000000);
-	PIPE_INIT_END(0x7000);
-
-	PIPE_INIT(0x7400);
-	for (i = 0; i < 48; i++)
-		NV_WRITE_PIPE_INIT(0x00000000);
-	PIPE_INIT_END(0x7400);
-
-	PIPE_INIT(0x7800);
-	for (i = 0; i < 48; i++)
-		NV_WRITE_PIPE_INIT(0x00000000);
-	PIPE_INIT_END(0x7800);
-
-	PIPE_INIT(0x4400);
-	for (i = 0; i < 32; i++)
-		NV_WRITE_PIPE_INIT(0x00000000);
-	PIPE_INIT_END(0x4400);
-
-	PIPE_INIT(0x0000);
-	for (i = 0; i < 16; i++)
-		NV_WRITE_PIPE_INIT(0x00000000);
-	PIPE_INIT_END(0x0000);
-
-	PIPE_INIT(0x0040);
-	for (i = 0; i < 4; i++)
-		NV_WRITE_PIPE_INIT(0x00000000);
-	PIPE_INIT_END(0x0040);
-
-#undef PIPE_INIT
-#undef PIPE_INIT_END
-#undef NV_WRITE_PIPE_INIT
-}
-
-static int
-nv10_graph_ctx_regs_find_offset(struct nv10_graph_priv *priv, int reg)
-{
-	int i;
-	for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++) {
-		if (nv10_graph_ctx_regs[i] == reg)
-			return i;
-	}
-	nv_error(priv, "unknow offset nv10_ctx_regs %d\n", reg);
-	return -1;
-}
-
-static int
-nv17_graph_ctx_regs_find_offset(struct nv10_graph_priv *priv, int reg)
-{
-	int i;
-	for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++) {
-		if (nv17_graph_ctx_regs[i] == reg)
-			return i;
-	}
-	nv_error(priv, "unknow offset nv17_ctx_regs %d\n", reg);
-	return -1;
-}
-
-static void
-nv10_graph_load_dma_vtxbuf(struct nv10_graph_chan *chan, int chid, u32 inst)
-{
-	struct nv10_graph_priv *priv = nv10_graph_priv(chan);
-	u32 st2, st2_dl, st2_dh, fifo_ptr, fifo[0x60/4];
-	u32 ctx_user, ctx_switch[5];
-	int i, subchan = -1;
-
-	/* NV10TCL_DMA_VTXBUF (method 0x18c) modifies hidden state
-	 * that cannot be restored via MMIO. Do it through the FIFO
-	 * instead.
-	 */
-
-	/* Look for a celsius object */
-	for (i = 0; i < 8; i++) {
-		int class = nv_rd32(priv, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff;
-
-		if (class == 0x56 || class == 0x96 || class == 0x99) {
-			subchan = i;
-			break;
-		}
-	}
-
-	if (subchan < 0 || !inst)
-		return;
-
-	/* Save the current ctx object */
-	ctx_user = nv_rd32(priv, NV10_PGRAPH_CTX_USER);
-	for (i = 0; i < 5; i++)
-		ctx_switch[i] = nv_rd32(priv, NV10_PGRAPH_CTX_SWITCH(i));
-
-	/* Save the FIFO state */
-	st2 = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2);
-	st2_dl = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2_DL);
-	st2_dh = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2_DH);
-	fifo_ptr = nv_rd32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR);
-
-	for (i = 0; i < ARRAY_SIZE(fifo); i++)
-		fifo[i] = nv_rd32(priv, 0x4007a0 + 4 * i);
-
-	/* Switch to the celsius subchannel */
-	for (i = 0; i < 5; i++)
-		nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(i),
-			nv_rd32(priv, NV10_PGRAPH_CTX_CACHE(subchan, i)));
-	nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13);
-
-	/* Inject NV10TCL_DMA_VTXBUF */
-	nv_wr32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR, 0);
-	nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2,
-		0x2c000000 | chid << 20 | subchan << 16 | 0x18c);
-	nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DL, inst);
-	nv_mask(priv, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000);
-	nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
-	nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
-
-	/* Restore the FIFO state */
-	for (i = 0; i < ARRAY_SIZE(fifo); i++)
-		nv_wr32(priv, 0x4007a0 + 4 * i, fifo[i]);
-
-	nv_wr32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR, fifo_ptr);
-	nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2, st2);
-	nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DL, st2_dl);
-	nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DH, st2_dh);
-
-	/* Restore the current ctx object */
-	for (i = 0; i < 5; i++)
-		nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(i), ctx_switch[i]);
-	nv_wr32(priv, NV10_PGRAPH_CTX_USER, ctx_user);
-}
-
-static int
-nv10_graph_load_context(struct nv10_graph_chan *chan, int chid)
-{
-	struct nv10_graph_priv *priv = nv10_graph_priv(chan);
-	u32 inst;
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++)
-		nv_wr32(priv, nv10_graph_ctx_regs[i], chan->nv10[i]);
-
-	if (nv_device(priv)->card_type >= NV_11 &&
-	    nv_device(priv)->chipset >= 0x17) {
-		for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++)
-			nv_wr32(priv, nv17_graph_ctx_regs[i], chan->nv17[i]);
-	}
-
-	nv10_graph_load_pipe(chan);
-
-	inst = nv_rd32(priv, NV10_PGRAPH_GLOBALSTATE1) & 0xffff;
-	nv10_graph_load_dma_vtxbuf(chan, chid, inst);
-
-	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
-	nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24);
-	nv_mask(priv, NV10_PGRAPH_FFINTFC_ST2, 0x30000000, 0x00000000);
-	return 0;
-}
-
-static int
-nv10_graph_unload_context(struct nv10_graph_chan *chan)
-{
-	struct nv10_graph_priv *priv = nv10_graph_priv(chan);
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++)
-		chan->nv10[i] = nv_rd32(priv, nv10_graph_ctx_regs[i]);
-
-	if (nv_device(priv)->card_type >= NV_11 &&
-	    nv_device(priv)->chipset >= 0x17) {
-		for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++)
-			chan->nv17[i] = nv_rd32(priv, nv17_graph_ctx_regs[i]);
-	}
-
-	nv10_graph_save_pipe(chan);
-
-	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000000);
-	nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000);
-	return 0;
-}
-
-static void
-nv10_graph_context_switch(struct nv10_graph_priv *priv)
-{
-	struct nv10_graph_chan *prev = NULL;
-	struct nv10_graph_chan *next = NULL;
-	unsigned long flags;
-	int chid;
-
-	spin_lock_irqsave(&priv->lock, flags);
-	nv04_graph_idle(priv);
-
-	/* If previous context is valid, we need to save it */
-	prev = nv10_graph_channel(priv);
-	if (prev)
-		nv10_graph_unload_context(prev);
-
-	/* load context for next channel */
-	chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
-	next = priv->chan[chid];
-	if (next)
-		nv10_graph_load_context(next, chid);
-
-	spin_unlock_irqrestore(&priv->lock, flags);
-}
-
-#define NV_WRITE_CTX(reg, val) do { \
-	int offset = nv10_graph_ctx_regs_find_offset(priv, reg); \
-	if (offset > 0) \
-		chan->nv10[offset] = val; \
-	} while (0)
-
-#define NV17_WRITE_CTX(reg, val) do { \
-	int offset = nv17_graph_ctx_regs_find_offset(priv, reg); \
-	if (offset > 0) \
-		chan->nv17[offset] = val; \
-	} while (0)
-
-static int
-nv10_graph_context_ctor(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass, void *data, u32 size,
-			struct nouveau_object **pobject)
-{
-	struct nouveau_fifo_chan *fifo = (void *)parent;
-	struct nv10_graph_priv *priv = (void *)engine;
-	struct nv10_graph_chan *chan;
-	unsigned long flags;
-	int ret;
-
-	ret = nouveau_object_create(parent, engine, oclass, 0, &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	spin_lock_irqsave(&priv->lock, flags);
-	if (priv->chan[fifo->chid]) {
-		*pobject = nv_object(priv->chan[fifo->chid]);
-		atomic_inc(&(*pobject)->refcount);
-		spin_unlock_irqrestore(&priv->lock, flags);
-		nouveau_object_destroy(&chan->base);
-		return 1;
-	}
-
-	NV_WRITE_CTX(0x00400e88, 0x08000000);
-	NV_WRITE_CTX(0x00400e9c, 0x4b7fffff);
-	NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff);
-	NV_WRITE_CTX(0x00400e10, 0x00001000);
-	NV_WRITE_CTX(0x00400e14, 0x00001000);
-	NV_WRITE_CTX(0x00400e30, 0x00080008);
-	NV_WRITE_CTX(0x00400e34, 0x00080008);
-	if (nv_device(priv)->card_type >= NV_11 &&
-	    nv_device(priv)->chipset >= 0x17) {
-		/* is it really needed ??? */
-		NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4,
-					nv_rd32(priv, NV10_PGRAPH_DEBUG_4));
-		NV17_WRITE_CTX(0x004006b0, nv_rd32(priv, 0x004006b0));
-		NV17_WRITE_CTX(0x00400eac, 0x0fff0000);
-		NV17_WRITE_CTX(0x00400eb0, 0x0fff0000);
-		NV17_WRITE_CTX(0x00400ec0, 0x00000080);
-		NV17_WRITE_CTX(0x00400ed0, 0x00000080);
-	}
-	NV_WRITE_CTX(NV10_PGRAPH_CTX_USER, chan->chid << 24);
-
-	nv10_graph_create_pipe(chan);
-
-	priv->chan[fifo->chid] = chan;
-	chan->chid = fifo->chid;
-	spin_unlock_irqrestore(&priv->lock, flags);
-	return 0;
-}
-
-static void
-nv10_graph_context_dtor(struct nouveau_object *object)
-{
-	struct nv10_graph_priv *priv = (void *)object->engine;
-	struct nv10_graph_chan *chan = (void *)object;
-	unsigned long flags;
-
-	spin_lock_irqsave(&priv->lock, flags);
-	priv->chan[chan->chid] = NULL;
-	spin_unlock_irqrestore(&priv->lock, flags);
-
-	nouveau_object_destroy(&chan->base);
-}
-
-static int
-nv10_graph_context_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv10_graph_priv *priv = (void *)object->engine;
-	struct nv10_graph_chan *chan = (void *)object;
-	unsigned long flags;
-
-	spin_lock_irqsave(&priv->lock, flags);
-	nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
-	if (nv10_graph_channel(priv) == chan)
-		nv10_graph_unload_context(chan);
-	nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
-	spin_unlock_irqrestore(&priv->lock, flags);
-
-	return nouveau_object_fini(&chan->base, suspend);
-}
-
-static struct nouveau_oclass
-nv10_graph_cclass = {
-	.handle = NV_ENGCTX(GR, 0x10),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv10_graph_context_ctor,
-		.dtor = nv10_graph_context_dtor,
-		.init = nouveau_object_init,
-		.fini = nv10_graph_context_fini,
-	},
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-static void
-nv10_graph_tile_prog(struct nouveau_engine *engine, int i)
-{
-	struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
-	struct nouveau_fifo *pfifo = nouveau_fifo(engine);
-	struct nv10_graph_priv *priv = (void *)engine;
-	unsigned long flags;
-
-	pfifo->pause(pfifo, &flags);
-	nv04_graph_idle(priv);
-
-	nv_wr32(priv, NV10_PGRAPH_TLIMIT(i), tile->limit);
-	nv_wr32(priv, NV10_PGRAPH_TSIZE(i), tile->pitch);
-	nv_wr32(priv, NV10_PGRAPH_TILE(i), tile->addr);
-
-	pfifo->start(pfifo, &flags);
-}
-
-const struct nouveau_bitfield nv10_graph_intr_name[] = {
-	{ NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
-	{ NV_PGRAPH_INTR_ERROR,  "ERROR"  },
-	{}
-};
-
-const struct nouveau_bitfield nv10_graph_nstatus[] = {
-	{ NV10_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
-	{ NV10_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
-	{ NV10_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
-	{ NV10_PGRAPH_NSTATUS_PROTECTION_FAULT,   "PROTECTION_FAULT" },
-	{}
-};
-
-static void
-nv10_graph_intr(struct nouveau_subdev *subdev)
-{
-	struct nv10_graph_priv *priv = (void *)subdev;
-	struct nv10_graph_chan *chan = NULL;
-	struct nouveau_namedb *namedb = NULL;
-	struct nouveau_handle *handle = NULL;
-	u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
-	u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
-	u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
-	u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
-	u32 chid = (addr & 0x01f00000) >> 20;
-	u32 subc = (addr & 0x00070000) >> 16;
-	u32 mthd = (addr & 0x00001ffc);
-	u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
-	u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff;
-	u32 show = stat;
-	unsigned long flags;
-
-	spin_lock_irqsave(&priv->lock, flags);
-	chan = priv->chan[chid];
-	if (chan)
-		namedb = (void *)nv_pclass(nv_object(chan), NV_NAMEDB_CLASS);
-	spin_unlock_irqrestore(&priv->lock, flags);
-
-	if (stat & NV_PGRAPH_INTR_ERROR) {
-		if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) {
-			handle = nouveau_namedb_get_class(namedb, class);
-			if (handle && !nv_call(handle->object, mthd, data))
-				show &= ~NV_PGRAPH_INTR_ERROR;
-		}
-	}
-
-	if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
-		nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
-		stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
-		show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
-		nv10_graph_context_switch(priv);
-	}
-
-	nv_wr32(priv, NV03_PGRAPH_INTR, stat);
-	nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
-
-	if (show) {
-		nv_error(priv, "%s", "");
-		nouveau_bitfield_print(nv10_graph_intr_name, show);
-		pr_cont(" nsource:");
-		nouveau_bitfield_print(nv04_graph_nsource, nsource);
-		pr_cont(" nstatus:");
-		nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
-		pr_cont("\n");
-		nv_error(priv,
-			 "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
-			 chid, nouveau_client_name(chan), subc, class, mthd,
-			 data);
-	}
-
-	nouveau_namedb_put(handle);
-}
-
-static int
-nv10_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nv10_graph_priv *priv;
-	int ret;
-
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv10_graph_intr;
-	nv_engine(priv)->cclass = &nv10_graph_cclass;
-
-	if (nv_device(priv)->chipset <= 0x10)
-		nv_engine(priv)->sclass = nv10_graph_sclass;
-	else
-	if (nv_device(priv)->chipset <  0x17 ||
-	    nv_device(priv)->card_type < NV_11)
-		nv_engine(priv)->sclass = nv15_graph_sclass;
-	else
-		nv_engine(priv)->sclass = nv17_graph_sclass;
-
-	nv_engine(priv)->tile_prog = nv10_graph_tile_prog;
-	spin_lock_init(&priv->lock);
-	return 0;
-}
-
-static void
-nv10_graph_dtor(struct nouveau_object *object)
-{
-	struct nv10_graph_priv *priv = (void *)object;
-	nouveau_graph_destroy(&priv->base);
-}
-
-static int
-nv10_graph_init(struct nouveau_object *object)
-{
-	struct nouveau_engine *engine = nv_engine(object);
-	struct nouveau_fb *pfb = nouveau_fb(object);
-	struct nv10_graph_priv *priv = (void *)engine;
-	int ret, i;
-
-	ret = nouveau_graph_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
-	nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
-
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700);
-	/* nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x24E00810); */ /* 0x25f92ad9 */
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x25f92ad9);
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31));
-
-	if (nv_device(priv)->card_type >= NV_11 &&
-	    nv_device(priv)->chipset >= 0x17) {
-		nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x1f000000);
-		nv_wr32(priv, 0x400a10, 0x03ff3fb6);
-		nv_wr32(priv, 0x400838, 0x002f8684);
-		nv_wr32(priv, 0x40083c, 0x00115f3f);
-		nv_wr32(priv, 0x4006b0, 0x40000020);
-	} else {
-		nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000);
-	}
-
-	/* Turn all the tiling regions off. */
-	for (i = 0; i < pfb->tile.regions; i++)
-		engine->tile_prog(engine, i);
-
-	nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000);
-	nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000);
-	nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000);
-	nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000);
-	nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000);
-	nv_wr32(priv, NV10_PGRAPH_STATE, 0xFFFFFFFF);
-
-	nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000);
-	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
-	nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2, 0x08000000);
-	return 0;
-}
-
-static int
-nv10_graph_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv10_graph_priv *priv = (void *)object;
-	return nouveau_graph_fini(&priv->base, suspend);
-}
-
-struct nouveau_oclass
-nv10_graph_oclass = {
-	.handle = NV_ENGINE(GR, 0x10),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv10_graph_ctor,
-		.dtor = nv10_graph_dtor,
-		.init = nv10_graph_init,
-		.fini = nv10_graph_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv108.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv108.c
deleted file mode 100644
index 2b0e8f48c029..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv108.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv108_graph_sclass[] = {
-	{ 0x902d, &nouveau_object_ofuncs },
-	{ 0xa140, &nouveau_object_ofuncs },
-	{ KEPLER_B, &nvc0_fermi_ofuncs },
-	{ 0xa1c0, &nouveau_object_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH register lists
- ******************************************************************************/
-
-static const struct nvc0_graph_init
-nv108_graph_init_main_0[] = {
-	{ 0x400080,   1, 0x04, 0x003083c2 },
-	{ 0x400088,   1, 0x04, 0x0001bfe7 },
-	{ 0x40008c,   1, 0x04, 0x00000000 },
-	{ 0x400090,   1, 0x04, 0x00000030 },
-	{ 0x40013c,   1, 0x04, 0x003901f7 },
-	{ 0x400140,   1, 0x04, 0x00000100 },
-	{ 0x400144,   1, 0x04, 0x00000000 },
-	{ 0x400148,   1, 0x04, 0x00000110 },
-	{ 0x400138,   1, 0x04, 0x00000000 },
-	{ 0x400130,   2, 0x04, 0x00000000 },
-	{ 0x400124,   1, 0x04, 0x00000002 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nv108_graph_init_ds_0[] = {
-	{ 0x405844,   1, 0x04, 0x00ffffff },
-	{ 0x405850,   1, 0x04, 0x00000000 },
-	{ 0x405900,   1, 0x04, 0x00000000 },
-	{ 0x405908,   1, 0x04, 0x00000000 },
-	{ 0x405928,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nv108_graph_init_gpc_unk_0[] = {
-	{ 0x418604,   1, 0x04, 0x00000000 },
-	{ 0x418680,   1, 0x04, 0x00000000 },
-	{ 0x418714,   1, 0x04, 0x00000000 },
-	{ 0x418384,   2, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nv108_graph_init_setup_1[] = {
-	{ 0x4188c8,   2, 0x04, 0x00000000 },
-	{ 0x4188d0,   1, 0x04, 0x00010000 },
-	{ 0x4188d4,   1, 0x04, 0x00000201 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nv108_graph_init_tex_0[] = {
-	{ 0x419ab0,   1, 0x04, 0x00000000 },
-	{ 0x419ac8,   1, 0x04, 0x00000000 },
-	{ 0x419ab8,   1, 0x04, 0x000000e7 },
-	{ 0x419abc,   2, 0x04, 0x00000000 },
-	{ 0x419ab4,   1, 0x04, 0x00000000 },
-	{ 0x419aa8,   2, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nv108_graph_init_l1c_0[] = {
-	{ 0x419c98,   1, 0x04, 0x00000000 },
-	{ 0x419ca8,   1, 0x04, 0x00000000 },
-	{ 0x419cb0,   1, 0x04, 0x01000000 },
-	{ 0x419cb4,   1, 0x04, 0x00000000 },
-	{ 0x419cb8,   1, 0x04, 0x00b08bea },
-	{ 0x419c84,   1, 0x04, 0x00010384 },
-	{ 0x419cbc,   1, 0x04, 0x281b3646 },
-	{ 0x419cc0,   2, 0x04, 0x00000000 },
-	{ 0x419c80,   1, 0x04, 0x00000230 },
-	{ 0x419ccc,   2, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nv108_graph_pack_mmio[] = {
-	{ nv108_graph_init_main_0 },
-	{ nvf0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvd9_graph_init_pd_0 },
-	{ nv108_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvf0_graph_init_sked_0 },
-	{ nvf0_graph_init_cwd_0 },
-	{ nvd9_graph_init_prop_0 },
-	{ nv108_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nv108_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvd9_graph_init_gpm_0 },
-	{ nvf0_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nve4_graph_init_tpccs_0 },
-	{ nv108_graph_init_tex_0 },
-	{ nve4_graph_init_pe_0 },
-	{ nv108_graph_init_l1c_0 },
-	{ nvc0_graph_init_mpc_0 },
-	{ nvf0_graph_init_sm_0 },
-	{ nvd7_graph_init_pes_0 },
-	{ nvd7_graph_init_wwdx_0 },
-	{ nvd7_graph_init_cbm_0 },
-	{ nve4_graph_init_be_0 },
-	{ nvc0_graph_init_fe_1 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-static int
-nv108_graph_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nvc0_graph_priv *priv = (void *)object;
-	static const struct {
-		u32 addr;
-		u32 data;
-	} magic[] = {
-		{ 0x020520, 0xfffffffc },
-		{ 0x020524, 0xfffffffe },
-		{ 0x020524, 0xfffffffc },
-		{ 0x020524, 0xfffffff8 },
-		{ 0x020524, 0xffffffe0 },
-		{ 0x020530, 0xfffffffe },
-		{ 0x02052c, 0xfffffffa },
-		{ 0x02052c, 0xfffffff0 },
-		{ 0x02052c, 0xffffffc0 },
-		{ 0x02052c, 0xffffff00 },
-		{ 0x02052c, 0xfffffc00 },
-		{ 0x02052c, 0xfffcfc00 },
-		{ 0x02052c, 0xfff0fc00 },
-		{ 0x02052c, 0xff80fc00 },
-		{ 0x020528, 0xfffffffe },
-		{ 0x020528, 0xfffffffc },
-	};
-	int i;
-
-	nv_mask(priv, 0x000200, 0x08001000, 0x00000000);
-	nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000);
-	for (i = 0; i < ARRAY_SIZE(magic); i++) {
-		nv_wr32(priv, magic[i].addr, magic[i].data);
-		nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000);
-	}
-
-	return nouveau_graph_fini(&priv->base, suspend);
-}
-
-#include "fuc/hubnv108.fuc5.h"
-
-static struct nvc0_graph_ucode
-nv108_graph_fecs_ucode = {
-	.code.data = nv108_grhub_code,
-	.code.size = sizeof(nv108_grhub_code),
-	.data.data = nv108_grhub_data,
-	.data.size = sizeof(nv108_grhub_data),
-};
-
-#include "fuc/gpcnv108.fuc5.h"
-
-static struct nvc0_graph_ucode
-nv108_graph_gpccs_ucode = {
-	.code.data = nv108_grgpc_code,
-	.code.size = sizeof(nv108_grgpc_code),
-	.data.data = nv108_grgpc_data,
-	.data.size = sizeof(nv108_grgpc_data),
-};
-
-struct nouveau_oclass *
-nv108_graph_oclass = &(struct nvc0_graph_oclass) {
-	.base.handle = NV_ENGINE(GR, 0x08),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nve4_graph_init,
-		.fini = nv108_graph_fini,
-	},
-	.cclass = &nv108_grctx_oclass,
-	.sclass =  nv108_graph_sclass,
-	.mmio = nv108_graph_pack_mmio,
-	.fecs.ucode = &nv108_graph_fecs_ucode,
-	.gpccs.ucode = &nv108_graph_gpccs_ucode,
-	.ppc_nr = 1,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
deleted file mode 100644
index ceb9c746d94e..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
+++ /dev/null
@@ -1,383 +0,0 @@
-#include <core/client.h>
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/handle.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/graph.h>
-#include <engine/fifo.h>
-
-#include "nv20.h"
-#include "regs.h"
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv20_graph_sclass[] = {
-	{ 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
-	{ 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
-	{ 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
-	{ 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
-	{ 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
-	{ 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
-	{ 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
-	{ 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
-	{ 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
-	{ 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
-	{ 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
-	{ 0x0096, &nv04_graph_ofuncs, NULL }, /* celcius */
-	{ 0x0097, &nv04_graph_ofuncs, NULL }, /* kelvin */
-	{ 0x009e, &nv04_graph_ofuncs, NULL }, /* swzsurf */
-	{ 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
-	{},
-};
-
-/*******************************************************************************
- * PGRAPH context
- ******************************************************************************/
-
-static int
-nv20_graph_context_ctor(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass, void *data, u32 size,
-			struct nouveau_object **pobject)
-{
-	struct nv20_graph_chan *chan;
-	int ret, i;
-
-	ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
-					   0x37f0, 16, NVOBJ_FLAG_ZERO_ALLOC,
-					   &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	chan->chid = nouveau_fifo_chan(parent)->chid;
-
-	nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24));
-	nv_wo32(chan, 0x033c, 0xffff0000);
-	nv_wo32(chan, 0x03a0, 0x0fff0000);
-	nv_wo32(chan, 0x03a4, 0x0fff0000);
-	nv_wo32(chan, 0x047c, 0x00000101);
-	nv_wo32(chan, 0x0490, 0x00000111);
-	nv_wo32(chan, 0x04a8, 0x44400000);
-	for (i = 0x04d4; i <= 0x04e0; i += 4)
-		nv_wo32(chan, i, 0x00030303);
-	for (i = 0x04f4; i <= 0x0500; i += 4)
-		nv_wo32(chan, i, 0x00080000);
-	for (i = 0x050c; i <= 0x0518; i += 4)
-		nv_wo32(chan, i, 0x01012000);
-	for (i = 0x051c; i <= 0x0528; i += 4)
-		nv_wo32(chan, i, 0x000105b8);
-	for (i = 0x052c; i <= 0x0538; i += 4)
-		nv_wo32(chan, i, 0x00080008);
-	for (i = 0x055c; i <= 0x0598; i += 4)
-		nv_wo32(chan, i, 0x07ff0000);
-	nv_wo32(chan, 0x05a4, 0x4b7fffff);
-	nv_wo32(chan, 0x05fc, 0x00000001);
-	nv_wo32(chan, 0x0604, 0x00004000);
-	nv_wo32(chan, 0x0610, 0x00000001);
-	nv_wo32(chan, 0x0618, 0x00040000);
-	nv_wo32(chan, 0x061c, 0x00010000);
-	for (i = 0x1c1c; i <= 0x248c; i += 16) {
-		nv_wo32(chan, (i + 0), 0x10700ff9);
-		nv_wo32(chan, (i + 4), 0x0436086c);
-		nv_wo32(chan, (i + 8), 0x000c001b);
-	}
-	nv_wo32(chan, 0x281c, 0x3f800000);
-	nv_wo32(chan, 0x2830, 0x3f800000);
-	nv_wo32(chan, 0x285c, 0x40000000);
-	nv_wo32(chan, 0x2860, 0x3f800000);
-	nv_wo32(chan, 0x2864, 0x3f000000);
-	nv_wo32(chan, 0x286c, 0x40000000);
-	nv_wo32(chan, 0x2870, 0x3f800000);
-	nv_wo32(chan, 0x2878, 0xbf800000);
-	nv_wo32(chan, 0x2880, 0xbf800000);
-	nv_wo32(chan, 0x34a4, 0x000fe000);
-	nv_wo32(chan, 0x3530, 0x000003f8);
-	nv_wo32(chan, 0x3540, 0x002fe000);
-	for (i = 0x355c; i <= 0x3578; i += 4)
-		nv_wo32(chan, i, 0x001c527c);
-	return 0;
-}
-
-int
-nv20_graph_context_init(struct nouveau_object *object)
-{
-	struct nv20_graph_priv *priv = (void *)object->engine;
-	struct nv20_graph_chan *chan = (void *)object;
-	int ret;
-
-	ret = nouveau_graph_context_init(&chan->base);
-	if (ret)
-		return ret;
-
-	nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4);
-	return 0;
-}
-
-int
-nv20_graph_context_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv20_graph_priv *priv = (void *)object->engine;
-	struct nv20_graph_chan *chan = (void *)object;
-	int chid = -1;
-
-	nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
-	if (nv_rd32(priv, 0x400144) & 0x00010000)
-		chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24;
-	if (chan->chid == chid) {
-		nv_wr32(priv, 0x400784, nv_gpuobj(chan)->addr >> 4);
-		nv_wr32(priv, 0x400788, 0x00000002);
-		nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
-		nv_wr32(priv, 0x400144, 0x10000000);
-		nv_mask(priv, 0x400148, 0xff000000, 0x1f000000);
-	}
-	nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
-
-	nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000);
-	return nouveau_graph_context_fini(&chan->base, suspend);
-}
-
-static struct nouveau_oclass
-nv20_graph_cclass = {
-	.handle = NV_ENGCTX(GR, 0x20),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv20_graph_context_ctor,
-		.dtor = _nouveau_graph_context_dtor,
-		.init = nv20_graph_context_init,
-		.fini = nv20_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-void
-nv20_graph_tile_prog(struct nouveau_engine *engine, int i)
-{
-	struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
-	struct nouveau_fifo *pfifo = nouveau_fifo(engine);
-	struct nv20_graph_priv *priv = (void *)engine;
-	unsigned long flags;
-
-	pfifo->pause(pfifo, &flags);
-	nv04_graph_idle(priv);
-
-	nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
-	nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
-	nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
-
-	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
-	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit);
-	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
-	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch);
-	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
-	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr);
-
-	if (nv_device(engine)->chipset != 0x34) {
-		nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
-		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
-		nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp);
-	}
-
-	pfifo->start(pfifo, &flags);
-}
-
-void
-nv20_graph_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_engine *engine = nv_engine(subdev);
-	struct nouveau_object *engctx;
-	struct nouveau_handle *handle;
-	struct nv20_graph_priv *priv = (void *)subdev;
-	u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
-	u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
-	u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
-	u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
-	u32 chid = (addr & 0x01f00000) >> 20;
-	u32 subc = (addr & 0x00070000) >> 16;
-	u32 mthd = (addr & 0x00001ffc);
-	u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
-	u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff;
-	u32 show = stat;
-
-	engctx = nouveau_engctx_get(engine, chid);
-	if (stat & NV_PGRAPH_INTR_ERROR) {
-		if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
-			handle = nouveau_handle_get_class(engctx, class);
-			if (handle && !nv_call(handle->object, mthd, data))
-				show &= ~NV_PGRAPH_INTR_ERROR;
-			nouveau_handle_put(handle);
-		}
-	}
-
-	nv_wr32(priv, NV03_PGRAPH_INTR, stat);
-	nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
-
-	if (show) {
-		nv_error(priv, "%s", "");
-		nouveau_bitfield_print(nv10_graph_intr_name, show);
-		pr_cont(" nsource:");
-		nouveau_bitfield_print(nv04_graph_nsource, nsource);
-		pr_cont(" nstatus:");
-		nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
-		pr_cont("\n");
-		nv_error(priv,
-			 "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
-			 chid, nouveau_client_name(engctx), subc, class, mthd,
-			 data);
-	}
-
-	nouveau_engctx_put(engctx);
-}
-
-static int
-nv20_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv20_graph_priv *priv;
-	int ret;
-
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
-				 NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv20_graph_intr;
-	nv_engine(priv)->cclass = &nv20_graph_cclass;
-	nv_engine(priv)->sclass = nv20_graph_sclass;
-	nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
-	return 0;
-}
-
-void
-nv20_graph_dtor(struct nouveau_object *object)
-{
-	struct nv20_graph_priv *priv = (void *)object;
-	nouveau_gpuobj_ref(NULL, &priv->ctxtab);
-	nouveau_graph_destroy(&priv->base);
-}
-
-int
-nv20_graph_init(struct nouveau_object *object)
-{
-	struct nouveau_engine *engine = nv_engine(object);
-	struct nv20_graph_priv *priv = (void *)engine;
-	struct nouveau_fb *pfb = nouveau_fb(object);
-	u32 tmp, vramsz;
-	int ret, i;
-
-	ret = nouveau_graph_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4);
-
-	if (nv_device(priv)->chipset == 0x20) {
-		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
-		for (i = 0; i < 15; i++)
-			nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
-		nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
-	} else {
-		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
-		for (i = 0; i < 32; i++)
-			nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
-		nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
-	}
-
-	nv_wr32(priv, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
-	nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
-
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700);
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
-	nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000);
-	nv_wr32(priv, 0x40009C           , 0x00000040);
-
-	if (nv_device(priv)->chipset >= 0x25) {
-		nv_wr32(priv, 0x400890, 0x00a8cfff);
-		nv_wr32(priv, 0x400610, 0x304B1FB6);
-		nv_wr32(priv, 0x400B80, 0x1cbd3883);
-		nv_wr32(priv, 0x400B84, 0x44000000);
-		nv_wr32(priv, 0x400098, 0x40000080);
-		nv_wr32(priv, 0x400B88, 0x000000ff);
-
-	} else {
-		nv_wr32(priv, 0x400880, 0x0008c7df);
-		nv_wr32(priv, 0x400094, 0x00000005);
-		nv_wr32(priv, 0x400B80, 0x45eae20e);
-		nv_wr32(priv, 0x400B84, 0x24000000);
-		nv_wr32(priv, 0x400098, 0x00000040);
-		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
-		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
-		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
-		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
-	}
-
-	/* Turn all the tiling regions off. */
-	for (i = 0; i < pfb->tile.regions; i++)
-		engine->tile_prog(engine, i);
-
-	nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324));
-	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
-	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, nv_rd32(priv, 0x100324));
-
-	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
-	nv_wr32(priv, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
-
-	tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) & 0x0007ff00;
-	nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
-	tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) | 0x00020100;
-	nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
-
-	/* begin RAM config */
-	vramsz = nv_device_resource_len(nv_device(priv), 0) - 1;
-	nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
-	nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
-	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
-	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100200));
-	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
-	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100204));
-	nv_wr32(priv, 0x400820, 0);
-	nv_wr32(priv, 0x400824, 0);
-	nv_wr32(priv, 0x400864, vramsz - 1);
-	nv_wr32(priv, 0x400868, vramsz - 1);
-
-	/* interesting.. the below overwrites some of the tile setup above.. */
-	nv_wr32(priv, 0x400B20, 0x00000000);
-	nv_wr32(priv, 0x400B04, 0xFFFFFFFF);
-
-	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
-	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
-	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
-	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
-	return 0;
-}
-
-struct nouveau_oclass
-nv20_graph_oclass = {
-	.handle = NV_ENGINE(GR, 0x20),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv20_graph_ctor,
-		.dtor = nv20_graph_dtor,
-		.init = nv20_graph_init,
-		.fini = _nouveau_graph_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.h b/drivers/gpu/drm/nouveau/core/engine/graph/nv20.h
deleted file mode 100644
index 2bea7313e03f..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef __NV20_GRAPH_H__
-#define __NV20_GRAPH_H__
-
-#include <core/enum.h>
-
-#include <engine/graph.h>
-#include <engine/fifo.h>
-
-struct nv20_graph_priv {
-	struct nouveau_graph base;
-	struct nouveau_gpuobj *ctxtab;
-};
-
-struct nv20_graph_chan {
-	struct nouveau_graph_chan base;
-	int chid;
-};
-
-extern struct nouveau_oclass nv25_graph_sclass[];
-int  nv20_graph_context_init(struct nouveau_object *);
-int  nv20_graph_context_fini(struct nouveau_object *, bool);
-
-void nv20_graph_tile_prog(struct nouveau_engine *, int);
-void nv20_graph_intr(struct nouveau_subdev *);
-
-void nv20_graph_dtor(struct nouveau_object *);
-int  nv20_graph_init(struct nouveau_object *);
-
-int  nv30_graph_init(struct nouveau_object *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv25.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv25.c
deleted file mode 100644
index f8a6fdd7d5e8..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv25.c
+++ /dev/null
@@ -1,166 +0,0 @@
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/graph.h>
-
-#include "nv20.h"
-#include "regs.h"
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-struct nouveau_oclass
-nv25_graph_sclass[] = {
-	{ 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
-	{ 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
-	{ 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
-	{ 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
-	{ 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
-	{ 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
-	{ 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
-	{ 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
-	{ 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
-	{ 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
-	{ 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
-	{ 0x0096, &nv04_graph_ofuncs, NULL }, /* celcius */
-	{ 0x009e, &nv04_graph_ofuncs, NULL }, /* swzsurf */
-	{ 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
-	{ 0x0597, &nv04_graph_ofuncs, NULL }, /* kelvin */
-	{},
-};
-
-/*******************************************************************************
- * PGRAPH context
- ******************************************************************************/
-
-static int
-nv25_graph_context_ctor(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass, void *data, u32 size,
-			struct nouveau_object **pobject)
-{
-	struct nv20_graph_chan *chan;
-	int ret, i;
-
-	ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x3724,
-					   16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	chan->chid = nouveau_fifo_chan(parent)->chid;
-
-	nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
-	nv_wo32(chan, 0x035c, 0xffff0000);
-	nv_wo32(chan, 0x03c0, 0x0fff0000);
-	nv_wo32(chan, 0x03c4, 0x0fff0000);
-	nv_wo32(chan, 0x049c, 0x00000101);
-	nv_wo32(chan, 0x04b0, 0x00000111);
-	nv_wo32(chan, 0x04c8, 0x00000080);
-	nv_wo32(chan, 0x04cc, 0xffff0000);
-	nv_wo32(chan, 0x04d0, 0x00000001);
-	nv_wo32(chan, 0x04e4, 0x44400000);
-	nv_wo32(chan, 0x04fc, 0x4b800000);
-	for (i = 0x0510; i <= 0x051c; i += 4)
-		nv_wo32(chan, i, 0x00030303);
-	for (i = 0x0530; i <= 0x053c; i += 4)
-		nv_wo32(chan, i, 0x00080000);
-	for (i = 0x0548; i <= 0x0554; i += 4)
-		nv_wo32(chan, i, 0x01012000);
-	for (i = 0x0558; i <= 0x0564; i += 4)
-		nv_wo32(chan, i, 0x000105b8);
-	for (i = 0x0568; i <= 0x0574; i += 4)
-		nv_wo32(chan, i, 0x00080008);
-	for (i = 0x0598; i <= 0x05d4; i += 4)
-		nv_wo32(chan, i, 0x07ff0000);
-	nv_wo32(chan, 0x05e0, 0x4b7fffff);
-	nv_wo32(chan, 0x0620, 0x00000080);
-	nv_wo32(chan, 0x0624, 0x30201000);
-	nv_wo32(chan, 0x0628, 0x70605040);
-	nv_wo32(chan, 0x062c, 0xb0a09080);
-	nv_wo32(chan, 0x0630, 0xf0e0d0c0);
-	nv_wo32(chan, 0x0664, 0x00000001);
-	nv_wo32(chan, 0x066c, 0x00004000);
-	nv_wo32(chan, 0x0678, 0x00000001);
-	nv_wo32(chan, 0x0680, 0x00040000);
-	nv_wo32(chan, 0x0684, 0x00010000);
-	for (i = 0x1b04; i <= 0x2374; i += 16) {
-		nv_wo32(chan, (i + 0), 0x10700ff9);
-		nv_wo32(chan, (i + 4), 0x0436086c);
-		nv_wo32(chan, (i + 8), 0x000c001b);
-	}
-	nv_wo32(chan, 0x2704, 0x3f800000);
-	nv_wo32(chan, 0x2718, 0x3f800000);
-	nv_wo32(chan, 0x2744, 0x40000000);
-	nv_wo32(chan, 0x2748, 0x3f800000);
-	nv_wo32(chan, 0x274c, 0x3f000000);
-	nv_wo32(chan, 0x2754, 0x40000000);
-	nv_wo32(chan, 0x2758, 0x3f800000);
-	nv_wo32(chan, 0x2760, 0xbf800000);
-	nv_wo32(chan, 0x2768, 0xbf800000);
-	nv_wo32(chan, 0x308c, 0x000fe000);
-	nv_wo32(chan, 0x3108, 0x000003f8);
-	nv_wo32(chan, 0x3468, 0x002fe000);
-	for (i = 0x3484; i <= 0x34a0; i += 4)
-		nv_wo32(chan, i, 0x001c527c);
-	return 0;
-}
-
-static struct nouveau_oclass
-nv25_graph_cclass = {
-	.handle = NV_ENGCTX(GR, 0x25),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv25_graph_context_ctor,
-		.dtor = _nouveau_graph_context_dtor,
-		.init = nv20_graph_context_init,
-		.fini = nv20_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-static int
-nv25_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv20_graph_priv *priv;
-	int ret;
-
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
-				 NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv20_graph_intr;
-	nv_engine(priv)->cclass = &nv25_graph_cclass;
-	nv_engine(priv)->sclass = nv25_graph_sclass;
-	nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
-	return 0;
-}
-
-struct nouveau_oclass
-nv25_graph_oclass = {
-	.handle = NV_ENGINE(GR, 0x25),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv25_graph_ctor,
-		.dtor = nv20_graph_dtor,
-		.init = nv20_graph_init,
-		.fini = _nouveau_graph_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c
deleted file mode 100644
index 5de9caa2ef67..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c
+++ /dev/null
@@ -1,133 +0,0 @@
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/graph.h>
-
-#include "nv20.h"
-#include "regs.h"
-
-/*******************************************************************************
- * PGRAPH context
- ******************************************************************************/
-
-static int
-nv2a_graph_context_ctor(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass, void *data, u32 size,
-			struct nouveau_object **pobject)
-{
-	struct nv20_graph_chan *chan;
-	int ret, i;
-
-	ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x36b0,
-					   16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	chan->chid = nouveau_fifo_chan(parent)->chid;
-
-	nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24));
-	nv_wo32(chan, 0x033c, 0xffff0000);
-	nv_wo32(chan, 0x03a0, 0x0fff0000);
-	nv_wo32(chan, 0x03a4, 0x0fff0000);
-	nv_wo32(chan, 0x047c, 0x00000101);
-	nv_wo32(chan, 0x0490, 0x00000111);
-	nv_wo32(chan, 0x04a8, 0x44400000);
-	for (i = 0x04d4; i <= 0x04e0; i += 4)
-		nv_wo32(chan, i, 0x00030303);
-	for (i = 0x04f4; i <= 0x0500; i += 4)
-		nv_wo32(chan, i, 0x00080000);
-	for (i = 0x050c; i <= 0x0518; i += 4)
-		nv_wo32(chan, i, 0x01012000);
-	for (i = 0x051c; i <= 0x0528; i += 4)
-		nv_wo32(chan, i, 0x000105b8);
-	for (i = 0x052c; i <= 0x0538; i += 4)
-		nv_wo32(chan, i, 0x00080008);
-	for (i = 0x055c; i <= 0x0598; i += 4)
-		nv_wo32(chan, i, 0x07ff0000);
-	nv_wo32(chan, 0x05a4, 0x4b7fffff);
-	nv_wo32(chan, 0x05fc, 0x00000001);
-	nv_wo32(chan, 0x0604, 0x00004000);
-	nv_wo32(chan, 0x0610, 0x00000001);
-	nv_wo32(chan, 0x0618, 0x00040000);
-	nv_wo32(chan, 0x061c, 0x00010000);
-	for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */
-		nv_wo32(chan, (i + 0), 0x10700ff9);
-		nv_wo32(chan, (i + 4), 0x0436086c);
-		nv_wo32(chan, (i + 8), 0x000c001b);
-	}
-	nv_wo32(chan, 0x269c, 0x3f800000);
-	nv_wo32(chan, 0x26b0, 0x3f800000);
-	nv_wo32(chan, 0x26dc, 0x40000000);
-	nv_wo32(chan, 0x26e0, 0x3f800000);
-	nv_wo32(chan, 0x26e4, 0x3f000000);
-	nv_wo32(chan, 0x26ec, 0x40000000);
-	nv_wo32(chan, 0x26f0, 0x3f800000);
-	nv_wo32(chan, 0x26f8, 0xbf800000);
-	nv_wo32(chan, 0x2700, 0xbf800000);
-	nv_wo32(chan, 0x3024, 0x000fe000);
-	nv_wo32(chan, 0x30a0, 0x000003f8);
-	nv_wo32(chan, 0x33fc, 0x002fe000);
-	for (i = 0x341c; i <= 0x3438; i += 4)
-		nv_wo32(chan, i, 0x001c527c);
-	return 0;
-}
-
-static struct nouveau_oclass
-nv2a_graph_cclass = {
-	.handle = NV_ENGCTX(GR, 0x2a),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv2a_graph_context_ctor,
-		.dtor = _nouveau_graph_context_dtor,
-		.init = nv20_graph_context_init,
-		.fini = nv20_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-static int
-nv2a_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv20_graph_priv *priv;
-	int ret;
-
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
-				 NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv20_graph_intr;
-	nv_engine(priv)->cclass = &nv2a_graph_cclass;
-	nv_engine(priv)->sclass = nv25_graph_sclass;
-	nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
-	return 0;
-}
-
-struct nouveau_oclass
-nv2a_graph_oclass = {
-	.handle = NV_ENGINE(GR, 0x2a),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv2a_graph_ctor,
-		.dtor = nv20_graph_dtor,
-		.init = nv20_graph_init,
-		.fini = _nouveau_graph_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv30.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv30.c
deleted file mode 100644
index 2f9dbc709389..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv30.c
+++ /dev/null
@@ -1,237 +0,0 @@
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/graph.h>
-
-#include "nv20.h"
-#include "regs.h"
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv30_graph_sclass[] = {
-	{ 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
-	{ 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
-	{ 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
-	{ 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
-	{ 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
-	{ 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
-	{ 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
-	{ 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
-	{ 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
-	{ 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
-	{ 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
-	{ 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
-	{ 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */
-	{ 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */
-	{ 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */
-	{ 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */
-	{ 0x0397, &nv04_graph_ofuncs, NULL }, /* rankine */
-	{},
-};
-
-/*******************************************************************************
- * PGRAPH context
- ******************************************************************************/
-
-static int
-nv30_graph_context_ctor(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass, void *data, u32 size,
-			struct nouveau_object **pobject)
-{
-	struct nv20_graph_chan *chan;
-	int ret, i;
-
-	ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x5f48,
-					   16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	chan->chid = nouveau_fifo_chan(parent)->chid;
-
-	nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
-	nv_wo32(chan, 0x0410, 0x00000101);
-	nv_wo32(chan, 0x0424, 0x00000111);
-	nv_wo32(chan, 0x0428, 0x00000060);
-	nv_wo32(chan, 0x0444, 0x00000080);
-	nv_wo32(chan, 0x0448, 0xffff0000);
-	nv_wo32(chan, 0x044c, 0x00000001);
-	nv_wo32(chan, 0x0460, 0x44400000);
-	nv_wo32(chan, 0x048c, 0xffff0000);
-	for (i = 0x04e0; i < 0x04e8; i += 4)
-		nv_wo32(chan, i, 0x0fff0000);
-	nv_wo32(chan, 0x04ec, 0x00011100);
-	for (i = 0x0508; i < 0x0548; i += 4)
-		nv_wo32(chan, i, 0x07ff0000);
-	nv_wo32(chan, 0x0550, 0x4b7fffff);
-	nv_wo32(chan, 0x058c, 0x00000080);
-	nv_wo32(chan, 0x0590, 0x30201000);
-	nv_wo32(chan, 0x0594, 0x70605040);
-	nv_wo32(chan, 0x0598, 0xb8a89888);
-	nv_wo32(chan, 0x059c, 0xf8e8d8c8);
-	nv_wo32(chan, 0x05b0, 0xb0000000);
-	for (i = 0x0600; i < 0x0640; i += 4)
-		nv_wo32(chan, i, 0x00010588);
-	for (i = 0x0640; i < 0x0680; i += 4)
-		nv_wo32(chan, i, 0x00030303);
-	for (i = 0x06c0; i < 0x0700; i += 4)
-		nv_wo32(chan, i, 0x0008aae4);
-	for (i = 0x0700; i < 0x0740; i += 4)
-		nv_wo32(chan, i, 0x01012000);
-	for (i = 0x0740; i < 0x0780; i += 4)
-		nv_wo32(chan, i, 0x00080008);
-	nv_wo32(chan, 0x085c, 0x00040000);
-	nv_wo32(chan, 0x0860, 0x00010000);
-	for (i = 0x0864; i < 0x0874; i += 4)
-		nv_wo32(chan, i, 0x00040004);
-	for (i = 0x1f18; i <= 0x3088 ; i += 16) {
-		nv_wo32(chan, i + 0, 0x10700ff9);
-		nv_wo32(chan, i + 1, 0x0436086c);
-		nv_wo32(chan, i + 2, 0x000c001b);
-	}
-	for (i = 0x30b8; i < 0x30c8; i += 4)
-		nv_wo32(chan, i, 0x0000ffff);
-	nv_wo32(chan, 0x344c, 0x3f800000);
-	nv_wo32(chan, 0x3808, 0x3f800000);
-	nv_wo32(chan, 0x381c, 0x3f800000);
-	nv_wo32(chan, 0x3848, 0x40000000);
-	nv_wo32(chan, 0x384c, 0x3f800000);
-	nv_wo32(chan, 0x3850, 0x3f000000);
-	nv_wo32(chan, 0x3858, 0x40000000);
-	nv_wo32(chan, 0x385c, 0x3f800000);
-	nv_wo32(chan, 0x3864, 0xbf800000);
-	nv_wo32(chan, 0x386c, 0xbf800000);
-	return 0;
-}
-
-static struct nouveau_oclass
-nv30_graph_cclass = {
-	.handle = NV_ENGCTX(GR, 0x30),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv30_graph_context_ctor,
-		.dtor = _nouveau_graph_context_dtor,
-		.init = nv20_graph_context_init,
-		.fini = nv20_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-static int
-nv30_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv20_graph_priv *priv;
-	int ret;
-
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
-				 NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv20_graph_intr;
-	nv_engine(priv)->cclass = &nv30_graph_cclass;
-	nv_engine(priv)->sclass = nv30_graph_sclass;
-	nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
-	return 0;
-}
-
-int
-nv30_graph_init(struct nouveau_object *object)
-{
-	struct nouveau_engine *engine = nv_engine(object);
-	struct nv20_graph_priv *priv = (void *)engine;
-	struct nouveau_fb *pfb = nouveau_fb(object);
-	int ret, i;
-
-	ret = nouveau_graph_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4);
-
-	nv_wr32(priv, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
-	nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
-
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0);
-	nv_wr32(priv, 0x400890, 0x01b463ff);
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf2de0475);
-	nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000);
-	nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
-	nv_wr32(priv, 0x400B80, 0x1003d888);
-	nv_wr32(priv, 0x400B84, 0x0c000000);
-	nv_wr32(priv, 0x400098, 0x00000000);
-	nv_wr32(priv, 0x40009C, 0x0005ad00);
-	nv_wr32(priv, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */
-	nv_wr32(priv, 0x4000a0, 0x00000000);
-	nv_wr32(priv, 0x4000a4, 0x00000008);
-	nv_wr32(priv, 0x4008a8, 0xb784a400);
-	nv_wr32(priv, 0x400ba0, 0x002f8685);
-	nv_wr32(priv, 0x400ba4, 0x00231f3f);
-	nv_wr32(priv, 0x4008a4, 0x40000020);
-
-	if (nv_device(priv)->chipset == 0x34) {
-		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
-		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00200201);
-		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
-		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000008);
-		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
-		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000032);
-		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00004);
-		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000002);
-	}
-
-	nv_wr32(priv, 0x4000c0, 0x00000016);
-
-	/* Turn all the tiling regions off. */
-	for (i = 0; i < pfb->tile.regions; i++)
-		engine->tile_prog(engine, i);
-
-	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
-	nv_wr32(priv, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
-	nv_wr32(priv, 0x0040075c             , 0x00000001);
-
-	/* begin RAM config */
-	/* vramsz = pci_resource_len(priv->dev->pdev, 0) - 1; */
-	nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
-	nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
-	if (nv_device(priv)->chipset != 0x34) {
-		nv_wr32(priv, 0x400750, 0x00EA0000);
-		nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100200));
-		nv_wr32(priv, 0x400750, 0x00EA0004);
-		nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100204));
-	}
-	return 0;
-}
-
-struct nouveau_oclass
-nv30_graph_oclass = {
-	.handle = NV_ENGINE(GR, 0x30),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv30_graph_ctor,
-		.dtor = nv20_graph_dtor,
-		.init = nv30_graph_init,
-		.fini = _nouveau_graph_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv34.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv34.c
deleted file mode 100644
index 34dd26c70b64..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv34.c
+++ /dev/null
@@ -1,167 +0,0 @@
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/graph.h>
-
-#include "nv20.h"
-#include "regs.h"
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv34_graph_sclass[] = {
-	{ 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
-	{ 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
-	{ 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
-	{ 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
-	{ 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
-	{ 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
-	{ 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
-	{ 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
-	{ 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
-	{ 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
-	{ 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
-	{ 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
-	{ 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */
-	{ 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */
-	{ 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */
-	{ 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */
-	{ 0x0697, &nv04_graph_ofuncs, NULL }, /* rankine */
-	{},
-};
-
-/*******************************************************************************
- * PGRAPH context
- ******************************************************************************/
-
-static int
-nv34_graph_context_ctor(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass, void *data, u32 size,
-			struct nouveau_object **pobject)
-{
-	struct nv20_graph_chan *chan;
-	int ret, i;
-
-	ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x46dc,
-					   16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	chan->chid = nouveau_fifo_chan(parent)->chid;
-
-	nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
-	nv_wo32(chan, 0x040c, 0x01000101);
-	nv_wo32(chan, 0x0420, 0x00000111);
-	nv_wo32(chan, 0x0424, 0x00000060);
-	nv_wo32(chan, 0x0440, 0x00000080);
-	nv_wo32(chan, 0x0444, 0xffff0000);
-	nv_wo32(chan, 0x0448, 0x00000001);
-	nv_wo32(chan, 0x045c, 0x44400000);
-	nv_wo32(chan, 0x0480, 0xffff0000);
-	for (i = 0x04d4; i < 0x04dc; i += 4)
-		nv_wo32(chan, i, 0x0fff0000);
-	nv_wo32(chan, 0x04e0, 0x00011100);
-	for (i = 0x04fc; i < 0x053c; i += 4)
-		nv_wo32(chan, i, 0x07ff0000);
-	nv_wo32(chan, 0x0544, 0x4b7fffff);
-	nv_wo32(chan, 0x057c, 0x00000080);
-	nv_wo32(chan, 0x0580, 0x30201000);
-	nv_wo32(chan, 0x0584, 0x70605040);
-	nv_wo32(chan, 0x0588, 0xb8a89888);
-	nv_wo32(chan, 0x058c, 0xf8e8d8c8);
-	nv_wo32(chan, 0x05a0, 0xb0000000);
-	for (i = 0x05f0; i < 0x0630; i += 4)
-		nv_wo32(chan, i, 0x00010588);
-	for (i = 0x0630; i < 0x0670; i += 4)
-		nv_wo32(chan, i, 0x00030303);
-	for (i = 0x06b0; i < 0x06f0; i += 4)
-		nv_wo32(chan, i, 0x0008aae4);
-	for (i = 0x06f0; i < 0x0730; i += 4)
-		nv_wo32(chan, i, 0x01012000);
-	for (i = 0x0730; i < 0x0770; i += 4)
-		nv_wo32(chan, i, 0x00080008);
-	nv_wo32(chan, 0x0850, 0x00040000);
-	nv_wo32(chan, 0x0854, 0x00010000);
-	for (i = 0x0858; i < 0x0868; i += 4)
-		nv_wo32(chan, i, 0x00040004);
-	for (i = 0x15ac; i <= 0x271c ; i += 16) {
-		nv_wo32(chan, i + 0, 0x10700ff9);
-		nv_wo32(chan, i + 1, 0x0436086c);
-		nv_wo32(chan, i + 2, 0x000c001b);
-	}
-	for (i = 0x274c; i < 0x275c; i += 4)
-		nv_wo32(chan, i, 0x0000ffff);
-	nv_wo32(chan, 0x2ae0, 0x3f800000);
-	nv_wo32(chan, 0x2e9c, 0x3f800000);
-	nv_wo32(chan, 0x2eb0, 0x3f800000);
-	nv_wo32(chan, 0x2edc, 0x40000000);
-	nv_wo32(chan, 0x2ee0, 0x3f800000);
-	nv_wo32(chan, 0x2ee4, 0x3f000000);
-	nv_wo32(chan, 0x2eec, 0x40000000);
-	nv_wo32(chan, 0x2ef0, 0x3f800000);
-	nv_wo32(chan, 0x2ef8, 0xbf800000);
-	nv_wo32(chan, 0x2f00, 0xbf800000);
-	return 0;
-}
-
-static struct nouveau_oclass
-nv34_graph_cclass = {
-	.handle = NV_ENGCTX(GR, 0x34),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv34_graph_context_ctor,
-		.dtor = _nouveau_graph_context_dtor,
-		.init = nv20_graph_context_init,
-		.fini = nv20_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-static int
-nv34_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv20_graph_priv *priv;
-	int ret;
-
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
-				 NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv20_graph_intr;
-	nv_engine(priv)->cclass = &nv34_graph_cclass;
-	nv_engine(priv)->sclass = nv34_graph_sclass;
-	nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
-	return 0;
-}
-
-struct nouveau_oclass
-nv34_graph_oclass = {
-	.handle = NV_ENGINE(GR, 0x34),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv34_graph_ctor,
-		.dtor = nv20_graph_dtor,
-		.init = nv30_graph_init,
-		.fini = _nouveau_graph_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv35.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv35.c
deleted file mode 100644
index 2fb5756d9f66..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv35.c
+++ /dev/null
@@ -1,165 +0,0 @@
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include "nv20.h"
-#include "regs.h"
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv35_graph_sclass[] = {
-	{ 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
-	{ 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
-	{ 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
-	{ 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
-	{ 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
-	{ 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
-	{ 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
-	{ 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
-	{ 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
-	{ 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
-	{ 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
-	{ 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
-	{ 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */
-	{ 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */
-	{ 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */
-	{ 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */
-	{ 0x0497, &nv04_graph_ofuncs, NULL }, /* rankine */
-	{},
-};
-
-/*******************************************************************************
- * PGRAPH context
- ******************************************************************************/
-
-static int
-nv35_graph_context_ctor(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass, void *data, u32 size,
-			struct nouveau_object **pobject)
-{
-	struct nv20_graph_chan *chan;
-	int ret, i;
-
-	ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x577c,
-					   16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	chan->chid = nouveau_fifo_chan(parent)->chid;
-
-	nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
-	nv_wo32(chan, 0x040c, 0x00000101);
-	nv_wo32(chan, 0x0420, 0x00000111);
-	nv_wo32(chan, 0x0424, 0x00000060);
-	nv_wo32(chan, 0x0440, 0x00000080);
-	nv_wo32(chan, 0x0444, 0xffff0000);
-	nv_wo32(chan, 0x0448, 0x00000001);
-	nv_wo32(chan, 0x045c, 0x44400000);
-	nv_wo32(chan, 0x0488, 0xffff0000);
-	for (i = 0x04dc; i < 0x04e4; i += 4)
-		nv_wo32(chan, i, 0x0fff0000);
-	nv_wo32(chan, 0x04e8, 0x00011100);
-	for (i = 0x0504; i < 0x0544; i += 4)
-		nv_wo32(chan, i, 0x07ff0000);
-	nv_wo32(chan, 0x054c, 0x4b7fffff);
-	nv_wo32(chan, 0x0588, 0x00000080);
-	nv_wo32(chan, 0x058c, 0x30201000);
-	nv_wo32(chan, 0x0590, 0x70605040);
-	nv_wo32(chan, 0x0594, 0xb8a89888);
-	nv_wo32(chan, 0x0598, 0xf8e8d8c8);
-	nv_wo32(chan, 0x05ac, 0xb0000000);
-	for (i = 0x0604; i < 0x0644; i += 4)
-		nv_wo32(chan, i, 0x00010588);
-	for (i = 0x0644; i < 0x0684; i += 4)
-		nv_wo32(chan, i, 0x00030303);
-	for (i = 0x06c4; i < 0x0704; i += 4)
-		nv_wo32(chan, i, 0x0008aae4);
-	for (i = 0x0704; i < 0x0744; i += 4)
-		nv_wo32(chan, i, 0x01012000);
-	for (i = 0x0744; i < 0x0784; i += 4)
-		nv_wo32(chan, i, 0x00080008);
-	nv_wo32(chan, 0x0860, 0x00040000);
-	nv_wo32(chan, 0x0864, 0x00010000);
-	for (i = 0x0868; i < 0x0878; i += 4)
-		nv_wo32(chan, i, 0x00040004);
-	for (i = 0x1f1c; i <= 0x308c ; i += 16) {
-		nv_wo32(chan, i + 0, 0x10700ff9);
-		nv_wo32(chan, i + 4, 0x0436086c);
-		nv_wo32(chan, i + 8, 0x000c001b);
-	}
-	for (i = 0x30bc; i < 0x30cc; i += 4)
-		nv_wo32(chan, i, 0x0000ffff);
-	nv_wo32(chan, 0x3450, 0x3f800000);
-	nv_wo32(chan, 0x380c, 0x3f800000);
-	nv_wo32(chan, 0x3820, 0x3f800000);
-	nv_wo32(chan, 0x384c, 0x40000000);
-	nv_wo32(chan, 0x3850, 0x3f800000);
-	nv_wo32(chan, 0x3854, 0x3f000000);
-	nv_wo32(chan, 0x385c, 0x40000000);
-	nv_wo32(chan, 0x3860, 0x3f800000);
-	nv_wo32(chan, 0x3868, 0xbf800000);
-	nv_wo32(chan, 0x3870, 0xbf800000);
-	return 0;
-}
-
-static struct nouveau_oclass
-nv35_graph_cclass = {
-	.handle = NV_ENGCTX(GR, 0x35),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv35_graph_context_ctor,
-		.dtor = _nouveau_graph_context_dtor,
-		.init = nv20_graph_context_init,
-		.fini = nv20_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-static int
-nv35_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv20_graph_priv *priv;
-	int ret;
-
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
-				 NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv20_graph_intr;
-	nv_engine(priv)->cclass = &nv35_graph_cclass;
-	nv_engine(priv)->sclass = nv35_graph_sclass;
-	nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
-	return 0;
-}
-
-struct nouveau_oclass
-nv35_graph_oclass = {
-	.handle = NV_ENGINE(GR, 0x35),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv35_graph_ctor,
-		.dtor = nv20_graph_dtor,
-		.init = nv30_graph_init,
-		.fini = _nouveau_graph_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
deleted file mode 100644
index 4f401174868d..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
+++ /dev/null
@@ -1,536 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <core/os.h>
-#include <core/handle.h>
-#include <core/engctx.h>
-
-#include <subdev/fb.h>
-#include <subdev/timer.h>
-
-#include <engine/graph.h>
-#include <engine/fifo.h>
-
-#include "nv40.h"
-#include "regs.h"
-
-struct nv40_graph_priv {
-	struct nouveau_graph base;
-	u32 size;
-};
-
-struct nv40_graph_chan {
-	struct nouveau_graph_chan base;
-};
-
-static u64
-nv40_graph_units(struct nouveau_graph *graph)
-{
-	struct nv40_graph_priv *priv = (void *)graph;
-
-	return nv_rd32(priv, 0x1540);
-}
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-static int
-nv40_graph_object_ctor(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, void *data, u32 size,
-		       struct nouveau_object **pobject)
-{
-	struct nouveau_gpuobj *obj;
-	int ret;
-
-	ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
-				    20, 16, 0, &obj);
-	*pobject = nv_object(obj);
-	if (ret)
-		return ret;
-
-	nv_wo32(obj, 0x00, nv_mclass(obj));
-	nv_wo32(obj, 0x04, 0x00000000);
-	nv_wo32(obj, 0x08, 0x00000000);
-#ifdef __BIG_ENDIAN
-	nv_mo32(obj, 0x08, 0x01000000, 0x01000000);
-#endif
-	nv_wo32(obj, 0x0c, 0x00000000);
-	nv_wo32(obj, 0x10, 0x00000000);
-	return 0;
-}
-
-static struct nouveau_ofuncs
-nv40_graph_ofuncs = {
-	.ctor = nv40_graph_object_ctor,
-	.dtor = _nouveau_gpuobj_dtor,
-	.init = _nouveau_gpuobj_init,
-	.fini = _nouveau_gpuobj_fini,
-	.rd32 = _nouveau_gpuobj_rd32,
-	.wr32 = _nouveau_gpuobj_wr32,
-};
-
-static struct nouveau_oclass
-nv40_graph_sclass[] = {
-	{ 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */
-	{ 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */
-	{ 0x0030, &nv40_graph_ofuncs, NULL }, /* null */
-	{ 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */
-	{ 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */
-	{ 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */
-	{ 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */
-	{ 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */
-	{ 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */
-	{ 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */
-	{ 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */
-	{ 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */
-	{ 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */
-	{ 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */
-	{ 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */
-	{ 0x4097, &nv40_graph_ofuncs, NULL }, /* curie */
-	{},
-};
-
-static struct nouveau_oclass
-nv44_graph_sclass[] = {
-	{ 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */
-	{ 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */
-	{ 0x0030, &nv40_graph_ofuncs, NULL }, /* null */
-	{ 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */
-	{ 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */
-	{ 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */
-	{ 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */
-	{ 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */
-	{ 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */
-	{ 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */
-	{ 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */
-	{ 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */
-	{ 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */
-	{ 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */
-	{ 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */
-	{ 0x4497, &nv40_graph_ofuncs, NULL }, /* curie */
-	{},
-};
-
-/*******************************************************************************
- * PGRAPH context
- ******************************************************************************/
-
-static int
-nv40_graph_context_ctor(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass, void *data, u32 size,
-			struct nouveau_object **pobject)
-{
-	struct nv40_graph_priv *priv = (void *)engine;
-	struct nv40_graph_chan *chan;
-	int ret;
-
-	ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
-					   priv->size, 16,
-					   NVOBJ_FLAG_ZERO_ALLOC, &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	nv40_grctx_fill(nv_device(priv), nv_gpuobj(chan));
-	nv_wo32(chan, 0x00000, nv_gpuobj(chan)->addr >> 4);
-	return 0;
-}
-
-static int
-nv40_graph_context_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv40_graph_priv *priv = (void *)object->engine;
-	struct nv40_graph_chan *chan = (void *)object;
-	u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4;
-	int ret = 0;
-
-	nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
-
-	if (nv_rd32(priv, 0x40032c) == inst) {
-		if (suspend) {
-			nv_wr32(priv, 0x400720, 0x00000000);
-			nv_wr32(priv, 0x400784, inst);
-			nv_mask(priv, 0x400310, 0x00000020, 0x00000020);
-			nv_mask(priv, 0x400304, 0x00000001, 0x00000001);
-			if (!nv_wait(priv, 0x400300, 0x00000001, 0x00000000)) {
-				u32 insn = nv_rd32(priv, 0x400308);
-				nv_warn(priv, "ctxprog timeout 0x%08x\n", insn);
-				ret = -EBUSY;
-			}
-		}
-
-		nv_mask(priv, 0x40032c, 0x01000000, 0x00000000);
-	}
-
-	if (nv_rd32(priv, 0x400330) == inst)
-		nv_mask(priv, 0x400330, 0x01000000, 0x00000000);
-
-	nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
-	return ret;
-}
-
-static struct nouveau_oclass
-nv40_graph_cclass = {
-	.handle = NV_ENGCTX(GR, 0x40),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv40_graph_context_ctor,
-		.dtor = _nouveau_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = nv40_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-static void
-nv40_graph_tile_prog(struct nouveau_engine *engine, int i)
-{
-	struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
-	struct nouveau_fifo *pfifo = nouveau_fifo(engine);
-	struct nv40_graph_priv *priv = (void *)engine;
-	unsigned long flags;
-
-	pfifo->pause(pfifo, &flags);
-	nv04_graph_idle(priv);
-
-	switch (nv_device(priv)->chipset) {
-	case 0x40:
-	case 0x41:
-	case 0x42:
-	case 0x43:
-	case 0x45:
-	case 0x4e:
-		nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
-		nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
-		nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
-		nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);
-		nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);
-		nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);
-		switch (nv_device(priv)->chipset) {
-		case 0x40:
-		case 0x45:
-			nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
-			nv_wr32(priv, NV40_PGRAPH_ZCOMP1(i), tile->zcomp);
-			break;
-		case 0x41:
-		case 0x42:
-		case 0x43:
-			nv_wr32(priv, NV41_PGRAPH_ZCOMP0(i), tile->zcomp);
-			nv_wr32(priv, NV41_PGRAPH_ZCOMP1(i), tile->zcomp);
-			break;
-		default:
-			break;
-		}
-		break;
-	case 0x44:
-	case 0x4a:
-		nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
-		nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
-		nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
-		break;
-	case 0x46:
-	case 0x4c:
-	case 0x47:
-	case 0x49:
-	case 0x4b:
-	case 0x63:
-	case 0x67:
-	case 0x68:
-		nv_wr32(priv, NV47_PGRAPH_TSIZE(i), tile->pitch);
-		nv_wr32(priv, NV47_PGRAPH_TLIMIT(i), tile->limit);
-		nv_wr32(priv, NV47_PGRAPH_TILE(i), tile->addr);
-		nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);
-		nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);
-		nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);
-		switch (nv_device(priv)->chipset) {
-		case 0x47:
-		case 0x49:
-		case 0x4b:
-			nv_wr32(priv, NV47_PGRAPH_ZCOMP0(i), tile->zcomp);
-			nv_wr32(priv, NV47_PGRAPH_ZCOMP1(i), tile->zcomp);
-			break;
-		default:
-			break;
-		}
-		break;
-	default:
-		break;
-	}
-
-	pfifo->start(pfifo, &flags);
-}
-
-static void
-nv40_graph_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
-	struct nouveau_engine *engine = nv_engine(subdev);
-	struct nouveau_object *engctx;
-	struct nouveau_handle *handle = NULL;
-	struct nv40_graph_priv *priv = (void *)subdev;
-	u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
-	u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
-	u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
-	u32 inst = nv_rd32(priv, 0x40032c) & 0x000fffff;
-	u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
-	u32 subc = (addr & 0x00070000) >> 16;
-	u32 mthd = (addr & 0x00001ffc);
-	u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
-	u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xffff;
-	u32 show = stat;
-	int chid;
-
-	engctx = nouveau_engctx_get(engine, inst);
-	chid   = pfifo->chid(pfifo, engctx);
-
-	if (stat & NV_PGRAPH_INTR_ERROR) {
-		if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
-			handle = nouveau_handle_get_class(engctx, class);
-			if (handle && !nv_call(handle->object, mthd, data))
-				show &= ~NV_PGRAPH_INTR_ERROR;
-			nouveau_handle_put(handle);
-		}
-
-		if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
-			nv_mask(priv, 0x402000, 0, 0);
-		}
-	}
-
-	nv_wr32(priv, NV03_PGRAPH_INTR, stat);
-	nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
-
-	if (show) {
-		nv_error(priv, "%s", "");
-		nouveau_bitfield_print(nv10_graph_intr_name, show);
-		pr_cont(" nsource:");
-		nouveau_bitfield_print(nv04_graph_nsource, nsource);
-		pr_cont(" nstatus:");
-		nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
-		pr_cont("\n");
-		nv_error(priv,
-			 "ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
-			 chid, inst << 4, nouveau_client_name(engctx), subc,
-			 class, mthd, data);
-	}
-
-	nouveau_engctx_put(engctx);
-}
-
-static int
-nv40_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv40_graph_priv *priv;
-	int ret;
-
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv40_graph_intr;
-	nv_engine(priv)->cclass = &nv40_graph_cclass;
-	if (nv44_graph_class(priv))
-		nv_engine(priv)->sclass = nv44_graph_sclass;
-	else
-		nv_engine(priv)->sclass = nv40_graph_sclass;
-	nv_engine(priv)->tile_prog = nv40_graph_tile_prog;
-
-	priv->base.units = nv40_graph_units;
-	return 0;
-}
-
-static int
-nv40_graph_init(struct nouveau_object *object)
-{
-	struct nouveau_engine *engine = nv_engine(object);
-	struct nouveau_fb *pfb = nouveau_fb(object);
-	struct nv40_graph_priv *priv = (void *)engine;
-	int ret, i, j;
-	u32 vramsz;
-
-	ret = nouveau_graph_init(&priv->base);
-	if (ret)
-		return ret;
-
-	/* generate and upload context program */
-	ret = nv40_grctx_init(nv_device(priv), &priv->size);
-	if (ret)
-		return ret;
-
-	/* No context present currently */
-	nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
-
-	nv_wr32(priv, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
-	nv_wr32(priv, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
-
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0);
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
-	nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000);
-	nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
-
-	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
-	nv_wr32(priv, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
-
-	j = nv_rd32(priv, 0x1540) & 0xff;
-	if (j) {
-		for (i = 0; !(j & 1); j >>= 1, i++)
-			;
-		nv_wr32(priv, 0x405000, i);
-	}
-
-	if (nv_device(priv)->chipset == 0x40) {
-		nv_wr32(priv, 0x4009b0, 0x83280fff);
-		nv_wr32(priv, 0x4009b4, 0x000000a0);
-	} else {
-		nv_wr32(priv, 0x400820, 0x83280eff);
-		nv_wr32(priv, 0x400824, 0x000000a0);
-	}
-
-	switch (nv_device(priv)->chipset) {
-	case 0x40:
-	case 0x45:
-		nv_wr32(priv, 0x4009b8, 0x0078e366);
-		nv_wr32(priv, 0x4009bc, 0x0000014c);
-		break;
-	case 0x41:
-	case 0x42: /* pciid also 0x00Cx */
-	/* case 0x0120: XXX (pciid) */
-		nv_wr32(priv, 0x400828, 0x007596ff);
-		nv_wr32(priv, 0x40082c, 0x00000108);
-		break;
-	case 0x43:
-		nv_wr32(priv, 0x400828, 0x0072cb77);
-		nv_wr32(priv, 0x40082c, 0x00000108);
-		break;
-	case 0x44:
-	case 0x46: /* G72 */
-	case 0x4a:
-	case 0x4c: /* G7x-based C51 */
-	case 0x4e:
-		nv_wr32(priv, 0x400860, 0);
-		nv_wr32(priv, 0x400864, 0);
-		break;
-	case 0x47: /* G70 */
-	case 0x49: /* G71 */
-	case 0x4b: /* G73 */
-		nv_wr32(priv, 0x400828, 0x07830610);
-		nv_wr32(priv, 0x40082c, 0x0000016A);
-		break;
-	default:
-		break;
-	}
-
-	nv_wr32(priv, 0x400b38, 0x2ffff800);
-	nv_wr32(priv, 0x400b3c, 0x00006000);
-
-	/* Tiling related stuff. */
-	switch (nv_device(priv)->chipset) {
-	case 0x44:
-	case 0x4a:
-		nv_wr32(priv, 0x400bc4, 0x1003d888);
-		nv_wr32(priv, 0x400bbc, 0xb7a7b500);
-		break;
-	case 0x46:
-		nv_wr32(priv, 0x400bc4, 0x0000e024);
-		nv_wr32(priv, 0x400bbc, 0xb7a7b520);
-		break;
-	case 0x4c:
-	case 0x4e:
-	case 0x67:
-		nv_wr32(priv, 0x400bc4, 0x1003d888);
-		nv_wr32(priv, 0x400bbc, 0xb7a7b540);
-		break;
-	default:
-		break;
-	}
-
-	/* Turn all the tiling regions off. */
-	for (i = 0; i < pfb->tile.regions; i++)
-		engine->tile_prog(engine, i);
-
-	/* begin RAM config */
-	vramsz = nv_device_resource_len(nv_device(priv), 0) - 1;
-	switch (nv_device(priv)->chipset) {
-	case 0x40:
-		nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
-		nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
-		nv_wr32(priv, 0x4069A4, nv_rd32(priv, 0x100200));
-		nv_wr32(priv, 0x4069A8, nv_rd32(priv, 0x100204));
-		nv_wr32(priv, 0x400820, 0);
-		nv_wr32(priv, 0x400824, 0);
-		nv_wr32(priv, 0x400864, vramsz);
-		nv_wr32(priv, 0x400868, vramsz);
-		break;
-	default:
-		switch (nv_device(priv)->chipset) {
-		case 0x41:
-		case 0x42:
-		case 0x43:
-		case 0x45:
-		case 0x4e:
-		case 0x44:
-		case 0x4a:
-			nv_wr32(priv, 0x4009F0, nv_rd32(priv, 0x100200));
-			nv_wr32(priv, 0x4009F4, nv_rd32(priv, 0x100204));
-			break;
-		default:
-			nv_wr32(priv, 0x400DF0, nv_rd32(priv, 0x100200));
-			nv_wr32(priv, 0x400DF4, nv_rd32(priv, 0x100204));
-			break;
-		}
-		nv_wr32(priv, 0x4069F0, nv_rd32(priv, 0x100200));
-		nv_wr32(priv, 0x4069F4, nv_rd32(priv, 0x100204));
-		nv_wr32(priv, 0x400840, 0);
-		nv_wr32(priv, 0x400844, 0);
-		nv_wr32(priv, 0x4008A0, vramsz);
-		nv_wr32(priv, 0x4008A4, vramsz);
-		break;
-	}
-
-	return 0;
-}
-
-struct nouveau_oclass
-nv40_graph_oclass = {
-	.handle = NV_ENGINE(GR, 0x40),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv40_graph_ctor,
-		.dtor = _nouveau_graph_dtor,
-		.init = nv40_graph_init,
-		.fini = _nouveau_graph_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h
deleted file mode 100644
index ad8209377529..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef __NV40_GRAPH_H__
-#define __NV40_GRAPH_H__
-
-#include <core/device.h>
-#include <core/gpuobj.h>
-
-/* returns 1 if device is one of the nv4x using the 0x4497 object class,
- * helpful to determine a number of other hardware features
- */
-static inline int
-nv44_graph_class(void *priv)
-{
-	struct nouveau_device *device = nv_device(priv);
-
-	if ((device->chipset & 0xf0) == 0x60)
-		return 1;
-
-	return !(0x0baf & (1 << (device->chipset & 0x0f)));
-}
-
-int  nv40_grctx_init(struct nouveau_device *, u32 *size);
-void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
deleted file mode 100644
index 38e0aa26f1cd..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
+++ /dev/null
@@ -1,1009 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/os.h>
-#include <core/client.h>
-#include <core/handle.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-#include <subdev/fb.h>
-#include <subdev/vm.h>
-#include <subdev/timer.h>
-
-#include <engine/fifo.h>
-#include <engine/graph.h>
-
-#include "nv50.h"
-
-struct nv50_graph_priv {
-	struct nouveau_graph base;
-	spinlock_t lock;
-	u32 size;
-};
-
-struct nv50_graph_chan {
-	struct nouveau_graph_chan base;
-};
-
-static u64
-nv50_graph_units(struct nouveau_graph *graph)
-{
-	struct nv50_graph_priv *priv = (void *)graph;
-
-	return nv_rd32(priv, 0x1540);
-}
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-static int
-nv50_graph_object_ctor(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, void *data, u32 size,
-		       struct nouveau_object **pobject)
-{
-	struct nouveau_gpuobj *obj;
-	int ret;
-
-	ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
-				    16, 16, 0, &obj);
-	*pobject = nv_object(obj);
-	if (ret)
-		return ret;
-
-	nv_wo32(obj, 0x00, nv_mclass(obj));
-	nv_wo32(obj, 0x04, 0x00000000);
-	nv_wo32(obj, 0x08, 0x00000000);
-	nv_wo32(obj, 0x0c, 0x00000000);
-	return 0;
-}
-
-static struct nouveau_ofuncs
-nv50_graph_ofuncs = {
-	.ctor = nv50_graph_object_ctor,
-	.dtor = _nouveau_gpuobj_dtor,
-	.init = _nouveau_gpuobj_init,
-	.fini = _nouveau_gpuobj_fini,
-	.rd32 = _nouveau_gpuobj_rd32,
-	.wr32 = _nouveau_gpuobj_wr32,
-};
-
-static struct nouveau_oclass
-nv50_graph_sclass[] = {
-	{ 0x0030, &nv50_graph_ofuncs },
-	{ 0x502d, &nv50_graph_ofuncs },
-	{ 0x5039, &nv50_graph_ofuncs },
-	{ 0x5097, &nv50_graph_ofuncs },
-	{ 0x50c0, &nv50_graph_ofuncs },
-	{}
-};
-
-static struct nouveau_oclass
-nv84_graph_sclass[] = {
-	{ 0x0030, &nv50_graph_ofuncs },
-	{ 0x502d, &nv50_graph_ofuncs },
-	{ 0x5039, &nv50_graph_ofuncs },
-	{ 0x50c0, &nv50_graph_ofuncs },
-	{ 0x8297, &nv50_graph_ofuncs },
-	{}
-};
-
-static struct nouveau_oclass
-nva0_graph_sclass[] = {
-	{ 0x0030, &nv50_graph_ofuncs },
-	{ 0x502d, &nv50_graph_ofuncs },
-	{ 0x5039, &nv50_graph_ofuncs },
-	{ 0x50c0, &nv50_graph_ofuncs },
-	{ 0x8397, &nv50_graph_ofuncs },
-	{}
-};
-
-static struct nouveau_oclass
-nva3_graph_sclass[] = {
-	{ 0x0030, &nv50_graph_ofuncs },
-	{ 0x502d, &nv50_graph_ofuncs },
-	{ 0x5039, &nv50_graph_ofuncs },
-	{ 0x50c0, &nv50_graph_ofuncs },
-	{ 0x8597, &nv50_graph_ofuncs },
-	{ 0x85c0, &nv50_graph_ofuncs },
-	{}
-};
-
-static struct nouveau_oclass
-nvaf_graph_sclass[] = {
-	{ 0x0030, &nv50_graph_ofuncs },
-	{ 0x502d, &nv50_graph_ofuncs },
-	{ 0x5039, &nv50_graph_ofuncs },
-	{ 0x50c0, &nv50_graph_ofuncs },
-	{ 0x85c0, &nv50_graph_ofuncs },
-	{ 0x8697, &nv50_graph_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH context
- ******************************************************************************/
-
-static int
-nv50_graph_context_ctor(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass, void *data, u32 size,
-			struct nouveau_object **pobject)
-{
-	struct nv50_graph_priv *priv = (void *)engine;
-	struct nv50_graph_chan *chan;
-	int ret;
-
-	ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
-					   priv->size, 0,
-					   NVOBJ_FLAG_ZERO_ALLOC, &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	nv50_grctx_fill(nv_device(priv), nv_gpuobj(chan));
-	return 0;
-}
-
-static struct nouveau_oclass
-nv50_graph_cclass = {
-	.handle = NV_ENGCTX(GR, 0x50),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_graph_context_ctor,
-		.dtor = _nouveau_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-static const struct nouveau_bitfield nv50_pgraph_status[] = {
-	{ 0x00000001, "BUSY" }, /* set when any bit is set */
-	{ 0x00000002, "DISPATCH" },
-	{ 0x00000004, "UNK2" },
-	{ 0x00000008, "UNK3" },
-	{ 0x00000010, "UNK4" },
-	{ 0x00000020, "UNK5" },
-	{ 0x00000040, "M2MF" },
-	{ 0x00000080, "UNK7" },
-	{ 0x00000100, "CTXPROG" },
-	{ 0x00000200, "VFETCH" },
-	{ 0x00000400, "CCACHE_PREGEOM" },
-	{ 0x00000800, "STRMOUT_VATTR_POSTGEOM" },
-	{ 0x00001000, "VCLIP" },
-	{ 0x00002000, "RATTR_APLANE" },
-	{ 0x00004000, "TRAST" },
-	{ 0x00008000, "CLIPID" },
-	{ 0x00010000, "ZCULL" },
-	{ 0x00020000, "ENG2D" },
-	{ 0x00040000, "RMASK" },
-	{ 0x00080000, "TPC_RAST" },
-	{ 0x00100000, "TPC_PROP" },
-	{ 0x00200000, "TPC_TEX" },
-	{ 0x00400000, "TPC_GEOM" },
-	{ 0x00800000, "TPC_MP" },
-	{ 0x01000000, "ROP" },
-	{}
-};
-
-static const char *const nv50_pgraph_vstatus_0[] = {
-	"VFETCH", "CCACHE", "PREGEOM", "POSTGEOM", "VATTR", "STRMOUT", "VCLIP",
-	NULL
-};
-
-static const char *const nv50_pgraph_vstatus_1[] = {
-	"TPC_RAST", "TPC_PROP", "TPC_TEX", "TPC_GEOM", "TPC_MP", NULL
-};
-
-static const char *const nv50_pgraph_vstatus_2[] = {
-	"RATTR", "APLANE", "TRAST", "CLIPID", "ZCULL", "ENG2D", "RMASK",
-	"ROP", NULL
-};
-
-static void nouveau_pgraph_vstatus_print(struct nv50_graph_priv *priv, int r,
-		const char *const units[], u32 status)
-{
-	int i;
-
-	nv_error(priv, "PGRAPH_VSTATUS%d: 0x%08x", r, status);
-
-	for (i = 0; units[i] && status; i++) {
-		if ((status & 7) == 1)
-			pr_cont(" %s", units[i]);
-		status >>= 3;
-	}
-	if (status)
-		pr_cont(" (invalid: 0x%x)", status);
-	pr_cont("\n");
-}
-
-static int
-nv84_graph_tlb_flush(struct nouveau_engine *engine)
-{
-	struct nouveau_timer *ptimer = nouveau_timer(engine);
-	struct nv50_graph_priv *priv = (void *)engine;
-	bool idle, timeout = false;
-	unsigned long flags;
-	u64 start;
-	u32 tmp;
-
-	spin_lock_irqsave(&priv->lock, flags);
-	nv_mask(priv, 0x400500, 0x00000001, 0x00000000);
-
-	start = ptimer->read(ptimer);
-	do {
-		idle = true;
-
-		for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) {
-			if ((tmp & 7) == 1)
-				idle = false;
-		}
-
-		for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) {
-			if ((tmp & 7) == 1)
-				idle = false;
-		}
-
-		for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) {
-			if ((tmp & 7) == 1)
-				idle = false;
-		}
-	} while (!idle &&
-		 !(timeout = ptimer->read(ptimer) - start > 2000000000));
-
-	if (timeout) {
-		nv_error(priv, "PGRAPH TLB flush idle timeout fail\n");
-
-		tmp = nv_rd32(priv, 0x400700);
-		nv_error(priv, "PGRAPH_STATUS  : 0x%08x", tmp);
-		nouveau_bitfield_print(nv50_pgraph_status, tmp);
-		pr_cont("\n");
-
-		nouveau_pgraph_vstatus_print(priv, 0, nv50_pgraph_vstatus_0,
-				nv_rd32(priv, 0x400380));
-		nouveau_pgraph_vstatus_print(priv, 1, nv50_pgraph_vstatus_1,
-				nv_rd32(priv, 0x400384));
-		nouveau_pgraph_vstatus_print(priv, 2, nv50_pgraph_vstatus_2,
-				nv_rd32(priv, 0x400388));
-	}
-
-
-	nv_wr32(priv, 0x100c80, 0x00000001);
-	if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000))
-		nv_error(priv, "vm flush timeout\n");
-	nv_mask(priv, 0x400500, 0x00000001, 0x00000001);
-	spin_unlock_irqrestore(&priv->lock, flags);
-	return timeout ? -EBUSY : 0;
-}
-
-static const struct nouveau_bitfield nv50_mp_exec_errors[] = {
-	{ 0x01, "STACK_UNDERFLOW" },
-	{ 0x02, "STACK_MISMATCH" },
-	{ 0x04, "QUADON_ACTIVE" },
-	{ 0x08, "TIMEOUT" },
-	{ 0x10, "INVALID_OPCODE" },
-	{ 0x20, "PM_OVERFLOW" },
-	{ 0x40, "BREAKPOINT" },
-	{}
-};
-
-static const struct nouveau_bitfield nv50_mpc_traps[] = {
-	{ 0x0000001, "LOCAL_LIMIT_READ" },
-	{ 0x0000010, "LOCAL_LIMIT_WRITE" },
-	{ 0x0000040, "STACK_LIMIT" },
-	{ 0x0000100, "GLOBAL_LIMIT_READ" },
-	{ 0x0001000, "GLOBAL_LIMIT_WRITE" },
-	{ 0x0010000, "MP0" },
-	{ 0x0020000, "MP1" },
-	{ 0x0040000, "GLOBAL_LIMIT_RED" },
-	{ 0x0400000, "GLOBAL_LIMIT_ATOM" },
-	{ 0x4000000, "MP2" },
-	{}
-};
-
-static const struct nouveau_bitfield nv50_tex_traps[] = {
-	{ 0x00000001, "" }, /* any bit set? */
-	{ 0x00000002, "FAULT" },
-	{ 0x00000004, "STORAGE_TYPE_MISMATCH" },
-	{ 0x00000008, "LINEAR_MISMATCH" },
-	{ 0x00000020, "WRONG_MEMTYPE" },
-	{}
-};
-
-static const struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
-	{ 0x00000001, "NOTIFY" },
-	{ 0x00000002, "IN" },
-	{ 0x00000004, "OUT" },
-	{}
-};
-
-static const struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
-	{ 0x00000001, "FAULT" },
-	{}
-};
-
-static const struct nouveau_bitfield nv50_graph_trap_strmout[] = {
-	{ 0x00000001, "FAULT" },
-	{}
-};
-
-static const struct nouveau_bitfield nv50_graph_trap_ccache[] = {
-	{ 0x00000001, "FAULT" },
-	{}
-};
-
-/* There must be a *lot* of these. Will take some time to gather them up. */
-const struct nouveau_enum nv50_data_error_names[] = {
-	{ 0x00000003, "INVALID_OPERATION", NULL },
-	{ 0x00000004, "INVALID_VALUE", NULL },
-	{ 0x00000005, "INVALID_ENUM", NULL },
-	{ 0x00000008, "INVALID_OBJECT", NULL },
-	{ 0x00000009, "READ_ONLY_OBJECT", NULL },
-	{ 0x0000000a, "SUPERVISOR_OBJECT", NULL },
-	{ 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
-	{ 0x0000000c, "INVALID_BITFIELD", NULL },
-	{ 0x0000000d, "BEGIN_END_ACTIVE", NULL },
-	{ 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
-	{ 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
-	{ 0x00000010, "RT_DOUBLE_BIND", NULL },
-	{ 0x00000011, "RT_TYPES_MISMATCH", NULL },
-	{ 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
-	{ 0x00000015, "FP_TOO_FEW_REGS", NULL },
-	{ 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
-	{ 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
-	{ 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
-	{ 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
-	{ 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
-	{ 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
-	{ 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
-	{ 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
-	{ 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
-	{ 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
-	{ 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
-	{ 0x00000024, "VP_ZERO_INPUTS", NULL },
-	{ 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
-	{ 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
-	{ 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
-	{ 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
-	{ 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
-	{ 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
-	{ 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
-	{ 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
-	{ 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
-	{ 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
-	{ 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
-	{ 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
-	{ 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
-	{ 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
-	{ 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
-	{}
-};
-
-static const struct nouveau_bitfield nv50_graph_intr_name[] = {
-	{ 0x00000001, "NOTIFY" },
-	{ 0x00000002, "COMPUTE_QUERY" },
-	{ 0x00000010, "ILLEGAL_MTHD" },
-	{ 0x00000020, "ILLEGAL_CLASS" },
-	{ 0x00000040, "DOUBLE_NOTIFY" },
-	{ 0x00001000, "CONTEXT_SWITCH" },
-	{ 0x00010000, "BUFFER_NOTIFY" },
-	{ 0x00100000, "DATA_ERROR" },
-	{ 0x00200000, "TRAP" },
-	{ 0x01000000, "SINGLE_STEP" },
-	{}
-};
-
-static const struct nouveau_bitfield nv50_graph_trap_prop[] = {
-	{ 0x00000004, "SURF_WIDTH_OVERRUN" },
-	{ 0x00000008, "SURF_HEIGHT_OVERRUN" },
-	{ 0x00000010, "DST2D_FAULT" },
-	{ 0x00000020, "ZETA_FAULT" },
-	{ 0x00000040, "RT_FAULT" },
-	{ 0x00000080, "CUDA_FAULT" },
-	{ 0x00000100, "DST2D_STORAGE_TYPE_MISMATCH" },
-	{ 0x00000200, "ZETA_STORAGE_TYPE_MISMATCH" },
-	{ 0x00000400, "RT_STORAGE_TYPE_MISMATCH" },
-	{ 0x00000800, "DST2D_LINEAR_MISMATCH" },
-	{ 0x00001000, "RT_LINEAR_MISMATCH" },
-	{}
-};
-
-static void
-nv50_priv_prop_trap(struct nv50_graph_priv *priv,
-		    u32 ustatus_addr, u32 ustatus, u32 tp)
-{
-	u32 e0c = nv_rd32(priv, ustatus_addr + 0x04);
-	u32 e10 = nv_rd32(priv, ustatus_addr + 0x08);
-	u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c);
-	u32 e18 = nv_rd32(priv, ustatus_addr + 0x10);
-	u32 e1c = nv_rd32(priv, ustatus_addr + 0x14);
-	u32 e20 = nv_rd32(priv, ustatus_addr + 0x18);
-	u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c);
-
-	/* CUDA memory: l[], g[] or stack. */
-	if (ustatus & 0x00000080) {
-		if (e18 & 0x80000000) {
-			/* g[] read fault? */
-			nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n",
-					 tp, e14, e10 | ((e18 >> 24) & 0x1f));
-			e18 &= ~0x1f000000;
-		} else if (e18 & 0xc) {
-			/* g[] write fault? */
-			nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n",
-				 tp, e14, e10 | ((e18 >> 7) & 0x1f));
-			e18 &= ~0x00000f80;
-		} else {
-			nv_error(priv, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n",
-				 tp, e14, e10);
-		}
-		ustatus &= ~0x00000080;
-	}
-	if (ustatus) {
-		nv_error(priv, "TRAP_PROP - TP %d -", tp);
-		nouveau_bitfield_print(nv50_graph_trap_prop, ustatus);
-		pr_cont(" - Address %02x%08x\n", e14, e10);
-	}
-	nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
-		 tp, e0c, e18, e1c, e20, e24);
-}
-
-static void
-nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display)
-{
-	u32 units = nv_rd32(priv, 0x1540);
-	u32 addr, mp10, status, pc, oplow, ophigh;
-	int i;
-	int mps = 0;
-	for (i = 0; i < 4; i++) {
-		if (!(units & 1 << (i+24)))
-			continue;
-		if (nv_device(priv)->chipset < 0xa0)
-			addr = 0x408200 + (tpid << 12) + (i << 7);
-		else
-			addr = 0x408100 + (tpid << 11) + (i << 7);
-		mp10 = nv_rd32(priv, addr + 0x10);
-		status = nv_rd32(priv, addr + 0x14);
-		if (!status)
-			continue;
-		if (display) {
-			nv_rd32(priv, addr + 0x20);
-			pc = nv_rd32(priv, addr + 0x24);
-			oplow = nv_rd32(priv, addr + 0x70);
-			ophigh = nv_rd32(priv, addr + 0x74);
-			nv_error(priv, "TRAP_MP_EXEC - "
-					"TP %d MP %d:", tpid, i);
-			nouveau_bitfield_print(nv50_mp_exec_errors, status);
-			pr_cont(" at %06x warp %d, opcode %08x %08x\n",
-					pc&0xffffff, pc >> 24,
-					oplow, ophigh);
-		}
-		nv_wr32(priv, addr + 0x10, mp10);
-		nv_wr32(priv, addr + 0x14, 0);
-		mps++;
-	}
-	if (!mps && display)
-		nv_error(priv, "TRAP_MP_EXEC - TP %d: "
-				"No MPs claiming errors?\n", tpid);
-}
-
-static void
-nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
-		u32 ustatus_new, int display, const char *name)
-{
-	int tps = 0;
-	u32 units = nv_rd32(priv, 0x1540);
-	int i, r;
-	u32 ustatus_addr, ustatus;
-	for (i = 0; i < 16; i++) {
-		if (!(units & (1 << i)))
-			continue;
-		if (nv_device(priv)->chipset < 0xa0)
-			ustatus_addr = ustatus_old + (i << 12);
-		else
-			ustatus_addr = ustatus_new + (i << 11);
-		ustatus = nv_rd32(priv, ustatus_addr) & 0x7fffffff;
-		if (!ustatus)
-			continue;
-		tps++;
-		switch (type) {
-		case 6: /* texture error... unknown for now */
-			if (display) {
-				nv_error(priv, "magic set %d:\n", i);
-				for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
-					nv_error(priv, "\t0x%08x: 0x%08x\n", r,
-						nv_rd32(priv, r));
-				if (ustatus) {
-					nv_error(priv, "%s - TP%d:", name, i);
-					nouveau_bitfield_print(nv50_tex_traps,
-							       ustatus);
-					pr_cont("\n");
-					ustatus = 0;
-				}
-			}
-			break;
-		case 7: /* MP error */
-			if (ustatus & 0x04030000) {
-				nv50_priv_mp_trap(priv, i, display);
-				ustatus &= ~0x04030000;
-			}
-			if (ustatus && display) {
-				nv_error(priv, "%s - TP%d:", name, i);
-				nouveau_bitfield_print(nv50_mpc_traps, ustatus);
-				pr_cont("\n");
-				ustatus = 0;
-			}
-			break;
-		case 8: /* PROP error */
-			if (display)
-				nv50_priv_prop_trap(
-						priv, ustatus_addr, ustatus, i);
-			ustatus = 0;
-			break;
-		}
-		if (ustatus) {
-			if (display)
-				nv_error(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
-		}
-		nv_wr32(priv, ustatus_addr, 0xc0000000);
-	}
-
-	if (!tps && display)
-		nv_warn(priv, "%s - No TPs claiming errors?\n", name);
-}
-
-static int
-nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
-			int chid, u64 inst, struct nouveau_object *engctx)
-{
-	u32 status = nv_rd32(priv, 0x400108);
-	u32 ustatus;
-
-	if (!status && display) {
-		nv_error(priv, "TRAP: no units reporting traps?\n");
-		return 1;
-	}
-
-	/* DISPATCH: Relays commands to other units and handles NOTIFY,
-	 * COND, QUERY. If you get a trap from it, the command is still stuck
-	 * in DISPATCH and you need to do something about it. */
-	if (status & 0x001) {
-		ustatus = nv_rd32(priv, 0x400804) & 0x7fffffff;
-		if (!ustatus && display) {
-			nv_error(priv, "TRAP_DISPATCH - no ustatus?\n");
-		}
-
-		nv_wr32(priv, 0x400500, 0x00000000);
-
-		/* Known to be triggered by screwed up NOTIFY and COND... */
-		if (ustatus & 0x00000001) {
-			u32 addr = nv_rd32(priv, 0x400808);
-			u32 subc = (addr & 0x00070000) >> 16;
-			u32 mthd = (addr & 0x00001ffc);
-			u32 datal = nv_rd32(priv, 0x40080c);
-			u32 datah = nv_rd32(priv, 0x400810);
-			u32 class = nv_rd32(priv, 0x400814);
-			u32 r848 = nv_rd32(priv, 0x400848);
-
-			nv_error(priv, "TRAP DISPATCH_FAULT\n");
-			if (display && (addr & 0x80000000)) {
-				nv_error(priv,
-					 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n",
-					 chid, inst,
-					 nouveau_client_name(engctx), subc,
-					 class, mthd, datah, datal, addr, r848);
-			} else
-			if (display) {
-				nv_error(priv, "no stuck command?\n");
-			}
-
-			nv_wr32(priv, 0x400808, 0);
-			nv_wr32(priv, 0x4008e8, nv_rd32(priv, 0x4008e8) & 3);
-			nv_wr32(priv, 0x400848, 0);
-			ustatus &= ~0x00000001;
-		}
-
-		if (ustatus & 0x00000002) {
-			u32 addr = nv_rd32(priv, 0x40084c);
-			u32 subc = (addr & 0x00070000) >> 16;
-			u32 mthd = (addr & 0x00001ffc);
-			u32 data = nv_rd32(priv, 0x40085c);
-			u32 class = nv_rd32(priv, 0x400814);
-
-			nv_error(priv, "TRAP DISPATCH_QUERY\n");
-			if (display && (addr & 0x80000000)) {
-				nv_error(priv,
-					 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n",
-					 chid, inst,
-					 nouveau_client_name(engctx), subc,
-					 class, mthd, data, addr);
-			} else
-			if (display) {
-				nv_error(priv, "no stuck command?\n");
-			}
-
-			nv_wr32(priv, 0x40084c, 0);
-			ustatus &= ~0x00000002;
-		}
-
-		if (ustatus && display) {
-			nv_error(priv, "TRAP_DISPATCH (unknown "
-				      "0x%08x)\n", ustatus);
-		}
-
-		nv_wr32(priv, 0x400804, 0xc0000000);
-		nv_wr32(priv, 0x400108, 0x001);
-		status &= ~0x001;
-		if (!status)
-			return 0;
-	}
-
-	/* M2MF: Memory to memory copy engine. */
-	if (status & 0x002) {
-		u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff;
-		if (display) {
-			nv_error(priv, "TRAP_M2MF");
-			nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
-			pr_cont("\n");
-			nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n",
-				nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808),
-				nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810));
-
-		}
-
-		/* No sane way found yet -- just reset the bugger. */
-		nv_wr32(priv, 0x400040, 2);
-		nv_wr32(priv, 0x400040, 0);
-		nv_wr32(priv, 0x406800, 0xc0000000);
-		nv_wr32(priv, 0x400108, 0x002);
-		status &= ~0x002;
-	}
-
-	/* VFETCH: Fetches data from vertex buffers. */
-	if (status & 0x004) {
-		u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff;
-		if (display) {
-			nv_error(priv, "TRAP_VFETCH");
-			nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
-			pr_cont("\n");
-			nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n",
-				nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08),
-				nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10));
-		}
-
-		nv_wr32(priv, 0x400c04, 0xc0000000);
-		nv_wr32(priv, 0x400108, 0x004);
-		status &= ~0x004;
-	}
-
-	/* STRMOUT: DirectX streamout / OpenGL transform feedback. */
-	if (status & 0x008) {
-		ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff;
-		if (display) {
-			nv_error(priv, "TRAP_STRMOUT");
-			nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
-			pr_cont("\n");
-			nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n",
-				nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808),
-				nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810));
-
-		}
-
-		/* No sane way found yet -- just reset the bugger. */
-		nv_wr32(priv, 0x400040, 0x80);
-		nv_wr32(priv, 0x400040, 0);
-		nv_wr32(priv, 0x401800, 0xc0000000);
-		nv_wr32(priv, 0x400108, 0x008);
-		status &= ~0x008;
-	}
-
-	/* CCACHE: Handles code and c[] caches and fills them. */
-	if (status & 0x010) {
-		ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff;
-		if (display) {
-			nv_error(priv, "TRAP_CCACHE");
-			nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
-			pr_cont("\n");
-			nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x"
-				     " %08x %08x %08x\n",
-				nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004),
-				nv_rd32(priv, 0x405008), nv_rd32(priv, 0x40500c),
-				nv_rd32(priv, 0x405010), nv_rd32(priv, 0x405014),
-				nv_rd32(priv, 0x40501c));
-
-		}
-
-		nv_wr32(priv, 0x405018, 0xc0000000);
-		nv_wr32(priv, 0x400108, 0x010);
-		status &= ~0x010;
-	}
-
-	/* Unknown, not seen yet... 0x402000 is the only trap status reg
-	 * remaining, so try to handle it anyway. Perhaps related to that
-	 * unknown DMA slot on tesla? */
-	if (status & 0x20) {
-		ustatus = nv_rd32(priv, 0x402000) & 0x7fffffff;
-		if (display)
-			nv_error(priv, "TRAP_UNKC04 0x%08x\n", ustatus);
-		nv_wr32(priv, 0x402000, 0xc0000000);
-		/* no status modifiction on purpose */
-	}
-
-	/* TEXTURE: CUDA texturing units */
-	if (status & 0x040) {
-		nv50_priv_tp_trap(priv, 6, 0x408900, 0x408600, display,
-				    "TRAP_TEXTURE");
-		nv_wr32(priv, 0x400108, 0x040);
-		status &= ~0x040;
-	}
-
-	/* MP: CUDA execution engines. */
-	if (status & 0x080) {
-		nv50_priv_tp_trap(priv, 7, 0x408314, 0x40831c, display,
-				    "TRAP_MP");
-		nv_wr32(priv, 0x400108, 0x080);
-		status &= ~0x080;
-	}
-
-	/* PROP:  Handles TP-initiated uncached memory accesses:
-	 * l[], g[], stack, 2d surfaces, render targets. */
-	if (status & 0x100) {
-		nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display,
-				    "TRAP_PROP");
-		nv_wr32(priv, 0x400108, 0x100);
-		status &= ~0x100;
-	}
-
-	if (status) {
-		if (display)
-			nv_error(priv, "TRAP: unknown 0x%08x\n", status);
-		nv_wr32(priv, 0x400108, status);
-	}
-
-	return 1;
-}
-
-static void
-nv50_graph_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
-	struct nouveau_engine *engine = nv_engine(subdev);
-	struct nouveau_object *engctx;
-	struct nouveau_handle *handle = NULL;
-	struct nv50_graph_priv *priv = (void *)subdev;
-	u32 stat = nv_rd32(priv, 0x400100);
-	u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff;
-	u32 addr = nv_rd32(priv, 0x400704);
-	u32 subc = (addr & 0x00070000) >> 16;
-	u32 mthd = (addr & 0x00001ffc);
-	u32 data = nv_rd32(priv, 0x400708);
-	u32 class = nv_rd32(priv, 0x400814);
-	u32 show = stat, show_bitfield = stat;
-	int chid;
-
-	engctx = nouveau_engctx_get(engine, inst);
-	chid   = pfifo->chid(pfifo, engctx);
-
-	if (stat & 0x00000010) {
-		handle = nouveau_handle_get_class(engctx, class);
-		if (handle && !nv_call(handle->object, mthd, data))
-			show &= ~0x00000010;
-		nouveau_handle_put(handle);
-	}
-
-	if (show & 0x00100000) {
-		u32 ecode = nv_rd32(priv, 0x400110);
-		nv_error(priv, "DATA_ERROR ");
-		nouveau_enum_print(nv50_data_error_names, ecode);
-		pr_cont("\n");
-		show_bitfield &= ~0x00100000;
-	}
-
-	if (stat & 0x00200000) {
-		if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12,
-				engctx))
-			show &= ~0x00200000;
-		show_bitfield &= ~0x00200000;
-	}
-
-	nv_wr32(priv, 0x400100, stat);
-	nv_wr32(priv, 0x400500, 0x00010001);
-
-	if (show) {
-		show &= show_bitfield;
-		if (show) {
-			nv_error(priv, "%s", "");
-			nouveau_bitfield_print(nv50_graph_intr_name, show);
-			pr_cont("\n");
-		}
-		nv_error(priv,
-			 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
-			 chid, (u64)inst << 12, nouveau_client_name(engctx),
-			 subc, class, mthd, data);
-	}
-
-	if (nv_rd32(priv, 0x400824) & (1 << 31))
-		nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31));
-
-	nouveau_engctx_put(engctx);
-}
-
-static int
-nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv50_graph_priv *priv;
-	int ret;
-
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00201000;
-	nv_subdev(priv)->intr = nv50_graph_intr;
-	nv_engine(priv)->cclass = &nv50_graph_cclass;
-
-	priv->base.units = nv50_graph_units;
-
-	switch (nv_device(priv)->chipset) {
-	case 0x50:
-		nv_engine(priv)->sclass = nv50_graph_sclass;
-		break;
-	case 0x84:
-	case 0x86:
-	case 0x92:
-	case 0x94:
-	case 0x96:
-	case 0x98:
-		nv_engine(priv)->sclass = nv84_graph_sclass;
-		break;
-	case 0xa0:
-	case 0xaa:
-	case 0xac:
-		nv_engine(priv)->sclass = nva0_graph_sclass;
-		break;
-	case 0xa3:
-	case 0xa5:
-	case 0xa8:
-		nv_engine(priv)->sclass = nva3_graph_sclass;
-		break;
-	case 0xaf:
-		nv_engine(priv)->sclass = nvaf_graph_sclass;
-		break;
-
-	}
-
-	/* unfortunate hw bug workaround... */
-	if (nv_device(priv)->chipset != 0x50 &&
-	    nv_device(priv)->chipset != 0xac)
-		nv_engine(priv)->tlb_flush = nv84_graph_tlb_flush;
-
-	spin_lock_init(&priv->lock);
-	return 0;
-}
-
-static int
-nv50_graph_init(struct nouveau_object *object)
-{
-	struct nv50_graph_priv *priv = (void *)object;
-	int ret, units, i;
-
-	ret = nouveau_graph_init(&priv->base);
-	if (ret)
-		return ret;
-
-	/* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */
-	nv_wr32(priv, 0x40008c, 0x00000004);
-
-	/* reset/enable traps and interrupts */
-	nv_wr32(priv, 0x400804, 0xc0000000);
-	nv_wr32(priv, 0x406800, 0xc0000000);
-	nv_wr32(priv, 0x400c04, 0xc0000000);
-	nv_wr32(priv, 0x401800, 0xc0000000);
-	nv_wr32(priv, 0x405018, 0xc0000000);
-	nv_wr32(priv, 0x402000, 0xc0000000);
-
-	units = nv_rd32(priv, 0x001540);
-	for (i = 0; i < 16; i++) {
-		if (!(units & (1 << i)))
-			continue;
-
-		if (nv_device(priv)->chipset < 0xa0) {
-			nv_wr32(priv, 0x408900 + (i << 12), 0xc0000000);
-			nv_wr32(priv, 0x408e08 + (i << 12), 0xc0000000);
-			nv_wr32(priv, 0x408314 + (i << 12), 0xc0000000);
-		} else {
-			nv_wr32(priv, 0x408600 + (i << 11), 0xc0000000);
-			nv_wr32(priv, 0x408708 + (i << 11), 0xc0000000);
-			nv_wr32(priv, 0x40831c + (i << 11), 0xc0000000);
-		}
-	}
-
-	nv_wr32(priv, 0x400108, 0xffffffff);
-	nv_wr32(priv, 0x400138, 0xffffffff);
-	nv_wr32(priv, 0x400100, 0xffffffff);
-	nv_wr32(priv, 0x40013c, 0xffffffff);
-	nv_wr32(priv, 0x400500, 0x00010001);
-
-	/* upload context program, initialise ctxctl defaults */
-	ret = nv50_grctx_init(nv_device(priv), &priv->size);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x400824, 0x00000000);
-	nv_wr32(priv, 0x400828, 0x00000000);
-	nv_wr32(priv, 0x40082c, 0x00000000);
-	nv_wr32(priv, 0x400830, 0x00000000);
-	nv_wr32(priv, 0x40032c, 0x00000000);
-	nv_wr32(priv, 0x400330, 0x00000000);
-
-	/* some unknown zcull magic */
-	switch (nv_device(priv)->chipset & 0xf0) {
-	case 0x50:
-	case 0x80:
-	case 0x90:
-		nv_wr32(priv, 0x402ca8, 0x00000800);
-		break;
-	case 0xa0:
-	default:
-		if (nv_device(priv)->chipset == 0xa0 ||
-		    nv_device(priv)->chipset == 0xaa ||
-		    nv_device(priv)->chipset == 0xac) {
-			nv_wr32(priv, 0x402ca8, 0x00000802);
-		} else {
-			nv_wr32(priv, 0x402cc0, 0x00000000);
-			nv_wr32(priv, 0x402ca8, 0x00000002);
-		}
-
-		break;
-	}
-
-	/* zero out zcull regions */
-	for (i = 0; i < 8; i++) {
-		nv_wr32(priv, 0x402c20 + (i * 0x10), 0x00000000);
-		nv_wr32(priv, 0x402c24 + (i * 0x10), 0x00000000);
-		nv_wr32(priv, 0x402c28 + (i * 0x10), 0x00000000);
-		nv_wr32(priv, 0x402c2c + (i * 0x10), 0x00000000);
-	}
-	return 0;
-}
-
-struct nouveau_oclass
-nv50_graph_oclass = {
-	.handle = NV_ENGINE(GR, 0x50),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_graph_ctor,
-		.dtor = _nouveau_graph_dtor,
-		.init = nv50_graph_init,
-		.fini = _nouveau_graph_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.h b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.h
deleted file mode 100644
index 0505fb419bde..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __NV50_GRAPH_H__
-#define __NV50_GRAPH_H__
-
-int  nv50_grctx_init(struct nouveau_device *, u32 *size);
-void nv50_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
deleted file mode 100644
index 17251e4b9e86..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ /dev/null
@@ -1,1667 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * Zero Bandwidth Clear
- ******************************************************************************/
-
-static void
-nvc0_graph_zbc_clear_color(struct nvc0_graph_priv *priv, int zbc)
-{
-	if (priv->zbc_color[zbc].format) {
-		nv_wr32(priv, 0x405804, priv->zbc_color[zbc].ds[0]);
-		nv_wr32(priv, 0x405808, priv->zbc_color[zbc].ds[1]);
-		nv_wr32(priv, 0x40580c, priv->zbc_color[zbc].ds[2]);
-		nv_wr32(priv, 0x405810, priv->zbc_color[zbc].ds[3]);
-	}
-	nv_wr32(priv, 0x405814, priv->zbc_color[zbc].format);
-	nv_wr32(priv, 0x405820, zbc);
-	nv_wr32(priv, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */
-}
-
-static int
-nvc0_graph_zbc_color_get(struct nvc0_graph_priv *priv, int format,
-			 const u32 ds[4], const u32 l2[4])
-{
-	struct nouveau_ltc *ltc = nouveau_ltc(priv);
-	int zbc = -ENOSPC, i;
-
-	for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
-		if (priv->zbc_color[i].format) {
-			if (priv->zbc_color[i].format != format)
-				continue;
-			if (memcmp(priv->zbc_color[i].ds, ds, sizeof(
-				   priv->zbc_color[i].ds)))
-				continue;
-			if (memcmp(priv->zbc_color[i].l2, l2, sizeof(
-				   priv->zbc_color[i].l2))) {
-				WARN_ON(1);
-				return -EINVAL;
-			}
-			return i;
-		} else {
-			zbc = (zbc < 0) ? i : zbc;
-		}
-	}
-
-	if (zbc < 0)
-		return zbc;
-
-	memcpy(priv->zbc_color[zbc].ds, ds, sizeof(priv->zbc_color[zbc].ds));
-	memcpy(priv->zbc_color[zbc].l2, l2, sizeof(priv->zbc_color[zbc].l2));
-	priv->zbc_color[zbc].format = format;
-	ltc->zbc_color_get(ltc, zbc, l2);
-	nvc0_graph_zbc_clear_color(priv, zbc);
-	return zbc;
-}
-
-static void
-nvc0_graph_zbc_clear_depth(struct nvc0_graph_priv *priv, int zbc)
-{
-	if (priv->zbc_depth[zbc].format)
-		nv_wr32(priv, 0x405818, priv->zbc_depth[zbc].ds);
-	nv_wr32(priv, 0x40581c, priv->zbc_depth[zbc].format);
-	nv_wr32(priv, 0x405820, zbc);
-	nv_wr32(priv, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */
-}
-
-static int
-nvc0_graph_zbc_depth_get(struct nvc0_graph_priv *priv, int format,
-			 const u32 ds, const u32 l2)
-{
-	struct nouveau_ltc *ltc = nouveau_ltc(priv);
-	int zbc = -ENOSPC, i;
-
-	for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
-		if (priv->zbc_depth[i].format) {
-			if (priv->zbc_depth[i].format != format)
-				continue;
-			if (priv->zbc_depth[i].ds != ds)
-				continue;
-			if (priv->zbc_depth[i].l2 != l2) {
-				WARN_ON(1);
-				return -EINVAL;
-			}
-			return i;
-		} else {
-			zbc = (zbc < 0) ? i : zbc;
-		}
-	}
-
-	if (zbc < 0)
-		return zbc;
-
-	priv->zbc_depth[zbc].format = format;
-	priv->zbc_depth[zbc].ds = ds;
-	priv->zbc_depth[zbc].l2 = l2;
-	ltc->zbc_depth_get(ltc, zbc, l2);
-	nvc0_graph_zbc_clear_depth(priv, zbc);
-	return zbc;
-}
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-static int
-nvc0_fermi_mthd_zbc_color(struct nouveau_object *object, void *data, u32 size)
-{
-	struct nvc0_graph_priv *priv = (void *)object->engine;
-	union {
-		struct fermi_a_zbc_color_v0 v0;
-	} *args = data;
-	int ret;
-
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		switch (args->v0.format) {
-		case FERMI_A_ZBC_COLOR_V0_FMT_ZERO:
-		case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE:
-		case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32:
-		case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16:
-		case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16:
-		case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16:
-		case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16:
-		case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16:
-		case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8:
-		case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8:
-		case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10:
-		case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10:
-		case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8:
-		case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8:
-		case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8:
-		case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8:
-		case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8:
-		case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10:
-		case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11:
-			ret = nvc0_graph_zbc_color_get(priv, args->v0.format,
-							     args->v0.ds,
-							     args->v0.l2);
-			if (ret >= 0) {
-				args->v0.index = ret;
-				return 0;
-			}
-			break;
-		default:
-			return -EINVAL;
-		}
-	}
-
-	return ret;
-}
-
-static int
-nvc0_fermi_mthd_zbc_depth(struct nouveau_object *object, void *data, u32 size)
-{
-	struct nvc0_graph_priv *priv = (void *)object->engine;
-	union {
-		struct fermi_a_zbc_depth_v0 v0;
-	} *args = data;
-	int ret;
-
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		switch (args->v0.format) {
-		case FERMI_A_ZBC_DEPTH_V0_FMT_FP32:
-			ret = nvc0_graph_zbc_depth_get(priv, args->v0.format,
-							     args->v0.ds,
-							     args->v0.l2);
-			return (ret >= 0) ? 0 : -ENOSPC;
-		default:
-			return -EINVAL;
-		}
-	}
-
-	return ret;
-}
-
-static int
-nvc0_fermi_mthd(struct nouveau_object *object, u32 mthd, void *data, u32 size)
-{
-	switch (mthd) {
-	case FERMI_A_ZBC_COLOR:
-		return nvc0_fermi_mthd_zbc_color(object, data, size);
-	case FERMI_A_ZBC_DEPTH:
-		return nvc0_fermi_mthd_zbc_depth(object, data, size);
-	default:
-		break;
-	}
-	return -EINVAL;
-}
-
-struct nouveau_ofuncs
-nvc0_fermi_ofuncs = {
-	.ctor = _nouveau_object_ctor,
-	.dtor = nouveau_object_destroy,
-	.init = nouveau_object_init,
-	.fini = nouveau_object_fini,
-	.mthd = nvc0_fermi_mthd,
-};
-
-static int
-nvc0_graph_set_shader_exceptions(struct nouveau_object *object, u32 mthd,
-				 void *pdata, u32 size)
-{
-	struct nvc0_graph_priv *priv = (void *)nv_engine(object);
-	if (size >= sizeof(u32)) {
-		u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000;
-		nv_wr32(priv, 0x419e44, data);
-		nv_wr32(priv, 0x419e4c, data);
-		return 0;
-	}
-	return -EINVAL;
-}
-
-struct nouveau_omthds
-nvc0_graph_9097_omthds[] = {
-	{ 0x1528, 0x1528, nvc0_graph_set_shader_exceptions },
-	{}
-};
-
-struct nouveau_omthds
-nvc0_graph_90c0_omthds[] = {
-	{ 0x1528, 0x1528, nvc0_graph_set_shader_exceptions },
-	{}
-};
-
-struct nouveau_oclass
-nvc0_graph_sclass[] = {
-	{ 0x902d, &nouveau_object_ofuncs },
-	{ 0x9039, &nouveau_object_ofuncs },
-	{ FERMI_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH context
- ******************************************************************************/
-
-int
-nvc0_graph_context_ctor(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass, void *args, u32 size,
-			struct nouveau_object **pobject)
-{
-	struct nouveau_vm *vm = nouveau_client(parent)->vm;
-	struct nvc0_graph_priv *priv = (void *)engine;
-	struct nvc0_graph_data *data = priv->mmio_data;
-	struct nvc0_graph_mmio *mmio = priv->mmio_list;
-	struct nvc0_graph_chan *chan;
-	int ret, i;
-
-	/* allocate memory for context, and fill with default values */
-	ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
-					   priv->size, 0x100,
-					   NVOBJ_FLAG_ZERO_ALLOC, &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	/* allocate memory for a "mmio list" buffer that's used by the HUB
-	 * fuc to modify some per-context register settings on first load
-	 * of the context.
-	 */
-	ret = nouveau_gpuobj_new(nv_object(chan), NULL, 0x1000, 0x100, 0,
-				&chan->mmio);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm,
-				    NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
-				    &chan->mmio_vma);
-	if (ret)
-		return ret;
-
-	/* allocate buffers referenced by mmio list */
-	for (i = 0; data->size && i < ARRAY_SIZE(priv->mmio_data); i++) {
-		ret = nouveau_gpuobj_new(nv_object(chan), NULL, data->size,
-					 data->align, 0, &chan->data[i].mem);
-		if (ret)
-			return ret;
-
-		ret = nouveau_gpuobj_map_vm(chan->data[i].mem, vm, data->access,
-					   &chan->data[i].vma);
-		if (ret)
-			return ret;
-
-		data++;
-	}
-
-	/* finally, fill in the mmio list and point the context at it */
-	for (i = 0; mmio->addr && i < ARRAY_SIZE(priv->mmio_list); i++) {
-		u32 addr = mmio->addr;
-		u32 data = mmio->data;
-
-		if (mmio->buffer >= 0) {
-			u64 info = chan->data[mmio->buffer].vma.offset;
-			data |= info >> mmio->shift;
-		}
-
-		nv_wo32(chan->mmio, chan->mmio_nr++ * 4, addr);
-		nv_wo32(chan->mmio, chan->mmio_nr++ * 4, data);
-		mmio++;
-	}
-
-	for (i = 0; i < priv->size; i += 4)
-		nv_wo32(chan, i, priv->data[i / 4]);
-
-	if (!priv->firmware) {
-		nv_wo32(chan, 0x00, chan->mmio_nr / 2);
-		nv_wo32(chan, 0x04, chan->mmio_vma.offset >> 8);
-	} else {
-		nv_wo32(chan, 0xf4, 0);
-		nv_wo32(chan, 0xf8, 0);
-		nv_wo32(chan, 0x10, chan->mmio_nr / 2);
-		nv_wo32(chan, 0x14, lower_32_bits(chan->mmio_vma.offset));
-		nv_wo32(chan, 0x18, upper_32_bits(chan->mmio_vma.offset));
-		nv_wo32(chan, 0x1c, 1);
-		nv_wo32(chan, 0x20, 0);
-		nv_wo32(chan, 0x28, 0);
-		nv_wo32(chan, 0x2c, 0);
-	}
-
-	return 0;
-}
-
-void
-nvc0_graph_context_dtor(struct nouveau_object *object)
-{
-	struct nvc0_graph_chan *chan = (void *)object;
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(chan->data); i++) {
-		nouveau_gpuobj_unmap(&chan->data[i].vma);
-		nouveau_gpuobj_ref(NULL, &chan->data[i].mem);
-	}
-
-	nouveau_gpuobj_unmap(&chan->mmio_vma);
-	nouveau_gpuobj_ref(NULL, &chan->mmio);
-
-	nouveau_graph_context_destroy(&chan->base);
-}
-
-/*******************************************************************************
- * PGRAPH register lists
- ******************************************************************************/
-
-const struct nvc0_graph_init
-nvc0_graph_init_main_0[] = {
-	{ 0x400080,   1, 0x04, 0x003083c2 },
-	{ 0x400088,   1, 0x04, 0x00006fe7 },
-	{ 0x40008c,   1, 0x04, 0x00000000 },
-	{ 0x400090,   1, 0x04, 0x00000030 },
-	{ 0x40013c,   1, 0x04, 0x013901f7 },
-	{ 0x400140,   1, 0x04, 0x00000100 },
-	{ 0x400144,   1, 0x04, 0x00000000 },
-	{ 0x400148,   1, 0x04, 0x00000110 },
-	{ 0x400138,   1, 0x04, 0x00000000 },
-	{ 0x400130,   2, 0x04, 0x00000000 },
-	{ 0x400124,   1, 0x04, 0x00000002 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_fe_0[] = {
-	{ 0x40415c,   1, 0x04, 0x00000000 },
-	{ 0x404170,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_pri_0[] = {
-	{ 0x404488,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_rstr2d_0[] = {
-	{ 0x407808,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_pd_0[] = {
-	{ 0x406024,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_ds_0[] = {
-	{ 0x405844,   1, 0x04, 0x00ffffff },
-	{ 0x405850,   1, 0x04, 0x00000000 },
-	{ 0x405908,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_scc_0[] = {
-	{ 0x40803c,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_prop_0[] = {
-	{ 0x4184a0,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_gpc_unk_0[] = {
-	{ 0x418604,   1, 0x04, 0x00000000 },
-	{ 0x418680,   1, 0x04, 0x00000000 },
-	{ 0x418714,   1, 0x04, 0x80000000 },
-	{ 0x418384,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_setup_0[] = {
-	{ 0x418814,   3, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_crstr_0[] = {
-	{ 0x418b04,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_setup_1[] = {
-	{ 0x4188c8,   1, 0x04, 0x80000000 },
-	{ 0x4188cc,   1, 0x04, 0x00000000 },
-	{ 0x4188d0,   1, 0x04, 0x00010000 },
-	{ 0x4188d4,   1, 0x04, 0x00000001 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_zcull_0[] = {
-	{ 0x418910,   1, 0x04, 0x00010001 },
-	{ 0x418914,   1, 0x04, 0x00000301 },
-	{ 0x418918,   1, 0x04, 0x00800000 },
-	{ 0x418980,   1, 0x04, 0x77777770 },
-	{ 0x418984,   3, 0x04, 0x77777777 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_gpm_0[] = {
-	{ 0x418c04,   1, 0x04, 0x00000000 },
-	{ 0x418c88,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_gpc_unk_1[] = {
-	{ 0x418d00,   1, 0x04, 0x00000000 },
-	{ 0x418f08,   1, 0x04, 0x00000000 },
-	{ 0x418e00,   1, 0x04, 0x00000050 },
-	{ 0x418e08,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_gcc_0[] = {
-	{ 0x41900c,   1, 0x04, 0x00000000 },
-	{ 0x419018,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_tpccs_0[] = {
-	{ 0x419d08,   2, 0x04, 0x00000000 },
-	{ 0x419d10,   1, 0x04, 0x00000014 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_tex_0[] = {
-	{ 0x419ab0,   1, 0x04, 0x00000000 },
-	{ 0x419ab8,   1, 0x04, 0x000000e7 },
-	{ 0x419abc,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_pe_0[] = {
-	{ 0x41980c,   3, 0x04, 0x00000000 },
-	{ 0x419844,   1, 0x04, 0x00000000 },
-	{ 0x41984c,   1, 0x04, 0x00005bc5 },
-	{ 0x419850,   4, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_l1c_0[] = {
-	{ 0x419c98,   1, 0x04, 0x00000000 },
-	{ 0x419ca8,   1, 0x04, 0x80000000 },
-	{ 0x419cb4,   1, 0x04, 0x00000000 },
-	{ 0x419cb8,   1, 0x04, 0x00008bf4 },
-	{ 0x419cbc,   1, 0x04, 0x28137606 },
-	{ 0x419cc0,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_wwdx_0[] = {
-	{ 0x419bd4,   1, 0x04, 0x00800000 },
-	{ 0x419bdc,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_tpccs_1[] = {
-	{ 0x419d2c,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_mpc_0[] = {
-	{ 0x419c0c,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc0_graph_init_sm_0[] = {
-	{ 0x419e00,   1, 0x04, 0x00000000 },
-	{ 0x419ea0,   1, 0x04, 0x00000000 },
-	{ 0x419ea4,   1, 0x04, 0x00000100 },
-	{ 0x419ea8,   1, 0x04, 0x00001100 },
-	{ 0x419eac,   1, 0x04, 0x11100702 },
-	{ 0x419eb0,   1, 0x04, 0x00000003 },
-	{ 0x419eb4,   4, 0x04, 0x00000000 },
-	{ 0x419ec8,   1, 0x04, 0x06060618 },
-	{ 0x419ed0,   1, 0x04, 0x0eff0e38 },
-	{ 0x419ed4,   1, 0x04, 0x011104f1 },
-	{ 0x419edc,   1, 0x04, 0x00000000 },
-	{ 0x419f00,   1, 0x04, 0x00000000 },
-	{ 0x419f2c,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_be_0[] = {
-	{ 0x40880c,   1, 0x04, 0x00000000 },
-	{ 0x408910,   9, 0x04, 0x00000000 },
-	{ 0x408950,   1, 0x04, 0x00000000 },
-	{ 0x408954,   1, 0x04, 0x0000ffff },
-	{ 0x408984,   1, 0x04, 0x00000000 },
-	{ 0x408988,   1, 0x04, 0x08040201 },
-	{ 0x40898c,   1, 0x04, 0x80402010 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_fe_1[] = {
-	{ 0x4040f0,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc0_graph_init_pe_1[] = {
-	{ 0x419880,   1, 0x04, 0x00000002 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvc0_graph_pack_mmio[] = {
-	{ nvc0_graph_init_main_0 },
-	{ nvc0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvc0_graph_init_pd_0 },
-	{ nvc0_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvc0_graph_init_prop_0 },
-	{ nvc0_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc0_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvc0_graph_init_gpm_0 },
-	{ nvc0_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nvc0_graph_init_tpccs_0 },
-	{ nvc0_graph_init_tex_0 },
-	{ nvc0_graph_init_pe_0 },
-	{ nvc0_graph_init_l1c_0 },
-	{ nvc0_graph_init_wwdx_0 },
-	{ nvc0_graph_init_tpccs_1 },
-	{ nvc0_graph_init_mpc_0 },
-	{ nvc0_graph_init_sm_0 },
-	{ nvc0_graph_init_be_0 },
-	{ nvc0_graph_init_fe_1 },
-	{ nvc0_graph_init_pe_1 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-void
-nvc0_graph_zbc_init(struct nvc0_graph_priv *priv)
-{
-	const u32  zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-			      0x00000000, 0x00000000, 0x00000000, 0x00000000 };
-	const u32   one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
-			      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff };
-	const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-			      0x00000000, 0x00000000, 0x00000000, 0x00000000 };
-	const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
-			      0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 };
-	struct nouveau_ltc *ltc = nouveau_ltc(priv);
-	int index;
-
-	if (!priv->zbc_color[0].format) {
-		nvc0_graph_zbc_color_get(priv, 1,  & zero[0],   &zero[4]);
-		nvc0_graph_zbc_color_get(priv, 2,  &  one[0],    &one[4]);
-		nvc0_graph_zbc_color_get(priv, 4,  &f32_0[0],  &f32_0[4]);
-		nvc0_graph_zbc_color_get(priv, 4,  &f32_1[0],  &f32_1[4]);
-		nvc0_graph_zbc_depth_get(priv, 1, 0x00000000, 0x00000000);
-		nvc0_graph_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000);
-	}
-
-	for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
-		nvc0_graph_zbc_clear_color(priv, index);
-	for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
-		nvc0_graph_zbc_clear_depth(priv, index);
-}
-
-void
-nvc0_graph_mmio(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p)
-{
-	const struct nvc0_graph_pack *pack;
-	const struct nvc0_graph_init *init;
-
-	pack_for_each_init(init, pack, p) {
-		u32 next = init->addr + init->count * init->pitch;
-		u32 addr = init->addr;
-		while (addr < next) {
-			nv_wr32(priv, addr, init->data);
-			addr += init->pitch;
-		}
-	}
-}
-
-void
-nvc0_graph_icmd(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p)
-{
-	const struct nvc0_graph_pack *pack;
-	const struct nvc0_graph_init *init;
-	u32 data = 0;
-
-	nv_wr32(priv, 0x400208, 0x80000000);
-
-	pack_for_each_init(init, pack, p) {
-		u32 next = init->addr + init->count * init->pitch;
-		u32 addr = init->addr;
-
-		if ((pack == p && init == p->init) || data != init->data) {
-			nv_wr32(priv, 0x400204, init->data);
-			data = init->data;
-		}
-
-		while (addr < next) {
-			nv_wr32(priv, 0x400200, addr);
-			nv_wait(priv, 0x400700, 0x00000002, 0x00000000);
-			addr += init->pitch;
-		}
-	}
-
-	nv_wr32(priv, 0x400208, 0x00000000);
-}
-
-void
-nvc0_graph_mthd(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p)
-{
-	const struct nvc0_graph_pack *pack;
-	const struct nvc0_graph_init *init;
-	u32 data = 0;
-
-	pack_for_each_init(init, pack, p) {
-		u32 ctrl = 0x80000000 | pack->type;
-		u32 next = init->addr + init->count * init->pitch;
-		u32 addr = init->addr;
-
-		if ((pack == p && init == p->init) || data != init->data) {
-			nv_wr32(priv, 0x40448c, init->data);
-			data = init->data;
-		}
-
-		while (addr < next) {
-			nv_wr32(priv, 0x404488, ctrl | (addr << 14));
-			addr += init->pitch;
-		}
-	}
-}
-
-u64
-nvc0_graph_units(struct nouveau_graph *graph)
-{
-	struct nvc0_graph_priv *priv = (void *)graph;
-	u64 cfg;
-
-	cfg  = (u32)priv->gpc_nr;
-	cfg |= (u32)priv->tpc_total << 8;
-	cfg |= (u64)priv->rop_nr << 32;
-
-	return cfg;
-}
-
-static const struct nouveau_enum nve0_sked_error[] = {
-	{ 7, "CONSTANT_BUFFER_SIZE" },
-	{ 9, "LOCAL_MEMORY_SIZE_POS" },
-	{ 10, "LOCAL_MEMORY_SIZE_NEG" },
-	{ 11, "WARP_CSTACK_SIZE" },
-	{ 12, "TOTAL_TEMP_SIZE" },
-	{ 13, "REGISTER_COUNT" },
-	{ 18, "TOTAL_THREADS" },
-	{ 20, "PROGRAM_OFFSET" },
-	{ 21, "SHARED_MEMORY_SIZE" },
-	{ 25, "SHARED_CONFIG_TOO_SMALL" },
-	{ 26, "TOTAL_REGISTER_COUNT" },
-	{}
-};
-
-static const struct nouveau_enum nvc0_gpc_rop_error[] = {
-	{ 1, "RT_PITCH_OVERRUN" },
-	{ 4, "RT_WIDTH_OVERRUN" },
-	{ 5, "RT_HEIGHT_OVERRUN" },
-	{ 7, "ZETA_STORAGE_TYPE_MISMATCH" },
-	{ 8, "RT_STORAGE_TYPE_MISMATCH" },
-	{ 10, "RT_LINEAR_MISMATCH" },
-	{}
-};
-
-static void
-nvc0_graph_trap_gpc_rop(struct nvc0_graph_priv *priv, int gpc)
-{
-	u32 trap[4];
-	int i;
-
-	trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420));
-	trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434));
-	trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438));
-	trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c));
-
-	nv_error(priv, "GPC%d/PROP trap:", gpc);
-	for (i = 0; i <= 29; ++i) {
-		if (!(trap[0] & (1 << i)))
-			continue;
-		pr_cont(" ");
-		nouveau_enum_print(nvc0_gpc_rop_error, i);
-	}
-	pr_cont("\n");
-
-	nv_error(priv, "x = %u, y = %u, format = %x, storage type = %x\n",
-		 trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f,
-		 trap[3] & 0xff);
-	nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
-}
-
-static const struct nouveau_enum nvc0_mp_warp_error[] = {
-	{ 0x00, "NO_ERROR" },
-	{ 0x01, "STACK_MISMATCH" },
-	{ 0x05, "MISALIGNED_PC" },
-	{ 0x08, "MISALIGNED_GPR" },
-	{ 0x09, "INVALID_OPCODE" },
-	{ 0x0d, "GPR_OUT_OF_BOUNDS" },
-	{ 0x0e, "MEM_OUT_OF_BOUNDS" },
-	{ 0x0f, "UNALIGNED_MEM_ACCESS" },
-	{ 0x11, "INVALID_PARAM" },
-	{}
-};
-
-static const struct nouveau_bitfield nvc0_mp_global_error[] = {
-	{ 0x00000004, "MULTIPLE_WARP_ERRORS" },
-	{ 0x00000008, "OUT_OF_STACK_SPACE" },
-	{}
-};
-
-static void
-nvc0_graph_trap_mp(struct nvc0_graph_priv *priv, int gpc, int tpc)
-{
-	u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648));
-	u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650));
-
-	nv_error(priv, "GPC%i/TPC%i/MP trap:", gpc, tpc);
-	nouveau_bitfield_print(nvc0_mp_global_error, gerr);
-	if (werr) {
-		pr_cont(" ");
-		nouveau_enum_print(nvc0_mp_warp_error, werr & 0xffff);
-	}
-	pr_cont("\n");
-
-	nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);
-	nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x650), gerr);
-}
-
-static void
-nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc)
-{
-	u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508));
-
-	if (stat & 0x00000001) {
-		u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0224));
-		nv_error(priv, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap);
-		nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
-		stat &= ~0x00000001;
-	}
-
-	if (stat & 0x00000002) {
-		nvc0_graph_trap_mp(priv, gpc, tpc);
-		stat &= ~0x00000002;
-	}
-
-	if (stat & 0x00000004) {
-		u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0084));
-		nv_error(priv, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap);
-		nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
-		stat &= ~0x00000004;
-	}
-
-	if (stat & 0x00000008) {
-		u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x048c));
-		nv_error(priv, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap);
-		nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
-		stat &= ~0x00000008;
-	}
-
-	if (stat) {
-		nv_error(priv, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat);
-	}
-}
-
-static void
-nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
-{
-	u32 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90));
-	int tpc;
-
-	if (stat & 0x00000001) {
-		nvc0_graph_trap_gpc_rop(priv, gpc);
-		stat &= ~0x00000001;
-	}
-
-	if (stat & 0x00000002) {
-		u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900));
-		nv_error(priv, "GPC%d/ZCULL: 0x%08x\n", gpc, trap);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
-		stat &= ~0x00000002;
-	}
-
-	if (stat & 0x00000004) {
-		u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028));
-		nv_error(priv, "GPC%d/CCACHE: 0x%08x\n", gpc, trap);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
-		stat &= ~0x00000004;
-	}
-
-	if (stat & 0x00000008) {
-		u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824));
-		nv_error(priv, "GPC%d/ESETUP: 0x%08x\n", gpc, trap);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
-		stat &= ~0x00000009;
-	}
-
-	for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
-		u32 mask = 0x00010000 << tpc;
-		if (stat & mask) {
-			nvc0_graph_trap_tpc(priv, gpc, tpc);
-			nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), mask);
-			stat &= ~mask;
-		}
-	}
-
-	if (stat) {
-		nv_error(priv, "GPC%d/0x%08x: unknown\n", gpc, stat);
-	}
-}
-
-static void
-nvc0_graph_trap_intr(struct nvc0_graph_priv *priv)
-{
-	u32 trap = nv_rd32(priv, 0x400108);
-	int rop, gpc, i;
-
-	if (trap & 0x00000001) {
-		u32 stat = nv_rd32(priv, 0x404000);
-		nv_error(priv, "DISPATCH 0x%08x\n", stat);
-		nv_wr32(priv, 0x404000, 0xc0000000);
-		nv_wr32(priv, 0x400108, 0x00000001);
-		trap &= ~0x00000001;
-	}
-
-	if (trap & 0x00000002) {
-		u32 stat = nv_rd32(priv, 0x404600);
-		nv_error(priv, "M2MF 0x%08x\n", stat);
-		nv_wr32(priv, 0x404600, 0xc0000000);
-		nv_wr32(priv, 0x400108, 0x00000002);
-		trap &= ~0x00000002;
-	}
-
-	if (trap & 0x00000008) {
-		u32 stat = nv_rd32(priv, 0x408030);
-		nv_error(priv, "CCACHE 0x%08x\n", stat);
-		nv_wr32(priv, 0x408030, 0xc0000000);
-		nv_wr32(priv, 0x400108, 0x00000008);
-		trap &= ~0x00000008;
-	}
-
-	if (trap & 0x00000010) {
-		u32 stat = nv_rd32(priv, 0x405840);
-		nv_error(priv, "SHADER 0x%08x\n", stat);
-		nv_wr32(priv, 0x405840, 0xc0000000);
-		nv_wr32(priv, 0x400108, 0x00000010);
-		trap &= ~0x00000010;
-	}
-
-	if (trap & 0x00000040) {
-		u32 stat = nv_rd32(priv, 0x40601c);
-		nv_error(priv, "UNK6 0x%08x\n", stat);
-		nv_wr32(priv, 0x40601c, 0xc0000000);
-		nv_wr32(priv, 0x400108, 0x00000040);
-		trap &= ~0x00000040;
-	}
-
-	if (trap & 0x00000080) {
-		u32 stat = nv_rd32(priv, 0x404490);
-		nv_error(priv, "MACRO 0x%08x\n", stat);
-		nv_wr32(priv, 0x404490, 0xc0000000);
-		nv_wr32(priv, 0x400108, 0x00000080);
-		trap &= ~0x00000080;
-	}
-
-	if (trap & 0x00000100) {
-		u32 stat = nv_rd32(priv, 0x407020);
-
-		nv_error(priv, "SKED:");
-		for (i = 0; i <= 29; ++i) {
-			if (!(stat & (1 << i)))
-				continue;
-			pr_cont(" ");
-			nouveau_enum_print(nve0_sked_error, i);
-		}
-		pr_cont("\n");
-
-		if (stat & 0x3fffffff)
-			nv_wr32(priv, 0x407020, 0x40000000);
-		nv_wr32(priv, 0x400108, 0x00000100);
-		trap &= ~0x00000100;
-	}
-
-	if (trap & 0x01000000) {
-		u32 stat = nv_rd32(priv, 0x400118);
-		for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) {
-			u32 mask = 0x00000001 << gpc;
-			if (stat & mask) {
-				nvc0_graph_trap_gpc(priv, gpc);
-				nv_wr32(priv, 0x400118, mask);
-				stat &= ~mask;
-			}
-		}
-		nv_wr32(priv, 0x400108, 0x01000000);
-		trap &= ~0x01000000;
-	}
-
-	if (trap & 0x02000000) {
-		for (rop = 0; rop < priv->rop_nr; rop++) {
-			u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070));
-			u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144));
-			nv_error(priv, "ROP%d 0x%08x 0x%08x\n",
-				 rop, statz, statc);
-			nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
-			nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
-		}
-		nv_wr32(priv, 0x400108, 0x02000000);
-		trap &= ~0x02000000;
-	}
-
-	if (trap) {
-		nv_error(priv, "TRAP UNHANDLED 0x%08x\n", trap);
-		nv_wr32(priv, 0x400108, trap);
-	}
-}
-
-static void
-nvc0_graph_ctxctl_debug_unit(struct nvc0_graph_priv *priv, u32 base)
-{
-	nv_error(priv, "%06x - done 0x%08x\n", base,
-		 nv_rd32(priv, base + 0x400));
-	nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
-		 nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804),
-		 nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c));
-	nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
-		 nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814),
-		 nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c));
-}
-
-void
-nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *priv)
-{
-	u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff;
-	u32 gpc;
-
-	nvc0_graph_ctxctl_debug_unit(priv, 0x409000);
-	for (gpc = 0; gpc < gpcnr; gpc++)
-		nvc0_graph_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000));
-}
-
-static void
-nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv)
-{
-	u32 stat = nv_rd32(priv, 0x409c18);
-
-	if (stat & 0x00000001) {
-		u32 code = nv_rd32(priv, 0x409814);
-		if (code == E_BAD_FWMTHD) {
-			u32 class = nv_rd32(priv, 0x409808);
-			u32  addr = nv_rd32(priv, 0x40980c);
-			u32  subc = (addr & 0x00070000) >> 16;
-			u32  mthd = (addr & 0x00003ffc);
-			u32  data = nv_rd32(priv, 0x409810);
-
-			nv_error(priv, "FECS MTHD subc %d class 0x%04x "
-				       "mthd 0x%04x data 0x%08x\n",
-				 subc, class, mthd, data);
-
-			nv_wr32(priv, 0x409c20, 0x00000001);
-			stat &= ~0x00000001;
-		} else {
-			nv_error(priv, "FECS ucode error %d\n", code);
-		}
-	}
-
-	if (stat & 0x00080000) {
-		nv_error(priv, "FECS watchdog timeout\n");
-		nvc0_graph_ctxctl_debug(priv);
-		nv_wr32(priv, 0x409c20, 0x00080000);
-		stat &= ~0x00080000;
-	}
-
-	if (stat) {
-		nv_error(priv, "FECS 0x%08x\n", stat);
-		nvc0_graph_ctxctl_debug(priv);
-		nv_wr32(priv, 0x409c20, stat);
-	}
-}
-
-static void
-nvc0_graph_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
-	struct nouveau_engine *engine = nv_engine(subdev);
-	struct nouveau_object *engctx;
-	struct nouveau_handle *handle;
-	struct nvc0_graph_priv *priv = (void *)subdev;
-	u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff;
-	u32 stat = nv_rd32(priv, 0x400100);
-	u32 addr = nv_rd32(priv, 0x400704);
-	u32 mthd = (addr & 0x00003ffc);
-	u32 subc = (addr & 0x00070000) >> 16;
-	u32 data = nv_rd32(priv, 0x400708);
-	u32 code = nv_rd32(priv, 0x400110);
-	u32 class = nv_rd32(priv, 0x404200 + (subc * 4));
-	int chid;
-
-	engctx = nouveau_engctx_get(engine, inst);
-	chid   = pfifo->chid(pfifo, engctx);
-
-	if (stat & 0x00000010) {
-		handle = nouveau_handle_get_class(engctx, class);
-		if (!handle || nv_call(handle->object, mthd, data)) {
-			nv_error(priv,
-				 "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
-				 chid, inst << 12, nouveau_client_name(engctx),
-				 subc, class, mthd, data);
-		}
-		nouveau_handle_put(handle);
-		nv_wr32(priv, 0x400100, 0x00000010);
-		stat &= ~0x00000010;
-	}
-
-	if (stat & 0x00000020) {
-		nv_error(priv,
-			 "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
-			 chid, inst << 12, nouveau_client_name(engctx), subc,
-			 class, mthd, data);
-		nv_wr32(priv, 0x400100, 0x00000020);
-		stat &= ~0x00000020;
-	}
-
-	if (stat & 0x00100000) {
-		nv_error(priv, "DATA_ERROR [");
-		nouveau_enum_print(nv50_data_error_names, code);
-		pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
-			chid, inst << 12, nouveau_client_name(engctx), subc,
-			class, mthd, data);
-		nv_wr32(priv, 0x400100, 0x00100000);
-		stat &= ~0x00100000;
-	}
-
-	if (stat & 0x00200000) {
-		nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12,
-			 nouveau_client_name(engctx));
-		nvc0_graph_trap_intr(priv);
-		nv_wr32(priv, 0x400100, 0x00200000);
-		stat &= ~0x00200000;
-	}
-
-	if (stat & 0x00080000) {
-		nvc0_graph_ctxctl_isr(priv);
-		nv_wr32(priv, 0x400100, 0x00080000);
-		stat &= ~0x00080000;
-	}
-
-	if (stat) {
-		nv_error(priv, "unknown stat 0x%08x\n", stat);
-		nv_wr32(priv, 0x400100, stat);
-	}
-
-	nv_wr32(priv, 0x400500, 0x00010001);
-	nouveau_engctx_put(engctx);
-}
-
-void
-nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base,
-		   struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data)
-{
-	int i;
-
-	nv_wr32(priv, fuc_base + 0x01c0, 0x01000000);
-	for (i = 0; i < data->size / 4; i++)
-		nv_wr32(priv, fuc_base + 0x01c4, data->data[i]);
-
-	nv_wr32(priv, fuc_base + 0x0180, 0x01000000);
-	for (i = 0; i < code->size / 4; i++) {
-		if ((i & 0x3f) == 0)
-			nv_wr32(priv, fuc_base + 0x0188, i >> 6);
-		nv_wr32(priv, fuc_base + 0x0184, code->data[i]);
-	}
-
-	/* code must be padded to 0x40 words */
-	for (; i & 0x3f; i++)
-		nv_wr32(priv, fuc_base + 0x0184, 0);
-}
-
-static void
-nvc0_graph_init_csdata(struct nvc0_graph_priv *priv,
-		       const struct nvc0_graph_pack *pack,
-		       u32 falcon, u32 starstar, u32 base)
-{
-	const struct nvc0_graph_pack *iter;
-	const struct nvc0_graph_init *init;
-	u32 addr = ~0, prev = ~0, xfer = 0;
-	u32 star, temp;
-
-	nv_wr32(priv, falcon + 0x01c0, 0x02000000 + starstar);
-	star = nv_rd32(priv, falcon + 0x01c4);
-	temp = nv_rd32(priv, falcon + 0x01c4);
-	if (temp > star)
-		star = temp;
-	nv_wr32(priv, falcon + 0x01c0, 0x01000000 + star);
-
-	pack_for_each_init(init, iter, pack) {
-		u32 head = init->addr - base;
-		u32 tail = head + init->count * init->pitch;
-		while (head < tail) {
-			if (head != prev + 4 || xfer >= 32) {
-				if (xfer) {
-					u32 data = ((--xfer << 26) | addr);
-					nv_wr32(priv, falcon + 0x01c4, data);
-					star += 4;
-				}
-				addr = head;
-				xfer = 0;
-			}
-			prev = head;
-			xfer = xfer + 1;
-			head = head + init->pitch;
-		}
-	}
-
-	nv_wr32(priv, falcon + 0x01c4, (--xfer << 26) | addr);
-	nv_wr32(priv, falcon + 0x01c0, 0x01000004 + starstar);
-	nv_wr32(priv, falcon + 0x01c4, star + 4);
-}
-
-int
-nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
-{
-	struct nvc0_graph_oclass *oclass = (void *)nv_object(priv)->oclass;
-	struct nvc0_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass;
-	int i;
-
-	if (priv->firmware) {
-		/* load fuc microcode */
-		nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
-		nvc0_graph_init_fw(priv, 0x409000, &priv->fuc409c,
-						   &priv->fuc409d);
-		nvc0_graph_init_fw(priv, 0x41a000, &priv->fuc41ac,
-						   &priv->fuc41ad);
-		nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
-
-		/* start both of them running */
-		nv_wr32(priv, 0x409840, 0xffffffff);
-		nv_wr32(priv, 0x41a10c, 0x00000000);
-		nv_wr32(priv, 0x40910c, 0x00000000);
-		nv_wr32(priv, 0x41a100, 0x00000002);
-		nv_wr32(priv, 0x409100, 0x00000002);
-		if (!nv_wait(priv, 0x409800, 0x00000001, 0x00000001))
-			nv_warn(priv, "0x409800 wait failed\n");
-
-		nv_wr32(priv, 0x409840, 0xffffffff);
-		nv_wr32(priv, 0x409500, 0x7fffffff);
-		nv_wr32(priv, 0x409504, 0x00000021);
-
-		nv_wr32(priv, 0x409840, 0xffffffff);
-		nv_wr32(priv, 0x409500, 0x00000000);
-		nv_wr32(priv, 0x409504, 0x00000010);
-		if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
-			nv_error(priv, "fuc09 req 0x10 timeout\n");
-			return -EBUSY;
-		}
-		priv->size = nv_rd32(priv, 0x409800);
-
-		nv_wr32(priv, 0x409840, 0xffffffff);
-		nv_wr32(priv, 0x409500, 0x00000000);
-		nv_wr32(priv, 0x409504, 0x00000016);
-		if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
-			nv_error(priv, "fuc09 req 0x16 timeout\n");
-			return -EBUSY;
-		}
-
-		nv_wr32(priv, 0x409840, 0xffffffff);
-		nv_wr32(priv, 0x409500, 0x00000000);
-		nv_wr32(priv, 0x409504, 0x00000025);
-		if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
-			nv_error(priv, "fuc09 req 0x25 timeout\n");
-			return -EBUSY;
-		}
-
-		if (nv_device(priv)->chipset >= 0xe0) {
-			nv_wr32(priv, 0x409800, 0x00000000);
-			nv_wr32(priv, 0x409500, 0x00000001);
-			nv_wr32(priv, 0x409504, 0x00000030);
-			if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
-				nv_error(priv, "fuc09 req 0x30 timeout\n");
-				return -EBUSY;
-			}
-
-			nv_wr32(priv, 0x409810, 0xb00095c8);
-			nv_wr32(priv, 0x409800, 0x00000000);
-			nv_wr32(priv, 0x409500, 0x00000001);
-			nv_wr32(priv, 0x409504, 0x00000031);
-			if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
-				nv_error(priv, "fuc09 req 0x31 timeout\n");
-				return -EBUSY;
-			}
-
-			nv_wr32(priv, 0x409810, 0x00080420);
-			nv_wr32(priv, 0x409800, 0x00000000);
-			nv_wr32(priv, 0x409500, 0x00000001);
-			nv_wr32(priv, 0x409504, 0x00000032);
-			if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
-				nv_error(priv, "fuc09 req 0x32 timeout\n");
-				return -EBUSY;
-			}
-
-			nv_wr32(priv, 0x409614, 0x00000070);
-			nv_wr32(priv, 0x409614, 0x00000770);
-			nv_wr32(priv, 0x40802c, 0x00000001);
-		}
-
-		if (priv->data == NULL) {
-			int ret = nvc0_grctx_generate(priv);
-			if (ret) {
-				nv_error(priv, "failed to construct context\n");
-				return ret;
-			}
-		}
-
-		return 0;
-	} else
-	if (!oclass->fecs.ucode) {
-		return -ENOSYS;
-	}
-
-	/* load HUB microcode */
-	nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
-	nv_wr32(priv, 0x4091c0, 0x01000000);
-	for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++)
-		nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]);
-
-	nv_wr32(priv, 0x409180, 0x01000000);
-	for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) {
-		if ((i & 0x3f) == 0)
-			nv_wr32(priv, 0x409188, i >> 6);
-		nv_wr32(priv, 0x409184, oclass->fecs.ucode->code.data[i]);
-	}
-
-	/* load GPC microcode */
-	nv_wr32(priv, 0x41a1c0, 0x01000000);
-	for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++)
-		nv_wr32(priv, 0x41a1c4, oclass->gpccs.ucode->data.data[i]);
-
-	nv_wr32(priv, 0x41a180, 0x01000000);
-	for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) {
-		if ((i & 0x3f) == 0)
-			nv_wr32(priv, 0x41a188, i >> 6);
-		nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]);
-	}
-	nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
-
-	/* load register lists */
-	nvc0_graph_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000);
-	nvc0_graph_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000);
-	nvc0_graph_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800);
-	nvc0_graph_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00);
-
-	/* start HUB ucode running, it'll init the GPCs */
-	nv_wr32(priv, 0x40910c, 0x00000000);
-	nv_wr32(priv, 0x409100, 0x00000002);
-	if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) {
-		nv_error(priv, "HUB_INIT timed out\n");
-		nvc0_graph_ctxctl_debug(priv);
-		return -EBUSY;
-	}
-
-	priv->size = nv_rd32(priv, 0x409804);
-	if (priv->data == NULL) {
-		int ret = nvc0_grctx_generate(priv);
-		if (ret) {
-			nv_error(priv, "failed to construct context\n");
-			return ret;
-		}
-	}
-
-	return 0;
-}
-
-int
-nvc0_graph_init(struct nouveau_object *object)
-{
-	struct nvc0_graph_oclass *oclass = (void *)object->oclass;
-	struct nvc0_graph_priv *priv = (void *)object;
-	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
-	u32 data[TPC_MAX / 8] = {};
-	u8  tpcnr[GPC_MAX];
-	int gpc, tpc, rop;
-	int ret, i;
-
-	ret = nouveau_graph_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
-	nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
-	nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000);
-	nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000);
-	nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000);
-	nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000);
-	nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
-	nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
-
-	nvc0_graph_mmio(priv, oclass->mmio);
-
-	memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
-	for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
-		do {
-			gpc = (gpc + 1) % priv->gpc_nr;
-		} while (!tpcnr[gpc]);
-		tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
-
-		data[i / 8] |= tpc << ((i % 8) * 4);
-	}
-
-	nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
-	nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
-	nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
-	nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
-
-	for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
-			priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
-			priv->tpc_total);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
-	}
-
-	if (nv_device(priv)->chipset != 0xd7)
-		nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918);
-	else
-		nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
-
-	nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
-
-	nv_wr32(priv, 0x400500, 0x00010001);
-
-	nv_wr32(priv, 0x400100, 0xffffffff);
-	nv_wr32(priv, 0x40013c, 0xffffffff);
-
-	nv_wr32(priv, 0x409c24, 0x000f0000);
-	nv_wr32(priv, 0x404000, 0xc0000000);
-	nv_wr32(priv, 0x404600, 0xc0000000);
-	nv_wr32(priv, 0x408030, 0xc0000000);
-	nv_wr32(priv, 0x40601c, 0xc0000000);
-	nv_wr32(priv, 0x404490, 0xc0000000);
-	nv_wr32(priv, 0x406018, 0xc0000000);
-	nv_wr32(priv, 0x405840, 0xc0000000);
-	nv_wr32(priv, 0x405844, 0x00ffffff);
-	nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
-	nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
-
-	for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
-		for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
-		}
-		nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
-	}
-
-	for (rop = 0; rop < priv->rop_nr; rop++) {
-		nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
-		nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
-		nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
-		nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
-	}
-
-	nv_wr32(priv, 0x400108, 0xffffffff);
-	nv_wr32(priv, 0x400138, 0xffffffff);
-	nv_wr32(priv, 0x400118, 0xffffffff);
-	nv_wr32(priv, 0x400130, 0xffffffff);
-	nv_wr32(priv, 0x40011c, 0xffffffff);
-	nv_wr32(priv, 0x400134, 0xffffffff);
-
-	nv_wr32(priv, 0x400054, 0x34ce3464);
-
-	nvc0_graph_zbc_init(priv);
-
-	return nvc0_graph_init_ctxctl(priv);
-}
-
-static void
-nvc0_graph_dtor_fw(struct nvc0_graph_fuc *fuc)
-{
-	kfree(fuc->data);
-	fuc->data = NULL;
-}
-
-int
-nvc0_graph_ctor_fw(struct nvc0_graph_priv *priv, const char *fwname,
-		   struct nvc0_graph_fuc *fuc)
-{
-	struct nouveau_device *device = nv_device(priv);
-	const struct firmware *fw;
-	char f[32];
-	int ret;
-
-	snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname);
-	ret = request_firmware(&fw, f, nv_device_base(device));
-	if (ret) {
-		snprintf(f, sizeof(f), "nouveau/%s", fwname);
-		ret = request_firmware(&fw, f, nv_device_base(device));
-		if (ret) {
-			nv_error(priv, "failed to load %s\n", fwname);
-			return ret;
-		}
-	}
-
-	fuc->size = fw->size;
-	fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
-	release_firmware(fw);
-	return (fuc->data != NULL) ? 0 : -ENOMEM;
-}
-
-void
-nvc0_graph_dtor(struct nouveau_object *object)
-{
-	struct nvc0_graph_priv *priv = (void *)object;
-
-	kfree(priv->data);
-
-	nvc0_graph_dtor_fw(&priv->fuc409c);
-	nvc0_graph_dtor_fw(&priv->fuc409d);
-	nvc0_graph_dtor_fw(&priv->fuc41ac);
-	nvc0_graph_dtor_fw(&priv->fuc41ad);
-
-	nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
-	nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
-
-	nouveau_graph_destroy(&priv->base);
-}
-
-int
-nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *bclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nvc0_graph_oclass *oclass = (void *)bclass;
-	struct nouveau_device *device = nv_device(parent);
-	struct nvc0_graph_priv *priv;
-	bool use_ext_fw, enable;
-	int ret, i, j;
-
-	use_ext_fw = nouveau_boolopt(device->cfgopt, "NvGrUseFW",
-				     oclass->fecs.ucode == NULL);
-	enable = use_ext_fw || oclass->fecs.ucode != NULL;
-
-	ret = nouveau_graph_create(parent, engine, bclass, enable, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x08001000;
-	nv_subdev(priv)->intr = nvc0_graph_intr;
-
-	priv->base.units = nvc0_graph_units;
-
-	if (use_ext_fw) {
-		nv_info(priv, "using external firmware\n");
-		if (nvc0_graph_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
-		    nvc0_graph_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
-		    nvc0_graph_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
-		    nvc0_graph_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
-			return -ENODEV;
-		priv->firmware = true;
-	}
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
-				&priv->unk4188b4);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
-				&priv->unk4188b8);
-	if (ret)
-		return ret;
-
-	for (i = 0; i < 0x1000; i += 4) {
-		nv_wo32(priv->unk4188b4, i, 0x00000010);
-		nv_wo32(priv->unk4188b8, i, 0x00000010);
-	}
-
-	priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16;
-	priv->gpc_nr =  nv_rd32(priv, 0x409604) & 0x0000001f;
-	for (i = 0; i < priv->gpc_nr; i++) {
-		priv->tpc_nr[i]  = nv_rd32(priv, GPC_UNIT(i, 0x2608));
-		priv->tpc_total += priv->tpc_nr[i];
-		priv->ppc_nr[i]  = oclass->ppc_nr;
-		for (j = 0; j < priv->ppc_nr[i]; j++) {
-			u8 mask = nv_rd32(priv, GPC_UNIT(i, 0x0c30 + (j * 4)));
-			priv->ppc_tpc_nr[i][j] = hweight8(mask);
-		}
-	}
-
-	/*XXX: these need figuring out... though it might not even matter */
-	switch (nv_device(priv)->chipset) {
-	case 0xc0:
-		if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */
-			priv->magic_not_rop_nr = 0x07;
-		} else
-		if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */
-			priv->magic_not_rop_nr = 0x05;
-		} else
-		if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */
-			priv->magic_not_rop_nr = 0x06;
-		}
-		break;
-	case 0xc3: /* 450, 4/0/0/0, 2 */
-		priv->magic_not_rop_nr = 0x03;
-		break;
-	case 0xc4: /* 460, 3/4/0/0, 4 */
-		priv->magic_not_rop_nr = 0x01;
-		break;
-	case 0xc1: /* 2/0/0/0, 1 */
-		priv->magic_not_rop_nr = 0x01;
-		break;
-	case 0xc8: /* 4/4/3/4, 5 */
-		priv->magic_not_rop_nr = 0x06;
-		break;
-	case 0xce: /* 4/4/0/0, 4 */
-		priv->magic_not_rop_nr = 0x03;
-		break;
-	case 0xcf: /* 4/0/0/0, 3 */
-		priv->magic_not_rop_nr = 0x03;
-		break;
-	case 0xd7:
-	case 0xd9: /* 1/0/0/0, 1 */
-		priv->magic_not_rop_nr = 0x01;
-		break;
-	}
-
-	nv_engine(priv)->cclass = *oclass->cclass;
-	nv_engine(priv)->sclass =  oclass->sclass;
-	return 0;
-}
-
-#include "fuc/hubnvc0.fuc.h"
-
-struct nvc0_graph_ucode
-nvc0_graph_fecs_ucode = {
-	.code.data = nvc0_grhub_code,
-	.code.size = sizeof(nvc0_grhub_code),
-	.data.data = nvc0_grhub_data,
-	.data.size = sizeof(nvc0_grhub_data),
-};
-
-#include "fuc/gpcnvc0.fuc.h"
-
-struct nvc0_graph_ucode
-nvc0_graph_gpccs_ucode = {
-	.code.data = nvc0_grgpc_code,
-	.code.size = sizeof(nvc0_grgpc_code),
-	.data.data = nvc0_grgpc_data,
-	.data.size = sizeof(nvc0_grgpc_data),
-};
-
-struct nouveau_oclass *
-nvc0_graph_oclass = &(struct nvc0_graph_oclass) {
-	.base.handle = NV_ENGINE(GR, 0xc0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nvc0_graph_init,
-		.fini = _nouveau_graph_fini,
-	},
-	.cclass = &nvc0_grctx_oclass,
-	.sclass =  nvc0_graph_sclass,
-	.mmio = nvc0_graph_pack_mmio,
-	.fecs.ucode = &nvc0_graph_fecs_ucode,
-	.gpccs.ucode = &nvc0_graph_gpccs_ucode,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
deleted file mode 100644
index 7ed9e89c3435..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * Copyright 2010 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#ifndef __NVC0_GRAPH_H__
-#define __NVC0_GRAPH_H__
-
-#include <core/client.h>
-#include <core/handle.h>
-#include <core/gpuobj.h>
-#include <core/option.h>
-
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/fb.h>
-#include <subdev/vm.h>
-#include <subdev/bar.h>
-#include <subdev/timer.h>
-#include <subdev/mc.h>
-#include <subdev/ltc.h>
-
-#include <engine/fifo.h>
-#include <engine/graph.h>
-
-#include "fuc/os.h"
-
-#define GPC_MAX 32
-#define TPC_MAX (GPC_MAX * 8)
-
-#define ROP_BCAST(r)      (0x408800 + (r))
-#define ROP_UNIT(u, r)    (0x410000 + (u) * 0x400 + (r))
-#define GPC_BCAST(r)      (0x418000 + (r))
-#define GPC_UNIT(t, r)    (0x500000 + (t) * 0x8000 + (r))
-#define PPC_UNIT(t, m, r) (0x503000 + (t) * 0x8000 + (m) * 0x200 + (r))
-#define TPC_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r))
-
-struct nvc0_graph_data {
-	u32 size;
-	u32 align;
-	u32 access;
-};
-
-struct nvc0_graph_mmio {
-	u32 addr;
-	u32 data;
-	u32 shift;
-	int buffer;
-};
-
-struct nvc0_graph_fuc {
-	u32 *data;
-	u32  size;
-};
-
-struct nvc0_graph_zbc_color {
-	u32 format;
-	u32 ds[4];
-	u32 l2[4];
-};
-
-struct nvc0_graph_zbc_depth {
-	u32 format;
-	u32 ds;
-	u32 l2;
-};
-
-struct nvc0_graph_priv {
-	struct nouveau_graph base;
-
-	struct nvc0_graph_fuc fuc409c;
-	struct nvc0_graph_fuc fuc409d;
-	struct nvc0_graph_fuc fuc41ac;
-	struct nvc0_graph_fuc fuc41ad;
-	bool firmware;
-
-	struct nvc0_graph_zbc_color zbc_color[NOUVEAU_LTC_MAX_ZBC_CNT];
-	struct nvc0_graph_zbc_depth zbc_depth[NOUVEAU_LTC_MAX_ZBC_CNT];
-
-	u8 rop_nr;
-	u8 gpc_nr;
-	u8 tpc_nr[GPC_MAX];
-	u8 tpc_total;
-	u8 ppc_nr[GPC_MAX];
-	u8 ppc_tpc_nr[GPC_MAX][4];
-
-	struct nouveau_gpuobj *unk4188b4;
-	struct nouveau_gpuobj *unk4188b8;
-
-	struct nvc0_graph_data mmio_data[4];
-	struct nvc0_graph_mmio mmio_list[4096/8];
-	u32  size;
-	u32 *data;
-
-	u8 magic_not_rop_nr;
-};
-
-struct nvc0_graph_chan {
-	struct nouveau_graph_chan base;
-
-	struct nouveau_gpuobj *mmio;
-	struct nouveau_vma mmio_vma;
-	int mmio_nr;
-	struct {
-		struct nouveau_gpuobj *mem;
-		struct nouveau_vma vma;
-	} data[4];
-};
-
-int  nvc0_graph_context_ctor(struct nouveau_object *, struct nouveau_object *,
-			     struct nouveau_oclass *, void *, u32,
-			     struct nouveau_object **);
-void nvc0_graph_context_dtor(struct nouveau_object *);
-
-void nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *);
-
-u64  nvc0_graph_units(struct nouveau_graph *);
-int  nvc0_graph_ctor(struct nouveau_object *, struct nouveau_object *,
-		     struct nouveau_oclass *, void *data, u32 size,
-		     struct nouveau_object **);
-void nvc0_graph_dtor(struct nouveau_object *);
-int  nvc0_graph_init(struct nouveau_object *);
-void nvc0_graph_zbc_init(struct nvc0_graph_priv *);
-
-int  nve4_graph_fini(struct nouveau_object *, bool);
-int  nve4_graph_init(struct nouveau_object *);
-
-int  nvf0_graph_fini(struct nouveau_object *, bool);
-
-extern struct nouveau_ofuncs nvc0_fermi_ofuncs;
-
-extern struct nouveau_oclass nvc0_graph_sclass[];
-extern struct nouveau_omthds nvc0_graph_9097_omthds[];
-extern struct nouveau_omthds nvc0_graph_90c0_omthds[];
-extern struct nouveau_oclass nvc8_graph_sclass[];
-extern struct nouveau_oclass nvf0_graph_sclass[];
-
-struct nvc0_graph_init {
-	u32 addr;
-	u8  count;
-	u8  pitch;
-	u32 data;
-};
-
-struct nvc0_graph_pack {
-	const struct nvc0_graph_init *init;
-	u32 type;
-};
-
-#define pack_for_each_init(init, pack, head)                                   \
-	for (pack = head; pack && pack->init; pack++)                          \
-		  for (init = pack->init; init && init->count; init++)
-
-struct nvc0_graph_ucode {
-	struct nvc0_graph_fuc code;
-	struct nvc0_graph_fuc data;
-};
-
-extern struct nvc0_graph_ucode nvc0_graph_fecs_ucode;
-extern struct nvc0_graph_ucode nvc0_graph_gpccs_ucode;
-
-extern struct nvc0_graph_ucode nvf0_graph_fecs_ucode;
-extern struct nvc0_graph_ucode nvf0_graph_gpccs_ucode;
-
-struct nvc0_graph_oclass {
-	struct nouveau_oclass base;
-	struct nouveau_oclass **cclass;
-	struct nouveau_oclass *sclass;
-	const struct nvc0_graph_pack *mmio;
-	struct {
-		struct nvc0_graph_ucode *ucode;
-	} fecs;
-	struct {
-		struct nvc0_graph_ucode *ucode;
-	} gpccs;
-	int ppc_nr;
-};
-
-void nvc0_graph_mmio(struct nvc0_graph_priv *, const struct nvc0_graph_pack *);
-void nvc0_graph_icmd(struct nvc0_graph_priv *, const struct nvc0_graph_pack *);
-void nvc0_graph_mthd(struct nvc0_graph_priv *, const struct nvc0_graph_pack *);
-int  nvc0_graph_init_ctxctl(struct nvc0_graph_priv *);
-
-/* register init value lists */
-
-extern const struct nvc0_graph_init nvc0_graph_init_main_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_fe_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_pri_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_rstr2d_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_pd_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_ds_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_scc_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_prop_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_gpc_unk_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_setup_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_crstr_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_setup_1[];
-extern const struct nvc0_graph_init nvc0_graph_init_zcull_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_gpm_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_gpc_unk_1[];
-extern const struct nvc0_graph_init nvc0_graph_init_gcc_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_tpccs_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_tex_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_pe_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_l1c_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_wwdx_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_tpccs_1[];
-extern const struct nvc0_graph_init nvc0_graph_init_mpc_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_be_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_fe_1[];
-extern const struct nvc0_graph_init nvc0_graph_init_pe_1[];
-
-extern const struct nvc0_graph_init nvc4_graph_init_ds_0[];
-extern const struct nvc0_graph_init nvc4_graph_init_tex_0[];
-extern const struct nvc0_graph_init nvc4_graph_init_sm_0[];
-
-extern const struct nvc0_graph_init nvc1_graph_init_gpc_unk_0[];
-extern const struct nvc0_graph_init nvc1_graph_init_setup_1[];
-
-extern const struct nvc0_graph_init nvd9_graph_init_pd_0[];
-extern const struct nvc0_graph_init nvd9_graph_init_ds_0[];
-extern const struct nvc0_graph_init nvd9_graph_init_prop_0[];
-extern const struct nvc0_graph_init nvd9_graph_init_gpm_0[];
-extern const struct nvc0_graph_init nvd9_graph_init_gpc_unk_1[];
-extern const struct nvc0_graph_init nvd9_graph_init_tex_0[];
-extern const struct nvc0_graph_init nvd9_graph_init_sm_0[];
-extern const struct nvc0_graph_init nvd9_graph_init_fe_1[];
-
-extern const struct nvc0_graph_init nvd7_graph_init_pes_0[];
-extern const struct nvc0_graph_init nvd7_graph_init_wwdx_0[];
-extern const struct nvc0_graph_init nvd7_graph_init_cbm_0[];
-
-extern const struct nvc0_graph_init nve4_graph_init_main_0[];
-extern const struct nvc0_graph_init nve4_graph_init_tpccs_0[];
-extern const struct nvc0_graph_init nve4_graph_init_pe_0[];
-extern const struct nvc0_graph_init nve4_graph_init_be_0[];
-extern const struct nvc0_graph_pack nve4_graph_pack_mmio[];
-
-extern const struct nvc0_graph_init nvf0_graph_init_fe_0[];
-extern const struct nvc0_graph_init nvf0_graph_init_ds_0[];
-extern const struct nvc0_graph_init nvf0_graph_init_sked_0[];
-extern const struct nvc0_graph_init nvf0_graph_init_cwd_0[];
-extern const struct nvc0_graph_init nvf0_graph_init_gpc_unk_1[];
-extern const struct nvc0_graph_init nvf0_graph_init_tex_0[];
-extern const struct nvc0_graph_init nvf0_graph_init_sm_0[];
-
-extern const struct nvc0_graph_init nv108_graph_init_gpc_unk_0[];
-
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c
deleted file mode 100644
index 93d58e5b82c2..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nvc1_graph_sclass[] = {
-	{ 0x902d, &nouveau_object_ofuncs },
-	{ 0x9039, &nouveau_object_ofuncs },
-	{ FERMI_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ FERMI_B, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH register lists
- ******************************************************************************/
-
-const struct nvc0_graph_init
-nvc1_graph_init_gpc_unk_0[] = {
-	{ 0x418604,   1, 0x04, 0x00000000 },
-	{ 0x418680,   1, 0x04, 0x00000000 },
-	{ 0x418714,   1, 0x04, 0x00000000 },
-	{ 0x418384,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc1_graph_init_setup_1[] = {
-	{ 0x4188c8,   2, 0x04, 0x00000000 },
-	{ 0x4188d0,   1, 0x04, 0x00010000 },
-	{ 0x4188d4,   1, 0x04, 0x00000001 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc1_graph_init_gpc_unk_1[] = {
-	{ 0x418d00,   1, 0x04, 0x00000000 },
-	{ 0x418f08,   1, 0x04, 0x00000000 },
-	{ 0x418e00,   1, 0x04, 0x00000003 },
-	{ 0x418e08,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc1_graph_init_pe_0[] = {
-	{ 0x41980c,   1, 0x04, 0x00000010 },
-	{ 0x419810,   1, 0x04, 0x00000000 },
-	{ 0x419814,   1, 0x04, 0x00000004 },
-	{ 0x419844,   1, 0x04, 0x00000000 },
-	{ 0x41984c,   1, 0x04, 0x00005bc5 },
-	{ 0x419850,   4, 0x04, 0x00000000 },
-	{ 0x419880,   1, 0x04, 0x00000002 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvc1_graph_pack_mmio[] = {
-	{ nvc0_graph_init_main_0 },
-	{ nvc0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvc0_graph_init_pd_0 },
-	{ nvc4_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvc0_graph_init_prop_0 },
-	{ nvc1_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc1_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvc0_graph_init_gpm_0 },
-	{ nvc1_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nvc0_graph_init_tpccs_0 },
-	{ nvc4_graph_init_tex_0 },
-	{ nvc1_graph_init_pe_0 },
-	{ nvc0_graph_init_l1c_0 },
-	{ nvc0_graph_init_wwdx_0 },
-	{ nvc0_graph_init_tpccs_1 },
-	{ nvc0_graph_init_mpc_0 },
-	{ nvc4_graph_init_sm_0 },
-	{ nvc0_graph_init_be_0 },
-	{ nvc0_graph_init_fe_1 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-struct nouveau_oclass *
-nvc1_graph_oclass = &(struct nvc0_graph_oclass) {
-	.base.handle = NV_ENGINE(GR, 0xc1),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nvc0_graph_init,
-		.fini = _nouveau_graph_fini,
-	},
-	.cclass = &nvc1_grctx_oclass,
-	.sclass = nvc1_graph_sclass,
-	.mmio = nvc1_graph_pack_mmio,
-	.fecs.ucode = &nvc0_graph_fecs_ucode,
-	.gpccs.ucode = &nvc0_graph_gpccs_ucode,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc4.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc4.c
deleted file mode 100644
index e82e70c53132..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc4.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * PGRAPH register lists
- ******************************************************************************/
-
-const struct nvc0_graph_init
-nvc4_graph_init_ds_0[] = {
-	{ 0x405844,   1, 0x04, 0x00ffffff },
-	{ 0x405850,   1, 0x04, 0x00000000 },
-	{ 0x405900,   1, 0x04, 0x00002834 },
-	{ 0x405908,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc4_graph_init_tex_0[] = {
-	{ 0x419ab0,   1, 0x04, 0x00000000 },
-	{ 0x419ac8,   1, 0x04, 0x00000000 },
-	{ 0x419ab8,   1, 0x04, 0x000000e7 },
-	{ 0x419abc,   2, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvc4_graph_init_pe_0[] = {
-	{ 0x41980c,   3, 0x04, 0x00000000 },
-	{ 0x419844,   1, 0x04, 0x00000000 },
-	{ 0x41984c,   1, 0x04, 0x00005bc5 },
-	{ 0x419850,   4, 0x04, 0x00000000 },
-	{ 0x419880,   1, 0x04, 0x00000002 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvc4_graph_init_sm_0[] = {
-	{ 0x419e00,   1, 0x04, 0x00000000 },
-	{ 0x419ea0,   1, 0x04, 0x00000000 },
-	{ 0x419ea4,   1, 0x04, 0x00000100 },
-	{ 0x419ea8,   1, 0x04, 0x00001100 },
-	{ 0x419eac,   1, 0x04, 0x11100702 },
-	{ 0x419eb0,   1, 0x04, 0x00000003 },
-	{ 0x419eb4,   4, 0x04, 0x00000000 },
-	{ 0x419ec8,   1, 0x04, 0x0e063818 },
-	{ 0x419ecc,   1, 0x04, 0x0e060e06 },
-	{ 0x419ed0,   1, 0x04, 0x00003818 },
-	{ 0x419ed4,   1, 0x04, 0x011104f1 },
-	{ 0x419edc,   1, 0x04, 0x00000000 },
-	{ 0x419f00,   1, 0x04, 0x00000000 },
-	{ 0x419f2c,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvc4_graph_pack_mmio[] = {
-	{ nvc0_graph_init_main_0 },
-	{ nvc0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvc0_graph_init_pd_0 },
-	{ nvc4_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvc0_graph_init_prop_0 },
-	{ nvc0_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc0_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvc0_graph_init_gpm_0 },
-	{ nvc0_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nvc0_graph_init_tpccs_0 },
-	{ nvc4_graph_init_tex_0 },
-	{ nvc4_graph_init_pe_0 },
-	{ nvc0_graph_init_l1c_0 },
-	{ nvc0_graph_init_wwdx_0 },
-	{ nvc0_graph_init_tpccs_1 },
-	{ nvc0_graph_init_mpc_0 },
-	{ nvc4_graph_init_sm_0 },
-	{ nvc0_graph_init_be_0 },
-	{ nvc0_graph_init_fe_1 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-struct nouveau_oclass *
-nvc4_graph_oclass = &(struct nvc0_graph_oclass) {
-	.base.handle = NV_ENGINE(GR, 0xc3),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nvc0_graph_init,
-		.fini = _nouveau_graph_fini,
-	},
-	.cclass = &nvc4_grctx_oclass,
-	.sclass = nvc0_graph_sclass,
-	.mmio = nvc4_graph_pack_mmio,
-	.fecs.ucode = &nvc0_graph_fecs_ucode,
-	.gpccs.ucode = &nvc0_graph_gpccs_ucode,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c
deleted file mode 100644
index 692e1eda0eb4..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-struct nouveau_oclass
-nvc8_graph_sclass[] = {
-	{ 0x902d, &nouveau_object_ofuncs },
-	{ 0x9039, &nouveau_object_ofuncs },
-	{ FERMI_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ FERMI_B, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ FERMI_C, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH register lists
- ******************************************************************************/
-
-static const struct nvc0_graph_init
-nvc8_graph_init_sm_0[] = {
-	{ 0x419e00,   1, 0x04, 0x00000000 },
-	{ 0x419ea0,   1, 0x04, 0x00000000 },
-	{ 0x419ea4,   1, 0x04, 0x00000100 },
-	{ 0x419ea8,   1, 0x04, 0x00001100 },
-	{ 0x419eac,   1, 0x04, 0x11100f02 },
-	{ 0x419eb0,   1, 0x04, 0x00000003 },
-	{ 0x419eb4,   4, 0x04, 0x00000000 },
-	{ 0x419ec8,   1, 0x04, 0x06060618 },
-	{ 0x419ed0,   1, 0x04, 0x0eff0e38 },
-	{ 0x419ed4,   1, 0x04, 0x011104f1 },
-	{ 0x419edc,   1, 0x04, 0x00000000 },
-	{ 0x419f00,   1, 0x04, 0x00000000 },
-	{ 0x419f2c,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvc8_graph_pack_mmio[] = {
-	{ nvc0_graph_init_main_0 },
-	{ nvc0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvc0_graph_init_pd_0 },
-	{ nvc0_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvc0_graph_init_prop_0 },
-	{ nvc0_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc1_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvc0_graph_init_gpm_0 },
-	{ nvc0_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nvc0_graph_init_tpccs_0 },
-	{ nvc0_graph_init_tex_0 },
-	{ nvc0_graph_init_pe_0 },
-	{ nvc0_graph_init_l1c_0 },
-	{ nvc0_graph_init_wwdx_0 },
-	{ nvc0_graph_init_tpccs_1 },
-	{ nvc0_graph_init_mpc_0 },
-	{ nvc8_graph_init_sm_0 },
-	{ nvc0_graph_init_be_0 },
-	{ nvc0_graph_init_fe_1 },
-	{ nvc0_graph_init_pe_1 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-struct nouveau_oclass *
-nvc8_graph_oclass = &(struct nvc0_graph_oclass) {
-	.base.handle = NV_ENGINE(GR, 0xc8),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nvc0_graph_init,
-		.fini = _nouveau_graph_fini,
-	},
-	.cclass = &nvc8_grctx_oclass,
-	.sclass = nvc8_graph_sclass,
-	.mmio = nvc8_graph_pack_mmio,
-	.fecs.ucode = &nvc0_graph_fecs_ucode,
-	.gpccs.ucode = &nvc0_graph_gpccs_ucode,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c
deleted file mode 100644
index 41e8445c7eea..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * PGRAPH register lists
- ******************************************************************************/
-
-static const struct nvc0_graph_init
-nvd7_graph_init_pe_0[] = {
-	{ 0x41980c,   1, 0x04, 0x00000010 },
-	{ 0x419844,   1, 0x04, 0x00000000 },
-	{ 0x41984c,   1, 0x04, 0x00005bc8 },
-	{ 0x419850,   3, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvd7_graph_init_pes_0[] = {
-	{ 0x41be04,   1, 0x04, 0x00000000 },
-	{ 0x41be08,   1, 0x04, 0x00000004 },
-	{ 0x41be0c,   1, 0x04, 0x00000000 },
-	{ 0x41be10,   1, 0x04, 0x003b8bc7 },
-	{ 0x41be14,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvd7_graph_init_wwdx_0[] = {
-	{ 0x41bfd4,   1, 0x04, 0x00800000 },
-	{ 0x41bfdc,   1, 0x04, 0x00000000 },
-	{ 0x41bff8,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvd7_graph_init_cbm_0[] = {
-	{ 0x41becc,   1, 0x04, 0x00000000 },
-	{ 0x41bee8,   2, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvd7_graph_pack_mmio[] = {
-	{ nvc0_graph_init_main_0 },
-	{ nvc0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvd9_graph_init_pd_0 },
-	{ nvd9_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvd9_graph_init_prop_0 },
-	{ nvc1_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc1_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvd9_graph_init_gpm_0 },
-	{ nvd9_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nvc0_graph_init_tpccs_0 },
-	{ nvd9_graph_init_tex_0 },
-	{ nvd7_graph_init_pe_0 },
-	{ nvc0_graph_init_l1c_0 },
-	{ nvc0_graph_init_mpc_0 },
-	{ nvd9_graph_init_sm_0 },
-	{ nvd7_graph_init_pes_0 },
-	{ nvd7_graph_init_wwdx_0 },
-	{ nvd7_graph_init_cbm_0 },
-	{ nvc0_graph_init_be_0 },
-	{ nvd9_graph_init_fe_1 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-#include "fuc/hubnvd7.fuc.h"
-
-struct nvc0_graph_ucode
-nvd7_graph_fecs_ucode = {
-	.code.data = nvd7_grhub_code,
-	.code.size = sizeof(nvd7_grhub_code),
-	.data.data = nvd7_grhub_data,
-	.data.size = sizeof(nvd7_grhub_data),
-};
-
-#include "fuc/gpcnvd7.fuc.h"
-
-struct nvc0_graph_ucode
-nvd7_graph_gpccs_ucode = {
-	.code.data = nvd7_grgpc_code,
-	.code.size = sizeof(nvd7_grgpc_code),
-	.data.data = nvd7_grgpc_data,
-	.data.size = sizeof(nvd7_grgpc_data),
-};
-
-struct nouveau_oclass *
-nvd7_graph_oclass = &(struct nvc0_graph_oclass) {
-	.base.handle = NV_ENGINE(GR, 0xd7),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nvc0_graph_init,
-		.fini = _nouveau_graph_fini,
-	},
-	.cclass = &nvd7_grctx_oclass,
-	.sclass = nvc8_graph_sclass,
-	.mmio = nvd7_graph_pack_mmio,
-	.fecs.ucode = &nvd7_graph_fecs_ucode,
-	.gpccs.ucode = &nvd7_graph_gpccs_ucode,
-	.ppc_nr = 1,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c
deleted file mode 100644
index 00fdf202fb92..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * PGRAPH register lists
- ******************************************************************************/
-
-const struct nvc0_graph_init
-nvd9_graph_init_pd_0[] = {
-	{ 0x406024,   1, 0x04, 0x00000000 },
-	{ 0x4064f0,   3, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvd9_graph_init_ds_0[] = {
-	{ 0x405844,   1, 0x04, 0x00ffffff },
-	{ 0x405850,   1, 0x04, 0x00000000 },
-	{ 0x405900,   1, 0x04, 0x00002834 },
-	{ 0x405908,   1, 0x04, 0x00000000 },
-	{ 0x405928,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvd9_graph_init_prop_0[] = {
-	{ 0x418408,   1, 0x04, 0x00000000 },
-	{ 0x4184a0,   3, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvd9_graph_init_gpm_0[] = {
-	{ 0x418c04,   1, 0x04, 0x00000000 },
-	{ 0x418c64,   2, 0x04, 0x00000000 },
-	{ 0x418c88,   1, 0x04, 0x00000000 },
-	{ 0x418cb4,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvd9_graph_init_gpc_unk_1[] = {
-	{ 0x418d00,   1, 0x04, 0x00000000 },
-	{ 0x418d28,   2, 0x04, 0x00000000 },
-	{ 0x418f00,   1, 0x04, 0x00000000 },
-	{ 0x418f08,   1, 0x04, 0x00000000 },
-	{ 0x418f20,   2, 0x04, 0x00000000 },
-	{ 0x418e00,   1, 0x04, 0x00000003 },
-	{ 0x418e08,   1, 0x04, 0x00000000 },
-	{ 0x418e1c,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvd9_graph_init_tex_0[] = {
-	{ 0x419ab0,   1, 0x04, 0x00000000 },
-	{ 0x419ac8,   1, 0x04, 0x00000000 },
-	{ 0x419ab8,   1, 0x04, 0x000000e7 },
-	{ 0x419abc,   2, 0x04, 0x00000000 },
-	{ 0x419ab4,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvd9_graph_init_pe_0[] = {
-	{ 0x41980c,   1, 0x04, 0x00000010 },
-	{ 0x419810,   1, 0x04, 0x00000000 },
-	{ 0x419814,   1, 0x04, 0x00000004 },
-	{ 0x419844,   1, 0x04, 0x00000000 },
-	{ 0x41984c,   1, 0x04, 0x0000a918 },
-	{ 0x419850,   4, 0x04, 0x00000000 },
-	{ 0x419880,   1, 0x04, 0x00000002 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvd9_graph_init_wwdx_0[] = {
-	{ 0x419bd4,   1, 0x04, 0x00800000 },
-	{ 0x419bdc,   1, 0x04, 0x00000000 },
-	{ 0x419bf8,   2, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvd9_graph_init_tpccs_1[] = {
-	{ 0x419d2c,   1, 0x04, 0x00000000 },
-	{ 0x419d48,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvd9_graph_init_sm_0[] = {
-	{ 0x419e00,   1, 0x04, 0x00000000 },
-	{ 0x419ea0,   1, 0x04, 0x00000000 },
-	{ 0x419ea4,   1, 0x04, 0x00000100 },
-	{ 0x419ea8,   1, 0x04, 0x02001100 },
-	{ 0x419eac,   1, 0x04, 0x11100702 },
-	{ 0x419eb0,   1, 0x04, 0x00000003 },
-	{ 0x419eb4,   4, 0x04, 0x00000000 },
-	{ 0x419ec8,   1, 0x04, 0x0e063818 },
-	{ 0x419ecc,   1, 0x04, 0x0e060e06 },
-	{ 0x419ed0,   1, 0x04, 0x00003818 },
-	{ 0x419ed4,   1, 0x04, 0x011104f1 },
-	{ 0x419edc,   1, 0x04, 0x00000000 },
-	{ 0x419f00,   1, 0x04, 0x00000000 },
-	{ 0x419f2c,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvd9_graph_init_fe_1[] = {
-	{ 0x40402c,   1, 0x04, 0x00000000 },
-	{ 0x4040f0,   1, 0x04, 0x00000000 },
-	{ 0x404174,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvd9_graph_pack_mmio[] = {
-	{ nvc0_graph_init_main_0 },
-	{ nvc0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvd9_graph_init_pd_0 },
-	{ nvd9_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvd9_graph_init_prop_0 },
-	{ nvc1_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc1_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvd9_graph_init_gpm_0 },
-	{ nvd9_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nvc0_graph_init_tpccs_0 },
-	{ nvd9_graph_init_tex_0 },
-	{ nvd9_graph_init_pe_0 },
-	{ nvc0_graph_init_l1c_0 },
-	{ nvd9_graph_init_wwdx_0 },
-	{ nvd9_graph_init_tpccs_1 },
-	{ nvc0_graph_init_mpc_0 },
-	{ nvd9_graph_init_sm_0 },
-	{ nvc0_graph_init_be_0 },
-	{ nvd9_graph_init_fe_1 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-struct nouveau_oclass *
-nvd9_graph_oclass = &(struct nvc0_graph_oclass) {
-	.base.handle = NV_ENGINE(GR, 0xd9),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nvc0_graph_init,
-		.fini = _nouveau_graph_fini,
-	},
-	.cclass = &nvd9_grctx_oclass,
-	.sclass = nvc8_graph_sclass,
-	.mmio = nvd9_graph_pack_mmio,
-	.fecs.ucode = &nvc0_graph_fecs_ucode,
-	.gpccs.ucode = &nvc0_graph_gpccs_ucode,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c b/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
deleted file mode 100644
index 0c71f5c67ae0..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
+++ /dev/null
@@ -1,347 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include <subdev/pwr.h>
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nve4_graph_sclass[] = {
-	{ 0x902d, &nouveau_object_ofuncs },
-	{ 0xa040, &nouveau_object_ofuncs },
-	{ KEPLER_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH register lists
- ******************************************************************************/
-
-const struct nvc0_graph_init
-nve4_graph_init_main_0[] = {
-	{ 0x400080,   1, 0x04, 0x003083c2 },
-	{ 0x400088,   1, 0x04, 0x0001ffe7 },
-	{ 0x40008c,   1, 0x04, 0x00000000 },
-	{ 0x400090,   1, 0x04, 0x00000030 },
-	{ 0x40013c,   1, 0x04, 0x003901f7 },
-	{ 0x400140,   1, 0x04, 0x00000100 },
-	{ 0x400144,   1, 0x04, 0x00000000 },
-	{ 0x400148,   1, 0x04, 0x00000110 },
-	{ 0x400138,   1, 0x04, 0x00000000 },
-	{ 0x400130,   2, 0x04, 0x00000000 },
-	{ 0x400124,   1, 0x04, 0x00000002 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nve4_graph_init_ds_0[] = {
-	{ 0x405844,   1, 0x04, 0x00ffffff },
-	{ 0x405850,   1, 0x04, 0x00000000 },
-	{ 0x405900,   1, 0x04, 0x0000ff34 },
-	{ 0x405908,   1, 0x04, 0x00000000 },
-	{ 0x405928,   2, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nve4_graph_init_sked_0[] = {
-	{ 0x407010,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nve4_graph_init_cwd_0[] = {
-	{ 0x405b50,   1, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nve4_graph_init_gpc_unk_1[] = {
-	{ 0x418d00,   1, 0x04, 0x00000000 },
-	{ 0x418d28,   2, 0x04, 0x00000000 },
-	{ 0x418f00,   1, 0x04, 0x00000000 },
-	{ 0x418f08,   1, 0x04, 0x00000000 },
-	{ 0x418f20,   2, 0x04, 0x00000000 },
-	{ 0x418e00,   1, 0x04, 0x00000060 },
-	{ 0x418e08,   1, 0x04, 0x00000000 },
-	{ 0x418e1c,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nve4_graph_init_tpccs_0[] = {
-	{ 0x419d0c,   1, 0x04, 0x00000000 },
-	{ 0x419d10,   1, 0x04, 0x00000014 },
-	{}
-};
-
-const struct nvc0_graph_init
-nve4_graph_init_pe_0[] = {
-	{ 0x41980c,   1, 0x04, 0x00000010 },
-	{ 0x419844,   1, 0x04, 0x00000000 },
-	{ 0x419850,   1, 0x04, 0x00000004 },
-	{ 0x419854,   2, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nve4_graph_init_l1c_0[] = {
-	{ 0x419c98,   1, 0x04, 0x00000000 },
-	{ 0x419ca8,   1, 0x04, 0x00000000 },
-	{ 0x419cb0,   1, 0x04, 0x01000000 },
-	{ 0x419cb4,   1, 0x04, 0x00000000 },
-	{ 0x419cb8,   1, 0x04, 0x00b08bea },
-	{ 0x419c84,   1, 0x04, 0x00010384 },
-	{ 0x419cbc,   1, 0x04, 0x28137646 },
-	{ 0x419cc0,   2, 0x04, 0x00000000 },
-	{ 0x419c80,   1, 0x04, 0x00020232 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nve4_graph_init_sm_0[] = {
-	{ 0x419e00,   1, 0x04, 0x00000000 },
-	{ 0x419ea0,   1, 0x04, 0x00000000 },
-	{ 0x419ee4,   1, 0x04, 0x00000000 },
-	{ 0x419ea4,   1, 0x04, 0x00000100 },
-	{ 0x419ea8,   1, 0x04, 0x00000000 },
-	{ 0x419eb4,   4, 0x04, 0x00000000 },
-	{ 0x419edc,   1, 0x04, 0x00000000 },
-	{ 0x419f00,   1, 0x04, 0x00000000 },
-	{ 0x419f74,   1, 0x04, 0x00000555 },
-	{}
-};
-
-const struct nvc0_graph_init
-nve4_graph_init_be_0[] = {
-	{ 0x40880c,   1, 0x04, 0x00000000 },
-	{ 0x408850,   1, 0x04, 0x00000004 },
-	{ 0x408910,   9, 0x04, 0x00000000 },
-	{ 0x408950,   1, 0x04, 0x00000000 },
-	{ 0x408954,   1, 0x04, 0x0000ffff },
-	{ 0x408958,   1, 0x04, 0x00000034 },
-	{ 0x408984,   1, 0x04, 0x00000000 },
-	{ 0x408988,   1, 0x04, 0x08040201 },
-	{ 0x40898c,   1, 0x04, 0x80402010 },
-	{}
-};
-
-const struct nvc0_graph_pack
-nve4_graph_pack_mmio[] = {
-	{ nve4_graph_init_main_0 },
-	{ nvc0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvd9_graph_init_pd_0 },
-	{ nve4_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nve4_graph_init_sked_0 },
-	{ nve4_graph_init_cwd_0 },
-	{ nvd9_graph_init_prop_0 },
-	{ nvc1_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc1_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvd9_graph_init_gpm_0 },
-	{ nve4_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nve4_graph_init_tpccs_0 },
-	{ nvd9_graph_init_tex_0 },
-	{ nve4_graph_init_pe_0 },
-	{ nve4_graph_init_l1c_0 },
-	{ nvc0_graph_init_mpc_0 },
-	{ nve4_graph_init_sm_0 },
-	{ nvd7_graph_init_pes_0 },
-	{ nvd7_graph_init_wwdx_0 },
-	{ nvd7_graph_init_cbm_0 },
-	{ nve4_graph_init_be_0 },
-	{ nvc0_graph_init_fe_1 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-int
-nve4_graph_init(struct nouveau_object *object)
-{
-	struct nvc0_graph_oclass *oclass = (void *)object->oclass;
-	struct nvc0_graph_priv *priv = (void *)object;
-	struct nouveau_pwr *ppwr = nouveau_pwr(priv);
-	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
-	u32 data[TPC_MAX / 8] = {};
-	u8  tpcnr[GPC_MAX];
-	int gpc, tpc, rop;
-	int ret, i;
-
-	if (ppwr)
-		ppwr->pgob(ppwr, false);
-
-	ret = nouveau_graph_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
-	nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
-	nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000);
-	nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000);
-	nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000);
-	nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000);
-	nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
-	nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
-
-	nvc0_graph_mmio(priv, oclass->mmio);
-
-	nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
-
-	memset(data, 0x00, sizeof(data));
-	memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
-	for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
-		do {
-			gpc = (gpc + 1) % priv->gpc_nr;
-		} while (!tpcnr[gpc]);
-		tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
-
-		data[i / 8] |= tpc << ((i % 8) * 4);
-	}
-
-	nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
-	nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
-	nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
-	nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
-
-	for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
-			priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
-			priv->tpc_total);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
-	}
-
-	nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
-	nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
-
-	nv_wr32(priv, 0x400500, 0x00010001);
-
-	nv_wr32(priv, 0x400100, 0xffffffff);
-	nv_wr32(priv, 0x40013c, 0xffffffff);
-
-	nv_wr32(priv, 0x409ffc, 0x00000000);
-	nv_wr32(priv, 0x409c14, 0x00003e3e);
-	nv_wr32(priv, 0x409c24, 0x000f0001);
-	nv_wr32(priv, 0x404000, 0xc0000000);
-	nv_wr32(priv, 0x404600, 0xc0000000);
-	nv_wr32(priv, 0x408030, 0xc0000000);
-	nv_wr32(priv, 0x404490, 0xc0000000);
-	nv_wr32(priv, 0x406018, 0xc0000000);
-	nv_wr32(priv, 0x407020, 0x40000000);
-	nv_wr32(priv, 0x405840, 0xc0000000);
-	nv_wr32(priv, 0x405844, 0x00ffffff);
-	nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
-	nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
-
-	for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-		nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
-		for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
-			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
-		}
-		nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
-		nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
-	}
-
-	for (rop = 0; rop < priv->rop_nr; rop++) {
-		nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
-		nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
-		nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
-		nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
-	}
-
-	nv_wr32(priv, 0x400108, 0xffffffff);
-	nv_wr32(priv, 0x400138, 0xffffffff);
-	nv_wr32(priv, 0x400118, 0xffffffff);
-	nv_wr32(priv, 0x400130, 0xffffffff);
-	nv_wr32(priv, 0x40011c, 0xffffffff);
-	nv_wr32(priv, 0x400134, 0xffffffff);
-
-	nv_wr32(priv, 0x400054, 0x34ce3464);
-
-	nvc0_graph_zbc_init(priv);
-
-	return nvc0_graph_init_ctxctl(priv);
-}
-
-#include "fuc/hubnve0.fuc.h"
-
-static struct nvc0_graph_ucode
-nve4_graph_fecs_ucode = {
-	.code.data = nve0_grhub_code,
-	.code.size = sizeof(nve0_grhub_code),
-	.data.data = nve0_grhub_data,
-	.data.size = sizeof(nve0_grhub_data),
-};
-
-#include "fuc/gpcnve0.fuc.h"
-
-static struct nvc0_graph_ucode
-nve4_graph_gpccs_ucode = {
-	.code.data = nve0_grgpc_code,
-	.code.size = sizeof(nve0_grgpc_code),
-	.data.data = nve0_grgpc_data,
-	.data.size = sizeof(nve0_grgpc_data),
-};
-
-struct nouveau_oclass *
-nve4_graph_oclass = &(struct nvc0_graph_oclass) {
-	.base.handle = NV_ENGINE(GR, 0xe4),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nve4_graph_init,
-		.fini = _nouveau_graph_fini,
-	},
-	.cclass = &nve4_grctx_oclass,
-	.sclass = nve4_graph_sclass,
-	.mmio = nve4_graph_pack_mmio,
-	.fecs.ucode = &nve4_graph_fecs_ucode,
-	.gpccs.ucode = &nve4_graph_gpccs_ucode,
-	.ppc_nr = 1,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
deleted file mode 100644
index c306c0f2fc84..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-struct nouveau_oclass
-nvf0_graph_sclass[] = {
-	{ 0x902d, &nouveau_object_ofuncs },
-	{ 0xa140, &nouveau_object_ofuncs },
-	{ KEPLER_B, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ KEPLER_COMPUTE_B, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH register lists
- ******************************************************************************/
-
-const struct nvc0_graph_init
-nvf0_graph_init_fe_0[] = {
-	{ 0x40415c,   1, 0x04, 0x00000000 },
-	{ 0x404170,   1, 0x04, 0x00000000 },
-	{ 0x4041b4,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvf0_graph_init_ds_0[] = {
-	{ 0x405844,   1, 0x04, 0x00ffffff },
-	{ 0x405850,   1, 0x04, 0x00000000 },
-	{ 0x405900,   1, 0x04, 0x0000ff00 },
-	{ 0x405908,   1, 0x04, 0x00000000 },
-	{ 0x405928,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvf0_graph_init_sked_0[] = {
-	{ 0x407010,   1, 0x04, 0x00000000 },
-	{ 0x407040,   1, 0x04, 0x80440424 },
-	{ 0x407048,   1, 0x04, 0x0000000a },
-	{}
-};
-
-const struct nvc0_graph_init
-nvf0_graph_init_cwd_0[] = {
-	{ 0x405b44,   1, 0x04, 0x00000000 },
-	{ 0x405b50,   1, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvf0_graph_init_gpc_unk_1[] = {
-	{ 0x418d00,   1, 0x04, 0x00000000 },
-	{ 0x418d28,   2, 0x04, 0x00000000 },
-	{ 0x418f00,   1, 0x04, 0x00000400 },
-	{ 0x418f08,   1, 0x04, 0x00000000 },
-	{ 0x418f20,   2, 0x04, 0x00000000 },
-	{ 0x418e00,   1, 0x04, 0x00000000 },
-	{ 0x418e08,   1, 0x04, 0x00000000 },
-	{ 0x418e1c,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvf0_graph_init_tex_0[] = {
-	{ 0x419ab0,   1, 0x04, 0x00000000 },
-	{ 0x419ac8,   1, 0x04, 0x00000000 },
-	{ 0x419ab8,   1, 0x04, 0x000000e7 },
-	{ 0x419aec,   1, 0x04, 0x00000000 },
-	{ 0x419abc,   2, 0x04, 0x00000000 },
-	{ 0x419ab4,   1, 0x04, 0x00000000 },
-	{ 0x419aa8,   2, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_init
-nvf0_graph_init_l1c_0[] = {
-	{ 0x419c98,   1, 0x04, 0x00000000 },
-	{ 0x419ca8,   1, 0x04, 0x00000000 },
-	{ 0x419cb0,   1, 0x04, 0x01000000 },
-	{ 0x419cb4,   1, 0x04, 0x00000000 },
-	{ 0x419cb8,   1, 0x04, 0x00b08bea },
-	{ 0x419c84,   1, 0x04, 0x00010384 },
-	{ 0x419cbc,   1, 0x04, 0x281b3646 },
-	{ 0x419cc0,   2, 0x04, 0x00000000 },
-	{ 0x419c80,   1, 0x04, 0x00020230 },
-	{ 0x419ccc,   2, 0x04, 0x00000000 },
-	{}
-};
-
-const struct nvc0_graph_init
-nvf0_graph_init_sm_0[] = {
-	{ 0x419e00,   1, 0x04, 0x00000080 },
-	{ 0x419ea0,   1, 0x04, 0x00000000 },
-	{ 0x419ee4,   1, 0x04, 0x00000000 },
-	{ 0x419ea4,   1, 0x04, 0x00000100 },
-	{ 0x419ea8,   1, 0x04, 0x00000000 },
-	{ 0x419eb4,   1, 0x04, 0x00000000 },
-	{ 0x419ebc,   2, 0x04, 0x00000000 },
-	{ 0x419edc,   1, 0x04, 0x00000000 },
-	{ 0x419f00,   1, 0x04, 0x00000000 },
-	{ 0x419ed0,   1, 0x04, 0x00003234 },
-	{ 0x419f74,   1, 0x04, 0x00015555 },
-	{ 0x419f80,   4, 0x04, 0x00000000 },
-	{}
-};
-
-static const struct nvc0_graph_pack
-nvf0_graph_pack_mmio[] = {
-	{ nve4_graph_init_main_0 },
-	{ nvf0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvd9_graph_init_pd_0 },
-	{ nvf0_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvf0_graph_init_sked_0 },
-	{ nvf0_graph_init_cwd_0 },
-	{ nvd9_graph_init_prop_0 },
-	{ nvc1_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc1_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvd9_graph_init_gpm_0 },
-	{ nvf0_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nve4_graph_init_tpccs_0 },
-	{ nvf0_graph_init_tex_0 },
-	{ nve4_graph_init_pe_0 },
-	{ nvf0_graph_init_l1c_0 },
-	{ nvc0_graph_init_mpc_0 },
-	{ nvf0_graph_init_sm_0 },
-	{ nvd7_graph_init_pes_0 },
-	{ nvd7_graph_init_wwdx_0 },
-	{ nvd7_graph_init_cbm_0 },
-	{ nve4_graph_init_be_0 },
-	{ nvc0_graph_init_fe_1 },
-	{}
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-int
-nvf0_graph_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nvc0_graph_priv *priv = (void *)object;
-	static const struct {
-		u32 addr;
-		u32 data;
-	} magic[] = {
-		{ 0x020520, 0xfffffffc },
-		{ 0x020524, 0xfffffffe },
-		{ 0x020524, 0xfffffffc },
-		{ 0x020524, 0xfffffff8 },
-		{ 0x020524, 0xffffffe0 },
-		{ 0x020530, 0xfffffffe },
-		{ 0x02052c, 0xfffffffa },
-		{ 0x02052c, 0xfffffff0 },
-		{ 0x02052c, 0xffffffc0 },
-		{ 0x02052c, 0xffffff00 },
-		{ 0x02052c, 0xfffffc00 },
-		{ 0x02052c, 0xfffcfc00 },
-		{ 0x02052c, 0xfff0fc00 },
-		{ 0x02052c, 0xff80fc00 },
-		{ 0x020528, 0xfffffffe },
-		{ 0x020528, 0xfffffffc },
-	};
-	int i;
-
-	nv_mask(priv, 0x000200, 0x08001000, 0x00000000);
-	nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000);
-	for (i = 0; i < ARRAY_SIZE(magic); i++) {
-		nv_wr32(priv, magic[i].addr, magic[i].data);
-		nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000);
-	}
-
-	return nouveau_graph_fini(&priv->base, suspend);
-}
-
-#include "fuc/hubnvf0.fuc.h"
-
-struct nvc0_graph_ucode
-nvf0_graph_fecs_ucode = {
-	.code.data = nvf0_grhub_code,
-	.code.size = sizeof(nvf0_grhub_code),
-	.data.data = nvf0_grhub_data,
-	.data.size = sizeof(nvf0_grhub_data),
-};
-
-#include "fuc/gpcnvf0.fuc.h"
-
-struct nvc0_graph_ucode
-nvf0_graph_gpccs_ucode = {
-	.code.data = nvf0_grgpc_code,
-	.code.size = sizeof(nvf0_grgpc_code),
-	.data.data = nvf0_grgpc_data,
-	.data.size = sizeof(nvf0_grgpc_data),
-};
-
-struct nouveau_oclass *
-nvf0_graph_oclass = &(struct nvc0_graph_oclass) {
-	.base.handle = NV_ENGINE(GR, 0xf0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nve4_graph_init,
-		.fini = nvf0_graph_fini,
-	},
-	.cclass = &nvf0_grctx_oclass,
-	.sclass =  nvf0_graph_sclass,
-	.mmio = nvf0_graph_pack_mmio,
-	.fecs.ucode = &nvf0_graph_fecs_ucode,
-	.gpccs.ucode = &nvf0_graph_gpccs_ucode,
-	.ppc_nr = 2,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/regs.h b/drivers/gpu/drm/nouveau/core/engine/graph/regs.h
deleted file mode 100644
index fde8e24415e4..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/regs.h
+++ /dev/null
@@ -1,274 +0,0 @@
-#ifndef __NOUVEAU_GRAPH_REGS_H__
-#define __NOUVEAU_GRAPH_REGS_H__
-
-#define NV04_PGRAPH_DEBUG_0                                0x00400080
-#define NV04_PGRAPH_DEBUG_1                                0x00400084
-#define NV04_PGRAPH_DEBUG_2                                0x00400088
-#define NV04_PGRAPH_DEBUG_3                                0x0040008c
-#define NV10_PGRAPH_DEBUG_4                                0x00400090
-#define NV03_PGRAPH_INTR                                   0x00400100
-#define NV03_PGRAPH_NSTATUS                                0x00400104
-#    define NV04_PGRAPH_NSTATUS_STATE_IN_USE                  (1<<11)
-#    define NV04_PGRAPH_NSTATUS_INVALID_STATE                 (1<<12)
-#    define NV04_PGRAPH_NSTATUS_BAD_ARGUMENT                  (1<<13)
-#    define NV04_PGRAPH_NSTATUS_PROTECTION_FAULT              (1<<14)
-#    define NV10_PGRAPH_NSTATUS_STATE_IN_USE                  (1<<23)
-#    define NV10_PGRAPH_NSTATUS_INVALID_STATE                 (1<<24)
-#    define NV10_PGRAPH_NSTATUS_BAD_ARGUMENT                  (1<<25)
-#    define NV10_PGRAPH_NSTATUS_PROTECTION_FAULT              (1<<26)
-#define NV03_PGRAPH_NSOURCE                                0x00400108
-#    define NV03_PGRAPH_NSOURCE_NOTIFICATION                   (1<<0)
-#    define NV03_PGRAPH_NSOURCE_DATA_ERROR                     (1<<1)
-#    define NV03_PGRAPH_NSOURCE_PROTECTION_ERROR               (1<<2)
-#    define NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION                (1<<3)
-#    define NV03_PGRAPH_NSOURCE_LIMIT_COLOR                    (1<<4)
-#    define NV03_PGRAPH_NSOURCE_LIMIT_ZETA                     (1<<5)
-#    define NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD                   (1<<6)
-#    define NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION               (1<<7)
-#    define NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION               (1<<8)
-#    define NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION               (1<<9)
-#    define NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION               (1<<10)
-#    define NV03_PGRAPH_NSOURCE_STATE_INVALID                 (1<<11)
-#    define NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY                 (1<<12)
-#    define NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE                 (1<<13)
-#    define NV03_PGRAPH_NSOURCE_METHOD_CNT                    (1<<14)
-#    define NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION              (1<<15)
-#    define NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION            (1<<16)
-#    define NV03_PGRAPH_NSOURCE_DMA_WIDTH_A                   (1<<17)
-#    define NV03_PGRAPH_NSOURCE_DMA_WIDTH_B                   (1<<18)
-#define NV03_PGRAPH_INTR_EN                                0x00400140
-#define NV40_PGRAPH_INTR_EN                                0x0040013C
-#    define NV_PGRAPH_INTR_NOTIFY                              (1<<0)
-#    define NV_PGRAPH_INTR_MISSING_HW                          (1<<4)
-#    define NV_PGRAPH_INTR_CONTEXT_SWITCH                     (1<<12)
-#    define NV_PGRAPH_INTR_BUFFER_NOTIFY                      (1<<16)
-#    define NV_PGRAPH_INTR_ERROR                              (1<<20)
-#define NV10_PGRAPH_CTX_CONTROL                            0x00400144
-#define NV10_PGRAPH_CTX_USER                               0x00400148
-#define NV10_PGRAPH_CTX_SWITCH(i)                         (0x0040014C + 0x4*(i))
-#define NV04_PGRAPH_CTX_SWITCH1                            0x00400160
-#define NV10_PGRAPH_CTX_CACHE(i, j)                       (0x00400160	\
-							   + 0x4*(i) + 0x20*(j))
-#define NV04_PGRAPH_CTX_SWITCH2                            0x00400164
-#define NV04_PGRAPH_CTX_SWITCH3                            0x00400168
-#define NV04_PGRAPH_CTX_SWITCH4                            0x0040016C
-#define NV04_PGRAPH_CTX_CONTROL                            0x00400170
-#define NV04_PGRAPH_CTX_USER                               0x00400174
-#define NV04_PGRAPH_CTX_CACHE1                             0x00400180
-#define NV03_PGRAPH_CTX_CONTROL                            0x00400190
-#define NV03_PGRAPH_CTX_USER                               0x00400194
-#define NV04_PGRAPH_CTX_CACHE2                             0x004001A0
-#define NV04_PGRAPH_CTX_CACHE3                             0x004001C0
-#define NV04_PGRAPH_CTX_CACHE4                             0x004001E0
-#define NV40_PGRAPH_CTXCTL_0304                            0x00400304
-#define NV40_PGRAPH_CTXCTL_0304_XFER_CTX                   0x00000001
-#define NV40_PGRAPH_CTXCTL_UCODE_STAT                      0x00400308
-#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_MASK              0xff000000
-#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT                     24
-#define NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK              0x00ffffff
-#define NV40_PGRAPH_CTXCTL_0310                            0x00400310
-#define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE                  0x00000020
-#define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD                  0x00000040
-#define NV40_PGRAPH_CTXCTL_030C                            0x0040030c
-#define NV40_PGRAPH_CTXCTL_UCODE_INDEX                     0x00400324
-#define NV40_PGRAPH_CTXCTL_UCODE_DATA                      0x00400328
-#define NV40_PGRAPH_CTXCTL_CUR                             0x0040032c
-#define NV40_PGRAPH_CTXCTL_CUR_LOADED                      0x01000000
-#define NV40_PGRAPH_CTXCTL_CUR_INSTANCE                    0x000FFFFF
-#define NV40_PGRAPH_CTXCTL_NEXT                            0x00400330
-#define NV40_PGRAPH_CTXCTL_NEXT_INSTANCE                   0x000fffff
-#define NV50_PGRAPH_CTXCTL_CUR                             0x0040032c
-#define NV50_PGRAPH_CTXCTL_CUR_LOADED                      0x80000000
-#define NV50_PGRAPH_CTXCTL_CUR_INSTANCE                    0x00ffffff
-#define NV50_PGRAPH_CTXCTL_NEXT                            0x00400330
-#define NV50_PGRAPH_CTXCTL_NEXT_INSTANCE                   0x00ffffff
-#define NV03_PGRAPH_ABS_X_RAM                              0x00400400
-#define NV03_PGRAPH_ABS_Y_RAM                              0x00400480
-#define NV03_PGRAPH_X_MISC                                 0x00400500
-#define NV03_PGRAPH_Y_MISC                                 0x00400504
-#define NV04_PGRAPH_VALID1                                 0x00400508
-#define NV04_PGRAPH_SOURCE_COLOR                           0x0040050C
-#define NV04_PGRAPH_MISC24_0                               0x00400510
-#define NV03_PGRAPH_XY_LOGIC_MISC0                         0x00400514
-#define NV03_PGRAPH_XY_LOGIC_MISC1                         0x00400518
-#define NV03_PGRAPH_XY_LOGIC_MISC2                         0x0040051C
-#define NV03_PGRAPH_XY_LOGIC_MISC3                         0x00400520
-#define NV03_PGRAPH_CLIPX_0                                0x00400524
-#define NV03_PGRAPH_CLIPX_1                                0x00400528
-#define NV03_PGRAPH_CLIPY_0                                0x0040052C
-#define NV03_PGRAPH_CLIPY_1                                0x00400530
-#define NV03_PGRAPH_ABS_ICLIP_XMAX                         0x00400534
-#define NV03_PGRAPH_ABS_ICLIP_YMAX                         0x00400538
-#define NV03_PGRAPH_ABS_UCLIP_XMIN                         0x0040053C
-#define NV03_PGRAPH_ABS_UCLIP_YMIN                         0x00400540
-#define NV03_PGRAPH_ABS_UCLIP_XMAX                         0x00400544
-#define NV03_PGRAPH_ABS_UCLIP_YMAX                         0x00400548
-#define NV03_PGRAPH_ABS_UCLIPA_XMIN                        0x00400560
-#define NV03_PGRAPH_ABS_UCLIPA_YMIN                        0x00400564
-#define NV03_PGRAPH_ABS_UCLIPA_XMAX                        0x00400568
-#define NV03_PGRAPH_ABS_UCLIPA_YMAX                        0x0040056C
-#define NV04_PGRAPH_MISC24_1                               0x00400570
-#define NV04_PGRAPH_MISC24_2                               0x00400574
-#define NV04_PGRAPH_VALID2                                 0x00400578
-#define NV04_PGRAPH_PASSTHRU_0                             0x0040057C
-#define NV04_PGRAPH_PASSTHRU_1                             0x00400580
-#define NV04_PGRAPH_PASSTHRU_2                             0x00400584
-#define NV10_PGRAPH_DIMX_TEXTURE                           0x00400588
-#define NV10_PGRAPH_WDIMX_TEXTURE                          0x0040058C
-#define NV04_PGRAPH_COMBINE_0_ALPHA                        0x00400590
-#define NV04_PGRAPH_COMBINE_0_COLOR                        0x00400594
-#define NV04_PGRAPH_COMBINE_1_ALPHA                        0x00400598
-#define NV04_PGRAPH_COMBINE_1_COLOR                        0x0040059C
-#define NV04_PGRAPH_FORMAT_0                               0x004005A8
-#define NV04_PGRAPH_FORMAT_1                               0x004005AC
-#define NV04_PGRAPH_FILTER_0                               0x004005B0
-#define NV04_PGRAPH_FILTER_1                               0x004005B4
-#define NV03_PGRAPH_MONO_COLOR0                            0x00400600
-#define NV04_PGRAPH_ROP3                                   0x00400604
-#define NV04_PGRAPH_BETA_AND                               0x00400608
-#define NV04_PGRAPH_BETA_PREMULT                           0x0040060C
-#define NV04_PGRAPH_LIMIT_VIOL_PIX                         0x00400610
-#define NV04_PGRAPH_FORMATS                                0x00400618
-#define NV10_PGRAPH_DEBUG_2                                0x00400620
-#define NV04_PGRAPH_BOFFSET0                               0x00400640
-#define NV04_PGRAPH_BOFFSET1                               0x00400644
-#define NV04_PGRAPH_BOFFSET2                               0x00400648
-#define NV04_PGRAPH_BOFFSET3                               0x0040064C
-#define NV04_PGRAPH_BOFFSET4                               0x00400650
-#define NV04_PGRAPH_BOFFSET5                               0x00400654
-#define NV04_PGRAPH_BBASE0                                 0x00400658
-#define NV04_PGRAPH_BBASE1                                 0x0040065C
-#define NV04_PGRAPH_BBASE2                                 0x00400660
-#define NV04_PGRAPH_BBASE3                                 0x00400664
-#define NV04_PGRAPH_BBASE4                                 0x00400668
-#define NV04_PGRAPH_BBASE5                                 0x0040066C
-#define NV04_PGRAPH_BPITCH0                                0x00400670
-#define NV04_PGRAPH_BPITCH1                                0x00400674
-#define NV04_PGRAPH_BPITCH2                                0x00400678
-#define NV04_PGRAPH_BPITCH3                                0x0040067C
-#define NV04_PGRAPH_BPITCH4                                0x00400680
-#define NV04_PGRAPH_BLIMIT0                                0x00400684
-#define NV04_PGRAPH_BLIMIT1                                0x00400688
-#define NV04_PGRAPH_BLIMIT2                                0x0040068C
-#define NV04_PGRAPH_BLIMIT3                                0x00400690
-#define NV04_PGRAPH_BLIMIT4                                0x00400694
-#define NV04_PGRAPH_BLIMIT5                                0x00400698
-#define NV04_PGRAPH_BSWIZZLE2                              0x0040069C
-#define NV04_PGRAPH_BSWIZZLE5                              0x004006A0
-#define NV03_PGRAPH_STATUS                                 0x004006B0
-#define NV04_PGRAPH_STATUS                                 0x00400700
-#    define NV40_PGRAPH_STATUS_SYNC_STALL                  0x00004000
-#define NV04_PGRAPH_TRAPPED_ADDR                           0x00400704
-#define NV04_PGRAPH_TRAPPED_DATA                           0x00400708
-#define NV04_PGRAPH_SURFACE                                0x0040070C
-#define NV10_PGRAPH_TRAPPED_DATA_HIGH                      0x0040070C
-#define NV04_PGRAPH_STATE                                  0x00400710
-#define NV10_PGRAPH_SURFACE                                0x00400710
-#define NV04_PGRAPH_NOTIFY                                 0x00400714
-#define NV10_PGRAPH_STATE                                  0x00400714
-#define NV10_PGRAPH_NOTIFY                                 0x00400718
-
-#define NV04_PGRAPH_FIFO                                   0x00400720
-
-#define NV04_PGRAPH_BPIXEL                                 0x00400724
-#define NV10_PGRAPH_RDI_INDEX                              0x00400750
-#define NV04_PGRAPH_FFINTFC_ST2                            0x00400754
-#define NV10_PGRAPH_RDI_DATA                               0x00400754
-#define NV04_PGRAPH_DMA_PITCH                              0x00400760
-#define NV10_PGRAPH_FFINTFC_FIFO_PTR                       0x00400760
-#define NV04_PGRAPH_DVD_COLORFMT                           0x00400764
-#define NV10_PGRAPH_FFINTFC_ST2                            0x00400764
-#define NV04_PGRAPH_SCALED_FORMAT                          0x00400768
-#define NV10_PGRAPH_FFINTFC_ST2_DL                         0x00400768
-#define NV10_PGRAPH_FFINTFC_ST2_DH                         0x0040076c
-#define NV10_PGRAPH_DMA_PITCH                              0x00400770
-#define NV10_PGRAPH_DVD_COLORFMT                           0x00400774
-#define NV10_PGRAPH_SCALED_FORMAT                          0x00400778
-#define NV20_PGRAPH_CHANNEL_CTX_TABLE                      0x00400780
-#define NV20_PGRAPH_CHANNEL_CTX_POINTER                    0x00400784
-#define NV20_PGRAPH_CHANNEL_CTX_XFER                       0x00400788
-#define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD                  0x00000001
-#define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE                  0x00000002
-#define NV04_PGRAPH_PATT_COLOR0                            0x00400800
-#define NV04_PGRAPH_PATT_COLOR1                            0x00400804
-#define NV04_PGRAPH_PATTERN                                0x00400808
-#define NV04_PGRAPH_PATTERN_SHAPE                          0x00400810
-#define NV04_PGRAPH_CHROMA                                 0x00400814
-#define NV04_PGRAPH_CONTROL0                               0x00400818
-#define NV04_PGRAPH_CONTROL1                               0x0040081C
-#define NV04_PGRAPH_CONTROL2                               0x00400820
-#define NV04_PGRAPH_BLEND                                  0x00400824
-#define NV04_PGRAPH_STORED_FMT                             0x00400830
-#define NV04_PGRAPH_PATT_COLORRAM                          0x00400900
-#define NV20_PGRAPH_TILE(i)                                (0x00400900 + (i*16))
-#define NV20_PGRAPH_TLIMIT(i)                              (0x00400904 + (i*16))
-#define NV20_PGRAPH_TSIZE(i)                               (0x00400908 + (i*16))
-#define NV20_PGRAPH_TSTATUS(i)                             (0x0040090C + (i*16))
-#define NV20_PGRAPH_ZCOMP(i)                               (0x00400980 + 4*(i))
-#define NV41_PGRAPH_ZCOMP0(i)                              (0x004009c0 + 4*(i))
-#define NV10_PGRAPH_TILE(i)                                (0x00400B00 + (i*16))
-#define NV10_PGRAPH_TLIMIT(i)                              (0x00400B04 + (i*16))
-#define NV10_PGRAPH_TSIZE(i)                               (0x00400B08 + (i*16))
-#define NV10_PGRAPH_TSTATUS(i)                             (0x00400B0C + (i*16))
-#define NV04_PGRAPH_U_RAM                                  0x00400D00
-#define NV47_PGRAPH_TILE(i)                                (0x00400D00 + (i*16))
-#define NV47_PGRAPH_TLIMIT(i)                              (0x00400D04 + (i*16))
-#define NV47_PGRAPH_TSIZE(i)                               (0x00400D08 + (i*16))
-#define NV47_PGRAPH_TSTATUS(i)                             (0x00400D0C + (i*16))
-#define NV04_PGRAPH_V_RAM                                  0x00400D40
-#define NV04_PGRAPH_W_RAM                                  0x00400D80
-#define NV47_PGRAPH_ZCOMP0(i)                              (0x00400e00 + 4*(i))
-#define NV10_PGRAPH_COMBINER0_IN_ALPHA                     0x00400E40
-#define NV10_PGRAPH_COMBINER1_IN_ALPHA                     0x00400E44
-#define NV10_PGRAPH_COMBINER0_IN_RGB                       0x00400E48
-#define NV10_PGRAPH_COMBINER1_IN_RGB                       0x00400E4C
-#define NV10_PGRAPH_COMBINER_COLOR0                        0x00400E50
-#define NV10_PGRAPH_COMBINER_COLOR1                        0x00400E54
-#define NV10_PGRAPH_COMBINER0_OUT_ALPHA                    0x00400E58
-#define NV10_PGRAPH_COMBINER1_OUT_ALPHA                    0x00400E5C
-#define NV10_PGRAPH_COMBINER0_OUT_RGB                      0x00400E60
-#define NV10_PGRAPH_COMBINER1_OUT_RGB                      0x00400E64
-#define NV10_PGRAPH_COMBINER_FINAL0                        0x00400E68
-#define NV10_PGRAPH_COMBINER_FINAL1                        0x00400E6C
-#define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL                  0x00400F00
-#define NV10_PGRAPH_WINDOWCLIP_VERTICAL                    0x00400F20
-#define NV10_PGRAPH_XFMODE0                                0x00400F40
-#define NV10_PGRAPH_XFMODE1                                0x00400F44
-#define NV10_PGRAPH_GLOBALSTATE0                           0x00400F48
-#define NV10_PGRAPH_GLOBALSTATE1                           0x00400F4C
-#define NV10_PGRAPH_PIPE_ADDRESS                           0x00400F50
-#define NV10_PGRAPH_PIPE_DATA                              0x00400F54
-#define NV04_PGRAPH_DMA_START_0                            0x00401000
-#define NV04_PGRAPH_DMA_START_1                            0x00401004
-#define NV04_PGRAPH_DMA_LENGTH                             0x00401008
-#define NV04_PGRAPH_DMA_MISC                               0x0040100C
-#define NV04_PGRAPH_DMA_DATA_0                             0x00401020
-#define NV04_PGRAPH_DMA_DATA_1                             0x00401024
-#define NV04_PGRAPH_DMA_RM                                 0x00401030
-#define NV04_PGRAPH_DMA_A_XLATE_INST                       0x00401040
-#define NV04_PGRAPH_DMA_A_CONTROL                          0x00401044
-#define NV04_PGRAPH_DMA_A_LIMIT                            0x00401048
-#define NV04_PGRAPH_DMA_A_TLB_PTE                          0x0040104C
-#define NV04_PGRAPH_DMA_A_TLB_TAG                          0x00401050
-#define NV04_PGRAPH_DMA_A_ADJ_OFFSET                       0x00401054
-#define NV04_PGRAPH_DMA_A_OFFSET                           0x00401058
-#define NV04_PGRAPH_DMA_A_SIZE                             0x0040105C
-#define NV04_PGRAPH_DMA_A_Y_SIZE                           0x00401060
-#define NV04_PGRAPH_DMA_B_XLATE_INST                       0x00401080
-#define NV04_PGRAPH_DMA_B_CONTROL                          0x00401084
-#define NV04_PGRAPH_DMA_B_LIMIT                            0x00401088
-#define NV04_PGRAPH_DMA_B_TLB_PTE                          0x0040108C
-#define NV04_PGRAPH_DMA_B_TLB_TAG                          0x00401090
-#define NV04_PGRAPH_DMA_B_ADJ_OFFSET                       0x00401094
-#define NV04_PGRAPH_DMA_B_OFFSET                           0x00401098
-#define NV04_PGRAPH_DMA_B_SIZE                             0x0040109C
-#define NV04_PGRAPH_DMA_B_Y_SIZE                           0x004010A0
-#define NV47_PGRAPH_ZCOMP1(i)                              (0x004068c0 + 4*(i))
-#define NV40_PGRAPH_TILE1(i)                               (0x00406900 + (i*16))
-#define NV40_PGRAPH_TLIMIT1(i)                             (0x00406904 + (i*16))
-#define NV40_PGRAPH_TSIZE1(i)                              (0x00406908 + (i*16))
-#define NV40_PGRAPH_TSTATUS1(i)                            (0x0040690C + (i*16))
-#define NV40_PGRAPH_ZCOMP1(i)                              (0x00406980 + 4*(i))
-#define NV41_PGRAPH_ZCOMP1(i)                              (0x004069c0 + 4*(i))
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
deleted file mode 100644
index d88c700b2f69..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/handle.h>
-
-#include <subdev/fb.h>
-#include <subdev/timer.h>
-#include <subdev/instmem.h>
-
-#include <engine/fifo.h>
-#include <engine/mpeg.h>
-#include <engine/mpeg/nv31.h>
-
-/*******************************************************************************
- * MPEG object classes
- ******************************************************************************/
-
-static int
-nv31_mpeg_object_ctor(struct nouveau_object *parent,
-		      struct nouveau_object *engine,
-		      struct nouveau_oclass *oclass, void *data, u32 size,
-		      struct nouveau_object **pobject)
-{
-	struct nouveau_gpuobj *obj;
-	int ret;
-
-	ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
-				    20, 16, 0, &obj);
-	*pobject = nv_object(obj);
-	if (ret)
-		return ret;
-
-	nv_wo32(obj, 0x00, nv_mclass(obj));
-	nv_wo32(obj, 0x04, 0x00000000);
-	nv_wo32(obj, 0x08, 0x00000000);
-	nv_wo32(obj, 0x0c, 0x00000000);
-	return 0;
-}
-
-static int
-nv31_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len)
-{
-	struct nouveau_instmem *imem = nouveau_instmem(object);
-	struct nv31_mpeg_priv *priv = (void *)object->engine;
-	u32 inst = *(u32 *)arg << 4;
-	u32 dma0 = nv_ro32(imem, inst + 0);
-	u32 dma1 = nv_ro32(imem, inst + 4);
-	u32 dma2 = nv_ro32(imem, inst + 8);
-	u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
-	u32 size = dma1 + 1;
-
-	/* only allow linear DMA objects */
-	if (!(dma0 & 0x00002000))
-		return -EINVAL;
-
-	if (mthd == 0x0190) {
-		/* DMA_CMD */
-		nv_mask(priv, 0x00b300, 0x00010000, (dma0 & 0x00030000) ? 0x00010000 : 0);
-		nv_wr32(priv, 0x00b334, base);
-		nv_wr32(priv, 0x00b324, size);
-	} else
-	if (mthd == 0x01a0) {
-		/* DMA_DATA */
-		nv_mask(priv, 0x00b300, 0x00020000, (dma0 & 0x00030000) ? 0x00020000 : 0);
-		nv_wr32(priv, 0x00b360, base);
-		nv_wr32(priv, 0x00b364, size);
-	} else {
-		/* DMA_IMAGE, VRAM only */
-		if (dma0 & 0x00030000)
-			return -EINVAL;
-
-		nv_wr32(priv, 0x00b370, base);
-		nv_wr32(priv, 0x00b374, size);
-	}
-
-	return 0;
-}
-
-struct nouveau_ofuncs
-nv31_mpeg_ofuncs = {
-	.ctor = nv31_mpeg_object_ctor,
-	.dtor = _nouveau_gpuobj_dtor,
-	.init = _nouveau_gpuobj_init,
-	.fini = _nouveau_gpuobj_fini,
-	.rd32 = _nouveau_gpuobj_rd32,
-	.wr32 = _nouveau_gpuobj_wr32,
-};
-
-static struct nouveau_omthds
-nv31_mpeg_omthds[] = {
-	{ 0x0190, 0x0190, nv31_mpeg_mthd_dma },
-	{ 0x01a0, 0x01a0, nv31_mpeg_mthd_dma },
-	{ 0x01b0, 0x01b0, nv31_mpeg_mthd_dma },
-	{}
-};
-
-struct nouveau_oclass
-nv31_mpeg_sclass[] = {
-	{ 0x3174, &nv31_mpeg_ofuncs, nv31_mpeg_omthds },
-	{}
-};
-
-/*******************************************************************************
- * PMPEG context
- ******************************************************************************/
-
-static int
-nv31_mpeg_context_ctor(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, void *data, u32 size,
-		       struct nouveau_object **pobject)
-{
-	struct nv31_mpeg_priv *priv = (void *)engine;
-	struct nv31_mpeg_chan *chan;
-	unsigned long flags;
-	int ret;
-
-	ret = nouveau_object_create(parent, engine, oclass, 0, &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	spin_lock_irqsave(&nv_engine(priv)->lock, flags);
-	if (priv->chan) {
-		spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
-		nouveau_object_destroy(&chan->base);
-		*pobject = NULL;
-		return -EBUSY;
-	}
-	priv->chan = chan;
-	spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
-	return 0;
-}
-
-static void
-nv31_mpeg_context_dtor(struct nouveau_object *object)
-{
-	struct nv31_mpeg_priv *priv = (void *)object->engine;
-	struct nv31_mpeg_chan *chan = (void *)object;
-	unsigned long flags;
-
-	spin_lock_irqsave(&nv_engine(priv)->lock, flags);
-	priv->chan = NULL;
-	spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
-	nouveau_object_destroy(&chan->base);
-}
-
-struct nouveau_oclass
-nv31_mpeg_cclass = {
-	.handle = NV_ENGCTX(MPEG, 0x31),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv31_mpeg_context_ctor,
-		.dtor = nv31_mpeg_context_dtor,
-		.init = nouveau_object_init,
-		.fini = nouveau_object_fini,
-	},
-};
-
-/*******************************************************************************
- * PMPEG engine/subdev functions
- ******************************************************************************/
-
-void
-nv31_mpeg_tile_prog(struct nouveau_engine *engine, int i)
-{
-	struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
-	struct nv31_mpeg_priv *priv = (void *)engine;
-
-	nv_wr32(priv, 0x00b008 + (i * 0x10), tile->pitch);
-	nv_wr32(priv, 0x00b004 + (i * 0x10), tile->limit);
-	nv_wr32(priv, 0x00b000 + (i * 0x10), tile->addr);
-}
-
-void
-nv31_mpeg_intr(struct nouveau_subdev *subdev)
-{
-	struct nv31_mpeg_priv *priv = (void *)subdev;
-	struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
-	struct nouveau_handle *handle;
-	struct nouveau_object *engctx;
-	u32 stat = nv_rd32(priv, 0x00b100);
-	u32 type = nv_rd32(priv, 0x00b230);
-	u32 mthd = nv_rd32(priv, 0x00b234);
-	u32 data = nv_rd32(priv, 0x00b238);
-	u32 show = stat;
-	unsigned long flags;
-
-	spin_lock_irqsave(&nv_engine(priv)->lock, flags);
-	engctx = nv_object(priv->chan);
-
-	if (stat & 0x01000000) {
-		/* happens on initial binding of the object */
-		if (type == 0x00000020 && mthd == 0x0000) {
-			nv_mask(priv, 0x00b308, 0x00000000, 0x00000000);
-			show &= ~0x01000000;
-		}
-
-		if (type == 0x00000010 && engctx) {
-			handle = nouveau_handle_get_class(engctx, 0x3174);
-			if (handle && !nv_call(handle->object, mthd, data))
-				show &= ~0x01000000;
-			nouveau_handle_put(handle);
-		}
-	}
-
-	nv_wr32(priv, 0x00b100, stat);
-	nv_wr32(priv, 0x00b230, 0x00000001);
-
-	if (show) {
-		nv_error(priv, "ch %d [%s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
-			 pfifo->chid(pfifo, engctx),
-			 nouveau_client_name(engctx), stat, type, mthd, data);
-	}
-
-	spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
-}
-
-static int
-nv31_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv31_mpeg_priv *priv;
-	int ret;
-
-	ret = nouveau_mpeg_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00000002;
-	nv_subdev(priv)->intr = nv31_mpeg_intr;
-	nv_engine(priv)->cclass = &nv31_mpeg_cclass;
-	nv_engine(priv)->sclass = nv31_mpeg_sclass;
-	nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog;
-	return 0;
-}
-
-int
-nv31_mpeg_init(struct nouveau_object *object)
-{
-	struct nouveau_engine *engine = nv_engine(object);
-	struct nv31_mpeg_priv *priv = (void *)object;
-	struct nouveau_fb *pfb = nouveau_fb(object);
-	int ret, i;
-
-	ret = nouveau_mpeg_init(&priv->base);
-	if (ret)
-		return ret;
-
-	/* VPE init */
-	nv_wr32(priv, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
-	nv_wr32(priv, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
-
-	for (i = 0; i < pfb->tile.regions; i++)
-		engine->tile_prog(engine, i);
-
-	/* PMPEG init */
-	nv_wr32(priv, 0x00b32c, 0x00000000);
-	nv_wr32(priv, 0x00b314, 0x00000100);
-	nv_wr32(priv, 0x00b220, 0x00000031);
-	nv_wr32(priv, 0x00b300, 0x02001ec1);
-	nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001);
-
-	nv_wr32(priv, 0x00b100, 0xffffffff);
-	nv_wr32(priv, 0x00b140, 0xffffffff);
-
-	if (!nv_wait(priv, 0x00b200, 0x00000001, 0x00000000)) {
-		nv_error(priv, "timeout 0x%08x\n", nv_rd32(priv, 0x00b200));
-		return -EBUSY;
-	}
-
-	return 0;
-}
-
-struct nouveau_oclass
-nv31_mpeg_oclass = {
-	.handle = NV_ENGINE(MPEG, 0x31),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv31_mpeg_ctor,
-		.dtor = _nouveau_mpeg_dtor,
-		.init = nv31_mpeg_init,
-		.fini = _nouveau_mpeg_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.h b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.h
deleted file mode 100644
index d08629d0b6ad..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef __NV31_MPEG_H__
-#define __NV31_MPEG_H__
-
-#include <engine/mpeg.h>
-
-struct nv31_mpeg_chan {
-	struct nouveau_object base;
-};
-
-struct nv31_mpeg_priv {
-	struct nouveau_mpeg base;
-	struct nv31_mpeg_chan *chan;
-};
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c
deleted file mode 100644
index bdb2f20ff7b1..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/os.h>
-#include <core/engctx.h>
-
-#include <subdev/fb.h>
-#include <subdev/timer.h>
-#include <subdev/instmem.h>
-
-#include <engine/mpeg.h>
-#include <engine/mpeg/nv31.h>
-
-/*******************************************************************************
- * MPEG object classes
- ******************************************************************************/
-
-static int
-nv40_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len)
-{
-	struct nouveau_instmem *imem = nouveau_instmem(object);
-	struct nv31_mpeg_priv *priv = (void *)object->engine;
-	u32 inst = *(u32 *)arg << 4;
-	u32 dma0 = nv_ro32(imem, inst + 0);
-	u32 dma1 = nv_ro32(imem, inst + 4);
-	u32 dma2 = nv_ro32(imem, inst + 8);
-	u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
-	u32 size = dma1 + 1;
-
-	/* only allow linear DMA objects */
-	if (!(dma0 & 0x00002000))
-		return -EINVAL;
-
-	if (mthd == 0x0190) {
-		/* DMA_CMD */
-		nv_mask(priv, 0x00b300, 0x00030000, (dma0 & 0x00030000));
-		nv_wr32(priv, 0x00b334, base);
-		nv_wr32(priv, 0x00b324, size);
-	} else
-	if (mthd == 0x01a0) {
-		/* DMA_DATA */
-		nv_mask(priv, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
-		nv_wr32(priv, 0x00b360, base);
-		nv_wr32(priv, 0x00b364, size);
-	} else {
-		/* DMA_IMAGE, VRAM only */
-		if (dma0 & 0x00030000)
-			return -EINVAL;
-
-		nv_wr32(priv, 0x00b370, base);
-		nv_wr32(priv, 0x00b374, size);
-	}
-
-	return 0;
-}
-
-static struct nouveau_omthds
-nv40_mpeg_omthds[] = {
-	{ 0x0190, 0x0190, nv40_mpeg_mthd_dma },
-	{ 0x01a0, 0x01a0, nv40_mpeg_mthd_dma },
-	{ 0x01b0, 0x01b0, nv40_mpeg_mthd_dma },
-	{}
-};
-
-struct nouveau_oclass
-nv40_mpeg_sclass[] = {
-	{ 0x3174, &nv31_mpeg_ofuncs, nv40_mpeg_omthds },
-	{}
-};
-
-/*******************************************************************************
- * PMPEG engine/subdev functions
- ******************************************************************************/
-
-static void
-nv40_mpeg_intr(struct nouveau_subdev *subdev)
-{
-	struct nv31_mpeg_priv *priv = (void *)subdev;
-	u32 stat;
-
-	if ((stat = nv_rd32(priv, 0x00b100)))
-		nv31_mpeg_intr(subdev);
-
-	if ((stat = nv_rd32(priv, 0x00b800))) {
-		nv_error(priv, "PMSRCH 0x%08x\n", stat);
-		nv_wr32(priv, 0x00b800, stat);
-	}
-}
-
-static int
-nv40_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv31_mpeg_priv *priv;
-	int ret;
-
-	ret = nouveau_mpeg_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00000002;
-	nv_subdev(priv)->intr = nv40_mpeg_intr;
-	nv_engine(priv)->cclass = &nv31_mpeg_cclass;
-	nv_engine(priv)->sclass = nv40_mpeg_sclass;
-	nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog;
-	return 0;
-}
-
-struct nouveau_oclass
-nv40_mpeg_oclass = {
-	.handle = NV_ENGINE(MPEG, 0x40),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv40_mpeg_ctor,
-		.dtor = _nouveau_mpeg_dtor,
-		.init = nv31_mpeg_init,
-		.fini = _nouveau_mpeg_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c
deleted file mode 100644
index 72c7f33fd29b..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/os.h>
-#include <core/client.h>
-#include <core/engctx.h>
-#include <core/handle.h>
-
-#include <subdev/fb.h>
-#include <subdev/timer.h>
-#include <subdev/instmem.h>
-
-#include <engine/fifo.h>
-#include <engine/mpeg.h>
-
-struct nv44_mpeg_priv {
-	struct nouveau_mpeg base;
-};
-
-struct nv44_mpeg_chan {
-	struct nouveau_mpeg_chan base;
-};
-
-/*******************************************************************************
- * PMPEG context
- ******************************************************************************/
-
-static int
-nv44_mpeg_context_ctor(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, void *data, u32 size,
-		       struct nouveau_object **pobject)
-{
-	struct nv44_mpeg_chan *chan;
-	int ret;
-
-	ret = nouveau_mpeg_context_create(parent, engine, oclass, NULL,
-					  264 * 4, 16,
-					  NVOBJ_FLAG_ZERO_ALLOC, &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	nv_wo32(&chan->base.base, 0x78, 0x02001ec1);
-	return 0;
-}
-
-static int
-nv44_mpeg_context_fini(struct nouveau_object *object, bool suspend)
-{
-
-	struct nv44_mpeg_priv *priv = (void *)object->engine;
-	struct nv44_mpeg_chan *chan = (void *)object;
-	u32 inst = 0x80000000 | nv_gpuobj(chan)->addr >> 4;
-
-	nv_mask(priv, 0x00b32c, 0x00000001, 0x00000000);
-	if (nv_rd32(priv, 0x00b318) == inst)
-		nv_mask(priv, 0x00b318, 0x80000000, 0x00000000);
-	nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001);
-	return 0;
-}
-
-static struct nouveau_oclass
-nv44_mpeg_cclass = {
-	.handle = NV_ENGCTX(MPEG, 0x44),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv44_mpeg_context_ctor,
-		.dtor = _nouveau_mpeg_context_dtor,
-		.init = _nouveau_mpeg_context_init,
-		.fini = nv44_mpeg_context_fini,
-		.rd32 = _nouveau_mpeg_context_rd32,
-		.wr32 = _nouveau_mpeg_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PMPEG engine/subdev functions
- ******************************************************************************/
-
-static void
-nv44_mpeg_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
-	struct nouveau_engine *engine = nv_engine(subdev);
-	struct nouveau_object *engctx;
-	struct nouveau_handle *handle;
-	struct nv44_mpeg_priv *priv = (void *)subdev;
-	u32 inst = nv_rd32(priv, 0x00b318) & 0x000fffff;
-	u32 stat = nv_rd32(priv, 0x00b100);
-	u32 type = nv_rd32(priv, 0x00b230);
-	u32 mthd = nv_rd32(priv, 0x00b234);
-	u32 data = nv_rd32(priv, 0x00b238);
-	u32 show = stat;
-	int chid;
-
-	engctx = nouveau_engctx_get(engine, inst);
-	chid   = pfifo->chid(pfifo, engctx);
-
-	if (stat & 0x01000000) {
-		/* happens on initial binding of the object */
-		if (type == 0x00000020 && mthd == 0x0000) {
-			nv_mask(priv, 0x00b308, 0x00000000, 0x00000000);
-			show &= ~0x01000000;
-		}
-
-		if (type == 0x00000010) {
-			handle = nouveau_handle_get_class(engctx, 0x3174);
-			if (handle && !nv_call(handle->object, mthd, data))
-				show &= ~0x01000000;
-			nouveau_handle_put(handle);
-		}
-	}
-
-	nv_wr32(priv, 0x00b100, stat);
-	nv_wr32(priv, 0x00b230, 0x00000001);
-
-	if (show) {
-		nv_error(priv,
-			 "ch %d [0x%08x %s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
-			 chid, inst << 4, nouveau_client_name(engctx), stat,
-			 type, mthd, data);
-	}
-
-	nouveau_engctx_put(engctx);
-}
-
-static void
-nv44_mpeg_me_intr(struct nouveau_subdev *subdev)
-{
-	struct nv44_mpeg_priv *priv = (void *)subdev;
-	u32 stat;
-
-	if ((stat = nv_rd32(priv, 0x00b100)))
-		nv44_mpeg_intr(subdev);
-
-	if ((stat = nv_rd32(priv, 0x00b800))) {
-		nv_error(priv, "PMSRCH 0x%08x\n", stat);
-		nv_wr32(priv, 0x00b800, stat);
-	}
-}
-
-static int
-nv44_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv44_mpeg_priv *priv;
-	int ret;
-
-	ret = nouveau_mpeg_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00000002;
-	nv_subdev(priv)->intr = nv44_mpeg_me_intr;
-	nv_engine(priv)->cclass = &nv44_mpeg_cclass;
-	nv_engine(priv)->sclass = nv40_mpeg_sclass;
-	nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog;
-	return 0;
-}
-
-struct nouveau_oclass
-nv44_mpeg_oclass = {
-	.handle = NV_ENGINE(MPEG, 0x44),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv44_mpeg_ctor,
-		.dtor = _nouveau_mpeg_dtor,
-		.init = nv31_mpeg_init,
-		.fini = _nouveau_mpeg_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
deleted file mode 100644
index cae33f86b11a..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/os.h>
-#include <core/engctx.h>
-
-#include <subdev/vm.h>
-#include <subdev/bar.h>
-#include <subdev/timer.h>
-
-#include <engine/mpeg.h>
-
-struct nv50_mpeg_priv {
-	struct nouveau_mpeg base;
-};
-
-struct nv50_mpeg_chan {
-	struct nouveau_mpeg_chan base;
-};
-
-/*******************************************************************************
- * MPEG object classes
- ******************************************************************************/
-
-static int
-nv50_mpeg_object_ctor(struct nouveau_object *parent,
-		      struct nouveau_object *engine,
-		      struct nouveau_oclass *oclass, void *data, u32 size,
-		      struct nouveau_object **pobject)
-{
-	struct nouveau_gpuobj *obj;
-	int ret;
-
-	ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
-				    16, 16, 0, &obj);
-	*pobject = nv_object(obj);
-	if (ret)
-		return ret;
-
-	nv_wo32(obj, 0x00, nv_mclass(obj));
-	nv_wo32(obj, 0x04, 0x00000000);
-	nv_wo32(obj, 0x08, 0x00000000);
-	nv_wo32(obj, 0x0c, 0x00000000);
-	return 0;
-}
-
-struct nouveau_ofuncs
-nv50_mpeg_ofuncs = {
-	.ctor = nv50_mpeg_object_ctor,
-	.dtor = _nouveau_gpuobj_dtor,
-	.init = _nouveau_gpuobj_init,
-	.fini = _nouveau_gpuobj_fini,
-	.rd32 = _nouveau_gpuobj_rd32,
-	.wr32 = _nouveau_gpuobj_wr32,
-};
-
-static struct nouveau_oclass
-nv50_mpeg_sclass[] = {
-	{ 0x3174, &nv50_mpeg_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * PMPEG context
- ******************************************************************************/
-
-int
-nv50_mpeg_context_ctor(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, void *data, u32 size,
-		       struct nouveau_object **pobject)
-{
-	struct nouveau_bar *bar = nouveau_bar(parent);
-	struct nv50_mpeg_chan *chan;
-	int ret;
-
-	ret = nouveau_mpeg_context_create(parent, engine, oclass, NULL, 128 * 4,
-					  0, NVOBJ_FLAG_ZERO_ALLOC, &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	nv_wo32(chan, 0x0070, 0x00801ec1);
-	nv_wo32(chan, 0x007c, 0x0000037c);
-	bar->flush(bar);
-	return 0;
-}
-
-static struct nouveau_oclass
-nv50_mpeg_cclass = {
-	.handle = NV_ENGCTX(MPEG, 0x50),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_mpeg_context_ctor,
-		.dtor = _nouveau_mpeg_context_dtor,
-		.init = _nouveau_mpeg_context_init,
-		.fini = _nouveau_mpeg_context_fini,
-		.rd32 = _nouveau_mpeg_context_rd32,
-		.wr32 = _nouveau_mpeg_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PMPEG engine/subdev functions
- ******************************************************************************/
-
-void
-nv50_mpeg_intr(struct nouveau_subdev *subdev)
-{
-	struct nv50_mpeg_priv *priv = (void *)subdev;
-	u32 stat = nv_rd32(priv, 0x00b100);
-	u32 type = nv_rd32(priv, 0x00b230);
-	u32 mthd = nv_rd32(priv, 0x00b234);
-	u32 data = nv_rd32(priv, 0x00b238);
-	u32 show = stat;
-
-	if (stat & 0x01000000) {
-		/* happens on initial binding of the object */
-		if (type == 0x00000020 && mthd == 0x0000) {
-			nv_wr32(priv, 0x00b308, 0x00000100);
-			show &= ~0x01000000;
-		}
-	}
-
-	if (show) {
-		nv_info(priv, "0x%08x 0x%08x 0x%08x 0x%08x\n",
-			stat, type, mthd, data);
-	}
-
-	nv_wr32(priv, 0x00b100, stat);
-	nv_wr32(priv, 0x00b230, 0x00000001);
-}
-
-static void
-nv50_vpe_intr(struct nouveau_subdev *subdev)
-{
-	struct nv50_mpeg_priv *priv = (void *)subdev;
-
-	if (nv_rd32(priv, 0x00b100))
-		nv50_mpeg_intr(subdev);
-
-	if (nv_rd32(priv, 0x00b800)) {
-		u32 stat = nv_rd32(priv, 0x00b800);
-		nv_info(priv, "PMSRCH: 0x%08x\n", stat);
-		nv_wr32(priv, 0xb800, stat);
-	}
-}
-
-static int
-nv50_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv50_mpeg_priv *priv;
-	int ret;
-
-	ret = nouveau_mpeg_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00400002;
-	nv_subdev(priv)->intr = nv50_vpe_intr;
-	nv_engine(priv)->cclass = &nv50_mpeg_cclass;
-	nv_engine(priv)->sclass = nv50_mpeg_sclass;
-	return 0;
-}
-
-int
-nv50_mpeg_init(struct nouveau_object *object)
-{
-	struct nv50_mpeg_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_mpeg_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x00b32c, 0x00000000);
-	nv_wr32(priv, 0x00b314, 0x00000100);
-	nv_wr32(priv, 0x00b0e0, 0x0000001a);
-
-	nv_wr32(priv, 0x00b220, 0x00000044);
-	nv_wr32(priv, 0x00b300, 0x00801ec1);
-	nv_wr32(priv, 0x00b390, 0x00000000);
-	nv_wr32(priv, 0x00b394, 0x00000000);
-	nv_wr32(priv, 0x00b398, 0x00000000);
-	nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001);
-
-	nv_wr32(priv, 0x00b100, 0xffffffff);
-	nv_wr32(priv, 0x00b140, 0xffffffff);
-
-	if (!nv_wait(priv, 0x00b200, 0x00000001, 0x00000000)) {
-		nv_error(priv, "timeout 0x%08x\n", nv_rd32(priv, 0x00b200));
-		return -EBUSY;
-	}
-
-	return 0;
-}
-
-struct nouveau_oclass
-nv50_mpeg_oclass = {
-	.handle = NV_ENGINE(MPEG, 0x50),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_mpeg_ctor,
-		.dtor = _nouveau_mpeg_dtor,
-		.init = nv50_mpeg_init,
-		.fini = _nouveau_mpeg_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c
deleted file mode 100644
index e9cc8b116a24..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/os.h>
-#include <core/engctx.h>
-
-#include <subdev/vm.h>
-#include <subdev/bar.h>
-#include <subdev/timer.h>
-
-#include <engine/mpeg.h>
-
-struct nv84_mpeg_priv {
-	struct nouveau_mpeg base;
-};
-
-struct nv84_mpeg_chan {
-	struct nouveau_mpeg_chan base;
-};
-
-/*******************************************************************************
- * MPEG object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv84_mpeg_sclass[] = {
-	{ 0x8274, &nv50_mpeg_ofuncs },
-	{}
-};
-
-/*******************************************************************************
- * PMPEG context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv84_mpeg_cclass = {
-	.handle = NV_ENGCTX(MPEG, 0x84),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_mpeg_context_ctor,
-		.dtor = _nouveau_mpeg_context_dtor,
-		.init = _nouveau_mpeg_context_init,
-		.fini = _nouveau_mpeg_context_fini,
-		.rd32 = _nouveau_mpeg_context_rd32,
-		.wr32 = _nouveau_mpeg_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PMPEG engine/subdev functions
- ******************************************************************************/
-
-static int
-nv84_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv84_mpeg_priv *priv;
-	int ret;
-
-	ret = nouveau_mpeg_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00000002;
-	nv_subdev(priv)->intr = nv50_mpeg_intr;
-	nv_engine(priv)->cclass = &nv84_mpeg_cclass;
-	nv_engine(priv)->sclass = nv84_mpeg_sclass;
-	return 0;
-}
-
-struct nouveau_oclass
-nv84_mpeg_oclass = {
-	.handle = NV_ENGINE(MPEG, 0x84),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv84_mpeg_ctor,
-		.dtor = _nouveau_mpeg_dtor,
-		.init = nv50_mpeg_init,
-		.fini = _nouveau_mpeg_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/base.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/base.c
deleted file mode 100644
index 63013812f7c9..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/base.c
+++ /dev/null
@@ -1,483 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <core/option.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-#include <nvif/ioctl.h>
-
-#include <subdev/clock.h>
-
-#include "priv.h"
-
-#define QUAD_MASK 0x0f
-#define QUAD_FREE 0x01
-
-static struct nouveau_perfsig *
-nouveau_perfsig_find_(struct nouveau_perfdom *dom, const char *name, u32 size)
-{
-	char path[64];
-	int i;
-
-	if (name[0] != '/') {
-		for (i = 0; i < dom->signal_nr; i++) {
-			if ( dom->signal[i].name &&
-			    !strncmp(name, dom->signal[i].name, size))
-				return &dom->signal[i];
-		}
-	} else {
-		for (i = 0; i < dom->signal_nr; i++) {
-			snprintf(path, sizeof(path), "/%s/%02x", dom->name, i);
-			if (!strncmp(name, path, size))
-				return &dom->signal[i];
-		}
-	}
-
-	return NULL;
-}
-
-struct nouveau_perfsig *
-nouveau_perfsig_find(struct nouveau_perfmon *ppm, const char *name, u32 size,
-		     struct nouveau_perfdom **pdom)
-{
-	struct nouveau_perfdom *dom = *pdom;
-	struct nouveau_perfsig *sig;
-
-	if (dom == NULL) {
-		list_for_each_entry(dom, &ppm->domains, head) {
-			sig = nouveau_perfsig_find_(dom, name, size);
-			if (sig) {
-				*pdom = dom;
-				return sig;
-			}
-		}
-
-		return NULL;
-	}
-
-	return nouveau_perfsig_find_(dom, name, size);
-}
-
-struct nouveau_perfctr *
-nouveau_perfsig_wrap(struct nouveau_perfmon *ppm, const char *name,
-		     struct nouveau_perfdom **pdom)
-{
-	struct nouveau_perfsig *sig;
-	struct nouveau_perfctr *ctr;
-
-	sig = nouveau_perfsig_find(ppm, name, strlen(name), pdom);
-	if (!sig)
-		return NULL;
-
-	ctr = kzalloc(sizeof(*ctr), GFP_KERNEL);
-	if (ctr) {
-		ctr->signal[0] = sig;
-		ctr->logic_op = 0xaaaa;
-	}
-
-	return ctr;
-}
-
-/*******************************************************************************
- * Perfmon object classes
- ******************************************************************************/
-static int
-nouveau_perfctr_query(struct nouveau_object *object, void *data, u32 size)
-{
-	union {
-		struct nvif_perfctr_query_v0 v0;
-	} *args = data;
-	struct nouveau_device *device = nv_device(object);
-	struct nouveau_perfmon *ppm = (void *)object->engine;
-	struct nouveau_perfdom *dom = NULL, *chk;
-	const bool all = nouveau_boolopt(device->cfgopt, "NvPmShowAll", false);
-	const bool raw = nouveau_boolopt(device->cfgopt, "NvPmUnnamed", all);
-	const char *name;
-	int tmp = 0, di, si;
-	int ret;
-
-	nv_ioctl(object, "perfctr query size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "perfctr query vers %d iter %08x\n",
-			 args->v0.version, args->v0.iter);
-		di = (args->v0.iter & 0xff000000) >> 24;
-		si = (args->v0.iter & 0x00ffffff) - 1;
-	} else
-		return ret;
-
-	list_for_each_entry(chk, &ppm->domains, head) {
-		if (tmp++ == di) {
-			dom = chk;
-			break;
-		}
-	}
-
-	if (dom == NULL || si >= (int)dom->signal_nr)
-		return -EINVAL;
-
-	if (si >= 0) {
-		if (raw || !(name = dom->signal[si].name)) {
-			snprintf(args->v0.name, sizeof(args->v0.name),
-				 "/%s/%02x", dom->name, si);
-		} else {
-			strncpy(args->v0.name, name, sizeof(args->v0.name));
-		}
-	}
-
-	do {
-		while (++si < dom->signal_nr) {
-			if (all || dom->signal[si].name) {
-				args->v0.iter = (di << 24) | ++si;
-				return 0;
-			}
-		}
-		si = -1;
-		di = di + 1;
-		dom = list_entry(dom->head.next, typeof(*dom), head);
-	} while (&dom->head != &ppm->domains);
-
-	args->v0.iter = 0xffffffff;
-	return 0;
-}
-
-static int
-nouveau_perfctr_sample(struct nouveau_object *object, void *data, u32 size)
-{
-	union {
-		struct nvif_perfctr_sample none;
-	} *args = data;
-	struct nouveau_perfmon *ppm = (void *)object->engine;
-	struct nouveau_perfctr *ctr, *tmp;
-	struct nouveau_perfdom *dom;
-	int ret;
-
-	nv_ioctl(object, "perfctr sample size %d\n", size);
-	if (nvif_unvers(args->none)) {
-		nv_ioctl(object, "perfctr sample\n");
-	} else
-		return ret;
-	ppm->sequence++;
-
-	list_for_each_entry(dom, &ppm->domains, head) {
-		/* sample previous batch of counters */
-		if (dom->quad != QUAD_MASK) {
-			dom->func->next(ppm, dom);
-			tmp = NULL;
-			while (!list_empty(&dom->list)) {
-				ctr = list_first_entry(&dom->list,
-							typeof(*ctr), head);
-				if (ctr->slot < 0) break;
-				if ( tmp && tmp == ctr) break;
-				if (!tmp) tmp = ctr;
-				dom->func->read(ppm, dom, ctr);
-				ctr->slot  = -1;
-				list_move_tail(&ctr->head, &dom->list);
-			}
-		}
-
-		dom->quad = QUAD_MASK;
-
-		/* setup next batch of counters for sampling */
-		list_for_each_entry(ctr, &dom->list, head) {
-			ctr->slot = ffs(dom->quad) - 1;
-			if (ctr->slot < 0)
-				break;
-			dom->quad &= ~(QUAD_FREE << ctr->slot);
-			dom->func->init(ppm, dom, ctr);
-		}
-
-		if (dom->quad != QUAD_MASK)
-			dom->func->next(ppm, dom);
-	}
-
-	return 0;
-}
-
-static int
-nouveau_perfctr_read(struct nouveau_object *object, void *data, u32 size)
-{
-	union {
-		struct nvif_perfctr_read_v0 v0;
-	} *args = data;
-	struct nouveau_perfctr *ctr = (void *)object;
-	int ret;
-
-	nv_ioctl(object, "perfctr read size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(object, "perfctr read vers %d\n", args->v0.version);
-	} else
-		return ret;
-
-	if (!ctr->clk)
-		return -EAGAIN;
-
-	args->v0.clk = ctr->clk;
-	args->v0.ctr = ctr->ctr;
-	return 0;
-}
-
-static int
-nouveau_perfctr_mthd(struct nouveau_object *object, u32 mthd,
-		     void *data, u32 size)
-{
-	switch (mthd) {
-	case NVIF_PERFCTR_V0_QUERY:
-		return nouveau_perfctr_query(object, data, size);
-	case NVIF_PERFCTR_V0_SAMPLE:
-		return nouveau_perfctr_sample(object, data, size);
-	case NVIF_PERFCTR_V0_READ:
-		return nouveau_perfctr_read(object, data, size);
-	default:
-		break;
-	}
-	return -EINVAL;
-}
-
-static void
-nouveau_perfctr_dtor(struct nouveau_object *object)
-{
-	struct nouveau_perfctr *ctr = (void *)object;
-	if (ctr->head.next)
-		list_del(&ctr->head);
-	nouveau_object_destroy(&ctr->base);
-}
-
-static int
-nouveau_perfctr_ctor(struct nouveau_object *parent,
-		     struct nouveau_object *engine,
-		     struct nouveau_oclass *oclass, void *data, u32 size,
-		     struct nouveau_object **pobject)
-{
-	union {
-		struct nvif_perfctr_v0 v0;
-	} *args = data;
-	struct nouveau_perfmon *ppm = (void *)engine;
-	struct nouveau_perfdom *dom = NULL;
-	struct nouveau_perfsig *sig[4] = {};
-	struct nouveau_perfctr *ctr;
-	int ret, i;
-
-	nv_ioctl(parent, "create perfctr size %d\n", size);
-	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nv_ioctl(parent, "create perfctr vers %d logic_op %04x\n",
-			 args->v0.version, args->v0.logic_op);
-	} else
-		return ret;
-
-	for (i = 0; i < ARRAY_SIZE(args->v0.name) && args->v0.name[i][0]; i++) {
-		sig[i] = nouveau_perfsig_find(ppm, args->v0.name[i],
-					      strnlen(args->v0.name[i],
-					      sizeof(args->v0.name[i])),
-					      &dom);
-		if (!sig[i])
-			return -EINVAL;
-	}
-
-	ret = nouveau_object_create(parent, engine, oclass, 0, &ctr);
-	*pobject = nv_object(ctr);
-	if (ret)
-		return ret;
-
-	ctr->slot = -1;
-	ctr->logic_op = args->v0.logic_op;
-	ctr->signal[0] = sig[0];
-	ctr->signal[1] = sig[1];
-	ctr->signal[2] = sig[2];
-	ctr->signal[3] = sig[3];
-	if (dom)
-		list_add_tail(&ctr->head, &dom->list);
-	return 0;
-}
-
-static struct nouveau_ofuncs
-nouveau_perfctr_ofuncs = {
-	.ctor = nouveau_perfctr_ctor,
-	.dtor = nouveau_perfctr_dtor,
-	.init = nouveau_object_init,
-	.fini = nouveau_object_fini,
-	.mthd = nouveau_perfctr_mthd,
-};
-
-struct nouveau_oclass
-nouveau_perfmon_sclass[] = {
-	{ .handle = NVIF_IOCTL_NEW_V0_PERFCTR,
-	  .ofuncs = &nouveau_perfctr_ofuncs,
-	},
-	{},
-};
-
-/*******************************************************************************
- * PPM context
- ******************************************************************************/
-static void
-nouveau_perfctx_dtor(struct nouveau_object *object)
-{
-	struct nouveau_perfmon *ppm = (void *)object->engine;
-	mutex_lock(&nv_subdev(ppm)->mutex);
-	nouveau_engctx_destroy(&ppm->context->base);
-	ppm->context = NULL;
-	mutex_unlock(&nv_subdev(ppm)->mutex);
-}
-
-static int
-nouveau_perfctx_ctor(struct nouveau_object *parent,
-		     struct nouveau_object *engine,
-		     struct nouveau_oclass *oclass, void *data, u32 size,
-		     struct nouveau_object **pobject)
-{
-	struct nouveau_perfmon *ppm = (void *)engine;
-	struct nouveau_perfctx *ctx;
-	int ret;
-
-	ret = nouveau_engctx_create(parent, engine, oclass, NULL,
-				    0, 0, 0, &ctx);
-	*pobject = nv_object(ctx);
-	if (ret)
-		return ret;
-
-	mutex_lock(&nv_subdev(ppm)->mutex);
-	if (ppm->context == NULL)
-		ppm->context = ctx;
-	mutex_unlock(&nv_subdev(ppm)->mutex);
-
-	if (ctx != ppm->context)
-		return -EBUSY;
-
-	return 0;
-}
-
-struct nouveau_oclass
-nouveau_perfmon_cclass = {
-	.handle = NV_ENGCTX(PERFMON, 0x00),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nouveau_perfctx_ctor,
-		.dtor = nouveau_perfctx_dtor,
-		.init = _nouveau_engctx_init,
-		.fini = _nouveau_engctx_fini,
-	},
-};
-
-/*******************************************************************************
- * PPM engine/subdev functions
- ******************************************************************************/
-int
-nouveau_perfdom_new(struct nouveau_perfmon *ppm, const char *name, u32 mask,
-		    u32 base, u32 size_unit, u32 size_domain,
-		    const struct nouveau_specdom *spec)
-{
-	const struct nouveau_specdom *sdom;
-	const struct nouveau_specsig *ssig;
-	struct nouveau_perfdom *dom;
-	int i;
-
-	for (i = 0; i == 0 || mask; i++) {
-		u32 addr = base + (i * size_unit);
-		if (i && !(mask & (1 << i)))
-			continue;
-
-		sdom = spec;
-		while (sdom->signal_nr) {
-			dom = kzalloc(sizeof(*dom) + sdom->signal_nr *
-				      sizeof(*dom->signal), GFP_KERNEL);
-			if (!dom)
-				return -ENOMEM;
-
-			if (mask) {
-				snprintf(dom->name, sizeof(dom->name),
-					 "%s/%02x/%02x", name, i,
-					 (int)(sdom - spec));
-			} else {
-				snprintf(dom->name, sizeof(dom->name),
-					 "%s/%02x", name, (int)(sdom - spec));
-			}
-
-			list_add_tail(&dom->head, &ppm->domains);
-			INIT_LIST_HEAD(&dom->list);
-			dom->func = sdom->func;
-			dom->addr = addr;
-			dom->quad = QUAD_MASK;
-			dom->signal_nr = sdom->signal_nr;
-
-			ssig = (sdom++)->signal;
-			while (ssig->name) {
-				dom->signal[ssig->signal].name = ssig->name;
-				ssig++;
-			}
-
-			addr += size_domain;
-		}
-
-		mask &= ~(1 << i);
-	}
-
-	return 0;
-}
-
-int
-_nouveau_perfmon_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nouveau_perfmon *ppm = (void *)object;
-	return nouveau_engine_fini(&ppm->base, suspend);
-}
-
-int
-_nouveau_perfmon_init(struct nouveau_object *object)
-{
-	struct nouveau_perfmon *ppm = (void *)object;
-	return nouveau_engine_init(&ppm->base);
-}
-
-void
-_nouveau_perfmon_dtor(struct nouveau_object *object)
-{
-	struct nouveau_perfmon *ppm = (void *)object;
-	struct nouveau_perfdom *dom, *tmp;
-
-	list_for_each_entry_safe(dom, tmp, &ppm->domains, head) {
-		list_del(&dom->head);
-		kfree(dom);
-	}
-
-	nouveau_engine_destroy(&ppm->base);
-}
-
-int
-nouveau_perfmon_create_(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass,
-			int length, void **pobject)
-{
-	struct nouveau_perfmon *ppm;
-	int ret;
-
-	ret = nouveau_engine_create_(parent, engine, oclass, true, "PPM",
-				     "perfmon", length, pobject);
-	ppm = *pobject;
-	if (ret)
-		return ret;
-
-	INIT_LIST_HEAD(&ppm->domains);
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/daemon.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/daemon.c
deleted file mode 100644
index 50696cc7b7d7..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/daemon.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-
-static void
-pwr_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
-		 struct nouveau_perfctr *ctr)
-{
-	u32 mask = 0x00000000;
-	u32 ctrl = 0x00000001;
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(ctr->signal) && ctr->signal[i]; i++)
-		mask |= 1 << (ctr->signal[i] - dom->signal);
-
-	nv_wr32(ppm, 0x10a504 + (ctr->slot * 0x10), mask);
-	nv_wr32(ppm, 0x10a50c + (ctr->slot * 0x10), ctrl);
-	nv_wr32(ppm, 0x10a50c + (ppm->last * 0x10), 0x00000003);
-}
-
-static void
-pwr_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
-		 struct nouveau_perfctr *ctr)
-{
-	ctr->ctr = ppm->pwr[ctr->slot];
-	ctr->clk = ppm->pwr[ppm->last];
-}
-
-static void
-pwr_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom)
-{
-	int i;
-
-	for (i = 0; i <= ppm->last; i++) {
-		ppm->pwr[i] = nv_rd32(ppm, 0x10a508 + (i * 0x10));
-		nv_wr32(ppm, 0x10a508 + (i * 0x10), 0x80000000);
-	}
-}
-
-static const struct nouveau_funcdom
-pwr_perfctr_func = {
-	.init = pwr_perfctr_init,
-	.read = pwr_perfctr_read,
-	.next = pwr_perfctr_next,
-};
-
-const struct nouveau_specdom
-nva3_perfmon_pwr[] = {
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{ 0x00, "pwr_gr_idle" },
-			{ 0x04, "pwr_bsp_idle" },
-			{ 0x05, "pwr_vp_idle" },
-			{ 0x06, "pwr_ppp_idle" },
-			{ 0x13, "pwr_ce0_idle" },
-			{}
-		}, &pwr_perfctr_func },
-	{}
-};
-
-const struct nouveau_specdom
-nvc0_perfmon_pwr[] = {
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{ 0x00, "pwr_gr_idle" },
-			{ 0x04, "pwr_bsp_idle" },
-			{ 0x05, "pwr_vp_idle" },
-			{ 0x06, "pwr_ppp_idle" },
-			{ 0x13, "pwr_ce0_idle" },
-			{ 0x14, "pwr_ce1_idle" },
-			{}
-		}, &pwr_perfctr_func },
-	{}
-};
-
-const struct nouveau_specdom
-nve0_perfmon_pwr[] = {
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{ 0x00, "pwr_gr_idle" },
-			{ 0x04, "pwr_bsp_idle" },
-			{ 0x05, "pwr_vp_idle" },
-			{ 0x06, "pwr_ppp_idle" },
-			{ 0x13, "pwr_ce0_idle" },
-			{ 0x14, "pwr_ce1_idle" },
-			{ 0x15, "pwr_ce2_idle" },
-			{}
-		}, &pwr_perfctr_func },
-	{}
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.c
deleted file mode 100644
index b2a10785adb1..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv40.h"
-
-/*******************************************************************************
- * Perfmon object classes
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM context
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM engine/subdev functions
- ******************************************************************************/
-
-static void
-nv40_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
-		  struct nouveau_perfctr *ctr)
-{
-	struct nv40_perfmon_priv *priv = (void *)ppm;
-	struct nv40_perfmon_cntr *cntr = (void *)ctr;
-	u32 log = ctr->logic_op;
-	u32 src = 0x00000000;
-	int i;
-
-	for (i = 0; i < 4 && ctr->signal[i]; i++)
-		src |= (ctr->signal[i] - dom->signal) << (i * 8);
-
-	nv_wr32(priv, 0x00a7c0 + dom->addr, 0x00000001);
-	nv_wr32(priv, 0x00a400 + dom->addr + (cntr->base.slot * 0x40), src);
-	nv_wr32(priv, 0x00a420 + dom->addr + (cntr->base.slot * 0x40), log);
-}
-
-static void
-nv40_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
-		  struct nouveau_perfctr *ctr)
-{
-	struct nv40_perfmon_priv *priv = (void *)ppm;
-	struct nv40_perfmon_cntr *cntr = (void *)ctr;
-
-	switch (cntr->base.slot) {
-	case 0: cntr->base.ctr = nv_rd32(priv, 0x00a700 + dom->addr); break;
-	case 1: cntr->base.ctr = nv_rd32(priv, 0x00a6c0 + dom->addr); break;
-	case 2: cntr->base.ctr = nv_rd32(priv, 0x00a680 + dom->addr); break;
-	case 3: cntr->base.ctr = nv_rd32(priv, 0x00a740 + dom->addr); break;
-	}
-	cntr->base.clk = nv_rd32(priv, 0x00a600 + dom->addr);
-}
-
-static void
-nv40_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom)
-{
-	struct nv40_perfmon_priv *priv = (void *)ppm;
-	if (priv->sequence != ppm->sequence) {
-		nv_wr32(priv, 0x400084, 0x00000020);
-		priv->sequence = ppm->sequence;
-	}
-}
-
-const struct nouveau_funcdom
-nv40_perfctr_func = {
-	.init = nv40_perfctr_init,
-	.read = nv40_perfctr_read,
-	.next = nv40_perfctr_next,
-};
-
-static const struct nouveau_specdom
-nv40_perfmon[] = {
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{}
-};
-
-int
-nv40_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 size,
-		  struct nouveau_object **pobject)
-{
-	struct nv40_perfmon_oclass *mclass = (void *)oclass;
-	struct nv40_perfmon_priv *priv;
-	int ret;
-
-	ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nouveau_perfdom_new(&priv->base, "pm", 0, 0, 0, 4, mclass->doms);
-	if (ret)
-		return ret;
-
-	nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
-	nv_engine(priv)->sclass =  nouveau_perfmon_sclass;
-	return 0;
-}
-
-struct nouveau_oclass *
-nv40_perfmon_oclass = &(struct nv40_perfmon_oclass) {
-	.base.handle = NV_ENGINE(PERFMON, 0x40),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv40_perfmon_ctor,
-		.dtor = _nouveau_perfmon_dtor,
-		.init = _nouveau_perfmon_init,
-		.fini = _nouveau_perfmon_fini,
-	},
-	.doms = nv40_perfmon,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.h b/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.h
deleted file mode 100644
index 1b5792d1df14..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef __NVKM_PM_NV40_H__
-#define __NVKM_PM_NV40_H__
-
-#include "priv.h"
-
-struct nv40_perfmon_oclass {
-	struct nouveau_oclass base;
-	const struct nouveau_specdom *doms;
-};
-
-struct nv40_perfmon_priv {
-	struct nouveau_perfmon base;
-	u32 sequence;
-};
-
-int nv40_perfmon_ctor(struct nouveau_object *, struct nouveau_object *,
-		      struct nouveau_oclass *, void *data, u32 size,
-		      struct nouveau_object **pobject);
-
-struct nv40_perfmon_cntr {
-	struct nouveau_perfctr base;
-};
-
-extern const struct nouveau_funcdom nv40_perfctr_func;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv50.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/nv50.c
deleted file mode 100644
index 94217691fe67..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv50.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv40.h"
-
-/*******************************************************************************
- * Perfmon object classes
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM context
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM engine/subdev functions
- ******************************************************************************/
-
-static const struct nouveau_specdom
-nv50_perfmon[] = {
-	{ 0x040, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x100, (const struct nouveau_specsig[]) {
-			{ 0xc8, "gr_idle" },
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x100, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x020, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x040, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{}
-};
-
-struct nouveau_oclass *
-nv50_perfmon_oclass = &(struct nv40_perfmon_oclass) {
-	.base.handle = NV_ENGINE(PERFMON, 0x50),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv40_perfmon_ctor,
-		.dtor = _nouveau_perfmon_dtor,
-		.init = _nouveau_perfmon_init,
-		.fini = _nouveau_perfmon_fini,
-	},
-	.doms = nv50_perfmon,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv84.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/nv84.c
deleted file mode 100644
index 9232c7fc6253..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv84.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv40.h"
-
-/*******************************************************************************
- * Perfmon object classes
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM context
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM engine/subdev functions
- ******************************************************************************/
-
-static const struct nouveau_specdom
-nv84_perfmon[] = {
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{}
-};
-
-struct nouveau_oclass *
-nv84_perfmon_oclass = &(struct nv40_perfmon_oclass) {
-	.base.handle = NV_ENGINE(PERFMON, 0x84),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv40_perfmon_ctor,
-		.dtor = _nouveau_perfmon_dtor,
-		.init = _nouveau_perfmon_init,
-		.fini = _nouveau_perfmon_fini,
-	},
-	.doms = nv84_perfmon,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nva3.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/nva3.c
deleted file mode 100644
index 6197ebdeb648..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nva3.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv40.h"
-
-/*******************************************************************************
- * Perfmon object classes
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM context
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM engine/subdev functions
- ******************************************************************************/
-
-static const struct nouveau_specdom
-nva3_perfmon[] = {
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{ 0x20, (const struct nouveau_specsig[]) {
-			{}
-		}, &nv40_perfctr_func },
-	{}
-};
-
-static int
-nva3_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 size,
-		  struct nouveau_object **object)
-{
-	int ret = nv40_perfmon_ctor(parent, engine, oclass, data, size, object);
-	if (ret == 0) {
-		struct nv40_perfmon_priv *priv = (void *)*object;
-		ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
-					   nva3_perfmon_pwr);
-		if (ret)
-			return ret;
-
-		priv->base.last = 3;
-	}
-	return ret;
-}
-
-struct nouveau_oclass *
-nva3_perfmon_oclass = &(struct nv40_perfmon_oclass) {
-	.base.handle = NV_ENGINE(PERFMON, 0xa3),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nva3_perfmon_ctor,
-		.dtor = _nouveau_perfmon_dtor,
-		.init = _nouveau_perfmon_init,
-		.fini = _nouveau_perfmon_fini,
-	},
-	.doms = nva3_perfmon,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.c
deleted file mode 100644
index 74b241042502..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nvc0.h"
-
-/*******************************************************************************
- * Perfmon object classes
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM context
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM engine/subdev functions
- ******************************************************************************/
-
-static const struct nouveau_specdom
-nvc0_perfmon_hub[] = {
-	{}
-};
-
-static const struct nouveau_specdom
-nvc0_perfmon_gpc[] = {
-	{}
-};
-
-static const struct nouveau_specdom
-nvc0_perfmon_part[] = {
-	{}
-};
-
-static void
-nvc0_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
-		  struct nouveau_perfctr *ctr)
-{
-	struct nvc0_perfmon_priv *priv = (void *)ppm;
-	struct nvc0_perfmon_cntr *cntr = (void *)ctr;
-	u32 log = ctr->logic_op;
-	u32 src = 0x00000000;
-	int i;
-
-	for (i = 0; i < 4 && ctr->signal[i]; i++)
-		src |= (ctr->signal[i] - dom->signal) << (i * 8);
-
-	nv_wr32(priv, dom->addr + 0x09c, 0x00040002);
-	nv_wr32(priv, dom->addr + 0x100, 0x00000000);
-	nv_wr32(priv, dom->addr + 0x040 + (cntr->base.slot * 0x08), src);
-	nv_wr32(priv, dom->addr + 0x044 + (cntr->base.slot * 0x08), log);
-}
-
-static void
-nvc0_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
-		  struct nouveau_perfctr *ctr)
-{
-	struct nvc0_perfmon_priv *priv = (void *)ppm;
-	struct nvc0_perfmon_cntr *cntr = (void *)ctr;
-
-	switch (cntr->base.slot) {
-	case 0: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x08c); break;
-	case 1: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x088); break;
-	case 2: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x080); break;
-	case 3: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x090); break;
-	}
-	cntr->base.clk = nv_rd32(priv, dom->addr + 0x070);
-}
-
-static void
-nvc0_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom)
-{
-	struct nvc0_perfmon_priv *priv = (void *)ppm;
-	nv_wr32(priv, dom->addr + 0x06c, dom->signal_nr - 0x40 + 0x27);
-	nv_wr32(priv, dom->addr + 0x0ec, 0x00000011);
-}
-
-const struct nouveau_funcdom
-nvc0_perfctr_func = {
-	.init = nvc0_perfctr_init,
-	.read = nvc0_perfctr_read,
-	.next = nvc0_perfctr_next,
-};
-
-int
-nvc0_perfmon_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nvc0_perfmon_priv *priv = (void *)object;
-	nv_mask(priv, 0x000200, 0x10000000, 0x00000000);
-	nv_mask(priv, 0x000200, 0x10000000, 0x10000000);
-	return nouveau_perfmon_fini(&priv->base, suspend);
-}
-
-static int
-nvc0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 size,
-		  struct nouveau_object **pobject)
-{
-	struct nvc0_perfmon_priv *priv;
-	u32 mask;
-	int ret;
-
-	ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
-				   nvc0_perfmon_pwr);
-	if (ret)
-		return ret;
-
-	/* HUB */
-	ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
-				   nvc0_perfmon_hub);
-	if (ret)
-		return ret;
-
-	/* GPC */
-	mask  = (1 << nv_rd32(priv, 0x022430)) - 1;
-	mask &= ~nv_rd32(priv, 0x022504);
-	mask &= ~nv_rd32(priv, 0x022584);
-
-	ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000,
-				  0x1000, 0x200, nvc0_perfmon_gpc);
-	if (ret)
-		return ret;
-
-	/* PART */
-	mask  = (1 << nv_rd32(priv, 0x022438)) - 1;
-	mask &= ~nv_rd32(priv, 0x022548);
-	mask &= ~nv_rd32(priv, 0x0225c8);
-
-	ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000,
-				  0x1000, 0x200, nvc0_perfmon_part);
-	if (ret)
-		return ret;
-
-	nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
-	nv_engine(priv)->sclass =  nouveau_perfmon_sclass;
-	priv->base.last = 7;
-	return 0;
-}
-
-struct nouveau_oclass
-nvc0_perfmon_oclass = {
-	.handle = NV_ENGINE(PERFMON, 0xc0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_perfmon_ctor,
-		.dtor = _nouveau_perfmon_dtor,
-		.init = _nouveau_perfmon_init,
-		.fini = nvc0_perfmon_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.h
deleted file mode 100644
index f66bca484263..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef __NVKM_PM_NVC0_H__
-#define __NVKM_PM_NVC0_H__
-
-#include "priv.h"
-
-struct nvc0_perfmon_priv {
-	struct nouveau_perfmon base;
-};
-
-struct nvc0_perfmon_cntr {
-	struct nouveau_perfctr base;
-};
-
-extern const struct nouveau_funcdom nvc0_perfctr_func;
-int nvc0_perfmon_fini(struct nouveau_object *, bool);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nve0.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/nve0.c
deleted file mode 100644
index 71d718c12075..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nve0.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nvc0.h"
-
-/*******************************************************************************
- * Perfmon object classes
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM context
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM engine/subdev functions
- ******************************************************************************/
-
-static const struct nouveau_specdom
-nve0_perfmon_hub[] = {
-	{ 0x60, (const struct nouveau_specsig[]) {
-			{ 0x47, "hub00_user_0" },
-			{}
-		}, &nvc0_perfctr_func },
-	{ 0x40, (const struct nouveau_specsig[]) {
-			{ 0x27, "hub01_user_0" },
-			{}
-		}, &nvc0_perfctr_func },
-	{ 0x60, (const struct nouveau_specsig[]) {
-			{ 0x47, "hub02_user_0" },
-			{}
-		}, &nvc0_perfctr_func },
-	{ 0x60, (const struct nouveau_specsig[]) {
-			{ 0x47, "hub03_user_0" },
-			{}
-		}, &nvc0_perfctr_func },
-	{ 0x40, (const struct nouveau_specsig[]) {
-			{ 0x03, "host_mmio_rd" },
-			{ 0x27, "hub04_user_0" },
-			{}
-		}, &nvc0_perfctr_func },
-	{ 0x60, (const struct nouveau_specsig[]) {
-			{ 0x47, "hub05_user_0" },
-			{}
-		}, &nvc0_perfctr_func },
-	{ 0xc0, (const struct nouveau_specsig[]) {
-			{ 0x74, "host_fb_rd3x" },
-			{ 0x75, "host_fb_rd3x_2" },
-			{ 0xa7, "hub06_user_0" },
-			{}
-		}, &nvc0_perfctr_func },
-	{ 0x60, (const struct nouveau_specsig[]) {
-			{ 0x47, "hub07_user_0" },
-			{}
-		}, &nvc0_perfctr_func },
-	{}
-};
-
-static const struct nouveau_specdom
-nve0_perfmon_gpc[] = {
-	{ 0xe0, (const struct nouveau_specsig[]) {
-			{ 0xc7, "gpc00_user_0" },
-			{}
-		}, &nvc0_perfctr_func },
-	{}
-};
-
-static const struct nouveau_specdom
-nve0_perfmon_part[] = {
-	{ 0x60, (const struct nouveau_specsig[]) {
-			{ 0x47, "part00_user_0" },
-			{}
-		}, &nvc0_perfctr_func },
-	{ 0x60, (const struct nouveau_specsig[]) {
-			{ 0x47, "part01_user_0" },
-			{}
-		}, &nvc0_perfctr_func },
-	{}
-};
-
-static int
-nve0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 size,
-		  struct nouveau_object **pobject)
-{
-	struct nvc0_perfmon_priv *priv;
-	u32 mask;
-	int ret;
-
-	ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	/* PDAEMON */
-	ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
-				   nve0_perfmon_pwr);
-	if (ret)
-		return ret;
-
-	/* HUB */
-	ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
-				   nve0_perfmon_hub);
-	if (ret)
-		return ret;
-
-	/* GPC */
-	mask  = (1 << nv_rd32(priv, 0x022430)) - 1;
-	mask &= ~nv_rd32(priv, 0x022504);
-	mask &= ~nv_rd32(priv, 0x022584);
-
-	ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000,
-				  0x1000, 0x200, nve0_perfmon_gpc);
-	if (ret)
-		return ret;
-
-	/* PART */
-	mask  = (1 << nv_rd32(priv, 0x022438)) - 1;
-	mask &= ~nv_rd32(priv, 0x022548);
-	mask &= ~nv_rd32(priv, 0x0225c8);
-
-	ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000,
-				  0x1000, 0x200, nve0_perfmon_part);
-	if (ret)
-		return ret;
-
-	nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
-	nv_engine(priv)->sclass =  nouveau_perfmon_sclass;
-	priv->base.last = 7;
-	return 0;
-}
-
-struct nouveau_oclass
-nve0_perfmon_oclass = {
-	.handle = NV_ENGINE(PERFMON, 0xe0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nve0_perfmon_ctor,
-		.dtor = _nouveau_perfmon_dtor,
-		.init = _nouveau_perfmon_init,
-		.fini = nvc0_perfmon_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/nvf0.c
deleted file mode 100644
index 47256f78a895..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvf0.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nvc0.h"
-
-/*******************************************************************************
- * Perfmon object classes
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM context
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM engine/subdev functions
- ******************************************************************************/
-
-static int
-nvf0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 size,
-		  struct nouveau_object **pobject)
-{
-	struct nvc0_perfmon_priv *priv;
-	int ret;
-
-	ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
-				   nve0_perfmon_pwr);
-	if (ret)
-		return ret;
-
-	nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
-	nv_engine(priv)->sclass =  nouveau_perfmon_sclass;
-	return 0;
-}
-
-struct nouveau_oclass
-nvf0_perfmon_oclass = {
-	.handle = NV_ENGINE(PERFMON, 0xf0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvf0_perfmon_ctor,
-		.dtor = _nouveau_perfmon_dtor,
-		.init = _nouveau_perfmon_init,
-		.fini = nvc0_perfmon_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/priv.h b/drivers/gpu/drm/nouveau/core/engine/perfmon/priv.h
deleted file mode 100644
index 0ac8714fe0ba..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/priv.h
+++ /dev/null
@@ -1,91 +0,0 @@
-#ifndef __NVKM_PERFMON_PRIV_H__
-#define __NVKM_PERFMON_PRIV_H__
-
-#include <engine/perfmon.h>
-
-struct nouveau_perfctr {
-	struct nouveau_object base;
-	struct list_head head;
-	struct nouveau_perfsig *signal[4];
-	int slot;
-	u32 logic_op;
-	u32 clk;
-	u32 ctr;
-};
-
-extern struct nouveau_oclass nouveau_perfmon_sclass[];
-
-struct nouveau_perfctx {
-	struct nouveau_engctx base;
-};
-
-extern struct nouveau_oclass nouveau_perfmon_cclass;
-
-struct nouveau_specsig {
-	u8 signal;
-	const char *name;
-};
-
-struct nouveau_perfsig {
-	const char *name;
-};
-
-struct nouveau_perfdom;
-struct nouveau_perfctr *
-nouveau_perfsig_wrap(struct nouveau_perfmon *, const char *,
-		     struct nouveau_perfdom **);
-
-struct nouveau_specdom {
-	u16 signal_nr;
-	const struct nouveau_specsig *signal;
-	const struct nouveau_funcdom *func;
-};
-
-extern const struct nouveau_specdom nva3_perfmon_pwr[];
-extern const struct nouveau_specdom nvc0_perfmon_pwr[];
-extern const struct nouveau_specdom nve0_perfmon_pwr[];
-
-struct nouveau_perfdom {
-	struct list_head head;
-	struct list_head list;
-	const struct nouveau_funcdom *func;
-	char name[32];
-	u32 addr;
-	u8  quad;
-	u32 signal_nr;
-	struct nouveau_perfsig signal[];
-};
-
-struct nouveau_funcdom {
-	void (*init)(struct nouveau_perfmon *, struct nouveau_perfdom *,
-		     struct nouveau_perfctr *);
-	void (*read)(struct nouveau_perfmon *, struct nouveau_perfdom *,
-		     struct nouveau_perfctr *);
-	void (*next)(struct nouveau_perfmon *, struct nouveau_perfdom *);
-};
-
-int nouveau_perfdom_new(struct nouveau_perfmon *, const char *, u32,
-			u32, u32, u32, const struct nouveau_specdom *);
-
-#define nouveau_perfmon_create(p,e,o,d)                                        \
-	nouveau_perfmon_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_perfmon_dtor(p) ({                                             \
-	struct nouveau_perfmon *c = (p);                                       \
-	_nouveau_perfmon_dtor(nv_object(c));                                   \
-})
-#define nouveau_perfmon_init(p) ({                                             \
-	struct nouveau_perfmon *c = (p);                                       \
-	_nouveau_perfmon_init(nv_object(c));                                   \
-})
-#define nouveau_perfmon_fini(p,s) ({                                           \
-	struct nouveau_perfmon *c = (p);                                       \
-	_nouveau_perfmon_fini(nv_object(c), (s));                              \
-})
-
-int nouveau_perfmon_create_(struct nouveau_object *, struct nouveau_object *,
-			    struct nouveau_oclass *, int, void **);
-void _nouveau_perfmon_dtor(struct nouveau_object *);
-int  _nouveau_perfmon_init(struct nouveau_object *);
-int  _nouveau_perfmon_fini(struct nouveau_object *, bool);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/ppp/nv98.c b/drivers/gpu/drm/nouveau/core/engine/ppp/nv98.c
deleted file mode 100644
index 13bf31c40aa1..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/ppp/nv98.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
- */
-
-#include <engine/falcon.h>
-#include <engine/ppp.h>
-
-struct nv98_ppp_priv {
-	struct nouveau_falcon base;
-};
-
-/*******************************************************************************
- * PPP object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv98_ppp_sclass[] = {
-	{ 0x88b3, &nouveau_object_ofuncs },
-	{ 0x85b3, &nouveau_object_ofuncs },
-	{},
-};
-
-/*******************************************************************************
- * PPPP context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv98_ppp_cclass = {
-	.handle = NV_ENGCTX(PPP, 0x98),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_falcon_context_ctor,
-		.dtor = _nouveau_falcon_context_dtor,
-		.init = _nouveau_falcon_context_init,
-		.fini = _nouveau_falcon_context_fini,
-		.rd32 = _nouveau_falcon_context_rd32,
-		.wr32 = _nouveau_falcon_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PPPP engine/subdev functions
- ******************************************************************************/
-
-static int
-nv98_ppp_init(struct nouveau_object *object)
-{
-	struct nv98_ppp_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_falcon_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x086010, 0x0000ffd2);
-	nv_wr32(priv, 0x08601c, 0x0000fff2);
-	return 0;
-}
-
-static int
-nv98_ppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 size,
-	      struct nouveau_object **pobject)
-{
-	struct nv98_ppp_priv *priv;
-	int ret;
-
-	ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true,
-				    "PPPP", "ppp", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00400002;
-	nv_engine(priv)->cclass = &nv98_ppp_cclass;
-	nv_engine(priv)->sclass = nv98_ppp_sclass;
-	return 0;
-}
-
-struct nouveau_oclass
-nv98_ppp_oclass = {
-	.handle = NV_ENGINE(PPP, 0x98),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv98_ppp_ctor,
-		.dtor = _nouveau_falcon_dtor,
-		.init = nv98_ppp_init,
-		.fini = _nouveau_falcon_fini,
-		.rd32 = _nouveau_falcon_rd32,
-		.wr32 = _nouveau_falcon_wr32,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/ppp/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/ppp/nvc0.c
deleted file mode 100644
index 73719aaa62d6..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/ppp/nvc0.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright 2012 Maarten Lankhorst
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Maarten Lankhorst
- */
-
-#include <engine/falcon.h>
-#include <engine/ppp.h>
-
-struct nvc0_ppp_priv {
-	struct nouveau_falcon base;
-};
-
-/*******************************************************************************
- * PPP object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nvc0_ppp_sclass[] = {
-	{ 0x90b3, &nouveau_object_ofuncs },
-	{},
-};
-
-/*******************************************************************************
- * PPPP context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nvc0_ppp_cclass = {
-	.handle = NV_ENGCTX(PPP, 0xc0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_falcon_context_ctor,
-		.dtor = _nouveau_falcon_context_dtor,
-		.init = _nouveau_falcon_context_init,
-		.fini = _nouveau_falcon_context_fini,
-		.rd32 = _nouveau_falcon_context_rd32,
-		.wr32 = _nouveau_falcon_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PPPP engine/subdev functions
- ******************************************************************************/
-
-static int
-nvc0_ppp_init(struct nouveau_object *object)
-{
-	struct nvc0_ppp_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_falcon_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x086010, 0x0000fff2);
-	nv_wr32(priv, 0x08601c, 0x0000fff2);
-	return 0;
-}
-
-static int
-nvc0_ppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 size,
-	      struct nouveau_object **pobject)
-{
-	struct nvc0_ppp_priv *priv;
-	int ret;
-
-	ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true,
-				    "PPPP", "ppp", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00000002;
-	nv_subdev(priv)->intr = nouveau_falcon_intr;
-	nv_engine(priv)->cclass = &nvc0_ppp_cclass;
-	nv_engine(priv)->sclass = nvc0_ppp_sclass;
-	return 0;
-}
-
-struct nouveau_oclass
-nvc0_ppp_oclass = {
-	.handle = NV_ENGINE(PPP, 0xc0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_ppp_ctor,
-		.dtor = _nouveau_falcon_dtor,
-		.init = nvc0_ppp_init,
-		.fini = _nouveau_falcon_fini,
-		.rd32 = _nouveau_falcon_rd32,
-		.wr32 = _nouveau_falcon_wr32,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv04.c b/drivers/gpu/drm/nouveau/core/engine/software/nv04.c
deleted file mode 100644
index 64df15c7f051..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/software/nv04.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/os.h>
-#include <core/engctx.h>
-
-#include <engine/software.h>
-#include <engine/fifo.h>
-
-struct nv04_software_priv {
-	struct nouveau_software base;
-};
-
-struct nv04_software_chan {
-	struct nouveau_software_chan base;
-};
-
-/*******************************************************************************
- * software object classes
- ******************************************************************************/
-
-static int
-nv04_software_set_ref(struct nouveau_object *object, u32 mthd,
-		      void *data, u32 size)
-{
-	struct nouveau_object *channel = (void *)nv_engctx(object->parent);
-	struct nouveau_fifo_chan *fifo = (void *)channel->parent;
-	atomic_set(&fifo->refcnt, *(u32*)data);
-	return 0;
-}
-
-static int
-nv04_software_flip(struct nouveau_object *object, u32 mthd,
-		   void *args, u32 size)
-{
-	struct nv04_software_chan *chan = (void *)nv_engctx(object->parent);
-	if (chan->base.flip)
-		return chan->base.flip(chan->base.flip_data);
-	return -EINVAL;
-}
-
-static struct nouveau_omthds
-nv04_software_omthds[] = {
-	{ 0x0150, 0x0150, nv04_software_set_ref },
-	{ 0x0500, 0x0500, nv04_software_flip },
-	{}
-};
-
-static struct nouveau_oclass
-nv04_software_sclass[] = {
-	{ 0x006e, &nouveau_object_ofuncs, nv04_software_omthds },
-	{}
-};
-
-/*******************************************************************************
- * software context
- ******************************************************************************/
-
-static int
-nv04_software_context_ctor(struct nouveau_object *parent,
-		      struct nouveau_object *engine,
-		      struct nouveau_oclass *oclass, void *data, u32 size,
-		      struct nouveau_object **pobject)
-{
-	struct nv04_software_chan *chan;
-	int ret;
-
-	ret = nouveau_software_context_create(parent, engine, oclass, &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-static struct nouveau_oclass
-nv04_software_cclass = {
-	.handle = NV_ENGCTX(SW, 0x04),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_software_context_ctor,
-		.dtor = _nouveau_software_context_dtor,
-		.init = _nouveau_software_context_init,
-		.fini = _nouveau_software_context_fini,
-	},
-};
-
-/*******************************************************************************
- * software engine/subdev functions
- ******************************************************************************/
-
-void
-nv04_software_intr(struct nouveau_subdev *subdev)
-{
-	nv_mask(subdev, 0x000100, 0x80000000, 0x00000000);
-}
-
-static int
-nv04_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 size,
-	      struct nouveau_object **pobject)
-{
-	struct nv04_software_priv *priv;
-	int ret;
-
-	ret = nouveau_software_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_engine(priv)->cclass = &nv04_software_cclass;
-	nv_engine(priv)->sclass = nv04_software_sclass;
-	nv_subdev(priv)->intr = nv04_software_intr;
-	return 0;
-}
-
-struct nouveau_oclass *
-nv04_software_oclass = &(struct nouveau_oclass) {
-	.handle = NV_ENGINE(SW, 0x04),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_software_ctor,
-		.dtor = _nouveau_software_dtor,
-		.init = _nouveau_software_init,
-		.fini = _nouveau_software_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv10.c b/drivers/gpu/drm/nouveau/core/engine/software/nv10.c
deleted file mode 100644
index f54a2253deca..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/software/nv10.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/os.h>
-#include <core/engctx.h>
-
-#include <engine/software.h>
-
-struct nv10_software_priv {
-	struct nouveau_software base;
-};
-
-struct nv10_software_chan {
-	struct nouveau_software_chan base;
-};
-
-/*******************************************************************************
- * software object classes
- ******************************************************************************/
-
-static int
-nv10_software_flip(struct nouveau_object *object, u32 mthd,
-		   void *args, u32 size)
-{
-	struct nv10_software_chan *chan = (void *)nv_engctx(object->parent);
-	if (chan->base.flip)
-		return chan->base.flip(chan->base.flip_data);
-	return -EINVAL;
-}
-
-static struct nouveau_omthds
-nv10_software_omthds[] = {
-	{ 0x0500, 0x0500, nv10_software_flip },
-	{}
-};
-
-static struct nouveau_oclass
-nv10_software_sclass[] = {
-	{ 0x016e, &nouveau_object_ofuncs, nv10_software_omthds },
-	{}
-};
-
-/*******************************************************************************
- * software context
- ******************************************************************************/
-
-static int
-nv10_software_context_ctor(struct nouveau_object *parent,
-		      struct nouveau_object *engine,
-		      struct nouveau_oclass *oclass, void *data, u32 size,
-		      struct nouveau_object **pobject)
-{
-	struct nv10_software_chan *chan;
-	int ret;
-
-	ret = nouveau_software_context_create(parent, engine, oclass, &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-static struct nouveau_oclass
-nv10_software_cclass = {
-	.handle = NV_ENGCTX(SW, 0x04),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv10_software_context_ctor,
-		.dtor = _nouveau_software_context_dtor,
-		.init = _nouveau_software_context_init,
-		.fini = _nouveau_software_context_fini,
-	},
-};
-
-/*******************************************************************************
- * software engine/subdev functions
- ******************************************************************************/
-
-static int
-nv10_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 size,
-	      struct nouveau_object **pobject)
-{
-	struct nv10_software_priv *priv;
-	int ret;
-
-	ret = nouveau_software_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_engine(priv)->cclass = &nv10_software_cclass;
-	nv_engine(priv)->sclass = nv10_software_sclass;
-	nv_subdev(priv)->intr = nv04_software_intr;
-	return 0;
-}
-
-struct nouveau_oclass *
-nv10_software_oclass = &(struct nouveau_oclass) {
-	.handle = NV_ENGINE(SW, 0x10),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv10_software_ctor,
-		.dtor = _nouveau_software_dtor,
-		.init = _nouveau_software_init,
-		.fini = _nouveau_software_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv50.c b/drivers/gpu/drm/nouveau/core/engine/software/nv50.c
deleted file mode 100644
index a0fec205f9db..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/software/nv50.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/namedb.h>
-#include <core/handle.h>
-#include <core/gpuobj.h>
-#include <core/event.h>
-#include <nvif/event.h>
-
-#include <subdev/bar.h>
-
-#include <engine/disp.h>
-
-#include "nv50.h"
-
-/*******************************************************************************
- * software object classes
- ******************************************************************************/
-
-static int
-nv50_software_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd,
-			      void *args, u32 size)
-{
-	struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
-	struct nouveau_fifo_chan *fifo = (void *)nv_object(chan)->parent;
-	struct nouveau_handle *handle;
-	int ret = -EINVAL;
-
-	handle = nouveau_namedb_get(nv_namedb(fifo), *(u32 *)args);
-	if (!handle)
-		return -ENOENT;
-
-	if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) {
-		struct nouveau_gpuobj *gpuobj = nv_gpuobj(handle->object);
-		chan->vblank.ctxdma = gpuobj->node->offset >> 4;
-		ret = 0;
-	}
-	nouveau_namedb_put(handle);
-	return ret;
-}
-
-static int
-nv50_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
-				 void *args, u32 size)
-{
-	struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
-	chan->vblank.offset = *(u32 *)args;
-	return 0;
-}
-
-int
-nv50_software_mthd_vblsem_value(struct nouveau_object *object, u32 mthd,
-				void *args, u32 size)
-{
-	struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
-	chan->vblank.value = *(u32 *)args;
-	return 0;
-}
-
-int
-nv50_software_mthd_vblsem_release(struct nouveau_object *object, u32 mthd,
-				  void *args, u32 size)
-{
-	struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
-	u32 head = *(u32 *)args;
-	if (head >= nouveau_disp(chan)->vblank.index_nr)
-		return -EINVAL;
-
-	nvkm_notify_get(&chan->vblank.notify[head]);
-	return 0;
-}
-
-int
-nv50_software_mthd_flip(struct nouveau_object *object, u32 mthd,
-			void *args, u32 size)
-{
-	struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
-	if (chan->base.flip)
-		return chan->base.flip(chan->base.flip_data);
-	return -EINVAL;
-}
-
-static struct nouveau_omthds
-nv50_software_omthds[] = {
-	{ 0x018c, 0x018c, nv50_software_mthd_dma_vblsem },
-	{ 0x0400, 0x0400, nv50_software_mthd_vblsem_offset },
-	{ 0x0404, 0x0404, nv50_software_mthd_vblsem_value },
-	{ 0x0408, 0x0408, nv50_software_mthd_vblsem_release },
-	{ 0x0500, 0x0500, nv50_software_mthd_flip },
-	{}
-};
-
-static struct nouveau_oclass
-nv50_software_sclass[] = {
-	{ 0x506e, &nouveau_object_ofuncs, nv50_software_omthds },
-	{}
-};
-
-/*******************************************************************************
- * software context
- ******************************************************************************/
-
-static int
-nv50_software_vblsem_release(struct nvkm_notify *notify)
-{
-	struct nv50_software_chan *chan =
-		container_of(notify, typeof(*chan), vblank.notify[notify->index]);
-	struct nv50_software_priv *priv = (void *)nv_object(chan)->engine;
-	struct nouveau_bar *bar = nouveau_bar(priv);
-
-	nv_wr32(priv, 0x001704, chan->vblank.channel);
-	nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
-	bar->flush(bar);
-
-	if (nv_device(priv)->chipset == 0x50) {
-		nv_wr32(priv, 0x001570, chan->vblank.offset);
-		nv_wr32(priv, 0x001574, chan->vblank.value);
-	} else {
-		nv_wr32(priv, 0x060010, chan->vblank.offset);
-		nv_wr32(priv, 0x060014, chan->vblank.value);
-	}
-
-	return NVKM_NOTIFY_DROP;
-}
-
-void
-nv50_software_context_dtor(struct nouveau_object *object)
-{
-	struct nv50_software_chan *chan = (void *)object;
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(chan->vblank.notify); i++)
-		nvkm_notify_fini(&chan->vblank.notify[i]);
-
-	nouveau_software_context_destroy(&chan->base);
-}
-
-int
-nv50_software_context_ctor(struct nouveau_object *parent,
-			   struct nouveau_object *engine,
-			   struct nouveau_oclass *oclass, void *data, u32 size,
-			   struct nouveau_object **pobject)
-{
-	struct nouveau_disp *pdisp = nouveau_disp(parent);
-	struct nv50_software_cclass *pclass = (void *)oclass;
-	struct nv50_software_chan *chan;
-	int ret, i;
-
-	ret = nouveau_software_context_create(parent, engine, oclass, &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	for (i = 0; pdisp && i < pdisp->vblank.index_nr; i++) {
-		ret = nvkm_notify_init(NULL, &pdisp->vblank, pclass->vblank,
-				       false,
-				       &(struct nvif_notify_head_req_v0) {
-					.head = i,
-				       },
-				       sizeof(struct nvif_notify_head_req_v0),
-				       sizeof(struct nvif_notify_head_rep_v0),
-				       &chan->vblank.notify[i]);
-		if (ret)
-			return ret;
-	}
-
-	chan->vblank.channel = nv_gpuobj(parent->parent)->addr >> 12;
-	return 0;
-}
-
-static struct nv50_software_cclass
-nv50_software_cclass = {
-	.base.handle = NV_ENGCTX(SW, 0x50),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_software_context_ctor,
-		.dtor = nv50_software_context_dtor,
-		.init = _nouveau_software_context_init,
-		.fini = _nouveau_software_context_fini,
-	},
-	.vblank = nv50_software_vblsem_release,
-};
-
-/*******************************************************************************
- * software engine/subdev functions
- ******************************************************************************/
-
-int
-nv50_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		   struct nouveau_oclass *oclass, void *data, u32 size,
-		   struct nouveau_object **pobject)
-{
-	struct nv50_software_oclass *pclass = (void *)oclass;
-	struct nv50_software_priv *priv;
-	int ret;
-
-	ret = nouveau_software_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_engine(priv)->cclass = pclass->cclass;
-	nv_engine(priv)->sclass = pclass->sclass;
-	nv_subdev(priv)->intr = nv04_software_intr;
-	return 0;
-}
-
-struct nouveau_oclass *
-nv50_software_oclass = &(struct nv50_software_oclass) {
-	.base.handle = NV_ENGINE(SW, 0x50),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_software_ctor,
-		.dtor = _nouveau_software_dtor,
-		.init = _nouveau_software_init,
-		.fini = _nouveau_software_fini,
-	},
-	.cclass = &nv50_software_cclass.base,
-	.sclass =  nv50_software_sclass,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv50.h b/drivers/gpu/drm/nouveau/core/engine/software/nv50.h
deleted file mode 100644
index 41542e725b4b..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/software/nv50.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef __NVKM_SW_NV50_H__
-#define __NVKM_SW_NV50_H__
-
-#include <engine/software.h>
-
-struct nv50_software_oclass {
-	struct nouveau_oclass base;
-	struct nouveau_oclass *cclass;
-	struct nouveau_oclass *sclass;
-};
-
-struct nv50_software_priv {
-	struct nouveau_software base;
-};
-
-int  nv50_software_ctor(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, void *, u32,
-			struct nouveau_object **);
-
-struct nv50_software_cclass {
-	struct nouveau_oclass base;
-	int (*vblank)(struct nvkm_notify *);
-};
-
-struct nv50_software_chan {
-	struct nouveau_software_chan base;
-	struct {
-		struct nvkm_notify notify[4];
-		u32 channel;
-		u32 ctxdma;
-		u64 offset;
-		u32 value;
-	} vblank;
-};
-
-int  nv50_software_context_ctor(struct nouveau_object *,
-				struct nouveau_object *,
-				struct nouveau_oclass *, void *, u32,
-				struct nouveau_object **);
-void nv50_software_context_dtor(struct nouveau_object *);
-
-int nv50_software_mthd_vblsem_value(struct nouveau_object *, u32, void *, u32);
-int nv50_software_mthd_vblsem_release(struct nouveau_object *, u32, void *, u32);
-int nv50_software_mthd_flip(struct nouveau_object *, u32, void *, u32);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c
deleted file mode 100644
index 6af370d3a06d..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/event.h>
-
-#include <subdev/bar.h>
-
-#include <engine/software.h>
-#include <engine/disp.h>
-
-#include "nv50.h"
-
-/*******************************************************************************
- * software object classes
- ******************************************************************************/
-
-static int
-nvc0_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
-				 void *args, u32 size)
-{
-	struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
-	u64 data = *(u32 *)args;
-	if (mthd == 0x0400) {
-		chan->vblank.offset &= 0x00ffffffffULL;
-		chan->vblank.offset |= data << 32;
-	} else {
-		chan->vblank.offset &= 0xff00000000ULL;
-		chan->vblank.offset |= data;
-	}
-	return 0;
-}
-
-static int
-nvc0_software_mthd_mp_control(struct nouveau_object *object, u32 mthd,
-                              void *args, u32 size)
-{
-	struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
-	struct nv50_software_priv *priv = (void *)nv_object(chan)->engine;
-	u32 data = *(u32 *)args;
-
-	switch (mthd) {
-	case 0x600:
-		nv_wr32(priv, 0x419e00, data); /* MP.PM_UNK000 */
-		break;
-	case 0x644:
-		if (data & ~0x1ffffe)
-			return -EINVAL;
-		nv_wr32(priv, 0x419e44, data); /* MP.TRAP_WARP_ERROR_EN */
-		break;
-	case 0x6ac:
-		nv_wr32(priv, 0x419eac, data); /* MP.PM_UNK0AC */
-		break;
-	default:
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static struct nouveau_omthds
-nvc0_software_omthds[] = {
-	{ 0x0400, 0x0400, nvc0_software_mthd_vblsem_offset },
-	{ 0x0404, 0x0404, nvc0_software_mthd_vblsem_offset },
-	{ 0x0408, 0x0408, nv50_software_mthd_vblsem_value },
-	{ 0x040c, 0x040c, nv50_software_mthd_vblsem_release },
-	{ 0x0500, 0x0500, nv50_software_mthd_flip },
-	{ 0x0600, 0x0600, nvc0_software_mthd_mp_control },
-	{ 0x0644, 0x0644, nvc0_software_mthd_mp_control },
-	{ 0x06ac, 0x06ac, nvc0_software_mthd_mp_control },
-	{}
-};
-
-static struct nouveau_oclass
-nvc0_software_sclass[] = {
-	{ 0x906e, &nouveau_object_ofuncs, nvc0_software_omthds },
-	{}
-};
-
-/*******************************************************************************
- * software context
- ******************************************************************************/
-
-static int
-nvc0_software_vblsem_release(struct nvkm_notify *notify)
-{
-	struct nv50_software_chan *chan =
-		container_of(notify, typeof(*chan), vblank.notify[notify->index]);
-	struct nv50_software_priv *priv = (void *)nv_object(chan)->engine;
-	struct nouveau_bar *bar = nouveau_bar(priv);
-
-	nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
-	bar->flush(bar);
-	nv_wr32(priv, 0x06000c, upper_32_bits(chan->vblank.offset));
-	nv_wr32(priv, 0x060010, lower_32_bits(chan->vblank.offset));
-	nv_wr32(priv, 0x060014, chan->vblank.value);
-
-	return NVKM_NOTIFY_DROP;
-}
-
-static struct nv50_software_cclass
-nvc0_software_cclass = {
-	.base.handle = NV_ENGCTX(SW, 0xc0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_software_context_ctor,
-		.dtor = nv50_software_context_dtor,
-		.init = _nouveau_software_context_init,
-		.fini = _nouveau_software_context_fini,
-	},
-	.vblank = nvc0_software_vblsem_release,
-};
-
-/*******************************************************************************
- * software engine/subdev functions
- ******************************************************************************/
-
-struct nouveau_oclass *
-nvc0_software_oclass = &(struct nv50_software_oclass) {
-	.base.handle = NV_ENGINE(SW, 0xc0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_software_ctor,
-		.dtor = _nouveau_software_dtor,
-		.init = _nouveau_software_init,
-		.fini = _nouveau_software_fini,
-	},
-	.cclass = &nvc0_software_cclass.base,
-	.sclass =  nvc0_software_sclass,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c
deleted file mode 100644
index fd6272b8cdb2..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs, Ilia Mirkin
- */
-
-#include <engine/xtensa.h>
-#include <engine/vp.h>
-
-/*******************************************************************************
- * VP object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv84_vp_sclass[] = {
-	{ 0x7476, &nouveau_object_ofuncs },
-	{},
-};
-
-/*******************************************************************************
- * PVP context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv84_vp_cclass = {
-	.handle = NV_ENGCTX(VP, 0x84),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_xtensa_engctx_ctor,
-		.dtor = _nouveau_engctx_dtor,
-		.init = _nouveau_engctx_init,
-		.fini = _nouveau_engctx_fini,
-		.rd32 = _nouveau_engctx_rd32,
-		.wr32 = _nouveau_engctx_wr32,
-	},
-};
-
-/*******************************************************************************
- * PVP engine/subdev functions
- ******************************************************************************/
-
-static int
-nv84_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	     struct nouveau_oclass *oclass, void *data, u32 size,
-	     struct nouveau_object **pobject)
-{
-	struct nouveau_xtensa *priv;
-	int ret;
-
-	ret = nouveau_xtensa_create(parent, engine, oclass, 0xf000, true,
-				    "PVP", "vp", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x01020000;
-	nv_engine(priv)->cclass = &nv84_vp_cclass;
-	nv_engine(priv)->sclass = nv84_vp_sclass;
-	priv->fifo_val = 0x111;
-	priv->unkd28 = 0x9c544;
-	return 0;
-}
-
-struct nouveau_oclass
-nv84_vp_oclass = {
-	.handle = NV_ENGINE(VP, 0x84),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv84_vp_ctor,
-		.dtor = _nouveau_xtensa_dtor,
-		.init = _nouveau_xtensa_init,
-		.fini = _nouveau_xtensa_fini,
-		.rd32 = _nouveau_xtensa_rd32,
-		.wr32 = _nouveau_xtensa_wr32,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nv98.c b/drivers/gpu/drm/nouveau/core/engine/vp/nv98.c
deleted file mode 100644
index fc9ae0ff1ef5..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/vp/nv98.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
- */
-
-#include <engine/falcon.h>
-#include <engine/vp.h>
-
-struct nv98_vp_priv {
-	struct nouveau_falcon base;
-};
-
-/*******************************************************************************
- * VP object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv98_vp_sclass[] = {
-	{ 0x88b2, &nouveau_object_ofuncs },
-	{ 0x85b2, &nouveau_object_ofuncs },
-	{},
-};
-
-/*******************************************************************************
- * PVP context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv98_vp_cclass = {
-	.handle = NV_ENGCTX(VP, 0x98),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_falcon_context_ctor,
-		.dtor = _nouveau_falcon_context_dtor,
-		.init = _nouveau_falcon_context_init,
-		.fini = _nouveau_falcon_context_fini,
-		.rd32 = _nouveau_falcon_context_rd32,
-		.wr32 = _nouveau_falcon_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PVP engine/subdev functions
- ******************************************************************************/
-
-static int
-nv98_vp_init(struct nouveau_object *object)
-{
-	struct nv98_vp_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_falcon_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x085010, 0x0000ffd2);
-	nv_wr32(priv, 0x08501c, 0x0000fff2);
-	return 0;
-}
-
-static int
-nv98_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	     struct nouveau_oclass *oclass, void *data, u32 size,
-	     struct nouveau_object **pobject)
-{
-	struct nv98_vp_priv *priv;
-	int ret;
-
-	ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true,
-				    "PVP", "vp", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x01020000;
-	nv_engine(priv)->cclass = &nv98_vp_cclass;
-	nv_engine(priv)->sclass = nv98_vp_sclass;
-	return 0;
-}
-
-struct nouveau_oclass
-nv98_vp_oclass = {
-	.handle = NV_ENGINE(VP, 0x98),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv98_vp_ctor,
-		.dtor = _nouveau_falcon_dtor,
-		.init = nv98_vp_init,
-		.fini = _nouveau_falcon_fini,
-		.rd32 = _nouveau_falcon_rd32,
-		.wr32 = _nouveau_falcon_wr32,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/vp/nvc0.c
deleted file mode 100644
index ac1f62aace72..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/vp/nvc0.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright 2012 Maarten Lankhorst
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Maarten Lankhorst
- */
-
-#include <engine/falcon.h>
-#include <engine/vp.h>
-
-struct nvc0_vp_priv {
-	struct nouveau_falcon base;
-};
-
-/*******************************************************************************
- * VP object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nvc0_vp_sclass[] = {
-	{ 0x90b2, &nouveau_object_ofuncs },
-	{},
-};
-
-/*******************************************************************************
- * PVP context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nvc0_vp_cclass = {
-	.handle = NV_ENGCTX(VP, 0xc0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_falcon_context_ctor,
-		.dtor = _nouveau_falcon_context_dtor,
-		.init = _nouveau_falcon_context_init,
-		.fini = _nouveau_falcon_context_fini,
-		.rd32 = _nouveau_falcon_context_rd32,
-		.wr32 = _nouveau_falcon_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PVP engine/subdev functions
- ******************************************************************************/
-
-static int
-nvc0_vp_init(struct nouveau_object *object)
-{
-	struct nvc0_vp_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_falcon_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x085010, 0x0000fff2);
-	nv_wr32(priv, 0x08501c, 0x0000fff2);
-	return 0;
-}
-
-static int
-nvc0_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	     struct nouveau_oclass *oclass, void *data, u32 size,
-	     struct nouveau_object **pobject)
-{
-	struct nvc0_vp_priv *priv;
-	int ret;
-
-	ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true,
-				    "PVP", "vp", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00020000;
-	nv_subdev(priv)->intr = nouveau_falcon_intr;
-	nv_engine(priv)->cclass = &nvc0_vp_cclass;
-	nv_engine(priv)->sclass = nvc0_vp_sclass;
-	return 0;
-}
-
-struct nouveau_oclass
-nvc0_vp_oclass = {
-	.handle = NV_ENGINE(VP, 0xc0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_vp_ctor,
-		.dtor = _nouveau_falcon_dtor,
-		.init = nvc0_vp_init,
-		.fini = _nouveau_falcon_fini,
-		.rd32 = _nouveau_falcon_rd32,
-		.wr32 = _nouveau_falcon_wr32,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nve0.c b/drivers/gpu/drm/nouveau/core/engine/vp/nve0.c
deleted file mode 100644
index d4c3108479c9..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/vp/nve0.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <engine/falcon.h>
-#include <engine/vp.h>
-
-struct nve0_vp_priv {
-	struct nouveau_falcon base;
-};
-
-/*******************************************************************************
- * VP object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nve0_vp_sclass[] = {
-	{ 0x95b2, &nouveau_object_ofuncs },
-	{},
-};
-
-/*******************************************************************************
- * PVP context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nve0_vp_cclass = {
-	.handle = NV_ENGCTX(VP, 0xe0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_falcon_context_ctor,
-		.dtor = _nouveau_falcon_context_dtor,
-		.init = _nouveau_falcon_context_init,
-		.fini = _nouveau_falcon_context_fini,
-		.rd32 = _nouveau_falcon_context_rd32,
-		.wr32 = _nouveau_falcon_context_wr32,
-	},
-};
-
-/*******************************************************************************
- * PVP engine/subdev functions
- ******************************************************************************/
-
-static int
-nve0_vp_init(struct nouveau_object *object)
-{
-	struct nve0_vp_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_falcon_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x085010, 0x0000fff2);
-	nv_wr32(priv, 0x08501c, 0x0000fff2);
-	return 0;
-}
-
-static int
-nve0_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	     struct nouveau_oclass *oclass, void *data, u32 size,
-	     struct nouveau_object **pobject)
-{
-	struct nve0_vp_priv *priv;
-	int ret;
-
-	ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true,
-				    "PVP", "vp", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->unit = 0x00020000;
-	nv_subdev(priv)->intr = nouveau_falcon_intr;
-	nv_engine(priv)->cclass = &nve0_vp_cclass;
-	nv_engine(priv)->sclass = nve0_vp_sclass;
-	return 0;
-}
-
-struct nouveau_oclass
-nve0_vp_oclass = {
-	.handle = NV_ENGINE(VP, 0xe0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nve0_vp_ctor,
-		.dtor = _nouveau_falcon_dtor,
-		.init = nve0_vp_init,
-		.fini = _nouveau_falcon_fini,
-		.rd32 = _nouveau_falcon_rd32,
-		.wr32 = _nouveau_falcon_wr32,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/xtensa.c b/drivers/gpu/drm/nouveau/core/engine/xtensa.c
deleted file mode 100644
index 92384759d2f5..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/xtensa.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * Copyright 2013 Ilia Mirkin
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <engine/xtensa.h>
-
-u32
-_nouveau_xtensa_rd32(struct nouveau_object *object, u64 addr)
-{
-	struct nouveau_xtensa *xtensa = (void *)object;
-	return nv_rd32(xtensa, xtensa->addr + addr);
-}
-
-void
-_nouveau_xtensa_wr32(struct nouveau_object *object, u64 addr, u32 data)
-{
-	struct nouveau_xtensa *xtensa = (void *)object;
-	nv_wr32(xtensa, xtensa->addr + addr, data);
-}
-
-int
-_nouveau_xtensa_engctx_ctor(struct nouveau_object *parent,
-			    struct nouveau_object *engine,
-			    struct nouveau_oclass *oclass, void *data, u32 size,
-			    struct nouveau_object **pobject)
-{
-	struct nouveau_engctx *engctx;
-	int ret;
-
-	ret = nouveau_engctx_create(parent, engine, oclass, NULL,
-				    0x10000, 0x1000,
-				    NVOBJ_FLAG_ZERO_ALLOC, &engctx);
-	*pobject = nv_object(engctx);
-	return ret;
-}
-
-void
-_nouveau_xtensa_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_xtensa *xtensa = (void *)subdev;
-	u32 unk104 = nv_ro32(xtensa, 0xd04);
-	u32 intr = nv_ro32(xtensa, 0xc20);
-	u32 chan = nv_ro32(xtensa, 0xc28);
-	u32 unk10c = nv_ro32(xtensa, 0xd0c);
-
-	if (intr & 0x10)
-		nv_warn(xtensa, "Watchdog interrupt, engine hung.\n");
-	nv_wo32(xtensa, 0xc20, intr);
-	intr = nv_ro32(xtensa, 0xc20);
-	if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) {
-		nv_debug(xtensa, "Enabling FIFO_CTRL\n");
-		nv_mask(xtensa, xtensa->addr + 0xd94, 0, xtensa->fifo_val);
-	}
-}
-
-int
-nouveau_xtensa_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, u32 addr, bool enable,
-		       const char *iname, const char *fname,
-		       int length, void **pobject)
-{
-	struct nouveau_xtensa *xtensa;
-	int ret;
-
-	ret = nouveau_engine_create_(parent, engine, oclass, enable, iname,
-				     fname, length, pobject);
-	xtensa = *pobject;
-	if (ret)
-		return ret;
-
-	nv_subdev(xtensa)->intr = _nouveau_xtensa_intr;
-
-	xtensa->addr = addr;
-
-	return 0;
-}
-
-int
-_nouveau_xtensa_init(struct nouveau_object *object)
-{
-	struct nouveau_device *device = nv_device(object);
-	struct nouveau_xtensa *xtensa = (void *)object;
-	const struct firmware *fw;
-	char name[32];
-	int i, ret;
-	u32 tmp;
-
-	ret = nouveau_engine_init(&xtensa->base);
-	if (ret)
-		return ret;
-
-	if (!xtensa->gpu_fw) {
-		snprintf(name, sizeof(name), "nouveau/nv84_xuc%03x",
-			 xtensa->addr >> 12);
-
-		ret = request_firmware(&fw, name, nv_device_base(device));
-		if (ret) {
-			nv_warn(xtensa, "unable to load firmware %s\n", name);
-			return ret;
-		}
-
-		if (fw->size > 0x40000) {
-			nv_warn(xtensa, "firmware %s too large\n", name);
-			release_firmware(fw);
-			return -EINVAL;
-		}
-
-		ret = nouveau_gpuobj_new(object, NULL, 0x40000, 0x1000, 0,
-					 &xtensa->gpu_fw);
-		if (ret) {
-			release_firmware(fw);
-			return ret;
-		}
-
-		nv_debug(xtensa, "Loading firmware to address: 0x%llx\n",
-			 xtensa->gpu_fw->addr);
-
-		for (i = 0; i < fw->size / 4; i++)
-			nv_wo32(xtensa->gpu_fw, i * 4, *((u32 *)fw->data + i));
-		release_firmware(fw);
-	}
-
-	nv_wo32(xtensa, 0xd10, 0x1fffffff); /* ?? */
-	nv_wo32(xtensa, 0xd08, 0x0fffffff); /* ?? */
-
-	nv_wo32(xtensa, 0xd28, xtensa->unkd28); /* ?? */
-	nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */
-	nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */
-
-	nv_wo32(xtensa, 0xcc0, xtensa->gpu_fw->addr >> 8); /* XT_REGION_BASE */
-	nv_wo32(xtensa, 0xcc4, 0x1c); /* XT_REGION_SETUP */
-	nv_wo32(xtensa, 0xcc8, xtensa->gpu_fw->size >> 8); /* XT_REGION_LIMIT */
-
-	tmp = nv_rd32(xtensa, 0x0);
-	nv_wo32(xtensa, 0xde0, tmp); /* SCRATCH_H2X */
-
-	nv_wo32(xtensa, 0xce8, 0xf); /* XT_REGION_SETUP */
-
-	nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */
-	nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */
-
-	return 0;
-}
-
-int
-_nouveau_xtensa_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nouveau_xtensa *xtensa = (void *)object;
-
-	nv_wo32(xtensa, 0xd84, 0); /* INTR_EN */
-	nv_wo32(xtensa, 0xd94, 0); /* FIFO_CTRL */
-
-	if (!suspend)
-		nouveau_gpuobj_ref(NULL, &xtensa->gpu_fw);
-
-	return nouveau_engine_fini(&xtensa->base, suspend);
-}
diff --git a/drivers/gpu/drm/nouveau/core/include/core/client.h b/drivers/gpu/drm/nouveau/core/include/core/client.h
deleted file mode 100644
index b0ce9f6680b5..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/client.h
+++ /dev/null
@@ -1,57 +0,0 @@
-#ifndef __NOUVEAU_CLIENT_H__
-#define __NOUVEAU_CLIENT_H__
-
-#include <core/namedb.h>
-
-struct nouveau_client {
-	struct nouveau_namedb base;
-	struct nouveau_handle *root;
-	struct nouveau_object *device;
-	char name[32];
-	u32 debug;
-	struct nouveau_vm *vm;
-	bool super;
-	void *data;
-
-	int (*ntfy)(const void *, u32, const void *, u32);
-	struct nvkm_client_notify *notify[16];
-};
-
-static inline struct nouveau_client *
-nv_client(void *obj)
-{
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
-	if (unlikely(!nv_iclass(obj, NV_CLIENT_CLASS)))
-		nv_assert("BAD CAST -> NvClient, %08x", nv_hclass(obj));
-#endif
-	return obj;
-}
-
-static inline struct nouveau_client *
-nouveau_client(void *obj)
-{
-	struct nouveau_object *client = nv_object(obj);
-	while (client && !(nv_iclass(client, NV_CLIENT_CLASS)))
-		client = client->parent;
-	return (void *)client;
-}
-
-#define nouveau_client_create(n,c,oc,od,d)                                     \
-	nouveau_client_create_((n), (c), (oc), (od), sizeof(**d), (void **)d)
-
-int  nouveau_client_create_(const char *name, u64 device, const char *cfg,
-			    const char *dbg, int, void **);
-#define nouveau_client_destroy(p)                                              \
-	nouveau_namedb_destroy(&(p)->base)
-
-int  nouveau_client_init(struct nouveau_client *);
-int  nouveau_client_fini(struct nouveau_client *, bool suspend);
-const char *nouveau_client_name(void *obj);
-
-int nvkm_client_notify_new(struct nouveau_object *, struct nvkm_event *,
-			   void *data, u32 size);
-int nvkm_client_notify_del(struct nouveau_client *, int index);
-int nvkm_client_notify_get(struct nouveau_client *, int index);
-int nvkm_client_notify_put(struct nouveau_client *, int index);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/debug.h b/drivers/gpu/drm/nouveau/core/include/core/debug.h
deleted file mode 100644
index 8092e2e90323..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/debug.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __NOUVEAU_DEBUG_H__
-#define __NOUVEAU_DEBUG_H__
-
-extern int nv_info_debug_level;
-
-#define NV_DBG_FATAL    0
-#define NV_DBG_ERROR    1
-#define NV_DBG_WARN     2
-#define NV_DBG_INFO     nv_info_debug_level
-#define NV_DBG_DEBUG    4
-#define NV_DBG_TRACE    5
-#define NV_DBG_PARANOIA 6
-#define NV_DBG_SPAM     7
-
-#define NV_DBG_INFO_NORMAL 3
-#define NV_DBG_INFO_SILENT NV_DBG_DEBUG
-
-#define nv_debug_level(a) nv_info_debug_level = NV_DBG_INFO_##a
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/device.h b/drivers/gpu/drm/nouveau/core/include/core/device.h
deleted file mode 100644
index 2ec2e50d3676..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/device.h
+++ /dev/null
@@ -1,184 +0,0 @@
-#ifndef __NOUVEAU_DEVICE_H__
-#define __NOUVEAU_DEVICE_H__
-
-#include <core/object.h>
-#include <core/subdev.h>
-#include <core/engine.h>
-#include <core/event.h>
-
-enum nv_subdev_type {
-	NVDEV_ENGINE_DEVICE,
-	NVDEV_SUBDEV_VBIOS,
-
-	/* All subdevs from DEVINIT to DEVINIT_LAST will be created before
-	 * *any* of them are initialised.  This subdev category is used
-	 * for any subdevs that the VBIOS init table parsing may call out
-	 * to during POST.
-	 */
-	NVDEV_SUBDEV_DEVINIT,
-	NVDEV_SUBDEV_IBUS,
-	NVDEV_SUBDEV_GPIO,
-	NVDEV_SUBDEV_I2C,
-	NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C,
-
-	/* This grouping of subdevs are initialised right after they've
-	 * been created, and are allowed to assume any subdevs in the
-	 * list above them exist and have been initialised.
-	 */
-	NVDEV_SUBDEV_FUSE,
-	NVDEV_SUBDEV_MXM,
-	NVDEV_SUBDEV_MC,
-	NVDEV_SUBDEV_BUS,
-	NVDEV_SUBDEV_TIMER,
-	NVDEV_SUBDEV_FB,
-	NVDEV_SUBDEV_LTC,
-	NVDEV_SUBDEV_INSTMEM,
-	NVDEV_SUBDEV_VM,
-	NVDEV_SUBDEV_BAR,
-	NVDEV_SUBDEV_PWR,
-	NVDEV_SUBDEV_VOLT,
-	NVDEV_SUBDEV_THERM,
-	NVDEV_SUBDEV_CLOCK,
-
-	NVDEV_ENGINE_FIRST,
-	NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST,
-	NVDEV_ENGINE_IFB,
-	NVDEV_ENGINE_FIFO,
-	NVDEV_ENGINE_SW,
-	NVDEV_ENGINE_GR,
-	NVDEV_ENGINE_MPEG,
-	NVDEV_ENGINE_ME,
-	NVDEV_ENGINE_VP,
-	NVDEV_ENGINE_CRYPT,
-	NVDEV_ENGINE_BSP,
-	NVDEV_ENGINE_PPP,
-	NVDEV_ENGINE_COPY0,
-	NVDEV_ENGINE_COPY1,
-	NVDEV_ENGINE_COPY2,
-	NVDEV_ENGINE_VIC,
-	NVDEV_ENGINE_VENC,
-	NVDEV_ENGINE_DISP,
-	NVDEV_ENGINE_PERFMON,
-
-	NVDEV_SUBDEV_NR,
-};
-
-struct nouveau_device {
-	struct nouveau_engine base;
-	struct list_head head;
-
-	struct pci_dev *pdev;
-	struct platform_device *platformdev;
-	u64 handle;
-
-	struct nvkm_event event;
-
-	const char *cfgopt;
-	const char *dbgopt;
-	const char *name;
-	const char *cname;
-	u64 disable_mask;
-
-	enum {
-		NV_04    = 0x04,
-		NV_10    = 0x10,
-		NV_11    = 0x11,
-		NV_20    = 0x20,
-		NV_30    = 0x30,
-		NV_40    = 0x40,
-		NV_50    = 0x50,
-		NV_C0    = 0xc0,
-		NV_E0    = 0xe0,
-		GM100    = 0x110,
-	} card_type;
-	u32 chipset;
-	u8  chiprev;
-	u32 crystal;
-
-	struct nouveau_oclass *oclass[NVDEV_SUBDEV_NR];
-	struct nouveau_object *subdev[NVDEV_SUBDEV_NR];
-
-	struct {
-		struct notifier_block nb;
-	} acpi;
-};
-
-int nouveau_device_list(u64 *name, int size);
-
-static inline struct nouveau_device *
-nv_device(void *obj)
-{
-	struct nouveau_object *object = nv_object(obj);
-	struct nouveau_object *device = object;
-
-	if (device->engine)
-		device = device->engine;
-	if (device->parent)
-		device = device->parent;
-
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
-	if (unlikely(!nv_iclass(device, NV_SUBDEV_CLASS) ||
-		     (nv_hclass(device) & 0xff) != NVDEV_ENGINE_DEVICE)) {
-		nv_assert("BAD CAST -> NvDevice, 0x%08x 0x%08x",
-			  nv_hclass(object), nv_hclass(device));
-	}
-#endif
-
-	return (void *)device;
-}
-
-static inline struct nouveau_subdev *
-nouveau_subdev(void *obj, int sub)
-{
-	if (nv_device(obj)->subdev[sub])
-		return nv_subdev(nv_device(obj)->subdev[sub]);
-	return NULL;
-}
-
-static inline struct nouveau_engine *
-nouveau_engine(void *obj, int sub)
-{
-	struct nouveau_subdev *subdev = nouveau_subdev(obj, sub);
-	if (subdev && nv_iclass(subdev, NV_ENGINE_CLASS))
-		return nv_engine(subdev);
-	return NULL;
-}
-
-static inline bool
-nv_device_match(struct nouveau_object *object, u16 dev, u16 ven, u16 sub)
-{
-	struct nouveau_device *device = nv_device(object);
-	return device->pdev->device == dev &&
-	       device->pdev->subsystem_vendor == ven &&
-	       device->pdev->subsystem_device == sub;
-}
-
-static inline bool
-nv_device_is_pci(struct nouveau_device *device)
-{
-	return device->pdev != NULL;
-}
-
-static inline bool
-nv_device_is_cpu_coherent(struct nouveau_device *device)
-{
-	return (!IS_ENABLED(CONFIG_ARM) && nv_device_is_pci(device));
-}
-
-static inline struct device *
-nv_device_base(struct nouveau_device *device)
-{
-	return nv_device_is_pci(device) ? &device->pdev->dev :
-					  &device->platformdev->dev;
-}
-
-resource_size_t
-nv_device_resource_start(struct nouveau_device *device, unsigned int bar);
-
-resource_size_t
-nv_device_resource_len(struct nouveau_device *device, unsigned int bar);
-
-int
-nv_device_get_irq(struct nouveau_device *device, bool stall);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/engctx.h b/drivers/gpu/drm/nouveau/core/include/core/engctx.h
deleted file mode 100644
index 2fd48b564c7d..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/engctx.h
+++ /dev/null
@@ -1,54 +0,0 @@
-#ifndef __NOUVEAU_ENGCTX_H__
-#define __NOUVEAU_ENGCTX_H__
-
-#include <core/object.h>
-#include <core/gpuobj.h>
-
-#include <subdev/vm.h>
-
-#define NV_ENGCTX_(eng,var) (NV_ENGCTX_CLASS | ((var) << 8) | (eng))
-#define NV_ENGCTX(name,var)  NV_ENGCTX_(NVDEV_ENGINE_##name, (var))
-
-struct nouveau_engctx {
-	struct nouveau_gpuobj base;
-	struct nouveau_vma vma;
-	struct list_head head;
-	unsigned long save;
-	u64 addr;
-};
-
-static inline struct nouveau_engctx *
-nv_engctx(void *obj)
-{
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
-	if (unlikely(!nv_iclass(obj, NV_ENGCTX_CLASS)))
-		nv_assert("BAD CAST -> NvEngCtx, %08x", nv_hclass(obj));
-#endif
-	return obj;
-}
-
-#define nouveau_engctx_create(p,e,c,g,s,a,f,d)                                 \
-	nouveau_engctx_create_((p), (e), (c), (g), (s), (a), (f),              \
-			       sizeof(**d), (void **)d)
-
-int  nouveau_engctx_create_(struct nouveau_object *, struct nouveau_object *,
-			    struct nouveau_oclass *, struct nouveau_object *,
-			    u32 size, u32 align, u32 flags,
-			    int length, void **data);
-void nouveau_engctx_destroy(struct nouveau_engctx *);
-int  nouveau_engctx_init(struct nouveau_engctx *);
-int  nouveau_engctx_fini(struct nouveau_engctx *, bool suspend);
-
-int  _nouveau_engctx_ctor(struct nouveau_object *, struct nouveau_object *,
-			  struct nouveau_oclass *, void *, u32,
-			  struct nouveau_object **);
-void _nouveau_engctx_dtor(struct nouveau_object *);
-int  _nouveau_engctx_init(struct nouveau_object *);
-int  _nouveau_engctx_fini(struct nouveau_object *, bool suspend);
-#define _nouveau_engctx_rd32 _nouveau_gpuobj_rd32
-#define _nouveau_engctx_wr32 _nouveau_gpuobj_wr32
-
-struct nouveau_object *nouveau_engctx_get(struct nouveau_engine *, u64 addr);
-void nouveau_engctx_put(struct nouveau_object *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/engine.h b/drivers/gpu/drm/nouveau/core/include/core/engine.h
deleted file mode 100644
index 666d06de77ec..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/engine.h
+++ /dev/null
@@ -1,57 +0,0 @@
-#ifndef __NOUVEAU_ENGINE_H__
-#define __NOUVEAU_ENGINE_H__
-
-#include <core/object.h>
-#include <core/subdev.h>
-
-#define NV_ENGINE_(eng,var) (NV_ENGINE_CLASS | ((var) << 8) | (eng))
-#define NV_ENGINE(name,var)  NV_ENGINE_(NVDEV_ENGINE_##name, (var))
-
-struct nouveau_engine {
-	struct nouveau_subdev base;
-	struct nouveau_oclass *cclass;
-	struct nouveau_oclass *sclass;
-
-	struct list_head contexts;
-	spinlock_t lock;
-
-	void (*tile_prog)(struct nouveau_engine *, int region);
-	int  (*tlb_flush)(struct nouveau_engine *);
-};
-
-static inline struct nouveau_engine *
-nv_engine(void *obj)
-{
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
-	if (unlikely(!nv_iclass(obj, NV_ENGINE_CLASS)))
-		nv_assert("BAD CAST -> NvEngine, %08x", nv_hclass(obj));
-#endif
-	return obj;
-}
-
-static inline int
-nv_engidx(struct nouveau_object *object)
-{
-	return nv_subidx(object);
-}
-
-#define nouveau_engine_create(p,e,c,d,i,f,r)                                   \
-	nouveau_engine_create_((p), (e), (c), (d), (i), (f),                   \
-			       sizeof(**r),(void **)r)
-
-#define nouveau_engine_destroy(p)                                              \
-	nouveau_subdev_destroy(&(p)->base)
-#define nouveau_engine_init(p)                                                 \
-	nouveau_subdev_init(&(p)->base)
-#define nouveau_engine_fini(p,s)                                               \
-	nouveau_subdev_fini(&(p)->base, (s))
-
-int nouveau_engine_create_(struct nouveau_object *, struct nouveau_object *,
-			   struct nouveau_oclass *, bool, const char *,
-			   const char *, int, void **);
-
-#define _nouveau_engine_dtor _nouveau_subdev_dtor
-#define _nouveau_engine_init _nouveau_subdev_init
-#define _nouveau_engine_fini _nouveau_subdev_fini
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/enum.h b/drivers/gpu/drm/nouveau/core/include/core/enum.h
deleted file mode 100644
index 4fc62bb8c1f0..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/enum.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef __NOUVEAU_ENUM_H__
-#define __NOUVEAU_ENUM_H__
-
-struct nouveau_enum {
-	u32 value;
-	const char *name;
-	const void *data;
-	u32 data2;
-};
-
-const struct nouveau_enum *
-nouveau_enum_find(const struct nouveau_enum *, u32 value);
-
-const struct nouveau_enum *
-nouveau_enum_print(const struct nouveau_enum *en, u32 value);
-
-struct nouveau_bitfield {
-	u32 mask;
-	const char *name;
-};
-
-void nouveau_bitfield_print(const struct nouveau_bitfield *, u32 value);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/event.h b/drivers/gpu/drm/nouveau/core/include/core/event.h
deleted file mode 100644
index 92876528972f..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/event.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef __NVKM_EVENT_H__
-#define __NVKM_EVENT_H__
-
-#include <core/notify.h>
-
-struct nvkm_event_func {
-	int  (*ctor)(struct nouveau_object *, void *data, u32 size,
-		     struct nvkm_notify *);
-	void (*send)(void *data, u32 size, struct nvkm_notify *);
-	void (*init)(struct nvkm_event *, int type, int index);
-	void (*fini)(struct nvkm_event *, int type, int index);
-};
-
-struct nvkm_event {
-	const struct nvkm_event_func *func;
-
-	int types_nr;
-	int index_nr;
-
-	spinlock_t refs_lock;
-	spinlock_t list_lock;
-	struct list_head list;
-	int *refs;
-};
-
-int  nvkm_event_init(const struct nvkm_event_func *func,
-		     int types_nr, int index_nr,
-		     struct nvkm_event *);
-void nvkm_event_fini(struct nvkm_event *);
-void nvkm_event_get(struct nvkm_event *, u32 types, int index);
-void nvkm_event_put(struct nvkm_event *, u32 types, int index);
-void nvkm_event_send(struct nvkm_event *, u32 types, int index,
-		     void *data, u32 size);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/gpuobj.h b/drivers/gpu/drm/nouveau/core/include/core/gpuobj.h
deleted file mode 100644
index b3b9ce4e9d38..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/gpuobj.h
+++ /dev/null
@@ -1,71 +0,0 @@
-#ifndef __NOUVEAU_GPUOBJ_H__
-#define __NOUVEAU_GPUOBJ_H__
-
-#include <core/object.h>
-#include <core/device.h>
-#include <core/parent.h>
-#include <core/mm.h>
-
-struct nouveau_vma;
-struct nouveau_vm;
-
-#define NVOBJ_FLAG_ZERO_ALLOC 0x00000001
-#define NVOBJ_FLAG_ZERO_FREE  0x00000002
-#define NVOBJ_FLAG_HEAP       0x00000004
-
-struct nouveau_gpuobj {
-	struct nouveau_object base;
-	struct nouveau_object *parent;
-	struct nouveau_mm_node *node;
-	struct nouveau_mm heap;
-
-	u32 flags;
-	u64 addr;
-	u32 size;
-};
-
-static inline struct nouveau_gpuobj *
-nv_gpuobj(void *obj)
-{
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
-	if (unlikely(!nv_iclass(obj, NV_GPUOBJ_CLASS)))
-		nv_assert("BAD CAST -> NvGpuObj, %08x", nv_hclass(obj));
-#endif
-	return obj;
-}
-
-#define nouveau_gpuobj_create(p,e,c,v,g,s,a,f,d)                               \
-	nouveau_gpuobj_create_((p), (e), (c), (v), (g), (s), (a), (f),         \
-			       sizeof(**d), (void **)d)
-#define nouveau_gpuobj_init(p) nouveau_object_init(&(p)->base)
-#define nouveau_gpuobj_fini(p,s) nouveau_object_fini(&(p)->base, (s))
-int  nouveau_gpuobj_create_(struct nouveau_object *, struct nouveau_object *,
-			    struct nouveau_oclass *, u32 pclass,
-			    struct nouveau_object *, u32 size, u32 align,
-			    u32 flags, int length, void **);
-void nouveau_gpuobj_destroy(struct nouveau_gpuobj *);
-
-int nouveau_gpuobj_new(struct nouveau_object *, struct nouveau_object *,
-		       u32 size, u32 align, u32 flags,
-		       struct nouveau_gpuobj **);
-int nouveau_gpuobj_dup(struct nouveau_object *, struct nouveau_gpuobj *,
-		       struct nouveau_gpuobj **);
-
-int nouveau_gpuobj_map(struct nouveau_gpuobj *, u32 acc, struct nouveau_vma *);
-int nouveau_gpuobj_map_vm(struct nouveau_gpuobj *, struct nouveau_vm *,
-			  u32 access, struct nouveau_vma *);
-void nouveau_gpuobj_unmap(struct nouveau_vma *);
-
-static inline void
-nouveau_gpuobj_ref(struct nouveau_gpuobj *obj, struct nouveau_gpuobj **ref)
-{
-	nouveau_object_ref(&obj->base, (struct nouveau_object **)ref);
-}
-
-void _nouveau_gpuobj_dtor(struct nouveau_object *);
-int  _nouveau_gpuobj_init(struct nouveau_object *);
-int  _nouveau_gpuobj_fini(struct nouveau_object *, bool);
-u32  _nouveau_gpuobj_rd32(struct nouveau_object *, u64);
-void _nouveau_gpuobj_wr32(struct nouveau_object *, u64, u32);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/handle.h b/drivers/gpu/drm/nouveau/core/include/core/handle.h
deleted file mode 100644
index d22a59138a9b..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/handle.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef __NOUVEAU_HANDLE_H__
-#define __NOUVEAU_HANDLE_H__
-
-struct nouveau_handle {
-	struct nouveau_namedb *namedb;
-	struct list_head node;
-
-	struct list_head head;
-	struct list_head tree;
-	u32 name;
-	u32 priv;
-
-	u8  route;
-	u64 token;
-
-	struct nouveau_handle *parent;
-	struct nouveau_object *object;
-};
-
-int  nouveau_handle_create(struct nouveau_object *, u32 parent, u32 handle,
-			   struct nouveau_object *, struct nouveau_handle **);
-void nouveau_handle_destroy(struct nouveau_handle *);
-int  nouveau_handle_init(struct nouveau_handle *);
-int  nouveau_handle_fini(struct nouveau_handle *, bool suspend);
-
-struct nouveau_object *
-nouveau_handle_ref(struct nouveau_object *, u32 name);
-
-struct nouveau_handle *nouveau_handle_get_class(struct nouveau_object *, u16);
-struct nouveau_handle *nouveau_handle_get_vinst(struct nouveau_object *, u64);
-struct nouveau_handle *nouveau_handle_get_cinst(struct nouveau_object *, u32);
-void nouveau_handle_put(struct nouveau_handle *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/ioctl.h b/drivers/gpu/drm/nouveau/core/include/core/ioctl.h
deleted file mode 100644
index ac7935c2474e..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/ioctl.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __NVKM_IOCTL_H__
-#define __NVKM_IOCTL_H__
-
-int nvkm_ioctl(struct nouveau_client *, bool, void *, u32, void **);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/mm.h b/drivers/gpu/drm/nouveau/core/include/core/mm.h
deleted file mode 100644
index bfe6931544fe..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/mm.h
+++ /dev/null
@@ -1,40 +0,0 @@
-#ifndef __NOUVEAU_MM_H__
-#define __NOUVEAU_MM_H__
-
-struct nouveau_mm_node {
-	struct list_head nl_entry;
-	struct list_head fl_entry;
-	struct list_head rl_entry;
-
-#define NVKM_MM_HEAP_ANY 0x00
-	u8  heap;
-#define NVKM_MM_TYPE_NONE 0x00
-#define NVKM_MM_TYPE_HOLE 0xff
-	u8  type;
-	u32 offset;
-	u32 length;
-};
-
-struct nouveau_mm {
-	struct list_head nodes;
-	struct list_head free;
-
-	u32 block_size;
-	int heap_nodes;
-};
-
-static inline bool
-nouveau_mm_initialised(struct nouveau_mm *mm)
-{
-	return mm->block_size != 0;
-}
-
-int  nouveau_mm_init(struct nouveau_mm *, u32 offset, u32 length, u32 block);
-int  nouveau_mm_fini(struct nouveau_mm *);
-int  nouveau_mm_head(struct nouveau_mm *, u8 heap, u8 type, u32 size_max,
-		     u32 size_min, u32 align, struct nouveau_mm_node **);
-int  nouveau_mm_tail(struct nouveau_mm *, u8 heap, u8 type, u32 size_max,
-		     u32 size_min, u32 align, struct nouveau_mm_node **);
-void nouveau_mm_free(struct nouveau_mm *, struct nouveau_mm_node **);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/namedb.h b/drivers/gpu/drm/nouveau/core/include/core/namedb.h
deleted file mode 100644
index f5b5fd8e1fc9..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/namedb.h
+++ /dev/null
@@ -1,56 +0,0 @@
-#ifndef __NOUVEAU_NAMEDB_H__
-#define __NOUVEAU_NAMEDB_H__
-
-#include <core/parent.h>
-
-struct nouveau_handle;
-
-struct nouveau_namedb {
-	struct nouveau_parent base;
-	rwlock_t lock;
-	struct list_head list;
-};
-
-static inline struct nouveau_namedb *
-nv_namedb(void *obj)
-{
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
-	if (unlikely(!nv_iclass(obj, NV_NAMEDB_CLASS)))
-		nv_assert("BAD CAST -> NvNameDB, %08x", nv_hclass(obj));
-#endif
-	return obj;
-}
-
-#define nouveau_namedb_create(p,e,c,v,s,m,d)                                   \
-	nouveau_namedb_create_((p), (e), (c), (v), (s), (m),                   \
-			       sizeof(**d), (void **)d)
-#define nouveau_namedb_init(p)                                                 \
-	nouveau_parent_init(&(p)->base)
-#define nouveau_namedb_fini(p,s)                                               \
-	nouveau_parent_fini(&(p)->base, (s))
-#define nouveau_namedb_destroy(p)                                              \
-	nouveau_parent_destroy(&(p)->base)
-
-int  nouveau_namedb_create_(struct nouveau_object *, struct nouveau_object *,
-			    struct nouveau_oclass *, u32 pclass,
-			    struct nouveau_oclass *, u64 engcls,
-			    int size, void **);
-
-int  _nouveau_namedb_ctor(struct nouveau_object *, struct nouveau_object *,
-			  struct nouveau_oclass *, void *, u32,
-			  struct nouveau_object **);
-#define _nouveau_namedb_dtor _nouveau_parent_dtor
-#define _nouveau_namedb_init _nouveau_parent_init
-#define _nouveau_namedb_fini _nouveau_parent_fini
-
-int  nouveau_namedb_insert(struct nouveau_namedb *, u32 name,
-			   struct nouveau_object *, struct nouveau_handle *);
-void nouveau_namedb_remove(struct nouveau_handle *);
-
-struct nouveau_handle *nouveau_namedb_get(struct nouveau_namedb *, u32);
-struct nouveau_handle *nouveau_namedb_get_class(struct nouveau_namedb *, u16);
-struct nouveau_handle *nouveau_namedb_get_vinst(struct nouveau_namedb *, u64);
-struct nouveau_handle *nouveau_namedb_get_cinst(struct nouveau_namedb *, u32);
-void nouveau_namedb_put(struct nouveau_handle *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/notify.h b/drivers/gpu/drm/nouveau/core/include/core/notify.h
deleted file mode 100644
index a7c3c5f578cc..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/notify.h
+++ /dev/null
@@ -1,37 +0,0 @@
-#ifndef __NVKM_NOTIFY_H__
-#define __NVKM_NOTIFY_H__
-
-struct nvkm_notify {
-	struct nvkm_event *event;
-	struct list_head head;
-#define NVKM_NOTIFY_USER 0
-#define NVKM_NOTIFY_WORK 1
-	unsigned long flags;
-	int block;
-#define NVKM_NOTIFY_DROP 0
-#define NVKM_NOTIFY_KEEP 1
-	int (*func)(struct nvkm_notify *);
-
-	/* set by nvkm_event ctor */
-	u32 types;
-	int index;
-	u32 size;
-
-	struct work_struct work;
-	/* this is const for a *very* good reason - the data might be on the
-	 * stack from an irq handler.  if you're not core/notify.c then you
-	 * should probably think twice before casting it away...
-	 */
-	const void *data;
-};
-
-int  nvkm_notify_init(struct nouveau_object *, struct nvkm_event *,
-		      int (*func)(struct nvkm_notify *), bool work,
-		      void *data, u32 size, u32 reply,
-		      struct nvkm_notify *);
-void nvkm_notify_fini(struct nvkm_notify *);
-void nvkm_notify_get(struct nvkm_notify *);
-void nvkm_notify_put(struct nvkm_notify *);
-void nvkm_notify_send(struct nvkm_notify *, void *data, u32 size);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/object.h b/drivers/gpu/drm/nouveau/core/include/core/object.h
deleted file mode 100644
index 2e2afa502c99..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/object.h
+++ /dev/null
@@ -1,206 +0,0 @@
-#ifndef __NOUVEAU_OBJECT_H__
-#define __NOUVEAU_OBJECT_H__
-
-#include <core/os.h>
-#include <core/printk.h>
-
-#define NV_PARENT_CLASS 0x80000000
-#define NV_NAMEDB_CLASS 0x40000000
-#define NV_CLIENT_CLASS 0x20000000
-#define NV_SUBDEV_CLASS 0x10000000
-#define NV_ENGINE_CLASS 0x08000000
-#define NV_MEMOBJ_CLASS 0x04000000
-#define NV_GPUOBJ_CLASS 0x02000000
-#define NV_ENGCTX_CLASS 0x01000000
-#define NV_OBJECT_CLASS 0x0000ffff
-
-struct nouveau_object {
-	struct nouveau_oclass *oclass;
-	struct nouveau_object *parent;
-	struct nouveau_object *engine;
-	atomic_t refcount;
-	atomic_t usecount;
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
-#define NOUVEAU_OBJECT_MAGIC 0x75ef0bad
-	struct list_head list;
-	u32 _magic;
-#endif
-};
-
-static inline struct nouveau_object *
-nv_object(void *obj)
-{
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
-	if (likely(obj)) {
-		struct nouveau_object *object = obj;
-		if (unlikely(object->_magic != NOUVEAU_OBJECT_MAGIC))
-			nv_assert("BAD CAST -> NvObject, invalid magic");
-	}
-#endif
-	return obj;
-}
-
-#define nouveau_object_create(p,e,c,s,d)                                       \
-	nouveau_object_create_((p), (e), (c), (s), sizeof(**d), (void **)d)
-int  nouveau_object_create_(struct nouveau_object *, struct nouveau_object *,
-			    struct nouveau_oclass *, u32, int size, void **);
-void nouveau_object_destroy(struct nouveau_object *);
-int  nouveau_object_init(struct nouveau_object *);
-int  nouveau_object_fini(struct nouveau_object *, bool suspend);
-
-int _nouveau_object_ctor(struct nouveau_object *, struct nouveau_object *,
-			 struct nouveau_oclass *, void *, u32,
-			 struct nouveau_object **);
-
-extern struct nouveau_ofuncs nouveau_object_ofuncs;
-
-/* Don't allocate dynamically, because lockdep needs lock_class_keys to be in
- * ".data". */
-struct nouveau_oclass {
-	u32 handle;
-	struct nouveau_ofuncs * const ofuncs;
-	struct nouveau_omthds * const omthds;
-	struct lock_class_key lock_class_key;
-};
-
-#define nv_oclass(o)    nv_object(o)->oclass
-#define nv_hclass(o)    nv_oclass(o)->handle
-#define nv_iclass(o,i) (nv_hclass(o) & (i))
-#define nv_mclass(o)    nv_iclass(o, NV_OBJECT_CLASS)
-
-static inline struct nouveau_object *
-nv_pclass(struct nouveau_object *parent, u32 oclass)
-{
-	while (parent && !nv_iclass(parent, oclass))
-		parent = parent->parent;
-	return parent;
-}
-
-struct nouveau_omthds {
-	u32 start;
-	u32 limit;
-	int (*call)(struct nouveau_object *, u32, void *, u32);
-};
-
-struct nvkm_event;
-struct nouveau_ofuncs {
-	int  (*ctor)(struct nouveau_object *, struct nouveau_object *,
-		     struct nouveau_oclass *, void *data, u32 size,
-		     struct nouveau_object **);
-	void (*dtor)(struct nouveau_object *);
-	int  (*init)(struct nouveau_object *);
-	int  (*fini)(struct nouveau_object *, bool suspend);
-	int  (*mthd)(struct nouveau_object *, u32, void *, u32);
-	int  (*ntfy)(struct nouveau_object *, u32, struct nvkm_event **);
-	int  (* map)(struct nouveau_object *, u64 *, u32 *);
-	u8   (*rd08)(struct nouveau_object *, u64 offset);
-	u16  (*rd16)(struct nouveau_object *, u64 offset);
-	u32  (*rd32)(struct nouveau_object *, u64 offset);
-	void (*wr08)(struct nouveau_object *, u64 offset, u8 data);
-	void (*wr16)(struct nouveau_object *, u64 offset, u16 data);
-	void (*wr32)(struct nouveau_object *, u64 offset, u32 data);
-};
-
-static inline struct nouveau_ofuncs *
-nv_ofuncs(void *obj)
-{
-	return nv_oclass(obj)->ofuncs;
-}
-
-int  nouveau_object_ctor(struct nouveau_object *, struct nouveau_object *,
-			 struct nouveau_oclass *, void *, u32,
-			 struct nouveau_object **);
-void nouveau_object_ref(struct nouveau_object *, struct nouveau_object **);
-int nouveau_object_inc(struct nouveau_object *);
-int nouveau_object_dec(struct nouveau_object *, bool suspend);
-
-void nouveau_object_debug(void);
-
-static inline int
-nv_exec(void *obj, u32 mthd, void *data, u32 size)
-{
-	struct nouveau_omthds *method = nv_oclass(obj)->omthds;
-
-	while (method && method->call) {
-		if (mthd >= method->start && mthd <= method->limit)
-			return method->call(obj, mthd, data, size);
-		method++;
-	}
-
-	return -EINVAL;
-}
-
-static inline int
-nv_call(void *obj, u32 mthd, u32 data)
-{
-	return nv_exec(obj, mthd, &data, sizeof(data));
-}
-
-static inline u8
-nv_ro08(void *obj, u64 addr)
-{
-	u8 data = nv_ofuncs(obj)->rd08(obj, addr);
-	nv_spam(obj, "nv_ro08 0x%08llx 0x%02x\n", addr, data);
-	return data;
-}
-
-static inline u16
-nv_ro16(void *obj, u64 addr)
-{
-	u16 data = nv_ofuncs(obj)->rd16(obj, addr);
-	nv_spam(obj, "nv_ro16 0x%08llx 0x%04x\n", addr, data);
-	return data;
-}
-
-static inline u32
-nv_ro32(void *obj, u64 addr)
-{
-	u32 data = nv_ofuncs(obj)->rd32(obj, addr);
-	nv_spam(obj, "nv_ro32 0x%08llx 0x%08x\n", addr, data);
-	return data;
-}
-
-static inline void
-nv_wo08(void *obj, u64 addr, u8 data)
-{
-	nv_spam(obj, "nv_wo08 0x%08llx 0x%02x\n", addr, data);
-	nv_ofuncs(obj)->wr08(obj, addr, data);
-}
-
-static inline void
-nv_wo16(void *obj, u64 addr, u16 data)
-{
-	nv_spam(obj, "nv_wo16 0x%08llx 0x%04x\n", addr, data);
-	nv_ofuncs(obj)->wr16(obj, addr, data);
-}
-
-static inline void
-nv_wo32(void *obj, u64 addr, u32 data)
-{
-	nv_spam(obj, "nv_wo32 0x%08llx 0x%08x\n", addr, data);
-	nv_ofuncs(obj)->wr32(obj, addr, data);
-}
-
-static inline u32
-nv_mo32(void *obj, u64 addr, u32 mask, u32 data)
-{
-	u32 temp = nv_ro32(obj, addr);
-	nv_wo32(obj, addr, (temp & ~mask) | data);
-	return temp;
-}
-
-static inline int
-nv_memcmp(void *obj, u32 addr, const char *str, u32 len)
-{
-	unsigned char c1, c2;
-
-	while (len--) {
-		c1 = nv_ro08(obj, addr++);
-		c2 = *(str++);
-		if (c1 != c2)
-			return c1 - c2;
-	}
-	return 0;
-}
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/option.h b/drivers/gpu/drm/nouveau/core/include/core/option.h
deleted file mode 100644
index ed055847887e..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/option.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __NOUVEAU_OPTION_H__
-#define __NOUVEAU_OPTION_H__
-
-#include <core/os.h>
-
-const char *nouveau_stropt(const char *optstr, const char *opt, int *len);
-bool nouveau_boolopt(const char *optstr, const char *opt, bool value);
-
-int nouveau_dbgopt(const char *optstr, const char *sub);
-
-/* compares unterminated string 'str' with zero-terminated string 'cmp' */
-static inline int
-strncasecmpz(const char *str, const char *cmp, size_t len)
-{
-	if (strlen(cmp) != len)
-		return len;
-	return strncasecmp(str, cmp, len);
-}
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/parent.h b/drivers/gpu/drm/nouveau/core/include/core/parent.h
deleted file mode 100644
index 12da418ec70a..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/parent.h
+++ /dev/null
@@ -1,62 +0,0 @@
-#ifndef __NOUVEAU_PARENT_H__
-#define __NOUVEAU_PARENT_H__
-
-#include <core/device.h>
-#include <core/object.h>
-
-struct nouveau_sclass {
-	struct nouveau_sclass *sclass;
-	struct nouveau_engine *engine;
-	struct nouveau_oclass *oclass;
-};
-
-struct nouveau_parent {
-	struct nouveau_object base;
-
-	struct nouveau_sclass *sclass;
-	u64 engine;
-
-	int  (*context_attach)(struct nouveau_object *,
-			       struct nouveau_object *);
-	int  (*context_detach)(struct nouveau_object *, bool suspend,
-			       struct nouveau_object *);
-
-	int  (*object_attach)(struct nouveau_object *parent,
-			      struct nouveau_object *object, u32 name);
-	void (*object_detach)(struct nouveau_object *parent, int cookie);
-};
-
-static inline struct nouveau_parent *
-nv_parent(void *obj)
-{
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
-	if (unlikely(!(nv_iclass(obj, NV_PARENT_CLASS))))
-		nv_assert("BAD CAST -> NvParent, %08x", nv_hclass(obj));
-#endif
-	return obj;
-}
-
-#define nouveau_parent_create(p,e,c,v,s,m,d)                                   \
-	nouveau_parent_create_((p), (e), (c), (v), (s), (m),                   \
-			       sizeof(**d), (void **)d)
-#define nouveau_parent_init(p)                                                 \
-	nouveau_object_init(&(p)->base)
-#define nouveau_parent_fini(p,s)                                               \
-	nouveau_object_fini(&(p)->base, (s))
-
-int  nouveau_parent_create_(struct nouveau_object *, struct nouveau_object *,
-			    struct nouveau_oclass *, u32 pclass,
-			    struct nouveau_oclass *, u64 engcls,
-			    int size, void **);
-void nouveau_parent_destroy(struct nouveau_parent *);
-
-void _nouveau_parent_dtor(struct nouveau_object *);
-#define _nouveau_parent_init nouveau_object_init
-#define _nouveau_parent_fini nouveau_object_fini
-
-int nouveau_parent_sclass(struct nouveau_object *, u16 handle,
-			  struct nouveau_object **pengine,
-			  struct nouveau_oclass **poclass);
-int nouveau_parent_lclass(struct nouveau_object *, u32 *, int);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/printk.h b/drivers/gpu/drm/nouveau/core/include/core/printk.h
deleted file mode 100644
index 451b6ed20b7e..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/printk.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef __NOUVEAU_PRINTK_H__
-#define __NOUVEAU_PRINTK_H__
-
-#include <core/os.h>
-#include <core/debug.h>
-
-struct nouveau_object;
-
-void __printf(3, 4)
-nv_printk_(struct nouveau_object *, int, const char *, ...);
-
-#define nv_printk(o,l,f,a...) do {                                             \
-	if (NV_DBG_##l <= CONFIG_NOUVEAU_DEBUG)                                \
-		nv_printk_(nv_object(o), NV_DBG_##l, f, ##a);                  \
-} while(0)
-
-#define nv_fatal(o,f,a...) nv_printk((o), FATAL, f, ##a)
-#define nv_error(o,f,a...) nv_printk((o), ERROR, f, ##a)
-#define nv_warn(o,f,a...) nv_printk((o), WARN, f, ##a)
-#define nv_info(o,f,a...) nv_printk((o), INFO, f, ##a)
-#define nv_debug(o,f,a...) nv_printk((o), DEBUG, f, ##a)
-#define nv_trace(o,f,a...) nv_printk((o), TRACE, f, ##a)
-#define nv_spam(o,f,a...) nv_printk((o), SPAM, f, ##a)
-#define nv_ioctl(o,f,a...) nv_trace(nouveau_client(o), "ioctl: "f, ##a)
-
-#define nv_assert(f,a...) do {                                                 \
-	if (NV_DBG_FATAL <= CONFIG_NOUVEAU_DEBUG)                              \
-		nv_printk_(NULL, NV_DBG_FATAL, f "\n", ##a);                   \
-	BUG_ON(1);                                                             \
-} while(0)
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/ramht.h b/drivers/gpu/drm/nouveau/core/include/core/ramht.h
deleted file mode 100644
index 47e4cacbca37..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/ramht.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef __NOUVEAU_RAMHT_H__
-#define __NOUVEAU_RAMHT_H__
-
-#include <core/gpuobj.h>
-
-struct nouveau_ramht {
-	struct nouveau_gpuobj base;
-	int bits;
-};
-
-int  nouveau_ramht_insert(struct nouveau_ramht *, int chid,
-			  u32 handle, u32 context);
-void nouveau_ramht_remove(struct nouveau_ramht *, int cookie);
-int  nouveau_ramht_new(struct nouveau_object *, struct nouveau_object *,
-		       u32 size, u32 align, struct nouveau_ramht **);
-
-static inline void
-nouveau_ramht_ref(struct nouveau_ramht *obj, struct nouveau_ramht **ref)
-{
-	nouveau_gpuobj_ref(&obj->base, (struct nouveau_gpuobj **)ref);
-}
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/subdev.h b/drivers/gpu/drm/nouveau/core/include/core/subdev.h
deleted file mode 100644
index e9632e931616..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/subdev.h
+++ /dev/null
@@ -1,118 +0,0 @@
-#ifndef __NOUVEAU_SUBDEV_H__
-#define __NOUVEAU_SUBDEV_H__
-
-#include <core/object.h>
-
-#define NV_SUBDEV_(sub,var) (NV_SUBDEV_CLASS | ((var) << 8) | (sub))
-#define NV_SUBDEV(name,var)  NV_SUBDEV_(NVDEV_SUBDEV_##name, (var))
-
-struct nouveau_subdev {
-	struct nouveau_object base;
-	struct mutex mutex;
-	const char *name;
-	void __iomem *mmio;
-	u32 debug;
-	u32 unit;
-
-	void (*intr)(struct nouveau_subdev *);
-};
-
-static inline struct nouveau_subdev *
-nv_subdev(void *obj)
-{
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
-	if (unlikely(!nv_iclass(obj, NV_SUBDEV_CLASS)))
-		nv_assert("BAD CAST -> NvSubDev, %08x", nv_hclass(obj));
-#endif
-	return obj;
-}
-
-static inline int
-nv_subidx(struct nouveau_object *object)
-{
-	return nv_hclass(nv_subdev(object)) & 0xff;
-}
-
-#define nouveau_subdev_create(p,e,o,v,s,f,d)                                   \
-	nouveau_subdev_create_((p), (e), (o), (v), (s), (f),                   \
-			       sizeof(**d),(void **)d)
-
-int  nouveau_subdev_create_(struct nouveau_object *, struct nouveau_object *,
-			    struct nouveau_oclass *, u32 pclass,
-			    const char *sname, const char *fname,
-			    int size, void **);
-void nouveau_subdev_destroy(struct nouveau_subdev *);
-int  nouveau_subdev_init(struct nouveau_subdev *);
-int  nouveau_subdev_fini(struct nouveau_subdev *, bool suspend);
-void nouveau_subdev_reset(struct nouveau_object *);
-
-void _nouveau_subdev_dtor(struct nouveau_object *);
-int  _nouveau_subdev_init(struct nouveau_object *);
-int  _nouveau_subdev_fini(struct nouveau_object *, bool suspend);
-
-#define s_printk(s,l,f,a...) do {                                              \
-	if ((s)->debug >= OS_DBG_##l) {                                        \
-		nv_printk((s)->base.parent, (s)->name, l, f, ##a);             \
-	}                                                                      \
-} while(0)
-
-static inline u8
-nv_rd08(void *obj, u32 addr)
-{
-	struct nouveau_subdev *subdev = nv_subdev(obj);
-	u8 data = ioread8(subdev->mmio + addr);
-	nv_spam(subdev, "nv_rd08 0x%06x 0x%02x\n", addr, data);
-	return data;
-}
-
-static inline u16
-nv_rd16(void *obj, u32 addr)
-{
-	struct nouveau_subdev *subdev = nv_subdev(obj);
-	u16 data = ioread16_native(subdev->mmio + addr);
-	nv_spam(subdev, "nv_rd16 0x%06x 0x%04x\n", addr, data);
-	return data;
-}
-
-static inline u32
-nv_rd32(void *obj, u32 addr)
-{
-	struct nouveau_subdev *subdev = nv_subdev(obj);
-	u32 data = ioread32_native(subdev->mmio + addr);
-	nv_spam(subdev, "nv_rd32 0x%06x 0x%08x\n", addr, data);
-	return data;
-}
-
-static inline void
-nv_wr08(void *obj, u32 addr, u8 data)
-{
-	struct nouveau_subdev *subdev = nv_subdev(obj);
-	nv_spam(subdev, "nv_wr08 0x%06x 0x%02x\n", addr, data);
-	iowrite8(data, subdev->mmio + addr);
-}
-
-static inline void
-nv_wr16(void *obj, u32 addr, u16 data)
-{
-	struct nouveau_subdev *subdev = nv_subdev(obj);
-	nv_spam(subdev, "nv_wr16 0x%06x 0x%04x\n", addr, data);
-	iowrite16_native(data, subdev->mmio + addr);
-}
-
-static inline void
-nv_wr32(void *obj, u32 addr, u32 data)
-{
-	struct nouveau_subdev *subdev = nv_subdev(obj);
-	nv_spam(subdev, "nv_wr32 0x%06x 0x%08x\n", addr, data);
-	iowrite32_native(data, subdev->mmio + addr);
-}
-
-static inline u32
-nv_mask(void *obj, u32 addr, u32 mask, u32 data)
-{
-	u32 temp = nv_rd32(obj, addr);
-	nv_wr32(obj, addr, (temp & ~mask) | data);
-	return temp;
-}
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/bsp.h b/drivers/gpu/drm/nouveau/core/include/engine/bsp.h
deleted file mode 100644
index 67662e2c4547..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/engine/bsp.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __NOUVEAU_BSP_H__
-#define __NOUVEAU_BSP_H__
-
-extern struct nouveau_oclass nv84_bsp_oclass;
-extern struct nouveau_oclass nv98_bsp_oclass;
-extern struct nouveau_oclass nvc0_bsp_oclass;
-extern struct nouveau_oclass nve0_bsp_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/copy.h b/drivers/gpu/drm/nouveau/core/include/engine/copy.h
deleted file mode 100644
index 316a28ae5f5c..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/engine/copy.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __NOUVEAU_COPY_H__
-#define __NOUVEAU_COPY_H__
-
-void nva3_copy_intr(struct nouveau_subdev *);
-
-extern struct nouveau_oclass nva3_copy_oclass;
-extern struct nouveau_oclass nvc0_copy0_oclass;
-extern struct nouveau_oclass nvc0_copy1_oclass;
-extern struct nouveau_oclass nve0_copy0_oclass;
-extern struct nouveau_oclass nve0_copy1_oclass;
-extern struct nouveau_oclass nve0_copy2_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/crypt.h b/drivers/gpu/drm/nouveau/core/include/engine/crypt.h
deleted file mode 100644
index db975618e937..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/engine/crypt.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __NOUVEAU_CRYPT_H__
-#define __NOUVEAU_CRYPT_H__
-
-extern struct nouveau_oclass nv84_crypt_oclass;
-extern struct nouveau_oclass nv98_crypt_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/device.h b/drivers/gpu/drm/nouveau/core/include/engine/device.h
deleted file mode 100644
index 672d3c8f4145..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/engine/device.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef __NOUVEAU_SUBDEV_DEVICE_H__
-#define __NOUVEAU_SUBDEV_DEVICE_H__
-
-#include <core/device.h>
-
-struct platform_device;
-
-enum nv_bus_type {
-	NOUVEAU_BUS_PCI,
-	NOUVEAU_BUS_PLATFORM,
-};
-
-#define nouveau_device_create(p,t,n,s,c,d,u)                                   \
-	nouveau_device_create_((void *)(p), (t), (n), (s), (c), (d),           \
-			       sizeof(**u), (void **)u)
-
-int  nouveau_device_create_(void *, enum nv_bus_type type, u64 name,
-			    const char *sname, const char *cfg, const char *dbg,
-			    int, void **);
-
-int nv04_identify(struct nouveau_device *);
-int nv10_identify(struct nouveau_device *);
-int nv20_identify(struct nouveau_device *);
-int nv30_identify(struct nouveau_device *);
-int nv40_identify(struct nouveau_device *);
-int nv50_identify(struct nouveau_device *);
-int nvc0_identify(struct nouveau_device *);
-int nve0_identify(struct nouveau_device *);
-int gm100_identify(struct nouveau_device *);
-
-struct nouveau_device *nouveau_device_find(u64 name);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/disp.h b/drivers/gpu/drm/nouveau/core/include/engine/disp.h
deleted file mode 100644
index fc307f1317ff..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/engine/disp.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef __NOUVEAU_DISP_H__
-#define __NOUVEAU_DISP_H__
-
-#include <core/object.h>
-#include <core/engine.h>
-#include <core/device.h>
-#include <core/event.h>
-
-struct nouveau_disp {
-	struct nouveau_engine base;
-
-	struct list_head outp;
-
-	struct nvkm_event hpd;
-	struct nvkm_event vblank;
-};
-
-static inline struct nouveau_disp *
-nouveau_disp(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_DISP];
-}
-
-extern struct nouveau_oclass *nv04_disp_oclass;
-extern struct nouveau_oclass *nv50_disp_oclass;
-extern struct nouveau_oclass *nv84_disp_oclass;
-extern struct nouveau_oclass *nva0_disp_oclass;
-extern struct nouveau_oclass *nv94_disp_oclass;
-extern struct nouveau_oclass *nva3_disp_oclass;
-extern struct nouveau_oclass *nvd0_disp_oclass;
-extern struct nouveau_oclass *nve0_disp_oclass;
-extern struct nouveau_oclass *nvf0_disp_oclass;
-extern struct nouveau_oclass *gm107_disp_oclass;
-extern struct nouveau_oclass *gm204_disp_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/dmaobj.h b/drivers/gpu/drm/nouveau/core/include/engine/dmaobj.h
deleted file mode 100644
index 1b283a7b78e6..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/engine/dmaobj.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef __NOUVEAU_DMAOBJ_H__
-#define __NOUVEAU_DMAOBJ_H__
-
-#include <core/object.h>
-#include <core/engine.h>
-
-struct nouveau_gpuobj;
-
-struct nouveau_dmaobj {
-	struct nouveau_object base;
-	u32 target;
-	u32 access;
-	u64 start;
-	u64 limit;
-};
-
-struct nouveau_dmaeng {
-	struct nouveau_engine base;
-
-	/* creates a "physical" dma object from a struct nouveau_dmaobj */
-	int (*bind)(struct nouveau_dmaobj *dmaobj,
-		    struct nouveau_object *parent,
-		    struct nouveau_gpuobj **);
-};
-
-extern struct nouveau_oclass *nv04_dmaeng_oclass;
-extern struct nouveau_oclass *nv50_dmaeng_oclass;
-extern struct nouveau_oclass *nvc0_dmaeng_oclass;
-extern struct nouveau_oclass *nvd0_dmaeng_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/falcon.h b/drivers/gpu/drm/nouveau/core/include/engine/falcon.h
deleted file mode 100644
index 181aa7da524d..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/engine/falcon.h
+++ /dev/null
@@ -1,83 +0,0 @@
-#ifndef __NOUVEAU_FALCON_H__
-#define __NOUVEAU_FALCON_H__
-
-#include <core/engine.h>
-#include <core/engctx.h>
-#include <core/gpuobj.h>
-
-struct nouveau_falcon_chan {
-	struct nouveau_engctx base;
-};
-
-#define nouveau_falcon_context_create(p,e,c,g,s,a,f,d)                         \
-	nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
-#define nouveau_falcon_context_destroy(d)                                      \
-	nouveau_engctx_destroy(&(d)->base)
-#define nouveau_falcon_context_init(d)                                         \
-	nouveau_engctx_init(&(d)->base)
-#define nouveau_falcon_context_fini(d,s)                                       \
-	nouveau_engctx_fini(&(d)->base, (s))
-
-#define _nouveau_falcon_context_ctor _nouveau_engctx_ctor
-#define _nouveau_falcon_context_dtor _nouveau_engctx_dtor
-#define _nouveau_falcon_context_init _nouveau_engctx_init
-#define _nouveau_falcon_context_fini _nouveau_engctx_fini
-#define _nouveau_falcon_context_rd32 _nouveau_engctx_rd32
-#define _nouveau_falcon_context_wr32 _nouveau_engctx_wr32
-
-struct nouveau_falcon_data {
-	bool external;
-};
-
-struct nouveau_falcon {
-	struct nouveau_engine base;
-
-	u32 addr;
-	u8  version;
-	u8  secret;
-
-	struct nouveau_gpuobj *core;
-	bool external;
-
-	struct {
-		u32 limit;
-		u32 *data;
-		u32  size;
-	} code;
-
-	struct {
-		u32 limit;
-		u32 *data;
-		u32  size;
-	} data;
-};
-
-#define nv_falcon(priv) (&(priv)->base)
-
-#define nouveau_falcon_create(p,e,c,b,d,i,f,r)                                 \
-	nouveau_falcon_create_((p), (e), (c), (b), (d), (i), (f),              \
-			       sizeof(**r),(void **)r)
-#define nouveau_falcon_destroy(p)                                              \
-	nouveau_engine_destroy(&(p)->base)
-#define nouveau_falcon_init(p) ({                                              \
-	struct nouveau_falcon *falcon = (p);                                   \
-	_nouveau_falcon_init(nv_object(falcon));                               \
-})
-#define nouveau_falcon_fini(p,s) ({                                            \
-	struct nouveau_falcon *falcon = (p);                                   \
-	_nouveau_falcon_fini(nv_object(falcon), (s));                          \
-})
-
-int nouveau_falcon_create_(struct nouveau_object *, struct nouveau_object *,
-			   struct nouveau_oclass *, u32, bool, const char *,
-			   const char *, int, void **);
-
-void nouveau_falcon_intr(struct nouveau_subdev *subdev);
-
-#define _nouveau_falcon_dtor _nouveau_engine_dtor
-int  _nouveau_falcon_init(struct nouveau_object *);
-int  _nouveau_falcon_fini(struct nouveau_object *, bool);
-u32  _nouveau_falcon_rd32(struct nouveau_object *, u64);
-void _nouveau_falcon_wr32(struct nouveau_object *, u64, u32);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
deleted file mode 100644
index 2007453f6fce..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
+++ /dev/null
@@ -1,126 +0,0 @@
-#ifndef __NOUVEAU_FIFO_H__
-#define __NOUVEAU_FIFO_H__
-
-#include <core/namedb.h>
-#include <core/gpuobj.h>
-#include <core/engine.h>
-#include <core/event.h>
-
-struct nouveau_fifo_chan {
-	struct nouveau_namedb base;
-	struct nouveau_dmaobj *pushdma;
-	struct nouveau_gpuobj *pushgpu;
-	void __iomem *user;
-	u64 addr;
-	u32 size;
-	u16 chid;
-	atomic_t refcnt; /* NV04_NVSW_SET_REF */
-};
-
-static inline struct nouveau_fifo_chan *
-nouveau_fifo_chan(void *obj)
-{
-	return (void *)nv_namedb(obj);
-}
-
-#define nouveau_fifo_channel_create(p,e,c,b,a,s,n,m,d)                         \
-	nouveau_fifo_channel_create_((p), (e), (c), (b), (a), (s), (n),        \
-				     (m), sizeof(**d), (void **)d)
-#define nouveau_fifo_channel_init(p)                                           \
-	nouveau_namedb_init(&(p)->base)
-#define nouveau_fifo_channel_fini(p,s)                                         \
-	nouveau_namedb_fini(&(p)->base, (s))
-
-int  nouveau_fifo_channel_create_(struct nouveau_object *,
-				  struct nouveau_object *,
-				  struct nouveau_oclass *,
-				  int bar, u32 addr, u32 size, u32 push,
-				  u64 engmask, int len, void **);
-void nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *);
-
-#define _nouveau_fifo_channel_init _nouveau_namedb_init
-#define _nouveau_fifo_channel_fini _nouveau_namedb_fini
-
-void _nouveau_fifo_channel_dtor(struct nouveau_object *);
-int  _nouveau_fifo_channel_map(struct nouveau_object *, u64 *, u32 *);
-u32  _nouveau_fifo_channel_rd32(struct nouveau_object *, u64);
-void _nouveau_fifo_channel_wr32(struct nouveau_object *, u64, u32);
-int  _nouveau_fifo_channel_ntfy(struct nouveau_object *, u32, struct nvkm_event **);
-
-struct nouveau_fifo_base {
-	struct nouveau_gpuobj base;
-};
-
-#define nouveau_fifo_context_create(p,e,c,g,s,a,f,d)                           \
-	nouveau_gpuobj_create((p), (e), (c), 0, (g), (s), (a), (f), (d))
-#define nouveau_fifo_context_destroy(p)                                        \
-	nouveau_gpuobj_destroy(&(p)->base)
-#define nouveau_fifo_context_init(p)                                           \
-	nouveau_gpuobj_init(&(p)->base)
-#define nouveau_fifo_context_fini(p,s)                                         \
-	nouveau_gpuobj_fini(&(p)->base, (s))
-
-#define _nouveau_fifo_context_dtor _nouveau_gpuobj_dtor
-#define _nouveau_fifo_context_init _nouveau_gpuobj_init
-#define _nouveau_fifo_context_fini _nouveau_gpuobj_fini
-#define _nouveau_fifo_context_rd32 _nouveau_gpuobj_rd32
-#define _nouveau_fifo_context_wr32 _nouveau_gpuobj_wr32
-
-struct nouveau_fifo {
-	struct nouveau_engine base;
-
-	struct nvkm_event cevent; /* channel creation event */
-	struct nvkm_event uevent; /* async user trigger */
-
-	struct nouveau_object **channel;
-	spinlock_t lock;
-	u16 min;
-	u16 max;
-
-	int  (*chid)(struct nouveau_fifo *, struct nouveau_object *);
-	void (*pause)(struct nouveau_fifo *, unsigned long *);
-	void (*start)(struct nouveau_fifo *, unsigned long *);
-};
-
-static inline struct nouveau_fifo *
-nouveau_fifo(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_FIFO];
-}
-
-#define nouveau_fifo_create(o,e,c,fc,lc,d)                                     \
-	nouveau_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d)
-#define nouveau_fifo_init(p)                                                   \
-	nouveau_engine_init(&(p)->base)
-#define nouveau_fifo_fini(p,s)                                                 \
-	nouveau_engine_fini(&(p)->base, (s))
-
-int nouveau_fifo_create_(struct nouveau_object *, struct nouveau_object *,
-			 struct nouveau_oclass *, int min, int max,
-			 int size, void **);
-void nouveau_fifo_destroy(struct nouveau_fifo *);
-const char *
-nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid);
-
-#define _nouveau_fifo_init _nouveau_engine_init
-#define _nouveau_fifo_fini _nouveau_engine_fini
-
-extern struct nouveau_oclass *nv04_fifo_oclass;
-extern struct nouveau_oclass *nv10_fifo_oclass;
-extern struct nouveau_oclass *nv17_fifo_oclass;
-extern struct nouveau_oclass *nv40_fifo_oclass;
-extern struct nouveau_oclass *nv50_fifo_oclass;
-extern struct nouveau_oclass *nv84_fifo_oclass;
-extern struct nouveau_oclass *nvc0_fifo_oclass;
-extern struct nouveau_oclass *nve0_fifo_oclass;
-extern struct nouveau_oclass *gk20a_fifo_oclass;
-extern struct nouveau_oclass *nv108_fifo_oclass;
-
-int  nouveau_fifo_uevent_ctor(struct nouveau_object *, void *, u32,
-			      struct nvkm_notify *);
-void nouveau_fifo_uevent(struct nouveau_fifo *);
-
-void nv04_fifo_intr(struct nouveau_subdev *);
-int  nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/graph.h b/drivers/gpu/drm/nouveau/core/include/engine/graph.h
deleted file mode 100644
index d5055570d01b..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/engine/graph.h
+++ /dev/null
@@ -1,86 +0,0 @@
-#ifndef __NOUVEAU_GRAPH_H__
-#define __NOUVEAU_GRAPH_H__
-
-#include <core/engine.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-struct nouveau_graph_chan {
-	struct nouveau_engctx base;
-};
-
-#define nouveau_graph_context_create(p,e,c,g,s,a,f,d)                          \
-	nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
-#define nouveau_graph_context_destroy(d)                                       \
-	nouveau_engctx_destroy(&(d)->base)
-#define nouveau_graph_context_init(d)                                          \
-	nouveau_engctx_init(&(d)->base)
-#define nouveau_graph_context_fini(d,s)                                        \
-	nouveau_engctx_fini(&(d)->base, (s))
-
-#define _nouveau_graph_context_dtor _nouveau_engctx_dtor
-#define _nouveau_graph_context_init _nouveau_engctx_init
-#define _nouveau_graph_context_fini _nouveau_engctx_fini
-#define _nouveau_graph_context_rd32 _nouveau_engctx_rd32
-#define _nouveau_graph_context_wr32 _nouveau_engctx_wr32
-
-struct nouveau_graph {
-	struct nouveau_engine base;
-
-	/* Returns chipset-specific counts of units packed into an u64.
-	 */
-	u64 (*units)(struct nouveau_graph *);
-};
-
-static inline struct nouveau_graph *
-nouveau_graph(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_GR];
-}
-
-#define nouveau_graph_create(p,e,c,y,d)                                        \
-	nouveau_engine_create((p), (e), (c), (y), "PGRAPH", "graphics", (d))
-#define nouveau_graph_destroy(d)                                               \
-	nouveau_engine_destroy(&(d)->base)
-#define nouveau_graph_init(d)                                                  \
-	nouveau_engine_init(&(d)->base)
-#define nouveau_graph_fini(d,s)                                                \
-	nouveau_engine_fini(&(d)->base, (s))
-
-#define _nouveau_graph_dtor _nouveau_engine_dtor
-#define _nouveau_graph_init _nouveau_engine_init
-#define _nouveau_graph_fini _nouveau_engine_fini
-
-extern struct nouveau_oclass nv04_graph_oclass;
-extern struct nouveau_oclass nv10_graph_oclass;
-extern struct nouveau_oclass nv20_graph_oclass;
-extern struct nouveau_oclass nv25_graph_oclass;
-extern struct nouveau_oclass nv2a_graph_oclass;
-extern struct nouveau_oclass nv30_graph_oclass;
-extern struct nouveau_oclass nv34_graph_oclass;
-extern struct nouveau_oclass nv35_graph_oclass;
-extern struct nouveau_oclass nv40_graph_oclass;
-extern struct nouveau_oclass nv50_graph_oclass;
-extern struct nouveau_oclass *nvc0_graph_oclass;
-extern struct nouveau_oclass *nvc1_graph_oclass;
-extern struct nouveau_oclass *nvc4_graph_oclass;
-extern struct nouveau_oclass *nvc8_graph_oclass;
-extern struct nouveau_oclass *nvd7_graph_oclass;
-extern struct nouveau_oclass *nvd9_graph_oclass;
-extern struct nouveau_oclass *nve4_graph_oclass;
-extern struct nouveau_oclass *gk20a_graph_oclass;
-extern struct nouveau_oclass *nvf0_graph_oclass;
-extern struct nouveau_oclass *gk110b_graph_oclass;
-extern struct nouveau_oclass *nv108_graph_oclass;
-extern struct nouveau_oclass *gm107_graph_oclass;
-
-extern const struct nouveau_bitfield nv04_graph_nsource[];
-extern struct nouveau_ofuncs nv04_graph_ofuncs;
-bool nv04_graph_idle(void *obj);
-
-extern const struct nouveau_bitfield nv10_graph_intr_name[];
-extern const struct nouveau_bitfield nv10_graph_nstatus[];
-
-extern const struct nouveau_enum nv50_data_error_names[];
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/mpeg.h b/drivers/gpu/drm/nouveau/core/include/engine/mpeg.h
deleted file mode 100644
index 9b0d938199f6..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/engine/mpeg.h
+++ /dev/null
@@ -1,63 +0,0 @@
-#ifndef __NOUVEAU_MPEG_H__
-#define __NOUVEAU_MPEG_H__
-
-#include <core/engine.h>
-#include <core/engctx.h>
-
-struct nouveau_mpeg_chan {
-	struct nouveau_engctx base;
-};
-
-#define nouveau_mpeg_context_create(p,e,c,g,s,a,f,d)                           \
-	nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
-#define nouveau_mpeg_context_destroy(d)                                        \
-	nouveau_engctx_destroy(&(d)->base)
-#define nouveau_mpeg_context_init(d)                                           \
-	nouveau_engctx_init(&(d)->base)
-#define nouveau_mpeg_context_fini(d,s)                                         \
-	nouveau_engctx_fini(&(d)->base, (s))
-
-#define _nouveau_mpeg_context_dtor _nouveau_engctx_dtor
-#define _nouveau_mpeg_context_init _nouveau_engctx_init
-#define _nouveau_mpeg_context_fini _nouveau_engctx_fini
-#define _nouveau_mpeg_context_rd32 _nouveau_engctx_rd32
-#define _nouveau_mpeg_context_wr32 _nouveau_engctx_wr32
-
-struct nouveau_mpeg {
-	struct nouveau_engine base;
-};
-
-#define nouveau_mpeg_create(p,e,c,d)                                           \
-	nouveau_engine_create((p), (e), (c), true, "PMPEG", "mpeg", (d))
-#define nouveau_mpeg_destroy(d)                                                \
-	nouveau_engine_destroy(&(d)->base)
-#define nouveau_mpeg_init(d)                                                   \
-	nouveau_engine_init(&(d)->base)
-#define nouveau_mpeg_fini(d,s)                                                 \
-	nouveau_engine_fini(&(d)->base, (s))
-
-#define _nouveau_mpeg_dtor _nouveau_engine_dtor
-#define _nouveau_mpeg_init _nouveau_engine_init
-#define _nouveau_mpeg_fini _nouveau_engine_fini
-
-extern struct nouveau_oclass nv31_mpeg_oclass;
-extern struct nouveau_oclass nv40_mpeg_oclass;
-extern struct nouveau_oclass nv44_mpeg_oclass;
-extern struct nouveau_oclass nv50_mpeg_oclass;
-extern struct nouveau_oclass nv84_mpeg_oclass;
-extern struct nouveau_ofuncs nv31_mpeg_ofuncs;
-extern struct nouveau_oclass nv31_mpeg_cclass;
-extern struct nouveau_oclass nv31_mpeg_sclass[];
-extern struct nouveau_oclass nv40_mpeg_sclass[];
-void nv31_mpeg_intr(struct nouveau_subdev *);
-void nv31_mpeg_tile_prog(struct nouveau_engine *, int);
-int  nv31_mpeg_init(struct nouveau_object *);
-
-extern struct nouveau_ofuncs nv50_mpeg_ofuncs;
-int  nv50_mpeg_context_ctor(struct nouveau_object *, struct nouveau_object *,
-			    struct nouveau_oclass *, void *, u32,
-			    struct nouveau_object **);
-void nv50_mpeg_intr(struct nouveau_subdev *);
-int  nv50_mpeg_init(struct nouveau_object *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h b/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h
deleted file mode 100644
index 88cc812baaa3..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef __NVKM_PERFMON_H__
-#define __NVKM_PERFMON_H__
-
-#include <core/device.h>
-#include <core/engine.h>
-#include <core/engctx.h>
-
-struct nouveau_perfdom;
-struct nouveau_perfctr;
-struct nouveau_perfmon {
-	struct nouveau_engine base;
-
-	struct nouveau_perfctx *context;
-	void *profile_data;
-
-	struct list_head domains;
-	u32 sequence;
-
-	/*XXX: temp for daemon backend */
-	u32 pwr[8];
-	u32 last;
-};
-
-static inline struct nouveau_perfmon *
-nouveau_perfmon(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_PERFMON];
-}
-
-extern struct nouveau_oclass *nv40_perfmon_oclass;
-extern struct nouveau_oclass *nv50_perfmon_oclass;
-extern struct nouveau_oclass *nv84_perfmon_oclass;
-extern struct nouveau_oclass *nva3_perfmon_oclass;
-extern struct nouveau_oclass nvc0_perfmon_oclass;
-extern struct nouveau_oclass nve0_perfmon_oclass;
-extern struct nouveau_oclass nvf0_perfmon_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/ppp.h b/drivers/gpu/drm/nouveau/core/include/engine/ppp.h
deleted file mode 100644
index 0a66781e8cf1..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/engine/ppp.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __NOUVEAU_PPP_H__
-#define __NOUVEAU_PPP_H__
-
-extern struct nouveau_oclass nv98_ppp_oclass;
-extern struct nouveau_oclass nvc0_ppp_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/software.h b/drivers/gpu/drm/nouveau/core/include/engine/software.h
deleted file mode 100644
index 23a462b50d03..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/engine/software.h
+++ /dev/null
@@ -1,51 +0,0 @@
-#ifndef __NOUVEAU_SOFTWARE_H__
-#define __NOUVEAU_SOFTWARE_H__
-
-#include <core/engine.h>
-#include <core/engctx.h>
-
-struct nouveau_software_chan {
-	struct nouveau_engctx base;
-
-	int (*flip)(void *);
-	void *flip_data;
-};
-
-#define nouveau_software_context_create(p,e,c,d)                               \
-	nouveau_engctx_create((p), (e), (c), (p), 0, 0, 0, (d))
-#define nouveau_software_context_destroy(d)                                    \
-	nouveau_engctx_destroy(&(d)->base)
-#define nouveau_software_context_init(d)                                       \
-	nouveau_engctx_init(&(d)->base)
-#define nouveau_software_context_fini(d,s)                                     \
-	nouveau_engctx_fini(&(d)->base, (s))
-
-#define _nouveau_software_context_dtor _nouveau_engctx_dtor
-#define _nouveau_software_context_init _nouveau_engctx_init
-#define _nouveau_software_context_fini _nouveau_engctx_fini
-
-struct nouveau_software {
-	struct nouveau_engine base;
-};
-
-#define nouveau_software_create(p,e,c,d)                                       \
-	nouveau_engine_create((p), (e), (c), true, "SW", "software", (d))
-#define nouveau_software_destroy(d)                                            \
-	nouveau_engine_destroy(&(d)->base)
-#define nouveau_software_init(d)                                               \
-	nouveau_engine_init(&(d)->base)
-#define nouveau_software_fini(d,s)                                             \
-	nouveau_engine_fini(&(d)->base, (s))
-
-#define _nouveau_software_dtor _nouveau_engine_dtor
-#define _nouveau_software_init _nouveau_engine_init
-#define _nouveau_software_fini _nouveau_engine_fini
-
-extern struct nouveau_oclass *nv04_software_oclass;
-extern struct nouveau_oclass *nv10_software_oclass;
-extern struct nouveau_oclass *nv50_software_oclass;
-extern struct nouveau_oclass *nvc0_software_oclass;
-
-void nv04_software_intr(struct nouveau_subdev *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/vp.h b/drivers/gpu/drm/nouveau/core/include/engine/vp.h
deleted file mode 100644
index 39baebec7fbb..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/engine/vp.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __NOUVEAU_VP_H__
-#define __NOUVEAU_VP_H__
-
-extern struct nouveau_oclass nv84_vp_oclass;
-extern struct nouveau_oclass nv98_vp_oclass;
-extern struct nouveau_oclass nvc0_vp_oclass;
-extern struct nouveau_oclass nve0_vp_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/xtensa.h b/drivers/gpu/drm/nouveau/core/include/engine/xtensa.h
deleted file mode 100644
index 306100f31f02..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/engine/xtensa.h
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef __NOUVEAU_XTENSA_H__
-#define __NOUVEAU_XTENSA_H__
-
-#include <core/engine.h>
-#include <core/engctx.h>
-#include <core/gpuobj.h>
-
-struct nouveau_xtensa {
-	struct nouveau_engine base;
-
-	u32 addr;
-	struct nouveau_gpuobj *gpu_fw;
-	u32 fifo_val;
-	u32 unkd28;
-};
-
-#define nouveau_xtensa_create(p,e,c,b,d,i,f,r)				\
-	nouveau_xtensa_create_((p), (e), (c), (b), (d), (i), (f),	\
-			       sizeof(**r),(void **)r)
-
-int _nouveau_xtensa_engctx_ctor(struct nouveau_object *,
-				struct nouveau_object *,
-				struct nouveau_oclass *, void *, u32,
-				struct nouveau_object **);
-
-void _nouveau_xtensa_intr(struct nouveau_subdev *);
-int nouveau_xtensa_create_(struct nouveau_object *,
-			   struct nouveau_object *,
-			   struct nouveau_oclass *, u32, bool,
-			   const char *, const char *,
-			   int, void **);
-#define _nouveau_xtensa_dtor _nouveau_engine_dtor
-int _nouveau_xtensa_init(struct nouveau_object *);
-int _nouveau_xtensa_fini(struct nouveau_object *, bool);
-u32  _nouveau_xtensa_rd32(struct nouveau_object *, u64);
-void _nouveau_xtensa_wr32(struct nouveau_object *, u64, u32);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/nvif/class.h b/drivers/gpu/drm/nouveau/core/include/nvif/class.h
deleted file mode 120000
index f1ac4859edd4..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/nvif/class.h
+++ /dev/null
@@ -1 +0,0 @@
-../../../nvif/class.h
\ No newline at end of file
diff --git a/drivers/gpu/drm/nouveau/core/include/nvif/event.h b/drivers/gpu/drm/nouveau/core/include/nvif/event.h
deleted file mode 120000
index 1b798538a725..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/nvif/event.h
+++ /dev/null
@@ -1 +0,0 @@
-../../../nvif/event.h
\ No newline at end of file
diff --git a/drivers/gpu/drm/nouveau/core/include/nvif/ioctl.h b/drivers/gpu/drm/nouveau/core/include/nvif/ioctl.h
deleted file mode 120000
index 8569c86907c5..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/nvif/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
-../../../nvif/ioctl.h
\ No newline at end of file
diff --git a/drivers/gpu/drm/nouveau/core/include/nvif/unpack.h b/drivers/gpu/drm/nouveau/core/include/nvif/unpack.h
deleted file mode 120000
index 69d99292bca4..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/nvif/unpack.h
+++ /dev/null
@@ -1 +0,0 @@
-../../../nvif/unpack.h
\ No newline at end of file
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bar.h b/drivers/gpu/drm/nouveau/core/include/subdev/bar.h
deleted file mode 100644
index 257ddf6d36d4..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bar.h
+++ /dev/null
@@ -1,37 +0,0 @@
-#ifndef __NOUVEAU_BAR_H__
-#define __NOUVEAU_BAR_H__
-
-#include <core/subdev.h>
-#include <core/device.h>
-
-struct nouveau_mem;
-struct nouveau_vma;
-
-struct nouveau_bar {
-	struct nouveau_subdev base;
-
-	int (*alloc)(struct nouveau_bar *, struct nouveau_object *,
-		     struct nouveau_mem *, struct nouveau_object **);
-
-	int (*kmap)(struct nouveau_bar *, struct nouveau_mem *,
-		    u32 flags, struct nouveau_vma *);
-	int (*umap)(struct nouveau_bar *, struct nouveau_mem *,
-		    u32 flags, struct nouveau_vma *);
-	void (*unmap)(struct nouveau_bar *, struct nouveau_vma *);
-	void (*flush)(struct nouveau_bar *);
-
-	/* whether the BAR supports to be ioremapped WC or should be uncached */
-	bool iomap_uncached;
-};
-
-static inline struct nouveau_bar *
-nouveau_bar(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_BAR];
-}
-
-extern struct nouveau_oclass nv50_bar_oclass;
-extern struct nouveau_oclass nvc0_bar_oclass;
-extern struct nouveau_oclass gk20a_bar_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios.h
deleted file mode 100644
index 5bd1ca8cd20d..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef __NOUVEAU_BIOS_H__
-#define __NOUVEAU_BIOS_H__
-
-#include <core/subdev.h>
-#include <core/device.h>
-
-struct nouveau_bios {
-	struct nouveau_subdev base;
-	u32 size;
-	u8 *data;
-
-	u32 bmp_offset;
-	u32 bit_offset;
-
-	struct {
-		u8 major;
-		u8 chip;
-		u8 minor;
-		u8 micro;
-		u8 patch;
-	} version;
-};
-
-static inline struct nouveau_bios *
-nouveau_bios(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_VBIOS];
-}
-
-u8  nvbios_checksum(const u8 *data, int size);
-u16 nvbios_findstr(const u8 *data, int size, const char *str, int len);
-
-extern struct nouveau_oclass nouveau_bios_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0203.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0203.h
deleted file mode 100644
index 1f84d3612dd8..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0203.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef __NVBIOS_M0203_H__
-#define __NVBIOS_M0203_H__
-
-struct nvbios_M0203T {
-#define M0203T_TYPE_RAMCFG 0x00
-	u8  type;
-	u16 pointer;
-};
-
-u32 nvbios_M0203Te(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u32 nvbios_M0203Tp(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		   struct nvbios_M0203T *);
-
-struct nvbios_M0203E {
-#define M0203E_TYPE_DDR2  0x0
-#define M0203E_TYPE_DDR3  0x1
-#define M0203E_TYPE_GDDR3 0x2
-#define M0203E_TYPE_GDDR5 0x3
-#define M0203E_TYPE_SKIP  0xf
-	u8 type;
-	u8 strap;
-	u8 group;
-};
-
-u32 nvbios_M0203Ee(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr);
-u32 nvbios_M0203Ep(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr,
-		   struct nvbios_M0203E *);
-u32 nvbios_M0203Em(struct nouveau_bios *, u8 ramcfg, u8 *ver, u8 *hdr,
-		   struct nvbios_M0203E *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0205.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0205.h
deleted file mode 100644
index e171120cec81..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0205.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef __NVBIOS_M0205_H__
-#define __NVBIOS_M0205_H__
-
-struct nvbios_M0205T {
-	u16 freq;
-};
-
-u32 nvbios_M0205Te(struct nouveau_bios *,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
-u32 nvbios_M0205Tp(struct nouveau_bios *,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz,
-		   struct nvbios_M0205T *);
-
-struct nvbios_M0205E {
-	u8 type;
-};
-
-u32 nvbios_M0205Ee(struct nouveau_bios *, int idx,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u32 nvbios_M0205Ep(struct nouveau_bios *, int idx,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		   struct nvbios_M0205E *);
-
-struct nvbios_M0205S {
-	u8 data;
-};
-
-u32 nvbios_M0205Se(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr);
-u32 nvbios_M0205Sp(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr,
-		   struct nvbios_M0205S *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0209.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0209.h
deleted file mode 100644
index 67dc50d837bc..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0209.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef __NVBIOS_M0209_H__
-#define __NVBIOS_M0209_H__
-
-u32 nvbios_M0209Te(struct nouveau_bios *,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
-
-struct nvbios_M0209E {
-	u8 v00_40;
-	u8 bits;
-	u8 modulo;
-	u8 v02_40;
-	u8 v02_07;
-	u8 v03;
-};
-
-u32 nvbios_M0209Ee(struct nouveau_bios *, int idx,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u32 nvbios_M0209Ep(struct nouveau_bios *, int idx,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		   struct nvbios_M0209E *);
-
-struct nvbios_M0209S {
-	u32 data[0x200];
-};
-
-u32 nvbios_M0209Se(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr);
-u32 nvbios_M0209Sp(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr,
-		   struct nvbios_M0209S *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/P0260.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/P0260.h
deleted file mode 100644
index bba01ab1e049..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/P0260.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef __NVBIOS_P0260_H__
-#define __NVBIOS_P0260_H__
-
-u32 nvbios_P0260Te(struct nouveau_bios *,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz);
-
-struct nvbios_P0260E {
-	u32 data;
-};
-
-u32 nvbios_P0260Ee(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr);
-u32 nvbios_P0260Ep(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr,
-		   struct nvbios_P0260E *);
-
-struct nvbios_P0260X {
-	u32 data;
-};
-
-u32 nvbios_P0260Xe(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr);
-u32 nvbios_P0260Xp(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr,
-		   struct nvbios_P0260X *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/bit.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/bit.h
deleted file mode 100644
index 73f060b07981..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/bit.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __NVBIOS_BIT_H__
-#define __NVBIOS_BIT_H__
-
-struct bit_entry {
-	u8  id;
-	u8  version;
-	u16 length;
-	u16 offset;
-};
-
-int bit_entry(struct nouveau_bios *, u8 id, struct bit_entry *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/bmp.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/bmp.h
deleted file mode 100644
index 10e4dbca649a..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/bmp.h
+++ /dev/null
@@ -1,39 +0,0 @@
-#ifndef __NVBIOS_BMP_H__
-#define __NVBIOS_BMP_H__
-
-static inline u16
-bmp_version(struct nouveau_bios *bios)
-{
-	if (bios->bmp_offset) {
-		return nv_ro08(bios, bios->bmp_offset + 5) << 8 |
-		       nv_ro08(bios, bios->bmp_offset + 6);
-	}
-
-	return 0x0000;
-}
-
-static inline u16
-bmp_mem_init_table(struct nouveau_bios *bios)
-{
-	if (bmp_version(bios) >= 0x0300)
-		return nv_ro16(bios, bios->bmp_offset + 24);
-	return 0x0000;
-}
-
-static inline u16
-bmp_sdr_seq_table(struct nouveau_bios *bios)
-{
-	if (bmp_version(bios) >= 0x0300)
-		return nv_ro16(bios, bios->bmp_offset + 26);
-	return 0x0000;
-}
-
-static inline u16
-bmp_ddr_seq_table(struct nouveau_bios *bios)
-{
-	if (bmp_version(bios) >= 0x0300)
-		return nv_ro16(bios, bios->bmp_offset + 28);
-	return 0x0000;
-}
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/boost.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/boost.h
deleted file mode 100644
index 662b20726851..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/boost.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef __NVBIOS_BOOST_H__
-#define __NVBIOS_BOOST_H__
-
-u16 nvbios_boostTe(struct nouveau_bios *, u8 *, u8 *, u8 *, u8 *, u8 *, u8 *);
-
-struct nvbios_boostE {
-	u8  pstate;
-	u32 min;
-	u32 max;
-};
-
-u16 nvbios_boostEe(struct nouveau_bios *, int idx, u8 *, u8 *, u8 *, u8 *);
-u16 nvbios_boostEp(struct nouveau_bios *, int idx, u8 *, u8 *, u8 *, u8 *,
-		   struct nvbios_boostE *);
-u16 nvbios_boostEm(struct nouveau_bios *, u8, u8 *, u8 *, u8 *, u8 *,
-		   struct nvbios_boostE *);
-
-struct nvbios_boostS {
-	u8  domain;
-	u8  percent;
-	u32 min;
-	u32 max;
-};
-
-u16 nvbios_boostSe(struct nouveau_bios *, int, u16, u8 *, u8 *, u8, u8);
-u16 nvbios_boostSp(struct nouveau_bios *, int, u16, u8 *, u8 *, u8, u8,
-		   struct nvbios_boostS *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/conn.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/conn.h
deleted file mode 100644
index f3930c27cb7a..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/conn.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef __NVBIOS_CONN_H__
-#define __NVBIOS_CONN_H__
-
-enum dcb_connector_type {
-	DCB_CONNECTOR_VGA = 0x00,
-	DCB_CONNECTOR_TV_0 = 0x10,
-	DCB_CONNECTOR_TV_1 = 0x11,
-	DCB_CONNECTOR_TV_3 = 0x13,
-	DCB_CONNECTOR_DVI_I = 0x30,
-	DCB_CONNECTOR_DVI_D = 0x31,
-	DCB_CONNECTOR_DMS59_0 = 0x38,
-	DCB_CONNECTOR_DMS59_1 = 0x39,
-	DCB_CONNECTOR_LVDS = 0x40,
-	DCB_CONNECTOR_LVDS_SPWG = 0x41,
-	DCB_CONNECTOR_DP = 0x46,
-	DCB_CONNECTOR_eDP = 0x47,
-	DCB_CONNECTOR_HDMI_0 = 0x60,
-	DCB_CONNECTOR_HDMI_1 = 0x61,
-	DCB_CONNECTOR_HDMI_C = 0x63,
-	DCB_CONNECTOR_DMS59_DP0 = 0x64,
-	DCB_CONNECTOR_DMS59_DP1 = 0x65,
-	DCB_CONNECTOR_NONE = 0xff
-};
-
-struct nvbios_connT {
-};
-
-u32 nvbios_connTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u32 nvbios_connTp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		  struct nvbios_connT *info);
-
-struct nvbios_connE {
-	u8 type;
-	u8 location;
-	u8 hpd;
-	u8 dp;
-	u8 di;
-	u8 sr;
-	u8 lcdid;
-};
-
-u32 nvbios_connEe(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *hdr);
-u32 nvbios_connEp(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *hdr,
-		  struct nvbios_connE *info);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/cstep.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/cstep.h
deleted file mode 100644
index a80a43809883..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/cstep.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef __NVBIOS_CSTEP_H__
-#define __NVBIOS_CSTEP_H__
-
-u16 nvbios_cstepTe(struct nouveau_bios *,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz);
-
-struct nvbios_cstepE {
-	u8  pstate;
-	u8  index;
-};
-
-u16 nvbios_cstepEe(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr);
-u16 nvbios_cstepEp(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr,
-		   struct nvbios_cstepE *);
-u16 nvbios_cstepEm(struct nouveau_bios *, u8 pstate, u8 *ver, u8 *hdr,
-		   struct nvbios_cstepE *);
-
-struct nvbios_cstepX {
-	u32 freq;
-	u8  unkn[2];
-	u8  voltage;
-};
-
-u16 nvbios_cstepXe(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr);
-u16 nvbios_cstepXp(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr,
-		   struct nvbios_cstepX *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/dcb.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/dcb.h
deleted file mode 100644
index 123270e9813a..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/dcb.h
+++ /dev/null
@@ -1,69 +0,0 @@
-#ifndef __NVBIOS_DCB_H__
-#define __NVBIOS_DCB_H__
-
-struct nouveau_bios;
-
-enum dcb_output_type {
-	DCB_OUTPUT_ANALOG	= 0x0,
-	DCB_OUTPUT_TV		= 0x1,
-	DCB_OUTPUT_TMDS		= 0x2,
-	DCB_OUTPUT_LVDS		= 0x3,
-	DCB_OUTPUT_DP		= 0x6,
-	DCB_OUTPUT_EOL		= 0xe,
-	DCB_OUTPUT_UNUSED	= 0xf,
-	DCB_OUTPUT_ANY = -1,
-};
-
-struct dcb_output {
-	int index;	/* may not be raw dcb index if merging has happened */
-	u16 hasht;
-	u16 hashm;
-	enum dcb_output_type type;
-	uint8_t i2c_index;
-	uint8_t heads;
-	uint8_t connector;
-	uint8_t bus;
-	uint8_t location;
-	uint8_t or;
-	uint8_t link;
-	bool duallink_possible;
-	uint8_t extdev;
-	union {
-		struct sor_conf {
-			int link;
-		} sorconf;
-		struct {
-			int maxfreq;
-		} crtconf;
-		struct {
-			struct sor_conf sor;
-			bool use_straps_for_mode;
-			bool use_acpi_for_edid;
-			bool use_power_scripts;
-		} lvdsconf;
-		struct {
-			bool has_component_output;
-		} tvconf;
-		struct {
-			struct sor_conf sor;
-			int link_nr;
-			int link_bw;
-		} dpconf;
-		struct {
-			struct sor_conf sor;
-			int slave_addr;
-		} tmdsconf;
-	};
-	bool i2c_upper_default;
-};
-
-u16 dcb_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *ent, u8 *len);
-u16 dcb_outp(struct nouveau_bios *, u8 idx, u8 *ver, u8 *len);
-u16 dcb_outp_parse(struct nouveau_bios *, u8 idx, u8 *, u8 *,
-		   struct dcb_output *);
-u16 dcb_outp_match(struct nouveau_bios *, u16 type, u16 mask, u8 *, u8 *,
-		   struct dcb_output *);
-int dcb_outp_foreach(struct nouveau_bios *, void *data, int (*exec)
-		     (struct nouveau_bios *, void *, int index, u16 entry));
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/disp.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/disp.h
deleted file mode 100644
index c35937e2f6a4..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/disp.h
+++ /dev/null
@@ -1,48 +0,0 @@
-#ifndef __NVBIOS_DISP_H__
-#define __NVBIOS_DISP_H__
-
-u16 nvbios_disp_table(struct nouveau_bios *,
-		      u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *sub);
-
-struct nvbios_disp {
-	u16 data;
-};
-
-u16 nvbios_disp_entry(struct nouveau_bios *, u8 idx,
-		      u8 *ver, u8 *hdr__, u8 *sub);
-u16 nvbios_disp_parse(struct nouveau_bios *, u8 idx,
-		      u8 *ver, u8 *hdr__, u8 *sub,
-		      struct nvbios_disp *);
-
-struct nvbios_outp {
-	u16 type;
-	u16 mask;
-	u16 script[3];
-};
-
-u16 nvbios_outp_entry(struct nouveau_bios *, u8 idx,
-		      u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u16 nvbios_outp_parse(struct nouveau_bios *, u8 idx,
-		      u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		      struct nvbios_outp *);
-u16 nvbios_outp_match(struct nouveau_bios *, u16 type, u16 mask,
-		      u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		      struct nvbios_outp *);
-
-
-struct nvbios_ocfg {
-	u16 match;
-	u16 clkcmp[2];
-};
-
-u16 nvbios_ocfg_entry(struct nouveau_bios *, u16 outp, u8 idx,
-		      u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u16 nvbios_ocfg_parse(struct nouveau_bios *, u16 outp, u8 idx,
-		      u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		      struct nvbios_ocfg *);
-u16 nvbios_ocfg_match(struct nouveau_bios *, u16 outp, u16 type,
-		      u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		      struct nvbios_ocfg *);
-u16 nvbios_oclk_match(struct nouveau_bios *, u16 cmp, u32 khz);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/dp.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/dp.h
deleted file mode 100644
index 728206e21777..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/dp.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef __NVBIOS_DP_H__
-#define __NVBIOS_DP_H__
-
-struct nvbios_dpout {
-	u16 type;
-	u16 mask;
-	u8  flags;
-	u32 script[5];
-	u32 lnkcmp;
-};
-
-u16 nvbios_dpout_parse(struct nouveau_bios *, u8 idx,
-		       u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		       struct nvbios_dpout *);
-u16 nvbios_dpout_match(struct nouveau_bios *, u16 type, u16 mask,
-		       u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		       struct nvbios_dpout *);
-
-struct nvbios_dpcfg {
-	u8 pc;
-	u8 dc;
-	u8 pe;
-	u8 tx_pu;
-};
-
-u16
-nvbios_dpcfg_parse(struct nouveau_bios *, u16 outp, u8 idx,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		   struct nvbios_dpcfg *);
-u16
-nvbios_dpcfg_match(struct nouveau_bios *, u16 outp, u8 pc, u8 vs, u8 pe,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		   struct nvbios_dpcfg *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/extdev.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/extdev.h
deleted file mode 100644
index 949fee3af8fb..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/extdev.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef __NVBIOS_EXTDEV_H__
-#define __NVBIOS_EXTDEV_H__
-
-struct nouveau_bios;
-
-enum nvbios_extdev_type {
-	NVBIOS_EXTDEV_LM89		= 0x02,
-	NVBIOS_EXTDEV_VT1103M		= 0x40,
-	NVBIOS_EXTDEV_PX3540		= 0x41,
-	NVBIOS_EXTDEV_VT1105M		= 0x42, /* or close enough... */
-	NVBIOS_EXTDEV_ADT7473		= 0x70, /* can also be a LM64 */
-	NVBIOS_EXTDEV_HDCP_EEPROM	= 0x90,
-	NVBIOS_EXTDEV_NONE		= 0xff,
-};
-
-struct nvbios_extdev_func {
-	u8 type;
-	u8 addr;
-	u8 bus;
-};
-
-int
-nvbios_extdev_parse(struct nouveau_bios *, int, struct nvbios_extdev_func *);
-
-int
-nvbios_extdev_find(struct nouveau_bios *, enum nvbios_extdev_type,
-		   struct nvbios_extdev_func *);
-
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/fan.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/fan.h
deleted file mode 100644
index 119d0874e041..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/fan.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __NVBIOS_FAN_H__
-#define __NVBIOS_FAN_H__
-
-#include <subdev/bios/therm.h>
-
-u16 nvbios_fan_parse(struct nouveau_bios *bios, struct nvbios_therm_fan *fan);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/gpio.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/gpio.h
deleted file mode 100644
index c7b2e586be0b..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/gpio.h
+++ /dev/null
@@ -1,48 +0,0 @@
-#ifndef __NVBIOS_GPIO_H__
-#define __NVBIOS_GPIO_H__
-
-enum dcb_gpio_func_name {
-	DCB_GPIO_PANEL_POWER = 0x01,
-	DCB_GPIO_TVDAC0 = 0x0c,
-	DCB_GPIO_TVDAC1 = 0x2d,
-	DCB_GPIO_FAN = 0x09,
-	DCB_GPIO_FAN_SENSE = 0x3d,
-	DCB_GPIO_UNUSED = 0xff,
-	DCB_GPIO_VID0 = 0x04,
-	DCB_GPIO_VID1 = 0x05,
-	DCB_GPIO_VID2 = 0x06,
-	DCB_GPIO_VID3 = 0x1a,
-	DCB_GPIO_VID4 = 0x73,
-	DCB_GPIO_VID5 = 0x74,
-	DCB_GPIO_VID6 = 0x75,
-	DCB_GPIO_VID7 = 0x76,
-};
-
-#define DCB_GPIO_LOG_DIR     0x02
-#define DCB_GPIO_LOG_DIR_OUT 0x00
-#define DCB_GPIO_LOG_DIR_IN  0x02
-#define DCB_GPIO_LOG_VAL     0x01
-#define DCB_GPIO_LOG_VAL_LO  0x00
-#define DCB_GPIO_LOG_VAL_HI  0x01
-
-struct dcb_gpio_func {
-	u8 func;
-	u8 line;
-	u8 log[2];
-
-	/* so far, "param" seems to only have an influence on PWM-related
-	 * GPIOs such as FAN_CONTROL and PANEL_BACKLIGHT_LEVEL.
-	 * if param equals 1, hardware PWM is available
-	 * if param equals 0, the host should toggle the GPIO itself
-	 */
-	u8 param;
-};
-
-u16 dcb_gpio_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u16 dcb_gpio_entry(struct nouveau_bios *, int idx, int ent, u8 *ver, u8 *len);
-u16 dcb_gpio_parse(struct nouveau_bios *, int idx, int ent, u8 *ver, u8 *len,
-		   struct dcb_gpio_func *);
-u16 dcb_gpio_match(struct nouveau_bios *, int idx, u8 func, u8 line,
-		   u8 *ver, u8 *len, struct dcb_gpio_func *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/i2c.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/i2c.h
deleted file mode 100644
index c9bb112895af..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/i2c.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef __NVBIOS_I2C_H__
-#define __NVBIOS_I2C_H__
-
-struct nouveau_bios;
-
-enum dcb_i2c_type {
-	/* matches bios type field prior to ccb 4.1 */
-	DCB_I2C_NV04_BIT = 0x00,
-	DCB_I2C_NV4E_BIT = 0x04,
-	DCB_I2C_NVIO_BIT = 0x05,
-	DCB_I2C_NVIO_AUX = 0x06,
-	/* made up - mostly */
-	DCB_I2C_PMGR     = 0x80,
-	DCB_I2C_UNUSED   = 0xff
-};
-
-struct dcb_i2c_entry {
-	enum dcb_i2c_type type;
-	u8 drive;
-	u8 sense;
-	u8 share;
-	u8 auxch;
-};
-
-u16 dcb_i2c_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u16 dcb_i2c_entry(struct nouveau_bios *, u8 index, u8 *ver, u8 *len);
-int dcb_i2c_parse(struct nouveau_bios *, u8 index, struct dcb_i2c_entry *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/image.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/image.h
deleted file mode 100644
index 3348b4580843..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/image.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __NVBIOS_IMAGE_H__
-#define __NVBIOS_IMAGE_H__
-
-struct nvbios_image {
-	u32  base;
-	u32  size;
-	u8   type;
-	bool last;
-};
-
-bool nvbios_image(struct nouveau_bios *, int, struct nvbios_image *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h
deleted file mode 100644
index ca2f6bf37f46..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef __NVBIOS_INIT_H__
-#define __NVBIOS_INIT_H__
-
-struct nvbios_init {
-	struct nouveau_subdev *subdev;
-	struct nouveau_bios *bios;
-	u16 offset;
-	struct dcb_output *outp;
-	int crtc;
-
-	/* internal state used during parsing */
-	u8 execute;
-	u32 nested;
-	u16 repeat;
-	u16 repend;
-	u32 ramcfg;
-};
-
-int nvbios_exec(struct nvbios_init *);
-int nvbios_init(struct nouveau_subdev *, bool execute);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/mxm.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/mxm.h
deleted file mode 100644
index 5572e60414e8..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/mxm.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __NVBIOS_MXM_H__
-#define __NVBIOS_MXM_H__
-
-u16 mxm_table(struct nouveau_bios *, u8 *ver, u8 *hdr);
-
-u8  mxm_sor_map(struct nouveau_bios *, u8 conn);
-u8  mxm_ddc_map(struct nouveau_bios *, u8 port);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/npde.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/npde.h
deleted file mode 100644
index b18413d951e5..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/npde.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __NVBIOS_NPDE_H__
-#define __NVBIOS_NPDE_H__
-
-struct nvbios_npdeT {
-	u32 image_size;
-	bool last;
-};
-
-u32 nvbios_npdeTe(struct nouveau_bios *, u32);
-u32 nvbios_npdeTp(struct nouveau_bios *, u32, struct nvbios_npdeT *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pcir.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/pcir.h
deleted file mode 100644
index 3d634a06dca1..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pcir.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef __NVBIOS_PCIR_H__
-#define __NVBIOS_PCIR_H__
-
-struct nvbios_pcirT {
-	u16 vendor_id;
-	u16 device_id;
-	u8  class_code[3];
-	u32 image_size;
-	u16 image_rev;
-	u8  image_type;
-	bool last;
-};
-
-u32 nvbios_pcirTe(struct nouveau_bios *, u32, u8 *ver, u16 *hdr);
-u32 nvbios_pcirTp(struct nouveau_bios *, u32, u8 *ver, u16 *hdr,
-		  struct nvbios_pcirT *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/perf.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/perf.h
deleted file mode 100644
index 16ff06ec2a88..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/perf.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef __NVBIOS_PERF_H__
-#define __NVBIOS_PERF_H__
-
-struct nouveau_bios;
-
-u16 nvbios_perf_table(struct nouveau_bios *, u8 *ver, u8 *hdr,
-		      u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
-
-struct nvbios_perfE {
-	u8  pstate;
-	u8  fanspeed;
-	u8  voltage;
-	u32 core;
-	u32 shader;
-	u32 memory;
-	u32 vdec;
-	u32 disp;
-	u32 script;
-};
-
-u16 nvbios_perf_entry(struct nouveau_bios *, int idx,
-		      u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u16 nvbios_perfEp(struct nouveau_bios *, int idx,
-		  u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_perfE *);
-
-struct nvbios_perfS {
-	union {
-		struct {
-			u32 freq;
-		} v40;
-	};
-};
-
-u32 nvbios_perfSe(struct nouveau_bios *, u32 data, int idx,
-		  u8 *ver, u8 *hdr, u8 cnt, u8 len);
-u32 nvbios_perfSp(struct nouveau_bios *, u32 data, int idx,
-		  u8 *ver, u8 *hdr, u8 cnt, u8 len, struct nvbios_perfS *);
-
-struct nvbios_perf_fan {
-	u32 pwm_divisor;
-};
-
-int
-nvbios_perf_fan_parse(struct nouveau_bios *, struct nvbios_perf_fan *);
-
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h
deleted file mode 100644
index b2f3d4d0aa49..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h
+++ /dev/null
@@ -1,79 +0,0 @@
-#ifndef __NVBIOS_PLL_H__
-#define __NVBIOS_PLL_H__
-
-/*XXX: kill me */
-struct nouveau_pll_vals {
-	union {
-		struct {
-#ifdef __BIG_ENDIAN
-			uint8_t N1, M1, N2, M2;
-#else
-			uint8_t M1, N1, M2, N2;
-#endif
-		};
-		struct {
-			uint16_t NM1, NM2;
-		} __attribute__((packed));
-	};
-	int log2P;
-
-	int refclk;
-};
-
-struct nouveau_bios;
-
-/* these match types in pll limits table version 0x40,
- * nouveau uses them on all chipsets internally where a
- * specific pll needs to be referenced, but the exact
- * register isn't known.
- */
-enum nvbios_pll_type {
-	PLL_CORE   = 0x01,
-	PLL_SHADER = 0x02,
-	PLL_UNK03  = 0x03,
-	PLL_MEMORY = 0x04,
-	PLL_VDEC   = 0x05,
-	PLL_UNK40  = 0x40,
-	PLL_UNK41  = 0x41,
-	PLL_UNK42  = 0x42,
-	PLL_VPLL0  = 0x80,
-	PLL_VPLL1  = 0x81,
-	PLL_VPLL2  = 0x82,
-	PLL_VPLL3  = 0x83,
-	PLL_MAX    = 0xff
-};
-
-struct nvbios_pll {
-	enum nvbios_pll_type type;
-	u32 reg;
-	u32 refclk;
-
-	u8 min_p;
-	u8 max_p;
-	u8 bias_p;
-
-	/*
-	 * for most pre nv50 cards setting a log2P of 7 (the common max_log2p
-	 * value) is no different to 6 (at least for vplls) so allowing the MNP
-	 * calc to use 7 causes the generated clock to be out by a factor of 2.
-	 * however, max_log2p cannot be fixed-up during parsing as the
-	 * unmodified max_log2p value is still needed for setting mplls, hence
-	 * an additional max_usable_log2p member
-	 */
-	u8 max_p_usable;
-
-	struct {
-		u32 min_freq;
-		u32 max_freq;
-		u32 min_inputfreq;
-		u32 max_inputfreq;
-		u8  min_m;
-		u8  max_m;
-		u8  min_n;
-		u8  max_n;
-	} vco1, vco2;
-};
-
-int nvbios_pll_parse(struct nouveau_bios *, u32 type, struct nvbios_pll *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pmu.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/pmu.h
deleted file mode 100644
index 9de593deaea8..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pmu.h
+++ /dev/null
@@ -1,37 +0,0 @@
-#ifndef __NVBIOS_PMU_H__
-#define __NVBIOS_PMU_H__
-
-struct nvbios_pmuT {
-};
-
-u32 nvbios_pmuTe(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u32 nvbios_pmuTp(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		 struct nvbios_pmuT *);
-
-struct nvbios_pmuE {
-	u8  type;
-	u32 data;
-};
-
-u32 nvbios_pmuEe(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr);
-u32 nvbios_pmuEp(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr,
-		 struct nvbios_pmuE *);
-
-struct nvbios_pmuR {
-	u32 boot_addr_pmu;
-	u32 boot_addr;
-	u32 boot_size;
-	u32 code_addr_pmu;
-	u32 code_addr;
-	u32 code_size;
-	u32 init_addr_pmu;
-
-	u32 data_addr_pmu;
-	u32 data_addr;
-	u32 data_size;
-	u32 args_addr_pmu;
-};
-
-bool nvbios_pmuRm(struct nouveau_bios *, u8 type, struct nvbios_pmuR *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h
deleted file mode 100644
index 4a0e0ceb41ba..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h
+++ /dev/null
@@ -1,145 +0,0 @@
-#ifndef __NVBIOS_RAMCFG_H__
-#define __NVBIOS_RAMCFG_H__
-
-struct nouveau_bios;
-
-struct nvbios_ramcfg {
-	unsigned rammap_ver;
-	unsigned rammap_hdr;
-	unsigned rammap_min;
-	unsigned rammap_max;
-	union {
-		struct {
-			unsigned rammap_10_04_02:1;
-			unsigned rammap_10_04_08:1;
-		};
-		struct {
-			unsigned rammap_11_08_01:1;
-			unsigned rammap_11_08_0c:2;
-			unsigned rammap_11_08_10:1;
-			unsigned rammap_11_09_01ff:9;
-			unsigned rammap_11_0a_03fe:9;
-			unsigned rammap_11_0a_0400:1;
-			unsigned rammap_11_0a_0800:1;
-			unsigned rammap_11_0b_01f0:5;
-			unsigned rammap_11_0b_0200:1;
-			unsigned rammap_11_0b_0400:1;
-			unsigned rammap_11_0b_0800:1;
-			unsigned rammap_11_0d:8;
-			unsigned rammap_11_0e:8;
-			unsigned rammap_11_0f:8;
-			unsigned rammap_11_11_0c:2;
-		};
-	};
-
-	unsigned ramcfg_ver;
-	unsigned ramcfg_hdr;
-	unsigned ramcfg_timing;
-	union {
-		struct {
-			unsigned ramcfg_10_02_01:1;
-			unsigned ramcfg_10_02_02:1;
-			unsigned ramcfg_10_02_04:1;
-			unsigned ramcfg_10_02_08:1;
-			unsigned ramcfg_10_02_10:1;
-			unsigned ramcfg_10_02_20:1;
-			unsigned ramcfg_10_DLLoff:1;
-			unsigned ramcfg_10_03_0f:4;
-			unsigned ramcfg_10_04_01:1;
-			unsigned ramcfg_10_05:8;
-			unsigned ramcfg_10_06:8;
-			unsigned ramcfg_10_07:8;
-			unsigned ramcfg_10_08:8;
-			unsigned ramcfg_10_09_0f:4;
-			unsigned ramcfg_10_09_f0:4;
-		};
-		struct {
-			unsigned ramcfg_11_01_01:1;
-			unsigned ramcfg_11_01_02:1;
-			unsigned ramcfg_11_01_04:1;
-			unsigned ramcfg_11_01_08:1;
-			unsigned ramcfg_11_01_10:1;
-			unsigned ramcfg_11_01_20:1;
-			unsigned ramcfg_11_01_40:1;
-			unsigned ramcfg_11_01_80:1;
-			unsigned ramcfg_11_02_03:2;
-			unsigned ramcfg_11_02_04:1;
-			unsigned ramcfg_11_02_08:1;
-			unsigned ramcfg_11_02_10:1;
-			unsigned ramcfg_11_02_40:1;
-			unsigned ramcfg_11_02_80:1;
-			unsigned ramcfg_11_03_0f:4;
-			unsigned ramcfg_11_03_30:2;
-			unsigned ramcfg_11_03_c0:2;
-			unsigned ramcfg_11_03_f0:4;
-			unsigned ramcfg_11_04:8;
-			unsigned ramcfg_11_06:8;
-			unsigned ramcfg_11_07_02:1;
-			unsigned ramcfg_11_07_04:1;
-			unsigned ramcfg_11_07_08:1;
-			unsigned ramcfg_11_07_10:1;
-			unsigned ramcfg_11_07_40:1;
-			unsigned ramcfg_11_07_80:1;
-			unsigned ramcfg_11_08_01:1;
-			unsigned ramcfg_11_08_02:1;
-			unsigned ramcfg_11_08_04:1;
-			unsigned ramcfg_11_08_08:1;
-			unsigned ramcfg_11_08_10:1;
-			unsigned ramcfg_11_08_20:1;
-			unsigned ramcfg_11_09:8;
-		};
-	};
-
-	unsigned timing_ver;
-	unsigned timing_hdr;
-	unsigned timing[11];
-	union {
-		struct {
-			unsigned timing_10_WR:8;
-			unsigned timing_10_WTR:8;
-			unsigned timing_10_CL:8;
-			unsigned timing_10_RC:8;
-			/*empty: 4 */
-			unsigned timing_10_RFC:8;        /* Byte 5 */
-			/*empty: 6 */
-			unsigned timing_10_RAS:8;        /* Byte 7 */
-			/*empty: 8 */
-			unsigned timing_10_RP:8;         /* Byte 9 */
-			unsigned timing_10_RCDRD:8;
-			unsigned timing_10_RCDWR:8;
-			unsigned timing_10_RRD:8;
-			unsigned timing_10_13:8;
-			unsigned timing_10_ODT:3;
-			/* empty: 15 */
-			unsigned timing_10_16:8;
-			/* empty: 17 */
-			unsigned timing_10_18:8;
-			unsigned timing_10_CWL:8;
-			unsigned timing_10_20:8;
-			unsigned timing_10_21:8;
-			/* empty: 22, 23 */
-			unsigned timing_10_24:8;
-		};
-		struct {
-			unsigned timing_20_2e_03:2;
-			unsigned timing_20_2e_30:2;
-			unsigned timing_20_2e_c0:2;
-			unsigned timing_20_2f_03:2;
-			unsigned timing_20_2c_003f:6;
-			unsigned timing_20_2c_1fc0:7;
-			unsigned timing_20_30_f8:5;
-			unsigned timing_20_30_07:3;
-			unsigned timing_20_31_0007:3;
-			unsigned timing_20_31_0078:4;
-			unsigned timing_20_31_0780:4;
-			unsigned timing_20_31_0800:1;
-			unsigned timing_20_31_7000:3;
-			unsigned timing_20_31_8000:1;
-		};
-	};
-};
-
-u8 nvbios_ramcfg_count(struct nouveau_bios *);
-u8 nvbios_ramcfg_index(struct nouveau_subdev *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h
deleted file mode 100644
index 47e021d3e20d..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef __NVBIOS_RAMMAP_H__
-#define __NVBIOS_RAMMAP_H__
-
-struct nvbios_ramcfg;
-
-u32 nvbios_rammapTe(struct nouveau_bios *, u8 *ver, u8 *hdr,
-		    u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
-
-u32 nvbios_rammapEe(struct nouveau_bios *, int idx,
-		    u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u32 nvbios_rammapEp(struct nouveau_bios *, int idx,
-		    u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		    struct nvbios_ramcfg *);
-u32 nvbios_rammapEm(struct nouveau_bios *, u16 mhz,
-		    u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		    struct nvbios_ramcfg *);
-
-u32 nvbios_rammapSe(struct nouveau_bios *, u32 data,
-		    u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
-		    u8 *ver, u8 *hdr);
-u32 nvbios_rammapSp(struct nouveau_bios *, u32 data,
-		    u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
-		    u8 *ver, u8 *hdr,
-		    struct nvbios_ramcfg *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/therm.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/therm.h
deleted file mode 100644
index 295d093f3b30..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/therm.h
+++ /dev/null
@@ -1,77 +0,0 @@
-#ifndef __NVBIOS_THERM_H__
-#define __NVBIOS_THERM_H__
-
-struct nouveau_bios;
-
-struct nvbios_therm_threshold {
-	u8 temp;
-	u8 hysteresis;
-};
-
-struct nvbios_therm_sensor {
-	/* diode */
-	s16 slope_mult;
-	s16 slope_div;
-	s16 offset_num;
-	s16 offset_den;
-	s8 offset_constant;
-
-	/* thresholds */
-	struct nvbios_therm_threshold thrs_fan_boost;
-	struct nvbios_therm_threshold thrs_down_clock;
-	struct nvbios_therm_threshold thrs_critical;
-	struct nvbios_therm_threshold thrs_shutdown;
-};
-
-enum nvbios_therm_fan_type {
-	NVBIOS_THERM_FAN_UNK = 0,
-	NVBIOS_THERM_FAN_TOGGLE = 1,
-	NVBIOS_THERM_FAN_PWM = 2,
-};
-
-/* no vbios have more than 6 */
-#define NOUVEAU_TEMP_FAN_TRIP_MAX 10
-struct nouveau_therm_trip_point {
-	int fan_duty;
-	int temp;
-	int hysteresis;
-};
-
-enum nvbios_therm_fan_mode {
-	NVBIOS_THERM_FAN_TRIP = 0,
-	NVBIOS_THERM_FAN_LINEAR = 1,
-	NVBIOS_THERM_FAN_OTHER = 2,
-};
-
-struct nvbios_therm_fan {
-	enum nvbios_therm_fan_type type;
-
-	u32 pwm_freq;
-
-	u8 min_duty;
-	u8 max_duty;
-
-	u16 bump_period;
-	u16 slow_down_period;
-
-	enum nvbios_therm_fan_mode fan_mode;
-	struct nouveau_therm_trip_point trip[NOUVEAU_TEMP_FAN_TRIP_MAX];
-	u8 nr_fan_trip;
-	u8 linear_min_temp;
-	u8 linear_max_temp;
-};
-
-enum nvbios_therm_domain {
-	NVBIOS_THERM_DOMAIN_CORE,
-	NVBIOS_THERM_DOMAIN_AMBIENT,
-};
-
-int
-nvbios_therm_sensor_parse(struct nouveau_bios *, enum nvbios_therm_domain,
-			  struct nvbios_therm_sensor *);
-
-int
-nvbios_therm_fan_parse(struct nouveau_bios *, struct nvbios_therm_fan *);
-
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h
deleted file mode 100644
index 76d914b67ab5..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef __NVBIOS_TIMING_H__
-#define __NVBIOS_TIMING_H__
-
-struct nvbios_ramcfg;
-
-u16 nvbios_timingTe(struct nouveau_bios *,
-		    u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
-u16 nvbios_timingEe(struct nouveau_bios *, int idx,
-		    u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u16 nvbios_timingEp(struct nouveau_bios *, int idx,
-		    u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		    struct nvbios_ramcfg *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/vmap.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/vmap.h
deleted file mode 100644
index ad5a8f20e113..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/vmap.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef __NVBIOS_VMAP_H__
-#define __NVBIOS_VMAP_H__
-
-struct nouveau_bios;
-
-struct nvbios_vmap {
-};
-
-u16 nvbios_vmap_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u16 nvbios_vmap_parse(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		      struct nvbios_vmap *);
-
-struct nvbios_vmap_entry {
-	u8  unk0;
-	u8  link;
-	u32 min;
-	u32 max;
-	s32 arg[6];
-};
-
-u16 nvbios_vmap_entry(struct nouveau_bios *, int idx, u8 *ver, u8 *len);
-u16 nvbios_vmap_entry_parse(struct nouveau_bios *, int idx, u8 *ver, u8 *len,
-			    struct nvbios_vmap_entry *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/volt.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/volt.h
deleted file mode 100644
index 6a11dcd59770..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/volt.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef __NVBIOS_VOLT_H__
-#define __NVBIOS_VOLT_H__
-
-struct nouveau_bios;
-
-struct nvbios_volt {
-	u8  vidmask;
-	u32 min;
-	u32 max;
-	u32 base;
-	s16 step;
-};
-
-u16 nvbios_volt_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u16 nvbios_volt_parse(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		      struct nvbios_volt *);
-
-struct nvbios_volt_entry {
-	u32 voltage;
-	u8  vid;
-};
-
-u16 nvbios_volt_entry(struct nouveau_bios *, int idx, u8 *ver, u8 *len);
-u16 nvbios_volt_entry_parse(struct nouveau_bios *, int idx, u8 *ver, u8 *len,
-			    struct nvbios_volt_entry *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/xpio.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/xpio.h
deleted file mode 100644
index 360baab52e4c..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/xpio.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef __NVBIOS_XPIO_H__
-#define __NVBIOS_XPIO_H__
-
-#define NVBIOS_XPIO_FLAG_AUX  0x10
-#define NVBIOS_XPIO_FLAG_AUX0 0x00
-#define NVBIOS_XPIO_FLAG_AUX1 0x10
-
-struct nvbios_xpio {
-	u8 type;
-	u8 addr;
-	u8 flags;
-};
-
-u16 dcb_xpio_table(struct nouveau_bios *, u8 idx,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u16 dcb_xpio_parse(struct nouveau_bios *, u8 idx,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_xpio *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bus.h b/drivers/gpu/drm/nouveau/core/include/subdev/bus.h
deleted file mode 100644
index 697f7ce70aab..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bus.h
+++ /dev/null
@@ -1,53 +0,0 @@
-#ifndef __NOUVEAU_BUS_H__
-#define __NOUVEAU_BUS_H__
-
-#include <core/subdev.h>
-#include <core/device.h>
-
-struct nouveau_bus_intr {
-	u32 stat;
-	u32 unit;
-};
-
-struct nouveau_bus {
-	struct nouveau_subdev base;
-	int (*hwsq_exec)(struct nouveau_bus *, u32 *, u32);
-	u32 hwsq_size;
-};
-
-static inline struct nouveau_bus *
-nouveau_bus(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_BUS];
-}
-
-#define nouveau_bus_create(p, e, o, d)                                         \
-	nouveau_subdev_create_((p), (e), (o), 0, "PBUS", "master",             \
-			       sizeof(**d), (void **)d)
-#define nouveau_bus_destroy(p)                                                 \
-	nouveau_subdev_destroy(&(p)->base)
-#define nouveau_bus_init(p)                                                    \
-	nouveau_subdev_init(&(p)->base)
-#define nouveau_bus_fini(p, s)                                                 \
-	nouveau_subdev_fini(&(p)->base, (s))
-
-#define _nouveau_bus_dtor _nouveau_subdev_dtor
-#define _nouveau_bus_init _nouveau_subdev_init
-#define _nouveau_bus_fini _nouveau_subdev_fini
-
-extern struct nouveau_oclass *nv04_bus_oclass;
-extern struct nouveau_oclass *nv31_bus_oclass;
-extern struct nouveau_oclass *nv50_bus_oclass;
-extern struct nouveau_oclass *nv94_bus_oclass;
-extern struct nouveau_oclass *nvc0_bus_oclass;
-
-/* interface to sequencer */
-struct nouveau_hwsq;
-int  nouveau_hwsq_init(struct nouveau_bus *, struct nouveau_hwsq **);
-int  nouveau_hwsq_fini(struct nouveau_hwsq **, bool exec);
-void nouveau_hwsq_wr32(struct nouveau_hwsq *, u32 addr, u32 data);
-void nouveau_hwsq_setf(struct nouveau_hwsq *, u8 flag, int data);
-void nouveau_hwsq_wait(struct nouveau_hwsq *, u8 flag, u8 data);
-void nouveau_hwsq_nsec(struct nouveau_hwsq *, u32 nsec);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
deleted file mode 100644
index 36ed035d4d42..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
+++ /dev/null
@@ -1,166 +0,0 @@
-#ifndef __NOUVEAU_CLOCK_H__
-#define __NOUVEAU_CLOCK_H__
-
-#include <core/device.h>
-#include <core/subdev.h>
-
-struct nouveau_pll_vals;
-struct nvbios_pll;
-
-enum nv_clk_src {
-	nv_clk_src_crystal,
-	nv_clk_src_href,
-
-	nv_clk_src_hclk,
-	nv_clk_src_hclkm3,
-	nv_clk_src_hclkm3d2,
-	nv_clk_src_hclkm2d3, /* NVAA */
-	nv_clk_src_hclkm4, /* NVAA */
-	nv_clk_src_cclk, /* NVAA */
-
-	nv_clk_src_host,
-
-	nv_clk_src_sppll0,
-	nv_clk_src_sppll1,
-
-	nv_clk_src_mpllsrcref,
-	nv_clk_src_mpllsrc,
-	nv_clk_src_mpll,
-	nv_clk_src_mdiv,
-
-	nv_clk_src_core,
-	nv_clk_src_core_intm,
-	nv_clk_src_shader,
-
-	nv_clk_src_mem,
-
-	nv_clk_src_gpc,
-	nv_clk_src_rop,
-	nv_clk_src_hubk01,
-	nv_clk_src_hubk06,
-	nv_clk_src_hubk07,
-	nv_clk_src_copy,
-	nv_clk_src_daemon,
-	nv_clk_src_disp,
-	nv_clk_src_vdec,
-
-	nv_clk_src_dom6,
-
-	nv_clk_src_max,
-};
-
-struct nouveau_cstate {
-	struct list_head head;
-	u8  voltage;
-	u32 domain[nv_clk_src_max];
-};
-
-struct nouveau_pstate {
-	struct list_head head;
-	struct list_head list; /* c-states */
-	struct nouveau_cstate base;
-	u8 pstate;
-	u8 fanspeed;
-};
-
-struct nouveau_clock {
-	struct nouveau_subdev base;
-
-	struct nouveau_clocks *domains;
-	struct nouveau_pstate bstate;
-
-	struct list_head states;
-	int state_nr;
-
-	struct work_struct work;
-	wait_queue_head_t wait;
-	atomic_t waiting;
-
-	struct nvkm_notify pwrsrc_ntfy;
-	int pwrsrc;
-	int pstate; /* current */
-	int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */
-	int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */
-	int astate; /* perfmon adjustment (base) */
-	int tstate; /* thermal adjustment (max-) */
-	int dstate; /* display adjustment (min+) */
-
-	bool allow_reclock;
-
-	int  (*read)(struct nouveau_clock *, enum nv_clk_src);
-	int  (*calc)(struct nouveau_clock *, struct nouveau_cstate *);
-	int  (*prog)(struct nouveau_clock *);
-	void (*tidy)(struct nouveau_clock *);
-
-	/*XXX: die, these are here *only* to support the completely
-	 *     bat-shit insane what-was-nouveau_hw.c code
-	 */
-	int (*pll_calc)(struct nouveau_clock *, struct nvbios_pll *,
-			int clk, struct nouveau_pll_vals *pv);
-	int (*pll_prog)(struct nouveau_clock *, u32 reg1,
-			struct nouveau_pll_vals *pv);
-};
-
-static inline struct nouveau_clock *
-nouveau_clock(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_CLOCK];
-}
-
-struct nouveau_clocks {
-	enum nv_clk_src name;
-	u8 bios; /* 0xff for none */
-#define NVKM_CLK_DOM_FLAG_CORE 0x01
-	u8 flags;
-	const char *mname;
-	int mdiv;
-};
-
-#define nouveau_clock_create(p,e,o,i,r,s,n,d)                                  \
-	nouveau_clock_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d),  \
-			      (void **)d)
-#define nouveau_clock_destroy(p) ({                                            \
-	struct nouveau_clock *clk = (p);                                       \
-	_nouveau_clock_dtor(nv_object(clk));                                   \
-})
-#define nouveau_clock_init(p) ({                                               \
-	struct nouveau_clock *clk = (p);                                       \
-	_nouveau_clock_init(nv_object(clk));                                   \
-})
-#define nouveau_clock_fini(p,s) ({                                             \
-	struct nouveau_clock *clk = (p);                                       \
-	_nouveau_clock_fini(nv_object(clk), (s));                              \
-})
-
-int  nouveau_clock_create_(struct nouveau_object *, struct nouveau_object *,
-			   struct nouveau_oclass *,
-			   struct nouveau_clocks *, struct nouveau_pstate *,
-			   int, bool, int, void **);
-void _nouveau_clock_dtor(struct nouveau_object *);
-int  _nouveau_clock_init(struct nouveau_object *);
-int  _nouveau_clock_fini(struct nouveau_object *, bool);
-
-extern struct nouveau_oclass nv04_clock_oclass;
-extern struct nouveau_oclass nv40_clock_oclass;
-extern struct nouveau_oclass *nv50_clock_oclass;
-extern struct nouveau_oclass *nv84_clock_oclass;
-extern struct nouveau_oclass *nvaa_clock_oclass;
-extern struct nouveau_oclass nva3_clock_oclass;
-extern struct nouveau_oclass nvc0_clock_oclass;
-extern struct nouveau_oclass nve0_clock_oclass;
-extern struct nouveau_oclass gk20a_clock_oclass;
-
-int nv04_clock_pll_set(struct nouveau_clock *, u32 type, u32 freq);
-int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
-			int clk, struct nouveau_pll_vals *);
-int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1,
-			struct nouveau_pll_vals *);
-int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
-			int clk, struct nouveau_pll_vals *);
-
-int nouveau_clock_ustate(struct nouveau_clock *, int req, int pwr);
-int nouveau_clock_astate(struct nouveau_clock *, int req, int rel);
-int nouveau_clock_dstate(struct nouveau_clock *, int req, int rel);
-int nouveau_clock_tstate(struct nouveau_clock *, int req, int rel);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h b/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h
deleted file mode 100644
index e007a9d44683..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef __NOUVEAU_DEVINIT_H__
-#define __NOUVEAU_DEVINIT_H__
-
-#include <core/subdev.h>
-#include <core/device.h>
-
-struct nouveau_devinit {
-	struct nouveau_subdev base;
-	bool post;
-	void (*meminit)(struct nouveau_devinit *);
-	int  (*pll_set)(struct nouveau_devinit *, u32 type, u32 freq);
-	u32  (*mmio)(struct nouveau_devinit *, u32 addr);
-};
-
-static inline struct nouveau_devinit *
-nouveau_devinit(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_DEVINIT];
-}
-
-extern struct nouveau_oclass *nv04_devinit_oclass;
-extern struct nouveau_oclass *nv05_devinit_oclass;
-extern struct nouveau_oclass *nv10_devinit_oclass;
-extern struct nouveau_oclass *nv1a_devinit_oclass;
-extern struct nouveau_oclass *nv20_devinit_oclass;
-extern struct nouveau_oclass *nv50_devinit_oclass;
-extern struct nouveau_oclass *nv84_devinit_oclass;
-extern struct nouveau_oclass *nv98_devinit_oclass;
-extern struct nouveau_oclass *nva3_devinit_oclass;
-extern struct nouveau_oclass *nvaf_devinit_oclass;
-extern struct nouveau_oclass *nvc0_devinit_oclass;
-extern struct nouveau_oclass *gm107_devinit_oclass;
-extern struct nouveau_oclass *gm204_devinit_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
deleted file mode 100644
index 8d0032f15205..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
+++ /dev/null
@@ -1,159 +0,0 @@
-#ifndef __NOUVEAU_FB_H__
-#define __NOUVEAU_FB_H__
-
-#include <core/subdev.h>
-#include <core/device.h>
-#include <core/mm.h>
-
-#include <subdev/vm.h>
-
-/* memory type/access flags, do not match hardware values */
-#define NV_MEM_ACCESS_RO  1
-#define NV_MEM_ACCESS_WO  2
-#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
-#define NV_MEM_ACCESS_SYS 4
-#define NV_MEM_ACCESS_VM  8
-#define NV_MEM_ACCESS_NOSNOOP 16
-
-#define NV_MEM_TARGET_VRAM        0
-#define NV_MEM_TARGET_PCI         1
-#define NV_MEM_TARGET_PCI_NOSNOOP 2
-#define NV_MEM_TARGET_VM          3
-#define NV_MEM_TARGET_GART        4
-
-#define NV_MEM_TYPE_VM 0x7f
-#define NV_MEM_COMP_VM 0x03
-
-struct nouveau_mem {
-	struct drm_device *dev;
-
-	struct nouveau_vma bar_vma;
-	struct nouveau_vma vma[2];
-	u8  page_shift;
-
-	struct nouveau_mm_node *tag;
-	struct list_head regions;
-	dma_addr_t *pages;
-	u32 memtype;
-	u64 offset;
-	u64 size;
-	struct sg_table *sg;
-};
-
-struct nouveau_fb_tile {
-	struct nouveau_mm_node *tag;
-	u32 addr;
-	u32 limit;
-	u32 pitch;
-	u32 zcomp;
-};
-
-struct nouveau_fb {
-	struct nouveau_subdev base;
-
-	bool (*memtype_valid)(struct nouveau_fb *, u32 memtype);
-
-	struct nouveau_ram *ram;
-
-	struct nouveau_mm vram;
-	struct nouveau_mm tags;
-
-	struct {
-		struct nouveau_fb_tile region[16];
-		int regions;
-		void (*init)(struct nouveau_fb *, int i, u32 addr, u32 size,
-			     u32 pitch, u32 flags, struct nouveau_fb_tile *);
-		void (*comp)(struct nouveau_fb *, int i, u32 size, u32 flags,
-			     struct nouveau_fb_tile *);
-		void (*fini)(struct nouveau_fb *, int i,
-			     struct nouveau_fb_tile *);
-		void (*prog)(struct nouveau_fb *, int i,
-			     struct nouveau_fb_tile *);
-	} tile;
-};
-
-static inline struct nouveau_fb *
-nouveau_fb(void *obj)
-{
-	/* fbram uses this before device subdev pointer is valid */
-	if (nv_iclass(obj, NV_SUBDEV_CLASS) &&
-	    nv_subidx(obj) == NVDEV_SUBDEV_FB)
-		return obj;
-
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_FB];
-}
-
-extern struct nouveau_oclass *nv04_fb_oclass;
-extern struct nouveau_oclass *nv10_fb_oclass;
-extern struct nouveau_oclass *nv1a_fb_oclass;
-extern struct nouveau_oclass *nv20_fb_oclass;
-extern struct nouveau_oclass *nv25_fb_oclass;
-extern struct nouveau_oclass *nv30_fb_oclass;
-extern struct nouveau_oclass *nv35_fb_oclass;
-extern struct nouveau_oclass *nv36_fb_oclass;
-extern struct nouveau_oclass *nv40_fb_oclass;
-extern struct nouveau_oclass *nv41_fb_oclass;
-extern struct nouveau_oclass *nv44_fb_oclass;
-extern struct nouveau_oclass *nv46_fb_oclass;
-extern struct nouveau_oclass *nv47_fb_oclass;
-extern struct nouveau_oclass *nv49_fb_oclass;
-extern struct nouveau_oclass *nv4e_fb_oclass;
-extern struct nouveau_oclass *nv50_fb_oclass;
-extern struct nouveau_oclass *nv84_fb_oclass;
-extern struct nouveau_oclass *nva3_fb_oclass;
-extern struct nouveau_oclass *nvaa_fb_oclass;
-extern struct nouveau_oclass *nvaf_fb_oclass;
-extern struct nouveau_oclass *nvc0_fb_oclass;
-extern struct nouveau_oclass *nve0_fb_oclass;
-extern struct nouveau_oclass *gk20a_fb_oclass;
-extern struct nouveau_oclass *gm107_fb_oclass;
-
-#include <subdev/bios/ramcfg.h>
-
-struct nouveau_ram_data {
-	struct list_head head;
-	struct nvbios_ramcfg bios;
-	u32 freq;
-};
-
-struct nouveau_ram {
-	struct nouveau_object base;
-	enum {
-		NV_MEM_TYPE_UNKNOWN = 0,
-		NV_MEM_TYPE_STOLEN,
-		NV_MEM_TYPE_SGRAM,
-		NV_MEM_TYPE_SDRAM,
-		NV_MEM_TYPE_DDR1,
-		NV_MEM_TYPE_DDR2,
-		NV_MEM_TYPE_DDR3,
-		NV_MEM_TYPE_GDDR2,
-		NV_MEM_TYPE_GDDR3,
-		NV_MEM_TYPE_GDDR4,
-		NV_MEM_TYPE_GDDR5
-	} type;
-	u64 stolen;
-	u64 size;
-	u32 tags;
-
-	int ranks;
-	int parts;
-	int part_mask;
-
-	int  (*get)(struct nouveau_fb *, u64 size, u32 align,
-		    u32 size_nc, u32 type, struct nouveau_mem **);
-	void (*put)(struct nouveau_fb *, struct nouveau_mem **);
-
-	int  (*calc)(struct nouveau_fb *, u32 freq);
-	int  (*prog)(struct nouveau_fb *);
-	void (*tidy)(struct nouveau_fb *);
-	u32 freq;
-	u32 mr[16];
-	u32 mr1_nuts;
-
-	struct nouveau_ram_data *next;
-	struct nouveau_ram_data former;
-	struct nouveau_ram_data xition;
-	struct nouveau_ram_data target;
-};
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fb/regsnv04.h b/drivers/gpu/drm/nouveau/core/include/subdev/fb/regsnv04.h
deleted file mode 100644
index 0f7fc0c52ab2..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/fb/regsnv04.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef __NOUVEAU_FB_REGS_04_H__
-#define __NOUVEAU_FB_REGS_04_H__
-
-#define NV04_PFB_BOOT_0						0x00100000
-#	define NV04_PFB_BOOT_0_RAM_AMOUNT			0x00000003
-#	define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB			0x00000000
-#	define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB			0x00000001
-#	define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB			0x00000002
-#	define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB			0x00000003
-#	define NV04_PFB_BOOT_0_RAM_WIDTH_128			0x00000004
-#	define NV04_PFB_BOOT_0_RAM_TYPE				0x00000028
-#	define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT		0x00000000
-#	define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT		0x00000008
-#	define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK	0x00000010
-#	define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT		0x00000018
-#	define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT		0x00000020
-#	define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16		0x00000028
-#	define NV04_PFB_BOOT_0_UMA_ENABLE			0x00000100
-#	define NV04_PFB_BOOT_0_UMA_SIZE				0x0000f000
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fuse.h b/drivers/gpu/drm/nouveau/core/include/subdev/fuse.h
deleted file mode 100644
index 2b1ddb2a9a7d..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/fuse.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef __NOUVEAU_FUSE_H__
-#define __NOUVEAU_FUSE_H__
-
-#include <core/subdev.h>
-#include <core/device.h>
-
-struct nouveau_fuse {
-	struct nouveau_subdev base;
-};
-
-static inline struct nouveau_fuse *
-nouveau_fuse(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_FUSE];
-}
-
-#define nouveau_fuse_create(p, e, o, d)                                        \
-	nouveau_fuse_create_((p), (e), (o), sizeof(**d), (void **)d)
-
-int  nouveau_fuse_create_(struct nouveau_object *, struct nouveau_object *,
-			  struct nouveau_oclass *, int, void **);
-void _nouveau_fuse_dtor(struct nouveau_object *);
-int  _nouveau_fuse_init(struct nouveau_object *);
-#define _nouveau_fuse_fini _nouveau_subdev_fini
-
-extern struct nouveau_oclass g80_fuse_oclass;
-extern struct nouveau_oclass gf100_fuse_oclass;
-extern struct nouveau_oclass gm107_fuse_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h b/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h
deleted file mode 100644
index f855140dbcb7..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef __NOUVEAU_GPIO_H__
-#define __NOUVEAU_GPIO_H__
-
-#include <core/subdev.h>
-#include <core/device.h>
-#include <core/event.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/gpio.h>
-
-struct nvkm_gpio_ntfy_req {
-#define NVKM_GPIO_HI                                                       0x01
-#define NVKM_GPIO_LO                                                       0x02
-#define NVKM_GPIO_TOGGLED                                                  0x03
-	u8 mask;
-	u8 line;
-};
-
-struct nvkm_gpio_ntfy_rep {
-	u8 mask;
-};
-
-struct nouveau_gpio {
-	struct nouveau_subdev base;
-
-	struct nvkm_event event;
-
-	void (*reset)(struct nouveau_gpio *, u8 func);
-	int  (*find)(struct nouveau_gpio *, int idx, u8 tag, u8 line,
-		     struct dcb_gpio_func *);
-	int  (*set)(struct nouveau_gpio *, int idx, u8 tag, u8 line, int state);
-	int  (*get)(struct nouveau_gpio *, int idx, u8 tag, u8 line);
-};
-
-static inline struct nouveau_gpio *
-nouveau_gpio(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_GPIO];
-}
-
-extern struct nouveau_oclass *nv10_gpio_oclass;
-extern struct nouveau_oclass *nv50_gpio_oclass;
-extern struct nouveau_oclass *nv94_gpio_oclass;
-extern struct nouveau_oclass *nvd0_gpio_oclass;
-extern struct nouveau_oclass *nve0_gpio_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h b/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h
deleted file mode 100644
index d94ccacb40bf..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h
+++ /dev/null
@@ -1,136 +0,0 @@
-#ifndef __NOUVEAU_I2C_H__
-#define __NOUVEAU_I2C_H__
-
-#include <core/subdev.h>
-#include <core/device.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/i2c.h>
-
-#define NV_I2C_PORT(n)    (0x00 + (n))
-#define NV_I2C_AUX(n)     (0x10 + (n))
-#define NV_I2C_EXT(n)     (0x20 + (n))
-#define NV_I2C_DEFAULT(n) (0x80 + (n))
-
-#define NV_I2C_TYPE_DCBI2C(n) (0x0000 | (n))
-#define NV_I2C_TYPE_EXTDDC(e) (0x0005 | (e) << 8)
-#define NV_I2C_TYPE_EXTAUX(e) (0x0006 | (e) << 8)
-
-struct nvkm_i2c_ntfy_req {
-#define NVKM_I2C_PLUG                                                      0x01
-#define NVKM_I2C_UNPLUG                                                    0x02
-#define NVKM_I2C_IRQ                                                       0x04
-#define NVKM_I2C_DONE                                                      0x08
-#define NVKM_I2C_ANY                                                       0x0f
-	u8 mask;
-	u8 port;
-};
-
-struct nvkm_i2c_ntfy_rep {
-	u8 mask;
-};
-
-struct nouveau_i2c_port {
-	struct nouveau_object base;
-	struct i2c_adapter adapter;
-	struct mutex mutex;
-
-	struct list_head head;
-	u8  index;
-	int aux;
-
-	const struct nouveau_i2c_func *func;
-};
-
-struct nouveau_i2c_func {
-	void (*drive_scl)(struct nouveau_i2c_port *, int);
-	void (*drive_sda)(struct nouveau_i2c_port *, int);
-	int  (*sense_scl)(struct nouveau_i2c_port *);
-	int  (*sense_sda)(struct nouveau_i2c_port *);
-
-	int  (*aux)(struct nouveau_i2c_port *, bool, u8, u32, u8 *, u8);
-	int  (*pattern)(struct nouveau_i2c_port *, int pattern);
-	int  (*lnk_ctl)(struct nouveau_i2c_port *, int nr, int bw, bool enh);
-	int  (*drv_ctl)(struct nouveau_i2c_port *, int lane, int sw, int pe);
-};
-
-struct nouveau_i2c_board_info {
-	struct i2c_board_info dev;
-	u8 udelay; /* set to 0 to use the standard delay */
-};
-
-struct nouveau_i2c {
-	struct nouveau_subdev base;
-	struct nvkm_event event;
-
-	struct nouveau_i2c_port *(*find)(struct nouveau_i2c *, u8 index);
-	struct nouveau_i2c_port *(*find_type)(struct nouveau_i2c *, u16 type);
-	int  (*acquire_pad)(struct nouveau_i2c_port *, unsigned long timeout);
-	void (*release_pad)(struct nouveau_i2c_port *);
-	int  (*acquire)(struct nouveau_i2c_port *, unsigned long timeout);
-	void (*release)(struct nouveau_i2c_port *);
-	int (*identify)(struct nouveau_i2c *, int index,
-			const char *what, struct nouveau_i2c_board_info *,
-			bool (*match)(struct nouveau_i2c_port *,
-				      struct i2c_board_info *, void *), void *);
-
-	wait_queue_head_t wait;
-	struct list_head ports;
-};
-
-static inline struct nouveau_i2c *
-nouveau_i2c(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_I2C];
-}
-
-extern struct nouveau_oclass *nv04_i2c_oclass;
-extern struct nouveau_oclass *nv4e_i2c_oclass;
-extern struct nouveau_oclass *nv50_i2c_oclass;
-extern struct nouveau_oclass *nv94_i2c_oclass;
-extern struct nouveau_oclass *nvd0_i2c_oclass;
-extern struct nouveau_oclass *gf117_i2c_oclass;
-extern struct nouveau_oclass *nve0_i2c_oclass;
-extern struct nouveau_oclass *gm204_i2c_oclass;
-
-static inline int
-nv_rdi2cr(struct nouveau_i2c_port *port, u8 addr, u8 reg)
-{
-	u8 val;
-	struct i2c_msg msgs[] = {
-		{ .addr = addr, .flags = 0, .len = 1, .buf = &reg },
-		{ .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = &val },
-	};
-
-	int ret = i2c_transfer(&port->adapter, msgs, 2);
-	if (ret != 2)
-		return -EIO;
-
-	return val;
-}
-
-static inline int
-nv_wri2cr(struct nouveau_i2c_port *port, u8 addr, u8 reg, u8 val)
-{
-	u8 buf[2] = { reg, val };
-	struct i2c_msg msgs[] = {
-		{ .addr = addr, .flags = 0, .len = 2, .buf = buf },
-	};
-
-	int ret = i2c_transfer(&port->adapter, msgs, 1);
-	if (ret != 1)
-		return -EIO;
-
-	return 0;
-}
-
-static inline bool
-nv_probe_i2c(struct nouveau_i2c_port *port, u8 addr)
-{
-	return nv_rdi2cr(port, addr, 0) >= 0;
-}
-
-int nv_rdaux(struct nouveau_i2c_port *, u32 addr, u8 *data, u8 size);
-int nv_wraux(struct nouveau_i2c_port *, u32 addr, u8 *data, u8 size);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/ibus.h b/drivers/gpu/drm/nouveau/core/include/subdev/ibus.h
deleted file mode 100644
index 31df634c0fdc..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/ibus.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef __NOUVEAU_IBUS_H__
-#define __NOUVEAU_IBUS_H__
-
-#include <core/subdev.h>
-#include <core/device.h>
-
-struct nouveau_ibus {
-	struct nouveau_subdev base;
-};
-
-static inline struct nouveau_ibus *
-nouveau_ibus(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_IBUS];
-}
-
-#define nouveau_ibus_create(p,e,o,d)                                           \
-	nouveau_subdev_create_((p), (e), (o), 0, "PIBUS", "ibus",              \
-			       sizeof(**d), (void **)d)
-#define nouveau_ibus_destroy(p)                                                \
-	nouveau_subdev_destroy(&(p)->base)
-#define nouveau_ibus_init(p)                                                   \
-	nouveau_subdev_init(&(p)->base)
-#define nouveau_ibus_fini(p,s)                                                 \
-	nouveau_subdev_fini(&(p)->base, (s))
-
-#define _nouveau_ibus_dtor _nouveau_subdev_dtor
-#define _nouveau_ibus_init _nouveau_subdev_init
-#define _nouveau_ibus_fini _nouveau_subdev_fini
-
-extern struct nouveau_oclass nvc0_ibus_oclass;
-extern struct nouveau_oclass nve0_ibus_oclass;
-extern struct nouveau_oclass gk20a_ibus_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h b/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h
deleted file mode 100644
index c1df26f3230c..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#ifndef __NOUVEAU_INSTMEM_H__
-#define __NOUVEAU_INSTMEM_H__
-
-#include <core/subdev.h>
-#include <core/device.h>
-#include <core/mm.h>
-
-struct nouveau_instobj {
-	struct nouveau_object base;
-	struct list_head head;
-	u32 *suspend;
-	u64 addr;
-	u32 size;
-};
-
-static inline struct nouveau_instobj *
-nv_memobj(void *obj)
-{
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
-	if (unlikely(!nv_iclass(obj, NV_MEMOBJ_CLASS)))
-		nv_assert("BAD CAST -> NvMemObj, %08x", nv_hclass(obj));
-#endif
-	return obj;
-}
-
-struct nouveau_instmem {
-	struct nouveau_subdev base;
-	struct list_head list;
-
-	u32 reserved;
-	int (*alloc)(struct nouveau_instmem *, struct nouveau_object *,
-		     u32 size, u32 align, struct nouveau_object **);
-};
-
-static inline struct nouveau_instmem *
-nouveau_instmem(void *obj)
-{
-	/* nv04/nv40 impls need to create objects in their constructor,
-	 * which is before the subdev pointer is valid
-	 */
-	if (nv_iclass(obj, NV_SUBDEV_CLASS) &&
-	    nv_subidx(obj) == NVDEV_SUBDEV_INSTMEM)
-		return obj;
-
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_INSTMEM];
-}
-
-extern struct nouveau_oclass *nv04_instmem_oclass;
-extern struct nouveau_oclass *nv40_instmem_oclass;
-extern struct nouveau_oclass *nv50_instmem_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/ltc.h b/drivers/gpu/drm/nouveau/core/include/subdev/ltc.h
deleted file mode 100644
index b909a7363f6b..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/ltc.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef __NOUVEAU_LTC_H__
-#define __NOUVEAU_LTC_H__
-
-#include <core/subdev.h>
-#include <core/device.h>
-
-#define NOUVEAU_LTC_MAX_ZBC_CNT 16
-
-struct nouveau_mm_node;
-
-struct nouveau_ltc {
-	struct nouveau_subdev base;
-
-	int  (*tags_alloc)(struct nouveau_ltc *, u32 count,
-	                   struct nouveau_mm_node **);
-	void (*tags_free)(struct nouveau_ltc *, struct nouveau_mm_node **);
-	void (*tags_clear)(struct nouveau_ltc *, u32 first, u32 count);
-
-	int zbc_min;
-	int zbc_max;
-	int (*zbc_color_get)(struct nouveau_ltc *, int index, const u32[4]);
-	int (*zbc_depth_get)(struct nouveau_ltc *, int index, const u32);
-};
-
-static inline struct nouveau_ltc *
-nouveau_ltc(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_LTC];
-}
-
-extern struct nouveau_oclass *gf100_ltc_oclass;
-extern struct nouveau_oclass *gk104_ltc_oclass;
-extern struct nouveau_oclass *gm107_ltc_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/mc.h b/drivers/gpu/drm/nouveau/core/include/subdev/mc.h
deleted file mode 100644
index 568e4dfc5e9e..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/mc.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef __NOUVEAU_MC_H__
-#define __NOUVEAU_MC_H__
-
-#include <core/subdev.h>
-#include <core/device.h>
-
-struct nouveau_mc {
-	struct nouveau_subdev base;
-	bool use_msi;
-	unsigned int irq;
-	void (*unk260)(struct nouveau_mc *, u32);
-};
-
-static inline struct nouveau_mc *
-nouveau_mc(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_MC];
-}
-
-extern struct nouveau_oclass *nv04_mc_oclass;
-extern struct nouveau_oclass *nv40_mc_oclass;
-extern struct nouveau_oclass *nv44_mc_oclass;
-extern struct nouveau_oclass *nv4c_mc_oclass;
-extern struct nouveau_oclass *nv50_mc_oclass;
-extern struct nouveau_oclass *nv94_mc_oclass;
-extern struct nouveau_oclass *nv98_mc_oclass;
-extern struct nouveau_oclass *nvc0_mc_oclass;
-extern struct nouveau_oclass *nvc3_mc_oclass;
-extern struct nouveau_oclass *gk20a_mc_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/mxm.h b/drivers/gpu/drm/nouveau/core/include/subdev/mxm.h
deleted file mode 100644
index b93b152cb566..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/mxm.h
+++ /dev/null
@@ -1,37 +0,0 @@
-#ifndef __NOUVEAU_MXM_H__
-#define __NOUVEAU_MXM_H__
-
-#include <core/subdev.h>
-#include <core/device.h>
-
-#define MXM_SANITISE_DCB 0x00000001
-
-struct nouveau_mxm {
-	struct nouveau_subdev base;
-	u32 action;
-	u8 *mxms;
-};
-
-static inline struct nouveau_mxm *
-nouveau_mxm(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_MXM];
-}
-
-#define nouveau_mxm_create(p,e,o,d)                                            \
-	nouveau_mxm_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_mxm_init(p)                                                    \
-	nouveau_subdev_init(&(p)->base)
-#define nouveau_mxm_fini(p,s)                                                  \
-	nouveau_subdev_fini(&(p)->base, (s))
-int  nouveau_mxm_create_(struct nouveau_object *, struct nouveau_object *,
-			 struct nouveau_oclass *, int, void **);
-void nouveau_mxm_destroy(struct nouveau_mxm *);
-
-#define _nouveau_mxm_dtor _nouveau_subdev_dtor
-#define _nouveau_mxm_init _nouveau_subdev_init
-#define _nouveau_mxm_fini _nouveau_subdev_fini
-
-extern struct nouveau_oclass nv50_mxm_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
deleted file mode 100644
index f2427bf5aeed..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
+++ /dev/null
@@ -1,56 +0,0 @@
-#ifndef __NOUVEAU_PWR_H__
-#define __NOUVEAU_PWR_H__
-
-#include <core/subdev.h>
-#include <core/device.h>
-
-struct nouveau_pwr {
-	struct nouveau_subdev base;
-
-	struct {
-		u32 base;
-		u32 size;
-	} send;
-
-	struct {
-		u32 base;
-		u32 size;
-
-		struct work_struct work;
-		wait_queue_head_t wait;
-		u32 process;
-		u32 message;
-		u32 data[2];
-	} recv;
-
-	int  (*message)(struct nouveau_pwr *, u32[2], u32, u32, u32, u32);
-	void (*pgob)(struct nouveau_pwr *, bool);
-};
-
-static inline struct nouveau_pwr *
-nouveau_pwr(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_PWR];
-}
-
-extern struct nouveau_oclass *nva3_pwr_oclass;
-extern struct nouveau_oclass *nvc0_pwr_oclass;
-extern struct nouveau_oclass *nvd0_pwr_oclass;
-extern struct nouveau_oclass *gk104_pwr_oclass;
-extern struct nouveau_oclass *nv108_pwr_oclass;
-
-/* interface to MEMX process running on PPWR */
-struct nouveau_memx;
-int  nouveau_memx_init(struct nouveau_pwr *, struct nouveau_memx **);
-int  nouveau_memx_fini(struct nouveau_memx **, bool exec);
-void nouveau_memx_wr32(struct nouveau_memx *, u32 addr, u32 data);
-void nouveau_memx_wait(struct nouveau_memx *,
-		       u32 addr, u32 mask, u32 data, u32 nsec);
-void nouveau_memx_nsec(struct nouveau_memx *, u32 nsec);
-void nouveau_memx_wait_vblank(struct nouveau_memx *);
-void nouveau_memx_train(struct nouveau_memx *);
-int  nouveau_memx_train_result(struct nouveau_pwr *, u32 *, int);
-void nouveau_memx_block(struct nouveau_memx *);
-void nouveau_memx_unblock(struct nouveau_memx *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/therm.h b/drivers/gpu/drm/nouveau/core/include/subdev/therm.h
deleted file mode 100644
index a437597dcafc..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/therm.h
+++ /dev/null
@@ -1,83 +0,0 @@
-#ifndef __NOUVEAU_THERM_H__
-#define __NOUVEAU_THERM_H__
-
-#include <core/device.h>
-#include <core/subdev.h>
-
-enum nouveau_therm_fan_mode {
-	NOUVEAU_THERM_CTRL_NONE = 0,
-	NOUVEAU_THERM_CTRL_MANUAL = 1,
-	NOUVEAU_THERM_CTRL_AUTO = 2,
-};
-
-enum nouveau_therm_attr_type {
-	NOUVEAU_THERM_ATTR_FAN_MIN_DUTY = 0,
-	NOUVEAU_THERM_ATTR_FAN_MAX_DUTY = 1,
-	NOUVEAU_THERM_ATTR_FAN_MODE = 2,
-
-	NOUVEAU_THERM_ATTR_THRS_FAN_BOOST = 10,
-	NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST = 11,
-	NOUVEAU_THERM_ATTR_THRS_DOWN_CLK = 12,
-	NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST = 13,
-	NOUVEAU_THERM_ATTR_THRS_CRITICAL = 14,
-	NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST = 15,
-	NOUVEAU_THERM_ATTR_THRS_SHUTDOWN = 16,
-	NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST = 17,
-};
-
-struct nouveau_therm {
-	struct nouveau_subdev base;
-
-	int (*pwm_ctrl)(struct nouveau_therm *, int line, bool);
-	int (*pwm_get)(struct nouveau_therm *, int line, u32 *, u32 *);
-	int (*pwm_set)(struct nouveau_therm *, int line, u32, u32);
-	int (*pwm_clock)(struct nouveau_therm *, int line);
-
-	int (*fan_get)(struct nouveau_therm *);
-	int (*fan_set)(struct nouveau_therm *, int);
-	int (*fan_sense)(struct nouveau_therm *);
-
-	int (*temp_get)(struct nouveau_therm *);
-
-	int (*attr_get)(struct nouveau_therm *, enum nouveau_therm_attr_type);
-	int (*attr_set)(struct nouveau_therm *,
-			enum nouveau_therm_attr_type, int);
-};
-
-static inline struct nouveau_therm *
-nouveau_therm(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_THERM];
-}
-
-#define nouveau_therm_create(p,e,o,d)                                          \
-	nouveau_therm_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_therm_destroy(p) ({                                            \
-	struct nouveau_therm *therm = (p);                                     \
-        _nouveau_therm_dtor(nv_object(therm));                                 \
-})
-#define nouveau_therm_init(p) ({                                               \
-	struct nouveau_therm *therm = (p);                                     \
-        _nouveau_therm_init(nv_object(therm));                                 \
-})
-#define nouveau_therm_fini(p,s) ({                                             \
-	struct nouveau_therm *therm = (p);                                     \
-        _nouveau_therm_init(nv_object(therm), (s));                            \
-})
-
-int  nouveau_therm_create_(struct nouveau_object *, struct nouveau_object *,
-			   struct nouveau_oclass *, int, void **);
-void _nouveau_therm_dtor(struct nouveau_object *);
-int  _nouveau_therm_init(struct nouveau_object *);
-int  _nouveau_therm_fini(struct nouveau_object *, bool);
-
-int  nouveau_therm_cstate(struct nouveau_therm *, int, int);
-
-extern struct nouveau_oclass nv40_therm_oclass;
-extern struct nouveau_oclass nv50_therm_oclass;
-extern struct nouveau_oclass nv84_therm_oclass;
-extern struct nouveau_oclass nva3_therm_oclass;
-extern struct nouveau_oclass nvd0_therm_oclass;
-extern struct nouveau_oclass gm107_therm_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/timer.h b/drivers/gpu/drm/nouveau/core/include/subdev/timer.h
deleted file mode 100644
index db9be803a874..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/timer.h
+++ /dev/null
@@ -1,64 +0,0 @@
-#ifndef __NOUVEAU_TIMER_H__
-#define __NOUVEAU_TIMER_H__
-
-#include <core/subdev.h>
-#include <core/device.h>
-
-struct nouveau_alarm {
-	struct list_head head;
-	u64 timestamp;
-	void (*func)(struct nouveau_alarm *);
-};
-
-static inline void
-nouveau_alarm_init(struct nouveau_alarm *alarm,
-		   void (*func)(struct nouveau_alarm *))
-{
-	INIT_LIST_HEAD(&alarm->head);
-	alarm->func = func;
-}
-
-bool nouveau_timer_wait_eq(void *, u64 nsec, u32 addr, u32 mask, u32 data);
-bool nouveau_timer_wait_ne(void *, u64 nsec, u32 addr, u32 mask, u32 data);
-bool nouveau_timer_wait_cb(void *, u64 nsec, bool (*func)(void *), void *data);
-void nouveau_timer_alarm(void *, u32 nsec, struct nouveau_alarm *);
-void nouveau_timer_alarm_cancel(void *, struct nouveau_alarm *);
-
-#define NV_WAIT_DEFAULT 2000000000ULL
-#define nv_wait(o,a,m,v)                                                       \
-	nouveau_timer_wait_eq((o), NV_WAIT_DEFAULT, (a), (m), (v))
-#define nv_wait_ne(o,a,m,v)                                                    \
-	nouveau_timer_wait_ne((o), NV_WAIT_DEFAULT, (a), (m), (v))
-#define nv_wait_cb(o,c,d)                                                      \
-	nouveau_timer_wait_cb((o), NV_WAIT_DEFAULT, (c), (d))
-
-struct nouveau_timer {
-	struct nouveau_subdev base;
-	u64  (*read)(struct nouveau_timer *);
-	void (*alarm)(struct nouveau_timer *, u64 time, struct nouveau_alarm *);
-	void (*alarm_cancel)(struct nouveau_timer *, struct nouveau_alarm *);
-};
-
-static inline struct nouveau_timer *
-nouveau_timer(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_TIMER];
-}
-
-#define nouveau_timer_create(p,e,o,d)                                          \
-	nouveau_subdev_create_((p), (e), (o), 0, "PTIMER", "timer",            \
-			       sizeof(**d), (void **)d)
-#define nouveau_timer_destroy(p)                                               \
-	nouveau_subdev_destroy(&(p)->base)
-#define nouveau_timer_init(p)                                                  \
-	nouveau_subdev_init(&(p)->base)
-#define nouveau_timer_fini(p,s)                                                \
-	nouveau_subdev_fini(&(p)->base, (s))
-
-int nouveau_timer_create_(struct nouveau_object *, struct nouveau_engine *,
-			  struct nouveau_oclass *, int size, void **);
-
-extern struct nouveau_oclass nv04_timer_oclass;
-extern struct nouveau_oclass gk20a_timer_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/vga.h b/drivers/gpu/drm/nouveau/core/include/subdev/vga.h
deleted file mode 100644
index fee09ad818e4..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/vga.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef __NOUVEAU_VGA_H__
-#define __NOUVEAU_VGA_H__
-
-#include <core/os.h>
-
-/* access to various legacy io ports */
-u8   nv_rdport(void *obj, int head, u16 port);
-void nv_wrport(void *obj, int head, u16 port, u8 value);
-
-/* VGA Sequencer */
-u8   nv_rdvgas(void *obj, int head, u8 index);
-void nv_wrvgas(void *obj, int head, u8 index, u8 value);
-
-/* VGA Graphics */
-u8   nv_rdvgag(void *obj, int head, u8 index);
-void nv_wrvgag(void *obj, int head, u8 index, u8 value);
-
-/* VGA CRTC */
-u8   nv_rdvgac(void *obj, int head, u8 index);
-void nv_wrvgac(void *obj, int head, u8 index, u8 value);
-
-/* VGA indexed port access dispatcher */
-u8   nv_rdvgai(void *obj, int head, u16 port, u8 index);
-void nv_wrvgai(void *obj, int head, u16 port, u8 index, u8 value);
-
-bool nv_lockvgac(void *obj, bool lock);
-u8   nv_rdvgaowner(void *obj);
-void nv_wrvgaowner(void *obj, u8);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/vm.h b/drivers/gpu/drm/nouveau/core/include/subdev/vm.h
deleted file mode 100644
index c9509039f94b..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/vm.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Copyright 2010 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#ifndef __NOUVEAU_VM_H__
-#define __NOUVEAU_VM_H__
-
-#include <core/object.h>
-#include <core/subdev.h>
-#include <core/device.h>
-#include <core/mm.h>
-
-struct nouveau_vm_pgt {
-	struct nouveau_gpuobj *obj[2];
-	u32 refcount[2];
-};
-
-struct nouveau_vm_pgd {
-	struct list_head head;
-	struct nouveau_gpuobj *obj;
-};
-
-struct nouveau_gpuobj;
-struct nouveau_mem;
-
-struct nouveau_vma {
-	struct list_head head;
-	int refcount;
-	struct nouveau_vm *vm;
-	struct nouveau_mm_node *node;
-	u64 offset;
-	u32 access;
-};
-
-struct nouveau_vm {
-	struct nouveau_vmmgr *vmm;
-	struct nouveau_mm mm;
-	struct kref refcount;
-
-	struct list_head pgd_list;
-	atomic_t engref[NVDEV_SUBDEV_NR];
-
-	struct nouveau_vm_pgt *pgt;
-	u32 fpde;
-	u32 lpde;
-};
-
-struct nouveau_vmmgr {
-	struct nouveau_subdev base;
-
-	u64 limit;
-	u8  dma_bits;
-	u32 pgt_bits;
-	u8  spg_shift;
-	u8  lpg_shift;
-
-	int  (*create)(struct nouveau_vmmgr *, u64 offset, u64 length,
-		       u64 mm_offset, struct nouveau_vm **);
-
-	void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde,
-			struct nouveau_gpuobj *pgt[2]);
-	void (*map)(struct nouveau_vma *, struct nouveau_gpuobj *,
-		    struct nouveau_mem *, u32 pte, u32 cnt,
-		    u64 phys, u64 delta);
-	void (*map_sg)(struct nouveau_vma *, struct nouveau_gpuobj *,
-		       struct nouveau_mem *, u32 pte, u32 cnt, dma_addr_t *);
-	void (*unmap)(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt);
-	void (*flush)(struct nouveau_vm *);
-};
-
-static inline struct nouveau_vmmgr *
-nouveau_vmmgr(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_VM];
-}
-
-#define nouveau_vmmgr_create(p,e,o,i,f,d)                                      \
-	nouveau_subdev_create((p), (e), (o), 0, (i), (f), (d))
-#define nouveau_vmmgr_destroy(p)                                               \
-	nouveau_subdev_destroy(&(p)->base)
-#define nouveau_vmmgr_init(p)                                                  \
-	nouveau_subdev_init(&(p)->base)
-#define nouveau_vmmgr_fini(p,s)                                                \
-	nouveau_subdev_fini(&(p)->base, (s))
-
-#define _nouveau_vmmgr_dtor _nouveau_subdev_dtor
-#define _nouveau_vmmgr_init _nouveau_subdev_init
-#define _nouveau_vmmgr_fini _nouveau_subdev_fini
-
-extern struct nouveau_oclass nv04_vmmgr_oclass;
-extern struct nouveau_oclass nv41_vmmgr_oclass;
-extern struct nouveau_oclass nv44_vmmgr_oclass;
-extern struct nouveau_oclass nv50_vmmgr_oclass;
-extern struct nouveau_oclass nvc0_vmmgr_oclass;
-
-int  nv04_vm_create(struct nouveau_vmmgr *, u64, u64, u64,
-		    struct nouveau_vm **);
-void nv04_vmmgr_dtor(struct nouveau_object *);
-
-/* nouveau_vm.c */
-int  nouveau_vm_create(struct nouveau_vmmgr *, u64 offset, u64 length,
-		       u64 mm_offset, u32 block, struct nouveau_vm **);
-int  nouveau_vm_new(struct nouveau_device *, u64 offset, u64 length,
-		    u64 mm_offset, struct nouveau_vm **);
-int  nouveau_vm_ref(struct nouveau_vm *, struct nouveau_vm **,
-		    struct nouveau_gpuobj *pgd);
-int  nouveau_vm_get(struct nouveau_vm *, u64 size, u32 page_shift,
-		    u32 access, struct nouveau_vma *);
-void nouveau_vm_put(struct nouveau_vma *);
-void nouveau_vm_map(struct nouveau_vma *, struct nouveau_mem *);
-void nouveau_vm_map_at(struct nouveau_vma *, u64 offset, struct nouveau_mem *);
-void nouveau_vm_unmap(struct nouveau_vma *);
-void nouveau_vm_unmap_at(struct nouveau_vma *, u64 offset, u64 length);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/volt.h b/drivers/gpu/drm/nouveau/core/include/subdev/volt.h
deleted file mode 100644
index 67db5e58880d..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/volt.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef __NOUVEAU_VOLT_H__
-#define __NOUVEAU_VOLT_H__
-
-#include <core/subdev.h>
-#include <core/device.h>
-
-struct nouveau_voltage {
-	u32 uv;
-	u8  id;
-};
-
-struct nouveau_volt {
-	struct nouveau_subdev base;
-
-	int (*vid_get)(struct nouveau_volt *);
-	int (*get)(struct nouveau_volt *);
-	int (*vid_set)(struct nouveau_volt *, u8 vid);
-	int (*set)(struct nouveau_volt *, u32 uv);
-	int (*set_id)(struct nouveau_volt *, u8 id, int condition);
-
-	u8 vid_mask;
-	u8 vid_nr;
-	struct {
-		u32 uv;
-		u8 vid;
-	} vid[256];
-};
-
-static inline struct nouveau_volt *
-nouveau_volt(void *obj)
-{
-	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_VOLT];
-}
-
-#define nouveau_volt_create(p, e, o, d)                                        \
-	nouveau_volt_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_volt_destroy(p) ({                                             \
-	struct nouveau_volt *v = (p);                                          \
-	_nouveau_volt_dtor(nv_object(v));                                      \
-})
-#define nouveau_volt_init(p) ({                                                \
-	struct nouveau_volt *v = (p);                                          \
-	_nouveau_volt_init(nv_object(v));                                      \
-})
-#define nouveau_volt_fini(p,s)                                                 \
-	nouveau_subdev_fini((p), (s))
-
-int  nouveau_volt_create_(struct nouveau_object *, struct nouveau_object *,
-			  struct nouveau_oclass *, int, void **);
-void _nouveau_volt_dtor(struct nouveau_object *);
-int  _nouveau_volt_init(struct nouveau_object *);
-#define _nouveau_volt_fini _nouveau_subdev_fini
-
-extern struct nouveau_oclass nv40_volt_oclass;
-extern struct nouveau_oclass gk20a_volt_oclass;
-
-int nouveau_voltgpio_init(struct nouveau_volt *);
-int nouveau_voltgpio_get(struct nouveau_volt *);
-int nouveau_voltgpio_set(struct nouveau_volt *, u8);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/os.h b/drivers/gpu/drm/nouveau/core/os.h
deleted file mode 100644
index bdd05ee7ec72..000000000000
--- a/drivers/gpu/drm/nouveau/core/os.h
+++ /dev/null
@@ -1,44 +0,0 @@
-#ifndef __NOUVEAU_OS_H__
-#define __NOUVEAU_OS_H__
-
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/mutex.h>
-#include <linux/pci.h>
-#include <linux/platform_device.h>
-#include <linux/printk.h>
-#include <linux/bitops.h>
-#include <linux/firmware.h>
-#include <linux/module.h>
-#include <linux/i2c.h>
-#include <linux/i2c-algo-bit.h>
-#include <linux/delay.h>
-#include <linux/io-mapping.h>
-#include <linux/acpi.h>
-#include <linux/vmalloc.h>
-#include <linux/dmi.h>
-#include <linux/reboot.h>
-#include <linux/interrupt.h>
-#include <linux/log2.h>
-#include <linux/pm_runtime.h>
-#include <linux/power_supply.h>
-#include <linux/clk.h>
-#include <linux/regulator/consumer.h>
-
-#include <asm/unaligned.h>
-
-#ifndef ioread32_native
-#ifdef __BIG_ENDIAN
-#define ioread16_native ioread16be
-#define iowrite16_native iowrite16be
-#define ioread32_native  ioread32be
-#define iowrite32_native iowrite32be
-#else /* def __BIG_ENDIAN */
-#define ioread16_native ioread16
-#define iowrite16_native iowrite16
-#define ioread32_native  ioread32
-#define iowrite32_native iowrite32
-#endif /* def __BIG_ENDIAN else */
-#endif /* !ioread32_native */
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c b/drivers/gpu/drm/nouveau/core/subdev/bar/base.c
deleted file mode 100644
index b1adc69efd88..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/object.h>
-
-#include <subdev/fb.h>
-#include <subdev/vm.h>
-
-#include "priv.h"
-
-struct nouveau_barobj {
-	struct nouveau_object base;
-	struct nouveau_vma vma;
-	void __iomem *iomem;
-};
-
-static int
-nouveau_barobj_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
-{
-	struct nouveau_device *device = nv_device(parent);
-	struct nouveau_bar *bar = (void *)engine;
-	struct nouveau_mem *mem = data;
-	struct nouveau_barobj *barobj;
-	int ret;
-
-	ret = nouveau_object_create(parent, engine, oclass, 0, &barobj);
-	*pobject = nv_object(barobj);
-	if (ret)
-		return ret;
-
-	ret = bar->kmap(bar, mem, NV_MEM_ACCESS_RW, &barobj->vma);
-	if (ret)
-		return ret;
-
-	barobj->iomem = ioremap(nv_device_resource_start(device, 3) +
-				(u32)barobj->vma.offset, mem->size << 12);
-	if (!barobj->iomem) {
-		nv_warn(bar, "PRAMIN ioremap failed\n");
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-static void
-nouveau_barobj_dtor(struct nouveau_object *object)
-{
-	struct nouveau_bar *bar = (void *)object->engine;
-	struct nouveau_barobj *barobj = (void *)object;
-	if (barobj->vma.node) {
-		if (barobj->iomem)
-			iounmap(barobj->iomem);
-		bar->unmap(bar, &barobj->vma);
-	}
-	nouveau_object_destroy(&barobj->base);
-}
-
-static u32
-nouveau_barobj_rd32(struct nouveau_object *object, u64 addr)
-{
-	struct nouveau_barobj *barobj = (void *)object;
-	return ioread32_native(barobj->iomem + addr);
-}
-
-static void
-nouveau_barobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
-{
-	struct nouveau_barobj *barobj = (void *)object;
-	iowrite32_native(data, barobj->iomem + addr);
-}
-
-static struct nouveau_oclass
-nouveau_barobj_oclass = {
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nouveau_barobj_ctor,
-		.dtor = nouveau_barobj_dtor,
-		.init = nouveau_object_init,
-		.fini = nouveau_object_fini,
-		.rd32 = nouveau_barobj_rd32,
-		.wr32 = nouveau_barobj_wr32,
-	},
-};
-
-int
-nouveau_bar_alloc(struct nouveau_bar *bar, struct nouveau_object *parent,
-		  struct nouveau_mem *mem, struct nouveau_object **pobject)
-{
-	struct nouveau_object *engine = nv_object(bar);
-	struct nouveau_object *gpuobj;
-	int ret = nouveau_object_ctor(parent, engine, &nouveau_barobj_oclass,
-				      mem, 0, &gpuobj);
-	if (ret == 0)
-		*pobject = gpuobj;
-	return ret;
-}
-
-int
-nouveau_bar_create_(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, int length, void **pobject)
-{
-	struct nouveau_bar *bar;
-	int ret;
-
-	ret = nouveau_subdev_create_(parent, engine, oclass, 0, "BARCTL",
-				     "bar", length, pobject);
-	bar = *pobject;
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-void
-nouveau_bar_destroy(struct nouveau_bar *bar)
-{
-	nouveau_subdev_destroy(&bar->base);
-}
-
-void
-_nouveau_bar_dtor(struct nouveau_object *object)
-{
-	struct nouveau_bar *bar = (void *)object;
-	nouveau_bar_destroy(bar);
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/bar/gk20a.c
deleted file mode 100644
index bf877af9d3bd..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bar/gk20a.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include <subdev/bar.h>
-
-#include "priv.h"
-
-int
-gk20a_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nouveau_bar *bar;
-	int ret;
-
-	ret = nvc0_bar_ctor(parent, engine, oclass, data, size, pobject);
-	if (ret)
-		return ret;
-
-	bar = (struct nouveau_bar *)*pobject;
-	bar->iomap_uncached = true;
-
-	return 0;
-}
-
-struct nouveau_oclass
-gk20a_bar_oclass = {
-	.handle = NV_SUBDEV(BAR, 0xea),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = gk20a_bar_ctor,
-		.dtor = nvc0_bar_dtor,
-		.init = nvc0_bar_init,
-		.fini = _nouveau_bar_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c
deleted file mode 100644
index f748ba49dfc8..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/gpuobj.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <subdev/vm.h>
-
-#include "priv.h"
-
-struct nv50_bar_priv {
-	struct nouveau_bar base;
-	spinlock_t lock;
-	struct nouveau_gpuobj *mem;
-	struct nouveau_gpuobj *pad;
-	struct nouveau_gpuobj *pgd;
-	struct nouveau_vm *bar1_vm;
-	struct nouveau_gpuobj *bar1;
-	struct nouveau_vm *bar3_vm;
-	struct nouveau_gpuobj *bar3;
-};
-
-static int
-nv50_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem,
-	      u32 flags, struct nouveau_vma *vma)
-{
-	struct nv50_bar_priv *priv = (void *)bar;
-	int ret;
-
-	ret = nouveau_vm_get(priv->bar3_vm, mem->size << 12, 12, flags, vma);
-	if (ret)
-		return ret;
-
-	nouveau_vm_map(vma, mem);
-	return 0;
-}
-
-static int
-nv50_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem,
-	      u32 flags, struct nouveau_vma *vma)
-{
-	struct nv50_bar_priv *priv = (void *)bar;
-	int ret;
-
-	ret = nouveau_vm_get(priv->bar1_vm, mem->size << 12, 12, flags, vma);
-	if (ret)
-		return ret;
-
-	nouveau_vm_map(vma, mem);
-	return 0;
-}
-
-static void
-nv50_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma)
-{
-	nouveau_vm_unmap(vma);
-	nouveau_vm_put(vma);
-}
-
-static void
-nv50_bar_flush(struct nouveau_bar *bar)
-{
-	struct nv50_bar_priv *priv = (void *)bar;
-	unsigned long flags;
-	spin_lock_irqsave(&priv->lock, flags);
-	nv_wr32(priv, 0x00330c, 0x00000001);
-	if (!nv_wait(priv, 0x00330c, 0x00000002, 0x00000000))
-		nv_warn(priv, "flush timeout\n");
-	spin_unlock_irqrestore(&priv->lock, flags);
-}
-
-void
-nv84_bar_flush(struct nouveau_bar *bar)
-{
-	struct nv50_bar_priv *priv = (void *)bar;
-	unsigned long flags;
-	spin_lock_irqsave(&priv->lock, flags);
-	nv_wr32(bar, 0x070000, 0x00000001);
-	if (!nv_wait(priv, 0x070000, 0x00000002, 0x00000000))
-		nv_warn(priv, "flush timeout\n");
-	spin_unlock_irqrestore(&priv->lock, flags);
-}
-
-static int
-nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 size,
-	      struct nouveau_object **pobject)
-{
-	struct nouveau_device *device = nv_device(parent);
-	struct nouveau_object *heap;
-	struct nouveau_vm *vm;
-	struct nv50_bar_priv *priv;
-	u64 start, limit;
-	int ret;
-
-	ret = nouveau_bar_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x20000, 0,
-				 NVOBJ_FLAG_HEAP, &priv->mem);
-	heap = nv_object(priv->mem);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), heap,
-				(device->chipset == 0x50) ? 0x1400 : 0x0200,
-				 0, 0, &priv->pad);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), heap, 0x4000, 0,
-				 0, &priv->pgd);
-	if (ret)
-		return ret;
-
-	/* BAR3 */
-	start = 0x0100000000ULL;
-	limit = start + nv_device_resource_len(device, 3);
-
-	ret = nouveau_vm_new(device, start, limit, start, &vm);
-	if (ret)
-		return ret;
-
-	atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
-
-	ret = nouveau_gpuobj_new(nv_object(priv), heap,
-				 ((limit-- - start) >> 12) * 8, 0x1000,
-				 NVOBJ_FLAG_ZERO_ALLOC, &vm->pgt[0].obj[0]);
-	vm->pgt[0].refcount[0] = 1;
-	if (ret)
-		return ret;
-
-	ret = nouveau_vm_ref(vm, &priv->bar3_vm, priv->pgd);
-	nouveau_vm_ref(NULL, &vm, NULL);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar3);
-	if (ret)
-		return ret;
-
-	nv_wo32(priv->bar3, 0x00, 0x7fc00000);
-	nv_wo32(priv->bar3, 0x04, lower_32_bits(limit));
-	nv_wo32(priv->bar3, 0x08, lower_32_bits(start));
-	nv_wo32(priv->bar3, 0x0c, upper_32_bits(limit) << 24 |
-				  upper_32_bits(start));
-	nv_wo32(priv->bar3, 0x10, 0x00000000);
-	nv_wo32(priv->bar3, 0x14, 0x00000000);
-
-	/* BAR1 */
-	start = 0x0000000000ULL;
-	limit = start + nv_device_resource_len(device, 1);
-
-	ret = nouveau_vm_new(device, start, limit--, start, &vm);
-	if (ret)
-		return ret;
-
-	atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
-
-	ret = nouveau_vm_ref(vm, &priv->bar1_vm, priv->pgd);
-	nouveau_vm_ref(NULL, &vm, NULL);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar1);
-	if (ret)
-		return ret;
-
-	nv_wo32(priv->bar1, 0x00, 0x7fc00000);
-	nv_wo32(priv->bar1, 0x04, lower_32_bits(limit));
-	nv_wo32(priv->bar1, 0x08, lower_32_bits(start));
-	nv_wo32(priv->bar1, 0x0c, upper_32_bits(limit) << 24 |
-				  upper_32_bits(start));
-	nv_wo32(priv->bar1, 0x10, 0x00000000);
-	nv_wo32(priv->bar1, 0x14, 0x00000000);
-
-	priv->base.alloc = nouveau_bar_alloc;
-	priv->base.kmap = nv50_bar_kmap;
-	priv->base.umap = nv50_bar_umap;
-	priv->base.unmap = nv50_bar_unmap;
-	if (device->chipset == 0x50)
-		priv->base.flush = nv50_bar_flush;
-	else
-		priv->base.flush = nv84_bar_flush;
-	spin_lock_init(&priv->lock);
-	return 0;
-}
-
-static void
-nv50_bar_dtor(struct nouveau_object *object)
-{
-	struct nv50_bar_priv *priv = (void *)object;
-	nouveau_gpuobj_ref(NULL, &priv->bar1);
-	nouveau_vm_ref(NULL, &priv->bar1_vm, priv->pgd);
-	nouveau_gpuobj_ref(NULL, &priv->bar3);
-	if (priv->bar3_vm) {
-		nouveau_gpuobj_ref(NULL, &priv->bar3_vm->pgt[0].obj[0]);
-		nouveau_vm_ref(NULL, &priv->bar3_vm, priv->pgd);
-	}
-	nouveau_gpuobj_ref(NULL, &priv->pgd);
-	nouveau_gpuobj_ref(NULL, &priv->pad);
-	nouveau_gpuobj_ref(NULL, &priv->mem);
-	nouveau_bar_destroy(&priv->base);
-}
-
-static int
-nv50_bar_init(struct nouveau_object *object)
-{
-	struct nv50_bar_priv *priv = (void *)object;
-	int ret, i;
-
-	ret = nouveau_bar_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
-	nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
-	nv_wr32(priv, 0x100c80, 0x00060001);
-	if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) {
-		nv_error(priv, "vm flush timeout\n");
-		return -EBUSY;
-	}
-
-	nv_wr32(priv, 0x001704, 0x00000000 | priv->mem->addr >> 12);
-	nv_wr32(priv, 0x001704, 0x40000000 | priv->mem->addr >> 12);
-	nv_wr32(priv, 0x001708, 0x80000000 | priv->bar1->node->offset >> 4);
-	nv_wr32(priv, 0x00170c, 0x80000000 | priv->bar3->node->offset >> 4);
-	for (i = 0; i < 8; i++)
-		nv_wr32(priv, 0x001900 + (i * 4), 0x00000000);
-	return 0;
-}
-
-static int
-nv50_bar_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv50_bar_priv *priv = (void *)object;
-	return nouveau_bar_fini(&priv->base, suspend);
-}
-
-struct nouveau_oclass
-nv50_bar_oclass = {
-	.handle = NV_SUBDEV(BAR, 0x50),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_bar_ctor,
-		.dtor = nv50_bar_dtor,
-		.init = nv50_bar_init,
-		.fini = nv50_bar_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
deleted file mode 100644
index 05a278bab247..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/gpuobj.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <subdev/vm.h>
-
-#include "priv.h"
-
-struct nvc0_bar_priv_vm {
-	struct nouveau_gpuobj *mem;
-	struct nouveau_gpuobj *pgd;
-	struct nouveau_vm *vm;
-};
-
-struct nvc0_bar_priv {
-	struct nouveau_bar base;
-	spinlock_t lock;
-	struct nvc0_bar_priv_vm bar[2];
-};
-
-static int
-nvc0_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem,
-	      u32 flags, struct nouveau_vma *vma)
-{
-	struct nvc0_bar_priv *priv = (void *)bar;
-	int ret;
-
-	ret = nouveau_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma);
-	if (ret)
-		return ret;
-
-	nouveau_vm_map(vma, mem);
-	return 0;
-}
-
-static int
-nvc0_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem,
-	      u32 flags, struct nouveau_vma *vma)
-{
-	struct nvc0_bar_priv *priv = (void *)bar;
-	int ret;
-
-	ret = nouveau_vm_get(priv->bar[1].vm, mem->size << 12,
-			     mem->page_shift, flags, vma);
-	if (ret)
-		return ret;
-
-	nouveau_vm_map(vma, mem);
-	return 0;
-}
-
-static void
-nvc0_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma)
-{
-	nouveau_vm_unmap(vma);
-	nouveau_vm_put(vma);
-}
-
-static int
-nvc0_bar_init_vm(struct nvc0_bar_priv *priv, struct nvc0_bar_priv_vm *bar_vm,
-		 int bar_nr)
-{
-	struct nouveau_device *device = nv_device(&priv->base);
-	struct nouveau_vm *vm;
-	resource_size_t bar_len;
-	int ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0,
-				&bar_vm->mem);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0,
-				&bar_vm->pgd);
-	if (ret)
-		return ret;
-
-	bar_len = nv_device_resource_len(device, bar_nr);
-
-	ret = nouveau_vm_new(device, 0, bar_len, 0, &vm);
-	if (ret)
-		return ret;
-
-	atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
-
-	/*
-	 * Bootstrap page table lookup.
-	 */
-	if (bar_nr == 3) {
-		ret = nouveau_gpuobj_new(nv_object(priv), NULL,
-					 (bar_len >> 12) * 8, 0x1000,
-					 NVOBJ_FLAG_ZERO_ALLOC,
-					&vm->pgt[0].obj[0]);
-		vm->pgt[0].refcount[0] = 1;
-		if (ret)
-			return ret;
-	}
-
-	ret = nouveau_vm_ref(vm, &bar_vm->vm, bar_vm->pgd);
-	nouveau_vm_ref(NULL, &vm, NULL);
-	if (ret)
-		return ret;
-
-	nv_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr));
-	nv_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr));
-	nv_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1));
-	nv_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1));
-
-	return 0;
-}
-
-int
-nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 size,
-	      struct nouveau_object **pobject)
-{
-	struct nouveau_device *device = nv_device(parent);
-	struct nvc0_bar_priv *priv;
-	bool has_bar3 = nv_device_resource_len(device, 3) != 0;
-	int ret;
-
-	ret = nouveau_bar_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	/* BAR3 */
-	if (has_bar3) {
-		ret = nvc0_bar_init_vm(priv, &priv->bar[0], 3);
-		if (ret)
-			return ret;
-		priv->base.alloc = nouveau_bar_alloc;
-		priv->base.kmap = nvc0_bar_kmap;
-	}
-
-	/* BAR1 */
-	ret = nvc0_bar_init_vm(priv, &priv->bar[1], 1);
-	if (ret)
-		return ret;
-
-	priv->base.umap = nvc0_bar_umap;
-	priv->base.unmap = nvc0_bar_unmap;
-	priv->base.flush = nv84_bar_flush;
-	spin_lock_init(&priv->lock);
-	return 0;
-}
-
-void
-nvc0_bar_dtor(struct nouveau_object *object)
-{
-	struct nvc0_bar_priv *priv = (void *)object;
-
-	nouveau_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd);
-	nouveau_gpuobj_ref(NULL, &priv->bar[1].pgd);
-	nouveau_gpuobj_ref(NULL, &priv->bar[1].mem);
-
-	if (priv->bar[0].vm) {
-		nouveau_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]);
-		nouveau_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd);
-	}
-	nouveau_gpuobj_ref(NULL, &priv->bar[0].pgd);
-	nouveau_gpuobj_ref(NULL, &priv->bar[0].mem);
-
-	nouveau_bar_destroy(&priv->base);
-}
-
-int
-nvc0_bar_init(struct nouveau_object *object)
-{
-	struct nvc0_bar_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_bar_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
-	nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
-
-	nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12);
-	if (priv->bar[0].mem)
-		nv_wr32(priv, 0x001714,
-			0xc0000000 | priv->bar[0].mem->addr >> 12);
-	return 0;
-}
-
-struct nouveau_oclass
-nvc0_bar_oclass = {
-	.handle = NV_SUBDEV(BAR, 0xc0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_bar_ctor,
-		.dtor = nvc0_bar_dtor,
-		.init = nvc0_bar_init,
-		.fini = _nouveau_bar_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/priv.h b/drivers/gpu/drm/nouveau/core/subdev/bar/priv.h
deleted file mode 100644
index 3ee8b1476d00..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bar/priv.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef __NVKM_BAR_PRIV_H__
-#define __NVKM_BAR_PRIV_H__
-
-#include <subdev/bar.h>
-
-#define nouveau_bar_create(p,e,o,d)                                            \
-	nouveau_bar_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_bar_init(p)                                                    \
-	nouveau_subdev_init(&(p)->base)
-#define nouveau_bar_fini(p,s)                                                  \
-	nouveau_subdev_fini(&(p)->base, (s))
-
-int nouveau_bar_create_(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, int, void **);
-void nouveau_bar_destroy(struct nouveau_bar *);
-
-void _nouveau_bar_dtor(struct nouveau_object *);
-#define _nouveau_bar_init _nouveau_subdev_init
-#define _nouveau_bar_fini _nouveau_subdev_fini
-
-int  nouveau_bar_alloc(struct nouveau_bar *, struct nouveau_object *,
-		       struct nouveau_mem *, struct nouveau_object **);
-
-void nv84_bar_flush(struct nouveau_bar *);
-
-int nvc0_bar_ctor(struct nouveau_object *, struct nouveau_object *,
-		  struct nouveau_oclass *, void *, u32,
-		  struct nouveau_object **);
-void nvc0_bar_dtor(struct nouveau_object *);
-int nvc0_bar_init(struct nouveau_object *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/M0203.c b/drivers/gpu/drm/nouveau/core/subdev/bios/M0203.c
deleted file mode 100644
index 28906b16d4e5..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/M0203.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/M0203.h>
-
-u32
-nvbios_M0203Te(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	struct bit_entry bit_M;
-	u32 data = 0x00000000;
-
-	if (!bit_entry(bios, 'M', &bit_M)) {
-		if (bit_M.version == 2 && bit_M.length > 0x04)
-			data = nv_ro16(bios, bit_M.offset + 0x03);
-		if (data) {
-			*ver = nv_ro08(bios, data + 0x00);
-			switch (*ver) {
-			case 0x10:
-				*hdr = nv_ro08(bios, data + 0x01);
-				*len = nv_ro08(bios, data + 0x02);
-				*cnt = nv_ro08(bios, data + 0x03);
-				return data;
-			default:
-				break;
-			}
-		}
-	}
-
-	return 0x00000000;
-}
-
-u32
-nvbios_M0203Tp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-	       struct nvbios_M0203T *info)
-{
-	u32 data = nvbios_M0203Te(bios, ver, hdr, cnt, len);
-	memset(info, 0x00, sizeof(*info));
-	switch (!!data * *ver) {
-	case 0x10:
-		info->type    = nv_ro08(bios, data + 0x04);
-		info->pointer = nv_ro16(bios, data + 0x05);
-		break;
-	default:
-		break;
-	}
-	return data;
-}
-
-u32
-nvbios_M0203Ee(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr)
-{
-	u8  cnt, len;
-	u32 data = nvbios_M0203Te(bios, ver, hdr, &cnt, &len);
-	if (data && idx < cnt) {
-		data = data + *hdr + idx * len;
-		*hdr = len;
-		return data;
-	}
-	return 0x00000000;
-}
-
-u32
-nvbios_M0203Ep(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
-	       struct nvbios_M0203E *info)
-{
-	u32 data = nvbios_M0203Ee(bios, idx, ver, hdr);
-	memset(info, 0x00, sizeof(*info));
-	switch (!!data * *ver) {
-	case 0x10:
-		info->type  = (nv_ro08(bios, data + 0x00) & 0x0f) >> 0;
-		info->strap = (nv_ro08(bios, data + 0x00) & 0xf0) >> 4;
-		info->group = (nv_ro08(bios, data + 0x01) & 0x0f) >> 0;
-		return data;
-	default:
-		break;
-	}
-	return 0x00000000;
-}
-
-u32
-nvbios_M0203Em(struct nouveau_bios *bios, u8 ramcfg, u8 *ver, u8 *hdr,
-	       struct nvbios_M0203E *info)
-{
-	struct nvbios_M0203T M0203T;
-	u8  cnt, len, idx = 0xff;
-	u32 data;
-
-	if (!nvbios_M0203Tp(bios, ver, hdr, &cnt, &len, &M0203T)) {
-		nv_warn(bios, "M0203T not found\n");
-		return 0x00000000;
-	}
-
-	while ((data = nvbios_M0203Ep(bios, ++idx, ver, hdr, info))) {
-		switch (M0203T.type) {
-		case M0203T_TYPE_RAMCFG:
-			if (info->strap != ramcfg)
-				continue;
-			return data;
-		default:
-			nv_warn(bios, "M0203T type %02x\n", M0203T.type);
-			return 0x00000000;
-		}
-	}
-
-	return data;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/M0205.c b/drivers/gpu/drm/nouveau/core/subdev/bios/M0205.c
deleted file mode 100644
index ac9617c5fc2a..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/M0205.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/M0205.h>
-
-u32
-nvbios_M0205Te(struct nouveau_bios *bios,
-	       u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
-{
-	struct bit_entry bit_M;
-	u32 data = 0x00000000;
-
-	if (!bit_entry(bios, 'M', &bit_M)) {
-		if (bit_M.version == 2 && bit_M.length > 0x08)
-			data = nv_ro32(bios, bit_M.offset + 0x05);
-		if (data) {
-			*ver = nv_ro08(bios, data + 0x00);
-			switch (*ver) {
-			case 0x10:
-				*hdr = nv_ro08(bios, data + 0x01);
-				*len = nv_ro08(bios, data + 0x02);
-				*ssz = nv_ro08(bios, data + 0x03);
-				*snr = nv_ro08(bios, data + 0x04);
-				*cnt = nv_ro08(bios, data + 0x05);
-				return data;
-			default:
-				break;
-			}
-		}
-	}
-
-	return 0x00000000;
-}
-
-u32
-nvbios_M0205Tp(struct nouveau_bios *bios,
-	       u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz,
-	       struct nvbios_M0205T *info)
-{
-	u32 data = nvbios_M0205Te(bios, ver, hdr, cnt, len, snr, ssz);
-	memset(info, 0x00, sizeof(*info));
-	switch (!!data * *ver) {
-	case 0x10:
-		info->freq = nv_ro16(bios, data + 0x06);
-		break;
-	default:
-		break;
-	}
-	return data;
-}
-
-u32
-nvbios_M0205Ee(struct nouveau_bios *bios, int idx,
-	       u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	u8  snr, ssz;
-	u32 data = nvbios_M0205Te(bios, ver, hdr, cnt, len, &snr, &ssz);
-	if (data && idx < *cnt) {
-		data = data + *hdr + idx * (*len + (snr * ssz));
-		*hdr = *len;
-		*cnt = snr;
-		*len = ssz;
-		return data;
-	}
-	return 0x00000000;
-}
-
-u32
-nvbios_M0205Ep(struct nouveau_bios *bios, int idx,
-	       u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-	       struct nvbios_M0205E *info)
-{
-	u32 data = nvbios_M0205Ee(bios, idx, ver, hdr, cnt, len);
-	memset(info, 0x00, sizeof(*info));
-	switch (!!data * *ver) {
-	case 0x10:
-		info->type = nv_ro08(bios, data + 0x00) & 0x0f;
-		return data;
-	default:
-		break;
-	}
-	return 0x00000000;
-}
-
-u32
-nvbios_M0205Se(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr)
-{
-
-	u8  cnt, len;
-	u32 data = nvbios_M0205Ee(bios, ent, ver, hdr, &cnt, &len);
-	if (data && idx < cnt) {
-		data = data + *hdr + idx * len;
-		*hdr = len;
-		return data;
-	}
-	return 0x00000000;
-}
-
-u32
-nvbios_M0205Sp(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr,
-	       struct nvbios_M0205S *info)
-{
-	u32 data = nvbios_M0205Se(bios, ent, idx, ver, hdr);
-	memset(info, 0x00, sizeof(*info));
-	switch (!!data * *ver) {
-	case 0x10:
-		info->data = nv_ro08(bios, data + 0x00);
-		return data;
-	default:
-		break;
-	}
-	return 0x00000000;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/M0209.c b/drivers/gpu/drm/nouveau/core/subdev/bios/M0209.c
deleted file mode 100644
index b142a510e89f..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/M0209.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/M0209.h>
-
-u32
-nvbios_M0209Te(struct nouveau_bios *bios,
-	       u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
-{
-	struct bit_entry bit_M;
-	u32 data = 0x00000000;
-
-	if (!bit_entry(bios, 'M', &bit_M)) {
-		if (bit_M.version == 2 && bit_M.length > 0x0c)
-			data = nv_ro32(bios, bit_M.offset + 0x09);
-		if (data) {
-			*ver = nv_ro08(bios, data + 0x00);
-			switch (*ver) {
-			case 0x10:
-				*hdr = nv_ro08(bios, data + 0x01);
-				*len = nv_ro08(bios, data + 0x02);
-				*ssz = nv_ro08(bios, data + 0x03);
-				*snr = 1;
-				*cnt = nv_ro08(bios, data + 0x04);
-				return data;
-			default:
-				break;
-			}
-		}
-	}
-
-	return 0x00000000;
-}
-
-u32
-nvbios_M0209Ee(struct nouveau_bios *bios, int idx,
-	       u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	u8  snr, ssz;
-	u32 data = nvbios_M0209Te(bios, ver, hdr, cnt, len, &snr, &ssz);
-	if (data && idx < *cnt) {
-		data = data + *hdr + idx * (*len + (snr * ssz));
-		*hdr = *len;
-		*cnt = snr;
-		*len = ssz;
-		return data;
-	}
-	return 0x00000000;
-}
-
-u32
-nvbios_M0209Ep(struct nouveau_bios *bios, int idx,
-	       u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-	       struct nvbios_M0209E *info)
-{
-	u32 data = nvbios_M0209Ee(bios, idx, ver, hdr, cnt, len);
-	memset(info, 0x00, sizeof(*info));
-	switch (!!data * *ver) {
-	case 0x10:
-		info->v00_40 = (nv_ro08(bios, data + 0x00) & 0x40) >> 6;
-		info->bits   =  nv_ro08(bios, data + 0x00) & 0x3f;
-		info->modulo =  nv_ro08(bios, data + 0x01);
-		info->v02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6;
-		info->v02_07 =  nv_ro08(bios, data + 0x02) & 0x07;
-		info->v03    =  nv_ro08(bios, data + 0x03);
-		return data;
-	default:
-		break;
-	}
-	return 0x00000000;
-}
-
-u32
-nvbios_M0209Se(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr)
-{
-
-	u8  cnt, len;
-	u32 data = nvbios_M0209Ee(bios, ent, ver, hdr, &cnt, &len);
-	if (data && idx < cnt) {
-		data = data + *hdr + idx * len;
-		*hdr = len;
-		return data;
-	}
-	return 0x00000000;
-}
-
-u32
-nvbios_M0209Sp(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr,
-	       struct nvbios_M0209S *info)
-{
-	struct nvbios_M0209E M0209E;
-	u8  cnt, len;
-	u32 data = nvbios_M0209Ep(bios, ent, ver, hdr, &cnt, &len, &M0209E);
-	if (data) {
-		u32 i, data = nvbios_M0209Se(bios, ent, idx, ver, hdr);
-		memset(info, 0x00, sizeof(*info));
-		switch (!!data * *ver) {
-		case 0x10:
-			for (i = 0; i < ARRAY_SIZE(info->data); i++) {
-				u32 bits = (i % M0209E.modulo) * M0209E.bits;
-				u32 mask = (1ULL << M0209E.bits) - 1;
-				u16  off = bits / 8;
-				u8   mod = bits % 8;
-				info->data[i] = nv_ro32(bios, data + off);
-				info->data[i] = info->data[i] >> mod;
-				info->data[i] = info->data[i] & mask;
-			}
-			return data;
-		default:
-			break;
-		}
-	}
-	return 0x00000000;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/P0260.c b/drivers/gpu/drm/nouveau/core/subdev/bios/P0260.c
deleted file mode 100644
index 199f4e5f7488..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/P0260.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/ramcfg.h>
-#include <subdev/bios/P0260.h>
-
-u32
-nvbios_P0260Te(struct nouveau_bios *bios,
-	       u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz)
-{
-	struct bit_entry bit_P;
-	u32 data = 0x00000000;
-
-	if (!bit_entry(bios, 'P', &bit_P)) {
-		if (bit_P.version == 2 && bit_P.length > 0x63)
-			data = nv_ro32(bios, bit_P.offset + 0x60);
-		if (data) {
-			*ver = nv_ro08(bios, data + 0);
-			switch (*ver) {
-			case 0x10:
-				*hdr = nv_ro08(bios, data + 1);
-				*cnt = nv_ro08(bios, data + 2);
-				*len = 4;
-				*xnr = nv_ro08(bios, data + 3);
-				*xsz = 4;
-				return data;
-			default:
-				break;
-			}
-		}
-	}
-
-	return 0x00000000;
-}
-
-u32
-nvbios_P0260Ee(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
-{
-	u8  hdr, cnt, xnr, xsz;
-	u32 data = nvbios_P0260Te(bios, ver, &hdr, &cnt, len, &xnr, &xsz);
-	if (data && idx < cnt)
-		return data + hdr + (idx * *len);
-	return 0x00000000;
-}
-
-u32
-nvbios_P0260Ep(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len,
-	       struct nvbios_P0260E *info)
-{
-	u32 data = nvbios_P0260Ee(bios, idx, ver, len);
-	memset(info, 0x00, sizeof(*info));
-	switch (!!data * *ver) {
-	case 0x10:
-		info->data = nv_ro32(bios, data);
-		return data;
-	default:
-		break;
-	}
-	return 0x00000000;
-}
-
-u32
-nvbios_P0260Xe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *xsz)
-{
-	u8  hdr, cnt, len, xnr;
-	u32 data = nvbios_P0260Te(bios, ver, &hdr, &cnt, &len, &xnr, xsz);
-	if (data && idx < xnr)
-		return data + hdr + (cnt * len) + (idx * *xsz);
-	return 0x00000000;
-}
-
-u32
-nvbios_P0260Xp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
-	       struct nvbios_P0260X *info)
-{
-	u32 data = nvbios_P0260Xe(bios, idx, ver, hdr);
-	memset(info, 0x00, sizeof(*info));
-	switch (!!data * *ver) {
-	case 0x10:
-		info->data = nv_ro32(bios, data);
-		return data;
-	default:
-		break;
-	}
-	return 0x00000000;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c b/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
deleted file mode 100644
index 7df3a273553d..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/object.h>
-#include <core/device.h>
-#include <core/subdev.h>
-#include <core/option.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/bmp.h>
-#include <subdev/bios/bit.h>
-
-#include "priv.h"
-
-u8
-nvbios_checksum(const u8 *data, int size)
-{
-	u8 sum = 0;
-	while (size--)
-		sum += *data++;
-	return sum;
-}
-
-u16
-nvbios_findstr(const u8 *data, int size, const char *str, int len)
-{
-	int i, j;
-
-	for (i = 0; i <= (size - len); i++) {
-		for (j = 0; j < len; j++)
-			if ((char)data[i + j] != str[j])
-				break;
-		if (j == len)
-			return i;
-	}
-
-	return 0;
-}
-
-int
-nvbios_extend(struct nouveau_bios *bios, u32 length)
-{
-	if (bios->size < length) {
-		u8 *prev = bios->data;
-		if (!(bios->data = kmalloc(length, GFP_KERNEL))) {
-			bios->data = prev;
-			return -ENOMEM;
-		}
-		memcpy(bios->data, prev, bios->size);
-		bios->size = length;
-		kfree(prev);
-		return 1;
-	}
-	return 0;
-}
-
-static u8
-nouveau_bios_rd08(struct nouveau_object *object, u64 addr)
-{
-	struct nouveau_bios *bios = (void *)object;
-	return bios->data[addr];
-}
-
-static u16
-nouveau_bios_rd16(struct nouveau_object *object, u64 addr)
-{
-	struct nouveau_bios *bios = (void *)object;
-	return get_unaligned_le16(&bios->data[addr]);
-}
-
-static u32
-nouveau_bios_rd32(struct nouveau_object *object, u64 addr)
-{
-	struct nouveau_bios *bios = (void *)object;
-	return get_unaligned_le32(&bios->data[addr]);
-}
-
-static void
-nouveau_bios_wr08(struct nouveau_object *object, u64 addr, u8 data)
-{
-	struct nouveau_bios *bios = (void *)object;
-	bios->data[addr] = data;
-}
-
-static void
-nouveau_bios_wr16(struct nouveau_object *object, u64 addr, u16 data)
-{
-	struct nouveau_bios *bios = (void *)object;
-	put_unaligned_le16(data, &bios->data[addr]);
-}
-
-static void
-nouveau_bios_wr32(struct nouveau_object *object, u64 addr, u32 data)
-{
-	struct nouveau_bios *bios = (void *)object;
-	put_unaligned_le32(data, &bios->data[addr]);
-}
-
-static int
-nouveau_bios_ctor(struct nouveau_object *parent,
-		  struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 size,
-		  struct nouveau_object **pobject)
-{
-	struct nouveau_bios *bios;
-	struct bit_entry bit_i;
-	int ret;
-
-	ret = nouveau_subdev_create(parent, engine, oclass, 0,
-				    "VBIOS", "bios", &bios);
-	*pobject = nv_object(bios);
-	if (ret)
-		return ret;
-
-	ret = nvbios_shadow(bios);
-	if (ret)
-		return ret;
-
-	/* detect type of vbios we're dealing with */
-	bios->bmp_offset = nvbios_findstr(bios->data, bios->size,
-					  "\xff\x7f""NV\0", 5);
-	if (bios->bmp_offset) {
-		nv_info(bios, "BMP version %x.%x\n",
-			bmp_version(bios) >> 8,
-			bmp_version(bios) & 0xff);
-	}
-
-	bios->bit_offset = nvbios_findstr(bios->data, bios->size,
-					  "\xff\xb8""BIT", 5);
-	if (bios->bit_offset)
-		nv_info(bios, "BIT signature found\n");
-
-	/* determine the vbios version number */
-	if (!bit_entry(bios, 'i', &bit_i) && bit_i.length >= 4) {
-		bios->version.major = nv_ro08(bios, bit_i.offset + 3);
-		bios->version.chip  = nv_ro08(bios, bit_i.offset + 2);
-		bios->version.minor = nv_ro08(bios, bit_i.offset + 1);
-		bios->version.micro = nv_ro08(bios, bit_i.offset + 0);
-		bios->version.patch = nv_ro08(bios, bit_i.offset + 4);
-	} else
-	if (bmp_version(bios)) {
-		bios->version.major = nv_ro08(bios, bios->bmp_offset + 13);
-		bios->version.chip  = nv_ro08(bios, bios->bmp_offset + 12);
-		bios->version.minor = nv_ro08(bios, bios->bmp_offset + 11);
-		bios->version.micro = nv_ro08(bios, bios->bmp_offset + 10);
-	}
-
-	nv_info(bios, "version %02x.%02x.%02x.%02x.%02x\n",
-		bios->version.major, bios->version.chip,
-		bios->version.minor, bios->version.micro, bios->version.patch);
-
-	return 0;
-}
-
-static void
-nouveau_bios_dtor(struct nouveau_object *object)
-{
-	struct nouveau_bios *bios = (void *)object;
-	kfree(bios->data);
-	nouveau_subdev_destroy(&bios->base);
-}
-
-static int
-nouveau_bios_init(struct nouveau_object *object)
-{
-	struct nouveau_bios *bios = (void *)object;
-	return nouveau_subdev_init(&bios->base);
-}
-
-static int
-nouveau_bios_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nouveau_bios *bios = (void *)object;
-	return nouveau_subdev_fini(&bios->base, suspend);
-}
-
-struct nouveau_oclass
-nouveau_bios_oclass = {
-	.handle = NV_SUBDEV(VBIOS, 0x00),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nouveau_bios_ctor,
-		.dtor = nouveau_bios_dtor,
-		.init = nouveau_bios_init,
-		.fini = nouveau_bios_fini,
-		.rd08 = nouveau_bios_rd08,
-		.rd16 = nouveau_bios_rd16,
-		.rd32 = nouveau_bios_rd32,
-		.wr08 = nouveau_bios_wr08,
-		.wr16 = nouveau_bios_wr16,
-		.wr32 = nouveau_bios_wr32,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/bit.c b/drivers/gpu/drm/nouveau/core/subdev/bios/bit.c
deleted file mode 100644
index 1d03a3f2b2d2..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/bit.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "core/object.h"
-
-#include "subdev/bios.h"
-#include "subdev/bios/bit.h"
-
-int
-bit_entry(struct nouveau_bios *bios, u8 id, struct bit_entry *bit)
-{
-	if (likely(bios->bit_offset)) {
-		u8  entries = nv_ro08(bios, bios->bit_offset + 10);
-		u32 entry   = bios->bit_offset + 12;
-		while (entries--) {
-			if (nv_ro08(bios, entry + 0) == id) {
-				bit->id      = nv_ro08(bios, entry + 0);
-				bit->version = nv_ro08(bios, entry + 1);
-				bit->length  = nv_ro16(bios, entry + 2);
-				bit->offset  = nv_ro16(bios, entry + 4);
-				return 0;
-			}
-
-			entry += nv_ro08(bios, bios->bit_offset + 9);
-		}
-
-		return -ENOENT;
-	}
-
-	return -EINVAL;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/boost.c b/drivers/gpu/drm/nouveau/core/subdev/bios/boost.c
deleted file mode 100644
index c1835e591c44..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/boost.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/boost.h>
-
-u16
-nvbios_boostTe(struct nouveau_bios *bios,
-	       u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
-{
-	struct bit_entry bit_P;
-	u16 boost = 0x0000;
-
-	if (!bit_entry(bios, 'P', &bit_P)) {
-		if (bit_P.version == 2)
-			boost = nv_ro16(bios, bit_P.offset + 0x30);
-
-		if (boost) {
-			*ver = nv_ro08(bios, boost + 0);
-			switch (*ver) {
-			case 0x11:
-				*hdr = nv_ro08(bios, boost + 1);
-				*cnt = nv_ro08(bios, boost + 5);
-				*len = nv_ro08(bios, boost + 2);
-				*snr = nv_ro08(bios, boost + 4);
-				*ssz = nv_ro08(bios, boost + 3);
-				return boost;
-			default:
-				break;
-			}
-		}
-	}
-
-	return 0x0000;
-}
-
-u16
-nvbios_boostEe(struct nouveau_bios *bios, int idx,
-	       u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	u8  snr, ssz;
-	u16 data = nvbios_boostTe(bios, ver, hdr, cnt, len, &snr, &ssz);
-	if (data && idx < *cnt) {
-		data = data + *hdr + (idx * (*len + (snr * ssz)));
-		*hdr = *len;
-		*cnt = snr;
-		*len = ssz;
-		return data;
-	}
-	return 0x0000;
-}
-
-u16
-nvbios_boostEp(struct nouveau_bios *bios, int idx,
-	       u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_boostE *info)
-{
-	u16 data = nvbios_boostEe(bios, idx, ver, hdr, cnt, len);
-	memset(info, 0x00, sizeof(*info));
-	if (data) {
-		info->pstate = (nv_ro16(bios, data + 0x00) & 0x01e0) >> 5;
-		info->min    =  nv_ro16(bios, data + 0x02) * 1000;
-		info->max    =  nv_ro16(bios, data + 0x04) * 1000;
-	}
-	return data;
-}
-
-u16
-nvbios_boostEm(struct nouveau_bios *bios, u8 pstate,
-	       u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_boostE *info)
-{
-	u32 data, idx = 0;
-	while ((data = nvbios_boostEp(bios, idx++, ver, hdr, cnt, len, info))) {
-		if (info->pstate == pstate)
-			break;
-	}
-	return data;
-}
-
-u16
-nvbios_boostSe(struct nouveau_bios *bios, int idx,
-	       u16 data, u8 *ver, u8 *hdr, u8 cnt, u8 len)
-{
-	if (data && idx < cnt) {
-		data = data + *hdr + (idx * len);
-		*hdr = len;
-		return data;
-	}
-	return 0x0000;
-}
-
-u16
-nvbios_boostSp(struct nouveau_bios *bios, int idx,
-	       u16 data, u8 *ver, u8 *hdr, u8 cnt, u8 len,
-	       struct nvbios_boostS *info)
-{
-	data = nvbios_boostSe(bios, idx, data, ver, hdr, cnt, len);
-	memset(info, 0x00, sizeof(*info));
-	if (data) {
-		info->domain  = nv_ro08(bios, data + 0x00);
-		info->percent = nv_ro08(bios, data + 0x01);
-		info->min     = nv_ro16(bios, data + 0x02) * 1000;
-		info->max     = nv_ro16(bios, data + 0x04) * 1000;
-	}
-	return data;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/conn.c b/drivers/gpu/drm/nouveau/core/subdev/bios/conn.c
deleted file mode 100644
index 2ede3bcd96a1..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/conn.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/device.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/conn.h>
-
-u32
-nvbios_connTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	u32 dcb = dcb_table(bios, ver, hdr, cnt, len);
-	if (dcb && *ver >= 0x30 && *hdr >= 0x16) {
-		u32 data = nv_ro16(bios, dcb + 0x14);
-		if (data) {
-			*ver = nv_ro08(bios, data + 0);
-			*hdr = nv_ro08(bios, data + 1);
-			*cnt = nv_ro08(bios, data + 2);
-			*len = nv_ro08(bios, data + 3);
-			return data;
-		}
-	}
-	return 0x00000000;
-}
-
-u32
-nvbios_connTp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-	      struct nvbios_connT *info)
-{
-	u32 data = nvbios_connTe(bios, ver, hdr, cnt, len);
-	memset(info, 0x00, sizeof(*info));
-	switch (!!data * *ver) {
-	case 0x30:
-	case 0x40:
-		return data;
-	default:
-		break;
-	}
-	return 0x00000000;
-}
-
-u32
-nvbios_connEe(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len)
-{
-	u8  hdr, cnt;
-	u32 data = nvbios_connTe(bios, ver, &hdr, &cnt, len);
-	if (data && idx < cnt)
-		return data + hdr + (idx * *len);
-	return 0x00000000;
-}
-
-u32
-nvbios_connEp(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len,
-	      struct nvbios_connE *info)
-{
-	u32 data = nvbios_connEe(bios, idx, ver, len);
-	memset(info, 0x00, sizeof(*info));
-	switch (!!data * *ver) {
-	case 0x30:
-	case 0x40:
-		info->type     =  nv_ro08(bios, data + 0x00);
-		info->location =  nv_ro08(bios, data + 0x01) & 0x0f;
-		info->hpd      = (nv_ro08(bios, data + 0x01) & 0x30) >> 4;
-		info->dp       = (nv_ro08(bios, data + 0x01) & 0xc0) >> 6;
-		if (*len < 4)
-			return data;
-		info->hpd     |= (nv_ro08(bios, data + 0x02) & 0x03) << 2;
-		info->dp      |=  nv_ro08(bios, data + 0x02) & 0x0c;
-		info->di       = (nv_ro08(bios, data + 0x02) & 0xf0) >> 4;
-		info->hpd     |= (nv_ro08(bios, data + 0x03) & 0x07) << 4;
-		info->sr       = (nv_ro08(bios, data + 0x03) & 0x08) >> 3;
-		info->lcdid    = (nv_ro08(bios, data + 0x03) & 0x70) >> 4;
-		return data;
-	default:
-		break;
-	}
-	return 0x00000000;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/cstep.c b/drivers/gpu/drm/nouveau/core/subdev/bios/cstep.c
deleted file mode 100644
index d3b15327fbfd..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/cstep.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/cstep.h>
-
-u16
-nvbios_cstepTe(struct nouveau_bios *bios,
-	       u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz)
-{
-	struct bit_entry bit_P;
-	u16 cstep = 0x0000;
-
-	if (!bit_entry(bios, 'P', &bit_P)) {
-		if (bit_P.version == 2)
-			cstep = nv_ro16(bios, bit_P.offset + 0x34);
-
-		if (cstep) {
-			*ver = nv_ro08(bios, cstep + 0);
-			switch (*ver) {
-			case 0x10:
-				*hdr = nv_ro08(bios, cstep + 1);
-				*cnt = nv_ro08(bios, cstep + 3);
-				*len = nv_ro08(bios, cstep + 2);
-				*xnr = nv_ro08(bios, cstep + 5);
-				*xsz = nv_ro08(bios, cstep + 4);
-				return cstep;
-			default:
-				break;
-			}
-		}
-	}
-
-	return 0x0000;
-}
-
-u16
-nvbios_cstepEe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr)
-{
-	u8  cnt, len, xnr, xsz;
-	u16 data = nvbios_cstepTe(bios, ver, hdr, &cnt, &len, &xnr, &xsz);
-	if (data && idx < cnt) {
-		data = data + *hdr + (idx * len);
-		*hdr = len;
-		return data;
-	}
-	return 0x0000;
-}
-
-u16
-nvbios_cstepEp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
-	       struct nvbios_cstepE *info)
-{
-	u16 data = nvbios_cstepEe(bios, idx, ver, hdr);
-	memset(info, 0x00, sizeof(*info));
-	if (data) {
-		info->pstate = (nv_ro16(bios, data + 0x00) & 0x01e0) >> 5;
-		info->index   = nv_ro08(bios, data + 0x03);
-	}
-	return data;
-}
-
-u16
-nvbios_cstepEm(struct nouveau_bios *bios, u8 pstate, u8 *ver, u8 *hdr,
-	       struct nvbios_cstepE *info)
-{
-	u32 data, idx = 0;
-	while ((data = nvbios_cstepEp(bios, idx++, ver, hdr, info))) {
-		if (info->pstate == pstate)
-			break;
-	}
-	return data;
-}
-
-u16
-nvbios_cstepXe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr)
-{
-	u8  cnt, len, xnr, xsz;
-	u16 data = nvbios_cstepTe(bios, ver, hdr, &cnt, &len, &xnr, &xsz);
-	if (data && idx < xnr) {
-		data = data + *hdr + (cnt * len) + (idx * xsz);
-		*hdr = xsz;
-		return data;
-	}
-	return 0x0000;
-}
-
-u16
-nvbios_cstepXp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
-	       struct nvbios_cstepX *info)
-{
-	u16 data = nvbios_cstepXe(bios, idx, ver, hdr);
-	memset(info, 0x00, sizeof(*info));
-	if (data) {
-		info->freq    = nv_ro16(bios, data + 0x00) * 1000;
-		info->unkn[0] = nv_ro08(bios, data + 0x02);
-		info->unkn[1] = nv_ro08(bios, data + 0x03);
-		info->voltage = nv_ro08(bios, data + 0x04);
-	}
-	return data;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c b/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c
deleted file mode 100644
index 96099aff8b41..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "core/device.h"
-
-#include "subdev/bios.h"
-#include "subdev/bios/dcb.h"
-
-u16
-dcb_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	struct nouveau_device *device = nv_device(bios);
-	u16 dcb = 0x0000;
-
-	if (device->card_type > NV_04)
-		dcb = nv_ro16(bios, 0x36);
-	if (!dcb) {
-		nv_warn(bios, "DCB table not found\n");
-		return dcb;
-	}
-
-	*ver = nv_ro08(bios, dcb);
-
-	if (*ver >= 0x42) {
-		nv_warn(bios, "DCB version 0x%02x unknown\n", *ver);
-		return 0x0000;
-	} else
-	if (*ver >= 0x30) {
-		if (nv_ro32(bios, dcb + 6) == 0x4edcbdcb) {
-			*hdr = nv_ro08(bios, dcb + 1);
-			*cnt = nv_ro08(bios, dcb + 2);
-			*len = nv_ro08(bios, dcb + 3);
-			return dcb;
-		}
-	} else
-	if (*ver >= 0x20) {
-		if (nv_ro32(bios, dcb + 4) == 0x4edcbdcb) {
-			u16 i2c = nv_ro16(bios, dcb + 2);
-			*hdr = 8;
-			*cnt = (i2c - dcb) / 8;
-			*len = 8;
-			return dcb;
-		}
-	} else
-	if (*ver >= 0x15) {
-		if (!nv_memcmp(bios, dcb - 7, "DEV_REC", 7)) {
-			u16 i2c = nv_ro16(bios, dcb + 2);
-			*hdr = 4;
-			*cnt = (i2c - dcb) / 10;
-			*len = 10;
-			return dcb;
-		}
-	} else {
-		/*
-		 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but
-		 * always has the same single (crt) entry, even when tv-out
-		 * present, so the conclusion is this version cannot really
-		 * be used.
-		 *
-		 * v1.2 tables (some NV6/10, and NV15+) normally have the
-		 * same 5 entries, which are not specific to the card and so
-		 * no use.
-		 *
-		 * v1.2 does have an I2C table that read_dcb_i2c_table can
-		 * handle, but cards exist (nv11 in #14821) with a bad i2c
-		 * table pointer, so use the indices parsed in
-		 * parse_bmp_structure.
-		 *
-		 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
-		 */
-		nv_warn(bios, "DCB contains no useful data\n");
-		return 0x0000;
-	}
-
-	nv_warn(bios, "DCB header validation failed\n");
-	return 0x0000;
-}
-
-u16
-dcb_outp(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len)
-{
-	u8  hdr, cnt;
-	u16 dcb = dcb_table(bios, ver, &hdr, &cnt, len);
-	if (dcb && idx < cnt)
-		return dcb + hdr + (idx * *len);
-	return 0x0000;
-}
-
-static inline u16
-dcb_outp_hasht(struct dcb_output *outp)
-{
-	return (outp->extdev << 8) | (outp->location << 4) | outp->type;
-}
-
-static inline u16
-dcb_outp_hashm(struct dcb_output *outp)
-{
-	return (outp->heads << 8) | (outp->link << 6) | outp->or;
-}
-
-u16
-dcb_outp_parse(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len,
-	       struct dcb_output *outp)
-{
-	u16 dcb = dcb_outp(bios, idx, ver, len);
-	memset(outp, 0x00, sizeof(*outp));
-	if (dcb) {
-		if (*ver >= 0x20) {
-			u32 conn = nv_ro32(bios, dcb + 0x00);
-			outp->or        = (conn & 0x0f000000) >> 24;
-			outp->location  = (conn & 0x00300000) >> 20;
-			outp->bus       = (conn & 0x000f0000) >> 16;
-			outp->connector = (conn & 0x0000f000) >> 12;
-			outp->heads     = (conn & 0x00000f00) >> 8;
-			outp->i2c_index = (conn & 0x000000f0) >> 4;
-			outp->type      = (conn & 0x0000000f);
-			outp->link      = 0;
-		} else {
-			dcb = 0x0000;
-		}
-
-		if (*ver >= 0x40) {
-			u32 conf = nv_ro32(bios, dcb + 0x04);
-			switch (outp->type) {
-			case DCB_OUTPUT_DP:
-				switch (conf & 0x00e00000) {
-				case 0x00000000:
-					outp->dpconf.link_bw = 0x06;
-					break;
-				case 0x00200000:
-					outp->dpconf.link_bw = 0x0a;
-					break;
-				case 0x00400000:
-				default:
-					outp->dpconf.link_bw = 0x14;
-					break;
-				}
-
-				outp->dpconf.link_nr = (conf & 0x0f000000) >> 24;
-				if (*ver < 0x41) {
-					switch (outp->dpconf.link_nr) {
-					case 0x0f:
-						outp->dpconf.link_nr = 4;
-						break;
-					case 0x03:
-						outp->dpconf.link_nr = 2;
-						break;
-					case 0x01:
-					default:
-						outp->dpconf.link_nr = 1;
-						break;
-					}
-				}
-
-				/* fall-through... */
-			case DCB_OUTPUT_TMDS:
-			case DCB_OUTPUT_LVDS:
-				outp->link = (conf & 0x00000030) >> 4;
-				outp->sorconf.link = outp->link; /*XXX*/
-				outp->extdev = 0x00;
-				if (outp->location != 0)
-					outp->extdev = (conf & 0x0000ff00) >> 8;
-				break;
-			default:
-				break;
-			}
-		}
-
-		outp->hasht = dcb_outp_hasht(outp);
-		outp->hashm = dcb_outp_hashm(outp);
-	}
-	return dcb;
-}
-
-u16
-dcb_outp_match(struct nouveau_bios *bios, u16 type, u16 mask,
-	       u8 *ver, u8 *len, struct dcb_output *outp)
-{
-	u16 dcb, idx = 0;
-	while ((dcb = dcb_outp_parse(bios, idx++, ver, len, outp))) {
-		if ((dcb_outp_hasht(outp) & 0x00ff) == (type & 0x00ff)) {
-			if ((dcb_outp_hashm(outp) & mask) == mask)
-				break;
-		}
-	}
-	return dcb;
-}
-
-int
-dcb_outp_foreach(struct nouveau_bios *bios, void *data,
-		 int (*exec)(struct nouveau_bios *, void *, int, u16))
-{
-	int ret, idx = -1;
-	u8  ver, len;
-	u16 outp;
-
-	while ((outp = dcb_outp(bios, ++idx, &ver, &len))) {
-		if (nv_ro32(bios, outp) == 0x00000000)
-			break; /* seen on an NV11 with DCB v1.5 */
-		if (nv_ro32(bios, outp) == 0xffffffff)
-			break; /* seen on an NV17 with DCB v2.0 */
-
-		if (nv_ro08(bios, outp) == DCB_OUTPUT_UNUSED)
-			continue;
-		if (nv_ro08(bios, outp) == DCB_OUTPUT_EOL)
-			break;
-
-		ret = exec(bios, data, idx, outp);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/disp.c b/drivers/gpu/drm/nouveau/core/subdev/bios/disp.c
deleted file mode 100644
index 51f355599694..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/disp.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/disp.h>
-
-u16
-nvbios_disp_table(struct nouveau_bios *bios,
-		  u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *sub)
-{
-	struct bit_entry U;
-
-	if (!bit_entry(bios, 'U', &U)) {
-		if (U.version == 1) {
-			u16 data = nv_ro16(bios, U.offset);
-			if (data) {
-				*ver = nv_ro08(bios, data + 0x00);
-				switch (*ver) {
-				case 0x20:
-				case 0x21:
-				case 0x22:
-					*hdr = nv_ro08(bios, data + 0x01);
-					*len = nv_ro08(bios, data + 0x02);
-					*cnt = nv_ro08(bios, data + 0x03);
-					*sub = nv_ro08(bios, data + 0x04);
-					return data;
-				default:
-					break;
-				}
-			}
-		}
-	}
-
-	return 0x0000;
-}
-
-u16
-nvbios_disp_entry(struct nouveau_bios *bios, u8 idx,
-		  u8 *ver, u8 *len, u8 *sub)
-{
-	u8  hdr, cnt;
-	u16 data = nvbios_disp_table(bios, ver, &hdr, &cnt, len, sub);
-	if (data && idx < cnt)
-		return data + hdr + (idx * *len);
-	*ver = 0x00;
-	return 0x0000;
-}
-
-u16
-nvbios_disp_parse(struct nouveau_bios *bios, u8 idx,
-		  u8 *ver, u8 *len, u8 *sub,
-		  struct nvbios_disp *info)
-{
-	u16 data = nvbios_disp_entry(bios, idx, ver, len, sub);
-	if (data && *len >= 2) {
-		info->data = nv_ro16(bios, data + 0);
-		return data;
-	}
-	return 0x0000;
-}
-
-u16
-nvbios_outp_entry(struct nouveau_bios *bios, u8 idx,
-		  u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	struct nvbios_disp info;
-	u16 data = nvbios_disp_parse(bios, idx, ver, len, hdr, &info);
-	if (data) {
-		*cnt = nv_ro08(bios, info.data + 0x05);
-		*len = 0x06;
-		data = info.data;
-	}
-	return data;
-}
-
-u16
-nvbios_outp_parse(struct nouveau_bios *bios, u8 idx,
-		  u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		  struct nvbios_outp *info)
-{
-	u16 data = nvbios_outp_entry(bios, idx, ver, hdr, cnt, len);
-	if (data && *hdr >= 0x0a) {
-		info->type      = nv_ro16(bios, data + 0x00);
-		info->mask      = nv_ro32(bios, data + 0x02);
-		if (*ver <= 0x20) /* match any link */
-			info->mask |= 0x00c0;
-		info->script[0] = nv_ro16(bios, data + 0x06);
-		info->script[1] = nv_ro16(bios, data + 0x08);
-		info->script[2] = 0x0000;
-		if (*hdr >= 0x0c)
-			info->script[2] = nv_ro16(bios, data + 0x0a);
-		return data;
-	}
-	return 0x0000;
-}
-
-u16
-nvbios_outp_match(struct nouveau_bios *bios, u16 type, u16 mask,
-		  u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		  struct nvbios_outp *info)
-{
-	u16 data, idx = 0;
-	while ((data = nvbios_outp_parse(bios, idx++, ver, hdr, cnt, len, info)) || *ver) {
-		if (data && info->type == type) {
-			if ((info->mask & mask) == mask)
-				break;
-		}
-	}
-	return data;
-}
-
-u16
-nvbios_ocfg_entry(struct nouveau_bios *bios, u16 outp, u8 idx,
-		  u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	if (idx < *cnt)
-		return outp + *hdr + (idx * *len);
-	return 0x0000;
-}
-
-u16
-nvbios_ocfg_parse(struct nouveau_bios *bios, u16 outp, u8 idx,
-		  u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		  struct nvbios_ocfg *info)
-{
-	u16 data = nvbios_ocfg_entry(bios, outp, idx, ver, hdr, cnt, len);
-	if (data) {
-		info->match     = nv_ro16(bios, data + 0x00);
-		info->clkcmp[0] = nv_ro16(bios, data + 0x02);
-		info->clkcmp[1] = nv_ro16(bios, data + 0x04);
-	}
-	return data;
-}
-
-u16
-nvbios_ocfg_match(struct nouveau_bios *bios, u16 outp, u16 type,
-		  u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		  struct nvbios_ocfg *info)
-{
-	u16 data, idx = 0;
-	while ((data = nvbios_ocfg_parse(bios, outp, idx++, ver, hdr, cnt, len, info))) {
-		if (info->match == type)
-			break;
-	}
-	return data;
-}
-
-u16
-nvbios_oclk_match(struct nouveau_bios *bios, u16 cmp, u32 khz)
-{
-	while (cmp) {
-		if (khz / 10 >= nv_ro16(bios, cmp + 0x00))
-			return  nv_ro16(bios, cmp + 0x02);
-		cmp += 0x04;
-	}
-	return 0x0000;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/dp.c b/drivers/gpu/drm/nouveau/core/subdev/bios/dp.c
deleted file mode 100644
index cef53f81f12b..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/dp.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-
-#include "subdev/bios.h"
-#include "subdev/bios/bit.h"
-#include "subdev/bios/dp.h"
-
-static u16
-nvbios_dp_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	struct bit_entry d;
-
-	if (!bit_entry(bios, 'd', &d)) {
-		if (d.version == 1 && d.length >= 2) {
-			u16 data = nv_ro16(bios, d.offset);
-			if (data) {
-				*ver = nv_ro08(bios, data + 0x00);
-				switch (*ver) {
-				case 0x21:
-				case 0x30:
-				case 0x40:
-				case 0x41:
-					*hdr = nv_ro08(bios, data + 0x01);
-					*len = nv_ro08(bios, data + 0x02);
-					*cnt = nv_ro08(bios, data + 0x03);
-					return data;
-				default:
-					break;
-				}
-			}
-		}
-	}
-
-	return 0x0000;
-}
-
-static u16
-nvbios_dpout_entry(struct nouveau_bios *bios, u8 idx,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	u16 data = nvbios_dp_table(bios, ver, hdr, cnt, len);
-	if (data && idx < *cnt) {
-		u16 outp = nv_ro16(bios, data + *hdr + idx * *len);
-		switch (*ver * !!outp) {
-		case 0x21:
-		case 0x30:
-			*hdr = nv_ro08(bios, data + 0x04);
-			*len = nv_ro08(bios, data + 0x05);
-			*cnt = nv_ro08(bios, outp + 0x04);
-			break;
-		case 0x40:
-		case 0x41:
-			*hdr = nv_ro08(bios, data + 0x04);
-			*cnt = 0;
-			*len = 0;
-			break;
-		default:
-			break;
-		}
-		return outp;
-	}
-	*ver = 0x00;
-	return 0x0000;
-}
-
-u16
-nvbios_dpout_parse(struct nouveau_bios *bios, u8 idx,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		   struct nvbios_dpout *info)
-{
-	u16 data = nvbios_dpout_entry(bios, idx, ver, hdr, cnt, len);
-	memset(info, 0x00, sizeof(*info));
-	if (data && *ver) {
-		info->type = nv_ro16(bios, data + 0x00);
-		info->mask = nv_ro16(bios, data + 0x02);
-		switch (*ver) {
-		case 0x21:
-		case 0x30:
-			info->flags     = nv_ro08(bios, data + 0x05);
-			info->script[0] = nv_ro16(bios, data + 0x06);
-			info->script[1] = nv_ro16(bios, data + 0x08);
-			info->lnkcmp    = nv_ro16(bios, data + 0x0a);
-			if (*len >= 0x0f) {
-				info->script[2] = nv_ro16(bios, data + 0x0c);
-				info->script[3] = nv_ro16(bios, data + 0x0e);
-			}
-			if (*len >= 0x11)
-				info->script[4] = nv_ro16(bios, data + 0x10);
-			break;
-		case 0x40:
-		case 0x41:
-			info->flags     = nv_ro08(bios, data + 0x04);
-			info->script[0] = nv_ro16(bios, data + 0x05);
-			info->script[1] = nv_ro16(bios, data + 0x07);
-			info->lnkcmp    = nv_ro16(bios, data + 0x09);
-			info->script[2] = nv_ro16(bios, data + 0x0b);
-			info->script[3] = nv_ro16(bios, data + 0x0d);
-			info->script[4] = nv_ro16(bios, data + 0x0f);
-			break;
-		default:
-			data = 0x0000;
-			break;
-		}
-	}
-	return data;
-}
-
-u16
-nvbios_dpout_match(struct nouveau_bios *bios, u16 type, u16 mask,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		   struct nvbios_dpout *info)
-{
-	u16 data, idx = 0;
-	while ((data = nvbios_dpout_parse(bios, idx++, ver, hdr, cnt, len, info)) || *ver) {
-		if (data && info->type == type) {
-			if ((info->mask & mask) == mask)
-				break;
-		}
-	}
-	return data;
-}
-
-static u16
-nvbios_dpcfg_entry(struct nouveau_bios *bios, u16 outp, u8 idx,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	if (*ver >= 0x40) {
-		outp = nvbios_dp_table(bios, ver, hdr, cnt, len);
-		*hdr = *hdr + (*len * * cnt);
-		*len = nv_ro08(bios, outp + 0x06);
-		*cnt = nv_ro08(bios, outp + 0x07);
-	}
-
-	if (idx < *cnt)
-		return outp + *hdr + (idx * *len);
-
-	return 0x0000;
-}
-
-u16
-nvbios_dpcfg_parse(struct nouveau_bios *bios, u16 outp, u8 idx,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		   struct nvbios_dpcfg *info)
-{
-	u16 data = nvbios_dpcfg_entry(bios, outp, idx, ver, hdr, cnt, len);
-	memset(info, 0x00, sizeof(*info));
-	if (data) {
-		switch (*ver) {
-		case 0x21:
-			info->dc    = nv_ro08(bios, data + 0x02);
-			info->pe    = nv_ro08(bios, data + 0x03);
-			info->tx_pu = nv_ro08(bios, data + 0x04);
-			break;
-		case 0x30:
-		case 0x40:
-		case 0x41:
-			info->pc    = nv_ro08(bios, data + 0x00);
-			info->dc    = nv_ro08(bios, data + 0x01);
-			info->pe    = nv_ro08(bios, data + 0x02);
-			info->tx_pu = nv_ro08(bios, data + 0x03) & 0x0f;
-			break;
-		default:
-			data = 0x0000;
-			break;
-		}
-	}
-	return data;
-}
-
-u16
-nvbios_dpcfg_match(struct nouveau_bios *bios, u16 outp, u8 pc, u8 vs, u8 pe,
-		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		   struct nvbios_dpcfg *info)
-{
-	u8 idx = 0xff;
-	u16 data;
-
-	if (*ver >= 0x30) {
-		/*XXX: there's a second set of these on at least 4.1, that
-		 *     i've witnessed nvidia using instead of the first
-		 *     on gm204.  figure out what/why
-		 */
-		const u8 vsoff[] = { 0, 4, 7, 9 };
-		idx = (pc * 10) + vsoff[vs] + pe;
-	} else {
-		while ((data = nvbios_dpcfg_entry(bios, outp, ++idx,
-						  ver, hdr, cnt, len))) {
-			if (nv_ro08(bios, data + 0x00) == vs &&
-			    nv_ro08(bios, data + 0x01) == pe)
-				break;
-		}
-	}
-
-	return nvbios_dpcfg_parse(bios, outp, idx, ver, hdr, cnt, len, info);
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/extdev.c b/drivers/gpu/drm/nouveau/core/subdev/bios/extdev.c
deleted file mode 100644
index 49285d4f7ca5..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/extdev.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright 2012 Nouveau Community
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/extdev.h>
-
-static u16
-extdev_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt)
-{
-	u8  dcb_ver, dcb_hdr, dcb_cnt, dcb_len;
-	u16 dcb, extdev = 0;
-
-	dcb = dcb_table(bios, &dcb_ver, &dcb_hdr, &dcb_cnt, &dcb_len);
-	if (!dcb || (dcb_ver != 0x30 && dcb_ver != 0x40))
-		return 0x0000;
-
-	extdev = nv_ro16(bios, dcb + 18);
-	if (!extdev)
-		return 0x0000;
-
-	*ver = nv_ro08(bios, extdev + 0);
-	*hdr = nv_ro08(bios, extdev + 1);
-	*cnt = nv_ro08(bios, extdev + 2);
-	*len = nv_ro08(bios, extdev + 3);
-
-	return extdev + *hdr;
-}
-
-static u16
-nvbios_extdev_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
-{
-	u8 hdr, cnt;
-	u16 extdev = extdev_table(bios, ver, &hdr, len, &cnt);
-	if (extdev && idx < cnt)
-		return extdev + idx * *len;
-	return 0x0000;
-}
-
-static void
-extdev_parse_entry(struct nouveau_bios *bios, u16 offset,
-			  struct nvbios_extdev_func *entry)
-{
-	entry->type = nv_ro08(bios, offset + 0);
-	entry->addr = nv_ro08(bios, offset + 1);
-	entry->bus = (nv_ro08(bios, offset + 2) >> 4) & 1;
-}
-
-int
-nvbios_extdev_parse(struct nouveau_bios *bios, int idx,
-		    struct nvbios_extdev_func *func)
-{
-	u8 ver, len;
-	u16 entry;
-
-	if (!(entry = nvbios_extdev_entry(bios, idx, &ver, &len)))
-		return -EINVAL;
-
-	extdev_parse_entry(bios, entry, func);
-
-	return 0;
-}
-
-int
-nvbios_extdev_find(struct nouveau_bios *bios, enum nvbios_extdev_type type,
-		   struct nvbios_extdev_func *func)
-{
-	u8 ver, len, i;
-	u16 entry;
-
-	i = 0;
-	while ((entry = nvbios_extdev_entry(bios, i++, &ver, &len))) {
-		extdev_parse_entry(bios, entry, func);
-		if (func->type == type)
-			return 0;
-	}
-
-	return -EINVAL;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/fan.c b/drivers/gpu/drm/nouveau/core/subdev/bios/fan.c
deleted file mode 100644
index e419892240f5..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/fan.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright 2014 Martin Peres
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/fan.h>
-
-u16
-nvbios_fan_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	struct bit_entry bit_P;
-	u16 fan = 0x0000;
-
-	if (!bit_entry(bios, 'P', &bit_P)) {
-		if (bit_P.version == 2 && bit_P.length >= 0x5a)
-			fan = nv_ro16(bios, bit_P.offset + 0x58);
-
-		if (fan) {
-			*ver = nv_ro08(bios, fan + 0);
-			switch (*ver) {
-			case 0x10:
-				*hdr = nv_ro08(bios, fan + 1);
-				*len = nv_ro08(bios, fan + 2);
-				*cnt = nv_ro08(bios, fan + 3);
-				return fan;
-			default:
-				break;
-			}
-		}
-	}
-
-	return 0x0000;
-}
-
-u16
-nvbios_fan_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
-		 u8 *cnt, u8 *len)
-{
-	u16 data = nvbios_fan_table(bios, ver, hdr, cnt, len);
-	if (data && idx < *cnt)
-		return data + *hdr + (idx * (*len));
-	return 0x0000;
-}
-
-u16
-nvbios_fan_parse(struct nouveau_bios *bios, struct nvbios_therm_fan *fan)
-{
-	u8 ver, hdr, cnt, len;
-
-	u16 data = nvbios_fan_entry(bios, 0, &ver, &hdr, &cnt, &len);
-	if (data) {
-		u8 type = nv_ro08(bios, data + 0x00);
-		switch (type) {
-		case 0:
-			fan->type = NVBIOS_THERM_FAN_TOGGLE;
-			break;
-		case 1:
-		case 2:
-			/* TODO: Understand the difference between the two! */
-			fan->type = NVBIOS_THERM_FAN_PWM;
-			break;
-		default:
-			fan->type = NVBIOS_THERM_FAN_UNK;
-		}
-
-		fan->min_duty = nv_ro08(bios, data + 0x02);
-		fan->max_duty = nv_ro08(bios, data + 0x03);
-
-		fan->pwm_freq = nv_ro32(bios, data + 0x0b) & 0xffffff;
-	}
-	return data;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/gpio.c b/drivers/gpu/drm/nouveau/core/subdev/bios/gpio.c
deleted file mode 100644
index 172a4f999990..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/gpio.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/gpio.h>
-#include <subdev/bios/xpio.h>
-
-u16
-dcb_gpio_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	u16 data = 0x0000;
-	u16 dcb = dcb_table(bios, ver, hdr, cnt, len);
-	if (dcb) {
-		if (*ver >= 0x30 && *hdr >= 0x0c)
-			data = nv_ro16(bios, dcb + 0x0a);
-		else
-		if (*ver >= 0x22 && nv_ro08(bios, dcb - 1) >= 0x13)
-			data = nv_ro16(bios, dcb - 0x0f);
-
-		if (data) {
-			*ver = nv_ro08(bios, data + 0x00);
-			if (*ver < 0x30) {
-				*hdr = 3;
-				*cnt = nv_ro08(bios, data + 0x02);
-				*len = nv_ro08(bios, data + 0x01);
-			} else
-			if (*ver <= 0x41) {
-				*hdr = nv_ro08(bios, data + 0x01);
-				*cnt = nv_ro08(bios, data + 0x02);
-				*len = nv_ro08(bios, data + 0x03);
-			} else {
-				data = 0x0000;
-			}
-		}
-	}
-	return data;
-}
-
-u16
-dcb_gpio_entry(struct nouveau_bios *bios, int idx, int ent, u8 *ver, u8 *len)
-{
-	u8  hdr, cnt, xver; /* use gpio version for xpio entry parsing */
-	u16 gpio;
-
-	if (!idx--)
-		gpio = dcb_gpio_table(bios, ver, &hdr, &cnt, len);
-	else
-		gpio = dcb_xpio_table(bios, idx, &xver, &hdr, &cnt, len);
-
-	if (gpio && ent < cnt)
-		return gpio + hdr + (ent * *len);
-	return 0x0000;
-}
-
-u16
-dcb_gpio_parse(struct nouveau_bios *bios, int idx, int ent, u8 *ver, u8 *len,
-	       struct dcb_gpio_func *gpio)
-{
-	u16 data = dcb_gpio_entry(bios, idx, ent, ver, len);
-	if (data) {
-		if (*ver < 0x40) {
-			u16 info = nv_ro16(bios, data);
-			*gpio = (struct dcb_gpio_func) {
-				.line = (info & 0x001f) >> 0,
-				.func = (info & 0x07e0) >> 5,
-				.log[0] = (info & 0x1800) >> 11,
-				.log[1] = (info & 0x6000) >> 13,
-				.param = !!(info & 0x8000),
-			};
-		} else
-		if (*ver < 0x41) {
-			u32 info = nv_ro32(bios, data);
-			*gpio = (struct dcb_gpio_func) {
-				.line = (info & 0x0000001f) >> 0,
-				.func = (info & 0x0000ff00) >> 8,
-				.log[0] = (info & 0x18000000) >> 27,
-				.log[1] = (info & 0x60000000) >> 29,
-				.param = !!(info & 0x80000000),
-			};
-		} else {
-			u32 info = nv_ro32(bios, data + 0);
-			u8 info1 = nv_ro32(bios, data + 4);
-			*gpio = (struct dcb_gpio_func) {
-				.line = (info & 0x0000003f) >> 0,
-				.func = (info & 0x0000ff00) >> 8,
-				.log[0] = (info1 & 0x30) >> 4,
-				.log[1] = (info1 & 0xc0) >> 6,
-				.param = !!(info & 0x80000000),
-			};
-		}
-	}
-
-	return data;
-}
-
-u16
-dcb_gpio_match(struct nouveau_bios *bios, int idx, u8 func, u8 line,
-	       u8 *ver, u8 *len, struct dcb_gpio_func *gpio)
-{
-	u8  hdr, cnt, i = 0;
-	u16 data;
-
-	while ((data = dcb_gpio_parse(bios, idx, i++, ver, len, gpio))) {
-		if ((line == 0xff || line == gpio->line) &&
-		    (func == 0xff || func == gpio->func))
-			return data;
-	}
-
-	/* DCB 2.2, fixed TVDAC GPIO data */
-	if ((data = dcb_table(bios, ver, &hdr, &cnt, len))) {
-		if (*ver >= 0x22 && *ver < 0x30 && func == DCB_GPIO_TVDAC0) {
-			u8 conf = nv_ro08(bios, data - 5);
-			u8 addr = nv_ro08(bios, data - 4);
-			if (conf & 0x01) {
-				*gpio = (struct dcb_gpio_func) {
-					.func = DCB_GPIO_TVDAC0,
-					.line = addr >> 4,
-					.log[0] = !!(conf & 0x02),
-					.log[1] =  !(conf & 0x02),
-				};
-				*ver = 0x00;
-				return data;
-			}
-		}
-	}
-
-	return 0x0000;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/i2c.c b/drivers/gpu/drm/nouveau/core/subdev/bios/i2c.c
deleted file mode 100644
index 282320ba9264..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/i2c.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-
-#include "subdev/bios.h"
-#include "subdev/bios/dcb.h"
-#include "subdev/bios/i2c.h"
-
-u16
-dcb_i2c_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	u16 i2c = 0x0000;
-	u16 dcb = dcb_table(bios, ver, hdr, cnt, len);
-	if (dcb) {
-		if (*ver >= 0x15)
-			i2c = nv_ro16(bios, dcb + 2);
-		if (*ver >= 0x30)
-			i2c = nv_ro16(bios, dcb + 4);
-	}
-
-	if (i2c && *ver >= 0x42) {
-		nv_warn(bios, "ccb %02x not supported\n", *ver);
-		return 0x0000;
-	}
-
-	if (i2c && *ver >= 0x30) {
-		*ver = nv_ro08(bios, i2c + 0);
-		*hdr = nv_ro08(bios, i2c + 1);
-		*cnt = nv_ro08(bios, i2c + 2);
-		*len = nv_ro08(bios, i2c + 3);
-	} else {
-		*ver = *ver; /* use DCB version */
-		*hdr = 0;
-		*cnt = 16;
-		*len = 4;
-	}
-
-	return i2c;
-}
-
-u16
-dcb_i2c_entry(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len)
-{
-	u8  hdr, cnt;
-	u16 i2c = dcb_i2c_table(bios, ver, &hdr, &cnt, len);
-	if (i2c && idx < cnt)
-		return i2c + hdr + (idx * *len);
-	return 0x0000;
-}
-
-int
-dcb_i2c_parse(struct nouveau_bios *bios, u8 idx, struct dcb_i2c_entry *info)
-{
-	u8  ver, len;
-	u16 ent = dcb_i2c_entry(bios, idx, &ver, &len);
-	if (ent) {
-		if (ver >= 0x41) {
-			if (!(nv_ro32(bios, ent) & 0x80000000))
-				info->type = DCB_I2C_UNUSED;
-			else
-				info->type = DCB_I2C_PMGR;
-		} else
-		if (ver >= 0x30) {
-			info->type = nv_ro08(bios, ent + 0x03);
-		} else {
-			info->type = nv_ro08(bios, ent + 0x03) & 0x07;
-			if (info->type == 0x07)
-				info->type = DCB_I2C_UNUSED;
-		}
-
-		info->drive = DCB_I2C_UNUSED;
-		info->sense = DCB_I2C_UNUSED;
-		info->share = DCB_I2C_UNUSED;
-		info->auxch = DCB_I2C_UNUSED;
-
-		switch (info->type) {
-		case DCB_I2C_NV04_BIT:
-			info->drive = nv_ro08(bios, ent + 0);
-			info->sense = nv_ro08(bios, ent + 1);
-			return 0;
-		case DCB_I2C_NV4E_BIT:
-			info->drive = nv_ro08(bios, ent + 1);
-			return 0;
-		case DCB_I2C_NVIO_BIT:
-			info->drive = nv_ro08(bios, ent + 0) & 0x0f;
-			if (nv_ro08(bios, ent + 1) & 0x01)
-				info->share = nv_ro08(bios, ent + 1) >> 1;
-			return 0;
-		case DCB_I2C_NVIO_AUX:
-			info->auxch = nv_ro08(bios, ent + 0) & 0x0f;
-			if (nv_ro08(bios, ent + 1) & 0x01)
-					info->share = info->auxch;
-			return 0;
-		case DCB_I2C_PMGR:
-			info->drive = (nv_ro16(bios, ent + 0) & 0x01f) >> 0;
-			if (info->drive == 0x1f)
-				info->drive = DCB_I2C_UNUSED;
-			info->auxch = (nv_ro16(bios, ent + 0) & 0x3e0) >> 5;
-			if (info->auxch == 0x1f)
-				info->auxch = DCB_I2C_UNUSED;
-			info->share = info->auxch;
-			return 0;
-		case DCB_I2C_UNUSED:
-			return 0;
-		default:
-			nv_warn(bios, "unknown i2c type %d\n", info->type);
-			info->type = DCB_I2C_UNUSED;
-			return 0;
-		}
-	}
-
-	if (bios->bmp_offset && idx < 2) {
-		/* BMP (from v4.0 has i2c info in the structure, it's in a
-		 * fixed location on earlier VBIOS
-		 */
-		if (nv_ro08(bios, bios->bmp_offset + 5) < 4)
-			ent = 0x0048;
-		else
-			ent = 0x0036 + bios->bmp_offset;
-
-		if (idx == 0) {
-			info->drive = nv_ro08(bios, ent + 4);
-			if (!info->drive) info->drive = 0x3f;
-			info->sense = nv_ro08(bios, ent + 5);
-			if (!info->sense) info->sense = 0x3e;
-		} else
-		if (idx == 1) {
-			info->drive = nv_ro08(bios, ent + 6);
-			if (!info->drive) info->drive = 0x37;
-			info->sense = nv_ro08(bios, ent + 7);
-			if (!info->sense) info->sense = 0x36;
-		}
-
-		info->type  = DCB_I2C_NV04_BIT;
-		info->share = DCB_I2C_UNUSED;
-		return 0;
-	}
-
-	return -ENOENT;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/image.c b/drivers/gpu/drm/nouveau/core/subdev/bios/image.c
deleted file mode 100644
index 373f9a564ac9..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/image.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/image.h>
-#include <subdev/bios/pcir.h>
-#include <subdev/bios/npde.h>
-
-static bool
-nvbios_imagen(struct nouveau_bios *bios, struct nvbios_image *image)
-{
-	struct nvbios_pcirT pcir;
-	struct nvbios_npdeT npde;
-	u8  ver;
-	u16 hdr;
-	u32 data;
-
-	switch ((data = nv_ro16(bios, image->base + 0x00))) {
-	case 0xaa55:
-	case 0xbb77:
-	case 0x4e56: /* NV */
-		break;
-	default:
-		nv_debug(bios, "%08x: ROM signature (%04x) unknown\n",
-			 image->base, data);
-		return false;
-	}
-
-	if (!(data = nvbios_pcirTp(bios, image->base, &ver, &hdr, &pcir)))
-		return false;
-	image->size = pcir.image_size;
-	image->type = pcir.image_type;
-	image->last = pcir.last;
-
-	if (image->type != 0x70) {
-		if (!(data = nvbios_npdeTp(bios, image->base, &npde)))
-			return true;
-		image->size = npde.image_size;
-		image->last = npde.last;
-	} else {
-		image->last = true;
-	}
-
-	return true;
-}
-
-bool
-nvbios_image(struct nouveau_bios *bios, int idx, struct nvbios_image *image)
-{
-	memset(image, 0x00, sizeof(*image));
-	do {
-		image->base += image->size;
-		if (image->last || !nvbios_imagen(bios, image))
-			return false;
-	} while(idx--);
-	return true;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c b/drivers/gpu/drm/nouveau/core/subdev/bios/init.c
deleted file mode 100644
index c6579ef32cd1..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c
+++ /dev/null
@@ -1,2227 +0,0 @@
-#include <core/engine.h>
-#include <core/device.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/bmp.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/conn.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/dp.h>
-#include <subdev/bios/gpio.h>
-#include <subdev/bios/init.h>
-#include <subdev/bios/ramcfg.h>
-#include <subdev/devinit.h>
-#include <subdev/i2c.h>
-#include <subdev/vga.h>
-#include <subdev/gpio.h>
-
-#define bioslog(lvl, fmt, args...) do {                                        \
-	nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset,            \
-		  init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args);   \
-} while(0)
-#define cont(fmt, args...) do {                                                \
-	if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE)                      \
-		printk(fmt, ##args);                                           \
-} while(0)
-#define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
-#define warn(fmt, args...) bioslog(WARN, fmt, ##args)
-#define error(fmt, args...) bioslog(ERROR, fmt, ##args)
-
-/******************************************************************************
- * init parser control flow helpers
- *****************************************************************************/
-
-static inline bool
-init_exec(struct nvbios_init *init)
-{
-	return (init->execute == 1) || ((init->execute & 5) == 5);
-}
-
-static inline void
-init_exec_set(struct nvbios_init *init, bool exec)
-{
-	if (exec) init->execute &= 0xfd;
-	else      init->execute |= 0x02;
-}
-
-static inline void
-init_exec_inv(struct nvbios_init *init)
-{
-	init->execute ^= 0x02;
-}
-
-static inline void
-init_exec_force(struct nvbios_init *init, bool exec)
-{
-	if (exec) init->execute |= 0x04;
-	else      init->execute &= 0xfb;
-}
-
-/******************************************************************************
- * init parser wrappers for normal register/i2c/whatever accessors
- *****************************************************************************/
-
-static inline int
-init_or(struct nvbios_init *init)
-{
-	if (init_exec(init)) {
-		if (init->outp)
-			return ffs(init->outp->or) - 1;
-		error("script needs OR!!\n");
-	}
-	return 0;
-}
-
-static inline int
-init_link(struct nvbios_init *init)
-{
-	if (init_exec(init)) {
-		if (init->outp)
-			return !(init->outp->sorconf.link & 1);
-		error("script needs OR link\n");
-	}
-	return 0;
-}
-
-static inline int
-init_crtc(struct nvbios_init *init)
-{
-	if (init_exec(init)) {
-		if (init->crtc >= 0)
-			return init->crtc;
-		error("script needs crtc\n");
-	}
-	return 0;
-}
-
-static u8
-init_conn(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	struct nvbios_connE connE;
-	u8  ver, hdr;
-	u32 conn;
-
-	if (init_exec(init)) {
-		if (init->outp) {
-			conn = init->outp->connector;
-			conn = nvbios_connEp(bios, conn, &ver, &hdr, &connE);
-			if (conn)
-				return connE.type;
-		}
-
-		error("script needs connector type\n");
-	}
-
-	return 0xff;
-}
-
-static inline u32
-init_nvreg(struct nvbios_init *init, u32 reg)
-{
-	struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
-
-	/* C51 (at least) sometimes has the lower bits set which the VBIOS
-	 * interprets to mean that access needs to go through certain IO
-	 * ports instead.  The NVIDIA binary driver has been seen to access
-	 * these through the NV register address, so lets assume we can
-	 * do the same
-	 */
-	reg &= ~0x00000003;
-
-	/* GF8+ display scripts need register addresses mangled a bit to
-	 * select a specific CRTC/OR
-	 */
-	if (nv_device(init->bios)->card_type >= NV_50) {
-		if (reg & 0x80000000) {
-			reg += init_crtc(init) * 0x800;
-			reg &= ~0x80000000;
-		}
-
-		if (reg & 0x40000000) {
-			reg += init_or(init) * 0x800;
-			reg &= ~0x40000000;
-			if (reg & 0x20000000) {
-				reg += init_link(init) * 0x80;
-				reg &= ~0x20000000;
-			}
-		}
-	}
-
-	if (reg & ~0x00fffffc)
-		warn("unknown bits in register 0x%08x\n", reg);
-
-	if (devinit->mmio)
-		reg = devinit->mmio(devinit, reg);
-	return reg;
-}
-
-static u32
-init_rd32(struct nvbios_init *init, u32 reg)
-{
-	reg = init_nvreg(init, reg);
-	if (reg != ~0 && init_exec(init))
-		return nv_rd32(init->subdev, reg);
-	return 0x00000000;
-}
-
-static void
-init_wr32(struct nvbios_init *init, u32 reg, u32 val)
-{
-	reg = init_nvreg(init, reg);
-	if (reg != ~0 && init_exec(init))
-		nv_wr32(init->subdev, reg, val);
-}
-
-static u32
-init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
-{
-	reg = init_nvreg(init, reg);
-	if (reg != ~0 && init_exec(init)) {
-		u32 tmp = nv_rd32(init->subdev, reg);
-		nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
-		return tmp;
-	}
-	return 0x00000000;
-}
-
-static u8
-init_rdport(struct nvbios_init *init, u16 port)
-{
-	if (init_exec(init))
-		return nv_rdport(init->subdev, init->crtc, port);
-	return 0x00;
-}
-
-static void
-init_wrport(struct nvbios_init *init, u16 port, u8 value)
-{
-	if (init_exec(init))
-		nv_wrport(init->subdev, init->crtc, port, value);
-}
-
-static u8
-init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
-{
-	struct nouveau_subdev *subdev = init->subdev;
-	if (init_exec(init)) {
-		int head = init->crtc < 0 ? 0 : init->crtc;
-		return nv_rdvgai(subdev, head, port, index);
-	}
-	return 0x00;
-}
-
-static void
-init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
-{
-	/* force head 0 for updates to cr44, it only exists on first head */
-	if (nv_device(init->subdev)->card_type < NV_50) {
-		if (port == 0x03d4 && index == 0x44)
-			init->crtc = 0;
-	}
-
-	if (init_exec(init)) {
-		int head = init->crtc < 0 ? 0 : init->crtc;
-		nv_wrvgai(init->subdev, head, port, index, value);
-	}
-
-	/* select head 1 if cr44 write selected it */
-	if (nv_device(init->subdev)->card_type < NV_50) {
-		if (port == 0x03d4 && index == 0x44 && value == 3)
-			init->crtc = 1;
-	}
-}
-
-static struct nouveau_i2c_port *
-init_i2c(struct nvbios_init *init, int index)
-{
-	struct nouveau_i2c *i2c = nouveau_i2c(init->bios);
-
-	if (index == 0xff) {
-		index = NV_I2C_DEFAULT(0);
-		if (init->outp && init->outp->i2c_upper_default)
-			index = NV_I2C_DEFAULT(1);
-	} else
-	if (index < 0) {
-		if (!init->outp) {
-			if (init_exec(init))
-				error("script needs output for i2c\n");
-			return NULL;
-		}
-
-		if (index == -2 && init->outp->location) {
-			index = NV_I2C_TYPE_EXTAUX(init->outp->extdev);
-			return i2c->find_type(i2c, index);
-		}
-
-		index = init->outp->i2c_index;
-		if (init->outp->type == DCB_OUTPUT_DP)
-			index += NV_I2C_AUX(0);
-	}
-
-	return i2c->find(i2c, index);
-}
-
-static int
-init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
-{
-	struct nouveau_i2c_port *port = init_i2c(init, index);
-	if (port && init_exec(init))
-		return nv_rdi2cr(port, addr, reg);
-	return -ENODEV;
-}
-
-static int
-init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
-{
-	struct nouveau_i2c_port *port = init_i2c(init, index);
-	if (port && init_exec(init))
-		return nv_wri2cr(port, addr, reg, val);
-	return -ENODEV;
-}
-
-static u8
-init_rdauxr(struct nvbios_init *init, u32 addr)
-{
-	struct nouveau_i2c_port *port = init_i2c(init, -2);
-	u8 data;
-
-	if (port && init_exec(init)) {
-		int ret = nv_rdaux(port, addr, &data, 1);
-		if (ret == 0)
-			return data;
-		trace("auxch read failed with %d\n", ret);
-	}
-
-	return 0x00;
-}
-
-static int
-init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
-{
-	struct nouveau_i2c_port *port = init_i2c(init, -2);
-	if (port && init_exec(init)) {
-		int ret = nv_wraux(port, addr, &data, 1);
-		if (ret)
-			trace("auxch write failed with %d\n", ret);
-		return ret;
-	}
-	return -ENODEV;
-}
-
-static void
-init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
-{
-	struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
-	if (devinit->pll_set && init_exec(init)) {
-		int ret = devinit->pll_set(devinit, id, freq);
-		if (ret)
-			warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
-	}
-}
-
-/******************************************************************************
- * parsing of bios structures that are required to execute init tables
- *****************************************************************************/
-
-static u16
-init_table(struct nouveau_bios *bios, u16 *len)
-{
-	struct bit_entry bit_I;
-
-	if (!bit_entry(bios, 'I', &bit_I)) {
-		*len = bit_I.length;
-		return bit_I.offset;
-	}
-
-	if (bmp_version(bios) >= 0x0510) {
-		*len = 14;
-		return bios->bmp_offset + 75;
-	}
-
-	return 0x0000;
-}
-
-static u16
-init_table_(struct nvbios_init *init, u16 offset, const char *name)
-{
-	struct nouveau_bios *bios = init->bios;
-	u16 len, data = init_table(bios, &len);
-	if (data) {
-		if (len >= offset + 2) {
-			data = nv_ro16(bios, data + offset);
-			if (data)
-				return data;
-
-			warn("%s pointer invalid\n", name);
-			return 0x0000;
-		}
-
-		warn("init data too short for %s pointer", name);
-		return 0x0000;
-	}
-
-	warn("init data not found\n");
-	return 0x0000;
-}
-
-#define init_script_table(b) init_table_((b), 0x00, "script table")
-#define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
-#define init_macro_table(b) init_table_((b), 0x04, "macro table")
-#define init_condition_table(b) init_table_((b), 0x06, "condition table")
-#define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
-#define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
-#define init_function_table(b) init_table_((b), 0x0c, "function table")
-#define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
-
-static u16
-init_script(struct nouveau_bios *bios, int index)
-{
-	struct nvbios_init init = { .bios = bios };
-	u16 bmp_ver = bmp_version(bios), data;
-
-	if (bmp_ver && bmp_ver < 0x0510) {
-		if (index > 1 || bmp_ver < 0x0100)
-			return 0x0000;
-
-		data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18);
-		return nv_ro16(bios, data + (index * 2));
-	}
-
-	data = init_script_table(&init);
-	if (data)
-		return nv_ro16(bios, data + (index * 2));
-
-	return 0x0000;
-}
-
-static u16
-init_unknown_script(struct nouveau_bios *bios)
-{
-	u16 len, data = init_table(bios, &len);
-	if (data && len >= 16)
-		return nv_ro16(bios, data + 14);
-	return 0x0000;
-}
-
-static u8
-init_ram_restrict_group_count(struct nvbios_init *init)
-{
-	return nvbios_ramcfg_count(init->bios);
-}
-
-static u8
-init_ram_restrict(struct nvbios_init *init)
-{
-	/* This appears to be the behaviour of the VBIOS parser, and *is*
-	 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
-	 * avoid fucking up the memory controller (somehow) by reading it
-	 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
-	 *
-	 * Preserving the non-caching behaviour on earlier chipsets just
-	 * in case *not* re-reading the strap causes similar breakage.
-	 */
-	if (!init->ramcfg || init->bios->version.major < 0x70)
-		init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev);
-	return (init->ramcfg & 0x7fffffff);
-}
-
-static u8
-init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
-{
-	struct nouveau_bios *bios = init->bios;
-	u16 table = init_xlat_table(init);
-	if (table) {
-		u16 data = nv_ro16(bios, table + (index * 2));
-		if (data)
-			return nv_ro08(bios, data + offset);
-		warn("xlat table pointer %d invalid\n", index);
-	}
-	return 0x00;
-}
-
-/******************************************************************************
- * utility functions used by various init opcode handlers
- *****************************************************************************/
-
-static bool
-init_condition_met(struct nvbios_init *init, u8 cond)
-{
-	struct nouveau_bios *bios = init->bios;
-	u16 table = init_condition_table(init);
-	if (table) {
-		u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
-		u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
-		u32 val = nv_ro32(bios, table + (cond * 12) + 8);
-		trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
-		      cond, reg, msk, val);
-		return (init_rd32(init, reg) & msk) == val;
-	}
-	return false;
-}
-
-static bool
-init_io_condition_met(struct nvbios_init *init, u8 cond)
-{
-	struct nouveau_bios *bios = init->bios;
-	u16 table = init_io_condition_table(init);
-	if (table) {
-		u16 port = nv_ro16(bios, table + (cond * 5) + 0);
-		u8 index = nv_ro08(bios, table + (cond * 5) + 2);
-		u8  mask = nv_ro08(bios, table + (cond * 5) + 3);
-		u8 value = nv_ro08(bios, table + (cond * 5) + 4);
-		trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
-		      cond, port, index, mask, value);
-		return (init_rdvgai(init, port, index) & mask) == value;
-	}
-	return false;
-}
-
-static bool
-init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
-{
-	struct nouveau_bios *bios = init->bios;
-	u16 table = init_io_flag_condition_table(init);
-	if (table) {
-		u16 port = nv_ro16(bios, table + (cond * 9) + 0);
-		u8 index = nv_ro08(bios, table + (cond * 9) + 2);
-		u8  mask = nv_ro08(bios, table + (cond * 9) + 3);
-		u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
-		u16 data = nv_ro16(bios, table + (cond * 9) + 5);
-		u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
-		u8 value = nv_ro08(bios, table + (cond * 9) + 8);
-		u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
-		return (nv_ro08(bios, data + ioval) & dmask) == value;
-	}
-	return false;
-}
-
-static inline u32
-init_shift(u32 data, u8 shift)
-{
-	if (shift < 0x80)
-		return data >> shift;
-	return data << (0x100 - shift);
-}
-
-static u32
-init_tmds_reg(struct nvbios_init *init, u8 tmds)
-{
-	/* For mlv < 0x80, it is an index into a table of TMDS base addresses.
-	 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
-	 * CR58 for CR57 = 0 to index a table of offsets to the basic
-	 * 0x6808b0 address.
-	 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
-	 * CR58 for CR57 = 0 to index a table of offsets to the basic
-	 * 0x6808b0 address, and then flip the offset by 8.
-	 */
-
-	const int pramdac_offset[13] = {
-		0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
-	const u32 pramdac_table[4] = {
-		0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
-
-	if (tmds >= 0x80) {
-		if (init->outp) {
-			u32 dacoffset = pramdac_offset[init->outp->or];
-			if (tmds == 0x81)
-				dacoffset ^= 8;
-			return 0x6808b0 + dacoffset;
-		}
-
-		if (init_exec(init))
-			error("tmds opcodes need dcb\n");
-	} else {
-		if (tmds < ARRAY_SIZE(pramdac_table))
-			return pramdac_table[tmds];
-
-		error("tmds selector 0x%02x unknown\n", tmds);
-	}
-
-	return 0;
-}
-
-/******************************************************************************
- * init opcode handlers
- *****************************************************************************/
-
-/**
- * init_reserved - stub for various unknown/unused single-byte opcodes
- *
- */
-static void
-init_reserved(struct nvbios_init *init)
-{
-	u8 opcode = nv_ro08(init->bios, init->offset);
-	u8 length, i;
-
-	switch (opcode) {
-	case 0xaa:
-		length = 4;
-		break;
-	default:
-		length = 1;
-		break;
-	}
-
-	trace("RESERVED 0x%02x\t", opcode);
-	for (i = 1; i < length; i++)
-		cont(" 0x%02x", nv_ro08(init->bios, init->offset + i));
-	cont("\n");
-	init->offset += length;
-}
-
-/**
- * INIT_DONE - opcode 0x71
- *
- */
-static void
-init_done(struct nvbios_init *init)
-{
-	trace("DONE\n");
-	init->offset = 0x0000;
-}
-
-/**
- * INIT_IO_RESTRICT_PROG - opcode 0x32
- *
- */
-static void
-init_io_restrict_prog(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u16 port = nv_ro16(bios, init->offset + 1);
-	u8 index = nv_ro08(bios, init->offset + 3);
-	u8  mask = nv_ro08(bios, init->offset + 4);
-	u8 shift = nv_ro08(bios, init->offset + 5);
-	u8 count = nv_ro08(bios, init->offset + 6);
-	u32  reg = nv_ro32(bios, init->offset + 7);
-	u8 conf, i;
-
-	trace("IO_RESTRICT_PROG\tR[0x%06x] = "
-	      "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
-	      reg, port, index, mask, shift);
-	init->offset += 11;
-
-	conf = (init_rdvgai(init, port, index) & mask) >> shift;
-	for (i = 0; i < count; i++) {
-		u32 data = nv_ro32(bios, init->offset);
-
-		if (i == conf) {
-			trace("\t0x%08x *\n", data);
-			init_wr32(init, reg, data);
-		} else {
-			trace("\t0x%08x\n", data);
-		}
-
-		init->offset += 4;
-	}
-	trace("}]\n");
-}
-
-/**
- * INIT_REPEAT - opcode 0x33
- *
- */
-static void
-init_repeat(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8 count = nv_ro08(bios, init->offset + 1);
-	u16 repeat = init->repeat;
-
-	trace("REPEAT\t0x%02x\n", count);
-	init->offset += 2;
-
-	init->repeat = init->offset;
-	init->repend = init->offset;
-	while (count--) {
-		init->offset = init->repeat;
-		nvbios_exec(init);
-		if (count)
-			trace("REPEAT\t0x%02x\n", count);
-	}
-	init->offset = init->repend;
-	init->repeat = repeat;
-}
-
-/**
- * INIT_IO_RESTRICT_PLL - opcode 0x34
- *
- */
-static void
-init_io_restrict_pll(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u16 port = nv_ro16(bios, init->offset + 1);
-	u8 index = nv_ro08(bios, init->offset + 3);
-	u8  mask = nv_ro08(bios, init->offset + 4);
-	u8 shift = nv_ro08(bios, init->offset + 5);
-	s8  iofc = nv_ro08(bios, init->offset + 6);
-	u8 count = nv_ro08(bios, init->offset + 7);
-	u32  reg = nv_ro32(bios, init->offset + 8);
-	u8 conf, i;
-
-	trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
-	      "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
-	      reg, port, index, mask, shift, iofc);
-	init->offset += 12;
-
-	conf = (init_rdvgai(init, port, index) & mask) >> shift;
-	for (i = 0; i < count; i++) {
-		u32 freq = nv_ro16(bios, init->offset) * 10;
-
-		if (i == conf) {
-			trace("\t%dkHz *\n", freq);
-			if (iofc > 0 && init_io_flag_condition_met(init, iofc))
-				freq *= 2;
-			init_prog_pll(init, reg, freq);
-		} else {
-			trace("\t%dkHz\n", freq);
-		}
-
-		init->offset += 2;
-	}
-	trace("}]\n");
-}
-
-/**
- * INIT_END_REPEAT - opcode 0x36
- *
- */
-static void
-init_end_repeat(struct nvbios_init *init)
-{
-	trace("END_REPEAT\n");
-	init->offset += 1;
-
-	if (init->repeat) {
-		init->repend = init->offset;
-		init->offset = 0;
-	}
-}
-
-/**
- * INIT_COPY - opcode 0x37
- *
- */
-static void
-init_copy(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32  reg = nv_ro32(bios, init->offset + 1);
-	u8 shift = nv_ro08(bios, init->offset + 5);
-	u8 smask = nv_ro08(bios, init->offset + 6);
-	u16 port = nv_ro16(bios, init->offset + 7);
-	u8 index = nv_ro08(bios, init->offset + 9);
-	u8  mask = nv_ro08(bios, init->offset + 10);
-	u8  data;
-
-	trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
-	      "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
-	      port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
-	      (shift & 0x80) ? (0x100 - shift) : shift, smask);
-	init->offset += 11;
-
-	data  = init_rdvgai(init, port, index) & mask;
-	data |= init_shift(init_rd32(init, reg), shift) & smask;
-	init_wrvgai(init, port, index, data);
-}
-
-/**
- * INIT_NOT - opcode 0x38
- *
- */
-static void
-init_not(struct nvbios_init *init)
-{
-	trace("NOT\n");
-	init->offset += 1;
-	init_exec_inv(init);
-}
-
-/**
- * INIT_IO_FLAG_CONDITION - opcode 0x39
- *
- */
-static void
-init_io_flag_condition(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8 cond = nv_ro08(bios, init->offset + 1);
-
-	trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
-	init->offset += 2;
-
-	if (!init_io_flag_condition_met(init, cond))
-		init_exec_set(init, false);
-}
-
-/**
- * INIT_DP_CONDITION - opcode 0x3a
- *
- */
-static void
-init_dp_condition(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	struct nvbios_dpout info;
-	u8  cond = nv_ro08(bios, init->offset + 1);
-	u8  unkn = nv_ro08(bios, init->offset + 2);
-	u8  ver, hdr, cnt, len;
-	u16 data;
-
-	trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
-	init->offset += 3;
-
-	switch (cond) {
-	case 0:
-		if (init_conn(init) != DCB_CONNECTOR_eDP)
-			init_exec_set(init, false);
-		break;
-	case 1:
-	case 2:
-		if ( init->outp &&
-		    (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
-					       (init->outp->or << 0) |
-					       (init->outp->sorconf.link << 6),
-					       &ver, &hdr, &cnt, &len, &info)))
-		{
-			if (!(info.flags & cond))
-				init_exec_set(init, false);
-			break;
-		}
-
-		if (init_exec(init))
-			warn("script needs dp output table data\n");
-		break;
-	case 5:
-		if (!(init_rdauxr(init, 0x0d) & 1))
-			init_exec_set(init, false);
-		break;
-	default:
-		warn("unknown dp condition 0x%02x\n", cond);
-		break;
-	}
-}
-
-/**
- * INIT_IO_MASK_OR - opcode 0x3b
- *
- */
-static void
-init_io_mask_or(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8 index = nv_ro08(bios, init->offset + 1);
-	u8    or = init_or(init);
-	u8  data;
-
-	trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
-	init->offset += 2;
-
-	data = init_rdvgai(init, 0x03d4, index);
-	init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
-}
-
-/**
- * INIT_IO_OR - opcode 0x3c
- *
- */
-static void
-init_io_or(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8 index = nv_ro08(bios, init->offset + 1);
-	u8    or = init_or(init);
-	u8  data;
-
-	trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
-	init->offset += 2;
-
-	data = init_rdvgai(init, 0x03d4, index);
-	init_wrvgai(init, 0x03d4, index, data | (1 << or));
-}
-
-/**
- * INIT_ANDN_REG - opcode 0x47
- *
- */
-static void
-init_andn_reg(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32  reg = nv_ro32(bios, init->offset + 1);
-	u32 mask = nv_ro32(bios, init->offset + 5);
-
-	trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask);
-	init->offset += 9;
-
-	init_mask(init, reg, mask, 0);
-}
-
-/**
- * INIT_OR_REG - opcode 0x48
- *
- */
-static void
-init_or_reg(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32  reg = nv_ro32(bios, init->offset + 1);
-	u32 mask = nv_ro32(bios, init->offset + 5);
-
-	trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask);
-	init->offset += 9;
-
-	init_mask(init, reg, 0, mask);
-}
-
-/**
- * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
- *
- */
-static void
-init_idx_addr_latched(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32 creg = nv_ro32(bios, init->offset + 1);
-	u32 dreg = nv_ro32(bios, init->offset + 5);
-	u32 mask = nv_ro32(bios, init->offset + 9);
-	u32 data = nv_ro32(bios, init->offset + 13);
-	u8 count = nv_ro08(bios, init->offset + 17);
-
-	trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg);
-	trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data);
-	init->offset += 18;
-
-	while (count--) {
-		u8 iaddr = nv_ro08(bios, init->offset + 0);
-		u8 idata = nv_ro08(bios, init->offset + 1);
-
-		trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
-		init->offset += 2;
-
-		init_wr32(init, dreg, idata);
-		init_mask(init, creg, ~mask, data | iaddr);
-	}
-}
-
-/**
- * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
- *
- */
-static void
-init_io_restrict_pll2(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u16 port = nv_ro16(bios, init->offset + 1);
-	u8 index = nv_ro08(bios, init->offset + 3);
-	u8  mask = nv_ro08(bios, init->offset + 4);
-	u8 shift = nv_ro08(bios, init->offset + 5);
-	u8 count = nv_ro08(bios, init->offset + 6);
-	u32  reg = nv_ro32(bios, init->offset + 7);
-	u8  conf, i;
-
-	trace("IO_RESTRICT_PLL2\t"
-	      "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
-	      reg, port, index, mask, shift);
-	init->offset += 11;
-
-	conf = (init_rdvgai(init, port, index) & mask) >> shift;
-	for (i = 0; i < count; i++) {
-		u32 freq = nv_ro32(bios, init->offset);
-		if (i == conf) {
-			trace("\t%dkHz *\n", freq);
-			init_prog_pll(init, reg, freq);
-		} else {
-			trace("\t%dkHz\n", freq);
-		}
-		init->offset += 4;
-	}
-	trace("}]\n");
-}
-
-/**
- * INIT_PLL2 - opcode 0x4b
- *
- */
-static void
-init_pll2(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32  reg = nv_ro32(bios, init->offset + 1);
-	u32 freq = nv_ro32(bios, init->offset + 5);
-
-	trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
-	init->offset += 9;
-
-	init_prog_pll(init, reg, freq);
-}
-
-/**
- * INIT_I2C_BYTE - opcode 0x4c
- *
- */
-static void
-init_i2c_byte(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8 index = nv_ro08(bios, init->offset + 1);
-	u8  addr = nv_ro08(bios, init->offset + 2) >> 1;
-	u8 count = nv_ro08(bios, init->offset + 3);
-
-	trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
-	init->offset += 4;
-
-	while (count--) {
-		u8  reg = nv_ro08(bios, init->offset + 0);
-		u8 mask = nv_ro08(bios, init->offset + 1);
-		u8 data = nv_ro08(bios, init->offset + 2);
-		int val;
-
-		trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
-		init->offset += 3;
-
-		val = init_rdi2cr(init, index, addr, reg);
-		if (val < 0)
-			continue;
-		init_wri2cr(init, index, addr, reg, (val & mask) | data);
-	}
-}
-
-/**
- * INIT_ZM_I2C_BYTE - opcode 0x4d
- *
- */
-static void
-init_zm_i2c_byte(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8 index = nv_ro08(bios, init->offset + 1);
-	u8  addr = nv_ro08(bios, init->offset + 2) >> 1;
-	u8 count = nv_ro08(bios, init->offset + 3);
-
-	trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
-	init->offset += 4;
-
-	while (count--) {
-		u8  reg = nv_ro08(bios, init->offset + 0);
-		u8 data = nv_ro08(bios, init->offset + 1);
-
-		trace("\t[0x%02x] = 0x%02x\n", reg, data);
-		init->offset += 2;
-
-		init_wri2cr(init, index, addr, reg, data);
-	}
-
-}
-
-/**
- * INIT_ZM_I2C - opcode 0x4e
- *
- */
-static void
-init_zm_i2c(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8 index = nv_ro08(bios, init->offset + 1);
-	u8  addr = nv_ro08(bios, init->offset + 2) >> 1;
-	u8 count = nv_ro08(bios, init->offset + 3);
-	u8 data[256], i;
-
-	trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
-	init->offset += 4;
-
-	for (i = 0; i < count; i++) {
-		data[i] = nv_ro08(bios, init->offset);
-		trace("\t0x%02x\n", data[i]);
-		init->offset++;
-	}
-
-	if (init_exec(init)) {
-		struct nouveau_i2c_port *port = init_i2c(init, index);
-		struct i2c_msg msg = {
-			.addr = addr, .flags = 0, .len = count, .buf = data,
-		};
-		int ret;
-
-		if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
-			warn("i2c wr failed, %d\n", ret);
-	}
-}
-
-/**
- * INIT_TMDS - opcode 0x4f
- *
- */
-static void
-init_tmds(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8 tmds = nv_ro08(bios, init->offset + 1);
-	u8 addr = nv_ro08(bios, init->offset + 2);
-	u8 mask = nv_ro08(bios, init->offset + 3);
-	u8 data = nv_ro08(bios, init->offset + 4);
-	u32 reg = init_tmds_reg(init, tmds);
-
-	trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
-	      tmds, addr, mask, data);
-	init->offset += 5;
-
-	if (reg == 0)
-		return;
-
-	init_wr32(init, reg + 0, addr | 0x00010000);
-	init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
-	init_wr32(init, reg + 0, addr);
-}
-
-/**
- * INIT_ZM_TMDS_GROUP - opcode 0x50
- *
- */
-static void
-init_zm_tmds_group(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8  tmds = nv_ro08(bios, init->offset + 1);
-	u8 count = nv_ro08(bios, init->offset + 2);
-	u32  reg = init_tmds_reg(init, tmds);
-
-	trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
-	init->offset += 3;
-
-	while (count--) {
-		u8 addr = nv_ro08(bios, init->offset + 0);
-		u8 data = nv_ro08(bios, init->offset + 1);
-
-		trace("\t[0x%02x] = 0x%02x\n", addr, data);
-		init->offset += 2;
-
-		init_wr32(init, reg + 4, data);
-		init_wr32(init, reg + 0, addr);
-	}
-}
-
-/**
- * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
- *
- */
-static void
-init_cr_idx_adr_latch(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8 addr0 = nv_ro08(bios, init->offset + 1);
-	u8 addr1 = nv_ro08(bios, init->offset + 2);
-	u8  base = nv_ro08(bios, init->offset + 3);
-	u8 count = nv_ro08(bios, init->offset + 4);
-	u8 save0;
-
-	trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
-	init->offset += 5;
-
-	save0 = init_rdvgai(init, 0x03d4, addr0);
-	while (count--) {
-		u8 data = nv_ro08(bios, init->offset);
-
-		trace("\t\t[0x%02x] = 0x%02x\n", base, data);
-		init->offset += 1;
-
-		init_wrvgai(init, 0x03d4, addr0, base++);
-		init_wrvgai(init, 0x03d4, addr1, data);
-	}
-	init_wrvgai(init, 0x03d4, addr0, save0);
-}
-
-/**
- * INIT_CR - opcode 0x52
- *
- */
-static void
-init_cr(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8 addr = nv_ro08(bios, init->offset + 1);
-	u8 mask = nv_ro08(bios, init->offset + 2);
-	u8 data = nv_ro08(bios, init->offset + 3);
-	u8 val;
-
-	trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
-	init->offset += 4;
-
-	val = init_rdvgai(init, 0x03d4, addr) & mask;
-	init_wrvgai(init, 0x03d4, addr, val | data);
-}
-
-/**
- * INIT_ZM_CR - opcode 0x53
- *
- */
-static void
-init_zm_cr(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8 addr = nv_ro08(bios, init->offset + 1);
-	u8 data = nv_ro08(bios, init->offset + 2);
-
-	trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr,  data);
-	init->offset += 3;
-
-	init_wrvgai(init, 0x03d4, addr, data);
-}
-
-/**
- * INIT_ZM_CR_GROUP - opcode 0x54
- *
- */
-static void
-init_zm_cr_group(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8 count = nv_ro08(bios, init->offset + 1);
-
-	trace("ZM_CR_GROUP\n");
-	init->offset += 2;
-
-	while (count--) {
-		u8 addr = nv_ro08(bios, init->offset + 0);
-		u8 data = nv_ro08(bios, init->offset + 1);
-
-		trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
-		init->offset += 2;
-
-		init_wrvgai(init, 0x03d4, addr, data);
-	}
-}
-
-/**
- * INIT_CONDITION_TIME - opcode 0x56
- *
- */
-static void
-init_condition_time(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8  cond = nv_ro08(bios, init->offset + 1);
-	u8 retry = nv_ro08(bios, init->offset + 2);
-	u8  wait = min((u16)retry * 50, 100);
-
-	trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
-	init->offset += 3;
-
-	if (!init_exec(init))
-		return;
-
-	while (wait--) {
-		if (init_condition_met(init, cond))
-			return;
-		mdelay(20);
-	}
-
-	init_exec_set(init, false);
-}
-
-/**
- * INIT_LTIME - opcode 0x57
- *
- */
-static void
-init_ltime(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u16 msec = nv_ro16(bios, init->offset + 1);
-
-	trace("LTIME\t0x%04x\n", msec);
-	init->offset += 3;
-
-	if (init_exec(init))
-		mdelay(msec);
-}
-
-/**
- * INIT_ZM_REG_SEQUENCE - opcode 0x58
- *
- */
-static void
-init_zm_reg_sequence(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32 base = nv_ro32(bios, init->offset + 1);
-	u8 count = nv_ro08(bios, init->offset + 5);
-
-	trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
-	init->offset += 6;
-
-	while (count--) {
-		u32 data = nv_ro32(bios, init->offset);
-
-		trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
-		init->offset += 4;
-
-		init_wr32(init, base, data);
-		base += 4;
-	}
-}
-
-/**
- * INIT_SUB_DIRECT - opcode 0x5b
- *
- */
-static void
-init_sub_direct(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u16 addr = nv_ro16(bios, init->offset + 1);
-	u16 save;
-
-	trace("SUB_DIRECT\t0x%04x\n", addr);
-
-	if (init_exec(init)) {
-		save = init->offset;
-		init->offset = addr;
-		if (nvbios_exec(init)) {
-			error("error parsing sub-table\n");
-			return;
-		}
-		init->offset = save;
-	}
-
-	init->offset += 3;
-}
-
-/**
- * INIT_JUMP - opcode 0x5c
- *
- */
-static void
-init_jump(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u16 offset = nv_ro16(bios, init->offset + 1);
-
-	trace("JUMP\t0x%04x\n", offset);
-
-	if (init_exec(init))
-		init->offset = offset;
-	else
-		init->offset += 3;
-}
-
-/**
- * INIT_I2C_IF - opcode 0x5e
- *
- */
-static void
-init_i2c_if(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8 index = nv_ro08(bios, init->offset + 1);
-	u8  addr = nv_ro08(bios, init->offset + 2);
-	u8   reg = nv_ro08(bios, init->offset + 3);
-	u8  mask = nv_ro08(bios, init->offset + 4);
-	u8  data = nv_ro08(bios, init->offset + 5);
-	u8 value;
-
-	trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
-	      index, addr, reg, mask, data);
-	init->offset += 6;
-	init_exec_force(init, true);
-
-	value = init_rdi2cr(init, index, addr, reg);
-	if ((value & mask) != data)
-		init_exec_set(init, false);
-
-	init_exec_force(init, false);
-}
-
-/**
- * INIT_COPY_NV_REG - opcode 0x5f
- *
- */
-static void
-init_copy_nv_reg(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32  sreg = nv_ro32(bios, init->offset + 1);
-	u8  shift = nv_ro08(bios, init->offset + 5);
-	u32 smask = nv_ro32(bios, init->offset + 6);
-	u32  sxor = nv_ro32(bios, init->offset + 10);
-	u32  dreg = nv_ro32(bios, init->offset + 14);
-	u32 dmask = nv_ro32(bios, init->offset + 18);
-	u32 data;
-
-	trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
-	      "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
-	      dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
-	      (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
-	init->offset += 22;
-
-	data = init_shift(init_rd32(init, sreg), shift);
-	init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
-}
-
-/**
- * INIT_ZM_INDEX_IO - opcode 0x62
- *
- */
-static void
-init_zm_index_io(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u16 port = nv_ro16(bios, init->offset + 1);
-	u8 index = nv_ro08(bios, init->offset + 3);
-	u8  data = nv_ro08(bios, init->offset + 4);
-
-	trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
-	init->offset += 5;
-
-	init_wrvgai(init, port, index, data);
-}
-
-/**
- * INIT_COMPUTE_MEM - opcode 0x63
- *
- */
-static void
-init_compute_mem(struct nvbios_init *init)
-{
-	struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
-
-	trace("COMPUTE_MEM\n");
-	init->offset += 1;
-
-	init_exec_force(init, true);
-	if (init_exec(init) && devinit->meminit)
-		devinit->meminit(devinit);
-	init_exec_force(init, false);
-}
-
-/**
- * INIT_RESET - opcode 0x65
- *
- */
-static void
-init_reset(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32   reg = nv_ro32(bios, init->offset + 1);
-	u32 data1 = nv_ro32(bios, init->offset + 5);
-	u32 data2 = nv_ro32(bios, init->offset + 9);
-	u32 savepci19;
-
-	trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
-	init->offset += 13;
-	init_exec_force(init, true);
-
-	savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
-	init_wr32(init, reg, data1);
-	udelay(10);
-	init_wr32(init, reg, data2);
-	init_wr32(init, 0x00184c, savepci19);
-	init_mask(init, 0x001850, 0x00000001, 0x00000000);
-
-	init_exec_force(init, false);
-}
-
-/**
- * INIT_CONFIGURE_MEM - opcode 0x66
- *
- */
-static u16
-init_configure_mem_clk(struct nvbios_init *init)
-{
-	u16 mdata = bmp_mem_init_table(init->bios);
-	if (mdata)
-		mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
-	return mdata;
-}
-
-static void
-init_configure_mem(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u16 mdata, sdata;
-	u32 addr, data;
-
-	trace("CONFIGURE_MEM\n");
-	init->offset += 1;
-
-	if (bios->version.major > 2) {
-		init_done(init);
-		return;
-	}
-	init_exec_force(init, true);
-
-	mdata = init_configure_mem_clk(init);
-	sdata = bmp_sdr_seq_table(bios);
-	if (nv_ro08(bios, mdata) & 0x01)
-		sdata = bmp_ddr_seq_table(bios);
-	mdata += 6; /* skip to data */
-
-	data = init_rdvgai(init, 0x03c4, 0x01);
-	init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
-
-	for (; (addr = nv_ro32(bios, sdata)) != 0xffffffff; sdata += 4) {
-		switch (addr) {
-		case 0x10021c: /* CKE_NORMAL */
-		case 0x1002d0: /* CMD_REFRESH */
-		case 0x1002d4: /* CMD_PRECHARGE */
-			data = 0x00000001;
-			break;
-		default:
-			data = nv_ro32(bios, mdata);
-			mdata += 4;
-			if (data == 0xffffffff)
-				continue;
-			break;
-		}
-
-		init_wr32(init, addr, data);
-	}
-
-	init_exec_force(init, false);
-}
-
-/**
- * INIT_CONFIGURE_CLK - opcode 0x67
- *
- */
-static void
-init_configure_clk(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u16 mdata, clock;
-
-	trace("CONFIGURE_CLK\n");
-	init->offset += 1;
-
-	if (bios->version.major > 2) {
-		init_done(init);
-		return;
-	}
-	init_exec_force(init, true);
-
-	mdata = init_configure_mem_clk(init);
-
-	/* NVPLL */
-	clock = nv_ro16(bios, mdata + 4) * 10;
-	init_prog_pll(init, 0x680500, clock);
-
-	/* MPLL */
-	clock = nv_ro16(bios, mdata + 2) * 10;
-	if (nv_ro08(bios, mdata) & 0x01)
-		clock *= 2;
-	init_prog_pll(init, 0x680504, clock);
-
-	init_exec_force(init, false);
-}
-
-/**
- * INIT_CONFIGURE_PREINIT - opcode 0x68
- *
- */
-static void
-init_configure_preinit(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32 strap;
-
-	trace("CONFIGURE_PREINIT\n");
-	init->offset += 1;
-
-	if (bios->version.major > 2) {
-		init_done(init);
-		return;
-	}
-	init_exec_force(init, true);
-
-	strap = init_rd32(init, 0x101000);
-	strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
-	init_wrvgai(init, 0x03d4, 0x3c, strap);
-
-	init_exec_force(init, false);
-}
-
-/**
- * INIT_IO - opcode 0x69
- *
- */
-static void
-init_io(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u16 port = nv_ro16(bios, init->offset + 1);
-	u8  mask = nv_ro16(bios, init->offset + 3);
-	u8  data = nv_ro16(bios, init->offset + 4);
-	u8 value;
-
-	trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
-	init->offset += 5;
-
-	/* ummm.. yes.. should really figure out wtf this is and why it's
-	 * needed some day..  it's almost certainly wrong, but, it also
-	 * somehow makes things work...
-	 */
-	if (nv_device(init->bios)->card_type >= NV_50 &&
-	    port == 0x03c3 && data == 0x01) {
-		init_mask(init, 0x614100, 0xf0800000, 0x00800000);
-		init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
-		init_mask(init, 0x614900, 0xf0800000, 0x00800000);
-		init_mask(init, 0x000200, 0x40000000, 0x00000000);
-		mdelay(10);
-		init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
-		init_mask(init, 0x000200, 0x40000000, 0x40000000);
-		init_wr32(init, 0x614100, 0x00800018);
-		init_wr32(init, 0x614900, 0x00800018);
-		mdelay(10);
-		init_wr32(init, 0x614100, 0x10000018);
-		init_wr32(init, 0x614900, 0x10000018);
-	}
-
-	value = init_rdport(init, port) & mask;
-	init_wrport(init, port, data | value);
-}
-
-/**
- * INIT_SUB - opcode 0x6b
- *
- */
-static void
-init_sub(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8 index = nv_ro08(bios, init->offset + 1);
-	u16 addr, save;
-
-	trace("SUB\t0x%02x\n", index);
-
-	addr = init_script(bios, index);
-	if (addr && init_exec(init)) {
-		save = init->offset;
-		init->offset = addr;
-		if (nvbios_exec(init)) {
-			error("error parsing sub-table\n");
-			return;
-		}
-		init->offset = save;
-	}
-
-	init->offset += 2;
-}
-
-/**
- * INIT_RAM_CONDITION - opcode 0x6d
- *
- */
-static void
-init_ram_condition(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8  mask = nv_ro08(bios, init->offset + 1);
-	u8 value = nv_ro08(bios, init->offset + 2);
-
-	trace("RAM_CONDITION\t"
-	      "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
-	init->offset += 3;
-
-	if ((init_rd32(init, 0x100000) & mask) != value)
-		init_exec_set(init, false);
-}
-
-/**
- * INIT_NV_REG - opcode 0x6e
- *
- */
-static void
-init_nv_reg(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32  reg = nv_ro32(bios, init->offset + 1);
-	u32 mask = nv_ro32(bios, init->offset + 5);
-	u32 data = nv_ro32(bios, init->offset + 9);
-
-	trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
-	init->offset += 13;
-
-	init_mask(init, reg, ~mask, data);
-}
-
-/**
- * INIT_MACRO - opcode 0x6f
- *
- */
-static void
-init_macro(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8  macro = nv_ro08(bios, init->offset + 1);
-	u16 table;
-
-	trace("MACRO\t0x%02x\n", macro);
-
-	table = init_macro_table(init);
-	if (table) {
-		u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
-		u32 data = nv_ro32(bios, table + (macro * 8) + 4);
-		trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
-		init_wr32(init, addr, data);
-	}
-
-	init->offset += 2;
-}
-
-/**
- * INIT_RESUME - opcode 0x72
- *
- */
-static void
-init_resume(struct nvbios_init *init)
-{
-	trace("RESUME\n");
-	init->offset += 1;
-	init_exec_set(init, true);
-}
-
-/**
- * INIT_TIME - opcode 0x74
- *
- */
-static void
-init_time(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u16 usec = nv_ro16(bios, init->offset + 1);
-
-	trace("TIME\t0x%04x\n", usec);
-	init->offset += 3;
-
-	if (init_exec(init)) {
-		if (usec < 1000)
-			udelay(usec);
-		else
-			mdelay((usec + 900) / 1000);
-	}
-}
-
-/**
- * INIT_CONDITION - opcode 0x75
- *
- */
-static void
-init_condition(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8 cond = nv_ro08(bios, init->offset + 1);
-
-	trace("CONDITION\t0x%02x\n", cond);
-	init->offset += 2;
-
-	if (!init_condition_met(init, cond))
-		init_exec_set(init, false);
-}
-
-/**
- * INIT_IO_CONDITION - opcode 0x76
- *
- */
-static void
-init_io_condition(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8 cond = nv_ro08(bios, init->offset + 1);
-
-	trace("IO_CONDITION\t0x%02x\n", cond);
-	init->offset += 2;
-
-	if (!init_io_condition_met(init, cond))
-		init_exec_set(init, false);
-}
-
-/**
- * INIT_INDEX_IO - opcode 0x78
- *
- */
-static void
-init_index_io(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u16 port = nv_ro16(bios, init->offset + 1);
-	u8 index = nv_ro16(bios, init->offset + 3);
-	u8  mask = nv_ro08(bios, init->offset + 4);
-	u8  data = nv_ro08(bios, init->offset + 5);
-	u8 value;
-
-	trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
-	      port, index, mask, data);
-	init->offset += 6;
-
-	value = init_rdvgai(init, port, index) & mask;
-	init_wrvgai(init, port, index, data | value);
-}
-
-/**
- * INIT_PLL - opcode 0x79
- *
- */
-static void
-init_pll(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32  reg = nv_ro32(bios, init->offset + 1);
-	u32 freq = nv_ro16(bios, init->offset + 5) * 10;
-
-	trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
-	init->offset += 7;
-
-	init_prog_pll(init, reg, freq);
-}
-
-/**
- * INIT_ZM_REG - opcode 0x7a
- *
- */
-static void
-init_zm_reg(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32 addr = nv_ro32(bios, init->offset + 1);
-	u32 data = nv_ro32(bios, init->offset + 5);
-
-	trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
-	init->offset += 9;
-
-	if (addr == 0x000200)
-		data |= 0x00000001;
-
-	init_wr32(init, addr, data);
-}
-
-/**
- * INIT_RAM_RESTRICT_PLL - opcde 0x87
- *
- */
-static void
-init_ram_restrict_pll(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8  type = nv_ro08(bios, init->offset + 1);
-	u8 count = init_ram_restrict_group_count(init);
-	u8 strap = init_ram_restrict(init);
-	u8 cconf;
-
-	trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
-	init->offset += 2;
-
-	for (cconf = 0; cconf < count; cconf++) {
-		u32 freq = nv_ro32(bios, init->offset);
-
-		if (cconf == strap) {
-			trace("%dkHz *\n", freq);
-			init_prog_pll(init, type, freq);
-		} else {
-			trace("%dkHz\n", freq);
-		}
-
-		init->offset += 4;
-	}
-}
-
-/**
- * INIT_GPIO - opcode 0x8e
- *
- */
-static void
-init_gpio(struct nvbios_init *init)
-{
-	struct nouveau_gpio *gpio = nouveau_gpio(init->bios);
-
-	trace("GPIO\n");
-	init->offset += 1;
-
-	if (init_exec(init) && gpio && gpio->reset)
-		gpio->reset(gpio, DCB_GPIO_UNUSED);
-}
-
-/**
- * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
- *
- */
-static void
-init_ram_restrict_zm_reg_group(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32 addr = nv_ro32(bios, init->offset + 1);
-	u8  incr = nv_ro08(bios, init->offset + 5);
-	u8   num = nv_ro08(bios, init->offset + 6);
-	u8 count = init_ram_restrict_group_count(init);
-	u8 index = init_ram_restrict(init);
-	u8 i, j;
-
-	trace("RAM_RESTRICT_ZM_REG_GROUP\t"
-	      "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
-	init->offset += 7;
-
-	for (i = 0; i < num; i++) {
-		trace("\tR[0x%06x] = {\n", addr);
-		for (j = 0; j < count; j++) {
-			u32 data = nv_ro32(bios, init->offset);
-
-			if (j == index) {
-				trace("\t\t0x%08x *\n", data);
-				init_wr32(init, addr, data);
-			} else {
-				trace("\t\t0x%08x\n", data);
-			}
-
-			init->offset += 4;
-		}
-		trace("\t}\n");
-		addr += incr;
-	}
-}
-
-/**
- * INIT_COPY_ZM_REG - opcode 0x90
- *
- */
-static void
-init_copy_zm_reg(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32 sreg = nv_ro32(bios, init->offset + 1);
-	u32 dreg = nv_ro32(bios, init->offset + 5);
-
-	trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
-	init->offset += 9;
-
-	init_wr32(init, dreg, init_rd32(init, sreg));
-}
-
-/**
- * INIT_ZM_REG_GROUP - opcode 0x91
- *
- */
-static void
-init_zm_reg_group(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32 addr = nv_ro32(bios, init->offset + 1);
-	u8 count = nv_ro08(bios, init->offset + 5);
-
-	trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
-	init->offset += 6;
-
-	while (count--) {
-		u32 data = nv_ro32(bios, init->offset);
-		trace("\t0x%08x\n", data);
-		init_wr32(init, addr, data);
-		init->offset += 4;
-	}
-}
-
-/**
- * INIT_XLAT - opcode 0x96
- *
- */
-static void
-init_xlat(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32 saddr = nv_ro32(bios, init->offset + 1);
-	u8 sshift = nv_ro08(bios, init->offset + 5);
-	u8  smask = nv_ro08(bios, init->offset + 6);
-	u8  index = nv_ro08(bios, init->offset + 7);
-	u32 daddr = nv_ro32(bios, init->offset + 8);
-	u32 dmask = nv_ro32(bios, init->offset + 12);
-	u8  shift = nv_ro08(bios, init->offset + 16);
-	u32 data;
-
-	trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
-	      "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
-	      daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
-	      (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
-	init->offset += 17;
-
-	data = init_shift(init_rd32(init, saddr), sshift) & smask;
-	data = init_xlat_(init, index, data) << shift;
-	init_mask(init, daddr, ~dmask, data);
-}
-
-/**
- * INIT_ZM_MASK_ADD - opcode 0x97
- *
- */
-static void
-init_zm_mask_add(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32 addr = nv_ro32(bios, init->offset + 1);
-	u32 mask = nv_ro32(bios, init->offset + 5);
-	u32  add = nv_ro32(bios, init->offset + 9);
-	u32 data;
-
-	trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
-	init->offset += 13;
-
-	data =  init_rd32(init, addr);
-	data = (data & mask) | ((data + add) & ~mask);
-	init_wr32(init, addr, data);
-}
-
-/**
- * INIT_AUXCH - opcode 0x98
- *
- */
-static void
-init_auxch(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32 addr = nv_ro32(bios, init->offset + 1);
-	u8 count = nv_ro08(bios, init->offset + 5);
-
-	trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
-	init->offset += 6;
-
-	while (count--) {
-		u8 mask = nv_ro08(bios, init->offset + 0);
-		u8 data = nv_ro08(bios, init->offset + 1);
-		trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
-		mask = init_rdauxr(init, addr) & mask;
-		init_wrauxr(init, addr, mask | data);
-		init->offset += 2;
-	}
-}
-
-/**
- * INIT_AUXCH - opcode 0x99
- *
- */
-static void
-init_zm_auxch(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u32 addr = nv_ro32(bios, init->offset + 1);
-	u8 count = nv_ro08(bios, init->offset + 5);
-
-	trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
-	init->offset += 6;
-
-	while (count--) {
-		u8 data = nv_ro08(bios, init->offset + 0);
-		trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
-		init_wrauxr(init, addr, data);
-		init->offset += 1;
-	}
-}
-
-/**
- * INIT_I2C_LONG_IF - opcode 0x9a
- *
- */
-static void
-init_i2c_long_if(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	u8 index = nv_ro08(bios, init->offset + 1);
-	u8  addr = nv_ro08(bios, init->offset + 2) >> 1;
-	u8 reglo = nv_ro08(bios, init->offset + 3);
-	u8 reghi = nv_ro08(bios, init->offset + 4);
-	u8  mask = nv_ro08(bios, init->offset + 5);
-	u8  data = nv_ro08(bios, init->offset + 6);
-	struct nouveau_i2c_port *port;
-
-	trace("I2C_LONG_IF\t"
-	      "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
-	      index, addr, reglo, reghi, mask, data);
-	init->offset += 7;
-
-	port = init_i2c(init, index);
-	if (port) {
-		u8 i[2] = { reghi, reglo };
-		u8 o[1] = {};
-		struct i2c_msg msg[] = {
-			{ .addr = addr, .flags = 0, .len = 2, .buf = i },
-			{ .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
-		};
-		int ret;
-
-		ret = i2c_transfer(&port->adapter, msg, 2);
-		if (ret == 2 && ((o[0] & mask) == data))
-			return;
-	}
-
-	init_exec_set(init, false);
-}
-
-/**
- * INIT_GPIO_NE - opcode 0xa9
- *
- */
-static void
-init_gpio_ne(struct nvbios_init *init)
-{
-	struct nouveau_bios *bios = init->bios;
-	struct nouveau_gpio *gpio = nouveau_gpio(bios);
-	struct dcb_gpio_func func;
-	u8 count = nv_ro08(bios, init->offset + 1);
-	u8 idx = 0, ver, len;
-	u16 data, i;
-
-	trace("GPIO_NE\t");
-	init->offset += 2;
-
-	for (i = init->offset; i < init->offset + count; i++)
-		cont("0x%02x ", nv_ro08(bios, i));
-	cont("\n");
-
-	while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
-		if (func.func != DCB_GPIO_UNUSED) {
-			for (i = init->offset; i < init->offset + count; i++) {
-				if (func.func == nv_ro08(bios, i))
-					break;
-			}
-
-			trace("\tFUNC[0x%02x]", func.func);
-			if (i == (init->offset + count)) {
-				cont(" *");
-				if (init_exec(init) && gpio && gpio->reset)
-					gpio->reset(gpio, func.func);
-			}
-			cont("\n");
-		}
-	}
-
-	init->offset += count;
-}
-
-static struct nvbios_init_opcode {
-	void (*exec)(struct nvbios_init *);
-} init_opcode[] = {
-	[0x32] = { init_io_restrict_prog },
-	[0x33] = { init_repeat },
-	[0x34] = { init_io_restrict_pll },
-	[0x36] = { init_end_repeat },
-	[0x37] = { init_copy },
-	[0x38] = { init_not },
-	[0x39] = { init_io_flag_condition },
-	[0x3a] = { init_dp_condition },
-	[0x3b] = { init_io_mask_or },
-	[0x3c] = { init_io_or },
-	[0x47] = { init_andn_reg },
-	[0x48] = { init_or_reg },
-	[0x49] = { init_idx_addr_latched },
-	[0x4a] = { init_io_restrict_pll2 },
-	[0x4b] = { init_pll2 },
-	[0x4c] = { init_i2c_byte },
-	[0x4d] = { init_zm_i2c_byte },
-	[0x4e] = { init_zm_i2c },
-	[0x4f] = { init_tmds },
-	[0x50] = { init_zm_tmds_group },
-	[0x51] = { init_cr_idx_adr_latch },
-	[0x52] = { init_cr },
-	[0x53] = { init_zm_cr },
-	[0x54] = { init_zm_cr_group },
-	[0x56] = { init_condition_time },
-	[0x57] = { init_ltime },
-	[0x58] = { init_zm_reg_sequence },
-	[0x5b] = { init_sub_direct },
-	[0x5c] = { init_jump },
-	[0x5e] = { init_i2c_if },
-	[0x5f] = { init_copy_nv_reg },
-	[0x62] = { init_zm_index_io },
-	[0x63] = { init_compute_mem },
-	[0x65] = { init_reset },
-	[0x66] = { init_configure_mem },
-	[0x67] = { init_configure_clk },
-	[0x68] = { init_configure_preinit },
-	[0x69] = { init_io },
-	[0x6b] = { init_sub },
-	[0x6d] = { init_ram_condition },
-	[0x6e] = { init_nv_reg },
-	[0x6f] = { init_macro },
-	[0x71] = { init_done },
-	[0x72] = { init_resume },
-	[0x74] = { init_time },
-	[0x75] = { init_condition },
-	[0x76] = { init_io_condition },
-	[0x78] = { init_index_io },
-	[0x79] = { init_pll },
-	[0x7a] = { init_zm_reg },
-	[0x87] = { init_ram_restrict_pll },
-	[0x8c] = { init_reserved },
-	[0x8d] = { init_reserved },
-	[0x8e] = { init_gpio },
-	[0x8f] = { init_ram_restrict_zm_reg_group },
-	[0x90] = { init_copy_zm_reg },
-	[0x91] = { init_zm_reg_group },
-	[0x92] = { init_reserved },
-	[0x96] = { init_xlat },
-	[0x97] = { init_zm_mask_add },
-	[0x98] = { init_auxch },
-	[0x99] = { init_zm_auxch },
-	[0x9a] = { init_i2c_long_if },
-	[0xa9] = { init_gpio_ne },
-	[0xaa] = { init_reserved },
-};
-
-#define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
-
-int
-nvbios_exec(struct nvbios_init *init)
-{
-	init->nested++;
-	while (init->offset) {
-		u8 opcode = nv_ro08(init->bios, init->offset);
-		if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
-			error("unknown opcode 0x%02x\n", opcode);
-			return -EINVAL;
-		}
-
-		init_opcode[opcode].exec(init);
-	}
-	init->nested--;
-	return 0;
-}
-
-int
-nvbios_init(struct nouveau_subdev *subdev, bool execute)
-{
-	struct nouveau_bios *bios = nouveau_bios(subdev);
-	int ret = 0;
-	int i = -1;
-	u16 data;
-
-	if (execute)
-		nv_info(bios, "running init tables\n");
-	while (!ret && (data = (init_script(bios, ++i)))) {
-		struct nvbios_init init = {
-			.subdev = subdev,
-			.bios = bios,
-			.offset = data,
-			.outp = NULL,
-			.crtc = -1,
-			.execute = execute ? 1 : 0,
-		};
-
-		ret = nvbios_exec(&init);
-	}
-
-	/* the vbios parser will run this right after the normal init
-	 * tables, whereas the binary driver appears to run it later.
-	 */
-	if (!ret && (data = init_unknown_script(bios))) {
-		struct nvbios_init init = {
-			.subdev = subdev,
-			.bios = bios,
-			.offset = data,
-			.outp = NULL,
-			.crtc = -1,
-			.execute = execute ? 1 : 0,
-		};
-
-		ret = nvbios_exec(&init);
-	}
-
-	return ret;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/mxm.c b/drivers/gpu/drm/nouveau/core/subdev/bios/mxm.c
deleted file mode 100644
index 2610b11a99b3..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/mxm.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/mxm.h>
-
-u16
-mxm_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr)
-{
-	struct bit_entry x;
-
-	if (bit_entry(bios, 'x', &x)) {
-		nv_debug(bios, "BIT 'x' table not present\n");
-		return 0x0000;
-	}
-
-	*ver = x.version;
-	*hdr = x.length;
-	if (*ver != 1 || *hdr < 3) {
-		nv_warn(bios, "BIT 'x' table %d/%d unknown\n", *ver, *hdr);
-		return 0x0000;
-	}
-
-	return x.offset;
-}
-
-/* These map MXM v2.x digital connection values to the appropriate SOR/link,
- * hopefully they're correct for all boards within the same chipset...
- *
- * MXM v3.x VBIOS are nicer and provide pointers to these tables.
- */
-static u8 nv84_sor_map[16] = {
-	0x00, 0x12, 0x22, 0x11, 0x32, 0x31, 0x11, 0x31,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static u8 nv92_sor_map[16] = {
-	0x00, 0x12, 0x22, 0x11, 0x32, 0x31, 0x11, 0x31,
-	0x11, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static u8 nv94_sor_map[16] = {
-	0x00, 0x14, 0x24, 0x11, 0x34, 0x31, 0x11, 0x31,
-	0x11, 0x31, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static u8 nv98_sor_map[16] = {
-	0x00, 0x14, 0x12, 0x11, 0x00, 0x31, 0x11, 0x31,
-	0x11, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-u8
-mxm_sor_map(struct nouveau_bios *bios, u8 conn)
-{
-	u8  ver, hdr;
-	u16 mxm = mxm_table(bios, &ver, &hdr);
-	if (mxm && hdr >= 6) {
-		u16 map = nv_ro16(bios, mxm + 4);
-		if (map) {
-			ver = nv_ro08(bios, map);
-			if (ver == 0x10) {
-				if (conn < nv_ro08(bios, map + 3)) {
-					map += nv_ro08(bios, map + 1);
-					map += conn;
-					return nv_ro08(bios, map);
-				}
-
-				return 0x00;
-			}
-
-			nv_warn(bios, "unknown sor map v%02x\n", ver);
-		}
-	}
-
-	if (bios->version.chip == 0x84 || bios->version.chip == 0x86)
-		return nv84_sor_map[conn];
-	if (bios->version.chip == 0x92)
-		return nv92_sor_map[conn];
-	if (bios->version.chip == 0x94 || bios->version.chip == 0x96)
-		return nv94_sor_map[conn];
-	if (bios->version.chip == 0x98)
-		return nv98_sor_map[conn];
-
-	nv_warn(bios, "missing sor map\n");
-	return 0x00;
-}
-
-u8
-mxm_ddc_map(struct nouveau_bios *bios, u8 port)
-{
-	u8  ver, hdr;
-	u16 mxm = mxm_table(bios, &ver, &hdr);
-	if (mxm && hdr >= 8) {
-		u16 map = nv_ro16(bios, mxm + 6);
-		if (map) {
-			ver = nv_ro08(bios, map);
-			if (ver == 0x10) {
-				if (port < nv_ro08(bios, map + 3)) {
-					map += nv_ro08(bios, map + 1);
-					map += port;
-					return nv_ro08(bios, map);
-				}
-
-				return 0x00;
-			}
-
-			nv_warn(bios, "unknown ddc map v%02x\n", ver);
-		}
-	}
-
-	/* v2.x: directly write port as dcb i2cidx */
-	return (port << 4) | port;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/npde.c b/drivers/gpu/drm/nouveau/core/subdev/bios/npde.c
deleted file mode 100644
index d694716a166c..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/npde.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/npde.h>
-#include <subdev/bios/pcir.h>
-
-u32
-nvbios_npdeTe(struct nouveau_bios *bios, u32 base)
-{
-	struct nvbios_pcirT pcir;
-	u8  ver; u16 hdr;
-	u32 data = nvbios_pcirTp(bios, base, &ver, &hdr, &pcir);
-	if (data = (data + hdr + 0x0f) & ~0x0f, data) {
-		switch (nv_ro32(bios, data + 0x00)) {
-		case 0x4544504e: /* NPDE */
-			break;
-		default:
-			nv_debug(bios, "%08x: NPDE signature (%08x) unknown\n",
-				 data, nv_ro32(bios, data + 0x00));
-			data = 0;
-			break;
-		}
-	}
-	return data;
-}
-
-u32
-nvbios_npdeTp(struct nouveau_bios *bios, u32 base, struct nvbios_npdeT *info)
-{
-	u32 data = nvbios_npdeTe(bios, base);
-	memset(info, 0x00, sizeof(*info));
-	if (data) {
-		info->image_size = nv_ro16(bios, data + 0x08) * 512;
-		info->last = nv_ro08(bios, data + 0x0a) & 0x80;
-	}
-	return data;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/pcir.c b/drivers/gpu/drm/nouveau/core/subdev/bios/pcir.c
deleted file mode 100644
index 91dae26bc50f..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/pcir.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/pcir.h>
-
-u32
-nvbios_pcirTe(struct nouveau_bios *bios, u32 base, u8 *ver, u16 *hdr)
-{
-	u32 data = nv_ro16(bios, base + 0x18);
-	if (data) {
-		data += base;
-		switch (nv_ro32(bios, data + 0x00)) {
-		case 0x52494350: /* PCIR */
-		case 0x53494752: /* RGIS */
-		case 0x5344504e: /* NPDS */
-			*hdr = nv_ro16(bios, data + 0x0a);
-			*ver = nv_ro08(bios, data + 0x0c);
-			break;
-		default:
-			nv_debug(bios, "%08x: PCIR signature (%08x) unknown\n",
-				 data, nv_ro32(bios, data + 0x00));
-			data = 0;
-			break;
-		}
-	}
-	return data;
-}
-
-u32
-nvbios_pcirTp(struct nouveau_bios *bios, u32 base, u8 *ver, u16 *hdr,
-	      struct nvbios_pcirT *info)
-{
-	u32 data = nvbios_pcirTe(bios, base, ver, hdr);
-	memset(info, 0x00, sizeof(*info));
-	if (data) {
-		info->vendor_id = nv_ro16(bios, data + 0x04);
-		info->device_id = nv_ro16(bios, data + 0x06);
-		info->class_code[0] = nv_ro08(bios, data + 0x0d);
-		info->class_code[1] = nv_ro08(bios, data + 0x0e);
-		info->class_code[2] = nv_ro08(bios, data + 0x0f);
-		info->image_size = nv_ro16(bios, data + 0x10) * 512;
-		info->image_rev = nv_ro16(bios, data + 0x12);
-		info->image_type = nv_ro08(bios, data + 0x14);
-		info->last = nv_ro08(bios, data + 0x15) & 0x80;
-	}
-	return data;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/perf.c b/drivers/gpu/drm/nouveau/core/subdev/bios/perf.c
deleted file mode 100644
index 675e221680aa..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/perf.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Copyright 2012 Nouveau Community
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/perf.h>
-
-u16
-nvbios_perf_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr,
-		  u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
-{
-	struct bit_entry bit_P;
-	u16 perf = 0x0000;
-
-	if (!bit_entry(bios, 'P', &bit_P)) {
-		if (bit_P.version <= 2) {
-			perf = nv_ro16(bios, bit_P.offset + 0);
-			if (perf) {
-				*ver = nv_ro08(bios, perf + 0);
-				*hdr = nv_ro08(bios, perf + 1);
-				if (*ver >= 0x40 && *ver < 0x41) {
-					*cnt = nv_ro08(bios, perf + 5);
-					*len = nv_ro08(bios, perf + 2);
-					*snr = nv_ro08(bios, perf + 4);
-					*ssz = nv_ro08(bios, perf + 3);
-					return perf;
-				} else
-				if (*ver >= 0x20 && *ver < 0x40) {
-					*cnt = nv_ro08(bios, perf + 2);
-					*len = nv_ro08(bios, perf + 3);
-					*snr = nv_ro08(bios, perf + 4);
-					*ssz = nv_ro08(bios, perf + 5);
-					return perf;
-				}
-			}
-		}
-	}
-
-	if (bios->bmp_offset) {
-		if (nv_ro08(bios, bios->bmp_offset + 6) >= 0x25) {
-			perf = nv_ro16(bios, bios->bmp_offset + 0x94);
-			if (perf) {
-				*hdr = nv_ro08(bios, perf + 0);
-				*ver = nv_ro08(bios, perf + 1);
-				*cnt = nv_ro08(bios, perf + 2);
-				*len = nv_ro08(bios, perf + 3);
-				*snr = 0;
-				*ssz = 0;
-				return perf;
-			}
-		}
-	}
-
-	return 0x0000;
-}
-
-u16
-nvbios_perf_entry(struct nouveau_bios *bios, int idx,
-		  u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	u8  snr, ssz;
-	u16 perf = nvbios_perf_table(bios, ver, hdr, cnt, len, &snr, &ssz);
-	if (perf && idx < *cnt) {
-		perf = perf + *hdr + (idx * (*len + (snr * ssz)));
-		*hdr = *len;
-		*cnt = snr;
-		*len = ssz;
-		return perf;
-	}
-	return 0x0000;
-}
-
-u16
-nvbios_perfEp(struct nouveau_bios *bios, int idx,
-	      u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-	      struct nvbios_perfE *info)
-{
-	u16 perf = nvbios_perf_entry(bios, idx, ver, hdr, cnt, len);
-	memset(info, 0x00, sizeof(*info));
-	info->pstate = nv_ro08(bios, perf + 0x00);
-	switch (!!perf * *ver) {
-	case 0x12:
-	case 0x13:
-	case 0x14:
-		info->core     = nv_ro32(bios, perf + 0x01) * 10;
-		info->memory   = nv_ro32(bios, perf + 0x05) * 20;
-		info->fanspeed = nv_ro08(bios, perf + 0x37);
-		if (*hdr > 0x38)
-			info->voltage = nv_ro08(bios, perf + 0x38);
-		break;
-	case 0x21:
-	case 0x23:
-	case 0x24:
-		info->fanspeed = nv_ro08(bios, perf + 0x04);
-		info->voltage  = nv_ro08(bios, perf + 0x05);
-		info->shader   = nv_ro16(bios, perf + 0x06) * 1000;
-		info->core     = info->shader + (signed char)
-				 nv_ro08(bios, perf + 0x08) * 1000;
-		switch (nv_device(bios)->chipset) {
-		case 0x49:
-		case 0x4b:
-			info->memory = nv_ro16(bios, perf + 0x0b) * 1000;
-			break;
-		default:
-			info->memory = nv_ro16(bios, perf + 0x0b) * 2000;
-			break;
-		}
-		break;
-	case 0x25:
-		info->fanspeed = nv_ro08(bios, perf + 0x04);
-		info->voltage  = nv_ro08(bios, perf + 0x05);
-		info->core     = nv_ro16(bios, perf + 0x06) * 1000;
-		info->shader   = nv_ro16(bios, perf + 0x0a) * 1000;
-		info->memory   = nv_ro16(bios, perf + 0x0c) * 1000;
-		break;
-	case 0x30:
-		info->script   = nv_ro16(bios, perf + 0x02);
-	case 0x35:
-		info->fanspeed = nv_ro08(bios, perf + 0x06);
-		info->voltage  = nv_ro08(bios, perf + 0x07);
-		info->core     = nv_ro16(bios, perf + 0x08) * 1000;
-		info->shader   = nv_ro16(bios, perf + 0x0a) * 1000;
-		info->memory   = nv_ro16(bios, perf + 0x0c) * 1000;
-		info->vdec     = nv_ro16(bios, perf + 0x10) * 1000;
-		info->disp     = nv_ro16(bios, perf + 0x14) * 1000;
-		break;
-	case 0x40:
-		info->voltage  = nv_ro08(bios, perf + 0x02);
-		break;
-	default:
-		return 0x0000;
-	}
-	return perf;
-}
-
-u32
-nvbios_perfSe(struct nouveau_bios *bios, u32 perfE, int idx,
-	      u8 *ver, u8 *hdr, u8 cnt, u8 len)
-{
-	u32 data = 0x00000000;
-	if (idx < cnt) {
-		data = perfE + *hdr + (idx * len);
-		*hdr = len;
-	}
-	return data;
-}
-
-u32
-nvbios_perfSp(struct nouveau_bios *bios, u32 perfE, int idx,
-	      u8 *ver, u8 *hdr, u8 cnt, u8 len,
-	      struct nvbios_perfS *info)
-{
-	u32 data = nvbios_perfSe(bios, perfE, idx, ver, hdr, cnt, len);
-	memset(info, 0x00, sizeof(*info));
-	switch (!!data * *ver) {
-	case 0x40:
-		info->v40.freq = (nv_ro16(bios, data + 0x00) & 0x3fff) * 1000;
-		break;
-	default:
-		break;
-	}
-	return data;
-}
-
-int
-nvbios_perf_fan_parse(struct nouveau_bios *bios,
-		      struct nvbios_perf_fan *fan)
-{
-	u8  ver, hdr, cnt, len, snr, ssz;
-	u16 perf = nvbios_perf_table(bios, &ver, &hdr, &cnt, &len, &snr, &ssz);
-	if (!perf)
-		return -ENODEV;
-
-	if (ver >= 0x20 && ver < 0x40 && hdr > 6)
-		fan->pwm_divisor = nv_ro16(bios, perf + 6);
-	else
-		fan->pwm_divisor = 0;
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/pll.c b/drivers/gpu/drm/nouveau/core/subdev/bios/pll.c
deleted file mode 100644
index 1f76de597d4b..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/pll.c
+++ /dev/null
@@ -1,416 +0,0 @@
-/*
- * Copyright 2005-2006 Erik Waling
- * Copyright 2006 Stephane Marchesin
- * Copyright 2007-2009 Stuart Bennett
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#include <subdev/vga.h>
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/bmp.h>
-#include <subdev/bios/pll.h>
-
-struct pll_mapping {
-	u8  type;
-	u32 reg;
-};
-
-static struct pll_mapping
-nv04_pll_mapping[] = {
-	{ PLL_CORE  , 0x680500 },
-	{ PLL_MEMORY, 0x680504 },
-	{ PLL_VPLL0 , 0x680508 },
-	{ PLL_VPLL1 , 0x680520 },
-	{}
-};
-
-static struct pll_mapping
-nv40_pll_mapping[] = {
-	{ PLL_CORE  , 0x004000 },
-	{ PLL_MEMORY, 0x004020 },
-	{ PLL_VPLL0 , 0x680508 },
-	{ PLL_VPLL1 , 0x680520 },
-	{}
-};
-
-static struct pll_mapping
-nv50_pll_mapping[] = {
-	{ PLL_CORE  , 0x004028 },
-	{ PLL_SHADER, 0x004020 },
-	{ PLL_UNK03 , 0x004000 },
-	{ PLL_MEMORY, 0x004008 },
-	{ PLL_UNK40 , 0x00e810 },
-	{ PLL_UNK41 , 0x00e818 },
-	{ PLL_UNK42 , 0x00e824 },
-	{ PLL_VPLL0 , 0x614100 },
-	{ PLL_VPLL1 , 0x614900 },
-	{}
-};
-
-static struct pll_mapping
-nv84_pll_mapping[] = {
-	{ PLL_CORE  , 0x004028 },
-	{ PLL_SHADER, 0x004020 },
-	{ PLL_MEMORY, 0x004008 },
-	{ PLL_VDEC  , 0x004030 },
-	{ PLL_UNK41 , 0x00e818 },
-	{ PLL_VPLL0 , 0x614100 },
-	{ PLL_VPLL1 , 0x614900 },
-	{}
-};
-
-static u16
-pll_limits_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	struct bit_entry bit_C;
-
-	if (!bit_entry(bios, 'C', &bit_C) && bit_C.length >= 10) {
-		u16 data = nv_ro16(bios, bit_C.offset + 8);
-		if (data) {
-			*ver = nv_ro08(bios, data + 0);
-			*hdr = nv_ro08(bios, data + 1);
-			*len = nv_ro08(bios, data + 2);
-			*cnt = nv_ro08(bios, data + 3);
-			return data;
-		}
-	}
-
-	if (bmp_version(bios) >= 0x0524) {
-		u16 data = nv_ro16(bios, bios->bmp_offset + 142);
-		if (data) {
-			*ver = nv_ro08(bios, data + 0);
-			*hdr = 1;
-			*cnt = 1;
-			*len = 0x18;
-			return data;
-		}
-	}
-
-	*ver = 0x00;
-	return 0x0000;
-}
-
-static struct pll_mapping *
-pll_map(struct nouveau_bios *bios)
-{
-	switch (nv_device(bios)->card_type) {
-	case NV_04:
-	case NV_10:
-	case NV_11:
-	case NV_20:
-	case NV_30:
-		return nv04_pll_mapping;
-		break;
-	case NV_40:
-		return nv40_pll_mapping;
-	case NV_50:
-		if (nv_device(bios)->chipset == 0x50)
-			return nv50_pll_mapping;
-		else
-		if (nv_device(bios)->chipset <  0xa3 ||
-		    nv_device(bios)->chipset == 0xaa ||
-		    nv_device(bios)->chipset == 0xac)
-			return nv84_pll_mapping;
-	default:
-		return NULL;
-	}
-}
-
-static u16
-pll_map_reg(struct nouveau_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len)
-{
-	struct pll_mapping *map;
-	u8  hdr, cnt;
-	u16 data;
-
-	data = pll_limits_table(bios, ver, &hdr, &cnt, len);
-	if (data && *ver >= 0x30) {
-		data += hdr;
-		while (cnt--) {
-			if (nv_ro32(bios, data + 3) == reg) {
-				*type = nv_ro08(bios, data + 0);
-				return data;
-			}
-			data += *len;
-		}
-		return 0x0000;
-	}
-
-	map = pll_map(bios);
-	while (map->reg) {
-		if (map->reg == reg && *ver >= 0x20) {
-			u16 addr = (data += hdr);
-			*type = map->type;
-			while (cnt--) {
-				if (nv_ro32(bios, data) == map->reg)
-					return data;
-				data += *len;
-			}
-			return addr;
-		} else
-		if (map->reg == reg) {
-			*type = map->type;
-			return data + 1;
-		}
-		map++;
-	}
-
-	return 0x0000;
-}
-
-static u16
-pll_map_type(struct nouveau_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len)
-{
-	struct pll_mapping *map;
-	u8  hdr, cnt;
-	u16 data;
-
-	data = pll_limits_table(bios, ver, &hdr, &cnt, len);
-	if (data && *ver >= 0x30) {
-		data += hdr;
-		while (cnt--) {
-			if (nv_ro08(bios, data + 0) == type) {
-				*reg = nv_ro32(bios, data + 3);
-				return data;
-			}
-			data += *len;
-		}
-		return 0x0000;
-	}
-
-	map = pll_map(bios);
-	while (map->reg) {
-		if (map->type == type && *ver >= 0x20) {
-			u16 addr = (data += hdr);
-			*reg = map->reg;
-			while (cnt--) {
-				if (nv_ro32(bios, data) == map->reg)
-					return data;
-				data += *len;
-			}
-			return addr;
-		} else
-		if (map->type == type) {
-			*reg = map->reg;
-			return data + 1;
-		}
-		map++;
-	}
-
-	return 0x0000;
-}
-
-int
-nvbios_pll_parse(struct nouveau_bios *bios, u32 type, struct nvbios_pll *info)
-{
-	u8  ver, len;
-	u32 reg = type;
-	u16 data;
-
-	if (type > PLL_MAX) {
-		reg  = type;
-		data = pll_map_reg(bios, reg, &type, &ver, &len);
-	} else {
-		data = pll_map_type(bios, type, &reg, &ver, &len);
-	}
-
-	if (ver && !data)
-		return -ENOENT;
-
-	memset(info, 0, sizeof(*info));
-	info->type = type;
-	info->reg = reg;
-
-	switch (ver) {
-	case 0x00:
-		break;
-	case 0x10:
-	case 0x11:
-		info->vco1.min_freq = nv_ro32(bios, data + 0);
-		info->vco1.max_freq = nv_ro32(bios, data + 4);
-		info->vco2.min_freq = nv_ro32(bios, data + 8);
-		info->vco2.max_freq = nv_ro32(bios, data + 12);
-		info->vco1.min_inputfreq = nv_ro32(bios, data + 16);
-		info->vco2.min_inputfreq = nv_ro32(bios, data + 20);
-		info->vco1.max_inputfreq = INT_MAX;
-		info->vco2.max_inputfreq = INT_MAX;
-
-		info->max_p = 0x7;
-		info->max_p_usable = 0x6;
-
-		/* these values taken from nv30/31/36 */
-		switch (bios->version.chip) {
-		case 0x36:
-			info->vco1.min_n = 0x5;
-			break;
-		default:
-			info->vco1.min_n = 0x1;
-			break;
-		}
-		info->vco1.max_n = 0xff;
-		info->vco1.min_m = 0x1;
-		info->vco1.max_m = 0xd;
-
-		/*
-		 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
-		 * table version (apart from nv35)), N2 is compared to
-		 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
-		 * save a comparison
-		 */
-		info->vco2.min_n = 0x4;
-		switch (bios->version.chip) {
-		case 0x30:
-		case 0x35:
-			info->vco2.max_n = 0x1f;
-			break;
-		default:
-			info->vco2.max_n = 0x28;
-			break;
-		}
-		info->vco2.min_m = 0x1;
-		info->vco2.max_m = 0x4;
-		break;
-	case 0x20:
-	case 0x21:
-		info->vco1.min_freq = nv_ro16(bios, data + 4) * 1000;
-		info->vco1.max_freq = nv_ro16(bios, data + 6) * 1000;
-		info->vco2.min_freq = nv_ro16(bios, data + 8) * 1000;
-		info->vco2.max_freq = nv_ro16(bios, data + 10) * 1000;
-		info->vco1.min_inputfreq = nv_ro16(bios, data + 12) * 1000;
-		info->vco2.min_inputfreq = nv_ro16(bios, data + 14) * 1000;
-		info->vco1.max_inputfreq = nv_ro16(bios, data + 16) * 1000;
-		info->vco2.max_inputfreq = nv_ro16(bios, data + 18) * 1000;
-		info->vco1.min_n = nv_ro08(bios, data + 20);
-		info->vco1.max_n = nv_ro08(bios, data + 21);
-		info->vco1.min_m = nv_ro08(bios, data + 22);
-		info->vco1.max_m = nv_ro08(bios, data + 23);
-		info->vco2.min_n = nv_ro08(bios, data + 24);
-		info->vco2.max_n = nv_ro08(bios, data + 25);
-		info->vco2.min_m = nv_ro08(bios, data + 26);
-		info->vco2.max_m = nv_ro08(bios, data + 27);
-
-		info->max_p = nv_ro08(bios, data + 29);
-		info->max_p_usable = info->max_p;
-		if (bios->version.chip < 0x60)
-			info->max_p_usable = 0x6;
-		info->bias_p = nv_ro08(bios, data + 30);
-
-		if (len > 0x22)
-			info->refclk = nv_ro32(bios, data + 31);
-		break;
-	case 0x30:
-		data = nv_ro16(bios, data + 1);
-
-		info->vco1.min_freq = nv_ro16(bios, data + 0) * 1000;
-		info->vco1.max_freq = nv_ro16(bios, data + 2) * 1000;
-		info->vco2.min_freq = nv_ro16(bios, data + 4) * 1000;
-		info->vco2.max_freq = nv_ro16(bios, data + 6) * 1000;
-		info->vco1.min_inputfreq = nv_ro16(bios, data + 8) * 1000;
-		info->vco2.min_inputfreq = nv_ro16(bios, data + 10) * 1000;
-		info->vco1.max_inputfreq = nv_ro16(bios, data + 12) * 1000;
-		info->vco2.max_inputfreq = nv_ro16(bios, data + 14) * 1000;
-		info->vco1.min_n = nv_ro08(bios, data + 16);
-		info->vco1.max_n = nv_ro08(bios, data + 17);
-		info->vco1.min_m = nv_ro08(bios, data + 18);
-		info->vco1.max_m = nv_ro08(bios, data + 19);
-		info->vco2.min_n = nv_ro08(bios, data + 20);
-		info->vco2.max_n = nv_ro08(bios, data + 21);
-		info->vco2.min_m = nv_ro08(bios, data + 22);
-		info->vco2.max_m = nv_ro08(bios, data + 23);
-		info->max_p_usable = info->max_p = nv_ro08(bios, data + 25);
-		info->bias_p = nv_ro08(bios, data + 27);
-		info->refclk = nv_ro32(bios, data + 28);
-		break;
-	case 0x40:
-		info->refclk = nv_ro16(bios, data + 9) * 1000;
-		data = nv_ro16(bios, data + 1);
-
-		info->vco1.min_freq = nv_ro16(bios, data + 0) * 1000;
-		info->vco1.max_freq = nv_ro16(bios, data + 2) * 1000;
-		info->vco1.min_inputfreq = nv_ro16(bios, data + 4) * 1000;
-		info->vco1.max_inputfreq = nv_ro16(bios, data + 6) * 1000;
-		info->vco1.min_m = nv_ro08(bios, data + 8);
-		info->vco1.max_m = nv_ro08(bios, data + 9);
-		info->vco1.min_n = nv_ro08(bios, data + 10);
-		info->vco1.max_n = nv_ro08(bios, data + 11);
-		info->min_p = nv_ro08(bios, data + 12);
-		info->max_p = nv_ro08(bios, data + 13);
-		break;
-	default:
-		nv_error(bios, "unknown pll limits version 0x%02x\n", ver);
-		return -EINVAL;
-	}
-
-	if (!info->refclk) {
-		info->refclk = nv_device(bios)->crystal;
-		if (bios->version.chip == 0x51) {
-			u32 sel_clk = nv_rd32(bios, 0x680524);
-			if ((info->reg == 0x680508 && sel_clk & 0x20) ||
-			    (info->reg == 0x680520 && sel_clk & 0x80)) {
-				if (nv_rdvgac(bios, 0, 0x27) < 0xa3)
-					info->refclk = 200000;
-				else
-					info->refclk = 25000;
-			}
-		}
-	}
-
-	/*
-	 * By now any valid limit table ought to have set a max frequency for
-	 * vco1, so if it's zero it's either a pre limit table bios, or one
-	 * with an empty limit table (seen on nv18)
-	 */
-	if (!info->vco1.max_freq) {
-		info->vco1.max_freq = nv_ro32(bios, bios->bmp_offset + 67);
-		info->vco1.min_freq = nv_ro32(bios, bios->bmp_offset + 71);
-		if (bmp_version(bios) < 0x0506) {
-			info->vco1.max_freq = 256000;
-			info->vco1.min_freq = 128000;
-		}
-
-		info->vco1.min_inputfreq = 0;
-		info->vco1.max_inputfreq = INT_MAX;
-		info->vco1.min_n = 0x1;
-		info->vco1.max_n = 0xff;
-		info->vco1.min_m = 0x1;
-
-		if (nv_device(bios)->crystal == 13500) {
-			/* nv05 does this, nv11 doesn't, nv10 unknown */
-			if (bios->version.chip < 0x11)
-				info->vco1.min_m = 0x7;
-			info->vco1.max_m = 0xd;
-		} else {
-			if (bios->version.chip < 0x11)
-				info->vco1.min_m = 0x8;
-			info->vco1.max_m = 0xe;
-		}
-
-		if (bios->version.chip <  0x17 ||
-		    bios->version.chip == 0x1a ||
-		    bios->version.chip == 0x20)
-			info->max_p = 4;
-		else
-			info->max_p = 5;
-		info->max_p_usable = info->max_p;
-	}
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/pmu.c b/drivers/gpu/drm/nouveau/core/subdev/bios/pmu.c
deleted file mode 100644
index 66c56ba07d1b..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/pmu.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/image.h>
-#include <subdev/bios/pmu.h>
-
-static u32
-weirdo_pointer(struct nouveau_bios *bios, u32 data)
-{
-	struct nvbios_image image;
-	int idx = 0;
-	if (nvbios_image(bios, idx++, &image)) {
-		data -= image.size;
-		while (nvbios_image(bios, idx++, &image)) {
-			if (image.type == 0xe0)
-				return image.base + data;
-		}
-	}
-	return 0;
-}
-
-u32
-nvbios_pmuTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	struct bit_entry bit_p;
-	u32 data = 0;
-
-	if (!bit_entry(bios, 'p', &bit_p)) {
-		if (bit_p.version == 2 && bit_p.length >= 4)
-			data = nv_ro32(bios, bit_p.offset + 0x00);
-		if ((data = weirdo_pointer(bios, data))) {
-			*ver = nv_ro08(bios, data + 0x00); /* maybe? */
-			*hdr = nv_ro08(bios, data + 0x01);
-			*len = nv_ro08(bios, data + 0x02);
-			*cnt = nv_ro08(bios, data + 0x03);
-		}
-	}
-
-	return data;
-}
-
-u32
-nvbios_pmuTp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-	     struct nvbios_pmuT *info)
-{
-	u32 data = nvbios_pmuTe(bios, ver, hdr, cnt, len);
-	memset(info, 0x00, sizeof(*info));
-	switch (!!data * *ver) {
-	default:
-		break;
-	}
-	return data;
-}
-
-u32
-nvbios_pmuEe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr)
-{
-	u8  cnt, len;
-	u32 data = nvbios_pmuTe(bios, ver, hdr, &cnt, &len);
-	if (data && idx < cnt) {
-		data = data + *hdr + (idx * len);
-		*hdr = len;
-		return data;
-	}
-	return 0;
-}
-
-u32
-nvbios_pmuEp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
-	     struct nvbios_pmuE *info)
-{
-	u32 data = nvbios_pmuEe(bios, idx, ver, hdr);
-	memset(info, 0x00, sizeof(*info));
-	switch (!!data * *ver) {
-	default:
-		info->type = nv_ro08(bios, data + 0x00);
-		info->data = nv_ro32(bios, data + 0x02);
-		break;
-	}
-	return data;
-}
-
-bool
-nvbios_pmuRm(struct nouveau_bios *bios, u8 type, struct nvbios_pmuR *info)
-{
-	struct nvbios_pmuE pmuE;
-	u8  ver, hdr, idx = 0;
-	u32 data;
-	memset(info, 0x00, sizeof(*info));
-	while ((data = nvbios_pmuEp(bios, idx++, &ver, &hdr, &pmuE))) {
-		if ( pmuE.type == type &&
-		    (data = weirdo_pointer(bios, pmuE.data))) {
-			info->init_addr_pmu = nv_ro32(bios, data + 0x08);
-			info->args_addr_pmu = nv_ro32(bios, data + 0x0c);
-			info->boot_addr     = data + 0x30;
-			info->boot_addr_pmu = nv_ro32(bios, data + 0x10) +
-					      nv_ro32(bios, data + 0x18);
-			info->boot_size     = nv_ro32(bios, data + 0x1c) -
-					      nv_ro32(bios, data + 0x18);
-			info->code_addr     = info->boot_addr + info->boot_size;
-			info->code_addr_pmu = info->boot_addr_pmu +
-					      info->boot_size;
-			info->code_size     = nv_ro32(bios, data + 0x20);
-			info->data_addr     = data + 0x30 +
-					      nv_ro32(bios, data + 0x24);
-			info->data_addr_pmu = nv_ro32(bios, data + 0x28);
-			info->data_size     = nv_ro32(bios, data + 0x2c);
-			return true;
-		}
-	}
-	return false;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/priv.h b/drivers/gpu/drm/nouveau/core/subdev/bios/priv.h
deleted file mode 100644
index 187d225bd1e9..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/priv.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef __NVKM_BIOS_PRIV_H__
-#define __NVKM_BIOS_PRIV_H__
-
-#include <subdev/bios.h>
-
-struct nvbios_source {
-	const char *name;
-	void *(*init)(struct nouveau_bios *, const char *);
-	void  (*fini)(void *);
-	u32   (*read)(void *, u32 offset, u32 length, struct nouveau_bios *);
-	bool rw;
-};
-
-int nvbios_extend(struct nouveau_bios *, u32 length);
-int nvbios_shadow(struct nouveau_bios *);
-
-extern const struct nvbios_source nvbios_rom;
-extern const struct nvbios_source nvbios_ramin;
-extern const struct nvbios_source nvbios_acpi_fast;
-extern const struct nvbios_source nvbios_acpi_slow;
-extern const struct nvbios_source nvbios_pcirom;
-extern const struct nvbios_source nvbios_platform;
-extern const struct nvbios_source nvbios_of;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/ramcfg.c b/drivers/gpu/drm/nouveau/core/subdev/bios/ramcfg.c
deleted file mode 100644
index 1623c8dfe797..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/ramcfg.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/ramcfg.h>
-#include <subdev/bios/M0203.h>
-
-static u8
-nvbios_ramcfg_strap(struct nouveau_subdev *subdev)
-{
-	return (nv_rd32(subdev, 0x101000) & 0x0000003c) >> 2;
-}
-
-u8
-nvbios_ramcfg_count(struct nouveau_bios *bios)
-{
-	struct bit_entry bit_M;
-
-	if (!bit_entry(bios, 'M', &bit_M)) {
-		if (bit_M.version == 1 && bit_M.length >= 5)
-			return nv_ro08(bios, bit_M.offset + 2);
-		if (bit_M.version == 2 && bit_M.length >= 3)
-			return nv_ro08(bios, bit_M.offset + 0);
-	}
-
-	return 0x00;
-}
-
-u8
-nvbios_ramcfg_index(struct nouveau_subdev *subdev)
-{
-	struct nouveau_bios *bios = nouveau_bios(subdev);
-	u8 strap = nvbios_ramcfg_strap(subdev);
-	u32 xlat = 0x00000000;
-	struct bit_entry bit_M;
-	struct nvbios_M0203E M0203E;
-	u8 ver, hdr;
-
-	if (!bit_entry(bios, 'M', &bit_M)) {
-		if (bit_M.version == 1 && bit_M.length >= 5)
-			xlat = nv_ro16(bios, bit_M.offset + 3);
-		if (bit_M.version == 2 && bit_M.length >= 3) {
-			/*XXX: is M ever shorter than this?
-			 *     if not - what is xlat used for now?
-			 *     also - sigh..
-			 */
-			if (bit_M.length >= 7 &&
-			    nvbios_M0203Em(bios, strap, &ver, &hdr, &M0203E))
-				return M0203E.group;
-			xlat = nv_ro16(bios, bit_M.offset + 1);
-		}
-	}
-
-	if (xlat)
-		strap = nv_ro08(bios, xlat + strap);
-	return strap;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c b/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c
deleted file mode 100644
index c5685228c322..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/ramcfg.h>
-#include <subdev/bios/rammap.h>
-
-u32
-nvbios_rammapTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr,
-		u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
-{
-	struct bit_entry bit_P;
-	u16 rammap = 0x0000;
-
-	if (!bit_entry(bios, 'P', &bit_P)) {
-		if (bit_P.version == 2)
-			rammap = nv_ro16(bios, bit_P.offset + 4);
-
-		if (rammap) {
-			*ver = nv_ro08(bios, rammap + 0);
-			switch (*ver) {
-			case 0x10:
-			case 0x11:
-				*hdr = nv_ro08(bios, rammap + 1);
-				*cnt = nv_ro08(bios, rammap + 5);
-				*len = nv_ro08(bios, rammap + 2);
-				*snr = nv_ro08(bios, rammap + 4);
-				*ssz = nv_ro08(bios, rammap + 3);
-				return rammap;
-			default:
-				break;
-			}
-		}
-	}
-
-	return 0x0000;
-}
-
-u32
-nvbios_rammapEe(struct nouveau_bios *bios, int idx,
-		u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	u8  snr, ssz;
-	u16 rammap = nvbios_rammapTe(bios, ver, hdr, cnt, len, &snr, &ssz);
-	if (rammap && idx < *cnt) {
-		rammap = rammap + *hdr + (idx * (*len + (snr * ssz)));
-		*hdr = *len;
-		*cnt = snr;
-		*len = ssz;
-		return rammap;
-	}
-	return 0x0000;
-}
-
-u32
-nvbios_rammapEp(struct nouveau_bios *bios, int idx,
-		u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		struct nvbios_ramcfg *p)
-{
-	u32 data = nvbios_rammapEe(bios, idx, ver, hdr, cnt, len), temp;
-	memset(p, 0x00, sizeof(*p));
-	p->rammap_ver = *ver;
-	p->rammap_hdr = *hdr;
-	switch (!!data * *ver) {
-	case 0x10:
-		p->rammap_min      =  nv_ro16(bios, data + 0x00);
-		p->rammap_max      =  nv_ro16(bios, data + 0x02);
-		p->rammap_10_04_02 = (nv_ro08(bios, data + 0x04) & 0x02) >> 1;
-		p->rammap_10_04_08 = (nv_ro08(bios, data + 0x04) & 0x08) >> 3;
-		break;
-	case 0x11:
-		p->rammap_min      =  nv_ro16(bios, data + 0x00);
-		p->rammap_max      =  nv_ro16(bios, data + 0x02);
-		p->rammap_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0;
-		p->rammap_11_08_0c = (nv_ro08(bios, data + 0x08) & 0x0c) >> 2;
-		p->rammap_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4;
-		temp = nv_ro32(bios, data + 0x09);
-		p->rammap_11_09_01ff = (temp & 0x000001ff) >> 0;
-		p->rammap_11_0a_03fe = (temp & 0x0003fe00) >> 9;
-		p->rammap_11_0a_0400 = (temp & 0x00040000) >> 18;
-		p->rammap_11_0a_0800 = (temp & 0x00080000) >> 19;
-		p->rammap_11_0b_01f0 = (temp & 0x01f00000) >> 20;
-		p->rammap_11_0b_0200 = (temp & 0x02000000) >> 25;
-		p->rammap_11_0b_0400 = (temp & 0x04000000) >> 26;
-		p->rammap_11_0b_0800 = (temp & 0x08000000) >> 27;
-		p->rammap_11_0d    =  nv_ro08(bios, data + 0x0d);
-		p->rammap_11_0e    =  nv_ro08(bios, data + 0x0e);
-		p->rammap_11_0f    =  nv_ro08(bios, data + 0x0f);
-		p->rammap_11_11_0c = (nv_ro08(bios, data + 0x11) & 0x0c) >> 2;
-		break;
-	default:
-		data = 0;
-		break;
-	}
-	return data;
-}
-
-u32
-nvbios_rammapEm(struct nouveau_bios *bios, u16 mhz,
-		u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		struct nvbios_ramcfg *info)
-{
-	int idx = 0;
-	u32 data;
-	while ((data = nvbios_rammapEp(bios, idx++, ver, hdr, cnt, len, info))) {
-		if (mhz >= info->rammap_min && mhz <= info->rammap_max)
-			break;
-	}
-	return data;
-}
-
-u32
-nvbios_rammapSe(struct nouveau_bios *bios, u32 data,
-		u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
-		u8 *ver, u8 *hdr)
-{
-	if (idx < ecnt) {
-		data = data + ehdr + (idx * elen);
-		*ver = ever;
-		*hdr = elen;
-		return data;
-	}
-	return 0;
-}
-
-u32
-nvbios_rammapSp(struct nouveau_bios *bios, u32 data,
-		u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
-		u8 *ver, u8 *hdr, struct nvbios_ramcfg *p)
-{
-	data = nvbios_rammapSe(bios, data, ever, ehdr, ecnt, elen, idx, ver, hdr);
-	p->ramcfg_ver = *ver;
-	p->ramcfg_hdr = *hdr;
-	switch (!!data * *ver) {
-	case 0x10:
-		p->ramcfg_timing   =  nv_ro08(bios, data + 0x01);
-		p->ramcfg_10_02_01 = (nv_ro08(bios, data + 0x02) & 0x01) >> 0;
-		p->ramcfg_10_02_02 = (nv_ro08(bios, data + 0x02) & 0x02) >> 1;
-		p->ramcfg_10_02_04 = (nv_ro08(bios, data + 0x02) & 0x04) >> 2;
-		p->ramcfg_10_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3;
-		p->ramcfg_10_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4;
-		p->ramcfg_10_02_20 = (nv_ro08(bios, data + 0x02) & 0x20) >> 5;
-		p->ramcfg_10_DLLoff = (nv_ro08(bios, data + 0x02) & 0x40) >> 6;
-		p->ramcfg_10_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0;
-		p->ramcfg_10_04_01 = (nv_ro08(bios, data + 0x04) & 0x01) >> 0;
-		p->ramcfg_10_05    = (nv_ro08(bios, data + 0x05) & 0xff) >> 0;
-		p->ramcfg_10_06    = (nv_ro08(bios, data + 0x06) & 0xff) >> 0;
-		p->ramcfg_10_07    = (nv_ro08(bios, data + 0x07) & 0xff) >> 0;
-		p->ramcfg_10_08    = (nv_ro08(bios, data + 0x08) & 0xff) >> 0;
-		p->ramcfg_10_09_0f = (nv_ro08(bios, data + 0x09) & 0x0f) >> 0;
-		p->ramcfg_10_09_f0 = (nv_ro08(bios, data + 0x09) & 0xf0) >> 4;
-		break;
-	case 0x11:
-		p->ramcfg_timing   =  nv_ro08(bios, data + 0x00);
-		p->ramcfg_11_01_01 = (nv_ro08(bios, data + 0x01) & 0x01) >> 0;
-		p->ramcfg_11_01_02 = (nv_ro08(bios, data + 0x01) & 0x02) >> 1;
-		p->ramcfg_11_01_04 = (nv_ro08(bios, data + 0x01) & 0x04) >> 2;
-		p->ramcfg_11_01_08 = (nv_ro08(bios, data + 0x01) & 0x08) >> 3;
-		p->ramcfg_11_01_10 = (nv_ro08(bios, data + 0x01) & 0x10) >> 4;
-		p->ramcfg_11_01_20 = (nv_ro08(bios, data + 0x01) & 0x20) >> 5;
-		p->ramcfg_11_01_40 = (nv_ro08(bios, data + 0x01) & 0x40) >> 6;
-		p->ramcfg_11_01_80 = (nv_ro08(bios, data + 0x01) & 0x80) >> 7;
-		p->ramcfg_11_02_03 = (nv_ro08(bios, data + 0x02) & 0x03) >> 0;
-		p->ramcfg_11_02_04 = (nv_ro08(bios, data + 0x02) & 0x04) >> 2;
-		p->ramcfg_11_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3;
-		p->ramcfg_11_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4;
-		p->ramcfg_11_02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6;
-		p->ramcfg_11_02_80 = (nv_ro08(bios, data + 0x02) & 0x80) >> 7;
-		p->ramcfg_11_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0;
-		p->ramcfg_11_03_30 = (nv_ro08(bios, data + 0x03) & 0x30) >> 4;
-		p->ramcfg_11_03_c0 = (nv_ro08(bios, data + 0x03) & 0xc0) >> 6;
-		p->ramcfg_11_03_f0 = (nv_ro08(bios, data + 0x03) & 0xf0) >> 4;
-		p->ramcfg_11_04    = (nv_ro08(bios, data + 0x04) & 0xff) >> 0;
-		p->ramcfg_11_06    = (nv_ro08(bios, data + 0x06) & 0xff) >> 0;
-		p->ramcfg_11_07_02 = (nv_ro08(bios, data + 0x07) & 0x02) >> 1;
-		p->ramcfg_11_07_04 = (nv_ro08(bios, data + 0x07) & 0x04) >> 2;
-		p->ramcfg_11_07_08 = (nv_ro08(bios, data + 0x07) & 0x08) >> 3;
-		p->ramcfg_11_07_10 = (nv_ro08(bios, data + 0x07) & 0x10) >> 4;
-		p->ramcfg_11_07_40 = (nv_ro08(bios, data + 0x07) & 0x40) >> 6;
-		p->ramcfg_11_07_80 = (nv_ro08(bios, data + 0x07) & 0x80) >> 7;
-		p->ramcfg_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0;
-		p->ramcfg_11_08_02 = (nv_ro08(bios, data + 0x08) & 0x02) >> 1;
-		p->ramcfg_11_08_04 = (nv_ro08(bios, data + 0x08) & 0x04) >> 2;
-		p->ramcfg_11_08_08 = (nv_ro08(bios, data + 0x08) & 0x08) >> 3;
-		p->ramcfg_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4;
-		p->ramcfg_11_08_20 = (nv_ro08(bios, data + 0x08) & 0x20) >> 5;
-		p->ramcfg_11_09    = (nv_ro08(bios, data + 0x09) & 0xff) >> 0;
-		break;
-	default:
-		data = 0;
-		break;
-	}
-	return data;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/shadow.c b/drivers/gpu/drm/nouveau/core/subdev/bios/shadow.c
deleted file mode 100644
index bb9e0018d936..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/shadow.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "priv.h"
-#include <core/option.h>
-#include <subdev/bios/image.h>
-
-struct shadow {
-	struct nouveau_oclass base;
-	u32 skip;
-	const struct nvbios_source *func;
-	void *data;
-	u32 size;
-	int score;
-};
-
-static bool
-shadow_fetch(struct nouveau_bios *bios, u32 upto)
-{
-	struct shadow *mthd = (void *)nv_object(bios)->oclass;
-	const u32 limit = (upto + 3) & ~3;
-	const u32 start = bios->size;
-	void *data = mthd->data;
-	if (nvbios_extend(bios, limit) > 0) {
-		u32 read = mthd->func->read(data, start, limit - start, bios);
-		bios->size = start + read;
-	}
-	return bios->size >= limit;
-}
-
-static u8
-shadow_rd08(struct nouveau_object *object, u64 addr)
-{
-	struct nouveau_bios *bios = (void *)object;
-	if (shadow_fetch(bios, addr + 1))
-		return bios->data[addr];
-	return 0x00;
-}
-
-static u16
-shadow_rd16(struct nouveau_object *object, u64 addr)
-{
-	struct nouveau_bios *bios = (void *)object;
-	if (shadow_fetch(bios, addr + 2))
-		return get_unaligned_le16(&bios->data[addr]);
-	return 0x0000;
-}
-
-static u32
-shadow_rd32(struct nouveau_object *object, u64 addr)
-{
-	struct nouveau_bios *bios = (void *)object;
-	if (shadow_fetch(bios, addr + 4))
-		return get_unaligned_le32(&bios->data[addr]);
-	return 0x00000000;
-}
-
-static struct nouveau_oclass
-shadow_class = {
-	.handle = NV_SUBDEV(VBIOS, 0x00),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.rd08 = shadow_rd08,
-		.rd16 = shadow_rd16,
-		.rd32 = shadow_rd32,
-	},
-};
-
-static int
-shadow_image(struct nouveau_bios *bios, int idx, struct shadow *mthd)
-{
-	struct nvbios_image image;
-	int score = 1;
-
-	if (!nvbios_image(bios, idx, &image)) {
-		nv_debug(bios, "image %d invalid\n", idx);
-		return 0;
-	}
-	nv_debug(bios, "%08x: type %02x, %d bytes\n",
-		 image.base, image.type, image.size);
-
-	if (!shadow_fetch(bios, image.size)) {
-		nv_debug(bios, "%08x: fetch failed\n", image.base);
-		return 0;
-	}
-
-	switch (image.type) {
-	case 0x00:
-		if (nvbios_checksum(&bios->data[image.base], image.size)) {
-			nv_debug(bios, "%08x: checksum failed\n", image.base);
-			if (mthd->func->rw)
-				score += 1;
-			score += 1;
-		} else {
-			score += 3;
-		}
-		break;
-	default:
-		score += 3;
-		break;
-	}
-
-	if (!image.last)
-		score += shadow_image(bios, idx + 1, mthd);
-	return score;
-}
-
-static int
-shadow_score(struct nouveau_bios *bios, struct shadow *mthd)
-{
-	struct nouveau_oclass *oclass = nv_object(bios)->oclass;
-	int score;
-	nv_object(bios)->oclass = &mthd->base;
-	score = shadow_image(bios, 0, mthd);
-	nv_object(bios)->oclass = oclass;
-	return score;
-
-}
-
-static int
-shadow_method(struct nouveau_bios *bios, struct shadow *mthd, const char *name)
-{
-	const struct nvbios_source *func = mthd->func;
-	if (func->name) {
-		nv_debug(bios, "trying %s...\n", name ? name : func->name);
-		if (func->init) {
-			mthd->data = func->init(bios, name);
-			if (IS_ERR(mthd->data)) {
-				mthd->data = NULL;
-				return 0;
-			}
-		}
-		mthd->score = shadow_score(bios, mthd);
-		if (func->fini)
-			func->fini(mthd->data);
-		nv_debug(bios, "scored %d\n", mthd->score);
-		mthd->data = bios->data;
-		mthd->size = bios->size;
-		bios->data  = NULL;
-		bios->size  = 0;
-	}
-	return mthd->score;
-}
-
-static u32
-shadow_fw_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
-{
-	const struct firmware *fw = data;
-	if (offset + length <= fw->size) {
-		memcpy(bios->data + offset, fw->data + offset, length);
-		return length;
-	}
-	return 0;
-}
-
-static void *
-shadow_fw_init(struct nouveau_bios *bios, const char *name)
-{
-	struct device *dev = &nv_device(bios)->pdev->dev;
-	const struct firmware *fw;
-	int ret = request_firmware(&fw, name, dev);
-	if (ret)
-		return ERR_PTR(-ENOENT);
-	return (void *)fw;
-}
-
-static const struct nvbios_source
-shadow_fw = {
-	.name = "firmware",
-	.init = shadow_fw_init,
-	.fini = (void(*)(void *))release_firmware,
-	.read = shadow_fw_read,
-	.rw = false,
-};
-
-int
-nvbios_shadow(struct nouveau_bios *bios)
-{
-	struct shadow mthds[] = {
-		{ shadow_class, 0, &nvbios_of },
-		{ shadow_class, 0, &nvbios_ramin },
-		{ shadow_class, 0, &nvbios_rom },
-		{ shadow_class, 0, &nvbios_acpi_fast },
-		{ shadow_class, 4, &nvbios_acpi_slow },
-		{ shadow_class, 1, &nvbios_pcirom },
-		{ shadow_class, 1, &nvbios_platform },
-		{ shadow_class }
-	}, *mthd = mthds, *best = NULL;
-	const char *optarg;
-	char *source;
-	int optlen;
-
-	/* handle user-specified bios source */
-	optarg = nouveau_stropt(nv_device(bios)->cfgopt, "NvBios", &optlen);
-	source = optarg ? kstrndup(optarg, optlen, GFP_KERNEL) : NULL;
-	if (source) {
-		/* try to match one of the built-in methods */
-		for (mthd = mthds; mthd->func; mthd++) {
-			if (mthd->func->name &&
-			    !strcasecmp(source, mthd->func->name)) {
-				best = mthd;
-				if (shadow_method(bios, mthd, NULL))
-					break;
-			}
-		}
-
-		/* otherwise, attempt to load as firmware */
-		if (!best && (best = mthd)) {
-			mthd->func = &shadow_fw;
-			shadow_method(bios, mthd, source);
-			mthd->func = NULL;
-		}
-
-		if (!best->score) {
-			nv_error(bios, "%s invalid\n", source);
-			kfree(source);
-			source = NULL;
-		}
-	}
-
-	/* scan all potential bios sources, looking for best image */
-	if (!best || !best->score) {
-		for (mthd = mthds, best = mthd; mthd->func; mthd++) {
-			if (!mthd->skip || best->score < mthd->skip) {
-				if (shadow_method(bios, mthd, NULL)) {
-					if (mthd->score > best->score)
-						best = mthd;
-				}
-			}
-		}
-	}
-
-	/* cleanup the ones we didn't use */
-	for (mthd = mthds; mthd->func; mthd++) {
-		if (mthd != best)
-			kfree(mthd->data);
-	}
-
-	if (!best->score) {
-		nv_fatal(bios, "unable to locate usable image\n");
-		return -EINVAL;
-	}
-
-	nv_info(bios, "using image from %s\n", best->func ?
-		best->func->name : source);
-	bios->data = best->data;
-	bios->size = best->size;
-	kfree(source);
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowacpi.c b/drivers/gpu/drm/nouveau/core/subdev/bios/shadowacpi.c
deleted file mode 100644
index bc130c12ec06..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowacpi.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "priv.h"
-
-#if defined(CONFIG_ACPI) && defined(CONFIG_X86)
-int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
-bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
-#else
-static inline bool
-nouveau_acpi_rom_supported(struct pci_dev *pdev)
-{
-	return false;
-}
-
-static inline int
-nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len)
-{
-	return -EINVAL;
-}
-#endif
-
-/* This version of the shadow function disobeys the ACPI spec and tries
- * to fetch in units of more than 4KiB at a time.  This is a LOT faster
- * on some systems, such as Lenovo W530.
- */
-static u32
-acpi_read_fast(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
-{
-	u32 limit = (offset + length + 0xfff) & ~0xfff;
-	u32 start = offset & ~0x00000fff;
-	u32 fetch = limit - start;
-
-	if (nvbios_extend(bios, limit) > 0) {
-		int ret = nouveau_acpi_get_bios_chunk(bios->data, start, fetch);
-		if (ret == fetch)
-			return fetch;
-	}
-
-	return 0;
-}
-
-/* Other systems, such as the one in fdo#55948, will report a success
- * but only return 4KiB of data.  The common bios fetching logic will
- * detect an invalid image, and fall back to this version of the read
- * function.
- */
-static u32
-acpi_read_slow(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
-{
-	u32 limit = (offset + length + 0xfff) & ~0xfff;
-	u32 start = offset & ~0xfff;
-	u32 fetch = 0;
-
-	if (nvbios_extend(bios, limit) > 0) {
-		while (start + fetch < limit) {
-			int ret = nouveau_acpi_get_bios_chunk(bios->data,
-							      start + fetch,
-							      0x1000);
-			if (ret != 0x1000)
-				break;
-			fetch += 0x1000;
-		}
-	}
-
-	return fetch;
-}
-
-static void *
-acpi_init(struct nouveau_bios *bios, const char *name)
-{
-	if (!nouveau_acpi_rom_supported(nv_device(bios)->pdev))
-		return ERR_PTR(-ENODEV);
-	return NULL;
-}
-
-const struct nvbios_source
-nvbios_acpi_fast = {
-	.name = "ACPI",
-	.init = acpi_init,
-	.read = acpi_read_fast,
-	.rw = false,
-};
-
-const struct nvbios_source
-nvbios_acpi_slow = {
-	.name = "ACPI",
-	.init = acpi_init,
-	.read = acpi_read_slow,
-	.rw = false,
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowof.c b/drivers/gpu/drm/nouveau/core/subdev/bios/shadowof.c
deleted file mode 100644
index 3abe487a6025..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowof.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "priv.h"
-
-#if defined(__powerpc__)
-struct priv {
-	const void __iomem *data;
-	int size;
-};
-
-static u32
-of_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
-{
-	struct priv *priv = data;
-	if (offset + length <= priv->size) {
-		memcpy_fromio(bios->data + offset, priv->data + offset, length);
-		return length;
-	}
-	return 0;
-}
-
-static void *
-of_init(struct nouveau_bios *bios, const char *name)
-{
-	struct pci_dev *pdev = nv_device(bios)->pdev;
-	struct device_node *dn;
-	struct priv *priv;
-	if (!(dn = pci_device_to_OF_node(pdev)))
-		return ERR_PTR(-ENODEV);
-	if (!(priv = kzalloc(sizeof(*priv), GFP_KERNEL)))
-		return ERR_PTR(-ENOMEM);
-	if ((priv->data = of_get_property(dn, "NVDA,BMP", &priv->size)))
-		return priv;
-	kfree(priv);
-	return ERR_PTR(-EINVAL);
-}
-
-const struct nvbios_source
-nvbios_of = {
-	.name = "OpenFirmware",
-	.init = of_init,
-	.fini = (void(*)(void *))kfree,
-	.read = of_read,
-	.rw = false,
-};
-#else
-const struct nvbios_source
-nvbios_of = {
-};
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowpci.c b/drivers/gpu/drm/nouveau/core/subdev/bios/shadowpci.c
deleted file mode 100644
index 1d0389c0abef..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowpci.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "priv.h"
-
-struct priv {
-	struct pci_dev *pdev;
-	void __iomem *rom;
-	size_t size;
-};
-
-static u32
-pcirom_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
-{
-	struct priv *priv = data;
-	if (offset + length <= priv->size) {
-		memcpy_fromio(bios->data + offset, priv->rom + offset, length);
-		return length;
-	}
-	return 0;
-}
-
-static void
-pcirom_fini(void *data)
-{
-	struct priv *priv = data;
-	pci_unmap_rom(priv->pdev, priv->rom);
-	pci_disable_rom(priv->pdev);
-	kfree(priv);
-}
-
-static void *
-pcirom_init(struct nouveau_bios *bios, const char *name)
-{
-	struct pci_dev *pdev = nv_device(bios)->pdev;
-	struct priv *priv = NULL;
-	int ret;
-
-	if (!(ret = pci_enable_rom(pdev))) {
-		if (ret = -ENOMEM,
-		    (priv = kmalloc(sizeof(*priv), GFP_KERNEL))) {
-			if (ret = -EFAULT,
-			    (priv->rom = pci_map_rom(pdev, &priv->size))) {
-				priv->pdev = pdev;
-				return priv;
-			}
-			kfree(priv);
-		}
-		pci_disable_rom(pdev);
-	}
-
-	return ERR_PTR(ret);
-}
-
-const struct nvbios_source
-nvbios_pcirom = {
-	.name = "PCIROM",
-	.init = pcirom_init,
-	.fini = pcirom_fini,
-	.read = pcirom_read,
-	.rw = true,
-};
-
-static void *
-platform_init(struct nouveau_bios *bios, const char *name)
-{
-	struct pci_dev *pdev = nv_device(bios)->pdev;
-	struct priv *priv;
-	int ret = -ENOMEM;
-
-	if ((priv = kmalloc(sizeof(*priv), GFP_KERNEL))) {
-		if (ret = -ENODEV,
-		    (priv->rom = pci_platform_rom(pdev, &priv->size)))
-			return priv;
-		kfree(priv);
-	}
-
-	return ERR_PTR(ret);
-}
-
-const struct nvbios_source
-nvbios_platform = {
-	.name = "PLATFORM",
-	.init = platform_init,
-	.fini = (void(*)(void *))kfree,
-	.read = pcirom_read,
-	.rw = true,
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowramin.c b/drivers/gpu/drm/nouveau/core/subdev/bios/shadowramin.c
deleted file mode 100644
index a7a890fad1e5..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowramin.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "priv.h"
-
-struct priv {
-	struct nouveau_bios *bios;
-	u32 bar0;
-};
-
-static u32
-pramin_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
-{
-	u32 i;
-	if (offset + length <= 0x00100000) {
-		for (i = offset; i < offset + length; i += 4)
-			*(u32 *)&bios->data[i] = nv_rd32(bios, 0x700000 + i);
-		return length;
-	}
-	return 0;
-}
-
-static void
-pramin_fini(void *data)
-{
-	struct priv *priv = data;
-	if (priv) {
-		nv_wr32(priv->bios, 0x001700, priv->bar0);
-		kfree(priv);
-	}
-}
-
-static void *
-pramin_init(struct nouveau_bios *bios, const char *name)
-{
-	struct priv *priv = NULL;
-	u64 addr = 0;
-
-	/* PRAMIN always potentially available prior to nv50 */
-	if (nv_device(bios)->card_type < NV_50)
-		return NULL;
-
-	/* we can't get the bios image pointer without PDISP */
-	if (nv_device(bios)->card_type >= GM100)
-		addr = nv_rd32(bios, 0x021c04);
-	else
-	if (nv_device(bios)->card_type >= NV_C0)
-		addr = nv_rd32(bios, 0x022500);
-	if (addr & 0x00000001) {
-		nv_debug(bios, "... display disabled\n");
-		return ERR_PTR(-ENODEV);
-	}
-
-	/* check that the window is enabled and in vram, particularly
-	 * important as we don't want to be touching vram on an
-	 * uninitialised board
-	 */
-	addr = nv_rd32(bios, 0x619f04);
-	if (!(addr & 0x00000008)) {
-		nv_debug(bios, "... not enabled\n");
-		return ERR_PTR(-ENODEV);
-	}
-	if ( (addr & 0x00000003) != 1) {
-		nv_debug(bios, "... not in vram\n");
-		return ERR_PTR(-ENODEV);
-	}
-
-	/* some alternate method inherited from xf86-video-nv... */
-	addr = (addr & 0xffffff00) << 8;
-	if (!addr) {
-		addr  = (u64)nv_rd32(bios, 0x001700) << 16;
-		addr += 0xf0000;
-	}
-
-	/* modify bar0 PRAMIN window to cover the bios image */
-	if (!(priv = kmalloc(sizeof(*priv), GFP_KERNEL))) {
-		nv_error(bios, "... out of memory\n");
-		return ERR_PTR(-ENOMEM);
-	}
-
-	priv->bios = bios;
-	priv->bar0 = nv_rd32(bios, 0x001700);
-	nv_wr32(bios, 0x001700, addr >> 16);
-	return priv;
-}
-
-const struct nvbios_source
-nvbios_ramin = {
-	.name = "PRAMIN",
-	.init = pramin_init,
-	.fini = pramin_fini,
-	.read = pramin_read,
-	.rw = true,
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowrom.c b/drivers/gpu/drm/nouveau/core/subdev/bios/shadowrom.c
deleted file mode 100644
index b7992bc3ffa5..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowrom.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "priv.h"
-
-static u32
-prom_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
-{
-	u32 i;
-	if (offset + length <= 0x00100000) {
-		for (i = offset; i < offset + length; i += 4)
-			*(u32 *)&bios->data[i] = nv_rd32(bios, 0x300000 + i);
-		return length;
-	}
-	return 0;
-}
-
-static void
-prom_fini(void *data)
-{
-	struct nouveau_bios *bios = data;
-	if (nv_device(bios)->card_type < NV_50)
-		nv_mask(bios, 0x001850, 0x00000001, 0x00000001);
-	else
-		nv_mask(bios, 0x088050, 0x00000001, 0x00000001);
-}
-
-static void *
-prom_init(struct nouveau_bios *bios, const char *name)
-{
-	if (nv_device(bios)->card_type < NV_50) {
-		if (nv_device(bios)->card_type == NV_40 &&
-		    nv_device(bios)->chipset >= 0x4c)
-			return ERR_PTR(-ENODEV);
-		nv_mask(bios, 0x001850, 0x00000001, 0x00000000);
-	} else {
-		nv_mask(bios, 0x088050, 0x00000001, 0x00000000);
-	}
-	return bios;
-}
-
-const struct nvbios_source
-nvbios_rom = {
-	.name = "PROM",
-	.init = prom_init,
-	.fini = prom_fini,
-	.read = prom_read,
-	.rw = false,
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/therm.c b/drivers/gpu/drm/nouveau/core/subdev/bios/therm.c
deleted file mode 100644
index d15854094078..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/therm.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * Copyright 2012 Nouveau Community
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/therm.h>
-
-static u16
-therm_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt)
-{
-	struct bit_entry bit_P;
-	u16 therm = 0;
-
-	if (!bit_entry(bios, 'P', &bit_P)) {
-		if (bit_P.version == 1)
-			therm = nv_ro16(bios, bit_P.offset + 12);
-		else if (bit_P.version == 2)
-			therm = nv_ro16(bios, bit_P.offset + 16);
-		else
-			nv_error(bios,
-				"unknown offset for thermal in BIT P %d\n",
-				bit_P.version);
-	}
-
-	/* exit now if we haven't found the thermal table */
-	if (!therm)
-		return 0x0000;
-
-	*ver = nv_ro08(bios, therm + 0);
-	*hdr = nv_ro08(bios, therm + 1);
-	*len = nv_ro08(bios, therm + 2);
-	*cnt = nv_ro08(bios, therm + 3);
-
-	return therm + nv_ro08(bios, therm + 1);
-}
-
-static u16
-nvbios_therm_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
-{
-	u8 hdr, cnt;
-	u16 therm = therm_table(bios, ver, &hdr, len, &cnt);
-	if (therm && idx < cnt)
-		return therm + idx * *len;
-	return 0x0000;
-}
-
-int
-nvbios_therm_sensor_parse(struct nouveau_bios *bios,
-			  enum nvbios_therm_domain domain,
-			  struct nvbios_therm_sensor *sensor)
-{
-	s8 thrs_section, sensor_section, offset;
-	u8 ver, len, i;
-	u16 entry;
-
-	/* we only support the core domain for now */
-	if (domain != NVBIOS_THERM_DOMAIN_CORE)
-		return -EINVAL;
-
-	/* Read the entries from the table */
-	thrs_section = 0;
-	sensor_section = -1;
-	i = 0;
-	while ((entry = nvbios_therm_entry(bios, i++, &ver, &len))) {
-		s16 value = nv_ro16(bios, entry + 1);
-
-		switch (nv_ro08(bios, entry + 0)) {
-		case 0x0:
-			thrs_section = value;
-			if (value > 0)
-				return 0; /* we do not try to support ambient */
-			break;
-		case 0x01:
-			sensor_section++;
-			if (sensor_section == 0) {
-				offset = ((s8) nv_ro08(bios, entry + 2)) / 2;
-				sensor->offset_constant = offset;
-			}
-			break;
-
-		case 0x04:
-			if (thrs_section == 0) {
-				sensor->thrs_critical.temp = (value & 0xff0) >> 4;
-				sensor->thrs_critical.hysteresis = value & 0xf;
-			}
-			break;
-
-		case 0x07:
-			if (thrs_section == 0) {
-				sensor->thrs_down_clock.temp = (value & 0xff0) >> 4;
-				sensor->thrs_down_clock.hysteresis = value & 0xf;
-			}
-			break;
-
-		case 0x08:
-			if (thrs_section == 0) {
-				sensor->thrs_fan_boost.temp = (value & 0xff0) >> 4;
-				sensor->thrs_fan_boost.hysteresis = value & 0xf;
-			}
-			break;
-
-		case 0x10:
-			if (sensor_section == 0)
-				sensor->offset_num = value;
-			break;
-
-		case 0x11:
-			if (sensor_section == 0)
-				sensor->offset_den = value;
-			break;
-
-		case 0x12:
-			if (sensor_section == 0)
-				sensor->slope_mult = value;
-			break;
-
-		case 0x13:
-			if (sensor_section == 0)
-				sensor->slope_div = value;
-			break;
-		case 0x32:
-			if (thrs_section == 0) {
-				sensor->thrs_shutdown.temp = (value & 0xff0) >> 4;
-				sensor->thrs_shutdown.hysteresis = value & 0xf;
-			}
-			break;
-		}
-	}
-
-	return 0;
-}
-
-int
-nvbios_therm_fan_parse(struct nouveau_bios *bios,
-			  struct nvbios_therm_fan *fan)
-{
-	struct nouveau_therm_trip_point *cur_trip = NULL;
-	u8 ver, len, i;
-	u16 entry;
-
-	uint8_t duty_lut[] = { 0, 0, 25, 0, 40, 0, 50, 0,
-				75, 0, 85, 0, 100, 0, 100, 0 };
-
-	i = 0;
-	fan->nr_fan_trip = 0;
-	fan->fan_mode = NVBIOS_THERM_FAN_OTHER;
-	while ((entry = nvbios_therm_entry(bios, i++, &ver, &len))) {
-		s16 value = nv_ro16(bios, entry + 1);
-
-		switch (nv_ro08(bios, entry + 0)) {
-		case 0x22:
-			fan->min_duty = value & 0xff;
-			fan->max_duty = (value & 0xff00) >> 8;
-			break;
-		case 0x24:
-			fan->nr_fan_trip++;
-			if (fan->fan_mode > NVBIOS_THERM_FAN_TRIP)
-				fan->fan_mode = NVBIOS_THERM_FAN_TRIP;
-			cur_trip = &fan->trip[fan->nr_fan_trip - 1];
-			cur_trip->hysteresis = value & 0xf;
-			cur_trip->temp = (value & 0xff0) >> 4;
-			cur_trip->fan_duty = duty_lut[(value & 0xf000) >> 12];
-			break;
-		case 0x25:
-			cur_trip = &fan->trip[fan->nr_fan_trip - 1];
-			cur_trip->fan_duty = value;
-			break;
-		case 0x26:
-			if (!fan->pwm_freq)
-				fan->pwm_freq = value;
-			break;
-		case 0x3b:
-			fan->bump_period = value;
-			break;
-		case 0x3c:
-			fan->slow_down_period = value;
-			break;
-		case 0x46:
-			if (fan->fan_mode > NVBIOS_THERM_FAN_LINEAR)
-				fan->fan_mode = NVBIOS_THERM_FAN_LINEAR;
-			fan->linear_min_temp = nv_ro08(bios, entry + 1);
-			fan->linear_max_temp = nv_ro08(bios, entry + 2);
-			break;
-		}
-	}
-
-	/* starting from fermi, fan management is always linear */
-	if (nv_device(bios)->card_type >= NV_C0 &&
-		fan->fan_mode == NVBIOS_THERM_FAN_OTHER) {
-		fan->fan_mode = NVBIOS_THERM_FAN_LINEAR;
-	}
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c b/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c
deleted file mode 100644
index 8521eca1ed9c..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/ramcfg.h>
-#include <subdev/bios/timing.h>
-
-u16
-nvbios_timingTe(struct nouveau_bios *bios,
-		u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
-{
-	struct bit_entry bit_P;
-	u16 timing = 0x0000;
-
-	if (!bit_entry(bios, 'P', &bit_P)) {
-		if (bit_P.version == 1)
-			timing = nv_ro16(bios, bit_P.offset + 4);
-		else
-		if (bit_P.version == 2)
-			timing = nv_ro16(bios, bit_P.offset + 8);
-
-		if (timing) {
-			*ver = nv_ro08(bios, timing + 0);
-			switch (*ver) {
-			case 0x10:
-				*hdr = nv_ro08(bios, timing + 1);
-				*cnt = nv_ro08(bios, timing + 2);
-				*len = nv_ro08(bios, timing + 3);
-				*snr = 0;
-				*ssz = 0;
-				return timing;
-			case 0x20:
-				*hdr = nv_ro08(bios, timing + 1);
-				*cnt = nv_ro08(bios, timing + 5);
-				*len = nv_ro08(bios, timing + 2);
-				*snr = nv_ro08(bios, timing + 4);
-				*ssz = nv_ro08(bios, timing + 3);
-				return timing;
-			default:
-				break;
-			}
-		}
-	}
-
-	return 0x0000;
-}
-
-u16
-nvbios_timingEe(struct nouveau_bios *bios, int idx,
-		u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	u8  snr, ssz;
-	u16 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz);
-	if (timing && idx < *cnt) {
-		timing += *hdr + idx * (*len + (snr * ssz));
-		*hdr = *len;
-		*cnt = snr;
-		*len = ssz;
-		return timing;
-	}
-	return 0x0000;
-}
-
-u16
-nvbios_timingEp(struct nouveau_bios *bios, int idx,
-		u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		struct nvbios_ramcfg *p)
-{
-	u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp;
-	p->timing_ver = *ver;
-	p->timing_hdr = *hdr;
-	switch (!!data * *ver) {
-	case 0x10:
-		p->timing_10_WR    = nv_ro08(bios, data + 0x00);
-		p->timing_10_WTR   = nv_ro08(bios, data + 0x01);
-		p->timing_10_CL    = nv_ro08(bios, data + 0x02);
-		p->timing_10_RC    = nv_ro08(bios, data + 0x03);
-		p->timing_10_RFC   = nv_ro08(bios, data + 0x05);
-		p->timing_10_RAS   = nv_ro08(bios, data + 0x07);
-		p->timing_10_RP    = nv_ro08(bios, data + 0x09);
-		p->timing_10_RCDRD = nv_ro08(bios, data + 0x0a);
-		p->timing_10_RCDWR = nv_ro08(bios, data + 0x0b);
-		p->timing_10_RRD   = nv_ro08(bios, data + 0x0c);
-		p->timing_10_13    = nv_ro08(bios, data + 0x0d);
-		p->timing_10_ODT   = nv_ro08(bios, data + 0x0e) & 0x07;
-
-		p->timing_10_24  = 0xff;
-		p->timing_10_21  = 0;
-		p->timing_10_20  = 0;
-		p->timing_10_CWL = 0;
-		p->timing_10_18  = 0;
-		p->timing_10_16  = 0;
-
-		switch (min_t(u8, *hdr, 25)) {
-		case 25:
-			p->timing_10_24  = nv_ro08(bios, data + 0x18);
-		case 24:
-		case 23:
-		case 22:
-			p->timing_10_21  = nv_ro08(bios, data + 0x15);
-		case 21:
-			p->timing_10_20  = nv_ro08(bios, data + 0x14);
-		case 20:
-			p->timing_10_CWL = nv_ro08(bios, data + 0x13);
-		case 19:
-			p->timing_10_18  = nv_ro08(bios, data + 0x12);
-		case 18:
-		case 17:
-			p->timing_10_16  = nv_ro08(bios, data + 0x10);
-		}
-
-		break;
-	case 0x20:
-		p->timing[0] = nv_ro32(bios, data + 0x00);
-		p->timing[1] = nv_ro32(bios, data + 0x04);
-		p->timing[2] = nv_ro32(bios, data + 0x08);
-		p->timing[3] = nv_ro32(bios, data + 0x0c);
-		p->timing[4] = nv_ro32(bios, data + 0x10);
-		p->timing[5] = nv_ro32(bios, data + 0x14);
-		p->timing[6] = nv_ro32(bios, data + 0x18);
-		p->timing[7] = nv_ro32(bios, data + 0x1c);
-		p->timing[8] = nv_ro32(bios, data + 0x20);
-		p->timing[9] = nv_ro32(bios, data + 0x24);
-		p->timing[10] = nv_ro32(bios, data + 0x28);
-		p->timing_20_2e_03 = (nv_ro08(bios, data + 0x2e) & 0x03) >> 0;
-		p->timing_20_2e_30 = (nv_ro08(bios, data + 0x2e) & 0x30) >> 4;
-		p->timing_20_2e_c0 = (nv_ro08(bios, data + 0x2e) & 0xc0) >> 6;
-		p->timing_20_2f_03 = (nv_ro08(bios, data + 0x2f) & 0x03) >> 0;
-		temp = nv_ro16(bios, data + 0x2c);
-		p->timing_20_2c_003f = (temp & 0x003f) >> 0;
-		p->timing_20_2c_1fc0 = (temp & 0x1fc0) >> 6;
-		p->timing_20_30_07 = (nv_ro08(bios, data + 0x30) & 0x07) >> 0;
-		p->timing_20_30_f8 = (nv_ro08(bios, data + 0x30) & 0xf8) >> 3;
-		temp = nv_ro16(bios, data + 0x31);
-		p->timing_20_31_0007 = (temp & 0x0007) >> 0;
-		p->timing_20_31_0078 = (temp & 0x0078) >> 3;
-		p->timing_20_31_0780 = (temp & 0x0780) >> 7;
-		p->timing_20_31_0800 = (temp & 0x0800) >> 11;
-		p->timing_20_31_7000 = (temp & 0x7000) >> 12;
-		p->timing_20_31_8000 = (temp & 0x8000) >> 15;
-		break;
-	default:
-		data = 0;
-		break;
-	}
-	return data;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/vmap.c b/drivers/gpu/drm/nouveau/core/subdev/bios/vmap.c
deleted file mode 100644
index f343a1b060e8..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/vmap.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Copyright 2012 Nouveau Community
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/vmap.h>
-
-u16
-nvbios_vmap_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	struct bit_entry bit_P;
-	u16 vmap = 0x0000;
-
-	if (!bit_entry(bios, 'P', &bit_P)) {
-		if (bit_P.version == 2) {
-			vmap = nv_ro16(bios, bit_P.offset + 0x20);
-			if (vmap) {
-				*ver = nv_ro08(bios, vmap + 0);
-				switch (*ver) {
-				case 0x10:
-				case 0x20:
-					*hdr = nv_ro08(bios, vmap + 1);
-					*cnt = nv_ro08(bios, vmap + 3);
-					*len = nv_ro08(bios, vmap + 2);
-					return vmap;
-				default:
-					break;
-				}
-			}
-		}
-	}
-
-	return 0x0000;
-}
-
-u16
-nvbios_vmap_parse(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		  struct nvbios_vmap *info)
-{
-	u16 vmap = nvbios_vmap_table(bios, ver, hdr, cnt, len);
-	memset(info, 0x00, sizeof(*info));
-	switch (!!vmap * *ver) {
-	case 0x10:
-	case 0x20:
-		break;
-	}
-	return vmap;
-}
-
-u16
-nvbios_vmap_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
-{
-	u8  hdr, cnt;
-	u16 vmap = nvbios_vmap_table(bios, ver, &hdr, &cnt, len);
-	if (vmap && idx < cnt) {
-		vmap = vmap + hdr + (idx * *len);
-		return vmap;
-	}
-	return 0x0000;
-}
-
-u16
-nvbios_vmap_entry_parse(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len,
-			struct nvbios_vmap_entry *info)
-{
-	u16 vmap = nvbios_vmap_entry(bios, idx, ver, len);
-	memset(info, 0x00, sizeof(*info));
-	switch (!!vmap * *ver) {
-	case 0x10:
-		info->link   = 0xff;
-		info->min    = nv_ro32(bios, vmap + 0x00);
-		info->max    = nv_ro32(bios, vmap + 0x04);
-		info->arg[0] = nv_ro32(bios, vmap + 0x08);
-		info->arg[1] = nv_ro32(bios, vmap + 0x0c);
-		info->arg[2] = nv_ro32(bios, vmap + 0x10);
-		break;
-	case 0x20:
-		info->unk0   = nv_ro08(bios, vmap + 0x00);
-		info->link   = nv_ro08(bios, vmap + 0x01);
-		info->min    = nv_ro32(bios, vmap + 0x02);
-		info->max    = nv_ro32(bios, vmap + 0x06);
-		info->arg[0] = nv_ro32(bios, vmap + 0x0a);
-		info->arg[1] = nv_ro32(bios, vmap + 0x0e);
-		info->arg[2] = nv_ro32(bios, vmap + 0x12);
-		info->arg[3] = nv_ro32(bios, vmap + 0x16);
-		info->arg[4] = nv_ro32(bios, vmap + 0x1a);
-		info->arg[5] = nv_ro32(bios, vmap + 0x1e);
-		break;
-	}
-	return vmap;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/volt.c b/drivers/gpu/drm/nouveau/core/subdev/bios/volt.c
deleted file mode 100644
index bb590de4ecb2..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/volt.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * Copyright 2012 Nouveau Community
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/volt.h>
-
-u16
-nvbios_volt_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	struct bit_entry bit_P;
-	u16 volt = 0x0000;
-
-	if (!bit_entry(bios, 'P', &bit_P)) {
-		if (bit_P.version == 2)
-			volt = nv_ro16(bios, bit_P.offset + 0x0c);
-		else
-		if (bit_P.version == 1)
-			volt = nv_ro16(bios, bit_P.offset + 0x10);
-
-		if (volt) {
-			*ver = nv_ro08(bios, volt + 0);
-			switch (*ver) {
-			case 0x12:
-				*hdr = 5;
-				*cnt = nv_ro08(bios, volt + 2);
-				*len = nv_ro08(bios, volt + 1);
-				return volt;
-			case 0x20:
-				*hdr = nv_ro08(bios, volt + 1);
-				*cnt = nv_ro08(bios, volt + 2);
-				*len = nv_ro08(bios, volt + 3);
-				return volt;
-			case 0x30:
-			case 0x40:
-			case 0x50:
-				*hdr = nv_ro08(bios, volt + 1);
-				*cnt = nv_ro08(bios, volt + 3);
-				*len = nv_ro08(bios, volt + 2);
-				return volt;
-			}
-		}
-	}
-
-	return 0x0000;
-}
-
-u16
-nvbios_volt_parse(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-		  struct nvbios_volt *info)
-{
-	u16 volt = nvbios_volt_table(bios, ver, hdr, cnt, len);
-	memset(info, 0x00, sizeof(*info));
-	switch (!!volt * *ver) {
-	case 0x12:
-		info->vidmask = nv_ro08(bios, volt + 0x04);
-		break;
-	case 0x20:
-		info->vidmask = nv_ro08(bios, volt + 0x05);
-		break;
-	case 0x30:
-		info->vidmask = nv_ro08(bios, volt + 0x04);
-		break;
-	case 0x40:
-		info->base    = nv_ro32(bios, volt + 0x04);
-		info->step    = nv_ro16(bios, volt + 0x08);
-		info->vidmask = nv_ro08(bios, volt + 0x0b);
-		/*XXX*/
-		info->min     = 0;
-		info->max     = info->base;
-		break;
-	case 0x50:
-		info->vidmask = nv_ro08(bios, volt + 0x06);
-		info->min     = nv_ro32(bios, volt + 0x0a);
-		info->max     = nv_ro32(bios, volt + 0x0e);
-		info->base    = nv_ro32(bios, volt + 0x12) & 0x00ffffff;
-		info->step    = nv_ro16(bios, volt + 0x16);
-		break;
-	}
-	return volt;
-}
-
-u16
-nvbios_volt_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
-{
-	u8  hdr, cnt;
-	u16 volt = nvbios_volt_table(bios, ver, &hdr, &cnt, len);
-	if (volt && idx < cnt) {
-		volt = volt + hdr + (idx * *len);
-		return volt;
-	}
-	return 0x0000;
-}
-
-u16
-nvbios_volt_entry_parse(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len,
-			struct nvbios_volt_entry *info)
-{
-	u16 volt = nvbios_volt_entry(bios, idx, ver, len);
-	memset(info, 0x00, sizeof(*info));
-	switch (!!volt * *ver) {
-	case 0x12:
-	case 0x20:
-		info->voltage = nv_ro08(bios, volt + 0x00) * 10000;
-		info->vid     = nv_ro08(bios, volt + 0x01);
-		break;
-	case 0x30:
-		info->voltage = nv_ro08(bios, volt + 0x00) * 10000;
-		info->vid     = nv_ro08(bios, volt + 0x01) >> 2;
-		break;
-	case 0x40:
-	case 0x50:
-		break;
-	}
-	return volt;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/xpio.c b/drivers/gpu/drm/nouveau/core/subdev/bios/xpio.c
deleted file mode 100644
index e9b8e5d30a7a..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/xpio.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/gpio.h>
-#include <subdev/bios/xpio.h>
-
-static u16
-dcb_xpiod_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	u16 data = dcb_gpio_table(bios, ver, hdr, cnt, len);
-	if (data && *ver >= 0x40 && *hdr >= 0x06) {
-		u16 xpio = nv_ro16(bios, data + 0x04);
-		if (xpio) {
-			*ver = nv_ro08(bios, data + 0x00);
-			*hdr = nv_ro08(bios, data + 0x01);
-			*cnt = nv_ro08(bios, data + 0x02);
-			*len = nv_ro08(bios, data + 0x03);
-			return xpio;
-		}
-	}
-	return 0x0000;
-}
-
-u16
-dcb_xpio_table(struct nouveau_bios *bios, u8 idx,
-	       u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-	u16 data = dcb_xpiod_table(bios, ver, hdr, cnt, len);
-	if (data && idx < *cnt) {
-		u16 xpio = nv_ro16(bios, data + *hdr + (idx * *len));
-		if (xpio) {
-			*ver = nv_ro08(bios, data + 0x00);
-			*hdr = nv_ro08(bios, data + 0x01);
-			*cnt = nv_ro08(bios, data + 0x02);
-			*len = nv_ro08(bios, data + 0x03);
-			return xpio;
-		}
-	}
-	return 0x0000;
-}
-
-u16
-dcb_xpio_parse(struct nouveau_bios *bios, u8 idx,
-	       u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
-	       struct nvbios_xpio *info)
-{
-	u16 data = dcb_xpio_table(bios, idx, ver, hdr, cnt, len);
-	if (data && *len >= 6) {
-		info->type = nv_ro08(bios, data + 0x04);
-		info->addr = nv_ro08(bios, data + 0x05);
-		info->flags = nv_ro08(bios, data + 0x06);
-	}
-	return 0x0000;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.c b/drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.c
deleted file mode 100644
index f757470e2284..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include <subdev/timer.h>
-#include <subdev/bus.h>
-
-struct nouveau_hwsq {
-	struct nouveau_bus *pbus;
-	u32 addr;
-	u32 data;
-	struct {
-		u8 data[512];
-		u8 size;
-	} c;
-};
-
-static void
-hwsq_cmd(struct nouveau_hwsq *hwsq, int size, u8 data[])
-{
-	memcpy(&hwsq->c.data[hwsq->c.size], data, size * sizeof(data[0]));
-	hwsq->c.size += size;
-}
-
-int
-nouveau_hwsq_init(struct nouveau_bus *pbus, struct nouveau_hwsq **phwsq)
-{
-	struct nouveau_hwsq *hwsq;
-
-	hwsq = *phwsq = kmalloc(sizeof(*hwsq), GFP_KERNEL);
-	if (hwsq) {
-		hwsq->pbus = pbus;
-		hwsq->addr = ~0;
-		hwsq->data = ~0;
-		memset(hwsq->c.data, 0x7f, sizeof(hwsq->c.data));
-		hwsq->c.size = 0;
-	}
-
-	return hwsq ? 0 : -ENOMEM;
-}
-
-int
-nouveau_hwsq_fini(struct nouveau_hwsq **phwsq, bool exec)
-{
-	struct nouveau_hwsq *hwsq = *phwsq;
-	int ret = 0, i;
-	if (hwsq) {
-		struct nouveau_bus *pbus = hwsq->pbus;
-		hwsq->c.size = (hwsq->c.size + 4) / 4;
-		if (hwsq->c.size <= pbus->hwsq_size) {
-			if (exec)
-				ret = pbus->hwsq_exec(pbus, (u32 *)hwsq->c.data,
-						      hwsq->c.size);
-			if (ret)
-				nv_error(pbus, "hwsq exec failed: %d\n", ret);
-		} else {
-			nv_error(pbus, "hwsq ucode too large\n");
-			ret = -ENOSPC;
-		}
-
-		for (i = 0; ret && i < hwsq->c.size; i++)
-			nv_error(pbus, "\t0x%08x\n", ((u32 *)hwsq->c.data)[i]);
-
-		*phwsq = NULL;
-		kfree(hwsq);
-	}
-	return ret;
-}
-
-void
-nouveau_hwsq_wr32(struct nouveau_hwsq *hwsq, u32 addr, u32 data)
-{
-	nv_debug(hwsq->pbus, "R[%06x] = 0x%08x\n", addr, data);
-
-	if (hwsq->data != data) {
-		if ((data & 0xffff0000) != (hwsq->data & 0xffff0000)) {
-			hwsq_cmd(hwsq, 5, (u8[]){ 0xe2, data, data >> 8,
-						  data >> 16, data >> 24 });
-		} else {
-			hwsq_cmd(hwsq, 3, (u8[]){ 0x42, data, data >> 8 });
-		}
-	}
-
-	if ((addr & 0xffff0000) != (hwsq->addr & 0xffff0000)) {
-		hwsq_cmd(hwsq, 5, (u8[]){ 0xe0, addr, addr >> 8,
-					  addr >> 16, addr >> 24 });
-	} else {
-		hwsq_cmd(hwsq, 3, (u8[]){ 0x40, addr, addr >> 8 });
-	}
-
-	hwsq->addr = addr;
-	hwsq->data = data;
-}
-
-void
-nouveau_hwsq_setf(struct nouveau_hwsq *hwsq, u8 flag, int data)
-{
-	nv_debug(hwsq->pbus, " FLAG[%02x] = %d\n", flag, data);
-	flag += 0x80;
-	if (data >= 0)
-		flag += 0x20;
-	if (data >= 1)
-		flag += 0x20;
-	hwsq_cmd(hwsq, 1, (u8[]){ flag });
-}
-
-void
-nouveau_hwsq_wait(struct nouveau_hwsq *hwsq, u8 flag, u8 data)
-{
-	nv_debug(hwsq->pbus, " WAIT[%02x] = %d\n", flag, data);
-	hwsq_cmd(hwsq, 3, (u8[]){ 0x5f, flag, data });
-}
-
-void
-nouveau_hwsq_nsec(struct nouveau_hwsq *hwsq, u32 nsec)
-{
-	u8 shift = 0, usec = nsec / 1000;
-	while (usec & ~3) {
-		usec >>= 2;
-		shift++;
-	}
-
-	nv_debug(hwsq->pbus, "    DELAY = %d ns\n", nsec);
-	hwsq_cmd(hwsq, 1, (u8[]){ 0x00 | (shift << 2) | usec });
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.h b/drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.h
deleted file mode 100644
index 12176f9c1bc6..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.h
+++ /dev/null
@@ -1,113 +0,0 @@
-#ifndef __NVKM_BUS_HWSQ_H__
-#define __NVKM_BUS_HWSQ_H__
-
-#include <subdev/bus.h>
-
-struct hwsq {
-	struct nouveau_subdev *subdev;
-	struct nouveau_hwsq *hwsq;
-	int sequence;
-};
-
-struct hwsq_reg {
-	int sequence;
-	bool force;
-	u32 addr[2];
-	u32 data;
-};
-
-static inline struct hwsq_reg
-hwsq_reg2(u32 addr1, u32 addr2)
-{
-	return (struct hwsq_reg) {
-		.sequence = 0,
-		.force = 0,
-		.addr = { addr1, addr2 },
-		.data = 0xdeadbeef,
-	};
-}
-
-static inline struct hwsq_reg
-hwsq_reg(u32 addr)
-{
-	return hwsq_reg2(addr, addr);
-}
-
-static inline int
-hwsq_init(struct hwsq *ram, struct nouveau_subdev *subdev)
-{
-	struct nouveau_bus *pbus = nouveau_bus(subdev);
-	int ret;
-
-	ret = nouveau_hwsq_init(pbus, &ram->hwsq);
-	if (ret)
-		return ret;
-
-	ram->sequence++;
-	ram->subdev = subdev;
-	return 0;
-}
-
-static inline int
-hwsq_exec(struct hwsq *ram, bool exec)
-{
-	int ret = 0;
-	if (ram->subdev) {
-		ret = nouveau_hwsq_fini(&ram->hwsq, exec);
-		ram->subdev = NULL;
-	}
-	return ret;
-}
-
-static inline u32
-hwsq_rd32(struct hwsq *ram, struct hwsq_reg *reg)
-{
-	if (reg->sequence != ram->sequence)
-		reg->data = nv_rd32(ram->subdev, reg->addr[0]);
-	return reg->data;
-}
-
-static inline void
-hwsq_wr32(struct hwsq *ram, struct hwsq_reg *reg, u32 data)
-{
-	reg->sequence = ram->sequence;
-	reg->data = data;
-	if (reg->addr[0] != reg->addr[1])
-		nouveau_hwsq_wr32(ram->hwsq, reg->addr[1], reg->data);
-	nouveau_hwsq_wr32(ram->hwsq, reg->addr[0], reg->data);
-}
-
-static inline void
-hwsq_nuke(struct hwsq *ram, struct hwsq_reg *reg)
-{
-	reg->force = true;
-}
-
-static inline u32
-hwsq_mask(struct hwsq *ram, struct hwsq_reg *reg, u32 mask, u32 data)
-{
-	u32 temp = hwsq_rd32(ram, reg);
-	if (temp != ((temp & ~mask) | data) || reg->force)
-		hwsq_wr32(ram, reg, (temp & ~mask) | data);
-	return temp;
-}
-
-static inline void
-hwsq_setf(struct hwsq *ram, u8 flag, int data)
-{
-	nouveau_hwsq_setf(ram->hwsq, flag, data);
-}
-
-static inline void
-hwsq_wait(struct hwsq *ram, u8 flag, u8 data)
-{
-	nouveau_hwsq_wait(ram->hwsq, flag, data);
-}
-
-static inline void
-hwsq_nsec(struct hwsq *ram, u32 nsec)
-{
-	nouveau_hwsq_nsec(ram->hwsq, nsec);
-}
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c
deleted file mode 100644
index 23921b5351db..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Copyright 2012 Nouveau Community
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres <martin.peres@labri.fr>
- *          Ben Skeggs
- */
-
-#include "nv04.h"
-
-static void
-nv04_bus_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_bus *pbus = nouveau_bus(subdev);
-	u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
-
-	if (stat & 0x00000001) {
-		nv_error(pbus, "BUS ERROR\n");
-		stat &= ~0x00000001;
-		nv_wr32(pbus, 0x001100, 0x00000001);
-	}
-
-	if (stat & 0x00000110) {
-		subdev = nouveau_subdev(subdev, NVDEV_SUBDEV_GPIO);
-		if (subdev && subdev->intr)
-			subdev->intr(subdev);
-		stat &= ~0x00000110;
-		nv_wr32(pbus, 0x001100, 0x00000110);
-	}
-
-	if (stat) {
-		nv_error(pbus, "unknown intr 0x%08x\n", stat);
-		nv_mask(pbus, 0x001140, stat, 0x00000000);
-	}
-}
-
-static int
-nv04_bus_init(struct nouveau_object *object)
-{
-	struct nv04_bus_priv *priv = (void *)object;
-
-	nv_wr32(priv, 0x001100, 0xffffffff);
-	nv_wr32(priv, 0x001140, 0x00000111);
-
-	return nouveau_bus_init(&priv->base);
-}
-
-int
-nv04_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 size,
-	      struct nouveau_object **pobject)
-{
-	struct nv04_bus_impl *impl = (void *)oclass;
-	struct nv04_bus_priv *priv;
-	int ret;
-
-	ret = nouveau_bus_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->intr = impl->intr;
-	priv->base.hwsq_exec = impl->hwsq_exec;
-	priv->base.hwsq_size = impl->hwsq_size;
-	return 0;
-}
-
-struct nouveau_oclass *
-nv04_bus_oclass = &(struct nv04_bus_impl) {
-	.base.handle = NV_SUBDEV(BUS, 0x04),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_bus_ctor,
-		.dtor = _nouveau_bus_dtor,
-		.init = nv04_bus_init,
-		.fini = _nouveau_bus_fini,
-	},
-	.intr = nv04_bus_intr,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.h
deleted file mode 100644
index 4d7602450a20..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef __NVKM_BUS_NV04_H__
-#define __NVKM_BUS_NV04_H__
-
-#include <subdev/bus.h>
-
-struct nv04_bus_priv {
-	struct nouveau_bus base;
-};
-
-int  nv04_bus_ctor(struct nouveau_object *, struct nouveau_object *,
-		   struct nouveau_oclass *, void *, u32,
-		   struct nouveau_object **);
-int  nv50_bus_init(struct nouveau_object *);
-void nv50_bus_intr(struct nouveau_subdev *);
-
-struct nv04_bus_impl {
-	struct nouveau_oclass base;
-	void (*intr)(struct nouveau_subdev *);
-	int  (*hwsq_exec)(struct nouveau_bus *, u32 *, u32);
-	u32  hwsq_size;
-};
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c b/drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c
deleted file mode 100644
index 94da46f61627..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright 2012 Nouveau Community
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres <martin.peres@labri.fr>
- *          Ben Skeggs
- */
-
-#include "nv04.h"
-
-static void
-nv31_bus_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_bus *pbus = nouveau_bus(subdev);
-	u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
-	u32 gpio = nv_rd32(pbus, 0x001104) & nv_rd32(pbus, 0x001144);
-
-	if (gpio) {
-		subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_GPIO);
-		if (subdev && subdev->intr)
-			subdev->intr(subdev);
-	}
-
-	if (stat & 0x00000008) {  /* NV41- */
-		u32 addr = nv_rd32(pbus, 0x009084);
-		u32 data = nv_rd32(pbus, 0x009088);
-
-		nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x\n",
-			 (addr & 0x00000002) ? "write" : "read", data,
-			 (addr & 0x00fffffc));
-
-		stat &= ~0x00000008;
-		nv_wr32(pbus, 0x001100, 0x00000008);
-	}
-
-	if (stat & 0x00070000) {
-		subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_THERM);
-		if (subdev && subdev->intr)
-			subdev->intr(subdev);
-		stat &= ~0x00070000;
-		nv_wr32(pbus, 0x001100, 0x00070000);
-	}
-
-	if (stat) {
-		nv_error(pbus, "unknown intr 0x%08x\n", stat);
-		nv_mask(pbus, 0x001140, stat, 0x00000000);
-	}
-}
-
-static int
-nv31_bus_init(struct nouveau_object *object)
-{
-	struct nv04_bus_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_bus_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x001100, 0xffffffff);
-	nv_wr32(priv, 0x001140, 0x00070008);
-	return 0;
-}
-
-struct nouveau_oclass *
-nv31_bus_oclass = &(struct nv04_bus_impl) {
-	.base.handle = NV_SUBDEV(BUS, 0x31),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_bus_ctor,
-		.dtor = _nouveau_bus_dtor,
-		.init = nv31_bus_init,
-		.fini = _nouveau_bus_fini,
-	},
-	.intr = nv31_bus_intr,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c
deleted file mode 100644
index 11918f7e2aca..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright 2012 Nouveau Community
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres <martin.peres@labri.fr>
- *          Ben Skeggs
- */
-
-#include <subdev/timer.h>
-
-#include "nv04.h"
-
-static int
-nv50_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size)
-{
-	struct nv50_bus_priv *priv = (void *)pbus;
-	int i;
-
-	nv_mask(pbus, 0x001098, 0x00000008, 0x00000000);
-	nv_wr32(pbus, 0x001304, 0x00000000);
-	for (i = 0; i < size; i++)
-		nv_wr32(priv, 0x001400 + (i * 4), data[i]);
-	nv_mask(pbus, 0x001098, 0x00000018, 0x00000018);
-	nv_wr32(pbus, 0x00130c, 0x00000003);
-
-	return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
-}
-
-void
-nv50_bus_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_bus *pbus = nouveau_bus(subdev);
-	u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
-
-	if (stat & 0x00000008) {
-		u32 addr = nv_rd32(pbus, 0x009084);
-		u32 data = nv_rd32(pbus, 0x009088);
-
-		nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x\n",
-			 (addr & 0x00000002) ? "write" : "read", data,
-			 (addr & 0x00fffffc));
-
-		stat &= ~0x00000008;
-		nv_wr32(pbus, 0x001100, 0x00000008);
-	}
-
-	if (stat & 0x00010000) {
-		subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_THERM);
-		if (subdev && subdev->intr)
-			subdev->intr(subdev);
-		stat &= ~0x00010000;
-		nv_wr32(pbus, 0x001100, 0x00010000);
-	}
-
-	if (stat) {
-		nv_error(pbus, "unknown intr 0x%08x\n", stat);
-		nv_mask(pbus, 0x001140, stat, 0);
-	}
-}
-
-int
-nv50_bus_init(struct nouveau_object *object)
-{
-	struct nv04_bus_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_bus_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x001100, 0xffffffff);
-	nv_wr32(priv, 0x001140, 0x00010008);
-	return 0;
-}
-
-struct nouveau_oclass *
-nv50_bus_oclass = &(struct nv04_bus_impl) {
-	.base.handle = NV_SUBDEV(BUS, 0x50),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_bus_ctor,
-		.dtor = _nouveau_bus_dtor,
-		.init = nv50_bus_init,
-		.fini = _nouveau_bus_fini,
-	},
-	.intr = nv50_bus_intr,
-	.hwsq_exec = nv50_bus_hwsq_exec,
-	.hwsq_size = 64,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv94.c b/drivers/gpu/drm/nouveau/core/subdev/bus/nv94.c
deleted file mode 100644
index d3659055fa4b..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bus/nv94.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2012 Nouveau Community
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres <martin.peres@labri.fr>
- *          Ben Skeggs
- */
-
-#include <subdev/timer.h>
-
-#include "nv04.h"
-
-static int
-nv94_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size)
-{
-	struct nv50_bus_priv *priv = (void *)pbus;
-	int i;
-
-	nv_mask(pbus, 0x001098, 0x00000008, 0x00000000);
-	nv_wr32(pbus, 0x001304, 0x00000000);
-	nv_wr32(pbus, 0x001318, 0x00000000);
-	for (i = 0; i < size; i++)
-		nv_wr32(priv, 0x080000 + (i * 4), data[i]);
-	nv_mask(pbus, 0x001098, 0x00000018, 0x00000018);
-	nv_wr32(pbus, 0x00130c, 0x00000001);
-
-	return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
-}
-
-struct nouveau_oclass *
-nv94_bus_oclass = &(struct nv04_bus_impl) {
-	.base.handle = NV_SUBDEV(BUS, 0x94),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_bus_ctor,
-		.dtor = _nouveau_bus_dtor,
-		.init = nv50_bus_init,
-		.fini = _nouveau_bus_fini,
-	},
-	.intr = nv50_bus_intr,
-	.hwsq_exec = nv94_bus_hwsq_exec,
-	.hwsq_size = 128,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c
deleted file mode 100644
index 73839d7151a7..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright 2012 Nouveau Community
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres <martin.peres@labri.fr>
- *          Ben Skeggs
- */
-
-#include "nv04.h"
-
-static void
-nvc0_bus_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_bus *pbus = nouveau_bus(subdev);
-	u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
-
-	if (stat & 0x0000000e) {
-		u32 addr = nv_rd32(pbus, 0x009084);
-		u32 data = nv_rd32(pbus, 0x009088);
-
-		nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x [ %s%s%s]\n",
-			 (addr & 0x00000002) ? "write" : "read", data,
-			 (addr & 0x00fffffc),
-			 (stat & 0x00000002) ? "!ENGINE " : "",
-			 (stat & 0x00000004) ? "IBUS " : "",
-			 (stat & 0x00000008) ? "TIMEOUT " : "");
-
-		nv_wr32(pbus, 0x009084, 0x00000000);
-		nv_wr32(pbus, 0x001100, (stat & 0x0000000e));
-		stat &= ~0x0000000e;
-	}
-
-	if (stat) {
-		nv_error(pbus, "unknown intr 0x%08x\n", stat);
-		nv_mask(pbus, 0x001140, stat, 0x00000000);
-	}
-}
-
-static int
-nvc0_bus_init(struct nouveau_object *object)
-{
-	struct nv04_bus_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_bus_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x001100, 0xffffffff);
-	nv_wr32(priv, 0x001140, 0x0000000e);
-	return 0;
-}
-
-struct nouveau_oclass *
-nvc0_bus_oclass = &(struct nv04_bus_impl) {
-	.base.handle = NV_SUBDEV(BUS, 0xc0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_bus_ctor,
-		.dtor = _nouveau_bus_dtor,
-		.init = nvc0_bus_init,
-		.fini = _nouveau_bus_fini,
-	},
-	.intr = nvc0_bus_intr,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
deleted file mode 100644
index e51b72d47129..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
+++ /dev/null
@@ -1,597 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/option.h>
-
-#include <subdev/clock.h>
-#include <subdev/therm.h>
-#include <subdev/volt.h>
-#include <subdev/fb.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/boost.h>
-#include <subdev/bios/cstep.h>
-#include <subdev/bios/perf.h>
-
-/******************************************************************************
- * misc
- *****************************************************************************/
-static u32
-nouveau_clock_adjust(struct nouveau_clock *clk, bool adjust,
-		     u8 pstate, u8 domain, u32 input)
-{
-	struct nouveau_bios *bios = nouveau_bios(clk);
-	struct nvbios_boostE boostE;
-	u8  ver, hdr, cnt, len;
-	u16 data;
-
-	data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE);
-	if (data) {
-		struct nvbios_boostS boostS;
-		u8  idx = 0, sver, shdr;
-		u16 subd;
-
-		input = max(boostE.min, input);
-		input = min(boostE.max, input);
-		do {
-			sver = ver;
-			shdr = hdr;
-			subd = nvbios_boostSp(bios, idx++, data, &sver, &shdr,
-					      cnt, len, &boostS);
-			if (subd && boostS.domain == domain) {
-				if (adjust)
-					input = input * boostS.percent / 100;
-				input = max(boostS.min, input);
-				input = min(boostS.max, input);
-				break;
-			}
-		} while (subd);
-	}
-
-	return input;
-}
-
-/******************************************************************************
- * C-States
- *****************************************************************************/
-static int
-nouveau_cstate_prog(struct nouveau_clock *clk,
-		    struct nouveau_pstate *pstate, int cstatei)
-{
-	struct nouveau_therm *ptherm = nouveau_therm(clk);
-	struct nouveau_volt *volt = nouveau_volt(clk);
-	struct nouveau_cstate *cstate;
-	int ret;
-
-	if (!list_empty(&pstate->list)) {
-		cstate = list_entry(pstate->list.prev, typeof(*cstate), head);
-	} else {
-		cstate = &pstate->base;
-	}
-
-	if (ptherm) {
-		ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, +1);
-		if (ret && ret != -ENODEV) {
-			nv_error(clk, "failed to raise fan speed: %d\n", ret);
-			return ret;
-		}
-	}
-
-	if (volt) {
-		ret = volt->set_id(volt, cstate->voltage, +1);
-		if (ret && ret != -ENODEV) {
-			nv_error(clk, "failed to raise voltage: %d\n", ret);
-			return ret;
-		}
-	}
-
-	ret = clk->calc(clk, cstate);
-	if (ret == 0) {
-		ret = clk->prog(clk);
-		clk->tidy(clk);
-	}
-
-	if (volt) {
-		ret = volt->set_id(volt, cstate->voltage, -1);
-		if (ret && ret != -ENODEV)
-			nv_error(clk, "failed to lower voltage: %d\n", ret);
-	}
-
-	if (ptherm) {
-		ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, -1);
-		if (ret && ret != -ENODEV)
-			nv_error(clk, "failed to lower fan speed: %d\n", ret);
-	}
-
-	return 0;
-}
-
-static void
-nouveau_cstate_del(struct nouveau_cstate *cstate)
-{
-	list_del(&cstate->head);
-	kfree(cstate);
-}
-
-static int
-nouveau_cstate_new(struct nouveau_clock *clk, int idx,
-		   struct nouveau_pstate *pstate)
-{
-	struct nouveau_bios *bios = nouveau_bios(clk);
-	struct nouveau_clocks *domain = clk->domains;
-	struct nouveau_cstate *cstate = NULL;
-	struct nvbios_cstepX cstepX;
-	u8  ver, hdr;
-	u16 data;
-
-	data = nvbios_cstepXp(bios, idx, &ver, &hdr, &cstepX);
-	if (!data)
-		return -ENOENT;
-
-	cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
-	if (!cstate)
-		return -ENOMEM;
-
-	*cstate = pstate->base;
-	cstate->voltage = cstepX.voltage;
-
-	while (domain && domain->name != nv_clk_src_max) {
-		if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
-			u32 freq = nouveau_clock_adjust(clk, true,
-							pstate->pstate,
-							domain->bios,
-							cstepX.freq);
-			cstate->domain[domain->name] = freq;
-		}
-		domain++;
-	}
-
-	list_add(&cstate->head, &pstate->list);
-	return 0;
-}
-
-/******************************************************************************
- * P-States
- *****************************************************************************/
-static int
-nouveau_pstate_prog(struct nouveau_clock *clk, int pstatei)
-{
-	struct nouveau_fb *pfb = nouveau_fb(clk);
-	struct nouveau_pstate *pstate;
-	int ret, idx = 0;
-
-	list_for_each_entry(pstate, &clk->states, head) {
-		if (idx++ == pstatei)
-			break;
-	}
-
-	nv_debug(clk, "setting performance state %d\n", pstatei);
-	clk->pstate = pstatei;
-
-	if (pfb->ram->calc) {
-		int khz = pstate->base.domain[nv_clk_src_mem];
-		do {
-			ret = pfb->ram->calc(pfb, khz);
-			if (ret == 0)
-				ret = pfb->ram->prog(pfb);
-		} while (ret > 0);
-		pfb->ram->tidy(pfb);
-	}
-
-	return nouveau_cstate_prog(clk, pstate, 0);
-}
-
-static void
-nouveau_pstate_work(struct work_struct *work)
-{
-	struct nouveau_clock *clk = container_of(work, typeof(*clk), work);
-	int pstate;
-
-	if (!atomic_xchg(&clk->waiting, 0))
-		return;
-	clk->pwrsrc = power_supply_is_system_supplied();
-
-	nv_trace(clk, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n",
-		 clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc,
-		 clk->astate, clk->tstate, clk->dstate);
-
-	pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc;
-	if (clk->state_nr && pstate != -1) {
-		pstate = (pstate < 0) ? clk->astate : pstate;
-		pstate = min(pstate, clk->state_nr - 1 - clk->tstate);
-		pstate = max(pstate, clk->dstate);
-	} else {
-		pstate = clk->pstate = -1;
-	}
-
-	nv_trace(clk, "-> %d\n", pstate);
-	if (pstate != clk->pstate) {
-		int ret = nouveau_pstate_prog(clk, pstate);
-		if (ret) {
-			nv_error(clk, "error setting pstate %d: %d\n",
-				 pstate, ret);
-		}
-	}
-
-	wake_up_all(&clk->wait);
-	nvkm_notify_get(&clk->pwrsrc_ntfy);
-}
-
-static int
-nouveau_pstate_calc(struct nouveau_clock *clk, bool wait)
-{
-	atomic_set(&clk->waiting, 1);
-	schedule_work(&clk->work);
-	if (wait)
-		wait_event(clk->wait, !atomic_read(&clk->waiting));
-	return 0;
-}
-
-static void
-nouveau_pstate_info(struct nouveau_clock *clk, struct nouveau_pstate *pstate)
-{
-	struct nouveau_clocks *clock = clk->domains - 1;
-	struct nouveau_cstate *cstate;
-	char info[3][32] = { "", "", "" };
-	char name[4] = "--";
-	int i = -1;
-
-	if (pstate->pstate != 0xff)
-		snprintf(name, sizeof(name), "%02x", pstate->pstate);
-
-	while ((++clock)->name != nv_clk_src_max) {
-		u32 lo = pstate->base.domain[clock->name];
-		u32 hi = lo;
-		if (hi == 0)
-			continue;
-
-		nv_debug(clk, "%02x: %10d KHz\n", clock->name, lo);
-		list_for_each_entry(cstate, &pstate->list, head) {
-			u32 freq = cstate->domain[clock->name];
-			lo = min(lo, freq);
-			hi = max(hi, freq);
-			nv_debug(clk, "%10d KHz\n", freq);
-		}
-
-		if (clock->mname && ++i < ARRAY_SIZE(info)) {
-			lo /= clock->mdiv;
-			hi /= clock->mdiv;
-			if (lo == hi) {
-				snprintf(info[i], sizeof(info[i]), "%s %d MHz",
-					 clock->mname, lo);
-			} else {
-				snprintf(info[i], sizeof(info[i]),
-					 "%s %d-%d MHz", clock->mname, lo, hi);
-			}
-		}
-	}
-
-	nv_info(clk, "%s: %s %s %s\n", name, info[0], info[1], info[2]);
-}
-
-static void
-nouveau_pstate_del(struct nouveau_pstate *pstate)
-{
-	struct nouveau_cstate *cstate, *temp;
-
-	list_for_each_entry_safe(cstate, temp, &pstate->list, head) {
-		nouveau_cstate_del(cstate);
-	}
-
-	list_del(&pstate->head);
-	kfree(pstate);
-}
-
-static int
-nouveau_pstate_new(struct nouveau_clock *clk, int idx)
-{
-	struct nouveau_bios *bios = nouveau_bios(clk);
-	struct nouveau_clocks *domain = clk->domains - 1;
-	struct nouveau_pstate *pstate;
-	struct nouveau_cstate *cstate;
-	struct nvbios_cstepE cstepE;
-	struct nvbios_perfE perfE;
-	u8  ver, hdr, cnt, len;
-	u16 data;
-
-	data = nvbios_perfEp(bios, idx, &ver, &hdr, &cnt, &len, &perfE);
-	if (!data)
-		return -EINVAL;
-	if (perfE.pstate == 0xff)
-		return 0;
-
-	pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
-	cstate = &pstate->base;
-	if (!pstate)
-		return -ENOMEM;
-
-	INIT_LIST_HEAD(&pstate->list);
-
-	pstate->pstate = perfE.pstate;
-	pstate->fanspeed = perfE.fanspeed;
-	cstate->voltage = perfE.voltage;
-	cstate->domain[nv_clk_src_core] = perfE.core;
-	cstate->domain[nv_clk_src_shader] = perfE.shader;
-	cstate->domain[nv_clk_src_mem] = perfE.memory;
-	cstate->domain[nv_clk_src_vdec] = perfE.vdec;
-	cstate->domain[nv_clk_src_dom6] = perfE.disp;
-
-	while (ver >= 0x40 && (++domain)->name != nv_clk_src_max) {
-		struct nvbios_perfS perfS;
-		u8  sver = ver, shdr = hdr;
-		u32 perfSe = nvbios_perfSp(bios, data, domain->bios,
-					  &sver, &shdr, cnt, len, &perfS);
-		if (perfSe == 0 || sver != 0x40)
-			continue;
-
-		if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
-			perfS.v40.freq = nouveau_clock_adjust(clk, false,
-							      pstate->pstate,
-							      domain->bios,
-							      perfS.v40.freq);
-		}
-
-		cstate->domain[domain->name] = perfS.v40.freq;
-	}
-
-	data = nvbios_cstepEm(bios, pstate->pstate, &ver, &hdr, &cstepE);
-	if (data) {
-		int idx = cstepE.index;
-		do {
-			nouveau_cstate_new(clk, idx, pstate);
-		} while(idx--);
-	}
-
-	nouveau_pstate_info(clk, pstate);
-	list_add_tail(&pstate->head, &clk->states);
-	clk->state_nr++;
-	return 0;
-}
-
-/******************************************************************************
- * Adjustment triggers
- *****************************************************************************/
-static int
-nouveau_clock_ustate_update(struct nouveau_clock *clk, int req)
-{
-	struct nouveau_pstate *pstate;
-	int i = 0;
-
-	if (!clk->allow_reclock)
-		return -ENOSYS;
-
-	if (req != -1 && req != -2) {
-		list_for_each_entry(pstate, &clk->states, head) {
-			if (pstate->pstate == req)
-				break;
-			i++;
-		}
-
-		if (pstate->pstate != req)
-			return -EINVAL;
-		req = i;
-	}
-
-	return req + 2;
-}
-
-static int
-nouveau_clock_nstate(struct nouveau_clock *clk, const char *mode, int arglen)
-{
-	int ret = 1;
-
-	if (strncasecmpz(mode, "disabled", arglen)) {
-		char save = mode[arglen];
-		long v;
-
-		((char *)mode)[arglen] = '\0';
-		if (!kstrtol(mode, 0, &v)) {
-			ret = nouveau_clock_ustate_update(clk, v);
-			if (ret < 0)
-				ret = 1;
-		}
-		((char *)mode)[arglen] = save;
-	}
-
-	return ret - 2;
-}
-
-int
-nouveau_clock_ustate(struct nouveau_clock *clk, int req, int pwr)
-{
-	int ret = nouveau_clock_ustate_update(clk, req);
-	if (ret >= 0) {
-		if (ret -= 2, pwr) clk->ustate_ac = ret;
-		else		   clk->ustate_dc = ret;
-		return nouveau_pstate_calc(clk, true);
-	}
-	return ret;
-}
-
-int
-nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel)
-{
-	if (!rel) clk->astate  = req;
-	if ( rel) clk->astate += rel;
-	clk->astate = min(clk->astate, clk->state_nr - 1);
-	clk->astate = max(clk->astate, 0);
-	return nouveau_pstate_calc(clk, true);
-}
-
-int
-nouveau_clock_tstate(struct nouveau_clock *clk, int req, int rel)
-{
-	if (!rel) clk->tstate  = req;
-	if ( rel) clk->tstate += rel;
-	clk->tstate = min(clk->tstate, 0);
-	clk->tstate = max(clk->tstate, -(clk->state_nr - 1));
-	return nouveau_pstate_calc(clk, true);
-}
-
-int
-nouveau_clock_dstate(struct nouveau_clock *clk, int req, int rel)
-{
-	if (!rel) clk->dstate  = req;
-	if ( rel) clk->dstate += rel;
-	clk->dstate = min(clk->dstate, clk->state_nr - 1);
-	clk->dstate = max(clk->dstate, 0);
-	return nouveau_pstate_calc(clk, true);
-}
-
-static int
-nouveau_clock_pwrsrc(struct nvkm_notify *notify)
-{
-	struct nouveau_clock *clk =
-		container_of(notify, typeof(*clk), pwrsrc_ntfy);
-	nouveau_pstate_calc(clk, false);
-	return NVKM_NOTIFY_DROP;
-}
-
-/******************************************************************************
- * subdev base class implementation
- *****************************************************************************/
-
-int
-_nouveau_clock_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nouveau_clock *clk = (void *)object;
-	nvkm_notify_put(&clk->pwrsrc_ntfy);
-	return nouveau_subdev_fini(&clk->base, suspend);
-}
-
-int
-_nouveau_clock_init(struct nouveau_object *object)
-{
-	struct nouveau_clock *clk = (void *)object;
-	struct nouveau_clocks *clock = clk->domains;
-	int ret;
-
-	ret = nouveau_subdev_init(&clk->base);
-	if (ret)
-		return ret;
-
-	memset(&clk->bstate, 0x00, sizeof(clk->bstate));
-	INIT_LIST_HEAD(&clk->bstate.list);
-	clk->bstate.pstate = 0xff;
-
-	while (clock->name != nv_clk_src_max) {
-		ret = clk->read(clk, clock->name);
-		if (ret < 0) {
-			nv_error(clk, "%02x freq unknown\n", clock->name);
-			return ret;
-		}
-		clk->bstate.base.domain[clock->name] = ret;
-		clock++;
-	}
-
-	nouveau_pstate_info(clk, &clk->bstate);
-
-	clk->astate = clk->state_nr - 1;
-	clk->tstate = 0;
-	clk->dstate = 0;
-	clk->pstate = -1;
-	nouveau_pstate_calc(clk, true);
-	return 0;
-}
-
-void
-_nouveau_clock_dtor(struct nouveau_object *object)
-{
-	struct nouveau_clock *clk = (void *)object;
-	struct nouveau_pstate *pstate, *temp;
-
-	nvkm_notify_fini(&clk->pwrsrc_ntfy);
-
-	list_for_each_entry_safe(pstate, temp, &clk->states, head) {
-		nouveau_pstate_del(pstate);
-	}
-
-	nouveau_subdev_destroy(&clk->base);
-}
-
-int
-nouveau_clock_create_(struct nouveau_object *parent,
-		      struct nouveau_object *engine,
-		      struct nouveau_oclass *oclass,
-		      struct nouveau_clocks *clocks,
-		      struct nouveau_pstate *pstates, int nb_pstates,
-		      bool allow_reclock,
-		      int length, void **object)
-{
-	struct nouveau_device *device = nv_device(parent);
-	struct nouveau_clock *clk;
-	int ret, idx, arglen;
-	const char *mode;
-
-	ret = nouveau_subdev_create_(parent, engine, oclass, 0, "CLK",
-				     "clock", length, object);
-	clk = *object;
-	if (ret)
-		return ret;
-
-	INIT_LIST_HEAD(&clk->states);
-	clk->domains = clocks;
-	clk->ustate_ac = -1;
-	clk->ustate_dc = -1;
-
-	INIT_WORK(&clk->work, nouveau_pstate_work);
-	init_waitqueue_head(&clk->wait);
-	atomic_set(&clk->waiting, 0);
-
-	/* If no pstates are provided, try and fetch them from the BIOS */
-	if (!pstates) {
-		idx = 0;
-		do {
-			ret = nouveau_pstate_new(clk, idx++);
-		} while (ret == 0);
-	} else {
-		for (idx = 0; idx < nb_pstates; idx++)
-			list_add_tail(&pstates[idx].head, &clk->states);
-		clk->state_nr = nb_pstates;
-	}
-
-	clk->allow_reclock = allow_reclock;
-
-	ret = nvkm_notify_init(NULL, &device->event, nouveau_clock_pwrsrc, true,
-			       NULL, 0, 0, &clk->pwrsrc_ntfy);
-	if (ret)
-		return ret;
-
-	mode = nouveau_stropt(device->cfgopt, "NvClkMode", &arglen);
-	if (mode) {
-		clk->ustate_ac = nouveau_clock_nstate(clk, mode, arglen);
-		clk->ustate_dc = nouveau_clock_nstate(clk, mode, arglen);
-	}
-
-	mode = nouveau_stropt(device->cfgopt, "NvClkModeAC", &arglen);
-	if (mode)
-		clk->ustate_ac = nouveau_clock_nstate(clk, mode, arglen);
-
-	mode = nouveau_stropt(device->cfgopt, "NvClkModeDC", &arglen);
-	if (mode)
-		clk->ustate_dc = nouveau_clock_nstate(clk, mode, arglen);
-
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c
deleted file mode 100644
index fb4fad374bdd..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c
+++ /dev/null
@@ -1,680 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c
- *
- */
-
-#define MHZ (1000 * 1000)
-
-#define MASK(w)	((1 << w) - 1)
-
-#define SYS_GPCPLL_CFG_BASE			0x00137000
-#define GPC_BCASE_GPCPLL_CFG_BASE		0x00132800
-
-#define GPCPLL_CFG		(SYS_GPCPLL_CFG_BASE + 0)
-#define GPCPLL_CFG_ENABLE	BIT(0)
-#define GPCPLL_CFG_IDDQ		BIT(1)
-#define GPCPLL_CFG_LOCK_DET_OFF	BIT(4)
-#define GPCPLL_CFG_LOCK		BIT(17)
-
-#define GPCPLL_COEFF		(SYS_GPCPLL_CFG_BASE + 4)
-#define GPCPLL_COEFF_M_SHIFT	0
-#define GPCPLL_COEFF_M_WIDTH	8
-#define GPCPLL_COEFF_N_SHIFT	8
-#define GPCPLL_COEFF_N_WIDTH	8
-#define GPCPLL_COEFF_P_SHIFT	16
-#define GPCPLL_COEFF_P_WIDTH	6
-
-#define GPCPLL_CFG2			(SYS_GPCPLL_CFG_BASE + 0xc)
-#define GPCPLL_CFG2_SETUP2_SHIFT	16
-#define GPCPLL_CFG2_PLL_STEPA_SHIFT	24
-
-#define GPCPLL_CFG3			(SYS_GPCPLL_CFG_BASE + 0x18)
-#define GPCPLL_CFG3_PLL_STEPB_SHIFT	16
-
-#define GPCPLL_NDIV_SLOWDOWN			(SYS_GPCPLL_CFG_BASE + 0x1c)
-#define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT	0
-#define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT	8
-#define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT	16
-#define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT	22
-#define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT	31
-
-#define SEL_VCO				(SYS_GPCPLL_CFG_BASE + 0x100)
-#define SEL_VCO_GPC2CLK_OUT_SHIFT	0
-
-#define GPC2CLK_OUT			(SYS_GPCPLL_CFG_BASE + 0x250)
-#define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH	1
-#define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT	31
-#define GPC2CLK_OUT_SDIV14_INDIV4_MODE	1
-#define GPC2CLK_OUT_VCODIV_WIDTH	6
-#define GPC2CLK_OUT_VCODIV_SHIFT	8
-#define GPC2CLK_OUT_VCODIV1		0
-#define GPC2CLK_OUT_VCODIV_MASK		(MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \
-					GPC2CLK_OUT_VCODIV_SHIFT)
-#define	GPC2CLK_OUT_BYPDIV_WIDTH	6
-#define GPC2CLK_OUT_BYPDIV_SHIFT	0
-#define GPC2CLK_OUT_BYPDIV31		0x3c
-#define GPC2CLK_OUT_INIT_MASK	((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \
-		GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\
-		| (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\
-		| (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT))
-#define GPC2CLK_OUT_INIT_VAL	((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \
-		GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \
-		| (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \
-		| (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT))
-
-#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG	(GPC_BCASE_GPCPLL_CFG_BASE + 0xa0)
-#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT	24
-#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \
-	    (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT)
-
-#include <subdev/clock.h>
-#include <subdev/timer.h>
-
-#ifdef __KERNEL__
-#include <nouveau_platform.h>
-#endif
-
-static const u8 pl_to_div[] = {
-/* PL:   0, 1, 2, 3, 4, 5, 6,  7,  8,  9, 10, 11, 12, 13, 14 */
-/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32,
-};
-
-/* All frequencies in Mhz */
-struct gk20a_clk_pllg_params {
-	u32 min_vco, max_vco;
-	u32 min_u, max_u;
-	u32 min_m, max_m;
-	u32 min_n, max_n;
-	u32 min_pl, max_pl;
-};
-
-static const struct gk20a_clk_pllg_params gk20a_pllg_params = {
-	.min_vco = 1000, .max_vco = 2064,
-	.min_u = 12, .max_u = 38,
-	.min_m = 1, .max_m = 255,
-	.min_n = 8, .max_n = 255,
-	.min_pl = 1, .max_pl = 32,
-};
-
-struct gk20a_clock_priv {
-	struct nouveau_clock base;
-	const struct gk20a_clk_pllg_params *params;
-	u32 m, n, pl;
-	u32 parent_rate;
-};
-#define to_gk20a_clock(base) container_of(base, struct gk20a_clock_priv, base)
-
-static void
-gk20a_pllg_read_mnp(struct gk20a_clock_priv *priv)
-{
-	u32 val;
-
-	val = nv_rd32(priv, GPCPLL_COEFF);
-	priv->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
-	priv->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH);
-	priv->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
-}
-
-static u32
-gk20a_pllg_calc_rate(struct gk20a_clock_priv *priv)
-{
-	u32 rate;
-	u32 divider;
-
-	rate = priv->parent_rate * priv->n;
-	divider = priv->m * pl_to_div[priv->pl];
-	do_div(rate, divider);
-
-	return rate / 2;
-}
-
-static int
-gk20a_pllg_calc_mnp(struct gk20a_clock_priv *priv, unsigned long rate)
-{
-	u32 target_clk_f, ref_clk_f, target_freq;
-	u32 min_vco_f, max_vco_f;
-	u32 low_pl, high_pl, best_pl;
-	u32 target_vco_f, vco_f;
-	u32 best_m, best_n;
-	u32 u_f;
-	u32 m, n, n2;
-	u32 delta, lwv, best_delta = ~0;
-	u32 pl;
-
-	target_clk_f = rate * 2 / MHZ;
-	ref_clk_f = priv->parent_rate / MHZ;
-
-	max_vco_f = priv->params->max_vco;
-	min_vco_f = priv->params->min_vco;
-	best_m = priv->params->max_m;
-	best_n = priv->params->min_n;
-	best_pl = priv->params->min_pl;
-
-	target_vco_f = target_clk_f + target_clk_f / 50;
-	if (max_vco_f < target_vco_f)
-		max_vco_f = target_vco_f;
-
-	/* min_pl <= high_pl <= max_pl */
-	high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f;
-	high_pl = min(high_pl, priv->params->max_pl);
-	high_pl = max(high_pl, priv->params->min_pl);
-
-	/* min_pl <= low_pl <= max_pl */
-	low_pl = min_vco_f / target_vco_f;
-	low_pl = min(low_pl, priv->params->max_pl);
-	low_pl = max(low_pl, priv->params->min_pl);
-
-	/* Find Indices of high_pl and low_pl */
-	for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) {
-		if (pl_to_div[pl] >= low_pl) {
-			low_pl = pl;
-			break;
-		}
-	}
-	for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) {
-		if (pl_to_div[pl] >= high_pl) {
-			high_pl = pl;
-			break;
-		}
-	}
-
-	nv_debug(priv, "low_PL %d(div%d), high_PL %d(div%d)", low_pl,
-		 pl_to_div[low_pl], high_pl, pl_to_div[high_pl]);
-
-	/* Select lowest possible VCO */
-	for (pl = low_pl; pl <= high_pl; pl++) {
-		target_vco_f = target_clk_f * pl_to_div[pl];
-		for (m = priv->params->min_m; m <= priv->params->max_m; m++) {
-			u_f = ref_clk_f / m;
-
-			if (u_f < priv->params->min_u)
-				break;
-			if (u_f > priv->params->max_u)
-				continue;
-
-			n = (target_vco_f * m) / ref_clk_f;
-			n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f;
-
-			if (n > priv->params->max_n)
-				break;
-
-			for (; n <= n2; n++) {
-				if (n < priv->params->min_n)
-					continue;
-				if (n > priv->params->max_n)
-					break;
-
-				vco_f = ref_clk_f * n / m;
-
-				if (vco_f >= min_vco_f && vco_f <= max_vco_f) {
-					lwv = (vco_f + (pl_to_div[pl] / 2))
-						/ pl_to_div[pl];
-					delta = abs(lwv - target_clk_f);
-
-					if (delta < best_delta) {
-						best_delta = delta;
-						best_m = m;
-						best_n = n;
-						best_pl = pl;
-
-						if (best_delta == 0)
-							goto found_match;
-					}
-				}
-			}
-		}
-	}
-
-found_match:
-	WARN_ON(best_delta == ~0);
-
-	if (best_delta != 0)
-		nv_debug(priv, "no best match for target @ %dMHz on gpc_pll",
-			 target_clk_f);
-
-	priv->m = best_m;
-	priv->n = best_n;
-	priv->pl = best_pl;
-
-	target_freq = gk20a_pllg_calc_rate(priv) / MHZ;
-
-	nv_debug(priv, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n",
-		 target_freq, priv->m, priv->n, priv->pl, pl_to_div[priv->pl]);
-
-	return 0;
-}
-
-static int
-gk20a_pllg_slide(struct gk20a_clock_priv *priv, u32 n)
-{
-	u32 val;
-	int ramp_timeout;
-
-	/* get old coefficients */
-	val = nv_rd32(priv, GPCPLL_COEFF);
-	/* do nothing if NDIV is the same */
-	if (n == ((val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH)))
-		return 0;
-
-	/* setup */
-	nv_mask(priv, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT,
-		0x2b << GPCPLL_CFG2_PLL_STEPA_SHIFT);
-	nv_mask(priv, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT,
-		0xb << GPCPLL_CFG3_PLL_STEPB_SHIFT);
-
-	/* pll slowdown mode */
-	nv_mask(priv, GPCPLL_NDIV_SLOWDOWN,
-		BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT),
-		BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT));
-
-	/* new ndiv ready for ramp */
-	val = nv_rd32(priv, GPCPLL_COEFF);
-	val &= ~(MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT);
-	val |= (n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT;
-	udelay(1);
-	nv_wr32(priv, GPCPLL_COEFF, val);
-
-	/* dynamic ramp to new ndiv */
-	val = nv_rd32(priv, GPCPLL_NDIV_SLOWDOWN);
-	val |= 0x1 << GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT;
-	udelay(1);
-	nv_wr32(priv, GPCPLL_NDIV_SLOWDOWN, val);
-
-	for (ramp_timeout = 500; ramp_timeout > 0; ramp_timeout--) {
-		udelay(1);
-		val = nv_rd32(priv, GPC_BCAST_NDIV_SLOWDOWN_DEBUG);
-		if (val & GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK)
-			break;
-	}
-
-	/* exit slowdown mode */
-	nv_mask(priv, GPCPLL_NDIV_SLOWDOWN,
-		BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) |
-		BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0);
-	nv_rd32(priv, GPCPLL_NDIV_SLOWDOWN);
-
-	if (ramp_timeout <= 0) {
-		nv_error(priv, "gpcpll dynamic ramp timeout\n");
-		return -ETIMEDOUT;
-	}
-
-	return 0;
-}
-
-static void
-_gk20a_pllg_enable(struct gk20a_clock_priv *priv)
-{
-	nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE);
-	nv_rd32(priv, GPCPLL_CFG);
-}
-
-static void
-_gk20a_pllg_disable(struct gk20a_clock_priv *priv)
-{
-	nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0);
-	nv_rd32(priv, GPCPLL_CFG);
-}
-
-static int
-_gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv, bool allow_slide)
-{
-	u32 val, cfg;
-	u32 m_old, pl_old, n_lo;
-
-	/* get old coefficients */
-	val = nv_rd32(priv, GPCPLL_COEFF);
-	m_old = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
-	pl_old = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
-
-	/* do NDIV slide if there is no change in M and PL */
-	cfg = nv_rd32(priv, GPCPLL_CFG);
-	if (allow_slide && priv->m == m_old && priv->pl == pl_old &&
-	    (cfg & GPCPLL_CFG_ENABLE)) {
-		return gk20a_pllg_slide(priv, priv->n);
-	}
-
-	/* slide down to NDIV_LO */
-	n_lo = DIV_ROUND_UP(m_old * priv->params->min_vco,
-			    priv->parent_rate / MHZ);
-	if (allow_slide && (cfg & GPCPLL_CFG_ENABLE)) {
-		int ret = gk20a_pllg_slide(priv, n_lo);
-
-		if (ret)
-			return ret;
-	}
-
-	/* split FO-to-bypass jump in halfs by setting out divider 1:2 */
-	nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,
-		0x2 << GPC2CLK_OUT_VCODIV_SHIFT);
-
-	/* put PLL in bypass before programming it */
-	val = nv_rd32(priv, SEL_VCO);
-	val &= ~(BIT(SEL_VCO_GPC2CLK_OUT_SHIFT));
-	udelay(2);
-	nv_wr32(priv, SEL_VCO, val);
-
-	/* get out from IDDQ */
-	val = nv_rd32(priv, GPCPLL_CFG);
-	if (val & GPCPLL_CFG_IDDQ) {
-		val &= ~GPCPLL_CFG_IDDQ;
-		nv_wr32(priv, GPCPLL_CFG, val);
-		nv_rd32(priv, GPCPLL_CFG);
-		udelay(2);
-	}
-
-	_gk20a_pllg_disable(priv);
-
-	nv_debug(priv, "%s: m=%d n=%d pl=%d\n", __func__, priv->m, priv->n,
-		 priv->pl);
-
-	n_lo = DIV_ROUND_UP(priv->m * priv->params->min_vco,
-			    priv->parent_rate / MHZ);
-	val = priv->m << GPCPLL_COEFF_M_SHIFT;
-	val |= (allow_slide ? n_lo : priv->n) << GPCPLL_COEFF_N_SHIFT;
-	val |= priv->pl << GPCPLL_COEFF_P_SHIFT;
-	nv_wr32(priv, GPCPLL_COEFF, val);
-
-	_gk20a_pllg_enable(priv);
-
-	val = nv_rd32(priv, GPCPLL_CFG);
-	if (val & GPCPLL_CFG_LOCK_DET_OFF) {
-		val &= ~GPCPLL_CFG_LOCK_DET_OFF;
-		nv_wr32(priv, GPCPLL_CFG, val);
-	}
-
-	if (!nouveau_timer_wait_eq(priv, 300000, GPCPLL_CFG, GPCPLL_CFG_LOCK,
-				   GPCPLL_CFG_LOCK)) {
-		nv_error(priv, "%s: timeout waiting for pllg lock\n", __func__);
-		return -ETIMEDOUT;
-	}
-
-	/* switch to VCO mode */
-	nv_mask(priv, SEL_VCO, 0, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT));
-
-	/* restore out divider 1:1 */
-	val = nv_rd32(priv, GPC2CLK_OUT);
-	val &= ~GPC2CLK_OUT_VCODIV_MASK;
-	udelay(2);
-	nv_wr32(priv, GPC2CLK_OUT, val);
-
-	/* slide up to new NDIV */
-	return allow_slide ? gk20a_pllg_slide(priv, priv->n) : 0;
-}
-
-static int
-gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv)
-{
-	int err;
-
-	err = _gk20a_pllg_program_mnp(priv, true);
-	if (err)
-		err = _gk20a_pllg_program_mnp(priv, false);
-
-	return err;
-}
-
-static void
-gk20a_pllg_disable(struct gk20a_clock_priv *priv)
-{
-	u32 val;
-
-	/* slide to VCO min */
-	val = nv_rd32(priv, GPCPLL_CFG);
-	if (val & GPCPLL_CFG_ENABLE) {
-		u32 coeff, m, n_lo;
-
-		coeff = nv_rd32(priv, GPCPLL_COEFF);
-		m = (coeff >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
-		n_lo = DIV_ROUND_UP(m * priv->params->min_vco,
-				    priv->parent_rate / MHZ);
-		gk20a_pllg_slide(priv, n_lo);
-	}
-
-	/* put PLL in bypass before disabling it */
-	nv_mask(priv, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0);
-
-	_gk20a_pllg_disable(priv);
-}
-
-#define GK20A_CLK_GPC_MDIV 1000
-
-static struct nouveau_clocks
-gk20a_domains[] = {
-	{ nv_clk_src_crystal, 0xff },
-	{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
-	{ nv_clk_src_max }
-};
-
-static struct nouveau_pstate
-gk20a_pstates[] = {
-	{
-		.base = {
-			.domain[nv_clk_src_gpc] = 72000,
-			.voltage = 0,
-		},
-	},
-	{
-		.base = {
-			.domain[nv_clk_src_gpc] = 108000,
-			.voltage = 1,
-		},
-	},
-	{
-		.base = {
-			.domain[nv_clk_src_gpc] = 180000,
-			.voltage = 2,
-		},
-	},
-	{
-		.base = {
-			.domain[nv_clk_src_gpc] = 252000,
-			.voltage = 3,
-		},
-	},
-	{
-		.base = {
-			.domain[nv_clk_src_gpc] = 324000,
-			.voltage = 4,
-		},
-	},
-	{
-		.base = {
-			.domain[nv_clk_src_gpc] = 396000,
-			.voltage = 5,
-		},
-	},
-	{
-		.base = {
-			.domain[nv_clk_src_gpc] = 468000,
-			.voltage = 6,
-		},
-	},
-	{
-		.base = {
-			.domain[nv_clk_src_gpc] = 540000,
-			.voltage = 7,
-		},
-	},
-	{
-		.base = {
-			.domain[nv_clk_src_gpc] = 612000,
-			.voltage = 8,
-		},
-	},
-	{
-		.base = {
-			.domain[nv_clk_src_gpc] = 648000,
-			.voltage = 9,
-		},
-	},
-	{
-		.base = {
-			.domain[nv_clk_src_gpc] = 684000,
-			.voltage = 10,
-		},
-	},
-	{
-		.base = {
-			.domain[nv_clk_src_gpc] = 708000,
-			.voltage = 11,
-		},
-	},
-	{
-		.base = {
-			.domain[nv_clk_src_gpc] = 756000,
-			.voltage = 12,
-		},
-	},
-	{
-		.base = {
-			.domain[nv_clk_src_gpc] = 804000,
-			.voltage = 13,
-		},
-	},
-	{
-		.base = {
-			.domain[nv_clk_src_gpc] = 852000,
-			.voltage = 14,
-		},
-	},
-};
-
-static int
-gk20a_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
-{
-	struct gk20a_clock_priv *priv = (void *)clk;
-
-	switch (src) {
-	case nv_clk_src_crystal:
-		return nv_device(clk)->crystal;
-	case nv_clk_src_gpc:
-		gk20a_pllg_read_mnp(priv);
-		return gk20a_pllg_calc_rate(priv) / GK20A_CLK_GPC_MDIV;
-	default:
-		nv_error(clk, "invalid clock source %d\n", src);
-		return -EINVAL;
-	}
-}
-
-static int
-gk20a_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
-{
-	struct gk20a_clock_priv *priv = (void *)clk;
-
-	return gk20a_pllg_calc_mnp(priv, cstate->domain[nv_clk_src_gpc] *
-					 GK20A_CLK_GPC_MDIV);
-}
-
-static int
-gk20a_clock_prog(struct nouveau_clock *clk)
-{
-	struct gk20a_clock_priv *priv = (void *)clk;
-
-	return gk20a_pllg_program_mnp(priv);
-}
-
-static void
-gk20a_clock_tidy(struct nouveau_clock *clk)
-{
-}
-
-static int
-gk20a_clock_fini(struct nouveau_object *object, bool suspend)
-{
-	struct gk20a_clock_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_clock_fini(&priv->base, false);
-
-	gk20a_pllg_disable(priv);
-
-	return ret;
-}
-
-static int
-gk20a_clock_init(struct nouveau_object *object)
-{
-	struct gk20a_clock_priv *priv = (void *)object;
-	int ret;
-
-	nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL);
-
-	ret = nouveau_clock_init(&priv->base);
-	if (ret)
-		return ret;
-
-	ret = gk20a_clock_prog(&priv->base);
-	if (ret) {
-		nv_error(priv, "cannot initialize clock\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static int
-gk20a_clock_ctor(struct nouveau_object *parent,  struct nouveau_object *engine,
-		 struct nouveau_oclass *oclass, void *data, u32 size,
-		 struct nouveau_object **pobject)
-{
-	struct gk20a_clock_priv *priv;
-	struct nouveau_platform_device *plat;
-	int ret;
-	int i;
-
-	/* Finish initializing the pstates */
-	for (i = 0; i < ARRAY_SIZE(gk20a_pstates); i++) {
-		INIT_LIST_HEAD(&gk20a_pstates[i].list);
-		gk20a_pstates[i].pstate = i + 1;
-	}
-
-	ret = nouveau_clock_create(parent, engine, oclass, gk20a_domains,
-			gk20a_pstates, ARRAY_SIZE(gk20a_pstates), true, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->params = &gk20a_pllg_params;
-
-	plat = nv_device_to_platform(nv_device(parent));
-	priv->parent_rate = clk_get_rate(plat->gpu->clk);
-	nv_info(priv, "parent clock rate: %d Mhz\n", priv->parent_rate / MHZ);
-
-	priv->base.read = gk20a_clock_read;
-	priv->base.calc = gk20a_clock_calc;
-	priv->base.prog = gk20a_clock_prog;
-	priv->base.tidy = gk20a_clock_tidy;
-
-	return 0;
-}
-
-struct nouveau_oclass
-gk20a_clock_oclass = {
-	.handle = NV_SUBDEV(CLOCK, 0xea),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = gk20a_clock_ctor,
-		.dtor = _nouveau_subdev_dtor,
-		.init = gk20a_clock_init,
-		.fini = gk20a_clock_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c
deleted file mode 100644
index 4c48232686be..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/pll.h>
-#include <subdev/clock.h>
-#include <subdev/devinit/nv04.h>
-
-#include "pll.h"
-
-struct nv04_clock_priv {
-	struct nouveau_clock base;
-};
-
-int
-nv04_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
-		    int clk, struct nouveau_pll_vals *pv)
-{
-	int N1, M1, N2, M2, P;
-	int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P);
-	if (ret) {
-		pv->refclk = info->refclk;
-		pv->N1 = N1;
-		pv->M1 = M1;
-		pv->N2 = N2;
-		pv->M2 = M2;
-		pv->log2P = P;
-	}
-	return ret;
-}
-
-int
-nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1,
-		    struct nouveau_pll_vals *pv)
-{
-	struct nouveau_devinit *devinit = nouveau_devinit(clk);
-	int cv = nouveau_bios(clk)->version.chip;
-
-	if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
-	    cv >= 0x40) {
-		if (reg1 > 0x405c)
-			setPLL_double_highregs(devinit, reg1, pv);
-		else
-			setPLL_double_lowregs(devinit, reg1, pv);
-	} else
-		setPLL_single(devinit, reg1, pv);
-
-	return 0;
-}
-
-static struct nouveau_clocks
-nv04_domain[] = {
-	{ nv_clk_src_max }
-};
-
-static int
-nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nv04_clock_priv *priv;
-	int ret;
-
-	ret = nouveau_clock_create(parent, engine, oclass, nv04_domain, NULL, 0,
-				   false, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.pll_calc = nv04_clock_pll_calc;
-	priv->base.pll_prog = nv04_clock_pll_prog;
-	return 0;
-}
-
-struct nouveau_oclass
-nv04_clock_oclass = {
-	.handle = NV_SUBDEV(CLOCK, 0x04),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_clock_ctor,
-		.dtor = _nouveau_clock_dtor,
-		.init = _nouveau_clock_init,
-		.fini = _nouveau_clock_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c
deleted file mode 100644
index 08368fe97029..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/clock.h>
-#include <subdev/bios.h>
-#include <subdev/bios/pll.h>
-
-#include "pll.h"
-
-struct nv40_clock_priv {
-	struct nouveau_clock base;
-	u32 ctrl;
-	u32 npll_ctrl;
-	u32 npll_coef;
-	u32 spll;
-};
-
-static struct nouveau_clocks
-nv40_domain[] = {
-	{ nv_clk_src_crystal, 0xff },
-	{ nv_clk_src_href   , 0xff },
-	{ nv_clk_src_core   , 0xff, 0, "core", 1000 },
-	{ nv_clk_src_shader , 0xff, 0, "shader", 1000 },
-	{ nv_clk_src_mem    , 0xff, 0, "memory", 1000 },
-	{ nv_clk_src_max }
-};
-
-static u32
-read_pll_1(struct nv40_clock_priv *priv, u32 reg)
-{
-	u32 ctrl = nv_rd32(priv, reg + 0x00);
-	int P = (ctrl & 0x00070000) >> 16;
-	int N = (ctrl & 0x0000ff00) >> 8;
-	int M = (ctrl & 0x000000ff) >> 0;
-	u32 ref = 27000, clk = 0;
-
-	if (ctrl & 0x80000000)
-		clk = ref * N / M;
-
-	return clk >> P;
-}
-
-static u32
-read_pll_2(struct nv40_clock_priv *priv, u32 reg)
-{
-	u32 ctrl = nv_rd32(priv, reg + 0x00);
-	u32 coef = nv_rd32(priv, reg + 0x04);
-	int N2 = (coef & 0xff000000) >> 24;
-	int M2 = (coef & 0x00ff0000) >> 16;
-	int N1 = (coef & 0x0000ff00) >> 8;
-	int M1 = (coef & 0x000000ff) >> 0;
-	int P = (ctrl & 0x00070000) >> 16;
-	u32 ref = 27000, clk = 0;
-
-	if ((ctrl & 0x80000000) && M1) {
-		clk = ref * N1 / M1;
-		if ((ctrl & 0x40000100) == 0x40000000) {
-			if (M2)
-				clk = clk * N2 / M2;
-			else
-				clk = 0;
-		}
-	}
-
-	return clk >> P;
-}
-
-static u32
-read_clk(struct nv40_clock_priv *priv, u32 src)
-{
-	switch (src) {
-	case 3:
-		return read_pll_2(priv, 0x004000);
-	case 2:
-		return read_pll_1(priv, 0x004008);
-	default:
-		break;
-	}
-
-	return 0;
-}
-
-static int
-nv40_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
-{
-	struct nv40_clock_priv *priv = (void *)clk;
-	u32 mast = nv_rd32(priv, 0x00c040);
-
-	switch (src) {
-	case nv_clk_src_crystal:
-		return nv_device(priv)->crystal;
-	case nv_clk_src_href:
-		return 100000; /*XXX: PCIE/AGP differ*/
-	case nv_clk_src_core:
-		return read_clk(priv, (mast & 0x00000003) >> 0);
-	case nv_clk_src_shader:
-		return read_clk(priv, (mast & 0x00000030) >> 4);
-	case nv_clk_src_mem:
-		return read_pll_2(priv, 0x4020);
-	default:
-		break;
-	}
-
-	nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast);
-	return -EINVAL;
-}
-
-static int
-nv40_clock_calc_pll(struct nv40_clock_priv *priv, u32 reg, u32 clk,
-		    int *N1, int *M1, int *N2, int *M2, int *log2P)
-{
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	struct nvbios_pll pll;
-	int ret;
-
-	ret = nvbios_pll_parse(bios, reg, &pll);
-	if (ret)
-		return ret;
-
-	if (clk < pll.vco1.max_freq)
-		pll.vco2.max_freq = 0;
-
-	ret = nv04_pll_calc(nv_subdev(priv), &pll, clk, N1, M1, N2, M2, log2P);
-	if (ret == 0)
-		return -ERANGE;
-	return ret;
-}
-
-static int
-nv40_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
-{
-	struct nv40_clock_priv *priv = (void *)clk;
-	int gclk = cstate->domain[nv_clk_src_core];
-	int sclk = cstate->domain[nv_clk_src_shader];
-	int N1, M1, N2, M2, log2P;
-	int ret;
-
-	/* core/geometric clock */
-	ret = nv40_clock_calc_pll(priv, 0x004000, gclk,
-				 &N1, &M1, &N2, &M2, &log2P);
-	if (ret < 0)
-		return ret;
-
-	if (N2 == M2) {
-		priv->npll_ctrl = 0x80000100 | (log2P << 16);
-		priv->npll_coef = (N1 << 8) | M1;
-	} else {
-		priv->npll_ctrl = 0xc0000000 | (log2P << 16);
-		priv->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
-	}
-
-	/* use the second pll for shader/rop clock, if it differs from core */
-	if (sclk && sclk != gclk) {
-		ret = nv40_clock_calc_pll(priv, 0x004008, sclk,
-					 &N1, &M1, NULL, NULL, &log2P);
-		if (ret < 0)
-			return ret;
-
-		priv->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;
-		priv->ctrl = 0x00000223;
-	} else {
-		priv->spll = 0x00000000;
-		priv->ctrl = 0x00000333;
-	}
-
-	return 0;
-}
-
-static int
-nv40_clock_prog(struct nouveau_clock *clk)
-{
-	struct nv40_clock_priv *priv = (void *)clk;
-	nv_mask(priv, 0x00c040, 0x00000333, 0x00000000);
-	nv_wr32(priv, 0x004004, priv->npll_coef);
-	nv_mask(priv, 0x004000, 0xc0070100, priv->npll_ctrl);
-	nv_mask(priv, 0x004008, 0xc007ffff, priv->spll);
-	mdelay(5);
-	nv_mask(priv, 0x00c040, 0x00000333, priv->ctrl);
-	return 0;
-}
-
-static void
-nv40_clock_tidy(struct nouveau_clock *clk)
-{
-}
-
-static int
-nv40_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nv40_clock_priv *priv;
-	int ret;
-
-	ret = nouveau_clock_create(parent, engine, oclass, nv40_domain, NULL, 0,
-				   true, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.pll_calc = nv04_clock_pll_calc;
-	priv->base.pll_prog = nv04_clock_pll_prog;
-	priv->base.read = nv40_clock_read;
-	priv->base.calc = nv40_clock_calc;
-	priv->base.prog = nv40_clock_prog;
-	priv->base.tidy = nv40_clock_tidy;
-	return 0;
-}
-
-struct nouveau_oclass
-nv40_clock_oclass = {
-	.handle = NV_SUBDEV(CLOCK, 0x40),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv40_clock_ctor,
-		.dtor = _nouveau_clock_dtor,
-		.init = _nouveau_clock_init,
-		.fini = _nouveau_clock_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c
deleted file mode 100644
index 5070ebc260f8..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c
+++ /dev/null
@@ -1,559 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/pll.h>
-
-#include "nv50.h"
-#include "pll.h"
-#include "seq.h"
-
-static u32
-read_div(struct nv50_clock_priv *priv)
-{
-	switch (nv_device(priv)->chipset) {
-	case 0x50: /* it exists, but only has bit 31, not the dividers.. */
-	case 0x84:
-	case 0x86:
-	case 0x98:
-	case 0xa0:
-		return nv_rd32(priv, 0x004700);
-	case 0x92:
-	case 0x94:
-	case 0x96:
-		return nv_rd32(priv, 0x004800);
-	default:
-		return 0x00000000;
-	}
-}
-
-static u32
-read_pll_src(struct nv50_clock_priv *priv, u32 base)
-{
-	struct nouveau_clock *clk = &priv->base;
-	u32 coef, ref = clk->read(clk, nv_clk_src_crystal);
-	u32 rsel = nv_rd32(priv, 0x00e18c);
-	int P, N, M, id;
-
-	switch (nv_device(priv)->chipset) {
-	case 0x50:
-	case 0xa0:
-		switch (base) {
-		case 0x4020:
-		case 0x4028: id = !!(rsel & 0x00000004); break;
-		case 0x4008: id = !!(rsel & 0x00000008); break;
-		case 0x4030: id = 0; break;
-		default:
-			nv_error(priv, "ref: bad pll 0x%06x\n", base);
-			return 0;
-		}
-
-		coef = nv_rd32(priv, 0x00e81c + (id * 0x0c));
-		ref *=  (coef & 0x01000000) ? 2 : 4;
-		P    =  (coef & 0x00070000) >> 16;
-		N    = ((coef & 0x0000ff00) >> 8) + 1;
-		M    = ((coef & 0x000000ff) >> 0) + 1;
-		break;
-	case 0x84:
-	case 0x86:
-	case 0x92:
-		coef = nv_rd32(priv, 0x00e81c);
-		P    = (coef & 0x00070000) >> 16;
-		N    = (coef & 0x0000ff00) >> 8;
-		M    = (coef & 0x000000ff) >> 0;
-		break;
-	case 0x94:
-	case 0x96:
-	case 0x98:
-		rsel = nv_rd32(priv, 0x00c050);
-		switch (base) {
-		case 0x4020: rsel = (rsel & 0x00000003) >> 0; break;
-		case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break;
-		case 0x4028: rsel = (rsel & 0x00001800) >> 11; break;
-		case 0x4030: rsel = 3; break;
-		default:
-			nv_error(priv, "ref: bad pll 0x%06x\n", base);
-			return 0;
-		}
-
-		switch (rsel) {
-		case 0: id = 1; break;
-		case 1: return clk->read(clk, nv_clk_src_crystal);
-		case 2: return clk->read(clk, nv_clk_src_href);
-		case 3: id = 0; break;
-		}
-
-		coef =  nv_rd32(priv, 0x00e81c + (id * 0x28));
-		P    = (nv_rd32(priv, 0x00e824 + (id * 0x28)) >> 16) & 7;
-		P   += (coef & 0x00070000) >> 16;
-		N    = (coef & 0x0000ff00) >> 8;
-		M    = (coef & 0x000000ff) >> 0;
-		break;
-	default:
-		BUG_ON(1);
-	}
-
-	if (M)
-		return (ref * N / M) >> P;
-	return 0;
-}
-
-static u32
-read_pll_ref(struct nv50_clock_priv *priv, u32 base)
-{
-	struct nouveau_clock *clk = &priv->base;
-	u32 src, mast = nv_rd32(priv, 0x00c040);
-
-	switch (base) {
-	case 0x004028:
-		src = !!(mast & 0x00200000);
-		break;
-	case 0x004020:
-		src = !!(mast & 0x00400000);
-		break;
-	case 0x004008:
-		src = !!(mast & 0x00010000);
-		break;
-	case 0x004030:
-		src = !!(mast & 0x02000000);
-		break;
-	case 0x00e810:
-		return clk->read(clk, nv_clk_src_crystal);
-	default:
-		nv_error(priv, "bad pll 0x%06x\n", base);
-		return 0;
-	}
-
-	if (src)
-		return clk->read(clk, nv_clk_src_href);
-	return read_pll_src(priv, base);
-}
-
-static u32
-read_pll(struct nv50_clock_priv *priv, u32 base)
-{
-	struct nouveau_clock *clk = &priv->base;
-	u32 mast = nv_rd32(priv, 0x00c040);
-	u32 ctrl = nv_rd32(priv, base + 0);
-	u32 coef = nv_rd32(priv, base + 4);
-	u32 ref = read_pll_ref(priv, base);
-	u32 freq = 0;
-	int N1, N2, M1, M2;
-
-	if (base == 0x004028 && (mast & 0x00100000)) {
-		/* wtf, appears to only disable post-divider on nva0 */
-		if (nv_device(priv)->chipset != 0xa0)
-			return clk->read(clk, nv_clk_src_dom6);
-	}
-
-	N2 = (coef & 0xff000000) >> 24;
-	M2 = (coef & 0x00ff0000) >> 16;
-	N1 = (coef & 0x0000ff00) >> 8;
-	M1 = (coef & 0x000000ff);
-	if ((ctrl & 0x80000000) && M1) {
-		freq = ref * N1 / M1;
-		if ((ctrl & 0x40000100) == 0x40000000) {
-			if (M2)
-				freq = freq * N2 / M2;
-			else
-				freq = 0;
-		}
-	}
-
-	return freq;
-}
-
-static int
-nv50_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
-{
-	struct nv50_clock_priv *priv = (void *)clk;
-	u32 mast = nv_rd32(priv, 0x00c040);
-	u32 P = 0;
-
-	switch (src) {
-	case nv_clk_src_crystal:
-		return nv_device(priv)->crystal;
-	case nv_clk_src_href:
-		return 100000; /* PCIE reference clock */
-	case nv_clk_src_hclk:
-		return div_u64((u64)clk->read(clk, nv_clk_src_href) * 27778, 10000);
-	case nv_clk_src_hclkm3:
-		return clk->read(clk, nv_clk_src_hclk) * 3;
-	case nv_clk_src_hclkm3d2:
-		return clk->read(clk, nv_clk_src_hclk) * 3 / 2;
-	case nv_clk_src_host:
-		switch (mast & 0x30000000) {
-		case 0x00000000: return clk->read(clk, nv_clk_src_href);
-		case 0x10000000: break;
-		case 0x20000000: /* !0x50 */
-		case 0x30000000: return clk->read(clk, nv_clk_src_hclk);
-		}
-		break;
-	case nv_clk_src_core:
-		if (!(mast & 0x00100000))
-			P = (nv_rd32(priv, 0x004028) & 0x00070000) >> 16;
-		switch (mast & 0x00000003) {
-		case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P;
-		case 0x00000001: return clk->read(clk, nv_clk_src_dom6);
-		case 0x00000002: return read_pll(priv, 0x004020) >> P;
-		case 0x00000003: return read_pll(priv, 0x004028) >> P;
-		}
-		break;
-	case nv_clk_src_shader:
-		P = (nv_rd32(priv, 0x004020) & 0x00070000) >> 16;
-		switch (mast & 0x00000030) {
-		case 0x00000000:
-			if (mast & 0x00000080)
-				return clk->read(clk, nv_clk_src_host) >> P;
-			return clk->read(clk, nv_clk_src_crystal) >> P;
-		case 0x00000010: break;
-		case 0x00000020: return read_pll(priv, 0x004028) >> P;
-		case 0x00000030: return read_pll(priv, 0x004020) >> P;
-		}
-		break;
-	case nv_clk_src_mem:
-		P = (nv_rd32(priv, 0x004008) & 0x00070000) >> 16;
-		if (nv_rd32(priv, 0x004008) & 0x00000200) {
-			switch (mast & 0x0000c000) {
-			case 0x00000000:
-				return clk->read(clk, nv_clk_src_crystal) >> P;
-			case 0x00008000:
-			case 0x0000c000:
-				return clk->read(clk, nv_clk_src_href) >> P;
-			}
-		} else {
-			return read_pll(priv, 0x004008) >> P;
-		}
-		break;
-	case nv_clk_src_vdec:
-		P = (read_div(priv) & 0x00000700) >> 8;
-		switch (nv_device(priv)->chipset) {
-		case 0x84:
-		case 0x86:
-		case 0x92:
-		case 0x94:
-		case 0x96:
-		case 0xa0:
-			switch (mast & 0x00000c00) {
-			case 0x00000000:
-				if (nv_device(priv)->chipset == 0xa0) /* wtf?? */
-					return clk->read(clk, nv_clk_src_core) >> P;
-				return clk->read(clk, nv_clk_src_crystal) >> P;
-			case 0x00000400:
-				return 0;
-			case 0x00000800:
-				if (mast & 0x01000000)
-					return read_pll(priv, 0x004028) >> P;
-				return read_pll(priv, 0x004030) >> P;
-			case 0x00000c00:
-				return clk->read(clk, nv_clk_src_core) >> P;
-			}
-			break;
-		case 0x98:
-			switch (mast & 0x00000c00) {
-			case 0x00000000:
-				return clk->read(clk, nv_clk_src_core) >> P;
-			case 0x00000400:
-				return 0;
-			case 0x00000800:
-				return clk->read(clk, nv_clk_src_hclkm3d2) >> P;
-			case 0x00000c00:
-				return clk->read(clk, nv_clk_src_mem) >> P;
-			}
-			break;
-		}
-		break;
-	case nv_clk_src_dom6:
-		switch (nv_device(priv)->chipset) {
-		case 0x50:
-		case 0xa0:
-			return read_pll(priv, 0x00e810) >> 2;
-		case 0x84:
-		case 0x86:
-		case 0x92:
-		case 0x94:
-		case 0x96:
-		case 0x98:
-			P = (read_div(priv) & 0x00000007) >> 0;
-			switch (mast & 0x0c000000) {
-			case 0x00000000: return clk->read(clk, nv_clk_src_href);
-			case 0x04000000: break;
-			case 0x08000000: return clk->read(clk, nv_clk_src_hclk);
-			case 0x0c000000:
-				return clk->read(clk, nv_clk_src_hclkm3) >> P;
-			}
-			break;
-		default:
-			break;
-		}
-	default:
-		break;
-	}
-
-	nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast);
-	return -EINVAL;
-}
-
-static u32
-calc_pll(struct nv50_clock_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P)
-{
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	struct nvbios_pll pll;
-	int ret;
-
-	ret = nvbios_pll_parse(bios, reg, &pll);
-	if (ret)
-		return 0;
-
-	pll.vco2.max_freq = 0;
-	pll.refclk = read_pll_ref(priv, reg);
-	if (!pll.refclk)
-		return 0;
-
-	return nv04_pll_calc(nv_subdev(priv), &pll, clk, N, M, NULL, NULL, P);
-}
-
-static inline u32
-calc_div(u32 src, u32 target, int *div)
-{
-	u32 clk0 = src, clk1 = src;
-	for (*div = 0; *div <= 7; (*div)++) {
-		if (clk0 <= target) {
-			clk1 = clk0 << (*div ? 1 : 0);
-			break;
-		}
-		clk0 >>= 1;
-	}
-
-	if (target - clk0 <= clk1 - target)
-		return clk0;
-	(*div)--;
-	return clk1;
-}
-
-static inline u32
-clk_same(u32 a, u32 b)
-{
-	return ((a / 1000) == (b / 1000));
-}
-
-static int
-nv50_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
-{
-	struct nv50_clock_priv *priv = (void *)clk;
-	struct nv50_clock_hwsq *hwsq = &priv->hwsq;
-	const int shader = cstate->domain[nv_clk_src_shader];
-	const int core = cstate->domain[nv_clk_src_core];
-	const int vdec = cstate->domain[nv_clk_src_vdec];
-	const int dom6 = cstate->domain[nv_clk_src_dom6];
-	u32 mastm = 0, mastv = 0;
-	u32 divsm = 0, divsv = 0;
-	int N, M, P1, P2;
-	int freq, out;
-
-	/* prepare a hwsq script from which we'll perform the reclock */
-	out = clk_init(hwsq, nv_subdev(clk));
-	if (out)
-		return out;
-
-	clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */
-	clk_nsec(hwsq, 8000);
-	clk_setf(hwsq, 0x10, 0x00); /* disable fb */
-	clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */
-
-	/* vdec: avoid modifying xpll until we know exactly how the other
-	 * clock domains work, i suspect at least some of them can also be
-	 * tied to xpll...
-	 */
-	if (vdec) {
-		/* see how close we can get using nvclk as a source */
-		freq = calc_div(core, vdec, &P1);
-
-		/* see how close we can get using xpll/hclk as a source */
-		if (nv_device(priv)->chipset != 0x98)
-			out = read_pll(priv, 0x004030);
-		else
-			out = clk->read(clk, nv_clk_src_hclkm3d2);
-		out = calc_div(out, vdec, &P2);
-
-		/* select whichever gets us closest */
-		if (abs(vdec - freq) <= abs(vdec - out)) {
-			if (nv_device(priv)->chipset != 0x98)
-				mastv |= 0x00000c00;
-			divsv |= P1 << 8;
-		} else {
-			mastv |= 0x00000800;
-			divsv |= P2 << 8;
-		}
-
-		mastm |= 0x00000c00;
-		divsm |= 0x00000700;
-	}
-
-	/* dom6: nfi what this is, but we're limited to various combinations
-	 * of the host clock frequency
-	 */
-	if (dom6) {
-		if (clk_same(dom6, clk->read(clk, nv_clk_src_href))) {
-			mastv |= 0x00000000;
-		} else
-		if (clk_same(dom6, clk->read(clk, nv_clk_src_hclk))) {
-			mastv |= 0x08000000;
-		} else {
-			freq = clk->read(clk, nv_clk_src_hclk) * 3;
-			freq = calc_div(freq, dom6, &P1);
-
-			mastv |= 0x0c000000;
-			divsv |= P1;
-		}
-
-		mastm |= 0x0c000000;
-		divsm |= 0x00000007;
-	}
-
-	/* vdec/dom6: switch to "safe" clocks temporarily, update dividers
-	 * and then switch to target clocks
-	 */
-	clk_mask(hwsq, mast, mastm, 0x00000000);
-	clk_mask(hwsq, divs, divsm, divsv);
-	clk_mask(hwsq, mast, mastm, mastv);
-
-	/* core/shader: disconnect nvclk/sclk from their PLLs (nvclk to dom6,
-	 * sclk to hclk) before reprogramming
-	 */
-	if (nv_device(priv)->chipset < 0x92)
-		clk_mask(hwsq, mast, 0x001000b0, 0x00100080);
-	else
-		clk_mask(hwsq, mast, 0x000000b3, 0x00000081);
-
-	/* core: for the moment at least, always use nvpll */
-	freq = calc_pll(priv, 0x4028, core, &N, &M, &P1);
-	if (freq == 0)
-		return -ERANGE;
-
-	clk_mask(hwsq, nvpll[0], 0xc03f0100,
-				 0x80000000 | (P1 << 19) | (P1 << 16));
-	clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M);
-
-	/* shader: tie to nvclk if possible, otherwise use spll.  have to be
-	 * very careful that the shader clock is at least twice the core, or
-	 * some chipsets will be very unhappy.  i expect most or all of these
-	 * cases will be handled by tying to nvclk, but it's possible there's
-	 * corners
-	 */
-	if (P1-- && shader == (core << 1)) {
-		clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16));
-		clk_mask(hwsq, mast, 0x00100033, 0x00000023);
-	} else {
-		freq = calc_pll(priv, 0x4020, shader, &N, &M, &P1);
-		if (freq == 0)
-			return -ERANGE;
-
-		clk_mask(hwsq, spll[0], 0xc03f0100,
-					0x80000000 | (P1 << 19) | (P1 << 16));
-		clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M);
-		clk_mask(hwsq, mast, 0x00100033, 0x00000033);
-	}
-
-	/* restore normal operation */
-	clk_setf(hwsq, 0x10, 0x01); /* enable fb */
-	clk_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */
-	clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */
-	return 0;
-}
-
-static int
-nv50_clock_prog(struct nouveau_clock *clk)
-{
-	struct nv50_clock_priv *priv = (void *)clk;
-	return clk_exec(&priv->hwsq, true);
-}
-
-static void
-nv50_clock_tidy(struct nouveau_clock *clk)
-{
-	struct nv50_clock_priv *priv = (void *)clk;
-	clk_exec(&priv->hwsq, false);
-}
-
-int
-nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nv50_clock_oclass *pclass = (void *)oclass;
-	struct nv50_clock_priv *priv;
-	int ret;
-
-	ret = nouveau_clock_create(parent, engine, oclass, pclass->domains,
-				   NULL, 0, false, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->hwsq.r_fifo = hwsq_reg(0x002504);
-	priv->hwsq.r_spll[0] = hwsq_reg(0x004020);
-	priv->hwsq.r_spll[1] = hwsq_reg(0x004024);
-	priv->hwsq.r_nvpll[0] = hwsq_reg(0x004028);
-	priv->hwsq.r_nvpll[1] = hwsq_reg(0x00402c);
-	switch (nv_device(priv)->chipset) {
-	case 0x92:
-	case 0x94:
-	case 0x96:
-		priv->hwsq.r_divs = hwsq_reg(0x004800);
-		break;
-	default:
-		priv->hwsq.r_divs = hwsq_reg(0x004700);
-		break;
-	}
-	priv->hwsq.r_mast = hwsq_reg(0x00c040);
-
-	priv->base.read = nv50_clock_read;
-	priv->base.calc = nv50_clock_calc;
-	priv->base.prog = nv50_clock_prog;
-	priv->base.tidy = nv50_clock_tidy;
-	return 0;
-}
-
-static struct nouveau_clocks
-nv50_domains[] = {
-	{ nv_clk_src_crystal, 0xff },
-	{ nv_clk_src_href   , 0xff },
-	{ nv_clk_src_core   , 0xff, 0, "core", 1000 },
-	{ nv_clk_src_shader , 0xff, 0, "shader", 1000 },
-	{ nv_clk_src_mem    , 0xff, 0, "memory", 1000 },
-	{ nv_clk_src_max }
-};
-
-struct nouveau_oclass *
-nv50_clock_oclass = &(struct nv50_clock_oclass) {
-	.base.handle = NV_SUBDEV(CLOCK, 0x50),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_clock_ctor,
-		.dtor = _nouveau_clock_dtor,
-		.init = _nouveau_clock_init,
-		.fini = _nouveau_clock_fini,
-	},
-	.domains = nv50_domains,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.h b/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.h
deleted file mode 100644
index f10917d789e8..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef __NVKM_CLK_NV50_H__
-#define __NVKM_CLK_NV50_H__
-
-#include <subdev/bus.h>
-#include <subdev/bus/hwsq.h>
-#include <subdev/clock.h>
-
-struct nv50_clock_hwsq {
-	struct hwsq base;
-	struct hwsq_reg r_fifo;
-	struct hwsq_reg r_spll[2];
-	struct hwsq_reg r_nvpll[2];
-	struct hwsq_reg r_divs;
-	struct hwsq_reg r_mast;
-};
-
-struct nv50_clock_priv {
-	struct nouveau_clock base;
-	struct nv50_clock_hwsq hwsq;
-};
-
-int  nv50_clock_ctor(struct nouveau_object *, struct nouveau_object *,
-		     struct nouveau_oclass *, void *, u32,
-		     struct nouveau_object **);
-
-struct nv50_clock_oclass {
-	struct nouveau_oclass base;
-	struct nouveau_clocks *domains;
-};
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv84.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv84.c
deleted file mode 100644
index b0b7c1437f10..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv84.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "nv50.h"
-
-static struct nouveau_clocks
-nv84_domains[] = {
-	{ nv_clk_src_crystal, 0xff },
-	{ nv_clk_src_href   , 0xff },
-	{ nv_clk_src_core   , 0xff, 0, "core", 1000 },
-	{ nv_clk_src_shader , 0xff, 0, "shader", 1000 },
-	{ nv_clk_src_mem    , 0xff, 0, "memory", 1000 },
-	{ nv_clk_src_vdec   , 0xff },
-	{ nv_clk_src_max }
-};
-
-struct nouveau_oclass *
-nv84_clock_oclass = &(struct nv50_clock_oclass) {
-	.base.handle = NV_SUBDEV(CLOCK, 0x84),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_clock_ctor,
-		.dtor = _nouveau_clock_dtor,
-		.init = _nouveau_clock_init,
-		.fini = _nouveau_clock_fini,
-	},
-	.domains = nv84_domains,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
deleted file mode 100644
index 07ad01247675..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
+++ /dev/null
@@ -1,534 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- *          Roy Spliet
- */
-
-#include <engine/fifo.h>
-#include <subdev/bios.h>
-#include <subdev/bios/pll.h>
-#include <subdev/timer.h>
-
-#include "pll.h"
-
-#include "nva3.h"
-
-struct nva3_clock_priv {
-	struct nouveau_clock base;
-	struct nva3_clock_info eng[nv_clk_src_max];
-};
-
-static u32 read_clk(struct nva3_clock_priv *, int, bool);
-static u32 read_pll(struct nva3_clock_priv *, int, u32);
-
-static u32
-read_vco(struct nva3_clock_priv *priv, int clk)
-{
-	u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4));
-
-	switch (sctl & 0x00000030) {
-	case 0x00000000:
-		return nv_device(priv)->crystal;
-	case 0x00000020:
-		return read_pll(priv, 0x41, 0x00e820);
-	case 0x00000030:
-		return read_pll(priv, 0x42, 0x00e8a0);
-	default:
-		return 0;
-	}
-}
-
-static u32
-read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en)
-{
-	u32 sctl, sdiv, sclk;
-
-	/* refclk for the 0xe8xx plls is a fixed frequency */
-	if (clk >= 0x40) {
-		if (nv_device(priv)->chipset == 0xaf) {
-			/* no joke.. seriously.. sigh.. */
-			return nv_rd32(priv, 0x00471c) * 1000;
-		}
-
-		return nv_device(priv)->crystal;
-	}
-
-	sctl = nv_rd32(priv, 0x4120 + (clk * 4));
-	if (!ignore_en && !(sctl & 0x00000100))
-		return 0;
-
-	/* out_alt */
-	if (sctl & 0x00000400)
-		return 108000;
-
-	/* vco_out */
-	switch (sctl & 0x00003000) {
-	case 0x00000000:
-		if (!(sctl & 0x00000200))
-			return nv_device(priv)->crystal;
-		return 0;
-	case 0x00002000:
-		if (sctl & 0x00000040)
-			return 108000;
-		return 100000;
-	case 0x00003000:
-		/* vco_enable */
-		if (!(sctl & 0x00000001))
-			return 0;
-
-		sclk = read_vco(priv, clk);
-		sdiv = ((sctl & 0x003f0000) >> 16) + 2;
-		return (sclk * 2) / sdiv;
-	default:
-		return 0;
-	}
-}
-
-static u32
-read_pll(struct nva3_clock_priv *priv, int clk, u32 pll)
-{
-	u32 ctrl = nv_rd32(priv, pll + 0);
-	u32 sclk = 0, P = 1, N = 1, M = 1;
-
-	if (!(ctrl & 0x00000008)) {
-		if (ctrl & 0x00000001) {
-			u32 coef = nv_rd32(priv, pll + 4);
-			M = (coef & 0x000000ff) >> 0;
-			N = (coef & 0x0000ff00) >> 8;
-			P = (coef & 0x003f0000) >> 16;
-
-			/* no post-divider on these..
-			 * XXX: it looks more like two post-"dividers" that
-			 * cross each other out in the default RPLL config */
-			if ((pll & 0x00ff00) == 0x00e800)
-				P = 1;
-
-			sclk = read_clk(priv, 0x00 + clk, false);
-		}
-	} else {
-		sclk = read_clk(priv, 0x10 + clk, false);
-	}
-
-	if (M * P)
-		return sclk * N / (M * P);
-	return 0;
-}
-
-static int
-nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
-{
-	struct nva3_clock_priv *priv = (void *)clk;
-	u32 hsrc;
-
-	switch (src) {
-	case nv_clk_src_crystal:
-		return nv_device(priv)->crystal;
-	case nv_clk_src_core:
-	case nv_clk_src_core_intm:
-		return read_pll(priv, 0x00, 0x4200);
-	case nv_clk_src_shader:
-		return read_pll(priv, 0x01, 0x4220);
-	case nv_clk_src_mem:
-		return read_pll(priv, 0x02, 0x4000);
-	case nv_clk_src_disp:
-		return read_clk(priv, 0x20, false);
-	case nv_clk_src_vdec:
-		return read_clk(priv, 0x21, false);
-	case nv_clk_src_daemon:
-		return read_clk(priv, 0x25, false);
-	case nv_clk_src_host:
-		hsrc = (nv_rd32(priv, 0xc040) & 0x30000000) >> 28;
-		switch (hsrc) {
-		case 0:
-			return read_clk(priv, 0x1d, false);
-		case 2:
-		case 3:
-			return 277000;
-		default:
-			nv_error(clk, "unknown HOST clock source %d\n", hsrc);
-			return -EINVAL;
-		}
-	default:
-		nv_error(clk, "invalid clock source %d\n", src);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-int
-nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz,
-		struct nva3_clock_info *info)
-{
-	struct nva3_clock_priv *priv = (void *)clock;
-	u32 oclk, sclk, sdiv, diff;
-
-	info->clk = 0;
-
-	switch (khz) {
-	case 27000:
-		info->clk = 0x00000100;
-		return khz;
-	case 100000:
-		info->clk = 0x00002100;
-		return khz;
-	case 108000:
-		info->clk = 0x00002140;
-		return khz;
-	default:
-		sclk = read_vco(priv, clk);
-		sdiv = min((sclk * 2) / khz, (u32)65);
-		oclk = (sclk * 2) / sdiv;
-		diff = ((khz + 3000) - oclk);
-
-		/* When imprecise, play it safe and aim for a clock lower than
-		 * desired rather than higher */
-		if (diff < 0) {
-			sdiv++;
-			oclk = (sclk * 2) / sdiv;
-		}
-
-		/* divider can go as low as 2, limited here because NVIDIA
-		 * and the VBIOS on my NVA8 seem to prefer using the PLL
-		 * for 810MHz - is there a good reason?
-		 * XXX: PLLs with refclk 810MHz?  */
-		if (sdiv > 4) {
-			info->clk = (((sdiv - 2) << 16) | 0x00003100);
-			return oclk;
-		}
-
-		break;
-	}
-
-	return -ERANGE;
-}
-
-int
-nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
-		struct nva3_clock_info *info)
-{
-	struct nouveau_bios *bios = nouveau_bios(clock);
-	struct nva3_clock_priv *priv = (void *)clock;
-	struct nvbios_pll limits;
-	int P, N, M, diff;
-	int ret;
-
-	info->pll = 0;
-
-	/* If we can get a within [-2, 3) MHz of a divider, we'll disable the
-	 * PLL and use the divider instead. */
-	ret = nva3_clk_info(clock, clk, khz, info);
-	diff = khz - ret;
-	if (!pll || (diff >= -2000 && diff < 3000)) {
-		goto out;
-	}
-
-	/* Try with PLL */
-	ret = nvbios_pll_parse(bios, pll, &limits);
-	if (ret)
-		return ret;
-
-	ret = nva3_clk_info(clock, clk - 0x10, limits.refclk, info);
-	if (ret != limits.refclk)
-		return -EINVAL;
-
-	ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P);
-	if (ret >= 0) {
-		info->pll = (P << 16) | (N << 8) | M;
-	}
-
-out:
-	info->fb_delay = max(((khz + 7566) / 15133), (u32) 18);
-
-	return ret ? ret : -ERANGE;
-}
-
-static int
-calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate,
-	 int clk, u32 pll, int idx)
-{
-	int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx],
-				  &priv->eng[idx]);
-	if (ret >= 0)
-		return 0;
-	return ret;
-}
-
-static int
-calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate)
-{
-	int ret = 0;
-	u32 kHz = cstate->domain[nv_clk_src_host];
-	struct nva3_clock_info *info = &priv->eng[nv_clk_src_host];
-
-	if (kHz == 277000) {
-		info->clk = 0;
-		info->host_out = NVA3_HOST_277;
-		return 0;
-	}
-
-	info->host_out = NVA3_HOST_CLK;
-
-	ret = nva3_clk_info(&priv->base, 0x1d, kHz, info);
-	if (ret >= 0)
-		return 0;
-	return ret;
-}
-
-int
-nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags)
-{
-	struct nouveau_fifo *pfifo = nouveau_fifo(clk);
-
-	/* halt and idle execution engines */
-	nv_mask(clk, 0x020060, 0x00070000, 0x00000000);
-	nv_mask(clk, 0x002504, 0x00000001, 0x00000001);
-	/* Wait until the interrupt handler is finished */
-	if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000))
-		return -EBUSY;
-
-	if (pfifo)
-		pfifo->pause(pfifo, flags);
-
-	if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010))
-		return -EIO;
-	if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f))
-		return -EIO;
-
-	return 0;
-}
-
-void
-nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags)
-{
-	struct nouveau_fifo *pfifo = nouveau_fifo(clk);
-
-	if (pfifo && flags)
-		pfifo->start(pfifo, flags);
-
-	nv_mask(clk, 0x002504, 0x00000001, 0x00000000);
-	nv_mask(clk, 0x020060, 0x00070000, 0x00040000);
-}
-
-static void
-disable_clk_src(struct nva3_clock_priv *priv, u32 src)
-{
-	nv_mask(priv, src, 0x00000100, 0x00000000);
-	nv_mask(priv, src, 0x00000001, 0x00000000);
-}
-
-static void
-prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
-{
-	struct nva3_clock_info *info = &priv->eng[idx];
-	const u32 src0 = 0x004120 + (clk * 4);
-	const u32 src1 = 0x004160 + (clk * 4);
-	const u32 ctrl = pll + 0;
-	const u32 coef = pll + 4;
-	u32 bypass;
-
-	if (info->pll) {
-		/* Always start from a non-PLL clock */
-		bypass = nv_rd32(priv, ctrl)  & 0x00000008;
-		if (!bypass) {
-			nv_mask(priv, src1, 0x00000101, 0x00000101);
-			nv_mask(priv, ctrl, 0x00000008, 0x00000008);
-			udelay(20);
-		}
-
-		nv_mask(priv, src0, 0x003f3141, 0x00000101 | info->clk);
-		nv_wr32(priv, coef, info->pll);
-		nv_mask(priv, ctrl, 0x00000015, 0x00000015);
-		nv_mask(priv, ctrl, 0x00000010, 0x00000000);
-		if (!nv_wait(priv, ctrl, 0x00020000, 0x00020000)) {
-			nv_mask(priv, ctrl, 0x00000010, 0x00000010);
-			nv_mask(priv, src0, 0x00000101, 0x00000000);
-			return;
-		}
-		nv_mask(priv, ctrl, 0x00000010, 0x00000010);
-		nv_mask(priv, ctrl, 0x00000008, 0x00000000);
-		disable_clk_src(priv, src1);
-	} else {
-		nv_mask(priv, src1, 0x003f3141, 0x00000101 | info->clk);
-		nv_mask(priv, ctrl, 0x00000018, 0x00000018);
-		udelay(20);
-		nv_mask(priv, ctrl, 0x00000001, 0x00000000);
-		disable_clk_src(priv, src0);
-	}
-}
-
-static void
-prog_clk(struct nva3_clock_priv *priv, int clk, int idx)
-{
-	struct nva3_clock_info *info = &priv->eng[idx];
-	nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk);
-}
-
-static void
-prog_host(struct nva3_clock_priv *priv)
-{
-	struct nva3_clock_info *info = &priv->eng[nv_clk_src_host];
-	u32 hsrc = (nv_rd32(priv, 0xc040));
-
-	switch (info->host_out) {
-	case NVA3_HOST_277:
-		if ((hsrc & 0x30000000) == 0) {
-			nv_wr32(priv, 0xc040, hsrc | 0x20000000);
-			disable_clk_src(priv, 0x4194);
-		}
-		break;
-	case NVA3_HOST_CLK:
-		prog_clk(priv, 0x1d, nv_clk_src_host);
-		if ((hsrc & 0x30000000) >= 0x20000000) {
-			nv_wr32(priv, 0xc040, hsrc & ~0x30000000);
-		}
-		break;
-	default:
-		break;
-	}
-
-	/* This seems to be a clock gating factor on idle, always set to 64 */
-	nv_wr32(priv, 0xc044, 0x3e);
-}
-
-static void
-prog_core(struct nva3_clock_priv *priv, int idx)
-{
-	struct nva3_clock_info *info = &priv->eng[idx];
-	u32 fb_delay = nv_rd32(priv, 0x10002c);
-
-	if (fb_delay < info->fb_delay)
-		nv_wr32(priv, 0x10002c, info->fb_delay);
-
-	prog_pll(priv, 0x00, 0x004200, idx);
-
-	if (fb_delay > info->fb_delay)
-		nv_wr32(priv, 0x10002c, info->fb_delay);
-}
-
-static int
-nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
-{
-	struct nva3_clock_priv *priv = (void *)clk;
-	struct nva3_clock_info *core = &priv->eng[nv_clk_src_core];
-	int ret;
-
-	if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) ||
-	    (ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) ||
-	    (ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) ||
-	    (ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)) ||
-	    (ret = calc_host(priv, cstate)))
-		return ret;
-
-	/* XXX: Should be reading the highest bit in the VBIOS clock to decide
-	 * whether to use a PLL or not... but using a PLL defeats the purpose */
-	if (core->pll) {
-		ret = nva3_clk_info(clk, 0x10,
-				cstate->domain[nv_clk_src_core_intm],
-				&priv->eng[nv_clk_src_core_intm]);
-		if (ret < 0)
-			return ret;
-	}
-
-	return 0;
-}
-
-static int
-nva3_clock_prog(struct nouveau_clock *clk)
-{
-	struct nva3_clock_priv *priv = (void *)clk;
-	struct nva3_clock_info *core = &priv->eng[nv_clk_src_core];
-	int ret = 0;
-	unsigned long flags;
-	unsigned long *f = &flags;
-
-	ret = nva3_clock_pre(clk, f);
-	if (ret)
-		goto out;
-
-	if (core->pll)
-		prog_core(priv, nv_clk_src_core_intm);
-
-	prog_core(priv,  nv_clk_src_core);
-	prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader);
-	prog_clk(priv, 0x20, nv_clk_src_disp);
-	prog_clk(priv, 0x21, nv_clk_src_vdec);
-	prog_host(priv);
-
-out:
-	if (ret == -EBUSY)
-		f = NULL;
-
-	nva3_clock_post(clk, f);
-
-	return ret;
-}
-
-static void
-nva3_clock_tidy(struct nouveau_clock *clk)
-{
-}
-
-static struct nouveau_clocks
-nva3_domain[] = {
-	{ nv_clk_src_crystal  , 0xff },
-	{ nv_clk_src_core     , 0x00, 0, "core", 1000 },
-	{ nv_clk_src_shader   , 0x01, 0, "shader", 1000 },
-	{ nv_clk_src_mem      , 0x02, 0, "memory", 1000 },
-	{ nv_clk_src_vdec     , 0x03 },
-	{ nv_clk_src_disp     , 0x04 },
-	{ nv_clk_src_host     , 0x05 },
-	{ nv_clk_src_core_intm, 0x06 },
-	{ nv_clk_src_max }
-};
-
-static int
-nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nva3_clock_priv *priv;
-	int ret;
-
-	ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, NULL, 0,
-				   true, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.read = nva3_clock_read;
-	priv->base.calc = nva3_clock_calc;
-	priv->base.prog = nva3_clock_prog;
-	priv->base.tidy = nva3_clock_tidy;
-	return 0;
-}
-
-struct nouveau_oclass
-nva3_clock_oclass = {
-	.handle = NV_SUBDEV(CLOCK, 0xa3),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nva3_clock_ctor,
-		.dtor = _nouveau_clock_dtor,
-		.init = _nouveau_clock_init,
-		.fini = _nouveau_clock_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h
deleted file mode 100644
index a45a1038b12f..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __NVKM_CLK_NVA3_H__
-#define __NVKM_CLK_NVA3_H__
-
-#include <subdev/clock.h>
-
-struct nva3_clock_info {
-	u32 clk;
-	u32 pll;
-	enum {
-		NVA3_HOST_277,
-		NVA3_HOST_CLK,
-	} host_out;
-	u32 fb_delay;
-};
-
-int nva3_pll_info(struct nouveau_clock *, int, u32, u32,
-		    struct nva3_clock_info *);
-int nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags);
-void nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags);
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c
deleted file mode 100644
index 54aeab8005a0..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c
+++ /dev/null
@@ -1,435 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <engine/fifo.h>
-#include <subdev/bios.h>
-#include <subdev/bios/pll.h>
-#include <subdev/timer.h>
-#include <subdev/clock.h>
-
-#include "nva3.h"
-#include "pll.h"
-
-struct nvaa_clock_priv {
-	struct nouveau_clock base;
-	enum nv_clk_src csrc, ssrc, vsrc;
-	u32 cctrl, sctrl;
-	u32 ccoef, scoef;
-	u32 cpost, spost;
-	u32 vdiv;
-};
-
-static u32
-read_div(struct nouveau_clock *clk)
-{
-	return nv_rd32(clk, 0x004600);
-}
-
-static u32
-read_pll(struct nouveau_clock *clk, u32 base)
-{
-	u32 ctrl = nv_rd32(clk, base + 0);
-	u32 coef = nv_rd32(clk, base + 4);
-	u32 ref = clk->read(clk, nv_clk_src_href);
-	u32 post_div = 0;
-	u32 clock = 0;
-	int N1, M1;
-
-	switch (base){
-	case 0x4020:
-		post_div = 1 << ((nv_rd32(clk, 0x4070) & 0x000f0000) >> 16);
-		break;
-	case 0x4028:
-		post_div = (nv_rd32(clk, 0x4040) & 0x000f0000) >> 16;
-		break;
-	default:
-		break;
-	}
-
-	N1 = (coef & 0x0000ff00) >> 8;
-	M1 = (coef & 0x000000ff);
-	if ((ctrl & 0x80000000) && M1) {
-		clock = ref * N1 / M1;
-		clock = clock / post_div;
-	}
-
-	return clock;
-}
-
-static int
-nvaa_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
-{
-	struct nvaa_clock_priv *priv = (void *)clk;
-	u32 mast = nv_rd32(clk, 0x00c054);
-	u32 P = 0;
-
-	switch (src) {
-	case nv_clk_src_crystal:
-		return nv_device(priv)->crystal;
-	case nv_clk_src_href:
-		return 100000; /* PCIE reference clock */
-	case nv_clk_src_hclkm4:
-		return clk->read(clk, nv_clk_src_href) * 4;
-	case nv_clk_src_hclkm2d3:
-		return clk->read(clk, nv_clk_src_href) * 2 / 3;
-	case nv_clk_src_host:
-		switch (mast & 0x000c0000) {
-		case 0x00000000: return clk->read(clk, nv_clk_src_hclkm2d3);
-		case 0x00040000: break;
-		case 0x00080000: return clk->read(clk, nv_clk_src_hclkm4);
-		case 0x000c0000: return clk->read(clk, nv_clk_src_cclk);
-		}
-		break;
-	case nv_clk_src_core:
-		P = (nv_rd32(clk, 0x004028) & 0x00070000) >> 16;
-
-		switch (mast & 0x00000003) {
-		case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P;
-		case 0x00000001: return 0;
-		case 0x00000002: return clk->read(clk, nv_clk_src_hclkm4) >> P;
-		case 0x00000003: return read_pll(clk, 0x004028) >> P;
-		}
-		break;
-	case nv_clk_src_cclk:
-		if ((mast & 0x03000000) != 0x03000000)
-			return clk->read(clk, nv_clk_src_core);
-
-		if ((mast & 0x00000200) == 0x00000000)
-			return clk->read(clk, nv_clk_src_core);
-
-		switch (mast & 0x00000c00) {
-		case 0x00000000: return clk->read(clk, nv_clk_src_href);
-		case 0x00000400: return clk->read(clk, nv_clk_src_hclkm4);
-		case 0x00000800: return clk->read(clk, nv_clk_src_hclkm2d3);
-		default: return 0;
-		}
-	case nv_clk_src_shader:
-		P = (nv_rd32(clk, 0x004020) & 0x00070000) >> 16;
-		switch (mast & 0x00000030) {
-		case 0x00000000:
-			if (mast & 0x00000040)
-				return clk->read(clk, nv_clk_src_href) >> P;
-			return clk->read(clk, nv_clk_src_crystal) >> P;
-		case 0x00000010: break;
-		case 0x00000020: return read_pll(clk, 0x004028) >> P;
-		case 0x00000030: return read_pll(clk, 0x004020) >> P;
-		}
-		break;
-	case nv_clk_src_mem:
-		return 0;
-		break;
-	case nv_clk_src_vdec:
-		P = (read_div(clk) & 0x00000700) >> 8;
-
-		switch (mast & 0x00400000) {
-		case 0x00400000:
-			return clk->read(clk, nv_clk_src_core) >> P;
-			break;
-		default:
-			return 500000 >> P;
-			break;
-		}
-		break;
-	default:
-		break;
-	}
-
-	nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast);
-	return 0;
-}
-
-static u32
-calc_pll(struct nvaa_clock_priv *priv, u32 reg,
-	 u32 clock, int *N, int *M, int *P)
-{
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	struct nvbios_pll pll;
-	struct nouveau_clock *clk = &priv->base;
-	int ret;
-
-	ret = nvbios_pll_parse(bios, reg, &pll);
-	if (ret)
-		return 0;
-
-	pll.vco2.max_freq = 0;
-	pll.refclk = clk->read(clk, nv_clk_src_href);
-	if (!pll.refclk)
-		return 0;
-
-	return nv04_pll_calc(nv_subdev(priv), &pll, clock, N, M, NULL, NULL, P);
-}
-
-static inline u32
-calc_P(u32 src, u32 target, int *div)
-{
-	u32 clk0 = src, clk1 = src;
-	for (*div = 0; *div <= 7; (*div)++) {
-		if (clk0 <= target) {
-			clk1 = clk0 << (*div ? 1 : 0);
-			break;
-		}
-		clk0 >>= 1;
-	}
-
-	if (target - clk0 <= clk1 - target)
-		return clk0;
-	(*div)--;
-	return clk1;
-}
-
-static int
-nvaa_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
-{
-	struct nvaa_clock_priv *priv = (void *)clk;
-	const int shader = cstate->domain[nv_clk_src_shader];
-	const int core = cstate->domain[nv_clk_src_core];
-	const int vdec = cstate->domain[nv_clk_src_vdec];
-	u32 out = 0, clock = 0;
-	int N, M, P1, P2 = 0;
-	int divs = 0;
-
-	/* cclk: find suitable source, disable PLL if we can */
-	if (core < clk->read(clk, nv_clk_src_hclkm4))
-		out = calc_P(clk->read(clk, nv_clk_src_hclkm4), core, &divs);
-
-	/* Calculate clock * 2, so shader clock can use it too */
-	clock = calc_pll(priv, 0x4028, (core << 1), &N, &M, &P1);
-
-	if (abs(core - out) <=
-	    abs(core - (clock >> 1))) {
-		priv->csrc = nv_clk_src_hclkm4;
-		priv->cctrl = divs << 16;
-	} else {
-		/* NVCTRL is actually used _after_ NVPOST, and after what we
-		 * call NVPLL. To make matters worse, NVPOST is an integer
-		 * divider instead of a right-shift number. */
-		if(P1 > 2) {
-			P2 = P1 - 2;
-			P1 = 2;
-		}
-
-		priv->csrc = nv_clk_src_core;
-		priv->ccoef = (N << 8) | M;
-
-		priv->cctrl = (P2 + 1) << 16;
-		priv->cpost = (1 << P1) << 16;
-	}
-
-	/* sclk: nvpll + divisor, href or spll */
-	out = 0;
-	if (shader == clk->read(clk, nv_clk_src_href)) {
-		priv->ssrc = nv_clk_src_href;
-	} else {
-		clock = calc_pll(priv, 0x4020, shader, &N, &M, &P1);
-		if (priv->csrc == nv_clk_src_core) {
-			out = calc_P((core << 1), shader, &divs);
-		}
-
-		if (abs(shader - out) <=
-		    abs(shader - clock) &&
-		   (divs + P2) <= 7) {
-			priv->ssrc = nv_clk_src_core;
-			priv->sctrl = (divs + P2) << 16;
-		} else {
-			priv->ssrc = nv_clk_src_shader;
-			priv->scoef = (N << 8) | M;
-			priv->sctrl = P1 << 16;
-		}
-	}
-
-	/* vclk */
-	out = calc_P(core, vdec, &divs);
-	clock = calc_P(500000, vdec, &P1);
-	if(abs(vdec - out) <=
-	   abs(vdec - clock)) {
-		priv->vsrc = nv_clk_src_cclk;
-		priv->vdiv = divs << 16;
-	} else {
-		priv->vsrc = nv_clk_src_vdec;
-		priv->vdiv = P1 << 16;
-	}
-
-	/* Print strategy! */
-	nv_debug(priv, "nvpll: %08x %08x %08x\n",
-			priv->ccoef, priv->cpost, priv->cctrl);
-	nv_debug(priv, " spll: %08x %08x %08x\n",
-			priv->scoef, priv->spost, priv->sctrl);
-	nv_debug(priv, " vdiv: %08x\n", priv->vdiv);
-	if (priv->csrc == nv_clk_src_hclkm4)
-		nv_debug(priv, "core: hrefm4\n");
-	else
-		nv_debug(priv, "core: nvpll\n");
-
-	if (priv->ssrc == nv_clk_src_hclkm4)
-		nv_debug(priv, "shader: hrefm4\n");
-	else if (priv->ssrc == nv_clk_src_core)
-		nv_debug(priv, "shader: nvpll\n");
-	else
-		nv_debug(priv, "shader: spll\n");
-
-	if (priv->vsrc == nv_clk_src_hclkm4)
-		nv_debug(priv, "vdec: 500MHz\n");
-	else
-		nv_debug(priv, "vdec: core\n");
-
-	return 0;
-}
-
-static int
-nvaa_clock_prog(struct nouveau_clock *clk)
-{
-	struct nvaa_clock_priv *priv = (void *)clk;
-	u32 pllmask = 0, mast;
-	unsigned long flags;
-	unsigned long *f = &flags;
-	int ret = 0;
-
-	ret = nva3_clock_pre(clk, f);
-	if (ret)
-		goto out;
-
-	/* First switch to safe clocks: href */
-	mast = nv_mask(clk, 0xc054, 0x03400e70, 0x03400640);
-	mast &= ~0x00400e73;
-	mast |= 0x03000000;
-
-	switch (priv->csrc) {
-	case nv_clk_src_hclkm4:
-		nv_mask(clk, 0x4028, 0x00070000, priv->cctrl);
-		mast |= 0x00000002;
-		break;
-	case nv_clk_src_core:
-		nv_wr32(clk, 0x402c, priv->ccoef);
-		nv_wr32(clk, 0x4028, 0x80000000 | priv->cctrl);
-		nv_wr32(clk, 0x4040, priv->cpost);
-		pllmask |= (0x3 << 8);
-		mast |= 0x00000003;
-		break;
-	default:
-		nv_warn(priv,"Reclocking failed: unknown core clock\n");
-		goto resume;
-	}
-
-	switch (priv->ssrc) {
-	case nv_clk_src_href:
-		nv_mask(clk, 0x4020, 0x00070000, 0x00000000);
-		/* mast |= 0x00000000; */
-		break;
-	case nv_clk_src_core:
-		nv_mask(clk, 0x4020, 0x00070000, priv->sctrl);
-		mast |= 0x00000020;
-		break;
-	case nv_clk_src_shader:
-		nv_wr32(clk, 0x4024, priv->scoef);
-		nv_wr32(clk, 0x4020, 0x80000000 | priv->sctrl);
-		nv_wr32(clk, 0x4070, priv->spost);
-		pllmask |= (0x3 << 12);
-		mast |= 0x00000030;
-		break;
-	default:
-		nv_warn(priv,"Reclocking failed: unknown sclk clock\n");
-		goto resume;
-	}
-
-	if (!nv_wait(clk, 0x004080, pllmask, pllmask)) {
-		nv_warn(priv,"Reclocking failed: unstable PLLs\n");
-		goto resume;
-	}
-
-	switch (priv->vsrc) {
-	case nv_clk_src_cclk:
-		mast |= 0x00400000;
-	default:
-		nv_wr32(clk, 0x4600, priv->vdiv);
-	}
-
-	nv_wr32(clk, 0xc054, mast);
-
-resume:
-	/* Disable some PLLs and dividers when unused */
-	if (priv->csrc != nv_clk_src_core) {
-		nv_wr32(clk, 0x4040, 0x00000000);
-		nv_mask(clk, 0x4028, 0x80000000, 0x00000000);
-	}
-
-	if (priv->ssrc != nv_clk_src_shader) {
-		nv_wr32(clk, 0x4070, 0x00000000);
-		nv_mask(clk, 0x4020, 0x80000000, 0x00000000);
-	}
-
-out:
-	if (ret == -EBUSY)
-		f = NULL;
-
-	nva3_clock_post(clk, f);
-
-	return ret;
-}
-
-static void
-nvaa_clock_tidy(struct nouveau_clock *clk)
-{
-}
-
-static struct nouveau_clocks
-nvaa_domains[] = {
-	{ nv_clk_src_crystal, 0xff },
-	{ nv_clk_src_href   , 0xff },
-	{ nv_clk_src_core   , 0xff, 0, "core", 1000 },
-	{ nv_clk_src_shader , 0xff, 0, "shader", 1000 },
-	{ nv_clk_src_vdec   , 0xff, 0, "vdec", 1000 },
-	{ nv_clk_src_max }
-};
-
-static int
-nvaa_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nvaa_clock_priv *priv;
-	int ret;
-
-	ret = nouveau_clock_create(parent, engine, oclass, nvaa_domains, NULL,
-				   0, true, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.read = nvaa_clock_read;
-	priv->base.calc = nvaa_clock_calc;
-	priv->base.prog = nvaa_clock_prog;
-	priv->base.tidy = nvaa_clock_tidy;
-	return 0;
-}
-
-struct nouveau_oclass *
-nvaa_clock_oclass = &(struct nouveau_oclass) {
-	.handle = NV_SUBDEV(CLOCK, 0xaa),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvaa_clock_ctor,
-		.dtor = _nouveau_clock_dtor,
-		.init = _nouveau_clock_init,
-		.fini = _nouveau_clock_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
deleted file mode 100644
index 1234abaab2db..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
+++ /dev/null
@@ -1,462 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/clock.h>
-#include <subdev/bios.h>
-#include <subdev/bios/pll.h>
-#include <subdev/timer.h>
-
-#include "pll.h"
-
-struct nvc0_clock_info {
-	u32 freq;
-	u32 ssel;
-	u32 mdiv;
-	u32 dsrc;
-	u32 ddiv;
-	u32 coef;
-};
-
-struct nvc0_clock_priv {
-	struct nouveau_clock base;
-	struct nvc0_clock_info eng[16];
-};
-
-static u32 read_div(struct nvc0_clock_priv *, int, u32, u32);
-
-static u32
-read_vco(struct nvc0_clock_priv *priv, u32 dsrc)
-{
-	struct nouveau_clock *clk = &priv->base;
-	u32 ssrc = nv_rd32(priv, dsrc);
-	if (!(ssrc & 0x00000100))
-		return clk->read(clk, nv_clk_src_sppll0);
-	return clk->read(clk, nv_clk_src_sppll1);
-}
-
-static u32
-read_pll(struct nvc0_clock_priv *priv, u32 pll)
-{
-	struct nouveau_clock *clk = &priv->base;
-	u32 ctrl = nv_rd32(priv, pll + 0x00);
-	u32 coef = nv_rd32(priv, pll + 0x04);
-	u32 P = (coef & 0x003f0000) >> 16;
-	u32 N = (coef & 0x0000ff00) >> 8;
-	u32 M = (coef & 0x000000ff) >> 0;
-	u32 sclk;
-
-	if (!(ctrl & 0x00000001))
-		return 0;
-
-	switch (pll) {
-	case 0x00e800:
-	case 0x00e820:
-		sclk = nv_device(priv)->crystal;
-		P = 1;
-		break;
-	case 0x132000:
-		sclk = clk->read(clk, nv_clk_src_mpllsrc);
-		break;
-	case 0x132020:
-		sclk = clk->read(clk, nv_clk_src_mpllsrcref);
-		break;
-	case 0x137000:
-	case 0x137020:
-	case 0x137040:
-	case 0x1370e0:
-		sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140);
-		break;
-	default:
-		return 0;
-	}
-
-	return sclk * N / M / P;
-}
-
-static u32
-read_div(struct nvc0_clock_priv *priv, int doff, u32 dsrc, u32 dctl)
-{
-	u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
-	u32 sctl = nv_rd32(priv, dctl + (doff * 4));
-
-	switch (ssrc & 0x00000003) {
-	case 0:
-		if ((ssrc & 0x00030000) != 0x00030000)
-			return nv_device(priv)->crystal;
-		return 108000;
-	case 2:
-		return 100000;
-	case 3:
-		if (sctl & 0x80000000) {
-			u32 sclk = read_vco(priv, dsrc + (doff * 4));
-			u32 sdiv = (sctl & 0x0000003f) + 2;
-			return (sclk * 2) / sdiv;
-		}
-
-		return read_vco(priv, dsrc + (doff * 4));
-	default:
-		return 0;
-	}
-}
-
-static u32
-read_clk(struct nvc0_clock_priv *priv, int clk)
-{
-	u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
-	u32 ssel = nv_rd32(priv, 0x137100);
-	u32 sclk, sdiv;
-
-	if (ssel & (1 << clk)) {
-		if (clk < 7)
-			sclk = read_pll(priv, 0x137000 + (clk * 0x20));
-		else
-			sclk = read_pll(priv, 0x1370e0);
-		sdiv = ((sctl & 0x00003f00) >> 8) + 2;
-	} else {
-		sclk = read_div(priv, clk, 0x137160, 0x1371d0);
-		sdiv = ((sctl & 0x0000003f) >> 0) + 2;
-	}
-
-	if (sctl & 0x80000000)
-		return (sclk * 2) / sdiv;
-
-	return sclk;
-}
-
-static int
-nvc0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
-{
-	struct nouveau_device *device = nv_device(clk);
-	struct nvc0_clock_priv *priv = (void *)clk;
-
-	switch (src) {
-	case nv_clk_src_crystal:
-		return device->crystal;
-	case nv_clk_src_href:
-		return 100000;
-	case nv_clk_src_sppll0:
-		return read_pll(priv, 0x00e800);
-	case nv_clk_src_sppll1:
-		return read_pll(priv, 0x00e820);
-
-	case nv_clk_src_mpllsrcref:
-		return read_div(priv, 0, 0x137320, 0x137330);
-	case nv_clk_src_mpllsrc:
-		return read_pll(priv, 0x132020);
-	case nv_clk_src_mpll:
-		return read_pll(priv, 0x132000);
-	case nv_clk_src_mdiv:
-		return read_div(priv, 0, 0x137300, 0x137310);
-	case nv_clk_src_mem:
-		if (nv_rd32(priv, 0x1373f0) & 0x00000002)
-			return clk->read(clk, nv_clk_src_mpll);
-		return clk->read(clk, nv_clk_src_mdiv);
-
-	case nv_clk_src_gpc:
-		return read_clk(priv, 0x00);
-	case nv_clk_src_rop:
-		return read_clk(priv, 0x01);
-	case nv_clk_src_hubk07:
-		return read_clk(priv, 0x02);
-	case nv_clk_src_hubk06:
-		return read_clk(priv, 0x07);
-	case nv_clk_src_hubk01:
-		return read_clk(priv, 0x08);
-	case nv_clk_src_copy:
-		return read_clk(priv, 0x09);
-	case nv_clk_src_daemon:
-		return read_clk(priv, 0x0c);
-	case nv_clk_src_vdec:
-		return read_clk(priv, 0x0e);
-	default:
-		nv_error(clk, "invalid clock source %d\n", src);
-		return -EINVAL;
-	}
-}
-
-static u32
-calc_div(struct nvc0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
-{
-	u32 div = min((ref * 2) / freq, (u32)65);
-	if (div < 2)
-		div = 2;
-
-	*ddiv = div - 2;
-	return (ref * 2) / div;
-}
-
-static u32
-calc_src(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
-{
-	u32 sclk;
-
-	/* use one of the fixed frequencies if possible */
-	*ddiv = 0x00000000;
-	switch (freq) {
-	case  27000:
-	case 108000:
-		*dsrc = 0x00000000;
-		if (freq == 108000)
-			*dsrc |= 0x00030000;
-		return freq;
-	case 100000:
-		*dsrc = 0x00000002;
-		return freq;
-	default:
-		*dsrc = 0x00000003;
-		break;
-	}
-
-	/* otherwise, calculate the closest divider */
-	sclk = read_vco(priv, 0x137160 + (clk * 4));
-	if (clk < 7)
-		sclk = calc_div(priv, clk, sclk, freq, ddiv);
-	return sclk;
-}
-
-static u32
-calc_pll(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *coef)
-{
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	struct nvbios_pll limits;
-	int N, M, P, ret;
-
-	ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits);
-	if (ret)
-		return 0;
-
-	limits.refclk = read_div(priv, clk, 0x137120, 0x137140);
-	if (!limits.refclk)
-		return 0;
-
-	ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P);
-	if (ret <= 0)
-		return 0;
-
-	*coef = (P << 16) | (N << 8) | M;
-	return ret;
-}
-
-static int
-calc_clk(struct nvc0_clock_priv *priv,
-	 struct nouveau_cstate *cstate, int clk, int dom)
-{
-	struct nvc0_clock_info *info = &priv->eng[clk];
-	u32 freq = cstate->domain[dom];
-	u32 src0, div0, div1D, div1P = 0;
-	u32 clk0, clk1 = 0;
-
-	/* invalid clock domain */
-	if (!freq)
-		return 0;
-
-	/* first possible path, using only dividers */
-	clk0 = calc_src(priv, clk, freq, &src0, &div0);
-	clk0 = calc_div(priv, clk, clk0, freq, &div1D);
-
-	/* see if we can get any closer using PLLs */
-	if (clk0 != freq && (0x00004387 & (1 << clk))) {
-		if (clk <= 7)
-			clk1 = calc_pll(priv, clk, freq, &info->coef);
-		else
-			clk1 = cstate->domain[nv_clk_src_hubk06];
-		clk1 = calc_div(priv, clk, clk1, freq, &div1P);
-	}
-
-	/* select the method which gets closest to target freq */
-	if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
-		info->dsrc = src0;
-		if (div0) {
-			info->ddiv |= 0x80000000;
-			info->ddiv |= div0 << 8;
-			info->ddiv |= div0;
-		}
-		if (div1D) {
-			info->mdiv |= 0x80000000;
-			info->mdiv |= div1D;
-		}
-		info->ssel = info->coef = 0;
-		info->freq = clk0;
-	} else {
-		if (div1P) {
-			info->mdiv |= 0x80000000;
-			info->mdiv |= div1P << 8;
-		}
-		info->ssel = (1 << clk);
-		info->freq = clk1;
-	}
-
-	return 0;
-}
-
-static int
-nvc0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
-{
-	struct nvc0_clock_priv *priv = (void *)clk;
-	int ret;
-
-	if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
-	    (ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) ||
-	    (ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) ||
-	    (ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) ||
-	    (ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) ||
-	    (ret = calc_clk(priv, cstate, 0x09, nv_clk_src_copy)) ||
-	    (ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) ||
-	    (ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec)))
-		return ret;
-
-	return 0;
-}
-
-static void
-nvc0_clock_prog_0(struct nvc0_clock_priv *priv, int clk)
-{
-	struct nvc0_clock_info *info = &priv->eng[clk];
-	if (clk < 7 && !info->ssel) {
-		nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
-		nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
-	}
-}
-
-static void
-nvc0_clock_prog_1(struct nvc0_clock_priv *priv, int clk)
-{
-	nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
-	nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
-}
-
-static void
-nvc0_clock_prog_2(struct nvc0_clock_priv *priv, int clk)
-{
-	struct nvc0_clock_info *info = &priv->eng[clk];
-	const u32 addr = 0x137000 + (clk * 0x20);
-	if (clk <= 7) {
-		nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
-		nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000);
-		if (info->coef) {
-			nv_wr32(priv, addr + 0x04, info->coef);
-			nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001);
-			nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000);
-			nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004);
-		}
-	}
-}
-
-static void
-nvc0_clock_prog_3(struct nvc0_clock_priv *priv, int clk)
-{
-	struct nvc0_clock_info *info = &priv->eng[clk];
-	if (info->ssel) {
-		nv_mask(priv, 0x137100, (1 << clk), info->ssel);
-		nv_wait(priv, 0x137100, (1 << clk), info->ssel);
-	}
-}
-
-static void
-nvc0_clock_prog_4(struct nvc0_clock_priv *priv, int clk)
-{
-	struct nvc0_clock_info *info = &priv->eng[clk];
-	nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
-}
-
-static int
-nvc0_clock_prog(struct nouveau_clock *clk)
-{
-	struct nvc0_clock_priv *priv = (void *)clk;
-	struct {
-		void (*exec)(struct nvc0_clock_priv *, int);
-	} stage[] = {
-		{ nvc0_clock_prog_0 }, /* div programming */
-		{ nvc0_clock_prog_1 }, /* select div mode */
-		{ nvc0_clock_prog_2 }, /* (maybe) program pll */
-		{ nvc0_clock_prog_3 }, /* (maybe) select pll mode */
-		{ nvc0_clock_prog_4 }, /* final divider */
-	};
-	int i, j;
-
-	for (i = 0; i < ARRAY_SIZE(stage); i++) {
-		for (j = 0; j < ARRAY_SIZE(priv->eng); j++) {
-			if (!priv->eng[j].freq)
-				continue;
-			stage[i].exec(priv, j);
-		}
-	}
-
-	return 0;
-}
-
-static void
-nvc0_clock_tidy(struct nouveau_clock *clk)
-{
-	struct nvc0_clock_priv *priv = (void *)clk;
-	memset(priv->eng, 0x00, sizeof(priv->eng));
-}
-
-static struct nouveau_clocks
-nvc0_domain[] = {
-	{ nv_clk_src_crystal, 0xff },
-	{ nv_clk_src_href   , 0xff },
-	{ nv_clk_src_hubk06 , 0x00 },
-	{ nv_clk_src_hubk01 , 0x01 },
-	{ nv_clk_src_copy   , 0x02 },
-	{ nv_clk_src_gpc    , 0x03, 0, "core", 2000 },
-	{ nv_clk_src_rop    , 0x04 },
-	{ nv_clk_src_mem    , 0x05, 0, "memory", 1000 },
-	{ nv_clk_src_vdec   , 0x06 },
-	{ nv_clk_src_daemon , 0x0a },
-	{ nv_clk_src_hubk07 , 0x0b },
-	{ nv_clk_src_max }
-};
-
-static int
-nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nvc0_clock_priv *priv;
-	int ret;
-
-	ret = nouveau_clock_create(parent, engine, oclass, nvc0_domain, NULL, 0,
-				   false, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.read = nvc0_clock_read;
-	priv->base.calc = nvc0_clock_calc;
-	priv->base.prog = nvc0_clock_prog;
-	priv->base.tidy = nvc0_clock_tidy;
-	return 0;
-}
-
-struct nouveau_oclass
-nvc0_clock_oclass = {
-	.handle = NV_SUBDEV(CLOCK, 0xc0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_clock_ctor,
-		.dtor = _nouveau_clock_dtor,
-		.init = _nouveau_clock_init,
-		.fini = _nouveau_clock_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c
deleted file mode 100644
index 7eccad57512e..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c
+++ /dev/null
@@ -1,500 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/clock.h>
-#include <subdev/timer.h>
-#include <subdev/bios.h>
-#include <subdev/bios/pll.h>
-
-#include "pll.h"
-
-struct nve0_clock_info {
-	u32 freq;
-	u32 ssel;
-	u32 mdiv;
-	u32 dsrc;
-	u32 ddiv;
-	u32 coef;
-};
-
-struct nve0_clock_priv {
-	struct nouveau_clock base;
-	struct nve0_clock_info eng[16];
-};
-
-static u32 read_div(struct nve0_clock_priv *, int, u32, u32);
-static u32 read_pll(struct nve0_clock_priv *, u32);
-
-static u32
-read_vco(struct nve0_clock_priv *priv, u32 dsrc)
-{
-	u32 ssrc = nv_rd32(priv, dsrc);
-	if (!(ssrc & 0x00000100))
-		return read_pll(priv, 0x00e800);
-	return read_pll(priv, 0x00e820);
-}
-
-static u32
-read_pll(struct nve0_clock_priv *priv, u32 pll)
-{
-	u32 ctrl = nv_rd32(priv, pll + 0x00);
-	u32 coef = nv_rd32(priv, pll + 0x04);
-	u32 P = (coef & 0x003f0000) >> 16;
-	u32 N = (coef & 0x0000ff00) >> 8;
-	u32 M = (coef & 0x000000ff) >> 0;
-	u32 sclk;
-	u16 fN = 0xf000;
-
-	if (!(ctrl & 0x00000001))
-		return 0;
-
-	switch (pll) {
-	case 0x00e800:
-	case 0x00e820:
-		sclk = nv_device(priv)->crystal;
-		P = 1;
-		break;
-	case 0x132000:
-		sclk = read_pll(priv, 0x132020);
-		P = (coef & 0x10000000) ? 2 : 1;
-		break;
-	case 0x132020:
-		sclk = read_div(priv, 0, 0x137320, 0x137330);
-		fN   = nv_rd32(priv, pll + 0x10) >> 16;
-		break;
-	case 0x137000:
-	case 0x137020:
-	case 0x137040:
-	case 0x1370e0:
-		sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140);
-		break;
-	default:
-		return 0;
-	}
-
-	if (P == 0)
-		P = 1;
-
-	sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13);
-	return sclk / (M * P);
-}
-
-static u32
-read_div(struct nve0_clock_priv *priv, int doff, u32 dsrc, u32 dctl)
-{
-	u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
-	u32 sctl = nv_rd32(priv, dctl + (doff * 4));
-
-	switch (ssrc & 0x00000003) {
-	case 0:
-		if ((ssrc & 0x00030000) != 0x00030000)
-			return nv_device(priv)->crystal;
-		return 108000;
-	case 2:
-		return 100000;
-	case 3:
-		if (sctl & 0x80000000) {
-			u32 sclk = read_vco(priv, dsrc + (doff * 4));
-			u32 sdiv = (sctl & 0x0000003f) + 2;
-			return (sclk * 2) / sdiv;
-		}
-
-		return read_vco(priv, dsrc + (doff * 4));
-	default:
-		return 0;
-	}
-}
-
-static u32
-read_mem(struct nve0_clock_priv *priv)
-{
-	switch (nv_rd32(priv, 0x1373f4) & 0x0000000f) {
-	case 1: return read_pll(priv, 0x132020);
-	case 2: return read_pll(priv, 0x132000);
-	default:
-		return 0;
-	}
-}
-
-static u32
-read_clk(struct nve0_clock_priv *priv, int clk)
-{
-	u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
-	u32 sclk, sdiv;
-
-	if (clk < 7) {
-		u32 ssel = nv_rd32(priv, 0x137100);
-		if (ssel & (1 << clk)) {
-			sclk = read_pll(priv, 0x137000 + (clk * 0x20));
-			sdiv = 1;
-		} else {
-			sclk = read_div(priv, clk, 0x137160, 0x1371d0);
-			sdiv = 0;
-		}
-	} else {
-		u32 ssrc = nv_rd32(priv, 0x137160 + (clk * 0x04));
-		if ((ssrc & 0x00000003) == 0x00000003) {
-			sclk = read_div(priv, clk, 0x137160, 0x1371d0);
-			if (ssrc & 0x00000100) {
-				if (ssrc & 0x40000000)
-					sclk = read_pll(priv, 0x1370e0);
-				sdiv = 1;
-			} else {
-				sdiv = 0;
-			}
-		} else {
-			sclk = read_div(priv, clk, 0x137160, 0x1371d0);
-			sdiv = 0;
-		}
-	}
-
-	if (sctl & 0x80000000) {
-		if (sdiv)
-			sdiv = ((sctl & 0x00003f00) >> 8) + 2;
-		else
-			sdiv = ((sctl & 0x0000003f) >> 0) + 2;
-		return (sclk * 2) / sdiv;
-	}
-
-	return sclk;
-}
-
-static int
-nve0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
-{
-	struct nouveau_device *device = nv_device(clk);
-	struct nve0_clock_priv *priv = (void *)clk;
-
-	switch (src) {
-	case nv_clk_src_crystal:
-		return device->crystal;
-	case nv_clk_src_href:
-		return 100000;
-	case nv_clk_src_mem:
-		return read_mem(priv);
-	case nv_clk_src_gpc:
-		return read_clk(priv, 0x00);
-	case nv_clk_src_rop:
-		return read_clk(priv, 0x01);
-	case nv_clk_src_hubk07:
-		return read_clk(priv, 0x02);
-	case nv_clk_src_hubk06:
-		return read_clk(priv, 0x07);
-	case nv_clk_src_hubk01:
-		return read_clk(priv, 0x08);
-	case nv_clk_src_daemon:
-		return read_clk(priv, 0x0c);
-	case nv_clk_src_vdec:
-		return read_clk(priv, 0x0e);
-	default:
-		nv_error(clk, "invalid clock source %d\n", src);
-		return -EINVAL;
-	}
-}
-
-static u32
-calc_div(struct nve0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
-{
-	u32 div = min((ref * 2) / freq, (u32)65);
-	if (div < 2)
-		div = 2;
-
-	*ddiv = div - 2;
-	return (ref * 2) / div;
-}
-
-static u32
-calc_src(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
-{
-	u32 sclk;
-
-	/* use one of the fixed frequencies if possible */
-	*ddiv = 0x00000000;
-	switch (freq) {
-	case  27000:
-	case 108000:
-		*dsrc = 0x00000000;
-		if (freq == 108000)
-			*dsrc |= 0x00030000;
-		return freq;
-	case 100000:
-		*dsrc = 0x00000002;
-		return freq;
-	default:
-		*dsrc = 0x00000003;
-		break;
-	}
-
-	/* otherwise, calculate the closest divider */
-	sclk = read_vco(priv, 0x137160 + (clk * 4));
-	if (clk < 7)
-		sclk = calc_div(priv, clk, sclk, freq, ddiv);
-	return sclk;
-}
-
-static u32
-calc_pll(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *coef)
-{
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	struct nvbios_pll limits;
-	int N, M, P, ret;
-
-	ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits);
-	if (ret)
-		return 0;
-
-	limits.refclk = read_div(priv, clk, 0x137120, 0x137140);
-	if (!limits.refclk)
-		return 0;
-
-	ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P);
-	if (ret <= 0)
-		return 0;
-
-	*coef = (P << 16) | (N << 8) | M;
-	return ret;
-}
-
-static int
-calc_clk(struct nve0_clock_priv *priv,
-	 struct nouveau_cstate *cstate, int clk, int dom)
-{
-	struct nve0_clock_info *info = &priv->eng[clk];
-	u32 freq = cstate->domain[dom];
-	u32 src0, div0, div1D, div1P = 0;
-	u32 clk0, clk1 = 0;
-
-	/* invalid clock domain */
-	if (!freq)
-		return 0;
-
-	/* first possible path, using only dividers */
-	clk0 = calc_src(priv, clk, freq, &src0, &div0);
-	clk0 = calc_div(priv, clk, clk0, freq, &div1D);
-
-	/* see if we can get any closer using PLLs */
-	if (clk0 != freq && (0x0000ff87 & (1 << clk))) {
-		if (clk <= 7)
-			clk1 = calc_pll(priv, clk, freq, &info->coef);
-		else
-			clk1 = cstate->domain[nv_clk_src_hubk06];
-		clk1 = calc_div(priv, clk, clk1, freq, &div1P);
-	}
-
-	/* select the method which gets closest to target freq */
-	if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
-		info->dsrc = src0;
-		if (div0) {
-			info->ddiv |= 0x80000000;
-			info->ddiv |= div0;
-		}
-		if (div1D) {
-			info->mdiv |= 0x80000000;
-			info->mdiv |= div1D;
-		}
-		info->ssel = 0;
-		info->freq = clk0;
-	} else {
-		if (div1P) {
-			info->mdiv |= 0x80000000;
-			info->mdiv |= div1P << 8;
-		}
-		info->ssel = (1 << clk);
-		info->dsrc = 0x40000100;
-		info->freq = clk1;
-	}
-
-	return 0;
-}
-
-static int
-nve0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
-{
-	struct nve0_clock_priv *priv = (void *)clk;
-	int ret;
-
-	if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
-	    (ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) ||
-	    (ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) ||
-	    (ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) ||
-	    (ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) ||
-	    (ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) ||
-	    (ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec)))
-		return ret;
-
-	return 0;
-}
-
-static void
-nve0_clock_prog_0(struct nve0_clock_priv *priv, int clk)
-{
-	struct nve0_clock_info *info = &priv->eng[clk];
-	if (!info->ssel) {
-		nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x8000003f, info->ddiv);
-		nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
-	}
-}
-
-static void
-nve0_clock_prog_1_0(struct nve0_clock_priv *priv, int clk)
-{
-	nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
-	nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
-}
-
-static void
-nve0_clock_prog_1_1(struct nve0_clock_priv *priv, int clk)
-{
-	nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000000);
-}
-
-static void
-nve0_clock_prog_2(struct nve0_clock_priv *priv, int clk)
-{
-	struct nve0_clock_info *info = &priv->eng[clk];
-	const u32 addr = 0x137000 + (clk * 0x20);
-	nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
-	nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000);
-	if (info->coef) {
-		nv_wr32(priv, addr + 0x04, info->coef);
-		nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001);
-		nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000);
-		nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004);
-	}
-}
-
-static void
-nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk)
-{
-	struct nve0_clock_info *info = &priv->eng[clk];
-	if (info->ssel)
-		nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f00, info->mdiv);
-	else
-		nv_mask(priv, 0x137250 + (clk * 0x04), 0x0000003f, info->mdiv);
-}
-
-static void
-nve0_clock_prog_4_0(struct nve0_clock_priv *priv, int clk)
-{
-	struct nve0_clock_info *info = &priv->eng[clk];
-	if (info->ssel) {
-		nv_mask(priv, 0x137100, (1 << clk), info->ssel);
-		nv_wait(priv, 0x137100, (1 << clk), info->ssel);
-	}
-}
-
-static void
-nve0_clock_prog_4_1(struct nve0_clock_priv *priv, int clk)
-{
-	struct nve0_clock_info *info = &priv->eng[clk];
-	if (info->ssel) {
-		nv_mask(priv, 0x137160 + (clk * 0x04), 0x40000000, 0x40000000);
-		nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000100);
-	}
-}
-
-static int
-nve0_clock_prog(struct nouveau_clock *clk)
-{
-	struct nve0_clock_priv *priv = (void *)clk;
-	struct {
-		u32 mask;
-		void (*exec)(struct nve0_clock_priv *, int);
-	} stage[] = {
-		{ 0x007f, nve0_clock_prog_0   }, /* div programming */
-		{ 0x007f, nve0_clock_prog_1_0 }, /* select div mode */
-		{ 0xff80, nve0_clock_prog_1_1 },
-		{ 0x00ff, nve0_clock_prog_2   }, /* (maybe) program pll */
-		{ 0xff80, nve0_clock_prog_3   }, /* final divider */
-		{ 0x007f, nve0_clock_prog_4_0 }, /* (maybe) select pll mode */
-		{ 0xff80, nve0_clock_prog_4_1 },
-	};
-	int i, j;
-
-	for (i = 0; i < ARRAY_SIZE(stage); i++) {
-		for (j = 0; j < ARRAY_SIZE(priv->eng); j++) {
-			if (!(stage[i].mask & (1 << j)))
-				continue;
-			if (!priv->eng[j].freq)
-				continue;
-			stage[i].exec(priv, j);
-		}
-	}
-
-	return 0;
-}
-
-static void
-nve0_clock_tidy(struct nouveau_clock *clk)
-{
-	struct nve0_clock_priv *priv = (void *)clk;
-	memset(priv->eng, 0x00, sizeof(priv->eng));
-}
-
-static struct nouveau_clocks
-nve0_domain[] = {
-	{ nv_clk_src_crystal, 0xff },
-	{ nv_clk_src_href   , 0xff },
-	{ nv_clk_src_gpc    , 0x00, NVKM_CLK_DOM_FLAG_CORE, "core", 2000 },
-	{ nv_clk_src_hubk07 , 0x01, NVKM_CLK_DOM_FLAG_CORE },
-	{ nv_clk_src_rop    , 0x02, NVKM_CLK_DOM_FLAG_CORE },
-	{ nv_clk_src_mem    , 0x03, 0, "memory", 500 },
-	{ nv_clk_src_hubk06 , 0x04, NVKM_CLK_DOM_FLAG_CORE },
-	{ nv_clk_src_hubk01 , 0x05 },
-	{ nv_clk_src_vdec   , 0x06 },
-	{ nv_clk_src_daemon , 0x07 },
-	{ nv_clk_src_max }
-};
-
-static int
-nve0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nve0_clock_priv *priv;
-	int ret;
-
-	ret = nouveau_clock_create(parent, engine, oclass, nve0_domain, NULL, 0,
-				   true, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.read = nve0_clock_read;
-	priv->base.calc = nve0_clock_calc;
-	priv->base.prog = nve0_clock_prog;
-	priv->base.tidy = nve0_clock_tidy;
-	return 0;
-}
-
-struct nouveau_oclass
-nve0_clock_oclass = {
-	.handle = NV_SUBDEV(CLOCK, 0xe0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nve0_clock_ctor,
-		.dtor = _nouveau_clock_dtor,
-		.init = _nouveau_clock_init,
-		.fini = _nouveau_clock_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/pll.h b/drivers/gpu/drm/nouveau/core/subdev/clock/pll.h
deleted file mode 100644
index 445b14c33a98..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/pll.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __NOUVEAU_PLL_H__
-#define __NOUVEAU_PLL_H__
-
-int nv04_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq,
-		  int *N1, int *M1, int *N2, int *M2, int *P);
-int nva3_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq,
-		  int *N, int *fN, int *M, int *P);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c b/drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c
deleted file mode 100644
index b47d543ab2e3..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * Copyright 1993-2003 NVIDIA, Corporation
- * Copyright 2007-2009 Stuart Bennett
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/pll.h>
-
-#include "pll.h"
-
-static int
-getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
-	      int *pN, int *pM, int *pP)
-{
-	/* Find M, N and P for a single stage PLL
-	 *
-	 * Note that some bioses (NV3x) have lookup tables of precomputed MNP
-	 * values, but we're too lazy to use those atm
-	 *
-	 * "clk" parameter in kHz
-	 * returns calculated clock
-	 */
-	struct nouveau_bios *bios = nouveau_bios(subdev);
-	int minvco = info->vco1.min_freq, maxvco = info->vco1.max_freq;
-	int minM = info->vco1.min_m, maxM = info->vco1.max_m;
-	int minN = info->vco1.min_n, maxN = info->vco1.max_n;
-	int minU = info->vco1.min_inputfreq;
-	int maxU = info->vco1.max_inputfreq;
-	int minP = info->min_p;
-	int maxP = info->max_p_usable;
-	int crystal = info->refclk;
-	int M, N, thisP, P;
-	int clkP, calcclk;
-	int delta, bestdelta = INT_MAX;
-	int bestclk = 0;
-
-	/* this division verified for nv20, nv18, nv28 (Haiku), and nv34 */
-	/* possibly correlated with introduction of 27MHz crystal */
-	if (bios->version.major < 0x60) {
-		int cv = bios->version.chip;
-		if (cv < 0x17 || cv == 0x1a || cv == 0x20) {
-			if (clk > 250000)
-				maxM = 6;
-			if (clk > 340000)
-				maxM = 2;
-		} else if (cv < 0x40) {
-			if (clk > 150000)
-				maxM = 6;
-			if (clk > 200000)
-				maxM = 4;
-			if (clk > 340000)
-				maxM = 2;
-		}
-	}
-
-	P = 1 << maxP;
-	if ((clk * P) < minvco) {
-		minvco = clk * maxP;
-		maxvco = minvco * 2;
-	}
-
-	if (clk + clk/200 > maxvco)	/* +0.5% */
-		maxvco = clk + clk/200;
-
-	/* NV34 goes maxlog2P->0, NV20 goes 0->maxlog2P */
-	for (thisP = minP; thisP <= maxP; thisP++) {
-		P = 1 << thisP;
-		clkP = clk * P;
-
-		if (clkP < minvco)
-			continue;
-		if (clkP > maxvco)
-			return bestclk;
-
-		for (M = minM; M <= maxM; M++) {
-			if (crystal/M < minU)
-				return bestclk;
-			if (crystal/M > maxU)
-				continue;
-
-			/* add crystal/2 to round better */
-			N = (clkP * M + crystal/2) / crystal;
-
-			if (N < minN)
-				continue;
-			if (N > maxN)
-				break;
-
-			/* more rounding additions */
-			calcclk = ((N * crystal + P/2) / P + M/2) / M;
-			delta = abs(calcclk - clk);
-			/* we do an exhaustive search rather than terminating
-			 * on an optimality condition...
-			 */
-			if (delta < bestdelta) {
-				bestdelta = delta;
-				bestclk = calcclk;
-				*pN = N;
-				*pM = M;
-				*pP = thisP;
-				if (delta == 0)	/* except this one */
-					return bestclk;
-			}
-		}
-	}
-
-	return bestclk;
-}
-
-static int
-getMNP_double(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
-	      int *pN1, int *pM1, int *pN2, int *pM2, int *pP)
-{
-	/* Find M, N and P for a two stage PLL
-	 *
-	 * Note that some bioses (NV30+) have lookup tables of precomputed MNP
-	 * values, but we're too lazy to use those atm
-	 *
-	 * "clk" parameter in kHz
-	 * returns calculated clock
-	 */
-	int chip_version = nouveau_bios(subdev)->version.chip;
-	int minvco1 = info->vco1.min_freq, maxvco1 = info->vco1.max_freq;
-	int minvco2 = info->vco2.min_freq, maxvco2 = info->vco2.max_freq;
-	int minU1 = info->vco1.min_inputfreq, minU2 = info->vco2.min_inputfreq;
-	int maxU1 = info->vco1.max_inputfreq, maxU2 = info->vco2.max_inputfreq;
-	int minM1 = info->vco1.min_m, maxM1 = info->vco1.max_m;
-	int minN1 = info->vco1.min_n, maxN1 = info->vco1.max_n;
-	int minM2 = info->vco2.min_m, maxM2 = info->vco2.max_m;
-	int minN2 = info->vco2.min_n, maxN2 = info->vco2.max_n;
-	int maxlog2P = info->max_p_usable;
-	int crystal = info->refclk;
-	bool fixedgain2 = (minM2 == maxM2 && minN2 == maxN2);
-	int M1, N1, M2, N2, log2P;
-	int clkP, calcclk1, calcclk2, calcclkout;
-	int delta, bestdelta = INT_MAX;
-	int bestclk = 0;
-
-	int vco2 = (maxvco2 - maxvco2/200) / 2;
-	for (log2P = 0; clk && log2P < maxlog2P && clk <= (vco2 >> log2P); log2P++)
-		;
-	clkP = clk << log2P;
-
-	if (maxvco2 < clk + clk/200)	/* +0.5% */
-		maxvco2 = clk + clk/200;
-
-	for (M1 = minM1; M1 <= maxM1; M1++) {
-		if (crystal/M1 < minU1)
-			return bestclk;
-		if (crystal/M1 > maxU1)
-			continue;
-
-		for (N1 = minN1; N1 <= maxN1; N1++) {
-			calcclk1 = crystal * N1 / M1;
-			if (calcclk1 < minvco1)
-				continue;
-			if (calcclk1 > maxvco1)
-				break;
-
-			for (M2 = minM2; M2 <= maxM2; M2++) {
-				if (calcclk1/M2 < minU2)
-					break;
-				if (calcclk1/M2 > maxU2)
-					continue;
-
-				/* add calcclk1/2 to round better */
-				N2 = (clkP * M2 + calcclk1/2) / calcclk1;
-				if (N2 < minN2)
-					continue;
-				if (N2 > maxN2)
-					break;
-
-				if (!fixedgain2) {
-					if (chip_version < 0x60)
-						if (N2/M2 < 4 || N2/M2 > 10)
-							continue;
-
-					calcclk2 = calcclk1 * N2 / M2;
-					if (calcclk2 < minvco2)
-						break;
-					if (calcclk2 > maxvco2)
-						continue;
-				} else
-					calcclk2 = calcclk1;
-
-				calcclkout = calcclk2 >> log2P;
-				delta = abs(calcclkout - clk);
-				/* we do an exhaustive search rather than terminating
-				 * on an optimality condition...
-				 */
-				if (delta < bestdelta) {
-					bestdelta = delta;
-					bestclk = calcclkout;
-					*pN1 = N1;
-					*pM1 = M1;
-					*pN2 = N2;
-					*pM2 = M2;
-					*pP = log2P;
-					if (delta == 0)	/* except this one */
-						return bestclk;
-				}
-			}
-		}
-	}
-
-	return bestclk;
-}
-
-int
-nv04_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info, u32 freq,
-	      int *N1, int *M1, int *N2, int *M2, int *P)
-{
-	int ret;
-
-	if (!info->vco2.max_freq || !N2) {
-		ret = getMNP_single(subdev, info, freq, N1, M1, P);
-		if (N2) {
-			*N2 = 1;
-			*M2 = 1;
-		}
-	} else {
-		ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P);
-	}
-
-	if (!ret)
-		nv_error(subdev, "unable to compute acceptable pll values\n");
-	return ret;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/pllnva3.c b/drivers/gpu/drm/nouveau/core/subdev/clock/pllnva3.c
deleted file mode 100644
index 8eca457c2814..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/pllnva3.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright 2010 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/clock.h>
-#include <subdev/bios.h>
-#include <subdev/bios/pll.h>
-
-#include "pll.h"
-
-int
-nva3_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info,
-	      u32 freq, int *pN, int *pfN, int *pM, int *P)
-{
-	u32 best_err = ~0, err;
-	int M, lM, hM, N, fN;
-
-	*P = info->vco1.max_freq / freq;
-	if (*P > info->max_p)
-		*P = info->max_p;
-	if (*P < info->min_p)
-		*P = info->min_p;
-
-	lM = (info->refclk + info->vco1.max_inputfreq) / info->vco1.max_inputfreq;
-	lM = max(lM, (int)info->vco1.min_m);
-	hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq;
-	hM = min(hM, (int)info->vco1.max_m);
-	lM = min(lM, hM);
-
-	for (M = lM; M <= hM; M++) {
-		u32 tmp = freq * *P * M;
-		N  = tmp / info->refclk;
-		fN = tmp % info->refclk;
-
-		if (!pfN) {
-			if (fN >= info->refclk / 2)
-				N++;
-		} else {
-			if (fN <  info->refclk / 2)
-				N--;
-			fN = tmp - (N * info->refclk);
-		}
-
-		if (N < info->vco1.min_n)
-			continue;
-		if (N > info->vco1.max_n)
-			break;
-
-		err = abs(freq - (info->refclk * N / M / *P));
-		if (err < best_err) {
-			best_err = err;
-			*pN = N;
-			*pM = M;
-		}
-
-		if (pfN) {
-			*pfN = ((fN << 13) + info->refclk / 2) / info->refclk;
-			*pfN = (*pfN - 4096) & 0xffff;
-			return freq;
-		}
-	}
-
-	if (unlikely(best_err == ~0)) {
-		nv_error(subdev, "unable to find matching pll values\n");
-		return -EINVAL;
-	}
-
-	return info->refclk * *pN / *pM / *P;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/seq.h b/drivers/gpu/drm/nouveau/core/subdev/clock/seq.h
deleted file mode 100644
index fb33f06ebd59..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/seq.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef __NVKM_CLK_SEQ_H__
-#define __NVKM_CLK_SEQ_H__
-
-#include <subdev/bus.h>
-#include <subdev/bus/hwsq.h>
-
-#define clk_init(s,p)       hwsq_init(&(s)->base, (p))
-#define clk_exec(s,e)       hwsq_exec(&(s)->base, (e))
-#define clk_have(s,r)       ((s)->r_##r.addr != 0x000000)
-#define clk_rd32(s,r)       hwsq_rd32(&(s)->base, &(s)->r_##r)
-#define clk_wr32(s,r,d)     hwsq_wr32(&(s)->base, &(s)->r_##r, (d))
-#define clk_mask(s,r,m,d)   hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d))
-#define clk_setf(s,f,d)     hwsq_setf(&(s)->base, (f), (d))
-#define clk_wait(s,f,d)     hwsq_wait(&(s)->base, (f), (d))
-#define clk_nsec(s,n)       hwsq_nsec(&(s)->base, (n))
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c
deleted file mode 100644
index 0e45cee82463..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/option.h>
-
-#include <subdev/vga.h>
-
-#include "priv.h"
-
-int
-_nouveau_devinit_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nouveau_devinit *devinit = (void *)object;
-
-	/* force full reinit on resume */
-	if (suspend)
-		devinit->post = true;
-
-	/* unlock the extended vga crtc regs */
-	nv_lockvgac(devinit, false);
-
-	return nouveau_subdev_fini(&devinit->base, suspend);
-}
-
-int
-_nouveau_devinit_init(struct nouveau_object *object)
-{
-	struct nouveau_devinit_impl *impl = (void *)object->oclass;
-	struct nouveau_devinit *devinit = (void *)object;
-	int ret;
-
-	ret = nouveau_subdev_init(&devinit->base);
-	if (ret)
-		return ret;
-
-	ret = impl->post(&devinit->base, devinit->post);
-	if (ret)
-		return ret;
-
-	if (impl->disable)
-		nv_device(devinit)->disable_mask |= impl->disable(devinit);
-	return 0;
-}
-
-void
-_nouveau_devinit_dtor(struct nouveau_object *object)
-{
-	struct nouveau_devinit *devinit = (void *)object;
-
-	/* lock crtc regs */
-	nv_lockvgac(devinit, true);
-
-	nouveau_subdev_destroy(&devinit->base);
-}
-
-int
-nouveau_devinit_create_(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass,
-			int size, void **pobject)
-{
-	struct nouveau_devinit_impl *impl = (void *)oclass;
-	struct nouveau_device *device = nv_device(parent);
-	struct nouveau_devinit *devinit;
-	int ret;
-
-	ret = nouveau_subdev_create_(parent, engine, oclass, 0, "DEVINIT",
-				     "init", size, pobject);
-	devinit = *pobject;
-	if (ret)
-		return ret;
-
-	devinit->post = nouveau_boolopt(device->cfgopt, "NvForcePost", false);
-	devinit->meminit = impl->meminit;
-	devinit->pll_set = impl->pll_set;
-	devinit->mmio    = impl->mmio;
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h
deleted file mode 100644
index 6103484fea72..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include <core/device.h>
-
-#include <subdev/fb/regsnv04.h>
-
-#define NV04_PFB_DEBUG_0					0x00100080
-#	define NV04_PFB_DEBUG_0_PAGE_MODE			0x00000001
-#	define NV04_PFB_DEBUG_0_REFRESH_OFF			0x00000010
-#	define NV04_PFB_DEBUG_0_REFRESH_COUNTX64		0x00003f00
-#	define NV04_PFB_DEBUG_0_REFRESH_SLOW_CLK		0x00004000
-#	define NV04_PFB_DEBUG_0_SAFE_MODE			0x00008000
-#	define NV04_PFB_DEBUG_0_ALOM_ENABLE			0x00010000
-#	define NV04_PFB_DEBUG_0_CASOE				0x00100000
-#	define NV04_PFB_DEBUG_0_CKE_INVERT			0x10000000
-#	define NV04_PFB_DEBUG_0_REFINC				0x20000000
-#	define NV04_PFB_DEBUG_0_SAVE_POWER_OFF			0x40000000
-#define NV04_PFB_CFG0						0x00100200
-#	define NV04_PFB_CFG0_SCRAMBLE				0x20000000
-#define NV04_PFB_CFG1						0x00100204
-#define NV04_PFB_SCRAMBLE(i)                         (0x00100400 + 4 * (i))
-
-#define NV10_PFB_REFCTRL					0x00100210
-#	define NV10_PFB_REFCTRL_VALID_1				(1 << 31)
-
-static inline struct io_mapping *
-fbmem_init(struct nouveau_device *dev)
-{
-	return io_mapping_create_wc(nv_device_resource_start(dev, 1),
-				    nv_device_resource_len(dev, 1));
-}
-
-static inline void
-fbmem_fini(struct io_mapping *fb)
-{
-	io_mapping_free(fb);
-}
-
-static inline u32
-fbmem_peek(struct io_mapping *fb, u32 off)
-{
-	u8 __iomem *p = io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
-	u32 val = ioread32(p + (off & ~PAGE_MASK));
-	io_mapping_unmap_atomic(p);
-	return val;
-}
-
-static inline void
-fbmem_poke(struct io_mapping *fb, u32 off, u32 val)
-{
-	u8 __iomem *p = io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
-	iowrite32(val, p + (off & ~PAGE_MASK));
-	wmb();
-	io_mapping_unmap_atomic(p);
-}
-
-static inline bool
-fbmem_readback(struct io_mapping *fb, u32 off, u32 val)
-{
-	fbmem_poke(fb, off, val);
-	return val == fbmem_peek(fb, off);
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/gm107.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/gm107.c
deleted file mode 100644
index 4ba43d6a1ec8..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/gm107.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv50.h"
-
-u64
-gm107_devinit_disable(struct nouveau_devinit *devinit)
-{
-	struct nv50_devinit_priv *priv = (void *)devinit;
-	u32 r021c00 = nv_rd32(priv, 0x021c00);
-	u32 r021c04 = nv_rd32(priv, 0x021c04);
-	u64 disable = 0ULL;
-
-	if (r021c00 & 0x00000001)
-		disable |= (1ULL << NVDEV_ENGINE_COPY0);
-	if (r021c00 & 0x00000004)
-		disable |= (1ULL << NVDEV_ENGINE_COPY2);
-	if (r021c04 & 0x00000001)
-		disable |= (1ULL << NVDEV_ENGINE_DISP);
-
-	return disable;
-}
-
-struct nouveau_oclass *
-gm107_devinit_oclass = &(struct nouveau_devinit_impl) {
-	.base.handle = NV_SUBDEV(DEVINIT, 0x07),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_devinit_ctor,
-		.dtor = _nouveau_devinit_dtor,
-		.init = nv50_devinit_init,
-		.fini = _nouveau_devinit_fini,
-	},
-	.pll_set = nvc0_devinit_pll_set,
-	.disable = gm107_devinit_disable,
-	.post = nvbios_init,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/gm204.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/gm204.c
deleted file mode 100644
index e44a86662a2a..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/gm204.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/pmu.h>
-
-#include "nv50.h"
-
-static void
-pmu_code(struct nv50_devinit_priv *priv, u32 pmu, u32 img, u32 len, bool sec)
-{
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	int i;
-
-	nv_wr32(priv, 0x10a180, 0x01000000 | (sec ? 0x10000000 : 0) | pmu);
-	for (i = 0; i < len; i += 4) {
-		if ((i & 0xff) == 0)
-			nv_wr32(priv, 0x10a188, (pmu + i) >> 8);
-		nv_wr32(priv, 0x10a184, nv_ro32(bios, img + i));
-	}
-
-	while (i & 0xff) {
-		nv_wr32(priv, 0x10a184, 0x00000000);
-		i += 4;
-	}
-}
-
-static void
-pmu_data(struct nv50_devinit_priv *priv, u32 pmu, u32 img, u32 len)
-{
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	int i;
-
-	nv_wr32(priv, 0x10a1c0, 0x01000000 | pmu);
-	for (i = 0; i < len; i += 4)
-		nv_wr32(priv, 0x10a1c4, nv_ro32(bios, img + i));
-}
-
-static u32
-pmu_args(struct nv50_devinit_priv *priv, u32 argp, u32 argi)
-{
-	nv_wr32(priv, 0x10a1c0, argp);
-	nv_wr32(priv, 0x10a1c0, nv_rd32(priv, 0x10a1c4) + argi);
-	return nv_rd32(priv, 0x10a1c4);
-}
-
-static void
-pmu_exec(struct nv50_devinit_priv *priv, u32 init_addr)
-{
-	nv_wr32(priv, 0x10a104, init_addr);
-	nv_wr32(priv, 0x10a10c, 0x00000000);
-	nv_wr32(priv, 0x10a100, 0x00000002);
-}
-
-static int
-pmu_load(struct nv50_devinit_priv *priv, u8 type, bool post,
-	 u32 *init_addr_pmu, u32 *args_addr_pmu)
-{
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	struct nvbios_pmuR pmu;
-
-	if (!nvbios_pmuRm(bios, type, &pmu)) {
-		nv_error(priv, "VBIOS PMU fuc %02x not found\n", type);
-		return -EINVAL;
-	}
-
-	if (!post)
-		return 0;
-
-	pmu_code(priv, pmu.boot_addr_pmu, pmu.boot_addr, pmu.boot_size, false);
-	pmu_code(priv, pmu.code_addr_pmu, pmu.code_addr, pmu.code_size, true);
-	pmu_data(priv, pmu.data_addr_pmu, pmu.data_addr, pmu.data_size);
-
-	if (init_addr_pmu) {
-		*init_addr_pmu = pmu.init_addr_pmu;
-		*args_addr_pmu = pmu.args_addr_pmu;
-		return 0;
-	}
-
-	return pmu_exec(priv, pmu.init_addr_pmu), 0;
-}
-
-static int
-gm204_devinit_post(struct nouveau_subdev *subdev, bool post)
-{
-	struct nv50_devinit_priv *priv = (void *)nouveau_devinit(subdev);
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	struct bit_entry bit_I;
-	u32 init, args;
-	int ret;
-
-	if (bit_entry(bios, 'I', &bit_I) || bit_I.version != 1 ||
-					    bit_I.length < 0x1c) {
-		nv_error(priv, "VBIOS PMU init data not found\n");
-		return -EINVAL;
-	}
-
-	/* reset PMU and load init table parser ucode */
-	if (post) {
-		nv_mask(priv, 0x000200, 0x00002000, 0x00000000);
-		nv_mask(priv, 0x000200, 0x00002000, 0x00002000);
-		nv_rd32(priv, 0x000200);
-		while (nv_rd32(priv, 0x10a10c) & 0x00000006) {
-		}
-	}
-
-	ret = pmu_load(priv, 0x04, post, &init, &args);
-	if (ret)
-		return ret;
-
-	/* upload first chunk of init data */
-	if (post) {
-		u32 pmu = pmu_args(priv, args + 0x08, 0x08);
-		u32 img = nv_ro16(bios, bit_I.offset + 0x14);
-		u32 len = nv_ro16(bios, bit_I.offset + 0x16);
-		pmu_data(priv, pmu, img, len);
-	}
-
-	/* upload second chunk of init data */
-	if (post) {
-		u32 pmu = pmu_args(priv, args + 0x08, 0x10);
-		u32 img = nv_ro16(bios, bit_I.offset + 0x18);
-		u32 len = nv_ro16(bios, bit_I.offset + 0x1a);
-		pmu_data(priv, pmu, img, len);
-	}
-
-	/* execute init tables */
-	if (post) {
-		nv_wr32(priv, 0x10a040, 0x00005000);
-		pmu_exec(priv, init);
-		while (!(nv_rd32(priv, 0x10a040) & 0x00002000)) {
-		}
-	}
-
-	/* load and execute some other ucode image (bios therm?) */
-	return pmu_load(priv, 0x01, post, NULL, NULL);
-}
-
-struct nouveau_oclass *
-gm204_devinit_oclass = &(struct nouveau_devinit_impl) {
-	.base.handle = NV_SUBDEV(DEVINIT, 0x07),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_devinit_ctor,
-		.dtor = _nouveau_devinit_dtor,
-		.init = nv50_devinit_init,
-		.fini = _nouveau_devinit_fini,
-	},
-	.pll_set = nvc0_devinit_pll_set,
-	.disable = gm107_devinit_disable,
-	.post = gm204_devinit_post,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c
deleted file mode 100644
index 65651c50f6ea..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c
+++ /dev/null
@@ -1,468 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include <subdev/vga.h>
-
-#include "fbmem.h"
-#include "nv04.h"
-
-static void
-nv04_devinit_meminit(struct nouveau_devinit *devinit)
-{
-	struct nv04_devinit_priv *priv = (void *)devinit;
-	u32 patt = 0xdeadbeef;
-	struct io_mapping *fb;
-	int i;
-
-	/* Map the framebuffer aperture */
-	fb = fbmem_init(nv_device(priv));
-	if (!fb) {
-		nv_error(priv, "failed to map fb\n");
-		return;
-	}
-
-	/* Sequencer and refresh off */
-	nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) | 0x20);
-	nv_mask(priv, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
-
-	nv_mask(priv, NV04_PFB_BOOT_0, ~0,
-		      NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
-		      NV04_PFB_BOOT_0_RAM_WIDTH_128 |
-		      NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
-
-	for (i = 0; i < 4; i++)
-		fbmem_poke(fb, 4 * i, patt);
-
-	fbmem_poke(fb, 0x400000, patt + 1);
-
-	if (fbmem_peek(fb, 0) == patt + 1) {
-		nv_mask(priv, NV04_PFB_BOOT_0,
-			      NV04_PFB_BOOT_0_RAM_TYPE,
-			      NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
-		nv_mask(priv, NV04_PFB_DEBUG_0,
-			      NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
-
-		for (i = 0; i < 4; i++)
-			fbmem_poke(fb, 4 * i, patt);
-
-		if ((fbmem_peek(fb, 0xc) & 0xffff) != (patt & 0xffff))
-			nv_mask(priv, NV04_PFB_BOOT_0,
-				      NV04_PFB_BOOT_0_RAM_WIDTH_128 |
-				      NV04_PFB_BOOT_0_RAM_AMOUNT,
-				      NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
-	} else
-	if ((fbmem_peek(fb, 0xc) & 0xffff0000) != (patt & 0xffff0000)) {
-		nv_mask(priv, NV04_PFB_BOOT_0,
-			      NV04_PFB_BOOT_0_RAM_WIDTH_128 |
-			      NV04_PFB_BOOT_0_RAM_AMOUNT,
-			      NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
-	} else
-	if (fbmem_peek(fb, 0) != patt) {
-		if (fbmem_readback(fb, 0x800000, patt))
-			nv_mask(priv, NV04_PFB_BOOT_0,
-				      NV04_PFB_BOOT_0_RAM_AMOUNT,
-				      NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
-		else
-			nv_mask(priv, NV04_PFB_BOOT_0,
-				      NV04_PFB_BOOT_0_RAM_AMOUNT,
-				      NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
-
-		nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
-			      NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
-	} else
-	if (!fbmem_readback(fb, 0x800000, patt)) {
-		nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
-			      NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
-
-	}
-
-	/* Refresh on, sequencer on */
-	nv_mask(priv, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
-	nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) & ~0x20);
-	fbmem_fini(fb);
-}
-
-static int
-powerctrl_1_shift(int chip_version, int reg)
-{
-	int shift = -4;
-
-	if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20)
-		return shift;
-
-	switch (reg) {
-	case 0x680520:
-		shift += 4;
-	case 0x680508:
-		shift += 4;
-	case 0x680504:
-		shift += 4;
-	case 0x680500:
-		shift += 4;
-	}
-
-	/*
-	 * the shift for vpll regs is only used for nv3x chips with a single
-	 * stage pll
-	 */
-	if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 ||
-			  chip_version == 0x36 || chip_version >= 0x40))
-		shift = -4;
-
-	return shift;
-}
-
-void
-setPLL_single(struct nouveau_devinit *devinit, u32 reg,
-	      struct nouveau_pll_vals *pv)
-{
-	int chip_version = nouveau_bios(devinit)->version.chip;
-	uint32_t oldpll = nv_rd32(devinit, reg);
-	int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff;
-	uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;
-	uint32_t saved_powerctrl_1 = 0;
-	int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg);
-
-	if (oldpll == pll)
-		return;	/* already set */
-
-	if (shift_powerctrl_1 >= 0) {
-		saved_powerctrl_1 = nv_rd32(devinit, 0x001584);
-		nv_wr32(devinit, 0x001584,
-			(saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
-			1 << shift_powerctrl_1);
-	}
-
-	if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
-		/* upclock -- write new post divider first */
-		nv_wr32(devinit, reg, pv->log2P << 16 | (oldpll & 0xffff));
-	else
-		/* downclock -- write new NM first */
-		nv_wr32(devinit, reg, (oldpll & 0xffff0000) | pv->NM1);
-
-	if ((chip_version < 0x17 || chip_version == 0x1a) &&
-	    chip_version != 0x11)
-		/* wait a bit on older chips */
-		msleep(64);
-	nv_rd32(devinit, reg);
-
-	/* then write the other half as well */
-	nv_wr32(devinit, reg, pll);
-
-	if (shift_powerctrl_1 >= 0)
-		nv_wr32(devinit, 0x001584, saved_powerctrl_1);
-}
-
-static uint32_t
-new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580)
-{
-	bool head_a = (reg1 == 0x680508);
-
-	if (ss)	/* single stage pll mode */
-		ramdac580 |= head_a ? 0x00000100 : 0x10000000;
-	else
-		ramdac580 &= head_a ? 0xfffffeff : 0xefffffff;
-
-	return ramdac580;
-}
-
-void
-setPLL_double_highregs(struct nouveau_devinit *devinit, u32 reg1,
-		       struct nouveau_pll_vals *pv)
-{
-	int chip_version = nouveau_bios(devinit)->version.chip;
-	bool nv3035 = chip_version == 0x30 || chip_version == 0x35;
-	uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);
-	uint32_t oldpll1 = nv_rd32(devinit, reg1);
-	uint32_t oldpll2 = !nv3035 ? nv_rd32(devinit, reg2) : 0;
-	uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;
-	uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;
-	uint32_t oldramdac580 = 0, ramdac580 = 0;
-	bool single_stage = !pv->NM2 || pv->N2 == pv->M2;	/* nv41+ only */
-	uint32_t saved_powerctrl_1 = 0, savedc040 = 0;
-	int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);
-
-	/* model specific additions to generic pll1 and pll2 set up above */
-	if (nv3035) {
-		pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
-		       (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
-		pll2 = 0;
-	}
-	if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */
-		oldramdac580 = nv_rd32(devinit, 0x680580);
-		ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);
-		if (oldramdac580 != ramdac580)
-			oldpll1 = ~0;	/* force mismatch */
-		if (single_stage)
-			/* magic value used by nvidia in single stage mode */
-			pll2 |= 0x011f;
-	}
-	if (chip_version > 0x70)
-		/* magic bits set by the blob (but not the bios) on g71-73 */
-		pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28;
-
-	if (oldpll1 == pll1 && oldpll2 == pll2)
-		return;	/* already set */
-
-	if (shift_powerctrl_1 >= 0) {
-		saved_powerctrl_1 = nv_rd32(devinit, 0x001584);
-		nv_wr32(devinit, 0x001584,
-			(saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
-			1 << shift_powerctrl_1);
-	}
-
-	if (chip_version >= 0x40) {
-		int shift_c040 = 14;
-
-		switch (reg1) {
-		case 0x680504:
-			shift_c040 += 2;
-		case 0x680500:
-			shift_c040 += 2;
-		case 0x680520:
-			shift_c040 += 2;
-		case 0x680508:
-			shift_c040 += 2;
-		}
-
-		savedc040 = nv_rd32(devinit, 0xc040);
-		if (shift_c040 != 14)
-			nv_wr32(devinit, 0xc040, savedc040 & ~(3 << shift_c040));
-	}
-
-	if (oldramdac580 != ramdac580)
-		nv_wr32(devinit, 0x680580, ramdac580);
-
-	if (!nv3035)
-		nv_wr32(devinit, reg2, pll2);
-	nv_wr32(devinit, reg1, pll1);
-
-	if (shift_powerctrl_1 >= 0)
-		nv_wr32(devinit, 0x001584, saved_powerctrl_1);
-	if (chip_version >= 0x40)
-		nv_wr32(devinit, 0xc040, savedc040);
-}
-
-void
-setPLL_double_lowregs(struct nouveau_devinit *devinit, u32 NMNMreg,
-		      struct nouveau_pll_vals *pv)
-{
-	/* When setting PLLs, there is a merry game of disabling and enabling
-	 * various bits of hardware during the process. This function is a
-	 * synthesis of six nv4x traces, nearly each card doing a subtly
-	 * different thing. With luck all the necessary bits for each card are
-	 * combined herein. Without luck it deviates from each card's formula
-	 * so as to not work on any :)
-	 */
-
-	uint32_t Preg = NMNMreg - 4;
-	bool mpll = Preg == 0x4020;
-	uint32_t oldPval = nv_rd32(devinit, Preg);
-	uint32_t NMNM = pv->NM2 << 16 | pv->NM1;
-	uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) |
-			0xc << 28 | pv->log2P << 16;
-	uint32_t saved4600 = 0;
-	/* some cards have different maskc040s */
-	uint32_t maskc040 = ~(3 << 14), savedc040;
-	bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
-
-	if (nv_rd32(devinit, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
-		return;
-
-	if (Preg == 0x4000)
-		maskc040 = ~0x333;
-	if (Preg == 0x4058)
-		maskc040 = ~(0xc << 24);
-
-	if (mpll) {
-		struct nvbios_pll info;
-		uint8_t Pval2;
-
-		if (nvbios_pll_parse(nouveau_bios(devinit), Preg, &info))
-			return;
-
-		Pval2 = pv->log2P + info.bias_p;
-		if (Pval2 > info.max_p)
-			Pval2 = info.max_p;
-		Pval |= 1 << 28 | Pval2 << 20;
-
-		saved4600 = nv_rd32(devinit, 0x4600);
-		nv_wr32(devinit, 0x4600, saved4600 | 8 << 28);
-	}
-	if (single_stage)
-		Pval |= mpll ? 1 << 12 : 1 << 8;
-
-	nv_wr32(devinit, Preg, oldPval | 1 << 28);
-	nv_wr32(devinit, Preg, Pval & ~(4 << 28));
-	if (mpll) {
-		Pval |= 8 << 20;
-		nv_wr32(devinit, 0x4020, Pval & ~(0xc << 28));
-		nv_wr32(devinit, 0x4038, Pval & ~(0xc << 28));
-	}
-
-	savedc040 = nv_rd32(devinit, 0xc040);
-	nv_wr32(devinit, 0xc040, savedc040 & maskc040);
-
-	nv_wr32(devinit, NMNMreg, NMNM);
-	if (NMNMreg == 0x4024)
-		nv_wr32(devinit, 0x403c, NMNM);
-
-	nv_wr32(devinit, Preg, Pval);
-	if (mpll) {
-		Pval &= ~(8 << 20);
-		nv_wr32(devinit, 0x4020, Pval);
-		nv_wr32(devinit, 0x4038, Pval);
-		nv_wr32(devinit, 0x4600, saved4600);
-	}
-
-	nv_wr32(devinit, 0xc040, savedc040);
-
-	if (mpll) {
-		nv_wr32(devinit, 0x4020, Pval & ~(1 << 28));
-		nv_wr32(devinit, 0x4038, Pval & ~(1 << 28));
-	}
-}
-
-int
-nv04_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
-{
-	struct nouveau_bios *bios = nouveau_bios(devinit);
-	struct nouveau_pll_vals pv;
-	struct nvbios_pll info;
-	int cv = bios->version.chip;
-	int N1, M1, N2, M2, P;
-	int ret;
-
-	ret = nvbios_pll_parse(bios, type > 0x405c ? type : type - 4, &info);
-	if (ret)
-		return ret;
-
-	ret = nv04_pll_calc(nv_subdev(devinit), &info, freq,
-			   &N1, &M1, &N2, &M2, &P);
-	if (!ret)
-		return -EINVAL;
-
-	pv.refclk = info.refclk;
-	pv.N1 = N1;
-	pv.M1 = M1;
-	pv.N2 = N2;
-	pv.M2 = M2;
-	pv.log2P = P;
-
-	if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
-	    cv >= 0x40) {
-		if (type > 0x405c)
-			setPLL_double_highregs(devinit, type, &pv);
-		else
-			setPLL_double_lowregs(devinit, type, &pv);
-	} else
-		setPLL_single(devinit, type, &pv);
-
-	return 0;
-}
-
-int
-nv04_devinit_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv04_devinit_priv *priv = (void *)object;
-	int ret;
-
-	/* make i2c busses accessible */
-	nv_mask(priv, 0x000200, 0x00000001, 0x00000001);
-
-	ret = nouveau_devinit_fini(&priv->base, suspend);
-	if (ret)
-		return ret;
-
-	/* unslave crtcs */
-	if (priv->owner < 0)
-		priv->owner = nv_rdvgaowner(priv);
-	nv_wrvgaowner(priv, 0);
-
-	return 0;
-}
-
-int
-nv04_devinit_init(struct nouveau_object *object)
-{
-	struct nv04_devinit_priv *priv = (void *)object;
-
-	if (!priv->base.post) {
-		u32 htotal = nv_rdvgac(priv, 0, 0x06);
-		htotal |= (nv_rdvgac(priv, 0, 0x07) & 0x01) << 8;
-		htotal |= (nv_rdvgac(priv, 0, 0x07) & 0x20) << 4;
-		htotal |= (nv_rdvgac(priv, 0, 0x25) & 0x01) << 10;
-		htotal |= (nv_rdvgac(priv, 0, 0x41) & 0x01) << 11;
-		if (!htotal) {
-			nv_info(priv, "adaptor not initialised\n");
-			priv->base.post = true;
-		}
-	}
-
-	return nouveau_devinit_init(&priv->base);
-}
-
-void
-nv04_devinit_dtor(struct nouveau_object *object)
-{
-	struct nv04_devinit_priv *priv = (void *)object;
-
-	/* restore vga owner saved at first init */
-	nv_wrvgaowner(priv, priv->owner);
-
-	nouveau_devinit_destroy(&priv->base);
-}
-
-int
-nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 size,
-		  struct nouveau_object **pobject)
-{
-	struct nv04_devinit_priv *priv;
-	int ret;
-
-	ret = nouveau_devinit_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->owner = -1;
-	return 0;
-}
-
-struct nouveau_oclass *
-nv04_devinit_oclass = &(struct nouveau_devinit_impl) {
-	.base.handle = NV_SUBDEV(DEVINIT, 0x04),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_devinit_ctor,
-		.dtor = nv04_devinit_dtor,
-		.init = nv04_devinit_init,
-		.fini = nv04_devinit_fini,
-	},
-	.meminit = nv04_devinit_meminit,
-	.pll_set = nv04_devinit_pll_set,
-	.post = nvbios_init,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h
deleted file mode 100644
index 23470a57510c..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef __NVKM_DEVINIT_NV04_H__
-#define __NVKM_DEVINIT_NV04_H__
-
-#include "priv.h"
-
-struct nv04_devinit_priv {
-	struct nouveau_devinit base;
-	u8 owner;
-};
-
-int  nv04_devinit_ctor(struct nouveau_object *, struct nouveau_object *,
-		       struct nouveau_oclass *, void *, u32,
-		       struct nouveau_object **);
-void nv04_devinit_dtor(struct nouveau_object *);
-int  nv04_devinit_init(struct nouveau_object *);
-int  nv04_devinit_fini(struct nouveau_object *, bool);
-int  nv04_devinit_pll_set(struct nouveau_devinit *, u32, u32);
-
-void setPLL_single(struct nouveau_devinit *, u32, struct nouveau_pll_vals *);
-void setPLL_double_highregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *);
-void setPLL_double_lowregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c
deleted file mode 100644
index a2007a3efc4d..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bmp.h>
-#include <subdev/vga.h>
-
-#include "fbmem.h"
-#include "nv04.h"
-
-static void
-nv05_devinit_meminit(struct nouveau_devinit *devinit)
-{
-	static const u8 default_config_tab[][2] = {
-		{ 0x24, 0x00 },
-		{ 0x28, 0x00 },
-		{ 0x24, 0x01 },
-		{ 0x1f, 0x00 },
-		{ 0x0f, 0x00 },
-		{ 0x17, 0x00 },
-		{ 0x06, 0x00 },
-		{ 0x00, 0x00 }
-	};
-	struct nv04_devinit_priv *priv = (void *)devinit;
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	struct io_mapping *fb;
-	u32 patt = 0xdeadbeef;
-	u16 data;
-	u8 strap, ramcfg[2];
-	int i, v;
-
-	/* Map the framebuffer aperture */
-	fb = fbmem_init(nv_device(priv));
-	if (!fb) {
-		nv_error(priv, "failed to map fb\n");
-		return;
-	}
-
-	strap = (nv_rd32(priv, 0x101000) & 0x0000003c) >> 2;
-	if ((data = bmp_mem_init_table(bios))) {
-		ramcfg[0] = nv_ro08(bios, data + 2 * strap + 0);
-		ramcfg[1] = nv_ro08(bios, data + 2 * strap + 1);
-	} else {
-		ramcfg[0] = default_config_tab[strap][0];
-		ramcfg[1] = default_config_tab[strap][1];
-	}
-
-	/* Sequencer off */
-	nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) | 0x20);
-
-	if (nv_rd32(priv, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
-		goto out;
-
-	nv_mask(priv, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
-
-	/* If present load the hardcoded scrambling table */
-	if (data) {
-		for (i = 0, data += 0x10; i < 8; i++, data += 4) {
-			u32 scramble = nv_ro32(bios, data);
-			nv_wr32(priv, NV04_PFB_SCRAMBLE(i), scramble);
-		}
-	}
-
-	/* Set memory type/width/length defaults depending on the straps */
-	nv_mask(priv, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
-
-	if (ramcfg[1] & 0x80)
-		nv_mask(priv, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
-
-	nv_mask(priv, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
-	nv_mask(priv, NV04_PFB_CFG1, 0, 1);
-
-	/* Probe memory bus width */
-	for (i = 0; i < 4; i++)
-		fbmem_poke(fb, 4 * i, patt);
-
-	if (fbmem_peek(fb, 0xc) != patt)
-		nv_mask(priv, NV04_PFB_BOOT_0,
-			  NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
-
-	/* Probe memory length */
-	v = nv_rd32(priv, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
-
-	if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
-	    (!fbmem_readback(fb, 0x1000000, ++patt) ||
-	     !fbmem_readback(fb, 0, ++patt)))
-		nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
-			  NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
-
-	if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
-	    !fbmem_readback(fb, 0x800000, ++patt))
-		nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
-			  NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
-
-	if (!fbmem_readback(fb, 0x400000, ++patt))
-		nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
-			  NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
-
-out:
-	/* Sequencer on */
-	nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) & ~0x20);
-	fbmem_fini(fb);
-}
-
-struct nouveau_oclass *
-nv05_devinit_oclass = &(struct nouveau_devinit_impl) {
-	.base.handle = NV_SUBDEV(DEVINIT, 0x05),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_devinit_ctor,
-		.dtor = nv04_devinit_dtor,
-		.init = nv04_devinit_init,
-		.fini = nv04_devinit_fini,
-	},
-	.meminit = nv05_devinit_meminit,
-	.pll_set = nv04_devinit_pll_set,
-	.post = nvbios_init,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c
deleted file mode 100644
index 178b46f79b50..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include <subdev/vga.h>
-
-#include "fbmem.h"
-#include "nv04.h"
-
-static void
-nv10_devinit_meminit(struct nouveau_devinit *devinit)
-{
-	struct nv04_devinit_priv *priv = (void *)devinit;
-	static const int mem_width[] = { 0x10, 0x00, 0x20 };
-	int mem_width_count;
-	uint32_t patt = 0xdeadbeef;
-	struct io_mapping *fb;
-	int i, j, k;
-
-	if (nv_device(priv)->card_type >= NV_11 &&
-	    nv_device(priv)->chipset >= 0x17)
-		mem_width_count = 3;
-	else
-		mem_width_count = 2;
-
-	/* Map the framebuffer aperture */
-	fb = fbmem_init(nv_device(priv));
-	if (!fb) {
-		nv_error(priv, "failed to map fb\n");
-		return;
-	}
-
-	nv_wr32(priv, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
-
-	/* Probe memory bus width */
-	for (i = 0; i < mem_width_count; i++) {
-		nv_mask(priv, NV04_PFB_CFG0, 0x30, mem_width[i]);
-
-		for (j = 0; j < 4; j++) {
-			for (k = 0; k < 4; k++)
-				fbmem_poke(fb, 0x1c, 0);
-
-			fbmem_poke(fb, 0x1c, patt);
-			fbmem_poke(fb, 0x3c, 0);
-
-			if (fbmem_peek(fb, 0x1c) == patt)
-				goto mem_width_found;
-		}
-	}
-
-mem_width_found:
-	patt <<= 1;
-
-	/* Probe amount of installed memory */
-	for (i = 0; i < 4; i++) {
-		int off = nv_rd32(priv, 0x10020c) - 0x100000;
-
-		fbmem_poke(fb, off, patt);
-		fbmem_poke(fb, 0, 0);
-
-		fbmem_peek(fb, 0);
-		fbmem_peek(fb, 0);
-		fbmem_peek(fb, 0);
-		fbmem_peek(fb, 0);
-
-		if (fbmem_peek(fb, off) == patt)
-			goto amount_found;
-	}
-
-	/* IC missing - disable the upper half memory space. */
-	nv_mask(priv, NV04_PFB_CFG0, 0x1000, 0);
-
-amount_found:
-	fbmem_fini(fb);
-}
-
-struct nouveau_oclass *
-nv10_devinit_oclass = &(struct nouveau_devinit_impl) {
-	.base.handle = NV_SUBDEV(DEVINIT, 0x10),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_devinit_ctor,
-		.dtor = nv04_devinit_dtor,
-		.init = nv04_devinit_init,
-		.fini = nv04_devinit_fini,
-	},
-	.meminit = nv10_devinit_meminit,
-	.pll_set = nv04_devinit_pll_set,
-	.post = nvbios_init,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c
deleted file mode 100644
index 995dd97af3e9..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv04.h"
-
-struct nouveau_oclass *
-nv1a_devinit_oclass = &(struct nouveau_devinit_impl) {
-	.base.handle = NV_SUBDEV(DEVINIT, 0x1a),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_devinit_ctor,
-		.dtor = nv04_devinit_dtor,
-		.init = nv04_devinit_init,
-		.fini = nv04_devinit_fini,
-	},
-	.pll_set = nv04_devinit_pll_set,
-	.post = nvbios_init,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c
deleted file mode 100644
index 915089fb46f7..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "nv04.h"
-#include "fbmem.h"
-
-static void
-nv20_devinit_meminit(struct nouveau_devinit *devinit)
-{
-	struct nv04_devinit_priv *priv = (void *)devinit;
-	struct nouveau_device *device = nv_device(priv);
-	uint32_t mask = (device->chipset >= 0x25 ? 0x300 : 0x900);
-	uint32_t amount, off;
-	struct io_mapping *fb;
-
-	/* Map the framebuffer aperture */
-	fb = fbmem_init(nv_device(priv));
-	if (!fb) {
-		nv_error(priv, "failed to map fb\n");
-		return;
-	}
-
-	nv_wr32(priv, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
-
-	/* Allow full addressing */
-	nv_mask(priv, NV04_PFB_CFG0, 0, mask);
-
-	amount = nv_rd32(priv, 0x10020c);
-	for (off = amount; off > 0x2000000; off -= 0x2000000)
-		fbmem_poke(fb, off - 4, off);
-
-	amount = nv_rd32(priv, 0x10020c);
-	if (amount != fbmem_peek(fb, amount - 4))
-		/* IC missing - disable the upper half memory space. */
-		nv_mask(priv, NV04_PFB_CFG0, mask, 0);
-
-	fbmem_fini(fb);
-}
-
-struct nouveau_oclass *
-nv20_devinit_oclass = &(struct nouveau_devinit_impl) {
-	.base.handle = NV_SUBDEV(DEVINIT, 0x20),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_devinit_ctor,
-		.dtor = nv04_devinit_dtor,
-		.init = nv04_devinit_init,
-		.fini = nv04_devinit_fini,
-	},
-	.meminit = nv20_devinit_meminit,
-	.pll_set = nv04_devinit_pll_set,
-	.post = nvbios_init,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c
deleted file mode 100644
index 968334d1dca4..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/disp.h>
-#include <subdev/bios/init.h>
-#include <subdev/ibus.h>
-#include <subdev/vga.h>
-
-#include "nv50.h"
-
-int
-nv50_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
-{
-	struct nv50_devinit_priv *priv = (void *)devinit;
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	struct nvbios_pll info;
-	int N1, M1, N2, M2, P;
-	int ret;
-
-	ret = nvbios_pll_parse(bios, type, &info);
-	if (ret) {
-		nv_error(devinit, "failed to retrieve pll data, %d\n", ret);
-		return ret;
-	}
-
-	ret = nv04_pll_calc(nv_subdev(devinit), &info, freq, &N1, &M1, &N2, &M2, &P);
-	if (!ret) {
-		nv_error(devinit, "failed pll calculation\n");
-		return ret;
-	}
-
-	switch (info.type) {
-	case PLL_VPLL0:
-	case PLL_VPLL1:
-		nv_wr32(priv, info.reg + 0, 0x10000611);
-		nv_mask(priv, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1);
-		nv_mask(priv, info.reg + 8, 0x7fff00ff, (P  << 28) |
-							(M2 << 16) | N2);
-		break;
-	case PLL_MEMORY:
-		nv_mask(priv, info.reg + 0, 0x01ff0000, (P << 22) |
-						        (info.bias_p << 19) |
-							(P << 16));
-		nv_wr32(priv, info.reg + 4, (N1 << 8) | M1);
-		break;
-	default:
-		nv_mask(priv, info.reg + 0, 0x00070000, (P << 16));
-		nv_wr32(priv, info.reg + 4, (N1 << 8) | M1);
-		break;
-	}
-
-	return 0;
-}
-
-static u64
-nv50_devinit_disable(struct nouveau_devinit *devinit)
-{
-	struct nv50_devinit_priv *priv = (void *)devinit;
-	u32 r001540 = nv_rd32(priv, 0x001540);
-	u64 disable = 0ULL;
-
-	if (!(r001540 & 0x40000000))
-		disable |= (1ULL << NVDEV_ENGINE_MPEG);
-
-	return disable;
-}
-
-int
-nv50_devinit_init(struct nouveau_object *object)
-{
-	struct nouveau_bios *bios = nouveau_bios(object);
-	struct nouveau_ibus *ibus = nouveau_ibus(object);
-	struct nv50_devinit_priv *priv = (void *)object;
-	struct nvbios_outp info;
-	struct dcb_output outp;
-	u8  ver = 0xff, hdr, cnt, len;
-	int ret, i = 0;
-
-	if (!priv->base.post) {
-		if (!nv_rdvgac(priv, 0, 0x00) &&
-		    !nv_rdvgac(priv, 0, 0x1a)) {
-			nv_info(priv, "adaptor not initialised\n");
-			priv->base.post = true;
-		}
-	}
-
-	/* some boards appear to require certain priv register timeouts
-	 * to be bumped before runing devinit scripts.  not a clue why
-	 * the vbios engineers didn't make the scripts just work...
-	 */
-	if (priv->base.post && ibus)
-		nv_ofuncs(ibus)->init(nv_object(ibus));
-
-	ret = nouveau_devinit_init(&priv->base);
-	if (ret)
-		return ret;
-
-	/* if we ran the init tables, we have to execute the first script
-	 * pointer of each dcb entry's display encoder table in order
-	 * to properly initialise each encoder.
-	 */
-	while (priv->base.post && dcb_outp_parse(bios, i, &ver, &hdr, &outp)) {
-		if (nvbios_outp_match(bios, outp.hasht, outp.hashm,
-				     &ver, &hdr, &cnt, &len, &info)) {
-			struct nvbios_init init = {
-				.subdev = nv_subdev(priv),
-				.bios = bios,
-				.offset = info.script[0],
-				.outp = &outp,
-				.crtc = -1,
-				.execute = 1,
-			};
-
-			nvbios_exec(&init);
-		}
-		i++;
-	}
-
-	return 0;
-}
-
-int
-nv50_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 size,
-		  struct nouveau_object **pobject)
-{
-	struct nv50_devinit_priv *priv;
-	int ret;
-
-	ret = nouveau_devinit_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-struct nouveau_oclass *
-nv50_devinit_oclass = &(struct nouveau_devinit_impl) {
-	.base.handle = NV_SUBDEV(DEVINIT, 0x50),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_devinit_ctor,
-		.dtor = _nouveau_devinit_dtor,
-		.init = nv50_devinit_init,
-		.fini = _nouveau_devinit_fini,
-	},
-	.pll_set = nv50_devinit_pll_set,
-	.disable = nv50_devinit_disable,
-	.post = nvbios_init,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h
deleted file mode 100644
index f412bb7f780e..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef __NVKM_DEVINIT_NV50_H__
-#define __NVKM_DEVINIT_NV50_H__
-
-#include "priv.h"
-
-struct nv50_devinit_priv {
-	struct nouveau_devinit base;
-	u32 r001540;
-};
-
-int  nv50_devinit_ctor(struct nouveau_object *, struct nouveau_object *,
-		       struct nouveau_oclass *, void *, u32,
-		       struct nouveau_object **);
-int  nv50_devinit_init(struct nouveau_object *);
-int  nv50_devinit_pll_set(struct nouveau_devinit *, u32, u32);
-
-int  nva3_devinit_pll_set(struct nouveau_devinit *, u32, u32);
-
-int  nvc0_devinit_pll_set(struct nouveau_devinit *, u32, u32);
-
-u64  gm107_devinit_disable(struct nouveau_devinit *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv84.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv84.c
deleted file mode 100644
index a7c80ded77cd..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv84.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv50.h"
-
-static u64
-nv84_devinit_disable(struct nouveau_devinit *devinit)
-{
-	struct nv50_devinit_priv *priv = (void *)devinit;
-	u32 r001540 = nv_rd32(priv, 0x001540);
-	u32 r00154c = nv_rd32(priv, 0x00154c);
-	u64 disable = 0ULL;
-
-	if (!(r001540 & 0x40000000)) {
-		disable |= (1ULL << NVDEV_ENGINE_MPEG);
-		disable |= (1ULL << NVDEV_ENGINE_VP);
-		disable |= (1ULL << NVDEV_ENGINE_BSP);
-		disable |= (1ULL << NVDEV_ENGINE_CRYPT);
-	}
-
-	if (!(r00154c & 0x00000004))
-		disable |= (1ULL << NVDEV_ENGINE_DISP);
-	if (!(r00154c & 0x00000020))
-		disable |= (1ULL << NVDEV_ENGINE_BSP);
-	if (!(r00154c & 0x00000040))
-		disable |= (1ULL << NVDEV_ENGINE_CRYPT);
-
-	return disable;
-}
-
-struct nouveau_oclass *
-nv84_devinit_oclass = &(struct nouveau_devinit_impl) {
-	.base.handle = NV_SUBDEV(DEVINIT, 0x84),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_devinit_ctor,
-		.dtor = _nouveau_devinit_dtor,
-		.init = nv50_devinit_init,
-		.fini = _nouveau_devinit_fini,
-	},
-	.pll_set = nv50_devinit_pll_set,
-	.disable = nv84_devinit_disable,
-	.post = nvbios_init,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv98.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv98.c
deleted file mode 100644
index a773253a17f6..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv98.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv50.h"
-
-static u64
-nv98_devinit_disable(struct nouveau_devinit *devinit)
-{
-	struct nv50_devinit_priv *priv = (void *)devinit;
-	u32 r001540 = nv_rd32(priv, 0x001540);
-	u32 r00154c = nv_rd32(priv, 0x00154c);
-	u64 disable = 0ULL;
-
-	if (!(r001540 & 0x40000000)) {
-		disable |= (1ULL << NVDEV_ENGINE_VP);
-		disable |= (1ULL << NVDEV_ENGINE_BSP);
-		disable |= (1ULL << NVDEV_ENGINE_PPP);
-	}
-
-	if (!(r00154c & 0x00000004))
-		disable |= (1ULL << NVDEV_ENGINE_DISP);
-	if (!(r00154c & 0x00000020))
-		disable |= (1ULL << NVDEV_ENGINE_BSP);
-	if (!(r00154c & 0x00000040))
-		disable |= (1ULL << NVDEV_ENGINE_CRYPT);
-
-	return disable;
-}
-
-struct nouveau_oclass *
-nv98_devinit_oclass = &(struct nouveau_devinit_impl) {
-	.base.handle = NV_SUBDEV(DEVINIT, 0x98),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_devinit_ctor,
-		.dtor = _nouveau_devinit_dtor,
-		.init = nv50_devinit_init,
-		.fini = _nouveau_devinit_fini,
-	},
-	.pll_set = nv50_devinit_pll_set,
-	.disable = nv98_devinit_disable,
-	.post = nvbios_init,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c
deleted file mode 100644
index b9cd9e53f760..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv50.h"
-
-int
-nva3_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
-{
-	struct nv50_devinit_priv *priv = (void *)devinit;
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	struct nvbios_pll info;
-	int N, fN, M, P;
-	int ret;
-
-	ret = nvbios_pll_parse(bios, type, &info);
-	if (ret)
-		return ret;
-
-	ret = nva3_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P);
-	if (ret < 0)
-		return ret;
-
-	switch (info.type) {
-	case PLL_VPLL0:
-	case PLL_VPLL1:
-		nv_wr32(priv, info.reg + 0, 0x50000610);
-		nv_mask(priv, info.reg + 4, 0x003fffff,
-					    (P << 16) | (M << 8) | N);
-		nv_wr32(priv, info.reg + 8, fN);
-		break;
-	default:
-		nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq);
-		ret = -EINVAL;
-		break;
-	}
-
-	return ret;
-}
-
-static u64
-nva3_devinit_disable(struct nouveau_devinit *devinit)
-{
-	struct nv50_devinit_priv *priv = (void *)devinit;
-	u32 r001540 = nv_rd32(priv, 0x001540);
-	u32 r00154c = nv_rd32(priv, 0x00154c);
-	u64 disable = 0ULL;
-
-	if (!(r001540 & 0x40000000)) {
-		disable |= (1ULL << NVDEV_ENGINE_VP);
-		disable |= (1ULL << NVDEV_ENGINE_PPP);
-	}
-
-	if (!(r00154c & 0x00000004))
-		disable |= (1ULL << NVDEV_ENGINE_DISP);
-	if (!(r00154c & 0x00000020))
-		disable |= (1ULL << NVDEV_ENGINE_BSP);
-	if (!(r00154c & 0x00000200))
-		disable |= (1ULL << NVDEV_ENGINE_COPY0);
-
-	return disable;
-}
-
-static u32
-nva3_devinit_mmio_part[] = {
-	0x100720, 0x1008bc, 4,
-	0x100a20, 0x100adc, 4,
-	0x100d80, 0x100ddc, 4,
-	0x110000, 0x110f9c, 4,
-	0x111000, 0x11103c, 8,
-	0x111080, 0x1110fc, 4,
-	0x111120, 0x1111fc, 4,
-	0x111300, 0x1114bc, 4,
-	0,
-};
-
-static u32
-nva3_devinit_mmio(struct nouveau_devinit *devinit, u32 addr)
-{
-	struct nv50_devinit_priv *priv = (void *)devinit;
-	u32 *mmio = nva3_devinit_mmio_part;
-
-	/* the init tables on some boards have INIT_RAM_RESTRICT_ZM_REG_GROUP
-	 * instructions which touch registers that may not even exist on
-	 * some configurations (Quadro 400), which causes the register
-	 * interface to screw up for some amount of time after attempting to
-	 * write to one of these, and results in all sorts of things going
-	 * horribly wrong.
-	 *
-	 * the binary driver avoids touching these registers at all, however,
-	 * the video bios doesn't care and does what the scripts say.  it's
-	 * presumed that the io-port access to priv registers isn't effected
-	 * by the screw-up bug mentioned above.
-	 *
-	 * really, a new opcode should've been invented to handle these
-	 * requirements, but whatever, it's too late for that now.
-	 */
-	while (mmio[0]) {
-		if (addr >= mmio[0] && addr <= mmio[1]) {
-			u32 part = (addr / mmio[2]) & 7;
-			if (!priv->r001540)
-				priv->r001540 = nv_rd32(priv, 0x001540);
-			if (part >= hweight8((priv->r001540 >> 16) & 0xff))
-				return ~0;
-			return addr;
-		}
-		mmio += 3;
-	}
-
-	return addr;
-}
-
-struct nouveau_oclass *
-nva3_devinit_oclass = &(struct nouveau_devinit_impl) {
-	.base.handle = NV_SUBDEV(DEVINIT, 0xa3),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_devinit_ctor,
-		.dtor = _nouveau_devinit_dtor,
-		.init = nv50_devinit_init,
-		.fini = _nouveau_devinit_fini,
-	},
-	.pll_set = nva3_devinit_pll_set,
-	.disable = nva3_devinit_disable,
-	.mmio    = nva3_devinit_mmio,
-	.post = nvbios_init,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvaf.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nvaf.c
deleted file mode 100644
index 3729846a8e5c..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvaf.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv50.h"
-
-static u64
-nvaf_devinit_disable(struct nouveau_devinit *devinit)
-{
-	struct nv50_devinit_priv *priv = (void *)devinit;
-	u32 r001540 = nv_rd32(priv, 0x001540);
-	u32 r00154c = nv_rd32(priv, 0x00154c);
-	u64 disable = 0;
-
-	if (!(r001540 & 0x40000000)) {
-		disable |= (1ULL << NVDEV_ENGINE_VP);
-		disable |= (1ULL << NVDEV_ENGINE_PPP);
-	}
-
-	if (!(r00154c & 0x00000004))
-		disable |= (1ULL << NVDEV_ENGINE_DISP);
-	if (!(r00154c & 0x00000020))
-		disable |= (1ULL << NVDEV_ENGINE_BSP);
-	if (!(r00154c & 0x00000040))
-		disable |= (1ULL << NVDEV_ENGINE_VIC);
-	if (!(r00154c & 0x00000200))
-		disable |= (1ULL << NVDEV_ENGINE_COPY0);
-
-	return disable;
-}
-
-struct nouveau_oclass *
-nvaf_devinit_oclass = &(struct nouveau_devinit_impl) {
-	.base.handle = NV_SUBDEV(DEVINIT, 0xaf),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_devinit_ctor,
-		.dtor = _nouveau_devinit_dtor,
-		.init = nv50_devinit_init,
-		.fini = _nouveau_devinit_fini,
-	},
-	.pll_set = nva3_devinit_pll_set,
-	.disable = nvaf_devinit_disable,
-	.post = nvbios_init,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c
deleted file mode 100644
index 80bd7f5eda3d..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv50.h"
-
-int
-nvc0_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
-{
-	struct nv50_devinit_priv *priv = (void *)devinit;
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	struct nvbios_pll info;
-	int N, fN, M, P;
-	int ret;
-
-	ret = nvbios_pll_parse(bios, type, &info);
-	if (ret)
-		return ret;
-
-	ret = nva3_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P);
-	if (ret < 0)
-		return ret;
-
-	switch (info.type) {
-	case PLL_VPLL0:
-	case PLL_VPLL1:
-	case PLL_VPLL2:
-	case PLL_VPLL3:
-		nv_mask(priv, info.reg + 0x0c, 0x00000000, 0x00000100);
-		nv_wr32(priv, info.reg + 0x04, (P << 16) | (N << 8) | M);
-		nv_wr32(priv, info.reg + 0x10, fN << 16);
-		break;
-	default:
-		nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq);
-		ret = -EINVAL;
-		break;
-	}
-
-	return ret;
-}
-
-static u64
-nvc0_devinit_disable(struct nouveau_devinit *devinit)
-{
-	struct nv50_devinit_priv *priv = (void *)devinit;
-	u32 r022500 = nv_rd32(priv, 0x022500);
-	u64 disable = 0ULL;
-
-	if (r022500 & 0x00000001)
-		disable |= (1ULL << NVDEV_ENGINE_DISP);
-
-	if (r022500 & 0x00000002) {
-		disable |= (1ULL << NVDEV_ENGINE_VP);
-		disable |= (1ULL << NVDEV_ENGINE_PPP);
-	}
-
-	if (r022500 & 0x00000004)
-		disable |= (1ULL << NVDEV_ENGINE_BSP);
-	if (r022500 & 0x00000008)
-		disable |= (1ULL << NVDEV_ENGINE_VENC);
-	if (r022500 & 0x00000100)
-		disable |= (1ULL << NVDEV_ENGINE_COPY0);
-	if (r022500 & 0x00000200)
-		disable |= (1ULL << NVDEV_ENGINE_COPY1);
-
-	return disable;
-}
-
-static int
-nvc0_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 size,
-		  struct nouveau_object **pobject)
-{
-	struct nv50_devinit_priv *priv;
-	int ret;
-
-	ret = nouveau_devinit_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	if (nv_rd32(priv, 0x022500) & 0x00000001)
-		priv->base.post = true;
-	return 0;
-}
-
-struct nouveau_oclass *
-nvc0_devinit_oclass = &(struct nouveau_devinit_impl) {
-	.base.handle = NV_SUBDEV(DEVINIT, 0xc0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_devinit_ctor,
-		.dtor = _nouveau_devinit_dtor,
-		.init = nv50_devinit_init,
-		.fini = _nouveau_devinit_fini,
-	},
-	.pll_set = nvc0_devinit_pll_set,
-	.disable = nvc0_devinit_disable,
-	.post = nvbios_init,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h
deleted file mode 100644
index cbcd51852472..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h
+++ /dev/null
@@ -1,40 +0,0 @@
-#ifndef __NVKM_DEVINIT_PRIV_H__
-#define __NVKM_DEVINIT_PRIV_H__
-
-#include <subdev/bios.h>
-#include <subdev/bios/pll.h>
-#include <subdev/bios/init.h>
-#include <subdev/clock/pll.h>
-#include <subdev/devinit.h>
-
-struct nouveau_devinit_impl {
-	struct nouveau_oclass base;
-	void (*meminit)(struct nouveau_devinit *);
-	int  (*pll_set)(struct nouveau_devinit *, u32 type, u32 freq);
-	u64  (*disable)(struct nouveau_devinit *);
-	u32  (*mmio)(struct nouveau_devinit *, u32);
-	int  (*post)(struct nouveau_subdev *, bool);
-};
-
-#define nouveau_devinit_create(p,e,o,d)                                        \
-	nouveau_devinit_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_devinit_destroy(p) ({                                          \
-	struct nouveau_devinit *d = (p);                                       \
-	_nouveau_devinit_dtor(nv_object(d));                                   \
-})
-#define nouveau_devinit_init(p) ({                                             \
-	struct nouveau_devinit *d = (p);                                       \
-	_nouveau_devinit_init(nv_object(d));                                   \
-})
-#define nouveau_devinit_fini(p,s) ({                                           \
-	struct nouveau_devinit *d = (p);                                       \
-	_nouveau_devinit_fini(nv_object(d), (s));                              \
-})
-
-int nouveau_devinit_create_(struct nouveau_object *, struct nouveau_object *,
-			    struct nouveau_oclass *, int, void **);
-void _nouveau_devinit_dtor(struct nouveau_object *);
-int _nouveau_devinit_init(struct nouveau_object *);
-int _nouveau_devinit_fini(struct nouveau_object *, bool suspend);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/base.c b/drivers/gpu/drm/nouveau/core/subdev/fb/base.c
deleted file mode 100644
index c866148c440f..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/base.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/M0203.h>
-
-#include "priv.h"
-
-int
-nouveau_fb_bios_memtype(struct nouveau_bios *bios)
-{
-	const u8 ramcfg = (nv_rd32(bios, 0x101000) & 0x0000003c) >> 2;
-	struct nvbios_M0203E M0203E;
-	u8 ver, hdr;
-
-	if (nvbios_M0203Em(bios, ramcfg, &ver, &hdr, &M0203E)) {
-		switch (M0203E.type) {
-		case M0203E_TYPE_DDR2 : return NV_MEM_TYPE_DDR2;
-		case M0203E_TYPE_DDR3 : return NV_MEM_TYPE_DDR3;
-		case M0203E_TYPE_GDDR3: return NV_MEM_TYPE_GDDR3;
-		case M0203E_TYPE_GDDR5: return NV_MEM_TYPE_GDDR5;
-		default:
-			nv_warn(bios, "M0203E type %02x\n", M0203E.type);
-			return NV_MEM_TYPE_UNKNOWN;
-		}
-	}
-
-	nv_warn(bios, "M0203E not matched!\n");
-	return NV_MEM_TYPE_UNKNOWN;
-}
-
-int
-_nouveau_fb_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nouveau_fb *pfb = (void *)object;
-	int ret;
-
-	ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend);
-	if (ret && suspend)
-		return ret;
-
-	return nouveau_subdev_fini(&pfb->base, suspend);
-}
-
-int
-_nouveau_fb_init(struct nouveau_object *object)
-{
-	struct nouveau_fb *pfb = (void *)object;
-	int ret, i;
-
-	ret = nouveau_subdev_init(&pfb->base);
-	if (ret)
-		return ret;
-
-	ret = nv_ofuncs(pfb->ram)->init(nv_object(pfb->ram));
-	if (ret)
-		return ret;
-
-	for (i = 0; i < pfb->tile.regions; i++)
-		pfb->tile.prog(pfb, i, &pfb->tile.region[i]);
-
-	return 0;
-}
-
-void
-_nouveau_fb_dtor(struct nouveau_object *object)
-{
-	struct nouveau_fb *pfb = (void *)object;
-	int i;
-
-	for (i = 0; i < pfb->tile.regions; i++)
-		pfb->tile.fini(pfb, i, &pfb->tile.region[i]);
-	nouveau_mm_fini(&pfb->tags);
-	nouveau_mm_fini(&pfb->vram);
-
-	nouveau_object_ref(NULL, (struct nouveau_object **)&pfb->ram);
-	nouveau_subdev_destroy(&pfb->base);
-}
-
-int
-nouveau_fb_create_(struct nouveau_object *parent, struct nouveau_object *engine,
-		   struct nouveau_oclass *oclass, int length, void **pobject)
-{
-	struct nouveau_fb_impl *impl = (void *)oclass;
-	static const char *name[] = {
-		[NV_MEM_TYPE_UNKNOWN] = "unknown",
-		[NV_MEM_TYPE_STOLEN ] = "stolen system memory",
-		[NV_MEM_TYPE_SGRAM  ] = "SGRAM",
-		[NV_MEM_TYPE_SDRAM  ] = "SDRAM",
-		[NV_MEM_TYPE_DDR1   ] = "DDR1",
-		[NV_MEM_TYPE_DDR2   ] = "DDR2",
-		[NV_MEM_TYPE_DDR3   ] = "DDR3",
-		[NV_MEM_TYPE_GDDR2  ] = "GDDR2",
-		[NV_MEM_TYPE_GDDR3  ] = "GDDR3",
-		[NV_MEM_TYPE_GDDR4  ] = "GDDR4",
-		[NV_MEM_TYPE_GDDR5  ] = "GDDR5",
-	};
-	struct nouveau_object *ram;
-	struct nouveau_fb *pfb;
-	int ret;
-
-	ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PFB", "fb",
-				     length, pobject);
-	pfb = *pobject;
-	if (ret)
-		return ret;
-
-	pfb->memtype_valid = impl->memtype;
-
-	ret = nouveau_object_ctor(nv_object(pfb), nv_object(pfb),
-				  impl->ram, NULL, 0, &ram);
-	if (ret) {
-		nv_fatal(pfb, "error detecting memory configuration!!\n");
-		return ret;
-	}
-
-	atomic_dec(&ram->parent->refcount);
-	atomic_dec(&ram->engine->refcount);
-	pfb->ram = (void *)ram;
-
-	if (!nouveau_mm_initialised(&pfb->vram)) {
-		ret = nouveau_mm_init(&pfb->vram, 0, pfb->ram->size >> 12, 1);
-		if (ret)
-			return ret;
-	}
-
-	if (!nouveau_mm_initialised(&pfb->tags)) {
-		ret = nouveau_mm_init(&pfb->tags, 0, pfb->ram->tags ?
-				     ++pfb->ram->tags : 0, 1);
-		if (ret)
-			return ret;
-	}
-
-	nv_info(pfb, "RAM type: %s\n", name[pfb->ram->type]);
-	nv_info(pfb, "RAM size: %d MiB\n", (int)(pfb->ram->size >> 20));
-	nv_info(pfb, "   ZCOMP: %d tags\n", pfb->ram->tags);
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/gddr3.c
deleted file mode 100644
index d85a25d027ee..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr3.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- * 	    Roy Spliet <rspliet@eclipso.eu>
- */
-
-#include <subdev/bios.h>
-#include "priv.h"
-
-struct ramxlat {
-	int id;
-	u8 enc;
-};
-
-static inline int
-ramxlat(const struct ramxlat *xlat, int id)
-{
-	while (xlat->id >= 0) {
-		if (xlat->id == id)
-			return xlat->enc;
-		xlat++;
-	}
-	return -EINVAL;
-}
-
-static const struct ramxlat
-ramgddr3_cl_lo[] = {
-	{ 7, 7 }, { 8, 0 }, { 9, 1 }, { 10, 2 }, { 11, 3 },
-	/* the below are mentioned in some, but not all, gddr3 docs */
-	{ 12, 4 }, { 13, 5 }, { 14, 6 },
-	/* XXX: Per Samsung docs, are these used? They overlap with Qimonda */
-	/* { 4, 4 }, { 5, 5 }, { 6, 6 }, { 12, 8 }, { 13, 9 }, { 14, 10 },
-	 * { 15, 11 }, */
-	{ -1 }
-};
-
-static const struct ramxlat
-ramgddr3_cl_hi[] = {
-	{ 10, 2 }, { 11, 3 }, { 12, 4 }, { 13, 5 }, { 14, 6 }, { 15, 7 },
-	{ 16, 0 }, { 17, 1 },
-	{ -1 }
-};
-
-static const struct ramxlat
-ramgddr3_wr_lo[] = {
-	{ 5, 2 }, { 7, 4 }, { 8, 5 }, { 9, 6 }, { 10, 7 },
-	{ 11, 0 },
-	/* the below are mentioned in some, but not all, gddr3 docs */
-	{ 4, 1 }, { 6, 3 }, { 12, 1 }, { 13 , 2 },
-	{ -1 }
-};
-
-int
-nouveau_gddr3_calc(struct nouveau_ram *ram)
-{
-	int CL, WR, CWL, DLL = 0, ODT = 0, hi;
-
-	switch (ram->next->bios.timing_ver) {
-	case 0x10:
-		CWL = ram->next->bios.timing_10_CWL;
-		CL  = ram->next->bios.timing_10_CL;
-		WR  = ram->next->bios.timing_10_WR;
-		DLL = !ram->next->bios.ramcfg_10_DLLoff;
-		ODT = ram->next->bios.timing_10_ODT;
-		break;
-	case 0x20:
-		CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
-		CL  = (ram->next->bios.timing[1] & 0x0000001f) >> 0;
-		WR  = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
-		/* XXX: Get these values from the VBIOS instead */
-		DLL = !(ram->mr[1] & 0x1);
-		ODT =  (ram->mr[1] & 0x004) >> 2 |
-		       (ram->mr[1] & 0x040) >> 5 |
-		       (ram->mr[1] & 0x200) >> 7;
-		break;
-	default:
-		return -ENOSYS;
-	}
-
-	hi = ram->mr[2] & 0x1;
-	CL  = ramxlat(hi ? ramgddr3_cl_hi : ramgddr3_cl_lo, CL);
-	WR  = ramxlat(ramgddr3_wr_lo, WR);
-	if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0)
-		return -EINVAL;
-
-	ram->mr[0] &= ~0xf74;
-	ram->mr[0] |= (CWL & 0x07) << 9;
-	ram->mr[0] |= (CL & 0x07) << 4;
-	ram->mr[0] |= (CL & 0x08) >> 1;
-
-	ram->mr[1] &= ~0x3fc;
-	ram->mr[1] |= (ODT & 0x03) << 2;
-	ram->mr[1] |= (ODT & 0x03) << 8;
-	ram->mr[1] |= (WR  & 0x03) << 4;
-	ram->mr[1] |= (WR  & 0x04) << 5;
-	ram->mr[1] |= !DLL << 6;
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c b/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c
deleted file mode 100644
index 7fbbe05d5c60..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include <subdev/bios.h>
-#include "priv.h"
-
-/* binary driver only executes this path if the condition (a) is true
- * for any configuration (combination of rammap+ramcfg+timing) that
- * can be reached on a given card.  for now, we will execute the branch
- * unconditionally in the hope that a "false everywhere" in the bios
- * tables doesn't actually mean "don't touch this".
- */
-#define NOTE00(a) 1
-
-int
-nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts)
-{
-	int pd, lf, xd, vh, vr, vo, l3;
-	int WL, CL, WR, at[2], dt, ds;
-	int rq = ram->freq < 1000000; /* XXX */
-
-	switch (ram->next->bios.ramcfg_ver) {
-	case 0x11:
-		pd =  ram->next->bios.ramcfg_11_01_80;
-		lf =  ram->next->bios.ramcfg_11_01_40;
-		xd = !ram->next->bios.ramcfg_11_01_20;
-		vh =  ram->next->bios.ramcfg_11_02_10;
-		vr =  ram->next->bios.ramcfg_11_02_04;
-		vo =  ram->next->bios.ramcfg_11_06;
-		l3 = !ram->next->bios.ramcfg_11_07_02;
-		break;
-	default:
-		return -ENOSYS;
-	}
-
-	switch (ram->next->bios.timing_ver) {
-	case 0x20:
-		WL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
-		CL = (ram->next->bios.timing[1] & 0x0000001f);
-		WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
-		at[0] = ram->next->bios.timing_20_2e_c0;
-		at[1] = ram->next->bios.timing_20_2e_30;
-		dt =  ram->next->bios.timing_20_2e_03;
-		ds =  ram->next->bios.timing_20_2f_03;
-		break;
-	default:
-		return -ENOSYS;
-	}
-
-	if (WL < 1 || WL > 7 || CL < 5 || CL > 36 || WR < 4 || WR > 35)
-		return -EINVAL;
-	CL -= 5;
-	WR -= 4;
-
-	ram->mr[0] &= ~0xf7f;
-	ram->mr[0] |= (WR & 0x0f) << 8;
-	ram->mr[0] |= (CL & 0x0f) << 3;
-	ram->mr[0] |= (WL & 0x07) << 0;
-
-	ram->mr[1] &= ~0x0bf;
-	ram->mr[1] |= (xd & 0x01) << 7;
-	ram->mr[1] |= (at[0] & 0x03) << 4;
-	ram->mr[1] |= (dt & 0x03) << 2;
-	ram->mr[1] |= (ds & 0x03) << 0;
-
-	/* this seems wrong, alternate field used for the broadcast
-	 * on nuts vs non-nuts configs..  meh, it matches for now.
-	 */
-	ram->mr1_nuts = ram->mr[1];
-	if (nuts) {
-		ram->mr[1] &= ~0x030;
-		ram->mr[1] |= (at[1] & 0x03) << 4;
-	}
-
-	ram->mr[3] &= ~0x020;
-	ram->mr[3] |= (rq & 0x01) << 5;
-
-	ram->mr[5] &= ~0x004;
-	ram->mr[5] |= (l3 << 2);
-
-	if (!vo)
-		vo = (ram->mr[6] & 0xff0) >> 4;
-	if (ram->mr[6] & 0x001)
-		pd = 1; /* binary driver does this.. bug? */
-	ram->mr[6] &= ~0xff1;
-	ram->mr[6] |= (vo & 0xff) << 4;
-	ram->mr[6] |= (pd & 0x01) << 0;
-
-	if (NOTE00(vr)) {
-		ram->mr[7] &= ~0x300;
-		ram->mr[7] |= (vr & 0x03) << 8;
-	}
-	ram->mr[7] &= ~0x088;
-	ram->mr[7] |= (vh & 0x01) << 7;
-	ram->mr[7] |= (lf & 0x01) << 3;
-
-	ram->mr[8] &= ~0x003;
-	ram->mr[8] |= (WR & 0x10) >> 3;
-	ram->mr[8] |= (CL & 0x10) >> 4;
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/fb/gk20a.c
deleted file mode 100644
index fde42e4d1b56..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/gk20a.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include "nvc0.h"
-
-struct gk20a_fb_priv {
-	struct nouveau_fb base;
-};
-
-static int
-gk20a_fb_init(struct nouveau_object *object)
-{
-	struct gk20a_fb_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_fb_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_mask(priv, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */
-	return 0;
-}
-
-static int
-gk20a_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	     struct nouveau_oclass *oclass, void *data, u32 size,
-	     struct nouveau_object **pobject)
-{
-	struct gk20a_fb_priv *priv;
-	int ret;
-
-	ret = nouveau_fb_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-struct nouveau_oclass *
-gk20a_fb_oclass = &(struct nouveau_fb_impl) {
-	.base.handle = NV_SUBDEV(FB, 0xea),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = gk20a_fb_ctor,
-		.dtor = _nouveau_fb_dtor,
-		.init = gk20a_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.memtype = nvc0_fb_memtype_valid,
-	.ram = &gk20a_ram_oclass,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gm107.c b/drivers/gpu/drm/nouveau/core/subdev/fb/gm107.c
deleted file mode 100644
index c4840aedc2dc..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/gm107.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nvc0.h"
-
-struct nouveau_oclass *
-gm107_fb_oclass = &(struct nouveau_fb_impl) {
-	.base.handle = NV_SUBDEV(FB, 0x07),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_fb_ctor,
-		.dtor = nvc0_fb_dtor,
-		.init = nvc0_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.memtype = nvc0_fb_memtype_valid,
-	.ram = &gm107_ram_oclass,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.c
deleted file mode 100644
index 8309fe33fe84..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv04.h"
-
-#define NV04_PFB_CFG0						0x00100200
-
-bool
-nv04_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags)
-{
-	if (!(tile_flags & 0xff00))
-		return true;
-
-	return false;
-}
-
-static int
-nv04_fb_init(struct nouveau_object *object)
-{
-	struct nv04_fb_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_fb_init(&priv->base);
-	if (ret)
-		return ret;
-
-	/* This is what the DDX did for NV_ARCH_04, but a mmio-trace shows
-	 * nvidia reading PFB_CFG_0, then writing back its original value.
-	 * (which was 0x701114 in this case)
-	 */
-	nv_wr32(priv, NV04_PFB_CFG0, 0x1114);
-	return 0;
-}
-
-int
-nv04_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	     struct nouveau_oclass *oclass, void *data, u32 size,
-	     struct nouveau_object **pobject)
-{
-	struct nv04_fb_impl *impl = (void *)oclass;
-	struct nv04_fb_priv *priv;
-	int ret;
-
-	ret = nouveau_fb_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.tile.regions = impl->tile.regions;
-	priv->base.tile.init = impl->tile.init;
-	priv->base.tile.comp = impl->tile.comp;
-	priv->base.tile.fini = impl->tile.fini;
-	priv->base.tile.prog = impl->tile.prog;
-	return 0;
-}
-
-struct nouveau_oclass *
-nv04_fb_oclass = &(struct nv04_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0x04),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fb_ctor,
-		.dtor = _nouveau_fb_dtor,
-		.init = nv04_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv04_fb_memtype_valid,
-	.base.ram = &nv04_ram_oclass,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.h
deleted file mode 100644
index 06ce71f87a74..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef __NVKM_FB_NV04_H__
-#define __NVKM_FB_NV04_H__
-
-#include "priv.h"
-
-struct nv04_fb_priv {
-	struct nouveau_fb base;
-};
-
-int  nv04_fb_ctor(struct nouveau_object *, struct nouveau_object *,
-		  struct nouveau_oclass *, void *, u32,
-		  struct nouveau_object **);
-
-struct nv04_fb_impl {
-	struct nouveau_fb_impl base;
-	struct {
-		int regions;
-		void (*init)(struct nouveau_fb *, int i, u32 addr, u32 size,
-			     u32 pitch, u32 flags, struct nouveau_fb_tile *);
-		void (*comp)(struct nouveau_fb *, int i, u32 size, u32 flags,
-			     struct nouveau_fb_tile *);
-		void (*fini)(struct nouveau_fb *, int i,
-			     struct nouveau_fb_tile *);
-		void (*prog)(struct nouveau_fb *, int i,
-			     struct nouveau_fb_tile *);
-	} tile;
-};
-
-void nv10_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
-		       u32 pitch, u32 flags, struct nouveau_fb_tile *);
-void nv10_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *);
-void nv10_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
-
-void nv20_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
-		       u32 pitch, u32 flags, struct nouveau_fb_tile *);
-void nv20_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *);
-void nv20_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
-
-int  nv30_fb_init(struct nouveau_object *);
-void nv30_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
-		       u32 pitch, u32 flags, struct nouveau_fb_tile *);
-
-void nv40_fb_tile_comp(struct nouveau_fb *, int i, u32 size, u32 flags,
-		       struct nouveau_fb_tile *);
-
-int  nv41_fb_init(struct nouveau_object *);
-void nv41_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
-
-int  nv44_fb_init(struct nouveau_object *);
-void nv44_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
-
-void nv46_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
-		       u32 pitch, u32 flags, struct nouveau_fb_tile *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv10.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv10.c
deleted file mode 100644
index ffb7ec6d97aa..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv10.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "nv04.h"
-
-void
-nv10_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
-		  u32 flags, struct nouveau_fb_tile *tile)
-{
-	tile->addr  = 0x80000000 | addr;
-	tile->limit = max(1u, addr + size) - 1;
-	tile->pitch = pitch;
-}
-
-void
-nv10_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
-{
-	tile->addr  = 0;
-	tile->limit = 0;
-	tile->pitch = 0;
-	tile->zcomp = 0;
-}
-
-void
-nv10_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
-{
-	nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit);
-	nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch);
-	nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr);
-	nv_rd32(pfb, 0x100240 + (i * 0x10));
-}
-
-struct nouveau_oclass *
-nv10_fb_oclass = &(struct nv04_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0x10),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fb_ctor,
-		.dtor = _nouveau_fb_dtor,
-		.init = _nouveau_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv04_fb_memtype_valid,
-	.base.ram = &nv10_ram_oclass,
-	.tile.regions = 8,
-	.tile.init = nv10_fb_tile_init,
-	.tile.fini = nv10_fb_tile_fini,
-	.tile.prog = nv10_fb_tile_prog,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c
deleted file mode 100644
index 265d1253624a..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "nv04.h"
-
-struct nouveau_oclass *
-nv1a_fb_oclass = &(struct nv04_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0x1a),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fb_ctor,
-		.dtor = _nouveau_fb_dtor,
-		.init = _nouveau_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv04_fb_memtype_valid,
-	.base.ram = &nv1a_ram_oclass,
-	.tile.regions = 8,
-	.tile.init = nv10_fb_tile_init,
-	.tile.fini = nv10_fb_tile_fini,
-	.tile.prog = nv10_fb_tile_prog,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c
deleted file mode 100644
index 2209ade63339..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "nv04.h"
-
-void
-nv20_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
-		  u32 flags, struct nouveau_fb_tile *tile)
-{
-	tile->addr  = 0x00000001 | addr;
-	tile->limit = max(1u, addr + size) - 1;
-	tile->pitch = pitch;
-	if (flags & 4) {
-		pfb->tile.comp(pfb, i, size, flags, tile);
-		tile->addr |= 2;
-	}
-}
-
-static void
-nv20_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
-		  struct nouveau_fb_tile *tile)
-{
-	u32 tiles = DIV_ROUND_UP(size, 0x40);
-	u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
-	if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
-		if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */
-		else              tile->zcomp = 0x04000000; /* Z24S8 */
-		tile->zcomp |= tile->tag->offset;
-		tile->zcomp |= 0x80000000; /* enable */
-#ifdef __BIG_ENDIAN
-		tile->zcomp |= 0x08000000;
-#endif
-	}
-}
-
-void
-nv20_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
-{
-	tile->addr  = 0;
-	tile->limit = 0;
-	tile->pitch = 0;
-	tile->zcomp = 0;
-	nouveau_mm_free(&pfb->tags, &tile->tag);
-}
-
-void
-nv20_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
-{
-	nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit);
-	nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch);
-	nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr);
-	nv_rd32(pfb, 0x100240 + (i * 0x10));
-	nv_wr32(pfb, 0x100300 + (i * 0x04), tile->zcomp);
-}
-
-struct nouveau_oclass *
-nv20_fb_oclass = &(struct nv04_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0x20),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fb_ctor,
-		.dtor = _nouveau_fb_dtor,
-		.init = _nouveau_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv04_fb_memtype_valid,
-	.base.ram = &nv20_ram_oclass,
-	.tile.regions = 8,
-	.tile.init = nv20_fb_tile_init,
-	.tile.comp = nv20_fb_tile_comp,
-	.tile.fini = nv20_fb_tile_fini,
-	.tile.prog = nv20_fb_tile_prog,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c
deleted file mode 100644
index e2a66c355c50..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "nv04.h"
-
-static void
-nv25_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
-		  struct nouveau_fb_tile *tile)
-{
-	u32 tiles = DIV_ROUND_UP(size, 0x40);
-	u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
-	if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
-		if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */
-		else              tile->zcomp = 0x00200000; /* Z24S8 */
-		tile->zcomp |= tile->tag->offset;
-#ifdef __BIG_ENDIAN
-		tile->zcomp |= 0x01000000;
-#endif
-	}
-}
-
-struct nouveau_oclass *
-nv25_fb_oclass = &(struct nv04_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0x25),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fb_ctor,
-		.dtor = _nouveau_fb_dtor,
-		.init = _nouveau_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv04_fb_memtype_valid,
-	.base.ram = &nv20_ram_oclass,
-	.tile.regions = 8,
-	.tile.init = nv20_fb_tile_init,
-	.tile.comp = nv25_fb_tile_comp,
-	.tile.fini = nv20_fb_tile_fini,
-	.tile.prog = nv20_fb_tile_prog,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c
deleted file mode 100644
index cbec402ba5b9..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "nv04.h"
-
-void
-nv30_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
-		  u32 flags, struct nouveau_fb_tile *tile)
-{
-	/* for performance, select alternate bank offset for zeta */
-	if (!(flags & 4)) {
-		tile->addr = (0 << 4);
-	} else {
-		if (pfb->tile.comp) /* z compression */
-			pfb->tile.comp(pfb, i, size, flags, tile);
-		tile->addr = (1 << 4);
-	}
-
-	tile->addr |= 0x00000001; /* enable */
-	tile->addr |= addr;
-	tile->limit = max(1u, addr + size) - 1;
-	tile->pitch = pitch;
-}
-
-static void
-nv30_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
-		  struct nouveau_fb_tile *tile)
-{
-	u32 tiles = DIV_ROUND_UP(size, 0x40);
-	u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
-	if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
-		if (flags & 2) tile->zcomp |= 0x01000000; /* Z16 */
-		else           tile->zcomp |= 0x02000000; /* Z24S8 */
-		tile->zcomp |= ((tile->tag->offset           ) >> 6);
-		tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 12;
-#ifdef __BIG_ENDIAN
-		tile->zcomp |= 0x10000000;
-#endif
-	}
-}
-
-static int
-calc_bias(struct nv04_fb_priv *priv, int k, int i, int j)
-{
-	struct nouveau_device *device = nv_device(priv);
-	int b = (device->chipset > 0x30 ?
-		 nv_rd32(priv, 0x122c + 0x10 * k + 0x4 * j) >> (4 * (i ^ 1)) :
-		 0) & 0xf;
-
-	return 2 * (b & 0x8 ? b - 0x10 : b);
-}
-
-static int
-calc_ref(struct nv04_fb_priv *priv, int l, int k, int i)
-{
-	int j, x = 0;
-
-	for (j = 0; j < 4; j++) {
-		int m = (l >> (8 * i) & 0xff) + calc_bias(priv, k, i, j);
-
-		x |= (0x80 | clamp(m, 0, 0x1f)) << (8 * j);
-	}
-
-	return x;
-}
-
-int
-nv30_fb_init(struct nouveau_object *object)
-{
-	struct nouveau_device *device = nv_device(object);
-	struct nv04_fb_priv *priv = (void *)object;
-	int ret, i, j;
-
-	ret = nouveau_fb_init(&priv->base);
-	if (ret)
-		return ret;
-
-	/* Init the memory timing regs at 0x10037c/0x1003ac */
-	if (device->chipset == 0x30 ||
-	    device->chipset == 0x31 ||
-	    device->chipset == 0x35) {
-		/* Related to ROP count */
-		int n = (device->chipset == 0x31 ? 2 : 4);
-		int l = nv_rd32(priv, 0x1003d0);
-
-		for (i = 0; i < n; i++) {
-			for (j = 0; j < 3; j++)
-				nv_wr32(priv, 0x10037c + 0xc * i + 0x4 * j,
-					calc_ref(priv, l, 0, j));
-
-			for (j = 0; j < 2; j++)
-				nv_wr32(priv, 0x1003ac + 0x8 * i + 0x4 * j,
-					calc_ref(priv, l, 1, j));
-		}
-	}
-
-	return 0;
-}
-
-struct nouveau_oclass *
-nv30_fb_oclass = &(struct nv04_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0x30),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fb_ctor,
-		.dtor = _nouveau_fb_dtor,
-		.init = nv30_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv04_fb_memtype_valid,
-	.base.ram = &nv20_ram_oclass,
-	.tile.regions = 8,
-	.tile.init = nv30_fb_tile_init,
-	.tile.comp = nv30_fb_tile_comp,
-	.tile.fini = nv20_fb_tile_fini,
-	.tile.prog = nv20_fb_tile_prog,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c
deleted file mode 100644
index b2cf8c69fb2e..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "nv04.h"
-
-static void
-nv35_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
-		  struct nouveau_fb_tile *tile)
-{
-	u32 tiles = DIV_ROUND_UP(size, 0x40);
-	u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
-	if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
-		if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */
-		else           tile->zcomp |= 0x08000000; /* Z24S8 */
-		tile->zcomp |= ((tile->tag->offset           ) >> 6);
-		tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13;
-#ifdef __BIG_ENDIAN
-		tile->zcomp |= 0x40000000;
-#endif
-	}
-}
-
-struct nouveau_oclass *
-nv35_fb_oclass = &(struct nv04_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0x35),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fb_ctor,
-		.dtor = _nouveau_fb_dtor,
-		.init = nv30_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv04_fb_memtype_valid,
-	.base.ram = &nv20_ram_oclass,
-	.tile.regions = 8,
-	.tile.init = nv30_fb_tile_init,
-	.tile.comp = nv35_fb_tile_comp,
-	.tile.fini = nv20_fb_tile_fini,
-	.tile.prog = nv20_fb_tile_prog,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c
deleted file mode 100644
index b4cdae2a3b2f..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "nv04.h"
-
-static void
-nv36_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
-		  struct nouveau_fb_tile *tile)
-{
-	u32 tiles = DIV_ROUND_UP(size, 0x40);
-	u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
-	if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
-		if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */
-		else           tile->zcomp |= 0x20000000; /* Z24S8 */
-		tile->zcomp |= ((tile->tag->offset           ) >> 6);
-		tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14;
-#ifdef __BIG_ENDIAN
-		tile->zcomp |= 0x80000000;
-#endif
-	}
-}
-
-struct nouveau_oclass *
-nv36_fb_oclass = &(struct nv04_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0x36),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fb_ctor,
-		.dtor = _nouveau_fb_dtor,
-		.init = nv30_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv04_fb_memtype_valid,
-	.base.ram = &nv20_ram_oclass,
-	.tile.regions = 8,
-	.tile.init = nv30_fb_tile_init,
-	.tile.comp = nv36_fb_tile_comp,
-	.tile.fini = nv20_fb_tile_fini,
-	.tile.prog = nv20_fb_tile_prog,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c
deleted file mode 100644
index 52814258c212..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "nv04.h"
-
-void
-nv40_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
-		  struct nouveau_fb_tile *tile)
-{
-	u32 tiles = DIV_ROUND_UP(size, 0x80);
-	u32 tags  = round_up(tiles / pfb->ram->parts, 0x100);
-	if ( (flags & 2) &&
-	    !nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
-		tile->zcomp  = 0x28000000; /* Z24S8_SPLIT_GRAD */
-		tile->zcomp |= ((tile->tag->offset           ) >> 8);
-		tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13;
-#ifdef __BIG_ENDIAN
-		tile->zcomp |= 0x40000000;
-#endif
-	}
-}
-
-static int
-nv40_fb_init(struct nouveau_object *object)
-{
-	struct nv04_fb_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_fb_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_mask(priv, 0x10033c, 0x00008000, 0x00000000);
-	return 0;
-}
-
-struct nouveau_oclass *
-nv40_fb_oclass = &(struct nv04_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0x40),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fb_ctor,
-		.dtor = _nouveau_fb_dtor,
-		.init = nv40_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv04_fb_memtype_valid,
-	.base.ram = &nv40_ram_oclass,
-	.tile.regions = 8,
-	.tile.init = nv30_fb_tile_init,
-	.tile.comp = nv40_fb_tile_comp,
-	.tile.fini = nv20_fb_tile_fini,
-	.tile.prog = nv20_fb_tile_prog,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.h b/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.h
deleted file mode 100644
index 581f808527f2..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef __NVKM_FB_NV40_H__
-#define __NVKM_FB_NV40_H__
-
-#include "priv.h"
-
-struct nv40_ram {
-	struct nouveau_ram base;
-	u32 ctrl;
-	u32 coef;
-};
-
-
-int  nv40_ram_calc(struct nouveau_fb *, u32);
-int  nv40_ram_prog(struct nouveau_fb *);
-void nv40_ram_tidy(struct nouveau_fb *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c
deleted file mode 100644
index b239a8615599..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "nv04.h"
-
-void
-nv41_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
-{
-	nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit);
-	nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch);
-	nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr);
-	nv_rd32(pfb, 0x100600 + (i * 0x10));
-	nv_wr32(pfb, 0x100700 + (i * 0x04), tile->zcomp);
-}
-
-int
-nv41_fb_init(struct nouveau_object *object)
-{
-	struct nv04_fb_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_fb_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x100800, 0x00000001);
-	return 0;
-}
-
-struct nouveau_oclass *
-nv41_fb_oclass = &(struct nv04_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0x41),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fb_ctor,
-		.dtor = _nouveau_fb_dtor,
-		.init = nv41_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv04_fb_memtype_valid,
-	.base.ram = &nv41_ram_oclass,
-	.tile.regions = 12,
-	.tile.init = nv30_fb_tile_init,
-	.tile.comp = nv40_fb_tile_comp,
-	.tile.fini = nv20_fb_tile_fini,
-	.tile.prog = nv41_fb_tile_prog,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv44.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv44.c
deleted file mode 100644
index d8478208a681..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv44.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "nv04.h"
-
-static void
-nv44_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
-		  u32 flags, struct nouveau_fb_tile *tile)
-{
-	tile->addr  = 0x00000001; /* mode = vram */
-	tile->addr |= addr;
-	tile->limit = max(1u, addr + size) - 1;
-	tile->pitch = pitch;
-}
-
-void
-nv44_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
-{
-	nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit);
-	nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch);
-	nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr);
-	nv_rd32(pfb, 0x100600 + (i * 0x10));
-}
-
-int
-nv44_fb_init(struct nouveau_object *object)
-{
-	struct nv04_fb_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_fb_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x100850, 0x80000000);
-	nv_wr32(priv, 0x100800, 0x00000001);
-	return 0;
-}
-
-struct nouveau_oclass *
-nv44_fb_oclass = &(struct nv04_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0x44),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fb_ctor,
-		.dtor = _nouveau_fb_dtor,
-		.init = nv44_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv04_fb_memtype_valid,
-	.base.ram = &nv44_ram_oclass,
-	.tile.regions = 12,
-	.tile.init = nv44_fb_tile_init,
-	.tile.fini = nv20_fb_tile_fini,
-	.tile.prog = nv44_fb_tile_prog,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv46.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv46.c
deleted file mode 100644
index a5b77514d35b..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv46.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "nv04.h"
-
-void
-nv46_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
-		  u32 flags, struct nouveau_fb_tile *tile)
-{
-	/* for performance, select alternate bank offset for zeta */
-	if (!(flags & 4)) tile->addr = (0 << 3);
-	else              tile->addr = (1 << 3);
-
-	tile->addr |= 0x00000001; /* mode = vram */
-	tile->addr |= addr;
-	tile->limit = max(1u, addr + size) - 1;
-	tile->pitch = pitch;
-}
-
-struct nouveau_oclass *
-nv46_fb_oclass = &(struct nv04_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0x46),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fb_ctor,
-		.dtor = _nouveau_fb_dtor,
-		.init = nv44_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv04_fb_memtype_valid,
-	.base.ram = &nv44_ram_oclass,
-	.tile.regions = 15,
-	.tile.init = nv46_fb_tile_init,
-	.tile.fini = nv20_fb_tile_fini,
-	.tile.prog = nv44_fb_tile_prog,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c
deleted file mode 100644
index 3bea142376bc..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "nv04.h"
-
-struct nouveau_oclass *
-nv47_fb_oclass = &(struct nv04_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0x47),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fb_ctor,
-		.dtor = _nouveau_fb_dtor,
-		.init = nv41_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv04_fb_memtype_valid,
-	.base.ram = &nv41_ram_oclass,
-	.tile.regions = 15,
-	.tile.init = nv30_fb_tile_init,
-	.tile.comp = nv40_fb_tile_comp,
-	.tile.fini = nv20_fb_tile_fini,
-	.tile.prog = nv41_fb_tile_prog,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c
deleted file mode 100644
index 666cbd5d47f5..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "nv04.h"
-
-struct nouveau_oclass *
-nv49_fb_oclass = &(struct nv04_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0x49),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fb_ctor,
-		.dtor = _nouveau_fb_dtor,
-		.init = nv41_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv04_fb_memtype_valid,
-	.base.ram = &nv49_ram_oclass,
-	.tile.regions = 15,
-	.tile.init = nv30_fb_tile_init,
-	.tile.comp = nv40_fb_tile_comp,
-	.tile.fini = nv20_fb_tile_fini,
-	.tile.prog = nv41_fb_tile_prog,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv4e.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv4e.c
deleted file mode 100644
index 42e64f364ec1..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv4e.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (C) 2010 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "nv04.h"
-
-struct nouveau_oclass *
-nv4e_fb_oclass = &(struct nv04_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0x4e),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_fb_ctor,
-		.dtor = _nouveau_fb_dtor,
-		.init = nv44_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv04_fb_memtype_valid,
-	.base.ram = &nv4e_ram_oclass,
-	.tile.regions = 12,
-	.tile.init = nv46_fb_tile_init,
-	.tile.fini = nv20_fb_tile_fini,
-	.tile.prog = nv44_fb_tile_prog,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
deleted file mode 100644
index 4150b0d10af8..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <core/enum.h>
-#include <core/engctx.h>
-#include <core/object.h>
-
-#include <subdev/bios.h>
-
-#include "nv50.h"
-
-int
-nv50_fb_memtype[0x80] = {
-	1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	1, 1, 1, 1, 0, 0, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0,
-	1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 2, 2, 2, 2, 2, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 0, 0,
-	0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 2, 2, 2, 2,
-	1, 0, 2, 0, 1, 0, 2, 0, 1, 1, 2, 2, 1, 1, 0, 0
-};
-
-bool
-nv50_fb_memtype_valid(struct nouveau_fb *pfb, u32 memtype)
-{
-	return nv50_fb_memtype[(memtype & 0xff00) >> 8] != 0;
-}
-
-static const struct nouveau_enum vm_dispatch_subclients[] = {
-	{ 0x00000000, "GRCTX", NULL },
-	{ 0x00000001, "NOTIFY", NULL },
-	{ 0x00000002, "QUERY", NULL },
-	{ 0x00000003, "COND", NULL },
-	{ 0x00000004, "M2M_IN", NULL },
-	{ 0x00000005, "M2M_OUT", NULL },
-	{ 0x00000006, "M2M_NOTIFY", NULL },
-	{}
-};
-
-static const struct nouveau_enum vm_ccache_subclients[] = {
-	{ 0x00000000, "CB", NULL },
-	{ 0x00000001, "TIC", NULL },
-	{ 0x00000002, "TSC", NULL },
-	{}
-};
-
-static const struct nouveau_enum vm_prop_subclients[] = {
-	{ 0x00000000, "RT0", NULL },
-	{ 0x00000001, "RT1", NULL },
-	{ 0x00000002, "RT2", NULL },
-	{ 0x00000003, "RT3", NULL },
-	{ 0x00000004, "RT4", NULL },
-	{ 0x00000005, "RT5", NULL },
-	{ 0x00000006, "RT6", NULL },
-	{ 0x00000007, "RT7", NULL },
-	{ 0x00000008, "ZETA", NULL },
-	{ 0x00000009, "LOCAL", NULL },
-	{ 0x0000000a, "GLOBAL", NULL },
-	{ 0x0000000b, "STACK", NULL },
-	{ 0x0000000c, "DST2D", NULL },
-	{}
-};
-
-static const struct nouveau_enum vm_pfifo_subclients[] = {
-	{ 0x00000000, "PUSHBUF", NULL },
-	{ 0x00000001, "SEMAPHORE", NULL },
-	{}
-};
-
-static const struct nouveau_enum vm_bar_subclients[] = {
-	{ 0x00000000, "FB", NULL },
-	{ 0x00000001, "IN", NULL },
-	{}
-};
-
-static const struct nouveau_enum vm_client[] = {
-	{ 0x00000000, "STRMOUT", NULL },
-	{ 0x00000003, "DISPATCH", vm_dispatch_subclients },
-	{ 0x00000004, "PFIFO_WRITE", NULL },
-	{ 0x00000005, "CCACHE", vm_ccache_subclients },
-	{ 0x00000006, "PPPP", NULL },
-	{ 0x00000007, "CLIPID", NULL },
-	{ 0x00000008, "PFIFO_READ", NULL },
-	{ 0x00000009, "VFETCH", NULL },
-	{ 0x0000000a, "TEXTURE", NULL },
-	{ 0x0000000b, "PROP", vm_prop_subclients },
-	{ 0x0000000c, "PVP", NULL },
-	{ 0x0000000d, "PBSP", NULL },
-	{ 0x0000000e, "PCRYPT", NULL },
-	{ 0x0000000f, "PCOUNTER", NULL },
-	{ 0x00000011, "PDAEMON", NULL },
-	{}
-};
-
-static const struct nouveau_enum vm_engine[] = {
-	{ 0x00000000, "PGRAPH", NULL, NVDEV_ENGINE_GR },
-	{ 0x00000001, "PVP", NULL, NVDEV_ENGINE_VP },
-	{ 0x00000004, "PEEPHOLE", NULL },
-	{ 0x00000005, "PFIFO", vm_pfifo_subclients, NVDEV_ENGINE_FIFO },
-	{ 0x00000006, "BAR", vm_bar_subclients },
-	{ 0x00000008, "PPPP", NULL, NVDEV_ENGINE_PPP },
-	{ 0x00000008, "PMPEG", NULL, NVDEV_ENGINE_MPEG },
-	{ 0x00000009, "PBSP", NULL, NVDEV_ENGINE_BSP },
-	{ 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CRYPT },
-	{ 0x0000000b, "PCOUNTER", NULL },
-	{ 0x0000000c, "SEMAPHORE_BG", NULL },
-	{ 0x0000000d, "PCOPY", NULL, NVDEV_ENGINE_COPY0 },
-	{ 0x0000000e, "PDAEMON", NULL },
-	{}
-};
-
-static const struct nouveau_enum vm_fault[] = {
-	{ 0x00000000, "PT_NOT_PRESENT", NULL },
-	{ 0x00000001, "PT_TOO_SHORT", NULL },
-	{ 0x00000002, "PAGE_NOT_PRESENT", NULL },
-	{ 0x00000003, "PAGE_SYSTEM_ONLY", NULL },
-	{ 0x00000004, "PAGE_READ_ONLY", NULL },
-	{ 0x00000006, "NULL_DMAOBJ", NULL },
-	{ 0x00000007, "WRONG_MEMTYPE", NULL },
-	{ 0x0000000b, "VRAM_LIMIT", NULL },
-	{ 0x0000000f, "DMAOBJ_LIMIT", NULL },
-	{}
-};
-
-static void
-nv50_fb_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_device *device = nv_device(subdev);
-	struct nouveau_engine *engine;
-	struct nv50_fb_priv *priv = (void *)subdev;
-	const struct nouveau_enum *en, *cl;
-	struct nouveau_object *engctx = NULL;
-	u32 trap[6], idx, chan;
-	u8 st0, st1, st2, st3;
-	int i;
-
-	idx = nv_rd32(priv, 0x100c90);
-	if (!(idx & 0x80000000))
-		return;
-	idx &= 0x00ffffff;
-
-	for (i = 0; i < 6; i++) {
-		nv_wr32(priv, 0x100c90, idx | i << 24);
-		trap[i] = nv_rd32(priv, 0x100c94);
-	}
-	nv_wr32(priv, 0x100c90, idx | 0x80000000);
-
-	/* decode status bits into something more useful */
-	if (device->chipset  < 0xa3 ||
-	    device->chipset == 0xaa || device->chipset == 0xac) {
-		st0 = (trap[0] & 0x0000000f) >> 0;
-		st1 = (trap[0] & 0x000000f0) >> 4;
-		st2 = (trap[0] & 0x00000f00) >> 8;
-		st3 = (trap[0] & 0x0000f000) >> 12;
-	} else {
-		st0 = (trap[0] & 0x000000ff) >> 0;
-		st1 = (trap[0] & 0x0000ff00) >> 8;
-		st2 = (trap[0] & 0x00ff0000) >> 16;
-		st3 = (trap[0] & 0xff000000) >> 24;
-	}
-	chan = (trap[2] << 16) | trap[1];
-
-	en = nouveau_enum_find(vm_engine, st0);
-
-	if (en && en->data2) {
-		const struct nouveau_enum *orig_en = en;
-		while (en->name && en->value == st0 && en->data2) {
-			engine = nouveau_engine(subdev, en->data2);
-			if (engine) {
-				engctx = nouveau_engctx_get(engine, chan);
-				if (engctx)
-					break;
-			}
-			en++;
-		}
-		if (!engctx)
-			en = orig_en;
-	}
-
-	nv_error(priv, "trapped %s at 0x%02x%04x%04x on channel 0x%08x [%s] ",
-		 (trap[5] & 0x00000100) ? "read" : "write",
-		 trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, chan,
-		 nouveau_client_name(engctx));
-
-	nouveau_engctx_put(engctx);
-
-	if (en)
-		pr_cont("%s/", en->name);
-	else
-		pr_cont("%02x/", st0);
-
-	cl = nouveau_enum_find(vm_client, st2);
-	if (cl)
-		pr_cont("%s/", cl->name);
-	else
-		pr_cont("%02x/", st2);
-
-	if      (cl && cl->data) cl = nouveau_enum_find(cl->data, st3);
-	else if (en && en->data) cl = nouveau_enum_find(en->data, st3);
-	else                     cl = NULL;
-	if (cl)
-		pr_cont("%s", cl->name);
-	else
-		pr_cont("%02x", st3);
-
-	pr_cont(" reason: ");
-	en = nouveau_enum_find(vm_fault, st1);
-	if (en)
-		pr_cont("%s\n", en->name);
-	else
-		pr_cont("0x%08x\n", st1);
-}
-
-int
-nv50_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	     struct nouveau_oclass *oclass, void *data, u32 size,
-	     struct nouveau_object **pobject)
-{
-	struct nouveau_device *device = nv_device(parent);
-	struct nv50_fb_priv *priv;
-	int ret;
-
-	ret = nouveau_fb_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
-	if (priv->r100c08_page) {
-		priv->r100c08 = dma_map_page(nv_device_base(device),
-					     priv->r100c08_page, 0, PAGE_SIZE,
-					     DMA_BIDIRECTIONAL);
-		if (dma_mapping_error(nv_device_base(device), priv->r100c08))
-			return -EFAULT;
-	} else {
-		nv_warn(priv, "failed 0x100c08 page alloc\n");
-	}
-
-	nv_subdev(priv)->intr = nv50_fb_intr;
-	return 0;
-}
-
-void
-nv50_fb_dtor(struct nouveau_object *object)
-{
-	struct nouveau_device *device = nv_device(object);
-	struct nv50_fb_priv *priv = (void *)object;
-
-	if (priv->r100c08_page) {
-		dma_unmap_page(nv_device_base(device), priv->r100c08, PAGE_SIZE,
-			       DMA_BIDIRECTIONAL);
-		__free_page(priv->r100c08_page);
-	}
-
-	nouveau_fb_destroy(&priv->base);
-}
-
-int
-nv50_fb_init(struct nouveau_object *object)
-{
-	struct nv50_fb_impl *impl = (void *)object->oclass;
-	struct nv50_fb_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_fb_init(&priv->base);
-	if (ret)
-		return ret;
-
-	/* Not a clue what this is exactly.  Without pointing it at a
-	 * scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
-	 * cause IOMMU "read from address 0" errors (rh#561267)
-	 */
-	nv_wr32(priv, 0x100c08, priv->r100c08 >> 8);
-
-	/* This is needed to get meaningful information from 100c90
-	 * on traps. No idea what these values mean exactly. */
-	nv_wr32(priv, 0x100c90, impl->trap);
-	return 0;
-}
-
-struct nouveau_oclass *
-nv50_fb_oclass = &(struct nv50_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0x50),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_fb_ctor,
-		.dtor = nv50_fb_dtor,
-		.init = nv50_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv50_fb_memtype_valid,
-	.base.ram = &nv50_ram_oclass,
-	.trap = 0x000707ff,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.h b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.h
deleted file mode 100644
index c5e5a888c607..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef __NVKM_FB_NV50_H__
-#define __NVKM_FB_NV50_H__
-
-#include "priv.h"
-
-struct nv50_fb_priv {
-	struct nouveau_fb base;
-	struct page *r100c08_page;
-	dma_addr_t r100c08;
-};
-
-int  nv50_fb_ctor(struct nouveau_object *, struct nouveau_object *,
-		  struct nouveau_oclass *, void *, u32,
-		  struct nouveau_object **);
-void nv50_fb_dtor(struct nouveau_object *);
-int  nv50_fb_init(struct nouveau_object *);
-
-struct nv50_fb_impl {
-	struct nouveau_fb_impl base;
-	u32 trap;
-};
-
-#define nv50_ram_create(p,e,o,d)                                               \
-	nv50_ram_create_((p), (e), (o), sizeof(**d), (void **)d)
-int  nv50_ram_create_(struct nouveau_object *, struct nouveau_object *,
-		      struct nouveau_oclass *, int, void **);
-int  nv50_ram_get(struct nouveau_fb *, u64 size, u32 align, u32 ncmin,
-		  u32 memtype, struct nouveau_mem **);
-void nv50_ram_put(struct nouveau_fb *, struct nouveau_mem **);
-void __nv50_ram_put(struct nouveau_fb *, struct nouveau_mem *);
-extern int nv50_fb_memtype[0x80];
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv84.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv84.c
deleted file mode 100644
index cf0e767d3833..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv84.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv50.h"
-
-struct nouveau_oclass *
-nv84_fb_oclass = &(struct nv50_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0x84),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_fb_ctor,
-		.dtor = nv50_fb_dtor,
-		.init = nv50_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv50_fb_memtype_valid,
-	.base.ram = &nv50_ram_oclass,
-	.trap = 0x001d07ff,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nva3.c
deleted file mode 100644
index dab6e1c63d48..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nva3.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv50.h"
-
-struct nouveau_oclass *
-nva3_fb_oclass = &(struct nv50_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0xa3),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_fb_ctor,
-		.dtor = nv50_fb_dtor,
-		.init = nv50_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv50_fb_memtype_valid,
-	.base.ram = &nva3_ram_oclass,
-	.trap = 0x000d0fff,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvaa.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nvaa.c
deleted file mode 100644
index cba8e6818035..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nvaa.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv50.h"
-
-struct nouveau_oclass *
-nvaa_fb_oclass = &(struct nv50_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0xaa),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_fb_ctor,
-		.dtor = nv50_fb_dtor,
-		.init = nv50_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv50_fb_memtype_valid,
-	.base.ram = &nvaa_ram_oclass,
-	.trap = 0x001d07ff,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvaf.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nvaf.c
deleted file mode 100644
index 5423faa2c09b..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nvaf.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv50.h"
-
-struct nouveau_oclass *
-nvaf_fb_oclass = &(struct nv50_fb_impl) {
-	.base.base.handle = NV_SUBDEV(FB, 0xaf),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_fb_ctor,
-		.dtor = nv50_fb_dtor,
-		.init = nv50_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.base.memtype = nv50_fb_memtype_valid,
-	.base.ram = &nvaa_ram_oclass,
-	.trap = 0x089d1fff,
-}.base.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c
deleted file mode 100644
index 32f28dc73ef2..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nvc0.h"
-
-extern const u8 nvc0_pte_storage_type_map[256];
-
-bool
-nvc0_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags)
-{
-	u8 memtype = (tile_flags & 0x0000ff00) >> 8;
-	return likely((nvc0_pte_storage_type_map[memtype] != 0xff));
-}
-
-static void
-nvc0_fb_intr(struct nouveau_subdev *subdev)
-{
-	struct nvc0_fb_priv *priv = (void *)subdev;
-	u32 intr = nv_rd32(priv, 0x000100);
-	if (intr & 0x08000000) {
-		nv_debug(priv, "PFFB intr\n");
-		intr &= ~0x08000000;
-	}
-	if (intr & 0x00002000) {
-		nv_debug(priv, "PBFB intr\n");
-		intr &= ~0x00002000;
-	}
-}
-
-int
-nvc0_fb_init(struct nouveau_object *object)
-{
-	struct nvc0_fb_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_fb_init(&priv->base);
-	if (ret)
-		return ret;
-
-	if (priv->r100c10_page)
-		nv_wr32(priv, 0x100c10, priv->r100c10 >> 8);
-	nv_mask(priv, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */
-	return 0;
-}
-
-void
-nvc0_fb_dtor(struct nouveau_object *object)
-{
-	struct nouveau_device *device = nv_device(object);
-	struct nvc0_fb_priv *priv = (void *)object;
-
-	if (priv->r100c10_page) {
-		dma_unmap_page(nv_device_base(device), priv->r100c10, PAGE_SIZE,
-			       DMA_BIDIRECTIONAL);
-		__free_page(priv->r100c10_page);
-	}
-
-	nouveau_fb_destroy(&priv->base);
-}
-
-int
-nvc0_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	     struct nouveau_oclass *oclass, void *data, u32 size,
-	     struct nouveau_object **pobject)
-{
-	struct nouveau_device *device = nv_device(parent);
-	struct nvc0_fb_priv *priv;
-	int ret;
-
-	ret = nouveau_fb_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->r100c10_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
-	if (priv->r100c10_page) {
-		priv->r100c10 = dma_map_page(nv_device_base(device),
-					     priv->r100c10_page, 0, PAGE_SIZE,
-					     DMA_BIDIRECTIONAL);
-		if (dma_mapping_error(nv_device_base(device), priv->r100c10))
-			return -EFAULT;
-	}
-
-	nv_subdev(priv)->intr = nvc0_fb_intr;
-	return 0;
-}
-
-struct nouveau_oclass *
-nvc0_fb_oclass = &(struct nouveau_fb_impl) {
-	.base.handle = NV_SUBDEV(FB, 0xc0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_fb_ctor,
-		.dtor = nvc0_fb_dtor,
-		.init = nvc0_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.memtype = nvc0_fb_memtype_valid,
-	.ram = &nvc0_ram_oclass,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.h b/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.h
deleted file mode 100644
index 705a06d755ad..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef __NVKM_RAM_NVC0_H__
-#define __NVKM_RAM_NVC0_H__
-
-#include "priv.h"
-#include "nv50.h"
-
-struct nvc0_fb_priv {
-	struct nouveau_fb base;
-	struct page *r100c10_page;
-	dma_addr_t r100c10;
-};
-
-int  nvc0_fb_ctor(struct nouveau_object *, struct nouveau_object *,
-		  struct nouveau_oclass *, void *, u32,
-		  struct nouveau_object **);
-void nvc0_fb_dtor(struct nouveau_object *);
-int  nvc0_fb_init(struct nouveau_object *);
-bool nvc0_fb_memtype_valid(struct nouveau_fb *, u32);
-
-
-#define nvc0_ram_create(p,e,o,m,d)                                             \
-	nvc0_ram_create_((p), (e), (o), (m), sizeof(**d), (void **)d)
-int  nvc0_ram_create_(struct nouveau_object *, struct nouveau_object *,
-		      struct nouveau_oclass *, u32, int, void **);
-int  nvc0_ram_get(struct nouveau_fb *, u64, u32, u32, u32,
-		  struct nouveau_mem **);
-void nvc0_ram_put(struct nouveau_fb *, struct nouveau_mem **);
-
-int  nve0_ram_init(struct nouveau_object*);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nve0.c
deleted file mode 100644
index 595db50cfef3..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nve0.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nvc0.h"
-
-struct nouveau_oclass *
-nve0_fb_oclass = &(struct nouveau_fb_impl) {
-	.base.handle = NV_SUBDEV(FB, 0xe0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_fb_ctor,
-		.dtor = nvc0_fb_dtor,
-		.init = nvc0_fb_init,
-		.fini = _nouveau_fb_fini,
-	},
-	.memtype = nvc0_fb_memtype_valid,
-	.ram = &nve0_ram_oclass,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h b/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h
deleted file mode 100644
index 283863f7aa9b..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h
+++ /dev/null
@@ -1,76 +0,0 @@
-#ifndef __NVKM_FB_PRIV_H__
-#define __NVKM_FB_PRIV_H__
-
-#include <subdev/fb.h>
-
-#define nouveau_ram_create(p,e,o,d)                                            \
-	nouveau_object_create_((p), (e), (o), 0, sizeof(**d), (void **)d)
-#define nouveau_ram_destroy(p)                                                 \
-	nouveau_object_destroy(&(p)->base)
-#define nouveau_ram_init(p)                                                    \
-	nouveau_object_init(&(p)->base)
-#define nouveau_ram_fini(p,s)                                                  \
-	nouveau_object_fini(&(p)->base, (s))
-
-#define nouveau_ram_create_(p,e,o,s,d)                                         \
-	nouveau_object_create_((p), (e), (o), 0, (s), (void **)d)
-#define _nouveau_ram_dtor nouveau_object_destroy
-#define _nouveau_ram_init nouveau_object_init
-#define _nouveau_ram_fini nouveau_object_fini
-
-extern struct nouveau_oclass nv04_ram_oclass;
-extern struct nouveau_oclass nv10_ram_oclass;
-extern struct nouveau_oclass nv1a_ram_oclass;
-extern struct nouveau_oclass nv20_ram_oclass;
-extern struct nouveau_oclass nv40_ram_oclass;
-extern struct nouveau_oclass nv41_ram_oclass;
-extern struct nouveau_oclass nv44_ram_oclass;
-extern struct nouveau_oclass nv49_ram_oclass;
-extern struct nouveau_oclass nv4e_ram_oclass;
-extern struct nouveau_oclass nv50_ram_oclass;
-extern struct nouveau_oclass nva3_ram_oclass;
-extern struct nouveau_oclass nvaa_ram_oclass;
-extern struct nouveau_oclass nvc0_ram_oclass;
-extern struct nouveau_oclass nve0_ram_oclass;
-extern struct nouveau_oclass gk20a_ram_oclass;
-extern struct nouveau_oclass gm107_ram_oclass;
-
-int nouveau_sddr2_calc(struct nouveau_ram *ram);
-int nouveau_sddr3_calc(struct nouveau_ram *ram);
-int nouveau_gddr3_calc(struct nouveau_ram *ram);
-int nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts);
-
-#define nouveau_fb_create(p,e,c,d)                                             \
-	nouveau_fb_create_((p), (e), (c), sizeof(**d), (void **)d)
-#define nouveau_fb_destroy(p) ({                                               \
-	struct nouveau_fb *pfb = (p);                                          \
-	_nouveau_fb_dtor(nv_object(pfb));                                      \
-})
-#define nouveau_fb_init(p) ({                                                  \
-	struct nouveau_fb *pfb = (p);                                          \
-	_nouveau_fb_init(nv_object(pfb));                                      \
-})
-#define nouveau_fb_fini(p,s) ({                                                \
-	struct nouveau_fb *pfb = (p);                                          \
-	_nouveau_fb_fini(nv_object(pfb), (s));                                 \
-})
-
-int nouveau_fb_create_(struct nouveau_object *, struct nouveau_object *,
-		       struct nouveau_oclass *, int, void **);
-void _nouveau_fb_dtor(struct nouveau_object *);
-int  _nouveau_fb_init(struct nouveau_object *);
-int  _nouveau_fb_fini(struct nouveau_object *, bool);
-
-struct nouveau_fb_impl {
-	struct nouveau_oclass base;
-	struct nouveau_oclass *ram;
-	bool (*memtype)(struct nouveau_fb *, u32);
-};
-
-bool nv04_fb_memtype_valid(struct nouveau_fb *, u32 memtype);
-bool nv50_fb_memtype_valid(struct nouveau_fb *, u32 memtype);
-
-struct nouveau_bios;
-int  nouveau_fb_bios_memtype(struct nouveau_bios *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h b/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h
deleted file mode 100644
index 0ac7256443bb..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h
+++ /dev/null
@@ -1,184 +0,0 @@
-#ifndef __NVKM_FBRAM_FUC_H__
-#define __NVKM_FBRAM_FUC_H__
-
-#include <subdev/pwr.h>
-
-struct ramfuc {
-	struct nouveau_memx *memx;
-	struct nouveau_fb *pfb;
-	int sequence;
-};
-
-struct ramfuc_reg {
-	int sequence;
-	bool force;
-	u32 addr;
-	u32 stride; /* in bytes */
-	u32 mask;
-	u32 data;
-};
-
-static inline struct ramfuc_reg
-ramfuc_stride(u32 addr, u32 stride, u32 mask)
-{
-	return (struct ramfuc_reg) {
-		.sequence = 0,
-		.addr = addr,
-		.stride = stride,
-		.mask = mask,
-		.data = 0xdeadbeef,
-	};
-}
-
-static inline struct ramfuc_reg
-ramfuc_reg2(u32 addr1, u32 addr2)
-{
-	return (struct ramfuc_reg) {
-		.sequence = 0,
-		.addr = addr1,
-		.stride = addr2 - addr1,
-		.mask = 0x3,
-		.data = 0xdeadbeef,
-	};
-}
-
-static noinline struct ramfuc_reg
-ramfuc_reg(u32 addr)
-{
-	return (struct ramfuc_reg) {
-		.sequence = 0,
-		.addr = addr,
-		.stride = 0,
-		.mask = 0x1,
-		.data = 0xdeadbeef,
-	};
-}
-
-static inline int
-ramfuc_init(struct ramfuc *ram, struct nouveau_fb *pfb)
-{
-	struct nouveau_pwr *ppwr = nouveau_pwr(pfb);
-	int ret;
-
-	ret = nouveau_memx_init(ppwr, &ram->memx);
-	if (ret)
-		return ret;
-
-	ram->sequence++;
-	ram->pfb = pfb;
-	return 0;
-}
-
-static inline int
-ramfuc_exec(struct ramfuc *ram, bool exec)
-{
-	int ret = 0;
-	if (ram->pfb) {
-		ret = nouveau_memx_fini(&ram->memx, exec);
-		ram->pfb = NULL;
-	}
-	return ret;
-}
-
-static inline u32
-ramfuc_rd32(struct ramfuc *ram, struct ramfuc_reg *reg)
-{
-	if (reg->sequence != ram->sequence)
-		reg->data = nv_rd32(ram->pfb, reg->addr);
-	return reg->data;
-}
-
-static inline void
-ramfuc_wr32(struct ramfuc *ram, struct ramfuc_reg *reg, u32 data)
-{
-	unsigned int mask, off = 0;
-
-	reg->sequence = ram->sequence;
-	reg->data = data;
-
-	for (mask = reg->mask; mask > 0; mask = (mask & ~1) >> 1) {
-		if (mask & 1) {
-			nouveau_memx_wr32(ram->memx, reg->addr+off, reg->data);
-		}
-
-		off += reg->stride;
-	}
-}
-
-static inline void
-ramfuc_nuke(struct ramfuc *ram, struct ramfuc_reg *reg)
-{
-	reg->force = true;
-}
-
-static inline u32
-ramfuc_mask(struct ramfuc *ram, struct ramfuc_reg *reg, u32 mask, u32 data)
-{
-	u32 temp = ramfuc_rd32(ram, reg);
-	if (temp != ((temp & ~mask) | data) || reg->force) {
-		ramfuc_wr32(ram, reg, (temp & ~mask) | data);
-		reg->force = false;
-	}
-	return temp;
-}
-
-static inline void
-ramfuc_wait(struct ramfuc *ram, u32 addr, u32 mask, u32 data, u32 nsec)
-{
-	nouveau_memx_wait(ram->memx, addr, mask, data, nsec);
-}
-
-static inline void
-ramfuc_nsec(struct ramfuc *ram, u32 nsec)
-{
-	nouveau_memx_nsec(ram->memx, nsec);
-}
-
-static inline void
-ramfuc_wait_vblank(struct ramfuc *ram)
-{
-	nouveau_memx_wait_vblank(ram->memx);
-}
-
-static inline void
-ramfuc_train(struct ramfuc *ram)
-{
-	nouveau_memx_train(ram->memx);
-}
-
-static inline int
-ramfuc_train_result(struct nouveau_fb *pfb, u32 *result, u32 rsize)
-{
-	struct nouveau_pwr *ppwr = nouveau_pwr(pfb);
-
-	return nouveau_memx_train_result(ppwr, result, rsize);
-}
-
-static inline void
-ramfuc_block(struct ramfuc *ram)
-{
-	nouveau_memx_block(ram->memx);
-}
-
-static inline void
-ramfuc_unblock(struct ramfuc *ram)
-{
-	nouveau_memx_unblock(ram->memx);
-}
-
-#define ram_init(s,p)        ramfuc_init(&(s)->base, (p))
-#define ram_exec(s,e)        ramfuc_exec(&(s)->base, (e))
-#define ram_have(s,r)        ((s)->r_##r.addr != 0x000000)
-#define ram_rd32(s,r)        ramfuc_rd32(&(s)->base, &(s)->r_##r)
-#define ram_wr32(s,r,d)      ramfuc_wr32(&(s)->base, &(s)->r_##r, (d))
-#define ram_nuke(s,r)        ramfuc_nuke(&(s)->base, &(s)->r_##r)
-#define ram_mask(s,r,m,d)    ramfuc_mask(&(s)->base, &(s)->r_##r, (m), (d))
-#define ram_wait(s,r,m,d,n)  ramfuc_wait(&(s)->base, (r), (m), (d), (n))
-#define ram_nsec(s,n)        ramfuc_nsec(&(s)->base, (n))
-#define ram_wait_vblank(s)   ramfuc_wait_vblank(&(s)->base)
-#define ram_train(s)         ramfuc_train(&(s)->base)
-#define ram_train_result(s,r,l) ramfuc_train_result((s), (r), (l))
-#define ram_block(s)         ramfuc_block(&(s)->base)
-#define ram_unblock(s)       ramfuc_unblock(&(s)->base)
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c
deleted file mode 100644
index 4d77d75e4673..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include "priv.h"
-
-#include <subdev/fb.h>
-
-struct gk20a_mem {
-	struct nouveau_mem base;
-	void *cpuaddr;
-	dma_addr_t handle;
-};
-#define to_gk20a_mem(m) container_of(m, struct gk20a_mem, base)
-
-static void
-gk20a_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
-{
-	struct device *dev = nv_device_base(nv_device(pfb));
-	struct gk20a_mem *mem = to_gk20a_mem(*pmem);
-
-	*pmem = NULL;
-	if (unlikely(mem == NULL))
-		return;
-
-	if (likely(mem->cpuaddr))
-		dma_free_coherent(dev, mem->base.size << PAGE_SHIFT,
-				  mem->cpuaddr, mem->handle);
-
-	kfree(mem->base.pages);
-	kfree(mem);
-}
-
-static int
-gk20a_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
-	     u32 memtype, struct nouveau_mem **pmem)
-{
-	struct device *dev = nv_device_base(nv_device(pfb));
-	struct gk20a_mem *mem;
-	u32 type = memtype & 0xff;
-	u32 npages, order;
-	int i;
-
-	nv_debug(pfb, "%s: size: %llx align: %x, ncmin: %x\n", __func__, size,
-		 align, ncmin);
-
-	npages = size >> PAGE_SHIFT;
-	if (npages == 0)
-		npages = 1;
-
-	if (align == 0)
-		align = PAGE_SIZE;
-	align >>= PAGE_SHIFT;
-
-	/* round alignment to the next power of 2, if needed */
-	order = fls(align);
-	if ((align & (align - 1)) == 0)
-		order--;
-	align = BIT(order);
-
-	/* ensure returned address is correctly aligned */
-	npages = max(align, npages);
-
-	mem = kzalloc(sizeof(*mem), GFP_KERNEL);
-	if (!mem)
-		return -ENOMEM;
-
-	mem->base.size = npages;
-	mem->base.memtype = type;
-
-	mem->base.pages = kzalloc(sizeof(dma_addr_t) * npages, GFP_KERNEL);
-	if (!mem->base.pages) {
-		kfree(mem);
-		return -ENOMEM;
-	}
-
-	*pmem = &mem->base;
-
-	mem->cpuaddr = dma_alloc_coherent(dev, npages << PAGE_SHIFT,
-					  &mem->handle, GFP_KERNEL);
-	if (!mem->cpuaddr) {
-		nv_error(pfb, "%s: cannot allocate memory!\n", __func__);
-		gk20a_ram_put(pfb, pmem);
-		return -ENOMEM;
-	}
-
-	align <<= PAGE_SHIFT;
-
-	/* alignment check */
-	if (unlikely(mem->handle & (align - 1)))
-		nv_warn(pfb, "memory not aligned as requested: %pad (0x%x)\n",
-			&mem->handle, align);
-
-	nv_debug(pfb, "alloc size: 0x%x, align: 0x%x, paddr: %pad, vaddr: %p\n",
-		 npages << PAGE_SHIFT, align, &mem->handle, mem->cpuaddr);
-
-	for (i = 0; i < npages; i++)
-		mem->base.pages[i] = mem->handle + (PAGE_SIZE * i);
-
-	mem->base.offset = (u64)mem->base.pages[0];
-
-	return 0;
-}
-
-static int
-gk20a_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 datasize,
-	      struct nouveau_object **pobject)
-{
-	struct nouveau_ram *ram;
-	int ret;
-
-	ret = nouveau_ram_create(parent, engine, oclass, &ram);
-	*pobject = nv_object(ram);
-	if (ret)
-		return ret;
-	ram->type = NV_MEM_TYPE_STOLEN;
-	ram->size = get_num_physpages() << PAGE_SHIFT;
-
-	ram->get = gk20a_ram_get;
-	ram->put = gk20a_ram_put;
-
-	return 0;
-}
-
-struct nouveau_oclass
-gk20a_ram_oclass = {
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = gk20a_ram_ctor,
-		.dtor = _nouveau_ram_dtor,
-		.init = _nouveau_ram_init,
-		.fini = _nouveau_ram_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgm107.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramgm107.c
deleted file mode 100644
index 4c6363595c79..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgm107.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nvc0.h"
-
-struct gm107_ram {
-	struct nouveau_ram base;
-};
-
-static int
-gm107_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct gm107_ram *ram;
-	int ret;
-
-	ret = nvc0_ram_create(parent, engine, oclass, 0x021c14, &ram);
-	*pobject = nv_object(ram);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-struct nouveau_oclass
-gm107_ram_oclass = {
-	.handle = 0,
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = gm107_ram_ctor,
-		.dtor = _nouveau_ram_dtor,
-		.init = nve0_ram_init,
-		.fini = _nouveau_ram_fini,
-	}
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c
deleted file mode 100644
index 1972268d1410..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/fb/regsnv04.h>
-
-#include "priv.h"
-
-static int
-nv04_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nouveau_fb *pfb = nouveau_fb(parent);
-	struct nouveau_ram *ram;
-	u32 boot0 = nv_rd32(pfb, NV04_PFB_BOOT_0);
-	int ret;
-
-	ret = nouveau_ram_create(parent, engine, oclass, &ram);
-	*pobject = nv_object(ram);
-	if (ret)
-		return ret;
-
-	if (boot0 & 0x00000100) {
-		ram->size  = ((boot0 >> 12) & 0xf) * 2 + 2;
-		ram->size *= 1024 * 1024;
-	} else {
-		switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
-		case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
-			ram->size = 32 * 1024 * 1024;
-			break;
-		case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
-			ram->size = 16 * 1024 * 1024;
-			break;
-		case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
-			ram->size = 8 * 1024 * 1024;
-			break;
-		case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
-			ram->size = 4 * 1024 * 1024;
-			break;
-		}
-	}
-
-	if ((boot0 & 0x00000038) <= 0x10)
-		ram->type = NV_MEM_TYPE_SGRAM;
-	else
-		ram->type = NV_MEM_TYPE_SDRAM;
-	return 0;
-}
-
-struct nouveau_oclass
-nv04_ram_oclass = {
-	.handle = 0,
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_ram_create,
-		.dtor = _nouveau_ram_dtor,
-		.init = _nouveau_ram_init,
-		.fini = _nouveau_ram_fini,
-	}
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv10.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv10.c
deleted file mode 100644
index 8311f3774edf..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv10.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-
-static int
-nv10_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nouveau_fb *pfb = nouveau_fb(parent);
-	struct nouveau_ram *ram;
-	u32 cfg0 = nv_rd32(pfb, 0x100200);
-	int ret;
-
-	ret = nouveau_ram_create(parent, engine, oclass, &ram);
-	*pobject = nv_object(ram);
-	if (ret)
-		return ret;
-
-	if (cfg0 & 0x00000001)
-		ram->type = NV_MEM_TYPE_DDR1;
-	else
-		ram->type = NV_MEM_TYPE_SDRAM;
-
-	ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000;
-	return 0;
-}
-
-
-struct nouveau_oclass
-nv10_ram_oclass = {
-	.handle = 0,
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv10_ram_create,
-		.dtor = _nouveau_ram_dtor,
-		.init = _nouveau_ram_init,
-		.fini = _nouveau_ram_fini,
-	}
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv1a.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv1a.c
deleted file mode 100644
index d0caddfb9db0..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv1a.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-
-static int
-nv1a_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nouveau_fb *pfb = nouveau_fb(parent);
-	struct nouveau_ram *ram;
-	struct pci_dev *bridge;
-	u32 mem, mib;
-	int ret;
-
-	bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
-	if (!bridge) {
-		nv_fatal(pfb, "no bridge device\n");
-		return -ENODEV;
-	}
-
-	ret = nouveau_ram_create(parent, engine, oclass, &ram);
-	*pobject = nv_object(ram);
-	if (ret)
-		return ret;
-
-	if (nv_device(pfb)->chipset == 0x1a) {
-		pci_read_config_dword(bridge, 0x7c, &mem);
-		mib = ((mem >> 6) & 31) + 1;
-	} else {
-		pci_read_config_dword(bridge, 0x84, &mem);
-		mib = ((mem >> 4) & 127) + 1;
-	}
-
-	ram->type = NV_MEM_TYPE_STOLEN;
-	ram->size = mib * 1024 * 1024;
-	return 0;
-}
-
-struct nouveau_oclass
-nv1a_ram_oclass = {
-	.handle = 0,
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv1a_ram_create,
-		.dtor = _nouveau_ram_dtor,
-		.init = _nouveau_ram_init,
-		.fini = _nouveau_ram_fini,
-	}
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv20.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv20.c
deleted file mode 100644
index fdc11bba226d..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv20.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-
-static int
-nv20_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nouveau_fb *pfb = nouveau_fb(parent);
-	struct nouveau_ram *ram;
-	u32 pbus1218 = nv_rd32(pfb, 0x001218);
-	int ret;
-
-	ret = nouveau_ram_create(parent, engine, oclass, &ram);
-	*pobject = nv_object(ram);
-	if (ret)
-		return ret;
-
-	switch (pbus1218 & 0x00000300) {
-	case 0x00000000: ram->type = NV_MEM_TYPE_SDRAM; break;
-	case 0x00000100: ram->type = NV_MEM_TYPE_DDR1; break;
-	case 0x00000200: ram->type = NV_MEM_TYPE_GDDR3; break;
-	case 0x00000300: ram->type = NV_MEM_TYPE_GDDR2; break;
-	}
-	ram->size  = (nv_rd32(pfb, 0x10020c) & 0xff000000);
-	ram->parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
-	ram->tags  = nv_rd32(pfb, 0x100320);
-	return 0;
-}
-
-struct nouveau_oclass
-nv20_ram_oclass = {
-	.handle = 0,
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv20_ram_create,
-		.dtor = _nouveau_ram_dtor,
-		.init = _nouveau_ram_init,
-		.fini = _nouveau_ram_fini,
-	}
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv40.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv40.c
deleted file mode 100644
index 7648beb11199..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv40.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/pll.h>
-#include <subdev/bios/init.h>
-#include <subdev/clock.h>
-#include <subdev/clock/pll.h>
-#include <subdev/timer.h>
-
-#include <engine/fifo.h>
-
-#include "nv40.h"
-
-int
-nv40_ram_calc(struct nouveau_fb *pfb, u32 freq)
-{
-	struct nouveau_bios *bios = nouveau_bios(pfb);
-	struct nv40_ram *ram = (void *)pfb->ram;
-	struct nvbios_pll pll;
-	int N1, M1, N2, M2;
-	int log2P, ret;
-
-	ret = nvbios_pll_parse(bios, 0x04, &pll);
-	if (ret) {
-		nv_error(pfb, "mclk pll data not found\n");
-		return ret;
-	}
-
-	ret = nv04_pll_calc(nv_subdev(pfb), &pll, freq,
-			    &N1, &M1, &N2, &M2, &log2P);
-	if (ret < 0)
-		return ret;
-
-	ram->ctrl  = 0x80000000 | (log2P << 16);
-	ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20;
-	if (N2 == M2) {
-		ram->ctrl |= 0x00000100;
-		ram->coef  = (N1 << 8) | M1;
-	} else {
-		ram->ctrl |= 0x40000000;
-		ram->coef  = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
-	}
-
-	return 0;
-}
-
-int
-nv40_ram_prog(struct nouveau_fb *pfb)
-{
-	struct nouveau_bios *bios = nouveau_bios(pfb);
-	struct nv40_ram *ram = (void *)pfb->ram;
-	struct bit_entry M;
-	u32 crtc_mask = 0;
-	u8  sr1[2];
-	int i;
-
-	/* determine which CRTCs are active, fetch VGA_SR1 for each */
-	for (i = 0; i < 2; i++) {
-		u32 vbl = nv_rd32(pfb, 0x600808 + (i * 0x2000));
-		u32 cnt = 0;
-		do {
-			if (vbl != nv_rd32(pfb, 0x600808 + (i * 0x2000))) {
-				nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01);
-				sr1[i] = nv_rd08(pfb, 0x0c03c5 + (i * 0x2000));
-				if (!(sr1[i] & 0x20))
-					crtc_mask |= (1 << i);
-				break;
-			}
-			udelay(1);
-		} while (cnt++ < 32);
-	}
-
-	/* wait for vblank start on active crtcs, disable memory access */
-	for (i = 0; i < 2; i++) {
-		if (!(crtc_mask & (1 << i)))
-			continue;
-		nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000);
-		nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
-		nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01);
-		nv_wr08(pfb, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20);
-	}
-
-	/* prepare ram for reclocking */
-	nv_wr32(pfb, 0x1002d4, 0x00000001); /* precharge */
-	nv_wr32(pfb, 0x1002d0, 0x00000001); /* refresh */
-	nv_wr32(pfb, 0x1002d0, 0x00000001); /* refresh */
-	nv_mask(pfb, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */
-	nv_wr32(pfb, 0x1002dc, 0x00000001); /* enable self-refresh */
-
-	/* change the PLL of each memory partition */
-	nv_mask(pfb, 0x00c040, 0x0000c000, 0x00000000);
-	switch (nv_device(pfb)->chipset) {
-	case 0x40:
-	case 0x45:
-	case 0x41:
-	case 0x42:
-	case 0x47:
-		nv_mask(pfb, 0x004044, 0xc0771100, ram->ctrl);
-		nv_mask(pfb, 0x00402c, 0xc0771100, ram->ctrl);
-		nv_wr32(pfb, 0x004048, ram->coef);
-		nv_wr32(pfb, 0x004030, ram->coef);
-	case 0x43:
-	case 0x49:
-	case 0x4b:
-		nv_mask(pfb, 0x004038, 0xc0771100, ram->ctrl);
-		nv_wr32(pfb, 0x00403c, ram->coef);
-	default:
-		nv_mask(pfb, 0x004020, 0xc0771100, ram->ctrl);
-		nv_wr32(pfb, 0x004024, ram->coef);
-		break;
-	}
-	udelay(100);
-	nv_mask(pfb, 0x00c040, 0x0000c000, 0x0000c000);
-
-	/* re-enable normal operation of memory controller */
-	nv_wr32(pfb, 0x1002dc, 0x00000000);
-	nv_mask(pfb, 0x100210, 0x80000000, 0x80000000);
-	udelay(100);
-
-	/* execute memory reset script from vbios */
-	if (!bit_entry(bios, 'M', &M)) {
-		struct nvbios_init init = {
-			.subdev = nv_subdev(pfb),
-			.bios = bios,
-			.offset = nv_ro16(bios, M.offset + 0x00),
-			.execute = 1,
-		};
-
-		nvbios_exec(&init);
-	}
-
-	/* make sure we're in vblank (hopefully the same one as before), and
-	 * then re-enable crtc memory access
-	 */
-	for (i = 0; i < 2; i++) {
-		if (!(crtc_mask & (1 << i)))
-			continue;
-		nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
-		nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01);
-		nv_wr08(pfb, 0x0c03c5 + (i * 0x2000), sr1[i]);
-	}
-
-	return 0;
-}
-
-void
-nv40_ram_tidy(struct nouveau_fb *pfb)
-{
-}
-
-static int
-nv40_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nouveau_fb *pfb = nouveau_fb(parent);
-	struct nv40_ram *ram;
-	u32 pbus1218 = nv_rd32(pfb, 0x001218);
-	int ret;
-
-	ret = nouveau_ram_create(parent, engine, oclass, &ram);
-	*pobject = nv_object(ram);
-	if (ret)
-		return ret;
-
-	switch (pbus1218 & 0x00000300) {
-	case 0x00000000: ram->base.type = NV_MEM_TYPE_SDRAM; break;
-	case 0x00000100: ram->base.type = NV_MEM_TYPE_DDR1; break;
-	case 0x00000200: ram->base.type = NV_MEM_TYPE_GDDR3; break;
-	case 0x00000300: ram->base.type = NV_MEM_TYPE_DDR2; break;
-	}
-
-	ram->base.size  =  nv_rd32(pfb, 0x10020c) & 0xff000000;
-	ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
-	ram->base.tags  =  nv_rd32(pfb, 0x100320);
-	ram->base.calc = nv40_ram_calc;
-	ram->base.prog = nv40_ram_prog;
-	ram->base.tidy = nv40_ram_tidy;
-	return 0;
-}
-
-
-struct nouveau_oclass
-nv40_ram_oclass = {
-	.handle = 0,
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv40_ram_create,
-		.dtor = _nouveau_ram_dtor,
-		.init = _nouveau_ram_init,
-		.fini = _nouveau_ram_fini,
-	}
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv41.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv41.c
deleted file mode 100644
index d64498a4d9ee..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv41.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv40.h"
-
-static int
-nv41_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nouveau_fb *pfb = nouveau_fb(parent);
-	struct nv40_ram *ram;
-	u32 pfb474 = nv_rd32(pfb, 0x100474);
-	int ret;
-
-	ret = nouveau_ram_create(parent, engine, oclass, &ram);
-	*pobject = nv_object(ram);
-	if (ret)
-		return ret;
-
-	if (pfb474 & 0x00000004)
-		ram->base.type = NV_MEM_TYPE_GDDR3;
-	if (pfb474 & 0x00000002)
-		ram->base.type = NV_MEM_TYPE_DDR2;
-	if (pfb474 & 0x00000001)
-		ram->base.type = NV_MEM_TYPE_DDR1;
-
-	ram->base.size  =  nv_rd32(pfb, 0x10020c) & 0xff000000;
-	ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
-	ram->base.tags  =  nv_rd32(pfb, 0x100320);
-	ram->base.calc = nv40_ram_calc;
-	ram->base.prog = nv40_ram_prog;
-	ram->base.tidy = nv40_ram_tidy;
-	return 0;
-}
-
-struct nouveau_oclass
-nv41_ram_oclass = {
-	.handle = 0,
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv41_ram_create,
-		.dtor = _nouveau_ram_dtor,
-		.init = _nouveau_ram_init,
-		.fini = _nouveau_ram_fini,
-	}
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv44.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv44.c
deleted file mode 100644
index 089acac810c5..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv44.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv40.h"
-
-static int
-nv44_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nouveau_fb *pfb = nouveau_fb(parent);
-	struct nv40_ram *ram;
-	u32 pfb474 = nv_rd32(pfb, 0x100474);
-	int ret;
-
-	ret = nouveau_ram_create(parent, engine, oclass, &ram);
-	*pobject = nv_object(ram);
-	if (ret)
-		return ret;
-
-	if (pfb474 & 0x00000004)
-		ram->base.type = NV_MEM_TYPE_GDDR3;
-	if (pfb474 & 0x00000002)
-		ram->base.type = NV_MEM_TYPE_DDR2;
-	if (pfb474 & 0x00000001)
-		ram->base.type = NV_MEM_TYPE_DDR1;
-
-	ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000;
-	ram->base.calc = nv40_ram_calc;
-	ram->base.prog = nv40_ram_prog;
-	ram->base.tidy = nv40_ram_tidy;
-	return 0;
-}
-
-struct nouveau_oclass
-nv44_ram_oclass = {
-	.handle = 0,
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv44_ram_create,
-		.dtor = _nouveau_ram_dtor,
-		.init = _nouveau_ram_init,
-		.fini = _nouveau_ram_fini,
-	}
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv49.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv49.c
deleted file mode 100644
index baa013afa57b..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv49.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv40.h"
-
-static int
-nv49_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nouveau_fb *pfb = nouveau_fb(parent);
-	struct nv40_ram *ram;
-	u32 pfb914 = nv_rd32(pfb, 0x100914);
-	int ret;
-
-	ret = nouveau_ram_create(parent, engine, oclass, &ram);
-	*pobject = nv_object(ram);
-	if (ret)
-		return ret;
-
-	switch (pfb914 & 0x00000003) {
-	case 0x00000000: ram->base.type = NV_MEM_TYPE_DDR1; break;
-	case 0x00000001: ram->base.type = NV_MEM_TYPE_DDR2; break;
-	case 0x00000002: ram->base.type = NV_MEM_TYPE_GDDR3; break;
-	case 0x00000003: break;
-	}
-
-	ram->base.size  =  nv_rd32(pfb, 0x10020c) & 0xff000000;
-	ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
-	ram->base.tags  =  nv_rd32(pfb, 0x100320);
-	ram->base.calc = nv40_ram_calc;
-	ram->base.prog = nv40_ram_prog;
-	ram->base.tidy = nv40_ram_tidy;
-	return 0;
-}
-
-struct nouveau_oclass
-nv49_ram_oclass = {
-	.handle = 0,
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv49_ram_create,
-		.dtor = _nouveau_ram_dtor,
-		.init = _nouveau_ram_init,
-		.fini = _nouveau_ram_fini,
-	}
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv4e.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv4e.c
deleted file mode 100644
index 63a6aab86028..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv4e.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-
-static int
-nv4e_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nouveau_fb *pfb = nouveau_fb(parent);
-	struct nouveau_ram *ram;
-	int ret;
-
-	ret = nouveau_ram_create(parent, engine, oclass, &ram);
-	*pobject = nv_object(ram);
-	if (ret)
-		return ret;
-
-	ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000;
-	ram->type = NV_MEM_TYPE_STOLEN;
-	return 0;
-}
-
-struct nouveau_oclass
-nv4e_ram_oclass = {
-	.handle = 0,
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv4e_ram_create,
-		.dtor = _nouveau_ram_dtor,
-		.init = _nouveau_ram_init,
-		.fini = _nouveau_ram_fini,
-	}
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c
deleted file mode 100644
index 64a983c96625..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/pll.h>
-#include <subdev/bios/perf.h>
-#include <subdev/bios/timing.h>
-#include <subdev/clock/pll.h>
-#include <subdev/fb.h>
-
-#include <core/option.h>
-#include <core/mm.h>
-
-#include "ramseq.h"
-
-#include "nv50.h"
-
-struct nv50_ramseq {
-	struct hwsq base;
-	struct hwsq_reg r_0x002504;
-	struct hwsq_reg r_0x004008;
-	struct hwsq_reg r_0x00400c;
-	struct hwsq_reg r_0x00c040;
-	struct hwsq_reg r_0x100210;
-	struct hwsq_reg r_0x1002d0;
-	struct hwsq_reg r_0x1002d4;
-	struct hwsq_reg r_0x1002dc;
-	struct hwsq_reg r_0x100da0[8];
-	struct hwsq_reg r_0x100e20;
-	struct hwsq_reg r_0x100e24;
-	struct hwsq_reg r_0x611200;
-	struct hwsq_reg r_timing[9];
-	struct hwsq_reg r_mr[4];
-};
-
-struct nv50_ram {
-	struct nouveau_ram base;
-	struct nv50_ramseq hwsq;
-};
-
-#define QFX5800NVA0 1
-
-static int
-nv50_ram_calc(struct nouveau_fb *pfb, u32 freq)
-{
-	struct nouveau_bios *bios = nouveau_bios(pfb);
-	struct nv50_ram *ram = (void *)pfb->ram;
-	struct nv50_ramseq *hwsq = &ram->hwsq;
-	struct nvbios_perfE perfE;
-	struct nvbios_pll mpll;
-	struct {
-		u32 data;
-		u8  size;
-	} ramcfg, timing;
-	u8  ver, hdr, cnt, len, strap;
-	int N1, M1, N2, M2, P;
-	int ret, i;
-
-	/* lookup closest matching performance table entry for frequency */
-	i = 0;
-	do {
-		ramcfg.data = nvbios_perfEp(bios, i++, &ver, &hdr, &cnt,
-					   &ramcfg.size, &perfE);
-		if (!ramcfg.data || (ver < 0x25 || ver >= 0x40) ||
-		    (ramcfg.size < 2)) {
-			nv_error(pfb, "invalid/missing perftab entry\n");
-			return -EINVAL;
-		}
-	} while (perfE.memory < freq);
-
-	/* locate specific data set for the attached memory */
-	strap = nvbios_ramcfg_index(nv_subdev(pfb));
-	if (strap >= cnt) {
-		nv_error(pfb, "invalid ramcfg strap\n");
-		return -EINVAL;
-	}
-
-	ramcfg.data += hdr + (strap * ramcfg.size);
-
-	/* lookup memory timings, if bios says they're present */
-	strap = nv_ro08(bios, ramcfg.data + 0x01);
-	if (strap != 0xff) {
-		timing.data = nvbios_timingEe(bios, strap, &ver, &hdr,
-					     &cnt, &len);
-		if (!timing.data || ver != 0x10 || hdr < 0x12) {
-			nv_error(pfb, "invalid/missing timing entry "
-				 "%02x %04x %02x %02x\n",
-				 strap, timing.data, ver, hdr);
-			return -EINVAL;
-		}
-	} else {
-		timing.data = 0;
-	}
-
-	ret = ram_init(hwsq, nv_subdev(pfb));
-	if (ret)
-		return ret;
-
-	ram_wait(hwsq, 0x01, 0x00); /* wait for !vblank */
-	ram_wait(hwsq, 0x01, 0x01); /* wait for vblank */
-	ram_wr32(hwsq, 0x611200, 0x00003300);
-	ram_wr32(hwsq, 0x002504, 0x00000001); /* block fifo */
-	ram_nsec(hwsq, 8000);
-	ram_setf(hwsq, 0x10, 0x00); /* disable fb */
-	ram_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */
-
-	ram_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge */
-	ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */
-	ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */
-	ram_wr32(hwsq, 0x100210, 0x00000000); /* disable auto-refresh */
-	ram_wr32(hwsq, 0x1002dc, 0x00000001); /* enable self-refresh */
-
-	ret = nvbios_pll_parse(bios, 0x004008, &mpll);
-	mpll.vco2.max_freq = 0;
-	if (ret == 0) {
-		ret = nv04_pll_calc(nv_subdev(pfb), &mpll, freq,
-				   &N1, &M1, &N2, &M2, &P);
-		if (ret == 0)
-			ret = -EINVAL;
-	}
-
-	if (ret < 0)
-		return ret;
-
-	ram_mask(hwsq, 0x00c040, 0xc000c000, 0x0000c000);
-	ram_mask(hwsq, 0x004008, 0x00000200, 0x00000200);
-	ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1);
-	ram_mask(hwsq, 0x004008, 0x81ff0000, 0x80000000 | (mpll.bias_p << 19) |
-					     (P << 22) | (P << 16));
-#if QFX5800NVA0
-	for (i = 0; i < 8; i++)
-		ram_mask(hwsq, 0x100da0[i], 0x00000000, 0x00000000); /*XXX*/
-#endif
-	ram_nsec(hwsq, 96000); /*XXX*/
-	ram_mask(hwsq, 0x004008, 0x00002200, 0x00002000);
-
-	ram_wr32(hwsq, 0x1002dc, 0x00000000); /* disable self-refresh */
-	ram_wr32(hwsq, 0x100210, 0x80000000); /* enable auto-refresh */
-
-	ram_nsec(hwsq, 12000);
-
-	switch (ram->base.type) {
-	case NV_MEM_TYPE_DDR2:
-		ram_nuke(hwsq, mr[0]); /* force update */
-		ram_mask(hwsq, mr[0], 0x000, 0x000);
-		break;
-	case NV_MEM_TYPE_GDDR3:
-		ram_mask(hwsq, mr[2], 0x000, 0x000);
-		ram_nuke(hwsq, mr[0]); /* force update */
-		ram_mask(hwsq, mr[0], 0x000, 0x000);
-		break;
-	default:
-		break;
-	}
-
-	ram_mask(hwsq, timing[3], 0x00000000, 0x00000000); /*XXX*/
-	ram_mask(hwsq, timing[1], 0x00000000, 0x00000000); /*XXX*/
-	ram_mask(hwsq, timing[6], 0x00000000, 0x00000000); /*XXX*/
-	ram_mask(hwsq, timing[7], 0x00000000, 0x00000000); /*XXX*/
-	ram_mask(hwsq, timing[8], 0x00000000, 0x00000000); /*XXX*/
-	ram_mask(hwsq, timing[0], 0x00000000, 0x00000000); /*XXX*/
-	ram_mask(hwsq, timing[2], 0x00000000, 0x00000000); /*XXX*/
-	ram_mask(hwsq, timing[4], 0x00000000, 0x00000000); /*XXX*/
-	ram_mask(hwsq, timing[5], 0x00000000, 0x00000000); /*XXX*/
-
-	ram_mask(hwsq, timing[0], 0x00000000, 0x00000000); /*XXX*/
-
-#if QFX5800NVA0
-	ram_nuke(hwsq, 0x100e24);
-	ram_mask(hwsq, 0x100e24, 0x00000000, 0x00000000);
-	ram_nuke(hwsq, 0x100e20);
-	ram_mask(hwsq, 0x100e20, 0x00000000, 0x00000000);
-#endif
-
-	ram_mask(hwsq, mr[0], 0x100, 0x100);
-	ram_mask(hwsq, mr[0], 0x100, 0x000);
-
-	ram_setf(hwsq, 0x10, 0x01); /* enable fb */
-	ram_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */
-	ram_wr32(hwsq, 0x611200, 0x00003330);
-	ram_wr32(hwsq, 0x002504, 0x00000000); /* un-block fifo */
-	return 0;
-}
-
-static int
-nv50_ram_prog(struct nouveau_fb *pfb)
-{
-	struct nouveau_device *device = nv_device(pfb);
-	struct nv50_ram *ram = (void *)pfb->ram;
-	struct nv50_ramseq *hwsq = &ram->hwsq;
-
-	ram_exec(hwsq, nouveau_boolopt(device->cfgopt, "NvMemExec", true));
-	return 0;
-}
-
-static void
-nv50_ram_tidy(struct nouveau_fb *pfb)
-{
-	struct nv50_ram *ram = (void *)pfb->ram;
-	struct nv50_ramseq *hwsq = &ram->hwsq;
-	ram_exec(hwsq, false);
-}
-
-void
-__nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem *mem)
-{
-	struct nouveau_mm_node *this;
-
-	while (!list_empty(&mem->regions)) {
-		this = list_first_entry(&mem->regions, typeof(*this), rl_entry);
-
-		list_del(&this->rl_entry);
-		nouveau_mm_free(&pfb->vram, &this);
-	}
-
-	nouveau_mm_free(&pfb->tags, &mem->tag);
-}
-
-void
-nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
-{
-	struct nouveau_mem *mem = *pmem;
-
-	*pmem = NULL;
-	if (unlikely(mem == NULL))
-		return;
-
-	mutex_lock(&pfb->base.mutex);
-	__nv50_ram_put(pfb, mem);
-	mutex_unlock(&pfb->base.mutex);
-
-	kfree(mem);
-}
-
-int
-nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
-	     u32 memtype, struct nouveau_mem **pmem)
-{
-	struct nouveau_mm *heap = &pfb->vram;
-	struct nouveau_mm *tags = &pfb->tags;
-	struct nouveau_mm_node *r;
-	struct nouveau_mem *mem;
-	int comp = (memtype & 0x300) >> 8;
-	int type = (memtype & 0x07f);
-	int back = (memtype & 0x800);
-	int min, max, ret;
-
-	max = (size >> 12);
-	min = ncmin ? (ncmin >> 12) : max;
-	align >>= 12;
-
-	mem = kzalloc(sizeof(*mem), GFP_KERNEL);
-	if (!mem)
-		return -ENOMEM;
-
-	mutex_lock(&pfb->base.mutex);
-	if (comp) {
-		if (align == 16) {
-			int n = (max >> 4) * comp;
-
-			ret = nouveau_mm_head(tags, 0, 1, n, n, 1, &mem->tag);
-			if (ret)
-				mem->tag = NULL;
-		}
-
-		if (unlikely(!mem->tag))
-			comp = 0;
-	}
-
-	INIT_LIST_HEAD(&mem->regions);
-	mem->memtype = (comp << 7) | type;
-	mem->size = max;
-
-	type = nv50_fb_memtype[type];
-	do {
-		if (back)
-			ret = nouveau_mm_tail(heap, 0, type, max, min, align, &r);
-		else
-			ret = nouveau_mm_head(heap, 0, type, max, min, align, &r);
-		if (ret) {
-			mutex_unlock(&pfb->base.mutex);
-			pfb->ram->put(pfb, &mem);
-			return ret;
-		}
-
-		list_add_tail(&r->rl_entry, &mem->regions);
-		max -= r->length;
-	} while (max);
-	mutex_unlock(&pfb->base.mutex);
-
-	r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
-	mem->offset = (u64)r->offset << 12;
-	*pmem = mem;
-	return 0;
-}
-
-static u32
-nv50_fb_vram_rblock(struct nouveau_fb *pfb, struct nouveau_ram *ram)
-{
-	int colbits, rowbitsa, rowbitsb, banks;
-	u64 rowsize, predicted;
-	u32 r0, r4, rt, rblock_size;
-
-	r0 = nv_rd32(pfb, 0x100200);
-	r4 = nv_rd32(pfb, 0x100204);
-	rt = nv_rd32(pfb, 0x100250);
-	nv_debug(pfb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt,
-			nv_rd32(pfb, 0x001540));
-
-	colbits  =  (r4 & 0x0000f000) >> 12;
-	rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
-	rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
-	banks    = 1 << (((r4 & 0x03000000) >> 24) + 2);
-
-	rowsize = ram->parts * banks * (1 << colbits) * 8;
-	predicted = rowsize << rowbitsa;
-	if (r0 & 0x00000004)
-		predicted += rowsize << rowbitsb;
-
-	if (predicted != ram->size) {
-		nv_warn(pfb, "memory controller reports %d MiB VRAM\n",
-			(u32)(ram->size >> 20));
-	}
-
-	rblock_size = rowsize;
-	if (rt & 1)
-		rblock_size *= 3;
-
-	nv_debug(pfb, "rblock %d bytes\n", rblock_size);
-	return rblock_size;
-}
-
-int
-nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine,
-		 struct nouveau_oclass *oclass, int length, void **pobject)
-{
-	const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
-	const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
-	struct nouveau_bios *bios = nouveau_bios(parent);
-	struct nouveau_fb *pfb = nouveau_fb(parent);
-	struct nouveau_ram *ram;
-	int ret;
-
-	ret = nouveau_ram_create_(parent, engine, oclass, length, pobject);
-	ram = *pobject;
-	if (ret)
-		return ret;
-
-	ram->size = nv_rd32(pfb, 0x10020c);
-	ram->size = (ram->size & 0xffffff00) | ((ram->size & 0x000000ff) << 32);
-
-	ram->part_mask = (nv_rd32(pfb, 0x001540) & 0x00ff0000) >> 16;
-	ram->parts = hweight8(ram->part_mask);
-
-	switch (nv_rd32(pfb, 0x100714) & 0x00000007) {
-	case 0: ram->type = NV_MEM_TYPE_DDR1; break;
-	case 1:
-		if (nouveau_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3)
-			ram->type = NV_MEM_TYPE_DDR3;
-		else
-			ram->type = NV_MEM_TYPE_DDR2;
-		break;
-	case 2: ram->type = NV_MEM_TYPE_GDDR3; break;
-	case 3: ram->type = NV_MEM_TYPE_GDDR4; break;
-	case 4: ram->type = NV_MEM_TYPE_GDDR5; break;
-	default:
-		break;
-	}
-
-	ret = nouveau_mm_init(&pfb->vram, rsvd_head, (ram->size >> 12) -
-			      (rsvd_head + rsvd_tail),
-			      nv50_fb_vram_rblock(pfb, ram) >> 12);
-	if (ret)
-		return ret;
-
-	ram->ranks = (nv_rd32(pfb, 0x100200) & 0x4) ? 2 : 1;
-	ram->tags  =  nv_rd32(pfb, 0x100320);
-	ram->get = nv50_ram_get;
-	ram->put = nv50_ram_put;
-	return 0;
-}
-
-static int
-nv50_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 datasize,
-	      struct nouveau_object **pobject)
-{
-	struct nv50_ram *ram;
-	int ret, i;
-
-	ret = nv50_ram_create(parent, engine, oclass, &ram);
-	*pobject = nv_object(ram);
-	if (ret)
-		return ret;
-
-	switch (ram->base.type) {
-	case NV_MEM_TYPE_DDR2:
-	case NV_MEM_TYPE_GDDR3:
-		ram->base.calc = nv50_ram_calc;
-		ram->base.prog = nv50_ram_prog;
-		ram->base.tidy = nv50_ram_tidy;
-		break;
-	default:
-		nv_warn(ram, "reclocking of this ram type unsupported\n");
-		return 0;
-	}
-
-	ram->hwsq.r_0x002504 = hwsq_reg(0x002504);
-	ram->hwsq.r_0x00c040 = hwsq_reg(0x00c040);
-	ram->hwsq.r_0x004008 = hwsq_reg(0x004008);
-	ram->hwsq.r_0x00400c = hwsq_reg(0x00400c);
-	ram->hwsq.r_0x100210 = hwsq_reg(0x100210);
-	ram->hwsq.r_0x1002d0 = hwsq_reg(0x1002d0);
-	ram->hwsq.r_0x1002d4 = hwsq_reg(0x1002d4);
-	ram->hwsq.r_0x1002dc = hwsq_reg(0x1002dc);
-	for (i = 0; i < 8; i++)
-		ram->hwsq.r_0x100da0[i] = hwsq_reg(0x100da0 + (i * 0x04));
-	ram->hwsq.r_0x100e20 = hwsq_reg(0x100e20);
-	ram->hwsq.r_0x100e24 = hwsq_reg(0x100e24);
-	ram->hwsq.r_0x611200 = hwsq_reg(0x611200);
-
-	for (i = 0; i < 9; i++)
-		ram->hwsq.r_timing[i] = hwsq_reg(0x100220 + (i * 0x04));
-
-	if (ram->base.ranks > 1) {
-		ram->hwsq.r_mr[0] = hwsq_reg2(0x1002c0, 0x1002c8);
-		ram->hwsq.r_mr[1] = hwsq_reg2(0x1002c4, 0x1002cc);
-		ram->hwsq.r_mr[2] = hwsq_reg2(0x1002e0, 0x1002e8);
-		ram->hwsq.r_mr[3] = hwsq_reg2(0x1002e4, 0x1002ec);
-	} else {
-		ram->hwsq.r_mr[0] = hwsq_reg(0x1002c0);
-		ram->hwsq.r_mr[1] = hwsq_reg(0x1002c4);
-		ram->hwsq.r_mr[2] = hwsq_reg(0x1002e0);
-		ram->hwsq.r_mr[3] = hwsq_reg(0x1002e4);
-	}
-
-	return 0;
-}
-
-struct nouveau_oclass
-nv50_ram_oclass = {
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_ram_ctor,
-		.dtor = _nouveau_ram_dtor,
-		.init = _nouveau_ram_init,
-		.fini = _nouveau_ram_fini,
-	}
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
deleted file mode 100644
index 3b38a538845d..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
+++ /dev/null
@@ -1,1024 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- * 	    Roy Spliet <rspliet@eclipso.eu>
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/pll.h>
-#include <subdev/bios/rammap.h>
-#include <subdev/bios/M0205.h>
-#include <subdev/bios/timing.h>
-
-#include <subdev/clock/nva3.h>
-#include <subdev/clock/pll.h>
-
-#include <subdev/gpio.h>
-
-#include <subdev/timer.h>
-
-#include <engine/fifo.h>
-
-#include <core/option.h>
-
-#include "ramfuc.h"
-
-#include "nv50.h"
-
-/* XXX: Remove when memx gains GPIO support */
-extern int nv50_gpio_location(int line, u32 *reg, u32 *shift);
-
-struct nva3_ramfuc {
-	struct ramfuc base;
-	struct ramfuc_reg r_0x001610;
-	struct ramfuc_reg r_0x001700;
-	struct ramfuc_reg r_0x002504;
-	struct ramfuc_reg r_0x004000;
-	struct ramfuc_reg r_0x004004;
-	struct ramfuc_reg r_0x004018;
-	struct ramfuc_reg r_0x004128;
-	struct ramfuc_reg r_0x004168;
-	struct ramfuc_reg r_0x100080;
-	struct ramfuc_reg r_0x100200;
-	struct ramfuc_reg r_0x100210;
-	struct ramfuc_reg r_0x100220[9];
-	struct ramfuc_reg r_0x100264;
-	struct ramfuc_reg r_0x1002d0;
-	struct ramfuc_reg r_0x1002d4;
-	struct ramfuc_reg r_0x1002dc;
-	struct ramfuc_reg r_0x10053c;
-	struct ramfuc_reg r_0x1005a0;
-	struct ramfuc_reg r_0x1005a4;
-	struct ramfuc_reg r_0x100700;
-	struct ramfuc_reg r_0x100714;
-	struct ramfuc_reg r_0x100718;
-	struct ramfuc_reg r_0x10071c;
-	struct ramfuc_reg r_0x100720;
-	struct ramfuc_reg r_0x100760;
-	struct ramfuc_reg r_0x1007a0;
-	struct ramfuc_reg r_0x1007e0;
-	struct ramfuc_reg r_0x100da0;
-	struct ramfuc_reg r_0x10f804;
-	struct ramfuc_reg r_0x1110e0;
-	struct ramfuc_reg r_0x111100;
-	struct ramfuc_reg r_0x111104;
-	struct ramfuc_reg r_0x1111e0;
-	struct ramfuc_reg r_0x111400;
-	struct ramfuc_reg r_0x611200;
-	struct ramfuc_reg r_mr[4];
-	struct ramfuc_reg r_gpioFBVREF;
-};
-
-struct nva3_ltrain {
-	enum {
-		NVA3_TRAIN_UNKNOWN,
-		NVA3_TRAIN_UNSUPPORTED,
-		NVA3_TRAIN_ONCE,
-		NVA3_TRAIN_EXEC,
-		NVA3_TRAIN_DONE
-	} state;
-	u32 r_100720;
-	u32 r_1111e0;
-	u32 r_111400;
-	struct nouveau_mem *mem;
-};
-
-struct nva3_ram {
-	struct nouveau_ram base;
-	struct nva3_ramfuc fuc;
-	struct nva3_ltrain ltrain;
-};
-
-void
-nva3_link_train_calc(u32 *vals, struct nva3_ltrain *train)
-{
-	int i, lo, hi;
-	u8 median[8], bins[4] = {0, 0, 0, 0}, bin = 0, qty = 0;
-
-	for (i = 0; i < 8; i++) {
-		for (lo = 0; lo < 0x40; lo++) {
-			if (!(vals[lo] & 0x80000000))
-				continue;
-			if (vals[lo] & (0x101 << i))
-				break;
-		}
-
-		if (lo == 0x40)
-			return;
-
-		for (hi = lo + 1; hi < 0x40; hi++) {
-			if (!(vals[lo] & 0x80000000))
-				continue;
-			if (!(vals[hi] & (0x101 << i))) {
-				hi--;
-				break;
-			}
-		}
-
-		median[i] = ((hi - lo) >> 1) + lo;
-		bins[(median[i] & 0xf0) >> 4]++;
-		median[i] += 0x30;
-	}
-
-	/* Find the best value for 0x1111e0 */
-	for (i = 0; i < 4; i++) {
-		if (bins[i] > qty) {
-			bin = i + 3;
-			qty = bins[i];
-		}
-	}
-
-	train->r_100720 = 0;
-	for (i = 0; i < 8; i++) {
-		median[i] = max(median[i], (u8) (bin << 4));
-		median[i] = min(median[i], (u8) ((bin << 4) | 0xf));
-
-		train->r_100720 |= ((median[i] & 0x0f) << (i << 2));
-	}
-
-	train->r_1111e0 = 0x02000000 | (bin * 0x101);
-	train->r_111400 = 0x0;
-}
-
-/*
- * Link training for (at least) DDR3
- */
-int
-nva3_link_train(struct nouveau_fb *pfb)
-{
-	struct nouveau_bios *bios = nouveau_bios(pfb);
-	struct nva3_ram *ram = (void *)pfb->ram;
-	struct nouveau_clock *clk = nouveau_clock(pfb);
-	struct nva3_ltrain *train = &ram->ltrain;
-	struct nouveau_device *device = nv_device(pfb);
-	struct nva3_ramfuc *fuc = &ram->fuc;
-	u32 *result, r1700;
-	int ret, i;
-	struct nvbios_M0205T M0205T = { 0 };
-	u8 ver, hdr, cnt, len, snr, ssz;
-	unsigned int clk_current;
-	unsigned long flags;
-	unsigned long *f = &flags;
-
-	if (nouveau_boolopt(device->cfgopt, "NvMemExec", true) != true)
-		return -ENOSYS;
-
-	/* XXX: Multiple partitions? */
-	result = kmalloc(64 * sizeof(u32), GFP_KERNEL);
-	if (!result)
-		return -ENOMEM;
-
-	train->state = NVA3_TRAIN_EXEC;
-
-	/* Clock speeds for training and back */
-	nvbios_M0205Tp(bios, &ver, &hdr, &cnt, &len, &snr, &ssz, &M0205T);
-	if (M0205T.freq == 0)
-		return -ENOENT;
-
-	clk_current = clk->read(clk, nv_clk_src_mem);
-
-	ret = nva3_clock_pre(clk, f);
-	if (ret)
-		goto out;
-
-	/* First: clock up/down */
-	ret = ram->base.calc(pfb, (u32) M0205T.freq * 1000);
-	if (ret)
-		goto out;
-
-	/* Do this *after* calc, eliminates write in script */
-	nv_wr32(pfb, 0x111400, 0x00000000);
-	/* XXX: Magic writes that improve train reliability? */
-	nv_mask(pfb, 0x100674, 0x0000ffff, 0x00000000);
-	nv_mask(pfb, 0x1005e4, 0x0000ffff, 0x00000000);
-	nv_mask(pfb, 0x100b0c, 0x000000ff, 0x00000000);
-	nv_wr32(pfb, 0x100c04, 0x00000400);
-
-	/* Now the training script */
-	r1700 = ram_rd32(fuc, 0x001700);
-
-	ram_mask(fuc, 0x100200, 0x00000800, 0x00000000);
-	ram_wr32(fuc, 0x611200, 0x3300);
-	ram_wait_vblank(fuc);
-	ram_wait(fuc, 0x611200, 0x00000003, 0x00000000, 500000);
-	ram_mask(fuc, 0x001610, 0x00000083, 0x00000003);
-	ram_mask(fuc, 0x100080, 0x00000020, 0x00000000);
-	ram_mask(fuc, 0x10f804, 0x80000000, 0x00000000);
-	ram_wr32(fuc, 0x001700, 0x00000000);
-
-	ram_train(fuc);
-
-	/* Reset */
-	ram_mask(fuc, 0x10f804, 0x80000000, 0x80000000);
-	ram_wr32(fuc, 0x10053c, 0x0);
-	ram_wr32(fuc, 0x100720, train->r_100720);
-	ram_wr32(fuc, 0x1111e0, train->r_1111e0);
-	ram_wr32(fuc, 0x111400, train->r_111400);
-	ram_nuke(fuc, 0x100080);
-	ram_mask(fuc, 0x100080, 0x00000020, 0x00000020);
-	ram_nsec(fuc, 1000);
-
-	ram_wr32(fuc, 0x001700, r1700);
-	ram_mask(fuc, 0x001610, 0x00000083, 0x00000080);
-	ram_wr32(fuc, 0x611200, 0x3330);
-	ram_mask(fuc, 0x100200, 0x00000800, 0x00000800);
-
-	ram_exec(fuc, true);
-
-	ram->base.calc(pfb, clk_current);
-	ram_exec(fuc, true);
-
-	/* Post-processing, avoids flicker */
-	nv_mask(pfb, 0x616308, 0x10, 0x10);
-	nv_mask(pfb, 0x616b08, 0x10, 0x10);
-
-	nva3_clock_post(clk, f);
-
-	ram_train_result(pfb, result, 64);
-	for (i = 0; i < 64; i++)
-		nv_debug(pfb, "Train: %08x", result[i]);
-	nva3_link_train_calc(result, train);
-
-	nv_debug(pfb, "Train: %08x %08x %08x", train->r_100720,
-			train->r_1111e0, train->r_111400);
-
-	kfree(result);
-
-	train->state = NVA3_TRAIN_DONE;
-
-	return ret;
-
-out:
-	if(ret == -EBUSY)
-		f = NULL;
-
-	train->state = NVA3_TRAIN_UNSUPPORTED;
-
-	nva3_clock_post(clk, f);
-	return ret;
-}
-
-int
-nva3_link_train_init(struct nouveau_fb *pfb)
-{
-	static const u32 pattern[16] = {
-		0xaaaaaaaa, 0xcccccccc, 0xdddddddd, 0xeeeeeeee,
-		0x00000000, 0x11111111, 0x44444444, 0xdddddddd,
-		0x33333333, 0x55555555, 0x77777777, 0x66666666,
-		0x99999999, 0x88888888, 0xeeeeeeee, 0xbbbbbbbb,
-	};
-	struct nouveau_bios *bios = nouveau_bios(pfb);
-	struct nva3_ram *ram = (void *)pfb->ram;
-	struct nva3_ltrain *train = &ram->ltrain;
-	struct nouveau_mem *mem;
-	struct nvbios_M0205E M0205E;
-	u8 ver, hdr, cnt, len;
-	u32 r001700;
-	int ret, i = 0;
-
-	train->state = NVA3_TRAIN_UNSUPPORTED;
-
-	/* We support type "5"
-	 * XXX: training pattern table appears to be unused for this routine */
-	if (!nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E))
-		return -ENOENT;
-
-	if (M0205E.type != 5)
-		return 0;
-
-	train->state = NVA3_TRAIN_ONCE;
-
-	ret = pfb->ram->get(pfb, 0x8000, 0x10000, 0, 0x800, &ram->ltrain.mem);
-	if (ret)
-		return ret;
-
-	mem = ram->ltrain.mem;
-
-	nv_wr32(pfb, 0x100538, 0x10000000 | (mem->offset >> 16));
-	nv_wr32(pfb, 0x1005a8, 0x0000ffff);
-	nv_mask(pfb, 0x10f800, 0x00000001, 0x00000001);
-
-	for (i = 0; i < 0x30; i++) {
-		nv_wr32(pfb, 0x10f8c0, (i << 8) | i);
-		nv_wr32(pfb, 0x10f900, pattern[i % 16]);
-	}
-
-	for (i = 0; i < 0x30; i++) {
-		nv_wr32(pfb, 0x10f8e0, (i << 8) | i);
-		nv_wr32(pfb, 0x10f920, pattern[i % 16]);
-	}
-
-	/* And upload the pattern */
-	r001700 = nv_rd32(pfb, 0x1700);
-	nv_wr32(pfb, 0x1700, mem->offset >> 16);
-	for (i = 0; i < 16; i++)
-		nv_wr32(pfb, 0x700000 + (i << 2), pattern[i]);
-	for (i = 0; i < 16; i++)
-		nv_wr32(pfb, 0x700100 + (i << 2), pattern[i]);
-	nv_wr32(pfb, 0x1700, r001700);
-
-	train->r_100720 = nv_rd32(pfb, 0x100720);
-	train->r_1111e0 = nv_rd32(pfb, 0x1111e0);
-	train->r_111400 = nv_rd32(pfb, 0x111400);
-
-	return 0;
-}
-
-void
-nva3_link_train_fini(struct nouveau_fb *pfb)
-{
-	struct nva3_ram *ram = (void *)pfb->ram;
-
-	if (ram->ltrain.mem)
-		pfb->ram->put(pfb, &ram->ltrain.mem);
-}
-
-/*
- * RAM reclocking
- */
-#define T(t) cfg->timing_10_##t
-static int
-nva3_ram_timing_calc(struct nouveau_fb *pfb, u32 *timing)
-{
-	struct nva3_ram *ram = (void *)pfb->ram;
-	struct nvbios_ramcfg *cfg = &ram->base.target.bios;
-	int tUNK_base, tUNK_40_0, prevCL;
-	u32 cur2, cur3, cur7, cur8;
-
-	cur2 = nv_rd32(pfb, 0x100228);
-	cur3 = nv_rd32(pfb, 0x10022c);
-	cur7 = nv_rd32(pfb, 0x10023c);
-	cur8 = nv_rd32(pfb, 0x100240);
-
-
-	switch ((!T(CWL)) * ram->base.type) {
-	case NV_MEM_TYPE_DDR2:
-		T(CWL) = T(CL) - 1;
-		break;
-	case NV_MEM_TYPE_GDDR3:
-		T(CWL) = ((cur2 & 0xff000000) >> 24) + 1;
-		break;
-	}
-
-	prevCL = (cur3 & 0x000000ff) + 1;
-	tUNK_base = ((cur7 & 0x00ff0000) >> 16) - prevCL;
-
-	timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC));
-	timing[1] = (T(WR) + 1 + T(CWL)) << 24 |
-		    max_t(u8,T(18), 1) << 16 |
-		    (T(WTR) + 1 + T(CWL)) << 8 |
-		    (5 + T(CL) - T(CWL));
-	timing[2] = (T(CWL) - 1) << 24 |
-		    (T(RRD) << 16) |
-		    (T(RCDWR) << 8) |
-		    T(RCDRD);
-	timing[3] = (cur3 & 0x00ff0000) |
-		    (0x30 + T(CL)) << 24 |
-		    (0xb + T(CL)) << 8 |
-		    (T(CL) - 1);
-	timing[4] = T(20) << 24 |
-		    T(21) << 16 |
-		    T(13) << 8 |
-		    T(13);
-	timing[5] = T(RFC) << 24 |
-		    max_t(u8,T(RCDRD), T(RCDWR)) << 16 |
-		    max_t(u8, (T(CWL) + 6), (T(CL) + 2)) << 8 |
-		    T(RP);
-	timing[6] = (0x5a + T(CL)) << 16 |
-		    max_t(u8, 1, (6 - T(CL) + T(CWL))) << 8 |
-		    (0x50 + T(CL) - T(CWL));
-	timing[7] = (cur7 & 0xff000000) |
-		    ((tUNK_base + T(CL)) << 16) |
-		    0x202;
-	timing[8] = cur8 & 0xffffff00;
-
-	switch (ram->base.type) {
-	case NV_MEM_TYPE_DDR2:
-	case NV_MEM_TYPE_GDDR3:
-		tUNK_40_0 = prevCL - (cur8 & 0xff);
-		if (tUNK_40_0 > 0)
-			timing[8] |= T(CL);
-		break;
-	default:
-		break;
-	}
-
-	nv_debug(pfb, "Entry: 220: %08x %08x %08x %08x\n",
-			timing[0], timing[1], timing[2], timing[3]);
-	nv_debug(pfb, "  230: %08x %08x %08x %08x\n",
-			timing[4], timing[5], timing[6], timing[7]);
-	nv_debug(pfb, "  240: %08x\n", timing[8]);
-	return 0;
-}
-#undef T
-
-static void
-nouveau_sddr2_dll_reset(struct nva3_ramfuc *fuc)
-{
-	ram_mask(fuc, mr[0], 0x100, 0x100);
-	ram_nsec(fuc, 1000);
-	ram_mask(fuc, mr[0], 0x100, 0x000);
-	ram_nsec(fuc, 1000);
-}
-
-static void
-nouveau_sddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr)
-{
-	u32 mr1_old = ram_rd32(fuc, mr[1]);
-
-	if (!(mr1_old & 0x1)) {
-		ram_wr32(fuc, 0x1002d4, 0x00000001);
-		ram_wr32(fuc, mr[1], mr[1]);
-		ram_nsec(fuc, 1000);
-	}
-}
-
-static void
-nouveau_gddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr)
-{
-	u32 mr1_old = ram_rd32(fuc, mr[1]);
-
-	if (!(mr1_old & 0x40)) {
-		ram_wr32(fuc, mr[1], mr[1]);
-		ram_nsec(fuc, 1000);
-	}
-}
-
-static void
-nva3_ram_lock_pll(struct nva3_ramfuc *fuc, struct nva3_clock_info *mclk)
-{
-	ram_wr32(fuc, 0x004004, mclk->pll);
-	ram_mask(fuc, 0x004000, 0x00000001, 0x00000001);
-	ram_mask(fuc, 0x004000, 0x00000010, 0x00000000);
-	ram_wait(fuc, 0x004000, 0x00020000, 0x00020000, 64000);
-	ram_mask(fuc, 0x004000, 0x00000010, 0x00000010);
-}
-
-static void
-nva3_ram_fbvref(struct nva3_ramfuc *fuc, u32 val)
-{
-	struct nouveau_gpio *gpio = nouveau_gpio(fuc->base.pfb);
-	struct dcb_gpio_func func;
-	u32 reg, sh, gpio_val;
-	int ret;
-
-	if (gpio->get(gpio, 0, 0x2e, DCB_GPIO_UNUSED) != val) {
-		ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func);
-		if (ret)
-			return;
-
-		nv50_gpio_location(func.line, &reg, &sh);
-		gpio_val = ram_rd32(fuc, gpioFBVREF);
-		if (gpio_val & (8 << sh))
-			val = !val;
-
-		ram_mask(fuc, gpioFBVREF, (0x3 << sh), ((val | 0x2) << sh));
-		ram_nsec(fuc, 20000);
-	}
-}
-
-static int
-nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
-{
-	struct nouveau_bios *bios = nouveau_bios(pfb);
-	struct nva3_ram *ram = (void *)pfb->ram;
-	struct nva3_ramfuc *fuc = &ram->fuc;
-	struct nva3_ltrain *train = &ram->ltrain;
-	struct nva3_clock_info mclk;
-	struct nouveau_ram_data *next;
-	u8  ver, hdr, cnt, len, strap;
-	u32 data;
-	u32 r004018, r100760, r100da0, r111100, ctrl;
-	u32 unk714, unk718, unk71c;
-	int ret, i;
-	u32 timing[9];
-	bool pll2pll;
-
-	next = &ram->base.target;
-	next->freq = freq;
-	ram->base.next = next;
-
-	if (ram->ltrain.state == NVA3_TRAIN_ONCE)
-		nva3_link_train(pfb);
-
-	/* lookup memory config data relevant to the target frequency */
-	i = 0;
-	data = nvbios_rammapEm(bios, freq / 1000, &ver, &hdr, &cnt, &len,
-				      &next->bios);
-	if (!data || ver != 0x10 || hdr < 0x05) {
-		nv_error(pfb, "invalid/missing rammap entry\n");
-		return -EINVAL;
-	}
-
-	/* locate specific data set for the attached memory */
-	strap = nvbios_ramcfg_index(nv_subdev(pfb));
-	if (strap >= cnt) {
-		nv_error(pfb, "invalid ramcfg strap\n");
-		return -EINVAL;
-	}
-
-	data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, strap,
-			       &ver, &hdr, &next->bios);
-	if (!data || ver != 0x10 || hdr < 0x09) {
-		nv_error(pfb, "invalid/missing ramcfg entry\n");
-		return -EINVAL;
-	}
-
-	/* lookup memory timings, if bios says they're present */
-	if (next->bios.ramcfg_timing != 0xff) {
-		data = nvbios_timingEp(bios, next->bios.ramcfg_timing,
-				       &ver, &hdr, &cnt, &len,
-				       &next->bios);
-		if (!data || ver != 0x10 || hdr < 0x17) {
-			nv_error(pfb, "invalid/missing timing entry\n");
-			return -EINVAL;
-		}
-	}
-
-	ret = nva3_pll_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk);
-	if (ret < 0) {
-		nv_error(pfb, "failed mclk calculation\n");
-		return ret;
-	}
-
-	nva3_ram_timing_calc(pfb, timing);
-
-	ret = ram_init(fuc, pfb);
-	if (ret)
-		return ret;
-
-	/* Determine ram-specific MR values */
-	ram->base.mr[0] = ram_rd32(fuc, mr[0]);
-	ram->base.mr[1] = ram_rd32(fuc, mr[1]);
-	ram->base.mr[2] = ram_rd32(fuc, mr[2]);
-
-	switch (ram->base.type) {
-	case NV_MEM_TYPE_DDR2:
-		ret = nouveau_sddr2_calc(&ram->base);
-		break;
-	case NV_MEM_TYPE_DDR3:
-		ret = nouveau_sddr3_calc(&ram->base);
-		break;
-	case NV_MEM_TYPE_GDDR3:
-		ret = nouveau_gddr3_calc(&ram->base);
-		break;
-	default:
-		ret = -ENOSYS;
-		break;
-	}
-
-	if (ret)
-		return ret;
-
-	/* XXX: where the fuck does 750MHz come from? */
-	if (freq <= 750000) {
-		r004018 = 0x10000000;
-		r100760 = 0x22222222;
-		r100da0 = 0x00000010;
-	} else {
-		r004018 = 0x00000000;
-		r100760 = 0x00000000;
-		r100da0 = 0x00000000;
-	}
-
-	if (!next->bios.ramcfg_10_DLLoff)
-		r004018 |= 0x00004000;
-
-	/* pll2pll requires to switch to a safe clock first */
-	ctrl = ram_rd32(fuc, 0x004000);
-	pll2pll = (!(ctrl & 0x00000008)) && mclk.pll;
-
-	/* Pre, NVIDIA does this outside the script */
-	if (next->bios.ramcfg_10_02_10) {
-		ram_mask(fuc, 0x111104, 0x00000600, 0x00000000);
-	} else {
-		ram_mask(fuc, 0x111100, 0x40000000, 0x40000000);
-		ram_mask(fuc, 0x111104, 0x00000180, 0x00000000);
-	}
-	/* Always disable this bit during reclock */
-	ram_mask(fuc, 0x100200, 0x00000800, 0x00000000);
-
-	/* If switching from non-pll to pll, lock before disabling FB */
-	if (mclk.pll && !pll2pll) {
-		ram_mask(fuc, 0x004128, 0x003f3141, mclk.clk | 0x00000101);
-		nva3_ram_lock_pll(fuc, &mclk);
-	}
-
-	/* Start with disabling some CRTCs and PFIFO? */
-	ram_wait_vblank(fuc);
-	ram_wr32(fuc, 0x611200, 0x3300);
-	ram_mask(fuc, 0x002504, 0x1, 0x1);
-	ram_nsec(fuc, 10000);
-	ram_wait(fuc, 0x002504, 0x10, 0x10, 20000); /* XXX: or longer? */
-	ram_block(fuc);
-	ram_nsec(fuc, 2000);
-
-	if (!next->bios.ramcfg_10_02_10) {
-		if (ram->base.type == NV_MEM_TYPE_GDDR3)
-			ram_mask(fuc, 0x111100, 0x04020000, 0x00020000);
-		else
-			ram_mask(fuc, 0x111100, 0x04020000, 0x04020000);
-	}
-
-	/* If we're disabling the DLL, do it now */
-	switch (next->bios.ramcfg_10_DLLoff * ram->base.type) {
-	case NV_MEM_TYPE_DDR3:
-		nouveau_sddr3_dll_disable(fuc, ram->base.mr);
-		break;
-	case NV_MEM_TYPE_GDDR3:
-		nouveau_gddr3_dll_disable(fuc, ram->base.mr);
-		break;
-	}
-
-	if (fuc->r_gpioFBVREF.addr && next->bios.timing_10_ODT)
-		nva3_ram_fbvref(fuc, 0);
-
-	/* Brace RAM for impact */
-	ram_wr32(fuc, 0x1002d4, 0x00000001);
-	ram_wr32(fuc, 0x1002d0, 0x00000001);
-	ram_wr32(fuc, 0x1002d0, 0x00000001);
-	ram_wr32(fuc, 0x100210, 0x00000000);
-	ram_wr32(fuc, 0x1002dc, 0x00000001);
-	ram_nsec(fuc, 2000);
-
-	if (nv_device(pfb)->chipset == 0xa3 && freq <= 500000)
-		ram_mask(fuc, 0x100700, 0x00000006, 0x00000006);
-
-	/* Fiddle with clocks */
-	/* There's 4 scenario's
-	 * pll->pll: first switch to a 324MHz clock, set up new PLL, switch
-	 * clk->pll: Set up new PLL, switch
-	 * pll->clk: Set up clock, switch
-	 * clk->clk: Overwrite ctrl and other bits, switch */
-
-	/* Switch to regular clock - 324MHz */
-	if (pll2pll) {
-		ram_mask(fuc, 0x004000, 0x00000004, 0x00000004);
-		ram_mask(fuc, 0x004168, 0x003f3141, 0x00083101);
-		ram_mask(fuc, 0x004000, 0x00000008, 0x00000008);
-		ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
-		ram_wr32(fuc, 0x004018, 0x00001000);
-		nva3_ram_lock_pll(fuc, &mclk);
-	}
-
-	if (mclk.pll) {
-		ram_mask(fuc, 0x004000, 0x00000105, 0x00000105);
-		ram_wr32(fuc, 0x004018, 0x00001000 | r004018);
-		ram_wr32(fuc, 0x100da0, r100da0);
-	} else {
-		ram_mask(fuc, 0x004168, 0x003f3141, mclk.clk | 0x00000101);
-		ram_mask(fuc, 0x004000, 0x00000108, 0x00000008);
-		ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
-		ram_wr32(fuc, 0x004018, 0x00009000 | r004018);
-		ram_wr32(fuc, 0x100da0, r100da0);
-	}
-	ram_nsec(fuc, 20000);
-
-	if (next->bios.rammap_10_04_08) {
-		ram_wr32(fuc, 0x1005a0, next->bios.ramcfg_10_06 << 16 |
-					next->bios.ramcfg_10_05 << 8 |
-					next->bios.ramcfg_10_05);
-		ram_wr32(fuc, 0x1005a4, next->bios.ramcfg_10_08 << 8 |
-					next->bios.ramcfg_10_07);
-		ram_wr32(fuc, 0x10f804, next->bios.ramcfg_10_09_f0 << 20 |
-					next->bios.ramcfg_10_03_0f << 16 |
-					next->bios.ramcfg_10_09_0f |
-					0x80000000);
-		ram_mask(fuc, 0x10053c, 0x00001000, 0x00000000);
-	} else {
-		if (train->state == NVA3_TRAIN_DONE) {
-			ram_wr32(fuc, 0x100080, 0x1020);
-			ram_mask(fuc, 0x111400, 0xffffffff, train->r_111400);
-			ram_mask(fuc, 0x1111e0, 0xffffffff, train->r_1111e0);
-			ram_mask(fuc, 0x100720, 0xffffffff, train->r_100720);
-		}
-		ram_mask(fuc, 0x10053c, 0x00001000, 0x00001000);
-		ram_mask(fuc, 0x10f804, 0x80000000, 0x00000000);
-		ram_mask(fuc, 0x100760, 0x22222222, r100760);
-		ram_mask(fuc, 0x1007a0, 0x22222222, r100760);
-		ram_mask(fuc, 0x1007e0, 0x22222222, r100760);
-	}
-
-	if (nv_device(pfb)->chipset == 0xa3 && freq > 500000) {
-		ram_mask(fuc, 0x100700, 0x00000006, 0x00000000);
-	}
-
-	/* Final switch */
-	if (mclk.pll) {
-		ram_mask(fuc, 0x1110e0, 0x00088000, 0x00011000);
-		ram_mask(fuc, 0x004000, 0x00000008, 0x00000000);
-	}
-
-	ram_wr32(fuc, 0x1002dc, 0x00000000);
-	ram_wr32(fuc, 0x1002d4, 0x00000001);
-	ram_wr32(fuc, 0x100210, 0x80000000);
-	ram_nsec(fuc, 2000);
-
-	/* Set RAM MR parameters and timings */
-	for (i = 2; i >= 0; i--) {
-		if (ram_rd32(fuc, mr[i]) != ram->base.mr[i]) {
-			ram_wr32(fuc, mr[i], ram->base.mr[i]);
-			ram_nsec(fuc, 1000);
-		}
-	}
-
-	ram_wr32(fuc, 0x100220[3], timing[3]);
-	ram_wr32(fuc, 0x100220[1], timing[1]);
-	ram_wr32(fuc, 0x100220[6], timing[6]);
-	ram_wr32(fuc, 0x100220[7], timing[7]);
-	ram_wr32(fuc, 0x100220[2], timing[2]);
-	ram_wr32(fuc, 0x100220[4], timing[4]);
-	ram_wr32(fuc, 0x100220[5], timing[5]);
-	ram_wr32(fuc, 0x100220[0], timing[0]);
-	ram_wr32(fuc, 0x100220[8], timing[8]);
-
-	/* Misc */
-	ram_mask(fuc, 0x100200, 0x00001000, !next->bios.ramcfg_10_02_08 << 12);
-
-	/* XXX: A lot of "chipset"/"ram type" specific stuff...? */
-	unk714  = ram_rd32(fuc, 0x100714) & ~0xf0000130;
-	unk718  = ram_rd32(fuc, 0x100718) & ~0x00000100;
-	unk71c  = ram_rd32(fuc, 0x10071c) & ~0x00000100;
-	r111100 = ram_rd32(fuc, 0x111100) & ~0x3a800000;
-
-	if (next->bios.ramcfg_10_02_04) {
-		switch (ram->base.type) {
-		case NV_MEM_TYPE_DDR3:
-			if (nv_device(pfb)->chipset != 0xa8)
-				r111100 |= 0x00000004;
-			/* no break */
-		case NV_MEM_TYPE_DDR2:
-			r111100 |= 0x08000000;
-			break;
-		default:
-			break;
-		}
-	} else {
-		switch (ram->base.type) {
-		case NV_MEM_TYPE_DDR2:
-			r111100 |= 0x1a800000;
-			unk714  |= 0x00000010;
-			break;
-		case NV_MEM_TYPE_DDR3:
-			if (nv_device(pfb)->chipset == 0xa8) {
-				r111100 |=  0x08000000;
-			} else {
-				r111100 &= ~0x00000004;
-				r111100 |=  0x12800000;
-			}
-			unk714  |= 0x00000010;
-			break;
-		case NV_MEM_TYPE_GDDR3:
-			r111100 |= 0x30000000;
-			unk714  |= 0x00000020;
-			break;
-		default:
-			break;
-		}
-	}
-
-	unk714 |= (next->bios.ramcfg_10_04_01) << 8;
-
-	if (next->bios.ramcfg_10_02_20)
-		unk714 |= 0xf0000000;
-	if (next->bios.ramcfg_10_02_02)
-		unk718 |= 0x00000100;
-	if (next->bios.ramcfg_10_02_01)
-		unk71c |= 0x00000100;
-	if (next->bios.timing_10_24 != 0xff) {
-		unk718 &= ~0xf0000000;
-		unk718 |= next->bios.timing_10_24 << 28;
-	}
-	if (next->bios.ramcfg_10_02_10)
-		r111100 &= ~0x04020000;
-
-	ram_mask(fuc, 0x100714, 0xffffffff, unk714);
-	ram_mask(fuc, 0x10071c, 0xffffffff, unk71c);
-	ram_mask(fuc, 0x100718, 0xffffffff, unk718);
-	ram_mask(fuc, 0x111100, 0xffffffff, r111100);
-
-	if (fuc->r_gpioFBVREF.addr && !next->bios.timing_10_ODT)
-		nva3_ram_fbvref(fuc, 1);
-
-	/* Reset DLL */
-	if (!next->bios.ramcfg_10_DLLoff)
-		nouveau_sddr2_dll_reset(fuc);
-
-	if (ram->base.type == NV_MEM_TYPE_GDDR3) {
-		ram_nsec(fuc, 31000);
-	} else {
-		ram_nsec(fuc, 14000);
-	}
-
-	if (ram->base.type == NV_MEM_TYPE_DDR3) {
-		ram_wr32(fuc, 0x100264, 0x1);
-		ram_nsec(fuc, 2000);
-	}
-
-	ram_nuke(fuc, 0x100700);
-	ram_mask(fuc, 0x100700, 0x01000000, 0x01000000);
-	ram_mask(fuc, 0x100700, 0x01000000, 0x00000000);
-
-	/* Re-enable FB */
-	ram_unblock(fuc);
-	ram_wr32(fuc, 0x611200, 0x3330);
-
-	/* Post fiddlings */
-	if (next->bios.rammap_10_04_02)
-		ram_mask(fuc, 0x100200, 0x00000800, 0x00000800);
-	if (next->bios.ramcfg_10_02_10) {
-		ram_mask(fuc, 0x111104, 0x00000180, 0x00000180);
-		ram_mask(fuc, 0x111100, 0x40000000, 0x00000000);
-	} else {
-		ram_mask(fuc, 0x111104, 0x00000600, 0x00000600);
-	}
-
-	if (mclk.pll) {
-		ram_mask(fuc, 0x004168, 0x00000001, 0x00000000);
-		ram_mask(fuc, 0x004168, 0x00000100, 0x00000000);
-	} else {
-		ram_mask(fuc, 0x004000, 0x00000001, 0x00000000);
-		ram_mask(fuc, 0x004128, 0x00000001, 0x00000000);
-		ram_mask(fuc, 0x004128, 0x00000100, 0x00000000);
-	}
-
-	return 0;
-}
-
-static int
-nva3_ram_prog(struct nouveau_fb *pfb)
-{
-	struct nouveau_device *device = nv_device(pfb);
-	struct nva3_ram *ram = (void *)pfb->ram;
-	struct nva3_ramfuc *fuc = &ram->fuc;
-	bool exec = nouveau_boolopt(device->cfgopt, "NvMemExec", true);
-
-	if (exec) {
-		nv_mask(pfb, 0x001534, 0x2, 0x2);
-
-		ram_exec(fuc, true);
-
-		/* Post-processing, avoids flicker */
-		nv_mask(pfb, 0x002504, 0x1, 0x0);
-		nv_mask(pfb, 0x001534, 0x2, 0x0);
-
-		nv_mask(pfb, 0x616308, 0x10, 0x10);
-		nv_mask(pfb, 0x616b08, 0x10, 0x10);
-	} else {
-		ram_exec(fuc, false);
-	}
-	return 0;
-}
-
-static void
-nva3_ram_tidy(struct nouveau_fb *pfb)
-{
-	struct nva3_ram *ram = (void *)pfb->ram;
-	struct nva3_ramfuc *fuc = &ram->fuc;
-	ram_exec(fuc, false);
-}
-
-static int
-nva3_ram_init(struct nouveau_object *object)
-{
-	struct nouveau_fb *pfb = (void *)object->parent;
-	struct nva3_ram   *ram = (void *)object;
-	int ret;
-
-	ret = nouveau_ram_init(&ram->base);
-	if (ret)
-		return ret;
-
-	nva3_link_train_init(pfb);
-
-	return 0;
-}
-
-static int
-nva3_ram_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nouveau_fb *pfb = (void *)object->parent;
-
-	if (!suspend)
-		nva3_link_train_fini(pfb);
-
-	return 0;
-}
-
-static int
-nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 datasize,
-	      struct nouveau_object **pobject)
-{
-	struct nouveau_fb *pfb = nouveau_fb(parent);
-	struct nouveau_gpio *gpio = nouveau_gpio(pfb);
-	struct dcb_gpio_func func;
-	struct nva3_ram *ram;
-	int ret, i;
-	u32 reg, shift;
-
-	ret = nv50_ram_create(parent, engine, oclass, &ram);
-	*pobject = nv_object(ram);
-	if (ret)
-		return ret;
-
-	switch (ram->base.type) {
-	case NV_MEM_TYPE_DDR2:
-	case NV_MEM_TYPE_DDR3:
-	case NV_MEM_TYPE_GDDR3:
-		ram->base.calc = nva3_ram_calc;
-		ram->base.prog = nva3_ram_prog;
-		ram->base.tidy = nva3_ram_tidy;
-		break;
-	default:
-		nv_warn(ram, "reclocking of this ram type unsupported\n");
-		return 0;
-	}
-
-	ram->fuc.r_0x001610 = ramfuc_reg(0x001610);
-	ram->fuc.r_0x001700 = ramfuc_reg(0x001700);
-	ram->fuc.r_0x002504 = ramfuc_reg(0x002504);
-	ram->fuc.r_0x004000 = ramfuc_reg(0x004000);
-	ram->fuc.r_0x004004 = ramfuc_reg(0x004004);
-	ram->fuc.r_0x004018 = ramfuc_reg(0x004018);
-	ram->fuc.r_0x004128 = ramfuc_reg(0x004128);
-	ram->fuc.r_0x004168 = ramfuc_reg(0x004168);
-	ram->fuc.r_0x100080 = ramfuc_reg(0x100080);
-	ram->fuc.r_0x100200 = ramfuc_reg(0x100200);
-	ram->fuc.r_0x100210 = ramfuc_reg(0x100210);
-	for (i = 0; i < 9; i++)
-		ram->fuc.r_0x100220[i] = ramfuc_reg(0x100220 + (i * 4));
-	ram->fuc.r_0x100264 = ramfuc_reg(0x100264);
-	ram->fuc.r_0x1002d0 = ramfuc_reg(0x1002d0);
-	ram->fuc.r_0x1002d4 = ramfuc_reg(0x1002d4);
-	ram->fuc.r_0x1002dc = ramfuc_reg(0x1002dc);
-	ram->fuc.r_0x10053c = ramfuc_reg(0x10053c);
-	ram->fuc.r_0x1005a0 = ramfuc_reg(0x1005a0);
-	ram->fuc.r_0x1005a4 = ramfuc_reg(0x1005a4);
-	ram->fuc.r_0x100700 = ramfuc_reg(0x100700);
-	ram->fuc.r_0x100714 = ramfuc_reg(0x100714);
-	ram->fuc.r_0x100718 = ramfuc_reg(0x100718);
-	ram->fuc.r_0x10071c = ramfuc_reg(0x10071c);
-	ram->fuc.r_0x100720 = ramfuc_reg(0x100720);
-	ram->fuc.r_0x100760 = ramfuc_stride(0x100760, 4, ram->base.part_mask);
-	ram->fuc.r_0x1007a0 = ramfuc_stride(0x1007a0, 4, ram->base.part_mask);
-	ram->fuc.r_0x1007e0 = ramfuc_stride(0x1007e0, 4, ram->base.part_mask);
-	ram->fuc.r_0x100da0 = ramfuc_stride(0x100da0, 4, ram->base.part_mask);
-	ram->fuc.r_0x10f804 = ramfuc_reg(0x10f804);
-	ram->fuc.r_0x1110e0 = ramfuc_stride(0x1110e0, 4, ram->base.part_mask);
-	ram->fuc.r_0x111100 = ramfuc_reg(0x111100);
-	ram->fuc.r_0x111104 = ramfuc_reg(0x111104);
-	ram->fuc.r_0x1111e0 = ramfuc_reg(0x1111e0);
-	ram->fuc.r_0x111400 = ramfuc_reg(0x111400);
-	ram->fuc.r_0x611200 = ramfuc_reg(0x611200);
-
-	if (ram->base.ranks > 1) {
-		ram->fuc.r_mr[0] = ramfuc_reg2(0x1002c0, 0x1002c8);
-		ram->fuc.r_mr[1] = ramfuc_reg2(0x1002c4, 0x1002cc);
-		ram->fuc.r_mr[2] = ramfuc_reg2(0x1002e0, 0x1002e8);
-		ram->fuc.r_mr[3] = ramfuc_reg2(0x1002e4, 0x1002ec);
-	} else {
-		ram->fuc.r_mr[0] = ramfuc_reg(0x1002c0);
-		ram->fuc.r_mr[1] = ramfuc_reg(0x1002c4);
-		ram->fuc.r_mr[2] = ramfuc_reg(0x1002e0);
-		ram->fuc.r_mr[3] = ramfuc_reg(0x1002e4);
-	}
-
-	ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func);
-	if (ret == 0) {
-		nv50_gpio_location(func.line, &reg, &shift);
-		ram->fuc.r_gpioFBVREF = ramfuc_reg(reg);
-	}
-
-	return 0;
-}
-
-struct nouveau_oclass
-nva3_ram_oclass = {
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nva3_ram_ctor,
-		.dtor = _nouveau_ram_dtor,
-		.init = nva3_ram_init,
-		.fini = nva3_ram_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvaa.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvaa.c
deleted file mode 100644
index 033a8e999497..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvaa.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv50.h"
-
-struct nvaa_ram_priv {
-	struct nouveau_ram base;
-	u64 poller_base;
-};
-
-static int
-nvaa_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 datasize,
-	      struct nouveau_object **pobject)
-{
-	u32 rsvd_head = ( 256 * 1024); /* vga memory */
-	u32 rsvd_tail = (1024 * 1024); /* vbios etc */
-	struct nouveau_fb *pfb = nouveau_fb(parent);
-	struct nvaa_ram_priv *priv;
-	int ret;
-
-	ret = nouveau_ram_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.type   = NV_MEM_TYPE_STOLEN;
-	priv->base.stolen = (u64)nv_rd32(pfb, 0x100e10) << 12;
-	priv->base.size   = (u64)nv_rd32(pfb, 0x100e14) << 12;
-
-	rsvd_tail += 0x1000;
-	priv->poller_base = priv->base.size - rsvd_tail;
-
-	ret = nouveau_mm_init(&pfb->vram, rsvd_head >> 12,
-			      (priv->base.size  - (rsvd_head + rsvd_tail)) >> 12,
-			      1);
-	if (ret)
-		return ret;
-
-	priv->base.get = nv50_ram_get;
-	priv->base.put = nv50_ram_put;
-	return 0;
-}
-
-static int
-nvaa_ram_init(struct nouveau_object *object)
-{
-	struct nouveau_fb *pfb = nouveau_fb(object);
-	struct nvaa_ram_priv *priv = (void *)object;
-	int ret;
-	u64 dniso, hostnb, flush;
-
-	ret = nouveau_ram_init(&priv->base);
-	if (ret)
-		return ret;
-
-	dniso  = ((priv->base.size - (priv->poller_base + 0x00)) >> 5) - 1;
-	hostnb = ((priv->base.size - (priv->poller_base + 0x20)) >> 5) - 1;
-	flush  = ((priv->base.size - (priv->poller_base + 0x40)) >> 5) - 1;
-
-	/* Enable NISO poller for various clients and set their associated
-	 * read address, only for MCP77/78 and MCP79/7A. (fd#25701)
-	 */
-	nv_wr32(pfb, 0x100c18, dniso);
-	nv_mask(pfb, 0x100c14, 0x00000000, 0x00000001);
-	nv_wr32(pfb, 0x100c1c, hostnb);
-	nv_mask(pfb, 0x100c14, 0x00000000, 0x00000002);
-	nv_wr32(pfb, 0x100c24, flush);
-	nv_mask(pfb, 0x100c14, 0x00000000, 0x00010000);
-
-	return 0;
-}
-
-struct nouveau_oclass
-nvaa_ram_oclass = {
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvaa_ram_ctor,
-		.dtor = _nouveau_ram_dtor,
-		.init = nvaa_ram_init,
-		.fini = _nouveau_ram_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
deleted file mode 100644
index 735cb9580abe..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
+++ /dev/null
@@ -1,733 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/pll.h>
-#include <subdev/bios/rammap.h>
-#include <subdev/bios/timing.h>
-#include <subdev/ltc.h>
-
-#include <subdev/clock.h>
-#include <subdev/clock/pll.h>
-
-#include <core/option.h>
-
-#include "ramfuc.h"
-
-#include "nvc0.h"
-
-struct nvc0_ramfuc {
-	struct ramfuc base;
-
-	struct ramfuc_reg r_0x10fe20;
-	struct ramfuc_reg r_0x10fe24;
-	struct ramfuc_reg r_0x137320;
-	struct ramfuc_reg r_0x137330;
-
-	struct ramfuc_reg r_0x132000;
-	struct ramfuc_reg r_0x132004;
-	struct ramfuc_reg r_0x132100;
-
-	struct ramfuc_reg r_0x137390;
-
-	struct ramfuc_reg r_0x10f290;
-	struct ramfuc_reg r_0x10f294;
-	struct ramfuc_reg r_0x10f298;
-	struct ramfuc_reg r_0x10f29c;
-	struct ramfuc_reg r_0x10f2a0;
-
-	struct ramfuc_reg r_0x10f300;
-	struct ramfuc_reg r_0x10f338;
-	struct ramfuc_reg r_0x10f340;
-	struct ramfuc_reg r_0x10f344;
-	struct ramfuc_reg r_0x10f348;
-
-	struct ramfuc_reg r_0x10f910;
-	struct ramfuc_reg r_0x10f914;
-
-	struct ramfuc_reg r_0x100b0c;
-	struct ramfuc_reg r_0x10f050;
-	struct ramfuc_reg r_0x10f090;
-	struct ramfuc_reg r_0x10f200;
-	struct ramfuc_reg r_0x10f210;
-	struct ramfuc_reg r_0x10f310;
-	struct ramfuc_reg r_0x10f314;
-	struct ramfuc_reg r_0x10f610;
-	struct ramfuc_reg r_0x10f614;
-	struct ramfuc_reg r_0x10f800;
-	struct ramfuc_reg r_0x10f808;
-	struct ramfuc_reg r_0x10f824;
-	struct ramfuc_reg r_0x10f830;
-	struct ramfuc_reg r_0x10f988;
-	struct ramfuc_reg r_0x10f98c;
-	struct ramfuc_reg r_0x10f990;
-	struct ramfuc_reg r_0x10f998;
-	struct ramfuc_reg r_0x10f9b0;
-	struct ramfuc_reg r_0x10f9b4;
-	struct ramfuc_reg r_0x10fb04;
-	struct ramfuc_reg r_0x10fb08;
-	struct ramfuc_reg r_0x137300;
-	struct ramfuc_reg r_0x137310;
-	struct ramfuc_reg r_0x137360;
-	struct ramfuc_reg r_0x1373ec;
-	struct ramfuc_reg r_0x1373f0;
-	struct ramfuc_reg r_0x1373f8;
-
-	struct ramfuc_reg r_0x61c140;
-	struct ramfuc_reg r_0x611200;
-
-	struct ramfuc_reg r_0x13d8f4;
-};
-
-struct nvc0_ram {
-	struct nouveau_ram base;
-	struct nvc0_ramfuc fuc;
-	struct nvbios_pll refpll;
-	struct nvbios_pll mempll;
-};
-
-static void
-nvc0_ram_train(struct nvc0_ramfuc *fuc, u32 magic)
-{
-	struct nvc0_ram *ram = container_of(fuc, typeof(*ram), fuc);
-	struct nouveau_fb *pfb = nouveau_fb(ram);
-	u32 part = nv_rd32(pfb, 0x022438), i;
-	u32 mask = nv_rd32(pfb, 0x022554);
-	u32 addr = 0x110974;
-
-	ram_wr32(fuc, 0x10f910, magic);
-	ram_wr32(fuc, 0x10f914, magic);
-
-	for (i = 0; (magic & 0x80000000) && i < part; addr += 0x1000, i++) {
-		if (mask & (1 << i))
-			continue;
-		ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);
-	}
-}
-
-static int
-nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
-{
-	struct nouveau_clock *clk = nouveau_clock(pfb);
-	struct nouveau_bios *bios = nouveau_bios(pfb);
-	struct nvc0_ram *ram = (void *)pfb->ram;
-	struct nvc0_ramfuc *fuc = &ram->fuc;
-	struct nvbios_ramcfg cfg;
-	u8  ver, cnt, len, strap;
-	struct {
-		u32 data;
-		u8  size;
-	} rammap, ramcfg, timing;
-	int ref, div, out;
-	int from, mode;
-	int N1, M1, P;
-	int ret;
-
-	/* lookup memory config data relevant to the target frequency */
-	rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size,
-				     &cnt, &ramcfg.size, &cfg);
-	if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) {
-		nv_error(pfb, "invalid/missing rammap entry\n");
-		return -EINVAL;
-	}
-
-	/* locate specific data set for the attached memory */
-	strap = nvbios_ramcfg_index(nv_subdev(pfb));
-	if (strap >= cnt) {
-		nv_error(pfb, "invalid ramcfg strap\n");
-		return -EINVAL;
-	}
-
-	ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size);
-	if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) {
-		nv_error(pfb, "invalid/missing ramcfg entry\n");
-		return -EINVAL;
-	}
-
-	/* lookup memory timings, if bios says they're present */
-	strap = nv_ro08(bios, ramcfg.data + 0x01);
-	if (strap != 0xff) {
-		timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size,
-					     &cnt, &len);
-		if (!timing.data || ver != 0x10 || timing.size < 0x19) {
-			nv_error(pfb, "invalid/missing timing entry\n");
-			return -EINVAL;
-		}
-	} else {
-		timing.data = 0;
-	}
-
-	ret = ram_init(fuc, pfb);
-	if (ret)
-		return ret;
-
-	/* determine current mclk configuration */
-	from = !!(ram_rd32(fuc, 0x1373f0) & 0x00000002); /*XXX: ok? */
-
-	/* determine target mclk configuration */
-	if (!(ram_rd32(fuc, 0x137300) & 0x00000100))
-		ref = clk->read(clk, nv_clk_src_sppll0);
-	else
-		ref = clk->read(clk, nv_clk_src_sppll1);
-	div = max(min((ref * 2) / freq, (u32)65), (u32)2) - 2;
-	out = (ref * 2) / (div + 2);
-	mode = freq != out;
-
-	ram_mask(fuc, 0x137360, 0x00000002, 0x00000000);
-
-	if ((ram_rd32(fuc, 0x132000) & 0x00000002) || 0 /*XXX*/) {
-		ram_nuke(fuc, 0x132000);
-		ram_mask(fuc, 0x132000, 0x00000002, 0x00000002);
-		ram_mask(fuc, 0x132000, 0x00000002, 0x00000000);
-	}
-
-	if (mode == 1) {
-		ram_nuke(fuc, 0x10fe20);
-		ram_mask(fuc, 0x10fe20, 0x00000002, 0x00000002);
-		ram_mask(fuc, 0x10fe20, 0x00000002, 0x00000000);
-	}
-
-// 0x00020034 // 0x0000000a
-	ram_wr32(fuc, 0x132100, 0x00000001);
-
-	if (mode == 1 && from == 0) {
-		/* calculate refpll */
-		ret = nva3_pll_calc(nv_subdev(pfb), &ram->refpll,
-				    ram->mempll.refclk, &N1, NULL, &M1, &P);
-		if (ret <= 0) {
-			nv_error(pfb, "unable to calc refpll\n");
-			return ret ? ret : -ERANGE;
-		}
-
-		ram_wr32(fuc, 0x10fe20, 0x20010000);
-		ram_wr32(fuc, 0x137320, 0x00000003);
-		ram_wr32(fuc, 0x137330, 0x81200006);
-		ram_wr32(fuc, 0x10fe24, (P << 16) | (N1 << 8) | M1);
-		ram_wr32(fuc, 0x10fe20, 0x20010001);
-		ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
-
-		/* calculate mempll */
-		ret = nva3_pll_calc(nv_subdev(pfb), &ram->mempll, freq,
-				   &N1, NULL, &M1, &P);
-		if (ret <= 0) {
-			nv_error(pfb, "unable to calc refpll\n");
-			return ret ? ret : -ERANGE;
-		}
-
-		ram_wr32(fuc, 0x10fe20, 0x20010005);
-		ram_wr32(fuc, 0x132004, (P << 16) | (N1 << 8) | M1);
-		ram_wr32(fuc, 0x132000, 0x18010101);
-		ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);
-	} else
-	if (mode == 0) {
-		ram_wr32(fuc, 0x137300, 0x00000003);
-	}
-
-	if (from == 0) {
-		ram_nuke(fuc, 0x10fb04);
-		ram_mask(fuc, 0x10fb04, 0x0000ffff, 0x00000000);
-		ram_nuke(fuc, 0x10fb08);
-		ram_mask(fuc, 0x10fb08, 0x0000ffff, 0x00000000);
-		ram_wr32(fuc, 0x10f988, 0x2004ff00);
-		ram_wr32(fuc, 0x10f98c, 0x003fc040);
-		ram_wr32(fuc, 0x10f990, 0x20012001);
-		ram_wr32(fuc, 0x10f998, 0x00011a00);
-		ram_wr32(fuc, 0x13d8f4, 0x00000000);
-	} else {
-		ram_wr32(fuc, 0x10f988, 0x20010000);
-		ram_wr32(fuc, 0x10f98c, 0x00000000);
-		ram_wr32(fuc, 0x10f990, 0x20012001);
-		ram_wr32(fuc, 0x10f998, 0x00010a00);
-	}
-
-	if (from == 0) {
-// 0x00020039 // 0x000000ba
-	}
-
-// 0x0002003a // 0x00000002
-	ram_wr32(fuc, 0x100b0c, 0x00080012);
-// 0x00030014 // 0x00000000 // 0x02b5f070
-// 0x00030014 // 0x00010000 // 0x02b5f070
-	ram_wr32(fuc, 0x611200, 0x00003300);
-// 0x00020034 // 0x0000000a
-// 0x00030020 // 0x00000001 // 0x00000000
-
-	ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
-	ram_wr32(fuc, 0x10f210, 0x00000000);
-	ram_nsec(fuc, 1000);
-	if (mode == 0)
-		nvc0_ram_train(fuc, 0x000c1001);
-	ram_wr32(fuc, 0x10f310, 0x00000001);
-	ram_nsec(fuc, 1000);
-	ram_wr32(fuc, 0x10f090, 0x00000061);
-	ram_wr32(fuc, 0x10f090, 0xc000007f);
-	ram_nsec(fuc, 1000);
-
-	if (from == 0) {
-		ram_wr32(fuc, 0x10f824, 0x00007fd4);
-	} else {
-		ram_wr32(fuc, 0x1373ec, 0x00020404);
-	}
-
-	if (mode == 0) {
-		ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
-		ram_mask(fuc, 0x10f200, 0x00008000, 0x00008000);
-		ram_wr32(fuc, 0x10f830, 0x41500010);
-		ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
-		ram_mask(fuc, 0x132100, 0x00000100, 0x00000100);
-		ram_wr32(fuc, 0x10f050, 0xff000090);
-		ram_wr32(fuc, 0x1373ec, 0x00020f0f);
-		ram_wr32(fuc, 0x1373f0, 0x00000003);
-		ram_wr32(fuc, 0x137310, 0x81201616);
-		ram_wr32(fuc, 0x132100, 0x00000001);
-// 0x00020039 // 0x000000ba
-		ram_wr32(fuc, 0x10f830, 0x00300017);
-		ram_wr32(fuc, 0x1373f0, 0x00000001);
-		ram_wr32(fuc, 0x10f824, 0x00007e77);
-		ram_wr32(fuc, 0x132000, 0x18030001);
-		ram_wr32(fuc, 0x10f090, 0x4000007e);
-		ram_nsec(fuc, 2000);
-		ram_wr32(fuc, 0x10f314, 0x00000001);
-		ram_wr32(fuc, 0x10f210, 0x80000000);
-		ram_wr32(fuc, 0x10f338, 0x00300220);
-		ram_wr32(fuc, 0x10f300, 0x0000011d);
-		ram_nsec(fuc, 1000);
-		ram_wr32(fuc, 0x10f290, 0x02060505);
-		ram_wr32(fuc, 0x10f294, 0x34208288);
-		ram_wr32(fuc, 0x10f298, 0x44050411);
-		ram_wr32(fuc, 0x10f29c, 0x0000114c);
-		ram_wr32(fuc, 0x10f2a0, 0x42e10069);
-		ram_wr32(fuc, 0x10f614, 0x40044f77);
-		ram_wr32(fuc, 0x10f610, 0x40044f77);
-		ram_wr32(fuc, 0x10f344, 0x00600009);
-		ram_nsec(fuc, 1000);
-		ram_wr32(fuc, 0x10f348, 0x00700008);
-		ram_wr32(fuc, 0x61c140, 0x19240000);
-		ram_wr32(fuc, 0x10f830, 0x00300017);
-		nvc0_ram_train(fuc, 0x80021001);
-		nvc0_ram_train(fuc, 0x80081001);
-		ram_wr32(fuc, 0x10f340, 0x00500004);
-		ram_nsec(fuc, 1000);
-		ram_wr32(fuc, 0x10f830, 0x01300017);
-		ram_wr32(fuc, 0x10f830, 0x00300017);
-// 0x00030020 // 0x00000000 // 0x00000000
-// 0x00020034 // 0x0000000b
-		ram_wr32(fuc, 0x100b0c, 0x00080028);
-		ram_wr32(fuc, 0x611200, 0x00003330);
-	} else {
-		ram_wr32(fuc, 0x10f800, 0x00001800);
-		ram_wr32(fuc, 0x13d8f4, 0x00000000);
-		ram_wr32(fuc, 0x1373ec, 0x00020404);
-		ram_wr32(fuc, 0x1373f0, 0x00000003);
-		ram_wr32(fuc, 0x10f830, 0x40700010);
-		ram_wr32(fuc, 0x10f830, 0x40500010);
-		ram_wr32(fuc, 0x13d8f4, 0x00000000);
-		ram_wr32(fuc, 0x1373f8, 0x00000000);
-		ram_wr32(fuc, 0x132100, 0x00000101);
-		ram_wr32(fuc, 0x137310, 0x89201616);
-		ram_wr32(fuc, 0x10f050, 0xff000090);
-		ram_wr32(fuc, 0x1373ec, 0x00030404);
-		ram_wr32(fuc, 0x1373f0, 0x00000002);
-	// 0x00020039 // 0x00000011
-		ram_wr32(fuc, 0x132100, 0x00000001);
-		ram_wr32(fuc, 0x1373f8, 0x00002000);
-		ram_nsec(fuc, 2000);
-		ram_wr32(fuc, 0x10f808, 0x7aaa0050);
-		ram_wr32(fuc, 0x10f830, 0x00500010);
-		ram_wr32(fuc, 0x10f200, 0x00ce1000);
-		ram_wr32(fuc, 0x10f090, 0x4000007e);
-		ram_nsec(fuc, 2000);
-		ram_wr32(fuc, 0x10f314, 0x00000001);
-		ram_wr32(fuc, 0x10f210, 0x80000000);
-		ram_wr32(fuc, 0x10f338, 0x00300200);
-		ram_wr32(fuc, 0x10f300, 0x0000084d);
-		ram_nsec(fuc, 1000);
-		ram_wr32(fuc, 0x10f290, 0x0b343825);
-		ram_wr32(fuc, 0x10f294, 0x3483028e);
-		ram_wr32(fuc, 0x10f298, 0x440c0600);
-		ram_wr32(fuc, 0x10f29c, 0x0000214c);
-		ram_wr32(fuc, 0x10f2a0, 0x42e20069);
-		ram_wr32(fuc, 0x10f200, 0x00ce0000);
-		ram_wr32(fuc, 0x10f614, 0x60044e77);
-		ram_wr32(fuc, 0x10f610, 0x60044e77);
-		ram_wr32(fuc, 0x10f340, 0x00500000);
-		ram_nsec(fuc, 1000);
-		ram_wr32(fuc, 0x10f344, 0x00600228);
-		ram_nsec(fuc, 1000);
-		ram_wr32(fuc, 0x10f348, 0x00700000);
-		ram_wr32(fuc, 0x13d8f4, 0x00000000);
-		ram_wr32(fuc, 0x61c140, 0x09a40000);
-
-		nvc0_ram_train(fuc, 0x800e1008);
-
-		ram_nsec(fuc, 1000);
-		ram_wr32(fuc, 0x10f800, 0x00001804);
-	// 0x00030020 // 0x00000000 // 0x00000000
-	// 0x00020034 // 0x0000000b
-		ram_wr32(fuc, 0x13d8f4, 0x00000000);
-		ram_wr32(fuc, 0x100b0c, 0x00080028);
-		ram_wr32(fuc, 0x611200, 0x00003330);
-		ram_nsec(fuc, 100000);
-		ram_wr32(fuc, 0x10f9b0, 0x05313f41);
-		ram_wr32(fuc, 0x10f9b4, 0x00002f50);
-
-		nvc0_ram_train(fuc, 0x010c1001);
-	}
-
-	ram_mask(fuc, 0x10f200, 0x00000800, 0x00000800);
-// 0x00020016 // 0x00000000
-
-	if (mode == 0)
-		ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
-	return 0;
-}
-
-static int
-nvc0_ram_prog(struct nouveau_fb *pfb)
-{
-	struct nouveau_device *device = nv_device(pfb);
-	struct nvc0_ram *ram = (void *)pfb->ram;
-	struct nvc0_ramfuc *fuc = &ram->fuc;
-	ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", true));
-	return 0;
-}
-
-static void
-nvc0_ram_tidy(struct nouveau_fb *pfb)
-{
-	struct nvc0_ram *ram = (void *)pfb->ram;
-	struct nvc0_ramfuc *fuc = &ram->fuc;
-	ram_exec(fuc, false);
-}
-
-extern const u8 nvc0_pte_storage_type_map[256];
-
-void
-nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
-{
-	struct nouveau_ltc *ltc = nouveau_ltc(pfb);
-	struct nouveau_mem *mem = *pmem;
-
-	*pmem = NULL;
-	if (unlikely(mem == NULL))
-		return;
-
-	mutex_lock(&pfb->base.mutex);
-	if (mem->tag)
-		ltc->tags_free(ltc, &mem->tag);
-	__nv50_ram_put(pfb, mem);
-	mutex_unlock(&pfb->base.mutex);
-
-	kfree(mem);
-}
-
-int
-nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
-	     u32 memtype, struct nouveau_mem **pmem)
-{
-	struct nouveau_mm *mm = &pfb->vram;
-	struct nouveau_mm_node *r;
-	struct nouveau_mem *mem;
-	int type = (memtype & 0x0ff);
-	int back = (memtype & 0x800);
-	const bool comp = nvc0_pte_storage_type_map[type] != type;
-	int ret;
-
-	size  >>= 12;
-	align >>= 12;
-	ncmin >>= 12;
-	if (!ncmin)
-		ncmin = size;
-
-	mem = kzalloc(sizeof(*mem), GFP_KERNEL);
-	if (!mem)
-		return -ENOMEM;
-
-	INIT_LIST_HEAD(&mem->regions);
-	mem->size = size;
-
-	mutex_lock(&pfb->base.mutex);
-	if (comp) {
-		struct nouveau_ltc *ltc = nouveau_ltc(pfb);
-
-		/* compression only works with lpages */
-		if (align == (1 << (17 - 12))) {
-			int n = size >> 5;
-			ltc->tags_alloc(ltc, n, &mem->tag);
-		}
-
-		if (unlikely(!mem->tag))
-			type = nvc0_pte_storage_type_map[type];
-	}
-	mem->memtype = type;
-
-	do {
-		if (back)
-			ret = nouveau_mm_tail(mm, 0, 1, size, ncmin, align, &r);
-		else
-			ret = nouveau_mm_head(mm, 0, 1, size, ncmin, align, &r);
-		if (ret) {
-			mutex_unlock(&pfb->base.mutex);
-			pfb->ram->put(pfb, &mem);
-			return ret;
-		}
-
-		list_add_tail(&r->rl_entry, &mem->regions);
-		size -= r->length;
-	} while (size);
-	mutex_unlock(&pfb->base.mutex);
-
-	r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
-	mem->offset = (u64)r->offset << 12;
-	*pmem = mem;
-	return 0;
-}
-
-int
-nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine,
-		 struct nouveau_oclass *oclass, u32 maskaddr, int size,
-		 void **pobject)
-{
-	struct nouveau_fb *pfb = nouveau_fb(parent);
-	struct nouveau_bios *bios = nouveau_bios(pfb);
-	struct nouveau_ram *ram;
-	const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
-	const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
-	u32 parts = nv_rd32(pfb, 0x022438);
-	u32 pmask = nv_rd32(pfb, maskaddr);
-	u32 bsize = nv_rd32(pfb, 0x10f20c);
-	u32 offset, length;
-	bool uniform = true;
-	int ret, part;
-
-	ret = nouveau_ram_create_(parent, engine, oclass, size, pobject);
-	ram = *pobject;
-	if (ret)
-		return ret;
-
-	nv_debug(pfb, "0x100800: 0x%08x\n", nv_rd32(pfb, 0x100800));
-	nv_debug(pfb, "parts 0x%08x mask 0x%08x\n", parts, pmask);
-
-	ram->type = nouveau_fb_bios_memtype(bios);
-	ram->ranks = (nv_rd32(pfb, 0x10f200) & 0x00000004) ? 2 : 1;
-
-	/* read amount of vram attached to each memory controller */
-	for (part = 0; part < parts; part++) {
-		if (!(pmask & (1 << part))) {
-			u32 psize = nv_rd32(pfb, 0x11020c + (part * 0x1000));
-			if (psize != bsize) {
-				if (psize < bsize)
-					bsize = psize;
-				uniform = false;
-			}
-
-			nv_debug(pfb, "%d: mem_amount 0x%08x\n", part, psize);
-			ram->size += (u64)psize << 20;
-		}
-	}
-
-	/* if all controllers have the same amount attached, there's no holes */
-	if (uniform) {
-		offset = rsvd_head;
-		length = (ram->size >> 12) - rsvd_head - rsvd_tail;
-		ret = nouveau_mm_init(&pfb->vram, offset, length, 1);
-	} else {
-		/* otherwise, address lowest common amount from 0GiB */
-		ret = nouveau_mm_init(&pfb->vram, rsvd_head,
-				      (bsize << 8) * parts - rsvd_head, 1);
-		if (ret)
-			return ret;
-
-		/* and the rest starting from (8GiB + common_size) */
-		offset = (0x0200000000ULL >> 12) + (bsize << 8);
-		length = (ram->size >> 12) - ((bsize * parts) << 8) - rsvd_tail;
-
-		ret = nouveau_mm_init(&pfb->vram, offset, length, 1);
-		if (ret)
-			nouveau_mm_fini(&pfb->vram);
-	}
-
-	if (ret)
-		return ret;
-
-	ram->get = nvc0_ram_get;
-	ram->put = nvc0_ram_put;
-	return 0;
-}
-
-static int
-nvc0_ram_init(struct nouveau_object *object)
-{
-	struct nouveau_fb *pfb = (void *)object->parent;
-	struct nvc0_ram   *ram = (void *)object;
-	int ret, i;
-
-	ret = nouveau_ram_init(&ram->base);
-	if (ret)
-		return ret;
-
-	/* prepare for ddr link training, and load training patterns */
-	switch (ram->base.type) {
-	case NV_MEM_TYPE_GDDR5: {
-		static const u8  train0[] = {
-			0x00, 0xff, 0x55, 0xaa, 0x33, 0xcc,
-			0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
-		};
-		static const u32 train1[] = {
-			0x00000000, 0xffffffff,
-			0x55555555, 0xaaaaaaaa,
-			0x33333333, 0xcccccccc,
-			0xf0f0f0f0, 0x0f0f0f0f,
-			0x00ff00ff, 0xff00ff00,
-			0x0000ffff, 0xffff0000,
-		};
-
-		for (i = 0; i < 0x30; i++) {
-			nv_wr32(pfb, 0x10f968, 0x00000000 | (i << 8));
-			nv_wr32(pfb, 0x10f96c, 0x00000000 | (i << 8));
-			nv_wr32(pfb, 0x10f920, 0x00000100 | train0[i % 12]);
-			nv_wr32(pfb, 0x10f924, 0x00000100 | train0[i % 12]);
-			nv_wr32(pfb, 0x10f918,              train1[i % 12]);
-			nv_wr32(pfb, 0x10f91c,              train1[i % 12]);
-			nv_wr32(pfb, 0x10f920, 0x00000000 | train0[i % 12]);
-			nv_wr32(pfb, 0x10f924, 0x00000000 | train0[i % 12]);
-			nv_wr32(pfb, 0x10f918,              train1[i % 12]);
-			nv_wr32(pfb, 0x10f91c,              train1[i % 12]);
-		}
-	}	break;
-	default:
-		break;
-	}
-
-	return 0;
-}
-
-static int
-nvc0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 size,
-	      struct nouveau_object **pobject)
-{
-	struct nouveau_bios *bios = nouveau_bios(parent);
-	struct nvc0_ram *ram;
-	int ret;
-
-	ret = nvc0_ram_create(parent, engine, oclass, 0x022554, &ram);
-	*pobject = nv_object(ram);
-	if (ret)
-		return ret;
-
-	ret = nvbios_pll_parse(bios, 0x0c, &ram->refpll);
-	if (ret) {
-		nv_error(ram, "mclk refpll data not found\n");
-		return ret;
-	}
-
-	ret = nvbios_pll_parse(bios, 0x04, &ram->mempll);
-	if (ret) {
-		nv_error(ram, "mclk pll data not found\n");
-		return ret;
-	}
-
-	switch (ram->base.type) {
-	case NV_MEM_TYPE_GDDR5:
-		ram->base.calc = nvc0_ram_calc;
-		ram->base.prog = nvc0_ram_prog;
-		ram->base.tidy = nvc0_ram_tidy;
-		break;
-	default:
-		nv_warn(ram, "reclocking of this ram type unsupported\n");
-		return 0;
-	}
-
-	ram->fuc.r_0x10fe20 = ramfuc_reg(0x10fe20);
-	ram->fuc.r_0x10fe24 = ramfuc_reg(0x10fe24);
-	ram->fuc.r_0x137320 = ramfuc_reg(0x137320);
-	ram->fuc.r_0x137330 = ramfuc_reg(0x137330);
-
-	ram->fuc.r_0x132000 = ramfuc_reg(0x132000);
-	ram->fuc.r_0x132004 = ramfuc_reg(0x132004);
-	ram->fuc.r_0x132100 = ramfuc_reg(0x132100);
-
-	ram->fuc.r_0x137390 = ramfuc_reg(0x137390);
-
-	ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290);
-	ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294);
-	ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298);
-	ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c);
-	ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0);
-
-	ram->fuc.r_0x10f300 = ramfuc_reg(0x10f300);
-	ram->fuc.r_0x10f338 = ramfuc_reg(0x10f338);
-	ram->fuc.r_0x10f340 = ramfuc_reg(0x10f340);
-	ram->fuc.r_0x10f344 = ramfuc_reg(0x10f344);
-	ram->fuc.r_0x10f348 = ramfuc_reg(0x10f348);
-
-	ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910);
-	ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914);
-
-	ram->fuc.r_0x100b0c = ramfuc_reg(0x100b0c);
-	ram->fuc.r_0x10f050 = ramfuc_reg(0x10f050);
-	ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090);
-	ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200);
-	ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210);
-	ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310);
-	ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314);
-	ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610);
-	ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614);
-	ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800);
-	ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808);
-	ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824);
-	ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830);
-	ram->fuc.r_0x10f988 = ramfuc_reg(0x10f988);
-	ram->fuc.r_0x10f98c = ramfuc_reg(0x10f98c);
-	ram->fuc.r_0x10f990 = ramfuc_reg(0x10f990);
-	ram->fuc.r_0x10f998 = ramfuc_reg(0x10f998);
-	ram->fuc.r_0x10f9b0 = ramfuc_reg(0x10f9b0);
-	ram->fuc.r_0x10f9b4 = ramfuc_reg(0x10f9b4);
-	ram->fuc.r_0x10fb04 = ramfuc_reg(0x10fb04);
-	ram->fuc.r_0x10fb08 = ramfuc_reg(0x10fb08);
-	ram->fuc.r_0x137310 = ramfuc_reg(0x137300);
-	ram->fuc.r_0x137310 = ramfuc_reg(0x137310);
-	ram->fuc.r_0x137360 = ramfuc_reg(0x137360);
-	ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec);
-	ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0);
-	ram->fuc.r_0x1373f8 = ramfuc_reg(0x1373f8);
-
-	ram->fuc.r_0x61c140 = ramfuc_reg(0x61c140);
-	ram->fuc.r_0x611200 = ramfuc_reg(0x611200);
-
-	ram->fuc.r_0x13d8f4 = ramfuc_reg(0x13d8f4);
-	return 0;
-}
-
-struct nouveau_oclass
-nvc0_ram_oclass = {
-	.handle = 0,
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_ram_ctor,
-		.dtor = _nouveau_ram_dtor,
-		.init = nvc0_ram_init,
-		.fini = _nouveau_ram_fini,
-	}
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
deleted file mode 100644
index 6bae474abb44..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
+++ /dev/null
@@ -1,1646 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/gpio.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/pll.h>
-#include <subdev/bios/init.h>
-#include <subdev/bios/rammap.h>
-#include <subdev/bios/timing.h>
-#include <subdev/bios/M0205.h>
-#include <subdev/bios/M0209.h>
-
-#include <subdev/clock.h>
-#include <subdev/clock/pll.h>
-
-#include <subdev/timer.h>
-
-#include <core/option.h>
-
-#include "nvc0.h"
-
-#include "ramfuc.h"
-
-struct nve0_ramfuc {
-	struct ramfuc base;
-
-	struct nvbios_pll refpll;
-	struct nvbios_pll mempll;
-
-	struct ramfuc_reg r_gpioMV;
-	u32 r_funcMV[2];
-	struct ramfuc_reg r_gpio2E;
-	u32 r_func2E[2];
-	struct ramfuc_reg r_gpiotrig;
-
-	struct ramfuc_reg r_0x132020;
-	struct ramfuc_reg r_0x132028;
-	struct ramfuc_reg r_0x132024;
-	struct ramfuc_reg r_0x132030;
-	struct ramfuc_reg r_0x132034;
-	struct ramfuc_reg r_0x132000;
-	struct ramfuc_reg r_0x132004;
-	struct ramfuc_reg r_0x132040;
-
-	struct ramfuc_reg r_0x10f248;
-	struct ramfuc_reg r_0x10f290;
-	struct ramfuc_reg r_0x10f294;
-	struct ramfuc_reg r_0x10f298;
-	struct ramfuc_reg r_0x10f29c;
-	struct ramfuc_reg r_0x10f2a0;
-	struct ramfuc_reg r_0x10f2a4;
-	struct ramfuc_reg r_0x10f2a8;
-	struct ramfuc_reg r_0x10f2ac;
-	struct ramfuc_reg r_0x10f2cc;
-	struct ramfuc_reg r_0x10f2e8;
-	struct ramfuc_reg r_0x10f250;
-	struct ramfuc_reg r_0x10f24c;
-	struct ramfuc_reg r_0x10fec4;
-	struct ramfuc_reg r_0x10fec8;
-	struct ramfuc_reg r_0x10f604;
-	struct ramfuc_reg r_0x10f614;
-	struct ramfuc_reg r_0x10f610;
-	struct ramfuc_reg r_0x100770;
-	struct ramfuc_reg r_0x100778;
-	struct ramfuc_reg r_0x10f224;
-
-	struct ramfuc_reg r_0x10f870;
-	struct ramfuc_reg r_0x10f698;
-	struct ramfuc_reg r_0x10f694;
-	struct ramfuc_reg r_0x10f6b8;
-	struct ramfuc_reg r_0x10f808;
-	struct ramfuc_reg r_0x10f670;
-	struct ramfuc_reg r_0x10f60c;
-	struct ramfuc_reg r_0x10f830;
-	struct ramfuc_reg r_0x1373ec;
-	struct ramfuc_reg r_0x10f800;
-	struct ramfuc_reg r_0x10f82c;
-
-	struct ramfuc_reg r_0x10f978;
-	struct ramfuc_reg r_0x10f910;
-	struct ramfuc_reg r_0x10f914;
-
-	struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */
-
-	struct ramfuc_reg r_0x62c000;
-
-	struct ramfuc_reg r_0x10f200;
-
-	struct ramfuc_reg r_0x10f210;
-	struct ramfuc_reg r_0x10f310;
-	struct ramfuc_reg r_0x10f314;
-	struct ramfuc_reg r_0x10f318;
-	struct ramfuc_reg r_0x10f090;
-	struct ramfuc_reg r_0x10f69c;
-	struct ramfuc_reg r_0x10f824;
-	struct ramfuc_reg r_0x1373f0;
-	struct ramfuc_reg r_0x1373f4;
-	struct ramfuc_reg r_0x137320;
-	struct ramfuc_reg r_0x10f65c;
-	struct ramfuc_reg r_0x10f6bc;
-	struct ramfuc_reg r_0x100710;
-	struct ramfuc_reg r_0x100750;
-};
-
-struct nve0_ram {
-	struct nouveau_ram base;
-	struct nve0_ramfuc fuc;
-
-	struct list_head cfg;
-	u32 parts;
-	u32 pmask;
-	u32 pnuts;
-
-	struct nvbios_ramcfg diff;
-	int from;
-	int mode;
-	int N1, fN1, M1, P1;
-	int N2, M2, P2;
-};
-
-/*******************************************************************************
- * GDDR5
- ******************************************************************************/
-static void
-nve0_ram_train(struct nve0_ramfuc *fuc, u32 mask, u32 data)
-{
-	struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
-	u32 addr = 0x110974, i;
-
-	ram_mask(fuc, 0x10f910, mask, data);
-	ram_mask(fuc, 0x10f914, mask, data);
-
-	for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) {
-		if (ram->pmask & (1 << i))
-			continue;
-		ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);
-	}
-}
-
-static void
-r1373f4_init(struct nve0_ramfuc *fuc)
-{
-	struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
-	const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2);
-	const u32 rcoef = ((  ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
-	const u32 runk0 = ram->fN1 << 16;
-	const u32 runk1 = ram->fN1;
-
-	if (ram->from == 2) {
-		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
-		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
-	} else {
-		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
-	}
-
-	ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
-	ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
-
-	/* (re)program refpll, if required */
-	if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
-	    (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
-		ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
-		ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
-		ram_wr32(fuc, 0x137320, 0x00000000);
-		ram_mask(fuc, 0x132030, 0xffff0000, runk0);
-		ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
-		ram_wr32(fuc, 0x132024, rcoef);
-		ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
-		ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
-		ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
-		ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
-	}
-
-	/* (re)program mempll, if required */
-	if (ram->mode == 2) {
-		ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
-		ram_mask(fuc, 0x132000, 0x80000000, 0x80000000);
-		ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
-		ram_mask(fuc, 0x132004, 0x103fffff, mcoef);
-		ram_mask(fuc, 0x132000, 0x00000001, 0x00000001);
-		ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);
-		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
-	} else {
-		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010100);
-	}
-
-	ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
-}
-
-static void
-r1373f4_fini(struct nve0_ramfuc *fuc)
-{
-	struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
-	struct nouveau_ram_data *next = ram->base.next;
-	u8 v0 = next->bios.ramcfg_11_03_c0;
-	u8 v1 = next->bios.ramcfg_11_03_30;
-	u32 tmp;
-
-	tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
-	ram_wr32(fuc, 0x1373ec, tmp | (v1 << 16));
-	ram_mask(fuc, 0x1373f0, (~ram->mode & 3), 0x00000000);
-	if (ram->mode == 2) {
-		ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000002);
-		ram_mask(fuc, 0x1373f4, 0x00001100, 0x000000000);
-	} else {
-		ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000001);
-		ram_mask(fuc, 0x1373f4, 0x00010000, 0x000000000);
-	}
-	ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4);
-}
-
-static void
-nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg,
-	      u32 _mask, u32 _data, u32 _copy)
-{
-	struct nve0_fb_priv *priv = (void *)nouveau_fb(ram);
-	struct ramfuc *fuc = &ram->fuc.base;
-	u32 addr = 0x110000 + (reg->addr & 0xfff);
-	u32 mask = _mask | _copy;
-	u32 data = (_data & _mask) | (reg->data & _copy);
-	u32 i;
-
-	for (i = 0; i < 16; i++, addr += 0x1000) {
-		if (ram->pnuts & (1 << i)) {
-			u32 prev = nv_rd32(priv, addr);
-			u32 next = (prev & ~mask) | data;
-			nouveau_memx_wr32(fuc->memx, addr, next);
-		}
-	}
-}
-#define ram_nuts(s,r,m,d,c)                                                    \
-	nve0_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c))
-
-static int
-nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
-{
-	struct nve0_ram *ram = (void *)pfb->ram;
-	struct nve0_ramfuc *fuc = &ram->fuc;
-	struct nouveau_ram_data *next = ram->base.next;
-	int vc = !next->bios.ramcfg_11_02_08;
-	int mv = !next->bios.ramcfg_11_02_04;
-	u32 mask, data;
-
-	ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
-	ram_block(fuc);
-	ram_wr32(fuc, 0x62c000, 0x0f0f0000);
-
-	/* MR1: turn termination on early, for some reason.. */
-	if ((ram->base.mr[1] & 0x03c) != 0x030) {
-		ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c);
-		ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000);
-	}
-
-	if (vc == 1 && ram_have(fuc, gpio2E)) {
-		u32 temp  = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
-		if (temp != ram_rd32(fuc, gpio2E)) {
-			ram_wr32(fuc, gpiotrig, 1);
-			ram_nsec(fuc, 20000);
-		}
-	}
-
-	ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
-
-	nve0_ram_train(fuc, 0x01020000, 0x000c0000);
-
-	ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
-	ram_nsec(fuc, 1000);
-	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
-	ram_nsec(fuc, 1000);
-
-	ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
-	ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
-	ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
-	ram_wr32(fuc, 0x10f090, 0x00000061);
-	ram_wr32(fuc, 0x10f090, 0xc000007f);
-	ram_nsec(fuc, 1000);
-
-	ram_wr32(fuc, 0x10f698, 0x00000000);
-	ram_wr32(fuc, 0x10f69c, 0x00000000);
-
-	/*XXX: there does appear to be some kind of condition here, simply
-	 *     modifying these bits in the vbios from the default pl0
-	 *     entries shows no change.  however, the data does appear to
-	 *     be correct and may be required for the transition back
-	 */
-	mask = 0x800f07e0;
-	data = 0x00030000;
-	if (ram_rd32(fuc, 0x10f978) & 0x00800000)
-		data |= 0x00040000;
-
-	if (1) {
-		data |= 0x800807e0;
-		switch (next->bios.ramcfg_11_03_c0) {
-		case 3: data &= ~0x00000040; break;
-		case 2: data &= ~0x00000100; break;
-		case 1: data &= ~0x80000000; break;
-		case 0: data &= ~0x00000400; break;
-		}
-
-		switch (next->bios.ramcfg_11_03_30) {
-		case 3: data &= ~0x00000020; break;
-		case 2: data &= ~0x00000080; break;
-		case 1: data &= ~0x00080000; break;
-		case 0: data &= ~0x00000200; break;
-		}
-	}
-
-	if (next->bios.ramcfg_11_02_80)
-		mask |= 0x03000000;
-	if (next->bios.ramcfg_11_02_40)
-		mask |= 0x00002000;
-	if (next->bios.ramcfg_11_07_10)
-		mask |= 0x00004000;
-	if (next->bios.ramcfg_11_07_08)
-		mask |= 0x00000003;
-	else {
-		mask |= 0x34000000;
-		if (ram_rd32(fuc, 0x10f978) & 0x00800000)
-			mask |= 0x40000000;
-	}
-	ram_mask(fuc, 0x10f824, mask, data);
-
-	ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);
-
-	if (ram->from == 2 && ram->mode != 2) {
-		ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
-		ram_mask(fuc, 0x10f200, 0x18008000, 0x00008000);
-		ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004);
-		ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010);
-		ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
-		r1373f4_init(fuc);
-		ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001);
-		r1373f4_fini(fuc);
-		ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001);
-	} else
-	if (ram->from != 2 && ram->mode != 2) {
-		r1373f4_init(fuc);
-		r1373f4_fini(fuc);
-	}
-
-	if (ram_have(fuc, gpioMV)) {
-		u32 temp  = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
-		if (temp != ram_rd32(fuc, gpioMV)) {
-			ram_wr32(fuc, gpiotrig, 1);
-			ram_nsec(fuc, 64000);
-		}
-	}
-
-	if (next->bios.ramcfg_11_02_40 ||
-	    next->bios.ramcfg_11_07_10) {
-		ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
-		ram_nsec(fuc, 20000);
-	}
-
-	if (ram->from != 2 && ram->mode == 2) {
-		if (0 /*XXX: Titan */)
-			ram_mask(fuc, 0x10f200, 0x18000000, 0x18000000);
-		ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
-		ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002);
-		ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010);
-		r1373f4_init(fuc);
-		r1373f4_fini(fuc);
-		ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000);
-		ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000);
-	} else
-	if (ram->from == 2 && ram->mode == 2) {
-		ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
-		r1373f4_init(fuc);
-		r1373f4_fini(fuc);
-	}
-
-	if (ram->mode != 2) /*XXX*/ {
-		if (next->bios.ramcfg_11_07_40)
-			ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
-	}
-
-	ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
-	ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
-	ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
-
-	if (!next->bios.ramcfg_11_07_08 && !next->bios.ramcfg_11_07_04) {
-		ram_wr32(fuc, 0x10f698, 0x01010101 * next->bios.ramcfg_11_04);
-		ram_wr32(fuc, 0x10f69c, 0x01010101 * next->bios.ramcfg_11_04);
-	} else
-	if (!next->bios.ramcfg_11_07_08) {
-		ram_wr32(fuc, 0x10f698, 0x00000000);
-		ram_wr32(fuc, 0x10f69c, 0x00000000);
-	}
-
-	if (ram->mode != 2) {
-		u32 data = 0x01000100 * next->bios.ramcfg_11_04;
-		ram_nuke(fuc, 0x10f694);
-		ram_mask(fuc, 0x10f694, 0xff00ff00, data);
-	}
-
-	if (ram->mode == 2 && next->bios.ramcfg_11_08_10)
-		data = 0x00000080;
-	else
-		data = 0x00000000;
-	ram_mask(fuc, 0x10f60c, 0x00000080, data);
-
-	mask = 0x00070000;
-	data = 0x00000000;
-	if (!next->bios.ramcfg_11_02_80)
-		data |= 0x03000000;
-	if (!next->bios.ramcfg_11_02_40)
-		data |= 0x00002000;
-	if (!next->bios.ramcfg_11_07_10)
-		data |= 0x00004000;
-	if (!next->bios.ramcfg_11_07_08)
-		data |= 0x00000003;
-	else
-		data |= 0x74000000;
-	ram_mask(fuc, 0x10f824, mask, data);
-
-	if (next->bios.ramcfg_11_01_08)
-		data = 0x00000000;
-	else
-		data = 0x00001000;
-	ram_mask(fuc, 0x10f200, 0x00001000, data);
-
-	if (ram_rd32(fuc, 0x10f670) & 0x80000000) {
-		ram_nsec(fuc, 10000);
-		ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000);
-	}
-
-	if (next->bios.ramcfg_11_08_01)
-		data = 0x00100000;
-	else
-		data = 0x00000000;
-	ram_mask(fuc, 0x10f82c, 0x00100000, data);
-
-	data = 0x00000000;
-	if (next->bios.ramcfg_11_08_08)
-		data |= 0x00002000;
-	if (next->bios.ramcfg_11_08_04)
-		data |= 0x00001000;
-	if (next->bios.ramcfg_11_08_02)
-		data |= 0x00004000;
-	ram_mask(fuc, 0x10f830, 0x00007000, data);
-
-	/* PFB timing */
-	ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
-	ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
-	ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
-	ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
-	ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
-	ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
-	ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
-	ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
-	ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
-	ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
-	ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
-
-	data = mask = 0x00000000;
-	if (ram->diff.ramcfg_11_08_20) {
-		if (next->bios.ramcfg_11_08_20)
-			data |= 0x01000000;
-		mask |= 0x01000000;
-	}
-	ram_mask(fuc, 0x10f200, mask, data);
-
-	data = mask = 0x00000000;
-	if (ram->diff.ramcfg_11_02_03) {
-		data |= next->bios.ramcfg_11_02_03 << 8;
-		mask |= 0x00000300;
-	}
-	if (ram->diff.ramcfg_11_01_10) {
-		if (next->bios.ramcfg_11_01_10)
-			data |= 0x70000000;
-		mask |= 0x70000000;
-	}
-	ram_mask(fuc, 0x10f604, mask, data);
-
-	data = mask = 0x00000000;
-	if (ram->diff.timing_20_30_07) {
-		data |= next->bios.timing_20_30_07 << 28;
-		mask |= 0x70000000;
-	}
-	if (ram->diff.ramcfg_11_01_01) {
-		if (next->bios.ramcfg_11_01_01)
-			data |= 0x00000100;
-		mask |= 0x00000100;
-	}
-	ram_mask(fuc, 0x10f614, mask, data);
-
-	data = mask = 0x00000000;
-	if (ram->diff.timing_20_30_07) {
-		data |= next->bios.timing_20_30_07 << 28;
-		mask |= 0x70000000;
-	}
-	if (ram->diff.ramcfg_11_01_02) {
-		if (next->bios.ramcfg_11_01_02)
-			data |= 0x00000100;
-		mask |= 0x00000100;
-	}
-	ram_mask(fuc, 0x10f610, mask, data);
-
-	mask = 0x33f00000;
-	data = 0x00000000;
-	if (!next->bios.ramcfg_11_01_04)
-		data |= 0x20200000;
-	if (!next->bios.ramcfg_11_07_80)
-		data |= 0x12800000;
-	/*XXX: see note above about there probably being some condition
-	 *     for the 10f824 stuff that uses ramcfg 3...
-	 */
-	if (next->bios.ramcfg_11_03_f0) {
-		if (next->bios.rammap_11_08_0c) {
-			if (!next->bios.ramcfg_11_07_80)
-				mask |= 0x00000020;
-			else
-				data |= 0x00000020;
-			mask |= 0x00000004;
-		}
-	} else {
-		mask |= 0x40000020;
-		data |= 0x00000004;
-	}
-
-	ram_mask(fuc, 0x10f808, mask, data);
-
-	ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
-
-	data = mask = 0x00000000;
-	if (ram->diff.ramcfg_11_02_03) {
-		data |= next->bios.ramcfg_11_02_03;
-		mask |= 0x00000003;
-	}
-	if (ram->diff.ramcfg_11_01_10) {
-		if (next->bios.ramcfg_11_01_10)
-			data |= 0x00000004;
-		mask |= 0x00000004;
-	}
-
-	if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) {
-		ram_mask(fuc, 0x100750, 0x00000008, 0x00000008);
-		ram_wr32(fuc, 0x100710, 0x00000000);
-		ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000);
-	}
-
-	data = next->bios.timing_20_30_07 << 8;
-	if (next->bios.ramcfg_11_01_01)
-		data |= 0x80000000;
-	ram_mask(fuc, 0x100778, 0x00000700, data);
-
-	ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
-	data = (next->bios.timing[10] & 0x7f000000) >> 24;
-	if (data < next->bios.timing_20_2c_1fc0)
-		data = next->bios.timing_20_2c_1fc0;
-	ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
-	ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
-
-	ram_mask(fuc, 0x10fec4, 0x041e0f07, next->bios.timing_20_31_0800 << 26 |
-					    next->bios.timing_20_31_0780 << 17 |
-					    next->bios.timing_20_31_0078 << 8 |
-					    next->bios.timing_20_31_0007);
-	ram_mask(fuc, 0x10fec8, 0x00000027, next->bios.timing_20_31_8000 << 5 |
-					    next->bios.timing_20_31_7000);
-
-	ram_wr32(fuc, 0x10f090, 0x4000007e);
-	ram_nsec(fuc, 2000);
-	ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
-	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
-	ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
-
-	if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) {
-		u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000);
-		nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/
-		ram_nsec(fuc, 1000);
-		ram_wr32(fuc, 0x10f294, temp);
-	}
-
-	ram_mask(fuc, mr[3], 0xfff, ram->base.mr[3]);
-	ram_wr32(fuc, mr[0], ram->base.mr[0]);
-	ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]);
-	ram_nsec(fuc, 1000);
-	ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]);
-	ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */
-	ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]);
-	ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]);
-
-	if (vc == 0 && ram_have(fuc, gpio2E)) {
-		u32 temp  = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
-		if (temp != ram_rd32(fuc, gpio2E)) {
-			ram_wr32(fuc, gpiotrig, 1);
-			ram_nsec(fuc, 20000);
-		}
-	}
-
-	ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
-	ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
-	ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
-	ram_nsec(fuc, 1000);
-	ram_nuts(ram, 0x10f200, 0x18808800, 0x00000000, 0x18808800);
-
-	data  = ram_rd32(fuc, 0x10f978);
-	data &= ~0x00046144;
-	data |=  0x0000000b;
-	if (!next->bios.ramcfg_11_07_08) {
-		if (!next->bios.ramcfg_11_07_04)
-			data |= 0x0000200c;
-		else
-			data |= 0x00000000;
-	} else {
-		data |= 0x00040044;
-	}
-	ram_wr32(fuc, 0x10f978, data);
-
-	if (ram->mode == 1) {
-		data = ram_rd32(fuc, 0x10f830) | 0x00000001;
-		ram_wr32(fuc, 0x10f830, data);
-	}
-
-	if (!next->bios.ramcfg_11_07_08) {
-		data = 0x88020000;
-		if ( next->bios.ramcfg_11_07_04)
-			data |= 0x10000000;
-		if (!next->bios.rammap_11_08_10)
-			data |= 0x00080000;
-	} else {
-		data = 0xa40e0000;
-	}
-	nve0_ram_train(fuc, 0xbc0f0000, data);
-	if (1) /* XXX: not always? */
-		ram_nsec(fuc, 1000);
-
-	if (ram->mode == 2) { /*XXX*/
-		ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004);
-	}
-
-	/* LP3 */
-	if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5])
-		ram_nsec(fuc, 1000);
-
-	if (ram->mode != 2) {
-		ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
-		ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
-	}
-
-	if (next->bios.ramcfg_11_07_02)
-		nve0_ram_train(fuc, 0x80020000, 0x01000000);
-
-	ram_unblock(fuc);
-	ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
-
-	if (next->bios.rammap_11_08_01)
-		data = 0x00000800;
-	else
-		data = 0x00000000;
-	ram_mask(fuc, 0x10f200, 0x00000800, data);
-	ram_nuts(ram, 0x10f200, 0x18808800, data, 0x18808800);
-	return 0;
-}
-
-/*******************************************************************************
- * DDR3
- ******************************************************************************/
-
-static int
-nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
-{
-	struct nve0_ram *ram = (void *)pfb->ram;
-	struct nve0_ramfuc *fuc = &ram->fuc;
-	const u32 rcoef = ((  ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
-	const u32 runk0 = ram->fN1 << 16;
-	const u32 runk1 = ram->fN1;
-	struct nouveau_ram_data *next = ram->base.next;
-	int vc = !next->bios.ramcfg_11_02_08;
-	int mv = !next->bios.ramcfg_11_02_04;
-	u32 mask, data;
-
-	ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
-	ram_block(fuc);
-	ram_wr32(fuc, 0x62c000, 0x0f0f0000);
-
-	if (vc == 1 && ram_have(fuc, gpio2E)) {
-		u32 temp  = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
-		if (temp != ram_rd32(fuc, gpio2E)) {
-			ram_wr32(fuc, gpiotrig, 1);
-			ram_nsec(fuc, 20000);
-		}
-	}
-
-	ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
-	if (next->bios.ramcfg_11_03_f0)
-		ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000);
-
-	ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
-	ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
-	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
-	ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
-	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
-	ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
-	ram_nsec(fuc, 1000);
-
-	ram_wr32(fuc, 0x10f090, 0x00000060);
-	ram_wr32(fuc, 0x10f090, 0xc000007e);
-
-	/*XXX: there does appear to be some kind of condition here, simply
-	 *     modifying these bits in the vbios from the default pl0
-	 *     entries shows no change.  however, the data does appear to
-	 *     be correct and may be required for the transition back
-	 */
-	mask = 0x00010000;
-	data = 0x00010000;
-
-	if (1) {
-		mask |= 0x800807e0;
-		data |= 0x800807e0;
-		switch (next->bios.ramcfg_11_03_c0) {
-		case 3: data &= ~0x00000040; break;
-		case 2: data &= ~0x00000100; break;
-		case 1: data &= ~0x80000000; break;
-		case 0: data &= ~0x00000400; break;
-		}
-
-		switch (next->bios.ramcfg_11_03_30) {
-		case 3: data &= ~0x00000020; break;
-		case 2: data &= ~0x00000080; break;
-		case 1: data &= ~0x00080000; break;
-		case 0: data &= ~0x00000200; break;
-		}
-	}
-
-	if (next->bios.ramcfg_11_02_80)
-		mask |= 0x03000000;
-	if (next->bios.ramcfg_11_02_40)
-		mask |= 0x00002000;
-	if (next->bios.ramcfg_11_07_10)
-		mask |= 0x00004000;
-	if (next->bios.ramcfg_11_07_08)
-		mask |= 0x00000003;
-	else
-		mask |= 0x14000000;
-	ram_mask(fuc, 0x10f824, mask, data);
-
-	ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);
-
-	ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
-	data  = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
-	data |= next->bios.ramcfg_11_03_30 << 16;
-	ram_wr32(fuc, 0x1373ec, data);
-	ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
-	ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
-
-	/* (re)program refpll, if required */
-	if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
-	    (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
-		ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
-		ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
-		ram_wr32(fuc, 0x137320, 0x00000000);
-		ram_mask(fuc, 0x132030, 0xffff0000, runk0);
-		ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
-		ram_wr32(fuc, 0x132024, rcoef);
-		ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
-		ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
-		ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
-		ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
-	}
-
-	ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000010);
-	ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001);
-	ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
-
-	if (ram_have(fuc, gpioMV)) {
-		u32 temp  = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
-		if (temp != ram_rd32(fuc, gpioMV)) {
-			ram_wr32(fuc, gpiotrig, 1);
-			ram_nsec(fuc, 64000);
-		}
-	}
-
-	if (next->bios.ramcfg_11_02_40 ||
-	    next->bios.ramcfg_11_07_10) {
-		ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
-		ram_nsec(fuc, 20000);
-	}
-
-	if (ram->mode != 2) /*XXX*/ {
-		if (next->bios.ramcfg_11_07_40)
-			ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
-	}
-
-	ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
-	ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
-	ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
-
-	mask = 0x00010000;
-	data = 0x00000000;
-	if (!next->bios.ramcfg_11_02_80)
-		data |= 0x03000000;
-	if (!next->bios.ramcfg_11_02_40)
-		data |= 0x00002000;
-	if (!next->bios.ramcfg_11_07_10)
-		data |= 0x00004000;
-	if (!next->bios.ramcfg_11_07_08)
-		data |= 0x00000003;
-	else
-		data |= 0x14000000;
-	ram_mask(fuc, 0x10f824, mask, data);
-	ram_nsec(fuc, 1000);
-
-	if (next->bios.ramcfg_11_08_01)
-		data = 0x00100000;
-	else
-		data = 0x00000000;
-	ram_mask(fuc, 0x10f82c, 0x00100000, data);
-
-	/* PFB timing */
-	ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
-	ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
-	ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
-	ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
-	ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
-	ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
-	ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
-	ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
-	ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
-	ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
-	ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
-
-	mask = 0x33f00000;
-	data = 0x00000000;
-	if (!next->bios.ramcfg_11_01_04)
-		data |= 0x20200000;
-	if (!next->bios.ramcfg_11_07_80)
-		data |= 0x12800000;
-	/*XXX: see note above about there probably being some condition
-	 *     for the 10f824 stuff that uses ramcfg 3...
-	 */
-	if (next->bios.ramcfg_11_03_f0) {
-		if (next->bios.rammap_11_08_0c) {
-			if (!next->bios.ramcfg_11_07_80)
-				mask |= 0x00000020;
-			else
-				data |= 0x00000020;
-			mask |= 0x08000004;
-		}
-		data |= 0x04000000;
-	} else {
-		mask |= 0x44000020;
-		data |= 0x08000004;
-	}
-
-	ram_mask(fuc, 0x10f808, mask, data);
-
-	ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
-
-	ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
-
-	data = (next->bios.timing[10] & 0x7f000000) >> 24;
-	if (data < next->bios.timing_20_2c_1fc0)
-		data = next->bios.timing_20_2c_1fc0;
-	ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
-
-	ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
-
-	ram_wr32(fuc, 0x10f090, 0x4000007f);
-	ram_nsec(fuc, 1000);
-
-	ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
-	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
-	ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
-	ram_nsec(fuc, 1000);
-
-	ram_nuke(fuc, mr[0]);
-	ram_mask(fuc, mr[0], 0x100, 0x100);
-	ram_mask(fuc, mr[0], 0x100, 0x000);
-
-	ram_mask(fuc, mr[2], 0xfff, ram->base.mr[2]);
-	ram_wr32(fuc, mr[0], ram->base.mr[0]);
-	ram_nsec(fuc, 1000);
-
-	ram_nuke(fuc, mr[0]);
-	ram_mask(fuc, mr[0], 0x100, 0x100);
-	ram_mask(fuc, mr[0], 0x100, 0x000);
-
-	if (vc == 0 && ram_have(fuc, gpio2E)) {
-		u32 temp  = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
-		if (temp != ram_rd32(fuc, gpio2E)) {
-			ram_wr32(fuc, gpiotrig, 1);
-			ram_nsec(fuc, 20000);
-		}
-	}
-
-	if (ram->mode != 2) {
-		ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
-		ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
-	}
-
-	ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
-	ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
-	ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
-	ram_nsec(fuc, 1000);
-
-	ram_unblock(fuc);
-	ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
-
-	if (next->bios.rammap_11_08_01)
-		data = 0x00000800;
-	else
-		data = 0x00000000;
-	ram_mask(fuc, 0x10f200, 0x00000800, data);
-	return 0;
-}
-
-/*******************************************************************************
- * main hooks
- ******************************************************************************/
-
-static int
-nve0_ram_calc_data(struct nouveau_fb *pfb, u32 khz,
-		   struct nouveau_ram_data *data)
-{
-	struct nve0_ram *ram = (void *)pfb->ram;
-	struct nouveau_ram_data *cfg;
-	u32 mhz = khz / 1000;
-
-	list_for_each_entry(cfg, &ram->cfg, head) {
-		if (mhz >= cfg->bios.rammap_min &&
-		    mhz <= cfg->bios.rammap_max) {
-			*data = *cfg;
-			data->freq = khz;
-			return 0;
-		}
-	}
-
-	nv_error(ram, "ramcfg data for %dMHz not found\n", mhz);
-	return -EINVAL;
-}
-
-static int
-nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next)
-{
-	struct nve0_ram *ram = (void *)pfb->ram;
-	struct nve0_ramfuc *fuc = &ram->fuc;
-	int refclk, i;
-	int ret;
-
-	ret = ram_init(fuc, pfb);
-	if (ret)
-		return ret;
-
-	ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1;
-	ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f;
-
-	/* XXX: this is *not* what nvidia do.  on fermi nvidia generally
-	 * select, based on some unknown condition, one of the two possible
-	 * reference frequencies listed in the vbios table for mempll and
-	 * program refpll to that frequency.
-	 *
-	 * so far, i've seen very weird values being chosen by nvidia on
-	 * kepler boards, no idea how/why they're chosen.
-	 */
-	refclk = next->freq;
-	if (ram->mode == 2)
-		refclk = fuc->mempll.refclk;
-
-	/* calculate refpll coefficients */
-	ret = nva3_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1,
-			   &ram->fN1, &ram->M1, &ram->P1);
-	fuc->mempll.refclk = ret;
-	if (ret <= 0) {
-		nv_error(pfb, "unable to calc refpll\n");
-		return -EINVAL;
-	}
-
-	/* calculate mempll coefficients, if we're using it */
-	if (ram->mode == 2) {
-		/* post-divider doesn't work... the reg takes the values but
-		 * appears to completely ignore it.  there *is* a bit at
-		 * bit 28 that appears to divide the clock by 2 if set.
-		 */
-		fuc->mempll.min_p = 1;
-		fuc->mempll.max_p = 2;
-
-		ret = nva3_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq,
-				   &ram->N2, NULL, &ram->M2, &ram->P2);
-		if (ret <= 0) {
-			nv_error(pfb, "unable to calc mempll\n");
-			return -EINVAL;
-		}
-	}
-
-	for (i = 0; i < ARRAY_SIZE(fuc->r_mr); i++) {
-		if (ram_have(fuc, mr[i]))
-			ram->base.mr[i] = ram_rd32(fuc, mr[i]);
-	}
-	ram->base.freq = next->freq;
-
-	switch (ram->base.type) {
-	case NV_MEM_TYPE_DDR3:
-		ret = nouveau_sddr3_calc(&ram->base);
-		if (ret == 0)
-			ret = nve0_ram_calc_sddr3(pfb, next->freq);
-		break;
-	case NV_MEM_TYPE_GDDR5:
-		ret = nouveau_gddr5_calc(&ram->base, ram->pnuts != 0);
-		if (ret == 0)
-			ret = nve0_ram_calc_gddr5(pfb, next->freq);
-		break;
-	default:
-		ret = -ENOSYS;
-		break;
-	}
-
-	return ret;
-}
-
-static int
-nve0_ram_calc(struct nouveau_fb *pfb, u32 freq)
-{
-	struct nouveau_clock *clk = nouveau_clock(pfb);
-	struct nve0_ram *ram = (void *)pfb->ram;
-	struct nouveau_ram_data *xits = &ram->base.xition;
-	struct nouveau_ram_data *copy;
-	int ret;
-
-	if (ram->base.next == NULL) {
-		ret = nve0_ram_calc_data(pfb, clk->read(clk, nv_clk_src_mem),
-					&ram->base.former);
-		if (ret)
-			return ret;
-
-		ret = nve0_ram_calc_data(pfb, freq, &ram->base.target);
-		if (ret)
-			return ret;
-
-		if (ram->base.target.freq < ram->base.former.freq) {
-			*xits = ram->base.target;
-			copy = &ram->base.former;
-		} else {
-			*xits = ram->base.former;
-			copy = &ram->base.target;
-		}
-
-		xits->bios.ramcfg_11_02_04 = copy->bios.ramcfg_11_02_04;
-		xits->bios.ramcfg_11_02_03 = copy->bios.ramcfg_11_02_03;
-		xits->bios.timing_20_30_07 = copy->bios.timing_20_30_07;
-
-		ram->base.next = &ram->base.target;
-		if (memcmp(xits, &ram->base.former, sizeof(xits->bios)))
-			ram->base.next = &ram->base.xition;
-	} else {
-		BUG_ON(ram->base.next != &ram->base.xition);
-		ram->base.next = &ram->base.target;
-	}
-
-	return nve0_ram_calc_xits(pfb, ram->base.next);
-}
-
-static void
-nve0_ram_prog_0(struct nouveau_fb *pfb, u32 freq)
-{
-	struct nve0_ram *ram = (void *)pfb->ram;
-	struct nouveau_ram_data *cfg;
-	u32 mhz = freq / 1000;
-	u32 mask, data;
-
-	list_for_each_entry(cfg, &ram->cfg, head) {
-		if (mhz >= cfg->bios.rammap_min &&
-		    mhz <= cfg->bios.rammap_max)
-			break;
-	}
-
-	if (&cfg->head == &ram->cfg)
-		return;
-
-	if (mask = 0, data = 0, ram->diff.rammap_11_0a_03fe) {
-		data |= cfg->bios.rammap_11_0a_03fe << 12;
-		mask |= 0x001ff000;
-	}
-	if (ram->diff.rammap_11_09_01ff) {
-		data |= cfg->bios.rammap_11_09_01ff;
-		mask |= 0x000001ff;
-	}
-	nv_mask(pfb, 0x10f468, mask, data);
-
-	if (mask = 0, data = 0, ram->diff.rammap_11_0a_0400) {
-		data |= cfg->bios.rammap_11_0a_0400;
-		mask |= 0x00000001;
-	}
-	nv_mask(pfb, 0x10f420, mask, data);
-
-	if (mask = 0, data = 0, ram->diff.rammap_11_0a_0800) {
-		data |= cfg->bios.rammap_11_0a_0800;
-		mask |= 0x00000001;
-	}
-	nv_mask(pfb, 0x10f430, mask, data);
-
-	if (mask = 0, data = 0, ram->diff.rammap_11_0b_01f0) {
-		data |= cfg->bios.rammap_11_0b_01f0;
-		mask |= 0x0000001f;
-	}
-	nv_mask(pfb, 0x10f400, mask, data);
-
-	if (mask = 0, data = 0, ram->diff.rammap_11_0b_0200) {
-		data |= cfg->bios.rammap_11_0b_0200 << 9;
-		mask |= 0x00000200;
-	}
-	nv_mask(pfb, 0x10f410, mask, data);
-
-	if (mask = 0, data = 0, ram->diff.rammap_11_0d) {
-		data |= cfg->bios.rammap_11_0d << 16;
-		mask |= 0x00ff0000;
-	}
-	if (ram->diff.rammap_11_0f) {
-		data |= cfg->bios.rammap_11_0f << 8;
-		mask |= 0x0000ff00;
-	}
-	nv_mask(pfb, 0x10f440, mask, data);
-
-	if (mask = 0, data = 0, ram->diff.rammap_11_0e) {
-		data |= cfg->bios.rammap_11_0e << 8;
-		mask |= 0x0000ff00;
-	}
-	if (ram->diff.rammap_11_0b_0800) {
-		data |= cfg->bios.rammap_11_0b_0800 << 7;
-		mask |= 0x00000080;
-	}
-	if (ram->diff.rammap_11_0b_0400) {
-		data |= cfg->bios.rammap_11_0b_0400 << 5;
-		mask |= 0x00000020;
-	}
-	nv_mask(pfb, 0x10f444, mask, data);
-}
-
-static int
-nve0_ram_prog(struct nouveau_fb *pfb)
-{
-	struct nouveau_device *device = nv_device(pfb);
-	struct nve0_ram *ram = (void *)pfb->ram;
-	struct nve0_ramfuc *fuc = &ram->fuc;
-	struct nouveau_ram_data *next = ram->base.next;
-
-	if (!nouveau_boolopt(device->cfgopt, "NvMemExec", true)) {
-		ram_exec(fuc, false);
-		return (ram->base.next == &ram->base.xition);
-	}
-
-	nve0_ram_prog_0(pfb, 1000);
-	ram_exec(fuc, true);
-	nve0_ram_prog_0(pfb, next->freq);
-
-	return (ram->base.next == &ram->base.xition);
-}
-
-static void
-nve0_ram_tidy(struct nouveau_fb *pfb)
-{
-	struct nve0_ram *ram = (void *)pfb->ram;
-	struct nve0_ramfuc *fuc = &ram->fuc;
-	ram->base.next = NULL;
-	ram_exec(fuc, false);
-}
-
-struct nve0_ram_train {
-	u16 mask;
-	struct nvbios_M0209S remap;
-	struct nvbios_M0209S type00;
-	struct nvbios_M0209S type01;
-	struct nvbios_M0209S type04;
-	struct nvbios_M0209S type06;
-	struct nvbios_M0209S type07;
-	struct nvbios_M0209S type08;
-	struct nvbios_M0209S type09;
-};
-
-static int
-nve0_ram_train_type(struct nouveau_fb *pfb, int i, u8 ramcfg,
-		    struct nve0_ram_train *train)
-{
-	struct nouveau_bios *bios = nouveau_bios(pfb);
-	struct nvbios_M0205E M0205E;
-	struct nvbios_M0205S M0205S;
-	struct nvbios_M0209E M0209E;
-	struct nvbios_M0209S *remap = &train->remap;
-	struct nvbios_M0209S *value;
-	u8  ver, hdr, cnt, len;
-	u32 data;
-
-	/* determine type of data for this index */
-	if (!(data = nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E)))
-		return -ENOENT;
-
-	switch (M0205E.type) {
-	case 0x00: value = &train->type00; break;
-	case 0x01: value = &train->type01; break;
-	case 0x04: value = &train->type04; break;
-	case 0x06: value = &train->type06; break;
-	case 0x07: value = &train->type07; break;
-	case 0x08: value = &train->type08; break;
-	case 0x09: value = &train->type09; break;
-	default:
-		return 0;
-	}
-
-	/* training data index determined by ramcfg strap */
-	if (!(data = nvbios_M0205Sp(bios, i, ramcfg, &ver, &hdr, &M0205S)))
-		return -EINVAL;
-	i = M0205S.data;
-
-	/* training data format information */
-	if (!(data = nvbios_M0209Ep(bios, i, &ver, &hdr, &cnt, &len, &M0209E)))
-		return -EINVAL;
-
-	/* ... and the raw data */
-	if (!(data = nvbios_M0209Sp(bios, i, 0, &ver, &hdr, value)))
-		return -EINVAL;
-
-	if (M0209E.v02_07 == 2) {
-		/* of course! why wouldn't we have a pointer to another entry
-		 * in the same table, and use the first one as an array of
-		 * remap indices...
-		 */
-		if (!(data = nvbios_M0209Sp(bios, M0209E.v03, 0, &ver, &hdr,
-					    remap)))
-			return -EINVAL;
-
-		for (i = 0; i < ARRAY_SIZE(value->data); i++)
-			value->data[i] = remap->data[value->data[i]];
-	} else
-	if (M0209E.v02_07 != 1)
-		return -EINVAL;
-
-	train->mask |= 1 << M0205E.type;
-	return 0;
-}
-
-static int
-nve0_ram_train_init_0(struct nouveau_fb *pfb, struct nve0_ram_train *train)
-{
-	int i, j;
-
-	if ((train->mask & 0x03d3) != 0x03d3) {
-		nv_warn(pfb, "missing link training data\n");
-		return -EINVAL;
-	}
-
-	for (i = 0; i < 0x30; i++) {
-		for (j = 0; j < 8; j += 4) {
-			nv_wr32(pfb, 0x10f968 + j, 0x00000000 | (i << 8));
-			nv_wr32(pfb, 0x10f920 + j, 0x00000000 |
-						   train->type08.data[i] << 4 |
-						   train->type06.data[i]);
-			nv_wr32(pfb, 0x10f918 + j, train->type00.data[i]);
-			nv_wr32(pfb, 0x10f920 + j, 0x00000100 |
-						   train->type09.data[i] << 4 |
-						   train->type07.data[i]);
-			nv_wr32(pfb, 0x10f918 + j, train->type01.data[i]);
-		}
-	}
-
-	for (j = 0; j < 8; j += 4) {
-		for (i = 0; i < 0x100; i++) {
-			nv_wr32(pfb, 0x10f968 + j, i);
-			nv_wr32(pfb, 0x10f900 + j, train->type04.data[i]);
-		}
-	}
-
-	return 0;
-}
-
-static int
-nve0_ram_train_init(struct nouveau_fb *pfb)
-{
-	u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb));
-	struct nve0_ram_train *train;
-	int ret = -ENOMEM, i;
-
-	if ((train = kzalloc(sizeof(*train), GFP_KERNEL))) {
-		for (i = 0; i < 0x100; i++) {
-			ret = nve0_ram_train_type(pfb, i, ramcfg, train);
-			if (ret && ret != -ENOENT)
-				break;
-		}
-	}
-
-	switch (pfb->ram->type) {
-	case NV_MEM_TYPE_GDDR5:
-		ret = nve0_ram_train_init_0(pfb, train);
-		break;
-	default:
-		ret = 0;
-		break;
-	}
-
-	kfree(train);
-	return ret;
-}
-
-int
-nve0_ram_init(struct nouveau_object *object)
-{
-	struct nouveau_fb *pfb = (void *)object->parent;
-	struct nve0_ram *ram   = (void *)object;
-	struct nouveau_bios *bios = nouveau_bios(pfb);
-	u8  ver, hdr, cnt, len, snr, ssz;
-	u32 data, save;
-	int ret, i;
-
-	ret = nouveau_ram_init(&ram->base);
-	if (ret)
-		return ret;
-
-	/* run a bunch of tables from rammap table.  there's actually
-	 * individual pointers for each rammap entry too, but, nvidia
-	 * seem to just run the last two entries' scripts early on in
-	 * their init, and never again.. we'll just run 'em all once
-	 * for now.
-	 *
-	 * i strongly suspect that each script is for a separate mode
-	 * (likely selected by 0x10f65c's lower bits?), and the
-	 * binary driver skips the one that's already been setup by
-	 * the init tables.
-	 */
-	data = nvbios_rammapTe(bios, &ver, &hdr, &cnt, &len, &snr, &ssz);
-	if (!data || hdr < 0x15)
-		return -EINVAL;
-
-	cnt  = nv_ro08(bios, data + 0x14); /* guess at count */
-	data = nv_ro32(bios, data + 0x10); /* guess u32... */
-	save = nv_rd32(pfb, 0x10f65c) & 0x000000f0;
-	for (i = 0; i < cnt; i++, data += 4) {
-		if (i != save >> 4) {
-			nv_mask(pfb, 0x10f65c, 0x000000f0, i << 4);
-			nvbios_exec(&(struct nvbios_init) {
-					.subdev = nv_subdev(pfb),
-					.bios = bios,
-					.offset = nv_ro32(bios, data),
-					.execute = 1,
-				    });
-		}
-	}
-	nv_mask(pfb, 0x10f65c, 0x000000f0, save);
-	nv_mask(pfb, 0x10f584, 0x11000000, 0x00000000);
-	nv_wr32(pfb, 0x10ecc0, 0xffffffff);
-	nv_mask(pfb, 0x10f160, 0x00000010, 0x00000010);
-
-	return nve0_ram_train_init(pfb);
-}
-
-static int
-nve0_ram_ctor_data(struct nve0_ram *ram, u8 ramcfg, int i)
-{
-	struct nouveau_fb *pfb = (void *)nv_object(ram)->parent;
-	struct nouveau_bios *bios = nouveau_bios(pfb);
-	struct nouveau_ram_data *cfg;
-	struct nvbios_ramcfg *d = &ram->diff;
-	struct nvbios_ramcfg *p, *n;
-	u8  ver, hdr, cnt, len;
-	u32 data;
-	int ret;
-
-	if (!(cfg = kmalloc(sizeof(*cfg), GFP_KERNEL)))
-		return -ENOMEM;
-	p = &list_last_entry(&ram->cfg, typeof(*cfg), head)->bios;
-	n = &cfg->bios;
-
-	/* memory config data for a range of target frequencies */
-	data = nvbios_rammapEp(bios, i, &ver, &hdr, &cnt, &len, &cfg->bios);
-	if (ret = -ENOENT, !data)
-		goto done;
-	if (ret = -ENOSYS, ver != 0x11 || hdr < 0x12)
-		goto done;
-
-	/* ... and a portion specific to the attached memory */
-	data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, ramcfg,
-			       &ver, &hdr, &cfg->bios);
-	if (ret = -EINVAL, !data)
-		goto done;
-	if (ret = -ENOSYS, ver != 0x11 || hdr < 0x0a)
-		goto done;
-
-	/* lookup memory timings, if bios says they're present */
-	if (cfg->bios.ramcfg_timing != 0xff) {
-		data = nvbios_timingEp(bios, cfg->bios.ramcfg_timing,
-				       &ver, &hdr, &cnt, &len,
-				       &cfg->bios);
-		if (ret = -EINVAL, !data)
-			goto done;
-		if (ret = -ENOSYS, ver != 0x20 || hdr < 0x33)
-			goto done;
-	}
-
-	list_add_tail(&cfg->head, &ram->cfg);
-	if (ret = 0, i == 0)
-		goto done;
-
-	d->rammap_11_0a_03fe |= p->rammap_11_0a_03fe != n->rammap_11_0a_03fe;
-	d->rammap_11_09_01ff |= p->rammap_11_09_01ff != n->rammap_11_09_01ff;
-	d->rammap_11_0a_0400 |= p->rammap_11_0a_0400 != n->rammap_11_0a_0400;
-	d->rammap_11_0a_0800 |= p->rammap_11_0a_0800 != n->rammap_11_0a_0800;
-	d->rammap_11_0b_01f0 |= p->rammap_11_0b_01f0 != n->rammap_11_0b_01f0;
-	d->rammap_11_0b_0200 |= p->rammap_11_0b_0200 != n->rammap_11_0b_0200;
-	d->rammap_11_0d |= p->rammap_11_0d != n->rammap_11_0d;
-	d->rammap_11_0f |= p->rammap_11_0f != n->rammap_11_0f;
-	d->rammap_11_0e |= p->rammap_11_0e != n->rammap_11_0e;
-	d->rammap_11_0b_0800 |= p->rammap_11_0b_0800 != n->rammap_11_0b_0800;
-	d->rammap_11_0b_0400 |= p->rammap_11_0b_0400 != n->rammap_11_0b_0400;
-	d->ramcfg_11_01_01 |= p->ramcfg_11_01_01 != n->ramcfg_11_01_01;
-	d->ramcfg_11_01_02 |= p->ramcfg_11_01_02 != n->ramcfg_11_01_02;
-	d->ramcfg_11_01_10 |= p->ramcfg_11_01_10 != n->ramcfg_11_01_10;
-	d->ramcfg_11_02_03 |= p->ramcfg_11_02_03 != n->ramcfg_11_02_03;
-	d->ramcfg_11_08_20 |= p->ramcfg_11_08_20 != n->ramcfg_11_08_20;
-	d->timing_20_30_07 |= p->timing_20_30_07 != n->timing_20_30_07;
-done:
-	if (ret)
-		kfree(cfg);
-	return ret;
-}
-
-static void
-nve0_ram_dtor(struct nouveau_object *object)
-{
-	struct nve0_ram *ram = (void *)object;
-	struct nouveau_ram_data *cfg, *tmp;
-
-	list_for_each_entry_safe(cfg, tmp, &ram->cfg, head) {
-		kfree(cfg);
-	}
-
-	nouveau_ram_destroy(&ram->base);
-}
-
-static int
-nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 size,
-	      struct nouveau_object **pobject)
-{
-	struct nouveau_fb *pfb = nouveau_fb(parent);
-	struct nouveau_bios *bios = nouveau_bios(pfb);
-	struct nouveau_gpio *gpio = nouveau_gpio(pfb);
-	struct dcb_gpio_func func;
-	struct nve0_ram *ram;
-	int ret, i;
-	u8  ramcfg = nvbios_ramcfg_index(nv_subdev(pfb));
-	u32 tmp;
-
-	ret = nvc0_ram_create(parent, engine, oclass, 0x022554, &ram);
-	*pobject = nv_object(ram);
-	if (ret)
-		return ret;
-
-	INIT_LIST_HEAD(&ram->cfg);
-
-	switch (ram->base.type) {
-	case NV_MEM_TYPE_DDR3:
-	case NV_MEM_TYPE_GDDR5:
-		ram->base.calc = nve0_ram_calc;
-		ram->base.prog = nve0_ram_prog;
-		ram->base.tidy = nve0_ram_tidy;
-		break;
-	default:
-		nv_warn(pfb, "reclocking of this RAM type is unsupported\n");
-		break;
-	}
-
-	/* calculate a mask of differently configured memory partitions,
-	 * because, of course reclocking wasn't complicated enough
-	 * already without having to treat some of them differently to
-	 * the others....
-	 */
-	ram->parts = nv_rd32(pfb, 0x022438);
-	ram->pmask = nv_rd32(pfb, 0x022554);
-	ram->pnuts = 0;
-	for (i = 0, tmp = 0; i < ram->parts; i++) {
-		if (!(ram->pmask & (1 << i))) {
-			u32 cfg1 = nv_rd32(pfb, 0x110204 + (i * 0x1000));
-			if (tmp && tmp != cfg1) {
-				ram->pnuts |= (1 << i);
-				continue;
-			}
-			tmp = cfg1;
-		}
-	}
-
-	/* parse bios data for all rammap table entries up-front, and
-	 * build information on whether certain fields differ between
-	 * any of the entries.
-	 *
-	 * the binary driver appears to completely ignore some fields
-	 * when all entries contain the same value.  at first, it was
-	 * hoped that these were mere optimisations and the bios init
-	 * tables had configured as per the values here, but there is
-	 * evidence now to suggest that this isn't the case and we do
-	 * need to treat this condition as a "don't touch" indicator.
-	 */
-	for (i = 0; !ret; i++) {
-		ret = nve0_ram_ctor_data(ram, ramcfg, i);
-		if (ret && ret != -ENOENT) {
-			nv_error(pfb, "failed to parse ramcfg data\n");
-			return ret;
-		}
-	}
-
-	/* parse bios data for both pll's */
-	ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll);
-	if (ret) {
-		nv_error(pfb, "mclk refpll data not found\n");
-		return ret;
-	}
-
-	ret = nvbios_pll_parse(bios, 0x04, &ram->fuc.mempll);
-	if (ret) {
-		nv_error(pfb, "mclk pll data not found\n");
-		return ret;
-	}
-
-	/* lookup memory voltage gpios */
-	ret = gpio->find(gpio, 0, 0x18, DCB_GPIO_UNUSED, &func);
-	if (ret == 0) {
-		ram->fuc.r_gpioMV = ramfuc_reg(0x00d610 + (func.line * 0x04));
-		ram->fuc.r_funcMV[0] = (func.log[0] ^ 2) << 12;
-		ram->fuc.r_funcMV[1] = (func.log[1] ^ 2) << 12;
-	}
-
-	ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func);
-	if (ret == 0) {
-		ram->fuc.r_gpio2E = ramfuc_reg(0x00d610 + (func.line * 0x04));
-		ram->fuc.r_func2E[0] = (func.log[0] ^ 2) << 12;
-		ram->fuc.r_func2E[1] = (func.log[1] ^ 2) << 12;
-	}
-
-	ram->fuc.r_gpiotrig = ramfuc_reg(0x00d604);
-
-	ram->fuc.r_0x132020 = ramfuc_reg(0x132020);
-	ram->fuc.r_0x132028 = ramfuc_reg(0x132028);
-	ram->fuc.r_0x132024 = ramfuc_reg(0x132024);
-	ram->fuc.r_0x132030 = ramfuc_reg(0x132030);
-	ram->fuc.r_0x132034 = ramfuc_reg(0x132034);
-	ram->fuc.r_0x132000 = ramfuc_reg(0x132000);
-	ram->fuc.r_0x132004 = ramfuc_reg(0x132004);
-	ram->fuc.r_0x132040 = ramfuc_reg(0x132040);
-
-	ram->fuc.r_0x10f248 = ramfuc_reg(0x10f248);
-	ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290);
-	ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294);
-	ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298);
-	ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c);
-	ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0);
-	ram->fuc.r_0x10f2a4 = ramfuc_reg(0x10f2a4);
-	ram->fuc.r_0x10f2a8 = ramfuc_reg(0x10f2a8);
-	ram->fuc.r_0x10f2ac = ramfuc_reg(0x10f2ac);
-	ram->fuc.r_0x10f2cc = ramfuc_reg(0x10f2cc);
-	ram->fuc.r_0x10f2e8 = ramfuc_reg(0x10f2e8);
-	ram->fuc.r_0x10f250 = ramfuc_reg(0x10f250);
-	ram->fuc.r_0x10f24c = ramfuc_reg(0x10f24c);
-	ram->fuc.r_0x10fec4 = ramfuc_reg(0x10fec4);
-	ram->fuc.r_0x10fec8 = ramfuc_reg(0x10fec8);
-	ram->fuc.r_0x10f604 = ramfuc_reg(0x10f604);
-	ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614);
-	ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610);
-	ram->fuc.r_0x100770 = ramfuc_reg(0x100770);
-	ram->fuc.r_0x100778 = ramfuc_reg(0x100778);
-	ram->fuc.r_0x10f224 = ramfuc_reg(0x10f224);
-
-	ram->fuc.r_0x10f870 = ramfuc_reg(0x10f870);
-	ram->fuc.r_0x10f698 = ramfuc_reg(0x10f698);
-	ram->fuc.r_0x10f694 = ramfuc_reg(0x10f694);
-	ram->fuc.r_0x10f6b8 = ramfuc_reg(0x10f6b8);
-	ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808);
-	ram->fuc.r_0x10f670 = ramfuc_reg(0x10f670);
-	ram->fuc.r_0x10f60c = ramfuc_reg(0x10f60c);
-	ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830);
-	ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec);
-	ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800);
-	ram->fuc.r_0x10f82c = ramfuc_reg(0x10f82c);
-
-	ram->fuc.r_0x10f978 = ramfuc_reg(0x10f978);
-	ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910);
-	ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914);
-
-	switch (ram->base.type) {
-	case NV_MEM_TYPE_GDDR5:
-		ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
-		ram->fuc.r_mr[1] = ramfuc_reg(0x10f330);
-		ram->fuc.r_mr[2] = ramfuc_reg(0x10f334);
-		ram->fuc.r_mr[3] = ramfuc_reg(0x10f338);
-		ram->fuc.r_mr[4] = ramfuc_reg(0x10f33c);
-		ram->fuc.r_mr[5] = ramfuc_reg(0x10f340);
-		ram->fuc.r_mr[6] = ramfuc_reg(0x10f344);
-		ram->fuc.r_mr[7] = ramfuc_reg(0x10f348);
-		ram->fuc.r_mr[8] = ramfuc_reg(0x10f354);
-		ram->fuc.r_mr[15] = ramfuc_reg(0x10f34c);
-		break;
-	case NV_MEM_TYPE_DDR3:
-		ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
-		ram->fuc.r_mr[2] = ramfuc_reg(0x10f320);
-		break;
-	default:
-		break;
-	}
-
-	ram->fuc.r_0x62c000 = ramfuc_reg(0x62c000);
-	ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200);
-	ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210);
-	ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310);
-	ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314);
-	ram->fuc.r_0x10f318 = ramfuc_reg(0x10f318);
-	ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090);
-	ram->fuc.r_0x10f69c = ramfuc_reg(0x10f69c);
-	ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824);
-	ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0);
-	ram->fuc.r_0x1373f4 = ramfuc_reg(0x1373f4);
-	ram->fuc.r_0x137320 = ramfuc_reg(0x137320);
-	ram->fuc.r_0x10f65c = ramfuc_reg(0x10f65c);
-	ram->fuc.r_0x10f6bc = ramfuc_reg(0x10f6bc);
-	ram->fuc.r_0x100710 = ramfuc_reg(0x100710);
-	ram->fuc.r_0x100750 = ramfuc_reg(0x100750);
-	return 0;
-}
-
-struct nouveau_oclass
-nve0_ram_oclass = {
-	.handle = 0,
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nve0_ram_ctor,
-		.dtor = nve0_ram_dtor,
-		.init = nve0_ram_init,
-		.fini = _nouveau_ram_fini,
-	}
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramseq.h b/drivers/gpu/drm/nouveau/core/subdev/fb/ramseq.h
deleted file mode 100644
index 571077e39071..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramseq.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef __NVKM_FBRAM_SEQ_H__
-#define __NVKM_FBRAM_SEQ_H__
-
-#include <subdev/bus.h>
-#include <subdev/bus/hwsq.h>
-
-#define ram_init(s,p)       hwsq_init(&(s)->base, (p))
-#define ram_exec(s,e)       hwsq_exec(&(s)->base, (e))
-#define ram_have(s,r)       ((s)->r_##r.addr != 0x000000)
-#define ram_rd32(s,r)       hwsq_rd32(&(s)->base, &(s)->r_##r)
-#define ram_wr32(s,r,d)     hwsq_wr32(&(s)->base, &(s)->r_##r, (d))
-#define ram_nuke(s,r)       hwsq_nuke(&(s)->base, &(s)->r_##r)
-#define ram_mask(s,r,m,d)   hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d))
-#define ram_setf(s,f,d)     hwsq_setf(&(s)->base, (f), (d))
-#define ram_wait(s,f,d)     hwsq_wait(&(s)->base, (f), (d))
-#define ram_nsec(s,n)       hwsq_nsec(&(s)->base, (n))
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c
deleted file mode 100644
index 252575f3aa29..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright 2014 Roy Spliet
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Roy Spliet <rspliet@eclipso.eu>
- *          Ben Skeggs
- */
-
-#include "priv.h"
-
-struct ramxlat {
-	int id;
-	u8 enc;
-};
-
-static inline int
-ramxlat(const struct ramxlat *xlat, int id)
-{
-	while (xlat->id >= 0) {
-		if (xlat->id == id)
-			return xlat->enc;
-		xlat++;
-	}
-	return -EINVAL;
-}
-
-static const struct ramxlat
-ramddr2_cl[] = {
-	{ 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 },
-	/* The following are available in some, but not all DDR2 docs */
-	{ 7, 7 },
-	{ -1 }
-};
-
-static const struct ramxlat
-ramddr2_wr[] = {
-	{ 2, 1 }, { 3, 2 }, { 4, 3 }, { 5, 4 }, { 6, 5 },
-	/* The following are available in some, but not all DDR2 docs */
-	{ 7, 6 },
-	{ -1 }
-};
-
-int
-nouveau_sddr2_calc(struct nouveau_ram *ram)
-{
-	int CL, WR, DLL = 0, ODT = 0;
-
-	switch (ram->next->bios.timing_ver) {
-	case 0x10:
-		CL  = ram->next->bios.timing_10_CL;
-		WR  = ram->next->bios.timing_10_WR;
-		DLL = !ram->next->bios.ramcfg_10_DLLoff;
-		ODT = ram->next->bios.timing_10_ODT & 3;
-		break;
-	case 0x20:
-		CL  = (ram->next->bios.timing[1] & 0x0000001f);
-		WR  = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
-		break;
-	default:
-		return -ENOSYS;
-	}
-
-	CL  = ramxlat(ramddr2_cl, CL);
-	WR  = ramxlat(ramddr2_wr, WR);
-	if (CL < 0 || WR < 0)
-		return -EINVAL;
-
-	ram->mr[0] &= ~0xf70;
-	ram->mr[0] |= (WR & 0x07) << 9;
-	ram->mr[0] |= (CL & 0x07) << 4;
-
-	ram->mr[1] &= ~0x045;
-	ram->mr[1] |= (ODT & 0x1) << 2;
-	ram->mr[1] |= (ODT & 0x2) << 5;
-	ram->mr[1] |= !DLL;
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c
deleted file mode 100644
index a2dca4869e52..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- * 	    Roy Spliet <rspliet@eclipso.eu>
- */
-
-#include "priv.h"
-
-struct ramxlat {
-	int id;
-	u8 enc;
-};
-
-static inline int
-ramxlat(const struct ramxlat *xlat, int id)
-{
-	while (xlat->id >= 0) {
-		if (xlat->id == id)
-			return xlat->enc;
-		xlat++;
-	}
-	return -EINVAL;
-}
-
-static const struct ramxlat
-ramddr3_cl[] = {
-	{ 5, 2 }, { 6, 4 }, { 7, 6 }, { 8, 8 }, { 9, 10 }, { 10, 12 },
-	{ 11, 14 },
-	/* the below are mentioned in some, but not all, ddr3 docs */
-	{ 12, 1 }, { 13, 3 }, { 14, 5 },
-	{ -1 }
-};
-
-static const struct ramxlat
-ramddr3_wr[] = {
-	{ 5, 1 }, { 6, 2 }, { 7, 3 }, { 8, 4 }, { 10, 5 }, { 12, 6 },
-	/* the below are mentioned in some, but not all, ddr3 docs */
-	{ 14, 7 }, { 16, 0 },
-	{ -1 }
-};
-
-static const struct ramxlat
-ramddr3_cwl[] = {
-	{ 5, 0 }, { 6, 1 }, { 7, 2 }, { 8, 3 },
-	/* the below are mentioned in some, but not all, ddr3 docs */
-	{ 9, 4 },
-	{ -1 }
-};
-
-int
-nouveau_sddr3_calc(struct nouveau_ram *ram)
-{
-	int CWL, CL, WR, DLL = 0, ODT = 0;
-
-	switch (ram->next->bios.timing_ver) {
-	case 0x10:
-		if (ram->next->bios.timing_hdr < 0x17) {
-			/* XXX: NV50: Get CWL from the timing register */
-			return -ENOSYS;
-		}
-		CWL = ram->next->bios.timing_10_CWL;
-		CL  = ram->next->bios.timing_10_CL;
-		WR  = ram->next->bios.timing_10_WR;
-		DLL = !ram->next->bios.ramcfg_10_DLLoff;
-		ODT = ram->next->bios.timing_10_ODT;
-		break;
-	case 0x20:
-		CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
-		CL  = (ram->next->bios.timing[1] & 0x0000001f) >> 0;
-		WR  = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
-		/* XXX: Get these values from the VBIOS instead */
-		DLL = !(ram->mr[1] & 0x1);
-		ODT =   (ram->mr[1] & 0x004) >> 2 |
-			(ram->mr[1] & 0x040) >> 5 |
-		        (ram->mr[1] & 0x200) >> 7;
-		break;
-	default:
-		return -ENOSYS;
-	}
-
-	CWL = ramxlat(ramddr3_cwl, CWL);
-	CL  = ramxlat(ramddr3_cl, CL);
-	WR  = ramxlat(ramddr3_wr, WR);
-	if (CL < 0 || CWL < 0 || WR < 0)
-		return -EINVAL;
-
-	ram->mr[0] &= ~0xf74;
-	ram->mr[0] |= (WR & 0x07) << 9;
-	ram->mr[0] |= (CL & 0x0e) << 3;
-	ram->mr[0] |= (CL & 0x01) << 2;
-
-	ram->mr[1] &= ~0x245;
-	ram->mr[1] |= (ODT & 0x1) << 2;
-	ram->mr[1] |= (ODT & 0x2) << 5;
-	ram->mr[1] |= (ODT & 0x4) << 7;
-	ram->mr[1] |= !DLL;
-
-	ram->mr[2] &= ~0x038;
-	ram->mr[2] |= (CWL & 0x07) << 3;
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/base.c b/drivers/gpu/drm/nouveau/core/subdev/fuse/base.c
deleted file mode 100644
index 9e8e92127715..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fuse/base.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2014 Martin Peres
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres
- */
-
-#include <subdev/fuse.h>
-
-int
-_nouveau_fuse_init(struct nouveau_object *object)
-{
-	struct nouveau_fuse *fuse = (void *)object;
-	return nouveau_subdev_init(&fuse->base);
-}
-
-void
-_nouveau_fuse_dtor(struct nouveau_object *object)
-{
-	struct nouveau_fuse *fuse = (void *)object;
-	nouveau_subdev_destroy(&fuse->base);
-}
-
-int
-nouveau_fuse_create_(struct nouveau_object *parent,
-		     struct nouveau_object *engine,
-		     struct nouveau_oclass *oclass, int length, void **pobject)
-{
-	struct nouveau_fuse *fuse;
-	int ret;
-
-	ret = nouveau_subdev_create_(parent, engine, oclass, 0, "FUSE",
-				     "fuse", length, pobject);
-	fuse = *pobject;
-
-	return ret;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/g80.c b/drivers/gpu/drm/nouveau/core/subdev/fuse/g80.c
deleted file mode 100644
index a374ade485be..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fuse/g80.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright 2014 Martin Peres
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres
- */
-
-#include "priv.h"
-
-struct g80_fuse_priv {
-	struct nouveau_fuse base;
-
-	spinlock_t fuse_enable_lock;
-};
-
-static u32
-g80_fuse_rd32(struct nouveau_object *object, u64 addr)
-{
-	struct g80_fuse_priv *priv = (void *)object;
-	unsigned long flags;
-	u32 fuse_enable, val;
-
-	spin_lock_irqsave(&priv->fuse_enable_lock, flags);
-
-	/* racy if another part of nouveau start writing to this reg */
-	fuse_enable = nv_mask(priv, 0x1084, 0x800, 0x800);
-	val = nv_rd32(priv, 0x21000 + addr);
-	nv_wr32(priv, 0x1084, fuse_enable);
-
-	spin_unlock_irqrestore(&priv->fuse_enable_lock, flags);
-
-	return val;
-}
-
-
-static int
-g80_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct g80_fuse_priv *priv;
-	int ret;
-
-	ret = nouveau_fuse_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	spin_lock_init(&priv->fuse_enable_lock);
-
-	return 0;
-}
-
-struct nouveau_oclass
-g80_fuse_oclass = {
-	.handle = NV_SUBDEV(FUSE, 0x50),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = g80_fuse_ctor,
-		.dtor = _nouveau_fuse_dtor,
-		.init = _nouveau_fuse_init,
-		.fini = _nouveau_fuse_fini,
-		.rd32 = g80_fuse_rd32,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/gf100.c b/drivers/gpu/drm/nouveau/core/subdev/fuse/gf100.c
deleted file mode 100644
index 5ed03f54b3d4..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fuse/gf100.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright 2014 Martin Peres
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres
- */
-
-#include "priv.h"
-
-struct gf100_fuse_priv {
-	struct nouveau_fuse base;
-
-	spinlock_t fuse_enable_lock;
-};
-
-static u32
-gf100_fuse_rd32(struct nouveau_object *object, u64 addr)
-{
-	struct gf100_fuse_priv *priv = (void *)object;
-	unsigned long flags;
-	u32 fuse_enable, unk, val;
-
-	spin_lock_irqsave(&priv->fuse_enable_lock, flags);
-
-	/* racy if another part of nouveau start writing to these regs */
-	fuse_enable = nv_mask(priv, 0x22400, 0x800, 0x800);
-	unk = nv_mask(priv, 0x21000, 0x1, 0x1);
-	val = nv_rd32(priv, 0x21100 + addr);
-	nv_wr32(priv, 0x21000, unk);
-	nv_wr32(priv, 0x22400, fuse_enable);
-
-	spin_unlock_irqrestore(&priv->fuse_enable_lock, flags);
-
-	return val;
-}
-
-
-static int
-gf100_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct gf100_fuse_priv *priv;
-	int ret;
-
-	ret = nouveau_fuse_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	spin_lock_init(&priv->fuse_enable_lock);
-
-	return 0;
-}
-
-struct nouveau_oclass
-gf100_fuse_oclass = {
-	.handle = NV_SUBDEV(FUSE, 0xC0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = gf100_fuse_ctor,
-		.dtor = _nouveau_fuse_dtor,
-		.init = _nouveau_fuse_init,
-		.fini = _nouveau_fuse_fini,
-		.rd32 = gf100_fuse_rd32,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/gm107.c b/drivers/gpu/drm/nouveau/core/subdev/fuse/gm107.c
deleted file mode 100644
index 4f1a636c6538..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fuse/gm107.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright 2014 Martin Peres
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres
- */
-
-#include "priv.h"
-
-struct gm107_fuse_priv {
-	struct nouveau_fuse base;
-};
-
-static u32
-gm107_fuse_rd32(struct nouveau_object *object, u64 addr)
-{
-	struct gf100_fuse_priv *priv = (void *)object;
-
-	return nv_rd32(priv, 0x21100 + addr);
-}
-
-
-static int
-gm107_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct gm107_fuse_priv *priv;
-	int ret;
-
-	ret = nouveau_fuse_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-struct nouveau_oclass
-gm107_fuse_oclass = {
-	.handle = NV_SUBDEV(FUSE, 0x117),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = gm107_fuse_ctor,
-		.dtor = _nouveau_fuse_dtor,
-		.init = _nouveau_fuse_init,
-		.fini = _nouveau_fuse_fini,
-		.rd32 = gm107_fuse_rd32,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/priv.h b/drivers/gpu/drm/nouveau/core/subdev/fuse/priv.h
deleted file mode 100644
index d2085411a5cb..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/fuse/priv.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __NVKM_FUSE_PRIV_H__
-#define __NVKM_FUSE_PRIV_H__
-
-#include <subdev/fuse.h>
-
-int _nouveau_fuse_init(struct nouveau_object *object);
-void _nouveau_fuse_dtor(struct nouveau_object *object);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c
deleted file mode 100644
index 7ad99b763f4c..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * Copyright 2011 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/bios.h>
-#include <subdev/bios/gpio.h>
-
-#include "priv.h"
-
-static int
-nouveau_gpio_drive(struct nouveau_gpio *gpio,
-		   int idx, int line, int dir, int out)
-{
-	const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass;
-	return impl->drive ? impl->drive(gpio, line, dir, out) : -ENODEV;
-}
-
-static int
-nouveau_gpio_sense(struct nouveau_gpio *gpio, int idx, int line)
-{
-	const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass;
-	return impl->sense ? impl->sense(gpio, line) : -ENODEV;
-}
-
-static int
-nouveau_gpio_find(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line,
-		  struct dcb_gpio_func *func)
-{
-	struct nouveau_bios *bios = nouveau_bios(gpio);
-	u8  ver, len;
-	u16 data;
-
-	if (line == 0xff && tag == 0xff)
-		return -EINVAL;
-
-	data = dcb_gpio_match(bios, idx, tag, line, &ver, &len, func);
-	if (data)
-		return 0;
-
-	/* Apple iMac G4 NV18 */
-	if (nv_device_match(nv_object(gpio), 0x0189, 0x10de, 0x0010)) {
-		if (tag == DCB_GPIO_TVDAC0) {
-			*func = (struct dcb_gpio_func) {
-				.func = DCB_GPIO_TVDAC0,
-				.line = 4,
-				.log[0] = 0,
-				.log[1] = 1,
-			};
-			return 0;
-		}
-	}
-
-	return -ENOENT;
-}
-
-static int
-nouveau_gpio_set(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line, int state)
-{
-	struct dcb_gpio_func func;
-	int ret;
-
-	ret = nouveau_gpio_find(gpio, idx, tag, line, &func);
-	if (ret == 0) {
-		int dir = !!(func.log[state] & 0x02);
-		int out = !!(func.log[state] & 0x01);
-		ret = nouveau_gpio_drive(gpio, idx, func.line, dir, out);
-	}
-
-	return ret;
-}
-
-static int
-nouveau_gpio_get(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line)
-{
-	struct dcb_gpio_func func;
-	int ret;
-
-	ret = nouveau_gpio_find(gpio, idx, tag, line, &func);
-	if (ret == 0) {
-		ret = nouveau_gpio_sense(gpio, idx, func.line);
-		if (ret >= 0)
-			ret = (ret == (func.log[1] & 1));
-	}
-
-	return ret;
-}
-
-static void
-nouveau_gpio_intr_fini(struct nvkm_event *event, int type, int index)
-{
-	struct nouveau_gpio *gpio = container_of(event, typeof(*gpio), event);
-	const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass;
-	impl->intr_mask(gpio, type, 1 << index, 0);
-}
-
-static void
-nouveau_gpio_intr_init(struct nvkm_event *event, int type, int index)
-{
-	struct nouveau_gpio *gpio = container_of(event, typeof(*gpio), event);
-	const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass;
-	impl->intr_mask(gpio, type, 1 << index, 1 << index);
-}
-
-static int
-nouveau_gpio_intr_ctor(struct nouveau_object *object, void *data, u32 size,
-		       struct nvkm_notify *notify)
-{
-	struct nvkm_gpio_ntfy_req *req = data;
-	if (!WARN_ON(size != sizeof(*req))) {
-		notify->size  = sizeof(struct nvkm_gpio_ntfy_rep);
-		notify->types = req->mask;
-		notify->index = req->line;
-		return 0;
-	}
-	return -EINVAL;
-}
-
-static void
-nouveau_gpio_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_gpio *gpio = nouveau_gpio(subdev);
-	const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass;
-	u32 hi, lo, i;
-
-	impl->intr_stat(gpio, &hi, &lo);
-
-	for (i = 0; (hi | lo) && i < impl->lines; i++) {
-		struct nvkm_gpio_ntfy_rep rep = {
-			.mask = (NVKM_GPIO_HI * !!(hi & (1 << i))) |
-				(NVKM_GPIO_LO * !!(lo & (1 << i))),
-		};
-		nvkm_event_send(&gpio->event, rep.mask, i, &rep, sizeof(rep));
-	}
-}
-
-static const struct nvkm_event_func
-nouveau_gpio_intr_func = {
-	.ctor = nouveau_gpio_intr_ctor,
-	.init = nouveau_gpio_intr_init,
-	.fini = nouveau_gpio_intr_fini,
-};
-
-int
-_nouveau_gpio_fini(struct nouveau_object *object, bool suspend)
-{
-	const struct nouveau_gpio_impl *impl = (void *)object->oclass;
-	struct nouveau_gpio *gpio = nouveau_gpio(object);
-	u32 mask = (1 << impl->lines) - 1;
-
-	impl->intr_mask(gpio, NVKM_GPIO_TOGGLED, mask, 0);
-	impl->intr_stat(gpio, &mask, &mask);
-
-	return nouveau_subdev_fini(&gpio->base, suspend);
-}
-
-static struct dmi_system_id gpio_reset_ids[] = {
-	{
-		.ident = "Apple Macbook 10,1",
-		.matches = {
-			DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
-			DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro10,1"),
-		}
-	},
-	{ }
-};
-
-int
-_nouveau_gpio_init(struct nouveau_object *object)
-{
-	struct nouveau_gpio *gpio = nouveau_gpio(object);
-	int ret;
-
-	ret = nouveau_subdev_init(&gpio->base);
-	if (ret)
-		return ret;
-
-	if (gpio->reset && dmi_check_system(gpio_reset_ids))
-		gpio->reset(gpio, DCB_GPIO_UNUSED);
-
-	return ret;
-}
-
-void
-_nouveau_gpio_dtor(struct nouveau_object *object)
-{
-	struct nouveau_gpio *gpio = (void *)object;
-	nvkm_event_fini(&gpio->event);
-	nouveau_subdev_destroy(&gpio->base);
-}
-
-int
-nouveau_gpio_create_(struct nouveau_object *parent,
-		     struct nouveau_object *engine,
-		     struct nouveau_oclass *oclass,
-		     int length, void **pobject)
-{
-	const struct nouveau_gpio_impl *impl = (void *)oclass;
-	struct nouveau_gpio *gpio;
-	int ret;
-
-	ret = nouveau_subdev_create_(parent, engine, oclass, 0, "GPIO", "gpio",
-				     length, pobject);
-	gpio = *pobject;
-	if (ret)
-		return ret;
-
-	gpio->find = nouveau_gpio_find;
-	gpio->set  = nouveau_gpio_set;
-	gpio->get  = nouveau_gpio_get;
-	gpio->reset = impl->reset;
-
-	ret = nvkm_event_init(&nouveau_gpio_intr_func, 2, impl->lines,
-			      &gpio->event);
-	if (ret)
-		return ret;
-
-	nv_subdev(gpio)->intr = nouveau_gpio_intr;
-	return 0;
-}
-
-int
-_nouveau_gpio_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		   struct nouveau_oclass *oclass, void *data, u32 size,
-		   struct nouveau_object **pobject)
-{
-	struct nouveau_gpio *gpio;
-	int ret;
-
-	ret = nouveau_gpio_create(parent, engine, oclass, &gpio);
-	*pobject = nv_object(gpio);
-	if (ret)
-		return ret;
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv10.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/nv10.c
deleted file mode 100644
index 27ad23eaf185..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv10.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright (C) 2009 Francisco Jerez.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "priv.h"
-
-static int
-nv10_gpio_sense(struct nouveau_gpio *gpio, int line)
-{
-	if (line < 2) {
-		line = line * 16;
-		line = nv_rd32(gpio, 0x600818) >> line;
-		return !!(line & 0x0100);
-	} else
-	if (line < 10) {
-		line = (line - 2) * 4;
-		line = nv_rd32(gpio, 0x60081c) >> line;
-		return !!(line & 0x04);
-	} else
-	if (line < 14) {
-		line = (line - 10) * 4;
-		line = nv_rd32(gpio, 0x600850) >> line;
-		return !!(line & 0x04);
-	}
-
-	return -EINVAL;
-}
-
-static int
-nv10_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out)
-{
-	u32 reg, mask, data;
-
-	if (line < 2) {
-		line = line * 16;
-		reg  = 0x600818;
-		mask = 0x00000011;
-		data = (dir << 4) | out;
-	} else
-	if (line < 10) {
-		line = (line - 2) * 4;
-		reg  = 0x60081c;
-		mask = 0x00000003;
-		data = (dir << 1) | out;
-	} else
-	if (line < 14) {
-		line = (line - 10) * 4;
-		reg  = 0x600850;
-		mask = 0x00000003;
-		data = (dir << 1) | out;
-	} else {
-		return -EINVAL;
-	}
-
-	nv_mask(gpio, reg, mask << line, data << line);
-	return 0;
-}
-
-static void
-nv10_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo)
-{
-	u32 intr = nv_rd32(gpio, 0x001104);
-	u32 stat = nv_rd32(gpio, 0x001144) & intr;
-	*lo = (stat & 0xffff0000) >> 16;
-	*hi = (stat & 0x0000ffff);
-	nv_wr32(gpio, 0x001104, intr);
-}
-
-static void
-nv10_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data)
-{
-	u32 inte = nv_rd32(gpio, 0x001144);
-	if (type & NVKM_GPIO_LO)
-		inte = (inte & ~(mask << 16)) | (data << 16);
-	if (type & NVKM_GPIO_HI)
-		inte = (inte & ~mask) | data;
-	nv_wr32(gpio, 0x001144, inte);
-}
-
-struct nouveau_oclass *
-nv10_gpio_oclass = &(struct nouveau_gpio_impl) {
-	.base.handle = NV_SUBDEV(GPIO, 0x10),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_gpio_ctor,
-		.dtor = _nouveau_gpio_dtor,
-		.init = _nouveau_gpio_init,
-		.fini = _nouveau_gpio_fini,
-	},
-	.lines = 16,
-	.intr_stat = nv10_gpio_intr_stat,
-	.intr_mask = nv10_gpio_intr_mask,
-	.drive = nv10_gpio_drive,
-	.sense = nv10_gpio_sense,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c
deleted file mode 100644
index 2e30d5a62d6e..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-
-void
-nv50_gpio_reset(struct nouveau_gpio *gpio, u8 match)
-{
-	struct nouveau_bios *bios = nouveau_bios(gpio);
-	u8 ver, len;
-	u16 entry;
-	int ent = -1;
-
-	while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) {
-		static const u32 regs[] = { 0xe100, 0xe28c };
-		u32 data = nv_ro32(bios, entry);
-		u8  line =   (data & 0x0000001f);
-		u8  func =   (data & 0x0000ff00) >> 8;
-		u8  defs = !!(data & 0x01000000);
-		u8  unk0 = !!(data & 0x02000000);
-		u8  unk1 = !!(data & 0x04000000);
-		u32 val = (unk1 << 16) | unk0;
-		u32 reg = regs[line >> 4];
-		u32 lsh = line & 0x0f;
-
-		if ( func  == DCB_GPIO_UNUSED ||
-		    (match != DCB_GPIO_UNUSED && match != func))
-			continue;
-
-		gpio->set(gpio, 0, func, line, defs);
-
-		nv_mask(gpio, reg, 0x00010001 << lsh, val << lsh);
-	}
-}
-
-int
-nv50_gpio_location(int line, u32 *reg, u32 *shift)
-{
-	const u32 nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
-
-	if (line >= 32)
-		return -EINVAL;
-
-	*reg = nv50_gpio_reg[line >> 3];
-	*shift = (line & 7) << 2;
-	return 0;
-}
-
-int
-nv50_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out)
-{
-	u32 reg, shift;
-
-	if (nv50_gpio_location(line, &reg, &shift))
-		return -EINVAL;
-
-	nv_mask(gpio, reg, 3 << shift, (((dir ^ 1) << 1) | out) << shift);
-	return 0;
-}
-
-int
-nv50_gpio_sense(struct nouveau_gpio *gpio, int line)
-{
-	u32 reg, shift;
-
-	if (nv50_gpio_location(line, &reg, &shift))
-		return -EINVAL;
-
-	return !!(nv_rd32(gpio, reg) & (4 << shift));
-}
-
-static void
-nv50_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo)
-{
-	u32 intr = nv_rd32(gpio, 0x00e054);
-	u32 stat = nv_rd32(gpio, 0x00e050) & intr;
-	*lo = (stat & 0xffff0000) >> 16;
-	*hi = (stat & 0x0000ffff);
-	nv_wr32(gpio, 0x00e054, intr);
-}
-
-static void
-nv50_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data)
-{
-	u32 inte = nv_rd32(gpio, 0x00e050);
-	if (type & NVKM_GPIO_LO)
-		inte = (inte & ~(mask << 16)) | (data << 16);
-	if (type & NVKM_GPIO_HI)
-		inte = (inte & ~mask) | data;
-	nv_wr32(gpio, 0x00e050, inte);
-}
-
-struct nouveau_oclass *
-nv50_gpio_oclass = &(struct nouveau_gpio_impl) {
-	.base.handle = NV_SUBDEV(GPIO, 0x50),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_gpio_ctor,
-		.dtor = _nouveau_gpio_dtor,
-		.init = _nouveau_gpio_init,
-		.fini = _nouveau_gpio_fini,
-	},
-	.lines = 16,
-	.intr_stat = nv50_gpio_intr_stat,
-	.intr_mask = nv50_gpio_intr_mask,
-	.drive = nv50_gpio_drive,
-	.sense = nv50_gpio_sense,
-	.reset = nv50_gpio_reset,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv94.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/nv94.c
deleted file mode 100644
index cae404ccadac..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv94.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-
-void
-nv94_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo)
-{
-	u32 intr0 = nv_rd32(gpio, 0x00e054);
-	u32 intr1 = nv_rd32(gpio, 0x00e074);
-	u32 stat0 = nv_rd32(gpio, 0x00e050) & intr0;
-	u32 stat1 = nv_rd32(gpio, 0x00e070) & intr1;
-	*lo = (stat1 & 0xffff0000) | (stat0 >> 16);
-	*hi = (stat1 << 16) | (stat0 & 0x0000ffff);
-	nv_wr32(gpio, 0x00e054, intr0);
-	nv_wr32(gpio, 0x00e074, intr1);
-}
-
-void
-nv94_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data)
-{
-	u32 inte0 = nv_rd32(gpio, 0x00e050);
-	u32 inte1 = nv_rd32(gpio, 0x00e070);
-	if (type & NVKM_GPIO_LO)
-		inte0 = (inte0 & ~(mask << 16)) | (data << 16);
-	if (type & NVKM_GPIO_HI)
-		inte0 = (inte0 & ~(mask & 0xffff)) | (data & 0xffff);
-	mask >>= 16;
-	data >>= 16;
-	if (type & NVKM_GPIO_LO)
-		inte1 = (inte1 & ~(mask << 16)) | (data << 16);
-	if (type & NVKM_GPIO_HI)
-		inte1 = (inte1 & ~mask) | data;
-	nv_wr32(gpio, 0x00e050, inte0);
-	nv_wr32(gpio, 0x00e070, inte1);
-}
-
-struct nouveau_oclass *
-nv94_gpio_oclass = &(struct nouveau_gpio_impl) {
-	.base.handle = NV_SUBDEV(GPIO, 0x94),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_gpio_ctor,
-		.dtor = _nouveau_gpio_dtor,
-		.init = _nouveau_gpio_init,
-		.fini = _nouveau_gpio_fini,
-	},
-	.lines = 32,
-	.intr_stat = nv94_gpio_intr_stat,
-	.intr_mask = nv94_gpio_intr_mask,
-	.drive = nv50_gpio_drive,
-	.sense = nv50_gpio_sense,
-	.reset = nv50_gpio_reset,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c
deleted file mode 100644
index 480d6d2af770..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-
-void
-nvd0_gpio_reset(struct nouveau_gpio *gpio, u8 match)
-{
-	struct nouveau_bios *bios = nouveau_bios(gpio);
-	u8 ver, len;
-	u16 entry;
-	int ent = -1;
-
-	while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) {
-		u32 data = nv_ro32(bios, entry);
-		u8  line =   (data & 0x0000003f);
-		u8  defs = !!(data & 0x00000080);
-		u8  func =   (data & 0x0000ff00) >> 8;
-		u8  unk0 =   (data & 0x00ff0000) >> 16;
-		u8  unk1 =   (data & 0x1f000000) >> 24;
-
-		if ( func  == DCB_GPIO_UNUSED ||
-		    (match != DCB_GPIO_UNUSED && match != func))
-			continue;
-
-		gpio->set(gpio, 0, func, line, defs);
-
-		nv_mask(gpio, 0x00d610 + (line * 4), 0xff, unk0);
-		if (unk1--)
-			nv_mask(gpio, 0x00d740 + (unk1 * 4), 0xff, line);
-	}
-}
-
-int
-nvd0_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out)
-{
-	u32 data = ((dir ^ 1) << 13) | (out << 12);
-	nv_mask(gpio, 0x00d610 + (line * 4), 0x00003000, data);
-	nv_mask(gpio, 0x00d604, 0x00000001, 0x00000001); /* update? */
-	return 0;
-}
-
-int
-nvd0_gpio_sense(struct nouveau_gpio *gpio, int line)
-{
-	return !!(nv_rd32(gpio, 0x00d610 + (line * 4)) & 0x00004000);
-}
-
-struct nouveau_oclass *
-nvd0_gpio_oclass = &(struct nouveau_gpio_impl) {
-	.base.handle = NV_SUBDEV(GPIO, 0xd0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_gpio_ctor,
-		.dtor = _nouveau_gpio_dtor,
-		.init = _nouveau_gpio_init,
-		.fini = _nouveau_gpio_fini,
-	},
-	.lines = 32,
-	.intr_stat = nv94_gpio_intr_stat,
-	.intr_mask = nv94_gpio_intr_mask,
-	.drive = nvd0_gpio_drive,
-	.sense = nvd0_gpio_sense,
-	.reset = nvd0_gpio_reset,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/nve0.c
deleted file mode 100644
index e1145b48c76c..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nve0.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-
-static void
-nve0_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo)
-{
-	u32 intr0 = nv_rd32(gpio, 0x00dc00);
-	u32 intr1 = nv_rd32(gpio, 0x00dc80);
-	u32 stat0 = nv_rd32(gpio, 0x00dc08) & intr0;
-	u32 stat1 = nv_rd32(gpio, 0x00dc88) & intr1;
-	*lo = (stat1 & 0xffff0000) | (stat0 >> 16);
-	*hi = (stat1 << 16) | (stat0 & 0x0000ffff);
-	nv_wr32(gpio, 0x00dc00, intr0);
-	nv_wr32(gpio, 0x00dc80, intr1);
-}
-
-void
-nve0_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data)
-{
-	u32 inte0 = nv_rd32(gpio, 0x00dc08);
-	u32 inte1 = nv_rd32(gpio, 0x00dc88);
-	if (type & NVKM_GPIO_LO)
-		inte0 = (inte0 & ~(mask << 16)) | (data << 16);
-	if (type & NVKM_GPIO_HI)
-		inte0 = (inte0 & ~(mask & 0xffff)) | (data & 0xffff);
-	mask >>= 16;
-	data >>= 16;
-	if (type & NVKM_GPIO_LO)
-		inte1 = (inte1 & ~(mask << 16)) | (data << 16);
-	if (type & NVKM_GPIO_HI)
-		inte1 = (inte1 & ~mask) | data;
-	nv_wr32(gpio, 0x00dc08, inte0);
-	nv_wr32(gpio, 0x00dc88, inte1);
-}
-
-struct nouveau_oclass *
-nve0_gpio_oclass = &(struct nouveau_gpio_impl) {
-	.base.handle = NV_SUBDEV(GPIO, 0xe0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_gpio_ctor,
-		.dtor = _nouveau_gpio_dtor,
-		.init = _nouveau_gpio_init,
-		.fini = _nouveau_gpio_fini,
-	},
-	.lines = 32,
-	.intr_stat = nve0_gpio_intr_stat,
-	.intr_mask = nve0_gpio_intr_mask,
-	.drive = nvd0_gpio_drive,
-	.sense = nvd0_gpio_sense,
-	.reset = nvd0_gpio_reset,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h b/drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h
deleted file mode 100644
index bff98b86e2b5..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h
+++ /dev/null
@@ -1,67 +0,0 @@
-#ifndef __NVKM_GPIO_H__
-#define __NVKM_GPIO_H__
-
-#include <subdev/gpio.h>
-
-#define nouveau_gpio_create(p,e,o,d)                                           \
-	nouveau_gpio_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_gpio_destroy(p) ({                                             \
-	struct nouveau_gpio *gpio = (p);                                       \
-	_nouveau_gpio_dtor(nv_object(gpio));                                   \
-})
-#define nouveau_gpio_init(p) ({                                                \
-	struct nouveau_gpio *gpio = (p);                                       \
-	_nouveau_gpio_init(nv_object(gpio));                                   \
-})
-#define nouveau_gpio_fini(p,s) ({                                              \
-	struct nouveau_gpio *gpio = (p);                                       \
-	_nouveau_gpio_fini(nv_object(gpio), (s));                              \
-})
-
-int  nouveau_gpio_create_(struct nouveau_object *, struct nouveau_object *,
-			  struct nouveau_oclass *, int, void **);
-int  _nouveau_gpio_ctor(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, void *, u32,
-			struct nouveau_object **);
-void _nouveau_gpio_dtor(struct nouveau_object *);
-int  _nouveau_gpio_init(struct nouveau_object *);
-int  _nouveau_gpio_fini(struct nouveau_object *, bool);
-
-struct nouveau_gpio_impl {
-	struct nouveau_oclass base;
-	int lines;
-
-	/* read and ack pending interrupts, returning only data
-	 * for lines that have not been masked off, while still
-	 * performing the ack for anything that was pending.
-	 */
-	void (*intr_stat)(struct nouveau_gpio *, u32 *, u32 *);
-
-	/* mask on/off interrupts for hi/lo transitions on a
-	 * given set of gpio lines
-	 */
-	void (*intr_mask)(struct nouveau_gpio *, u32, u32, u32);
-
-	/* configure gpio direction and output value */
-	int  (*drive)(struct nouveau_gpio *, int line, int dir, int out);
-
-	/* sense current state of given gpio line */
-	int  (*sense)(struct nouveau_gpio *, int line);
-
-	/*XXX*/
-	void (*reset)(struct nouveau_gpio *, u8);
-};
-
-void nv50_gpio_reset(struct nouveau_gpio *, u8);
-int  nv50_gpio_drive(struct nouveau_gpio *, int, int, int);
-int  nv50_gpio_sense(struct nouveau_gpio *, int);
-
-void nv94_gpio_intr_stat(struct nouveau_gpio *, u32 *, u32 *);
-void nv94_gpio_intr_mask(struct nouveau_gpio *, u32, u32, u32);
-
-void nvd0_gpio_reset(struct nouveau_gpio *, u8);
-int  nvd0_gpio_drive(struct nouveau_gpio *, int, int, int);
-int  nvd0_gpio_sense(struct nouveau_gpio *, int);
-
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/anx9805.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/anx9805.c
deleted file mode 100644
index 2c2731a6cf91..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/anx9805.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "port.h"
-
-struct anx9805_i2c_port {
-	struct nouveau_i2c_port base;
-	u32 addr;
-	u32 ctrl;
-};
-
-static int
-anx9805_train(struct nouveau_i2c_port *port, int link_nr, int link_bw, bool enh)
-{
-	struct anx9805_i2c_port *chan = (void *)port;
-	struct nouveau_i2c_port *mast = (void *)nv_object(chan)->parent;
-	u8 tmp, i;
-
-	DBG("ANX9805 train %d 0x%02x %d\n", link_nr, link_bw, enh);
-
-	nv_wri2cr(mast, chan->addr, 0xa0, link_bw);
-	nv_wri2cr(mast, chan->addr, 0xa1, link_nr | (enh ? 0x80 : 0x00));
-	nv_wri2cr(mast, chan->addr, 0xa2, 0x01);
-	nv_wri2cr(mast, chan->addr, 0xa8, 0x01);
-
-	i = 0;
-	while ((tmp = nv_rdi2cr(mast, chan->addr, 0xa8)) & 0x01) {
-		mdelay(5);
-		if (i++ == 100) {
-			nv_error(port, "link training timed out\n");
-			return -ETIMEDOUT;
-		}
-	}
-
-	if (tmp & 0x70) {
-		nv_error(port, "link training failed: 0x%02x\n", tmp);
-		return -EIO;
-	}
-
-	return 1;
-}
-
-static int
-anx9805_aux(struct nouveau_i2c_port *port, bool retry,
-	    u8 type, u32 addr, u8 *data, u8 size)
-{
-	struct anx9805_i2c_port *chan = (void *)port;
-	struct nouveau_i2c_port *mast = (void *)nv_object(chan)->parent;
-	int i, ret = -ETIMEDOUT;
-	u8 buf[16] = {};
-	u8 tmp;
-
-	DBG("%02x %05x %d\n", type, addr, size);
-
-	tmp = nv_rdi2cr(mast, chan->ctrl, 0x07) & ~0x04;
-	nv_wri2cr(mast, chan->ctrl, 0x07, tmp | 0x04);
-	nv_wri2cr(mast, chan->ctrl, 0x07, tmp);
-	nv_wri2cr(mast, chan->ctrl, 0xf7, 0x01);
-
-	nv_wri2cr(mast, chan->addr, 0xe4, 0x80);
-	if (!(type & 1)) {
-		memcpy(buf, data, size);
-		DBG("%16ph", buf);
-		for (i = 0; i < size; i++)
-			nv_wri2cr(mast, chan->addr, 0xf0 + i, buf[i]);
-	}
-	nv_wri2cr(mast, chan->addr, 0xe5, ((size - 1) << 4) | type);
-	nv_wri2cr(mast, chan->addr, 0xe6, (addr & 0x000ff) >>  0);
-	nv_wri2cr(mast, chan->addr, 0xe7, (addr & 0x0ff00) >>  8);
-	nv_wri2cr(mast, chan->addr, 0xe8, (addr & 0xf0000) >> 16);
-	nv_wri2cr(mast, chan->addr, 0xe9, 0x01);
-
-	i = 0;
-	while ((tmp = nv_rdi2cr(mast, chan->addr, 0xe9)) & 0x01) {
-		mdelay(5);
-		if (i++ == 32)
-			goto done;
-	}
-
-	if ((tmp = nv_rdi2cr(mast, chan->ctrl, 0xf7)) & 0x01) {
-		ret = -EIO;
-		goto done;
-	}
-
-	if (type & 1) {
-		for (i = 0; i < size; i++)
-			buf[i] = nv_rdi2cr(mast, chan->addr, 0xf0 + i);
-		DBG("%16ph", buf);
-		memcpy(data, buf, size);
-	}
-
-	ret = 0;
-done:
-	nv_wri2cr(mast, chan->ctrl, 0xf7, 0x01);
-	return ret;
-}
-
-static const struct nouveau_i2c_func
-anx9805_aux_func = {
-	.aux = anx9805_aux,
-	.lnk_ctl = anx9805_train,
-};
-
-static int
-anx9805_aux_chan_ctor(struct nouveau_object *parent,
-		      struct nouveau_object *engine,
-		      struct nouveau_oclass *oclass, void *data, u32 index,
-		      struct nouveau_object **pobject)
-{
-	struct nouveau_i2c_port *mast = (void *)parent;
-	struct anx9805_i2c_port *chan;
-	int ret;
-
-	ret = nouveau_i2c_port_create(parent, engine, oclass, index,
-				      &nouveau_i2c_aux_algo, &anx9805_aux_func,
-				      &chan);
-	*pobject = nv_object(chan);
-	if (ret)
-		return ret;
-
-	switch ((oclass->handle & 0xff00) >> 8) {
-	case 0x0d:
-		chan->addr = 0x38;
-		chan->ctrl = 0x39;
-		break;
-	case 0x0e:
-		chan->addr = 0x3c;
-		chan->ctrl = 0x3b;
-		break;
-	default:
-		BUG_ON(1);
-	}
-
-	if (mast->adapter.algo == &i2c_bit_algo) {
-		struct i2c_algo_bit_data *algo = mast->adapter.algo_data;
-		algo->udelay = max(algo->udelay, 40);
-	}
-	return 0;
-}
-
-static struct nouveau_ofuncs
-anx9805_aux_ofuncs = {
-	.ctor =  anx9805_aux_chan_ctor,
-	.dtor = _nouveau_i2c_port_dtor,
-	.init = _nouveau_i2c_port_init,
-	.fini = _nouveau_i2c_port_fini,
-};
-
-static int
-anx9805_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
-{
-	struct anx9805_i2c_port *port = adap->algo_data;
-	struct nouveau_i2c_port *mast = (void *)nv_object(port)->parent;
-	struct i2c_msg *msg = msgs;
-	int ret = -ETIMEDOUT;
-	int i, j, cnt = num;
-	u8 seg = 0x00, off = 0x00, tmp;
-
-	tmp = nv_rdi2cr(mast, port->ctrl, 0x07) & ~0x10;
-	nv_wri2cr(mast, port->ctrl, 0x07, tmp | 0x10);
-	nv_wri2cr(mast, port->ctrl, 0x07, tmp);
-	nv_wri2cr(mast, port->addr, 0x43, 0x05);
-	mdelay(5);
-
-	while (cnt--) {
-		if ( (msg->flags & I2C_M_RD) && msg->addr == 0x50) {
-			nv_wri2cr(mast, port->addr, 0x40, msg->addr << 1);
-			nv_wri2cr(mast, port->addr, 0x41, seg);
-			nv_wri2cr(mast, port->addr, 0x42, off);
-			nv_wri2cr(mast, port->addr, 0x44, msg->len);
-			nv_wri2cr(mast, port->addr, 0x45, 0x00);
-			nv_wri2cr(mast, port->addr, 0x43, 0x01);
-			for (i = 0; i < msg->len; i++) {
-				j = 0;
-				while (nv_rdi2cr(mast, port->addr, 0x46) & 0x10) {
-					mdelay(5);
-					if (j++ == 32)
-						goto done;
-				}
-				msg->buf[i] = nv_rdi2cr(mast, port->addr, 0x47);
-			}
-		} else
-		if (!(msg->flags & I2C_M_RD)) {
-			if (msg->addr == 0x50 && msg->len == 0x01) {
-				off = msg->buf[0];
-			} else
-			if (msg->addr == 0x30 && msg->len == 0x01) {
-				seg = msg->buf[0];
-			} else
-				goto done;
-		} else {
-			goto done;
-		}
-		msg++;
-	}
-
-	ret = num;
-done:
-	nv_wri2cr(mast, port->addr, 0x43, 0x00);
-	return ret;
-}
-
-static u32
-anx9805_func(struct i2c_adapter *adap)
-{
-	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
-}
-
-static const struct i2c_algorithm
-anx9805_i2c_algo = {
-	.master_xfer = anx9805_xfer,
-	.functionality = anx9805_func
-};
-
-static const struct nouveau_i2c_func
-anx9805_i2c_func = {
-};
-
-static int
-anx9805_ddc_port_ctor(struct nouveau_object *parent,
-		      struct nouveau_object *engine,
-		      struct nouveau_oclass *oclass, void *data, u32 index,
-		      struct nouveau_object **pobject)
-{
-	struct nouveau_i2c_port *mast = (void *)parent;
-	struct anx9805_i2c_port *port;
-	int ret;
-
-	ret = nouveau_i2c_port_create(parent, engine, oclass, index,
-				      &anx9805_i2c_algo, &anx9805_i2c_func,
-				      &port);
-	*pobject = nv_object(port);
-	if (ret)
-		return ret;
-
-	switch ((oclass->handle & 0xff00) >> 8) {
-	case 0x0d:
-		port->addr = 0x3d;
-		port->ctrl = 0x39;
-		break;
-	case 0x0e:
-		port->addr = 0x3f;
-		port->ctrl = 0x3b;
-		break;
-	default:
-		BUG_ON(1);
-	}
-
-	if (mast->adapter.algo == &i2c_bit_algo) {
-		struct i2c_algo_bit_data *algo = mast->adapter.algo_data;
-		algo->udelay = max(algo->udelay, 40);
-	}
-	return 0;
-}
-
-static struct nouveau_ofuncs
-anx9805_ddc_ofuncs = {
-	.ctor =  anx9805_ddc_port_ctor,
-	.dtor = _nouveau_i2c_port_dtor,
-	.init = _nouveau_i2c_port_init,
-	.fini = _nouveau_i2c_port_fini,
-};
-
-struct nouveau_oclass
-nouveau_anx9805_sclass[] = {
-	{ .handle = NV_I2C_TYPE_EXTDDC(0x0d), .ofuncs = &anx9805_ddc_ofuncs },
-	{ .handle = NV_I2C_TYPE_EXTAUX(0x0d), .ofuncs = &anx9805_aux_ofuncs },
-	{ .handle = NV_I2C_TYPE_EXTDDC(0x0e), .ofuncs = &anx9805_ddc_ofuncs },
-	{ .handle = NV_I2C_TYPE_EXTAUX(0x0e), .ofuncs = &anx9805_aux_ofuncs },
-	{}
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/aux.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/aux.c
deleted file mode 100644
index 02eb42be2e9e..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/aux.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright 2009 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-
-int
-nv_rdaux(struct nouveau_i2c_port *port, u32 addr, u8 *data, u8 size)
-{
-	struct nouveau_i2c *i2c = nouveau_i2c(port);
-	if (port->func->aux) {
-		int ret = i2c->acquire(port, 0);
-		if (ret == 0) {
-			ret = port->func->aux(port, true, 9, addr, data, size);
-			i2c->release(port);
-		}
-		return ret;
-	}
-	return -ENODEV;
-}
-
-int
-nv_wraux(struct nouveau_i2c_port *port, u32 addr, u8 *data, u8 size)
-{
-	struct nouveau_i2c *i2c = nouveau_i2c(port);
-	if (port->func->aux) {
-		int ret = i2c->acquire(port, 0);
-		if (ret == 0) {
-			ret = port->func->aux(port, true, 8, addr, data, size);
-			i2c->release(port);
-		}
-		return ret;
-	}
-	return -ENODEV;
-}
-
-static int
-aux_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
-{
-	struct nouveau_i2c_port *port = adap->algo_data;
-	struct nouveau_i2c *i2c = nouveau_i2c(port);
-	struct i2c_msg *msg = msgs;
-	int ret, mcnt = num;
-
-	if (!port->func->aux)
-		return -ENODEV;
-
-	ret = i2c->acquire(port, 0);
-	if (ret)
-		return ret;
-
-	while (mcnt--) {
-		u8 remaining = msg->len;
-		u8 *ptr = msg->buf;
-
-		while (remaining) {
-			u8 cnt = (remaining > 16) ? 16 : remaining;
-			u8 cmd;
-
-			if (msg->flags & I2C_M_RD)
-				cmd = 1;
-			else
-				cmd = 0;
-
-			if (mcnt || remaining > 16)
-				cmd |= 4; /* MOT */
-
-			ret = port->func->aux(port, true, cmd, msg->addr, ptr, cnt);
-			if (ret < 0) {
-				i2c->release(port);
-				return ret;
-			}
-
-			ptr += cnt;
-			remaining -= cnt;
-		}
-
-		msg++;
-	}
-
-	i2c->release(port);
-	return num;
-}
-
-static u32
-aux_func(struct i2c_adapter *adap)
-{
-	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
-}
-
-const struct i2c_algorithm nouveau_i2c_aux_algo = {
-	.master_xfer = aux_xfer,
-	.functionality = aux_func
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c
deleted file mode 100644
index 0dc605db7ec8..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c
+++ /dev/null
@@ -1,634 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/option.h>
-#include <core/object.h>
-#include <core/event.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/i2c.h>
-#include <subdev/vga.h>
-
-#include "priv.h"
-#include "pad.h"
-
-/******************************************************************************
- * interface to linux i2c bit-banging algorithm
- *****************************************************************************/
-
-#ifdef CONFIG_NOUVEAU_I2C_INTERNAL_DEFAULT
-#define CSTMSEL true
-#else
-#define CSTMSEL false
-#endif
-
-static int
-nouveau_i2c_pre_xfer(struct i2c_adapter *adap)
-{
-	struct i2c_algo_bit_data *bit = adap->algo_data;
-	struct nouveau_i2c_port *port = bit->data;
-	return nouveau_i2c(port)->acquire(port, bit->timeout);
-}
-
-static void
-nouveau_i2c_post_xfer(struct i2c_adapter *adap)
-{
-	struct i2c_algo_bit_data *bit = adap->algo_data;
-	struct nouveau_i2c_port *port = bit->data;
-	return nouveau_i2c(port)->release(port);
-}
-
-static void
-nouveau_i2c_setscl(void *data, int state)
-{
-	struct nouveau_i2c_port *port = data;
-	port->func->drive_scl(port, state);
-}
-
-static void
-nouveau_i2c_setsda(void *data, int state)
-{
-	struct nouveau_i2c_port *port = data;
-	port->func->drive_sda(port, state);
-}
-
-static int
-nouveau_i2c_getscl(void *data)
-{
-	struct nouveau_i2c_port *port = data;
-	return port->func->sense_scl(port);
-}
-
-static int
-nouveau_i2c_getsda(void *data)
-{
-	struct nouveau_i2c_port *port = data;
-	return port->func->sense_sda(port);
-}
-
-/******************************************************************************
- * base i2c "port" class implementation
- *****************************************************************************/
-
-int
-_nouveau_i2c_port_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nouveau_i2c_port *port = (void *)object;
-	struct nvkm_i2c_pad *pad = nvkm_i2c_pad(port);
-	nv_ofuncs(pad)->fini(nv_object(pad), suspend);
-	return nouveau_object_fini(&port->base, suspend);
-}
-
-void
-_nouveau_i2c_port_dtor(struct nouveau_object *object)
-{
-	struct nouveau_i2c_port *port = (void *)object;
-	i2c_del_adapter(&port->adapter);
-	nouveau_object_destroy(&port->base);
-}
-
-int
-nouveau_i2c_port_create_(struct nouveau_object *parent,
-			 struct nouveau_object *engine,
-			 struct nouveau_oclass *oclass, u8 index,
-			 const struct i2c_algorithm *algo,
-			 const struct nouveau_i2c_func *func,
-			 int size, void **pobject)
-{
-	struct nouveau_device *device = nv_device(engine);
-	struct nouveau_i2c *i2c = (void *)engine;
-	struct nouveau_i2c_port *port;
-	int ret;
-
-	ret = nouveau_object_create_(parent, engine, oclass, 0, size, pobject);
-	port = *pobject;
-	if (ret)
-		return ret;
-
-	snprintf(port->adapter.name, sizeof(port->adapter.name),
-		 "nouveau-%s-%d", device->name, index);
-	port->adapter.owner = THIS_MODULE;
-	port->adapter.dev.parent = nv_device_base(device);
-	port->index = index;
-	port->aux = -1;
-	port->func = func;
-	mutex_init(&port->mutex);
-
-	if ( algo == &nouveau_i2c_bit_algo &&
-	    !nouveau_boolopt(device->cfgopt, "NvI2C", CSTMSEL)) {
-		struct i2c_algo_bit_data *bit;
-
-		bit = kzalloc(sizeof(*bit), GFP_KERNEL);
-		if (!bit)
-			return -ENOMEM;
-
-		bit->udelay = 10;
-		bit->timeout = usecs_to_jiffies(2200);
-		bit->data = port;
-		bit->pre_xfer = nouveau_i2c_pre_xfer;
-		bit->post_xfer = nouveau_i2c_post_xfer;
-		bit->setsda = nouveau_i2c_setsda;
-		bit->setscl = nouveau_i2c_setscl;
-		bit->getsda = nouveau_i2c_getsda;
-		bit->getscl = nouveau_i2c_getscl;
-
-		port->adapter.algo_data = bit;
-		ret = i2c_bit_add_bus(&port->adapter);
-	} else {
-		port->adapter.algo_data = port;
-		port->adapter.algo = algo;
-		ret = i2c_add_adapter(&port->adapter);
-	}
-
-	if (ret == 0)
-		list_add_tail(&port->head, &i2c->ports);
-	return ret;
-}
-
-/******************************************************************************
- * base i2c subdev class implementation
- *****************************************************************************/
-
-static struct nouveau_i2c_port *
-nouveau_i2c_find(struct nouveau_i2c *i2c, u8 index)
-{
-	struct nouveau_bios *bios = nouveau_bios(i2c);
-	struct nouveau_i2c_port *port;
-
-	if (index == NV_I2C_DEFAULT(0) ||
-	    index == NV_I2C_DEFAULT(1)) {
-		u8  ver, hdr, cnt, len;
-		u16 i2c = dcb_i2c_table(bios, &ver, &hdr, &cnt, &len);
-		if (i2c && ver >= 0x30) {
-			u8 auxidx = nv_ro08(bios, i2c + 4);
-			if (index == NV_I2C_DEFAULT(0))
-				index = (auxidx & 0x0f) >> 0;
-			else
-				index = (auxidx & 0xf0) >> 4;
-		} else {
-			index = 2;
-		}
-	}
-
-	list_for_each_entry(port, &i2c->ports, head) {
-		if (port->index == index)
-			return port;
-	}
-
-	return NULL;
-}
-
-static struct nouveau_i2c_port *
-nouveau_i2c_find_type(struct nouveau_i2c *i2c, u16 type)
-{
-	struct nouveau_i2c_port *port;
-
-	list_for_each_entry(port, &i2c->ports, head) {
-		if (nv_hclass(port) == type)
-			return port;
-	}
-
-	return NULL;
-}
-
-static void
-nouveau_i2c_release_pad(struct nouveau_i2c_port *port)
-{
-	struct nvkm_i2c_pad *pad = nvkm_i2c_pad(port);
-	struct nouveau_i2c *i2c = nouveau_i2c(port);
-
-	if (atomic_dec_and_test(&nv_object(pad)->usecount)) {
-		nv_ofuncs(pad)->fini(nv_object(pad), false);
-		wake_up_all(&i2c->wait);
-	}
-}
-
-static int
-nouveau_i2c_try_acquire_pad(struct nouveau_i2c_port *port)
-{
-	struct nvkm_i2c_pad *pad = nvkm_i2c_pad(port);
-
-	if (atomic_add_return(1, &nv_object(pad)->usecount) != 1) {
-		struct nouveau_object *owner = (void *)pad->port;
-		do {
-			if (owner == (void *)port)
-				return 0;
-			owner = owner->parent;
-		} while(owner);
-		nouveau_i2c_release_pad(port);
-		return -EBUSY;
-	}
-
-	pad->next = port;
-	nv_ofuncs(pad)->init(nv_object(pad));
-	return 0;
-}
-
-static int
-nouveau_i2c_acquire_pad(struct nouveau_i2c_port *port, unsigned long timeout)
-{
-	struct nouveau_i2c *i2c = nouveau_i2c(port);
-
-	if (timeout) {
-		if (wait_event_timeout(i2c->wait,
-				       nouveau_i2c_try_acquire_pad(port) == 0,
-				       timeout) == 0)
-			return -EBUSY;
-	} else {
-		wait_event(i2c->wait, nouveau_i2c_try_acquire_pad(port) == 0);
-	}
-
-	return 0;
-}
-
-static void
-nouveau_i2c_release(struct nouveau_i2c_port *port)
-__releases(pad->mutex)
-{
-	nouveau_i2c(port)->release_pad(port);
-	mutex_unlock(&port->mutex);
-}
-
-static int
-nouveau_i2c_acquire(struct nouveau_i2c_port *port, unsigned long timeout)
-__acquires(pad->mutex)
-{
-	int ret;
-	mutex_lock(&port->mutex);
-	if ((ret = nouveau_i2c(port)->acquire_pad(port, timeout)))
-		mutex_unlock(&port->mutex);
-	return ret;
-}
-
-static int
-nouveau_i2c_identify(struct nouveau_i2c *i2c, int index, const char *what,
-		     struct nouveau_i2c_board_info *info,
-		     bool (*match)(struct nouveau_i2c_port *,
-				   struct i2c_board_info *, void *), void *data)
-{
-	struct nouveau_i2c_port *port = nouveau_i2c_find(i2c, index);
-	int i;
-
-	if (!port) {
-		nv_debug(i2c, "no bus when probing %s on %d\n", what, index);
-		return -ENODEV;
-	}
-
-	nv_debug(i2c, "probing %ss on bus: %d\n", what, port->index);
-	for (i = 0; info[i].dev.addr; i++) {
-		u8 orig_udelay = 0;
-
-		if ((port->adapter.algo == &i2c_bit_algo) &&
-		    (info[i].udelay != 0)) {
-			struct i2c_algo_bit_data *algo = port->adapter.algo_data;
-			nv_debug(i2c, "using custom udelay %d instead of %d\n",
-			         info[i].udelay, algo->udelay);
-			orig_udelay = algo->udelay;
-			algo->udelay = info[i].udelay;
-		}
-
-		if (nv_probe_i2c(port, info[i].dev.addr) &&
-		    (!match || match(port, &info[i].dev, data))) {
-			nv_info(i2c, "detected %s: %s\n", what,
-				info[i].dev.type);
-			return i;
-		}
-
-		if (orig_udelay) {
-			struct i2c_algo_bit_data *algo = port->adapter.algo_data;
-			algo->udelay = orig_udelay;
-		}
-	}
-
-	nv_debug(i2c, "no devices found.\n");
-	return -ENODEV;
-}
-
-static void
-nouveau_i2c_intr_fini(struct nvkm_event *event, int type, int index)
-{
-	struct nouveau_i2c *i2c = container_of(event, typeof(*i2c), event);
-	struct nouveau_i2c_port *port = i2c->find(i2c, index);
-	const struct nouveau_i2c_impl *impl = (void *)nv_object(i2c)->oclass;
-	if (port && port->aux >= 0)
-		impl->aux_mask(i2c, type, 1 << port->aux, 0);
-}
-
-static void
-nouveau_i2c_intr_init(struct nvkm_event *event, int type, int index)
-{
-	struct nouveau_i2c *i2c = container_of(event, typeof(*i2c), event);
-	struct nouveau_i2c_port *port = i2c->find(i2c, index);
-	const struct nouveau_i2c_impl *impl = (void *)nv_object(i2c)->oclass;
-	if (port && port->aux >= 0)
-		impl->aux_mask(i2c, type, 1 << port->aux, 1 << port->aux);
-}
-
-static int
-nouveau_i2c_intr_ctor(struct nouveau_object *object, void *data, u32 size,
-		      struct nvkm_notify *notify)
-{
-	struct nvkm_i2c_ntfy_req *req = data;
-	if (!WARN_ON(size != sizeof(*req))) {
-		notify->size  = sizeof(struct nvkm_i2c_ntfy_rep);
-		notify->types = req->mask;
-		notify->index = req->port;
-		return 0;
-	}
-	return -EINVAL;
-}
-
-static void
-nouveau_i2c_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_i2c_impl *impl = (void *)nv_oclass(subdev);
-	struct nouveau_i2c *i2c = nouveau_i2c(subdev);
-	struct nouveau_i2c_port *port;
-	u32 hi, lo, rq, tx, e;
-
-	if (impl->aux_stat) {
-		impl->aux_stat(i2c, &hi, &lo, &rq, &tx);
-		if (hi || lo || rq || tx) {
-			list_for_each_entry(port, &i2c->ports, head) {
-				if (e = 0, port->aux < 0)
-					continue;
-
-				if (hi & (1 << port->aux)) e |= NVKM_I2C_PLUG;
-				if (lo & (1 << port->aux)) e |= NVKM_I2C_UNPLUG;
-				if (rq & (1 << port->aux)) e |= NVKM_I2C_IRQ;
-				if (tx & (1 << port->aux)) e |= NVKM_I2C_DONE;
-				if (e) {
-					struct nvkm_i2c_ntfy_rep rep = {
-						.mask = e,
-					};
-					nvkm_event_send(&i2c->event, rep.mask,
-							port->index, &rep,
-							sizeof(rep));
-				}
-			}
-		}
-	}
-}
-
-static const struct nvkm_event_func
-nouveau_i2c_intr_func = {
-	.ctor = nouveau_i2c_intr_ctor,
-	.init = nouveau_i2c_intr_init,
-	.fini = nouveau_i2c_intr_fini,
-};
-
-int
-_nouveau_i2c_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nouveau_i2c_impl *impl = (void *)nv_oclass(object);
-	struct nouveau_i2c *i2c = (void *)object;
-	struct nouveau_i2c_port *port;
-	u32 mask;
-	int ret;
-
-	list_for_each_entry(port, &i2c->ports, head) {
-		ret = nv_ofuncs(port)->fini(nv_object(port), suspend);
-		if (ret && suspend)
-			goto fail;
-	}
-
-	if ((mask = (1 << impl->aux) - 1), impl->aux_stat) {
-		impl->aux_mask(i2c, NVKM_I2C_ANY, mask, 0);
-		impl->aux_stat(i2c, &mask, &mask, &mask, &mask);
-	}
-
-	return nouveau_subdev_fini(&i2c->base, suspend);
-fail:
-	list_for_each_entry_continue_reverse(port, &i2c->ports, head) {
-		nv_ofuncs(port)->init(nv_object(port));
-	}
-
-	return ret;
-}
-
-int
-_nouveau_i2c_init(struct nouveau_object *object)
-{
-	struct nouveau_i2c *i2c = (void *)object;
-	struct nouveau_i2c_port *port;
-	int ret;
-
-	ret = nouveau_subdev_init(&i2c->base);
-	if (ret == 0) {
-		list_for_each_entry(port, &i2c->ports, head) {
-			ret = nv_ofuncs(port)->init(nv_object(port));
-			if (ret)
-				goto fail;
-		}
-	}
-
-	return ret;
-fail:
-	list_for_each_entry_continue_reverse(port, &i2c->ports, head) {
-		nv_ofuncs(port)->fini(nv_object(port), false);
-	}
-
-	return ret;
-}
-
-void
-_nouveau_i2c_dtor(struct nouveau_object *object)
-{
-	struct nouveau_i2c *i2c = (void *)object;
-	struct nouveau_i2c_port *port, *temp;
-
-	nvkm_event_fini(&i2c->event);
-
-	list_for_each_entry_safe(port, temp, &i2c->ports, head) {
-		nouveau_object_ref(NULL, (struct nouveau_object **)&port);
-	}
-
-	nouveau_subdev_destroy(&i2c->base);
-}
-
-static struct nouveau_oclass *
-nouveau_i2c_extdev_sclass[] = {
-	nouveau_anx9805_sclass,
-};
-
-static void
-nouveau_i2c_create_port(struct nouveau_i2c *i2c, int index, u8 type,
-			struct dcb_i2c_entry *info)
-{
-	const struct nouveau_i2c_impl *impl = (void *)nv_oclass(i2c);
-	struct nouveau_oclass *oclass;
-	struct nouveau_object *parent;
-	struct nouveau_object *object;
-	int ret, pad;
-
-	if (info->share != DCB_I2C_UNUSED) {
-		pad    = info->share;
-		oclass = impl->pad_s;
-	} else {
-		if (type != DCB_I2C_NVIO_AUX)
-			pad = 0x100 + info->drive;
-		else
-			pad = 0x100 + info->auxch;
-		oclass = impl->pad_x;
-	}
-
-	ret = nouveau_object_ctor(NULL, nv_object(i2c), oclass, NULL, pad,
-				 &parent);
-	if (ret < 0)
-		return;
-
-	oclass = impl->sclass;
-	do {
-		ret = -EINVAL;
-		if (oclass->handle == type) {
-			ret = nouveau_object_ctor(parent, nv_object(i2c),
-						  oclass, info, index,
-						 &object);
-		}
-	} while (ret && (++oclass)->handle);
-
-	nouveau_object_ref(NULL, &parent);
-}
-
-int
-nouveau_i2c_create_(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass,
-		    int length, void **pobject)
-{
-	struct nouveau_bios *bios = nouveau_bios(parent);
-	struct nouveau_i2c *i2c;
-	struct nouveau_object *object;
-	struct dcb_i2c_entry info;
-	int ret, i, j, index = -1;
-	struct dcb_output outp;
-	u8  ver, hdr;
-	u32 data;
-
-	ret = nouveau_subdev_create(parent, engine, oclass, 0,
-				    "I2C", "i2c", &i2c);
-	*pobject = nv_object(i2c);
-	if (ret)
-		return ret;
-
-	nv_subdev(i2c)->intr = nouveau_i2c_intr;
-	i2c->find = nouveau_i2c_find;
-	i2c->find_type = nouveau_i2c_find_type;
-	i2c->acquire_pad = nouveau_i2c_acquire_pad;
-	i2c->release_pad = nouveau_i2c_release_pad;
-	i2c->acquire = nouveau_i2c_acquire;
-	i2c->release = nouveau_i2c_release;
-	i2c->identify = nouveau_i2c_identify;
-	init_waitqueue_head(&i2c->wait);
-	INIT_LIST_HEAD(&i2c->ports);
-
-	while (!dcb_i2c_parse(bios, ++index, &info)) {
-		switch (info.type) {
-		case DCB_I2C_NV04_BIT:
-		case DCB_I2C_NV4E_BIT:
-		case DCB_I2C_NVIO_BIT:
-			nouveau_i2c_create_port(i2c, NV_I2C_PORT(index),
-						info.type, &info);
-			break;
-		case DCB_I2C_NVIO_AUX:
-			nouveau_i2c_create_port(i2c, NV_I2C_AUX(index),
-						info.type, &info);
-			break;
-		case DCB_I2C_PMGR:
-			if (info.drive != DCB_I2C_UNUSED) {
-				nouveau_i2c_create_port(i2c, NV_I2C_PORT(index),
-							DCB_I2C_NVIO_BIT,
-							&info);
-			}
-			if (info.auxch != DCB_I2C_UNUSED) {
-				nouveau_i2c_create_port(i2c, NV_I2C_AUX(index),
-							DCB_I2C_NVIO_AUX,
-							&info);
-			}
-			break;
-		case DCB_I2C_UNUSED:
-		default:
-			continue;
-		}
-	}
-
-	/* in addition to the busses specified in the i2c table, there
-	 * may be ddc/aux channels hiding behind external tmds/dp/etc
-	 * transmitters.
-	 */
-	index = NV_I2C_EXT(0);
-	i = -1;
-	while ((data = dcb_outp_parse(bios, ++i, &ver, &hdr, &outp))) {
-		if (!outp.location || !outp.extdev)
-			continue;
-
-		switch (outp.type) {
-		case DCB_OUTPUT_TMDS:
-			info.type = NV_I2C_TYPE_EXTDDC(outp.extdev);
-			break;
-		case DCB_OUTPUT_DP:
-			info.type = NV_I2C_TYPE_EXTAUX(outp.extdev);
-			break;
-		default:
-			continue;
-		}
-
-		ret = -ENODEV;
-		j = -1;
-		while (ret && ++j < ARRAY_SIZE(nouveau_i2c_extdev_sclass)) {
-			parent = nv_object(i2c->find(i2c, outp.i2c_index));
-			oclass = nouveau_i2c_extdev_sclass[j];
-			do {
-				if (oclass->handle != info.type)
-					continue;
-				ret = nouveau_object_ctor(parent, *pobject,
-							  oclass, NULL,
-							  index++, &object);
-			} while (ret && (++oclass)->handle);
-		}
-	}
-
-	ret = nvkm_event_init(&nouveau_i2c_intr_func, 4, index, &i2c->event);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-int
-_nouveau_i2c_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 size,
-		  struct nouveau_object **pobject)
-{
-	struct nouveau_i2c *i2c;
-	int ret;
-
-	ret = nouveau_i2c_create(parent, engine, oclass, &i2c);
-	*pobject = nv_object(i2c);
-	if (ret)
-		return ret;
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/bit.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/bit.c
deleted file mode 100644
index 813ffc96e864..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/bit.c
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-
-#ifdef CONFIG_NOUVEAU_I2C_INTERNAL
-#define T_TIMEOUT  2200000
-#define T_RISEFALL 1000
-#define T_HOLD     5000
-
-static inline void
-i2c_drive_scl(struct nouveau_i2c_port *port, int state)
-{
-	port->func->drive_scl(port, state);
-}
-
-static inline void
-i2c_drive_sda(struct nouveau_i2c_port *port, int state)
-{
-	port->func->drive_sda(port, state);
-}
-
-static inline int
-i2c_sense_scl(struct nouveau_i2c_port *port)
-{
-	return port->func->sense_scl(port);
-}
-
-static inline int
-i2c_sense_sda(struct nouveau_i2c_port *port)
-{
-	return port->func->sense_sda(port);
-}
-
-static void
-i2c_delay(struct nouveau_i2c_port *port, u32 nsec)
-{
-	udelay((nsec + 500) / 1000);
-}
-
-static bool
-i2c_raise_scl(struct nouveau_i2c_port *port)
-{
-	u32 timeout = T_TIMEOUT / T_RISEFALL;
-
-	i2c_drive_scl(port, 1);
-	do {
-		i2c_delay(port, T_RISEFALL);
-	} while (!i2c_sense_scl(port) && --timeout);
-
-	return timeout != 0;
-}
-
-static int
-i2c_start(struct nouveau_i2c_port *port)
-{
-	int ret = 0;
-
-	if (!i2c_sense_scl(port) ||
-	    !i2c_sense_sda(port)) {
-		i2c_drive_scl(port, 0);
-		i2c_drive_sda(port, 1);
-		if (!i2c_raise_scl(port))
-			ret = -EBUSY;
-	}
-
-	i2c_drive_sda(port, 0);
-	i2c_delay(port, T_HOLD);
-	i2c_drive_scl(port, 0);
-	i2c_delay(port, T_HOLD);
-	return ret;
-}
-
-static void
-i2c_stop(struct nouveau_i2c_port *port)
-{
-	i2c_drive_scl(port, 0);
-	i2c_drive_sda(port, 0);
-	i2c_delay(port, T_RISEFALL);
-
-	i2c_drive_scl(port, 1);
-	i2c_delay(port, T_HOLD);
-	i2c_drive_sda(port, 1);
-	i2c_delay(port, T_HOLD);
-}
-
-static int
-i2c_bitw(struct nouveau_i2c_port *port, int sda)
-{
-	i2c_drive_sda(port, sda);
-	i2c_delay(port, T_RISEFALL);
-
-	if (!i2c_raise_scl(port))
-		return -ETIMEDOUT;
-	i2c_delay(port, T_HOLD);
-
-	i2c_drive_scl(port, 0);
-	i2c_delay(port, T_HOLD);
-	return 0;
-}
-
-static int
-i2c_bitr(struct nouveau_i2c_port *port)
-{
-	int sda;
-
-	i2c_drive_sda(port, 1);
-	i2c_delay(port, T_RISEFALL);
-
-	if (!i2c_raise_scl(port))
-		return -ETIMEDOUT;
-	i2c_delay(port, T_HOLD);
-
-	sda = i2c_sense_sda(port);
-
-	i2c_drive_scl(port, 0);
-	i2c_delay(port, T_HOLD);
-	return sda;
-}
-
-static int
-i2c_get_byte(struct nouveau_i2c_port *port, u8 *byte, bool last)
-{
-	int i, bit;
-
-	*byte = 0;
-	for (i = 7; i >= 0; i--) {
-		bit = i2c_bitr(port);
-		if (bit < 0)
-			return bit;
-		*byte |= bit << i;
-	}
-
-	return i2c_bitw(port, last ? 1 : 0);
-}
-
-static int
-i2c_put_byte(struct nouveau_i2c_port *port, u8 byte)
-{
-	int i, ret;
-	for (i = 7; i >= 0; i--) {
-		ret = i2c_bitw(port, !!(byte & (1 << i)));
-		if (ret < 0)
-			return ret;
-	}
-
-	ret = i2c_bitr(port);
-	if (ret == 1) /* nack */
-		ret = -EIO;
-	return ret;
-}
-
-static int
-i2c_addr(struct nouveau_i2c_port *port, struct i2c_msg *msg)
-{
-	u32 addr = msg->addr << 1;
-	if (msg->flags & I2C_M_RD)
-		addr |= 1;
-	return i2c_put_byte(port, addr);
-}
-
-static int
-i2c_bit_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
-{
-	struct nouveau_i2c_port *port = adap->algo_data;
-	struct i2c_msg *msg = msgs;
-	int ret = 0, mcnt = num;
-
-	ret = nouveau_i2c(port)->acquire(port, nsecs_to_jiffies(T_TIMEOUT));
-	if (ret)
-		return ret;
-
-	while (!ret && mcnt--) {
-		u8 remaining = msg->len;
-		u8 *ptr = msg->buf;
-
-		ret = i2c_start(port);
-		if (ret == 0)
-			ret = i2c_addr(port, msg);
-
-		if (msg->flags & I2C_M_RD) {
-			while (!ret && remaining--)
-				ret = i2c_get_byte(port, ptr++, !remaining);
-		} else {
-			while (!ret && remaining--)
-				ret = i2c_put_byte(port, *ptr++);
-		}
-
-		msg++;
-	}
-
-	i2c_stop(port);
-	nouveau_i2c(port)->release(port);
-	return (ret < 0) ? ret : num;
-}
-#else
-static int
-i2c_bit_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
-{
-	return -ENODEV;
-}
-#endif
-
-static u32
-i2c_bit_func(struct i2c_adapter *adap)
-{
-	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
-}
-
-const struct i2c_algorithm nouveau_i2c_bit_algo = {
-	.master_xfer = i2c_bit_xfer,
-	.functionality = i2c_bit_func
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c
deleted file mode 100644
index fa891c39866b..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv50.h"
-
-struct nouveau_oclass *
-gf117_i2c_oclass = &(struct nouveau_i2c_impl) {
-	.base.handle = NV_SUBDEV(I2C, 0xd7),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_i2c_ctor,
-		.dtor = _nouveau_i2c_dtor,
-		.init = _nouveau_i2c_init,
-		.fini = _nouveau_i2c_fini,
-	},
-	.sclass = nvd0_i2c_sclass,
-	.pad_x = &nv04_i2c_pad_oclass,
-	.pad_s = &nv04_i2c_pad_oclass,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/gm204.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/gm204.c
deleted file mode 100644
index 06a2b87ccbf1..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/gm204.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv50.h"
-
-#define AUX_DBG(fmt, args...) nv_debug(aux, "AUXCH(%d): " fmt, ch, ##args)
-#define AUX_ERR(fmt, args...) nv_error(aux, "AUXCH(%d): " fmt, ch, ##args)
-
-static void
-auxch_fini(struct nouveau_i2c *aux, int ch)
-{
-	nv_mask(aux, 0x00d954 + (ch * 0x50), 0x00310000, 0x00000000);
-}
-
-static int
-auxch_init(struct nouveau_i2c *aux, int ch)
-{
-	const u32 unksel = 1; /* nfi which to use, or if it matters.. */
-	const u32 ureq = unksel ? 0x00100000 : 0x00200000;
-	const u32 urep = unksel ? 0x01000000 : 0x02000000;
-	u32 ctrl, timeout;
-
-	/* wait up to 1ms for any previous transaction to be done... */
-	timeout = 1000;
-	do {
-		ctrl = nv_rd32(aux, 0x00d954 + (ch * 0x50));
-		udelay(1);
-		if (!timeout--) {
-			AUX_ERR("begin idle timeout 0x%08x\n", ctrl);
-			return -EBUSY;
-		}
-	} while (ctrl & 0x03010000);
-
-	/* set some magic, and wait up to 1ms for it to appear */
-	nv_mask(aux, 0x00d954 + (ch * 0x50), 0x00300000, ureq);
-	timeout = 1000;
-	do {
-		ctrl = nv_rd32(aux, 0x00d954 + (ch * 0x50));
-		udelay(1);
-		if (!timeout--) {
-			AUX_ERR("magic wait 0x%08x\n", ctrl);
-			auxch_fini(aux, ch);
-			return -EBUSY;
-		}
-	} while ((ctrl & 0x03000000) != urep);
-
-	return 0;
-}
-
-int
-gm204_aux(struct nouveau_i2c_port *base, bool retry,
-	 u8 type, u32 addr, u8 *data, u8 size)
-{
-	struct nouveau_i2c *aux = nouveau_i2c(base);
-	struct nv50_i2c_port *port = (void *)base;
-	u32 ctrl, stat, timeout, retries;
-	u32 xbuf[4] = {};
-	int ch = port->addr;
-	int ret, i;
-
-	AUX_DBG("%d: 0x%08x %d\n", type, addr, size);
-
-	ret = auxch_init(aux, ch);
-	if (ret)
-		goto out;
-
-	stat = nv_rd32(aux, 0x00d958 + (ch * 0x50));
-	if (!(stat & 0x10000000)) {
-		AUX_DBG("sink not detected\n");
-		ret = -ENXIO;
-		goto out;
-	}
-
-	if (!(type & 1)) {
-		memcpy(xbuf, data, size);
-		for (i = 0; i < 16; i += 4) {
-			AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
-			nv_wr32(aux, 0x00d930 + (ch * 0x50) + i, xbuf[i / 4]);
-		}
-	}
-
-	ctrl  = nv_rd32(aux, 0x00d954 + (ch * 0x50));
-	ctrl &= ~0x0001f0ff;
-	ctrl |= type << 12;
-	ctrl |= size - 1;
-	nv_wr32(aux, 0x00d950 + (ch * 0x50), addr);
-
-	/* (maybe) retry transaction a number of times on failure... */
-	for (retries = 0; !ret && retries < 32; retries++) {
-		/* reset, and delay a while if this is a retry */
-		nv_wr32(aux, 0x00d954 + (ch * 0x50), 0x80000000 | ctrl);
-		nv_wr32(aux, 0x00d954 + (ch * 0x50), 0x00000000 | ctrl);
-		if (retries)
-			udelay(400);
-
-		/* transaction request, wait up to 1ms for it to complete */
-		nv_wr32(aux, 0x00d954 + (ch * 0x50), 0x00010000 | ctrl);
-
-		timeout = 1000;
-		do {
-			ctrl = nv_rd32(aux, 0x00d954 + (ch * 0x50));
-			udelay(1);
-			if (!timeout--) {
-				AUX_ERR("tx req timeout 0x%08x\n", ctrl);
-				ret = -EIO;
-				goto out;
-			}
-		} while (ctrl & 0x00010000);
-		ret = 1;
-
-		/* read status, and check if transaction completed ok */
-		stat = nv_mask(aux, 0x00d958 + (ch * 0x50), 0, 0);
-		if ((stat & 0x000f0000) == 0x00080000 ||
-		    (stat & 0x000f0000) == 0x00020000)
-			ret = retry ? 0 : 1;
-		if ((stat & 0x00000100))
-			ret = -ETIMEDOUT;
-		if ((stat & 0x00000e00))
-			ret = -EIO;
-
-		AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
-	}
-
-	if (type & 1) {
-		for (i = 0; i < 16; i += 4) {
-			xbuf[i / 4] = nv_rd32(aux, 0x00d940 + (ch * 0x50) + i);
-			AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
-		}
-		memcpy(data, xbuf, size);
-	}
-
-out:
-	auxch_fini(aux, ch);
-	return ret < 0 ? ret : (stat & 0x000f0000) >> 16;
-}
-
-static const struct nouveau_i2c_func
-gm204_aux_func = {
-	.aux       = gm204_aux,
-};
-
-int
-gm204_aux_port_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 index,
-		    struct nouveau_object **pobject)
-{
-	struct dcb_i2c_entry *info = data;
-	struct nv50_i2c_port *port;
-	int ret;
-
-	ret = nouveau_i2c_port_create(parent, engine, oclass, index,
-				      &nouveau_i2c_aux_algo, &gm204_aux_func,
-				      &port);
-	*pobject = nv_object(port);
-	if (ret)
-		return ret;
-
-	port->base.aux = info->auxch;
-	port->addr = info->auxch;
-	return 0;
-}
-
-struct nouveau_oclass
-gm204_i2c_sclass[] = {
-	{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT),
-	  .ofuncs = &(struct nouveau_ofuncs) {
-		  .ctor = nvd0_i2c_port_ctor,
-		  .dtor = _nouveau_i2c_port_dtor,
-		  .init = nv50_i2c_port_init,
-		  .fini = _nouveau_i2c_port_fini,
-	  },
-	},
-	{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX),
-	  .ofuncs = &(struct nouveau_ofuncs) {
-		  .ctor = gm204_aux_port_ctor,
-		  .dtor = _nouveau_i2c_port_dtor,
-		  .init = _nouveau_i2c_port_init,
-		  .fini = _nouveau_i2c_port_fini,
-	  },
-	},
-	{}
-};
-
-struct nouveau_oclass *
-gm204_i2c_oclass = &(struct nouveau_i2c_impl) {
-	.base.handle = NV_SUBDEV(I2C, 0x24),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_i2c_ctor,
-		.dtor = _nouveau_i2c_dtor,
-		.init = _nouveau_i2c_init,
-		.fini = _nouveau_i2c_fini,
-	},
-	.sclass = gm204_i2c_sclass,
-	.pad_x = &nv04_i2c_pad_oclass,
-	.pad_s = &gm204_i2c_pad_oclass,
-	.aux = 8,
-	.aux_stat = nve0_aux_stat,
-	.aux_mask = nve0_aux_mask,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/nv04.c
deleted file mode 100644
index b1725bdea967..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv04.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/vga.h>
-
-#include "priv.h"
-
-struct nv04_i2c_priv {
-	struct nouveau_i2c base;
-};
-
-struct nv04_i2c_port {
-	struct nouveau_i2c_port base;
-	u8 drive;
-	u8 sense;
-};
-
-static void
-nv04_i2c_drive_scl(struct nouveau_i2c_port *base, int state)
-{
-	struct nv04_i2c_priv *priv = (void *)nv_object(base)->engine;
-	struct nv04_i2c_port *port = (void *)base;
-	u8 val = nv_rdvgac(priv, 0, port->drive);
-	if (state) val |= 0x20;
-	else	   val &= 0xdf;
-	nv_wrvgac(priv, 0, port->drive, val | 0x01);
-}
-
-static void
-nv04_i2c_drive_sda(struct nouveau_i2c_port *base, int state)
-{
-	struct nv04_i2c_priv *priv = (void *)nv_object(base)->engine;
-	struct nv04_i2c_port *port = (void *)base;
-	u8 val = nv_rdvgac(priv, 0, port->drive);
-	if (state) val |= 0x10;
-	else	   val &= 0xef;
-	nv_wrvgac(priv, 0, port->drive, val | 0x01);
-}
-
-static int
-nv04_i2c_sense_scl(struct nouveau_i2c_port *base)
-{
-	struct nv04_i2c_priv *priv = (void *)nv_object(base)->engine;
-	struct nv04_i2c_port *port = (void *)base;
-	return !!(nv_rdvgac(priv, 0, port->sense) & 0x04);
-}
-
-static int
-nv04_i2c_sense_sda(struct nouveau_i2c_port *base)
-{
-	struct nv04_i2c_priv *priv = (void *)nv_object(base)->engine;
-	struct nv04_i2c_port *port = (void *)base;
-	return !!(nv_rdvgac(priv, 0, port->sense) & 0x08);
-}
-
-static const struct nouveau_i2c_func
-nv04_i2c_func = {
-	.drive_scl = nv04_i2c_drive_scl,
-	.drive_sda = nv04_i2c_drive_sda,
-	.sense_scl = nv04_i2c_sense_scl,
-	.sense_sda = nv04_i2c_sense_sda,
-};
-
-static int
-nv04_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		   struct nouveau_oclass *oclass, void *data, u32 index,
-		   struct nouveau_object **pobject)
-{
-	struct dcb_i2c_entry *info = data;
-	struct nv04_i2c_port *port;
-	int ret;
-
-	ret = nouveau_i2c_port_create(parent, engine, oclass, index,
-				      &nouveau_i2c_bit_algo, &nv04_i2c_func,
-				      &port);
-	*pobject = nv_object(port);
-	if (ret)
-		return ret;
-
-	port->drive = info->drive;
-	port->sense = info->sense;
-	return 0;
-}
-
-static struct nouveau_oclass
-nv04_i2c_sclass[] = {
-	{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NV04_BIT),
-	  .ofuncs = &(struct nouveau_ofuncs) {
-		  .ctor = nv04_i2c_port_ctor,
-		  .dtor = _nouveau_i2c_port_dtor,
-		  .init = _nouveau_i2c_port_init,
-		  .fini = _nouveau_i2c_port_fini,
-	  },
-	},
-	{}
-};
-
-struct nouveau_oclass *
-nv04_i2c_oclass = &(struct nouveau_i2c_impl) {
-	.base.handle = NV_SUBDEV(I2C, 0x04),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_i2c_ctor,
-		.dtor = _nouveau_i2c_dtor,
-		.init = _nouveau_i2c_init,
-		.fini = _nouveau_i2c_fini,
-	},
-	.sclass = nv04_i2c_sclass,
-	.pad_x = &nv04_i2c_pad_oclass,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv4e.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/nv4e.c
deleted file mode 100644
index f16c87ce5ba1..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv4e.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/vga.h>
-
-#include "priv.h"
-
-struct nv4e_i2c_priv {
-	struct nouveau_i2c base;
-};
-
-struct nv4e_i2c_port {
-	struct nouveau_i2c_port base;
-	u32 addr;
-};
-
-static void
-nv4e_i2c_drive_scl(struct nouveau_i2c_port *base, int state)
-{
-	struct nv4e_i2c_priv *priv = (void *)nv_object(base)->engine;
-	struct nv4e_i2c_port *port = (void *)base;
-	nv_mask(priv, port->addr, 0x2f, state ? 0x21 : 0x01);
-}
-
-static void
-nv4e_i2c_drive_sda(struct nouveau_i2c_port *base, int state)
-{
-	struct nv4e_i2c_priv *priv = (void *)nv_object(base)->engine;
-	struct nv4e_i2c_port *port = (void *)base;
-	nv_mask(priv, port->addr, 0x1f, state ? 0x11 : 0x01);
-}
-
-static int
-nv4e_i2c_sense_scl(struct nouveau_i2c_port *base)
-{
-	struct nv4e_i2c_priv *priv = (void *)nv_object(base)->engine;
-	struct nv4e_i2c_port *port = (void *)base;
-	return !!(nv_rd32(priv, port->addr) & 0x00040000);
-}
-
-static int
-nv4e_i2c_sense_sda(struct nouveau_i2c_port *base)
-{
-	struct nv4e_i2c_priv *priv = (void *)nv_object(base)->engine;
-	struct nv4e_i2c_port *port = (void *)base;
-	return !!(nv_rd32(priv, port->addr) & 0x00080000);
-}
-
-static const struct nouveau_i2c_func
-nv4e_i2c_func = {
-	.drive_scl = nv4e_i2c_drive_scl,
-	.drive_sda = nv4e_i2c_drive_sda,
-	.sense_scl = nv4e_i2c_sense_scl,
-	.sense_sda = nv4e_i2c_sense_sda,
-};
-
-static int
-nv4e_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		   struct nouveau_oclass *oclass, void *data, u32 index,
-		   struct nouveau_object **pobject)
-{
-	struct dcb_i2c_entry *info = data;
-	struct nv4e_i2c_port *port;
-	int ret;
-
-	ret = nouveau_i2c_port_create(parent, engine, oclass, index,
-				      &nouveau_i2c_bit_algo, &nv4e_i2c_func,
-				      &port);
-	*pobject = nv_object(port);
-	if (ret)
-		return ret;
-
-	port->addr = 0x600800 + info->drive;
-	return 0;
-}
-
-static struct nouveau_oclass
-nv4e_i2c_sclass[] = {
-	{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NV4E_BIT),
-	  .ofuncs = &(struct nouveau_ofuncs) {
-		  .ctor = nv4e_i2c_port_ctor,
-		  .dtor = _nouveau_i2c_port_dtor,
-		  .init = _nouveau_i2c_port_init,
-		  .fini = _nouveau_i2c_port_fini,
-	  },
-	},
-	{}
-};
-
-struct nouveau_oclass *
-nv4e_i2c_oclass = &(struct nouveau_i2c_impl) {
-	.base.handle = NV_SUBDEV(I2C, 0x4e),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_i2c_ctor,
-		.dtor = _nouveau_i2c_dtor,
-		.init = _nouveau_i2c_init,
-		.fini = _nouveau_i2c_fini,
-	},
-	.sclass = nv4e_i2c_sclass,
-	.pad_x = &nv04_i2c_pad_oclass,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.c
deleted file mode 100644
index 7b8756d4df08..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv50.h"
-
-void
-nv50_i2c_drive_scl(struct nouveau_i2c_port *base, int state)
-{
-	struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine;
-	struct nv50_i2c_port *port = (void *)base;
-	if (state) port->state |= 0x01;
-	else	   port->state &= 0xfe;
-	nv_wr32(priv, port->addr, port->state);
-}
-
-void
-nv50_i2c_drive_sda(struct nouveau_i2c_port *base, int state)
-{
-	struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine;
-	struct nv50_i2c_port *port = (void *)base;
-	if (state) port->state |= 0x02;
-	else	   port->state &= 0xfd;
-	nv_wr32(priv, port->addr, port->state);
-}
-
-int
-nv50_i2c_sense_scl(struct nouveau_i2c_port *base)
-{
-	struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine;
-	struct nv50_i2c_port *port = (void *)base;
-	return !!(nv_rd32(priv, port->addr) & 0x00000001);
-}
-
-int
-nv50_i2c_sense_sda(struct nouveau_i2c_port *base)
-{
-	struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine;
-	struct nv50_i2c_port *port = (void *)base;
-	return !!(nv_rd32(priv, port->addr) & 0x00000002);
-}
-
-static const struct nouveau_i2c_func
-nv50_i2c_func = {
-	.drive_scl = nv50_i2c_drive_scl,
-	.drive_sda = nv50_i2c_drive_sda,
-	.sense_scl = nv50_i2c_sense_scl,
-	.sense_sda = nv50_i2c_sense_sda,
-};
-
-const u32 nv50_i2c_addr[] = {
-	0x00e138, 0x00e150, 0x00e168, 0x00e180,
-	0x00e254, 0x00e274, 0x00e764, 0x00e780,
-	0x00e79c, 0x00e7b8
-};
-const int nv50_i2c_addr_nr = ARRAY_SIZE(nv50_i2c_addr);
-
-static int
-nv50_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		   struct nouveau_oclass *oclass, void *data, u32 index,
-		   struct nouveau_object **pobject)
-{
-	struct dcb_i2c_entry *info = data;
-	struct nv50_i2c_port *port;
-	int ret;
-
-	ret = nouveau_i2c_port_create(parent, engine, oclass, index,
-				      &nouveau_i2c_bit_algo, &nv50_i2c_func,
-				      &port);
-	*pobject = nv_object(port);
-	if (ret)
-		return ret;
-
-	if (info->drive >= nv50_i2c_addr_nr)
-		return -EINVAL;
-
-	port->state = 0x00000007;
-	port->addr = nv50_i2c_addr[info->drive];
-	return 0;
-}
-
-int
-nv50_i2c_port_init(struct nouveau_object *object)
-{
-	struct nv50_i2c_priv *priv = (void *)object->engine;
-	struct nv50_i2c_port *port = (void *)object;
-	nv_wr32(priv, port->addr, port->state);
-	return nouveau_i2c_port_init(&port->base);
-}
-
-static struct nouveau_oclass
-nv50_i2c_sclass[] = {
-	{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT),
-	  .ofuncs = &(struct nouveau_ofuncs) {
-		  .ctor = nv50_i2c_port_ctor,
-		  .dtor = _nouveau_i2c_port_dtor,
-		  .init = nv50_i2c_port_init,
-		  .fini = _nouveau_i2c_port_fini,
-	  },
-	},
-	{}
-};
-
-struct nouveau_oclass *
-nv50_i2c_oclass = &(struct nouveau_i2c_impl) {
-	.base.handle = NV_SUBDEV(I2C, 0x50),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_i2c_ctor,
-		.dtor = _nouveau_i2c_dtor,
-		.init = _nouveau_i2c_init,
-		.fini = _nouveau_i2c_fini,
-	},
-	.sclass = nv50_i2c_sclass,
-	.pad_x = &nv04_i2c_pad_oclass,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.h b/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.h
deleted file mode 100644
index 9ef965692fb1..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef __NV50_I2C_H__
-#define __NV50_I2C_H__
-
-#include "priv.h"
-
-struct nv50_i2c_priv {
-	struct nouveau_i2c base;
-};
-
-struct nv50_i2c_port {
-	struct nouveau_i2c_port base;
-	u32 addr;
-	u32 state;
-};
-
-extern const u32 nv50_i2c_addr[];
-extern const int nv50_i2c_addr_nr;
-int  nv50_i2c_port_init(struct nouveau_object *);
-int  nv50_i2c_sense_scl(struct nouveau_i2c_port *);
-int  nv50_i2c_sense_sda(struct nouveau_i2c_port *);
-void nv50_i2c_drive_scl(struct nouveau_i2c_port *, int state);
-void nv50_i2c_drive_sda(struct nouveau_i2c_port *, int state);
-
-int  nv94_aux_port_ctor(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, void *, u32,
-			struct nouveau_object **);
-void nv94_i2c_acquire(struct nouveau_i2c_port *);
-void nv94_i2c_release(struct nouveau_i2c_port *);
-
-int  nvd0_i2c_port_ctor(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, void *, u32,
-			struct nouveau_object **);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv94.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/nv94.c
deleted file mode 100644
index e383ee81f4d2..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv94.c
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv50.h"
-
-void
-nv94_aux_stat(struct nouveau_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx)
-{
-	u32 intr = nv_rd32(i2c, 0x00e06c);
-	u32 stat = nv_rd32(i2c, 0x00e068) & intr, i;
-	for (i = 0, *hi = *lo = *rq = *tx = 0; i < 8; i++) {
-		if ((stat & (1 << (i * 4)))) *hi |= 1 << i;
-		if ((stat & (2 << (i * 4)))) *lo |= 1 << i;
-		if ((stat & (4 << (i * 4)))) *rq |= 1 << i;
-		if ((stat & (8 << (i * 4)))) *tx |= 1 << i;
-	}
-	nv_wr32(i2c, 0x00e06c, intr);
-}
-
-void
-nv94_aux_mask(struct nouveau_i2c *i2c, u32 type, u32 mask, u32 data)
-{
-	u32 temp = nv_rd32(i2c, 0x00e068), i;
-	for (i = 0; i < 8; i++) {
-		if (mask & (1 << i)) {
-			if (!(data & (1 << i))) {
-				temp &= ~(type << (i * 4));
-				continue;
-			}
-			temp |= type << (i * 4);
-		}
-	}
-	nv_wr32(i2c, 0x00e068, temp);
-}
-
-#define AUX_DBG(fmt, args...) nv_debug(aux, "AUXCH(%d): " fmt, ch, ##args)
-#define AUX_ERR(fmt, args...) nv_error(aux, "AUXCH(%d): " fmt, ch, ##args)
-
-static void
-auxch_fini(struct nouveau_i2c *aux, int ch)
-{
-	nv_mask(aux, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000);
-}
-
-static int
-auxch_init(struct nouveau_i2c *aux, int ch)
-{
-	const u32 unksel = 1; /* nfi which to use, or if it matters.. */
-	const u32 ureq = unksel ? 0x00100000 : 0x00200000;
-	const u32 urep = unksel ? 0x01000000 : 0x02000000;
-	u32 ctrl, timeout;
-
-	/* wait up to 1ms for any previous transaction to be done... */
-	timeout = 1000;
-	do {
-		ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50));
-		udelay(1);
-		if (!timeout--) {
-			AUX_ERR("begin idle timeout 0x%08x\n", ctrl);
-			return -EBUSY;
-		}
-	} while (ctrl & 0x03010000);
-
-	/* set some magic, and wait up to 1ms for it to appear */
-	nv_mask(aux, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq);
-	timeout = 1000;
-	do {
-		ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50));
-		udelay(1);
-		if (!timeout--) {
-			AUX_ERR("magic wait 0x%08x\n", ctrl);
-			auxch_fini(aux, ch);
-			return -EBUSY;
-		}
-	} while ((ctrl & 0x03000000) != urep);
-
-	return 0;
-}
-
-int
-nv94_aux(struct nouveau_i2c_port *base, bool retry,
-	 u8 type, u32 addr, u8 *data, u8 size)
-{
-	struct nouveau_i2c *aux = nouveau_i2c(base);
-	struct nv50_i2c_port *port = (void *)base;
-	u32 ctrl, stat, timeout, retries;
-	u32 xbuf[4] = {};
-	int ch = port->addr;
-	int ret, i;
-
-	AUX_DBG("%d: 0x%08x %d\n", type, addr, size);
-
-	ret = auxch_init(aux, ch);
-	if (ret)
-		goto out;
-
-	stat = nv_rd32(aux, 0x00e4e8 + (ch * 0x50));
-	if (!(stat & 0x10000000)) {
-		AUX_DBG("sink not detected\n");
-		ret = -ENXIO;
-		goto out;
-	}
-
-	if (!(type & 1)) {
-		memcpy(xbuf, data, size);
-		for (i = 0; i < 16; i += 4) {
-			AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
-			nv_wr32(aux, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]);
-		}
-	}
-
-	ctrl  = nv_rd32(aux, 0x00e4e4 + (ch * 0x50));
-	ctrl &= ~0x0001f0ff;
-	ctrl |= type << 12;
-	ctrl |= size - 1;
-	nv_wr32(aux, 0x00e4e0 + (ch * 0x50), addr);
-
-	/* (maybe) retry transaction a number of times on failure... */
-	for (retries = 0; !ret && retries < 32; retries++) {
-		/* reset, and delay a while if this is a retry */
-		nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl);
-		nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl);
-		if (retries)
-			udelay(400);
-
-		/* transaction request, wait up to 1ms for it to complete */
-		nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl);
-
-		timeout = 1000;
-		do {
-			ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50));
-			udelay(1);
-			if (!timeout--) {
-				AUX_ERR("tx req timeout 0x%08x\n", ctrl);
-				ret = -EIO;
-				goto out;
-			}
-		} while (ctrl & 0x00010000);
-		ret = 1;
-
-		/* read status, and check if transaction completed ok */
-		stat = nv_mask(aux, 0x00e4e8 + (ch * 0x50), 0, 0);
-		if ((stat & 0x000f0000) == 0x00080000 ||
-		    (stat & 0x000f0000) == 0x00020000)
-			ret = retry ? 0 : 1;
-		if ((stat & 0x00000100))
-			ret = -ETIMEDOUT;
-		if ((stat & 0x00000e00))
-			ret = -EIO;
-
-		AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
-	}
-
-	if (type & 1) {
-		for (i = 0; i < 16; i += 4) {
-			xbuf[i / 4] = nv_rd32(aux, 0x00e4d0 + (ch * 0x50) + i);
-			AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
-		}
-		memcpy(data, xbuf, size);
-	}
-
-out:
-	auxch_fini(aux, ch);
-	return ret < 0 ? ret : (stat & 0x000f0000) >> 16;
-}
-
-static const struct nouveau_i2c_func
-nv94_i2c_func = {
-	.drive_scl = nv50_i2c_drive_scl,
-	.drive_sda = nv50_i2c_drive_sda,
-	.sense_scl = nv50_i2c_sense_scl,
-	.sense_sda = nv50_i2c_sense_sda,
-};
-
-static int
-nv94_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		   struct nouveau_oclass *oclass, void *data, u32 index,
-		   struct nouveau_object **pobject)
-{
-	struct dcb_i2c_entry *info = data;
-	struct nv50_i2c_port *port;
-	int ret;
-
-	ret = nouveau_i2c_port_create(parent, engine, oclass, index,
-				      &nouveau_i2c_bit_algo, &nv94_i2c_func,
-				      &port);
-	*pobject = nv_object(port);
-	if (ret)
-		return ret;
-
-	if (info->drive >= nv50_i2c_addr_nr)
-		return -EINVAL;
-
-	port->state = 7;
-	port->addr = nv50_i2c_addr[info->drive];
-	return 0;
-}
-
-static const struct nouveau_i2c_func
-nv94_aux_func = {
-	.aux       = nv94_aux,
-};
-
-int
-nv94_aux_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		   struct nouveau_oclass *oclass, void *data, u32 index,
-		   struct nouveau_object **pobject)
-{
-	struct dcb_i2c_entry *info = data;
-	struct nv50_i2c_port *port;
-	int ret;
-
-	ret = nouveau_i2c_port_create(parent, engine, oclass, index,
-				      &nouveau_i2c_aux_algo, &nv94_aux_func,
-				      &port);
-	*pobject = nv_object(port);
-	if (ret)
-		return ret;
-
-	port->base.aux = info->auxch;
-	port->addr = info->auxch;
-	return 0;
-}
-
-static struct nouveau_oclass
-nv94_i2c_sclass[] = {
-	{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT),
-	  .ofuncs = &(struct nouveau_ofuncs) {
-		  .ctor = nv94_i2c_port_ctor,
-		  .dtor = _nouveau_i2c_port_dtor,
-		  .init = nv50_i2c_port_init,
-		  .fini = _nouveau_i2c_port_fini,
-	  },
-	},
-	{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX),
-	  .ofuncs = &(struct nouveau_ofuncs) {
-		  .ctor = nv94_aux_port_ctor,
-		  .dtor = _nouveau_i2c_port_dtor,
-		  .init = _nouveau_i2c_port_init,
-		  .fini = _nouveau_i2c_port_fini,
-	  },
-	},
-	{}
-};
-
-struct nouveau_oclass *
-nv94_i2c_oclass = &(struct nouveau_i2c_impl) {
-	.base.handle = NV_SUBDEV(I2C, 0x94),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_i2c_ctor,
-		.dtor = _nouveau_i2c_dtor,
-		.init = _nouveau_i2c_init,
-		.fini = _nouveau_i2c_fini,
-	},
-	.sclass = nv94_i2c_sclass,
-	.pad_x = &nv04_i2c_pad_oclass,
-	.pad_s = &nv94_i2c_pad_oclass,
-	.aux = 4,
-	.aux_stat = nv94_aux_stat,
-	.aux_mask = nv94_aux_mask,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nvd0.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/nvd0.c
deleted file mode 100644
index fd99380502ec..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nvd0.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv50.h"
-
-static int
-nvd0_i2c_sense_scl(struct nouveau_i2c_port *base)
-{
-	struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine;
-	struct nv50_i2c_port *port = (void *)base;
-	return !!(nv_rd32(priv, port->addr) & 0x00000010);
-}
-
-static int
-nvd0_i2c_sense_sda(struct nouveau_i2c_port *base)
-{
-	struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine;
-	struct nv50_i2c_port *port = (void *)base;
-	return !!(nv_rd32(priv, port->addr) & 0x00000020);
-}
-
-static const struct nouveau_i2c_func
-nvd0_i2c_func = {
-	.drive_scl = nv50_i2c_drive_scl,
-	.drive_sda = nv50_i2c_drive_sda,
-	.sense_scl = nvd0_i2c_sense_scl,
-	.sense_sda = nvd0_i2c_sense_sda,
-};
-
-int
-nvd0_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		   struct nouveau_oclass *oclass, void *data, u32 index,
-		   struct nouveau_object **pobject)
-{
-	struct dcb_i2c_entry *info = data;
-	struct nv50_i2c_port *port;
-	int ret;
-
-	ret = nouveau_i2c_port_create(parent, engine, oclass, index,
-				      &nouveau_i2c_bit_algo, &nvd0_i2c_func,
-				      &port);
-	*pobject = nv_object(port);
-	if (ret)
-		return ret;
-
-	port->state = 0x00000007;
-	port->addr = 0x00d014 + (info->drive * 0x20);
-	return 0;
-}
-
-struct nouveau_oclass
-nvd0_i2c_sclass[] = {
-	{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT),
-	  .ofuncs = &(struct nouveau_ofuncs) {
-		  .ctor = nvd0_i2c_port_ctor,
-		  .dtor = _nouveau_i2c_port_dtor,
-		  .init = nv50_i2c_port_init,
-		  .fini = _nouveau_i2c_port_fini,
-	  },
-	},
-	{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX),
-	  .ofuncs = &(struct nouveau_ofuncs) {
-		  .ctor = nv94_aux_port_ctor,
-		  .dtor = _nouveau_i2c_port_dtor,
-		  .init = _nouveau_i2c_port_init,
-		  .fini = _nouveau_i2c_port_fini,
-	  },
-	},
-	{}
-};
-
-struct nouveau_oclass *
-nvd0_i2c_oclass = &(struct nouveau_i2c_impl) {
-	.base.handle = NV_SUBDEV(I2C, 0xd0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_i2c_ctor,
-		.dtor = _nouveau_i2c_dtor,
-		.init = _nouveau_i2c_init,
-		.fini = _nouveau_i2c_fini,
-	},
-	.sclass = nvd0_i2c_sclass,
-	.pad_x = &nv04_i2c_pad_oclass,
-	.pad_s = &nv94_i2c_pad_oclass,
-	.aux = 4,
-	.aux_stat = nv94_aux_stat,
-	.aux_mask = nv94_aux_mask,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/nve0.c
deleted file mode 100644
index 25fe5c2d110e..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nve0.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv50.h"
-
-void
-nve0_aux_stat(struct nouveau_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx)
-{
-	u32 intr = nv_rd32(i2c, 0x00dc60);
-	u32 stat = nv_rd32(i2c, 0x00dc68) & intr, i;
-	for (i = 0, *hi = *lo = *rq = *tx = 0; i < 8; i++) {
-		if ((stat & (1 << (i * 4)))) *hi |= 1 << i;
-		if ((stat & (2 << (i * 4)))) *lo |= 1 << i;
-		if ((stat & (4 << (i * 4)))) *rq |= 1 << i;
-		if ((stat & (8 << (i * 4)))) *tx |= 1 << i;
-	}
-	nv_wr32(i2c, 0x00dc60, intr);
-}
-
-void
-nve0_aux_mask(struct nouveau_i2c *i2c, u32 type, u32 mask, u32 data)
-{
-	u32 temp = nv_rd32(i2c, 0x00dc68), i;
-	for (i = 0; i < 8; i++) {
-		if (mask & (1 << i)) {
-			if (!(data & (1 << i))) {
-				temp &= ~(type << (i * 4));
-				continue;
-			}
-			temp |= type << (i * 4);
-		}
-	}
-	nv_wr32(i2c, 0x00dc68, temp);
-}
-
-struct nouveau_oclass *
-nve0_i2c_oclass = &(struct nouveau_i2c_impl) {
-	.base.handle = NV_SUBDEV(I2C, 0xe0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_i2c_ctor,
-		.dtor = _nouveau_i2c_dtor,
-		.init = _nouveau_i2c_init,
-		.fini = _nouveau_i2c_fini,
-	},
-	.sclass = nvd0_i2c_sclass,
-	.pad_x = &nv04_i2c_pad_oclass,
-	.pad_s = &nv94_i2c_pad_oclass,
-	.aux = 4,
-	.aux_stat = nve0_aux_stat,
-	.aux_mask = nve0_aux_mask,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.c
deleted file mode 100644
index e9e412477c12..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "pad.h"
-
-int
-_nvkm_i2c_pad_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nvkm_i2c_pad *pad = (void *)object;
-	DBG("-> NULL\n");
-	pad->port = NULL;
-	return nouveau_object_fini(&pad->base, suspend);
-}
-
-int
-_nvkm_i2c_pad_init(struct nouveau_object *object)
-{
-	struct nvkm_i2c_pad *pad = (void *)object;
-	DBG("-> PORT:%02x\n", pad->next->index);
-	pad->port = pad->next;
-	return nouveau_object_init(&pad->base);
-}
-
-int
-nvkm_i2c_pad_create_(struct nouveau_object *parent,
-		     struct nouveau_object *engine,
-		     struct nouveau_oclass *oclass, int index,
-		     int size, void **pobject)
-{
-	struct nouveau_i2c *i2c = (void *)engine;
-	struct nouveau_i2c_port *port;
-	struct nvkm_i2c_pad *pad;
-	int ret;
-
-	list_for_each_entry(port, &i2c->ports, head) {
-		pad = nvkm_i2c_pad(port);
-		if (pad->index == index) {
-			atomic_inc(&nv_object(pad)->refcount);
-			*pobject = pad;
-			return 1;
-		}
-	}
-
-	ret = nouveau_object_create_(parent, engine, oclass, 0, size, pobject);
-	pad = *pobject;
-	if (ret)
-		return ret;
-
-	pad->index = index;
-	return 0;
-}
-
-int
-_nvkm_i2c_pad_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		   struct nouveau_oclass *oclass, void *data, u32 index,
-		   struct nouveau_object **pobject)
-{
-	struct nvkm_i2c_pad *pad;
-	int ret;
-	ret = nvkm_i2c_pad_create(parent, engine, oclass, index, &pad);
-	*pobject = nv_object(pad);
-	return ret;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h b/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h
deleted file mode 100644
index 452ac10c3004..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef __NVKM_I2C_PAD_H__
-#define __NVKM_I2C_PAD_H__
-
-#include "priv.h"
-
-struct nvkm_i2c_pad {
-	struct nouveau_object base;
-	int index;
-	struct nouveau_i2c_port *port;
-	struct nouveau_i2c_port *next;
-};
-
-static inline struct nvkm_i2c_pad *
-nvkm_i2c_pad(struct nouveau_i2c_port *port)
-{
-	struct nouveau_object *pad = nv_object(port);
-	while (pad->parent)
-		pad = pad->parent;
-	return (void *)pad;
-}
-
-#define nvkm_i2c_pad_create(p,e,o,i,d)                                         \
-	nvkm_i2c_pad_create_((p), (e), (o), (i), sizeof(**d), (void **)d)
-#define nvkm_i2c_pad_destroy(p) ({                                             \
-	struct nvkm_i2c_pad *_p = (p);                                         \
-	_nvkm_i2c_pad_dtor(nv_object(_p));                                     \
-})
-#define nvkm_i2c_pad_init(p) ({                                                \
-	struct nvkm_i2c_pad *_p = (p);                                         \
-	_nvkm_i2c_pad_init(nv_object(_p));                                     \
-})
-#define nvkm_i2c_pad_fini(p,s) ({                                              \
-	struct nvkm_i2c_pad *_p = (p);                                         \
-	_nvkm_i2c_pad_fini(nv_object(_p), (s));                                \
-})
-
-int nvkm_i2c_pad_create_(struct nouveau_object *, struct nouveau_object *,
-			 struct nouveau_oclass *, int index, int, void **);
-
-int _nvkm_i2c_pad_ctor(struct nouveau_object *, struct nouveau_object *,
-		       struct nouveau_oclass *, void *, u32,
-		       struct nouveau_object **);
-#define _nvkm_i2c_pad_dtor nouveau_object_destroy
-int _nvkm_i2c_pad_init(struct nouveau_object *);
-int _nvkm_i2c_pad_fini(struct nouveau_object *, bool);
-
-#ifndef MSG
-#define MSG(l,f,a...) do {                                                     \
-	struct nvkm_i2c_pad *_pad = (void *)pad;                               \
-	nv_##l(nv_object(_pad)->engine, "PAD:%c:%02x: "f,                      \
-	       _pad->index >= 0x100 ? 'X' : 'S',                               \
-	       _pad->index >= 0x100 ? _pad->index - 0x100 : _pad->index, ##a); \
-} while(0)
-#define DBG(f,a...) MSG(debug, f, ##a)
-#define ERR(f,a...) MSG(error, f, ##a)
-#endif
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/padgm204.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/padgm204.c
deleted file mode 100644
index f0e6fbbaa8cd..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/padgm204.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "pad.h"
-
-struct gm204_i2c_pad {
-	struct nvkm_i2c_pad base;
-	int addr;
-};
-
-static int
-gm204_i2c_pad_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nouveau_i2c *i2c = (void *)object->engine;
-	struct gm204_i2c_pad *pad = (void *)object;
-	nv_mask(i2c, 0x00d97c + pad->addr, 0x00000001, 0x00000001);
-	return nvkm_i2c_pad_fini(&pad->base, suspend);
-}
-
-static int
-gm204_i2c_pad_init(struct nouveau_object *object)
-{
-	struct nouveau_i2c *i2c = (void *)object->engine;
-	struct gm204_i2c_pad *pad = (void *)object;
-
-	switch (nv_oclass(pad->base.next)->handle) {
-	case NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX):
-		nv_mask(i2c, 0x00d970 + pad->addr, 0x0000c003, 0x00000002);
-		break;
-	case NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT):
-	default:
-		nv_mask(i2c, 0x00d970 + pad->addr, 0x0000c003, 0x0000c001);
-		break;
-	}
-
-	nv_mask(i2c, 0x00d97c + pad->addr, 0x00000001, 0x00000000);
-	return nvkm_i2c_pad_init(&pad->base);
-}
-
-static int
-gm204_i2c_pad_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 index,
-		  struct nouveau_object **pobject)
-{
-	struct gm204_i2c_pad *pad;
-	int ret;
-
-	ret = nvkm_i2c_pad_create(parent, engine, oclass, index, &pad);
-	*pobject = nv_object(pad);
-	if (ret)
-		return ret;
-
-	pad->addr = index * 0x50;;
-	return 0;
-}
-
-struct nouveau_oclass
-gm204_i2c_pad_oclass = {
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = gm204_i2c_pad_ctor,
-		.dtor = _nvkm_i2c_pad_dtor,
-		.init = gm204_i2c_pad_init,
-		.fini = gm204_i2c_pad_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv04.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv04.c
deleted file mode 100644
index 2c4b61296dd1..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv04.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "pad.h"
-
-struct nouveau_oclass
-nv04_i2c_pad_oclass = {
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nvkm_i2c_pad_ctor,
-		.dtor = _nvkm_i2c_pad_dtor,
-		.init = _nvkm_i2c_pad_init,
-		.fini = _nvkm_i2c_pad_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv94.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv94.c
deleted file mode 100644
index 0dc6753014f0..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv94.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "pad.h"
-
-struct nv94_i2c_pad {
-	struct nvkm_i2c_pad base;
-	int addr;
-};
-
-static int
-nv94_i2c_pad_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nouveau_i2c *i2c = (void *)object->engine;
-	struct nv94_i2c_pad *pad = (void *)object;
-	nv_mask(i2c, 0x00e50c + pad->addr, 0x00000001, 0x00000001);
-	return nvkm_i2c_pad_fini(&pad->base, suspend);
-}
-
-static int
-nv94_i2c_pad_init(struct nouveau_object *object)
-{
-	struct nouveau_i2c *i2c = (void *)object->engine;
-	struct nv94_i2c_pad *pad = (void *)object;
-
-	switch (nv_oclass(pad->base.next)->handle) {
-	case NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX):
-		nv_mask(i2c, 0x00e500 + pad->addr, 0x0000c003, 0x00000002);
-		break;
-	case NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT):
-	default:
-		nv_mask(i2c, 0x00e500 + pad->addr, 0x0000c003, 0x0000c001);
-		break;
-	}
-
-	nv_mask(i2c, 0x00e50c + pad->addr, 0x00000001, 0x00000000);
-	return nvkm_i2c_pad_init(&pad->base);
-}
-
-static int
-nv94_i2c_pad_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 index,
-		  struct nouveau_object **pobject)
-{
-	struct nv94_i2c_pad *pad;
-	int ret;
-
-	ret = nvkm_i2c_pad_create(parent, engine, oclass, index, &pad);
-	*pobject = nv_object(pad);
-	if (ret)
-		return ret;
-
-	pad->addr = index * 0x50;;
-	return 0;
-}
-
-struct nouveau_oclass
-nv94_i2c_pad_oclass = {
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv94_i2c_pad_ctor,
-		.dtor = _nvkm_i2c_pad_dtor,
-		.init = nv94_i2c_pad_init,
-		.fini = nv94_i2c_pad_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/port.h b/drivers/gpu/drm/nouveau/core/subdev/i2c/port.h
deleted file mode 100644
index a8ff6e077af5..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/port.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef __NVKM_I2C_PORT_H__
-#define __NVKM_I2C_PORT_H__
-
-#include "priv.h"
-
-#ifndef MSG
-#define MSG(l,f,a...) do {                                                     \
-	struct nouveau_i2c_port *_port = (void *)port;                         \
-	nv_##l(nv_object(_port)->engine, "PORT:%02x: "f, _port->index, ##a);   \
-} while(0)
-#define DBG(f,a...) MSG(debug, f, ##a)
-#define ERR(f,a...) MSG(error, f, ##a)
-#endif
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/priv.h b/drivers/gpu/drm/nouveau/core/subdev/i2c/priv.h
deleted file mode 100644
index 4fe7ae3fde4e..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/priv.h
+++ /dev/null
@@ -1,89 +0,0 @@
-#ifndef __NVKM_I2C_H__
-#define __NVKM_I2C_H__
-
-#include <subdev/i2c.h>
-
-extern struct nouveau_oclass nv04_i2c_pad_oclass;
-extern struct nouveau_oclass nv94_i2c_pad_oclass;
-extern struct nouveau_oclass gm204_i2c_pad_oclass;
-
-#define nouveau_i2c_port_create(p,e,o,i,a,f,d)                                 \
-	nouveau_i2c_port_create_((p), (e), (o), (i), (a), (f),                 \
-				 sizeof(**d), (void **)d)
-#define nouveau_i2c_port_destroy(p) ({                                         \
-	struct nouveau_i2c_port *port = (p);                                   \
-	_nouveau_i2c_port_dtor(nv_object(i2c));                                \
-})
-#define nouveau_i2c_port_init(p)                                               \
-	nouveau_object_init(&(p)->base)
-#define nouveau_i2c_port_fini(p,s)                                             \
-	nouveau_object_fini(&(p)->base, (s))
-
-int nouveau_i2c_port_create_(struct nouveau_object *, struct nouveau_object *,
-			     struct nouveau_oclass *, u8,
-			     const struct i2c_algorithm *,
-			     const struct nouveau_i2c_func *,
-			     int, void **);
-void _nouveau_i2c_port_dtor(struct nouveau_object *);
-#define _nouveau_i2c_port_init nouveau_object_init
-int  _nouveau_i2c_port_fini(struct nouveau_object *, bool);
-
-#define nouveau_i2c_create(p,e,o,d)                                            \
-	nouveau_i2c_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_i2c_destroy(p) ({                                              \
-	struct nouveau_i2c *i2c = (p);                                         \
-	_nouveau_i2c_dtor(nv_object(i2c));                                     \
-})
-#define nouveau_i2c_init(p) ({                                                 \
-	struct nouveau_i2c *i2c = (p);                                         \
-	_nouveau_i2c_init(nv_object(i2c));                                     \
-})
-#define nouveau_i2c_fini(p,s) ({                                               \
-	struct nouveau_i2c *i2c = (p);                                         \
-	_nouveau_i2c_fini(nv_object(i2c), (s));                                \
-})
-
-int nouveau_i2c_create_(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, int, void **);
-int  _nouveau_i2c_ctor(struct nouveau_object *, struct nouveau_object *,
-		       struct nouveau_oclass *, void *, u32,
-		       struct nouveau_object **);
-void _nouveau_i2c_dtor(struct nouveau_object *);
-int  _nouveau_i2c_init(struct nouveau_object *);
-int  _nouveau_i2c_fini(struct nouveau_object *, bool);
-
-extern struct nouveau_oclass nouveau_anx9805_sclass[];
-extern struct nouveau_oclass nvd0_i2c_sclass[];
-
-extern const struct i2c_algorithm nouveau_i2c_bit_algo;
-extern const struct i2c_algorithm nouveau_i2c_aux_algo;
-
-struct nouveau_i2c_impl {
-	struct nouveau_oclass base;
-
-	/* supported i2c port classes */
-	struct nouveau_oclass *sclass;
-	struct nouveau_oclass *pad_x;
-	struct nouveau_oclass *pad_s;
-
-	/* number of native dp aux channels present */
-	int aux;
-
-	/* read and ack pending interrupts, returning only data
-	 * for ports that have not been masked off, while still
-	 * performing the ack for anything that was pending.
-	 */
-	void (*aux_stat)(struct nouveau_i2c *, u32 *, u32 *, u32 *, u32 *);
-
-	/* mask on/off interrupt types for a given set of auxch
-	 */
-	void (*aux_mask)(struct nouveau_i2c *, u32, u32, u32);
-};
-
-void nv94_aux_stat(struct nouveau_i2c *, u32 *, u32 *, u32 *, u32 *);
-void nv94_aux_mask(struct nouveau_i2c *, u32, u32, u32);
-
-void nve0_aux_stat(struct nouveau_i2c *, u32 *, u32 *, u32 *, u32 *);
-void nve0_aux_mask(struct nouveau_i2c *, u32, u32, u32);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/ibus/gk20a.c
deleted file mode 100644
index 245f0ebaa6af..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/ibus/gk20a.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include <subdev/ibus.h>
-#include <subdev/timer.h>
-
-struct gk20a_ibus_priv {
-	struct nouveau_ibus base;
-};
-
-static void
-gk20a_ibus_init_priv_ring(struct gk20a_ibus_priv *priv)
-{
-	nv_mask(priv, 0x137250, 0x3f, 0);
-
-	nv_mask(priv, 0x000200, 0x20, 0);
-	usleep_range(20, 30);
-	nv_mask(priv, 0x000200, 0x20, 0x20);
-
-	nv_wr32(priv, 0x12004c, 0x4);
-	nv_wr32(priv, 0x122204, 0x2);
-	nv_rd32(priv, 0x122204);
-}
-
-static void
-gk20a_ibus_intr(struct nouveau_subdev *subdev)
-{
-	struct gk20a_ibus_priv *priv = (void *)subdev;
-	u32 status0 = nv_rd32(priv, 0x120058);
-
-	if (status0 & 0x7) {
-		nv_debug(priv, "resetting priv ring\n");
-		gk20a_ibus_init_priv_ring(priv);
-	}
-
-	/* Acknowledge interrupt */
-	nv_mask(priv, 0x12004c, 0x2, 0x2);
-
-	if (!nv_wait(subdev, 0x12004c, 0x3f, 0x00))
-		nv_warn(priv, "timeout waiting for ringmaster ack\n");
-}
-
-static int
-gk20a_ibus_init(struct nouveau_object *object)
-{
-	struct gk20a_ibus_priv *priv = (void *)object;
-	int ret;
-
-	ret = _nouveau_ibus_init(object);
-	if (ret)
-		return ret;
-
-	gk20a_ibus_init_priv_ring(priv);
-
-	return 0;
-}
-
-static int
-gk20a_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct gk20a_ibus_priv *priv;
-	int ret;
-
-	ret = nouveau_ibus_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->intr = gk20a_ibus_intr;
-	return 0;
-}
-
-struct nouveau_oclass
-gk20a_ibus_oclass = {
-	.handle = NV_SUBDEV(IBUS, 0xea),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = gk20a_ibus_ctor,
-		.dtor = _nouveau_ibus_dtor,
-		.init = gk20a_ibus_init,
-		.fini = _nouveau_ibus_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/ibus/nvc0.c
deleted file mode 100644
index 4e977ff27e44..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/ibus/nvc0.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/ibus.h>
-
-struct nvc0_ibus_priv {
-	struct nouveau_ibus base;
-};
-
-static void
-nvc0_ibus_intr_hub(struct nvc0_ibus_priv *priv, int i)
-{
-	u32 addr = nv_rd32(priv, 0x122120 + (i * 0x0400));
-	u32 data = nv_rd32(priv, 0x122124 + (i * 0x0400));
-	u32 stat = nv_rd32(priv, 0x122128 + (i * 0x0400));
-	nv_error(priv, "HUB%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat);
-	nv_mask(priv, 0x122128 + (i * 0x0400), 0x00000200, 0x00000000);
-}
-
-static void
-nvc0_ibus_intr_rop(struct nvc0_ibus_priv *priv, int i)
-{
-	u32 addr = nv_rd32(priv, 0x124120 + (i * 0x0400));
-	u32 data = nv_rd32(priv, 0x124124 + (i * 0x0400));
-	u32 stat = nv_rd32(priv, 0x124128 + (i * 0x0400));
-	nv_error(priv, "ROP%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat);
-	nv_mask(priv, 0x124128 + (i * 0x0400), 0x00000200, 0x00000000);
-}
-
-static void
-nvc0_ibus_intr_gpc(struct nvc0_ibus_priv *priv, int i)
-{
-	u32 addr = nv_rd32(priv, 0x128120 + (i * 0x0400));
-	u32 data = nv_rd32(priv, 0x128124 + (i * 0x0400));
-	u32 stat = nv_rd32(priv, 0x128128 + (i * 0x0400));
-	nv_error(priv, "GPC%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat);
-	nv_mask(priv, 0x128128 + (i * 0x0400), 0x00000200, 0x00000000);
-}
-
-static void
-nvc0_ibus_intr(struct nouveau_subdev *subdev)
-{
-	struct nvc0_ibus_priv *priv = (void *)subdev;
-	u32 intr0 = nv_rd32(priv, 0x121c58);
-	u32 intr1 = nv_rd32(priv, 0x121c5c);
-	u32 hubnr = nv_rd32(priv, 0x121c70);
-	u32 ropnr = nv_rd32(priv, 0x121c74);
-	u32 gpcnr = nv_rd32(priv, 0x121c78);
-	u32 i;
-
-	for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) {
-		u32 stat = 0x00000100 << i;
-		if (intr0 & stat) {
-			nvc0_ibus_intr_hub(priv, i);
-			intr0 &= ~stat;
-		}
-	}
-
-	for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) {
-		u32 stat = 0x00010000 << i;
-		if (intr0 & stat) {
-			nvc0_ibus_intr_rop(priv, i);
-			intr0 &= ~stat;
-		}
-	}
-
-	for (i = 0; intr1 && i < gpcnr; i++) {
-		u32 stat = 0x00000001 << i;
-		if (intr1 & stat) {
-			nvc0_ibus_intr_gpc(priv, i);
-			intr1 &= ~stat;
-		}
-	}
-}
-
-static int
-nvc0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nvc0_ibus_priv *priv;
-	int ret;
-
-	ret = nouveau_ibus_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->intr = nvc0_ibus_intr;
-	return 0;
-}
-
-struct nouveau_oclass
-nvc0_ibus_oclass = {
-	.handle = NV_SUBDEV(IBUS, 0xc0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_ibus_ctor,
-		.dtor = _nouveau_ibus_dtor,
-		.init = _nouveau_ibus_init,
-		.fini = _nouveau_ibus_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c
deleted file mode 100644
index ebef970a0645..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/ibus.h>
-
-struct nve0_ibus_priv {
-	struct nouveau_ibus base;
-};
-
-static void
-nve0_ibus_intr_hub(struct nve0_ibus_priv *priv, int i)
-{
-	u32 addr = nv_rd32(priv, 0x122120 + (i * 0x0800));
-	u32 data = nv_rd32(priv, 0x122124 + (i * 0x0800));
-	u32 stat = nv_rd32(priv, 0x122128 + (i * 0x0800));
-	nv_error(priv, "HUB%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat);
-	nv_mask(priv, 0x122128 + (i * 0x0800), 0x00000200, 0x00000000);
-}
-
-static void
-nve0_ibus_intr_rop(struct nve0_ibus_priv *priv, int i)
-{
-	u32 addr = nv_rd32(priv, 0x124120 + (i * 0x0800));
-	u32 data = nv_rd32(priv, 0x124124 + (i * 0x0800));
-	u32 stat = nv_rd32(priv, 0x124128 + (i * 0x0800));
-	nv_error(priv, "ROP%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat);
-	nv_mask(priv, 0x124128 + (i * 0x0800), 0x00000200, 0x00000000);
-}
-
-static void
-nve0_ibus_intr_gpc(struct nve0_ibus_priv *priv, int i)
-{
-	u32 addr = nv_rd32(priv, 0x128120 + (i * 0x0800));
-	u32 data = nv_rd32(priv, 0x128124 + (i * 0x0800));
-	u32 stat = nv_rd32(priv, 0x128128 + (i * 0x0800));
-	nv_error(priv, "GPC%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat);
-	nv_mask(priv, 0x128128 + (i * 0x0800), 0x00000200, 0x00000000);
-}
-
-static void
-nve0_ibus_intr(struct nouveau_subdev *subdev)
-{
-	struct nve0_ibus_priv *priv = (void *)subdev;
-	u32 intr0 = nv_rd32(priv, 0x120058);
-	u32 intr1 = nv_rd32(priv, 0x12005c);
-	u32 hubnr = nv_rd32(priv, 0x120070);
-	u32 ropnr = nv_rd32(priv, 0x120074);
-	u32 gpcnr = nv_rd32(priv, 0x120078);
-	u32 i;
-
-	for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) {
-		u32 stat = 0x00000100 << i;
-		if (intr0 & stat) {
-			nve0_ibus_intr_hub(priv, i);
-			intr0 &= ~stat;
-		}
-	}
-
-	for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) {
-		u32 stat = 0x00010000 << i;
-		if (intr0 & stat) {
-			nve0_ibus_intr_rop(priv, i);
-			intr0 &= ~stat;
-		}
-	}
-
-	for (i = 0; intr1 && i < gpcnr; i++) {
-		u32 stat = 0x00000001 << i;
-		if (intr1 & stat) {
-			nve0_ibus_intr_gpc(priv, i);
-			intr1 &= ~stat;
-		}
-	}
-}
-
-static int
-nve0_ibus_init(struct nouveau_object *object)
-{
-	struct nve0_ibus_priv *priv = (void *)object;
-	int ret = nouveau_ibus_init(&priv->base);
-	if (ret == 0) {
-		nv_mask(priv, 0x122318, 0x0003ffff, 0x00001000);
-		nv_mask(priv, 0x12231c, 0x0003ffff, 0x00000200);
-		nv_mask(priv, 0x122310, 0x0003ffff, 0x00000800);
-		nv_mask(priv, 0x122348, 0x0003ffff, 0x00000100);
-		nv_mask(priv, 0x1223b0, 0x0003ffff, 0x00000fff);
-		nv_mask(priv, 0x122348, 0x0003ffff, 0x00000200);
-		nv_mask(priv, 0x122358, 0x0003ffff, 0x00002880);
-	}
-	return ret;
-}
-
-static int
-nve0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nve0_ibus_priv *priv;
-	int ret;
-
-	ret = nouveau_ibus_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->intr = nve0_ibus_intr;
-	return 0;
-}
-
-struct nouveau_oclass
-nve0_ibus_oclass = {
-	.handle = NV_SUBDEV(IBUS, 0xe0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nve0_ibus_ctor,
-		.dtor = _nouveau_ibus_dtor,
-		.init = nve0_ibus_init,
-		.fini = _nouveau_ibus_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c
deleted file mode 100644
index 14706d9842ca..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-
-/******************************************************************************
- * instmem object base implementation
- *****************************************************************************/
-
-void
-_nouveau_instobj_dtor(struct nouveau_object *object)
-{
-	struct nouveau_instmem *imem = (void *)object->engine;
-	struct nouveau_instobj *iobj = (void *)object;
-
-	mutex_lock(&nv_subdev(imem)->mutex);
-	list_del(&iobj->head);
-	mutex_unlock(&nv_subdev(imem)->mutex);
-
-	return nouveau_object_destroy(&iobj->base);
-}
-
-int
-nouveau_instobj_create_(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass,
-			int length, void **pobject)
-{
-	struct nouveau_instmem *imem = (void *)engine;
-	struct nouveau_instobj *iobj;
-	int ret;
-
-	ret = nouveau_object_create_(parent, engine, oclass, NV_MEMOBJ_CLASS,
-				     length, pobject);
-	iobj = *pobject;
-	if (ret)
-		return ret;
-
-	mutex_lock(&imem->base.mutex);
-	list_add(&iobj->head, &imem->list);
-	mutex_unlock(&imem->base.mutex);
-	return 0;
-}
-
-/******************************************************************************
- * instmem subdev base implementation
- *****************************************************************************/
-
-static int
-nouveau_instmem_alloc(struct nouveau_instmem *imem,
-		      struct nouveau_object *parent, u32 size, u32 align,
-		      struct nouveau_object **pobject)
-{
-	struct nouveau_object *engine = nv_object(imem);
-	struct nouveau_instmem_impl *impl = (void *)engine->oclass;
-	struct nouveau_instobj_args args = { .size = size, .align = align };
-	return nouveau_object_ctor(parent, engine, impl->instobj, &args,
-				   sizeof(args), pobject);
-}
-
-int
-_nouveau_instmem_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nouveau_instmem *imem = (void *)object;
-	struct nouveau_instobj *iobj;
-	int i, ret = 0;
-
-	if (suspend) {
-		mutex_lock(&imem->base.mutex);
-
-		list_for_each_entry(iobj, &imem->list, head) {
-			iobj->suspend = vmalloc(iobj->size);
-			if (!iobj->suspend) {
-				ret = -ENOMEM;
-				break;
-			}
-
-			for (i = 0; i < iobj->size; i += 4)
-				iobj->suspend[i / 4] = nv_ro32(iobj, i);
-		}
-
-		mutex_unlock(&imem->base.mutex);
-
-		if (ret)
-			return ret;
-	}
-
-	return nouveau_subdev_fini(&imem->base, suspend);
-}
-
-int
-_nouveau_instmem_init(struct nouveau_object *object)
-{
-	struct nouveau_instmem *imem = (void *)object;
-	struct nouveau_instobj *iobj;
-	int ret, i;
-
-	ret = nouveau_subdev_init(&imem->base);
-	if (ret)
-		return ret;
-
-	mutex_lock(&imem->base.mutex);
-
-	list_for_each_entry(iobj, &imem->list, head) {
-		if (iobj->suspend) {
-			for (i = 0; i < iobj->size; i += 4)
-				nv_wo32(iobj, i, iobj->suspend[i / 4]);
-			vfree(iobj->suspend);
-			iobj->suspend = NULL;
-		}
-	}
-
-	mutex_unlock(&imem->base.mutex);
-
-	return 0;
-}
-
-int
-nouveau_instmem_create_(struct nouveau_object *parent,
-			struct nouveau_object *engine,
-			struct nouveau_oclass *oclass,
-			int length, void **pobject)
-{
-	struct nouveau_instmem *imem;
-	int ret;
-
-	ret = nouveau_subdev_create_(parent, engine, oclass, 0,
-				     "INSTMEM", "instmem", length, pobject);
-	imem = *pobject;
-	if (ret)
-		return ret;
-
-	INIT_LIST_HEAD(&imem->list);
-	imem->alloc = nouveau_instmem_alloc;
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c
deleted file mode 100644
index e8b1401c59c0..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv04.h"
-
-/******************************************************************************
- * instmem object implementation
- *****************************************************************************/
-
-static u32
-nv04_instobj_rd32(struct nouveau_object *object, u64 addr)
-{
-	struct nv04_instobj_priv *node = (void *)object;
-	return nv_ro32(object->engine, node->mem->offset + addr);
-}
-
-static void
-nv04_instobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
-{
-	struct nv04_instobj_priv *node = (void *)object;
-	nv_wo32(object->engine, node->mem->offset + addr, data);
-}
-
-static void
-nv04_instobj_dtor(struct nouveau_object *object)
-{
-	struct nv04_instmem_priv *priv = (void *)object->engine;
-	struct nv04_instobj_priv *node = (void *)object;
-	nouveau_mm_free(&priv->heap, &node->mem);
-	nouveau_instobj_destroy(&node->base);
-}
-
-static int
-nv04_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 size,
-		  struct nouveau_object **pobject)
-{
-	struct nv04_instmem_priv *priv = (void *)engine;
-	struct nv04_instobj_priv *node;
-	struct nouveau_instobj_args *args = data;
-	int ret;
-
-	if (!args->align)
-		args->align = 1;
-
-	ret = nouveau_instobj_create(parent, engine, oclass, &node);
-	*pobject = nv_object(node);
-	if (ret)
-		return ret;
-
-	ret = nouveau_mm_head(&priv->heap, 0, 1, args->size, args->size,
-			      args->align, &node->mem);
-	if (ret)
-		return ret;
-
-	node->base.addr = node->mem->offset;
-	node->base.size = node->mem->length;
-	return 0;
-}
-
-struct nouveau_instobj_impl
-nv04_instobj_oclass = {
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_instobj_ctor,
-		.dtor = nv04_instobj_dtor,
-		.init = _nouveau_instobj_init,
-		.fini = _nouveau_instobj_fini,
-		.rd32 = nv04_instobj_rd32,
-		.wr32 = nv04_instobj_wr32,
-	},
-};
-
-/******************************************************************************
- * instmem subdev implementation
- *****************************************************************************/
-
-static u32
-nv04_instmem_rd32(struct nouveau_object *object, u64 addr)
-{
-	return nv_rd32(object, 0x700000 + addr);
-}
-
-static void
-nv04_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data)
-{
-	return nv_wr32(object, 0x700000 + addr, data);
-}
-
-void
-nv04_instmem_dtor(struct nouveau_object *object)
-{
-	struct nv04_instmem_priv *priv = (void *)object;
-	nouveau_gpuobj_ref(NULL, &priv->ramfc);
-	nouveau_gpuobj_ref(NULL, &priv->ramro);
-	nouveau_ramht_ref(NULL, &priv->ramht);
-	nouveau_gpuobj_ref(NULL, &priv->vbios);
-	nouveau_mm_fini(&priv->heap);
-	if (priv->iomem)
-		iounmap(priv->iomem);
-	nouveau_instmem_destroy(&priv->base);
-}
-
-static int
-nv04_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 size,
-		  struct nouveau_object **pobject)
-{
-	struct nv04_instmem_priv *priv;
-	int ret;
-
-	ret = nouveau_instmem_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	/* PRAMIN aperture maps over the end of VRAM, reserve it */
-	priv->base.reserved = 512 * 1024;
-
-	ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1);
-	if (ret)
-		return ret;
-
-	/* 0x00000-0x10000: reserve for probable vbios image */
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0,
-				&priv->vbios);
-	if (ret)
-		return ret;
-
-	/* 0x10000-0x18000: reserve for RAMHT */
-	ret = nouveau_ramht_new(nv_object(priv), NULL, 0x08000, 0, &priv->ramht);
-	if (ret)
-		return ret;
-
-	/* 0x18000-0x18800: reserve for RAMFC (enough for 32 nv30 channels) */
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x00800, 0,
-				 NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc);
-	if (ret)
-		return ret;
-
-	/* 0x18800-0x18a00: reserve for RAMRO */
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x00200, 0, 0,
-				&priv->ramro);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-struct nouveau_oclass *
-nv04_instmem_oclass = &(struct nouveau_instmem_impl) {
-	.base.handle = NV_SUBDEV(INSTMEM, 0x04),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_instmem_ctor,
-		.dtor = nv04_instmem_dtor,
-		.init = _nouveau_instmem_init,
-		.fini = _nouveau_instmem_fini,
-		.rd32 = nv04_instmem_rd32,
-		.wr32 = nv04_instmem_wr32,
-	},
-	.instobj = &nv04_instobj_oclass.base,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h
deleted file mode 100644
index 095fbc6fc099..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h
+++ /dev/null
@@ -1,40 +0,0 @@
-#ifndef __NV04_INSTMEM_H__
-#define __NV04_INSTMEM_H__
-
-#include <core/gpuobj.h>
-#include <core/ramht.h>
-#include <core/mm.h>
-
-#include "priv.h"
-
-extern struct nouveau_instobj_impl nv04_instobj_oclass;
-
-struct nv04_instmem_priv {
-	struct nouveau_instmem base;
-
-	void __iomem *iomem;
-	struct nouveau_mm heap;
-
-	struct nouveau_gpuobj *vbios;
-	struct nouveau_ramht  *ramht;
-	struct nouveau_gpuobj *ramro;
-	struct nouveau_gpuobj *ramfc;
-};
-
-static inline struct nv04_instmem_priv *
-nv04_instmem(void *obj)
-{
-	return (void *)nouveau_instmem(obj);
-}
-
-struct nv04_instobj_priv {
-	struct nouveau_instobj base;
-	struct nouveau_mm_node *mem;
-};
-
-void nv04_instmem_dtor(struct nouveau_object *);
-
-int nv04_instmem_alloc(struct nouveau_instmem *, struct nouveau_object *,
-		       u32 size, u32 align, struct nouveau_object **pobject);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c
deleted file mode 100644
index 8803809f9fc5..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <engine/graph/nv40.h>
-
-#include "nv04.h"
-
-/******************************************************************************
- * instmem subdev implementation
- *****************************************************************************/
-
-static u32
-nv40_instmem_rd32(struct nouveau_object *object, u64 addr)
-{
-	struct nv04_instmem_priv *priv = (void *)object;
-	return ioread32_native(priv->iomem + addr);
-}
-
-static void
-nv40_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data)
-{
-	struct nv04_instmem_priv *priv = (void *)object;
-	iowrite32_native(data, priv->iomem + addr);
-}
-
-static int
-nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 size,
-		  struct nouveau_object **pobject)
-{
-	struct nouveau_device *device = nv_device(parent);
-	struct nv04_instmem_priv *priv;
-	int ret, bar, vs;
-
-	ret = nouveau_instmem_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	/* map bar */
-	if (nv_device_resource_len(device, 2))
-		bar = 2;
-	else
-		bar = 3;
-
-	priv->iomem = ioremap(nv_device_resource_start(device, bar),
-			      nv_device_resource_len(device, bar));
-	if (!priv->iomem) {
-		nv_error(priv, "unable to map PRAMIN BAR\n");
-		return -EFAULT;
-	}
-
-	/* PRAMIN aperture maps over the end of vram, reserve enough space
-	 * to fit graphics contexts for every channel, the magics come
-	 * from engine/graph/nv40.c
-	 */
-	vs = hweight8((nv_rd32(priv, 0x001540) & 0x0000ff00) >> 8);
-	if      (device->chipset == 0x40) priv->base.reserved = 0x6aa0 * vs;
-	else if (device->chipset  < 0x43) priv->base.reserved = 0x4f00 * vs;
-	else if (nv44_graph_class(priv))  priv->base.reserved = 0x4980 * vs;
-	else				  priv->base.reserved = 0x4a40 * vs;
-	priv->base.reserved += 16 * 1024;
-	priv->base.reserved *= 32;		/* per-channel */
-	priv->base.reserved += 512 * 1024;	/* pci(e)gart table */
-	priv->base.reserved += 512 * 1024;	/* object storage */
-
-	priv->base.reserved = round_up(priv->base.reserved, 4096);
-
-	ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1);
-	if (ret)
-		return ret;
-
-	/* 0x00000-0x10000: reserve for probable vbios image */
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0,
-				&priv->vbios);
-	if (ret)
-		return ret;
-
-	/* 0x10000-0x18000: reserve for RAMHT */
-	ret = nouveau_ramht_new(nv_object(priv), NULL, 0x08000, 0,
-			       &priv->ramht);
-	if (ret)
-		return ret;
-
-	/* 0x18000-0x18200: reserve for RAMRO
-	 * 0x18200-0x20000: padding
-	 */
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x08000, 0, 0,
-				&priv->ramro);
-	if (ret)
-		return ret;
-
-	/* 0x20000-0x21000: reserve for RAMFC
-	 * 0x21000-0x40000: padding and some unknown crap
-	 */
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x20000, 0,
-				 NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-struct nouveau_oclass *
-nv40_instmem_oclass = &(struct nouveau_instmem_impl) {
-	.base.handle = NV_SUBDEV(INSTMEM, 0x40),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv40_instmem_ctor,
-		.dtor = nv04_instmem_dtor,
-		.init = _nouveau_instmem_init,
-		.fini = _nouveau_instmem_fini,
-		.rd32 = nv40_instmem_rd32,
-		.wr32 = nv40_instmem_wr32,
-	},
-	.instobj = &nv04_instobj_oclass.base,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c
deleted file mode 100644
index 7cb3b098a08d..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/fb.h>
-#include <core/mm.h>
-
-#include "priv.h"
-
-struct nv50_instmem_priv {
-	struct nouveau_instmem base;
-	spinlock_t lock;
-	u64 addr;
-};
-
-struct nv50_instobj_priv {
-	struct nouveau_instobj base;
-	struct nouveau_mem *mem;
-};
-
-/******************************************************************************
- * instmem object implementation
- *****************************************************************************/
-
-static u32
-nv50_instobj_rd32(struct nouveau_object *object, u64 offset)
-{
-	struct nv50_instmem_priv *priv = (void *)object->engine;
-	struct nv50_instobj_priv *node = (void *)object;
-	unsigned long flags;
-	u64 base = (node->mem->offset + offset) & 0xffffff00000ULL;
-	u64 addr = (node->mem->offset + offset) & 0x000000fffffULL;
-	u32 data;
-
-	spin_lock_irqsave(&priv->lock, flags);
-	if (unlikely(priv->addr != base)) {
-		nv_wr32(priv, 0x001700, base >> 16);
-		priv->addr = base;
-	}
-	data = nv_rd32(priv, 0x700000 + addr);
-	spin_unlock_irqrestore(&priv->lock, flags);
-	return data;
-}
-
-static void
-nv50_instobj_wr32(struct nouveau_object *object, u64 offset, u32 data)
-{
-	struct nv50_instmem_priv *priv = (void *)object->engine;
-	struct nv50_instobj_priv *node = (void *)object;
-	unsigned long flags;
-	u64 base = (node->mem->offset + offset) & 0xffffff00000ULL;
-	u64 addr = (node->mem->offset + offset) & 0x000000fffffULL;
-
-	spin_lock_irqsave(&priv->lock, flags);
-	if (unlikely(priv->addr != base)) {
-		nv_wr32(priv, 0x001700, base >> 16);
-		priv->addr = base;
-	}
-	nv_wr32(priv, 0x700000 + addr, data);
-	spin_unlock_irqrestore(&priv->lock, flags);
-}
-
-static void
-nv50_instobj_dtor(struct nouveau_object *object)
-{
-	struct nv50_instobj_priv *node = (void *)object;
-	struct nouveau_fb *pfb = nouveau_fb(object);
-	pfb->ram->put(pfb, &node->mem);
-	nouveau_instobj_destroy(&node->base);
-}
-
-static int
-nv50_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 size,
-		  struct nouveau_object **pobject)
-{
-	struct nouveau_fb *pfb = nouveau_fb(parent);
-	struct nouveau_instobj_args *args = data;
-	struct nv50_instobj_priv *node;
-	int ret;
-
-	args->size  = max((args->size  + 4095) & ~4095, (u32)4096);
-	args->align = max((args->align + 4095) & ~4095, (u32)4096);
-
-	ret = nouveau_instobj_create(parent, engine, oclass, &node);
-	*pobject = nv_object(node);
-	if (ret)
-		return ret;
-
-	ret = pfb->ram->get(pfb, args->size, args->align, 0, 0x800, &node->mem);
-	if (ret)
-		return ret;
-
-	node->base.addr = node->mem->offset;
-	node->base.size = node->mem->size << 12;
-	node->mem->page_shift = 12;
-	return 0;
-}
-
-static struct nouveau_instobj_impl
-nv50_instobj_oclass = {
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_instobj_ctor,
-		.dtor = nv50_instobj_dtor,
-		.init = _nouveau_instobj_init,
-		.fini = _nouveau_instobj_fini,
-		.rd32 = nv50_instobj_rd32,
-		.wr32 = nv50_instobj_wr32,
-	},
-};
-
-/******************************************************************************
- * instmem subdev implementation
- *****************************************************************************/
-
-static int
-nv50_instmem_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv50_instmem_priv *priv = (void *)object;
-	priv->addr = ~0ULL;
-	return nouveau_instmem_fini(&priv->base, suspend);
-}
-
-static int
-nv50_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 size,
-		  struct nouveau_object **pobject)
-{
-	struct nv50_instmem_priv *priv;
-	int ret;
-
-	ret = nouveau_instmem_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	spin_lock_init(&priv->lock);
-	return 0;
-}
-
-struct nouveau_oclass *
-nv50_instmem_oclass = &(struct nouveau_instmem_impl) {
-	.base.handle = NV_SUBDEV(INSTMEM, 0x50),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_instmem_ctor,
-		.dtor = _nouveau_instmem_dtor,
-		.init = _nouveau_instmem_init,
-		.fini = nv50_instmem_fini,
-	},
-	.instobj = &nv50_instobj_oclass.base,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/priv.h b/drivers/gpu/drm/nouveau/core/subdev/instmem/priv.h
deleted file mode 100644
index 8d67dedc5bb2..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/priv.h
+++ /dev/null
@@ -1,56 +0,0 @@
-#ifndef __NVKM_INSTMEM_PRIV_H__
-#define __NVKM_INSTMEM_PRIV_H__
-
-#include <subdev/instmem.h>
-
-struct nouveau_instobj_impl {
-	struct nouveau_oclass base;
-};
-
-struct nouveau_instobj_args {
-	u32 size;
-	u32 align;
-};
-
-#define nouveau_instobj_create(p,e,o,d)                                        \
-	nouveau_instobj_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_instobj_destroy(p) ({                                          \
-	struct nouveau_instobj *iobj = (p);                                    \
-	_nouveau_instobj_dtor(nv_object(iobj));                                \
-})
-#define nouveau_instobj_init(p)                                                \
-	nouveau_object_init(&(p)->base)
-#define nouveau_instobj_fini(p,s)                                              \
-	nouveau_object_fini(&(p)->base, (s))
-
-int  nouveau_instobj_create_(struct nouveau_object *, struct nouveau_object *,
-			     struct nouveau_oclass *, int, void **);
-void _nouveau_instobj_dtor(struct nouveau_object *);
-#define _nouveau_instobj_init nouveau_object_init
-#define _nouveau_instobj_fini nouveau_object_fini
-
-struct nouveau_instmem_impl {
-	struct nouveau_oclass base;
-	struct nouveau_oclass *instobj;
-};
-
-#define nouveau_instmem_create(p,e,o,d)                                        \
-	nouveau_instmem_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_instmem_destroy(p)                                             \
-	nouveau_subdev_destroy(&(p)->base)
-#define nouveau_instmem_init(p) ({                                             \
-	struct nouveau_instmem *imem = (p);                                    \
-	_nouveau_instmem_init(nv_object(imem));                                \
-})
-#define nouveau_instmem_fini(p,s) ({                                           \
-	struct nouveau_instmem *imem = (p);                                    \
-	_nouveau_instmem_fini(nv_object(imem), (s));                           \
-})
-
-int nouveau_instmem_create_(struct nouveau_object *, struct nouveau_object *,
-			    struct nouveau_oclass *, int, void **);
-#define _nouveau_instmem_dtor _nouveau_subdev_dtor
-int _nouveau_instmem_init(struct nouveau_object *);
-int _nouveau_instmem_fini(struct nouveau_object *, bool);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c
deleted file mode 100644
index 7fa331516f84..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "priv.h"
-
-static int
-nvkm_ltc_tags_alloc(struct nouveau_ltc *ltc, u32 n,
-		    struct nouveau_mm_node **pnode)
-{
-	struct nvkm_ltc_priv *priv = (void *)ltc;
-	int ret;
-
-	ret = nouveau_mm_head(&priv->tags, 0, 1, n, n, 1, pnode);
-	if (ret)
-		*pnode = NULL;
-
-	return ret;
-}
-
-static void
-nvkm_ltc_tags_free(struct nouveau_ltc *ltc, struct nouveau_mm_node **pnode)
-{
-	struct nvkm_ltc_priv *priv = (void *)ltc;
-	nouveau_mm_free(&priv->tags, pnode);
-}
-
-static void
-nvkm_ltc_tags_clear(struct nouveau_ltc *ltc, u32 first, u32 count)
-{
-	const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc);
-	struct nvkm_ltc_priv *priv = (void *)ltc;
-	const u32 limit = first + count - 1;
-
-	BUG_ON((first > limit) || (limit >= priv->num_tags));
-
-	impl->cbc_clear(priv, first, limit);
-	impl->cbc_wait(priv);
-}
-
-static int
-nvkm_ltc_zbc_color_get(struct nouveau_ltc *ltc, int index, const u32 color[4])
-{
-	const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc);
-	struct nvkm_ltc_priv *priv = (void *)ltc;
-	memcpy(priv->zbc_color[index], color, sizeof(priv->zbc_color[index]));
-	impl->zbc_clear_color(priv, index, color);
-	return index;
-}
-
-static int
-nvkm_ltc_zbc_depth_get(struct nouveau_ltc *ltc, int index, const u32 depth)
-{
-	const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc);
-	struct nvkm_ltc_priv *priv = (void *)ltc;
-	priv->zbc_depth[index] = depth;
-	impl->zbc_clear_depth(priv, index, depth);
-	return index;
-}
-
-int
-_nvkm_ltc_init(struct nouveau_object *object)
-{
-	const struct nvkm_ltc_impl *impl = (void *)nv_oclass(object);
-	struct nvkm_ltc_priv *priv = (void *)object;
-	int ret, i;
-
-	ret = nouveau_subdev_init(&priv->base.base);
-	if (ret)
-		return ret;
-
-	for (i = priv->base.zbc_min; i <= priv->base.zbc_max; i++) {
-		impl->zbc_clear_color(priv, i, priv->zbc_color[i]);
-		impl->zbc_clear_depth(priv, i, priv->zbc_depth[i]);
-	}
-
-	return 0;
-}
-
-int
-nvkm_ltc_create_(struct nouveau_object *parent, struct nouveau_object *engine,
-		 struct nouveau_oclass *oclass, int length, void **pobject)
-{
-	const struct nvkm_ltc_impl *impl = (void *)oclass;
-	struct nvkm_ltc_priv *priv;
-	int ret;
-
-	ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PLTCG",
-				     "l2c", length, pobject);
-	priv = *pobject;
-	if (ret)
-		return ret;
-
-	memset(priv->zbc_color, 0x00, sizeof(priv->zbc_color));
-	memset(priv->zbc_depth, 0x00, sizeof(priv->zbc_depth));
-
-	priv->base.base.intr = impl->intr;
-	priv->base.tags_alloc = nvkm_ltc_tags_alloc;
-	priv->base.tags_free = nvkm_ltc_tags_free;
-	priv->base.tags_clear = nvkm_ltc_tags_clear;
-	priv->base.zbc_min = 1; /* reserve 0 for disabled */
-	priv->base.zbc_max = min(impl->zbc, NOUVEAU_LTC_MAX_ZBC_CNT) - 1;
-	priv->base.zbc_color_get = nvkm_ltc_zbc_color_get;
-	priv->base.zbc_depth_get = nvkm_ltc_zbc_depth_get;
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c
deleted file mode 100644
index 2db0977284f8..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/fb.h>
-#include <subdev/timer.h>
-
-#include "priv.h"
-
-void
-gf100_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit)
-{
-	nv_wr32(priv, 0x17e8cc, start);
-	nv_wr32(priv, 0x17e8d0, limit);
-	nv_wr32(priv, 0x17e8c8, 0x00000004);
-}
-
-void
-gf100_ltc_cbc_wait(struct nvkm_ltc_priv *priv)
-{
-	int c, s;
-	for (c = 0; c < priv->ltc_nr; c++) {
-		for (s = 0; s < priv->lts_nr; s++)
-			nv_wait(priv, 0x1410c8 + c * 0x2000 + s * 0x400, ~0, 0);
-	}
-}
-
-void
-gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *priv, int i, const u32 color[4])
-{
-	nv_mask(priv, 0x17ea44, 0x0000000f, i);
-	nv_wr32(priv, 0x17ea48, color[0]);
-	nv_wr32(priv, 0x17ea4c, color[1]);
-	nv_wr32(priv, 0x17ea50, color[2]);
-	nv_wr32(priv, 0x17ea54, color[3]);
-}
-
-void
-gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *priv, int i, const u32 depth)
-{
-	nv_mask(priv, 0x17ea44, 0x0000000f, i);
-	nv_wr32(priv, 0x17ea58, depth);
-}
-
-static const struct nouveau_bitfield
-gf100_ltc_lts_intr_name[] = {
-	{ 0x00000001, "IDLE_ERROR_IQ" },
-	{ 0x00000002, "IDLE_ERROR_CBC" },
-	{ 0x00000004, "IDLE_ERROR_TSTG" },
-	{ 0x00000008, "IDLE_ERROR_DSTG" },
-	{ 0x00000010, "EVICTED_CB" },
-	{ 0x00000020, "ILLEGAL_COMPSTAT" },
-	{ 0x00000040, "BLOCKLINEAR_CB" },
-	{ 0x00000100, "ECC_SEC_ERROR" },
-	{ 0x00000200, "ECC_DED_ERROR" },
-	{ 0x00000400, "DEBUG" },
-	{ 0x00000800, "ATOMIC_TO_Z" },
-	{ 0x00001000, "ILLEGAL_ATOMIC" },
-	{ 0x00002000, "BLKACTIVITY_ERR" },
-	{}
-};
-
-static void
-gf100_ltc_lts_intr(struct nvkm_ltc_priv *priv, int ltc, int lts)
-{
-	u32 base = 0x141000 + (ltc * 0x2000) + (lts * 0x400);
-	u32 intr = nv_rd32(priv, base + 0x020);
-	u32 stat = intr & 0x0000ffff;
-
-	if (stat) {
-		nv_info(priv, "LTC%d_LTS%d:", ltc, lts);
-		nouveau_bitfield_print(gf100_ltc_lts_intr_name, stat);
-		pr_cont("\n");
-	}
-
-	nv_wr32(priv, base + 0x020, intr);
-}
-
-void
-gf100_ltc_intr(struct nouveau_subdev *subdev)
-{
-	struct nvkm_ltc_priv *priv = (void *)subdev;
-	u32 mask;
-
-	mask = nv_rd32(priv, 0x00017c);
-	while (mask) {
-		u32 lts, ltc = __ffs(mask);
-		for (lts = 0; lts < priv->lts_nr; lts++)
-			gf100_ltc_lts_intr(priv, ltc, lts);
-		mask &= ~(1 << ltc);
-	}
-}
-
-static int
-gf100_ltc_init(struct nouveau_object *object)
-{
-	struct nvkm_ltc_priv *priv = (void *)object;
-	u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001);
-	int ret;
-
-	ret = nvkm_ltc_init(priv);
-	if (ret)
-		return ret;
-
-	nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
-	nv_wr32(priv, 0x17e8d8, priv->ltc_nr);
-	nv_wr32(priv, 0x17e8d4, priv->tag_base);
-	nv_mask(priv, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
-	return 0;
-}
-
-void
-gf100_ltc_dtor(struct nouveau_object *object)
-{
-	struct nouveau_fb *pfb = nouveau_fb(object);
-	struct nvkm_ltc_priv *priv = (void *)object;
-
-	nouveau_mm_fini(&priv->tags);
-	nouveau_mm_free(&pfb->vram, &priv->tag_ram);
-
-	nvkm_ltc_destroy(priv);
-}
-
-/* TODO: Figure out tag memory details and drop the over-cautious allocation.
- */
-int
-gf100_ltc_init_tag_ram(struct nouveau_fb *pfb, struct nvkm_ltc_priv *priv)
-{
-	u32 tag_size, tag_margin, tag_align;
-	int ret;
-
-	/* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */
-	priv->num_tags = (pfb->ram->size >> 17) / 4;
-	if (priv->num_tags > (1 << 17))
-		priv->num_tags = 1 << 17; /* we have 17 bits in PTE */
-	priv->num_tags = (priv->num_tags + 63) & ~63; /* round up to 64 */
-
-	tag_align = priv->ltc_nr * 0x800;
-	tag_margin = (tag_align < 0x6000) ? 0x6000 : tag_align;
-
-	/* 4 part 4 sub: 0x2000 bytes for 56 tags */
-	/* 3 part 4 sub: 0x6000 bytes for 168 tags */
-	/*
-	 * About 147 bytes per tag. Let's be safe and allocate x2, which makes
-	 * 0x4980 bytes for 64 tags, and round up to 0x6000 bytes for 64 tags.
-	 *
-	 * For 4 GiB of memory we'll have 8192 tags which makes 3 MiB, < 0.1 %.
-	 */
-	tag_size  = (priv->num_tags / 64) * 0x6000 + tag_margin;
-	tag_size += tag_align;
-	tag_size  = (tag_size + 0xfff) >> 12; /* round up */
-
-	ret = nouveau_mm_tail(&pfb->vram, 1, 1, tag_size, tag_size, 1,
-	                      &priv->tag_ram);
-	if (ret) {
-		priv->num_tags = 0;
-	} else {
-		u64 tag_base = ((u64)priv->tag_ram->offset << 12) + tag_margin;
-
-		tag_base += tag_align - 1;
-		ret = do_div(tag_base, tag_align);
-
-		priv->tag_base = tag_base;
-	}
-
-	ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1);
-	return ret;
-}
-
-int
-gf100_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nouveau_fb *pfb = nouveau_fb(parent);
-	struct nvkm_ltc_priv *priv;
-	u32 parts, mask;
-	int ret, i;
-
-	ret = nvkm_ltc_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	parts = nv_rd32(priv, 0x022438);
-	mask = nv_rd32(priv, 0x022554);
-	for (i = 0; i < parts; i++) {
-		if (!(mask & (1 << i)))
-			priv->ltc_nr++;
-	}
-	priv->lts_nr = nv_rd32(priv, 0x17e8dc) >> 28;
-
-	ret = gf100_ltc_init_tag_ram(pfb, priv);
-	if (ret)
-		return ret;
-
-	nv_subdev(priv)->intr = gf100_ltc_intr;
-	return 0;
-}
-
-struct nouveau_oclass *
-gf100_ltc_oclass = &(struct nvkm_ltc_impl) {
-	.base.handle = NV_SUBDEV(LTC, 0xc0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = gf100_ltc_ctor,
-		.dtor = gf100_ltc_dtor,
-		.init = gf100_ltc_init,
-		.fini = _nvkm_ltc_fini,
-	},
-	.intr = gf100_ltc_intr,
-	.cbc_clear = gf100_ltc_cbc_clear,
-	.cbc_wait = gf100_ltc_cbc_wait,
-	.zbc = 16,
-	.zbc_clear_color = gf100_ltc_zbc_clear_color,
-	.zbc_clear_depth = gf100_ltc_zbc_clear_depth,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c
deleted file mode 100644
index b39b5d0eb8f9..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-
-static int
-gk104_ltc_init(struct nouveau_object *object)
-{
-	struct nvkm_ltc_priv *priv = (void *)object;
-	u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001);
-	int ret;
-
-	ret = nvkm_ltc_init(priv);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x17e8d8, priv->ltc_nr);
-	nv_wr32(priv, 0x17e000, priv->ltc_nr);
-	nv_wr32(priv, 0x17e8d4, priv->tag_base);
-	nv_mask(priv, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
-	return 0;
-}
-
-struct nouveau_oclass *
-gk104_ltc_oclass = &(struct nvkm_ltc_impl) {
-	.base.handle = NV_SUBDEV(LTC, 0xe4),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = gf100_ltc_ctor,
-		.dtor = gf100_ltc_dtor,
-		.init = gk104_ltc_init,
-		.fini = _nvkm_ltc_fini,
-	},
-	.intr = gf100_ltc_intr,
-	.cbc_clear = gf100_ltc_cbc_clear,
-	.cbc_wait = gf100_ltc_cbc_wait,
-	.zbc = 16,
-	.zbc_clear_color = gf100_ltc_zbc_clear_color,
-	.zbc_clear_depth = gf100_ltc_zbc_clear_depth,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c
deleted file mode 100644
index 89fc4238f50c..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * Copyright 2014 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/fb.h>
-#include <subdev/timer.h>
-
-#include "priv.h"
-
-static void
-gm107_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit)
-{
-	nv_wr32(priv, 0x17e270, start);
-	nv_wr32(priv, 0x17e274, limit);
-	nv_wr32(priv, 0x17e26c, 0x00000004);
-}
-
-static void
-gm107_ltc_cbc_wait(struct nvkm_ltc_priv *priv)
-{
-	int c, s;
-	for (c = 0; c < priv->ltc_nr; c++) {
-		for (s = 0; s < priv->lts_nr; s++)
-			nv_wait(priv, 0x14046c + c * 0x2000 + s * 0x200, ~0, 0);
-	}
-}
-
-static void
-gm107_ltc_zbc_clear_color(struct nvkm_ltc_priv *priv, int i, const u32 color[4])
-{
-	nv_mask(priv, 0x17e338, 0x0000000f, i);
-	nv_wr32(priv, 0x17e33c, color[0]);
-	nv_wr32(priv, 0x17e340, color[1]);
-	nv_wr32(priv, 0x17e344, color[2]);
-	nv_wr32(priv, 0x17e348, color[3]);
-}
-
-static void
-gm107_ltc_zbc_clear_depth(struct nvkm_ltc_priv *priv, int i, const u32 depth)
-{
-	nv_mask(priv, 0x17e338, 0x0000000f, i);
-	nv_wr32(priv, 0x17e34c, depth);
-}
-
-static void
-gm107_ltc_lts_isr(struct nvkm_ltc_priv *priv, int ltc, int lts)
-{
-	u32 base = 0x140000 + (ltc * 0x2000) + (lts * 0x400);
-	u32 stat = nv_rd32(priv, base + 0x00c);
-
-	if (stat) {
-		nv_info(priv, "LTC%d_LTS%d: 0x%08x\n", ltc, lts, stat);
-		nv_wr32(priv, base + 0x00c, stat);
-	}
-}
-
-static void
-gm107_ltc_intr(struct nouveau_subdev *subdev)
-{
-	struct nvkm_ltc_priv *priv = (void *)subdev;
-	u32 mask;
-
-	mask = nv_rd32(priv, 0x00017c);
-	while (mask) {
-		u32 lts, ltc = __ffs(mask);
-		for (lts = 0; lts < priv->lts_nr; lts++)
-			gm107_ltc_lts_isr(priv, ltc, lts);
-		mask &= ~(1 << ltc);
-	}
-}
-
-static int
-gm107_ltc_init(struct nouveau_object *object)
-{
-	struct nvkm_ltc_priv *priv = (void *)object;
-	u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001);
-	int ret;
-
-	ret = nvkm_ltc_init(priv);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x17e27c, priv->ltc_nr);
-	nv_wr32(priv, 0x17e278, priv->tag_base);
-	nv_mask(priv, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
-	return 0;
-}
-
-static int
-gm107_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nouveau_fb *pfb = nouveau_fb(parent);
-	struct nvkm_ltc_priv *priv;
-	u32 parts, mask;
-	int ret, i;
-
-	ret = nvkm_ltc_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	parts = nv_rd32(priv, 0x022438);
-	mask = nv_rd32(priv, 0x021c14);
-	for (i = 0; i < parts; i++) {
-		if (!(mask & (1 << i)))
-			priv->ltc_nr++;
-	}
-	priv->lts_nr = nv_rd32(priv, 0x17e280) >> 28;
-
-	ret = gf100_ltc_init_tag_ram(pfb, priv);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-struct nouveau_oclass *
-gm107_ltc_oclass = &(struct nvkm_ltc_impl) {
-	.base.handle = NV_SUBDEV(LTC, 0xff),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = gm107_ltc_ctor,
-		.dtor = gf100_ltc_dtor,
-		.init = gm107_ltc_init,
-		.fini = _nvkm_ltc_fini,
-	},
-	.intr = gm107_ltc_intr,
-	.cbc_clear = gm107_ltc_cbc_clear,
-	.cbc_wait = gm107_ltc_cbc_wait,
-	.zbc = 16,
-	.zbc_clear_color = gm107_ltc_zbc_clear_color,
-	.zbc_clear_depth = gm107_ltc_zbc_clear_depth,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h b/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h
deleted file mode 100644
index 41f179d93da6..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h
+++ /dev/null
@@ -1,71 +0,0 @@
-#ifndef __NVKM_LTC_PRIV_H__
-#define __NVKM_LTC_PRIV_H__
-
-#include <subdev/ltc.h>
-#include <subdev/fb.h>
-
-#include <core/enum.h>
-
-struct nvkm_ltc_priv {
-	struct nouveau_ltc base;
-	u32 ltc_nr;
-	u32 lts_nr;
-
-	u32 num_tags;
-	u32 tag_base;
-	struct nouveau_mm tags;
-	struct nouveau_mm_node *tag_ram;
-
-	u32 zbc_color[NOUVEAU_LTC_MAX_ZBC_CNT][4];
-	u32 zbc_depth[NOUVEAU_LTC_MAX_ZBC_CNT];
-};
-
-#define nvkm_ltc_create(p,e,o,d)                                               \
-	nvkm_ltc_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nvkm_ltc_destroy(p) ({                                                 \
-	struct nvkm_ltc_priv *_priv = (p);                                     \
-	_nvkm_ltc_dtor(nv_object(_priv));                                      \
-})
-#define nvkm_ltc_init(p) ({                                                    \
-	struct nvkm_ltc_priv *_priv = (p);                                     \
-	_nvkm_ltc_init(nv_object(_priv));                                      \
-})
-#define nvkm_ltc_fini(p,s) ({                                                  \
-	struct nvkm_ltc_priv *_priv = (p);                                     \
-	_nvkm_ltc_fini(nv_object(_priv), (s));                                 \
-})
-
-int  nvkm_ltc_create_(struct nouveau_object *, struct nouveau_object *,
-		      struct nouveau_oclass *, int, void **);
-
-#define _nvkm_ltc_dtor _nouveau_subdev_dtor
-int _nvkm_ltc_init(struct nouveau_object *);
-#define _nvkm_ltc_fini _nouveau_subdev_fini
-
-int  gf100_ltc_ctor(struct nouveau_object *, struct nouveau_object *,
-		    struct nouveau_oclass *, void *, u32,
-		    struct nouveau_object **);
-void gf100_ltc_dtor(struct nouveau_object *);
-int  gf100_ltc_init_tag_ram(struct nouveau_fb *, struct nvkm_ltc_priv *);
-int  gf100_ltc_tags_alloc(struct nouveau_ltc *, u32, struct nouveau_mm_node **);
-void gf100_ltc_tags_free(struct nouveau_ltc *, struct nouveau_mm_node **);
-
-struct nvkm_ltc_impl {
-	struct nouveau_oclass base;
-	void (*intr)(struct nouveau_subdev *);
-
-	void (*cbc_clear)(struct nvkm_ltc_priv *, u32 start, u32 limit);
-	void (*cbc_wait)(struct nvkm_ltc_priv *);
-
-	int zbc;
-	void (*zbc_clear_color)(struct nvkm_ltc_priv *, int, const u32[4]);
-	void (*zbc_clear_depth)(struct nvkm_ltc_priv *, int, const u32);
-};
-
-void gf100_ltc_intr(struct nouveau_subdev *);
-void gf100_ltc_cbc_clear(struct nvkm_ltc_priv *, u32, u32);
-void gf100_ltc_cbc_wait(struct nvkm_ltc_priv *);
-void gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *, int, const u32[4]);
-void gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *, int, const u32);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/base.c b/drivers/gpu/drm/nouveau/core/subdev/mc/base.c
deleted file mode 100644
index ca7cee3a314a..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/base.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-#include <core/option.h>
-
-static inline void
-nouveau_mc_unk260(struct nouveau_mc *pmc, u32 data)
-{
-	const struct nouveau_mc_oclass *impl = (void *)nv_oclass(pmc);
-	if (impl->unk260)
-		impl->unk260(pmc, data);
-}
-
-static inline u32
-nouveau_mc_intr_mask(struct nouveau_mc *pmc)
-{
-	u32 intr = nv_rd32(pmc, 0x000100);
-	if (intr == 0xffffffff) /* likely fallen off the bus */
-		intr = 0x00000000;
-	return intr;
-}
-
-static irqreturn_t
-nouveau_mc_intr(int irq, void *arg)
-{
-	struct nouveau_mc *pmc = arg;
-	const struct nouveau_mc_oclass *oclass = (void *)nv_object(pmc)->oclass;
-	const struct nouveau_mc_intr *map = oclass->intr;
-	struct nouveau_subdev *unit;
-	u32 intr;
-
-	nv_wr32(pmc, 0x000140, 0x00000000);
-	nv_rd32(pmc, 0x000140);
-	intr = nouveau_mc_intr_mask(pmc);
-	if (pmc->use_msi)
-		oclass->msi_rearm(pmc);
-
-	if (intr) {
-		u32 stat = intr = nouveau_mc_intr_mask(pmc);
-		while (map->stat) {
-			if (intr & map->stat) {
-				unit = nouveau_subdev(pmc, map->unit);
-				if (unit && unit->intr)
-					unit->intr(unit);
-				stat &= ~map->stat;
-			}
-			map++;
-		}
-
-		if (stat)
-			nv_error(pmc, "unknown intr 0x%08x\n", stat);
-	}
-
-	nv_wr32(pmc, 0x000140, 0x00000001);
-	return intr ? IRQ_HANDLED : IRQ_NONE;
-}
-
-int
-_nouveau_mc_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nouveau_mc *pmc = (void *)object;
-	nv_wr32(pmc, 0x000140, 0x00000000);
-	return nouveau_subdev_fini(&pmc->base, suspend);
-}
-
-int
-_nouveau_mc_init(struct nouveau_object *object)
-{
-	struct nouveau_mc *pmc = (void *)object;
-	int ret = nouveau_subdev_init(&pmc->base);
-	if (ret)
-		return ret;
-	nv_wr32(pmc, 0x000140, 0x00000001);
-	return 0;
-}
-
-void
-_nouveau_mc_dtor(struct nouveau_object *object)
-{
-	struct nouveau_device *device = nv_device(object);
-	struct nouveau_mc *pmc = (void *)object;
-	free_irq(pmc->irq, pmc);
-	if (pmc->use_msi)
-		pci_disable_msi(device->pdev);
-	nouveau_subdev_destroy(&pmc->base);
-}
-
-int
-nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine,
-		   struct nouveau_oclass *bclass, int length, void **pobject)
-{
-	const struct nouveau_mc_oclass *oclass = (void *)bclass;
-	struct nouveau_device *device = nv_device(parent);
-	struct nouveau_mc *pmc;
-	int ret;
-
-	ret = nouveau_subdev_create_(parent, engine, bclass, 0, "PMC",
-				     "master", length, pobject);
-	pmc = *pobject;
-	if (ret)
-		return ret;
-
-	pmc->unk260 = nouveau_mc_unk260;
-
-	if (nv_device_is_pci(device))
-		switch (device->pdev->device & 0x0ff0) {
-		case 0x00f0:
-		case 0x02e0:
-			/* BR02? NFI how these would be handled yet exactly */
-			break;
-		default:
-			switch (device->chipset) {
-			case 0xaa:
-				/* reported broken, nv also disable it */
-				break;
-			default:
-				pmc->use_msi = true;
-				break;
-		}
-
-		pmc->use_msi = nouveau_boolopt(device->cfgopt, "NvMSI",
-					       pmc->use_msi);
-
-		if (pmc->use_msi && oclass->msi_rearm) {
-			pmc->use_msi = pci_enable_msi(device->pdev) == 0;
-			if (pmc->use_msi) {
-				nv_info(pmc, "MSI interrupts enabled\n");
-				oclass->msi_rearm(pmc);
-			}
-		} else {
-			pmc->use_msi = false;
-		}
-	}
-
-	ret = nv_device_get_irq(device, true);
-	if (ret < 0)
-		return ret;
-	pmc->irq = ret;
-
-	ret = request_irq(pmc->irq, nouveau_mc_intr, IRQF_SHARED, "nouveau",
-			  pmc);
-
-	if (ret < 0)
-		return ret;
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/mc/gk20a.c
deleted file mode 100644
index b8d6cb435d0a..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/gk20a.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv04.h"
-
-struct nouveau_oclass *
-gk20a_mc_oclass = &(struct nouveau_mc_oclass) {
-	.base.handle = NV_SUBDEV(MC, 0xea),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_mc_ctor,
-		.dtor = _nouveau_mc_dtor,
-		.init = nv50_mc_init,
-		.fini = _nouveau_mc_fini,
-	},
-	.intr = nvc0_mc_intr,
-	.msi_rearm = nv40_mc_msi_rearm,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c
deleted file mode 100644
index 2d787e4dfefa..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv04.h"
-
-const struct nouveau_mc_intr
-nv04_mc_intr[] = {
-	{ 0x00000001, NVDEV_ENGINE_MPEG },	/* NV17- MPEG/ME */
-	{ 0x00000100, NVDEV_ENGINE_FIFO },
-	{ 0x00001000, NVDEV_ENGINE_GR },
-	{ 0x00010000, NVDEV_ENGINE_DISP },
-	{ 0x00020000, NVDEV_ENGINE_VP },	/* NV40- */
-	{ 0x00100000, NVDEV_SUBDEV_TIMER },
-	{ 0x01000000, NVDEV_ENGINE_DISP },	/* NV04- PCRTC0 */
-	{ 0x02000000, NVDEV_ENGINE_DISP },	/* NV11- PCRTC1 */
-	{ 0x10000000, NVDEV_SUBDEV_BUS },
-	{ 0x80000000, NVDEV_ENGINE_SW },
-	{}
-};
-
-int
-nv04_mc_init(struct nouveau_object *object)
-{
-	struct nv04_mc_priv *priv = (void *)object;
-
-	nv_wr32(priv, 0x000200, 0xffffffff); /* everything enabled */
-	nv_wr32(priv, 0x001850, 0x00000001); /* disable rom access */
-
-	return nouveau_mc_init(&priv->base);
-}
-
-int
-nv04_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	     struct nouveau_oclass *oclass, void *data, u32 size,
-	     struct nouveau_object **pobject)
-{
-	struct nv04_mc_priv *priv;
-	int ret;
-
-	ret = nouveau_mc_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-struct nouveau_oclass *
-nv04_mc_oclass = &(struct nouveau_mc_oclass) {
-	.base.handle = NV_SUBDEV(MC, 0x04),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_mc_ctor,
-		.dtor = _nouveau_mc_dtor,
-		.init = nv04_mc_init,
-		.fini = _nouveau_mc_fini,
-	},
-	.intr = nv04_mc_intr,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h
deleted file mode 100644
index 4d9ea46c47c2..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef __NVKM_MC_NV04_H__
-#define __NVKM_MC_NV04_H__
-
-#include "priv.h"
-
-struct nv04_mc_priv {
-	struct nouveau_mc base;
-};
-
-int  nv04_mc_ctor(struct nouveau_object *, struct nouveau_object *,
-		  struct nouveau_oclass *, void *, u32,
-		  struct nouveau_object **);
-
-extern const struct nouveau_mc_intr nv04_mc_intr[];
-int  nv04_mc_init(struct nouveau_object *);
-void nv40_mc_msi_rearm(struct nouveau_mc *);
-int  nv44_mc_init(struct nouveau_object *object);
-int  nv50_mc_init(struct nouveau_object *);
-extern const struct nouveau_mc_intr nv50_mc_intr[];
-extern const struct nouveau_mc_intr nvc0_mc_intr[];
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv40.c
deleted file mode 100644
index 5b1faecfed2d..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv40.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv04.h"
-
-void
-nv40_mc_msi_rearm(struct nouveau_mc *pmc)
-{
-	struct nv04_mc_priv *priv = (void *)pmc;
-	nv_wr08(priv, 0x088068, 0xff);
-}
-
-struct nouveau_oclass *
-nv40_mc_oclass = &(struct nouveau_mc_oclass) {
-	.base.handle = NV_SUBDEV(MC, 0x40),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_mc_ctor,
-		.dtor = _nouveau_mc_dtor,
-		.init = nv04_mc_init,
-		.fini = _nouveau_mc_fini,
-	},
-	.intr = nv04_mc_intr,
-	.msi_rearm = nv40_mc_msi_rearm,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c
deleted file mode 100644
index cc4d0d2d886e..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv04.h"
-
-int
-nv44_mc_init(struct nouveau_object *object)
-{
-	struct nv04_mc_priv *priv = (void *)object;
-	u32 tmp = nv_rd32(priv, 0x10020c);
-
-	nv_wr32(priv, 0x000200, 0xffffffff); /* everything enabled */
-
-	nv_wr32(priv, 0x001700, tmp);
-	nv_wr32(priv, 0x001704, 0);
-	nv_wr32(priv, 0x001708, 0);
-	nv_wr32(priv, 0x00170c, tmp);
-
-	return nouveau_mc_init(&priv->base);
-}
-
-struct nouveau_oclass *
-nv44_mc_oclass = &(struct nouveau_mc_oclass) {
-	.base.handle = NV_SUBDEV(MC, 0x44),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_mc_ctor,
-		.dtor = _nouveau_mc_dtor,
-		.init = nv44_mc_init,
-		.fini = _nouveau_mc_fini,
-	},
-	.intr = nv04_mc_intr,
-	.msi_rearm = nv40_mc_msi_rearm,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c
deleted file mode 100644
index 165401c4045c..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright 2014 Ilia Mirkin
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ilia Mirkin
- */
-
-#include "nv04.h"
-
-struct nouveau_oclass *
-nv4c_mc_oclass = &(struct nouveau_mc_oclass) {
-	.base.handle = NV_SUBDEV(MC, 0x4c),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_mc_ctor,
-		.dtor = _nouveau_mc_dtor,
-		.init = nv44_mc_init,
-		.fini = _nouveau_mc_fini,
-	},
-	.intr = nv04_mc_intr,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c
deleted file mode 100644
index 9ca93e2718f7..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv04.h"
-
-const struct nouveau_mc_intr
-nv50_mc_intr[] = {
-	{ 0x04000000, NVDEV_ENGINE_DISP },  /* DISP before FIFO, so pageflip-timestamping works! */
-	{ 0x00000001, NVDEV_ENGINE_MPEG },
-	{ 0x00000100, NVDEV_ENGINE_FIFO },
-	{ 0x00001000, NVDEV_ENGINE_GR },
-	{ 0x00004000, NVDEV_ENGINE_CRYPT },	/* NV84- */
-	{ 0x00008000, NVDEV_ENGINE_BSP },	/* NV84- */
-	{ 0x00020000, NVDEV_ENGINE_VP },	/* NV84- */
-	{ 0x00100000, NVDEV_SUBDEV_TIMER },
-	{ 0x00200000, NVDEV_SUBDEV_GPIO },	/* PMGR->GPIO */
-	{ 0x00200000, NVDEV_SUBDEV_I2C }, 	/* PMGR->I2C/AUX */
-	{ 0x10000000, NVDEV_SUBDEV_BUS },
-	{ 0x80000000, NVDEV_ENGINE_SW },
-	{ 0x0002d101, NVDEV_SUBDEV_FB },
-	{},
-};
-
-static void
-nv50_mc_msi_rearm(struct nouveau_mc *pmc)
-{
-	struct nouveau_device *device = nv_device(pmc);
-	pci_write_config_byte(device->pdev, 0x68, 0xff);
-}
-
-int
-nv50_mc_init(struct nouveau_object *object)
-{
-	struct nv04_mc_priv *priv = (void *)object;
-	nv_wr32(priv, 0x000200, 0xffffffff); /* everything on */
-	return nouveau_mc_init(&priv->base);
-}
-
-struct nouveau_oclass *
-nv50_mc_oclass = &(struct nouveau_mc_oclass) {
-	.base.handle = NV_SUBDEV(MC, 0x50),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_mc_ctor,
-		.dtor = _nouveau_mc_dtor,
-		.init = nv50_mc_init,
-		.fini = _nouveau_mc_fini,
-	},
-	.intr = nv50_mc_intr,
-	.msi_rearm = nv50_mc_msi_rearm,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv94.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv94.c
deleted file mode 100644
index 5f4541105e73..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv94.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv04.h"
-
-struct nouveau_oclass *
-nv94_mc_oclass = &(struct nouveau_mc_oclass) {
-	.base.handle = NV_SUBDEV(MC, 0x94),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_mc_ctor,
-		.dtor = _nouveau_mc_dtor,
-		.init = nv50_mc_init,
-		.fini = _nouveau_mc_fini,
-	},
-	.intr = nv50_mc_intr,
-	.msi_rearm = nv40_mc_msi_rearm,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c
deleted file mode 100644
index 3c76d9038f38..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv04.h"
-
-static const struct nouveau_mc_intr
-nv98_mc_intr[] = {
-	{ 0x04000000, NVDEV_ENGINE_DISP },  /* DISP first, so pageflip timestamps work */
-	{ 0x00000001, NVDEV_ENGINE_PPP },
-	{ 0x00000100, NVDEV_ENGINE_FIFO },
-	{ 0x00001000, NVDEV_ENGINE_GR },
-	{ 0x00004000, NVDEV_ENGINE_CRYPT },	/* NV84:NVA3 */
-	{ 0x00008000, NVDEV_ENGINE_BSP },
-	{ 0x00020000, NVDEV_ENGINE_VP },
-	{ 0x00040000, NVDEV_SUBDEV_PWR },	/* NVA3:NVC0 */
-	{ 0x00080000, NVDEV_SUBDEV_THERM },	/* NVA3:NVC0 */
-	{ 0x00100000, NVDEV_SUBDEV_TIMER },
-	{ 0x00200000, NVDEV_SUBDEV_GPIO },	/* PMGR->GPIO */
-	{ 0x00200000, NVDEV_SUBDEV_I2C }, 	/* PMGR->I2C/AUX */
-	{ 0x00400000, NVDEV_ENGINE_COPY0 },	/* NVA3-     */
-	{ 0x10000000, NVDEV_SUBDEV_BUS },
-	{ 0x80000000, NVDEV_ENGINE_SW },
-	{ 0x0042d101, NVDEV_SUBDEV_FB },
-	{},
-};
-
-struct nouveau_oclass *
-nv98_mc_oclass = &(struct nouveau_mc_oclass) {
-	.base.handle = NV_SUBDEV(MC, 0x98),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_mc_ctor,
-		.dtor = _nouveau_mc_dtor,
-		.init = nv50_mc_init,
-		.fini = _nouveau_mc_fini,
-	},
-	.intr = nv98_mc_intr,
-	.msi_rearm = nv40_mc_msi_rearm,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
deleted file mode 100644
index 15d41dc176ff..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv04.h"
-
-const struct nouveau_mc_intr
-nvc0_mc_intr[] = {
-	{ 0x04000000, NVDEV_ENGINE_DISP },  /* DISP first, so pageflip timestamps work. */
-	{ 0x00000001, NVDEV_ENGINE_PPP },
-	{ 0x00000020, NVDEV_ENGINE_COPY0 },
-	{ 0x00000040, NVDEV_ENGINE_COPY1 },
-	{ 0x00000080, NVDEV_ENGINE_COPY2 },
-	{ 0x00000100, NVDEV_ENGINE_FIFO },
-	{ 0x00001000, NVDEV_ENGINE_GR },
-	{ 0x00002000, NVDEV_SUBDEV_FB },
-	{ 0x00008000, NVDEV_ENGINE_BSP },
-	{ 0x00040000, NVDEV_SUBDEV_THERM },
-	{ 0x00020000, NVDEV_ENGINE_VP },
-	{ 0x00100000, NVDEV_SUBDEV_TIMER },
-	{ 0x00200000, NVDEV_SUBDEV_GPIO },	/* PMGR->GPIO */
-	{ 0x00200000, NVDEV_SUBDEV_I2C },	/* PMGR->I2C/AUX */
-	{ 0x01000000, NVDEV_SUBDEV_PWR },
-	{ 0x02000000, NVDEV_SUBDEV_LTC },
-	{ 0x08000000, NVDEV_SUBDEV_FB },
-	{ 0x10000000, NVDEV_SUBDEV_BUS },
-	{ 0x40000000, NVDEV_SUBDEV_IBUS },
-	{ 0x80000000, NVDEV_ENGINE_SW },
-	{},
-};
-
-static void
-nvc0_mc_msi_rearm(struct nouveau_mc *pmc)
-{
-	struct nv04_mc_priv *priv = (void *)pmc;
-	nv_wr32(priv, 0x088704, 0x00000000);
-}
-
-void
-nvc0_mc_unk260(struct nouveau_mc *pmc, u32 data)
-{
-	nv_wr32(pmc, 0x000260, data);
-}
-
-struct nouveau_oclass *
-nvc0_mc_oclass = &(struct nouveau_mc_oclass) {
-	.base.handle = NV_SUBDEV(MC, 0xc0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_mc_ctor,
-		.dtor = _nouveau_mc_dtor,
-		.init = nv50_mc_init,
-		.fini = _nouveau_mc_fini,
-	},
-	.intr = nvc0_mc_intr,
-	.msi_rearm = nvc0_mc_msi_rearm,
-	.unk260 = nvc0_mc_unk260,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc3.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc3.c
deleted file mode 100644
index 68b5f61aadb5..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc3.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv04.h"
-
-struct nouveau_oclass *
-nvc3_mc_oclass = &(struct nouveau_mc_oclass) {
-	.base.handle = NV_SUBDEV(MC, 0xc3),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_mc_ctor,
-		.dtor = _nouveau_mc_dtor,
-		.init = nv50_mc_init,
-		.fini = _nouveau_mc_fini,
-	},
-	.intr = nvc0_mc_intr,
-	.msi_rearm = nv40_mc_msi_rearm,
-	.unk260 = nvc0_mc_unk260,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/priv.h b/drivers/gpu/drm/nouveau/core/subdev/mc/priv.h
deleted file mode 100644
index 911e66392587..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/priv.h
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef __NVKM_MC_PRIV_H__
-#define __NVKM_MC_PRIV_H__
-
-#include <subdev/mc.h>
-
-#define nouveau_mc_create(p,e,o,d)                                             \
-	nouveau_mc_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_mc_destroy(p) ({                                               \
-	struct nouveau_mc *pmc = (p); _nouveau_mc_dtor(nv_object(pmc));        \
-})
-#define nouveau_mc_init(p) ({                                                  \
-	struct nouveau_mc *pmc = (p); _nouveau_mc_init(nv_object(pmc));        \
-})
-#define nouveau_mc_fini(p,s) ({                                                \
-	struct nouveau_mc *pmc = (p); _nouveau_mc_fini(nv_object(pmc), (s));   \
-})
-
-int  nouveau_mc_create_(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, int, void **);
-void _nouveau_mc_dtor(struct nouveau_object *);
-int  _nouveau_mc_init(struct nouveau_object *);
-int  _nouveau_mc_fini(struct nouveau_object *, bool);
-
-struct nouveau_mc_intr {
-	u32 stat;
-	u32 unit;
-};
-
-struct nouveau_mc_oclass {
-	struct nouveau_oclass base;
-	const struct nouveau_mc_intr *intr;
-	void (*msi_rearm)(struct nouveau_mc *);
-	void (*unk260)(struct nouveau_mc *, u32);
-};
-
-void nvc0_mc_unk260(struct nouveau_mc *, u32);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/base.c b/drivers/gpu/drm/nouveau/core/subdev/mxm/base.c
deleted file mode 100644
index 51fcf7960417..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/mxm/base.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * Copyright 2011 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/option.h>
-
-#include <subdev/i2c.h>
-#include <subdev/mxm.h>
-#include <subdev/bios.h>
-#include <subdev/bios/mxm.h>
-
-#include "mxms.h"
-
-static bool
-mxm_shadow_rom_fetch(struct nouveau_i2c_port *i2c, u8 addr,
-		     u8 offset, u8 size, u8 *data)
-{
-	struct i2c_msg msgs[] = {
-		{ .addr = addr, .flags = 0, .len = 1, .buf = &offset },
-		{ .addr = addr, .flags = I2C_M_RD, .len = size, .buf = data, },
-	};
-
-	return i2c_transfer(&i2c->adapter, msgs, 2) == 2;
-}
-
-static bool
-mxm_shadow_rom(struct nouveau_mxm *mxm, u8 version)
-{
-	struct nouveau_bios *bios = nouveau_bios(mxm);
-	struct nouveau_i2c *i2c = nouveau_i2c(mxm);
-	struct nouveau_i2c_port *port = NULL;
-	u8 i2cidx, mxms[6], addr, size;
-
-	i2cidx = mxm_ddc_map(bios, 1 /* LVDS_DDC */) & 0x0f;
-	if (i2cidx < 0x0f)
-		port = i2c->find(i2c, i2cidx);
-	if (!port)
-		return false;
-
-	addr = 0x54;
-	if (!mxm_shadow_rom_fetch(port, addr, 0, 6, mxms)) {
-		addr = 0x56;
-		if (!mxm_shadow_rom_fetch(port, addr, 0, 6, mxms))
-			return false;
-	}
-
-	mxm->mxms = mxms;
-	size = mxms_headerlen(mxm) + mxms_structlen(mxm);
-	mxm->mxms = kmalloc(size, GFP_KERNEL);
-
-	if (mxm->mxms &&
-	    mxm_shadow_rom_fetch(port, addr, 0, size, mxm->mxms))
-		return true;
-
-	kfree(mxm->mxms);
-	mxm->mxms = NULL;
-	return false;
-}
-
-#if defined(CONFIG_ACPI)
-static bool
-mxm_shadow_dsm(struct nouveau_mxm *mxm, u8 version)
-{
-	struct nouveau_device *device = nv_device(mxm);
-	static char muid[] = {
-		0x00, 0xA4, 0x04, 0x40, 0x7D, 0x91, 0xF2, 0x4C,
-		0xB8, 0x9C, 0x79, 0xB6, 0x2F, 0xD5, 0x56, 0x65
-	};
-	u32 mxms_args[] = { 0x00000000 };
-	union acpi_object argv4 = {
-		.buffer.type = ACPI_TYPE_BUFFER,
-		.buffer.length = sizeof(mxms_args),
-		.buffer.pointer = (char *)mxms_args,
-	};
-	union acpi_object *obj;
-	acpi_handle handle;
-	int rev;
-
-	handle = ACPI_HANDLE(nv_device_base(device));
-	if (!handle)
-		return false;
-
-	/*
-	 * spec says this can be zero to mean "highest revision", but
-	 * of course there's at least one bios out there which fails
-	 * unless you pass in exactly the version it supports..
-	 */
-	rev = (version & 0xf0) << 4 | (version & 0x0f);
-	obj = acpi_evaluate_dsm(handle, muid, rev, 0x00000010, &argv4);
-	if (!obj) {
-		nv_debug(mxm, "DSM MXMS failed\n");
-		return false;
-	}
-
-	if (obj->type == ACPI_TYPE_BUFFER) {
-		mxm->mxms = kmemdup(obj->buffer.pointer,
-					 obj->buffer.length, GFP_KERNEL);
-	} else if (obj->type == ACPI_TYPE_INTEGER) {
-		nv_debug(mxm, "DSM MXMS returned 0x%llx\n", obj->integer.value);
-	}
-
-	ACPI_FREE(obj);
-	return mxm->mxms != NULL;
-}
-#endif
-
-#if defined(CONFIG_ACPI_WMI) || defined(CONFIG_ACPI_WMI_MODULE)
-
-#define WMI_WMMX_GUID "F6CB5C3C-9CAE-4EBD-B577-931EA32A2CC0"
-
-static u8
-wmi_wmmx_mxmi(struct nouveau_mxm *mxm, u8 version)
-{
-	u32 mxmi_args[] = { 0x494D584D /* MXMI */, version, 0 };
-	struct acpi_buffer args = { sizeof(mxmi_args), mxmi_args };
-	struct acpi_buffer retn = { ACPI_ALLOCATE_BUFFER, NULL };
-	union acpi_object *obj;
-	acpi_status status;
-
-	status = wmi_evaluate_method(WMI_WMMX_GUID, 0, 0, &args, &retn);
-	if (ACPI_FAILURE(status)) {
-		nv_debug(mxm, "WMMX MXMI returned %d\n", status);
-		return 0x00;
-	}
-
-	obj = retn.pointer;
-	if (obj->type == ACPI_TYPE_INTEGER) {
-		version = obj->integer.value;
-		nv_debug(mxm, "WMMX MXMI version %d.%d\n",
-			     (version >> 4), version & 0x0f);
-	} else {
-		version = 0;
-		nv_debug(mxm, "WMMX MXMI returned non-integer\n");
-	}
-
-	kfree(obj);
-	return version;
-}
-
-static bool
-mxm_shadow_wmi(struct nouveau_mxm *mxm, u8 version)
-{
-	u32 mxms_args[] = { 0x534D584D /* MXMS */, version, 0 };
-	struct acpi_buffer args = { sizeof(mxms_args), mxms_args };
-	struct acpi_buffer retn = { ACPI_ALLOCATE_BUFFER, NULL };
-	union acpi_object *obj;
-	acpi_status status;
-
-	if (!wmi_has_guid(WMI_WMMX_GUID)) {
-		nv_debug(mxm, "WMMX GUID not found\n");
-		return false;
-	}
-
-	mxms_args[1] = wmi_wmmx_mxmi(mxm, 0x00);
-	if (!mxms_args[1])
-		mxms_args[1] = wmi_wmmx_mxmi(mxm, version);
-	if (!mxms_args[1])
-		return false;
-
-	status = wmi_evaluate_method(WMI_WMMX_GUID, 0, 0, &args, &retn);
-	if (ACPI_FAILURE(status)) {
-		nv_debug(mxm, "WMMX MXMS returned %d\n", status);
-		return false;
-	}
-
-	obj = retn.pointer;
-	if (obj->type == ACPI_TYPE_BUFFER) {
-		mxm->mxms = kmemdup(obj->buffer.pointer,
-					 obj->buffer.length, GFP_KERNEL);
-	}
-
-	kfree(obj);
-	return mxm->mxms != NULL;
-}
-#endif
-
-static struct mxm_shadow_h {
-	const char *name;
-	bool (*exec)(struct nouveau_mxm *, u8 version);
-} _mxm_shadow[] = {
-	{ "ROM", mxm_shadow_rom },
-#if defined(CONFIG_ACPI)
-	{ "DSM", mxm_shadow_dsm },
-#endif
-#if defined(CONFIG_ACPI_WMI) || defined(CONFIG_ACPI_WMI_MODULE)
-	{ "WMI", mxm_shadow_wmi },
-#endif
-	{}
-};
-
-static int
-mxm_shadow(struct nouveau_mxm *mxm, u8 version)
-{
-	struct mxm_shadow_h *shadow = _mxm_shadow;
-	do {
-		nv_debug(mxm, "checking %s\n", shadow->name);
-		if (shadow->exec(mxm, version)) {
-			if (mxms_valid(mxm))
-				return 0;
-			kfree(mxm->mxms);
-			mxm->mxms = NULL;
-		}
-	} while ((++shadow)->name);
-	return -ENOENT;
-}
-
-int
-nouveau_mxm_create_(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, int length, void **pobject)
-{
-	struct nouveau_device *device = nv_device(parent);
-	struct nouveau_bios *bios = nouveau_bios(device);
-	struct nouveau_mxm *mxm;
-	u8  ver, len;
-	u16 data;
-	int ret;
-
-	ret = nouveau_subdev_create_(parent, engine, oclass, 0, "MXM", "mxm",
-				     length, pobject);
-	mxm = *pobject;
-	if (ret)
-		return ret;
-
-	data = mxm_table(bios, &ver, &len);
-	if (!data || !(ver = nv_ro08(bios, data))) {
-		nv_debug(mxm, "no VBIOS data, nothing to do\n");
-		return 0;
-	}
-
-	nv_info(mxm, "BIOS version %d.%d\n", ver >> 4, ver & 0x0f);
-
-	if (mxm_shadow(mxm, ver)) {
-		nv_info(mxm, "failed to locate valid SIS\n");
-#if 0
-		/* we should, perhaps, fall back to some kind of limited
-		 * mode here if the x86 vbios hasn't already done the
-		 * work for us (so we prevent loading with completely
-		 * whacked vbios tables).
-		 */
-		return -EINVAL;
-#else
-		return 0;
-#endif
-	}
-
-	nv_info(mxm, "MXMS Version %d.%d\n",
-		mxms_version(mxm) >> 8, mxms_version(mxm) & 0xff);
-	mxms_foreach(mxm, 0, NULL, NULL);
-
-	if (nouveau_boolopt(device->cfgopt, "NvMXMDCB", true))
-		mxm->action |= MXM_SANITISE_DCB;
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.c b/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.c
deleted file mode 100644
index 4bde7f7f7b81..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/mxm.h>
-#include "mxms.h"
-
-#define ROM16(x) le16_to_cpu(*(u16 *)&(x))
-#define ROM32(x) le32_to_cpu(*(u32 *)&(x))
-
-static u8 *
-mxms_data(struct nouveau_mxm *mxm)
-{
-	return mxm->mxms;
-
-}
-
-u16
-mxms_version(struct nouveau_mxm *mxm)
-{
-	u8 *mxms = mxms_data(mxm);
-	u16 version = (mxms[4] << 8) | mxms[5];
-	switch (version ) {
-	case 0x0200:
-	case 0x0201:
-	case 0x0300:
-		return version;
-	default:
-		break;
-	}
-
-	nv_debug(mxm, "unknown version %d.%d\n", mxms[4], mxms[5]);
-	return 0x0000;
-}
-
-u16
-mxms_headerlen(struct nouveau_mxm *mxm)
-{
-	return 8;
-}
-
-u16
-mxms_structlen(struct nouveau_mxm *mxm)
-{
-	return *(u16 *)&mxms_data(mxm)[6];
-}
-
-bool
-mxms_checksum(struct nouveau_mxm *mxm)
-{
-	u16 size = mxms_headerlen(mxm) + mxms_structlen(mxm);
-	u8 *mxms = mxms_data(mxm), sum = 0;
-	while (size--)
-		sum += *mxms++;
-	if (sum) {
-		nv_debug(mxm, "checksum invalid\n");
-		return false;
-	}
-	return true;
-}
-
-bool
-mxms_valid(struct nouveau_mxm *mxm)
-{
-	u8 *mxms = mxms_data(mxm);
-	if (*(u32 *)mxms != 0x5f4d584d) {
-		nv_debug(mxm, "signature invalid\n");
-		return false;
-	}
-
-	if (!mxms_version(mxm) || !mxms_checksum(mxm))
-		return false;
-
-	return true;
-}
-
-bool
-mxms_foreach(struct nouveau_mxm *mxm, u8 types,
-	     bool (*exec)(struct nouveau_mxm *, u8 *, void *), void *info)
-{
-	u8 *mxms = mxms_data(mxm);
-	u8 *desc = mxms + mxms_headerlen(mxm);
-	u8 *fini = desc + mxms_structlen(mxm) - 1;
-	while (desc < fini) {
-		u8 type = desc[0] & 0x0f;
-		u8 headerlen = 0;
-		u8 recordlen = 0;
-		u8 entries = 0;
-
-		switch (type) {
-		case 0: /* Output Device Structure */
-			if (mxms_version(mxm) >= 0x0300)
-				headerlen = 8;
-			else
-				headerlen = 6;
-			break;
-		case 1: /* System Cooling Capability Structure */
-		case 2: /* Thermal Structure */
-		case 3: /* Input Power Structure */
-			headerlen = 4;
-			break;
-		case 4: /* GPIO Device Structure */
-			headerlen = 4;
-			recordlen = 2;
-			entries   = (ROM32(desc[0]) & 0x01f00000) >> 20;
-			break;
-		case 5: /* Vendor Specific Structure */
-			headerlen = 8;
-			break;
-		case 6: /* Backlight Control Structure */
-			if (mxms_version(mxm) >= 0x0300) {
-				headerlen = 4;
-				recordlen = 8;
-				entries   = (desc[1] & 0xf0) >> 4;
-			} else {
-				headerlen = 8;
-			}
-			break;
-		case 7: /* Fan Control Structure */
-			headerlen = 8;
-			recordlen = 4;
-			entries   = desc[1] & 0x07;
-			break;
-		default:
-			nv_debug(mxm, "unknown descriptor type %d\n", type);
-			return false;
-		}
-
-		if (nv_subdev(mxm)->debug >= NV_DBG_DEBUG && (exec == NULL)) {
-			static const char * mxms_desc_name[] = {
-				"ODS", "SCCS", "TS", "IPS",
-				"GSD", "VSS", "BCS", "FCS",
-			};
-			u8 *dump = desc;
-			int i, j;
-
-			nv_debug(mxm, "%4s: ", mxms_desc_name[type]);
-			for (j = headerlen - 1; j >= 0; j--)
-				pr_cont("%02x", dump[j]);
-			pr_cont("\n");
-			dump += headerlen;
-
-			for (i = 0; i < entries; i++, dump += recordlen) {
-				nv_debug(mxm, "      ");
-				for (j = recordlen - 1; j >= 0; j--)
-					pr_cont("%02x", dump[j]);
-				pr_cont("\n");
-			}
-		}
-
-		if (types & (1 << type)) {
-			if (!exec(mxm, desc, info))
-				return false;
-		}
-
-		desc += headerlen + (entries * recordlen);
-	}
-
-	return true;
-}
-
-void
-mxms_output_device(struct nouveau_mxm *mxm, u8 *pdata, struct mxms_odev *desc)
-{
-	u64 data = ROM32(pdata[0]);
-	if (mxms_version(mxm) >= 0x0300)
-		data |= (u64)ROM16(pdata[4]) << 32;
-
-	desc->outp_type = (data & 0x00000000000000f0ULL) >> 4;
-	desc->ddc_port  = (data & 0x0000000000000f00ULL) >> 8;
-	desc->conn_type = (data & 0x000000000001f000ULL) >> 12;
-	desc->dig_conn  = (data & 0x0000000000780000ULL) >> 19;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.h b/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.h
deleted file mode 100644
index 5e0be0c591ca..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef __NVMXM_MXMS_H__
-#define __NVMXM_MXMS_H__
-
-struct mxms_odev {
-	u8 outp_type;
-	u8 conn_type;
-	u8 ddc_port;
-	u8 dig_conn;
-};
-
-void mxms_output_device(struct nouveau_mxm *, u8 *, struct mxms_odev *);
-
-u16  mxms_version(struct nouveau_mxm *);
-u16  mxms_headerlen(struct nouveau_mxm *);
-u16  mxms_structlen(struct nouveau_mxm *);
-bool mxms_checksum(struct nouveau_mxm *);
-bool mxms_valid(struct nouveau_mxm *);
-
-bool mxms_foreach(struct nouveau_mxm *, u8,
-		  bool (*)(struct nouveau_mxm *, u8 *, void *), void *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/mxm/nv50.c
deleted file mode 100644
index fcaabe8456e3..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/mxm/nv50.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
- * Copyright 2011 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/mxm.h>
-#include <subdev/bios.h>
-#include <subdev/bios/conn.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/mxm.h>
-
-#include "mxms.h"
-
-struct nv50_mxm_priv {
-	struct nouveau_mxm base;
-};
-
-struct context {
-	u32 *outp;
-	struct mxms_odev desc;
-};
-
-static bool
-mxm_match_tmds_partner(struct nouveau_mxm *mxm, u8 *data, void *info)
-{
-	struct context *ctx = info;
-	struct mxms_odev desc;
-
-	mxms_output_device(mxm, data, &desc);
-	if (desc.outp_type == 2 &&
-	    desc.dig_conn == ctx->desc.dig_conn)
-		return false;
-	return true;
-}
-
-static bool
-mxm_match_dcb(struct nouveau_mxm *mxm, u8 *data, void *info)
-{
-	struct nouveau_bios *bios = nouveau_bios(mxm);
-	struct context *ctx = info;
-	u64 desc = *(u64 *)data;
-
-	mxms_output_device(mxm, data, &ctx->desc);
-
-	/* match dcb encoder type to mxm-ods device type */
-	if ((ctx->outp[0] & 0x0000000f) != ctx->desc.outp_type)
-		return true;
-
-	/* digital output, have some extra stuff to match here, there's a
-	 * table in the vbios that provides a mapping from the mxm digital
-	 * connection enum values to SOR/link
-	 */
-	if ((desc & 0x00000000000000f0) >= 0x20) {
-		/* check against sor index */
-		u8 link = mxm_sor_map(bios, ctx->desc.dig_conn);
-		if ((ctx->outp[0] & 0x0f000000) != (link & 0x0f) << 24)
-			return true;
-
-		/* check dcb entry has a compatible link field */
-		link = (link & 0x30) >> 4;
-		if ((link & ((ctx->outp[1] & 0x00000030) >> 4)) != link)
-			return true;
-	}
-
-	/* mark this descriptor accounted for by setting invalid device type,
-	 * except of course some manufactures don't follow specs properly and
-	 * we need to avoid killing off the TMDS function on DP connectors
-	 * if MXM-SIS is missing an entry for it.
-	 */
-	data[0] &= ~0xf0;
-	if (ctx->desc.outp_type == 6 && ctx->desc.conn_type == 6 &&
-	    mxms_foreach(mxm, 0x01, mxm_match_tmds_partner, ctx)) {
-		data[0] |= 0x20; /* modify descriptor to match TMDS now */
-	} else {
-		data[0] |= 0xf0;
-	}
-
-	return false;
-}
-
-static int
-mxm_dcb_sanitise_entry(struct nouveau_bios *bios, void *data, int idx, u16 pdcb)
-{
-	struct nouveau_mxm *mxm = data;
-	struct context ctx = { .outp = (u32 *)(bios->data + pdcb) };
-	u8 type, i2cidx, link, ver, len;
-	u8 *conn;
-
-	/* look for an output device structure that matches this dcb entry.
-	 * if one isn't found, disable it.
-	 */
-	if (mxms_foreach(mxm, 0x01, mxm_match_dcb, &ctx)) {
-		nv_debug(mxm, "disable %d: 0x%08x 0x%08x\n",
-			idx, ctx.outp[0], ctx.outp[1]);
-		ctx.outp[0] |= 0x0000000f;
-		return 0;
-	}
-
-	/* modify the output's ddc/aux port, there's a pointer to a table
-	 * with the mapping from mxm ddc/aux port to dcb i2c_index in the
-	 * vbios mxm table
-	 */
-	i2cidx = mxm_ddc_map(bios, ctx.desc.ddc_port);
-	if ((ctx.outp[0] & 0x0000000f) != DCB_OUTPUT_DP)
-		i2cidx = (i2cidx & 0x0f) << 4;
-	else
-		i2cidx = (i2cidx & 0xf0);
-
-	if (i2cidx != 0xf0) {
-		ctx.outp[0] &= ~0x000000f0;
-		ctx.outp[0] |= i2cidx;
-	}
-
-	/* override dcb sorconf.link, based on what mxm data says */
-	switch (ctx.desc.outp_type) {
-	case 0x00: /* Analog CRT */
-	case 0x01: /* Analog TV/HDTV */
-		break;
-	default:
-		link = mxm_sor_map(bios, ctx.desc.dig_conn) & 0x30;
-		ctx.outp[1] &= ~0x00000030;
-		ctx.outp[1] |= link;
-		break;
-	}
-
-	/* we may need to fixup various other vbios tables based on what
-	 * the descriptor says the connector type should be.
-	 *
-	 * in a lot of cases, the vbios tables will claim DVI-I is possible,
-	 * and the mxm data says the connector is really HDMI.  another
-	 * common example is DP->eDP.
-	 */
-	conn  = bios->data;
-	conn += nvbios_connEe(bios, (ctx.outp[0] & 0x0000f000) >> 12, &ver, &len);
-	type  = conn[0];
-	switch (ctx.desc.conn_type) {
-	case 0x01: /* LVDS */
-		ctx.outp[1] |= 0x00000004; /* use_power_scripts */
-		/* XXX: modify default link width in LVDS table */
-		break;
-	case 0x02: /* HDMI */
-		type = DCB_CONNECTOR_HDMI_1;
-		break;
-	case 0x03: /* DVI-D */
-		type = DCB_CONNECTOR_DVI_D;
-		break;
-	case 0x0e: /* eDP, falls through to DPint */
-		ctx.outp[1] |= 0x00010000;
-	case 0x07: /* DP internal, wtf is this?? HP8670w */
-		ctx.outp[1] |= 0x00000004; /* use_power_scripts? */
-		type = DCB_CONNECTOR_eDP;
-		break;
-	default:
-		break;
-	}
-
-	if (mxms_version(mxm) >= 0x0300)
-		conn[0] = type;
-
-	return 0;
-}
-
-static bool
-mxm_show_unmatched(struct nouveau_mxm *mxm, u8 *data, void *info)
-{
-	u64 desc = *(u64 *)data;
-	if ((desc & 0xf0) != 0xf0)
-	nv_info(mxm, "unmatched output device 0x%016llx\n", desc);
-	return true;
-}
-
-static void
-mxm_dcb_sanitise(struct nouveau_mxm *mxm)
-{
-	struct nouveau_bios *bios = nouveau_bios(mxm);
-	u8  ver, hdr, cnt, len;
-	u16 dcb = dcb_table(bios, &ver, &hdr, &cnt, &len);
-	if (dcb == 0x0000 || ver != 0x40) {
-		nv_debug(mxm, "unsupported DCB version\n");
-		return;
-	}
-
-	dcb_outp_foreach(bios, mxm, mxm_dcb_sanitise_entry);
-	mxms_foreach(mxm, 0x01, mxm_show_unmatched, NULL);
-}
-
-static int
-nv50_mxm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 size,
-	      struct nouveau_object **pobject)
-{
-	struct nv50_mxm_priv *priv;
-	int ret;
-
-	ret = nouveau_mxm_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	if (priv->base.action & MXM_SANITISE_DCB)
-		mxm_dcb_sanitise(&priv->base);
-	return 0;
-}
-
-struct nouveau_oclass
-nv50_mxm_oclass = {
-	.handle = NV_SUBDEV(MXM, 0x50),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_mxm_ctor,
-		.dtor = _nouveau_mxm_dtor,
-		.init = _nouveau_mxm_init,
-		.fini = _nouveau_mxm_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
deleted file mode 100644
index 0ab55f27ec45..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/timer.h>
-
-#include "priv.h"
-
-static void
-nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable)
-{
-	const struct nvkm_pwr_impl *impl = (void *)nv_oclass(ppwr);
-	if (impl->pgob)
-		impl->pgob(ppwr, enable);
-}
-
-static int
-nouveau_pwr_send(struct nouveau_pwr *ppwr, u32 reply[2],
-		 u32 process, u32 message, u32 data0, u32 data1)
-{
-	struct nouveau_subdev *subdev = nv_subdev(ppwr);
-	u32 addr;
-
-	/* wait for a free slot in the fifo */
-	addr  = nv_rd32(ppwr, 0x10a4a0);
-	if (!nv_wait_ne(ppwr, 0x10a4b0, 0xffffffff, addr ^ 8))
-		return -EBUSY;
-
-	/* we currently only support a single process at a time waiting
-	 * on a synchronous reply, take the PPWR mutex and tell the
-	 * receive handler what we're waiting for
-	 */
-	if (reply) {
-		mutex_lock(&subdev->mutex);
-		ppwr->recv.message = message;
-		ppwr->recv.process = process;
-	}
-
-	/* acquire data segment access */
-	do {
-		nv_wr32(ppwr, 0x10a580, 0x00000001);
-	} while (nv_rd32(ppwr, 0x10a580) != 0x00000001);
-
-	/* write the packet */
-	nv_wr32(ppwr, 0x10a1c0, 0x01000000 | (((addr & 0x07) << 4) +
-				ppwr->send.base));
-	nv_wr32(ppwr, 0x10a1c4, process);
-	nv_wr32(ppwr, 0x10a1c4, message);
-	nv_wr32(ppwr, 0x10a1c4, data0);
-	nv_wr32(ppwr, 0x10a1c4, data1);
-	nv_wr32(ppwr, 0x10a4a0, (addr + 1) & 0x0f);
-
-	/* release data segment access */
-	nv_wr32(ppwr, 0x10a580, 0x00000000);
-
-	/* wait for reply, if requested */
-	if (reply) {
-		wait_event(ppwr->recv.wait, (ppwr->recv.process == 0));
-		reply[0] = ppwr->recv.data[0];
-		reply[1] = ppwr->recv.data[1];
-		mutex_unlock(&subdev->mutex);
-	}
-
-	return 0;
-}
-
-static void
-nouveau_pwr_recv(struct work_struct *work)
-{
-	struct nouveau_pwr *ppwr =
-		container_of(work, struct nouveau_pwr, recv.work);
-	u32 process, message, data0, data1;
-
-	/* nothing to do if GET == PUT */
-	u32 addr =  nv_rd32(ppwr, 0x10a4cc);
-	if (addr == nv_rd32(ppwr, 0x10a4c8))
-		return;
-
-	/* acquire data segment access */
-	do {
-		nv_wr32(ppwr, 0x10a580, 0x00000002);
-	} while (nv_rd32(ppwr, 0x10a580) != 0x00000002);
-
-	/* read the packet */
-	nv_wr32(ppwr, 0x10a1c0, 0x02000000 | (((addr & 0x07) << 4) +
-				ppwr->recv.base));
-	process = nv_rd32(ppwr, 0x10a1c4);
-	message = nv_rd32(ppwr, 0x10a1c4);
-	data0   = nv_rd32(ppwr, 0x10a1c4);
-	data1   = nv_rd32(ppwr, 0x10a1c4);
-	nv_wr32(ppwr, 0x10a4cc, (addr + 1) & 0x0f);
-
-	/* release data segment access */
-	nv_wr32(ppwr, 0x10a580, 0x00000000);
-
-	/* wake process if it's waiting on a synchronous reply */
-	if (ppwr->recv.process) {
-		if (process == ppwr->recv.process &&
-		    message == ppwr->recv.message) {
-			ppwr->recv.data[0] = data0;
-			ppwr->recv.data[1] = data1;
-			ppwr->recv.process = 0;
-			wake_up(&ppwr->recv.wait);
-			return;
-		}
-	}
-
-	/* right now there's no other expected responses from the engine,
-	 * so assume that any unexpected message is an error.
-	 */
-	nv_warn(ppwr, "%c%c%c%c 0x%08x 0x%08x 0x%08x 0x%08x\n",
-		(char)((process & 0x000000ff) >>  0),
-		(char)((process & 0x0000ff00) >>  8),
-		(char)((process & 0x00ff0000) >> 16),
-		(char)((process & 0xff000000) >> 24),
-		process, message, data0, data1);
-}
-
-static void
-nouveau_pwr_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_pwr *ppwr = (void *)subdev;
-	u32 disp = nv_rd32(ppwr, 0x10a01c);
-	u32 intr = nv_rd32(ppwr, 0x10a008) & disp & ~(disp >> 16);
-
-	if (intr & 0x00000020) {
-		u32 stat = nv_rd32(ppwr, 0x10a16c);
-		if (stat & 0x80000000) {
-			nv_error(ppwr, "UAS fault at 0x%06x addr 0x%08x\n",
-				 stat & 0x00ffffff, nv_rd32(ppwr, 0x10a168));
-			nv_wr32(ppwr, 0x10a16c, 0x00000000);
-			intr &= ~0x00000020;
-		}
-	}
-
-	if (intr & 0x00000040) {
-		schedule_work(&ppwr->recv.work);
-		nv_wr32(ppwr, 0x10a004, 0x00000040);
-		intr &= ~0x00000040;
-	}
-
-	if (intr & 0x00000080) {
-		nv_info(ppwr, "wr32 0x%06x 0x%08x\n", nv_rd32(ppwr, 0x10a7a0),
-						      nv_rd32(ppwr, 0x10a7a4));
-		nv_wr32(ppwr, 0x10a004, 0x00000080);
-		intr &= ~0x00000080;
-	}
-
-	if (intr) {
-		nv_error(ppwr, "intr 0x%08x\n", intr);
-		nv_wr32(ppwr, 0x10a004, intr);
-	}
-}
-
-int
-_nouveau_pwr_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nouveau_pwr *ppwr = (void *)object;
-
-	nv_wr32(ppwr, 0x10a014, 0x00000060);
-	flush_work(&ppwr->recv.work);
-
-	return nouveau_subdev_fini(&ppwr->base, suspend);
-}
-
-int
-_nouveau_pwr_init(struct nouveau_object *object)
-{
-	const struct nvkm_pwr_impl *impl = (void *)object->oclass;
-	struct nouveau_pwr *ppwr = (void *)object;
-	int ret, i;
-
-	ret = nouveau_subdev_init(&ppwr->base);
-	if (ret)
-		return ret;
-
-	nv_subdev(ppwr)->intr = nouveau_pwr_intr;
-	ppwr->message = nouveau_pwr_send;
-	ppwr->pgob = nouveau_pwr_pgob;
-
-	/* prevent previous ucode from running, wait for idle, reset */
-	nv_wr32(ppwr, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */
-	nv_wait(ppwr, 0x10a04c, 0xffffffff, 0x00000000);
-	nv_mask(ppwr, 0x000200, 0x00002000, 0x00000000);
-	nv_mask(ppwr, 0x000200, 0x00002000, 0x00002000);
-	nv_rd32(ppwr, 0x000200);
-	nv_wait(ppwr, 0x10a10c, 0x00000006, 0x00000000);
-
-	/* upload data segment */
-	nv_wr32(ppwr, 0x10a1c0, 0x01000000);
-	for (i = 0; i < impl->data.size / 4; i++)
-		nv_wr32(ppwr, 0x10a1c4, impl->data.data[i]);
-
-	/* upload code segment */
-	nv_wr32(ppwr, 0x10a180, 0x01000000);
-	for (i = 0; i < impl->code.size / 4; i++) {
-		if ((i & 0x3f) == 0)
-			nv_wr32(ppwr, 0x10a188, i >> 6);
-		nv_wr32(ppwr, 0x10a184, impl->code.data[i]);
-	}
-
-	/* start it running */
-	nv_wr32(ppwr, 0x10a10c, 0x00000000);
-	nv_wr32(ppwr, 0x10a104, 0x00000000);
-	nv_wr32(ppwr, 0x10a100, 0x00000002);
-
-	/* wait for valid host->pwr ring configuration */
-	if (!nv_wait_ne(ppwr, 0x10a4d0, 0xffffffff, 0x00000000))
-		return -EBUSY;
-	ppwr->send.base = nv_rd32(ppwr, 0x10a4d0) & 0x0000ffff;
-	ppwr->send.size = nv_rd32(ppwr, 0x10a4d0) >> 16;
-
-	/* wait for valid pwr->host ring configuration */
-	if (!nv_wait_ne(ppwr, 0x10a4dc, 0xffffffff, 0x00000000))
-		return -EBUSY;
-	ppwr->recv.base = nv_rd32(ppwr, 0x10a4dc) & 0x0000ffff;
-	ppwr->recv.size = nv_rd32(ppwr, 0x10a4dc) >> 16;
-
-	nv_wr32(ppwr, 0x10a010, 0x000000e0);
-	return 0;
-}
-
-int
-nouveau_pwr_create_(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, int length, void **pobject)
-{
-	struct nouveau_pwr *ppwr;
-	int ret;
-
-	ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PPWR",
-				     "pwr", length, pobject);
-	ppwr = *pobject;
-	if (ret)
-		return ret;
-
-	INIT_WORK(&ppwr->recv.work, nouveau_pwr_recv);
-	init_waitqueue_head(&ppwr->recv.wait);
-	return 0;
-}
-
-int
-_nouveau_pwr_ctor(struct nouveau_object *parent,
-		  struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *data, u32 size,
-		  struct nouveau_object **pobject)
-{
-	struct nouveau_pwr *ppwr;
-	int ret = nouveau_pwr_create(parent, engine, oclass, &ppwr);
-	*pobject = nv_object(ppwr);
-	return ret;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/arith.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/arith.fuc
deleted file mode 100644
index 214a6d9e088d..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/arith.fuc
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright 2014 Martin Peres <martin.peres@free.fr>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the folloing conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres
- */
-
-/******************************************************************************
- * arith data segment
- *****************************************************************************/
-#ifdef INCLUDE_PROC
-#endif
-
-#ifdef INCLUDE_DATA
-#endif
-
-/******************************************************************************
- * arith code segment
- *****************************************************************************/
-#ifdef INCLUDE_CODE
-
-// does a 32x32 -> 64 multiplication
-//
-// A * B = A_lo * B_lo
-//        + ( A_hi * B_lo ) << 16
-//        + ( A_lo * B_hi ) << 16
-//        + ( A_hi * B_hi ) << 32
-//
-// $r15 - current
-// $r14 - A
-// $r13 - B
-// $r12 - mul_lo (return)
-// $r11 - mul_hi (return)
-// $r0  - zero
-mulu32_32_64:
-	push $r1 // A_hi
-	push $r2 // B_hi
-	push $r3 // tmp0
-	push $r4 // tmp1
-
-	shr b32 $r1 $r14 16
-	shr b32 $r2 $r13 16
-
-	clear b32 $r12
-	clear b32 $r11
-
-	// A_lo * B_lo
-	mulu $r12 $r14 $r13
-
-	// ( A_hi * B_lo ) << 16
-	mulu $r3 $r1 $r13 // tmp0 = A_hi * B_lo
-	mov b32 $r4 $r3
-	and $r3 0xffff // tmp0 = tmp0_lo
-	shl b32 $r3 16
-	shr b32 $r4 16 // tmp1 = tmp0_hi
-	add b32 $r12 $r3
-	adc b32 $r11 $r4
-
-	// ( A_lo * B_hi ) << 16
-	mulu $r3 $r14 $r2 // tmp0 = A_lo * B_hi
-	mov b32 $r4 $r3
-	and $r3 0xffff // tmp0 = tmp0_lo
-	shl b32 $r3 16
-	shr b32 $r4 16 // tmp1 = tmp0_hi
-	add b32 $r12 $r3
-	adc b32 $r11 $r4
-
-	// ( A_hi * B_hi ) << 32
-	mulu $r3 $r1 $r2 // tmp0 = A_hi * B_hi
-	add b32 $r11 $r3
-
-	pop $r4
-	pop $r3
-	pop $r2
-	pop $r1
-	ret
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc
deleted file mode 100644
index c2bb616a8da5..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#ifdef INCLUDE_PROC
-process(PROC_HOST, #host_init, #host_recv)
-#endif
-
-/******************************************************************************
- * HOST data segment
- *****************************************************************************/
-#ifdef INCLUDE_DATA
-// HOST (R)FIFO packet format
-.equ #fifo_process 0x00
-.equ #fifo_message 0x04
-.equ #fifo_data0   0x08
-.equ #fifo_data1   0x0c
-
-// HOST HOST->PWR queue description
-.equ #fifo_qlen 4 // log2(size of queue entry in bytes)
-.equ #fifo_qnum 3 // log2(max number of entries in queue)
-.equ #fifo_qmaskb (1 << #fifo_qnum) // max number of entries in queue
-.equ #fifo_qmaskp (#fifo_qmaskb - 1)
-.equ #fifo_qmaskf ((#fifo_qmaskb << 1) - 1)
-.equ #fifo_qsize  (1 << (#fifo_qlen + #fifo_qnum))
-fifo_queue: .skip 128 // #fifo_qsize
-
-// HOST PWR->HOST queue description
-.equ #rfifo_qlen 4 // log2(size of queue entry in bytes)
-.equ #rfifo_qnum 3 // log2(max number of entries in queue)
-.equ #rfifo_qmaskb (1 << #rfifo_qnum) // max number of entries in queue
-.equ #rfifo_qmaskp (#rfifo_qmaskb - 1)
-.equ #rfifo_qmaskf ((#rfifo_qmaskb << 1) - 1)
-.equ #rfifo_qsize  (1 << (#rfifo_qlen + #rfifo_qnum))
-rfifo_queue: .skip 128 // #rfifo_qsize
-#endif
-
-/******************************************************************************
- * HOST code segment
- *****************************************************************************/
-#ifdef INCLUDE_CODE
-// HOST->PWR comms - dequeue message(s) for process(es) from FIFO
-//
-// $r15 - current (host)
-// $r0  - zero
-host_send:
-	nv_iord($r1, NV_PPWR_FIFO_GET(0))
-	nv_iord($r2, NV_PPWR_FIFO_PUT(0))
-	cmp b32 $r1 $r2
-	bra e #host_send_done
-		// calculate address of message
-		and $r14 $r1 #fifo_qmaskp
-		shl b32 $r14 $r14 #fifo_qlen
-		add b32 $r14 #fifo_queue
-
-		// read message data, and pass to appropriate process
-		ld b32 $r11 D[$r14 + #fifo_data1]
-		ld b32 $r12 D[$r14 + #fifo_data0]
-		ld b32 $r13 D[$r14 + #fifo_message]
-		ld b32 $r14 D[$r14 + #fifo_process]
-		call(send)
-
-		// increment GET
-		add b32 $r1 0x1
-		and $r14 $r1 #fifo_qmaskf
-		nv_iowr(NV_PPWR_FIFO_GET(0), $r14)
-		bra #host_send
-	host_send_done:
-	ret
-
-// PWR->HOST comms - enqueue message for HOST to RFIFO
-//
-// $r15 - current (host)
-// $r14 - process
-// $r13 - message
-// $r12 - message data 0
-// $r11 - message data 1
-// $r0  - zero
-host_recv:
-	// message from intr handler == HOST->PWR comms pending
-	mov $r1 (PROC_KERN & 0x0000ffff)
-	sethi $r1 (PROC_KERN & 0xffff0000)
-	cmp b32 $r14 $r1
-	bra e #host_send
-
-	// wait for space in RFIFO
-	host_recv_wait:
-	nv_iord($r1, NV_PPWR_RFIFO_GET)
-	nv_iord($r2, NV_PPWR_RFIFO_PUT)
-	xor $r1 #rfifo_qmaskb
-	cmp b32 $r1 $r2
-	bra e #host_recv_wait
-
-	and $r3 $r2 #rfifo_qmaskp
-	shl b32 $r3 #rfifo_qlen
-	add b32 $r3 #rfifo_queue
-
-	// enqueue message
-	st b32 D[$r3 + #fifo_data1] $r11
-	st b32 D[$r3 + #fifo_data0] $r12
-	st b32 D[$r3 + #fifo_message] $r13
-	st b32 D[$r3 + #fifo_process] $r14
-
-	add b32 $r2 0x1
-	and $r2 #rfifo_qmaskf
-	nv_iowr(NV_PPWR_RFIFO_PUT, $r2)
-
-	// notify host of pending message
-	mov $r2 NV_PPWR_INTR_TRIGGER_USER0
-	nv_iowr(NV_PPWR_INTR_TRIGGER, $r2)
-	ret
-
-// $r15 - current (host)
-// $r0  - zero
-host_init:
-	// store each fifo's base/size in H2D/D2H scratch regs
-	mov $r1 #fifo_qsize
-	shl b32 $r1 16
-	or $r1 #fifo_queue
-	nv_iowr(NV_PPWR_H2D, $r1);
-
-	mov $r1 #rfifo_qsize
-	shl b32 $r1 16
-	or $r1 #rfifo_queue
-	nv_iowr(NV_PPWR_D2H, $r1);
-
-	// enable fifo subintr for first fifo
-	mov $r1 1
-	nv_iowr(NV_PPWR_FIFO_INTR_EN, $r1)
-	ret
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/i2c_.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/i2c_.fuc
deleted file mode 100644
index 757dda700024..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/i2c_.fuc
+++ /dev/null
@@ -1,393 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#define T_TIMEOUT  2200000
-#define T_RISEFALL 1000
-#define T_HOLD     5000
-
-#ifdef INCLUDE_PROC
-process(PROC_I2C_, #i2c_init, #i2c_recv)
-#endif
-
-/******************************************************************************
- * I2C_ data segment
- *****************************************************************************/
-#ifdef INCLUDE_DATA
-i2c_scl_map:
-.b32 NV_PPWR_OUTPUT_I2C_0_SCL
-.b32 NV_PPWR_OUTPUT_I2C_1_SCL
-.b32 NV_PPWR_OUTPUT_I2C_2_SCL
-.b32 NV_PPWR_OUTPUT_I2C_3_SCL
-.b32 NV_PPWR_OUTPUT_I2C_4_SCL
-.b32 NV_PPWR_OUTPUT_I2C_5_SCL
-.b32 NV_PPWR_OUTPUT_I2C_6_SCL
-.b32 NV_PPWR_OUTPUT_I2C_7_SCL
-.b32 NV_PPWR_OUTPUT_I2C_8_SCL
-.b32 NV_PPWR_OUTPUT_I2C_9_SCL
-i2c_sda_map:
-.b32 NV_PPWR_OUTPUT_I2C_0_SDA
-.b32 NV_PPWR_OUTPUT_I2C_1_SDA
-.b32 NV_PPWR_OUTPUT_I2C_2_SDA
-.b32 NV_PPWR_OUTPUT_I2C_3_SDA
-.b32 NV_PPWR_OUTPUT_I2C_4_SDA
-.b32 NV_PPWR_OUTPUT_I2C_5_SDA
-.b32 NV_PPWR_OUTPUT_I2C_6_SDA
-.b32 NV_PPWR_OUTPUT_I2C_7_SDA
-.b32 NV_PPWR_OUTPUT_I2C_8_SDA
-.b32 NV_PPWR_OUTPUT_I2C_9_SDA
-#if NVKM_PPWR_CHIPSET < GF119
-i2c_ctrl:
-.b32 0x00e138
-.b32 0x00e150
-.b32 0x00e168
-.b32 0x00e180
-.b32 0x00e254
-.b32 0x00e274
-.b32 0x00e764
-.b32 0x00e780
-.b32 0x00e79c
-.b32 0x00e7b8
-#endif
-#endif
-
-/******************************************************************************
- * I2C_ code segment
- *****************************************************************************/
-#ifdef INCLUDE_CODE
-
-// $r3  - value
-// $r2  - sda line
-// $r1  - scl line
-// $r0  - zero
-i2c_drive_scl:
-	cmp b32 $r3 0
-	bra e #i2c_drive_scl_lo
-	nv_iowr(NV_PPWR_OUTPUT_SET, $r1)
-	ret
-	i2c_drive_scl_lo:
-	nv_iowr(NV_PPWR_OUTPUT_CLR, $r1)
-	ret
-
-i2c_drive_sda:
-	cmp b32 $r3 0
-	bra e #i2c_drive_sda_lo
-	nv_iowr(NV_PPWR_OUTPUT_SET, $r2)
-	ret
-	i2c_drive_sda_lo:
-	nv_iowr(NV_PPWR_OUTPUT_CLR, $r2)
-	ret
-
-i2c_sense_scl:
-	bclr $flags $p1
-	nv_iord($r3, NV_PPWR_INPUT)
-	and $r3 $r1
-	bra z #i2c_sense_scl_done
-		bset $flags $p1
-	i2c_sense_scl_done:
-	ret
-
-i2c_sense_sda:
-	bclr $flags $p1
-	nv_iord($r3, NV_PPWR_INPUT)
-	and $r3 $r2
-	bra z #i2c_sense_sda_done
-		bset $flags $p1
-	i2c_sense_sda_done:
-	ret
-
-#define i2c_drive_scl(v) /*
-*/	mov $r3 (v) /*
-*/	call(i2c_drive_scl)
-#define i2c_drive_sda(v) /*
-*/	mov $r3 (v) /*
-*/	call(i2c_drive_sda)
-#define i2c_sense_scl() /*
-*/	call(i2c_sense_scl)
-#define i2c_sense_sda() /*
-*/	call(i2c_sense_sda)
-#define i2c_delay(v) /*
-*/	mov $r14 (v) /*
-*/	call(nsec)
-
-#define i2c_trace_init() /*
-*/	imm32($r6, 0x10000000) /*
-*/	sub b32 $r7 $r6 1 /*
-*/
-#define i2c_trace_down() /*
-*/	shr b32 $r6 4 /*
-*/	push $r5 /*
-*/	shl b32 $r5 $r6 4 /*
-*/	sub b32 $r5 $r6 /*
-*/	not b32 $r5 /*
-*/	and $r7 $r5 /*
-*/	pop $r5 /*
-*/
-#define i2c_trace_exit() /*
-*/	shl b32 $r6 4 /*
-*/
-#define i2c_trace_next() /*
-*/	add b32 $r7 $r6 /*
-*/
-#define i2c_trace_call(func) /*
-*/	i2c_trace_next() /*
-*/	i2c_trace_down() /*
-*/	call(func) /*
-*/	i2c_trace_exit() /*
-*/
-
-i2c_raise_scl:
-	push $r4
-	mov $r4 (T_TIMEOUT / T_RISEFALL)
-	i2c_drive_scl(1)
-	i2c_raise_scl_wait:
-		i2c_delay(T_RISEFALL)
-		i2c_sense_scl()
-		bra $p1 #i2c_raise_scl_done
-		sub b32 $r4 1
-		bra nz #i2c_raise_scl_wait
-	i2c_raise_scl_done:
-	pop $r4
-	ret
-
-i2c_start:
-	i2c_sense_scl()
-	bra not $p1 #i2c_start_rep
-	i2c_sense_sda()
-	bra not $p1 #i2c_start_rep
-	bra #i2c_start_send
-	i2c_start_rep:
-		i2c_drive_scl(0)
-		i2c_drive_sda(1)
-		i2c_trace_call(i2c_raise_scl)
-		bra not $p1 #i2c_start_out
-	i2c_start_send:
-	i2c_drive_sda(0)
-	i2c_delay(T_HOLD)
-	i2c_drive_scl(0)
-	i2c_delay(T_HOLD)
-	i2c_start_out:
-	ret
-
-i2c_stop:
-	i2c_drive_scl(0)
-	i2c_drive_sda(0)
-	i2c_delay(T_RISEFALL)
-	i2c_drive_scl(1)
-	i2c_delay(T_HOLD)
-	i2c_drive_sda(1)
-	i2c_delay(T_HOLD)
-	ret
-
-// $r3  - value
-// $r2  - sda line
-// $r1  - scl line
-// $r0  - zero
-i2c_bitw:
-	call(i2c_drive_sda)
-	i2c_delay(T_RISEFALL)
-	i2c_trace_call(i2c_raise_scl)
-	bra not $p1 #i2c_bitw_out
-	i2c_delay(T_HOLD)
-	i2c_drive_scl(0)
-	i2c_delay(T_HOLD)
-	i2c_bitw_out:
-	ret
-
-// $r3  - value (out)
-// $r2  - sda line
-// $r1  - scl line
-// $r0  - zero
-i2c_bitr:
-	i2c_drive_sda(1)
-	i2c_delay(T_RISEFALL)
-	i2c_trace_call(i2c_raise_scl)
-	bra not $p1 #i2c_bitr_done
-	i2c_sense_sda()
-	i2c_drive_scl(0)
-	i2c_delay(T_HOLD)
-	xbit $r3 $flags $p1
-	bset $flags $p1
-	i2c_bitr_done:
-	ret
-
-i2c_get_byte:
-	mov $r5 0
-	mov $r4 8
-	i2c_get_byte_next:
-		shl b32 $r5 1
-		i2c_trace_call(i2c_bitr)
-		bra not $p1 #i2c_get_byte_done
-		or $r5 $r3
-		sub b32 $r4 1
-		bra nz #i2c_get_byte_next
-	mov $r3 1
-	i2c_trace_call(i2c_bitw)
-	i2c_get_byte_done:
-	ret
-
-i2c_put_byte:
-	mov $r4 8
-	i2c_put_byte_next:
-		sub b32 $r4 1
-		xbit $r3 $r5 $r4
-		i2c_trace_call(i2c_bitw)
-		bra not $p1 #i2c_put_byte_done
-		cmp b32 $r4 0
-		bra ne #i2c_put_byte_next
-	i2c_trace_call(i2c_bitr)
-	bra not $p1 #i2c_put_byte_done
-	i2c_trace_next()
-	cmp b32 $r3 1
-	bra ne #i2c_put_byte_done
-	bclr $flags $p1	// nack
-	i2c_put_byte_done:
-	ret
-
-i2c_addr:
-	i2c_trace_call(i2c_start)
-	bra not $p1 #i2c_addr_done
-	extr $r3 $r12 I2C__MSG_DATA0_ADDR
-	shl b32 $r3 1
-	or $r5 $r3
-	i2c_trace_call(i2c_put_byte)
-	i2c_addr_done:
-	ret
-
-i2c_acquire_addr:
-	extr $r14 $r12 I2C__MSG_DATA0_PORT
-#if NVKM_PPWR_CHIPSET < GF119
-	shl b32 $r14 2
-	add b32 $r14 #i2c_ctrl
-	ld b32 $r14 D[$r14]
-#else
-	shl b32 $r14 5
-	add b32 $r14 0x00d014
-#endif
-	ret
-
-i2c_acquire:
-	call(i2c_acquire_addr)
-	call(rd32)
-	bset $r13 3
-	call(wr32)
-	ret
-
-i2c_release:
-	call(i2c_acquire_addr)
-	call(rd32)
-	bclr $r13 3
-	call(wr32)
-	ret
-
-// description
-//
-// $r15 - current (i2c)
-// $r14 - sender process name
-// $r13 - message
-// $r12 - data0
-// $r11 - data1
-// $r0  - zero
-i2c_recv:
-	bclr $flags $p1
-	extr $r1 $r12 I2C__MSG_DATA0_PORT
-	shl b32 $r1 2
-	cmp b32 $r1 (#i2c_sda_map - #i2c_scl_map)
-	bra ge #i2c_recv_done
-	add b32 $r3 $r1 #i2c_sda_map
-	ld b32 $r2 D[$r3]
-	add b32 $r3 $r1 #i2c_scl_map
-	ld b32 $r1 D[$r3]
-
-	bset $flags $p2
-	push $r13
-	push $r14
-
-	push $r13
-	i2c_trace_init()
-	i2c_trace_call(i2c_acquire)
-	pop $r13
-
-	cmp b32 $r13 I2C__MSG_RD08
-	bra ne #i2c_recv_not_rd08
-		mov $r5 0
-		i2c_trace_call(i2c_addr)
-		bra not $p1 #i2c_recv_done
-		extr $r5 $r12 I2C__MSG_DATA0_RD08_REG
-		i2c_trace_call(i2c_put_byte)
-		bra not $p1 #i2c_recv_done
-		mov $r5 1
-		i2c_trace_call(i2c_addr)
-		bra not $p1 #i2c_recv_done
-		i2c_trace_call(i2c_get_byte)
-		bra not $p1 #i2c_recv_done
-		ins $r11 $r5 I2C__MSG_DATA1_RD08_VAL
-		i2c_trace_call(i2c_stop)
-		mov b32 $r11 $r5
-		clear b32 $r7
-		bra #i2c_recv_done
-
-	i2c_recv_not_rd08:
-	cmp b32 $r13 I2C__MSG_WR08
-	bra ne #i2c_recv_not_wr08
-		mov $r5 0
-		call(i2c_addr)
-		bra not $p1 #i2c_recv_done
-		extr $r5 $r12 I2C__MSG_DATA0_WR08_REG
-		call(i2c_put_byte)
-		bra not $p1 #i2c_recv_done
-		mov $r5 0
-		call(i2c_addr)
-		bra not $p1 #i2c_recv_done
-		extr $r5 $r11 I2C__MSG_DATA1_WR08_VAL
-		call(i2c_put_byte)
-		bra not $p1 #i2c_recv_done
-		call(i2c_stop)
-		clear b32 $r7
-		extr $r5 $r12 I2C__MSG_DATA0_WR08_SYNC
-		bra nz #i2c_recv_done
-		bclr $flags $p2
-		bra #i2c_recv_done
-
-	i2c_recv_not_wr08:
-
-	i2c_recv_done:
-	extr $r14 $r12 I2C__MSG_DATA0_PORT
-	call(i2c_release)
-
-	pop $r14
-	pop $r13
-	bra not $p2 #i2c_recv_exit
-	mov b32 $r12 $r7
-	call(send)
-
-	i2c_recv_exit:
-	ret
-
-// description
-//
-// $r15 - current (i2c)
-// $r0  - zero
-i2c_init:
-	ret
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/idle.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/idle.fuc
deleted file mode 100644
index 98f1c3738b42..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/idle.fuc
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#ifdef INCLUDE_PROC
-process(PROC_IDLE, #idle, #idle_recv)
-#endif
-
-/******************************************************************************
- * IDLE data segment
- *****************************************************************************/
-#ifdef INCLUDE_DATA
-#endif
-
-/******************************************************************************
- * IDLE code segment
- *****************************************************************************/
-#ifdef INCLUDE_CODE
-// description
-//
-// $r15 - current (idle)
-// $r14 - message
-// $r0  - zero
-idle_recv:
-	ret
-
-// description
-//
-// $r15 - current (idle)
-// $r0  - zero
-idle:
-	// set our "no interrupt has occurred during our execution" flag
-	bset $flags $p0
-
-	// count IDLE invocations for debugging purposes
-	nv_iord($r1, NV_PPWR_DSCRATCH(1))
-	add b32 $r1 1
-	nv_iowr(NV_PPWR_DSCRATCH(1), $r1)
-
-	// keep looping while there's pending messages for any process
-	idle_loop:
-	mov $r1 #proc_list_head
-	bclr $flags $p2
-	idle_proc:
-		// process the process' messages until there's none left
-		idle_proc_exec:
-			push $r1
-			mov b32 $r14 $r1
-			call(recv)
-			pop $r1
-			bra not $p1 #idle_proc_next
-			bset $flags $p2
-			bra #idle_proc_exec
-		// next process!
-		idle_proc_next:
-		add b32 $r1 #proc_size
-		cmp b32 $r1 $r15
-		bra ne #idle_proc
-	bra $p2 #idle_loop
-
-	// sleep if no interrupts have occurred
-	sleep $p0
-	bra #idle
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc
deleted file mode 100644
index 5cf5be63cbef..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc
+++ /dev/null
@@ -1,556 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-/******************************************************************************
- * kernel data segment
- *****************************************************************************/
-#ifdef INCLUDE_PROC
-proc_kern:
-process(PROC_KERN, 0, 0)
-proc_list_head:
-#endif
-
-#ifdef INCLUDE_DATA
-proc_list_tail:
-time_prev: .b32 0
-time_next: .b32 0
-#endif
-
-/******************************************************************************
- * kernel code segment
- *****************************************************************************/
-#ifdef INCLUDE_CODE
-	bra #init
-
-// read nv register
-//
-// $r15 - current
-// $r14 - addr
-// $r13 - data (return)
-// $r0  - zero
-rd32:
-	nv_iowr(NV_PPWR_MMIO_ADDR, $r14)
-	mov $r13 NV_PPWR_MMIO_CTRL_OP_RD
-	sethi $r13 NV_PPWR_MMIO_CTRL_TRIGGER
-	nv_iowr(NV_PPWR_MMIO_CTRL, $r13)
-	rd32_wait:
-		nv_iord($r13, NV_PPWR_MMIO_CTRL)
-		and $r13 NV_PPWR_MMIO_CTRL_STATUS
-		bra nz #rd32_wait
-	nv_iord($r13, NV_PPWR_MMIO_DATA)
-	ret
-
-// write nv register
-//
-// $r15 - current
-// $r14 - addr
-// $r13 - data
-// $r0  - zero
-wr32:
-	nv_iowr(NV_PPWR_MMIO_ADDR, $r14)
-	nv_iowr(NV_PPWR_MMIO_DATA, $r13)
-	mov $r13 NV_PPWR_MMIO_CTRL_OP_WR
-	or $r13 NV_PPWR_MMIO_CTRL_MASK_B32_0
-	sethi $r13 NV_PPWR_MMIO_CTRL_TRIGGER
-
-#ifdef NVKM_FALCON_MMIO_TRAP
-	push $r13
-	mov $r13 NV_PPWR_INTR_TRIGGER_USER1
-	nv_iowr(NV_PPWR_INTR_TRIGGER, $r13)
-	wr32_host:
-		nv_iord($r13, NV_PPWR_INTR)
-		and $r13 NV_PPWR_INTR_USER1
-		bra nz #wr32_host
-	pop $r13
-#endif
-
-	nv_iowr(NV_PPWR_MMIO_CTRL, $r13)
-	wr32_wait:
-		nv_iord($r13, NV_PPWR_MMIO_CTRL)
-		and $r13 NV_PPWR_MMIO_CTRL_STATUS
-		bra nz #wr32_wait
-	ret
-
-// busy-wait for a period of time
-//
-// $r15 - current
-// $r14 - ns
-// $r0  - zero
-nsec:
-	push $r9
-	push $r8
-	nv_iord($r8, NV_PPWR_TIMER_LOW)
-	nsec_loop:
-		nv_iord($r9, NV_PPWR_TIMER_LOW)
-		sub b32 $r9 $r8
-		cmp b32 $r9 $r14
-		bra l #nsec_loop
-	pop $r8
-	pop $r9
-	ret
-
-// busy-wait for a period of time
-//
-// $r15 - current
-// $r14 - addr
-// $r13 - mask
-// $r12 - data
-// $r11 - timeout (ns)
-// $r0  - zero
-wait:
-	push $r9
-	push $r8
-	nv_iord($r8, NV_PPWR_TIMER_LOW)
-	wait_loop:
-		nv_rd32($r10, $r14)
-		and $r10 $r13
-		cmp b32 $r10 $r12
-		bra e #wait_done
-		nv_iord($r9, NV_PPWR_TIMER_LOW)
-		sub b32 $r9 $r8
-		cmp b32 $r9 $r11
-		bra l #wait_loop
-	wait_done:
-	pop $r8
-	pop $r9
-	ret
-
-// $r15 - current (kern)
-// $r14 - process
-// $r8  - NV_PPWR_INTR
-intr_watchdog:
-	// read process' timer status, skip if not enabled
-	ld b32 $r9 D[$r14 + #proc_time]
-	cmp b32 $r9 0
-	bra z #intr_watchdog_next_proc
-
-	// subtract last timer's value from process' timer,
-	// if it's <= 0 then the timer has expired
-	ld b32 $r10 D[$r0 + #time_prev]
-	sub b32 $r9 $r10
-	bra g #intr_watchdog_next_time
-		mov $r13 KMSG_ALARM
-		call(send_proc)
-		clear b32 $r9
-		bra #intr_watchdog_next_proc
-
-	// otherwise, update the next timer's value if this
-	// process' timer is the soonest
-	intr_watchdog_next_time:
-		// ... or if there's no next timer yet
-		ld b32 $r10 D[$r0 + #time_next]
-		cmp b32 $r10 0
-		bra z #intr_watchdog_next_time_set
-
-		cmp b32 $r9 $r10
-		bra g #intr_watchdog_next_proc
-		intr_watchdog_next_time_set:
-		st b32 D[$r0 + #time_next] $r9
-
-	// update process' timer status, and advance
-	intr_watchdog_next_proc:
-	st b32 D[$r14 + #proc_time] $r9
-	add b32 $r14 #proc_size
-	cmp b32 $r14 #proc_list_tail
-	bra ne #intr_watchdog
-	ret
-
-intr:
-	push $r0
-	clear b32 $r0
-	push $r8
-	push $r9
-	push $r10
-	push $r11
-	push $r12
-	push $r13
-	push $r14
-	push $r15
-	mov $r15 #proc_kern
-	mov $r8 $flags
-	push $r8
-
-	nv_iord($r8, NV_PPWR_DSCRATCH(0))
-	add b32 $r8 1
-	nv_iowr(NV_PPWR_DSCRATCH(0), $r8)
-
-	nv_iord($r8, NV_PPWR_INTR)
-	and $r9 $r8 NV_PPWR_INTR_WATCHDOG
-	bra z #intr_skip_watchdog
-		st b32 D[$r0 + #time_next] $r0
-		mov $r14 #proc_list_head
-		call(intr_watchdog)
-		ld b32 $r9 D[$r0 + #time_next]
-		cmp b32 $r9 0
-		bra z #intr_skip_watchdog
-			nv_iowr(NV_PPWR_WATCHDOG_TIME, $r9)
-			st b32 D[$r0 + #time_prev] $r9
-
-	intr_skip_watchdog:
-	and $r9 $r8 NV_PPWR_INTR_SUBINTR
-	bra z #intr_skip_subintr
-		nv_iord($r9, NV_PPWR_SUBINTR)
-		and $r10 $r9 NV_PPWR_SUBINTR_FIFO
-		bra z #intr_subintr_skip_fifo
-			nv_iord($r12, NV_PPWR_FIFO_INTR)
-			push $r12
-			mov $r14 (PROC_HOST & 0x0000ffff)
-			sethi $r14 (PROC_HOST & 0xffff0000)
-			mov $r13 KMSG_FIFO
-			call(send)
-			pop $r12
-			nv_iowr(NV_PPWR_FIFO_INTR, $r12)
-		intr_subintr_skip_fifo:
-		nv_iowr(NV_PPWR_SUBINTR, $r9)
-
-	intr_skip_subintr:
-	and $r9 $r8 NV_PPWR_INTR_PAUSE
-	bra z #intr_skip_pause
-		and $r10 0xffbf
-
-	intr_skip_pause:
-	and $r9 $r8 NV_PPWR_INTR_USER0
-	bra z #intr_skip_user0
-		and $r10 0xffbf
-
-	intr_skip_user0:
-	nv_iowr(NV_PPWR_INTR_ACK, $r8)
-	pop $r8
-	mov $flags $r8
-	pop $r15
-	pop $r14
-	pop $r13
-	pop $r12
-	pop $r11
-	pop $r10
-	pop $r9
-	pop $r8
-	pop $r0
-	bclr $flags $p0
-	iret
-
-// calculate the number of ticks in the specified nanoseconds delay
-//
-// $r15 - current
-// $r14 - ns
-// $r14 - ticks (return)
-// $r0  - zero
-ticks_from_ns:
-	push $r12
-	push $r11
-
-	/* try not losing precision (multiply then divide) */
-	imm32($r13, HW_TICKS_PER_US)
-	call #mulu32_32_64
-
-	/* use an immeditate, it's ok because HW_TICKS_PER_US < 16 bits */
-	div $r12 $r12 1000
-
-	/* check if there wasn't any overflow */
-	cmpu b32 $r11 0
-	bra e #ticks_from_ns_quit
-
-	/* let's divide then multiply, too bad for the precision! */
-	div $r14 $r14 1000
-	imm32($r13, HW_TICKS_PER_US)
-	call #mulu32_32_64
-
-	/* this cannot overflow as long as HW_TICKS_PER_US < 1000 */
-
-ticks_from_ns_quit:
-	mov b32 $r14 $r12
-	pop $r11
-	pop $r12
-	ret
-
-// calculate the number of ticks in the specified microsecond delay
-//
-// $r15 - current
-// $r14 - us
-// $r14 - ticks (return)
-// $r0  - zero
-ticks_from_us:
-	push $r12
-	push $r11
-
-	/* simply multiply $us by HW_TICKS_PER_US */
-	imm32($r13, HW_TICKS_PER_US)
-	call #mulu32_32_64
-	mov b32 $r14 $r12
-
-	/* check if there wasn't any overflow */
-	cmpu b32 $r11 0
-	bra e #ticks_from_us_quit
-
-	/* Overflow! */
-	clear b32 $r14
-
-ticks_from_us_quit:
-	pop $r11
-	pop $r12
-	ret
-
-// calculate the number of ticks in the specified microsecond delay
-//
-// $r15 - current
-// $r14 - ticks
-// $r14 - us (return)
-// $r0  - zero
-ticks_to_us:
-	/* simply divide $ticks by HW_TICKS_PER_US */
-	imm32($r13, HW_TICKS_PER_US)
-	div $r14 $r14 $r13
-
-	ret
-
-// request the current process be sent a message after a timeout expires
-//
-// $r15 - current
-// $r14 - ticks (make sure it is < 2^31 to avoid any possible overflow)
-// $r0  - zero
-timer:
-	push $r9
-	push $r8
-
-	// interrupts off to prevent racing with timer isr
-	bclr $flags ie0
-
-	// if current process already has a timer set, bail
-	ld b32 $r8 D[$r15 + #proc_time]
-	cmp b32 $r8 0
-	bra g #timer_done
-
-	// halt watchdog timer temporarily
-	clear b32 $r8
-	nv_iowr(NV_PPWR_WATCHDOG_ENABLE, $r8)
-
-	// find out how much time elapsed since the last update
-	// of the watchdog and add this time to the wanted ticks
-	nv_iord($r8, NV_PPWR_WATCHDOG_TIME)
-	ld b32 $r9 D[$r0 + #time_prev]
-	sub b32 $r9 $r8
-	add b32 $r14 $r9
-	st b32 D[$r15 + #proc_time] $r14
-
-	// check for a pending interrupt.  if there's one already
-	// pending, we can just bail since the timer isr will
-	// queue the next soonest right after it's done
-	nv_iord($r8, NV_PPWR_INTR)
-	and $r8 NV_PPWR_INTR_WATCHDOG
-	bra nz #timer_enable
-
-	// update the watchdog if this timer should expire first,
-	// or if there's no timeout already set
-	nv_iord($r8, NV_PPWR_WATCHDOG_TIME)
-	cmp b32 $r14 $r0
-	bra e #timer_reset
-	cmp b32 $r14 $r8
-	bra g #timer_enable
-		timer_reset:
-		nv_iowr(NV_PPWR_WATCHDOG_TIME, $r14)
-		st b32 D[$r0 + #time_prev] $r14
-
-	// re-enable the watchdog timer
-	timer_enable:
-	mov $r8 1
-	nv_iowr(NV_PPWR_WATCHDOG_ENABLE, $r8)
-
-	// interrupts back on
-	timer_done:
-	bset $flags ie0
-
-	pop $r8
-	pop $r9
-	ret
-
-// send message to another process
-//
-// $r15 - current
-// $r14 - process
-// $r13 - message
-// $r12 - message data 0
-// $r11 - message data 1
-// $r0  - zero
-send_proc:
-	push $r8
-	push $r9
-	// check for space in queue
-	ld b32 $r8 D[$r14 + #proc_qget]
-	ld b32 $r9 D[$r14 + #proc_qput]
-	xor $r8 #proc_qmaskb
-	cmp b32 $r8 $r9
-	bra e #send_done
-
-	// enqueue message
-	and $r8 $r9 #proc_qmaskp
-	shl b32 $r8 $r8 #proc_qlen
-	add b32 $r8 #proc_queue
-	add b32 $r8 $r14
-
-	ld b32 $r10 D[$r15 + #proc_id]
-	st b32 D[$r8 + #msg_process] $r10
-	st b32 D[$r8 + #msg_message] $r13
-	st b32 D[$r8 + #msg_data0] $r12
-	st b32 D[$r8 + #msg_data1] $r11
-
-	// increment PUT
-	add b32 $r9 1
-	and $r9 #proc_qmaskf
-	st b32 D[$r14 + #proc_qput] $r9
-	bset $flags $p2
-	send_done:
-	pop $r9
-	pop $r8
-	ret
-
-// lookup process structure by its name
-//
-// $r15 - current
-// $r14 - process name
-// $r0  - zero
-//
-// $r14 - process
-// $p1  - success
-find:
-	push $r8
-	mov $r8 #proc_list_head
-	bset $flags $p1
-	find_loop:
-		ld b32 $r10 D[$r8 + #proc_id]
-		cmp b32 $r10 $r14
-		bra e #find_done
-		add b32 $r8 #proc_size
-		cmp b32 $r8 #proc_list_tail
-		bra ne #find_loop
-		bclr $flags $p1
-	find_done:
-	mov b32 $r14 $r8
-	pop $r8
-	ret
-
-// send message to another process
-//
-// $r15 - current
-// $r14 - process id
-// $r13 - message
-// $r12 - message data 0
-// $r11 - message data 1
-// $r0  - zero
-send:
-	call(find)
-	bra $p1 #send_proc
-	ret
-
-// process single message for a given process
-//
-// $r15 - current
-// $r14 - process
-// $r0  - zero
-recv:
-	push $r9
-	push $r8
-
-	ld b32 $r8 D[$r14 + #proc_qget]
-	ld b32 $r9 D[$r14 + #proc_qput]
-	bclr $flags $p1
-	cmp b32 $r8 $r9
-	bra e #recv_done
-		// dequeue message
-		and $r9 $r8 #proc_qmaskp
-		add b32 $r8 1
-		and $r8 #proc_qmaskf
-		st b32 D[$r14 + #proc_qget] $r8
-		ld b32 $r10 D[$r14 + #proc_recv]
-
-		push $r15
-		mov $r15 $flags
-		push $r15
-		mov b32 $r15 $r14
-
-		shl b32 $r9 $r9 #proc_qlen
-		add b32 $r14 $r9
-		add b32 $r14 #proc_queue
-		ld b32 $r11 D[$r14 + #msg_data1]
-		ld b32 $r12 D[$r14 + #msg_data0]
-		ld b32 $r13 D[$r14 + #msg_message]
-		ld b32 $r14 D[$r14 + #msg_process]
-
-		// process it
-		call $r10
-		pop $r15
-		mov $flags $r15
-		bset $flags $p1
-		pop $r15
-	recv_done:
-	pop $r8
-	pop $r9
-	ret
-
-init:
-	// setup stack
-	nv_iord($r1, NV_PPWR_CAPS)
-	extr $r1 $r1 9:17
-	shl b32 $r1 8
-	mov $sp $r1
-
-#ifdef NVKM_FALCON_MMIO_UAS
-	// somehow allows the magic "access mmio via D[]" stuff that's
-	// used by the nv_rd32/nv_wr32 macros to work
-	mov $r1 0x0010
-	sethi $r1 NV_PPWR_UAS_CONFIG_ENABLE
-	nv_iowrs(NV_PPWR_UAS_CONFIG, $r1)
-#endif
-
-	// route all interrupts except user0/1 and pause to fuc
-	mov $r1 0x00e0
-	sethi $r1 0x00000000
-	nv_iowr(NV_PPWR_INTR_ROUTE, $r1)
-
-	// enable watchdog and subintr intrs
-	mov $r1 NV_PPWR_INTR_EN_CLR_MASK
-	nv_iowr(NV_PPWR_INTR_EN_CLR, $r1)
-	mov $r1 NV_PPWR_INTR_EN_SET_WATCHDOG
-	or $r1 NV_PPWR_INTR_EN_SET_SUBINTR
-	nv_iowr(NV_PPWR_INTR_EN_SET, $r1)
-
-	// enable interrupts globally
-	mov $r1 #intr
-	sethi $r1 0x00000000
-	mov $iv0 $r1
-	bset $flags ie0
-
-	// enable watchdog timer
-	mov $r1 1
-	nv_iowr(NV_PPWR_WATCHDOG_ENABLE, $r1)
-
-	// bootstrap processes, idle process will be last, and not return
-	mov $r15 #proc_list_head
-	init_proc:
-		ld b32 $r1 D[$r15 + #proc_init]
-		cmp b32 $r1 0
-		bra z #init_proc
-		call $r1
-		add b32 $r15 #proc_size
-		bra #init_proc
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc
deleted file mode 100644
index 96fc984dafdc..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#define GT215 0xa3
-#define GF100 0xc0
-#define GF119 0xd9
-#define GK208 0x108
-
-#include "os.h"
-
-// IO addresses
-#define NV_PPWR_INTR_TRIGGER                                             0x0000
-#define NV_PPWR_INTR_TRIGGER_USER1                                   0x00000080
-#define NV_PPWR_INTR_TRIGGER_USER0                                   0x00000040
-#define NV_PPWR_INTR_ACK                                                 0x0004
-#define NV_PPWR_INTR_ACK_SUBINTR                                     0x00000800
-#define NV_PPWR_INTR_ACK_WATCHDOG                                    0x00000002
-#define NV_PPWR_INTR                                                     0x0008
-#define NV_PPWR_INTR_SUBINTR                                         0x00000800
-#define NV_PPWR_INTR_USER1                                           0x00000080
-#define NV_PPWR_INTR_USER0                                           0x00000040
-#define NV_PPWR_INTR_PAUSE                                           0x00000020
-#define NV_PPWR_INTR_WATCHDOG                                        0x00000002
-#define NV_PPWR_INTR_EN_SET                                              0x0010
-#define NV_PPWR_INTR_EN_SET_SUBINTR                                  0x00000800
-#define NV_PPWR_INTR_EN_SET_WATCHDOG                                 0x00000002
-#define NV_PPWR_INTR_EN_CLR                                              0x0014
-#define NV_PPWR_INTR_EN_CLR_MASK                    /* fuck i hate envyas */ -1
-#define NV_PPWR_INTR_ROUTE                                               0x001c
-#define NV_PPWR_TIMER_LOW                                                0x002c
-#define NV_PPWR_WATCHDOG_TIME                                            0x0034
-#define NV_PPWR_WATCHDOG_ENABLE                                          0x0038
-#define NV_PPWR_CAPS                                                     0x0108
-#define NV_PPWR_UAS_CONFIG                                               0x0164
-#define NV_PPWR_UAS_CONFIG_ENABLE                                    0x00010000
-#if NVKM_PPWR_CHIPSET >= GK208
-#define NV_PPWR_DSCRATCH(i)                                   (4 * (i) + 0x0450)
-#endif
-#define NV_PPWR_FIFO_PUT(i)                                   (4 * (i) + 0x04a0)
-#define NV_PPWR_FIFO_GET(i)                                   (4 * (i) + 0x04b0)
-#define NV_PPWR_FIFO_INTR                                                0x04c0
-#define NV_PPWR_FIFO_INTR_EN                                             0x04c4
-#define NV_PPWR_RFIFO_PUT                                                0x04c8
-#define NV_PPWR_RFIFO_GET                                                0x04cc
-#define NV_PPWR_H2D                                                      0x04d0
-#define NV_PPWR_D2H                                                      0x04dc
-#if NVKM_PPWR_CHIPSET < GK208
-#define NV_PPWR_DSCRATCH(i)                                   (4 * (i) + 0x05d0)
-#endif
-#define NV_PPWR_SUBINTR                                                  0x0688
-#define NV_PPWR_SUBINTR_FIFO                                         0x00000002
-#define NV_PPWR_MMIO_ADDR                                                0x07a0
-#define NV_PPWR_MMIO_DATA                                                0x07a4
-#define NV_PPWR_MMIO_CTRL                                                0x07ac
-#define NV_PPWR_MMIO_CTRL_TRIGGER                                    0x00010000
-#define NV_PPWR_MMIO_CTRL_STATUS                                     0x00007000
-#define NV_PPWR_MMIO_CTRL_STATUS_IDLE                                0x00000000
-#define NV_PPWR_MMIO_CTRL_MASK                                       0x000000f0
-#define NV_PPWR_MMIO_CTRL_MASK_B32_0                                 0x000000f0
-#define NV_PPWR_MMIO_CTRL_OP                                         0x00000003
-#define NV_PPWR_MMIO_CTRL_OP_RD                                      0x00000001
-#define NV_PPWR_MMIO_CTRL_OP_WR                                      0x00000002
-#define NV_PPWR_OUTPUT                                                   0x07c0
-#define NV_PPWR_OUTPUT_FB_PAUSE                                      0x00000004
-#if NVKM_PPWR_CHIPSET < GF119
-#define NV_PPWR_OUTPUT_I2C_3_SCL                                     0x00000100
-#define NV_PPWR_OUTPUT_I2C_3_SDA                                     0x00000200
-#define NV_PPWR_OUTPUT_I2C_0_SCL                                     0x00001000
-#define NV_PPWR_OUTPUT_I2C_0_SDA                                     0x00002000
-#define NV_PPWR_OUTPUT_I2C_1_SCL                                     0x00004000
-#define NV_PPWR_OUTPUT_I2C_1_SDA                                     0x00008000
-#define NV_PPWR_OUTPUT_I2C_2_SCL                                     0x00010000
-#define NV_PPWR_OUTPUT_I2C_2_SDA                                     0x00020000
-#define NV_PPWR_OUTPUT_I2C_4_SCL                                     0x00040000
-#define NV_PPWR_OUTPUT_I2C_4_SDA                                     0x00080000
-#define NV_PPWR_OUTPUT_I2C_5_SCL                                     0x00100000
-#define NV_PPWR_OUTPUT_I2C_5_SDA                                     0x00200000
-#define NV_PPWR_OUTPUT_I2C_6_SCL                                     0x00400000
-#define NV_PPWR_OUTPUT_I2C_6_SDA                                     0x00800000
-#define NV_PPWR_OUTPUT_I2C_7_SCL                                     0x01000000
-#define NV_PPWR_OUTPUT_I2C_7_SDA                                     0x02000000
-#define NV_PPWR_OUTPUT_I2C_8_SCL                                     0x04000000
-#define NV_PPWR_OUTPUT_I2C_8_SDA                                     0x08000000
-#define NV_PPWR_OUTPUT_I2C_9_SCL                                     0x10000000
-#define NV_PPWR_OUTPUT_I2C_9_SDA                                     0x20000000
-#else
-#define NV_PPWR_OUTPUT_I2C_0_SCL                                     0x00000400
-#define NV_PPWR_OUTPUT_I2C_1_SCL                                     0x00000800
-#define NV_PPWR_OUTPUT_I2C_2_SCL                                     0x00001000
-#define NV_PPWR_OUTPUT_I2C_3_SCL                                     0x00002000
-#define NV_PPWR_OUTPUT_I2C_4_SCL                                     0x00004000
-#define NV_PPWR_OUTPUT_I2C_5_SCL                                     0x00008000
-#define NV_PPWR_OUTPUT_I2C_6_SCL                                     0x00010000
-#define NV_PPWR_OUTPUT_I2C_7_SCL                                     0x00020000
-#define NV_PPWR_OUTPUT_I2C_8_SCL                                     0x00040000
-#define NV_PPWR_OUTPUT_I2C_9_SCL                                     0x00080000
-#define NV_PPWR_OUTPUT_I2C_0_SDA                                     0x00100000
-#define NV_PPWR_OUTPUT_I2C_1_SDA                                     0x00200000
-#define NV_PPWR_OUTPUT_I2C_2_SDA                                     0x00400000
-#define NV_PPWR_OUTPUT_I2C_3_SDA                                     0x00800000
-#define NV_PPWR_OUTPUT_I2C_4_SDA                                     0x01000000
-#define NV_PPWR_OUTPUT_I2C_5_SDA                                     0x02000000
-#define NV_PPWR_OUTPUT_I2C_6_SDA                                     0x04000000
-#define NV_PPWR_OUTPUT_I2C_7_SDA                                     0x08000000
-#define NV_PPWR_OUTPUT_I2C_8_SDA                                     0x10000000
-#define NV_PPWR_OUTPUT_I2C_9_SDA                                     0x20000000
-#endif
-#define NV_PPWR_INPUT                                                    0x07c4
-#define NV_PPWR_OUTPUT_SET                                               0x07e0
-#define NV_PPWR_OUTPUT_SET_FB_PAUSE                                  0x00000004
-#define NV_PPWR_OUTPUT_CLR                                               0x07e4
-#define NV_PPWR_OUTPUT_CLR_FB_PAUSE                                  0x00000004
-
-// Inter-process message format
-.equ #msg_process 0x00 /* send() target, recv() sender */
-.equ #msg_message 0x04
-.equ #msg_data0   0x08
-.equ #msg_data1   0x0c
-
-// Kernel message IDs
-#define KMSG_FIFO  0x00000000
-#define KMSG_ALARM 0x00000001
-
-// Process message queue description
-.equ #proc_qlen 4 // log2(size of queue entry in bytes)
-.equ #proc_qnum 2 // log2(max number of entries in queue)
-.equ #proc_qmaskb (1 << #proc_qnum) // max number of entries in queue
-.equ #proc_qmaskp (#proc_qmaskb - 1)
-.equ #proc_qmaskf ((#proc_qmaskb << 1) - 1)
-.equ #proc_qsize  (1 << (#proc_qlen + #proc_qnum))
-
-// Process table entry
-.equ #proc_id    0x00
-.equ #proc_init  0x04
-.equ #proc_recv  0x08
-.equ #proc_time  0x0c
-.equ #proc_qput  0x10
-.equ #proc_qget  0x14
-.equ #proc_queue 0x18
-.equ #proc_size (0x18 + #proc_qsize)
-
-#define process(id,init,recv) /*
-*/	.b32 id /*
-*/	.b32 init /*
-*/	.b32 recv /*
-*/	.b32 0 /*
-*/	.b32 0 /*
-*/	.b32 0 /*
-*/	.skip 64
-
-#if NV_PPWR_CHIPSET < GK208
-#define imm32(reg,val) /*
-*/	movw reg  ((val) & 0x0000ffff) /*
-*/	sethi reg ((val) & 0xffff0000)
-#else
-#define imm32(reg,val) /*
-*/	mov reg (val)
-#endif
-
-#ifndef NVKM_FALCON_UNSHIFTED_IO
-#define nv_iord(reg,ior) /*
-*/	mov reg ior /*
-*/ 	shl b32 reg 6 /*
-*/ 	iord reg I[reg + 0x000]
-#else
-#define nv_iord(reg,ior) /*
-*/	mov reg ior /*
-*/ 	iord reg I[reg + 0x000]
-#endif
-
-#ifndef NVKM_FALCON_UNSHIFTED_IO
-#define nv_iowr(ior,reg) /*
-*/	mov $r0 ior /*
-*/ 	shl b32 $r0 6 /*
-*/ 	iowr I[$r0 + 0x000] reg /*
-*/	clear b32 $r0
-#else
-#define nv_iowr(ior,reg) /*
-*/	mov $r0 ior /*
-*/ 	iowr I[$r0 + 0x000] reg /*
-*/	clear b32 $r0
-#endif
-
-#ifndef NVKM_FALCON_UNSHIFTED_IO
-#define nv_iowrs(ior,reg) /*
-*/	mov $r0 ior /*
-*/ 	shl b32 $r0 6 /*
-*/ 	iowrs I[$r0 + 0x000] reg /*
-*/	clear b32 $r0
-#else
-#define nv_iowrs(ior,reg) /*
-*/	mov $r0 ior /*
-*/ 	iowrs I[$r0 + 0x000] reg /*
-*/	clear b32 $r0
-#endif
-
-#define hash #
-#define fn(a) a
-#ifndef NVKM_FALCON_PC24
-#define call(a) call fn(hash)a
-#else
-#define call(a) lcall fn(hash)a
-#endif
-
-#ifndef NVKM_FALCON_MMIO_UAS
-#define nv_rd32(reg,addr) /*
-*/	mov b32 $r14 addr /*
-*/	call(rd32) /*
-*/	mov b32 reg $r13
-#else
-#define nv_rd32(reg,addr) /*
-*/ 	sethi $r0 0x14000000 /*
-*/	or $r0 addr /*
-*/	ld b32 reg D[$r0] /*
-*/	clear b32 $r0
-#endif
-
-#if !defined(NVKM_FALCON_MMIO_UAS) || defined(NVKM_FALCON_MMIO_TRAP)
-#define nv_wr32(addr,reg) /*
-*/	push addr /*
-*/	push reg /*
-*/	pop $r13 /*
-*/	pop $r14 /*
-*/	call(wr32)
-#else
-#define nv_wr32(addr,reg) /*
-*/ 	sethi $r0 0x14000000 /*
-*/	or $r0 addr /*
-*/	st b32 D[$r0] reg /*
-*/	clear b32 $r0
-#endif
-
-#define st(size, addr, reg) /*
-*/	movw $r0 addr /*
-*/	st size D[$r0] reg /*
-*/	clear b32 $r0
-
-#define ld(size, reg, addr) /*
-*/	movw $r0 addr /*
-*/	ld size reg D[$r0] /*
-*/	clear b32 $r0
-
-// does a 64+64 -> 64 unsigned addition (C = A + B)
-#define addu64(reg_a_c_hi, reg_a_c_lo, b_hi, b_lo) /*
-*/    add b32 reg_a_c_lo b_lo /*
-*/    adc b32 reg_a_c_hi b_hi
-
-// does a 64+64 -> 64 substraction (C = A - B)
-#define subu64(reg_a_c_hi, reg_a_c_lo, b_hi, b_lo) /*
-*/    sub b32 reg_a_c_lo b_lo /*
-*/    sbb b32 reg_a_c_hi b_hi
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc
deleted file mode 100644
index ec03f9a4290b..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc
+++ /dev/null
@@ -1,447 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#ifdef INCLUDE_PROC
-process(PROC_MEMX, #memx_init, #memx_recv)
-#endif
-
-/******************************************************************************
- * MEMX data segment
- *****************************************************************************/
-#ifdef INCLUDE_DATA
-.equ #memx_opcode 0
-.equ #memx_header 2
-.equ #memx_length 4
-.equ #memx_func   8
-
-#define handler(cmd,hdr,len,func) /*
-*/	.b16 MEMX_##cmd /*
-*/	.b16 hdr /*
-*/	.b16 len /*
-*/      .b16 0 /*
-*/	.b32 func
-
-memx_func_head:
-handler(ENTER , 0x0000, 0x0000, #memx_func_enter)
-memx_func_next:
-handler(LEAVE , 0x0000, 0x0000, #memx_func_leave)
-handler(WR32  , 0x0000, 0x0002, #memx_func_wr32)
-handler(WAIT  , 0x0004, 0x0000, #memx_func_wait)
-handler(DELAY , 0x0001, 0x0000, #memx_func_delay)
-handler(VBLANK, 0x0001, 0x0000, #memx_func_wait_vblank)
-handler(TRAIN , 0x0000, 0x0000, #memx_func_train)
-memx_func_tail:
-
-.equ #memx_func_size #memx_func_next - #memx_func_head
-.equ #memx_func_num (#memx_func_tail - #memx_func_head) / #memx_func_size
-
-memx_ts_start:
-.b32 0
-memx_ts_end:
-.b32 0
-
-memx_data_head:
-.skip 0x0800
-memx_data_tail:
-
-memx_train_head:
-.skip 0x0100
-memx_train_tail:
-#endif
-
-/******************************************************************************
- * MEMX code segment
- *****************************************************************************/
-#ifdef INCLUDE_CODE
-// description
-//
-// $r15 - current (memx)
-// $r4  - packet length
-// $r3  - opcode desciption
-// $r0  - zero
-memx_func_enter:
-#if NVKM_PPWR_CHIPSET == GT215
-	movw $r8 0x1610
-	nv_rd32($r7, $r8)
-	imm32($r6, 0xfffffffc)
-	and $r7 $r6
-	movw $r6 0x2
-	or $r7 $r6
-	nv_wr32($r8, $r7)
-#else
-	movw $r6 0x001620
-	imm32($r7, ~0x00000aa2);
-	nv_rd32($r8, $r6)
-	and $r8 $r7
-	nv_wr32($r6, $r8)
-
-	imm32($r7, ~0x00000001)
-	nv_rd32($r8, $r6)
-	and $r8 $r7
-	nv_wr32($r6, $r8)
-
-	movw $r6 0x0026f0
-	nv_rd32($r8, $r6)
-	and $r8 $r7
-	nv_wr32($r6, $r8)
-#endif
-
-	mov $r6 NV_PPWR_OUTPUT_SET_FB_PAUSE
-	nv_iowr(NV_PPWR_OUTPUT_SET, $r6)
-	memx_func_enter_wait:
-		nv_iord($r6, NV_PPWR_OUTPUT)
-		and $r6 NV_PPWR_OUTPUT_FB_PAUSE
-		bra z #memx_func_enter_wait
-
-	nv_iord($r6, NV_PPWR_TIMER_LOW)
-	st b32 D[$r0 + #memx_ts_start] $r6
-	ret
-
-// description
-//
-// $r15 - current (memx)
-// $r4  - packet length
-// $r3  - opcode desciption
-// $r0  - zero
-memx_func_leave:
-	nv_iord($r6, NV_PPWR_TIMER_LOW)
-	st b32 D[$r0 + #memx_ts_end] $r6
-
-	mov $r6 NV_PPWR_OUTPUT_CLR_FB_PAUSE
-	nv_iowr(NV_PPWR_OUTPUT_CLR, $r6)
-	memx_func_leave_wait:
-		nv_iord($r6, NV_PPWR_OUTPUT)
-		and $r6 NV_PPWR_OUTPUT_FB_PAUSE
-		bra nz #memx_func_leave_wait
-
-#if NVKM_PPWR_CHIPSET == GT215
-	movw $r8 0x1610
-	nv_rd32($r7, $r8)
-	imm32($r6, 0xffffffcc)
-	and $r7 $r6
-	nv_wr32($r8, $r7)
-#else
-	movw $r6 0x0026f0
-	imm32($r7, 0x00000001)
-	nv_rd32($r8, $r6)
-	or $r8 $r7
-	nv_wr32($r6, $r8)
-
-	movw $r6 0x001620
-	nv_rd32($r8, $r6)
-	or $r8 $r7
-	nv_wr32($r6, $r8)
-
-	imm32($r7, 0x00000aa2);
-	nv_rd32($r8, $r6)
-	or $r8 $r7
-	nv_wr32($r6, $r8)
-#endif
-	ret
-
-#if NVKM_PPWR_CHIPSET < GF119
-// description
-//
-// $r15 - current (memx)
-// $r4  - packet length
-//	+00: head to wait for vblank on
-// $r3  - opcode desciption
-// $r0  - zero
-memx_func_wait_vblank:
-	ld b32 $r6 D[$r1 + 0x00]
-	cmp b32 $r6 0x0
-	bra z #memx_func_wait_vblank_head0
-	cmp b32 $r6 0x1
-	bra z #memx_func_wait_vblank_head1
-	bra #memx_func_wait_vblank_fini
-
-	memx_func_wait_vblank_head1:
-	movw $r7 0x20
-	bra #memx_func_wait_vblank_0
-
-	memx_func_wait_vblank_head0:
-	movw $r7 0x8
-
-	memx_func_wait_vblank_0:
-		nv_iord($r6, NV_PPWR_INPUT)
-		and $r6 $r7
-		bra nz #memx_func_wait_vblank_0
-
-	memx_func_wait_vblank_1:
-		nv_iord($r6, NV_PPWR_INPUT)
-		and $r6 $r7
-		bra z #memx_func_wait_vblank_1
-
-	memx_func_wait_vblank_fini:
-	add b32 $r1 0x4
-	ret
-
-#else
-
-// XXX: currently no-op
-//
-// $r15 - current (memx)
-// $r4  - packet length
-//	+00: head to wait for vblank on
-// $r3  - opcode desciption
-// $r0  - zero
-memx_func_wait_vblank:
-	add b32 $r1 0x4
-	ret
-
-#endif
-
-// description
-//
-// $r15 - current (memx)
-// $r4  - packet length
-//	+00*n: addr
-//	+04*n: data
-// $r3  - opcode desciption
-// $r0  - zero
-memx_func_wr32:
-	ld b32 $r6 D[$r1 + 0x00]
-	ld b32 $r5 D[$r1 + 0x04]
-	add b32 $r1 0x08
-	nv_wr32($r6, $r5)
-	sub b32 $r4 0x02
-	bra nz #memx_func_wr32
-	ret
-
-// description
-//
-// $r15 - current (memx)
-// $r4  - packet length
-//	+00: addr
-//	+04: mask
-//	+08: data
-//	+0c: timeout (ns)
-// $r3  - opcode desciption
-// $r0  - zero
-memx_func_wait:
-	nv_iord($r8, NV_PPWR_TIMER_LOW)
-	ld b32 $r14 D[$r1 + 0x00]
-	ld b32 $r13 D[$r1 + 0x04]
-	ld b32 $r12 D[$r1 + 0x08]
-	ld b32 $r11 D[$r1 + 0x0c]
-	add b32 $r1 0x10
-	call(wait)
-	ret
-
-// description
-//
-// $r15 - current (memx)
-// $r4  - packet length
-//	+00: time (ns)
-// $r3  - opcode desciption
-// $r0  - zero
-memx_func_delay:
-	ld b32 $r14 D[$r1 + 0x00]
-	add b32 $r1 0x04
-	call(nsec)
-	ret
-
-// description
-//
-// $r15 - current (memx)
-// $r4  - packet length
-// $r3  - opcode desciption
-// $r0  - zero
-memx_func_train:
-#if NVKM_PPWR_CHIPSET == GT215
-// $r5 - outer loop counter
-// $r6 - inner loop counter
-// $r7 - entry counter (#memx_train_head + $r7)
-	movw $r5 0x3
-	movw $r7 0x0
-
-// Read random memory to wake up... things
-	imm32($r9, 0x700000)
-	nv_rd32($r8,$r9)
-	movw $r14 0x2710
-	call(nsec)
-
-	memx_func_train_loop_outer:
-		mulu $r8 $r5 0x101
-		sethi $r8 0x02000000
-		imm32($r9, 0x1111e0)
-		nv_wr32($r9, $r8)
-		push $r5
-
-		movw $r6 0x0
-		memx_func_train_loop_inner:
-			movw $r8 0x1111
-			mulu $r9 $r6 $r8
-			shl b32 $r8 $r9 0x10
-			or $r8 $r9
-			imm32($r9, 0x100720)
-			nv_wr32($r9, $r8)
-
-			imm32($r9, 0x100080)
-			nv_rd32($r8, $r9)
-			or $r8 $r8 0x20
-			nv_wr32($r9, $r8)
-
-			imm32($r9, 0x10053c)
-			imm32($r8, 0x80003002)
-			nv_wr32($r9, $r8)
-
-			imm32($r14, 0x100560)
-			imm32($r13, 0x80000000)
-			add b32 $r12 $r13 0
-			imm32($r11, 0x001e8480)
-			call(wait)
-
-			// $r5 - inner inner loop counter
-			// $r9 - result
-			movw $r5 0
-			imm32($r9, 0x8300ffff)
-			memx_func_train_loop_4x:
-				imm32($r10, 0x100080)
-				nv_rd32($r8, $r10)
-				imm32($r11, 0xffffffdf)
-				and $r8 $r11
-				nv_wr32($r10, $r8)
-
-				imm32($r10, 0x10053c)
-				imm32($r8, 0x80003002)
-				nv_wr32($r10, $r8)
-
-				imm32($r14, 0x100560)
-				imm32($r13, 0x80000000)
-				mov b32 $r12 $r13
-				imm32($r11, 0x00002710)
-				call(wait)
-
-				nv_rd32($r13, $r14)
-				and $r9 $r9 $r13
-
-				add b32 $r5 1
-				cmp b16 $r5 0x4
-				bra l #memx_func_train_loop_4x
-
-			add b32 $r10 $r7 #memx_train_head
-			st b32 D[$r10 + 0] $r9
-			add b32 $r6 1
-			add b32 $r7 4
-
-			cmp b16 $r6 0x10
-			bra l #memx_func_train_loop_inner
-
-		pop $r5
-		add b32 $r5 1
-		cmp b16 $r5 7
-		bra l #memx_func_train_loop_outer
-
-#endif
-	ret
-
-// description
-//
-// $r15 - current (memx)
-// $r14 - sender process name
-// $r13 - message (exec)
-// $r12 - head of script
-// $r11 - tail of script
-// $r0  - zero
-memx_exec:
-	push $r14
-	push $r13
-	mov b32 $r1 $r12
-	mov b32 $r2 $r11
-
-	memx_exec_next:
-		// fetch the packet header
-		ld b32 $r3 D[$r1]
-		add b32 $r1 4
-		extr $r4 $r3 16:31
-		extr $r3 $r3 0:15
-
-		// execute the opcode handler
-		sub b32 $r3 1
-		mulu $r3 #memx_func_size
-		ld b32 $r5 D[$r3 + #memx_func_head + #memx_func]
-		call $r5
-
-		// keep going, if we haven't reached the end
-		cmp b32 $r1 $r2
-		bra l #memx_exec_next
-
-	// send completion reply
-	ld b32 $r11 D[$r0 + #memx_ts_start]
-	ld b32 $r12 D[$r0 + #memx_ts_end]
-	sub b32 $r12 $r11
-	nv_iord($r11, NV_PPWR_INPUT)
-	pop $r13
-	pop $r14
-	call(send)
-	ret
-
-// description
-//
-// $r15 - current (memx)
-// $r14 - sender process name
-// $r13 - message
-// $r12 - data0
-// $r11 - data1
-// $r0  - zero
-memx_info:
-	cmp b16 $r12 0x1
-	bra e #memx_info_train
-
-	memx_info_data:
-	mov $r12 #memx_data_head
-	mov $r11 #memx_data_tail - #memx_data_head
-	bra #memx_info_send
-
-	memx_info_train:
-	mov $r12 #memx_train_head
-	mov $r11 #memx_train_tail - #memx_train_head
-
-	memx_info_send:
-	call(send)
-	ret
-
-// description
-//
-// $r15 - current (memx)
-// $r14 - sender process name
-// $r13 - message
-// $r12 - data0
-// $r11 - data1
-// $r0  - zero
-memx_recv:
-	cmp b32 $r13 MEMX_MSG_EXEC
-	bra e #memx_exec
-	cmp b32 $r13 MEMX_MSG_INFO
-	bra e #memx_info
-	ret
-
-// description
-//
-// $r15 - current (memx)
-// $r0  - zero
-memx_init:
-	ret
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc
deleted file mode 100644
index b439519ec866..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#define NVKM_PPWR_CHIPSET GK208
-#define HW_TICKS_PER_US 324
-
-#define NVKM_FALCON_PC24
-#define NVKM_FALCON_UNSHIFTED_IO
-//#define NVKM_FALCON_MMIO_UAS
-//#define NVKM_FALCON_MMIO_TRAP
-
-#include "macros.fuc"
-
-.section #nv108_pwr_data
-#define INCLUDE_PROC
-#include "kernel.fuc"
-#include "arith.fuc"
-#include "host.fuc"
-#include "memx.fuc"
-#include "perf.fuc"
-#include "i2c_.fuc"
-#include "test.fuc"
-#include "idle.fuc"
-#undef INCLUDE_PROC
-
-#define INCLUDE_DATA
-#include "kernel.fuc"
-#include "arith.fuc"
-#include "host.fuc"
-#include "memx.fuc"
-#include "perf.fuc"
-#include "i2c_.fuc"
-#include "test.fuc"
-#include "idle.fuc"
-#undef INCLUDE_DATA
-.align 256
-
-.section #nv108_pwr_code
-#define INCLUDE_CODE
-#include "kernel.fuc"
-#include "arith.fuc"
-#include "host.fuc"
-#include "memx.fuc"
-#include "perf.fuc"
-#include "i2c_.fuc"
-#include "test.fuc"
-#include "idle.fuc"
-#undef INCLUDE_CODE
-.align 256
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
deleted file mode 100644
index 713e11e2953d..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
+++ /dev/null
@@ -1,1731 +0,0 @@
-uint32_t nv108_pwr_data[] = {
-/* 0x0000: proc_kern */
-	0x52544e49,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0058: proc_list_head */
-	0x54534f48,
-	0x00000453,
-	0x00000404,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x584d454d,
-	0x0000062d,
-	0x0000061f,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x46524550,
-	0x00000631,
-	0x0000062f,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x5f433249,
-	0x00000a35,
-	0x000008dc,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x54534554,
-	0x00000a56,
-	0x00000a37,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x454c4449,
-	0x00000a61,
-	0x00000a5f,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0268: proc_list_tail */
-/* 0x0268: time_prev */
-	0x00000000,
-/* 0x026c: time_next */
-	0x00000000,
-/* 0x0270: fifo_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x02f0: rfifo_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0370: memx_func_head */
-	0x00000001,
-	0x00000000,
-	0x00000483,
-/* 0x037c: memx_func_next */
-	0x00000002,
-	0x00000000,
-	0x00000500,
-	0x00000003,
-	0x00000002,
-	0x00000580,
-	0x00040004,
-	0x00000000,
-	0x0000059d,
-	0x00010005,
-	0x00000000,
-	0x000005b7,
-	0x00010006,
-	0x00000000,
-	0x0000057b,
-	0x00000007,
-	0x00000000,
-	0x000005c3,
-/* 0x03c4: memx_func_tail */
-/* 0x03c4: memx_ts_start */
-	0x00000000,
-/* 0x03c8: memx_ts_end */
-	0x00000000,
-/* 0x03cc: memx_data_head */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0bcc: memx_data_tail */
-/* 0x0bcc: memx_train_head */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0ccc: memx_train_tail */
-/* 0x0ccc: i2c_scl_map */
-	0x00000400,
-	0x00000800,
-	0x00001000,
-	0x00002000,
-	0x00004000,
-	0x00008000,
-	0x00010000,
-	0x00020000,
-	0x00040000,
-	0x00080000,
-/* 0x0cf4: i2c_sda_map */
-	0x00100000,
-	0x00200000,
-	0x00400000,
-	0x00800000,
-	0x01000000,
-	0x02000000,
-	0x04000000,
-	0x08000000,
-	0x10000000,
-	0x20000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-uint32_t nv108_pwr_code[] = {
-	0x031c0ef5,
-/* 0x0004: rd32 */
-	0xf607a040,
-	0x04bd000e,
-	0xd3f0010d,
-	0x07ac4001,
-	0xbd000df6,
-/* 0x0019: rd32_wait */
-	0x07ac4d04,
-	0xf100ddcf,
-	0xf47000d4,
-	0xa44df61b,
-	0x00ddcf07,
-/* 0x002e: wr32 */
-	0xa04000f8,
-	0x000ef607,
-	0xa44004bd,
-	0x000df607,
-	0x020d04bd,
-	0xf0f0d5f0,
-	0xac4001d3,
-	0x000df607,
-/* 0x004e: wr32_wait */
-	0xac4d04bd,
-	0x00ddcf07,
-	0x7000d4f1,
-	0xf8f61bf4,
-/* 0x005d: nsec */
-	0xf990f900,
-	0xcf2c0880,
-/* 0x0066: nsec_loop */
-	0x2c090088,
-	0xbb0099cf,
-	0x9ea60298,
-	0xfcf61ef4,
-	0xf890fc80,
-/* 0x0079: wait */
-	0xf990f900,
-	0xcf2c0880,
-/* 0x0082: wait_loop */
-	0xeeb20088,
-	0x0000047e,
-	0xadfddab2,
-	0xf4aca604,
-	0x2c09100b,
-	0xbb0099cf,
-	0x9ba60298,
-/* 0x009f: wait_done */
-	0xfce61ef4,
-	0xf890fc80,
-/* 0x00a5: intr_watchdog */
-	0x03e99800,
-	0xf40096b0,
-	0x0a98280b,
-	0x029abb9a,
-	0x0d0e1cf4,
-	0x02617e01,
-	0xf494bd00,
-/* 0x00c2: intr_watchdog_next_time */
-	0x0a98140e,
-	0x00a6b09b,
-	0xa6080bf4,
-	0x061cf49a,
-/* 0x00d0: intr_watchdog_next_time_set */
-/* 0x00d3: intr_watchdog_next_proc */
-	0xb59b09b5,
-	0xe0b603e9,
-	0x68e6b158,
-	0xc81bf402,
-/* 0x00e2: intr */
-	0x00f900f8,
-	0x80f904bd,
-	0xa0f990f9,
-	0xc0f9b0f9,
-	0xe0f9d0f9,
-	0x000ff0f9,
-	0xf90188fe,
-	0x04504880,
-	0xb60088cf,
-	0x50400180,
-	0x0008f604,
-	0x080804bd,
-	0xc40088cf,
-	0x0bf40289,
-	0x9b00b51f,
-	0xa57e580e,
-	0x09980000,
-	0x0096b09b,
-	0x000d0bf4,
-	0x0009f634,
-	0x09b504bd,
-/* 0x0135: intr_skip_watchdog */
-	0x0089e49a,
-	0x360bf408,
-	0xcf068849,
-	0x9ac40099,
-	0x220bf402,
-	0xcf04c04c,
-	0xc0f900cc,
-	0xf14f484e,
-	0x0d5453e3,
-	0x02c27e00,
-	0x40c0fc00,
-	0x0cf604c0,
-/* 0x0167: intr_subintr_skip_fifo */
-	0x4004bd00,
-	0x09f60688,
-/* 0x016f: intr_skip_subintr */
-	0xc404bd00,
-	0x0bf42089,
-	0xbfa4f107,
-/* 0x0179: intr_skip_pause */
-	0x4089c4ff,
-	0xf1070bf4,
-/* 0x0183: intr_skip_user0 */
-	0x00ffbfa4,
-	0x0008f604,
-	0x80fc04bd,
-	0xfc0088fe,
-	0xfce0fcf0,
-	0xfcc0fcd0,
-	0xfca0fcb0,
-	0xfc80fc90,
-	0x0032f400,
-/* 0x01a6: ticks_from_ns */
-	0xc0f901f8,
-	0xd7f1b0f9,
-	0xd3f00144,
-	0x7721f500,
-	0xe8ccec03,
-	0x00b4b003,
-	0xec120bf4,
-	0xf103e8ee,
-	0xf00144d7,
-	0x21f500d3,
-/* 0x01ce: ticks_from_ns_quit */
-	0xceb20377,
-	0xc0fcb0fc,
-/* 0x01d6: ticks_from_us */
-	0xc0f900f8,
-	0xd7f1b0f9,
-	0xd3f00144,
-	0x7721f500,
-	0xb0ceb203,
-	0x0bf400b4,
-/* 0x01ef: ticks_from_us_quit */
-	0xfce4bd05,
-	0xf8c0fcb0,
-/* 0x01f5: ticks_to_us */
-	0x44d7f100,
-	0x00d3f001,
-	0xf8ecedff,
-/* 0x0201: timer */
-	0xf990f900,
-	0x1032f480,
-	0xb003f898,
-	0x1cf40086,
-	0x0084bd4a,
-	0x0008f638,
-	0x340804bd,
-	0x980088cf,
-	0x98bb9a09,
-	0x00e9bb02,
-	0x0803feb5,
-	0x0088cf08,
-	0xf40284f0,
-	0x34081c1b,
-	0xa60088cf,
-	0x080bf4e0,
-	0x1cf4e8a6,
-/* 0x0245: timer_reset */
-	0xf634000d,
-	0x04bd000e,
-/* 0x024f: timer_enable */
-	0x089a0eb5,
-	0xf6380001,
-	0x04bd0008,
-/* 0x0258: timer_done */
-	0xfc1031f4,
-	0xf890fc80,
-/* 0x0261: send_proc */
-	0xf980f900,
-	0x05e89890,
-	0xf004e998,
-	0x89a60486,
-	0xc42a0bf4,
-	0x88940398,
-	0x1880b604,
-	0x98008ebb,
-	0x8ab500fa,
-	0x018db500,
-	0xb5028cb5,
-	0x90b6038b,
-	0x0794f001,
-	0xf404e9b5,
-/* 0x029a: send_done */
-	0x90fc0231,
-	0x00f880fc,
-/* 0x02a0: find */
-	0x580880f9,
-/* 0x02a7: find_loop */
-	0x980131f4,
-	0xaea6008a,
-	0xb6100bf4,
-	0x86b15880,
-	0x1bf40268,
-	0x0132f4f1,
-/* 0x02bc: find_done */
-	0x80fc8eb2,
-/* 0x02c2: send */
-	0xa07e00f8,
-	0x01f40002,
-/* 0x02cb: recv */
-	0xf900f89b,
-	0x9880f990,
-	0xe99805e8,
-	0x0132f404,
-	0x0bf489a6,
-	0x0389c43c,
-	0xf00180b6,
-	0xe8b50784,
-	0x02ea9805,
-	0x8ffef0f9,
-	0xb2f0f901,
-	0x049994ef,
-	0xb600e9bb,
-	0xeb9818e0,
-	0x02ec9803,
-	0x9801ed98,
-	0xa5f900ee,
-	0xf8fef0fc,
-	0x0131f400,
-/* 0x0316: recv_done */
-	0x80fcf0fc,
-	0x00f890fc,
-/* 0x031c: init */
-	0xcf010841,
-	0x11e70011,
-	0x14b60109,
-	0x0014fe08,
-	0xf000e041,
-	0x1c000013,
-	0xbd0001f6,
-	0x00ff0104,
-	0x0001f614,
-	0x020104bd,
-	0x080015f1,
-	0x01f61000,
-	0x4104bd00,
-	0x13f000e2,
-	0x0010fe00,
-	0x011031f4,
-	0xf6380001,
-	0x04bd0001,
-/* 0x0366: init_proc */
-	0xf198580f,
-	0x0016b001,
-	0xf9fa0bf4,
-	0x58f0b615,
-/* 0x0377: mulu32_32_64 */
-	0xf9f20ef4,
-	0xf920f910,
-	0x9540f930,
-	0xd29510e1,
-	0xbdc4bd10,
-	0xc0edffb4,
-	0xb2301dff,
-	0xff34f134,
-	0x1034b6ff,
-	0xbb1045b6,
-	0xb4bb00c3,
-	0x30e2ff01,
-	0x34f134b2,
-	0x34b6ffff,
-	0x1045b610,
-	0xbb00c3bb,
-	0x12ff01b4,
-	0x00b3bb30,
-	0x30fc40fc,
-	0x10fc20fc,
-/* 0x03c6: host_send */
-	0xb04100f8,
-	0x0011cf04,
-	0xcf04a042,
-	0x12a60022,
-	0xc42e0bf4,
-	0xee94071e,
-	0x70e0b704,
-	0x03eb9802,
-	0x9802ec98,
-	0xee9801ed,
-	0x02c27e00,
-	0x0110b600,
-	0x400f1ec4,
-	0x0ef604b0,
-	0xf404bd00,
-/* 0x0402: host_send_done */
-	0x00f8c70e,
-/* 0x0404: host_recv */
-	0xf14e4941,
-	0xa6525413,
-	0xb90bf4e1,
-/* 0x0410: host_recv_wait */
-	0xcf04cc41,
-	0xc8420011,
-	0x0022cf04,
-	0xa60816f0,
-	0xef0bf412,
-	0xb60723c4,
-	0x30b70434,
-	0x3bb502f0,
-	0x023cb503,
-	0xb5013db5,
-	0x20b6003e,
-	0x0f24f001,
-	0xf604c840,
-	0x04bd0002,
-	0x00004002,
-	0xbd0002f6,
-/* 0x0453: host_init */
-	0x4100f804,
-	0x14b60080,
-	0x7015f110,
-	0x04d04002,
-	0xbd0001f6,
-	0x00804104,
-	0xf11014b6,
-	0x4002f015,
-	0x01f604dc,
-	0x0104bd00,
-	0x04c44001,
-	0xbd0001f6,
-/* 0x0483: memx_func_enter */
-	0xf100f804,
-	0xf1162067,
-	0xf1f55d77,
-	0xb2ffff73,
-	0x00047e6e,
-	0xfdd8b200,
-	0x60f90487,
-	0xd0fc80f9,
-	0x2e7ee0fc,
-	0x77f10000,
-	0x73f1fffe,
-	0x6eb2ffff,
-	0x0000047e,
-	0x87fdd8b2,
-	0xf960f904,
-	0xfcd0fc80,
-	0x002e7ee0,
-	0xf067f100,
-	0x7e6eb226,
-	0xb2000004,
-	0x0487fdd8,
-	0x80f960f9,
-	0xe0fcd0fc,
-	0x00002e7e,
-	0xe0400406,
-	0x0006f607,
-/* 0x04ea: memx_func_enter_wait */
-	0xc04604bd,
-	0x0066cf07,
-	0xf40464f0,
-	0x2c06f70b,
-	0xb50066cf,
-	0x00f8f106,
-/* 0x0500: memx_func_leave */
-	0x66cf2c06,
-	0xf206b500,
-	0xe4400406,
-	0x0006f607,
-/* 0x0512: memx_func_leave_wait */
-	0xc04604bd,
-	0x0066cf07,
-	0xf40464f0,
-	0x67f1f71b,
-	0x77f126f0,
-	0x73f00001,
-	0x7e6eb200,
-	0xb2000004,
-	0x0587fdd8,
-	0x80f960f9,
-	0xe0fcd0fc,
-	0x00002e7e,
-	0x162067f1,
-	0x047e6eb2,
-	0xd8b20000,
-	0xf90587fd,
-	0xfc80f960,
-	0x7ee0fcd0,
-	0xf100002e,
-	0xf00aa277,
-	0x6eb20073,
-	0x0000047e,
-	0x87fdd8b2,
-	0xf960f905,
-	0xfcd0fc80,
-	0x002e7ee0,
-/* 0x057b: memx_func_wait_vblank */
-	0xb600f800,
-	0x00f80410,
-/* 0x0580: memx_func_wr32 */
-	0x98001698,
-	0x10b60115,
-	0xf960f908,
-	0xfcd0fc50,
-	0x002e7ee0,
-	0x0242b600,
-	0xf8e81bf4,
-/* 0x059d: memx_func_wait */
-	0xcf2c0800,
-	0x1e980088,
-	0x011d9800,
-	0x98021c98,
-	0x10b6031b,
-	0x00797e10,
-/* 0x05b7: memx_func_delay */
-	0x9800f800,
-	0x10b6001e,
-	0x005d7e04,
-/* 0x05c3: memx_func_train */
-	0xf800f800,
-/* 0x05c5: memx_exec */
-	0xf9e0f900,
-	0xb2c1b2d0,
-/* 0x05cd: memx_exec_next */
-	0x001398b2,
-	0xe70410b6,
-	0xe701f034,
-	0xb601e033,
-	0x30f00132,
-	0xde35980c,
-	0x12a655f9,
-	0x98e51ef4,
-	0x0c98f10b,
-	0x02cbbbf2,
-	0xcf07c44b,
-	0xd0fc00bb,
-	0xc27ee0fc,
-	0x00f80002,
-/* 0x0604: memx_info */
-	0xf401c670,
-/* 0x060a: memx_info_data */
-	0xcc4c0c0b,
-	0x08004b03,
-/* 0x0613: memx_info_train */
-	0x4c090ef4,
-	0x004b0bcc,
-/* 0x0619: memx_info_send */
-	0x02c27e01,
-/* 0x061f: memx_recv */
-	0xb000f800,
-	0x0bf401d6,
-	0x00d6b0a3,
-	0xf8dc0bf4,
-/* 0x062d: memx_init */
-/* 0x062f: perf_recv */
-	0xf800f800,
-/* 0x0631: perf_init */
-/* 0x0633: i2c_drive_scl */
-	0xb000f800,
-	0x0bf40036,
-	0x07e0400d,
-	0xbd0001f6,
-/* 0x0643: i2c_drive_scl_lo */
-	0x4000f804,
-	0x01f607e4,
-	0xf804bd00,
-/* 0x064d: i2c_drive_sda */
-	0x0036b000,
-	0x400d0bf4,
-	0x02f607e0,
-	0xf804bd00,
-/* 0x065d: i2c_drive_sda_lo */
-	0x07e44000,
-	0xbd0002f6,
-/* 0x0667: i2c_sense_scl */
-	0xf400f804,
-	0xc4430132,
-	0x0033cf07,
-	0xf40431fd,
-	0x31f4060b,
-/* 0x0679: i2c_sense_scl_done */
-/* 0x067b: i2c_sense_sda */
-	0xf400f801,
-	0xc4430132,
-	0x0033cf07,
-	0xf40432fd,
-	0x31f4060b,
-/* 0x068d: i2c_sense_sda_done */
-/* 0x068f: i2c_raise_scl */
-	0xf900f801,
-	0x08984440,
-	0x337e0103,
-/* 0x069a: i2c_raise_scl_wait */
-	0xe84e0006,
-	0x005d7e03,
-	0x06677e00,
-	0x0901f400,
-	0xf40142b6,
-/* 0x06ae: i2c_raise_scl_done */
-	0x40fcef1b,
-/* 0x06b2: i2c_start */
-	0x677e00f8,
-	0x11f40006,
-	0x067b7e0d,
-	0x0611f400,
-/* 0x06c3: i2c_start_rep */
-	0x032e0ef4,
-	0x06337e00,
-	0x7e010300,
-	0xbb00064d,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x00068f7e,
-	0xf40464b6,
-/* 0x06ee: i2c_start_send */
-	0x00031d11,
-	0x00064d7e,
-	0x7e13884e,
-	0x0300005d,
-	0x06337e00,
-	0x13884e00,
-	0x00005d7e,
-/* 0x0708: i2c_start_out */
-/* 0x070a: i2c_stop */
-	0x000300f8,
-	0x0006337e,
-	0x4d7e0003,
-	0xe84e0006,
-	0x005d7e03,
-	0x7e010300,
-	0x4e000633,
-	0x5d7e1388,
-	0x01030000,
-	0x00064d7e,
-	0x7e13884e,
-	0xf800005d,
-/* 0x0739: i2c_bitw */
-	0x064d7e00,
-	0x03e84e00,
-	0x00005d7e,
-	0xb60076bb,
-	0x50f90465,
-	0xbb046594,
-	0x50bd0256,
-	0xfc0475fd,
-	0x068f7e50,
-	0x0464b600,
-	0x4e1711f4,
-	0x5d7e1388,
-	0x00030000,
-	0x0006337e,
-	0x7e13884e,
-/* 0x0777: i2c_bitw_out */
-	0xf800005d,
-/* 0x0779: i2c_bitr */
-	0x7e010300,
-	0x4e00064d,
-	0x5d7e03e8,
-	0x76bb0000,
-	0x0465b600,
-	0x659450f9,
-	0x0256bb04,
-	0x75fd50bd,
-	0x7e50fc04,
-	0xb600068f,
-	0x11f40464,
-	0x067b7e1a,
-	0x7e000300,
-	0x4e000633,
-	0x5d7e1388,
-	0x3cf00000,
-	0x0131f401,
-/* 0x07bc: i2c_bitr_done */
-/* 0x07be: i2c_get_byte */
-	0x000500f8,
-/* 0x07c2: i2c_get_byte_next */
-	0x54b60804,
-	0x0076bb01,
-	0xf90465b6,
-	0x04659450,
-	0xbd0256bb,
-	0x0475fd50,
-	0x797e50fc,
-	0x64b60007,
-	0x2a11f404,
-	0xb60553fd,
-	0x1bf40142,
-	0xbb0103d8,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x0007397e,
-/* 0x080b: i2c_get_byte_done */
-	0xf80464b6,
-/* 0x080d: i2c_put_byte */
-/* 0x080f: i2c_put_byte_next */
-	0xb6080400,
-	0x54ff0142,
-	0x0076bb38,
-	0xf90465b6,
-	0x04659450,
-	0xbd0256bb,
-	0x0475fd50,
-	0x397e50fc,
-	0x64b60007,
-	0x3411f404,
-	0xf40046b0,
-	0x76bbd81b,
-	0x0465b600,
-	0x659450f9,
-	0x0256bb04,
-	0x75fd50bd,
-	0x7e50fc04,
-	0xb6000779,
-	0x11f40464,
-	0x0076bb0f,
-	0xf40136b0,
-	0x32f4061b,
-/* 0x0865: i2c_put_byte_done */
-/* 0x0867: i2c_addr */
-	0xbb00f801,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x0006b27e,
-	0xf40464b6,
-	0xc3e72911,
-	0x34b6012e,
-	0x0553fd01,
-	0xb60076bb,
-	0x50f90465,
-	0xbb046594,
-	0x50bd0256,
-	0xfc0475fd,
-	0x080d7e50,
-	0x0464b600,
-/* 0x08ac: i2c_addr_done */
-/* 0x08ae: i2c_acquire_addr */
-	0xcec700f8,
-	0x05e4b6f8,
-	0xd014e0b7,
-/* 0x08ba: i2c_acquire */
-	0xae7e00f8,
-	0x047e0008,
-	0xd9f00000,
-	0x002e7e03,
-/* 0x08cb: i2c_release */
-	0x7e00f800,
-	0x7e0008ae,
-	0xf0000004,
-	0x2e7e03da,
-	0x00f80000,
-/* 0x08dc: i2c_recv */
-	0xc70132f4,
-	0x14b6f8c1,
-	0x2816b002,
-	0x01371ff5,
-	0x0cf413b8,
-	0x00329800,
-	0x0ccc13b8,
-	0x00319800,
-	0xf90231f4,
-	0xf9e0f9d0,
-	0x0067f1d0,
-	0x0063f100,
-	0x01679210,
-	0xb60076bb,
-	0x50f90465,
-	0xbb046594,
-	0x50bd0256,
-	0xfc0475fd,
-	0x08ba7e50,
-	0x0464b600,
-	0xd6b0d0fc,
-	0xb01bf500,
-	0xbb000500,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x0008677e,
-	0xf50464b6,
-	0xc700cc11,
-	0x76bbe0c5,
-	0x0465b600,
-	0x659450f9,
-	0x0256bb04,
-	0x75fd50bd,
-	0x7e50fc04,
-	0xb600080d,
-	0x11f50464,
-	0x010500a9,
-	0xb60076bb,
-	0x50f90465,
-	0xbb046594,
-	0x50bd0256,
-	0xfc0475fd,
-	0x08677e50,
-	0x0464b600,
-	0x008711f5,
-	0xb60076bb,
-	0x50f90465,
-	0xbb046594,
-	0x50bd0256,
-	0xfc0475fd,
-	0x07be7e50,
-	0x0464b600,
-	0xcb6711f4,
-	0x76bbe05b,
-	0x0465b600,
-	0x659450f9,
-	0x0256bb04,
-	0x75fd50bd,
-	0x7e50fc04,
-	0xb600070a,
-	0x5bb20464,
-	0x0ef474bd,
-/* 0x09e1: i2c_recv_not_rd08 */
-	0x01d6b041,
-	0x053b1bf4,
-	0x08677e00,
-	0x3211f400,
-	0x7ee0c5c7,
-	0xf400080d,
-	0x00052811,
-	0x0008677e,
-	0xc71f11f4,
-	0x0d7ee0b5,
-	0x11f40008,
-	0x070a7e15,
-	0xc774bd00,
-	0x1bf408c5,
-	0x0232f409,
-/* 0x0a1f: i2c_recv_not_wr08 */
-/* 0x0a1f: i2c_recv_done */
-	0xc7030ef4,
-	0xcb7ef8ce,
-	0xe0fc0008,
-	0x12f4d0fc,
-	0x7e7cb209,
-/* 0x0a33: i2c_recv_exit */
-	0xf80002c2,
-/* 0x0a35: i2c_init */
-/* 0x0a37: test_recv */
-	0x4100f800,
-	0x11cf0458,
-	0x0110b600,
-	0xf6045840,
-	0x04bd0001,
-	0xd900e7f1,
-	0x134fe3f1,
-	0x0002017e,
-/* 0x0a56: test_init */
-	0x004e00f8,
-	0x02017e08,
-/* 0x0a5f: idle_recv */
-	0xf800f800,
-/* 0x0a61: idle */
-	0x0031f400,
-	0xcf045441,
-	0x10b60011,
-	0x04544001,
-	0xbd0001f6,
-/* 0x0a75: idle_loop */
-	0xf4580104,
-/* 0x0a7a: idle_proc */
-/* 0x0a7a: idle_proc_exec */
-	0x10f90232,
-	0xcb7e1eb2,
-	0x10fc0002,
-	0xf40911f4,
-	0x0ef40231,
-/* 0x0a8d: idle_proc_next */
-	0x5810b6f0,
-	0x1bf41fa6,
-	0xe002f4e8,
-	0xf40028f4,
-	0x0000c60e,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc
deleted file mode 100644
index daa06c1c655e..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#define NVKM_PPWR_CHIPSET GT215
-#define HW_TICKS_PER_US 203 // should be 202.5
-
-//#define NVKM_FALCON_PC24
-//#define NVKM_FALCON_UNSHIFTED_IO
-//#define NVKM_FALCON_MMIO_UAS
-//#define NVKM_FALCON_MMIO_TRAP
-
-#include "macros.fuc"
-
-.section #nva3_pwr_data
-#define INCLUDE_PROC
-#include "kernel.fuc"
-#include "arith.fuc"
-#include "host.fuc"
-#include "memx.fuc"
-#include "perf.fuc"
-#include "i2c_.fuc"
-#include "test.fuc"
-#include "idle.fuc"
-#undef INCLUDE_PROC
-
-#define INCLUDE_DATA
-#include "kernel.fuc"
-#include "arith.fuc"
-#include "host.fuc"
-#include "memx.fuc"
-#include "perf.fuc"
-#include "i2c_.fuc"
-#include "test.fuc"
-#include "idle.fuc"
-#undef INCLUDE_DATA
-.align 256
-
-.section #nva3_pwr_code
-#define INCLUDE_CODE
-#include "kernel.fuc"
-#include "arith.fuc"
-#include "host.fuc"
-#include "memx.fuc"
-#include "perf.fuc"
-#include "i2c_.fuc"
-#include "test.fuc"
-#include "idle.fuc"
-#undef INCLUDE_CODE
-.align 256
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
deleted file mode 100644
index d1f9b6cb66d7..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
+++ /dev/null
@@ -1,1868 +0,0 @@
-uint32_t nva3_pwr_data[] = {
-/* 0x0000: proc_kern */
-	0x52544e49,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0058: proc_list_head */
-	0x54534f48,
-	0x00000512,
-	0x000004af,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x584d454d,
-	0x00000842,
-	0x00000834,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x46524550,
-	0x00000846,
-	0x00000844,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x5f433249,
-	0x00000c76,
-	0x00000b19,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x54534554,
-	0x00000c9f,
-	0x00000c78,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x454c4449,
-	0x00000cab,
-	0x00000ca9,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0268: proc_list_tail */
-/* 0x0268: time_prev */
-	0x00000000,
-/* 0x026c: time_next */
-	0x00000000,
-/* 0x0270: fifo_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x02f0: rfifo_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0370: memx_func_head */
-	0x00000001,
-	0x00000000,
-	0x00000551,
-/* 0x037c: memx_func_next */
-	0x00000002,
-	0x00000000,
-	0x000005a8,
-	0x00000003,
-	0x00000002,
-	0x0000063a,
-	0x00040004,
-	0x00000000,
-	0x00000656,
-	0x00010005,
-	0x00000000,
-	0x00000673,
-	0x00010006,
-	0x00000000,
-	0x000005f8,
-	0x00000007,
-	0x00000000,
-	0x0000067e,
-/* 0x03c4: memx_func_tail */
-/* 0x03c4: memx_ts_start */
-	0x00000000,
-/* 0x03c8: memx_ts_end */
-	0x00000000,
-/* 0x03cc: memx_data_head */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0bcc: memx_data_tail */
-/* 0x0bcc: memx_train_head */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0ccc: memx_train_tail */
-/* 0x0ccc: i2c_scl_map */
-	0x00001000,
-	0x00004000,
-	0x00010000,
-	0x00000100,
-	0x00040000,
-	0x00100000,
-	0x00400000,
-	0x01000000,
-	0x04000000,
-	0x10000000,
-/* 0x0cf4: i2c_sda_map */
-	0x00002000,
-	0x00008000,
-	0x00020000,
-	0x00000200,
-	0x00080000,
-	0x00200000,
-	0x00800000,
-	0x02000000,
-	0x08000000,
-	0x20000000,
-/* 0x0d1c: i2c_ctrl */
-	0x0000e138,
-	0x0000e150,
-	0x0000e168,
-	0x0000e180,
-	0x0000e254,
-	0x0000e274,
-	0x0000e764,
-	0x0000e780,
-	0x0000e79c,
-	0x0000e7b8,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-uint32_t nva3_pwr_code[] = {
-	0x039e0ef5,
-/* 0x0004: rd32 */
-	0x07a007f1,
-	0xd00604b6,
-	0x04bd000e,
-	0xf001d7f0,
-	0x07f101d3,
-	0x04b607ac,
-	0x000dd006,
-/* 0x0022: rd32_wait */
-	0xd7f104bd,
-	0xd4b607ac,
-	0x00ddcf06,
-	0x7000d4f1,
-	0xf1f21bf4,
-	0xb607a4d7,
-	0xddcf06d4,
-/* 0x003f: wr32 */
-	0xf100f800,
-	0xb607a007,
-	0x0ed00604,
-	0xf104bd00,
-	0xb607a407,
-	0x0dd00604,
-	0xf004bd00,
-	0xd5f002d7,
-	0x01d3f0f0,
-	0x07ac07f1,
-	0xd00604b6,
-	0x04bd000d,
-/* 0x006c: wr32_wait */
-	0x07acd7f1,
-	0xcf06d4b6,
-	0xd4f100dd,
-	0x1bf47000,
-/* 0x007f: nsec */
-	0xf900f8f2,
-	0xf080f990,
-	0x84b62c87,
-	0x0088cf06,
-/* 0x008c: nsec_loop */
-	0xb62c97f0,
-	0x99cf0694,
-	0x0298bb00,
-	0xf4069eb8,
-	0x80fcf11e,
-	0x00f890fc,
-/* 0x00a4: wait */
-	0x80f990f9,
-	0xb62c87f0,
-	0x88cf0684,
-/* 0x00b1: wait_loop */
-	0x02eeb900,
-	0xb90421f4,
-	0xadfd02da,
-	0x06acb804,
-	0xf0150bf4,
-	0x94b62c97,
-	0x0099cf06,
-	0xb80298bb,
-	0x1ef4069b,
-/* 0x00d5: wait_done */
-	0xfc80fcdf,
-/* 0x00db: intr_watchdog */
-	0x9800f890,
-	0x96b003e9,
-	0x2a0bf400,
-	0xbb9a0a98,
-	0x1cf4029a,
-	0x01d7f00f,
-	0x02dd21f5,
-	0x0ef494bd,
-/* 0x00f9: intr_watchdog_next_time */
-	0x9b0a9815,
-	0xf400a6b0,
-	0x9ab8090b,
-	0x061cf406,
-/* 0x0108: intr_watchdog_next_time_set */
-/* 0x010b: intr_watchdog_next_proc */
-	0x809b0980,
-	0xe0b603e9,
-	0x68e6b158,
-	0xc61bf402,
-/* 0x011a: intr */
-	0x00f900f8,
-	0x80f904bd,
-	0xa0f990f9,
-	0xc0f9b0f9,
-	0xe0f9d0f9,
-	0xf7f0f0f9,
-	0x0188fe00,
-	0x87f180f9,
-	0x84b605d0,
-	0x0088cf06,
-	0xf10180b6,
-	0xb605d007,
-	0x08d00604,
-	0xf004bd00,
-	0x84b60887,
-	0x0088cf06,
-	0xf40289c4,
-	0x0080230b,
-	0x58e7f09b,
-	0x98db21f4,
-	0x96b09b09,
-	0x110bf400,
-	0xb63407f0,
-	0x09d00604,
-	0x8004bd00,
-/* 0x017e: intr_skip_watchdog */
-	0x89e49a09,
-	0x0bf40800,
-	0x8897f148,
-	0x0694b606,
-	0xc40099cf,
-	0x0bf4029a,
-	0xc0c7f12c,
-	0x06c4b604,
-	0xf900cccf,
-	0x48e7f1c0,
-	0x53e3f14f,
-	0x00d7f054,
-	0x034221f5,
-	0x07f1c0fc,
-	0x04b604c0,
-	0x000cd006,
-/* 0x01be: intr_subintr_skip_fifo */
-	0x07f104bd,
-	0x04b60688,
-	0x0009d006,
-/* 0x01ca: intr_skip_subintr */
-	0x89c404bd,
-	0x070bf420,
-	0xffbfa4f1,
-/* 0x01d4: intr_skip_pause */
-	0xf44089c4,
-	0xa4f1070b,
-/* 0x01de: intr_skip_user0 */
-	0x07f0ffbf,
-	0x0604b604,
-	0xbd0008d0,
-	0xfe80fc04,
-	0xf0fc0088,
-	0xd0fce0fc,
-	0xb0fcc0fc,
-	0x90fca0fc,
-	0x00fc80fc,
-	0xf80032f4,
-/* 0x0205: ticks_from_ns */
-	0xf9c0f901,
-	0xcbd7f1b0,
-	0x00d3f000,
-	0x041321f5,
-	0x03e8ccec,
-	0xf400b4b0,
-	0xeeec120b,
-	0xd7f103e8,
-	0xd3f000cb,
-	0x1321f500,
-/* 0x022d: ticks_from_ns_quit */
-	0x02ceb904,
-	0xc0fcb0fc,
-/* 0x0236: ticks_from_us */
-	0xc0f900f8,
-	0xd7f1b0f9,
-	0xd3f000cb,
-	0x1321f500,
-	0x02ceb904,
-	0xf400b4b0,
-	0xe4bd050b,
-/* 0x0250: ticks_from_us_quit */
-	0xc0fcb0fc,
-/* 0x0256: ticks_to_us */
-	0xd7f100f8,
-	0xd3f000cb,
-	0xecedff00,
-/* 0x0262: timer */
-	0x90f900f8,
-	0x32f480f9,
-	0x03f89810,
-	0xf40086b0,
-	0x84bd651c,
-	0xb63807f0,
-	0x08d00604,
-	0xf004bd00,
-	0x84b63487,
-	0x0088cf06,
-	0xbb9a0998,
-	0xe9bb0298,
-	0x03fe8000,
-	0xb60887f0,
-	0x88cf0684,
-	0x0284f000,
-	0xf0261bf4,
-	0x84b63487,
-	0x0088cf06,
-	0xf406e0b8,
-	0xe8b8090b,
-	0x111cf406,
-/* 0x02b8: timer_reset */
-	0xb63407f0,
-	0x0ed00604,
-	0x8004bd00,
-/* 0x02c6: timer_enable */
-	0x87f09a0e,
-	0x3807f001,
-	0xd00604b6,
-	0x04bd0008,
-/* 0x02d4: timer_done */
-	0xfc1031f4,
-	0xf890fc80,
-/* 0x02dd: send_proc */
-	0xf980f900,
-	0x05e89890,
-	0xf004e998,
-	0x89b80486,
-	0x2a0bf406,
-	0x940398c4,
-	0x80b60488,
-	0x008ebb18,
-	0x8000fa98,
-	0x8d80008a,
-	0x028c8001,
-	0xb6038b80,
-	0x94f00190,
-	0x04e98007,
-/* 0x0317: send_done */
-	0xfc0231f4,
-	0xf880fc90,
-/* 0x031d: find */
-	0xf080f900,
-	0x31f45887,
-/* 0x0325: find_loop */
-	0x008a9801,
-	0xf406aeb8,
-	0x80b6100b,
-	0x6886b158,
-	0xf01bf402,
-/* 0x033b: find_done */
-	0xb90132f4,
-	0x80fc028e,
-/* 0x0342: send */
-	0x21f500f8,
-	0x01f4031d,
-/* 0x034b: recv */
-	0xf900f897,
-	0x9880f990,
-	0xe99805e8,
-	0x0132f404,
-	0xf40689b8,
-	0x89c43d0b,
-	0x0180b603,
-	0x800784f0,
-	0xea9805e8,
-	0xfef0f902,
-	0xf0f9018f,
-	0x9402efb9,
-	0xe9bb0499,
-	0x18e0b600,
-	0x9803eb98,
-	0xed9802ec,
-	0x00ee9801,
-	0xf0fca5f9,
-	0xf400f8fe,
-	0xf0fc0131,
-/* 0x0398: recv_done */
-	0x90fc80fc,
-/* 0x039e: init */
-	0x17f100f8,
-	0x14b60108,
-	0x0011cf06,
-	0x010911e7,
-	0xfe0814b6,
-	0x17f10014,
-	0x13f000e0,
-	0x1c07f000,
-	0xd00604b6,
-	0x04bd0001,
-	0xf0ff17f0,
-	0x04b61407,
-	0x0001d006,
-	0x17f004bd,
-	0x0015f102,
-	0x1007f008,
-	0xd00604b6,
-	0x04bd0001,
-	0x011a17f1,
-	0xfe0013f0,
-	0x31f40010,
-	0x0117f010,
-	0xb63807f0,
-	0x01d00604,
-	0xf004bd00,
-/* 0x0402: init_proc */
-	0xf19858f7,
-	0x0016b001,
-	0xf9fa0bf4,
-	0x58f0b615,
-/* 0x0413: mulu32_32_64 */
-	0xf9f20ef4,
-	0xf920f910,
-	0x9540f930,
-	0xd29510e1,
-	0xbdc4bd10,
-	0xc0edffb4,
-	0xb9301dff,
-	0x34f10234,
-	0x34b6ffff,
-	0x1045b610,
-	0xbb00c3bb,
-	0xe2ff01b4,
-	0x0234b930,
-	0xffff34f1,
-	0xb61034b6,
-	0xc3bb1045,
-	0x01b4bb00,
-	0xbb3012ff,
-	0x40fc00b3,
-	0x20fc30fc,
-	0x00f810fc,
-/* 0x0464: host_send */
-	0x04b017f1,
-	0xcf0614b6,
-	0x27f10011,
-	0x24b604a0,
-	0x0022cf06,
-	0xf40612b8,
-	0x1ec4320b,
-	0x04ee9407,
-	0x0270e0b7,
-	0x9803eb98,
-	0xed9802ec,
-	0x00ee9801,
-	0x034221f5,
-	0xc40110b6,
-	0x07f10f1e,
-	0x04b604b0,
-	0x000ed006,
-	0x0ef404bd,
-/* 0x04ad: host_send_done */
-/* 0x04af: host_recv */
-	0xf100f8ba,
-	0xf14e4917,
-	0xb8525413,
-	0x0bf406e1,
-/* 0x04bd: host_recv_wait */
-	0xcc17f1aa,
-	0x0614b604,
-	0xf10011cf,
-	0xb604c827,
-	0x22cf0624,
-	0x0816f000,
-	0xf40612b8,
-	0x23c4e60b,
-	0x0434b607,
-	0x02f030b7,
-	0x80033b80,
-	0x3d80023c,
-	0x003e8001,
-	0xf00120b6,
-	0x07f10f24,
-	0x04b604c8,
-	0x0002d006,
-	0x27f004bd,
-	0x0007f040,
-	0xd00604b6,
-	0x04bd0002,
-/* 0x0512: host_init */
-	0x17f100f8,
-	0x14b60080,
-	0x7015f110,
-	0xd007f102,
-	0x0604b604,
-	0xbd0001d0,
-	0x8017f104,
-	0x1014b600,
-	0x02f015f1,
-	0x04dc07f1,
-	0xd00604b6,
-	0x04bd0001,
-	0xf10117f0,
-	0xb604c407,
-	0x01d00604,
-	0xf804bd00,
-/* 0x0551: memx_func_enter */
-	0x1087f100,
-	0x028eb916,
-	0xb90421f4,
-	0x67f102d7,
-	0x63f1fffc,
-	0x76fdffff,
-	0x0267f104,
-	0x0576fd00,
-	0x70f980f9,
-	0xe0fcd0fc,
-	0xf03f21f4,
-	0x07f10467,
-	0x04b607e0,
-	0x0006d006,
-/* 0x058a: memx_func_enter_wait */
-	0x67f104bd,
-	0x64b607c0,
-	0x0066cf06,
-	0xf40464f0,
-	0x67f0f30b,
-	0x0664b62c,
-	0x800066cf,
-	0x00f8f106,
-/* 0x05a8: memx_func_leave */
-	0xb62c67f0,
-	0x66cf0664,
-	0xf2068000,
-	0xf10467f0,
-	0xb607e407,
-	0x06d00604,
-/* 0x05c3: memx_func_leave_wait */
-	0xf104bd00,
-	0xb607c067,
-	0x66cf0664,
-	0x0464f000,
-	0xf1f31bf4,
-	0xb9161087,
-	0x21f4028e,
-	0x02d7b904,
-	0xffcc67f1,
-	0xffff63f1,
-	0xf90476fd,
-	0xfc70f980,
-	0xf4e0fcd0,
-	0x00f83f21,
-/* 0x05f8: memx_func_wait_vblank */
-	0xb0001698,
-	0x0bf40066,
-	0x0166b013,
-	0xf4060bf4,
-/* 0x060a: memx_func_wait_vblank_head1 */
-	0x77f12e0e,
-	0x0ef40020,
-/* 0x0611: memx_func_wait_vblank_head0 */
-	0x0877f107,
-/* 0x0615: memx_func_wait_vblank_0 */
-	0xc467f100,
-	0x0664b607,
-	0xfd0066cf,
-	0x1bf40467,
-/* 0x0625: memx_func_wait_vblank_1 */
-	0xc467f1f3,
-	0x0664b607,
-	0xfd0066cf,
-	0x0bf40467,
-/* 0x0635: memx_func_wait_vblank_fini */
-	0x0410b6f3,
-/* 0x063a: memx_func_wr32 */
-	0x169800f8,
-	0x01159800,
-	0xf90810b6,
-	0xfc50f960,
-	0xf4e0fcd0,
-	0x42b63f21,
-	0xe91bf402,
-/* 0x0656: memx_func_wait */
-	0x87f000f8,
-	0x0684b62c,
-	0x980088cf,
-	0x1d98001e,
-	0x021c9801,
-	0xb6031b98,
-	0x21f41010,
-/* 0x0673: memx_func_delay */
-	0x9800f8a4,
-	0x10b6001e,
-	0x7f21f404,
-/* 0x067e: memx_func_train */
-	0x57f100f8,
-	0x77f10003,
-	0x97f10000,
-	0x93f00000,
-	0x029eb970,
-	0xb90421f4,
-	0xe7f102d8,
-	0x21f42710,
-/* 0x069d: memx_func_train_loop_outer */
-	0x0158e07f,
-	0x0083f101,
-	0xe097f102,
-	0x1193f011,
-	0x80f990f9,
-	0xe0fcd0fc,
-	0xf93f21f4,
-	0x0067f150,
-/* 0x06bd: memx_func_train_loop_inner */
-	0x1187f100,
-	0x9068ff11,
-	0xfd109894,
-	0x97f10589,
-	0x93f00720,
-	0xf990f910,
-	0xfcd0fc80,
-	0x3f21f4e0,
-	0x008097f1,
-	0xb91093f0,
-	0x21f4029e,
-	0x02d8b904,
-	0xf92088c5,
-	0xfc80f990,
-	0xf4e0fcd0,
-	0x97f13f21,
-	0x93f0053c,
-	0x0287f110,
-	0x0083f130,
-	0xf990f980,
-	0xfcd0fc80,
-	0x3f21f4e0,
-	0x0560e7f1,
-	0xf110e3f0,
-	0xf10000d7,
-	0x908000d3,
-	0xb7f100dc,
-	0xb3f08480,
-	0xa421f41e,
-	0x000057f1,
-	0xffff97f1,
-	0x830093f1,
-/* 0x073c: memx_func_train_loop_4x */
-	0x0080a7f1,
-	0xb910a3f0,
-	0x21f402ae,
-	0x02d8b904,
-	0xffdfb7f1,
-	0xffffb3f1,
-	0xf9048bfd,
-	0xfc80f9a0,
-	0xf4e0fcd0,
-	0xa7f13f21,
-	0xa3f0053c,
-	0x0287f110,
-	0x0083f130,
-	0xf9a0f980,
-	0xfcd0fc80,
-	0x3f21f4e0,
-	0x0560e7f1,
-	0xf110e3f0,
-	0xf10000d7,
-	0xb98000d3,
-	0xb7f102dc,
-	0xb3f02710,
-	0xa421f400,
-	0xf402eeb9,
-	0xddb90421,
-	0x949dff02,
-	0x700150b6,
-	0x1ef40456,
-	0xcc7aa092,
-	0x00a9800b,
-	0xb60160b6,
-	0x66700470,
-	0x001ef510,
-	0xb650fcff,
-	0x56700150,
-	0xd41ef507,
-/* 0x07cf: memx_exec */
-	0xf900f8fe,
-	0xb9d0f9e0,
-	0xb2b902c1,
-/* 0x07d9: memx_exec_next */
-	0x00139802,
-	0xe70410b6,
-	0xe701f034,
-	0xb601e033,
-	0x30f00132,
-	0xde35980c,
-	0x12b855f9,
-	0xe41ef406,
-	0x98f10b98,
-	0xcbbbf20c,
-	0xc4b7f102,
-	0x06b4b607,
-	0xfc00bbcf,
-	0xf5e0fcd0,
-	0xf8034221,
-/* 0x0815: memx_info */
-	0x01c67000,
-/* 0x081b: memx_info_data */
-	0xf10e0bf4,
-	0xf103ccc7,
-	0xf40800b7,
-/* 0x0826: memx_info_train */
-	0xc7f10b0e,
-	0xb7f10bcc,
-/* 0x082e: memx_info_send */
-	0x21f50100,
-	0x00f80342,
-/* 0x0834: memx_recv */
-	0xf401d6b0,
-	0xd6b0980b,
-	0xd80bf400,
-/* 0x0842: memx_init */
-	0x00f800f8,
-/* 0x0844: perf_recv */
-/* 0x0846: perf_init */
-	0x00f800f8,
-/* 0x0848: i2c_drive_scl */
-	0xf40036b0,
-	0x07f1110b,
-	0x04b607e0,
-	0x0001d006,
-	0x00f804bd,
-/* 0x085c: i2c_drive_scl_lo */
-	0x07e407f1,
-	0xd00604b6,
-	0x04bd0001,
-/* 0x086a: i2c_drive_sda */
-	0x36b000f8,
-	0x110bf400,
-	0x07e007f1,
-	0xd00604b6,
-	0x04bd0002,
-/* 0x087e: i2c_drive_sda_lo */
-	0x07f100f8,
-	0x04b607e4,
-	0x0002d006,
-	0x00f804bd,
-/* 0x088c: i2c_sense_scl */
-	0xf10132f4,
-	0xb607c437,
-	0x33cf0634,
-	0x0431fd00,
-	0xf4060bf4,
-/* 0x08a2: i2c_sense_scl_done */
-	0x00f80131,
-/* 0x08a4: i2c_sense_sda */
-	0xf10132f4,
-	0xb607c437,
-	0x33cf0634,
-	0x0432fd00,
-	0xf4060bf4,
-/* 0x08ba: i2c_sense_sda_done */
-	0x00f80131,
-/* 0x08bc: i2c_raise_scl */
-	0x47f140f9,
-	0x37f00898,
-	0x4821f501,
-/* 0x08c9: i2c_raise_scl_wait */
-	0xe8e7f108,
-	0x7f21f403,
-	0x088c21f5,
-	0xb60901f4,
-	0x1bf40142,
-/* 0x08dd: i2c_raise_scl_done */
-	0xf840fcef,
-/* 0x08e1: i2c_start */
-	0x8c21f500,
-	0x0d11f408,
-	0x08a421f5,
-	0xf40611f4,
-/* 0x08f2: i2c_start_rep */
-	0x37f0300e,
-	0x4821f500,
-	0x0137f008,
-	0x086a21f5,
-	0xb60076bb,
-	0x50f90465,
-	0xbb046594,
-	0x50bd0256,
-	0xfc0475fd,
-	0xbc21f550,
-	0x0464b608,
-/* 0x091f: i2c_start_send */
-	0xf01f11f4,
-	0x21f50037,
-	0xe7f1086a,
-	0x21f41388,
-	0x0037f07f,
-	0x084821f5,
-	0x1388e7f1,
-/* 0x093b: i2c_start_out */
-	0xf87f21f4,
-/* 0x093d: i2c_stop */
-	0x0037f000,
-	0x084821f5,
-	0xf50037f0,
-	0xf1086a21,
-	0xf403e8e7,
-	0x37f07f21,
-	0x4821f501,
-	0x88e7f108,
-	0x7f21f413,
-	0xf50137f0,
-	0xf1086a21,
-	0xf41388e7,
-	0x00f87f21,
-/* 0x0970: i2c_bitw */
-	0x086a21f5,
-	0x03e8e7f1,
-	0xbb7f21f4,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x08bc21f5,
-	0xf40464b6,
-	0xe7f11811,
-	0x21f41388,
-	0x0037f07f,
-	0x084821f5,
-	0x1388e7f1,
-/* 0x09af: i2c_bitw_out */
-	0xf87f21f4,
-/* 0x09b1: i2c_bitr */
-	0x0137f000,
-	0x086a21f5,
-	0x03e8e7f1,
-	0xbb7f21f4,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x08bc21f5,
-	0xf40464b6,
-	0x21f51b11,
-	0x37f008a4,
-	0x4821f500,
-	0x88e7f108,
-	0x7f21f413,
-	0xf4013cf0,
-/* 0x09f6: i2c_bitr_done */
-	0x00f80131,
-/* 0x09f8: i2c_get_byte */
-	0xf00057f0,
-/* 0x09fe: i2c_get_byte_next */
-	0x54b60847,
-	0x0076bb01,
-	0xf90465b6,
-	0x04659450,
-	0xbd0256bb,
-	0x0475fd50,
-	0x21f550fc,
-	0x64b609b1,
-	0x2b11f404,
-	0xb60553fd,
-	0x1bf40142,
-	0x0137f0d8,
-	0xb60076bb,
-	0x50f90465,
-	0xbb046594,
-	0x50bd0256,
-	0xfc0475fd,
-	0x7021f550,
-	0x0464b609,
-/* 0x0a48: i2c_get_byte_done */
-/* 0x0a4a: i2c_put_byte */
-	0x47f000f8,
-/* 0x0a4d: i2c_put_byte_next */
-	0x0142b608,
-	0xbb3854ff,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x097021f5,
-	0xf40464b6,
-	0x46b03411,
-	0xd81bf400,
-	0xb60076bb,
-	0x50f90465,
-	0xbb046594,
-	0x50bd0256,
-	0xfc0475fd,
-	0xb121f550,
-	0x0464b609,
-	0xbb0f11f4,
-	0x36b00076,
-	0x061bf401,
-/* 0x0aa3: i2c_put_byte_done */
-	0xf80132f4,
-/* 0x0aa5: i2c_addr */
-	0x0076bb00,
-	0xf90465b6,
-	0x04659450,
-	0xbd0256bb,
-	0x0475fd50,
-	0x21f550fc,
-	0x64b608e1,
-	0x2911f404,
-	0x012ec3e7,
-	0xfd0134b6,
-	0x76bb0553,
-	0x0465b600,
-	0x659450f9,
-	0x0256bb04,
-	0x75fd50bd,
-	0xf550fc04,
-	0xb60a4a21,
-/* 0x0aea: i2c_addr_done */
-	0x00f80464,
-/* 0x0aec: i2c_acquire_addr */
-	0xb6f8cec7,
-	0xe0b702e4,
-	0xee980d1c,
-/* 0x0afb: i2c_acquire */
-	0xf500f800,
-	0xf40aec21,
-	0xd9f00421,
-	0x3f21f403,
-/* 0x0b0a: i2c_release */
-	0x21f500f8,
-	0x21f40aec,
-	0x03daf004,
-	0xf83f21f4,
-/* 0x0b19: i2c_recv */
-	0x0132f400,
-	0xb6f8c1c7,
-	0x16b00214,
-	0x3a1ff528,
-	0xf413a001,
-	0x0032980c,
-	0x0ccc13a0,
-	0xf4003198,
-	0xd0f90231,
-	0xd0f9e0f9,
-	0x000067f1,
-	0x100063f1,
-	0xbb016792,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x0afb21f5,
-	0xfc0464b6,
-	0x00d6b0d0,
-	0x00b31bf5,
-	0xbb0057f0,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x0aa521f5,
-	0xf50464b6,
-	0xc700d011,
-	0x76bbe0c5,
-	0x0465b600,
-	0x659450f9,
-	0x0256bb04,
-	0x75fd50bd,
-	0xf550fc04,
-	0xb60a4a21,
-	0x11f50464,
-	0x57f000ad,
-	0x0076bb01,
-	0xf90465b6,
-	0x04659450,
-	0xbd0256bb,
-	0x0475fd50,
-	0x21f550fc,
-	0x64b60aa5,
-	0x8a11f504,
-	0x0076bb00,
-	0xf90465b6,
-	0x04659450,
-	0xbd0256bb,
-	0x0475fd50,
-	0x21f550fc,
-	0x64b609f8,
-	0x6a11f404,
-	0xbbe05bcb,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x093d21f5,
-	0xb90464b6,
-	0x74bd025b,
-/* 0x0c1f: i2c_recv_not_rd08 */
-	0xb0430ef4,
-	0x1bf401d6,
-	0x0057f03d,
-	0x0aa521f5,
-	0xc73311f4,
-	0x21f5e0c5,
-	0x11f40a4a,
-	0x0057f029,
-	0x0aa521f5,
-	0xc71f11f4,
-	0x21f5e0b5,
-	0x11f40a4a,
-	0x3d21f515,
-	0xc774bd09,
-	0x1bf408c5,
-	0x0232f409,
-/* 0x0c5f: i2c_recv_not_wr08 */
-/* 0x0c5f: i2c_recv_done */
-	0xc7030ef4,
-	0x21f5f8ce,
-	0xe0fc0b0a,
-	0x12f4d0fc,
-	0x027cb90a,
-	0x034221f5,
-/* 0x0c74: i2c_recv_exit */
-/* 0x0c76: i2c_init */
-	0x00f800f8,
-/* 0x0c78: test_recv */
-	0x05d817f1,
-	0xcf0614b6,
-	0x10b60011,
-	0xd807f101,
-	0x0604b605,
-	0xbd0001d0,
-	0x00e7f104,
-	0x4fe3f1d9,
-	0x6221f513,
-/* 0x0c9f: test_init */
-	0xf100f802,
-	0xf50800e7,
-	0xf8026221,
-/* 0x0ca9: idle_recv */
-/* 0x0cab: idle */
-	0xf400f800,
-	0x17f10031,
-	0x14b605d4,
-	0x0011cf06,
-	0xf10110b6,
-	0xb605d407,
-	0x01d00604,
-/* 0x0cc7: idle_loop */
-	0xf004bd00,
-	0x32f45817,
-/* 0x0ccd: idle_proc */
-/* 0x0ccd: idle_proc_exec */
-	0xb910f902,
-	0x21f5021e,
-	0x10fc034b,
-	0xf40911f4,
-	0x0ef40231,
-/* 0x0ce1: idle_proc_next */
-	0x5810b6ef,
-	0xf4061fb8,
-	0x02f4e61b,
-	0x0028f4dd,
-	0x00bb0ef4,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc
deleted file mode 100644
index 21bf8cc7618f..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#define NVKM_PPWR_CHIPSET GF100
-#define HW_TICKS_PER_US 203 // should be 202.5
-
-//#define NVKM_FALCON_PC24
-//#define NVKM_FALCON_UNSHIFTED_IO
-//#define NVKM_FALCON_MMIO_UAS
-//#define NVKM_FALCON_MMIO_TRAP
-
-#include "macros.fuc"
-
-.section #nvc0_pwr_data
-#define INCLUDE_PROC
-#include "kernel.fuc"
-#include "arith.fuc"
-#include "host.fuc"
-#include "memx.fuc"
-#include "perf.fuc"
-#include "i2c_.fuc"
-#include "test.fuc"
-#include "idle.fuc"
-#undef INCLUDE_PROC
-
-#define INCLUDE_DATA
-#include "kernel.fuc"
-#include "arith.fuc"
-#include "host.fuc"
-#include "memx.fuc"
-#include "perf.fuc"
-#include "i2c_.fuc"
-#include "test.fuc"
-#include "idle.fuc"
-#undef INCLUDE_DATA
-.align 256
-
-.section #nvc0_pwr_code
-#define INCLUDE_CODE
-#include "kernel.fuc"
-#include "arith.fuc"
-#include "host.fuc"
-#include "memx.fuc"
-#include "perf.fuc"
-#include "i2c_.fuc"
-#include "test.fuc"
-#include "idle.fuc"
-#undef INCLUDE_CODE
-.align 256
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
deleted file mode 100644
index 90221d973f84..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
+++ /dev/null
@@ -1,1865 +0,0 @@
-uint32_t nvc0_pwr_data[] = {
-/* 0x0000: proc_kern */
-	0x52544e49,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0058: proc_list_head */
-	0x54534f48,
-	0x00000512,
-	0x000004af,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x584d454d,
-	0x0000075e,
-	0x00000750,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x46524550,
-	0x00000762,
-	0x00000760,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x5f433249,
-	0x00000b92,
-	0x00000a35,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x54534554,
-	0x00000bbb,
-	0x00000b94,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x454c4449,
-	0x00000bc7,
-	0x00000bc5,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0268: proc_list_tail */
-/* 0x0268: time_prev */
-	0x00000000,
-/* 0x026c: time_next */
-	0x00000000,
-/* 0x0270: fifo_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x02f0: rfifo_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0370: memx_func_head */
-	0x00000001,
-	0x00000000,
-	0x00000551,
-/* 0x037c: memx_func_next */
-	0x00000002,
-	0x00000000,
-	0x000005db,
-	0x00000003,
-	0x00000002,
-	0x000006a5,
-	0x00040004,
-	0x00000000,
-	0x000006c1,
-	0x00010005,
-	0x00000000,
-	0x000006de,
-	0x00010006,
-	0x00000000,
-	0x00000663,
-	0x00000007,
-	0x00000000,
-	0x000006e9,
-/* 0x03c4: memx_func_tail */
-/* 0x03c4: memx_ts_start */
-	0x00000000,
-/* 0x03c8: memx_ts_end */
-	0x00000000,
-/* 0x03cc: memx_data_head */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0bcc: memx_data_tail */
-/* 0x0bcc: memx_train_head */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0ccc: memx_train_tail */
-/* 0x0ccc: i2c_scl_map */
-	0x00001000,
-	0x00004000,
-	0x00010000,
-	0x00000100,
-	0x00040000,
-	0x00100000,
-	0x00400000,
-	0x01000000,
-	0x04000000,
-	0x10000000,
-/* 0x0cf4: i2c_sda_map */
-	0x00002000,
-	0x00008000,
-	0x00020000,
-	0x00000200,
-	0x00080000,
-	0x00200000,
-	0x00800000,
-	0x02000000,
-	0x08000000,
-	0x20000000,
-/* 0x0d1c: i2c_ctrl */
-	0x0000e138,
-	0x0000e150,
-	0x0000e168,
-	0x0000e180,
-	0x0000e254,
-	0x0000e274,
-	0x0000e764,
-	0x0000e780,
-	0x0000e79c,
-	0x0000e7b8,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-uint32_t nvc0_pwr_code[] = {
-	0x039e0ef5,
-/* 0x0004: rd32 */
-	0x07a007f1,
-	0xd00604b6,
-	0x04bd000e,
-	0xf001d7f0,
-	0x07f101d3,
-	0x04b607ac,
-	0x000dd006,
-/* 0x0022: rd32_wait */
-	0xd7f104bd,
-	0xd4b607ac,
-	0x00ddcf06,
-	0x7000d4f1,
-	0xf1f21bf4,
-	0xb607a4d7,
-	0xddcf06d4,
-/* 0x003f: wr32 */
-	0xf100f800,
-	0xb607a007,
-	0x0ed00604,
-	0xf104bd00,
-	0xb607a407,
-	0x0dd00604,
-	0xf004bd00,
-	0xd5f002d7,
-	0x01d3f0f0,
-	0x07ac07f1,
-	0xd00604b6,
-	0x04bd000d,
-/* 0x006c: wr32_wait */
-	0x07acd7f1,
-	0xcf06d4b6,
-	0xd4f100dd,
-	0x1bf47000,
-/* 0x007f: nsec */
-	0xf900f8f2,
-	0xf080f990,
-	0x84b62c87,
-	0x0088cf06,
-/* 0x008c: nsec_loop */
-	0xb62c97f0,
-	0x99cf0694,
-	0x0298bb00,
-	0xf4069eb8,
-	0x80fcf11e,
-	0x00f890fc,
-/* 0x00a4: wait */
-	0x80f990f9,
-	0xb62c87f0,
-	0x88cf0684,
-/* 0x00b1: wait_loop */
-	0x02eeb900,
-	0xb90421f4,
-	0xadfd02da,
-	0x06acb804,
-	0xf0150bf4,
-	0x94b62c97,
-	0x0099cf06,
-	0xb80298bb,
-	0x1ef4069b,
-/* 0x00d5: wait_done */
-	0xfc80fcdf,
-/* 0x00db: intr_watchdog */
-	0x9800f890,
-	0x96b003e9,
-	0x2a0bf400,
-	0xbb9a0a98,
-	0x1cf4029a,
-	0x01d7f00f,
-	0x02dd21f5,
-	0x0ef494bd,
-/* 0x00f9: intr_watchdog_next_time */
-	0x9b0a9815,
-	0xf400a6b0,
-	0x9ab8090b,
-	0x061cf406,
-/* 0x0108: intr_watchdog_next_time_set */
-/* 0x010b: intr_watchdog_next_proc */
-	0x809b0980,
-	0xe0b603e9,
-	0x68e6b158,
-	0xc61bf402,
-/* 0x011a: intr */
-	0x00f900f8,
-	0x80f904bd,
-	0xa0f990f9,
-	0xc0f9b0f9,
-	0xe0f9d0f9,
-	0xf7f0f0f9,
-	0x0188fe00,
-	0x87f180f9,
-	0x84b605d0,
-	0x0088cf06,
-	0xf10180b6,
-	0xb605d007,
-	0x08d00604,
-	0xf004bd00,
-	0x84b60887,
-	0x0088cf06,
-	0xf40289c4,
-	0x0080230b,
-	0x58e7f09b,
-	0x98db21f4,
-	0x96b09b09,
-	0x110bf400,
-	0xb63407f0,
-	0x09d00604,
-	0x8004bd00,
-/* 0x017e: intr_skip_watchdog */
-	0x89e49a09,
-	0x0bf40800,
-	0x8897f148,
-	0x0694b606,
-	0xc40099cf,
-	0x0bf4029a,
-	0xc0c7f12c,
-	0x06c4b604,
-	0xf900cccf,
-	0x48e7f1c0,
-	0x53e3f14f,
-	0x00d7f054,
-	0x034221f5,
-	0x07f1c0fc,
-	0x04b604c0,
-	0x000cd006,
-/* 0x01be: intr_subintr_skip_fifo */
-	0x07f104bd,
-	0x04b60688,
-	0x0009d006,
-/* 0x01ca: intr_skip_subintr */
-	0x89c404bd,
-	0x070bf420,
-	0xffbfa4f1,
-/* 0x01d4: intr_skip_pause */
-	0xf44089c4,
-	0xa4f1070b,
-/* 0x01de: intr_skip_user0 */
-	0x07f0ffbf,
-	0x0604b604,
-	0xbd0008d0,
-	0xfe80fc04,
-	0xf0fc0088,
-	0xd0fce0fc,
-	0xb0fcc0fc,
-	0x90fca0fc,
-	0x00fc80fc,
-	0xf80032f4,
-/* 0x0205: ticks_from_ns */
-	0xf9c0f901,
-	0xcbd7f1b0,
-	0x00d3f000,
-	0x041321f5,
-	0x03e8ccec,
-	0xf400b4b0,
-	0xeeec120b,
-	0xd7f103e8,
-	0xd3f000cb,
-	0x1321f500,
-/* 0x022d: ticks_from_ns_quit */
-	0x02ceb904,
-	0xc0fcb0fc,
-/* 0x0236: ticks_from_us */
-	0xc0f900f8,
-	0xd7f1b0f9,
-	0xd3f000cb,
-	0x1321f500,
-	0x02ceb904,
-	0xf400b4b0,
-	0xe4bd050b,
-/* 0x0250: ticks_from_us_quit */
-	0xc0fcb0fc,
-/* 0x0256: ticks_to_us */
-	0xd7f100f8,
-	0xd3f000cb,
-	0xecedff00,
-/* 0x0262: timer */
-	0x90f900f8,
-	0x32f480f9,
-	0x03f89810,
-	0xf40086b0,
-	0x84bd651c,
-	0xb63807f0,
-	0x08d00604,
-	0xf004bd00,
-	0x84b63487,
-	0x0088cf06,
-	0xbb9a0998,
-	0xe9bb0298,
-	0x03fe8000,
-	0xb60887f0,
-	0x88cf0684,
-	0x0284f000,
-	0xf0261bf4,
-	0x84b63487,
-	0x0088cf06,
-	0xf406e0b8,
-	0xe8b8090b,
-	0x111cf406,
-/* 0x02b8: timer_reset */
-	0xb63407f0,
-	0x0ed00604,
-	0x8004bd00,
-/* 0x02c6: timer_enable */
-	0x87f09a0e,
-	0x3807f001,
-	0xd00604b6,
-	0x04bd0008,
-/* 0x02d4: timer_done */
-	0xfc1031f4,
-	0xf890fc80,
-/* 0x02dd: send_proc */
-	0xf980f900,
-	0x05e89890,
-	0xf004e998,
-	0x89b80486,
-	0x2a0bf406,
-	0x940398c4,
-	0x80b60488,
-	0x008ebb18,
-	0x8000fa98,
-	0x8d80008a,
-	0x028c8001,
-	0xb6038b80,
-	0x94f00190,
-	0x04e98007,
-/* 0x0317: send_done */
-	0xfc0231f4,
-	0xf880fc90,
-/* 0x031d: find */
-	0xf080f900,
-	0x31f45887,
-/* 0x0325: find_loop */
-	0x008a9801,
-	0xf406aeb8,
-	0x80b6100b,
-	0x6886b158,
-	0xf01bf402,
-/* 0x033b: find_done */
-	0xb90132f4,
-	0x80fc028e,
-/* 0x0342: send */
-	0x21f500f8,
-	0x01f4031d,
-/* 0x034b: recv */
-	0xf900f897,
-	0x9880f990,
-	0xe99805e8,
-	0x0132f404,
-	0xf40689b8,
-	0x89c43d0b,
-	0x0180b603,
-	0x800784f0,
-	0xea9805e8,
-	0xfef0f902,
-	0xf0f9018f,
-	0x9402efb9,
-	0xe9bb0499,
-	0x18e0b600,
-	0x9803eb98,
-	0xed9802ec,
-	0x00ee9801,
-	0xf0fca5f9,
-	0xf400f8fe,
-	0xf0fc0131,
-/* 0x0398: recv_done */
-	0x90fc80fc,
-/* 0x039e: init */
-	0x17f100f8,
-	0x14b60108,
-	0x0011cf06,
-	0x010911e7,
-	0xfe0814b6,
-	0x17f10014,
-	0x13f000e0,
-	0x1c07f000,
-	0xd00604b6,
-	0x04bd0001,
-	0xf0ff17f0,
-	0x04b61407,
-	0x0001d006,
-	0x17f004bd,
-	0x0015f102,
-	0x1007f008,
-	0xd00604b6,
-	0x04bd0001,
-	0x011a17f1,
-	0xfe0013f0,
-	0x31f40010,
-	0x0117f010,
-	0xb63807f0,
-	0x01d00604,
-	0xf004bd00,
-/* 0x0402: init_proc */
-	0xf19858f7,
-	0x0016b001,
-	0xf9fa0bf4,
-	0x58f0b615,
-/* 0x0413: mulu32_32_64 */
-	0xf9f20ef4,
-	0xf920f910,
-	0x9540f930,
-	0xd29510e1,
-	0xbdc4bd10,
-	0xc0edffb4,
-	0xb9301dff,
-	0x34f10234,
-	0x34b6ffff,
-	0x1045b610,
-	0xbb00c3bb,
-	0xe2ff01b4,
-	0x0234b930,
-	0xffff34f1,
-	0xb61034b6,
-	0xc3bb1045,
-	0x01b4bb00,
-	0xbb3012ff,
-	0x40fc00b3,
-	0x20fc30fc,
-	0x00f810fc,
-/* 0x0464: host_send */
-	0x04b017f1,
-	0xcf0614b6,
-	0x27f10011,
-	0x24b604a0,
-	0x0022cf06,
-	0xf40612b8,
-	0x1ec4320b,
-	0x04ee9407,
-	0x0270e0b7,
-	0x9803eb98,
-	0xed9802ec,
-	0x00ee9801,
-	0x034221f5,
-	0xc40110b6,
-	0x07f10f1e,
-	0x04b604b0,
-	0x000ed006,
-	0x0ef404bd,
-/* 0x04ad: host_send_done */
-/* 0x04af: host_recv */
-	0xf100f8ba,
-	0xf14e4917,
-	0xb8525413,
-	0x0bf406e1,
-/* 0x04bd: host_recv_wait */
-	0xcc17f1aa,
-	0x0614b604,
-	0xf10011cf,
-	0xb604c827,
-	0x22cf0624,
-	0x0816f000,
-	0xf40612b8,
-	0x23c4e60b,
-	0x0434b607,
-	0x02f030b7,
-	0x80033b80,
-	0x3d80023c,
-	0x003e8001,
-	0xf00120b6,
-	0x07f10f24,
-	0x04b604c8,
-	0x0002d006,
-	0x27f004bd,
-	0x0007f040,
-	0xd00604b6,
-	0x04bd0002,
-/* 0x0512: host_init */
-	0x17f100f8,
-	0x14b60080,
-	0x7015f110,
-	0xd007f102,
-	0x0604b604,
-	0xbd0001d0,
-	0x8017f104,
-	0x1014b600,
-	0x02f015f1,
-	0x04dc07f1,
-	0xd00604b6,
-	0x04bd0001,
-	0xf10117f0,
-	0xb604c407,
-	0x01d00604,
-	0xf804bd00,
-/* 0x0551: memx_func_enter */
-	0x2067f100,
-	0x5d77f116,
-	0xff73f1f5,
-	0x026eb9ff,
-	0xb90421f4,
-	0x87fd02d8,
-	0xf960f904,
-	0xfcd0fc80,
-	0x3f21f4e0,
-	0xfffe77f1,
-	0xffff73f1,
-	0xf4026eb9,
-	0xd8b90421,
-	0x0487fd02,
-	0x80f960f9,
-	0xe0fcd0fc,
-	0xf13f21f4,
-	0xb926f067,
-	0x21f4026e,
-	0x02d8b904,
-	0xf90487fd,
-	0xfc80f960,
-	0xf4e0fcd0,
-	0x67f03f21,
-	0xe007f104,
-	0x0604b607,
-	0xbd0006d0,
-/* 0x05bd: memx_func_enter_wait */
-	0xc067f104,
-	0x0664b607,
-	0xf00066cf,
-	0x0bf40464,
-	0x2c67f0f3,
-	0xcf0664b6,
-	0x06800066,
-/* 0x05db: memx_func_leave */
-	0xf000f8f1,
-	0x64b62c67,
-	0x0066cf06,
-	0xf0f20680,
-	0x07f10467,
-	0x04b607e4,
-	0x0006d006,
-/* 0x05f6: memx_func_leave_wait */
-	0x67f104bd,
-	0x64b607c0,
-	0x0066cf06,
-	0xf40464f0,
-	0x67f1f31b,
-	0x77f126f0,
-	0x73f00001,
-	0x026eb900,
-	0xb90421f4,
-	0x87fd02d8,
-	0xf960f905,
-	0xfcd0fc80,
-	0x3f21f4e0,
-	0x162067f1,
-	0xf4026eb9,
-	0xd8b90421,
-	0x0587fd02,
-	0x80f960f9,
-	0xe0fcd0fc,
-	0xf13f21f4,
-	0xf00aa277,
-	0x6eb90073,
-	0x0421f402,
-	0xfd02d8b9,
-	0x60f90587,
-	0xd0fc80f9,
-	0x21f4e0fc,
-/* 0x0663: memx_func_wait_vblank */
-	0x9800f83f,
-	0x66b00016,
-	0x130bf400,
-	0xf40166b0,
-	0x0ef4060b,
-/* 0x0675: memx_func_wait_vblank_head1 */
-	0x2077f12e,
-	0x070ef400,
-/* 0x067c: memx_func_wait_vblank_head0 */
-	0x000877f1,
-/* 0x0680: memx_func_wait_vblank_0 */
-	0x07c467f1,
-	0xcf0664b6,
-	0x67fd0066,
-	0xf31bf404,
-/* 0x0690: memx_func_wait_vblank_1 */
-	0x07c467f1,
-	0xcf0664b6,
-	0x67fd0066,
-	0xf30bf404,
-/* 0x06a0: memx_func_wait_vblank_fini */
-	0xf80410b6,
-/* 0x06a5: memx_func_wr32 */
-	0x00169800,
-	0xb6011598,
-	0x60f90810,
-	0xd0fc50f9,
-	0x21f4e0fc,
-	0x0242b63f,
-	0xf8e91bf4,
-/* 0x06c1: memx_func_wait */
-	0x2c87f000,
-	0xcf0684b6,
-	0x1e980088,
-	0x011d9800,
-	0x98021c98,
-	0x10b6031b,
-	0xa421f410,
-/* 0x06de: memx_func_delay */
-	0x1e9800f8,
-	0x0410b600,
-	0xf87f21f4,
-/* 0x06e9: memx_func_train */
-/* 0x06eb: memx_exec */
-	0xf900f800,
-	0xb9d0f9e0,
-	0xb2b902c1,
-/* 0x06f5: memx_exec_next */
-	0x00139802,
-	0xe70410b6,
-	0xe701f034,
-	0xb601e033,
-	0x30f00132,
-	0xde35980c,
-	0x12b855f9,
-	0xe41ef406,
-	0x98f10b98,
-	0xcbbbf20c,
-	0xc4b7f102,
-	0x06b4b607,
-	0xfc00bbcf,
-	0xf5e0fcd0,
-	0xf8034221,
-/* 0x0731: memx_info */
-	0x01c67000,
-/* 0x0737: memx_info_data */
-	0xf10e0bf4,
-	0xf103ccc7,
-	0xf40800b7,
-/* 0x0742: memx_info_train */
-	0xc7f10b0e,
-	0xb7f10bcc,
-/* 0x074a: memx_info_send */
-	0x21f50100,
-	0x00f80342,
-/* 0x0750: memx_recv */
-	0xf401d6b0,
-	0xd6b0980b,
-	0xd80bf400,
-/* 0x075e: memx_init */
-	0x00f800f8,
-/* 0x0760: perf_recv */
-/* 0x0762: perf_init */
-	0x00f800f8,
-/* 0x0764: i2c_drive_scl */
-	0xf40036b0,
-	0x07f1110b,
-	0x04b607e0,
-	0x0001d006,
-	0x00f804bd,
-/* 0x0778: i2c_drive_scl_lo */
-	0x07e407f1,
-	0xd00604b6,
-	0x04bd0001,
-/* 0x0786: i2c_drive_sda */
-	0x36b000f8,
-	0x110bf400,
-	0x07e007f1,
-	0xd00604b6,
-	0x04bd0002,
-/* 0x079a: i2c_drive_sda_lo */
-	0x07f100f8,
-	0x04b607e4,
-	0x0002d006,
-	0x00f804bd,
-/* 0x07a8: i2c_sense_scl */
-	0xf10132f4,
-	0xb607c437,
-	0x33cf0634,
-	0x0431fd00,
-	0xf4060bf4,
-/* 0x07be: i2c_sense_scl_done */
-	0x00f80131,
-/* 0x07c0: i2c_sense_sda */
-	0xf10132f4,
-	0xb607c437,
-	0x33cf0634,
-	0x0432fd00,
-	0xf4060bf4,
-/* 0x07d6: i2c_sense_sda_done */
-	0x00f80131,
-/* 0x07d8: i2c_raise_scl */
-	0x47f140f9,
-	0x37f00898,
-	0x6421f501,
-/* 0x07e5: i2c_raise_scl_wait */
-	0xe8e7f107,
-	0x7f21f403,
-	0x07a821f5,
-	0xb60901f4,
-	0x1bf40142,
-/* 0x07f9: i2c_raise_scl_done */
-	0xf840fcef,
-/* 0x07fd: i2c_start */
-	0xa821f500,
-	0x0d11f407,
-	0x07c021f5,
-	0xf40611f4,
-/* 0x080e: i2c_start_rep */
-	0x37f0300e,
-	0x6421f500,
-	0x0137f007,
-	0x078621f5,
-	0xb60076bb,
-	0x50f90465,
-	0xbb046594,
-	0x50bd0256,
-	0xfc0475fd,
-	0xd821f550,
-	0x0464b607,
-/* 0x083b: i2c_start_send */
-	0xf01f11f4,
-	0x21f50037,
-	0xe7f10786,
-	0x21f41388,
-	0x0037f07f,
-	0x076421f5,
-	0x1388e7f1,
-/* 0x0857: i2c_start_out */
-	0xf87f21f4,
-/* 0x0859: i2c_stop */
-	0x0037f000,
-	0x076421f5,
-	0xf50037f0,
-	0xf1078621,
-	0xf403e8e7,
-	0x37f07f21,
-	0x6421f501,
-	0x88e7f107,
-	0x7f21f413,
-	0xf50137f0,
-	0xf1078621,
-	0xf41388e7,
-	0x00f87f21,
-/* 0x088c: i2c_bitw */
-	0x078621f5,
-	0x03e8e7f1,
-	0xbb7f21f4,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x07d821f5,
-	0xf40464b6,
-	0xe7f11811,
-	0x21f41388,
-	0x0037f07f,
-	0x076421f5,
-	0x1388e7f1,
-/* 0x08cb: i2c_bitw_out */
-	0xf87f21f4,
-/* 0x08cd: i2c_bitr */
-	0x0137f000,
-	0x078621f5,
-	0x03e8e7f1,
-	0xbb7f21f4,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x07d821f5,
-	0xf40464b6,
-	0x21f51b11,
-	0x37f007c0,
-	0x6421f500,
-	0x88e7f107,
-	0x7f21f413,
-	0xf4013cf0,
-/* 0x0912: i2c_bitr_done */
-	0x00f80131,
-/* 0x0914: i2c_get_byte */
-	0xf00057f0,
-/* 0x091a: i2c_get_byte_next */
-	0x54b60847,
-	0x0076bb01,
-	0xf90465b6,
-	0x04659450,
-	0xbd0256bb,
-	0x0475fd50,
-	0x21f550fc,
-	0x64b608cd,
-	0x2b11f404,
-	0xb60553fd,
-	0x1bf40142,
-	0x0137f0d8,
-	0xb60076bb,
-	0x50f90465,
-	0xbb046594,
-	0x50bd0256,
-	0xfc0475fd,
-	0x8c21f550,
-	0x0464b608,
-/* 0x0964: i2c_get_byte_done */
-/* 0x0966: i2c_put_byte */
-	0x47f000f8,
-/* 0x0969: i2c_put_byte_next */
-	0x0142b608,
-	0xbb3854ff,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x088c21f5,
-	0xf40464b6,
-	0x46b03411,
-	0xd81bf400,
-	0xb60076bb,
-	0x50f90465,
-	0xbb046594,
-	0x50bd0256,
-	0xfc0475fd,
-	0xcd21f550,
-	0x0464b608,
-	0xbb0f11f4,
-	0x36b00076,
-	0x061bf401,
-/* 0x09bf: i2c_put_byte_done */
-	0xf80132f4,
-/* 0x09c1: i2c_addr */
-	0x0076bb00,
-	0xf90465b6,
-	0x04659450,
-	0xbd0256bb,
-	0x0475fd50,
-	0x21f550fc,
-	0x64b607fd,
-	0x2911f404,
-	0x012ec3e7,
-	0xfd0134b6,
-	0x76bb0553,
-	0x0465b600,
-	0x659450f9,
-	0x0256bb04,
-	0x75fd50bd,
-	0xf550fc04,
-	0xb6096621,
-/* 0x0a06: i2c_addr_done */
-	0x00f80464,
-/* 0x0a08: i2c_acquire_addr */
-	0xb6f8cec7,
-	0xe0b702e4,
-	0xee980d1c,
-/* 0x0a17: i2c_acquire */
-	0xf500f800,
-	0xf40a0821,
-	0xd9f00421,
-	0x3f21f403,
-/* 0x0a26: i2c_release */
-	0x21f500f8,
-	0x21f40a08,
-	0x03daf004,
-	0xf83f21f4,
-/* 0x0a35: i2c_recv */
-	0x0132f400,
-	0xb6f8c1c7,
-	0x16b00214,
-	0x3a1ff528,
-	0xf413a001,
-	0x0032980c,
-	0x0ccc13a0,
-	0xf4003198,
-	0xd0f90231,
-	0xd0f9e0f9,
-	0x000067f1,
-	0x100063f1,
-	0xbb016792,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x0a1721f5,
-	0xfc0464b6,
-	0x00d6b0d0,
-	0x00b31bf5,
-	0xbb0057f0,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x09c121f5,
-	0xf50464b6,
-	0xc700d011,
-	0x76bbe0c5,
-	0x0465b600,
-	0x659450f9,
-	0x0256bb04,
-	0x75fd50bd,
-	0xf550fc04,
-	0xb6096621,
-	0x11f50464,
-	0x57f000ad,
-	0x0076bb01,
-	0xf90465b6,
-	0x04659450,
-	0xbd0256bb,
-	0x0475fd50,
-	0x21f550fc,
-	0x64b609c1,
-	0x8a11f504,
-	0x0076bb00,
-	0xf90465b6,
-	0x04659450,
-	0xbd0256bb,
-	0x0475fd50,
-	0x21f550fc,
-	0x64b60914,
-	0x6a11f404,
-	0xbbe05bcb,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x085921f5,
-	0xb90464b6,
-	0x74bd025b,
-/* 0x0b3b: i2c_recv_not_rd08 */
-	0xb0430ef4,
-	0x1bf401d6,
-	0x0057f03d,
-	0x09c121f5,
-	0xc73311f4,
-	0x21f5e0c5,
-	0x11f40966,
-	0x0057f029,
-	0x09c121f5,
-	0xc71f11f4,
-	0x21f5e0b5,
-	0x11f40966,
-	0x5921f515,
-	0xc774bd08,
-	0x1bf408c5,
-	0x0232f409,
-/* 0x0b7b: i2c_recv_not_wr08 */
-/* 0x0b7b: i2c_recv_done */
-	0xc7030ef4,
-	0x21f5f8ce,
-	0xe0fc0a26,
-	0x12f4d0fc,
-	0x027cb90a,
-	0x034221f5,
-/* 0x0b90: i2c_recv_exit */
-/* 0x0b92: i2c_init */
-	0x00f800f8,
-/* 0x0b94: test_recv */
-	0x05d817f1,
-	0xcf0614b6,
-	0x10b60011,
-	0xd807f101,
-	0x0604b605,
-	0xbd0001d0,
-	0x00e7f104,
-	0x4fe3f1d9,
-	0x6221f513,
-/* 0x0bbb: test_init */
-	0xf100f802,
-	0xf50800e7,
-	0xf8026221,
-/* 0x0bc5: idle_recv */
-/* 0x0bc7: idle */
-	0xf400f800,
-	0x17f10031,
-	0x14b605d4,
-	0x0011cf06,
-	0xf10110b6,
-	0xb605d407,
-	0x01d00604,
-/* 0x0be3: idle_loop */
-	0xf004bd00,
-	0x32f45817,
-/* 0x0be9: idle_proc */
-/* 0x0be9: idle_proc_exec */
-	0xb910f902,
-	0x21f5021e,
-	0x10fc034b,
-	0xf40911f4,
-	0x0ef40231,
-/* 0x0bfd: idle_proc_next */
-	0x5810b6ef,
-	0xf4061fb8,
-	0x02f4e61b,
-	0x0028f4dd,
-	0x00bb0ef4,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc
deleted file mode 100644
index b85443261569..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#define NVKM_PPWR_CHIPSET GF119
-#define HW_TICKS_PER_US 324
-
-//#define NVKM_FALCON_PC24
-#define NVKM_FALCON_UNSHIFTED_IO
-//#define NVKM_FALCON_MMIO_UAS
-//#define NVKM_FALCON_MMIO_TRAP
-
-#include "macros.fuc"
-
-.section #nvd0_pwr_data
-#define INCLUDE_PROC
-#include "kernel.fuc"
-#include "arith.fuc"
-#include "host.fuc"
-#include "memx.fuc"
-#include "perf.fuc"
-#include "i2c_.fuc"
-#include "test.fuc"
-#include "idle.fuc"
-#undef INCLUDE_PROC
-
-#define INCLUDE_DATA
-#include "kernel.fuc"
-#include "arith.fuc"
-#include "host.fuc"
-#include "memx.fuc"
-#include "perf.fuc"
-#include "i2c_.fuc"
-#include "test.fuc"
-#include "idle.fuc"
-#undef INCLUDE_DATA
-.align 256
-
-.section #nvd0_pwr_code
-#define INCLUDE_CODE
-#include "kernel.fuc"
-#include "arith.fuc"
-#include "host.fuc"
-#include "memx.fuc"
-#include "perf.fuc"
-#include "i2c_.fuc"
-#include "test.fuc"
-#include "idle.fuc"
-#undef INCLUDE_CODE
-.align 256
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
deleted file mode 100644
index 7e16aab44d85..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
+++ /dev/null
@@ -1,1795 +0,0 @@
-uint32_t nvd0_pwr_data[] = {
-/* 0x0000: proc_kern */
-	0x52544e49,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0058: proc_list_head */
-	0x54534f48,
-	0x0000049d,
-	0x00000446,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x584d454d,
-	0x0000068b,
-	0x0000067d,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x46524550,
-	0x0000068f,
-	0x0000068d,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x5f433249,
-	0x00000aaa,
-	0x0000094d,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x54534554,
-	0x00000acd,
-	0x00000aac,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x454c4449,
-	0x00000ad9,
-	0x00000ad7,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0268: proc_list_tail */
-/* 0x0268: time_prev */
-	0x00000000,
-/* 0x026c: time_next */
-	0x00000000,
-/* 0x0270: fifo_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x02f0: rfifo_queue */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0370: memx_func_head */
-	0x00000001,
-	0x00000000,
-	0x000004d3,
-/* 0x037c: memx_func_next */
-	0x00000002,
-	0x00000000,
-	0x00000554,
-	0x00000003,
-	0x00000002,
-	0x000005d8,
-	0x00040004,
-	0x00000000,
-	0x000005f4,
-	0x00010005,
-	0x00000000,
-	0x0000060e,
-	0x00010006,
-	0x00000000,
-	0x000005d3,
-	0x00000007,
-	0x00000000,
-	0x00000619,
-/* 0x03c4: memx_func_tail */
-/* 0x03c4: memx_ts_start */
-	0x00000000,
-/* 0x03c8: memx_ts_end */
-	0x00000000,
-/* 0x03cc: memx_data_head */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0bcc: memx_data_tail */
-/* 0x0bcc: memx_train_head */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0ccc: memx_train_tail */
-/* 0x0ccc: i2c_scl_map */
-	0x00000400,
-	0x00000800,
-	0x00001000,
-	0x00002000,
-	0x00004000,
-	0x00008000,
-	0x00010000,
-	0x00020000,
-	0x00040000,
-	0x00080000,
-/* 0x0cf4: i2c_sda_map */
-	0x00100000,
-	0x00200000,
-	0x00400000,
-	0x00800000,
-	0x01000000,
-	0x02000000,
-	0x04000000,
-	0x08000000,
-	0x10000000,
-	0x20000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-uint32_t nvd0_pwr_code[] = {
-	0x034d0ef5,
-/* 0x0004: rd32 */
-	0x07a007f1,
-	0xbd000ed0,
-	0x01d7f004,
-	0xf101d3f0,
-	0xd007ac07,
-	0x04bd000d,
-/* 0x001c: rd32_wait */
-	0x07acd7f1,
-	0xf100ddcf,
-	0xf47000d4,
-	0xd7f1f51b,
-	0xddcf07a4,
-/* 0x0033: wr32 */
-	0xf100f800,
-	0xd007a007,
-	0x04bd000e,
-	0x07a407f1,
-	0xbd000dd0,
-	0x02d7f004,
-	0xf0f0d5f0,
-	0x07f101d3,
-	0x0dd007ac,
-/* 0x0057: wr32_wait */
-	0xf104bd00,
-	0xcf07acd7,
-	0xd4f100dd,
-	0x1bf47000,
-/* 0x0067: nsec */
-	0xf900f8f5,
-	0xf080f990,
-	0x88cf2c87,
-/* 0x0071: nsec_loop */
-	0x2c97f000,
-	0xbb0099cf,
-	0x9eb80298,
-	0xf41ef406,
-	0x90fc80fc,
-/* 0x0086: wait */
-	0x90f900f8,
-	0x87f080f9,
-	0x0088cf2c,
-/* 0x0090: wait_loop */
-	0xf402eeb9,
-	0xdab90421,
-	0x04adfd02,
-	0xf406acb8,
-	0x97f0120b,
-	0x0099cf2c,
-	0xb80298bb,
-	0x1ef4069b,
-/* 0x00b1: wait_done */
-	0xfc80fce2,
-/* 0x00b7: intr_watchdog */
-	0x9800f890,
-	0x96b003e9,
-	0x2a0bf400,
-	0xbb9a0a98,
-	0x1cf4029a,
-	0x01d7f00f,
-	0x028c21f5,
-	0x0ef494bd,
-/* 0x00d5: intr_watchdog_next_time */
-	0x9b0a9815,
-	0xf400a6b0,
-	0x9ab8090b,
-	0x061cf406,
-/* 0x00e4: intr_watchdog_next_time_set */
-/* 0x00e7: intr_watchdog_next_proc */
-	0x809b0980,
-	0xe0b603e9,
-	0x68e6b158,
-	0xc61bf402,
-/* 0x00f6: intr */
-	0x00f900f8,
-	0x80f904bd,
-	0xa0f990f9,
-	0xc0f9b0f9,
-	0xe0f9d0f9,
-	0xf7f0f0f9,
-	0x0188fe00,
-	0x87f180f9,
-	0x88cf05d0,
-	0x0180b600,
-	0x05d007f1,
-	0xbd0008d0,
-	0x0887f004,
-	0xc40088cf,
-	0x0bf40289,
-	0x9b008020,
-	0xf458e7f0,
-	0x0998b721,
-	0x0096b09b,
-	0xf00e0bf4,
-	0x09d03407,
-	0x8004bd00,
-/* 0x014e: intr_skip_watchdog */
-	0x89e49a09,
-	0x0bf40800,
-	0x8897f13c,
-	0x0099cf06,
-	0xf4029ac4,
-	0xc7f1260b,
-	0xcccf04c0,
-	0xf1c0f900,
-	0xf14f48e7,
-	0xf05453e3,
-	0x21f500d7,
-	0xc0fc02f1,
-	0x04c007f1,
-	0xbd000cd0,
-/* 0x0185: intr_subintr_skip_fifo */
-	0x8807f104,
-	0x0009d006,
-/* 0x018e: intr_skip_subintr */
-	0x89c404bd,
-	0x070bf420,
-	0xffbfa4f1,
-/* 0x0198: intr_skip_pause */
-	0xf44089c4,
-	0xa4f1070b,
-/* 0x01a2: intr_skip_user0 */
-	0x07f0ffbf,
-	0x0008d004,
-	0x80fc04bd,
-	0xfc0088fe,
-	0xfce0fcf0,
-	0xfcc0fcd0,
-	0xfca0fcb0,
-	0xfc80fc90,
-	0x0032f400,
-/* 0x01c6: ticks_from_ns */
-	0xc0f901f8,
-	0xd7f1b0f9,
-	0xd3f00144,
-	0xb321f500,
-	0xe8ccec03,
-	0x00b4b003,
-	0xec120bf4,
-	0xf103e8ee,
-	0xf00144d7,
-	0x21f500d3,
-/* 0x01ee: ticks_from_ns_quit */
-	0xceb903b3,
-	0xfcb0fc02,
-/* 0x01f7: ticks_from_us */
-	0xf900f8c0,
-	0xf1b0f9c0,
-	0xf00144d7,
-	0x21f500d3,
-	0xceb903b3,
-	0x00b4b002,
-	0xbd050bf4,
-/* 0x0211: ticks_from_us_quit */
-	0xfcb0fce4,
-/* 0x0217: ticks_to_us */
-	0xf100f8c0,
-	0xf00144d7,
-	0xedff00d3,
-/* 0x0223: timer */
-	0xf900f8ec,
-	0xf480f990,
-	0xf8981032,
-	0x0086b003,
-	0xbd531cf4,
-	0x3807f084,
-	0xbd0008d0,
-	0x3487f004,
-	0x980088cf,
-	0x98bb9a09,
-	0x00e9bb02,
-	0xf003fe80,
-	0x88cf0887,
-	0x0284f000,
-	0xf0201bf4,
-	0x88cf3487,
-	0x06e0b800,
-	0xb8090bf4,
-	0x1cf406e8,
-/* 0x026d: timer_reset */
-	0x3407f00e,
-	0xbd000ed0,
-	0x9a0e8004,
-/* 0x0278: timer_enable */
-	0xf00187f0,
-	0x08d03807,
-/* 0x0283: timer_done */
-	0xf404bd00,
-	0x80fc1031,
-	0x00f890fc,
-/* 0x028c: send_proc */
-	0x90f980f9,
-	0x9805e898,
-	0x86f004e9,
-	0x0689b804,
-	0xc42a0bf4,
-	0x88940398,
-	0x1880b604,
-	0x98008ebb,
-	0x8a8000fa,
-	0x018d8000,
-	0x80028c80,
-	0x90b6038b,
-	0x0794f001,
-	0xf404e980,
-/* 0x02c6: send_done */
-	0x90fc0231,
-	0x00f880fc,
-/* 0x02cc: find */
-	0x87f080f9,
-	0x0131f458,
-/* 0x02d4: find_loop */
-	0xb8008a98,
-	0x0bf406ae,
-	0x5880b610,
-	0x026886b1,
-	0xf4f01bf4,
-/* 0x02ea: find_done */
-	0x8eb90132,
-	0xf880fc02,
-/* 0x02f1: send */
-	0xcc21f500,
-	0x9701f402,
-/* 0x02fa: recv */
-	0x90f900f8,
-	0xe89880f9,
-	0x04e99805,
-	0xb80132f4,
-	0x0bf40689,
-	0x0389c43d,
-	0xf00180b6,
-	0xe8800784,
-	0x02ea9805,
-	0x8ffef0f9,
-	0xb9f0f901,
-	0x999402ef,
-	0x00e9bb04,
-	0x9818e0b6,
-	0xec9803eb,
-	0x01ed9802,
-	0xf900ee98,
-	0xfef0fca5,
-	0x31f400f8,
-/* 0x0347: recv_done */
-	0xfcf0fc01,
-	0xf890fc80,
-/* 0x034d: init */
-	0x0817f100,
-	0x0011cf01,
-	0x010911e7,
-	0xfe0814b6,
-	0x17f10014,
-	0x13f000e0,
-	0x1c07f000,
-	0xbd0001d0,
-	0xff17f004,
-	0xd01407f0,
-	0x04bd0001,
-	0xf10217f0,
-	0xf0080015,
-	0x01d01007,
-	0xf104bd00,
-	0xf000f617,
-	0x10fe0013,
-	0x1031f400,
-	0xf00117f0,
-	0x01d03807,
-	0xf004bd00,
-/* 0x03a2: init_proc */
-	0xf19858f7,
-	0x0016b001,
-	0xf9fa0bf4,
-	0x58f0b615,
-/* 0x03b3: mulu32_32_64 */
-	0xf9f20ef4,
-	0xf920f910,
-	0x9540f930,
-	0xd29510e1,
-	0xbdc4bd10,
-	0xc0edffb4,
-	0xb9301dff,
-	0x34f10234,
-	0x34b6ffff,
-	0x1045b610,
-	0xbb00c3bb,
-	0xe2ff01b4,
-	0x0234b930,
-	0xffff34f1,
-	0xb61034b6,
-	0xc3bb1045,
-	0x01b4bb00,
-	0xbb3012ff,
-	0x40fc00b3,
-	0x20fc30fc,
-	0x00f810fc,
-/* 0x0404: host_send */
-	0x04b017f1,
-	0xf10011cf,
-	0xcf04a027,
-	0x12b80022,
-	0x2f0bf406,
-	0x94071ec4,
-	0xe0b704ee,
-	0xeb980270,
-	0x02ec9803,
-	0x9801ed98,
-	0x21f500ee,
-	0x10b602f1,
-	0x0f1ec401,
-	0x04b007f1,
-	0xbd000ed0,
-	0xc30ef404,
-/* 0x0444: host_send_done */
-/* 0x0446: host_recv */
-	0x17f100f8,
-	0x13f14e49,
-	0xe1b85254,
-	0xb30bf406,
-/* 0x0454: host_recv_wait */
-	0x04cc17f1,
-	0xf10011cf,
-	0xcf04c827,
-	0x16f00022,
-	0x0612b808,
-	0xc4ec0bf4,
-	0x34b60723,
-	0xf030b704,
-	0x033b8002,
-	0x80023c80,
-	0x3e80013d,
-	0x0120b600,
-	0xf10f24f0,
-	0xd004c807,
-	0x04bd0002,
-	0xf04027f0,
-	0x02d00007,
-	0xf804bd00,
-/* 0x049d: host_init */
-	0x8017f100,
-	0x1014b600,
-	0x027015f1,
-	0x04d007f1,
-	0xbd0001d0,
-	0x8017f104,
-	0x1014b600,
-	0x02f015f1,
-	0x04dc07f1,
-	0xbd0001d0,
-	0x0117f004,
-	0x04c407f1,
-	0xbd0001d0,
-/* 0x04d3: memx_func_enter */
-	0xf100f804,
-	0xf1162067,
-	0xf1f55d77,
-	0xb9ffff73,
-	0x21f4026e,
-	0x02d8b904,
-	0xf90487fd,
-	0xfc80f960,
-	0xf4e0fcd0,
-	0x77f13321,
-	0x73f1fffe,
-	0x6eb9ffff,
-	0x0421f402,
-	0xfd02d8b9,
-	0x60f90487,
-	0xd0fc80f9,
-	0x21f4e0fc,
-	0xf067f133,
-	0x026eb926,
-	0xb90421f4,
-	0x87fd02d8,
-	0xf960f904,
-	0xfcd0fc80,
-	0x3321f4e0,
-	0xf10467f0,
-	0xd007e007,
-	0x04bd0006,
-/* 0x053c: memx_func_enter_wait */
-	0x07c067f1,
-	0xf00066cf,
-	0x0bf40464,
-	0x2c67f0f6,
-	0x800066cf,
-	0x00f8f106,
-/* 0x0554: memx_func_leave */
-	0xcf2c67f0,
-	0x06800066,
-	0x0467f0f2,
-	0x07e407f1,
-	0xbd0006d0,
-/* 0x0569: memx_func_leave_wait */
-	0xc067f104,
-	0x0066cf07,
-	0xf40464f0,
-	0x67f1f61b,
-	0x77f126f0,
-	0x73f00001,
-	0x026eb900,
-	0xb90421f4,
-	0x87fd02d8,
-	0xf960f905,
-	0xfcd0fc80,
-	0x3321f4e0,
-	0x162067f1,
-	0xf4026eb9,
-	0xd8b90421,
-	0x0587fd02,
-	0x80f960f9,
-	0xe0fcd0fc,
-	0xf13321f4,
-	0xf00aa277,
-	0x6eb90073,
-	0x0421f402,
-	0xfd02d8b9,
-	0x60f90587,
-	0xd0fc80f9,
-	0x21f4e0fc,
-/* 0x05d3: memx_func_wait_vblank */
-	0xb600f833,
-	0x00f80410,
-/* 0x05d8: memx_func_wr32 */
-	0x98001698,
-	0x10b60115,
-	0xf960f908,
-	0xfcd0fc50,
-	0x3321f4e0,
-	0xf40242b6,
-	0x00f8e91b,
-/* 0x05f4: memx_func_wait */
-	0xcf2c87f0,
-	0x1e980088,
-	0x011d9800,
-	0x98021c98,
-	0x10b6031b,
-	0x8621f410,
-/* 0x060e: memx_func_delay */
-	0x1e9800f8,
-	0x0410b600,
-	0xf86721f4,
-/* 0x0619: memx_func_train */
-/* 0x061b: memx_exec */
-	0xf900f800,
-	0xb9d0f9e0,
-	0xb2b902c1,
-/* 0x0625: memx_exec_next */
-	0x00139802,
-	0xe70410b6,
-	0xe701f034,
-	0xb601e033,
-	0x30f00132,
-	0xde35980c,
-	0x12b855f9,
-	0xe41ef406,
-	0x98f10b98,
-	0xcbbbf20c,
-	0xc4b7f102,
-	0x00bbcf07,
-	0xe0fcd0fc,
-	0x02f121f5,
-/* 0x065e: memx_info */
-	0xc67000f8,
-	0x0e0bf401,
-/* 0x0664: memx_info_data */
-	0x03ccc7f1,
-	0x0800b7f1,
-/* 0x066f: memx_info_train */
-	0xf10b0ef4,
-	0xf10bccc7,
-/* 0x0677: memx_info_send */
-	0xf50100b7,
-	0xf802f121,
-/* 0x067d: memx_recv */
-	0x01d6b000,
-	0xb09b0bf4,
-	0x0bf400d6,
-/* 0x068b: memx_init */
-	0xf800f8d8,
-/* 0x068d: perf_recv */
-/* 0x068f: perf_init */
-	0xf800f800,
-/* 0x0691: i2c_drive_scl */
-	0x0036b000,
-	0xf10e0bf4,
-	0xd007e007,
-	0x04bd0001,
-/* 0x06a2: i2c_drive_scl_lo */
-	0x07f100f8,
-	0x01d007e4,
-	0xf804bd00,
-/* 0x06ad: i2c_drive_sda */
-	0x0036b000,
-	0xf10e0bf4,
-	0xd007e007,
-	0x04bd0002,
-/* 0x06be: i2c_drive_sda_lo */
-	0x07f100f8,
-	0x02d007e4,
-	0xf804bd00,
-/* 0x06c9: i2c_sense_scl */
-	0x0132f400,
-	0x07c437f1,
-	0xfd0033cf,
-	0x0bf40431,
-	0x0131f406,
-/* 0x06dc: i2c_sense_scl_done */
-/* 0x06de: i2c_sense_sda */
-	0x32f400f8,
-	0xc437f101,
-	0x0033cf07,
-	0xf40432fd,
-	0x31f4060b,
-/* 0x06f1: i2c_sense_sda_done */
-/* 0x06f3: i2c_raise_scl */
-	0xf900f801,
-	0x9847f140,
-	0x0137f008,
-	0x069121f5,
-/* 0x0700: i2c_raise_scl_wait */
-	0x03e8e7f1,
-	0xf56721f4,
-	0xf406c921,
-	0x42b60901,
-	0xef1bf401,
-/* 0x0714: i2c_raise_scl_done */
-	0x00f840fc,
-/* 0x0718: i2c_start */
-	0x06c921f5,
-	0xf50d11f4,
-	0xf406de21,
-	0x0ef40611,
-/* 0x0729: i2c_start_rep */
-	0x0037f030,
-	0x069121f5,
-	0xf50137f0,
-	0xbb06ad21,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x06f321f5,
-	0xf40464b6,
-/* 0x0756: i2c_start_send */
-	0x37f01f11,
-	0xad21f500,
-	0x88e7f106,
-	0x6721f413,
-	0xf50037f0,
-	0xf1069121,
-	0xf41388e7,
-/* 0x0772: i2c_start_out */
-	0x00f86721,
-/* 0x0774: i2c_stop */
-	0xf50037f0,
-	0xf0069121,
-	0x21f50037,
-	0xe7f106ad,
-	0x21f403e8,
-	0x0137f067,
-	0x069121f5,
-	0x1388e7f1,
-	0xf06721f4,
-	0x21f50137,
-	0xe7f106ad,
-	0x21f41388,
-/* 0x07a7: i2c_bitw */
-	0xf500f867,
-	0xf106ad21,
-	0xf403e8e7,
-	0x76bb6721,
-	0x0465b600,
-	0x659450f9,
-	0x0256bb04,
-	0x75fd50bd,
-	0xf550fc04,
-	0xb606f321,
-	0x11f40464,
-	0x88e7f118,
-	0x6721f413,
-	0xf50037f0,
-	0xf1069121,
-	0xf41388e7,
-/* 0x07e6: i2c_bitw_out */
-	0x00f86721,
-/* 0x07e8: i2c_bitr */
-	0xf50137f0,
-	0xf106ad21,
-	0xf403e8e7,
-	0x76bb6721,
-	0x0465b600,
-	0x659450f9,
-	0x0256bb04,
-	0x75fd50bd,
-	0xf550fc04,
-	0xb606f321,
-	0x11f40464,
-	0xde21f51b,
-	0x0037f006,
-	0x069121f5,
-	0x1388e7f1,
-	0xf06721f4,
-	0x31f4013c,
-/* 0x082d: i2c_bitr_done */
-/* 0x082f: i2c_get_byte */
-	0xf000f801,
-	0x47f00057,
-/* 0x0835: i2c_get_byte_next */
-	0x0154b608,
-	0xb60076bb,
-	0x50f90465,
-	0xbb046594,
-	0x50bd0256,
-	0xfc0475fd,
-	0xe821f550,
-	0x0464b607,
-	0xfd2b11f4,
-	0x42b60553,
-	0xd81bf401,
-	0xbb0137f0,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x07a721f5,
-/* 0x087f: i2c_get_byte_done */
-	0xf80464b6,
-/* 0x0881: i2c_put_byte */
-	0x0847f000,
-/* 0x0884: i2c_put_byte_next */
-	0xff0142b6,
-	0x76bb3854,
-	0x0465b600,
-	0x659450f9,
-	0x0256bb04,
-	0x75fd50bd,
-	0xf550fc04,
-	0xb607a721,
-	0x11f40464,
-	0x0046b034,
-	0xbbd81bf4,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x07e821f5,
-	0xf40464b6,
-	0x76bb0f11,
-	0x0136b000,
-	0xf4061bf4,
-/* 0x08da: i2c_put_byte_done */
-	0x00f80132,
-/* 0x08dc: i2c_addr */
-	0xb60076bb,
-	0x50f90465,
-	0xbb046594,
-	0x50bd0256,
-	0xfc0475fd,
-	0x1821f550,
-	0x0464b607,
-	0xe72911f4,
-	0xb6012ec3,
-	0x53fd0134,
-	0x0076bb05,
-	0xf90465b6,
-	0x04659450,
-	0xbd0256bb,
-	0x0475fd50,
-	0x21f550fc,
-	0x64b60881,
-/* 0x0921: i2c_addr_done */
-/* 0x0923: i2c_acquire_addr */
-	0xc700f804,
-	0xe4b6f8ce,
-	0x14e0b705,
-/* 0x092f: i2c_acquire */
-	0xf500f8d0,
-	0xf4092321,
-	0xd9f00421,
-	0x3321f403,
-/* 0x093e: i2c_release */
-	0x21f500f8,
-	0x21f40923,
-	0x03daf004,
-	0xf83321f4,
-/* 0x094d: i2c_recv */
-	0x0132f400,
-	0xb6f8c1c7,
-	0x16b00214,
-	0x3a1ff528,
-	0xf413a001,
-	0x0032980c,
-	0x0ccc13a0,
-	0xf4003198,
-	0xd0f90231,
-	0xd0f9e0f9,
-	0x000067f1,
-	0x100063f1,
-	0xbb016792,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x092f21f5,
-	0xfc0464b6,
-	0x00d6b0d0,
-	0x00b31bf5,
-	0xbb0057f0,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x08dc21f5,
-	0xf50464b6,
-	0xc700d011,
-	0x76bbe0c5,
-	0x0465b600,
-	0x659450f9,
-	0x0256bb04,
-	0x75fd50bd,
-	0xf550fc04,
-	0xb6088121,
-	0x11f50464,
-	0x57f000ad,
-	0x0076bb01,
-	0xf90465b6,
-	0x04659450,
-	0xbd0256bb,
-	0x0475fd50,
-	0x21f550fc,
-	0x64b608dc,
-	0x8a11f504,
-	0x0076bb00,
-	0xf90465b6,
-	0x04659450,
-	0xbd0256bb,
-	0x0475fd50,
-	0x21f550fc,
-	0x64b6082f,
-	0x6a11f404,
-	0xbbe05bcb,
-	0x65b60076,
-	0x9450f904,
-	0x56bb0465,
-	0xfd50bd02,
-	0x50fc0475,
-	0x077421f5,
-	0xb90464b6,
-	0x74bd025b,
-/* 0x0a53: i2c_recv_not_rd08 */
-	0xb0430ef4,
-	0x1bf401d6,
-	0x0057f03d,
-	0x08dc21f5,
-	0xc73311f4,
-	0x21f5e0c5,
-	0x11f40881,
-	0x0057f029,
-	0x08dc21f5,
-	0xc71f11f4,
-	0x21f5e0b5,
-	0x11f40881,
-	0x7421f515,
-	0xc774bd07,
-	0x1bf408c5,
-	0x0232f409,
-/* 0x0a93: i2c_recv_not_wr08 */
-/* 0x0a93: i2c_recv_done */
-	0xc7030ef4,
-	0x21f5f8ce,
-	0xe0fc093e,
-	0x12f4d0fc,
-	0x027cb90a,
-	0x02f121f5,
-/* 0x0aa8: i2c_recv_exit */
-/* 0x0aaa: i2c_init */
-	0x00f800f8,
-/* 0x0aac: test_recv */
-	0x05d817f1,
-	0xb60011cf,
-	0x07f10110,
-	0x01d005d8,
-	0xf104bd00,
-	0xf1d900e7,
-	0xf5134fe3,
-	0xf8022321,
-/* 0x0acd: test_init */
-	0x00e7f100,
-	0x2321f508,
-/* 0x0ad7: idle_recv */
-	0xf800f802,
-/* 0x0ad9: idle */
-	0x0031f400,
-	0x05d417f1,
-	0xb60011cf,
-	0x07f10110,
-	0x01d005d4,
-/* 0x0aef: idle_loop */
-	0xf004bd00,
-	0x32f45817,
-/* 0x0af5: idle_proc */
-/* 0x0af5: idle_proc_exec */
-	0xb910f902,
-	0x21f5021e,
-	0x10fc02fa,
-	0xf40911f4,
-	0x0ef40231,
-/* 0x0b09: idle_proc_next */
-	0x5810b6ef,
-	0xf4061fb8,
-	0x02f4e61b,
-	0x0028f4dd,
-	0x00c10ef4,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h
deleted file mode 100644
index c8b06cb77e72..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#ifndef __NVKM_PWR_OS_H__
-#define __NVKM_PWR_OS_H__
-
-/* Process names */
-#define PROC_KERN 0x52544e49
-#define PROC_IDLE 0x454c4449
-#define PROC_HOST 0x54534f48
-#define PROC_MEMX 0x584d454d
-#define PROC_PERF 0x46524550
-#define PROC_I2C_ 0x5f433249
-#define PROC_TEST 0x54534554
-
-/* KERN: message identifiers */
-#define KMSG_FIFO   0x00000000
-#define KMSG_ALARM  0x00000001
-
-/* MEMX: message identifiers */
-#define MEMX_MSG_INFO 0
-#define MEMX_MSG_EXEC 1
-
-/* MEMX: info types */
-#define MEMX_INFO_DATA  0
-#define MEMX_INFO_TRAIN 1
-
-/* MEMX: script opcode definitions */
-#define MEMX_ENTER  1
-#define MEMX_LEAVE  2
-#define MEMX_WR32   3
-#define MEMX_WAIT   4
-#define MEMX_DELAY  5
-#define MEMX_VBLANK 6
-#define MEMX_TRAIN  7
-
-/* I2C_: message identifiers */
-#define I2C__MSG_RD08 0
-#define I2C__MSG_WR08 1
-
-#define I2C__MSG_DATA0_PORT 24:31
-#define I2C__MSG_DATA0_ADDR 14:23
-
-#define I2C__MSG_DATA0_RD08_PORT I2C__MSG_DATA0_PORT
-#define I2C__MSG_DATA0_RD08_ADDR I2C__MSG_DATA0_ADDR
-#define I2C__MSG_DATA0_RD08_REG 0:7
-#define I2C__MSG_DATA1_RD08_VAL 0:7
-
-#define I2C__MSG_DATA0_WR08_PORT I2C__MSG_DATA0_PORT
-#define I2C__MSG_DATA0_WR08_ADDR I2C__MSG_DATA0_ADDR
-#define I2C__MSG_DATA0_WR08_SYNC 8:8
-#define I2C__MSG_DATA0_WR08_REG 0:7
-#define I2C__MSG_DATA1_WR08_VAL 0:7
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/perf.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/perf.fuc
deleted file mode 100644
index 38eadf705cbf..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/perf.fuc
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#ifdef INCLUDE_PROC
-process(PROC_PERF, #perf_init, #perf_recv)
-#endif
-
-/******************************************************************************
- * PERF data segment
- *****************************************************************************/
-#ifdef INCLUDE_DATA
-#endif
-
-/******************************************************************************
- * PERF code segment
- *****************************************************************************/
-#ifdef INCLUDE_CODE
-
-// description
-//
-// $r15 - current (perf)
-// $r14 - sender process name
-// $r13 - message
-// $r12 - data0
-// $r11 - data1
-// $r0  - zero
-perf_recv:
-	ret
-
-// description
-//
-// $r15 - current (perf)
-// $r0  - zero
-perf_init:
-	ret
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/test.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/test.fuc
deleted file mode 100644
index 0c3a71bf5459..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/test.fuc
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#ifdef INCLUDE_PROC
-process(PROC_TEST, #test_init, #test_recv)
-#endif
-
-/******************************************************************************
- * TEST data segment
- *****************************************************************************/
-#ifdef INCLUDE_DATA
-#endif
-
-/******************************************************************************
- * TEST code segment
- *****************************************************************************/
-#ifdef INCLUDE_CODE
-// description
-//
-// $r15 - current (test)
-// $r14 - sender process name
-// $r13 - message
-// $r12 - data0
-// $r11 - data1
-// $r0  - zero
-test_recv:
-	nv_iord($r1, NV_PPWR_DSCRATCH(2))
-	add b32 $r1 1
-	nv_iowr(NV_PPWR_DSCRATCH(2), $r1)
-	mov $r14 -0x2700 /* 0xd900, envyas grrr! */
-	sethi $r14 0x134f0000
-	call(timer)
-	ret
-
-// description
-//
-// $r15 - current (test)
-// $r0  - zero
-test_init:
-	mov $r14 0x800
-	call(timer)
-	ret
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/gk104.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/gk104.c
deleted file mode 100644
index d76612999b9f..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/gk104.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-
-#define nvd0_pwr_code gk104_pwr_code
-#define nvd0_pwr_data gk104_pwr_data
-#include "fuc/nvd0.fuc.h"
-
-static void
-gk104_pwr_pgob(struct nouveau_pwr *ppwr, bool enable)
-{
-	nv_mask(ppwr, 0x000200, 0x00001000, 0x00000000);
-	nv_rd32(ppwr, 0x000200);
-	nv_mask(ppwr, 0x000200, 0x08000000, 0x08000000);
-	msleep(50);
-
-	nv_mask(ppwr, 0x10a78c, 0x00000002, 0x00000002);
-	nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000001);
-	nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000000);
-
-	nv_mask(ppwr, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000);
-	msleep(50);
-
-	nv_mask(ppwr, 0x10a78c, 0x00000002, 0x00000000);
-	nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000001);
-	nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000000);
-
-	nv_mask(ppwr, 0x000200, 0x08000000, 0x00000000);
-	nv_mask(ppwr, 0x000200, 0x00001000, 0x00001000);
-	nv_rd32(ppwr, 0x000200);
-}
-
-struct nouveau_oclass *
-gk104_pwr_oclass = &(struct nvkm_pwr_impl) {
-	.base.handle = NV_SUBDEV(PWR, 0xe4),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_pwr_ctor,
-		.dtor = _nouveau_pwr_dtor,
-		.init = _nouveau_pwr_init,
-		.fini = _nouveau_pwr_fini,
-	},
-	.code.data = gk104_pwr_code,
-	.code.size = sizeof(gk104_pwr_code),
-	.data.data = gk104_pwr_data,
-	.data.size = sizeof(gk104_pwr_data),
-	.pgob = gk104_pwr_pgob,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c
deleted file mode 100644
index 7a9299d7159f..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c
+++ /dev/null
@@ -1,201 +0,0 @@
-#ifndef __NVKM_PWR_MEMX_H__
-#define __NVKM_PWR_MEMX_H__
-
-#include "priv.h"
-
-struct nouveau_memx {
-	struct nouveau_pwr *ppwr;
-	u32 base;
-	u32 size;
-	struct {
-		u32 mthd;
-		u32 size;
-		u32 data[64];
-	} c;
-};
-
-static void
-memx_out(struct nouveau_memx *memx)
-{
-	struct nouveau_pwr *ppwr = memx->ppwr;
-	int i;
-
-	if (memx->c.mthd) {
-		nv_wr32(ppwr, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd);
-		for (i = 0; i < memx->c.size; i++)
-			nv_wr32(ppwr, 0x10a1c4, memx->c.data[i]);
-		memx->c.mthd = 0;
-		memx->c.size = 0;
-	}
-}
-
-static void
-memx_cmd(struct nouveau_memx *memx, u32 mthd, u32 size, u32 data[])
-{
-	if ((memx->c.size + size >= ARRAY_SIZE(memx->c.data)) ||
-	    (memx->c.mthd && memx->c.mthd != mthd))
-		memx_out(memx);
-	memcpy(&memx->c.data[memx->c.size], data, size * sizeof(data[0]));
-	memx->c.size += size;
-	memx->c.mthd  = mthd;
-}
-
-int
-nouveau_memx_init(struct nouveau_pwr *ppwr, struct nouveau_memx **pmemx)
-{
-	struct nouveau_memx *memx;
-	u32 reply[2];
-	int ret;
-
-	ret = ppwr->message(ppwr, reply, PROC_MEMX, MEMX_MSG_INFO,
-					MEMX_INFO_DATA, 0);
-	if (ret)
-		return ret;
-
-	memx = *pmemx = kzalloc(sizeof(*memx), GFP_KERNEL);
-	if (!memx)
-		return -ENOMEM;
-	memx->ppwr = ppwr;
-	memx->base = reply[0];
-	memx->size = reply[1];
-
-	/* acquire data segment access */
-	do {
-		nv_wr32(ppwr, 0x10a580, 0x00000003);
-	} while (nv_rd32(ppwr, 0x10a580) != 0x00000003);
-	nv_wr32(ppwr, 0x10a1c0, 0x01000000 | memx->base);
-
-	return 0;
-}
-
-int
-nouveau_memx_fini(struct nouveau_memx **pmemx, bool exec)
-{
-	struct nouveau_memx *memx = *pmemx;
-	struct nouveau_pwr *ppwr = memx->ppwr;
-	u32 finish, reply[2];
-
-	/* flush the cache... */
-	memx_out(memx);
-
-	/* release data segment access */
-	finish = nv_rd32(ppwr, 0x10a1c0) & 0x00ffffff;
-	nv_wr32(ppwr, 0x10a580, 0x00000000);
-
-	/* call MEMX process to execute the script, and wait for reply */
-	if (exec) {
-		ppwr->message(ppwr, reply, PROC_MEMX, MEMX_MSG_EXEC,
-				 memx->base, finish);
-	}
-
-	nv_debug(memx->ppwr, "Exec took %uns, PPWR_IN %08x\n",
-		 reply[0], reply[1]);
-	kfree(memx);
-	return 0;
-}
-
-void
-nouveau_memx_wr32(struct nouveau_memx *memx, u32 addr, u32 data)
-{
-	nv_debug(memx->ppwr, "R[%06x] = 0x%08x\n", addr, data);
-	memx_cmd(memx, MEMX_WR32, 2, (u32[]){ addr, data });
-}
-
-void
-nouveau_memx_wait(struct nouveau_memx *memx,
-		  u32 addr, u32 mask, u32 data, u32 nsec)
-{
-	nv_debug(memx->ppwr, "R[%06x] & 0x%08x == 0x%08x, %d us\n",
-				addr, mask, data, nsec);
-	memx_cmd(memx, MEMX_WAIT, 4, (u32[]){ addr, mask, data, nsec });
-	memx_out(memx); /* fuc can't handle multiple */
-}
-
-void
-nouveau_memx_nsec(struct nouveau_memx *memx, u32 nsec)
-{
-	nv_debug(memx->ppwr, "    DELAY = %d ns\n", nsec);
-	memx_cmd(memx, MEMX_DELAY, 1, (u32[]){ nsec });
-	memx_out(memx); /* fuc can't handle multiple */
-}
-
-void
-nouveau_memx_wait_vblank(struct nouveau_memx *memx)
-{
-	struct nouveau_pwr *ppwr = memx->ppwr;
-	u32 heads, x, y, px = 0;
-	int i, head_sync;
-
-	if (nv_device(ppwr)->chipset < 0xd0) {
-		heads = nv_rd32(ppwr, 0x610050);
-		for (i = 0; i < 2; i++) {
-			/* Heuristic: sync to head with biggest resolution */
-			if (heads & (2 << (i << 3))) {
-				x = nv_rd32(ppwr, 0x610b40 + (0x540 * i));
-				y = (x & 0xffff0000) >> 16;
-				x &= 0x0000ffff;
-				if ((x * y) > px) {
-					px = (x * y);
-					head_sync = i;
-				}
-			}
-		}
-	}
-
-	if (px == 0) {
-		nv_debug(memx->ppwr, "WAIT VBLANK !NO ACTIVE HEAD\n");
-		return;
-	}
-
-	nv_debug(memx->ppwr, "WAIT VBLANK HEAD%d\n", head_sync);
-	memx_cmd(memx, MEMX_VBLANK, 1, (u32[]){ head_sync });
-	memx_out(memx); /* fuc can't handle multiple */
-}
-
-void
-nouveau_memx_train(struct nouveau_memx *memx)
-{
-	nv_debug(memx->ppwr, "   MEM TRAIN\n");
-	memx_cmd(memx, MEMX_TRAIN, 0, NULL);
-}
-
-int
-nouveau_memx_train_result(struct nouveau_pwr *ppwr, u32 *res, int rsize)
-{
-	u32 reply[2], base, size, i;
-	int ret;
-
-	ret = ppwr->message(ppwr, reply, PROC_MEMX, MEMX_MSG_INFO,
-					MEMX_INFO_TRAIN, 0);
-	if (ret)
-		return ret;
-
-	base = reply[0];
-	size = reply[1] >> 2;
-	if (size > rsize)
-		return -ENOMEM;
-
-	/* read the packet */
-	nv_wr32(ppwr, 0x10a1c0, 0x02000000 | base);
-
-	for (i = 0; i < size; i++)
-		res[i] = nv_rd32(ppwr, 0x10a1c4);
-
-	return 0;
-}
-
-void
-nouveau_memx_block(struct nouveau_memx *memx)
-{
-	nv_debug(memx->ppwr, "   HOST BLOCKED\n");
-	memx_cmd(memx, MEMX_ENTER, 0, NULL);
-}
-
-void
-nouveau_memx_unblock(struct nouveau_memx *memx)
-{
-	nv_debug(memx->ppwr, "   HOST UNBLOCKED\n");
-	memx_cmd(memx, MEMX_LEAVE, 0, NULL);
-}
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c
deleted file mode 100644
index 04ff7c3c34e9..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-#include "fuc/nv108.fuc.h"
-
-struct nouveau_oclass *
-nv108_pwr_oclass = &(struct nvkm_pwr_impl) {
-	.base.handle = NV_SUBDEV(PWR, 0x00),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_pwr_ctor,
-		.dtor = _nouveau_pwr_dtor,
-		.init = _nouveau_pwr_init,
-		.fini = _nouveau_pwr_fini,
-	},
-	.code.data = nv108_pwr_code,
-	.code.size = sizeof(nv108_pwr_code),
-	.data.data = nv108_pwr_data,
-	.data.size = sizeof(nv108_pwr_data),
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c
deleted file mode 100644
index 998d53076b8b..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-#include "fuc/nva3.fuc.h"
-
-static int
-nva3_pwr_init(struct nouveau_object *object)
-{
-	struct nouveau_pwr *ppwr = (void *)object;
-	nv_mask(ppwr, 0x022210, 0x00000001, 0x00000000);
-	nv_mask(ppwr, 0x022210, 0x00000001, 0x00000001);
-	return nouveau_pwr_init(ppwr);
-}
-
-struct nouveau_oclass *
-nva3_pwr_oclass = &(struct nvkm_pwr_impl) {
-	.base.handle = NV_SUBDEV(PWR, 0xa3),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_pwr_ctor,
-		.dtor = _nouveau_pwr_dtor,
-		.init = nva3_pwr_init,
-		.fini = _nouveau_pwr_fini,
-	},
-	.code.data = nva3_pwr_code,
-	.code.size = sizeof(nva3_pwr_code),
-	.data.data = nva3_pwr_data,
-	.data.size = sizeof(nva3_pwr_data),
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c
deleted file mode 100644
index 9a773e66efa4..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-#include "fuc/nvc0.fuc.h"
-
-struct nouveau_oclass *
-nvc0_pwr_oclass = &(struct nvkm_pwr_impl) {
-	.base.handle = NV_SUBDEV(PWR, 0xc0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_pwr_ctor,
-		.dtor = _nouveau_pwr_dtor,
-		.init = _nouveau_pwr_init,
-		.fini = _nouveau_pwr_fini,
-	},
-	.code.data = nvc0_pwr_code,
-	.code.size = sizeof(nvc0_pwr_code),
-	.data.data = nvc0_pwr_data,
-	.data.size = sizeof(nvc0_pwr_data),
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c
deleted file mode 100644
index 2b29be5d08ac..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-#include "fuc/nvd0.fuc.h"
-
-struct nouveau_oclass *
-nvd0_pwr_oclass = &(struct nvkm_pwr_impl) {
-	.base.handle = NV_SUBDEV(PWR, 0xd0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_pwr_ctor,
-		.dtor = _nouveau_pwr_dtor,
-		.init = _nouveau_pwr_init,
-		.fini = _nouveau_pwr_fini,
-	},
-	.code.data = nvd0_pwr_code,
-	.code.size = sizeof(nvd0_pwr_code),
-	.data.data = nvd0_pwr_data,
-	.data.size = sizeof(nvd0_pwr_data),
-}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h
deleted file mode 100644
index 3814a341db32..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h
+++ /dev/null
@@ -1,44 +0,0 @@
-#ifndef __NVKM_PWR_PRIV_H__
-#define __NVKM_PWR_PRIV_H__
-
-#include <subdev/pwr.h>
-#include <subdev/pwr/fuc/os.h>
-
-#define nouveau_pwr_create(p, e, o, d)                                         \
-	nouveau_pwr_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_pwr_destroy(p)                                                 \
-	nouveau_subdev_destroy(&(p)->base)
-#define nouveau_pwr_init(p) ({                                                 \
-	struct nouveau_pwr *_ppwr = (p);                                       \
-	_nouveau_pwr_init(nv_object(_ppwr));                                   \
-})
-#define nouveau_pwr_fini(p,s) ({                                               \
-	struct nouveau_pwr *_ppwr = (p);                                       \
-	_nouveau_pwr_fini(nv_object(_ppwr), (s));                              \
-})
-
-int nouveau_pwr_create_(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, int, void **);
-
-int _nouveau_pwr_ctor(struct nouveau_object *, struct nouveau_object *,
-		      struct nouveau_oclass *, void *, u32,
-		      struct nouveau_object **);
-#define _nouveau_pwr_dtor _nouveau_subdev_dtor
-int _nouveau_pwr_init(struct nouveau_object *);
-int _nouveau_pwr_fini(struct nouveau_object *, bool);
-
-struct nvkm_pwr_impl {
-	struct nouveau_oclass base;
-	struct {
-		u32 *data;
-		u32  size;
-	} code;
-	struct {
-		u32 *data;
-		u32  size;
-	} data;
-
-	void (*pgob)(struct nouveau_pwr *, bool);
-};
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/base.c b/drivers/gpu/drm/nouveau/core/subdev/therm/base.c
deleted file mode 100644
index 9ad01da6eacb..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/base.c
+++ /dev/null
@@ -1,374 +0,0 @@
-/*
- * Copyright 2012 The Nouveau community
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres
- */
-
-#include <core/object.h>
-#include <core/device.h>
-
-#include <subdev/bios.h>
-
-#include "priv.h"
-
-static int
-nouveau_therm_update_trip(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	struct nouveau_therm_trip_point *trip = priv->fan->bios.trip,
-					*cur_trip = NULL,
-					*last_trip = priv->last_trip;
-	u8  temp = therm->temp_get(therm);
-	u16 duty, i;
-
-	/* look for the trip point corresponding to the current temperature */
-	cur_trip = NULL;
-	for (i = 0; i < priv->fan->bios.nr_fan_trip; i++) {
-		if (temp >= trip[i].temp)
-			cur_trip = &trip[i];
-	}
-
-	/* account for the hysteresis cycle */
-	if (last_trip && temp <= (last_trip->temp) &&
-	    temp > (last_trip->temp - last_trip->hysteresis))
-		cur_trip = last_trip;
-
-	if (cur_trip) {
-		duty = cur_trip->fan_duty;
-		priv->last_trip = cur_trip;
-	} else {
-		duty = 0;
-		priv->last_trip = NULL;
-	}
-
-	return duty;
-}
-
-static int
-nouveau_therm_update_linear(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	u8  linear_min_temp = priv->fan->bios.linear_min_temp;
-	u8  linear_max_temp = priv->fan->bios.linear_max_temp;
-	u8  temp = therm->temp_get(therm);
-	u16 duty;
-
-	/* handle the non-linear part first */
-	if (temp < linear_min_temp)
-		return priv->fan->bios.min_duty;
-	else if (temp > linear_max_temp)
-		return priv->fan->bios.max_duty;
-
-	/* we are in the linear zone */
-	duty  = (temp - linear_min_temp);
-	duty *= (priv->fan->bios.max_duty - priv->fan->bios.min_duty);
-	duty /= (linear_max_temp - linear_min_temp);
-	duty += priv->fan->bios.min_duty;
-
-	return duty;
-}
-
-static void
-nouveau_therm_update(struct nouveau_therm *therm, int mode)
-{
-	struct nouveau_timer *ptimer = nouveau_timer(therm);
-	struct nouveau_therm_priv *priv = (void *)therm;
-	unsigned long flags;
-	bool immd = true;
-	bool poll = true;
-	int duty = -1;
-
-	spin_lock_irqsave(&priv->lock, flags);
-	if (mode < 0)
-		mode = priv->mode;
-	priv->mode = mode;
-
-	switch (mode) {
-	case NOUVEAU_THERM_CTRL_MANUAL:
-		ptimer->alarm_cancel(ptimer, &priv->alarm);
-		duty = nouveau_therm_fan_get(therm);
-		if (duty < 0)
-			duty = 100;
-		poll = false;
-		break;
-	case NOUVEAU_THERM_CTRL_AUTO:
-		switch(priv->fan->bios.fan_mode) {
-		case NVBIOS_THERM_FAN_TRIP:
-			duty = nouveau_therm_update_trip(therm);
-			break;
-		case NVBIOS_THERM_FAN_LINEAR:
-			duty = nouveau_therm_update_linear(therm);
-			break;
-		case NVBIOS_THERM_FAN_OTHER:
-			if (priv->cstate)
-				duty = priv->cstate;
-			poll = false;
-			break;
-		}
-		immd = false;
-		break;
-	case NOUVEAU_THERM_CTRL_NONE:
-	default:
-		ptimer->alarm_cancel(ptimer, &priv->alarm);
-		poll = false;
-	}
-
-	if (list_empty(&priv->alarm.head) && poll)
-		ptimer->alarm(ptimer, 1000000000ULL, &priv->alarm);
-	spin_unlock_irqrestore(&priv->lock, flags);
-
-	if (duty >= 0) {
-		nv_debug(therm, "FAN target request: %d%%\n", duty);
-		nouveau_therm_fan_set(therm, immd, duty);
-	}
-}
-
-int
-nouveau_therm_cstate(struct nouveau_therm *ptherm, int fan, int dir)
-{
-	struct nouveau_therm_priv *priv = (void *)ptherm;
-	if (!dir || (dir < 0 && fan < priv->cstate) ||
-		    (dir > 0 && fan > priv->cstate)) {
-		nv_debug(ptherm, "default fan speed -> %d%%\n", fan);
-		priv->cstate = fan;
-		nouveau_therm_update(ptherm, -1);
-	}
-	return 0;
-}
-
-static void
-nouveau_therm_alarm(struct nouveau_alarm *alarm)
-{
-	struct nouveau_therm_priv *priv =
-	       container_of(alarm, struct nouveau_therm_priv, alarm);
-	nouveau_therm_update(&priv->base, -1);
-}
-
-int
-nouveau_therm_fan_mode(struct nouveau_therm *therm, int mode)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	struct nouveau_device *device = nv_device(therm);
-	static const char *name[] = {
-		"disabled",
-		"manual",
-		"automatic"
-	};
-
-	/* The default PPWR ucode on fermi interferes with fan management */
-	if ((mode >= ARRAY_SIZE(name)) ||
-	    (mode != NOUVEAU_THERM_CTRL_NONE && device->card_type >= NV_C0 &&
-	     !nouveau_subdev(device, NVDEV_SUBDEV_PWR)))
-		return -EINVAL;
-
-	/* do not allow automatic fan management if the thermal sensor is
-	 * not available */
-	if (mode == NOUVEAU_THERM_CTRL_AUTO && therm->temp_get(therm) < 0)
-		return -EINVAL;
-
-	if (priv->mode == mode)
-		return 0;
-
-	nv_info(therm, "fan management: %s\n", name[mode]);
-	nouveau_therm_update(therm, mode);
-	return 0;
-}
-
-int
-nouveau_therm_attr_get(struct nouveau_therm *therm,
-		       enum nouveau_therm_attr_type type)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-
-	switch (type) {
-	case NOUVEAU_THERM_ATTR_FAN_MIN_DUTY:
-		return priv->fan->bios.min_duty;
-	case NOUVEAU_THERM_ATTR_FAN_MAX_DUTY:
-		return priv->fan->bios.max_duty;
-	case NOUVEAU_THERM_ATTR_FAN_MODE:
-		return priv->mode;
-	case NOUVEAU_THERM_ATTR_THRS_FAN_BOOST:
-		return priv->bios_sensor.thrs_fan_boost.temp;
-	case NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST:
-		return priv->bios_sensor.thrs_fan_boost.hysteresis;
-	case NOUVEAU_THERM_ATTR_THRS_DOWN_CLK:
-		return priv->bios_sensor.thrs_down_clock.temp;
-	case NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST:
-		return priv->bios_sensor.thrs_down_clock.hysteresis;
-	case NOUVEAU_THERM_ATTR_THRS_CRITICAL:
-		return priv->bios_sensor.thrs_critical.temp;
-	case NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST:
-		return priv->bios_sensor.thrs_critical.hysteresis;
-	case NOUVEAU_THERM_ATTR_THRS_SHUTDOWN:
-		return priv->bios_sensor.thrs_shutdown.temp;
-	case NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST:
-		return priv->bios_sensor.thrs_shutdown.hysteresis;
-	}
-
-	return -EINVAL;
-}
-
-int
-nouveau_therm_attr_set(struct nouveau_therm *therm,
-		       enum nouveau_therm_attr_type type, int value)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-
-	switch (type) {
-	case NOUVEAU_THERM_ATTR_FAN_MIN_DUTY:
-		if (value < 0)
-			value = 0;
-		if (value > priv->fan->bios.max_duty)
-			value = priv->fan->bios.max_duty;
-		priv->fan->bios.min_duty = value;
-		return 0;
-	case NOUVEAU_THERM_ATTR_FAN_MAX_DUTY:
-		if (value < 0)
-			value = 0;
-		if (value < priv->fan->bios.min_duty)
-			value = priv->fan->bios.min_duty;
-		priv->fan->bios.max_duty = value;
-		return 0;
-	case NOUVEAU_THERM_ATTR_FAN_MODE:
-		return nouveau_therm_fan_mode(therm, value);
-	case NOUVEAU_THERM_ATTR_THRS_FAN_BOOST:
-		priv->bios_sensor.thrs_fan_boost.temp = value;
-		priv->sensor.program_alarms(therm);
-		return 0;
-	case NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST:
-		priv->bios_sensor.thrs_fan_boost.hysteresis = value;
-		priv->sensor.program_alarms(therm);
-		return 0;
-	case NOUVEAU_THERM_ATTR_THRS_DOWN_CLK:
-		priv->bios_sensor.thrs_down_clock.temp = value;
-		priv->sensor.program_alarms(therm);
-		return 0;
-	case NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST:
-		priv->bios_sensor.thrs_down_clock.hysteresis = value;
-		priv->sensor.program_alarms(therm);
-		return 0;
-	case NOUVEAU_THERM_ATTR_THRS_CRITICAL:
-		priv->bios_sensor.thrs_critical.temp = value;
-		priv->sensor.program_alarms(therm);
-		return 0;
-	case NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST:
-		priv->bios_sensor.thrs_critical.hysteresis = value;
-		priv->sensor.program_alarms(therm);
-		return 0;
-	case NOUVEAU_THERM_ATTR_THRS_SHUTDOWN:
-		priv->bios_sensor.thrs_shutdown.temp = value;
-		priv->sensor.program_alarms(therm);
-		return 0;
-	case NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST:
-		priv->bios_sensor.thrs_shutdown.hysteresis = value;
-		priv->sensor.program_alarms(therm);
-		return 0;
-	}
-
-	return -EINVAL;
-}
-
-int
-_nouveau_therm_init(struct nouveau_object *object)
-{
-	struct nouveau_therm *therm = (void *)object;
-	struct nouveau_therm_priv *priv = (void *)therm;
-	int ret;
-
-	ret = nouveau_subdev_init(&therm->base);
-	if (ret)
-		return ret;
-
-	if (priv->suspend >= 0) {
-		/* restore the pwm value only when on manual or auto mode */
-		if (priv->suspend > 0)
-			nouveau_therm_fan_set(therm, true, priv->fan->percent);
-
-		nouveau_therm_fan_mode(therm, priv->suspend);
-	}
-	nouveau_therm_sensor_init(therm);
-	nouveau_therm_fan_init(therm);
-	return 0;
-}
-
-int
-_nouveau_therm_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nouveau_therm *therm = (void *)object;
-	struct nouveau_therm_priv *priv = (void *)therm;
-
-	nouveau_therm_fan_fini(therm, suspend);
-	nouveau_therm_sensor_fini(therm, suspend);
-	if (suspend) {
-		priv->suspend = priv->mode;
-		priv->mode = NOUVEAU_THERM_CTRL_NONE;
-	}
-
-	return nouveau_subdev_fini(&therm->base, suspend);
-}
-
-int
-nouveau_therm_create_(struct nouveau_object *parent,
-		      struct nouveau_object *engine,
-		      struct nouveau_oclass *oclass,
-		      int length, void **pobject)
-{
-	struct nouveau_therm_priv *priv;
-	int ret;
-
-	ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PTHERM",
-				     "therm", length, pobject);
-	priv = *pobject;
-	if (ret)
-		return ret;
-
-	nouveau_alarm_init(&priv->alarm, nouveau_therm_alarm);
-	spin_lock_init(&priv->lock);
-	spin_lock_init(&priv->sensor.alarm_program_lock);
-
-	priv->base.fan_get = nouveau_therm_fan_user_get;
-	priv->base.fan_set = nouveau_therm_fan_user_set;
-	priv->base.fan_sense = nouveau_therm_fan_sense;
-	priv->base.attr_get = nouveau_therm_attr_get;
-	priv->base.attr_set = nouveau_therm_attr_set;
-	priv->mode = priv->suspend = -1; /* undefined */
-	return 0;
-}
-
-int
-nouveau_therm_preinit(struct nouveau_therm *therm)
-{
-	nouveau_therm_sensor_ctor(therm);
-	nouveau_therm_ic_ctor(therm);
-	nouveau_therm_fan_ctor(therm);
-
-	nouveau_therm_fan_mode(therm, NOUVEAU_THERM_CTRL_AUTO);
-	nouveau_therm_sensor_preinit(therm);
-	return 0;
-}
-
-void
-_nouveau_therm_dtor(struct nouveau_object *object)
-{
-	struct nouveau_therm_priv *priv = (void *)object;
-	kfree(priv->fan);
-	nouveau_subdev_destroy(&priv->base.base);
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fan.c b/drivers/gpu/drm/nouveau/core/subdev/therm/fan.c
deleted file mode 100644
index 3656d605168f..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/fan.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- * 	    Martin Peres
- */
-
-#include "priv.h"
-
-#include <core/object.h>
-#include <core/device.h>
-
-#include <subdev/gpio.h>
-#include <subdev/timer.h>
-
-#include <subdev/bios/fan.h>
-
-static int
-nouveau_fan_update(struct nouveau_fan *fan, bool immediate, int target)
-{
-	struct nouveau_therm *therm = fan->parent;
-	struct nouveau_therm_priv *priv = (void *)therm;
-	struct nouveau_timer *ptimer = nouveau_timer(priv);
-	unsigned long flags;
-	int ret = 0;
-	int duty;
-
-	/* update target fan speed, restricting to allowed range */
-	spin_lock_irqsave(&fan->lock, flags);
-	if (target < 0)
-		target = fan->percent;
-	target = max_t(u8, target, fan->bios.min_duty);
-	target = min_t(u8, target, fan->bios.max_duty);
-	if (fan->percent != target) {
-		nv_debug(therm, "FAN target: %d\n", target);
-		fan->percent = target;
-	}
-
-	/* check that we're not already at the target duty cycle */
-	duty = fan->get(therm);
-	if (duty == target) {
-		spin_unlock_irqrestore(&fan->lock, flags);
-		return 0;
-	}
-
-	/* smooth out the fanspeed increase/decrease */
-	if (!immediate && duty >= 0) {
-		/* the constant "3" is a rough approximation taken from
-		 * nvidia's behaviour.
-		 * it is meant to bump the fan speed more incrementally
-		 */
-		if (duty < target)
-			duty = min(duty + 3, target);
-		else if (duty > target)
-			duty = max(duty - 3, target);
-	} else {
-		duty = target;
-	}
-
-	nv_debug(therm, "FAN update: %d\n", duty);
-	ret = fan->set(therm, duty);
-	if (ret) {
-		spin_unlock_irqrestore(&fan->lock, flags);
-		return ret;
-	}
-
-	/* fan speed updated, drop the fan lock before grabbing the
-	 * alarm-scheduling lock and risking a deadlock
-	 */
-	spin_unlock_irqrestore(&fan->lock, flags);
-
-	/* schedule next fan update, if not at target speed already */
-	if (list_empty(&fan->alarm.head) && target != duty) {
-		u16 bump_period = fan->bios.bump_period;
-		u16 slow_down_period = fan->bios.slow_down_period;
-		u64 delay;
-
-		if (duty > target)
-			delay = slow_down_period;
-		else if (duty == target)
-			delay = min(bump_period, slow_down_period) ;
-		else
-			delay = bump_period;
-
-		ptimer->alarm(ptimer, delay * 1000 * 1000, &fan->alarm);
-	}
-
-	return ret;
-}
-
-static void
-nouveau_fan_alarm(struct nouveau_alarm *alarm)
-{
-	struct nouveau_fan *fan = container_of(alarm, struct nouveau_fan, alarm);
-	nouveau_fan_update(fan, false, -1);
-}
-
-int
-nouveau_therm_fan_get(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	return priv->fan->get(therm);
-}
-
-int
-nouveau_therm_fan_set(struct nouveau_therm *therm, bool immediate, int percent)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	return nouveau_fan_update(priv->fan, immediate, percent);
-}
-
-int
-nouveau_therm_fan_sense(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	struct nouveau_timer *ptimer = nouveau_timer(therm);
-	struct nouveau_gpio *gpio = nouveau_gpio(therm);
-	u32 cycles, cur, prev;
-	u64 start, end, tach;
-
-	if (priv->fan->tach.func == DCB_GPIO_UNUSED)
-		return -ENODEV;
-
-	/* Time a complete rotation and extrapolate to RPM:
-	 * When the fan spins, it changes the value of GPIO FAN_SENSE.
-	 * We get 4 changes (0 -> 1 -> 0 -> 1) per complete rotation.
-	 */
-	start = ptimer->read(ptimer);
-	prev = gpio->get(gpio, 0, priv->fan->tach.func, priv->fan->tach.line);
-	cycles = 0;
-	do {
-		usleep_range(500, 1000); /* supports 0 < rpm < 7500 */
-
-		cur = gpio->get(gpio, 0, priv->fan->tach.func, priv->fan->tach.line);
-		if (prev != cur) {
-			if (!start)
-				start = ptimer->read(ptimer);
-			cycles++;
-			prev = cur;
-		}
-	} while (cycles < 5 && ptimer->read(ptimer) - start < 250000000);
-	end = ptimer->read(ptimer);
-
-	if (cycles == 5) {
-		tach = (u64)60000000000ULL;
-		do_div(tach, (end - start));
-		return tach;
-	} else
-		return 0;
-}
-
-int
-nouveau_therm_fan_user_get(struct nouveau_therm *therm)
-{
-	return nouveau_therm_fan_get(therm);
-}
-
-int
-nouveau_therm_fan_user_set(struct nouveau_therm *therm, int percent)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-
-	if (priv->mode != NOUVEAU_THERM_CTRL_MANUAL)
-		return -EINVAL;
-
-	return nouveau_therm_fan_set(therm, true, percent);
-}
-
-static void
-nouveau_therm_fan_set_defaults(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-
-	priv->fan->bios.pwm_freq = 0;
-	priv->fan->bios.min_duty = 0;
-	priv->fan->bios.max_duty = 100;
-	priv->fan->bios.bump_period = 500;
-	priv->fan->bios.slow_down_period = 2000;
-	priv->fan->bios.linear_min_temp = 40;
-	priv->fan->bios.linear_max_temp = 85;
-}
-
-static void
-nouveau_therm_fan_safety_checks(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-
-	if (priv->fan->bios.min_duty > 100)
-		priv->fan->bios.min_duty = 100;
-	if (priv->fan->bios.max_duty > 100)
-		priv->fan->bios.max_duty = 100;
-
-	if (priv->fan->bios.min_duty > priv->fan->bios.max_duty)
-		priv->fan->bios.min_duty = priv->fan->bios.max_duty;
-}
-
-int
-nouveau_therm_fan_init(struct nouveau_therm *therm)
-{
-	return 0;
-}
-
-int
-nouveau_therm_fan_fini(struct nouveau_therm *therm, bool suspend)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	struct nouveau_timer *ptimer = nouveau_timer(therm);
-
-	if (suspend)
-		ptimer->alarm_cancel(ptimer, &priv->fan->alarm);
-	return 0;
-}
-
-int
-nouveau_therm_fan_ctor(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	struct nouveau_gpio *gpio = nouveau_gpio(therm);
-	struct nouveau_bios *bios = nouveau_bios(therm);
-	struct dcb_gpio_func func;
-	int ret;
-
-	/* attempt to locate a drivable fan, and determine control method */
-	ret = gpio->find(gpio, 0, DCB_GPIO_FAN, 0xff, &func);
-	if (ret == 0) {
-		/* FIXME: is this really the place to perform such checks ? */
-		if (func.line != 16 && func.log[0] & DCB_GPIO_LOG_DIR_IN) {
-			nv_debug(therm, "GPIO_FAN is in input mode\n");
-			ret = -EINVAL;
-		} else {
-			ret = nouveau_fanpwm_create(therm, &func);
-			if (ret != 0)
-				ret = nouveau_fantog_create(therm, &func);
-		}
-	}
-
-	/* no controllable fan found, create a dummy fan module */
-	if (ret != 0) {
-		ret = nouveau_fannil_create(therm);
-		if (ret)
-			return ret;
-	}
-
-	nv_info(therm, "FAN control: %s\n", priv->fan->type);
-
-	/* read the current speed, it is useful when resuming */
-	priv->fan->percent = nouveau_therm_fan_get(therm);
-
-	/* attempt to detect a tachometer connection */
-	ret = gpio->find(gpio, 0, DCB_GPIO_FAN_SENSE, 0xff, &priv->fan->tach);
-	if (ret)
-		priv->fan->tach.func = DCB_GPIO_UNUSED;
-
-	/* initialise fan bump/slow update handling */
-	priv->fan->parent = therm;
-	nouveau_alarm_init(&priv->fan->alarm, nouveau_fan_alarm);
-	spin_lock_init(&priv->fan->lock);
-
-	/* other random init... */
-	nouveau_therm_fan_set_defaults(therm);
-	nvbios_perf_fan_parse(bios, &priv->fan->perf);
-	if (!nvbios_fan_parse(bios, &priv->fan->bios)) {
-		nv_debug(therm, "parsing the fan table failed\n");
-		if (nvbios_therm_fan_parse(bios, &priv->fan->bios))
-			nv_error(therm, "parsing both fan tables failed\n");
-	}
-	nouveau_therm_fan_safety_checks(therm);
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fannil.c b/drivers/gpu/drm/nouveau/core/subdev/therm/fannil.c
deleted file mode 100644
index b78c182e1d51..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/fannil.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-
-static int
-nouveau_fannil_get(struct nouveau_therm *therm)
-{
-	return -ENODEV;
-}
-
-static int
-nouveau_fannil_set(struct nouveau_therm *therm, int percent)
-{
-	return -ENODEV;
-}
-
-int
-nouveau_fannil_create(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *tpriv = (void *)therm;
-	struct nouveau_fan *priv;
-
-	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
-	tpriv->fan = priv;
-	if (!priv)
-		return -ENOMEM;
-
-	priv->type = "none / external";
-	priv->get = nouveau_fannil_get;
-	priv->set = nouveau_fannil_set;
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fanpwm.c b/drivers/gpu/drm/nouveau/core/subdev/therm/fanpwm.c
deleted file mode 100644
index c629d7f2a6a4..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/fanpwm.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- * 	    Martin Peres
- */
-
-#include <core/option.h>
-#include <subdev/gpio.h>
-#include <subdev/bios.h>
-#include <subdev/bios/fan.h>
-
-#include "priv.h"
-
-struct nouveau_fanpwm_priv {
-	struct nouveau_fan base;
-	struct dcb_gpio_func func;
-};
-
-static int
-nouveau_fanpwm_get(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *tpriv = (void *)therm;
-	struct nouveau_fanpwm_priv *priv = (void *)tpriv->fan;
-	struct nouveau_gpio *gpio = nouveau_gpio(therm);
-	int card_type = nv_device(therm)->card_type;
-	u32 divs, duty;
-	int ret;
-
-	ret = therm->pwm_get(therm, priv->func.line, &divs, &duty);
-	if (ret == 0 && divs) {
-		divs = max(divs, duty);
-		if (card_type <= NV_40 || (priv->func.log[0] & 1))
-			duty = divs - duty;
-		return (duty * 100) / divs;
-	}
-
-	return gpio->get(gpio, 0, priv->func.func, priv->func.line) * 100;
-}
-
-static int
-nouveau_fanpwm_set(struct nouveau_therm *therm, int percent)
-{
-	struct nouveau_therm_priv *tpriv = (void *)therm;
-	struct nouveau_fanpwm_priv *priv = (void *)tpriv->fan;
-	int card_type = nv_device(therm)->card_type;
-	u32 divs, duty;
-	int ret;
-
-	divs = priv->base.perf.pwm_divisor;
-	if (priv->base.bios.pwm_freq) {
-		divs = 1;
-		if (therm->pwm_clock)
-			divs = therm->pwm_clock(therm, priv->func.line);
-		divs /= priv->base.bios.pwm_freq;
-	}
-
-	duty = ((divs * percent) + 99) / 100;
-	if (card_type <= NV_40 || (priv->func.log[0] & 1))
-		duty = divs - duty;
-
-	ret = therm->pwm_set(therm, priv->func.line, divs, duty);
-	if (ret == 0)
-		ret = therm->pwm_ctrl(therm, priv->func.line, true);
-	return ret;
-}
-
-int
-nouveau_fanpwm_create(struct nouveau_therm *therm, struct dcb_gpio_func *func)
-{
-	struct nouveau_device *device = nv_device(therm);
-	struct nouveau_therm_priv *tpriv = (void *)therm;
-	struct nouveau_bios *bios = nouveau_bios(therm);
-	struct nouveau_fanpwm_priv *priv;
-	struct nvbios_therm_fan fan;
-	u32 divs, duty;
-
-	nvbios_fan_parse(bios, &fan);
-
-	if (!nouveau_boolopt(device->cfgopt, "NvFanPWM", func->param) ||
-	    !therm->pwm_ctrl || fan.type == NVBIOS_THERM_FAN_TOGGLE ||
-	     therm->pwm_get(therm, func->line, &divs, &duty) == -ENODEV)
-		return -ENODEV;
-
-	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
-	tpriv->fan = &priv->base;
-	if (!priv)
-		return -ENOMEM;
-
-	priv->base.type = "PWM";
-	priv->base.get = nouveau_fanpwm_get;
-	priv->base.set = nouveau_fanpwm_set;
-	priv->func = *func;
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fantog.c b/drivers/gpu/drm/nouveau/core/subdev/therm/fantog.c
deleted file mode 100644
index f69dab11f720..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/fantog.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright 2012 The Nouveau community
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres
- */
-
-#include "priv.h"
-
-#include <core/object.h>
-#include <core/device.h>
-
-#include <subdev/gpio.h>
-#include <subdev/timer.h>
-
-struct nouveau_fantog_priv {
-	struct nouveau_fan base;
-	struct nouveau_alarm alarm;
-	spinlock_t lock;
-	u32 period_us;
-	u32 percent;
-	struct dcb_gpio_func func;
-};
-
-static void
-nouveau_fantog_update(struct nouveau_fantog_priv *priv, int percent)
-{
-	struct nouveau_therm_priv *tpriv = (void *)priv->base.parent;
-	struct nouveau_timer *ptimer = nouveau_timer(tpriv);
-	struct nouveau_gpio *gpio = nouveau_gpio(tpriv);
-	unsigned long flags;
-	int duty;
-
-	spin_lock_irqsave(&priv->lock, flags);
-	if (percent < 0)
-		percent = priv->percent;
-	priv->percent = percent;
-
-	duty = !gpio->get(gpio, 0, DCB_GPIO_FAN, 0xff);
-	gpio->set(gpio, 0, DCB_GPIO_FAN, 0xff, duty);
-
-	if (list_empty(&priv->alarm.head) && percent != (duty * 100)) {
-		u64 next_change = (percent * priv->period_us) / 100;
-		if (!duty)
-			next_change = priv->period_us - next_change;
-		ptimer->alarm(ptimer, next_change * 1000, &priv->alarm);
-	}
-	spin_unlock_irqrestore(&priv->lock, flags);
-}
-
-static void
-nouveau_fantog_alarm(struct nouveau_alarm *alarm)
-{
-	struct nouveau_fantog_priv *priv =
-	       container_of(alarm, struct nouveau_fantog_priv, alarm);
-	nouveau_fantog_update(priv, -1);
-}
-
-static int
-nouveau_fantog_get(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *tpriv = (void *)therm;
-	struct nouveau_fantog_priv *priv = (void *)tpriv->fan;
-	return priv->percent;
-}
-
-static int
-nouveau_fantog_set(struct nouveau_therm *therm, int percent)
-{
-	struct nouveau_therm_priv *tpriv = (void *)therm;
-	struct nouveau_fantog_priv *priv = (void *)tpriv->fan;
-	if (therm->pwm_ctrl)
-		therm->pwm_ctrl(therm, priv->func.line, false);
-	nouveau_fantog_update(priv, percent);
-	return 0;
-}
-
-int
-nouveau_fantog_create(struct nouveau_therm *therm, struct dcb_gpio_func *func)
-{
-	struct nouveau_therm_priv *tpriv = (void *)therm;
-	struct nouveau_fantog_priv *priv;
-	int ret;
-
-	if (therm->pwm_ctrl) {
-		ret = therm->pwm_ctrl(therm, func->line, false);
-		if (ret)
-			return ret;
-	}
-
-	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
-	tpriv->fan = &priv->base;
-	if (!priv)
-		return -ENOMEM;
-
-	priv->base.type = "toggle";
-	priv->base.get = nouveau_fantog_get;
-	priv->base.set = nouveau_fantog_set;
-	nouveau_alarm_init(&priv->alarm, nouveau_fantog_alarm);
-	priv->period_us = 100000; /* 10Hz */
-	priv->percent = 100;
-	priv->func = *func;
-	spin_lock_init(&priv->lock);
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/gm107.c b/drivers/gpu/drm/nouveau/core/subdev/therm/gm107.c
deleted file mode 100644
index 668cf3322285..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/gm107.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright 2014 Martin Peres
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres
- */
-
-#include "priv.h"
-
-struct gm107_therm_priv {
-	struct nouveau_therm_priv base;
-};
-
-static int
-gm107_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
-{
-	/* nothing to do, it seems hardwired */
-	return 0;
-}
-
-static int
-gm107_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
-{
-	*divs = nv_rd32(therm, 0x10eb20) & 0x1fff;
-	*duty = nv_rd32(therm, 0x10eb24) & 0x1fff;
-	return 0;
-}
-
-static int
-gm107_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
-{
-	nv_mask(therm, 0x10eb10, 0x1fff, divs); /* keep the high bits */
-	nv_wr32(therm, 0x10eb14, duty | 0x80000000);
-	return 0;
-}
-
-static int
-gm107_fan_pwm_clock(struct nouveau_therm *therm, int line)
-{
-	return nv_device(therm)->crystal * 1000;
-}
-
-static int
-gm107_therm_ctor(struct nouveau_object *parent,
-		struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct gm107_therm_priv *priv;
-	int ret;
-
-	ret = nouveau_therm_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.base.pwm_ctrl = gm107_fan_pwm_ctrl;
-	priv->base.base.pwm_get = gm107_fan_pwm_get;
-	priv->base.base.pwm_set = gm107_fan_pwm_set;
-	priv->base.base.pwm_clock = gm107_fan_pwm_clock;
-	priv->base.base.temp_get = nv84_temp_get;
-	priv->base.base.fan_sense = nva3_therm_fan_sense;
-	priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling;
-	return nouveau_therm_preinit(&priv->base.base);
-}
-
-struct nouveau_oclass
-gm107_therm_oclass = {
-	.handle = NV_SUBDEV(THERM, 0x117),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = gm107_therm_ctor,
-		.dtor = _nouveau_therm_dtor,
-		.init = nvd0_therm_init,
-		.fini = nv84_therm_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/ic.c b/drivers/gpu/drm/nouveau/core/subdev/therm/ic.c
deleted file mode 100644
index ca9ad9fd47be..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/ic.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * Copyright 2012 Nouveau community
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres
- */
-
-#include "priv.h"
-
-#include <subdev/i2c.h>
-#include <subdev/bios/extdev.h>
-
-static bool
-probe_monitoring_device(struct nouveau_i2c_port *i2c,
-			struct i2c_board_info *info, void *data)
-{
-	struct nouveau_therm_priv *priv = data;
-	struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
-	struct i2c_client *client;
-
-	request_module("%s%s", I2C_MODULE_PREFIX, info->type);
-
-	client = i2c_new_device(&i2c->adapter, info);
-	if (!client)
-		return false;
-
-	if (!client->dev.driver ||
-	    to_i2c_driver(client->dev.driver)->detect(client, info)) {
-		i2c_unregister_device(client);
-		return false;
-	}
-
-	nv_info(priv,
-		"Found an %s at address 0x%x (controlled by lm_sensors, "
-		"temp offset %+i C)\n",
-		info->type, info->addr, sensor->offset_constant);
-	priv->ic = client;
-
-	return true;
-}
-
-static struct nouveau_i2c_board_info
-nv_board_infos[] = {
-	{ { I2C_BOARD_INFO("w83l785ts", 0x2d) }, 0 },
-	{ { I2C_BOARD_INFO("w83781d", 0x2d) }, 0  },
-	{ { I2C_BOARD_INFO("adt7473", 0x2e) }, 40  },
-	{ { I2C_BOARD_INFO("adt7473", 0x2d) }, 40  },
-	{ { I2C_BOARD_INFO("adt7473", 0x2c) }, 40  },
-	{ { I2C_BOARD_INFO("f75375", 0x2e) }, 0  },
-	{ { I2C_BOARD_INFO("lm99", 0x4c) }, 0  },
-	{ { I2C_BOARD_INFO("lm90", 0x4c) }, 0  },
-	{ { I2C_BOARD_INFO("lm90", 0x4d) }, 0  },
-	{ { I2C_BOARD_INFO("adm1021", 0x18) }, 0  },
-	{ { I2C_BOARD_INFO("adm1021", 0x19) }, 0  },
-	{ { I2C_BOARD_INFO("adm1021", 0x1a) }, 0  },
-	{ { I2C_BOARD_INFO("adm1021", 0x29) }, 0  },
-	{ { I2C_BOARD_INFO("adm1021", 0x2a) }, 0  },
-	{ { I2C_BOARD_INFO("adm1021", 0x2b) }, 0  },
-	{ { I2C_BOARD_INFO("adm1021", 0x4c) }, 0  },
-	{ { I2C_BOARD_INFO("adm1021", 0x4d) }, 0  },
-	{ { I2C_BOARD_INFO("adm1021", 0x4e) }, 0  },
-	{ { I2C_BOARD_INFO("lm63", 0x18) }, 0  },
-	{ { I2C_BOARD_INFO("lm63", 0x4e) }, 0  },
-	{ }
-};
-
-void
-nouveau_therm_ic_ctor(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	struct nouveau_bios *bios = nouveau_bios(therm);
-	struct nouveau_i2c *i2c = nouveau_i2c(therm);
-	struct nvbios_extdev_func extdev_entry;
-
-	if (!nvbios_extdev_find(bios, NVBIOS_EXTDEV_LM89, &extdev_entry)) {
-		struct nouveau_i2c_board_info board[] = {
-		  { { I2C_BOARD_INFO("lm90", extdev_entry.addr >> 1) }, 0},
-		  { }
-		};
-
-		i2c->identify(i2c, NV_I2C_DEFAULT(0), "monitoring device",
-			      board, probe_monitoring_device, therm);
-		if (priv->ic)
-			return;
-	}
-
-	if (!nvbios_extdev_find(bios, NVBIOS_EXTDEV_ADT7473, &extdev_entry)) {
-		struct nouveau_i2c_board_info board[] = {
-		  { { I2C_BOARD_INFO("adt7473", extdev_entry.addr >> 1) }, 20 },
-		  { }
-		};
-
-		i2c->identify(i2c, NV_I2C_DEFAULT(0), "monitoring device",
-			      board, probe_monitoring_device, therm);
-		if (priv->ic)
-			return;
-	}
-
-	/* The vbios doesn't provide the address of an exisiting monitoring
-	   device. Let's try our static list.
-	 */
-	i2c->identify(i2c, NV_I2C_DEFAULT(0), "monitoring device",
-		      nv_board_infos, probe_monitoring_device, therm);
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/therm/nv40.c
deleted file mode 100644
index 002e51b3af93..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/nv40.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- * 	    Martin Peres
- */
-
-#include "priv.h"
-
-struct nv40_therm_priv {
-	struct nouveau_therm_priv base;
-};
-
-enum nv40_sensor_style { INVALID_STYLE = -1, OLD_STYLE = 0, NEW_STYLE = 1 };
-
-static enum nv40_sensor_style
-nv40_sensor_style(struct nouveau_therm *therm)
-{
-	struct nouveau_device *device = nv_device(therm);
-
-	switch (device->chipset) {
-	case 0x43:
-	case 0x44:
-	case 0x4a:
-	case 0x47:
-		return OLD_STYLE;
-
-	case 0x46:
-	case 0x49:
-	case 0x4b:
-	case 0x4e:
-	case 0x4c:
-	case 0x67:
-	case 0x68:
-	case 0x63:
-		return NEW_STYLE;
-	default:
-		return INVALID_STYLE;
-	}
-}
-
-static int
-nv40_sensor_setup(struct nouveau_therm *therm)
-{
-	enum nv40_sensor_style style = nv40_sensor_style(therm);
-
-	/* enable ADC readout and disable the ALARM threshold */
-	if (style == NEW_STYLE) {
-		nv_mask(therm, 0x15b8, 0x80000000, 0);
-		nv_wr32(therm, 0x15b0, 0x80003fff);
-		mdelay(20); /* wait for the temperature to stabilize */
-		return nv_rd32(therm, 0x15b4) & 0x3fff;
-	} else if (style == OLD_STYLE) {
-		nv_wr32(therm, 0x15b0, 0xff);
-		mdelay(20); /* wait for the temperature to stabilize */
-		return nv_rd32(therm, 0x15b4) & 0xff;
-	} else
-		return -ENODEV;
-}
-
-static int
-nv40_temp_get(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
-	enum nv40_sensor_style style = nv40_sensor_style(therm);
-	int core_temp;
-
-	if (style == NEW_STYLE) {
-		nv_wr32(therm, 0x15b0, 0x80003fff);
-		core_temp = nv_rd32(therm, 0x15b4) & 0x3fff;
-	} else if (style == OLD_STYLE) {
-		nv_wr32(therm, 0x15b0, 0xff);
-		core_temp = nv_rd32(therm, 0x15b4) & 0xff;
-	} else
-		return -ENODEV;
-
-	/* if the slope or the offset is unset, do no use the sensor */
-	if (!sensor->slope_div || !sensor->slope_mult ||
-	    !sensor->offset_num || !sensor->offset_den)
-	    return -ENODEV;
-
-	core_temp = core_temp * sensor->slope_mult / sensor->slope_div;
-	core_temp = core_temp + sensor->offset_num / sensor->offset_den;
-	core_temp = core_temp + sensor->offset_constant - 8;
-
-	/* reserve negative temperatures for errors */
-	if (core_temp < 0)
-		core_temp = 0;
-
-	return core_temp;
-}
-
-static int
-nv40_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
-{
-	u32 mask = enable ? 0x80000000 : 0x0000000;
-	if      (line == 2) nv_mask(therm, 0x0010f0, 0x80000000, mask);
-	else if (line == 9) nv_mask(therm, 0x0015f4, 0x80000000, mask);
-	else {
-		nv_error(therm, "unknown pwm ctrl for gpio %d\n", line);
-		return -ENODEV;
-	}
-	return 0;
-}
-
-static int
-nv40_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
-{
-	if (line == 2) {
-		u32 reg = nv_rd32(therm, 0x0010f0);
-		if (reg & 0x80000000) {
-			*duty = (reg & 0x7fff0000) >> 16;
-			*divs = (reg & 0x00007fff);
-			return 0;
-		}
-	} else
-	if (line == 9) {
-		u32 reg = nv_rd32(therm, 0x0015f4);
-		if (reg & 0x80000000) {
-			*divs = nv_rd32(therm, 0x0015f8);
-			*duty = (reg & 0x7fffffff);
-			return 0;
-		}
-	} else {
-		nv_error(therm, "unknown pwm ctrl for gpio %d\n", line);
-		return -ENODEV;
-	}
-
-	return -EINVAL;
-}
-
-static int
-nv40_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
-{
-	if (line == 2) {
-		nv_mask(therm, 0x0010f0, 0x7fff7fff, (duty << 16) | divs);
-	} else
-	if (line == 9) {
-		nv_wr32(therm, 0x0015f8, divs);
-		nv_mask(therm, 0x0015f4, 0x7fffffff, duty);
-	} else {
-		nv_error(therm, "unknown pwm ctrl for gpio %d\n", line);
-		return -ENODEV;
-	}
-
-	return 0;
-}
-
-void
-nv40_therm_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_therm *therm = nouveau_therm(subdev);
-	uint32_t stat = nv_rd32(therm, 0x1100);
-
-	/* traitement */
-
-	/* ack all IRQs */
-	nv_wr32(therm, 0x1100, 0x70000);
-
-	nv_error(therm, "THERM received an IRQ: stat = %x\n", stat);
-}
-
-static int
-nv40_therm_ctor(struct nouveau_object *parent,
-		struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nv40_therm_priv *priv;
-	int ret;
-
-	ret = nouveau_therm_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.base.pwm_ctrl = nv40_fan_pwm_ctrl;
-	priv->base.base.pwm_get = nv40_fan_pwm_get;
-	priv->base.base.pwm_set = nv40_fan_pwm_set;
-	priv->base.base.temp_get = nv40_temp_get;
-	priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling;
-	nv_subdev(priv)->intr = nv40_therm_intr;
-	return nouveau_therm_preinit(&priv->base.base);
-}
-
-static int
-nv40_therm_init(struct nouveau_object *object)
-{
-	struct nouveau_therm *therm = (void *)object;
-
-	nv40_sensor_setup(therm);
-
-	return _nouveau_therm_init(object);
-}
-
-struct nouveau_oclass
-nv40_therm_oclass = {
-	.handle = NV_SUBDEV(THERM, 0x40),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv40_therm_ctor,
-		.dtor = _nouveau_therm_dtor,
-		.init = nv40_therm_init,
-		.fini = _nouveau_therm_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/therm/nv50.c
deleted file mode 100644
index 321db927d638..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/nv50.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- * 	    Martin Peres
- */
-
-#include "priv.h"
-
-struct nv50_therm_priv {
-	struct nouveau_therm_priv base;
-};
-
-static int
-pwm_info(struct nouveau_therm *therm, int *line, int *ctrl, int *indx)
-{
-	if (*line == 0x04) {
-		*ctrl = 0x00e100;
-		*line = 4;
-		*indx = 0;
-	} else
-	if (*line == 0x09) {
-		*ctrl = 0x00e100;
-		*line = 9;
-		*indx = 1;
-	} else
-	if (*line == 0x10) {
-		*ctrl = 0x00e28c;
-		*line = 0;
-		*indx = 0;
-	} else {
-		nv_error(therm, "unknown pwm ctrl for gpio %d\n", *line);
-		return -ENODEV;
-	}
-
-	return 0;
-}
-
-int
-nv50_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
-{
-	u32 data = enable ? 0x00000001 : 0x00000000;
-	int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id);
-	if (ret == 0)
-		nv_mask(therm, ctrl, 0x00010001 << line, data << line);
-	return ret;
-}
-
-int
-nv50_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
-{
-	int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id);
-	if (ret)
-		return ret;
-
-	if (nv_rd32(therm, ctrl) & (1 << line)) {
-		*divs = nv_rd32(therm, 0x00e114 + (id * 8));
-		*duty = nv_rd32(therm, 0x00e118 + (id * 8));
-		return 0;
-	}
-
-	return -EINVAL;
-}
-
-int
-nv50_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
-{
-	int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id);
-	if (ret)
-		return ret;
-
-	nv_wr32(therm, 0x00e114 + (id * 8), divs);
-	nv_wr32(therm, 0x00e118 + (id * 8), duty | 0x80000000);
-	return 0;
-}
-
-int
-nv50_fan_pwm_clock(struct nouveau_therm *therm, int line)
-{
-	int chipset = nv_device(therm)->chipset;
-	int crystal = nv_device(therm)->crystal;
-	int pwm_clock;
-
-	/* determine the PWM source clock */
-	if (chipset > 0x50 && chipset < 0x94) {
-		u8 pwm_div = nv_rd32(therm, 0x410c);
-		if (nv_rd32(therm, 0xc040) & 0x800000) {
-			/* Use the HOST clock (100 MHz)
-			* Where does this constant(2.4) comes from? */
-			pwm_clock = (100000000 >> pwm_div) * 10 / 24;
-		} else {
-			/* Where does this constant(20) comes from? */
-			pwm_clock = (crystal * 1000) >> pwm_div;
-			pwm_clock /= 20;
-		}
-	} else {
-		pwm_clock = (crystal * 1000) / 20;
-	}
-
-	return pwm_clock;
-}
-
-static void
-nv50_sensor_setup(struct nouveau_therm *therm)
-{
-	nv_mask(therm, 0x20010, 0x40000000, 0x0);
-	mdelay(20); /* wait for the temperature to stabilize */
-}
-
-static int
-nv50_temp_get(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
-	int core_temp;
-
-	core_temp = nv_rd32(therm, 0x20014) & 0x3fff;
-
-	/* if the slope or the offset is unset, do no use the sensor */
-	if (!sensor->slope_div || !sensor->slope_mult ||
-	    !sensor->offset_num || !sensor->offset_den)
-	    return -ENODEV;
-
-	core_temp = core_temp * sensor->slope_mult / sensor->slope_div;
-	core_temp = core_temp + sensor->offset_num / sensor->offset_den;
-	core_temp = core_temp + sensor->offset_constant - 8;
-
-	/* reserve negative temperatures for errors */
-	if (core_temp < 0)
-		core_temp = 0;
-
-	return core_temp;
-}
-
-static int
-nv50_therm_ctor(struct nouveau_object *parent,
-		struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nv50_therm_priv *priv;
-	int ret;
-
-	ret = nouveau_therm_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.base.pwm_ctrl = nv50_fan_pwm_ctrl;
-	priv->base.base.pwm_get = nv50_fan_pwm_get;
-	priv->base.base.pwm_set = nv50_fan_pwm_set;
-	priv->base.base.pwm_clock = nv50_fan_pwm_clock;
-	priv->base.base.temp_get = nv50_temp_get;
-	priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling;
-	nv_subdev(priv)->intr = nv40_therm_intr;
-
-	return nouveau_therm_preinit(&priv->base.base);
-}
-
-static int
-nv50_therm_init(struct nouveau_object *object)
-{
-	struct nouveau_therm *therm = (void *)object;
-
-	nv50_sensor_setup(therm);
-
-	return _nouveau_therm_init(object);
-}
-
-struct nouveau_oclass
-nv50_therm_oclass = {
-	.handle = NV_SUBDEV(THERM, 0x50),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_therm_ctor,
-		.dtor = _nouveau_therm_dtor,
-		.init = nv50_therm_init,
-		.fini = _nouveau_therm_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c b/drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c
deleted file mode 100644
index 14e2e09bfc24..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- * 	    Martin Peres
- */
-
-#include "priv.h"
-#include <subdev/fuse.h>
-
-struct nv84_therm_priv {
-	struct nouveau_therm_priv base;
-};
-
-int
-nv84_temp_get(struct nouveau_therm *therm)
-{
-	struct nouveau_fuse *fuse = nouveau_fuse(therm);
-
-	if (nv_ro32(fuse, 0x1a8) == 1)
-		return nv_rd32(therm, 0x20400);
-	else
-		return -ENODEV;
-}
-
-void
-nv84_sensor_setup(struct nouveau_therm *therm)
-{
-	struct nouveau_fuse *fuse = nouveau_fuse(therm);
-
-	/* enable temperature reading for cards with insane defaults */
-	if (nv_ro32(fuse, 0x1a8) == 1) {
-		nv_mask(therm, 0x20008, 0x80008000, 0x80000000);
-		nv_mask(therm, 0x2000c, 0x80000003, 0x00000000);
-		mdelay(20); /* wait for the temperature to stabilize */
-	}
-}
-
-static void
-nv84_therm_program_alarms(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
-	unsigned long flags;
-
-	spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags);
-
-	/* enable RISING and FALLING IRQs for shutdown, THRS 0, 1, 2 and 4 */
-	nv_wr32(therm, 0x20000, 0x000003ff);
-
-	/* shutdown: The computer should be shutdown when reached */
-	nv_wr32(therm, 0x20484, sensor->thrs_shutdown.hysteresis);
-	nv_wr32(therm, 0x20480, sensor->thrs_shutdown.temp);
-
-	/* THRS_1 : fan boost*/
-	nv_wr32(therm, 0x204c4, sensor->thrs_fan_boost.temp);
-
-	/* THRS_2 : critical */
-	nv_wr32(therm, 0x204c0, sensor->thrs_critical.temp);
-
-	/* THRS_4 : down clock */
-	nv_wr32(therm, 0x20414, sensor->thrs_down_clock.temp);
-	spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags);
-
-	nv_debug(therm,
-		 "Programmed thresholds [ %d(%d), %d(%d), %d(%d), %d(%d) ]\n",
-		 sensor->thrs_fan_boost.temp, sensor->thrs_fan_boost.hysteresis,
-		 sensor->thrs_down_clock.temp,
-		 sensor->thrs_down_clock.hysteresis,
-		 sensor->thrs_critical.temp, sensor->thrs_critical.hysteresis,
-		 sensor->thrs_shutdown.temp, sensor->thrs_shutdown.hysteresis);
-
-}
-
-/* must be called with alarm_program_lock taken ! */
-static void
-nv84_therm_threshold_hyst_emulation(struct nouveau_therm *therm,
-				   uint32_t thrs_reg, u8 status_bit,
-				   const struct nvbios_therm_threshold *thrs,
-				   enum nouveau_therm_thrs thrs_name)
-{
-	enum nouveau_therm_thrs_direction direction;
-	enum nouveau_therm_thrs_state prev_state, new_state;
-	int temp, cur;
-
-	prev_state = nouveau_therm_sensor_get_threshold_state(therm, thrs_name);
-	temp = nv_rd32(therm, thrs_reg);
-
-	/* program the next threshold */
-	if (temp == thrs->temp) {
-		nv_wr32(therm, thrs_reg, thrs->temp - thrs->hysteresis);
-		new_state = NOUVEAU_THERM_THRS_HIGHER;
-	} else {
-		nv_wr32(therm, thrs_reg, thrs->temp);
-		new_state = NOUVEAU_THERM_THRS_LOWER;
-	}
-
-	/* fix the state (in case someone reprogrammed the alarms) */
-	cur = therm->temp_get(therm);
-	if (new_state == NOUVEAU_THERM_THRS_LOWER && cur > thrs->temp)
-		new_state = NOUVEAU_THERM_THRS_HIGHER;
-	else if (new_state == NOUVEAU_THERM_THRS_HIGHER &&
-		cur < thrs->temp - thrs->hysteresis)
-		new_state = NOUVEAU_THERM_THRS_LOWER;
-	nouveau_therm_sensor_set_threshold_state(therm, thrs_name, new_state);
-
-	/* find the direction */
-	if (prev_state < new_state)
-		direction = NOUVEAU_THERM_THRS_RISING;
-	else if (prev_state > new_state)
-		direction = NOUVEAU_THERM_THRS_FALLING;
-	else
-		return;
-
-	/* advertise a change in direction */
-	nouveau_therm_sensor_event(therm, thrs_name, direction);
-}
-
-static void
-nv84_therm_intr(struct nouveau_subdev *subdev)
-{
-	struct nouveau_therm *therm = nouveau_therm(subdev);
-	struct nouveau_therm_priv *priv = (void *)therm;
-	struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
-	unsigned long flags;
-	uint32_t intr;
-
-	spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags);
-
-	intr = nv_rd32(therm, 0x20100) & 0x3ff;
-
-	/* THRS_4: downclock */
-	if (intr & 0x002) {
-		nv84_therm_threshold_hyst_emulation(therm, 0x20414, 24,
-						  &sensor->thrs_down_clock,
-						  NOUVEAU_THERM_THRS_DOWNCLOCK);
-		intr &= ~0x002;
-	}
-
-	/* shutdown */
-	if (intr & 0x004) {
-		nv84_therm_threshold_hyst_emulation(therm, 0x20480, 20,
-						   &sensor->thrs_shutdown,
-						   NOUVEAU_THERM_THRS_SHUTDOWN);
-		intr &= ~0x004;
-	}
-
-	/* THRS_1 : fan boost */
-	if (intr & 0x008) {
-		nv84_therm_threshold_hyst_emulation(therm, 0x204c4, 21,
-						   &sensor->thrs_fan_boost,
-						   NOUVEAU_THERM_THRS_FANBOOST);
-		intr &= ~0x008;
-	}
-
-	/* THRS_2 : critical */
-	if (intr & 0x010) {
-		nv84_therm_threshold_hyst_emulation(therm, 0x204c0, 22,
-						   &sensor->thrs_critical,
-						   NOUVEAU_THERM_THRS_CRITICAL);
-		intr &= ~0x010;
-	}
-
-	if (intr)
-		nv_error(therm, "unhandled intr 0x%08x\n", intr);
-
-	/* ACK everything */
-	nv_wr32(therm, 0x20100, 0xffffffff);
-	nv_wr32(therm, 0x1100, 0x10000); /* PBUS */
-
-	spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags);
-}
-
-static int
-nv84_therm_init(struct nouveau_object *object)
-{
-	struct nv84_therm_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_therm_init(&priv->base.base);
-	if (ret)
-		return ret;
-
-	nv84_sensor_setup(&priv->base.base);
-
-	return 0;
-}
-
-static int
-nv84_therm_ctor(struct nouveau_object *parent,
-		struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nv84_therm_priv *priv;
-	int ret;
-
-	ret = nouveau_therm_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.base.pwm_ctrl = nv50_fan_pwm_ctrl;
-	priv->base.base.pwm_get = nv50_fan_pwm_get;
-	priv->base.base.pwm_set = nv50_fan_pwm_set;
-	priv->base.base.pwm_clock = nv50_fan_pwm_clock;
-	priv->base.base.temp_get = nv84_temp_get;
-	priv->base.sensor.program_alarms = nv84_therm_program_alarms;
-	nv_subdev(priv)->intr = nv84_therm_intr;
-
-	/* init the thresholds */
-	nouveau_therm_sensor_set_threshold_state(&priv->base.base,
-						 NOUVEAU_THERM_THRS_SHUTDOWN,
-						 NOUVEAU_THERM_THRS_LOWER);
-	nouveau_therm_sensor_set_threshold_state(&priv->base.base,
-						 NOUVEAU_THERM_THRS_FANBOOST,
-						 NOUVEAU_THERM_THRS_LOWER);
-	nouveau_therm_sensor_set_threshold_state(&priv->base.base,
-						 NOUVEAU_THERM_THRS_CRITICAL,
-						 NOUVEAU_THERM_THRS_LOWER);
-	nouveau_therm_sensor_set_threshold_state(&priv->base.base,
-						 NOUVEAU_THERM_THRS_DOWNCLOCK,
-						 NOUVEAU_THERM_THRS_LOWER);
-
-	return nouveau_therm_preinit(&priv->base.base);
-}
-
-int
-nv84_therm_fini(struct nouveau_object *object, bool suspend)
-{
-	/* Disable PTherm IRQs */
-	nv_wr32(object, 0x20000, 0x00000000);
-
-	/* ACK all PTherm IRQs */
-	nv_wr32(object, 0x20100, 0xffffffff);
-	nv_wr32(object, 0x1100, 0x10000); /* PBUS */
-
-	return _nouveau_therm_fini(object, suspend);
-}
-
-struct nouveau_oclass
-nv84_therm_oclass = {
-	.handle = NV_SUBDEV(THERM, 0x84),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv84_therm_ctor,
-		.dtor = _nouveau_therm_dtor,
-		.init = nv84_therm_init,
-		.fini = nv84_therm_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c
deleted file mode 100644
index 7893357a7e9f..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/gpio.h>
-
-#include "priv.h"
-
-struct nva3_therm_priv {
-	struct nouveau_therm_priv base;
-};
-
-int
-nva3_therm_fan_sense(struct nouveau_therm *therm)
-{
-	u32 tach = nv_rd32(therm, 0x00e728) & 0x0000ffff;
-	u32 ctrl = nv_rd32(therm, 0x00e720);
-	if (ctrl & 0x00000001)
-		return tach * 60 / 2;
-	return -ENODEV;
-}
-
-static int
-nva3_therm_init(struct nouveau_object *object)
-{
-	struct nva3_therm_priv *priv = (void *)object;
-	struct dcb_gpio_func *tach = &priv->base.fan->tach;
-	int ret;
-
-	ret = nouveau_therm_init(&priv->base.base);
-	if (ret)
-		return ret;
-
-	nv84_sensor_setup(&priv->base.base);
-
-	/* enable fan tach, count revolutions per-second */
-	nv_mask(priv, 0x00e720, 0x00000003, 0x00000002);
-	if (tach->func != DCB_GPIO_UNUSED) {
-		nv_wr32(priv, 0x00e724, nv_device(priv)->crystal * 1000);
-		nv_mask(priv, 0x00e720, 0x001f0000, tach->line << 16);
-		nv_mask(priv, 0x00e720, 0x00000001, 0x00000001);
-	}
-	nv_mask(priv, 0x00e720, 0x00000002, 0x00000000);
-
-	return 0;
-}
-
-static int
-nva3_therm_ctor(struct nouveau_object *parent,
-		struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nva3_therm_priv *priv;
-	int ret;
-
-	ret = nouveau_therm_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.base.pwm_ctrl = nv50_fan_pwm_ctrl;
-	priv->base.base.pwm_get = nv50_fan_pwm_get;
-	priv->base.base.pwm_set = nv50_fan_pwm_set;
-	priv->base.base.pwm_clock = nv50_fan_pwm_clock;
-	priv->base.base.temp_get = nv84_temp_get;
-	priv->base.base.fan_sense = nva3_therm_fan_sense;
-	priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling;
-	return nouveau_therm_preinit(&priv->base.base);
-}
-
-struct nouveau_oclass
-nva3_therm_oclass = {
-	.handle = NV_SUBDEV(THERM, 0xa3),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nva3_therm_ctor,
-		.dtor = _nouveau_therm_dtor,
-		.init = nva3_therm_init,
-		.fini = nv84_therm_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c b/drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c
deleted file mode 100644
index b70f7cc649b8..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "priv.h"
-
-struct nvd0_therm_priv {
-	struct nouveau_therm_priv base;
-};
-
-static int
-pwm_info(struct nouveau_therm *therm, int line)
-{
-	u32 gpio = nv_rd32(therm, 0x00d610 + (line * 0x04));
-
-	switch (gpio & 0x000000c0) {
-	case 0x00000000: /* normal mode, possibly pwm forced off by us */
-	case 0x00000040: /* nvio special */
-		switch (gpio & 0x0000001f) {
-		case 0x00: return 2;
-		case 0x19: return 1;
-		case 0x1c: return 0;
-		case 0x1e: return 2;
-		default:
-			break;
-		}
-	default:
-		break;
-	}
-
-	nv_error(therm, "GPIO %d unknown PWM: 0x%08x\n", line, gpio);
-	return -ENODEV;
-}
-
-static int
-nvd0_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
-{
-	u32 data = enable ? 0x00000040 : 0x00000000;
-	int indx = pwm_info(therm, line);
-	if (indx < 0)
-		return indx;
-	else if (indx < 2)
-		nv_mask(therm, 0x00d610 + (line * 0x04), 0x000000c0, data);
-	/* nothing to do for indx == 2, it seems hardwired to PTHERM */
-	return 0;
-}
-
-static int
-nvd0_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
-{
-	int indx = pwm_info(therm, line);
-	if (indx < 0)
-		return indx;
-	else if (indx < 2) {
-		if (nv_rd32(therm, 0x00d610 + (line * 0x04)) & 0x00000040) {
-			*divs = nv_rd32(therm, 0x00e114 + (indx * 8));
-			*duty = nv_rd32(therm, 0x00e118 + (indx * 8));
-			return 0;
-		}
-	} else if (indx == 2) {
-		*divs = nv_rd32(therm, 0x0200d8) & 0x1fff;
-		*duty = nv_rd32(therm, 0x0200dc) & 0x1fff;
-		return 0;
-	}
-
-	return -EINVAL;
-}
-
-static int
-nvd0_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
-{
-	int indx = pwm_info(therm, line);
-	if (indx < 0)
-		return indx;
-	else if (indx < 2) {
-		nv_wr32(therm, 0x00e114 + (indx * 8), divs);
-		nv_wr32(therm, 0x00e118 + (indx * 8), duty | 0x80000000);
-	} else if (indx == 2) {
-		nv_mask(therm, 0x0200d8, 0x1fff, divs); /* keep the high bits */
-		nv_wr32(therm, 0x0200dc, duty | 0x40000000);
-	}
-	return 0;
-}
-
-static int
-nvd0_fan_pwm_clock(struct nouveau_therm *therm, int line)
-{
-	int indx = pwm_info(therm, line);
-	if (indx < 0)
-		return 0;
-	else if (indx < 2)
-		return (nv_device(therm)->crystal * 1000) / 20;
-	else
-		return nv_device(therm)->crystal * 1000 / 10;
-}
-
-int
-nvd0_therm_init(struct nouveau_object *object)
-{
-	struct nvd0_therm_priv *priv = (void *)object;
-	int ret;
-
-	ret = nouveau_therm_init(&priv->base.base);
-	if (ret)
-		return ret;
-
-	/* enable fan tach, count revolutions per-second */
-	nv_mask(priv, 0x00e720, 0x00000003, 0x00000002);
-	if (priv->base.fan->tach.func != DCB_GPIO_UNUSED) {
-		nv_mask(priv, 0x00d79c, 0x000000ff, priv->base.fan->tach.line);
-		nv_wr32(priv, 0x00e724, nv_device(priv)->crystal * 1000);
-		nv_mask(priv, 0x00e720, 0x00000001, 0x00000001);
-	}
-	nv_mask(priv, 0x00e720, 0x00000002, 0x00000000);
-
-	return 0;
-}
-
-static int
-nvd0_therm_ctor(struct nouveau_object *parent,
-		struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nvd0_therm_priv *priv;
-	int ret;
-
-	ret = nouveau_therm_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	nv84_sensor_setup(&priv->base.base);
-
-	priv->base.base.pwm_ctrl = nvd0_fan_pwm_ctrl;
-	priv->base.base.pwm_get = nvd0_fan_pwm_get;
-	priv->base.base.pwm_set = nvd0_fan_pwm_set;
-	priv->base.base.pwm_clock = nvd0_fan_pwm_clock;
-	priv->base.base.temp_get = nv84_temp_get;
-	priv->base.base.fan_sense = nva3_therm_fan_sense;
-	priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling;
-	return nouveau_therm_preinit(&priv->base.base);
-}
-
-struct nouveau_oclass
-nvd0_therm_oclass = {
-	.handle = NV_SUBDEV(THERM, 0xd0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvd0_therm_ctor,
-		.dtor = _nouveau_therm_dtor,
-		.init = nvd0_therm_init,
-		.fini = nv84_therm_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/priv.h b/drivers/gpu/drm/nouveau/core/subdev/therm/priv.h
deleted file mode 100644
index 7dba8c281a0b..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/priv.h
+++ /dev/null
@@ -1,159 +0,0 @@
-#ifndef __NVTHERM_PRIV_H__
-#define __NVTHERM_PRIV_H__
-
-/*
- * Copyright 2012 The Nouveau community
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres
- */
-
-#include <subdev/therm.h>
-
-#include <subdev/bios/extdev.h>
-#include <subdev/bios/gpio.h>
-#include <subdev/bios/perf.h>
-#include <subdev/bios/therm.h>
-#include <subdev/timer.h>
-
-struct nouveau_fan {
-	struct nouveau_therm *parent;
-	const char *type;
-
-	struct nvbios_therm_fan bios;
-	struct nvbios_perf_fan perf;
-
-	struct nouveau_alarm alarm;
-	spinlock_t lock;
-	int percent;
-
-	int (*get)(struct nouveau_therm *therm);
-	int (*set)(struct nouveau_therm *therm, int percent);
-
-	struct dcb_gpio_func tach;
-};
-
-enum nouveau_therm_thrs_direction {
-	NOUVEAU_THERM_THRS_FALLING = 0,
-	NOUVEAU_THERM_THRS_RISING = 1
-};
-
-enum nouveau_therm_thrs_state {
-	NOUVEAU_THERM_THRS_LOWER = 0,
-	NOUVEAU_THERM_THRS_HIGHER = 1
-};
-
-enum nouveau_therm_thrs {
-	NOUVEAU_THERM_THRS_FANBOOST = 0,
-	NOUVEAU_THERM_THRS_DOWNCLOCK = 1,
-	NOUVEAU_THERM_THRS_CRITICAL = 2,
-	NOUVEAU_THERM_THRS_SHUTDOWN = 3,
-	NOUVEAU_THERM_THRS_NR
-};
-
-struct nouveau_therm_priv {
-	struct nouveau_therm base;
-
-	/* automatic thermal management */
-	struct nouveau_alarm alarm;
-	spinlock_t lock;
-	struct nouveau_therm_trip_point *last_trip;
-	int mode;
-	int cstate;
-	int suspend;
-
-	/* bios */
-	struct nvbios_therm_sensor bios_sensor;
-
-	/* fan priv */
-	struct nouveau_fan *fan;
-
-	/* alarms priv */
-	struct {
-		spinlock_t alarm_program_lock;
-		struct nouveau_alarm therm_poll_alarm;
-		enum nouveau_therm_thrs_state alarm_state[NOUVEAU_THERM_THRS_NR];
-		void (*program_alarms)(struct nouveau_therm *);
-	} sensor;
-
-	/* what should be done if the card overheats */
-	struct {
-		void (*downclock)(struct nouveau_therm *, bool active);
-		void (*pause)(struct nouveau_therm *, bool active);
-	} emergency;
-
-	/* ic */
-	struct i2c_client *ic;
-};
-
-int nouveau_therm_fan_mode(struct nouveau_therm *therm, int mode);
-int nouveau_therm_attr_get(struct nouveau_therm *therm,
-		       enum nouveau_therm_attr_type type);
-int nouveau_therm_attr_set(struct nouveau_therm *therm,
-		       enum nouveau_therm_attr_type type, int value);
-
-void nouveau_therm_ic_ctor(struct nouveau_therm *therm);
-
-int nouveau_therm_sensor_ctor(struct nouveau_therm *therm);
-
-int nouveau_therm_fan_ctor(struct nouveau_therm *therm);
-int nouveau_therm_fan_init(struct nouveau_therm *therm);
-int nouveau_therm_fan_fini(struct nouveau_therm *therm, bool suspend);
-int nouveau_therm_fan_get(struct nouveau_therm *therm);
-int nouveau_therm_fan_set(struct nouveau_therm *therm, bool now, int percent);
-int nouveau_therm_fan_user_get(struct nouveau_therm *therm);
-int nouveau_therm_fan_user_set(struct nouveau_therm *therm, int percent);
-
-int nouveau_therm_fan_sense(struct nouveau_therm *therm);
-
-int nouveau_therm_preinit(struct nouveau_therm *);
-
-int nouveau_therm_sensor_init(struct nouveau_therm *therm);
-int nouveau_therm_sensor_fini(struct nouveau_therm *therm, bool suspend);
-void nouveau_therm_sensor_preinit(struct nouveau_therm *);
-void nouveau_therm_sensor_set_threshold_state(struct nouveau_therm *therm,
-					     enum nouveau_therm_thrs thrs,
-					     enum nouveau_therm_thrs_state st);
-enum nouveau_therm_thrs_state
-nouveau_therm_sensor_get_threshold_state(struct nouveau_therm *therm,
-					 enum nouveau_therm_thrs thrs);
-void nouveau_therm_sensor_event(struct nouveau_therm *therm,
-			        enum nouveau_therm_thrs thrs,
-			        enum nouveau_therm_thrs_direction dir);
-void nouveau_therm_program_alarms_polling(struct nouveau_therm *therm);
-
-void nv40_therm_intr(struct nouveau_subdev *);
-int nv50_fan_pwm_ctrl(struct nouveau_therm *, int, bool);
-int nv50_fan_pwm_get(struct nouveau_therm *, int, u32 *, u32 *);
-int nv50_fan_pwm_set(struct nouveau_therm *, int, u32, u32);
-int nv50_fan_pwm_clock(struct nouveau_therm *, int);
-int nv84_temp_get(struct nouveau_therm *therm);
-void nv84_sensor_setup(struct nouveau_therm *therm);
-int nv84_therm_fini(struct nouveau_object *object, bool suspend);
-
-int nva3_therm_fan_sense(struct nouveau_therm *);
-
-int nvd0_therm_init(struct nouveau_object *object);
-
-int nouveau_fanpwm_create(struct nouveau_therm *, struct dcb_gpio_func *);
-int nouveau_fantog_create(struct nouveau_therm *, struct dcb_gpio_func *);
-int nouveau_fannil_create(struct nouveau_therm *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/temp.c b/drivers/gpu/drm/nouveau/core/subdev/therm/temp.c
deleted file mode 100644
index 6212537b90c5..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/temp.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * Copyright 2012 The Nouveau community
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres
- */
-
-#include "priv.h"
-
-#include <core/object.h>
-#include <core/device.h>
-
-#include <subdev/bios.h>
-
-static void
-nouveau_therm_temp_set_defaults(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-
-	priv->bios_sensor.offset_constant = 0;
-
-	priv->bios_sensor.thrs_fan_boost.temp = 90;
-	priv->bios_sensor.thrs_fan_boost.hysteresis = 3;
-
-	priv->bios_sensor.thrs_down_clock.temp = 95;
-	priv->bios_sensor.thrs_down_clock.hysteresis = 3;
-
-	priv->bios_sensor.thrs_critical.temp = 105;
-	priv->bios_sensor.thrs_critical.hysteresis = 5;
-
-	priv->bios_sensor.thrs_shutdown.temp = 135;
-	priv->bios_sensor.thrs_shutdown.hysteresis = 5; /*not that it matters */
-}
-
-
-static void
-nouveau_therm_temp_safety_checks(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	struct nvbios_therm_sensor *s = &priv->bios_sensor;
-
-	/* enforce a minimum hysteresis on thresholds */
-	s->thrs_fan_boost.hysteresis = max_t(u8, s->thrs_fan_boost.hysteresis, 2);
-	s->thrs_down_clock.hysteresis = max_t(u8, s->thrs_down_clock.hysteresis, 2);
-	s->thrs_critical.hysteresis = max_t(u8, s->thrs_critical.hysteresis, 2);
-	s->thrs_shutdown.hysteresis = max_t(u8, s->thrs_shutdown.hysteresis, 2);
-}
-
-/* must be called with alarm_program_lock taken ! */
-void nouveau_therm_sensor_set_threshold_state(struct nouveau_therm *therm,
-					     enum nouveau_therm_thrs thrs,
-					     enum nouveau_therm_thrs_state st)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	priv->sensor.alarm_state[thrs] = st;
-}
-
-/* must be called with alarm_program_lock taken ! */
-enum nouveau_therm_thrs_state
-nouveau_therm_sensor_get_threshold_state(struct nouveau_therm *therm,
-					 enum nouveau_therm_thrs thrs)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	return priv->sensor.alarm_state[thrs];
-}
-
-static void
-nv_poweroff_work(struct work_struct *work)
-{
-	orderly_poweroff(true);
-	kfree(work);
-}
-
-void nouveau_therm_sensor_event(struct nouveau_therm *therm,
-			        enum nouveau_therm_thrs thrs,
-			        enum nouveau_therm_thrs_direction dir)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	bool active;
-	const char *thresolds[] = {
-		"fanboost", "downclock", "critical", "shutdown"
-	};
-	int temperature = therm->temp_get(therm);
-
-	if (thrs < 0 || thrs > 3)
-		return;
-
-	if (dir == NOUVEAU_THERM_THRS_FALLING)
-		nv_info(therm, "temperature (%i C) went below the '%s' threshold\n",
-			temperature, thresolds[thrs]);
-	else
-		nv_info(therm, "temperature (%i C) hit the '%s' threshold\n",
-			temperature, thresolds[thrs]);
-
-	active = (dir == NOUVEAU_THERM_THRS_RISING);
-	switch (thrs) {
-	case NOUVEAU_THERM_THRS_FANBOOST:
-		if (active) {
-			nouveau_therm_fan_set(therm, true, 100);
-			nouveau_therm_fan_mode(therm, NOUVEAU_THERM_CTRL_AUTO);
-		}
-		break;
-	case NOUVEAU_THERM_THRS_DOWNCLOCK:
-		if (priv->emergency.downclock)
-			priv->emergency.downclock(therm, active);
-		break;
-	case NOUVEAU_THERM_THRS_CRITICAL:
-		if (priv->emergency.pause)
-			priv->emergency.pause(therm, active);
-		break;
-	case NOUVEAU_THERM_THRS_SHUTDOWN:
-		if (active) {
-			struct work_struct *work;
-
-			work = kmalloc(sizeof(*work), GFP_ATOMIC);
-			if (work) {
-				INIT_WORK(work, nv_poweroff_work);
-				schedule_work(work);
-			}
-		}
-		break;
-	case NOUVEAU_THERM_THRS_NR:
-		break;
-	}
-
-}
-
-/* must be called with alarm_program_lock taken ! */
-static void
-nouveau_therm_threshold_hyst_polling(struct nouveau_therm *therm,
-				   const struct nvbios_therm_threshold *thrs,
-				   enum nouveau_therm_thrs thrs_name)
-{
-	enum nouveau_therm_thrs_direction direction;
-	enum nouveau_therm_thrs_state prev_state, new_state;
-	int temp = therm->temp_get(therm);
-
-	prev_state = nouveau_therm_sensor_get_threshold_state(therm, thrs_name);
-
-	if (temp >= thrs->temp && prev_state == NOUVEAU_THERM_THRS_LOWER) {
-		direction = NOUVEAU_THERM_THRS_RISING;
-		new_state = NOUVEAU_THERM_THRS_HIGHER;
-	} else if (temp <= thrs->temp - thrs->hysteresis &&
-			prev_state == NOUVEAU_THERM_THRS_HIGHER) {
-		direction = NOUVEAU_THERM_THRS_FALLING;
-		new_state = NOUVEAU_THERM_THRS_LOWER;
-	} else
-		return; /* nothing to do */
-
-	nouveau_therm_sensor_set_threshold_state(therm, thrs_name, new_state);
-	nouveau_therm_sensor_event(therm, thrs_name, direction);
-}
-
-static void
-alarm_timer_callback(struct nouveau_alarm *alarm)
-{
-	struct nouveau_therm_priv *priv =
-	container_of(alarm, struct nouveau_therm_priv, sensor.therm_poll_alarm);
-	struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
-	struct nouveau_timer *ptimer = nouveau_timer(priv);
-	struct nouveau_therm *therm = &priv->base;
-	unsigned long flags;
-
-	spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags);
-
-	nouveau_therm_threshold_hyst_polling(therm, &sensor->thrs_fan_boost,
-					     NOUVEAU_THERM_THRS_FANBOOST);
-
-	nouveau_therm_threshold_hyst_polling(therm, &sensor->thrs_down_clock,
-					     NOUVEAU_THERM_THRS_DOWNCLOCK);
-
-	nouveau_therm_threshold_hyst_polling(therm, &sensor->thrs_critical,
-					     NOUVEAU_THERM_THRS_CRITICAL);
-
-	nouveau_therm_threshold_hyst_polling(therm, &sensor->thrs_shutdown,
-					     NOUVEAU_THERM_THRS_SHUTDOWN);
-
-	spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags);
-
-	/* schedule the next poll in one second */
-	if (therm->temp_get(therm) >= 0 && list_empty(&alarm->head))
-		ptimer->alarm(ptimer, 1000000000ULL, alarm);
-}
-
-void
-nouveau_therm_program_alarms_polling(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
-
-	nv_debug(therm,
-		 "programmed thresholds [ %d(%d), %d(%d), %d(%d), %d(%d) ]\n",
-		 sensor->thrs_fan_boost.temp, sensor->thrs_fan_boost.hysteresis,
-		 sensor->thrs_down_clock.temp,
-		 sensor->thrs_down_clock.hysteresis,
-		 sensor->thrs_critical.temp, sensor->thrs_critical.hysteresis,
-		 sensor->thrs_shutdown.temp, sensor->thrs_shutdown.hysteresis);
-
-	alarm_timer_callback(&priv->sensor.therm_poll_alarm);
-}
-
-int
-nouveau_therm_sensor_init(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	priv->sensor.program_alarms(therm);
-	return 0;
-}
-
-int
-nouveau_therm_sensor_fini(struct nouveau_therm *therm, bool suspend)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	struct nouveau_timer *ptimer = nouveau_timer(therm);
-
-	if (suspend)
-		ptimer->alarm_cancel(ptimer, &priv->sensor.therm_poll_alarm);
-	return 0;
-}
-
-void
-nouveau_therm_sensor_preinit(struct nouveau_therm *therm)
-{
-	const char *sensor_avail = "yes";
-
-	if (therm->temp_get(therm) < 0)
-		sensor_avail = "no";
-
-	nv_info(therm, "internal sensor: %s\n", sensor_avail);
-}
-
-int
-nouveau_therm_sensor_ctor(struct nouveau_therm *therm)
-{
-	struct nouveau_therm_priv *priv = (void *)therm;
-	struct nouveau_bios *bios = nouveau_bios(therm);
-
-	nouveau_alarm_init(&priv->sensor.therm_poll_alarm, alarm_timer_callback);
-
-	nouveau_therm_temp_set_defaults(therm);
-	if (nvbios_therm_sensor_parse(bios, NVBIOS_THERM_DOMAIN_CORE,
-				      &priv->bios_sensor))
-		nv_error(therm, "nvbios_therm_sensor_parse failed\n");
-	nouveau_therm_temp_safety_checks(therm);
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/base.c b/drivers/gpu/drm/nouveau/core/subdev/timer/base.c
deleted file mode 100644
index cf8a0e0f8ee3..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/timer/base.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "subdev/timer.h"
-
-bool
-nouveau_timer_wait_eq(void *obj, u64 nsec, u32 addr, u32 mask, u32 data)
-{
-	struct nouveau_timer *ptimer = nouveau_timer(obj);
-	u64 time0;
-
-	time0 = ptimer->read(ptimer);
-	do {
-		if (nv_iclass(obj, NV_SUBDEV_CLASS)) {
-			if ((nv_rd32(obj, addr) & mask) == data)
-				return true;
-		} else {
-			if ((nv_ro32(obj, addr) & mask) == data)
-				return true;
-		}
-	} while (ptimer->read(ptimer) - time0 < nsec);
-
-	return false;
-}
-
-bool
-nouveau_timer_wait_ne(void *obj, u64 nsec, u32 addr, u32 mask, u32 data)
-{
-	struct nouveau_timer *ptimer = nouveau_timer(obj);
-	u64 time0;
-
-	time0 = ptimer->read(ptimer);
-	do {
-		if (nv_iclass(obj, NV_SUBDEV_CLASS)) {
-			if ((nv_rd32(obj, addr) & mask) != data)
-				return true;
-		} else {
-			if ((nv_ro32(obj, addr) & mask) != data)
-				return true;
-		}
-	} while (ptimer->read(ptimer) - time0 < nsec);
-
-	return false;
-}
-
-bool
-nouveau_timer_wait_cb(void *obj, u64 nsec, bool (*func)(void *), void *data)
-{
-	struct nouveau_timer *ptimer = nouveau_timer(obj);
-	u64 time0;
-
-	time0 = ptimer->read(ptimer);
-	do {
-		if (func(data) == true)
-			return true;
-	} while (ptimer->read(ptimer) - time0 < nsec);
-
-	return false;
-}
-
-void
-nouveau_timer_alarm(void *obj, u32 nsec, struct nouveau_alarm *alarm)
-{
-	struct nouveau_timer *ptimer = nouveau_timer(obj);
-	ptimer->alarm(ptimer, nsec, alarm);
-}
-
-void
-nouveau_timer_alarm_cancel(void *obj, struct nouveau_alarm *alarm)
-{
-	struct nouveau_timer *ptimer = nouveau_timer(obj);
-	ptimer->alarm_cancel(ptimer, alarm);
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/timer/gk20a.c
deleted file mode 100644
index 37484db1f7fc..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/timer/gk20a.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv04.h"
-
-static int
-gk20a_timer_init(struct nouveau_object *object)
-{
-	struct nv04_timer_priv *priv = (void *)object;
-	u32 hi = upper_32_bits(priv->suspend_time);
-	u32 lo = lower_32_bits(priv->suspend_time);
-	int ret;
-
-	ret = nouveau_timer_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_debug(priv, "time low        : 0x%08x\n", lo);
-	nv_debug(priv, "time high       : 0x%08x\n", hi);
-
-	/* restore the time before suspend */
-	nv_wr32(priv, NV04_PTIMER_TIME_1, hi);
-	nv_wr32(priv, NV04_PTIMER_TIME_0, lo);
-	return 0;
-}
-
-struct nouveau_oclass
-gk20a_timer_oclass = {
-	.handle = NV_SUBDEV(TIMER, 0xff),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_timer_ctor,
-		.dtor = nv04_timer_dtor,
-		.init = gk20a_timer_init,
-		.fini = nv04_timer_fini,
-	}
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c
deleted file mode 100644
index 240ed0b983a9..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nv04.h"
-
-static u64
-nv04_timer_read(struct nouveau_timer *ptimer)
-{
-	struct nv04_timer_priv *priv = (void *)ptimer;
-	u32 hi, lo;
-
-	do {
-		hi = nv_rd32(priv, NV04_PTIMER_TIME_1);
-		lo = nv_rd32(priv, NV04_PTIMER_TIME_0);
-	} while (hi != nv_rd32(priv, NV04_PTIMER_TIME_1));
-
-	return ((u64)hi << 32 | lo);
-}
-
-static void
-nv04_timer_alarm_trigger(struct nouveau_timer *ptimer)
-{
-	struct nv04_timer_priv *priv = (void *)ptimer;
-	struct nouveau_alarm *alarm, *atemp;
-	unsigned long flags;
-	LIST_HEAD(exec);
-
-	/* move any due alarms off the pending list */
-	spin_lock_irqsave(&priv->lock, flags);
-	list_for_each_entry_safe(alarm, atemp, &priv->alarms, head) {
-		if (alarm->timestamp <= ptimer->read(ptimer))
-			list_move_tail(&alarm->head, &exec);
-	}
-
-	/* reschedule interrupt for next alarm time */
-	if (!list_empty(&priv->alarms)) {
-		alarm = list_first_entry(&priv->alarms, typeof(*alarm), head);
-		nv_wr32(priv, NV04_PTIMER_ALARM_0, alarm->timestamp);
-		nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000001);
-	} else {
-		nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000);
-	}
-	spin_unlock_irqrestore(&priv->lock, flags);
-
-	/* execute any pending alarm handlers */
-	list_for_each_entry_safe(alarm, atemp, &exec, head) {
-		list_del_init(&alarm->head);
-		alarm->func(alarm);
-	}
-}
-
-static void
-nv04_timer_alarm(struct nouveau_timer *ptimer, u64 time,
-		 struct nouveau_alarm *alarm)
-{
-	struct nv04_timer_priv *priv = (void *)ptimer;
-	struct nouveau_alarm *list;
-	unsigned long flags;
-
-	alarm->timestamp = ptimer->read(ptimer) + time;
-
-	/* append new alarm to list, in soonest-alarm-first order */
-	spin_lock_irqsave(&priv->lock, flags);
-	if (!time) {
-		if (!list_empty(&alarm->head))
-			list_del(&alarm->head);
-	} else {
-		list_for_each_entry(list, &priv->alarms, head) {
-			if (list->timestamp > alarm->timestamp)
-				break;
-		}
-		list_add_tail(&alarm->head, &list->head);
-	}
-	spin_unlock_irqrestore(&priv->lock, flags);
-
-	/* process pending alarms */
-	nv04_timer_alarm_trigger(ptimer);
-}
-
-static void
-nv04_timer_alarm_cancel(struct nouveau_timer *ptimer,
-			struct nouveau_alarm *alarm)
-{
-	struct nv04_timer_priv *priv = (void *)ptimer;
-	unsigned long flags;
-	spin_lock_irqsave(&priv->lock, flags);
-	list_del_init(&alarm->head);
-	spin_unlock_irqrestore(&priv->lock, flags);
-}
-
-static void
-nv04_timer_intr(struct nouveau_subdev *subdev)
-{
-	struct nv04_timer_priv *priv = (void *)subdev;
-	u32 stat = nv_rd32(priv, NV04_PTIMER_INTR_0);
-
-	if (stat & 0x00000001) {
-		nv04_timer_alarm_trigger(&priv->base);
-		nv_wr32(priv, NV04_PTIMER_INTR_0, 0x00000001);
-		stat &= ~0x00000001;
-	}
-
-	if (stat) {
-		nv_error(priv, "unknown stat 0x%08x\n", stat);
-		nv_wr32(priv, NV04_PTIMER_INTR_0, stat);
-	}
-}
-
-int
-nv04_timer_fini(struct nouveau_object *object, bool suspend)
-{
-	struct nv04_timer_priv *priv = (void *)object;
-	if (suspend)
-		priv->suspend_time = nv04_timer_read(&priv->base);
-	nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000);
-	return nouveau_timer_fini(&priv->base, suspend);
-}
-
-static int
-nv04_timer_init(struct nouveau_object *object)
-{
-	struct nouveau_device *device = nv_device(object);
-	struct nv04_timer_priv *priv = (void *)object;
-	u32 m = 1, f, n, d, lo, hi;
-	int ret;
-
-	ret = nouveau_timer_init(&priv->base);
-	if (ret)
-		return ret;
-
-	/* aim for 31.25MHz, which gives us nanosecond timestamps */
-	d = 1000000 / 32;
-
-	/* determine base clock for timer source */
-#if 0 /*XXX*/
-	if (device->chipset < 0x40) {
-		n = nouveau_hw_get_clock(device, PLL_CORE);
-	} else
-#endif
-	if (device->chipset <= 0x40) {
-		/*XXX: figure this out */
-		f = -1;
-		n = 0;
-	} else {
-		f = device->crystal;
-		n = f;
-		while (n < (d * 2)) {
-			n += (n / m);
-			m++;
-		}
-
-		nv_wr32(priv, 0x009220, m - 1);
-	}
-
-	if (!n) {
-		nv_warn(priv, "unknown input clock freq\n");
-		if (!nv_rd32(priv, NV04_PTIMER_NUMERATOR) ||
-		    !nv_rd32(priv, NV04_PTIMER_DENOMINATOR)) {
-			nv_wr32(priv, NV04_PTIMER_NUMERATOR, 1);
-			nv_wr32(priv, NV04_PTIMER_DENOMINATOR, 1);
-		}
-		return 0;
-	}
-
-	/* reduce ratio to acceptable values */
-	while (((n % 5) == 0) && ((d % 5) == 0)) {
-		n /= 5;
-		d /= 5;
-	}
-
-	while (((n % 2) == 0) && ((d % 2) == 0)) {
-		n /= 2;
-		d /= 2;
-	}
-
-	while (n > 0xffff || d > 0xffff) {
-		n >>= 1;
-		d >>= 1;
-	}
-
-	/* restore the time before suspend */
-	lo = priv->suspend_time;
-	hi = (priv->suspend_time >> 32);
-
-	nv_debug(priv, "input frequency : %dHz\n", f);
-	nv_debug(priv, "input multiplier: %d\n", m);
-	nv_debug(priv, "numerator       : 0x%08x\n", n);
-	nv_debug(priv, "denominator     : 0x%08x\n", d);
-	nv_debug(priv, "timer frequency : %dHz\n", (f * m) * d / n);
-	nv_debug(priv, "time low        : 0x%08x\n", lo);
-	nv_debug(priv, "time high       : 0x%08x\n", hi);
-
-	nv_wr32(priv, NV04_PTIMER_NUMERATOR, n);
-	nv_wr32(priv, NV04_PTIMER_DENOMINATOR, d);
-	nv_wr32(priv, NV04_PTIMER_INTR_0, 0xffffffff);
-	nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000);
-	nv_wr32(priv, NV04_PTIMER_TIME_1, hi);
-	nv_wr32(priv, NV04_PTIMER_TIME_0, lo);
-
-	return 0;
-}
-
-void
-nv04_timer_dtor(struct nouveau_object *object)
-{
-	struct nv04_timer_priv *priv = (void *)object;
-	return nouveau_timer_destroy(&priv->base);
-}
-
-int
-nv04_timer_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nv04_timer_priv *priv;
-	int ret;
-
-	ret = nouveau_timer_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.base.intr = nv04_timer_intr;
-	priv->base.read = nv04_timer_read;
-	priv->base.alarm = nv04_timer_alarm;
-	priv->base.alarm_cancel = nv04_timer_alarm_cancel;
-	priv->suspend_time = 0;
-
-	INIT_LIST_HEAD(&priv->alarms);
-	spin_lock_init(&priv->lock);
-	return 0;
-}
-
-struct nouveau_oclass
-nv04_timer_oclass = {
-	.handle = NV_SUBDEV(TIMER, 0x04),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_timer_ctor,
-		.dtor = nv04_timer_dtor,
-		.init = nv04_timer_init,
-		.fini = nv04_timer_fini,
-	}
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.h
deleted file mode 100644
index 4bc152697c37..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef __NVKM_TIMER_NV04_H__
-#define __NVKM_TIMER_NV04_H__
-
-#include "priv.h"
-
-#define NV04_PTIMER_INTR_0      0x009100
-#define NV04_PTIMER_INTR_EN_0   0x009140
-#define NV04_PTIMER_NUMERATOR   0x009200
-#define NV04_PTIMER_DENOMINATOR 0x009210
-#define NV04_PTIMER_TIME_0      0x009400
-#define NV04_PTIMER_TIME_1      0x009410
-#define NV04_PTIMER_ALARM_0     0x009420
-
-struct nv04_timer_priv {
-	struct nouveau_timer base;
-	struct list_head alarms;
-	spinlock_t lock;
-	u64 suspend_time;
-};
-
-int  nv04_timer_ctor(struct nouveau_object *, struct nouveau_object *,
-		     struct nouveau_oclass *, void *, u32,
-		     struct nouveau_object **);
-void nv04_timer_dtor(struct nouveau_object *);
-int  nv04_timer_fini(struct nouveau_object *, bool);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/priv.h b/drivers/gpu/drm/nouveau/core/subdev/timer/priv.h
deleted file mode 100644
index 799dae3f2300..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/timer/priv.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __NVKM_TIMER_PRIV_H__
-#define __NVKM_TIMER_PRIV_H__
-
-#include <subdev/timer.h>
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c
deleted file mode 100644
index f75a683bd47a..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c
+++ /dev/null
@@ -1,483 +0,0 @@
-/*
- * Copyright 2010 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/gpuobj.h>
-#include <core/mm.h>
-
-#include <subdev/fb.h>
-#include <subdev/vm.h>
-
-void
-nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node)
-{
-	struct nouveau_vm *vm = vma->vm;
-	struct nouveau_vmmgr *vmm = vm->vmm;
-	struct nouveau_mm_node *r;
-	int big = vma->node->type != vmm->spg_shift;
-	u32 offset = vma->node->offset + (delta >> 12);
-	u32 bits = vma->node->type - 12;
-	u32 pde  = (offset >> vmm->pgt_bits) - vm->fpde;
-	u32 pte  = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits;
-	u32 max  = 1 << (vmm->pgt_bits - bits);
-	u32 end, len;
-
-	delta = 0;
-	list_for_each_entry(r, &node->regions, rl_entry) {
-		u64 phys = (u64)r->offset << 12;
-		u32 num  = r->length >> bits;
-
-		while (num) {
-			struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big];
-
-			end = (pte + num);
-			if (unlikely(end >= max))
-				end = max;
-			len = end - pte;
-
-			vmm->map(vma, pgt, node, pte, len, phys, delta);
-
-			num -= len;
-			pte += len;
-			if (unlikely(end >= max)) {
-				phys += len << (bits + 12);
-				pde++;
-				pte = 0;
-			}
-
-			delta += (u64)len << vma->node->type;
-		}
-	}
-
-	vmm->flush(vm);
-}
-
-static void
-nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length,
-			struct nouveau_mem *mem)
-{
-	struct nouveau_vm *vm = vma->vm;
-	struct nouveau_vmmgr *vmm = vm->vmm;
-	int big = vma->node->type != vmm->spg_shift;
-	u32 offset = vma->node->offset + (delta >> 12);
-	u32 bits = vma->node->type - 12;
-	u32 num  = length >> vma->node->type;
-	u32 pde  = (offset >> vmm->pgt_bits) - vm->fpde;
-	u32 pte  = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits;
-	u32 max  = 1 << (vmm->pgt_bits - bits);
-	unsigned m, sglen;
-	u32 end, len;
-	int i;
-	struct scatterlist *sg;
-
-	for_each_sg(mem->sg->sgl, sg, mem->sg->nents, i) {
-		struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big];
-		sglen = sg_dma_len(sg) >> PAGE_SHIFT;
-
-		end = pte + sglen;
-		if (unlikely(end >= max))
-			end = max;
-		len = end - pte;
-
-		for (m = 0; m < len; m++) {
-			dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
-
-			vmm->map_sg(vma, pgt, mem, pte, 1, &addr);
-			num--;
-			pte++;
-
-			if (num == 0)
-				goto finish;
-		}
-		if (unlikely(end >= max)) {
-			pde++;
-			pte = 0;
-		}
-		if (m < sglen) {
-			for (; m < sglen; m++) {
-				dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
-
-				vmm->map_sg(vma, pgt, mem, pte, 1, &addr);
-				num--;
-				pte++;
-				if (num == 0)
-					goto finish;
-			}
-		}
-
-	}
-finish:
-	vmm->flush(vm);
-}
-
-static void
-nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length,
-		  struct nouveau_mem *mem)
-{
-	struct nouveau_vm *vm = vma->vm;
-	struct nouveau_vmmgr *vmm = vm->vmm;
-	dma_addr_t *list = mem->pages;
-	int big = vma->node->type != vmm->spg_shift;
-	u32 offset = vma->node->offset + (delta >> 12);
-	u32 bits = vma->node->type - 12;
-	u32 num  = length >> vma->node->type;
-	u32 pde  = (offset >> vmm->pgt_bits) - vm->fpde;
-	u32 pte  = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits;
-	u32 max  = 1 << (vmm->pgt_bits - bits);
-	u32 end, len;
-
-	while (num) {
-		struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big];
-
-		end = (pte + num);
-		if (unlikely(end >= max))
-			end = max;
-		len = end - pte;
-
-		vmm->map_sg(vma, pgt, mem, pte, len, list);
-
-		num  -= len;
-		pte  += len;
-		list += len;
-		if (unlikely(end >= max)) {
-			pde++;
-			pte = 0;
-		}
-	}
-
-	vmm->flush(vm);
-}
-
-void
-nouveau_vm_map(struct nouveau_vma *vma, struct nouveau_mem *node)
-{
-	if (node->sg)
-		nouveau_vm_map_sg_table(vma, 0, node->size << 12, node);
-	else
-	if (node->pages)
-		nouveau_vm_map_sg(vma, 0, node->size << 12, node);
-	else
-		nouveau_vm_map_at(vma, 0, node);
-}
-
-void
-nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length)
-{
-	struct nouveau_vm *vm = vma->vm;
-	struct nouveau_vmmgr *vmm = vm->vmm;
-	int big = vma->node->type != vmm->spg_shift;
-	u32 offset = vma->node->offset + (delta >> 12);
-	u32 bits = vma->node->type - 12;
-	u32 num  = length >> vma->node->type;
-	u32 pde  = (offset >> vmm->pgt_bits) - vm->fpde;
-	u32 pte  = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits;
-	u32 max  = 1 << (vmm->pgt_bits - bits);
-	u32 end, len;
-
-	while (num) {
-		struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big];
-
-		end = (pte + num);
-		if (unlikely(end >= max))
-			end = max;
-		len = end - pte;
-
-		vmm->unmap(pgt, pte, len);
-
-		num -= len;
-		pte += len;
-		if (unlikely(end >= max)) {
-			pde++;
-			pte = 0;
-		}
-	}
-
-	vmm->flush(vm);
-}
-
-void
-nouveau_vm_unmap(struct nouveau_vma *vma)
-{
-	nouveau_vm_unmap_at(vma, 0, (u64)vma->node->length << 12);
-}
-
-static void
-nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde)
-{
-	struct nouveau_vmmgr *vmm = vm->vmm;
-	struct nouveau_vm_pgd *vpgd;
-	struct nouveau_vm_pgt *vpgt;
-	struct nouveau_gpuobj *pgt;
-	u32 pde;
-
-	for (pde = fpde; pde <= lpde; pde++) {
-		vpgt = &vm->pgt[pde - vm->fpde];
-		if (--vpgt->refcount[big])
-			continue;
-
-		pgt = vpgt->obj[big];
-		vpgt->obj[big] = NULL;
-
-		list_for_each_entry(vpgd, &vm->pgd_list, head) {
-			vmm->map_pgt(vpgd->obj, pde, vpgt->obj);
-		}
-
-		mutex_unlock(&nv_subdev(vmm)->mutex);
-		nouveau_gpuobj_ref(NULL, &pgt);
-		mutex_lock(&nv_subdev(vmm)->mutex);
-	}
-}
-
-static int
-nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type)
-{
-	struct nouveau_vmmgr *vmm = vm->vmm;
-	struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde];
-	struct nouveau_vm_pgd *vpgd;
-	struct nouveau_gpuobj *pgt;
-	int big = (type != vmm->spg_shift);
-	u32 pgt_size;
-	int ret;
-
-	pgt_size  = (1 << (vmm->pgt_bits + 12)) >> type;
-	pgt_size *= 8;
-
-	mutex_unlock(&nv_subdev(vmm)->mutex);
-	ret = nouveau_gpuobj_new(nv_object(vm->vmm), NULL, pgt_size, 0x1000,
-				 NVOBJ_FLAG_ZERO_ALLOC, &pgt);
-	mutex_lock(&nv_subdev(vmm)->mutex);
-	if (unlikely(ret))
-		return ret;
-
-	/* someone beat us to filling the PDE while we didn't have the lock */
-	if (unlikely(vpgt->refcount[big]++)) {
-		mutex_unlock(&nv_subdev(vmm)->mutex);
-		nouveau_gpuobj_ref(NULL, &pgt);
-		mutex_lock(&nv_subdev(vmm)->mutex);
-		return 0;
-	}
-
-	vpgt->obj[big] = pgt;
-	list_for_each_entry(vpgd, &vm->pgd_list, head) {
-		vmm->map_pgt(vpgd->obj, pde, vpgt->obj);
-	}
-
-	return 0;
-}
-
-int
-nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift,
-	       u32 access, struct nouveau_vma *vma)
-{
-	struct nouveau_vmmgr *vmm = vm->vmm;
-	u32 align = (1 << page_shift) >> 12;
-	u32 msize = size >> 12;
-	u32 fpde, lpde, pde;
-	int ret;
-
-	mutex_lock(&nv_subdev(vmm)->mutex);
-	ret = nouveau_mm_head(&vm->mm, 0, page_shift, msize, msize, align,
-			     &vma->node);
-	if (unlikely(ret != 0)) {
-		mutex_unlock(&nv_subdev(vmm)->mutex);
-		return ret;
-	}
-
-	fpde = (vma->node->offset >> vmm->pgt_bits);
-	lpde = (vma->node->offset + vma->node->length - 1) >> vmm->pgt_bits;
-
-	for (pde = fpde; pde <= lpde; pde++) {
-		struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde];
-		int big = (vma->node->type != vmm->spg_shift);
-
-		if (likely(vpgt->refcount[big])) {
-			vpgt->refcount[big]++;
-			continue;
-		}
-
-		ret = nouveau_vm_map_pgt(vm, pde, vma->node->type);
-		if (ret) {
-			if (pde != fpde)
-				nouveau_vm_unmap_pgt(vm, big, fpde, pde - 1);
-			nouveau_mm_free(&vm->mm, &vma->node);
-			mutex_unlock(&nv_subdev(vmm)->mutex);
-			return ret;
-		}
-	}
-	mutex_unlock(&nv_subdev(vmm)->mutex);
-
-	vma->vm = NULL;
-	nouveau_vm_ref(vm, &vma->vm, NULL);
-	vma->offset = (u64)vma->node->offset << 12;
-	vma->access = access;
-	return 0;
-}
-
-void
-nouveau_vm_put(struct nouveau_vma *vma)
-{
-	struct nouveau_vm *vm = vma->vm;
-	struct nouveau_vmmgr *vmm = vm->vmm;
-	u32 fpde, lpde;
-
-	if (unlikely(vma->node == NULL))
-		return;
-	fpde = (vma->node->offset >> vmm->pgt_bits);
-	lpde = (vma->node->offset + vma->node->length - 1) >> vmm->pgt_bits;
-
-	mutex_lock(&nv_subdev(vmm)->mutex);
-	nouveau_vm_unmap_pgt(vm, vma->node->type != vmm->spg_shift, fpde, lpde);
-	nouveau_mm_free(&vm->mm, &vma->node);
-	mutex_unlock(&nv_subdev(vmm)->mutex);
-
-	nouveau_vm_ref(NULL, &vma->vm, NULL);
-}
-
-int
-nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length,
-		  u64 mm_offset, u32 block, struct nouveau_vm **pvm)
-{
-	struct nouveau_vm *vm;
-	u64 mm_length = (offset + length) - mm_offset;
-	int ret;
-
-	vm = kzalloc(sizeof(*vm), GFP_KERNEL);
-	if (!vm)
-		return -ENOMEM;
-
-	INIT_LIST_HEAD(&vm->pgd_list);
-	vm->vmm = vmm;
-	kref_init(&vm->refcount);
-	vm->fpde = offset >> (vmm->pgt_bits + 12);
-	vm->lpde = (offset + length - 1) >> (vmm->pgt_bits + 12);
-
-	vm->pgt  = vzalloc((vm->lpde - vm->fpde + 1) * sizeof(*vm->pgt));
-	if (!vm->pgt) {
-		kfree(vm);
-		return -ENOMEM;
-	}
-
-	ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12,
-			      block >> 12);
-	if (ret) {
-		vfree(vm->pgt);
-		kfree(vm);
-		return ret;
-	}
-
-	*pvm = vm;
-
-	return 0;
-}
-
-int
-nouveau_vm_new(struct nouveau_device *device, u64 offset, u64 length,
-	       u64 mm_offset, struct nouveau_vm **pvm)
-{
-	struct nouveau_vmmgr *vmm = nouveau_vmmgr(device);
-	return vmm->create(vmm, offset, length, mm_offset, pvm);
-}
-
-static int
-nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd)
-{
-	struct nouveau_vmmgr *vmm = vm->vmm;
-	struct nouveau_vm_pgd *vpgd;
-	int i;
-
-	if (!pgd)
-		return 0;
-
-	vpgd = kzalloc(sizeof(*vpgd), GFP_KERNEL);
-	if (!vpgd)
-		return -ENOMEM;
-
-	nouveau_gpuobj_ref(pgd, &vpgd->obj);
-
-	mutex_lock(&nv_subdev(vmm)->mutex);
-	for (i = vm->fpde; i <= vm->lpde; i++)
-		vmm->map_pgt(pgd, i, vm->pgt[i - vm->fpde].obj);
-	list_add(&vpgd->head, &vm->pgd_list);
-	mutex_unlock(&nv_subdev(vmm)->mutex);
-	return 0;
-}
-
-static void
-nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd)
-{
-	struct nouveau_vmmgr *vmm = vm->vmm;
-	struct nouveau_vm_pgd *vpgd, *tmp;
-	struct nouveau_gpuobj *pgd = NULL;
-
-	if (!mpgd)
-		return;
-
-	mutex_lock(&nv_subdev(vmm)->mutex);
-	list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) {
-		if (vpgd->obj == mpgd) {
-			pgd = vpgd->obj;
-			list_del(&vpgd->head);
-			kfree(vpgd);
-			break;
-		}
-	}
-	mutex_unlock(&nv_subdev(vmm)->mutex);
-
-	nouveau_gpuobj_ref(NULL, &pgd);
-}
-
-static void
-nouveau_vm_del(struct kref *kref)
-{
-	struct nouveau_vm *vm = container_of(kref, typeof(*vm), refcount);
-	struct nouveau_vm_pgd *vpgd, *tmp;
-
-	list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) {
-		nouveau_vm_unlink(vm, vpgd->obj);
-	}
-
-	nouveau_mm_fini(&vm->mm);
-	vfree(vm->pgt);
-	kfree(vm);
-}
-
-int
-nouveau_vm_ref(struct nouveau_vm *ref, struct nouveau_vm **ptr,
-	       struct nouveau_gpuobj *pgd)
-{
-	if (ref) {
-		int ret = nouveau_vm_link(ref, pgd);
-		if (ret)
-			return ret;
-
-		kref_get(&ref->refcount);
-	}
-
-	if (*ptr) {
-		nouveau_vm_unlink(*ptr, pgd);
-		kref_put(&(*ptr)->refcount, nouveau_vm_del);
-	}
-
-	*ptr = ref;
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c
deleted file mode 100644
index ed45437167f2..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/gpuobj.h>
-
-#include "nv04.h"
-
-#define NV04_PDMA_SIZE (128 * 1024 * 1024)
-#define NV04_PDMA_PAGE (  4 * 1024)
-
-/*******************************************************************************
- * VM map/unmap callbacks
- ******************************************************************************/
-
-static void
-nv04_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
-	       struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
-{
-	pte = 0x00008 + (pte * 4);
-	while (cnt) {
-		u32 page = PAGE_SIZE / NV04_PDMA_PAGE;
-		u32 phys = (u32)*list++;
-		while (cnt && page--) {
-			nv_wo32(pgt, pte, phys | 3);
-			phys += NV04_PDMA_PAGE;
-			pte += 4;
-			cnt -= 1;
-		}
-	}
-}
-
-static void
-nv04_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
-{
-	pte = 0x00008 + (pte * 4);
-	while (cnt--) {
-		nv_wo32(pgt, pte, 0x00000000);
-		pte += 4;
-	}
-}
-
-static void
-nv04_vm_flush(struct nouveau_vm *vm)
-{
-}
-
-/*******************************************************************************
- * VM object
- ******************************************************************************/
-
-int
-nv04_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, u64 mmstart,
-	       struct nouveau_vm **pvm)
-{
-	return -EINVAL;
-}
-
-/*******************************************************************************
- * VMMGR subdev
- ******************************************************************************/
-
-static int
-nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nv04_vmmgr_priv *priv;
-	struct nouveau_gpuobj *dma;
-	int ret;
-
-	ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIGART",
-				   "pcigart", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.create = nv04_vm_create;
-	priv->base.limit = NV04_PDMA_SIZE;
-	priv->base.dma_bits = 32;
-	priv->base.pgt_bits = 32 - 12;
-	priv->base.spg_shift = 12;
-	priv->base.lpg_shift = 12;
-	priv->base.map_sg = nv04_vm_map_sg;
-	priv->base.unmap = nv04_vm_unmap;
-	priv->base.flush = nv04_vm_flush;
-
-	ret = nouveau_vm_create(&priv->base, 0, NV04_PDMA_SIZE, 0, 4096,
-				&priv->vm);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL,
-				 (NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 +
-				 8, 16, NVOBJ_FLAG_ZERO_ALLOC,
-				 &priv->vm->pgt[0].obj[0]);
-	dma = priv->vm->pgt[0].obj[0];
-	priv->vm->pgt[0].refcount[0] = 1;
-	if (ret)
-		return ret;
-
-	nv_wo32(dma, 0x00000, 0x0002103d); /* PCI, RW, PT, !LN */
-	nv_wo32(dma, 0x00004, NV04_PDMA_SIZE - 1);
-	return 0;
-}
-
-void
-nv04_vmmgr_dtor(struct nouveau_object *object)
-{
-	struct nv04_vmmgr_priv *priv = (void *)object;
-	if (priv->vm) {
-		nouveau_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]);
-		nouveau_vm_ref(NULL, &priv->vm, NULL);
-	}
-	if (priv->nullp) {
-		pci_free_consistent(nv_device(priv)->pdev, 16 * 1024,
-				    priv->nullp, priv->null);
-	}
-	nouveau_vmmgr_destroy(&priv->base);
-}
-
-struct nouveau_oclass
-nv04_vmmgr_oclass = {
-	.handle = NV_SUBDEV(VM, 0x04),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_vmmgr_ctor,
-		.dtor = nv04_vmmgr_dtor,
-		.init = _nouveau_vmmgr_init,
-		.fini = _nouveau_vmmgr_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h
deleted file mode 100644
index ec42d4bc86a6..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef __NV04_VMMGR_PRIV__
-#define __NV04_VMMGR_PRIV__
-
-#include <subdev/vm.h>
-
-struct nv04_vmmgr_priv {
-	struct nouveau_vmmgr base;
-	struct nouveau_vm *vm;
-	dma_addr_t null;
-	void *nullp;
-};
-
-static inline struct nv04_vmmgr_priv *
-nv04_vmmgr(void *obj)
-{
-	return (void *)nouveau_vmmgr(obj);
-}
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c
deleted file mode 100644
index 064c76262876..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/gpuobj.h>
-#include <core/option.h>
-
-#include <subdev/timer.h>
-#include <subdev/vm.h>
-
-#include "nv04.h"
-
-#define NV41_GART_SIZE (512 * 1024 * 1024)
-#define NV41_GART_PAGE (  4 * 1024)
-
-/*******************************************************************************
- * VM map/unmap callbacks
- ******************************************************************************/
-
-static void
-nv41_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
-	       struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
-{
-	pte = pte * 4;
-	while (cnt) {
-		u32 page = PAGE_SIZE / NV41_GART_PAGE;
-		u64 phys = (u64)*list++;
-		while (cnt && page--) {
-			nv_wo32(pgt, pte, (phys >> 7) | 1);
-			phys += NV41_GART_PAGE;
-			pte += 4;
-			cnt -= 1;
-		}
-	}
-}
-
-static void
-nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
-{
-	pte = pte * 4;
-	while (cnt--) {
-		nv_wo32(pgt, pte, 0x00000000);
-		pte += 4;
-	}
-}
-
-static void
-nv41_vm_flush(struct nouveau_vm *vm)
-{
-	struct nv04_vmmgr_priv *priv = (void *)vm->vmm;
-
-	mutex_lock(&nv_subdev(priv)->mutex);
-	nv_wr32(priv, 0x100810, 0x00000022);
-	if (!nv_wait(priv, 0x100810, 0x00000020, 0x00000020)) {
-		nv_warn(priv, "flush timeout, 0x%08x\n",
-			nv_rd32(priv, 0x100810));
-	}
-	nv_wr32(priv, 0x100810, 0x00000000);
-	mutex_unlock(&nv_subdev(priv)->mutex);
-}
-
-/*******************************************************************************
- * VMMGR subdev
- ******************************************************************************/
-
-static int
-nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nouveau_device *device = nv_device(parent);
-	struct nv04_vmmgr_priv *priv;
-	int ret;
-
-	if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
-	    !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) {
-		return nouveau_object_ctor(parent, engine, &nv04_vmmgr_oclass,
-					   data, size, pobject);
-	}
-
-	ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART",
-				   "pciegart", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.create = nv04_vm_create;
-	priv->base.limit = NV41_GART_SIZE;
-	priv->base.dma_bits = 39;
-	priv->base.pgt_bits = 32 - 12;
-	priv->base.spg_shift = 12;
-	priv->base.lpg_shift = 12;
-	priv->base.map_sg = nv41_vm_map_sg;
-	priv->base.unmap = nv41_vm_unmap;
-	priv->base.flush = nv41_vm_flush;
-
-	ret = nouveau_vm_create(&priv->base, 0, NV41_GART_SIZE, 0, 4096,
-				&priv->vm);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL,
-				(NV41_GART_SIZE / NV41_GART_PAGE) * 4,
-				 16, NVOBJ_FLAG_ZERO_ALLOC,
-				 &priv->vm->pgt[0].obj[0]);
-	priv->vm->pgt[0].refcount[0] = 1;
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-static int
-nv41_vmmgr_init(struct nouveau_object *object)
-{
-	struct nv04_vmmgr_priv *priv = (void *)object;
-	struct nouveau_gpuobj *dma = priv->vm->pgt[0].obj[0];
-	int ret;
-
-	ret = nouveau_vmmgr_init(&priv->base);
-	if (ret)
-		return ret;
-
-	nv_wr32(priv, 0x100800, dma->addr | 0x00000002);
-	nv_mask(priv, 0x10008c, 0x00000100, 0x00000100);
-	nv_wr32(priv, 0x100820, 0x00000000);
-	return 0;
-}
-
-struct nouveau_oclass
-nv41_vmmgr_oclass = {
-	.handle = NV_SUBDEV(VM, 0x41),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv41_vmmgr_ctor,
-		.dtor = nv04_vmmgr_dtor,
-		.init = nv41_vmmgr_init,
-		.fini = _nouveau_vmmgr_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c
deleted file mode 100644
index fae1f67d5948..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/gpuobj.h>
-#include <core/option.h>
-
-#include <subdev/timer.h>
-#include <subdev/vm.h>
-
-#include "nv04.h"
-
-#define NV44_GART_SIZE (512 * 1024 * 1024)
-#define NV44_GART_PAGE (  4 * 1024)
-
-/*******************************************************************************
- * VM map/unmap callbacks
- ******************************************************************************/
-
-static void
-nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null,
-	     dma_addr_t *list, u32 pte, u32 cnt)
-{
-	u32 base = (pte << 2) & ~0x0000000f;
-	u32 tmp[4];
-
-	tmp[0] = nv_ro32(pgt, base + 0x0);
-	tmp[1] = nv_ro32(pgt, base + 0x4);
-	tmp[2] = nv_ro32(pgt, base + 0x8);
-	tmp[3] = nv_ro32(pgt, base + 0xc);
-
-	while (cnt--) {
-		u32 addr = list ? (*list++ >> 12) : (null >> 12);
-		switch (pte++ & 0x3) {
-		case 0:
-			tmp[0] &= ~0x07ffffff;
-			tmp[0] |= addr;
-			break;
-		case 1:
-			tmp[0] &= ~0xf8000000;
-			tmp[0] |= addr << 27;
-			tmp[1] &= ~0x003fffff;
-			tmp[1] |= addr >> 5;
-			break;
-		case 2:
-			tmp[1] &= ~0xffc00000;
-			tmp[1] |= addr << 22;
-			tmp[2] &= ~0x0001ffff;
-			tmp[2] |= addr >> 10;
-			break;
-		case 3:
-			tmp[2] &= ~0xfffe0000;
-			tmp[2] |= addr << 17;
-			tmp[3] &= ~0x00000fff;
-			tmp[3] |= addr >> 15;
-			break;
-		}
-	}
-
-	nv_wo32(pgt, base + 0x0, tmp[0]);
-	nv_wo32(pgt, base + 0x4, tmp[1]);
-	nv_wo32(pgt, base + 0x8, tmp[2]);
-	nv_wo32(pgt, base + 0xc, tmp[3] | 0x40000000);
-}
-
-static void
-nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
-	       struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
-{
-	struct nv04_vmmgr_priv *priv = (void *)vma->vm->vmm;
-	u32 tmp[4];
-	int i;
-
-	if (pte & 3) {
-		u32  max = 4 - (pte & 3);
-		u32 part = (cnt > max) ? max : cnt;
-		nv44_vm_fill(pgt, priv->null, list, pte, part);
-		pte  += part;
-		list += part;
-		cnt  -= part;
-	}
-
-	while (cnt >= 4) {
-		for (i = 0; i < 4; i++)
-			tmp[i] = *list++ >> 12;
-		nv_wo32(pgt, pte++ * 4, tmp[0] >>  0 | tmp[1] << 27);
-		nv_wo32(pgt, pte++ * 4, tmp[1] >>  5 | tmp[2] << 22);
-		nv_wo32(pgt, pte++ * 4, tmp[2] >> 10 | tmp[3] << 17);
-		nv_wo32(pgt, pte++ * 4, tmp[3] >> 15 | 0x40000000);
-		cnt -= 4;
-	}
-
-	if (cnt)
-		nv44_vm_fill(pgt, priv->null, list, pte, cnt);
-}
-
-static void
-nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
-{
-	struct nv04_vmmgr_priv *priv = (void *)nouveau_vmmgr(pgt);
-
-	if (pte & 3) {
-		u32  max = 4 - (pte & 3);
-		u32 part = (cnt > max) ? max : cnt;
-		nv44_vm_fill(pgt, priv->null, NULL, pte, part);
-		pte  += part;
-		cnt  -= part;
-	}
-
-	while (cnt >= 4) {
-		nv_wo32(pgt, pte++ * 4, 0x00000000);
-		nv_wo32(pgt, pte++ * 4, 0x00000000);
-		nv_wo32(pgt, pte++ * 4, 0x00000000);
-		nv_wo32(pgt, pte++ * 4, 0x00000000);
-		cnt -= 4;
-	}
-
-	if (cnt)
-		nv44_vm_fill(pgt, priv->null, NULL, pte, cnt);
-}
-
-static void
-nv44_vm_flush(struct nouveau_vm *vm)
-{
-	struct nv04_vmmgr_priv *priv = (void *)vm->vmm;
-	nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE);
-	nv_wr32(priv, 0x100808, 0x00000020);
-	if (!nv_wait(priv, 0x100808, 0x00000001, 0x00000001))
-		nv_error(priv, "timeout: 0x%08x\n", nv_rd32(priv, 0x100808));
-	nv_wr32(priv, 0x100808, 0x00000000);
-}
-
-/*******************************************************************************
- * VMMGR subdev
- ******************************************************************************/
-
-static int
-nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nouveau_device *device = nv_device(parent);
-	struct nv04_vmmgr_priv *priv;
-	int ret;
-
-	if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
-	    !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) {
-		return nouveau_object_ctor(parent, engine, &nv04_vmmgr_oclass,
-					   data, size, pobject);
-	}
-
-	ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART",
-				   "pciegart", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.create = nv04_vm_create;
-	priv->base.limit = NV44_GART_SIZE;
-	priv->base.dma_bits = 39;
-	priv->base.pgt_bits = 32 - 12;
-	priv->base.spg_shift = 12;
-	priv->base.lpg_shift = 12;
-	priv->base.map_sg = nv44_vm_map_sg;
-	priv->base.unmap = nv44_vm_unmap;
-	priv->base.flush = nv44_vm_flush;
-
-	priv->nullp = pci_alloc_consistent(device->pdev, 16 * 1024, &priv->null);
-	if (!priv->nullp) {
-		nv_error(priv, "unable to allocate dummy pages\n");
-		return -ENOMEM;
-	}
-
-	ret = nouveau_vm_create(&priv->base, 0, NV44_GART_SIZE, 0, 4096,
-				&priv->vm);
-	if (ret)
-		return ret;
-
-	ret = nouveau_gpuobj_new(nv_object(priv), NULL,
-				(NV44_GART_SIZE / NV44_GART_PAGE) * 4,
-				 512 * 1024, NVOBJ_FLAG_ZERO_ALLOC,
-				 &priv->vm->pgt[0].obj[0]);
-	priv->vm->pgt[0].refcount[0] = 1;
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-static int
-nv44_vmmgr_init(struct nouveau_object *object)
-{
-	struct nv04_vmmgr_priv *priv = (void *)object;
-	struct nouveau_gpuobj *gart = priv->vm->pgt[0].obj[0];
-	u32 addr;
-	int ret;
-
-	ret = nouveau_vmmgr_init(&priv->base);
-	if (ret)
-		return ret;
-
-	/* calculate vram address of this PRAMIN block, object must be
-	 * allocated on 512KiB alignment, and not exceed a total size
-	 * of 512KiB for this to work correctly
-	 */
-	addr  = nv_rd32(priv, 0x10020c);
-	addr -= ((gart->addr >> 19) + 1) << 19;
-
-	nv_wr32(priv, 0x100850, 0x80000000);
-	nv_wr32(priv, 0x100818, priv->null);
-	nv_wr32(priv, 0x100804, NV44_GART_SIZE);
-	nv_wr32(priv, 0x100850, 0x00008000);
-	nv_mask(priv, 0x10008c, 0x00000200, 0x00000200);
-	nv_wr32(priv, 0x100820, 0x00000000);
-	nv_wr32(priv, 0x10082c, 0x00000001);
-	nv_wr32(priv, 0x100800, addr | 0x00000010);
-	return 0;
-}
-
-struct nouveau_oclass
-nv44_vmmgr_oclass = {
-	.handle = NV_SUBDEV(VM, 0x44),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv44_vmmgr_ctor,
-		.dtor = nv04_vmmgr_dtor,
-		.init = nv44_vmmgr_init,
-		.fini = _nouveau_vmmgr_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
deleted file mode 100644
index a4aa81a2173b..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * Copyright 2010 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/device.h>
-#include <core/gpuobj.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <subdev/bar.h>
-#include <subdev/vm.h>
-
-struct nv50_vmmgr_priv {
-	struct nouveau_vmmgr base;
-};
-
-static void
-nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
-		struct nouveau_gpuobj *pgt[2])
-{
-	u64 phys = 0xdeadcafe00000000ULL;
-	u32 coverage = 0;
-
-	if (pgt[0]) {
-		phys = 0x00000003 | pgt[0]->addr; /* present, 4KiB pages */
-		coverage = (pgt[0]->size >> 3) << 12;
-	} else
-	if (pgt[1]) {
-		phys = 0x00000001 | pgt[1]->addr; /* present */
-		coverage = (pgt[1]->size >> 3) << 16;
-	}
-
-	if (phys & 1) {
-		if (coverage <= 32 * 1024 * 1024)
-			phys |= 0x60;
-		else if (coverage <= 64 * 1024 * 1024)
-			phys |= 0x40;
-		else if (coverage <= 128 * 1024 * 1024)
-			phys |= 0x20;
-	}
-
-	nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys));
-	nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys));
-}
-
-static inline u64
-vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
-{
-	phys |= 1; /* present */
-	phys |= (u64)memtype << 40;
-	phys |= target << 4;
-	if (vma->access & NV_MEM_ACCESS_SYS)
-		phys |= (1 << 6);
-	if (!(vma->access & NV_MEM_ACCESS_WO))
-		phys |= (1 << 3);
-	return phys;
-}
-
-static void
-nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
-	    struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
-{
-	u32 comp = (mem->memtype & 0x180) >> 7;
-	u32 block, target;
-	int i;
-
-	/* IGPs don't have real VRAM, re-target to stolen system memory */
-	target = 0;
-	if (nouveau_fb(vma->vm->vmm)->ram->stolen) {
-		phys += nouveau_fb(vma->vm->vmm)->ram->stolen;
-		target = 3;
-	}
-
-	phys  = vm_addr(vma, phys, mem->memtype, target);
-	pte <<= 3;
-	cnt <<= 3;
-
-	while (cnt) {
-		u32 offset_h = upper_32_bits(phys);
-		u32 offset_l = lower_32_bits(phys);
-
-		for (i = 7; i >= 0; i--) {
-			block = 1 << (i + 3);
-			if (cnt >= block && !(pte & (block - 1)))
-				break;
-		}
-		offset_l |= (i << 7);
-
-		phys += block << (vma->node->type - 3);
-		cnt  -= block;
-		if (comp) {
-			u32 tag = mem->tag->offset + ((delta >> 16) * comp);
-			offset_h |= (tag << 17);
-			delta    += block << (vma->node->type - 3);
-		}
-
-		while (block) {
-			nv_wo32(pgt, pte + 0, offset_l);
-			nv_wo32(pgt, pte + 4, offset_h);
-			pte += 8;
-			block -= 8;
-		}
-	}
-}
-
-static void
-nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
-	       struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
-{
-	u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2;
-	pte <<= 3;
-	while (cnt--) {
-		u64 phys = vm_addr(vma, (u64)*list++, mem->memtype, target);
-		nv_wo32(pgt, pte + 0, lower_32_bits(phys));
-		nv_wo32(pgt, pte + 4, upper_32_bits(phys));
-		pte += 8;
-	}
-}
-
-static void
-nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
-{
-	pte <<= 3;
-	while (cnt--) {
-		nv_wo32(pgt, pte + 0, 0x00000000);
-		nv_wo32(pgt, pte + 4, 0x00000000);
-		pte += 8;
-	}
-}
-
-static void
-nv50_vm_flush(struct nouveau_vm *vm)
-{
-	struct nv50_vmmgr_priv *priv = (void *)vm->vmm;
-	struct nouveau_bar *bar = nouveau_bar(priv);
-	struct nouveau_engine *engine;
-	int i, vme;
-
-	bar->flush(bar);
-
-	mutex_lock(&nv_subdev(priv)->mutex);
-	for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
-		if (!atomic_read(&vm->engref[i]))
-			continue;
-
-		/* unfortunate hw bug workaround... */
-		engine = nouveau_engine(priv, i);
-		if (engine && engine->tlb_flush) {
-			engine->tlb_flush(engine);
-			continue;
-		}
-
-		switch (i) {
-		case NVDEV_ENGINE_GR   : vme = 0x00; break;
-		case NVDEV_ENGINE_VP   : vme = 0x01; break;
-		case NVDEV_SUBDEV_BAR  : vme = 0x06; break;
-		case NVDEV_ENGINE_PPP  :
-		case NVDEV_ENGINE_MPEG : vme = 0x08; break;
-		case NVDEV_ENGINE_BSP  : vme = 0x09; break;
-		case NVDEV_ENGINE_CRYPT: vme = 0x0a; break;
-		case NVDEV_ENGINE_COPY0: vme = 0x0d; break;
-		default:
-			continue;
-		}
-
-		nv_wr32(priv, 0x100c80, (vme << 16) | 1);
-		if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000))
-			nv_error(priv, "vm flush timeout: engine %d\n", vme);
-	}
-	mutex_unlock(&nv_subdev(priv)->mutex);
-}
-
-static int
-nv50_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length,
-	       u64 mm_offset, struct nouveau_vm **pvm)
-{
-	u32 block = (1 << (vmm->pgt_bits + 12));
-	if (block > length)
-		block = length;
-
-	return nouveau_vm_create(vmm, offset, length, mm_offset, block, pvm);
-}
-
-static int
-nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nv50_vmmgr_priv *priv;
-	int ret;
-
-	ret = nouveau_vmmgr_create(parent, engine, oclass, "VM", "vm", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.limit = 1ULL << 40;
-	priv->base.dma_bits = 40;
-	priv->base.pgt_bits  = 29 - 12;
-	priv->base.spg_shift = 12;
-	priv->base.lpg_shift = 16;
-	priv->base.create = nv50_vm_create;
-	priv->base.map_pgt = nv50_vm_map_pgt;
-	priv->base.map = nv50_vm_map;
-	priv->base.map_sg = nv50_vm_map_sg;
-	priv->base.unmap = nv50_vm_unmap;
-	priv->base.flush = nv50_vm_flush;
-	return 0;
-}
-
-struct nouveau_oclass
-nv50_vmmgr_oclass = {
-	.handle = NV_SUBDEV(VM, 0x50),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_vmmgr_ctor,
-		.dtor = _nouveau_vmmgr_dtor,
-		.init = _nouveau_vmmgr_init,
-		.fini = _nouveau_vmmgr_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
deleted file mode 100644
index 2d0988755530..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * Copyright 2010 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/device.h>
-#include <core/gpuobj.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <subdev/vm.h>
-#include <subdev/ltc.h>
-#include <subdev/bar.h>
-
-struct nvc0_vmmgr_priv {
-	struct nouveau_vmmgr base;
-};
-
-
-/* Map from compressed to corresponding uncompressed storage type.
- * The value 0xff represents an invalid storage type.
- */
-const u8 nvc0_pte_storage_type_map[256] =
-{
-	0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0xff, 0x01, /* 0x00 */
-	0x01, 0x01, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0x11, 0xff, 0xff, 0xff, 0xff, 0xff, 0x11, /* 0x10 */
-	0x11, 0x11, 0x11, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x26, 0x27, /* 0x20 */
-	0x28, 0x29, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x30 */
-	0xff, 0xff, 0x26, 0x27, 0x28, 0x29, 0x26, 0x27,
-	0x28, 0x29, 0xff, 0xff, 0xff, 0xff, 0x46, 0xff, /* 0x40 */
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0x46, 0x46, 0x46, 0x46, 0xff, 0xff, 0xff, /* 0x50 */
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x60 */
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x70 */
-	0xff, 0xff, 0xff, 0x7b, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7b, 0x7b, /* 0x80 */
-	0x7b, 0x7b, 0xff, 0x8b, 0x8c, 0x8d, 0x8e, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x90 */
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0x8b, 0x8c, 0x8d, 0x8e, 0xa7, /* 0xa0 */
-	0xa8, 0xa9, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0xb0 */
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa7,
-	0xa8, 0xa9, 0xaa, 0xc3, 0xff, 0xff, 0xff, 0xff, /* 0xc0 */
-	0xff, 0xff, 0xff, 0xff, 0xfe, 0xfe, 0xc3, 0xc3,
-	0xc3, 0xc3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0xd0 */
-	0xfe, 0xff, 0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe,
-	0xfe, 0xff, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xff, /* 0xe0 */
-	0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe, 0xfe, 0xff,
-	0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, /* 0xf0 */
-	0xfe, 0xfe, 0xfe, 0xfe, 0xff, 0xfd, 0xfe, 0xff
-};
-
-
-static void
-nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index,
-		struct nouveau_gpuobj *pgt[2])
-{
-	u32 pde[2] = { 0, 0 };
-
-	if (pgt[0])
-		pde[1] = 0x00000001 | (pgt[0]->addr >> 8);
-	if (pgt[1])
-		pde[0] = 0x00000001 | (pgt[1]->addr >> 8);
-
-	nv_wo32(pgd, (index * 8) + 0, pde[0]);
-	nv_wo32(pgd, (index * 8) + 4, pde[1]);
-}
-
-static inline u64
-nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
-{
-	phys >>= 8;
-
-	phys |= 0x00000001; /* present */
-	if (vma->access & NV_MEM_ACCESS_SYS)
-		phys |= 0x00000002;
-
-	phys |= ((u64)target  << 32);
-	phys |= ((u64)memtype << 36);
-
-	return phys;
-}
-
-static void
-nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
-	    struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
-{
-	u64 next = 1 << (vma->node->type - 8);
-
-	phys  = nvc0_vm_addr(vma, phys, mem->memtype, 0);
-	pte <<= 3;
-
-	if (mem->tag) {
-		struct nouveau_ltc *ltc =
-			nouveau_ltc(vma->vm->vmm->base.base.parent);
-		u32 tag = mem->tag->offset + (delta >> 17);
-		phys |= (u64)tag << (32 + 12);
-		next |= (u64)1   << (32 + 12);
-		ltc->tags_clear(ltc, tag, cnt);
-	}
-
-	while (cnt--) {
-		nv_wo32(pgt, pte + 0, lower_32_bits(phys));
-		nv_wo32(pgt, pte + 4, upper_32_bits(phys));
-		phys += next;
-		pte  += 8;
-	}
-}
-
-static void
-nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
-	       struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
-{
-	u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5;
-	/* compressed storage types are invalid for system memory */
-	u32 memtype = nvc0_pte_storage_type_map[mem->memtype & 0xff];
-
-	pte <<= 3;
-	while (cnt--) {
-		u64 phys = nvc0_vm_addr(vma, *list++, memtype, target);
-		nv_wo32(pgt, pte + 0, lower_32_bits(phys));
-		nv_wo32(pgt, pte + 4, upper_32_bits(phys));
-		pte += 8;
-	}
-}
-
-static void
-nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
-{
-	pte <<= 3;
-	while (cnt--) {
-		nv_wo32(pgt, pte + 0, 0x00000000);
-		nv_wo32(pgt, pte + 4, 0x00000000);
-		pte += 8;
-	}
-}
-
-static void
-nvc0_vm_flush(struct nouveau_vm *vm)
-{
-	struct nvc0_vmmgr_priv *priv = (void *)vm->vmm;
-	struct nouveau_bar *bar = nouveau_bar(priv);
-	struct nouveau_vm_pgd *vpgd;
-	u32 type;
-
-	bar->flush(bar);
-
-	type = 0x00000001; /* PAGE_ALL */
-	if (atomic_read(&vm->engref[NVDEV_SUBDEV_BAR]))
-		type |= 0x00000004; /* HUB_ONLY */
-
-	mutex_lock(&nv_subdev(priv)->mutex);
-	list_for_each_entry(vpgd, &vm->pgd_list, head) {
-		/* looks like maybe a "free flush slots" counter, the
-		 * faster you write to 0x100cbc to more it decreases
-		 */
-		if (!nv_wait_ne(priv, 0x100c80, 0x00ff0000, 0x00000000)) {
-			nv_error(priv, "vm timeout 0: 0x%08x %d\n",
-				 nv_rd32(priv, 0x100c80), type);
-		}
-
-		nv_wr32(priv, 0x100cb8, vpgd->obj->addr >> 8);
-		nv_wr32(priv, 0x100cbc, 0x80000000 | type);
-
-		/* wait for flush to be queued? */
-		if (!nv_wait(priv, 0x100c80, 0x00008000, 0x00008000)) {
-			nv_error(priv, "vm timeout 1: 0x%08x %d\n",
-				 nv_rd32(priv, 0x100c80), type);
-		}
-	}
-	mutex_unlock(&nv_subdev(priv)->mutex);
-}
-
-static int
-nvc0_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length,
-	       u64 mm_offset, struct nouveau_vm **pvm)
-{
-	return nouveau_vm_create(vmm, offset, length, mm_offset, 4096, pvm);
-}
-
-static int
-nvc0_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		struct nouveau_oclass *oclass, void *data, u32 size,
-		struct nouveau_object **pobject)
-{
-	struct nvc0_vmmgr_priv *priv;
-	int ret;
-
-	ret = nouveau_vmmgr_create(parent, engine, oclass, "VM", "vm", &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	priv->base.limit = 1ULL << 40;
-	priv->base.dma_bits = 40;
-	priv->base.pgt_bits  = 27 - 12;
-	priv->base.spg_shift = 12;
-	priv->base.lpg_shift = 17;
-	priv->base.create = nvc0_vm_create;
-	priv->base.map_pgt = nvc0_vm_map_pgt;
-	priv->base.map = nvc0_vm_map;
-	priv->base.map_sg = nvc0_vm_map_sg;
-	priv->base.unmap = nvc0_vm_unmap;
-	priv->base.flush = nvc0_vm_flush;
-	return 0;
-}
-
-struct nouveau_oclass
-nvc0_vmmgr_oclass = {
-	.handle = NV_SUBDEV(VM, 0xc0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_vmmgr_ctor,
-		.dtor = _nouveau_vmmgr_dtor,
-		.init = _nouveau_vmmgr_init,
-		.fini = _nouveau_vmmgr_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/volt/base.c b/drivers/gpu/drm/nouveau/core/subdev/volt/base.c
deleted file mode 100644
index 26ccd8df193f..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/volt/base.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/volt.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/vmap.h>
-#include <subdev/bios/volt.h>
-
-static int
-nouveau_volt_get(struct nouveau_volt *volt)
-{
-	if (volt->vid_get) {
-		int ret = volt->vid_get(volt), i;
-		if (ret >= 0) {
-			for (i = 0; i < volt->vid_nr; i++) {
-				if (volt->vid[i].vid == ret)
-					return volt->vid[i].uv;
-			}
-			ret = -EINVAL;
-		}
-		return ret;
-	}
-	return -ENODEV;
-}
-
-static int
-nouveau_volt_set(struct nouveau_volt *volt, u32 uv)
-{
-	if (volt->vid_set) {
-		int i, ret = -EINVAL;
-		for (i = 0; i < volt->vid_nr; i++) {
-			if (volt->vid[i].uv == uv) {
-				ret = volt->vid_set(volt, volt->vid[i].vid);
-				nv_debug(volt, "set %duv: %d\n", uv, ret);
-				break;
-			}
-		}
-		return ret;
-	}
-	return -ENODEV;
-}
-
-static int
-nouveau_volt_map(struct nouveau_volt *volt, u8 id)
-{
-	struct nouveau_bios *bios = nouveau_bios(volt);
-	struct nvbios_vmap_entry info;
-	u8  ver, len;
-	u16 vmap;
-
-	vmap = nvbios_vmap_entry_parse(bios, id, &ver, &len, &info);
-	if (vmap) {
-		if (info.link != 0xff) {
-			int ret = nouveau_volt_map(volt, info.link);
-			if (ret < 0)
-				return ret;
-			info.min += ret;
-		}
-		return info.min;
-	}
-
-	return id ? id * 10000 : -ENODEV;
-}
-
-static int
-nouveau_volt_set_id(struct nouveau_volt *volt, u8 id, int condition)
-{
-	int ret = nouveau_volt_map(volt, id);
-	if (ret >= 0) {
-		int prev = nouveau_volt_get(volt);
-		if (!condition || prev < 0 ||
-		    (condition < 0 && ret < prev) ||
-		    (condition > 0 && ret > prev)) {
-			ret = nouveau_volt_set(volt, ret);
-		} else {
-			ret = 0;
-		}
-	}
-	return ret;
-}
-
-static void nouveau_volt_parse_bios(struct nouveau_bios *bios,
-		struct nouveau_volt *volt)
-{
-	struct nvbios_volt_entry ivid;
-	struct nvbios_volt info;
-	u8  ver, hdr, cnt, len;
-	u16 data;
-	int i;
-
-	data = nvbios_volt_parse(bios, &ver, &hdr, &cnt, &len, &info);
-	if (data && info.vidmask && info.base && info.step) {
-		for (i = 0; i < info.vidmask + 1; i++) {
-			if (info.base >= info.min &&
-				info.base <= info.max) {
-				volt->vid[volt->vid_nr].uv = info.base;
-				volt->vid[volt->vid_nr].vid = i;
-				volt->vid_nr++;
-			}
-			info.base += info.step;
-		}
-		volt->vid_mask = info.vidmask;
-	} else if (data && info.vidmask) {
-		for (i = 0; i < cnt; i++) {
-			data = nvbios_volt_entry_parse(bios, i, &ver, &hdr,
-							  &ivid);
-			if (data) {
-				volt->vid[volt->vid_nr].uv = ivid.voltage;
-				volt->vid[volt->vid_nr].vid = ivid.vid;
-				volt->vid_nr++;
-			}
-		}
-		volt->vid_mask = info.vidmask;
-	}
-}
-
-int
-_nouveau_volt_init(struct nouveau_object *object)
-{
-	struct nouveau_volt *volt = (void *)object;
-	int ret;
-
-	ret = nouveau_subdev_init(&volt->base);
-	if (ret)
-		return ret;
-
-	ret = volt->get(volt);
-	if (ret < 0) {
-		if (ret != -ENODEV)
-			nv_debug(volt, "current voltage unknown\n");
-		return 0;
-	}
-
-	nv_info(volt, "GPU voltage: %duv\n", ret);
-	return 0;
-}
-
-void
-_nouveau_volt_dtor(struct nouveau_object *object)
-{
-	struct nouveau_volt *volt = (void *)object;
-	nouveau_subdev_destroy(&volt->base);
-}
-
-int
-nouveau_volt_create_(struct nouveau_object *parent,
-		     struct nouveau_object *engine,
-		     struct nouveau_oclass *oclass, int length, void **pobject)
-{
-	struct nouveau_bios *bios = nouveau_bios(parent);
-	struct nouveau_volt *volt;
-	int ret, i;
-
-	ret = nouveau_subdev_create_(parent, engine, oclass, 0, "VOLT",
-				     "voltage", length, pobject);
-	volt = *pobject;
-	if (ret)
-		return ret;
-
-	volt->get = nouveau_volt_get;
-	volt->set = nouveau_volt_set;
-	volt->set_id = nouveau_volt_set_id;
-
-	/* Assuming the non-bios device should build the voltage table later */
-	if (bios)
-		nouveau_volt_parse_bios(bios, volt);
-
-	if (volt->vid_nr) {
-		for (i = 0; i < volt->vid_nr; i++) {
-			nv_debug(volt, "VID %02x: %duv\n",
-				 volt->vid[i].vid, volt->vid[i].uv);
-		}
-
-		/*XXX: this is an assumption.. there probably exists boards
-		 * out there with i2c-connected voltage controllers too..
-		 */
-		ret = nouveau_voltgpio_init(volt);
-		if (ret == 0) {
-			volt->vid_get = nouveau_voltgpio_get;
-			volt->vid_set = nouveau_voltgpio_set;
-		}
-	}
-
-	return ret;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/volt/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/volt/gk20a.c
deleted file mode 100644
index 717368ef31ac..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/volt/gk20a.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef __KERNEL__
-#include <nouveau_platform.h>
-#endif
-#include <subdev/volt.h>
-
-struct cvb_coef {
-	int c0;
-	int c1;
-	int c2;
-	int c3;
-	int c4;
-	int c5;
-};
-
-struct gk20a_volt_priv {
-	struct nouveau_volt base;
-	struct regulator *vdd;
-};
-
-const struct cvb_coef gk20a_cvb_coef[] = {
-	/* MHz,        c0,     c1,   c2,    c3,     c4,   c5 */
-	/*  72 */ { 1209886, -36468,  515,   417, -13123,  203},
-	/* 108 */ { 1130804, -27659,  296,   298, -10834,  221},
-	/* 180 */ { 1162871, -27110,  247,   238, -10681,  268},
-	/* 252 */ { 1220458, -28654,  247,   179, -10376,  298},
-	/* 324 */ { 1280953, -30204,  247,   119,  -9766,  304},
-	/* 396 */ { 1344547, -31777,  247,   119,  -8545,  292},
-	/* 468 */ { 1420168, -34227,  269,    60,  -7172,  256},
-	/* 540 */ { 1490757, -35955,  274,    60,  -5188,  197},
-	/* 612 */ { 1599112, -42583,  398,     0,  -1831,  119},
-	/* 648 */ { 1366986, -16459, -274,     0,  -3204,   72},
-	/* 684 */ { 1391884, -17078, -274,   -60,  -1526,   30},
-	/* 708 */ { 1415522, -17497, -274,   -60,   -458,    0},
-	/* 756 */ { 1464061, -18331, -274,  -119,   1831,  -72},
-	/* 804 */ { 1524225, -20064, -254,  -119,   4272, -155},
-	/* 852 */ { 1608418, -21643, -269,     0,    763,  -48},
-};
-
-/**
- * cvb_mv = ((c2 * speedo / s_scale + c1) * speedo / s_scale + c0)
- */
-static inline int
-gk20a_volt_get_cvb_voltage(int speedo, int s_scale,
-		const struct cvb_coef *coef)
-{
-	int mv;
-
-	mv = DIV_ROUND_CLOSEST(coef->c2 * speedo, s_scale);
-	mv = DIV_ROUND_CLOSEST((mv + coef->c1) * speedo, s_scale) + coef->c0;
-	return mv;
-}
-
-/**
- * cvb_t_mv =
- * ((c2 * speedo / s_scale + c1) * speedo / s_scale + c0) +
- * ((c3 * speedo / s_scale + c4 + c5 * T / t_scale) * T / t_scale)
- */
-static inline int
-gk20a_volt_get_cvb_t_voltage(int speedo, int temp, int s_scale, int t_scale,
-		const struct cvb_coef *coef)
-{
-	int cvb_mv, mv;
-
-	cvb_mv = gk20a_volt_get_cvb_voltage(speedo, s_scale, coef);
-
-	mv = DIV_ROUND_CLOSEST(coef->c3 * speedo, s_scale) + coef->c4 +
-		DIV_ROUND_CLOSEST(coef->c5 * temp, t_scale);
-	mv = DIV_ROUND_CLOSEST(mv * temp, t_scale) + cvb_mv;
-	return mv;
-}
-
-static int
-gk20a_volt_calc_voltage(const struct cvb_coef *coef, int speedo)
-{
-	int mv;
-
-	mv = gk20a_volt_get_cvb_t_voltage(speedo, -10, 100, 10, coef);
-	mv = DIV_ROUND_UP(mv, 1000);
-
-	return mv * 1000;
-}
-
-static int
-gk20a_volt_vid_get(struct nouveau_volt *volt)
-{
-	struct gk20a_volt_priv *priv = (void *)volt;
-	int i, uv;
-
-	uv = regulator_get_voltage(priv->vdd);
-
-	for (i = 0; i < volt->vid_nr; i++)
-		if (volt->vid[i].uv >= uv)
-			return i;
-
-	return -EINVAL;
-}
-
-static int
-gk20a_volt_vid_set(struct nouveau_volt *volt, u8 vid)
-{
-	struct gk20a_volt_priv *priv = (void *)volt;
-
-	nv_debug(volt, "set voltage as %duv\n", volt->vid[vid].uv);
-	return regulator_set_voltage(priv->vdd, volt->vid[vid].uv, 1200000);
-}
-
-static int
-gk20a_volt_set_id(struct nouveau_volt *volt, u8 id, int condition)
-{
-	struct gk20a_volt_priv *priv = (void *)volt;
-	int prev_uv = regulator_get_voltage(priv->vdd);
-	int target_uv = volt->vid[id].uv;
-	int ret;
-
-	nv_debug(volt, "prev=%d, target=%d, condition=%d\n",
-			prev_uv, target_uv, condition);
-	if (!condition ||
-		(condition < 0 && target_uv < prev_uv) ||
-		(condition > 0 && target_uv > prev_uv)) {
-		ret = gk20a_volt_vid_set(volt, volt->vid[id].vid);
-	} else {
-		ret = 0;
-	}
-
-	return ret;
-}
-
-static int
-gk20a_volt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct gk20a_volt_priv *priv;
-	struct nouveau_volt *volt;
-	struct nouveau_platform_device *plat;
-	int i, ret, uv;
-
-	ret = nouveau_volt_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	volt = &priv->base;
-
-	plat = nv_device_to_platform(nv_device(parent));
-
-	uv = regulator_get_voltage(plat->gpu->vdd);
-	nv_info(priv, "The default voltage is %duV\n", uv);
-
-	priv->vdd = plat->gpu->vdd;
-	priv->base.vid_get = gk20a_volt_vid_get;
-	priv->base.vid_set = gk20a_volt_vid_set;
-	priv->base.set_id = gk20a_volt_set_id;
-
-	volt->vid_nr = ARRAY_SIZE(gk20a_cvb_coef);
-	nv_debug(priv, "%s - vid_nr = %d\n", __func__, volt->vid_nr);
-	for (i = 0; i < volt->vid_nr; i++) {
-		volt->vid[i].vid = i;
-		volt->vid[i].uv = gk20a_volt_calc_voltage(&gk20a_cvb_coef[i],
-					plat->gpu_speedo);
-		nv_debug(priv, "%2d: vid=%d, uv=%d\n", i, volt->vid[i].vid,
-					volt->vid[i].uv);
-	}
-
-	return 0;
-}
-
-struct nouveau_oclass
-gk20a_volt_oclass = {
-	.handle = NV_SUBDEV(VOLT, 0xea),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = gk20a_volt_ctor,
-		.dtor = _nouveau_volt_dtor,
-		.init = _nouveau_volt_init,
-		.fini = _nouveau_volt_fini,
-	},
-};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/volt/gpio.c b/drivers/gpu/drm/nouveau/core/subdev/volt/gpio.c
deleted file mode 100644
index 755fa91bcd09..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/volt/gpio.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/volt.h>
-#include <subdev/gpio.h>
-#include <subdev/bios/gpio.h>
-
-static const u8 tags[] = {
-	DCB_GPIO_VID0, DCB_GPIO_VID1, DCB_GPIO_VID2, DCB_GPIO_VID3,
-	DCB_GPIO_VID4, DCB_GPIO_VID5, DCB_GPIO_VID6, DCB_GPIO_VID7,
-};
-
-int
-nouveau_voltgpio_get(struct nouveau_volt *volt)
-{
-	struct nouveau_gpio *gpio = nouveau_gpio(volt);
-	u8 vid = 0;
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(tags); i++) {
-		if (volt->vid_mask & (1 << i)) {
-			int ret = gpio->get(gpio, 0, tags[i], 0xff);
-			if (ret < 0)
-				return ret;
-			vid |= ret << i;
-		}
-	}
-
-	return vid;
-}
-
-int
-nouveau_voltgpio_set(struct nouveau_volt *volt, u8 vid)
-{
-	struct nouveau_gpio *gpio = nouveau_gpio(volt);
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(tags); i++, vid >>= 1) {
-		if (volt->vid_mask & (1 << i)) {
-			int ret = gpio->set(gpio, 0, tags[i], 0xff, vid & 1);
-			if (ret < 0)
-				return ret;
-		}
-	}
-
-	return 0;
-}
-
-int
-nouveau_voltgpio_init(struct nouveau_volt *volt)
-{
-	struct nouveau_gpio *gpio = nouveau_gpio(volt);
-	struct dcb_gpio_func func;
-	int i;
-
-	/* check we have gpio function info for each vid bit.  on some
-	 * boards (ie. nvs295) the vid mask has more bits than there
-	 * are valid gpio functions... from traces, nvidia appear to
-	 * just touch the existing ones, so let's mask off the invalid
-	 * bits and continue with life
-	 */
-	for (i = 0; i < ARRAY_SIZE(tags); i++) {
-		if (volt->vid_mask & (1 << i)) {
-			int ret = gpio->find(gpio, 0, tags[i], 0xff, &func);
-			if (ret) {
-				if (ret != -ENOENT)
-					return ret;
-				nv_debug(volt, "VID bit %d has no GPIO\n", i);
-				volt->vid_mask &= ~(1 << i);
-			}
-		}
-	}
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/volt/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/volt/nv40.c
deleted file mode 100644
index 87d5358376a6..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/volt/nv40.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/volt.h>
-
-struct nv40_volt_priv {
-	struct nouveau_volt base;
-};
-
-static int
-nv40_volt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
-{
-	struct nv40_volt_priv *priv;
-	int ret;
-
-	ret = nouveau_volt_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-struct nouveau_oclass
-nv40_volt_oclass = {
-	.handle = NV_SUBDEV(VOLT, 0x40),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv40_volt_ctor,
-		.dtor = _nouveau_volt_dtor,
-		.init = _nouveau_volt_init,
-		.fini = _nouveau_volt_fini,
-	},
-};