diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/include/nvkm/subdev')
51 files changed, 2236 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h new file mode 100644 index 000000000000..c7a007b8bc10 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h @@ -0,0 +1,33 @@ +#ifndef __NVKM_BAR_H__ +#define __NVKM_BAR_H__ +#include <core/subdev.h> +struct nvkm_mem; +struct nvkm_vma; + +struct nvkm_bar { + struct nvkm_subdev base; + + int (*alloc)(struct nvkm_bar *, struct nvkm_object *, + struct nvkm_mem *, struct nvkm_object **); + + int (*kmap)(struct nvkm_bar *, struct nvkm_mem *, u32 flags, + struct nvkm_vma *); + int (*umap)(struct nvkm_bar *, struct nvkm_mem *, u32 flags, + struct nvkm_vma *); + void (*unmap)(struct nvkm_bar *, struct nvkm_vma *); + void (*flush)(struct nvkm_bar *); + + /* whether the BAR supports to be ioremapped WC or should be uncached */ + bool iomap_uncached; +}; + +static inline struct nvkm_bar * +nvkm_bar(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_BAR); +} + +extern struct nvkm_oclass nv50_bar_oclass; +extern struct nvkm_oclass gf100_bar_oclass; +extern struct nvkm_oclass gk20a_bar_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h new file mode 100644 index 000000000000..cef287e0bbf2 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h @@ -0,0 +1,32 @@ +#ifndef __NVKM_BIOS_H__ +#define __NVKM_BIOS_H__ +#include <core/subdev.h> + +struct nvkm_bios { + struct nvkm_subdev base; + u32 size; + u8 *data; + + u32 bmp_offset; + u32 bit_offset; + + struct { + u8 major; + u8 chip; + u8 minor; + u8 micro; + u8 patch; + } version; +}; + +static inline struct nvkm_bios * +nvkm_bios(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_VBIOS); +} + +u8 nvbios_checksum(const u8 *data, int size); +u16 nvbios_findstr(const u8 *data, int size, const char *str, int len); + +extern struct nvkm_oclass nvkm_bios_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0203.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0203.h new file mode 100644 index 000000000000..cf202c793a1d --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0203.h @@ -0,0 +1,29 @@ +#ifndef __NVBIOS_M0203_H__ +#define __NVBIOS_M0203_H__ +struct nvbios_M0203T { +#define M0203T_TYPE_RAMCFG 0x00 + u8 type; + u16 pointer; +}; + +u32 nvbios_M0203Te(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u32 nvbios_M0203Tp(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, + struct nvbios_M0203T *); + +struct nvbios_M0203E { +#define M0203E_TYPE_DDR2 0x0 +#define M0203E_TYPE_DDR3 0x1 +#define M0203E_TYPE_GDDR3 0x2 +#define M0203E_TYPE_GDDR5 0x3 +#define M0203E_TYPE_SKIP 0xf + u8 type; + u8 strap; + u8 group; +}; + +u32 nvbios_M0203Ee(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr); +u32 nvbios_M0203Ep(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, + struct nvbios_M0203E *); +u32 nvbios_M0203Em(struct nvkm_bios *, u8 ramcfg, u8 *ver, u8 *hdr, + struct nvbios_M0203E *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h new file mode 100644 index 000000000000..d34608ff241e --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h @@ -0,0 +1,29 @@ +#ifndef __NVBIOS_M0205_H__ +#define __NVBIOS_M0205_H__ +struct nvbios_M0205T { + u16 freq; +}; + +u32 nvbios_M0205Te(struct nvkm_bios *, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz); +u32 nvbios_M0205Tp(struct nvkm_bios *, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz, + struct nvbios_M0205T *); + +struct nvbios_M0205E { + u8 type; +}; + +u32 nvbios_M0205Ee(struct nvkm_bios *, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u32 nvbios_M0205Ep(struct nvkm_bios *, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_M0205E *); + +struct nvbios_M0205S { + u8 data; +}; + +u32 nvbios_M0205Se(struct nvkm_bios *, int ent, int idx, u8 *ver, u8 *hdr); +u32 nvbios_M0205Sp(struct nvkm_bios *, int ent, int idx, u8 *ver, u8 *hdr, + struct nvbios_M0205S *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h new file mode 100644 index 000000000000..c7ff8d9526e7 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h @@ -0,0 +1,27 @@ +#ifndef __NVBIOS_M0209_H__ +#define __NVBIOS_M0209_H__ +u32 nvbios_M0209Te(struct nvkm_bios *, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz); + +struct nvbios_M0209E { + u8 v00_40; + u8 bits; + u8 modulo; + u8 v02_40; + u8 v02_07; + u8 v03; +}; + +u32 nvbios_M0209Ee(struct nvkm_bios *, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u32 nvbios_M0209Ep(struct nvkm_bios *, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_M0209E *); + +struct nvbios_M0209S { + u32 data[0x200]; +}; + +u32 nvbios_M0209Se(struct nvkm_bios *, int ent, int idx, u8 *ver, u8 *hdr); +u32 nvbios_M0209Sp(struct nvkm_bios *, int ent, int idx, u8 *ver, u8 *hdr, + struct nvbios_M0209S *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h new file mode 100644 index 000000000000..1c1c52eac97d --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h @@ -0,0 +1,21 @@ +#ifndef __NVBIOS_P0260_H__ +#define __NVBIOS_P0260_H__ +u32 nvbios_P0260Te(struct nvkm_bios *, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz); + +struct nvbios_P0260E { + u32 data; +}; + +u32 nvbios_P0260Ee(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr); +u32 nvbios_P0260Ep(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, + struct nvbios_P0260E *); + +struct nvbios_P0260X { + u32 data; +}; + +u32 nvbios_P0260Xe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr); +u32 nvbios_P0260Xp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, + struct nvbios_P0260X *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bit.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bit.h new file mode 100644 index 000000000000..6711732b7cb1 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bit.h @@ -0,0 +1,11 @@ +#ifndef __NVBIOS_BIT_H__ +#define __NVBIOS_BIT_H__ +struct bit_entry { + u8 id; + u8 version; + u16 length; + u16 offset; +}; + +int bit_entry(struct nvkm_bios *, u8 id, struct bit_entry *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h new file mode 100644 index 000000000000..4107aa546a21 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h @@ -0,0 +1,37 @@ +#ifndef __NVBIOS_BMP_H__ +#define __NVBIOS_BMP_H__ +static inline u16 +bmp_version(struct nvkm_bios *bios) +{ + if (bios->bmp_offset) { + return nv_ro08(bios, bios->bmp_offset + 5) << 8 | + nv_ro08(bios, bios->bmp_offset + 6); + } + + return 0x0000; +} + +static inline u16 +bmp_mem_init_table(struct nvkm_bios *bios) +{ + if (bmp_version(bios) >= 0x0300) + return nv_ro16(bios, bios->bmp_offset + 24); + return 0x0000; +} + +static inline u16 +bmp_sdr_seq_table(struct nvkm_bios *bios) +{ + if (bmp_version(bios) >= 0x0300) + return nv_ro16(bios, bios->bmp_offset + 26); + return 0x0000; +} + +static inline u16 +bmp_ddr_seq_table(struct nvkm_bios *bios) +{ + if (bmp_version(bios) >= 0x0300) + return nv_ro16(bios, bios->bmp_offset + 28); + return 0x0000; +} +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h new file mode 100644 index 000000000000..934b0ae5521d --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h @@ -0,0 +1,27 @@ +#ifndef __NVBIOS_BOOST_H__ +#define __NVBIOS_BOOST_H__ +u16 nvbios_boostTe(struct nvkm_bios *, u8 *, u8 *, u8 *, u8 *, u8 *, u8 *); + +struct nvbios_boostE { + u8 pstate; + u32 min; + u32 max; +}; + +u16 nvbios_boostEe(struct nvkm_bios *, int idx, u8 *, u8 *, u8 *, u8 *); +u16 nvbios_boostEp(struct nvkm_bios *, int idx, u8 *, u8 *, u8 *, u8 *, + struct nvbios_boostE *); +u16 nvbios_boostEm(struct nvkm_bios *, u8, u8 *, u8 *, u8 *, u8 *, + struct nvbios_boostE *); + +struct nvbios_boostS { + u8 domain; + u8 percent; + u32 min; + u32 max; +}; + +u16 nvbios_boostSe(struct nvkm_bios *, int, u16, u8 *, u8 *, u8, u8); +u16 nvbios_boostSp(struct nvkm_bios *, int, u16, u8 *, u8 *, u8, u8, + struct nvbios_boostS *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h new file mode 100644 index 000000000000..e8e77ee24776 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h @@ -0,0 +1,44 @@ +#ifndef __NVBIOS_CONN_H__ +#define __NVBIOS_CONN_H__ +enum dcb_connector_type { + DCB_CONNECTOR_VGA = 0x00, + DCB_CONNECTOR_TV_0 = 0x10, + DCB_CONNECTOR_TV_1 = 0x11, + DCB_CONNECTOR_TV_3 = 0x13, + DCB_CONNECTOR_DVI_I = 0x30, + DCB_CONNECTOR_DVI_D = 0x31, + DCB_CONNECTOR_DMS59_0 = 0x38, + DCB_CONNECTOR_DMS59_1 = 0x39, + DCB_CONNECTOR_LVDS = 0x40, + DCB_CONNECTOR_LVDS_SPWG = 0x41, + DCB_CONNECTOR_DP = 0x46, + DCB_CONNECTOR_eDP = 0x47, + DCB_CONNECTOR_HDMI_0 = 0x60, + DCB_CONNECTOR_HDMI_1 = 0x61, + DCB_CONNECTOR_HDMI_C = 0x63, + DCB_CONNECTOR_DMS59_DP0 = 0x64, + DCB_CONNECTOR_DMS59_DP1 = 0x65, + DCB_CONNECTOR_NONE = 0xff +}; + +struct nvbios_connT { +}; + +u32 nvbios_connTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u32 nvbios_connTp(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, + struct nvbios_connT *info); + +struct nvbios_connE { + u8 type; + u8 location; + u8 hpd; + u8 dp; + u8 di; + u8 sr; + u8 lcdid; +}; + +u32 nvbios_connEe(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *hdr); +u32 nvbios_connEp(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *hdr, + struct nvbios_connE *info); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h new file mode 100644 index 000000000000..2f0e0c8e83be --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h @@ -0,0 +1,26 @@ +#ifndef __NVBIOS_CSTEP_H__ +#define __NVBIOS_CSTEP_H__ +u16 nvbios_cstepTe(struct nvkm_bios *, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz); + +struct nvbios_cstepE { + u8 pstate; + u8 index; +}; + +u16 nvbios_cstepEe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr); +u16 nvbios_cstepEp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, + struct nvbios_cstepE *); +u16 nvbios_cstepEm(struct nvkm_bios *, u8 pstate, u8 *ver, u8 *hdr, + struct nvbios_cstepE *); + +struct nvbios_cstepX { + u32 freq; + u8 unkn[2]; + u8 voltage; +}; + +u16 nvbios_cstepXe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr); +u16 nvbios_cstepXp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, + struct nvbios_cstepX *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h new file mode 100644 index 000000000000..4892a65ddd48 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h @@ -0,0 +1,65 @@ +#ifndef __NVBIOS_DCB_H__ +#define __NVBIOS_DCB_H__ +enum dcb_output_type { + DCB_OUTPUT_ANALOG = 0x0, + DCB_OUTPUT_TV = 0x1, + DCB_OUTPUT_TMDS = 0x2, + DCB_OUTPUT_LVDS = 0x3, + DCB_OUTPUT_DP = 0x6, + DCB_OUTPUT_EOL = 0xe, + DCB_OUTPUT_UNUSED = 0xf, + DCB_OUTPUT_ANY = -1, +}; + +struct dcb_output { + int index; /* may not be raw dcb index if merging has happened */ + u16 hasht; + u16 hashm; + enum dcb_output_type type; + uint8_t i2c_index; + uint8_t heads; + uint8_t connector; + uint8_t bus; + uint8_t location; + uint8_t or; + uint8_t link; + bool duallink_possible; + uint8_t extdev; + union { + struct sor_conf { + int link; + } sorconf; + struct { + int maxfreq; + } crtconf; + struct { + struct sor_conf sor; + bool use_straps_for_mode; + bool use_acpi_for_edid; + bool use_power_scripts; + } lvdsconf; + struct { + bool has_component_output; + } tvconf; + struct { + struct sor_conf sor; + int link_nr; + int link_bw; + } dpconf; + struct { + struct sor_conf sor; + int slave_addr; + } tmdsconf; + }; + bool i2c_upper_default; +}; + +u16 dcb_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *ent, u8 *len); +u16 dcb_outp(struct nvkm_bios *, u8 idx, u8 *ver, u8 *len); +u16 dcb_outp_parse(struct nvkm_bios *, u8 idx, u8 *, u8 *, + struct dcb_output *); +u16 dcb_outp_match(struct nvkm_bios *, u16 type, u16 mask, u8 *, u8 *, + struct dcb_output *); +int dcb_outp_foreach(struct nvkm_bios *, void *data, int (*exec) + (struct nvkm_bios *, void *, int index, u16 entry)); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h new file mode 100644 index 000000000000..db10c11f0595 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h @@ -0,0 +1,39 @@ +#ifndef __NVBIOS_DISP_H__ +#define __NVBIOS_DISP_H__ +u16 nvbios_disp_table(struct nvkm_bios *, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *sub); + +struct nvbios_disp { + u16 data; +}; + +u16 nvbios_disp_entry(struct nvkm_bios *, u8 idx, u8 *ver, u8 *hdr, u8 *sub); +u16 nvbios_disp_parse(struct nvkm_bios *, u8 idx, u8 *ver, u8 *hdr, u8 *sub, + struct nvbios_disp *); + +struct nvbios_outp { + u16 type; + u16 mask; + u16 script[3]; +}; + +u16 nvbios_outp_entry(struct nvkm_bios *, u8 idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u16 nvbios_outp_parse(struct nvkm_bios *, u8 idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_outp *); +u16 nvbios_outp_match(struct nvkm_bios *, u16 type, u16 mask, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_outp *); + +struct nvbios_ocfg { + u16 match; + u16 clkcmp[2]; +}; + +u16 nvbios_ocfg_entry(struct nvkm_bios *, u16 outp, u8 idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u16 nvbios_ocfg_parse(struct nvkm_bios *, u16 outp, u8 idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ocfg *); +u16 nvbios_ocfg_match(struct nvkm_bios *, u16 outp, u16 type, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ocfg *); +u16 nvbios_oclk_match(struct nvkm_bios *, u16 cmp, u32 khz); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h new file mode 100644 index 000000000000..b4d39df70d4e --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h @@ -0,0 +1,31 @@ +#ifndef __NVBIOS_DP_H__ +#define __NVBIOS_DP_H__ +struct nvbios_dpout { + u16 type; + u16 mask; + u8 flags; + u32 script[5]; + u32 lnkcmp; +}; + +u16 nvbios_dpout_parse(struct nvkm_bios *, u8 idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, + struct nvbios_dpout *); +u16 nvbios_dpout_match(struct nvkm_bios *, u16 type, u16 mask, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, + struct nvbios_dpout *); + +struct nvbios_dpcfg { + u8 pc; + u8 dc; + u8 pe; + u8 tx_pu; +}; + +u16 +nvbios_dpcfg_parse(struct nvkm_bios *, u16 outp, u8 idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_dpcfg *); +u16 +nvbios_dpcfg_match(struct nvkm_bios *, u16 outp, u8 pc, u8 vs, u8 pe, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_dpcfg *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h new file mode 100644 index 000000000000..6d3bedc633b3 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h @@ -0,0 +1,25 @@ +#ifndef __NVBIOS_EXTDEV_H__ +#define __NVBIOS_EXTDEV_H__ +enum nvbios_extdev_type { + NVBIOS_EXTDEV_LM89 = 0x02, + NVBIOS_EXTDEV_VT1103M = 0x40, + NVBIOS_EXTDEV_PX3540 = 0x41, + NVBIOS_EXTDEV_VT1105M = 0x42, /* or close enough... */ + NVBIOS_EXTDEV_ADT7473 = 0x70, /* can also be a LM64 */ + NVBIOS_EXTDEV_HDCP_EEPROM = 0x90, + NVBIOS_EXTDEV_NONE = 0xff, +}; + +struct nvbios_extdev_func { + u8 type; + u8 addr; + u8 bus; +}; + +int +nvbios_extdev_parse(struct nvkm_bios *, int, struct nvbios_extdev_func *); + +int +nvbios_extdev_find(struct nvkm_bios *, enum nvbios_extdev_type, + struct nvbios_extdev_func *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h new file mode 100644 index 000000000000..693ea7d9ec43 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h @@ -0,0 +1,6 @@ +#ifndef __NVBIOS_FAN_H__ +#define __NVBIOS_FAN_H__ +#include <subdev/bios/therm.h> + +u16 nvbios_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h new file mode 100644 index 000000000000..33be260ddd38 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h @@ -0,0 +1,46 @@ +#ifndef __NVBIOS_GPIO_H__ +#define __NVBIOS_GPIO_H__ +enum dcb_gpio_func_name { + DCB_GPIO_PANEL_POWER = 0x01, + DCB_GPIO_TVDAC0 = 0x0c, + DCB_GPIO_TVDAC1 = 0x2d, + DCB_GPIO_FAN = 0x09, + DCB_GPIO_FAN_SENSE = 0x3d, + DCB_GPIO_UNUSED = 0xff, + DCB_GPIO_VID0 = 0x04, + DCB_GPIO_VID1 = 0x05, + DCB_GPIO_VID2 = 0x06, + DCB_GPIO_VID3 = 0x1a, + DCB_GPIO_VID4 = 0x73, + DCB_GPIO_VID5 = 0x74, + DCB_GPIO_VID6 = 0x75, + DCB_GPIO_VID7 = 0x76, +}; + +#define DCB_GPIO_LOG_DIR 0x02 +#define DCB_GPIO_LOG_DIR_OUT 0x00 +#define DCB_GPIO_LOG_DIR_IN 0x02 +#define DCB_GPIO_LOG_VAL 0x01 +#define DCB_GPIO_LOG_VAL_LO 0x00 +#define DCB_GPIO_LOG_VAL_HI 0x01 + +struct dcb_gpio_func { + u8 func; + u8 line; + u8 log[2]; + + /* so far, "param" seems to only have an influence on PWM-related + * GPIOs such as FAN_CONTROL and PANEL_BACKLIGHT_LEVEL. + * if param equals 1, hardware PWM is available + * if param equals 0, the host should toggle the GPIO itself + */ + u8 param; +}; + +u16 dcb_gpio_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u16 dcb_gpio_entry(struct nvkm_bios *, int idx, int ent, u8 *ver, u8 *len); +u16 dcb_gpio_parse(struct nvkm_bios *, int idx, int ent, u8 *ver, u8 *len, + struct dcb_gpio_func *); +u16 dcb_gpio_match(struct nvkm_bios *, int idx, u8 func, u8 line, + u8 *ver, u8 *len, struct dcb_gpio_func *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/i2c.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/i2c.h new file mode 100644 index 000000000000..85c529ecf9b1 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/i2c.h @@ -0,0 +1,25 @@ +#ifndef __NVBIOS_I2C_H__ +#define __NVBIOS_I2C_H__ +enum dcb_i2c_type { + /* matches bios type field prior to ccb 4.1 */ + DCB_I2C_NV04_BIT = 0x00, + DCB_I2C_NV4E_BIT = 0x04, + DCB_I2C_NVIO_BIT = 0x05, + DCB_I2C_NVIO_AUX = 0x06, + /* made up - mostly */ + DCB_I2C_PMGR = 0x80, + DCB_I2C_UNUSED = 0xff +}; + +struct dcb_i2c_entry { + enum dcb_i2c_type type; + u8 drive; + u8 sense; + u8 share; + u8 auxch; +}; + +u16 dcb_i2c_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u16 dcb_i2c_entry(struct nvkm_bios *, u8 index, u8 *ver, u8 *len); +int dcb_i2c_parse(struct nvkm_bios *, u8 index, struct dcb_i2c_entry *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h new file mode 100644 index 000000000000..e15d63b9a5eb --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h @@ -0,0 +1,11 @@ +#ifndef __NVBIOS_IMAGE_H__ +#define __NVBIOS_IMAGE_H__ +struct nvbios_image { + u32 base; + u32 size; + u8 type; + bool last; +}; + +bool nvbios_image(struct nvkm_bios *, int, struct nvbios_image *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h new file mode 100644 index 000000000000..578a667eed3b --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h @@ -0,0 +1,20 @@ +#ifndef __NVBIOS_INIT_H__ +#define __NVBIOS_INIT_H__ +struct nvbios_init { + struct nvkm_subdev *subdev; + struct nvkm_bios *bios; + u16 offset; + struct dcb_output *outp; + int crtc; + + /* internal state used during parsing */ + u8 execute; + u32 nested; + u16 repeat; + u16 repend; + u32 ramcfg; +}; + +int nvbios_exec(struct nvbios_init *); +int nvbios_init(struct nvkm_subdev *, bool execute); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h new file mode 100644 index 000000000000..4e31b64c5edf --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h @@ -0,0 +1,6 @@ +#ifndef __NVBIOS_MXM_H__ +#define __NVBIOS_MXM_H__ +u16 mxm_table(struct nvkm_bios *, u8 *ver, u8 *hdr); +u8 mxm_sor_map(struct nvkm_bios *, u8 conn); +u8 mxm_ddc_map(struct nvkm_bios *, u8 port); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h new file mode 100644 index 000000000000..64a59549b7ea --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h @@ -0,0 +1,10 @@ +#ifndef __NVBIOS_NPDE_H__ +#define __NVBIOS_NPDE_H__ +struct nvbios_npdeT { + u32 image_size; + bool last; +}; + +u32 nvbios_npdeTe(struct nvkm_bios *, u32); +u32 nvbios_npdeTp(struct nvkm_bios *, u32, struct nvbios_npdeT *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pcir.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pcir.h new file mode 100644 index 000000000000..e85931541f4f --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pcir.h @@ -0,0 +1,16 @@ +#ifndef __NVBIOS_PCIR_H__ +#define __NVBIOS_PCIR_H__ +struct nvbios_pcirT { + u16 vendor_id; + u16 device_id; + u8 class_code[3]; + u32 image_size; + u16 image_rev; + u8 image_type; + bool last; +}; + +u32 nvbios_pcirTe(struct nvkm_bios *, u32, u8 *ver, u16 *hdr); +u32 nvbios_pcirTp(struct nvkm_bios *, u32, u8 *ver, u16 *hdr, + struct nvbios_pcirT *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h new file mode 100644 index 000000000000..7cc2becabc69 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h @@ -0,0 +1,41 @@ +#ifndef __NVBIOS_PERF_H__ +#define __NVBIOS_PERF_H__ +u16 nvbios_perf_table(struct nvkm_bios *, u8 *ver, u8 *hdr, + u8 *cnt, u8 *len, u8 *snr, u8 *ssz); + +struct nvbios_perfE { + u8 pstate; + u8 fanspeed; + u8 voltage; + u32 core; + u32 shader; + u32 memory; + u32 vdec; + u32 disp; + u32 script; +}; + +u16 nvbios_perf_entry(struct nvkm_bios *, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u16 nvbios_perfEp(struct nvkm_bios *, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_perfE *); + +struct nvbios_perfS { + union { + struct { + u32 freq; + } v40; + }; +}; + +u32 nvbios_perfSe(struct nvkm_bios *, u32 data, int idx, + u8 *ver, u8 *hdr, u8 cnt, u8 len); +u32 nvbios_perfSp(struct nvkm_bios *, u32 data, int idx, + u8 *ver, u8 *hdr, u8 cnt, u8 len, struct nvbios_perfS *); + +struct nvbios_perf_fan { + u32 pwm_divisor; +}; + +int nvbios_perf_fan_parse(struct nvkm_bios *, struct nvbios_perf_fan *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h new file mode 100644 index 000000000000..5a69978d1e3b --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h @@ -0,0 +1,75 @@ +#ifndef __NVBIOS_PLL_H__ +#define __NVBIOS_PLL_H__ +/*XXX: kill me */ +struct nvkm_pll_vals { + union { + struct { +#ifdef __BIG_ENDIAN + uint8_t N1, M1, N2, M2; +#else + uint8_t M1, N1, M2, N2; +#endif + }; + struct { + uint16_t NM1, NM2; + } __attribute__((packed)); + }; + int log2P; + + int refclk; +}; + +/* these match types in pll limits table version 0x40, + * nvkm uses them on all chipsets internally where a + * specific pll needs to be referenced, but the exact + * register isn't known. + */ +enum nvbios_pll_type { + PLL_CORE = 0x01, + PLL_SHADER = 0x02, + PLL_UNK03 = 0x03, + PLL_MEMORY = 0x04, + PLL_VDEC = 0x05, + PLL_UNK40 = 0x40, + PLL_UNK41 = 0x41, + PLL_UNK42 = 0x42, + PLL_VPLL0 = 0x80, + PLL_VPLL1 = 0x81, + PLL_VPLL2 = 0x82, + PLL_VPLL3 = 0x83, + PLL_MAX = 0xff +}; + +struct nvbios_pll { + enum nvbios_pll_type type; + u32 reg; + u32 refclk; + + u8 min_p; + u8 max_p; + u8 bias_p; + + /* + * for most pre nv50 cards setting a log2P of 7 (the common max_log2p + * value) is no different to 6 (at least for vplls) so allowing the MNP + * calc to use 7 causes the generated clock to be out by a factor of 2. + * however, max_log2p cannot be fixed-up during parsing as the + * unmodified max_log2p value is still needed for setting mplls, hence + * an additional max_usable_log2p member + */ + u8 max_p_usable; + + struct { + u32 min_freq; + u32 max_freq; + u32 min_inputfreq; + u32 max_inputfreq; + u8 min_m; + u8 max_m; + u8 min_n; + u8 max_n; + } vco1, vco2; +}; + +int nvbios_pll_parse(struct nvkm_bios *, u32 type, struct nvbios_pll *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h new file mode 100644 index 000000000000..d606875c125a --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h @@ -0,0 +1,35 @@ +#ifndef __NVBIOS_PMU_H__ +#define __NVBIOS_PMU_H__ +struct nvbios_pmuT { +}; + +u32 nvbios_pmuTe(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u32 nvbios_pmuTp(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, + struct nvbios_pmuT *); + +struct nvbios_pmuE { + u8 type; + u32 data; +}; + +u32 nvbios_pmuEe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr); +u32 nvbios_pmuEp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, + struct nvbios_pmuE *); + +struct nvbios_pmuR { + u32 boot_addr_pmu; + u32 boot_addr; + u32 boot_size; + u32 code_addr_pmu; + u32 code_addr; + u32 code_size; + u32 init_addr_pmu; + + u32 data_addr_pmu; + u32 data_addr; + u32 data_size; + u32 args_addr_pmu; +}; + +bool nvbios_pmuRm(struct nvkm_bios *, u8 type, struct nvbios_pmuR *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h new file mode 100644 index 000000000000..420426793880 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h @@ -0,0 +1,141 @@ +#ifndef __NVBIOS_RAMCFG_H__ +#define __NVBIOS_RAMCFG_H__ +struct nvbios_ramcfg { + unsigned rammap_ver; + unsigned rammap_hdr; + unsigned rammap_min; + unsigned rammap_max; + union { + struct { + unsigned rammap_10_04_02:1; + unsigned rammap_10_04_08:1; + }; + struct { + unsigned rammap_11_08_01:1; + unsigned rammap_11_08_0c:2; + unsigned rammap_11_08_10:1; + unsigned rammap_11_09_01ff:9; + unsigned rammap_11_0a_03fe:9; + unsigned rammap_11_0a_0400:1; + unsigned rammap_11_0a_0800:1; + unsigned rammap_11_0b_01f0:5; + unsigned rammap_11_0b_0200:1; + unsigned rammap_11_0b_0400:1; + unsigned rammap_11_0b_0800:1; + unsigned rammap_11_0d:8; + unsigned rammap_11_0e:8; + unsigned rammap_11_0f:8; + unsigned rammap_11_11_0c:2; + }; + }; + + unsigned ramcfg_ver; + unsigned ramcfg_hdr; + unsigned ramcfg_timing; + union { + struct { + unsigned ramcfg_10_02_01:1; + unsigned ramcfg_10_02_02:1; + unsigned ramcfg_10_02_04:1; + unsigned ramcfg_10_02_08:1; + unsigned ramcfg_10_02_10:1; + unsigned ramcfg_10_02_20:1; + unsigned ramcfg_10_DLLoff:1; + unsigned ramcfg_10_03_0f:4; + unsigned ramcfg_10_04_01:1; + unsigned ramcfg_10_05:8; + unsigned ramcfg_10_06:8; + unsigned ramcfg_10_07:8; + unsigned ramcfg_10_08:8; + unsigned ramcfg_10_09_0f:4; + unsigned ramcfg_10_09_f0:4; + }; + struct { + unsigned ramcfg_11_01_01:1; + unsigned ramcfg_11_01_02:1; + unsigned ramcfg_11_01_04:1; + unsigned ramcfg_11_01_08:1; + unsigned ramcfg_11_01_10:1; + unsigned ramcfg_11_01_20:1; + unsigned ramcfg_11_01_40:1; + unsigned ramcfg_11_01_80:1; + unsigned ramcfg_11_02_03:2; + unsigned ramcfg_11_02_04:1; + unsigned ramcfg_11_02_08:1; + unsigned ramcfg_11_02_10:1; + unsigned ramcfg_11_02_40:1; + unsigned ramcfg_11_02_80:1; + unsigned ramcfg_11_03_0f:4; + unsigned ramcfg_11_03_30:2; + unsigned ramcfg_11_03_c0:2; + unsigned ramcfg_11_03_f0:4; + unsigned ramcfg_11_04:8; + unsigned ramcfg_11_06:8; + unsigned ramcfg_11_07_02:1; + unsigned ramcfg_11_07_04:1; + unsigned ramcfg_11_07_08:1; + unsigned ramcfg_11_07_10:1; + unsigned ramcfg_11_07_40:1; + unsigned ramcfg_11_07_80:1; + unsigned ramcfg_11_08_01:1; + unsigned ramcfg_11_08_02:1; + unsigned ramcfg_11_08_04:1; + unsigned ramcfg_11_08_08:1; + unsigned ramcfg_11_08_10:1; + unsigned ramcfg_11_08_20:1; + unsigned ramcfg_11_09:8; + }; + }; + + unsigned timing_ver; + unsigned timing_hdr; + unsigned timing[11]; + union { + struct { + unsigned timing_10_WR:8; + unsigned timing_10_WTR:8; + unsigned timing_10_CL:8; + unsigned timing_10_RC:8; + /*empty: 4 */ + unsigned timing_10_RFC:8; /* Byte 5 */ + /*empty: 6 */ + unsigned timing_10_RAS:8; /* Byte 7 */ + /*empty: 8 */ + unsigned timing_10_RP:8; /* Byte 9 */ + unsigned timing_10_RCDRD:8; + unsigned timing_10_RCDWR:8; + unsigned timing_10_RRD:8; + unsigned timing_10_13:8; + unsigned timing_10_ODT:3; + /* empty: 15 */ + unsigned timing_10_16:8; + /* empty: 17 */ + unsigned timing_10_18:8; + unsigned timing_10_CWL:8; + unsigned timing_10_20:8; + unsigned timing_10_21:8; + /* empty: 22, 23 */ + unsigned timing_10_24:8; + }; + struct { + unsigned timing_20_2e_03:2; + unsigned timing_20_2e_30:2; + unsigned timing_20_2e_c0:2; + unsigned timing_20_2f_03:2; + unsigned timing_20_2c_003f:6; + unsigned timing_20_2c_1fc0:7; + unsigned timing_20_30_f8:5; + unsigned timing_20_30_07:3; + unsigned timing_20_31_0007:3; + unsigned timing_20_31_0078:4; + unsigned timing_20_31_0780:4; + unsigned timing_20_31_0800:1; + unsigned timing_20_31_7000:3; + unsigned timing_20_31_8000:1; + }; + }; +}; + +u8 nvbios_ramcfg_count(struct nvkm_bios *); +u8 nvbios_ramcfg_index(struct nvkm_subdev *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h new file mode 100644 index 000000000000..609a905ec780 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h @@ -0,0 +1,21 @@ +#ifndef __NVBIOS_RAMMAP_H__ +#define __NVBIOS_RAMMAP_H__ +#include <subdev/bios/ramcfg.h> + +u32 nvbios_rammapTe(struct nvkm_bios *, u8 *ver, u8 *hdr, + u8 *cnt, u8 *len, u8 *snr, u8 *ssz); + +u32 nvbios_rammapEe(struct nvkm_bios *, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u32 nvbios_rammapEp(struct nvkm_bios *, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *); +u32 nvbios_rammapEm(struct nvkm_bios *, u16 mhz, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *); + +u32 nvbios_rammapSe(struct nvkm_bios *, u32 data, + u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, + u8 *ver, u8 *hdr); +u32 nvbios_rammapSp(struct nvkm_bios *, u32 data, + u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, + u8 *ver, u8 *hdr, struct nvbios_ramcfg *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/therm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/therm.h new file mode 100644 index 000000000000..dd3ba960e75d --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/therm.h @@ -0,0 +1,72 @@ +#ifndef __NVBIOS_THERM_H__ +#define __NVBIOS_THERM_H__ +struct nvbios_therm_threshold { + u8 temp; + u8 hysteresis; +}; + +struct nvbios_therm_sensor { + /* diode */ + s16 slope_mult; + s16 slope_div; + s16 offset_num; + s16 offset_den; + s8 offset_constant; + + /* thresholds */ + struct nvbios_therm_threshold thrs_fan_boost; + struct nvbios_therm_threshold thrs_down_clock; + struct nvbios_therm_threshold thrs_critical; + struct nvbios_therm_threshold thrs_shutdown; +}; + +enum nvbios_therm_fan_type { + NVBIOS_THERM_FAN_UNK = 0, + NVBIOS_THERM_FAN_TOGGLE = 1, + NVBIOS_THERM_FAN_PWM = 2, +}; + +/* no vbios have more than 6 */ +#define NVKM_TEMP_FAN_TRIP_MAX 10 +struct nvbios_therm_trip_point { + int fan_duty; + int temp; + int hysteresis; +}; + +enum nvbios_therm_fan_mode { + NVBIOS_THERM_FAN_TRIP = 0, + NVBIOS_THERM_FAN_LINEAR = 1, + NVBIOS_THERM_FAN_OTHER = 2, +}; + +struct nvbios_therm_fan { + enum nvbios_therm_fan_type type; + + u32 pwm_freq; + + u8 min_duty; + u8 max_duty; + + u16 bump_period; + u16 slow_down_period; + + enum nvbios_therm_fan_mode fan_mode; + struct nvbios_therm_trip_point trip[NVKM_TEMP_FAN_TRIP_MAX]; + u8 nr_fan_trip; + u8 linear_min_temp; + u8 linear_max_temp; +}; + +enum nvbios_therm_domain { + NVBIOS_THERM_DOMAIN_CORE, + NVBIOS_THERM_DOMAIN_AMBIENT, +}; + +int +nvbios_therm_sensor_parse(struct nvkm_bios *, enum nvbios_therm_domain, + struct nvbios_therm_sensor *); + +int +nvbios_therm_fan_parse(struct nvkm_bios *, struct nvbios_therm_fan *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h new file mode 100644 index 000000000000..339a826aa176 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h @@ -0,0 +1,11 @@ +#ifndef __NVBIOS_TIMING_H__ +#define __NVBIOS_TIMING_H__ +#include <subdev/bios/ramcfg.h> + +u16 nvbios_timingTe(struct nvkm_bios *, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz); +u16 nvbios_timingEe(struct nvkm_bios *, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u16 nvbios_timingEp(struct nvkm_bios *, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h new file mode 100644 index 000000000000..6633c6db9281 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h @@ -0,0 +1,21 @@ +#ifndef __NVBIOS_VMAP_H__ +#define __NVBIOS_VMAP_H__ +struct nvbios_vmap { +}; + +u16 nvbios_vmap_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u16 nvbios_vmap_parse(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, + struct nvbios_vmap *); + +struct nvbios_vmap_entry { + u8 unk0; + u8 link; + u32 min; + u32 max; + s32 arg[6]; +}; + +u16 nvbios_vmap_entry(struct nvkm_bios *, int idx, u8 *ver, u8 *len); +u16 nvbios_vmap_entry_parse(struct nvkm_bios *, int idx, u8 *ver, u8 *len, + struct nvbios_vmap_entry *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h new file mode 100644 index 000000000000..eb2de4b85bbd --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h @@ -0,0 +1,23 @@ +#ifndef __NVBIOS_VOLT_H__ +#define __NVBIOS_VOLT_H__ +struct nvbios_volt { + u8 vidmask; + u32 min; + u32 max; + u32 base; + s16 step; +}; + +u16 nvbios_volt_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u16 nvbios_volt_parse(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, + struct nvbios_volt *); + +struct nvbios_volt_entry { + u32 voltage; + u8 vid; +}; + +u16 nvbios_volt_entry(struct nvkm_bios *, int idx, u8 *ver, u8 *len); +u16 nvbios_volt_entry_parse(struct nvkm_bios *, int idx, u8 *ver, u8 *len, + struct nvbios_volt_entry *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/xpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/xpio.h new file mode 100644 index 000000000000..0c0fe234ff12 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/xpio.h @@ -0,0 +1,18 @@ +#ifndef __NVBIOS_XPIO_H__ +#define __NVBIOS_XPIO_H__ + +#define NVBIOS_XPIO_FLAG_AUX 0x10 +#define NVBIOS_XPIO_FLAG_AUX0 0x00 +#define NVBIOS_XPIO_FLAG_AUX1 0x10 + +struct nvbios_xpio { + u8 type; + u8 addr; + u8 flags; +}; + +u16 dcb_xpio_table(struct nvkm_bios *, u8 idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u16 dcb_xpio_parse(struct nvkm_bios *, u8 idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_xpio *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h new file mode 100644 index 000000000000..fba83c04849e --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h @@ -0,0 +1,50 @@ +#ifndef __NVKM_BUS_H__ +#define __NVKM_BUS_H__ +#include <core/subdev.h> + +struct nvkm_bus_intr { + u32 stat; + u32 unit; +}; + +struct nvkm_bus { + struct nvkm_subdev base; + int (*hwsq_exec)(struct nvkm_bus *, u32 *, u32); + u32 hwsq_size; +}; + +static inline struct nvkm_bus * +nvkm_bus(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_BUS); +} + +#define nvkm_bus_create(p, e, o, d) \ + nvkm_subdev_create_((p), (e), (o), 0, "PBUS", "master", \ + sizeof(**d), (void **)d) +#define nvkm_bus_destroy(p) \ + nvkm_subdev_destroy(&(p)->base) +#define nvkm_bus_init(p) \ + nvkm_subdev_init(&(p)->base) +#define nvkm_bus_fini(p, s) \ + nvkm_subdev_fini(&(p)->base, (s)) + +#define _nvkm_bus_dtor _nvkm_subdev_dtor +#define _nvkm_bus_init _nvkm_subdev_init +#define _nvkm_bus_fini _nvkm_subdev_fini + +extern struct nvkm_oclass *nv04_bus_oclass; +extern struct nvkm_oclass *nv31_bus_oclass; +extern struct nvkm_oclass *nv50_bus_oclass; +extern struct nvkm_oclass *g94_bus_oclass; +extern struct nvkm_oclass *gf100_bus_oclass; + +/* interface to sequencer */ +struct nvkm_hwsq; +int nvkm_hwsq_init(struct nvkm_bus *, struct nvkm_hwsq **); +int nvkm_hwsq_fini(struct nvkm_hwsq **, bool exec); +void nvkm_hwsq_wr32(struct nvkm_hwsq *, u32 addr, u32 data); +void nvkm_hwsq_setf(struct nvkm_hwsq *, u8 flag, int data); +void nvkm_hwsq_wait(struct nvkm_hwsq *, u8 flag, u8 data); +void nvkm_hwsq_nsec(struct nvkm_hwsq *, u32 nsec); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h new file mode 100644 index 000000000000..f5d303850d8c --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h @@ -0,0 +1,161 @@ +#ifndef __NVKM_CLK_H__ +#define __NVKM_CLK_H__ +#include <core/subdev.h> +#include <core/notify.h> +struct nvbios_pll; +struct nvkm_pll_vals; + +enum nv_clk_src { + nv_clk_src_crystal, + nv_clk_src_href, + + nv_clk_src_hclk, + nv_clk_src_hclkm3, + nv_clk_src_hclkm3d2, + nv_clk_src_hclkm2d3, /* NVAA */ + nv_clk_src_hclkm4, /* NVAA */ + nv_clk_src_cclk, /* NVAA */ + + nv_clk_src_host, + + nv_clk_src_sppll0, + nv_clk_src_sppll1, + + nv_clk_src_mpllsrcref, + nv_clk_src_mpllsrc, + nv_clk_src_mpll, + nv_clk_src_mdiv, + + nv_clk_src_core, + nv_clk_src_core_intm, + nv_clk_src_shader, + + nv_clk_src_mem, + + nv_clk_src_gpc, + nv_clk_src_rop, + nv_clk_src_hubk01, + nv_clk_src_hubk06, + nv_clk_src_hubk07, + nv_clk_src_copy, + nv_clk_src_daemon, + nv_clk_src_disp, + nv_clk_src_vdec, + + nv_clk_src_dom6, + + nv_clk_src_max, +}; + +struct nvkm_cstate { + struct list_head head; + u8 voltage; + u32 domain[nv_clk_src_max]; +}; + +struct nvkm_pstate { + struct list_head head; + struct list_head list; /* c-states */ + struct nvkm_cstate base; + u8 pstate; + u8 fanspeed; +}; + +struct nvkm_domain { + enum nv_clk_src name; + u8 bios; /* 0xff for none */ +#define NVKM_CLK_DOM_FLAG_CORE 0x01 + u8 flags; + const char *mname; + int mdiv; +}; + +struct nvkm_clk { + struct nvkm_subdev base; + + struct nvkm_domain *domains; + struct nvkm_pstate bstate; + + struct list_head states; + int state_nr; + + struct work_struct work; + wait_queue_head_t wait; + atomic_t waiting; + + struct nvkm_notify pwrsrc_ntfy; + int pwrsrc; + int pstate; /* current */ + int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */ + int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */ + int astate; /* perfmon adjustment (base) */ + int tstate; /* thermal adjustment (max-) */ + int dstate; /* display adjustment (min+) */ + + bool allow_reclock; + + int (*read)(struct nvkm_clk *, enum nv_clk_src); + int (*calc)(struct nvkm_clk *, struct nvkm_cstate *); + int (*prog)(struct nvkm_clk *); + void (*tidy)(struct nvkm_clk *); + + /*XXX: die, these are here *only* to support the completely + * bat-shit insane what-was-nvkm_hw.c code + */ + int (*pll_calc)(struct nvkm_clk *, struct nvbios_pll *, int clk, + struct nvkm_pll_vals *pv); + int (*pll_prog)(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *pv); +}; + +static inline struct nvkm_clk * +nvkm_clk(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_CLK); +} + +#define nvkm_clk_create(p,e,o,i,r,s,n,d) \ + nvkm_clk_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d), \ + (void **)d) +#define nvkm_clk_destroy(p) ({ \ + struct nvkm_clk *clk = (p); \ + _nvkm_clk_dtor(nv_object(clk)); \ +}) +#define nvkm_clk_init(p) ({ \ + struct nvkm_clk *clk = (p); \ + _nvkm_clk_init(nv_object(clk)); \ +}) +#define nvkm_clk_fini(p,s) ({ \ + struct nvkm_clk *clk = (p); \ + _nvkm_clk_fini(nv_object(clk), (s)); \ +}) + +int nvkm_clk_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, + struct nvkm_domain *, struct nvkm_pstate *, + int, bool, int, void **); +void _nvkm_clk_dtor(struct nvkm_object *); +int _nvkm_clk_init(struct nvkm_object *); +int _nvkm_clk_fini(struct nvkm_object *, bool); + +extern struct nvkm_oclass nv04_clk_oclass; +extern struct nvkm_oclass nv40_clk_oclass; +extern struct nvkm_oclass *nv50_clk_oclass; +extern struct nvkm_oclass *g84_clk_oclass; +extern struct nvkm_oclass *mcp77_clk_oclass; +extern struct nvkm_oclass gt215_clk_oclass; +extern struct nvkm_oclass gf100_clk_oclass; +extern struct nvkm_oclass gk104_clk_oclass; +extern struct nvkm_oclass gk20a_clk_oclass; + +int nv04_clk_pll_set(struct nvkm_clk *, u32 type, u32 freq); +int nv04_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *, int clk, + struct nvkm_pll_vals *); +int nv04_clk_pll_prog(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *); +int gt215_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *, + int clk, struct nvkm_pll_vals *); + +int nvkm_clk_ustate(struct nvkm_clk *, int req, int pwr); +int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait); +int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel); +int nvkm_clk_tstate(struct nvkm_clk *, int req, int rel); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h new file mode 100644 index 000000000000..d1bbe0d62b35 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h @@ -0,0 +1,32 @@ +#ifndef __NVKM_DEVINIT_H__ +#define __NVKM_DEVINIT_H__ +#include <core/subdev.h> + +struct nvkm_devinit { + struct nvkm_subdev base; + bool post; + void (*meminit)(struct nvkm_devinit *); + int (*pll_set)(struct nvkm_devinit *, u32 type, u32 freq); + u32 (*mmio)(struct nvkm_devinit *, u32 addr); +}; + +static inline struct nvkm_devinit * +nvkm_devinit(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_DEVINIT); +} + +extern struct nvkm_oclass *nv04_devinit_oclass; +extern struct nvkm_oclass *nv05_devinit_oclass; +extern struct nvkm_oclass *nv10_devinit_oclass; +extern struct nvkm_oclass *nv1a_devinit_oclass; +extern struct nvkm_oclass *nv20_devinit_oclass; +extern struct nvkm_oclass *nv50_devinit_oclass; +extern struct nvkm_oclass *g84_devinit_oclass; +extern struct nvkm_oclass *g98_devinit_oclass; +extern struct nvkm_oclass *gt215_devinit_oclass; +extern struct nvkm_oclass *mcp89_devinit_oclass; +extern struct nvkm_oclass *gf100_devinit_oclass; +extern struct nvkm_oclass *gm107_devinit_oclass; +extern struct nvkm_oclass *gm204_devinit_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h new file mode 100644 index 000000000000..16da56cf43b0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h @@ -0,0 +1,154 @@ +#ifndef __NVKM_FB_H__ +#define __NVKM_FB_H__ +#include <core/subdev.h> + +#include <subdev/mmu.h> + +/* memory type/access flags, do not match hardware values */ +#define NV_MEM_ACCESS_RO 1 +#define NV_MEM_ACCESS_WO 2 +#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) +#define NV_MEM_ACCESS_SYS 4 +#define NV_MEM_ACCESS_VM 8 +#define NV_MEM_ACCESS_NOSNOOP 16 + +#define NV_MEM_TARGET_VRAM 0 +#define NV_MEM_TARGET_PCI 1 +#define NV_MEM_TARGET_PCI_NOSNOOP 2 +#define NV_MEM_TARGET_VM 3 +#define NV_MEM_TARGET_GART 4 + +#define NV_MEM_TYPE_VM 0x7f +#define NV_MEM_COMP_VM 0x03 + +struct nvkm_mem { + struct drm_device *dev; + + struct nvkm_vma bar_vma; + struct nvkm_vma vma[2]; + u8 page_shift; + + struct nvkm_mm_node *tag; + struct list_head regions; + dma_addr_t *pages; + u32 memtype; + u64 offset; + u64 size; + struct sg_table *sg; +}; + +struct nvkm_fb_tile { + struct nvkm_mm_node *tag; + u32 addr; + u32 limit; + u32 pitch; + u32 zcomp; +}; + +struct nvkm_fb { + struct nvkm_subdev base; + + bool (*memtype_valid)(struct nvkm_fb *, u32 memtype); + + struct nvkm_ram *ram; + + struct nvkm_mm vram; + struct nvkm_mm tags; + + struct { + struct nvkm_fb_tile region[16]; + int regions; + void (*init)(struct nvkm_fb *, int i, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); + void (*comp)(struct nvkm_fb *, int i, u32 size, u32 flags, + struct nvkm_fb_tile *); + void (*fini)(struct nvkm_fb *, int i, struct nvkm_fb_tile *); + void (*prog)(struct nvkm_fb *, int i, struct nvkm_fb_tile *); + } tile; +}; + +static inline struct nvkm_fb * +nvkm_fb(void *obj) +{ + /* fbram uses this before device subdev pointer is valid */ + if (nv_iclass(obj, NV_SUBDEV_CLASS) && + nv_subidx(obj) == NVDEV_SUBDEV_FB) + return obj; + + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_FB); +} + +extern struct nvkm_oclass *nv04_fb_oclass; +extern struct nvkm_oclass *nv10_fb_oclass; +extern struct nvkm_oclass *nv1a_fb_oclass; +extern struct nvkm_oclass *nv20_fb_oclass; +extern struct nvkm_oclass *nv25_fb_oclass; +extern struct nvkm_oclass *nv30_fb_oclass; +extern struct nvkm_oclass *nv35_fb_oclass; +extern struct nvkm_oclass *nv36_fb_oclass; +extern struct nvkm_oclass *nv40_fb_oclass; +extern struct nvkm_oclass *nv41_fb_oclass; +extern struct nvkm_oclass *nv44_fb_oclass; +extern struct nvkm_oclass *nv46_fb_oclass; +extern struct nvkm_oclass *nv47_fb_oclass; +extern struct nvkm_oclass *nv49_fb_oclass; +extern struct nvkm_oclass *nv4e_fb_oclass; +extern struct nvkm_oclass *nv50_fb_oclass; +extern struct nvkm_oclass *g84_fb_oclass; +extern struct nvkm_oclass *gt215_fb_oclass; +extern struct nvkm_oclass *mcp77_fb_oclass; +extern struct nvkm_oclass *mcp89_fb_oclass; +extern struct nvkm_oclass *gf100_fb_oclass; +extern struct nvkm_oclass *gk104_fb_oclass; +extern struct nvkm_oclass *gk20a_fb_oclass; +extern struct nvkm_oclass *gm107_fb_oclass; + +#include <subdev/bios.h> +#include <subdev/bios/ramcfg.h> + +struct nvkm_ram_data { + struct list_head head; + struct nvbios_ramcfg bios; + u32 freq; +}; + +struct nvkm_ram { + struct nvkm_object base; + enum { + NV_MEM_TYPE_UNKNOWN = 0, + NV_MEM_TYPE_STOLEN, + NV_MEM_TYPE_SGRAM, + NV_MEM_TYPE_SDRAM, + NV_MEM_TYPE_DDR1, + NV_MEM_TYPE_DDR2, + NV_MEM_TYPE_DDR3, + NV_MEM_TYPE_GDDR2, + NV_MEM_TYPE_GDDR3, + NV_MEM_TYPE_GDDR4, + NV_MEM_TYPE_GDDR5 + } type; + u64 stolen; + u64 size; + u32 tags; + + int ranks; + int parts; + int part_mask; + + int (*get)(struct nvkm_fb *, u64 size, u32 align, u32 size_nc, + u32 type, struct nvkm_mem **); + void (*put)(struct nvkm_fb *, struct nvkm_mem **); + + int (*calc)(struct nvkm_fb *, u32 freq); + int (*prog)(struct nvkm_fb *); + void (*tidy)(struct nvkm_fb *); + u32 freq; + u32 mr[16]; + u32 mr1_nuts; + + struct nvkm_ram_data *next; + struct nvkm_ram_data former; + struct nvkm_ram_data xition; + struct nvkm_ram_data target; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h new file mode 100644 index 000000000000..a1384786adc9 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h @@ -0,0 +1,28 @@ +#ifndef __NVKM_FUSE_H__ +#define __NVKM_FUSE_H__ +#include <core/subdev.h> +#include <core/device.h> + +struct nvkm_fuse { + struct nvkm_subdev base; +}; + +static inline struct nvkm_fuse * +nvkm_fuse(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_FUSE); +} + +#define nvkm_fuse_create(p, e, o, d) \ + nvkm_fuse_create_((p), (e), (o), sizeof(**d), (void **)d) + +int nvkm_fuse_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +void _nvkm_fuse_dtor(struct nvkm_object *); +int _nvkm_fuse_init(struct nvkm_object *); +#define _nvkm_fuse_fini _nvkm_subdev_fini + +extern struct nvkm_oclass nv50_fuse_oclass; +extern struct nvkm_oclass gf100_fuse_oclass; +extern struct nvkm_oclass gm107_fuse_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h new file mode 100644 index 000000000000..ca5099a81b5a --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h @@ -0,0 +1,44 @@ +#ifndef __NVKM_GPIO_H__ +#define __NVKM_GPIO_H__ +#include <core/subdev.h> +#include <core/event.h> + +#include <subdev/bios.h> +#include <subdev/bios/gpio.h> + +struct nvkm_gpio_ntfy_req { +#define NVKM_GPIO_HI 0x01 +#define NVKM_GPIO_LO 0x02 +#define NVKM_GPIO_TOGGLED 0x03 + u8 mask; + u8 line; +}; + +struct nvkm_gpio_ntfy_rep { + u8 mask; +}; + +struct nvkm_gpio { + struct nvkm_subdev base; + + struct nvkm_event event; + + void (*reset)(struct nvkm_gpio *, u8 func); + int (*find)(struct nvkm_gpio *, int idx, u8 tag, u8 line, + struct dcb_gpio_func *); + int (*set)(struct nvkm_gpio *, int idx, u8 tag, u8 line, int state); + int (*get)(struct nvkm_gpio *, int idx, u8 tag, u8 line); +}; + +static inline struct nvkm_gpio * +nvkm_gpio(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_GPIO); +} + +extern struct nvkm_oclass *nv10_gpio_oclass; +extern struct nvkm_oclass *nv50_gpio_oclass; +extern struct nvkm_oclass *g94_gpio_oclass; +extern struct nvkm_oclass *gf110_gpio_oclass; +extern struct nvkm_oclass *gk104_gpio_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h new file mode 100644 index 000000000000..a2e33730f05e --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h @@ -0,0 +1,135 @@ +#ifndef __NVKM_I2C_H__ +#define __NVKM_I2C_H__ +#include <core/subdev.h> +#include <core/event.h> + +#include <subdev/bios.h> +#include <subdev/bios/i2c.h> + +#define NV_I2C_PORT(n) (0x00 + (n)) +#define NV_I2C_AUX(n) (0x10 + (n)) +#define NV_I2C_EXT(n) (0x20 + (n)) +#define NV_I2C_DEFAULT(n) (0x80 + (n)) + +#define NV_I2C_TYPE_DCBI2C(n) (0x0000 | (n)) +#define NV_I2C_TYPE_EXTDDC(e) (0x0005 | (e) << 8) +#define NV_I2C_TYPE_EXTAUX(e) (0x0006 | (e) << 8) + +struct nvkm_i2c_ntfy_req { +#define NVKM_I2C_PLUG 0x01 +#define NVKM_I2C_UNPLUG 0x02 +#define NVKM_I2C_IRQ 0x04 +#define NVKM_I2C_DONE 0x08 +#define NVKM_I2C_ANY 0x0f + u8 mask; + u8 port; +}; + +struct nvkm_i2c_ntfy_rep { + u8 mask; +}; + +struct nvkm_i2c_port { + struct nvkm_object base; + struct i2c_adapter adapter; + struct mutex mutex; + + struct list_head head; + u8 index; + int aux; + + const struct nvkm_i2c_func *func; +}; + +struct nvkm_i2c_func { + void (*drive_scl)(struct nvkm_i2c_port *, int); + void (*drive_sda)(struct nvkm_i2c_port *, int); + int (*sense_scl)(struct nvkm_i2c_port *); + int (*sense_sda)(struct nvkm_i2c_port *); + + int (*aux)(struct nvkm_i2c_port *, bool, u8, u32, u8 *, u8); + int (*pattern)(struct nvkm_i2c_port *, int pattern); + int (*lnk_ctl)(struct nvkm_i2c_port *, int nr, int bw, bool enh); + int (*drv_ctl)(struct nvkm_i2c_port *, int lane, int sw, int pe); +}; + +struct nvkm_i2c_board_info { + struct i2c_board_info dev; + u8 udelay; /* set to 0 to use the standard delay */ +}; + +struct nvkm_i2c { + struct nvkm_subdev base; + struct nvkm_event event; + + struct nvkm_i2c_port *(*find)(struct nvkm_i2c *, u8 index); + struct nvkm_i2c_port *(*find_type)(struct nvkm_i2c *, u16 type); + int (*acquire_pad)(struct nvkm_i2c_port *, unsigned long timeout); + void (*release_pad)(struct nvkm_i2c_port *); + int (*acquire)(struct nvkm_i2c_port *, unsigned long timeout); + void (*release)(struct nvkm_i2c_port *); + int (*identify)(struct nvkm_i2c *, int index, + const char *what, struct nvkm_i2c_board_info *, + bool (*match)(struct nvkm_i2c_port *, + struct i2c_board_info *, void *), + void *); + + wait_queue_head_t wait; + struct list_head ports; +}; + +static inline struct nvkm_i2c * +nvkm_i2c(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_I2C); +} + +extern struct nvkm_oclass *nv04_i2c_oclass; +extern struct nvkm_oclass *nv4e_i2c_oclass; +extern struct nvkm_oclass *nv50_i2c_oclass; +extern struct nvkm_oclass *g94_i2c_oclass; +extern struct nvkm_oclass *gf110_i2c_oclass; +extern struct nvkm_oclass *gf117_i2c_oclass; +extern struct nvkm_oclass *gk104_i2c_oclass; +extern struct nvkm_oclass *gm204_i2c_oclass; + +static inline int +nv_rdi2cr(struct nvkm_i2c_port *port, u8 addr, u8 reg) +{ + u8 val; + struct i2c_msg msgs[] = { + { .addr = addr, .flags = 0, .len = 1, .buf = ® }, + { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = &val }, + }; + + int ret = i2c_transfer(&port->adapter, msgs, 2); + if (ret != 2) + return -EIO; + + return val; +} + +static inline int +nv_wri2cr(struct nvkm_i2c_port *port, u8 addr, u8 reg, u8 val) +{ + u8 buf[2] = { reg, val }; + struct i2c_msg msgs[] = { + { .addr = addr, .flags = 0, .len = 2, .buf = buf }, + }; + + int ret = i2c_transfer(&port->adapter, msgs, 1); + if (ret != 1) + return -EIO; + + return 0; +} + +static inline bool +nv_probe_i2c(struct nvkm_i2c_port *port, u8 addr) +{ + return nv_rdi2cr(port, addr, 0) >= 0; +} + +int nv_rdaux(struct nvkm_i2c_port *, u32 addr, u8 *data, u8 size); +int nv_wraux(struct nvkm_i2c_port *, u32 addr, u8 *data, u8 size); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h new file mode 100644 index 000000000000..2150d8af0040 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h @@ -0,0 +1,32 @@ +#ifndef __NVKM_IBUS_H__ +#define __NVKM_IBUS_H__ +#include <core/subdev.h> + +struct nvkm_ibus { + struct nvkm_subdev base; +}; + +static inline struct nvkm_ibus * +nvkm_ibus(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_IBUS); +} + +#define nvkm_ibus_create(p,e,o,d) \ + nvkm_subdev_create_((p), (e), (o), 0, "PIBUS", "ibus", \ + sizeof(**d), (void **)d) +#define nvkm_ibus_destroy(p) \ + nvkm_subdev_destroy(&(p)->base) +#define nvkm_ibus_init(p) \ + nvkm_subdev_init(&(p)->base) +#define nvkm_ibus_fini(p,s) \ + nvkm_subdev_fini(&(p)->base, (s)) + +#define _nvkm_ibus_dtor _nvkm_subdev_dtor +#define _nvkm_ibus_init _nvkm_subdev_init +#define _nvkm_ibus_fini _nvkm_subdev_fini + +extern struct nvkm_oclass gf100_ibus_oclass; +extern struct nvkm_oclass gk104_ibus_oclass; +extern struct nvkm_oclass gk20a_ibus_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h new file mode 100644 index 000000000000..d104c1aac807 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h @@ -0,0 +1,48 @@ +#ifndef __NVKM_INSTMEM_H__ +#define __NVKM_INSTMEM_H__ +#include <core/subdev.h> + +struct nvkm_instobj { + struct nvkm_object base; + struct list_head head; + u32 *suspend; + u64 addr; + u32 size; +}; + +static inline struct nvkm_instobj * +nv_memobj(void *obj) +{ +#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA + if (unlikely(!nv_iclass(obj, NV_MEMOBJ_CLASS))) + nv_assert("BAD CAST -> NvMemObj, %08x", nv_hclass(obj)); +#endif + return obj; +} + +struct nvkm_instmem { + struct nvkm_subdev base; + struct list_head list; + + u32 reserved; + int (*alloc)(struct nvkm_instmem *, struct nvkm_object *, + u32 size, u32 align, struct nvkm_object **); +}; + +static inline struct nvkm_instmem * +nvkm_instmem(void *obj) +{ + /* nv04/nv40 impls need to create objects in their constructor, + * which is before the subdev pointer is valid + */ + if (nv_iclass(obj, NV_SUBDEV_CLASS) && + nv_subidx(obj) == NVDEV_SUBDEV_INSTMEM) + return obj; + + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_INSTMEM); +} + +extern struct nvkm_oclass *nv04_instmem_oclass; +extern struct nvkm_oclass *nv40_instmem_oclass; +extern struct nvkm_oclass *nv50_instmem_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h new file mode 100644 index 000000000000..cd5d29fc0565 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h @@ -0,0 +1,31 @@ +#ifndef __NVKM_LTC_H__ +#define __NVKM_LTC_H__ +#include <core/subdev.h> +struct nvkm_mm_node; + +#define NVKM_LTC_MAX_ZBC_CNT 16 + +struct nvkm_ltc { + struct nvkm_subdev base; + + int (*tags_alloc)(struct nvkm_ltc *, u32 count, + struct nvkm_mm_node **); + void (*tags_free)(struct nvkm_ltc *, struct nvkm_mm_node **); + void (*tags_clear)(struct nvkm_ltc *, u32 first, u32 count); + + int zbc_min; + int zbc_max; + int (*zbc_color_get)(struct nvkm_ltc *, int index, const u32[4]); + int (*zbc_depth_get)(struct nvkm_ltc *, int index, const u32); +}; + +static inline struct nvkm_ltc * +nvkm_ltc(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_LTC); +} + +extern struct nvkm_oclass *gf100_ltc_oclass; +extern struct nvkm_oclass *gk104_ltc_oclass; +extern struct nvkm_oclass *gm107_ltc_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h new file mode 100644 index 000000000000..055bea7702a1 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h @@ -0,0 +1,28 @@ +#ifndef __NVKM_MC_H__ +#define __NVKM_MC_H__ +#include <core/subdev.h> + +struct nvkm_mc { + struct nvkm_subdev base; + bool use_msi; + unsigned int irq; + void (*unk260)(struct nvkm_mc *, u32); +}; + +static inline struct nvkm_mc * +nvkm_mc(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MC); +} + +extern struct nvkm_oclass *nv04_mc_oclass; +extern struct nvkm_oclass *nv40_mc_oclass; +extern struct nvkm_oclass *nv44_mc_oclass; +extern struct nvkm_oclass *nv4c_mc_oclass; +extern struct nvkm_oclass *nv50_mc_oclass; +extern struct nvkm_oclass *g94_mc_oclass; +extern struct nvkm_oclass *g98_mc_oclass; +extern struct nvkm_oclass *gf100_mc_oclass; +extern struct nvkm_oclass *gf106_mc_oclass; +extern struct nvkm_oclass *gk20a_mc_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h new file mode 100644 index 000000000000..3a5368776c31 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h @@ -0,0 +1,104 @@ +#ifndef __NVKM_MMU_H__ +#define __NVKM_MMU_H__ +#include <core/subdev.h> +#include <core/mm.h> +struct nvkm_device; +struct nvkm_mem; + +struct nvkm_vm_pgt { + struct nvkm_gpuobj *obj[2]; + u32 refcount[2]; +}; + +struct nvkm_vm_pgd { + struct list_head head; + struct nvkm_gpuobj *obj; +}; + +struct nvkm_vma { + struct list_head head; + int refcount; + struct nvkm_vm *vm; + struct nvkm_mm_node *node; + u64 offset; + u32 access; +}; + +struct nvkm_vm { + struct nvkm_mmu *mmu; + struct nvkm_mm mm; + struct kref refcount; + + struct list_head pgd_list; + atomic_t engref[NVDEV_SUBDEV_NR]; + + struct nvkm_vm_pgt *pgt; + u32 fpde; + u32 lpde; +}; + +struct nvkm_mmu { + struct nvkm_subdev base; + + u64 limit; + u8 dma_bits; + u32 pgt_bits; + u8 spg_shift; + u8 lpg_shift; + + int (*create)(struct nvkm_mmu *, u64 offset, u64 length, + u64 mm_offset, struct nvkm_vm **); + + void (*map_pgt)(struct nvkm_gpuobj *pgd, u32 pde, + struct nvkm_gpuobj *pgt[2]); + void (*map)(struct nvkm_vma *, struct nvkm_gpuobj *, + struct nvkm_mem *, u32 pte, u32 cnt, + u64 phys, u64 delta); + void (*map_sg)(struct nvkm_vma *, struct nvkm_gpuobj *, + struct nvkm_mem *, u32 pte, u32 cnt, dma_addr_t *); + void (*unmap)(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt); + void (*flush)(struct nvkm_vm *); +}; + +static inline struct nvkm_mmu * +nvkm_mmu(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MMU); +} + +#define nvkm_mmu_create(p,e,o,i,f,d) \ + nvkm_subdev_create((p), (e), (o), 0, (i), (f), (d)) +#define nvkm_mmu_destroy(p) \ + nvkm_subdev_destroy(&(p)->base) +#define nvkm_mmu_init(p) \ + nvkm_subdev_init(&(p)->base) +#define nvkm_mmu_fini(p,s) \ + nvkm_subdev_fini(&(p)->base, (s)) + +#define _nvkm_mmu_dtor _nvkm_subdev_dtor +#define _nvkm_mmu_init _nvkm_subdev_init +#define _nvkm_mmu_fini _nvkm_subdev_fini + +extern struct nvkm_oclass nv04_mmu_oclass; +extern struct nvkm_oclass nv41_mmu_oclass; +extern struct nvkm_oclass nv44_mmu_oclass; +extern struct nvkm_oclass nv50_mmu_oclass; +extern struct nvkm_oclass gf100_mmu_oclass; + +int nv04_vm_create(struct nvkm_mmu *, u64, u64, u64, + struct nvkm_vm **); +void nv04_mmu_dtor(struct nvkm_object *); + +int nvkm_vm_create(struct nvkm_mmu *, u64 offset, u64 length, u64 mm_offset, + u32 block, struct nvkm_vm **); +int nvkm_vm_new(struct nvkm_device *, u64 offset, u64 length, u64 mm_offset, + struct nvkm_vm **); +int nvkm_vm_ref(struct nvkm_vm *, struct nvkm_vm **, struct nvkm_gpuobj *pgd); +int nvkm_vm_get(struct nvkm_vm *, u64 size, u32 page_shift, u32 access, + struct nvkm_vma *); +void nvkm_vm_put(struct nvkm_vma *); +void nvkm_vm_map(struct nvkm_vma *, struct nvkm_mem *); +void nvkm_vm_map_at(struct nvkm_vma *, u64 offset, struct nvkm_mem *); +void nvkm_vm_unmap(struct nvkm_vma *); +void nvkm_vm_unmap_at(struct nvkm_vma *, u64 offset, u64 length); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h new file mode 100644 index 000000000000..fba613477b1a --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h @@ -0,0 +1,34 @@ +#ifndef __NVKM_MXM_H__ +#define __NVKM_MXM_H__ +#include <core/subdev.h> + +#define MXM_SANITISE_DCB 0x00000001 + +struct nvkm_mxm { + struct nvkm_subdev base; + u32 action; + u8 *mxms; +}; + +static inline struct nvkm_mxm * +nvkm_mxm(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MXM); +} + +#define nvkm_mxm_create(p,e,o,d) \ + nvkm_mxm_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nvkm_mxm_init(p) \ + nvkm_subdev_init(&(p)->base) +#define nvkm_mxm_fini(p,s) \ + nvkm_subdev_fini(&(p)->base, (s)) +int nvkm_mxm_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +void nvkm_mxm_destroy(struct nvkm_mxm *); + +#define _nvkm_mxm_dtor _nvkm_subdev_dtor +#define _nvkm_mxm_init _nvkm_subdev_init +#define _nvkm_mxm_fini _nvkm_subdev_fini + +extern struct nvkm_oclass nv50_mxm_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h new file mode 100644 index 000000000000..7b86acc634a0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h @@ -0,0 +1,53 @@ +#ifndef __NVKM_PMU_H__ +#define __NVKM_PMU_H__ +#include <core/subdev.h> + +struct nvkm_pmu { + struct nvkm_subdev base; + + struct { + u32 base; + u32 size; + } send; + + struct { + u32 base; + u32 size; + + struct work_struct work; + wait_queue_head_t wait; + u32 process; + u32 message; + u32 data[2]; + } recv; + + int (*message)(struct nvkm_pmu *, u32[2], u32, u32, u32, u32); + void (*pgob)(struct nvkm_pmu *, bool); +}; + +static inline struct nvkm_pmu * +nvkm_pmu(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_PMU); +} + +extern struct nvkm_oclass *gt215_pmu_oclass; +extern struct nvkm_oclass *gf100_pmu_oclass; +extern struct nvkm_oclass *gf110_pmu_oclass; +extern struct nvkm_oclass *gk104_pmu_oclass; +extern struct nvkm_oclass *gk208_pmu_oclass; +extern struct nvkm_oclass *gk20a_pmu_oclass; + +/* interface to MEMX process running on PMU */ +struct nvkm_memx; +int nvkm_memx_init(struct nvkm_pmu *, struct nvkm_memx **); +int nvkm_memx_fini(struct nvkm_memx **, bool exec); +void nvkm_memx_wr32(struct nvkm_memx *, u32 addr, u32 data); +void nvkm_memx_wait(struct nvkm_memx *, u32 addr, u32 mask, u32 data, u32 nsec); +void nvkm_memx_nsec(struct nvkm_memx *, u32 nsec); +void nvkm_memx_wait_vblank(struct nvkm_memx *); +void nvkm_memx_train(struct nvkm_memx *); +int nvkm_memx_train_result(struct nvkm_pmu *, u32 *, int); +void nvkm_memx_block(struct nvkm_memx *); +void nvkm_memx_unblock(struct nvkm_memx *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h new file mode 100644 index 000000000000..6662829b6db1 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h @@ -0,0 +1,79 @@ +#ifndef __NVKM_THERM_H__ +#define __NVKM_THERM_H__ +#include <core/subdev.h> + +enum nvkm_therm_fan_mode { + NVKM_THERM_CTRL_NONE = 0, + NVKM_THERM_CTRL_MANUAL = 1, + NVKM_THERM_CTRL_AUTO = 2, +}; + +enum nvkm_therm_attr_type { + NVKM_THERM_ATTR_FAN_MIN_DUTY = 0, + NVKM_THERM_ATTR_FAN_MAX_DUTY = 1, + NVKM_THERM_ATTR_FAN_MODE = 2, + + NVKM_THERM_ATTR_THRS_FAN_BOOST = 10, + NVKM_THERM_ATTR_THRS_FAN_BOOST_HYST = 11, + NVKM_THERM_ATTR_THRS_DOWN_CLK = 12, + NVKM_THERM_ATTR_THRS_DOWN_CLK_HYST = 13, + NVKM_THERM_ATTR_THRS_CRITICAL = 14, + NVKM_THERM_ATTR_THRS_CRITICAL_HYST = 15, + NVKM_THERM_ATTR_THRS_SHUTDOWN = 16, + NVKM_THERM_ATTR_THRS_SHUTDOWN_HYST = 17, +}; + +struct nvkm_therm { + struct nvkm_subdev base; + + int (*pwm_ctrl)(struct nvkm_therm *, int line, bool); + int (*pwm_get)(struct nvkm_therm *, int line, u32 *, u32 *); + int (*pwm_set)(struct nvkm_therm *, int line, u32, u32); + int (*pwm_clock)(struct nvkm_therm *, int line); + + int (*fan_get)(struct nvkm_therm *); + int (*fan_set)(struct nvkm_therm *, int); + int (*fan_sense)(struct nvkm_therm *); + + int (*temp_get)(struct nvkm_therm *); + + int (*attr_get)(struct nvkm_therm *, enum nvkm_therm_attr_type); + int (*attr_set)(struct nvkm_therm *, enum nvkm_therm_attr_type, int); +}; + +static inline struct nvkm_therm * +nvkm_therm(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_THERM); +} + +#define nvkm_therm_create(p,e,o,d) \ + nvkm_therm_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nvkm_therm_destroy(p) ({ \ + struct nvkm_therm *therm = (p); \ + _nvkm_therm_dtor(nv_object(therm)); \ +}) +#define nvkm_therm_init(p) ({ \ + struct nvkm_therm *therm = (p); \ + _nvkm_therm_init(nv_object(therm)); \ +}) +#define nvkm_therm_fini(p,s) ({ \ + struct nvkm_therm *therm = (p); \ + _nvkm_therm_init(nv_object(therm), (s)); \ +}) + +int nvkm_therm_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +void _nvkm_therm_dtor(struct nvkm_object *); +int _nvkm_therm_init(struct nvkm_object *); +int _nvkm_therm_fini(struct nvkm_object *, bool); + +int nvkm_therm_cstate(struct nvkm_therm *, int, int); + +extern struct nvkm_oclass nv40_therm_oclass; +extern struct nvkm_oclass nv50_therm_oclass; +extern struct nvkm_oclass g84_therm_oclass; +extern struct nvkm_oclass gt215_therm_oclass; +extern struct nvkm_oclass gf110_therm_oclass; +extern struct nvkm_oclass gm107_therm_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h new file mode 100644 index 000000000000..4ad55082ef7a --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h @@ -0,0 +1,61 @@ +#ifndef __NVKM_TIMER_H__ +#define __NVKM_TIMER_H__ +#include <core/subdev.h> + +struct nvkm_alarm { + struct list_head head; + u64 timestamp; + void (*func)(struct nvkm_alarm *); +}; + +static inline void +nvkm_alarm_init(struct nvkm_alarm *alarm, + void (*func)(struct nvkm_alarm *)) +{ + INIT_LIST_HEAD(&alarm->head); + alarm->func = func; +} + +bool nvkm_timer_wait_eq(void *, u64 nsec, u32 addr, u32 mask, u32 data); +bool nvkm_timer_wait_ne(void *, u64 nsec, u32 addr, u32 mask, u32 data); +bool nvkm_timer_wait_cb(void *, u64 nsec, bool (*func)(void *), void *data); +void nvkm_timer_alarm(void *, u32 nsec, struct nvkm_alarm *); +void nvkm_timer_alarm_cancel(void *, struct nvkm_alarm *); + +#define NV_WAIT_DEFAULT 2000000000ULL +#define nv_wait(o,a,m,v) \ + nvkm_timer_wait_eq((o), NV_WAIT_DEFAULT, (a), (m), (v)) +#define nv_wait_ne(o,a,m,v) \ + nvkm_timer_wait_ne((o), NV_WAIT_DEFAULT, (a), (m), (v)) +#define nv_wait_cb(o,c,d) \ + nvkm_timer_wait_cb((o), NV_WAIT_DEFAULT, (c), (d)) + +struct nvkm_timer { + struct nvkm_subdev base; + u64 (*read)(struct nvkm_timer *); + void (*alarm)(struct nvkm_timer *, u64 time, struct nvkm_alarm *); + void (*alarm_cancel)(struct nvkm_timer *, struct nvkm_alarm *); +}; + +static inline struct nvkm_timer * +nvkm_timer(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_TIMER); +} + +#define nvkm_timer_create(p,e,o,d) \ + nvkm_subdev_create_((p), (e), (o), 0, "PTIMER", "timer", \ + sizeof(**d), (void **)d) +#define nvkm_timer_destroy(p) \ + nvkm_subdev_destroy(&(p)->base) +#define nvkm_timer_init(p) \ + nvkm_subdev_init(&(p)->base) +#define nvkm_timer_fini(p,s) \ + nvkm_subdev_fini(&(p)->base, (s)) + +int nvkm_timer_create_(struct nvkm_object *, struct nvkm_engine *, + struct nvkm_oclass *, int size, void **); + +extern struct nvkm_oclass nv04_timer_oclass; +extern struct nvkm_oclass gk20a_timer_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h new file mode 100644 index 000000000000..fee09ad818e4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h @@ -0,0 +1,30 @@ +#ifndef __NOUVEAU_VGA_H__ +#define __NOUVEAU_VGA_H__ + +#include <core/os.h> + +/* access to various legacy io ports */ +u8 nv_rdport(void *obj, int head, u16 port); +void nv_wrport(void *obj, int head, u16 port, u8 value); + +/* VGA Sequencer */ +u8 nv_rdvgas(void *obj, int head, u8 index); +void nv_wrvgas(void *obj, int head, u8 index, u8 value); + +/* VGA Graphics */ +u8 nv_rdvgag(void *obj, int head, u8 index); +void nv_wrvgag(void *obj, int head, u8 index, u8 value); + +/* VGA CRTC */ +u8 nv_rdvgac(void *obj, int head, u8 index); +void nv_wrvgac(void *obj, int head, u8 index, u8 value); + +/* VGA indexed port access dispatcher */ +u8 nv_rdvgai(void *obj, int head, u16 port, u8 index); +void nv_wrvgai(void *obj, int head, u16 port, u8 index, u8 value); + +bool nv_lockvgac(void *obj, bool lock); +u8 nv_rdvgaowner(void *obj); +void nv_wrvgaowner(void *obj, u8); + +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h new file mode 100644 index 000000000000..e3d7243fbb1d --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h @@ -0,0 +1,58 @@ +#ifndef __NVKM_VOLT_H__ +#define __NVKM_VOLT_H__ +#include <core/subdev.h> + +struct nvkm_voltage { + u32 uv; + u8 id; +}; + +struct nvkm_volt { + struct nvkm_subdev base; + + int (*vid_get)(struct nvkm_volt *); + int (*get)(struct nvkm_volt *); + int (*vid_set)(struct nvkm_volt *, u8 vid); + int (*set)(struct nvkm_volt *, u32 uv); + int (*set_id)(struct nvkm_volt *, u8 id, int condition); + + u8 vid_mask; + u8 vid_nr; + struct { + u32 uv; + u8 vid; + } vid[256]; +}; + +static inline struct nvkm_volt * +nvkm_volt(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_VOLT); +} + +#define nvkm_volt_create(p, e, o, d) \ + nvkm_volt_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nvkm_volt_destroy(p) ({ \ + struct nvkm_volt *v = (p); \ + _nvkm_volt_dtor(nv_object(v)); \ +}) +#define nvkm_volt_init(p) ({ \ + struct nvkm_volt *v = (p); \ + _nvkm_volt_init(nv_object(v)); \ +}) +#define nvkm_volt_fini(p,s) \ + nvkm_subdev_fini((p), (s)) + +int nvkm_volt_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +void _nvkm_volt_dtor(struct nvkm_object *); +int _nvkm_volt_init(struct nvkm_object *); +#define _nvkm_volt_fini _nvkm_subdev_fini + +extern struct nvkm_oclass nv40_volt_oclass; +extern struct nvkm_oclass gk20a_volt_oclass; + +int nvkm_voltgpio_init(struct nvkm_volt *); +int nvkm_voltgpio_get(struct nvkm_volt *); +int nvkm_voltgpio_set(struct nvkm_volt *, u8); +#endif |