diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 90 |
1 files changed, 60 insertions, 30 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index afccf9721cf0..1053fe796466 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -149,16 +149,41 @@ gk104_fifo_uevent_init(struct nvkm_fifo *fifo) } void -gk104_fifo_runlist_commit(struct gk104_fifo *fifo, int runl) +gk104_fifo_runlist_commit(struct gk104_fifo *fifo, int runl, + struct nvkm_memory *mem, int nr) +{ + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + int target; + + switch (nvkm_memory_target(mem)) { + case NVKM_MEM_TARGET_VRAM: target = 0; break; + case NVKM_MEM_TARGET_NCOH: target = 3; break; + default: + WARN_ON(1); + return; + } + + nvkm_wr32(device, 0x002270, (nvkm_memory_addr(mem) >> 12) | + (target << 28)); + nvkm_wr32(device, 0x002274, (runl << 20) | nr); + + if (nvkm_msec(device, 2000, + if (!(nvkm_rd32(device, 0x002284 + (runl * 0x08)) & 0x00100000)) + break; + ) < 0) + nvkm_error(subdev, "runlist %d update timeout\n", runl); +} + +void +gk104_fifo_runlist_update(struct gk104_fifo *fifo, int runl) { const struct gk104_fifo_runlist_func *func = fifo->func->runlist; struct gk104_fifo_chan *chan; struct nvkm_subdev *subdev = &fifo->base.engine.subdev; - struct nvkm_device *device = subdev->device; struct nvkm_memory *mem; struct nvkm_fifo_cgrp *cgrp; int nr = 0; - int target; mutex_lock(&subdev->mutex); mem = fifo->runlist[runl].mem[fifo->runlist[runl].next]; @@ -177,24 +202,7 @@ gk104_fifo_runlist_commit(struct gk104_fifo *fifo, int runl) } nvkm_done(mem); - switch (nvkm_memory_target(mem)) { - case NVKM_MEM_TARGET_VRAM: target = 0; break; - case NVKM_MEM_TARGET_NCOH: target = 3; break; - default: - WARN_ON(1); - goto unlock; - } - - nvkm_wr32(device, 0x002270, (nvkm_memory_addr(mem) >> 12) | - (target << 28)); - nvkm_wr32(device, 0x002274, (runl << 20) | nr); - - if (nvkm_msec(device, 2000, - if (!(nvkm_rd32(device, 0x002284 + (runl * 0x08)) & 0x00100000)) - break; - ) < 0) - nvkm_error(subdev, "runlist %d update timeout\n", runl); -unlock: + func->commit(fifo, runl, mem, nr); mutex_unlock(&subdev->mutex); } @@ -238,6 +246,29 @@ const struct gk104_fifo_runlist_func gk104_fifo_runlist = { .size = 8, .chan = gk104_fifo_runlist_chan, + .commit = gk104_fifo_runlist_commit, +}; + +void +gk104_fifo_pbdma_init(struct gk104_fifo *fifo) +{ + struct nvkm_device *device = fifo->base.engine.subdev.device; + nvkm_wr32(device, 0x000204, (1 << fifo->pbdma_nr) - 1); +} + +int +gk104_fifo_pbdma_nr(struct gk104_fifo *fifo) +{ + struct nvkm_device *device = fifo->base.engine.subdev.device; + /* Determine number of PBDMAs by checking valid enable bits. */ + nvkm_wr32(device, 0x000204, 0xffffffff); + return hweight32(nvkm_rd32(device, 0x000204)); +} + +const struct gk104_fifo_pbdma_func +gk104_fifo_pbdma = { + .nr = gk104_fifo_pbdma_nr, + .init = gk104_fifo_pbdma_init, }; static void @@ -267,7 +298,7 @@ gk104_fifo_recover_work(struct work_struct *w) } for (todo = runm; runl = __ffs(todo), todo; todo &= ~BIT(runl)) - gk104_fifo_runlist_commit(fifo, runl); + gk104_fifo_runlist_update(fifo, runl); nvkm_wr32(device, 0x00262c, runm); nvkm_mask(device, 0x002630, runm, 0x00000000); @@ -456,10 +487,10 @@ gk104_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) if (ee && ee->data2) { switch (ee->data2) { case NVKM_SUBDEV_BAR: - nvkm_mask(device, 0x001704, 0x00000000, 0x00000000); + nvkm_bar_bar1_reset(device); break; case NVKM_SUBDEV_INSTMEM: - nvkm_mask(device, 0x001714, 0x00000000, 0x00000000); + nvkm_bar_bar2_reset(device); break; case NVKM_ENGINE_IFB: nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); @@ -904,9 +935,7 @@ gk104_fifo_oneinit(struct nvkm_fifo *base) enum nvkm_devidx engidx; u32 *map; - /* Determine number of PBDMAs by checking valid enable bits. */ - nvkm_wr32(device, 0x000204, 0xffffffff); - fifo->pbdma_nr = hweight32(nvkm_rd32(device, 0x000204)); + fifo->pbdma_nr = fifo->func->pbdma->nr(fifo); nvkm_debug(subdev, "%d PBDMA(s)\n", fifo->pbdma_nr); /* Read PBDMA->runlist(s) mapping from HW. */ @@ -978,7 +1007,7 @@ gk104_fifo_init(struct nvkm_fifo *base) int i; /* Enable PBDMAs. */ - nvkm_wr32(device, 0x000204, (1 << fifo->pbdma_nr) - 1); + fifo->func->pbdma->init(fifo); /* PBDMA[n] */ for (i = 0; i < fifo->pbdma_nr; i++) { @@ -995,8 +1024,8 @@ gk104_fifo_init(struct nvkm_fifo *base) nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar->addr >> 12); - if (fifo->func->init_pbdma_timeout) - fifo->func->init_pbdma_timeout(fifo); + if (fifo->func->pbdma->init_timeout) + fifo->func->pbdma->init_timeout(fifo); nvkm_wr32(device, 0x002100, 0xffffffff); nvkm_wr32(device, 0x002140, 0x7fffffff); @@ -1175,6 +1204,7 @@ gk104_fifo_fault_gpcclient[] = { static const struct gk104_fifo_func gk104_fifo = { + .pbdma = &gk104_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gk104_fifo_fault_engine, .fault.reason = gk104_fifo_fault_reason, |