diff options
Diffstat (limited to '')
| -rw-r--r-- | drivers/gpu/drm/panel/panel-sitronix-st7701.c | 547 |
1 files changed, 462 insertions, 85 deletions
diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c b/drivers/gpu/drm/panel/panel-sitronix-st7701.c index 320a2a8fd459..c481daa4bbce 100644 --- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c @@ -8,6 +8,7 @@ #include <drm/drm_modes.h> #include <drm/drm_panel.h> +#include <linux/bitfield.h> #include <linux/gpio/consumer.h> #include <linux/delay.h> #include <linux/module.h> @@ -41,59 +42,101 @@ /* * Command2 with BK function selection. * - * BIT[4, 0]: [CN2, BKXSEL] - * 10 = CMD2BK0, Command2 BK0 - * 11 = CMD2BK1, Command2 BK1 - * 00 = Command2 disable + * BIT[4].....CN2 + * BIT[1:0]...BKXSEL + * 1:00 = CMD2BK0, Command2 BK0 + * 1:01 = CMD2BK1, Command2 BK1 + * 1:11 = CMD2BK3, Command2 BK3 + * 0:00 = Command2 disable */ -#define DSI_CMD2BK1_SEL 0x11 #define DSI_CMD2BK0_SEL 0x10 +#define DSI_CMD2BK1_SEL 0x11 +#define DSI_CMD2BK3_SEL 0x13 #define DSI_CMD2BKX_SEL_NONE 0x00 /* Command2, BK0 bytes */ -#define DSI_LINESET_LINE 0x69 -#define DSI_LINESET_LDE_EN BIT(7) -#define DSI_LINESET_LINEDELTA GENMASK(1, 0) -#define DSI_CMD2_BK0_LNESET_B1 DSI_LINESET_LINEDELTA -#define DSI_CMD2_BK0_LNESET_B0 (DSI_LINESET_LDE_EN | DSI_LINESET_LINE) -#define DSI_INVSEL_DEFAULT GENMASK(5, 4) -#define DSI_INVSEL_NLINV GENMASK(2, 0) -#define DSI_INVSEL_RTNI GENMASK(2, 1) -#define DSI_CMD2_BK0_INVSEL_B1 DSI_INVSEL_RTNI -#define DSI_CMD2_BK0_INVSEL_B0 (DSI_INVSEL_DEFAULT | DSI_INVSEL_NLINV) -#define DSI_CMD2_BK0_PORCTRL_B0(m) ((m)->vtotal - (m)->vsync_end) -#define DSI_CMD2_BK0_PORCTRL_B1(m) ((m)->vsync_start - (m)->vdisplay) +#define DSI_CMD2_BK0_GAMCTRL_AJ_MASK GENMASK(7, 6) +#define DSI_CMD2_BK0_GAMCTRL_VC0_MASK GENMASK(3, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC4_MASK GENMASK(5, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC8_MASK GENMASK(5, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC16_MASK GENMASK(4, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC24_MASK GENMASK(4, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC52_MASK GENMASK(3, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC80_MASK GENMASK(5, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC108_MASK GENMASK(3, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC147_MASK GENMASK(3, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC175_MASK GENMASK(5, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC203_MASK GENMASK(3, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC231_MASK GENMASK(4, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC239_MASK GENMASK(4, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC247_MASK GENMASK(5, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC251_MASK GENMASK(5, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC255_MASK GENMASK(4, 0) +#define DSI_CMD2_BK0_LNESET_LINE_MASK GENMASK(6, 0) +#define DSI_CMD2_BK0_LNESET_LDE_EN BIT(7) +#define DSI_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0) +#define DSI_CMD2_BK0_PORCTRL_VBP_MASK GENMASK(7, 0) +#define DSI_CMD2_BK0_PORCTRL_VFP_MASK GENMASK(7, 0) +#define DSI_CMD2_BK0_INVSEL_ONES_MASK GENMASK(5, 4) +#define DSI_CMD2_BK0_INVSEL_NLINV_MASK GENMASK(2, 0) +#define DSI_CMD2_BK0_INVSEL_RTNI_MASK GENMASK(4, 0) /* Command2, BK1 bytes */ -#define DSI_CMD2_BK1_VRHA_SET 0x45 -#define DSI_CMD2_BK1_VCOM_SET 0x13 -#define DSI_CMD2_BK1_VGHSS_SET GENMASK(2, 0) +#define DSI_CMD2_BK1_VRHA_MASK GENMASK(7, 0) +#define DSI_CMD2_BK1_VCOM_MASK GENMASK(7, 0) +#define DSI_CMD2_BK1_VGHSS_MASK GENMASK(3, 0) #define DSI_CMD2_BK1_TESTCMD_VAL BIT(7) -#define DSI_VGLS_DEFAULT BIT(6) -#define DSI_VGLS_SEL GENMASK(2, 0) -#define DSI_CMD2_BK1_VGLS_SET (DSI_VGLS_DEFAULT | DSI_VGLS_SEL) -#define DSI_PWCTLR1_AP BIT(7) /* Gamma OP bias, max */ -#define DSI_PWCTLR1_APIS BIT(2) /* Source OP input bias, min */ -#define DSI_PWCTLR1_APOS BIT(0) /* Source OP output bias, min */ -#define DSI_CMD2_BK1_PWCTLR1_SET (DSI_PWCTLR1_AP | DSI_PWCTLR1_APIS | \ - DSI_PWCTLR1_APOS) -#define DSI_PWCTLR2_AVDD BIT(5) /* AVDD 6.6v */ -#define DSI_PWCTLR2_AVCL 0x0 /* AVCL -4.4v */ -#define DSI_CMD2_BK1_PWCTLR2_SET (DSI_PWCTLR2_AVDD | DSI_PWCTLR2_AVCL) -#define DSI_SPD1_T2D BIT(3) -#define DSI_CMD2_BK1_SPD1_SET (GENMASK(6, 4) | DSI_SPD1_T2D) -#define DSI_CMD2_BK1_SPD2_SET DSI_CMD2_BK1_SPD1_SET -#define DSI_MIPISET1_EOT_EN BIT(3) -#define DSI_CMD2_BK1_MIPISET1_SET (BIT(7) | DSI_MIPISET1_EOT_EN) +#define DSI_CMD2_BK1_VGLS_ONES BIT(6) +#define DSI_CMD2_BK1_VGLS_MASK GENMASK(3, 0) +#define DSI_CMD2_BK1_PWRCTRL1_AP_MASK GENMASK(7, 6) +#define DSI_CMD2_BK1_PWRCTRL1_APIS_MASK GENMASK(3, 2) +#define DSI_CMD2_BK1_PWRCTRL1_APOS_MASK GENMASK(1, 0) +#define DSI_CMD2_BK1_PWRCTRL2_AVDD_MASK GENMASK(5, 4) +#define DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK GENMASK(1, 0) +#define DSI_CMD2_BK1_SPD1_ONES_MASK GENMASK(6, 4) +#define DSI_CMD2_BK1_SPD1_T2D_MASK GENMASK(3, 0) +#define DSI_CMD2_BK1_SPD2_ONES_MASK GENMASK(6, 4) +#define DSI_CMD2_BK1_SPD2_T3D_MASK GENMASK(3, 0) +#define DSI_CMD2_BK1_MIPISET1_ONES BIT(7) +#define DSI_CMD2_BK1_MIPISET1_EOT_EN BIT(3) + +#define CFIELD_PREP(_mask, _val) \ + (((typeof(_mask))(_val) << (__builtin_ffsll(_mask) - 1)) & (_mask)) + +enum op_bias { + OP_BIAS_OFF = 0, + OP_BIAS_MIN, + OP_BIAS_MIDDLE, + OP_BIAS_MAX +}; + +struct st7701; struct st7701_panel_desc { const struct drm_display_mode *mode; unsigned int lanes; - unsigned long flags; enum mipi_dsi_pixel_format format; - const char *const *supply_names; - unsigned int num_supplies; unsigned int panel_sleep_delay; + + /* TFT matrix driver configuration, panel specific. */ + const u8 pv_gamma[16]; /* Positive voltage gamma control */ + const u8 nv_gamma[16]; /* Negative voltage gamma control */ + const u8 nlinv; /* Inversion selection */ + const u32 vop_uv; /* Vop in uV */ + const u32 vcom_uv; /* Vcom in uV */ + const u16 vgh_mv; /* Vgh in mV */ + const s16 vgl_mv; /* Vgl in mV */ + const u16 avdd_mv; /* Avdd in mV */ + const s16 avcl_mv; /* Avcl in mV */ + const enum op_bias gamma_op_bias; + const enum op_bias input_op_bias; + const enum op_bias output_op_bias; + const u16 t2d_ns; /* T2D in ns */ + const u16 t3d_ns; /* T3D in ns */ + const bool eot_en; + + /* GIP sequence, fully custom and undocumented. */ + void (*gip_sequence)(struct st7701 *st7701); }; struct st7701 { @@ -101,7 +144,7 @@ struct st7701 { struct mipi_dsi_device *dsi; const struct st7701_panel_desc *desc; - struct regulator_bulk_data *supplies; + struct regulator_bulk_data supplies[2]; struct gpio_desc *reset; unsigned int sleep_delay; }; @@ -123,9 +166,37 @@ static inline int st7701_dsi_write(struct st7701 *st7701, const void *seq, st7701_dsi_write(st7701, d, ARRAY_SIZE(d)); \ } +static u8 st7701_vgls_map(struct st7701 *st7701) +{ + const struct st7701_panel_desc *desc = st7701->desc; + struct { + s32 vgl; + u8 val; + } map[16] = { + { -7060, 0x0 }, { -7470, 0x1 }, + { -7910, 0x2 }, { -8140, 0x3 }, + { -8650, 0x4 }, { -8920, 0x5 }, + { -9210, 0x6 }, { -9510, 0x7 }, + { -9830, 0x8 }, { -10170, 0x9 }, + { -10530, 0xa }, { -10910, 0xb }, + { -11310, 0xc }, { -11730, 0xd }, + { -12200, 0xe }, { -12690, 0xf } + }; + int i; + + for (i = 0; i < ARRAY_SIZE(map); i++) + if (desc->vgl_mv == map[i].vgl) + return map[i].val; + + return 0; +} + static void st7701_init_sequence(struct st7701 *st7701) { - const struct drm_display_mode *mode = st7701->desc->mode; + const struct st7701_panel_desc *desc = st7701->desc; + const struct drm_display_mode *mode = desc->mode; + const u8 linecount8 = mode->vdisplay / 8; + const u8 linecountrem2 = (mode->vdisplay % 8) / 2; ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00); @@ -139,34 +210,105 @@ static void st7701_init_sequence(struct st7701 *st7701) /* Command2, BK0 */ ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK0_SEL); - ST7701_DSI(st7701, DSI_CMD2_BK0_PVGAMCTRL, 0x00, 0x0E, 0x15, 0x0F, - 0x11, 0x08, 0x08, 0x08, 0x08, 0x23, 0x04, 0x13, 0x12, - 0x2B, 0x34, 0x1F); - ST7701_DSI(st7701, DSI_CMD2_BK0_NVGAMCTRL, 0x00, 0x0E, 0x95, 0x0F, - 0x13, 0x07, 0x09, 0x08, 0x08, 0x22, 0x04, 0x10, 0x0E, - 0x2C, 0x34, 0x1F); + mipi_dsi_dcs_write(st7701->dsi, DSI_CMD2_BK0_PVGAMCTRL, + desc->pv_gamma, ARRAY_SIZE(desc->pv_gamma)); + mipi_dsi_dcs_write(st7701->dsi, DSI_CMD2_BK0_NVGAMCTRL, + desc->nv_gamma, ARRAY_SIZE(desc->nv_gamma)); + /* + * Vertical line count configuration: + * Line[6:0]: select number of vertical lines of the TFT matrix in + * multiples of 8 lines + * LDE_EN: enable sub-8-line granularity line count + * Line_delta[1:0]: add 0/2/4/6 extra lines to line count selected + * using Line[6:0] + * + * Total number of vertical lines: + * LN = ((Line[6:0] + 1) * 8) + (LDE_EN ? Line_delta[1:0] * 2 : 0) + */ ST7701_DSI(st7701, DSI_CMD2_BK0_LNESET, - DSI_CMD2_BK0_LNESET_B0, DSI_CMD2_BK0_LNESET_B1); + FIELD_PREP(DSI_CMD2_BK0_LNESET_LINE_MASK, linecount8 - 1) | + (linecountrem2 ? DSI_CMD2_BK0_LNESET_LDE_EN : 0), + FIELD_PREP(DSI_CMD2_BK0_LNESET_LINEDELTA, linecountrem2)); ST7701_DSI(st7701, DSI_CMD2_BK0_PORCTRL, - DSI_CMD2_BK0_PORCTRL_B0(mode), - DSI_CMD2_BK0_PORCTRL_B1(mode)); + FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VBP_MASK, + mode->vtotal - mode->vsync_end), + FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VFP_MASK, + mode->vsync_start - mode->vdisplay)); + /* + * Horizontal pixel count configuration: + * PCLK = 512 + (RTNI[4:0] * 16) + * The PCLK is number of pixel clock per line, which matches + * mode htotal. The minimum is 512 PCLK. + */ ST7701_DSI(st7701, DSI_CMD2_BK0_INVSEL, - DSI_CMD2_BK0_INVSEL_B0, DSI_CMD2_BK0_INVSEL_B1); + DSI_CMD2_BK0_INVSEL_ONES_MASK | + FIELD_PREP(DSI_CMD2_BK0_INVSEL_NLINV_MASK, desc->nlinv), + FIELD_PREP(DSI_CMD2_BK0_INVSEL_RTNI_MASK, + DIV_ROUND_UP(mode->htotal, 16))); /* Command2, BK1 */ ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK1_SEL); - ST7701_DSI(st7701, DSI_CMD2_BK1_VRHS, DSI_CMD2_BK1_VRHA_SET); - ST7701_DSI(st7701, DSI_CMD2_BK1_VCOM, DSI_CMD2_BK1_VCOM_SET); - ST7701_DSI(st7701, DSI_CMD2_BK1_VGHSS, DSI_CMD2_BK1_VGHSS_SET); + + /* Vop = 3.5375V + (VRHA[7:0] * 0.0125V) */ + ST7701_DSI(st7701, DSI_CMD2_BK1_VRHS, + FIELD_PREP(DSI_CMD2_BK1_VRHA_MASK, + DIV_ROUND_CLOSEST(desc->vop_uv - 3537500, 12500))); + + /* Vcom = 0.1V + (VCOM[7:0] * 0.0125V) */ + ST7701_DSI(st7701, DSI_CMD2_BK1_VCOM, + FIELD_PREP(DSI_CMD2_BK1_VCOM_MASK, + DIV_ROUND_CLOSEST(desc->vcom_uv - 100000, 12500))); + + /* Vgh = 11.5V + (VGHSS[7:0] * 0.5V) */ + ST7701_DSI(st7701, DSI_CMD2_BK1_VGHSS, + FIELD_PREP(DSI_CMD2_BK1_VGHSS_MASK, + DIV_ROUND_CLOSEST(clamp(desc->vgh_mv, + (u16)11500, + (u16)17000) - 11500, + 500))); + ST7701_DSI(st7701, DSI_CMD2_BK1_TESTCMD, DSI_CMD2_BK1_TESTCMD_VAL); - ST7701_DSI(st7701, DSI_CMD2_BK1_VGLS, DSI_CMD2_BK1_VGLS_SET); - ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR1, DSI_CMD2_BK1_PWCTLR1_SET); - ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR2, DSI_CMD2_BK1_PWCTLR2_SET); - ST7701_DSI(st7701, DSI_CMD2_BK1_SPD1, DSI_CMD2_BK1_SPD1_SET); - ST7701_DSI(st7701, DSI_CMD2_BK1_SPD2, DSI_CMD2_BK1_SPD2_SET); - ST7701_DSI(st7701, DSI_CMD2_BK1_MIPISET1, DSI_CMD2_BK1_MIPISET1_SET); + /* Vgl is non-linear */ + ST7701_DSI(st7701, DSI_CMD2_BK1_VGLS, + DSI_CMD2_BK1_VGLS_ONES | + FIELD_PREP(DSI_CMD2_BK1_VGLS_MASK, st7701_vgls_map(st7701))); + + ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR1, + FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_AP_MASK, + desc->gamma_op_bias) | + FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_APIS_MASK, + desc->input_op_bias) | + FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_APOS_MASK, + desc->output_op_bias)); + + /* Avdd = 6.2V + (AVDD[1:0] * 0.2V) , Avcl = -4.4V - (AVCL[1:0] * 0.2V) */ + ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR2, + FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVDD_MASK, + DIV_ROUND_CLOSEST(desc->avdd_mv - 6200, 200)) | + FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK, + DIV_ROUND_CLOSEST(-4400 + desc->avcl_mv, 200))); + + /* T2D = 0.2us * T2D[3:0] */ + ST7701_DSI(st7701, DSI_CMD2_BK1_SPD1, + DSI_CMD2_BK1_SPD1_ONES_MASK | + FIELD_PREP(DSI_CMD2_BK1_SPD1_T2D_MASK, + DIV_ROUND_CLOSEST(desc->t2d_ns, 200))); + + /* T3D = 4us + (0.8us * T3D[3:0]) */ + ST7701_DSI(st7701, DSI_CMD2_BK1_SPD2, + DSI_CMD2_BK1_SPD2_ONES_MASK | + FIELD_PREP(DSI_CMD2_BK1_SPD2_T3D_MASK, + DIV_ROUND_CLOSEST(desc->t3d_ns - 4000, 800))); + + ST7701_DSI(st7701, DSI_CMD2_BK1_MIPISET1, + DSI_CMD2_BK1_MIPISET1_ONES | + (desc->eot_en ? DSI_CMD2_BK1_MIPISET1_EOT_EN : 0)); +} + +static void ts8550b_gip_sequence(struct st7701 *st7701) +{ /** * ST7701_SPEC_V1.2 is unable to provide enough information above this * specific command sequence, so grab the same from vendor BSP driver. @@ -188,10 +330,78 @@ static void st7701_init_sequence(struct st7701 *st7701) ST7701_DSI(st7701, 0xEC, 0x00, 0x00); ST7701_DSI(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF); +} + +static void dmt028vghmcmi_1a_gip_sequence(struct st7701 *st7701) +{ + ST7701_DSI(st7701, 0xEE, 0x42); + ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02); + + ST7701_DSI(st7701, 0xE1, + 0x04, 0xA0, 0x06, 0xA0, + 0x05, 0xA0, 0x07, 0xA0, + 0x00, 0x44, 0x44); + ST7701_DSI(st7701, 0xE2, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00); + ST7701_DSI(st7701, 0xE3, + 0x00, 0x00, 0x22, 0x22); + ST7701_DSI(st7701, 0xE4, 0x44, 0x44); + ST7701_DSI(st7701, 0xE5, + 0x0C, 0x90, 0xA0, 0xA0, + 0x0E, 0x92, 0xA0, 0xA0, + 0x08, 0x8C, 0xA0, 0xA0, + 0x0A, 0x8E, 0xA0, 0xA0); + ST7701_DSI(st7701, 0xE6, + 0x00, 0x00, 0x22, 0x22); + ST7701_DSI(st7701, 0xE7, 0x44, 0x44); + ST7701_DSI(st7701, 0xE8, + 0x0D, 0x91, 0xA0, 0xA0, + 0x0F, 0x93, 0xA0, 0xA0, + 0x09, 0x8D, 0xA0, 0xA0, + 0x0B, 0x8F, 0xA0, 0xA0); + ST7701_DSI(st7701, 0xEB, + 0x00, 0x00, 0xE4, 0xE4, + 0x44, 0x00, 0x00); + ST7701_DSI(st7701, 0xED, + 0xFF, 0xF5, 0x47, 0x6F, + 0x0B, 0xA1, 0xAB, 0xFF, + 0xFF, 0xBA, 0x1A, 0xB0, + 0xF6, 0x74, 0x5F, 0xFF); + ST7701_DSI(st7701, 0xEF, + 0x08, 0x08, 0x08, 0x40, + 0x3F, 0x64); + + ST7701_DSI(st7701, DSI_CMD2BKX_SEL, + 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); + + ST7701_DSI(st7701, DSI_CMD2BKX_SEL, + 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK3_SEL); + ST7701_DSI(st7701, 0xE6, 0x7C); + ST7701_DSI(st7701, 0xE8, 0x00, 0x0E); + + ST7701_DSI(st7701, DSI_CMD2BKX_SEL, + 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); + ST7701_DSI(st7701, 0x11); + msleep(120); + + ST7701_DSI(st7701, DSI_CMD2BKX_SEL, + 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK3_SEL); + ST7701_DSI(st7701, 0xE8, 0x00, 0x0C); + msleep(10); + ST7701_DSI(st7701, 0xE8, 0x00, 0x00); + + ST7701_DSI(st7701, DSI_CMD2BKX_SEL, + 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); + ST7701_DSI(st7701, 0x11); + msleep(120); + ST7701_DSI(st7701, 0xE8, 0x00, 0x00); - /* disable Command2 */ ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); + + ST7701_DSI(st7701, 0x3A, 0x70); } static int st7701_prepare(struct drm_panel *panel) @@ -201,7 +411,7 @@ static int st7701_prepare(struct drm_panel *panel) gpiod_set_value(st7701->reset, 0); - ret = regulator_bulk_enable(st7701->desc->num_supplies, + ret = regulator_bulk_enable(ARRAY_SIZE(st7701->supplies), st7701->supplies); if (ret < 0) return ret; @@ -212,6 +422,13 @@ static int st7701_prepare(struct drm_panel *panel) st7701_init_sequence(st7701); + if (st7701->desc->gip_sequence) + st7701->desc->gip_sequence(st7701); + + /* Disable Command2 */ + ST7701_DSI(st7701, DSI_CMD2BKX_SEL, + 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); + return 0; } @@ -254,7 +471,7 @@ static int st7701_unprepare(struct drm_panel *panel) */ msleep(st7701->sleep_delay); - regulator_bulk_disable(st7701->desc->num_supplies, st7701->supplies); + regulator_bulk_disable(ARRAY_SIZE(st7701->supplies), st7701->supplies); return 0; } @@ -310,46 +527,207 @@ static const struct drm_display_mode ts8550b_mode = { .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, }; -static const char * const ts8550b_supply_names[] = { - "VCC", - "IOVCC", -}; - static const struct st7701_panel_desc ts8550b_desc = { .mode = &ts8550b_mode, .lanes = 2, - .flags = MIPI_DSI_MODE_VIDEO, .format = MIPI_DSI_FMT_RGB888, - .supply_names = ts8550b_supply_names, - .num_supplies = ARRAY_SIZE(ts8550b_supply_names), .panel_sleep_delay = 80, /* panel need extra 80ms for sleep out cmd */ + + .pv_gamma = { + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf), + + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x8), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x8), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), + + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x23), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13), + + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x12), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2b), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) + }, + .nv_gamma = { + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0x2) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf), + + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x13), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x7), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x9), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), + + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x22), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x10), + + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2c), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) + }, + .nlinv = 7, + .vop_uv = 4400000, + .vcom_uv = 337500, + .vgh_mv = 15000, + .vgl_mv = -9510, + .avdd_mv = 6600, + .avcl_mv = -4400, + .gamma_op_bias = OP_BIAS_MAX, + .input_op_bias = OP_BIAS_MIN, + .output_op_bias = OP_BIAS_MIN, + .t2d_ns = 1600, + .t3d_ns = 10400, + .eot_en = true, + .gip_sequence = ts8550b_gip_sequence, +}; + +static const struct drm_display_mode dmt028vghmcmi_1a_mode = { + .clock = 22325, + + .hdisplay = 480, + .hsync_start = 480 + 40, + .hsync_end = 480 + 40 + 4, + .htotal = 480 + 40 + 4 + 20, + + .vdisplay = 640, + .vsync_start = 640 + 2, + .vsync_end = 640 + 2 + 40, + .vtotal = 640 + 2 + 40 + 16, + + .width_mm = 56, + .height_mm = 78, + + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, + + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct st7701_panel_desc dmt028vghmcmi_1a_desc = { + .mode = &dmt028vghmcmi_1a_mode, + .lanes = 2, + .format = MIPI_DSI_FMT_RGB888, + .panel_sleep_delay = 5, /* panel need extra 5ms for sleep out cmd */ + + .pv_gamma = { + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd), + + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), + + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11), + + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) + }, + .nv_gamma = { + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe), + + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), + + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13), + + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) + }, + .nlinv = 1, + .vop_uv = 4800000, + .vcom_uv = 1650000, + .vgh_mv = 15000, + .vgl_mv = -10170, + .avdd_mv = 6600, + .avcl_mv = -4400, + .gamma_op_bias = OP_BIAS_MIDDLE, + .input_op_bias = OP_BIAS_MIN, + .output_op_bias = OP_BIAS_MIN, + .t2d_ns = 1600, + .t3d_ns = 10400, + .eot_en = true, + .gip_sequence = dmt028vghmcmi_1a_gip_sequence, }; static int st7701_dsi_probe(struct mipi_dsi_device *dsi) { const struct st7701_panel_desc *desc; struct st7701 *st7701; - int ret, i; + int ret; st7701 = devm_kzalloc(&dsi->dev, sizeof(*st7701), GFP_KERNEL); if (!st7701) return -ENOMEM; desc = of_device_get_match_data(&dsi->dev); - dsi->mode_flags = desc->flags; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; dsi->format = desc->format; dsi->lanes = desc->lanes; - st7701->supplies = devm_kcalloc(&dsi->dev, desc->num_supplies, - sizeof(*st7701->supplies), - GFP_KERNEL); - if (!st7701->supplies) - return -ENOMEM; - - for (i = 0; i < desc->num_supplies; i++) - st7701->supplies[i].supply = desc->supply_names[i]; + st7701->supplies[0].supply = "VCC"; + st7701->supplies[1].supply = "IOVCC"; - ret = devm_regulator_bulk_get(&dsi->dev, desc->num_supplies, + ret = devm_regulator_bulk_get(&dsi->dev, ARRAY_SIZE(st7701->supplies), st7701->supplies); if (ret < 0) return ret; @@ -387,17 +765,16 @@ static int st7701_dsi_probe(struct mipi_dsi_device *dsi) return mipi_dsi_attach(dsi); } -static int st7701_dsi_remove(struct mipi_dsi_device *dsi) +static void st7701_dsi_remove(struct mipi_dsi_device *dsi) { struct st7701 *st7701 = mipi_dsi_get_drvdata(dsi); mipi_dsi_detach(dsi); drm_panel_remove(&st7701->panel); - - return 0; } static const struct of_device_id st7701_of_match[] = { + { .compatible = "densitron,dmt028vghmcmi-1a", .data = &dmt028vghmcmi_1a_desc }, { .compatible = "techstar,ts8550b", .data = &ts8550b_desc }, { } }; |