diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/r520.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/r520.c | 245 |
1 files changed, 245 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c new file mode 100644 index 000000000000..ebd6b0f7bdff --- /dev/null +++ b/drivers/gpu/drm/radeon/r520.c @@ -0,0 +1,245 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#include "drmP.h" +#include "radeon_reg.h" +#include "radeon.h" +#include "radeon_share.h" + +/* r520,rv530,rv560,rv570,r580 depends on : */ +void r100_hdp_reset(struct radeon_device *rdev); +int rv370_pcie_gart_enable(struct radeon_device *rdev); +void rv370_pcie_gart_disable(struct radeon_device *rdev); +void r420_pipes_init(struct radeon_device *rdev); +void rs600_mc_disable_clients(struct radeon_device *rdev); +void rs600_disable_vga(struct radeon_device *rdev); +int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); +int rv515_debugfs_ga_info_init(struct radeon_device *rdev); + +/* This files gather functions specifics to: + * r520,rv530,rv560,rv570,r580 + * + * Some of these functions might be used by newer ASICs. + */ +void r520_gpu_init(struct radeon_device *rdev); +int r520_mc_wait_for_idle(struct radeon_device *rdev); + + +/* + * MC + */ +int r520_mc_init(struct radeon_device *rdev) +{ + uint32_t tmp; + int r; + + if (r100_debugfs_rbbm_init(rdev)) { + DRM_ERROR("Failed to register debugfs file for RBBM !\n"); + } + if (rv515_debugfs_pipes_info_init(rdev)) { + DRM_ERROR("Failed to register debugfs file for pipes !\n"); + } + if (rv515_debugfs_ga_info_init(rdev)) { + DRM_ERROR("Failed to register debugfs file for pipes !\n"); + } + + r520_gpu_init(rdev); + rv370_pcie_gart_disable(rdev); + + /* Setup GPU memory space */ + rdev->mc.vram_location = 0xFFFFFFFFUL; + rdev->mc.gtt_location = 0xFFFFFFFFUL; + if (rdev->flags & RADEON_IS_AGP) { + r = radeon_agp_init(rdev); + if (r) { + printk(KERN_WARNING "[drm] Disabling AGP\n"); + rdev->flags &= ~RADEON_IS_AGP; + rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; + } else { + rdev->mc.gtt_location = rdev->mc.agp_base; + } + } + r = radeon_mc_setup(rdev); + if (r) { + return r; + } + + /* Program GPU memory space */ + rs600_mc_disable_clients(rdev); + if (r520_mc_wait_for_idle(rdev)) { + printk(KERN_WARNING "Failed to wait MC idle while " + "programming pipes. Bad things might happen.\n"); + } + /* Write VRAM size in case we are limiting it */ + WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); + tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; + tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16); + tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16); + WREG32_MC(R520_MC_FB_LOCATION, tmp); + WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); + WREG32(0x310, rdev->mc.vram_location); + if (rdev->flags & RADEON_IS_AGP) { + tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; + tmp = REG_SET(R520_MC_AGP_TOP, tmp >> 16); + tmp |= REG_SET(R520_MC_AGP_START, rdev->mc.gtt_location >> 16); + WREG32_MC(R520_MC_AGP_LOCATION, tmp); + WREG32_MC(R520_MC_AGP_BASE, rdev->mc.agp_base); + WREG32_MC(R520_MC_AGP_BASE_2, 0); + } else { + WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF); + WREG32_MC(R520_MC_AGP_BASE, 0); + WREG32_MC(R520_MC_AGP_BASE_2, 0); + } + return 0; +} + +void r520_mc_fini(struct radeon_device *rdev) +{ + rv370_pcie_gart_disable(rdev); + radeon_gart_table_vram_free(rdev); + radeon_gart_fini(rdev); +} + + +/* + * Global GPU functions + */ +void r520_errata(struct radeon_device *rdev) +{ + rdev->pll_errata = 0; +} + +int r520_mc_wait_for_idle(struct radeon_device *rdev) +{ + unsigned i; + uint32_t tmp; + + for (i = 0; i < rdev->usec_timeout; i++) { + /* read MC_STATUS */ + tmp = RREG32_MC(R520_MC_STATUS); + if (tmp & R520_MC_STATUS_IDLE) { + return 0; + } + DRM_UDELAY(1); + } + return -1; +} + +void r520_gpu_init(struct radeon_device *rdev) +{ + unsigned pipe_select_current, gb_pipe_select, tmp; + + r100_hdp_reset(rdev); + rs600_disable_vga(rdev); + /* + * DST_PIPE_CONFIG 0x170C + * GB_TILE_CONFIG 0x4018 + * GB_FIFO_SIZE 0x4024 + * GB_PIPE_SELECT 0x402C + * GB_PIPE_SELECT2 0x4124 + * Z_PIPE_SHIFT 0 + * Z_PIPE_MASK 0x000000003 + * GB_FIFO_SIZE2 0x4128 + * SC_SFIFO_SIZE_SHIFT 0 + * SC_SFIFO_SIZE_MASK 0x000000003 + * SC_MFIFO_SIZE_SHIFT 2 + * SC_MFIFO_SIZE_MASK 0x00000000C + * FG_SFIFO_SIZE_SHIFT 4 + * FG_SFIFO_SIZE_MASK 0x000000030 + * ZB_MFIFO_SIZE_SHIFT 6 + * ZB_MFIFO_SIZE_MASK 0x0000000C0 + * GA_ENHANCE 0x4274 + * SU_REG_DEST 0x42C8 + */ + /* workaround for RV530 */ + if (rdev->family == CHIP_RV530) { + WREG32(0x4128, 0xFF); + } + r420_pipes_init(rdev); + gb_pipe_select = RREG32(0x402C); + tmp = RREG32(0x170C); + pipe_select_current = (tmp >> 2) & 3; + tmp = (1 << pipe_select_current) | + (((gb_pipe_select >> 8) & 0xF) << 4); + WREG32_PLL(0x000D, tmp); + if (r520_mc_wait_for_idle(rdev)) { + printk(KERN_WARNING "Failed to wait MC idle while " + "programming pipes. Bad things might happen.\n"); + } +} + + +/* + * VRAM info + */ +static void r520_vram_get_type(struct radeon_device *rdev) +{ + uint32_t tmp; + + rdev->mc.vram_width = 128; + rdev->mc.vram_is_ddr = true; + tmp = RREG32_MC(R520_MC_CNTL0); + switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { + case 0: + rdev->mc.vram_width = 32; + break; + case 1: + rdev->mc.vram_width = 64; + break; + case 2: + rdev->mc.vram_width = 128; + break; + case 3: + rdev->mc.vram_width = 256; + break; + default: + rdev->mc.vram_width = 128; + break; + } + if (tmp & R520_MC_CHANNEL_SIZE) + rdev->mc.vram_width *= 2; +} + +void r520_vram_info(struct radeon_device *rdev) +{ + fixed20_12 a; + + r520_vram_get_type(rdev); + + r100_vram_init_sizes(rdev); + /* FIXME: we should enforce default clock in case GPU is not in + * default setup + */ + a.full = rfixed_const(100); + rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); + rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); +} + +void r520_bandwidth_update(struct radeon_device *rdev) +{ + rv515_bandwidth_avivo_update(rdev); +} |