diff options
Diffstat (limited to 'drivers/gpu/drm/rockchip')
| -rw-r--r-- | drivers/gpu/drm/rockchip/Kconfig | 9 | ||||
| -rw-r--r-- | drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 175 | ||||
| -rw-r--r-- | drivers/gpu/drm/rockchip/inno_hdmi.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/rockchip/rk3066_hdmi.c | 10 | ||||
| -rw-r--r-- | drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 54 | ||||
| -rw-r--r-- | drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/rockchip/rockchip_lvds.c | 488 | ||||
| -rw-r--r-- | drivers/gpu/drm/rockchip/rockchip_lvds.h | 19 |
8 files changed, 538 insertions, 225 deletions
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index 6f4222f8beeb..310aa1546893 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -28,17 +28,17 @@ config ROCKCHIP_ANALOGIX_DP on RK3288 or RK3399 based SoC, you should select this option. config ROCKCHIP_CDN_DP - bool "Rockchip cdn DP" + bool "Rockchip cdn DP" depends on EXTCON=y || (EXTCON=m && DRM_ROCKCHIP=m) - help + help This selects support for Rockchip SoC specific extensions for the cdn DP driver. If you want to enable Dp on RK3399 based SoC, you should select this option. config ROCKCHIP_DW_HDMI - bool "Rockchip specific extensions for Synopsys DW HDMI" - help + bool "Rockchip specific extensions for Synopsys DW HDMI" + help This selects support for Rockchip SoC specific extensions for the Synopsys DesignWare HDMI driver. If you want to enable HDMI on RK3288 or RK3399 based SoC, you should select @@ -46,6 +46,7 @@ config ROCKCHIP_DW_HDMI config ROCKCHIP_DW_MIPI_DSI bool "Rockchip specific extensions for Synopsys DW MIPI DSI" + select GENERIC_PHY_MIPI_DPHY help This selects support for Rockchip SoC specific extensions for the Synopsys DesignWare HDMI driver. If you want to diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index bc073ec5c183..6e1270e45f97 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -12,6 +12,7 @@ #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/of_device.h> +#include <linux/phy/phy.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> @@ -139,6 +140,12 @@ #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) #define DW_MIPI_NEEDS_GRF_CLK BIT(1) +#define PX30_GRF_PD_VO_CON1 0x0438 +#define PX30_DSI_FORCETXSTOPMODE (0xf << 7) +#define PX30_DSI_FORCERXMODE BIT(6) +#define PX30_DSI_TURNDISABLE BIT(5) +#define PX30_DSI_LCDC_SEL BIT(0) + #define RK3288_GRF_SOC_CON6 0x025c #define RK3288_DSI0_LCDC_SEL BIT(6) #define RK3288_DSI1_LCDC_SEL BIT(9) @@ -223,6 +230,10 @@ struct dw_mipi_dsi_rockchip { bool is_slave; struct dw_mipi_dsi_rockchip *slave; + /* optional external dphy */ + struct phy *phy; + union phy_configure_opts phy_opts; + unsigned int lane_mbps; /* per lane */ u16 input_div; u16 feedback_div; @@ -359,6 +370,9 @@ static int dw_mipi_dsi_phy_init(void *priv_data) struct dw_mipi_dsi_rockchip *dsi = priv_data; int ret, i, vco; + if (dsi->phy) + return 0; + /* * Get vco from frequency(lane_mbps) * vco frequency table @@ -467,6 +481,28 @@ static int dw_mipi_dsi_phy_init(void *priv_data) return ret; } +static void dw_mipi_dsi_phy_power_on(void *priv_data) +{ + struct dw_mipi_dsi_rockchip *dsi = priv_data; + int ret; + + ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); + if (ret) { + DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); + return; + } + + phy_configure(dsi->phy, &dsi->phy_opts); + phy_power_on(dsi->phy); +} + +static void dw_mipi_dsi_phy_power_off(void *priv_data) +{ + struct dw_mipi_dsi_rockchip *dsi = priv_data; + + phy_power_off(dsi->phy); +} + static int dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, unsigned long mode_flags, u32 lanes, u32 format, @@ -504,6 +540,17 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, "DPHY clock frequency is out of range\n"); } + /* for external phy only a the mipi_dphy_config is necessary */ + if (dsi->phy) { + phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8, + bpp, lanes, + &dsi->phy_opts.mipi_dphy); + dsi->lane_mbps = target_mbps; + *lane_mbps = dsi->lane_mbps; + + return 0; + } + fin = clk_get_rate(dsi->pllref_clk); fout = target_mbps * USEC_PER_SEC; @@ -559,9 +606,89 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, return 0; } +struct hstt { + unsigned int maxfreq; + struct dw_mipi_dsi_dphy_timing timing; +}; + +#define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \ +{ \ + .maxfreq = _maxfreq, \ + .timing = { \ + .clk_lp2hs = _c_lp2hs, \ + .clk_hs2lp = _c_hs2lp, \ + .data_lp2hs = _d_lp2hs, \ + .data_hs2lp = _d_hs2lp, \ + } \ +} + +/* Table A-3 High-Speed Transition Times */ +struct hstt hstt_table[] = { + HSTT( 90, 32, 20, 26, 13), + HSTT( 100, 35, 23, 28, 14), + HSTT( 110, 32, 22, 26, 13), + HSTT( 130, 31, 20, 27, 13), + HSTT( 140, 33, 22, 26, 14), + HSTT( 150, 33, 21, 26, 14), + HSTT( 170, 32, 20, 27, 13), + HSTT( 180, 36, 23, 30, 15), + HSTT( 200, 40, 22, 33, 15), + HSTT( 220, 40, 22, 33, 15), + HSTT( 240, 44, 24, 36, 16), + HSTT( 250, 48, 24, 38, 17), + HSTT( 270, 48, 24, 38, 17), + HSTT( 300, 50, 27, 41, 18), + HSTT( 330, 56, 28, 45, 18), + HSTT( 360, 59, 28, 48, 19), + HSTT( 400, 61, 30, 50, 20), + HSTT( 450, 67, 31, 55, 21), + HSTT( 500, 73, 31, 59, 22), + HSTT( 550, 79, 36, 63, 24), + HSTT( 600, 83, 37, 68, 25), + HSTT( 650, 90, 38, 73, 27), + HSTT( 700, 95, 40, 77, 28), + HSTT( 750, 102, 40, 84, 28), + HSTT( 800, 106, 42, 87, 30), + HSTT( 850, 113, 44, 93, 31), + HSTT( 900, 118, 47, 98, 32), + HSTT( 950, 124, 47, 102, 34), + HSTT(1000, 130, 49, 107, 35), + HSTT(1050, 135, 51, 111, 37), + HSTT(1100, 139, 51, 114, 38), + HSTT(1150, 146, 54, 120, 40), + HSTT(1200, 153, 57, 125, 41), + HSTT(1250, 158, 58, 130, 42), + HSTT(1300, 163, 58, 135, 44), + HSTT(1350, 168, 60, 140, 45), + HSTT(1400, 172, 64, 144, 47), + HSTT(1450, 176, 65, 148, 48), + HSTT(1500, 181, 66, 153, 50) +}; + +static int +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, + struct dw_mipi_dsi_dphy_timing *timing) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(hstt_table); i++) + if (lane_mbps < hstt_table[i].maxfreq) + break; + + if (i == ARRAY_SIZE(hstt_table)) + i--; + + *timing = hstt_table[i].timing; + + return 0; +} + static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = { .init = dw_mipi_dsi_phy_init, + .power_on = dw_mipi_dsi_phy_power_on, + .power_off = dw_mipi_dsi_phy_power_off, .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, + .get_timing = dw_mipi_dsi_phy_get_timing, }; static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi, @@ -916,16 +1043,33 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev) } if (!dsi->cdata) { - dev_err(dev, "no dsi-config for %s node\n", np->name); + DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); return -EINVAL; } + /* try to get a possible external dphy */ + dsi->phy = devm_phy_optional_get(dev, "dphy"); + if (IS_ERR(dsi->phy)) { + ret = PTR_ERR(dsi->phy); + DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret); + return ret; + } + dsi->pllref_clk = devm_clk_get(dev, "ref"); if (IS_ERR(dsi->pllref_clk)) { - ret = PTR_ERR(dsi->pllref_clk); - DRM_DEV_ERROR(dev, - "Unable to get pll reference clock: %d\n", ret); - return ret; + if (dsi->phy) { + /* + * if external phy is present, pll will be + * generated there. + */ + dsi->pllref_clk = NULL; + } else { + ret = PTR_ERR(dsi->pllref_clk); + DRM_DEV_ERROR(dev, + "Unable to get pll reference clock: %d\n", + ret); + return ret; + } } if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { @@ -989,6 +1133,24 @@ static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev) return 0; } +static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = { + { + .reg = 0xff450000, + .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1, + .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL), + .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL, + PX30_DSI_LCDC_SEL), + + .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1, + .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE | + PX30_DSI_FORCERXMODE | + PX30_DSI_FORCETXSTOPMODE), + + .max_data_lanes = 4, + }, + { /* sentinel */ } +}; + static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { { .reg = 0xff960000, @@ -1057,6 +1219,9 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { { + .compatible = "rockchip,px30-mipi-dsi", + .data = &px30_chip_data, + }, { .compatible = "rockchip,rk3288-mipi-dsi", .data = &rk3288_chip_data, }, { diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c b/drivers/gpu/drm/rockchip/inno_hdmi.c index ed344a795b4d..e5864e823020 100644 --- a/drivers/gpu/drm/rockchip/inno_hdmi.c +++ b/drivers/gpu/drm/rockchip/inno_hdmi.c @@ -624,8 +624,10 @@ static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi) drm_connector_helper_add(&hdmi->connector, &inno_hdmi_connector_helper_funcs); - drm_connector_init(drm, &hdmi->connector, &inno_hdmi_connector_funcs, - DRM_MODE_CONNECTOR_HDMIA); + drm_connector_init_with_ddc(drm, &hdmi->connector, + &inno_hdmi_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA, + hdmi->ddc); drm_connector_attach_encoder(&hdmi->connector, encoder); diff --git a/drivers/gpu/drm/rockchip/rk3066_hdmi.c b/drivers/gpu/drm/rockchip/rk3066_hdmi.c index cdb401f4283d..fe203d38664e 100644 --- a/drivers/gpu/drm/rockchip/rk3066_hdmi.c +++ b/drivers/gpu/drm/rockchip/rk3066_hdmi.c @@ -564,9 +564,10 @@ rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi) drm_connector_helper_add(&hdmi->connector, &rk3066_hdmi_connector_helper_funcs); - drm_connector_init(drm, &hdmi->connector, - &rk3066_hdmi_connector_funcs, - DRM_MODE_CONNECTOR_HDMIA); + drm_connector_init_with_ddc(drm, &hdmi->connector, + &rk3066_hdmi_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA, + hdmi->ddc); drm_connector_attach_encoder(&hdmi->connector, encoder); @@ -640,6 +641,9 @@ static int rk3066_hdmi_i2c_write(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs) if (msgs->addr == DDC_ADDR) hdmi->i2c->ddc_addr = msgs->buf[0]; + /* Set edid fifo first address. */ + hdmi_writeb(hdmi, HDMI_EDID_FIFO_ADDR, 0x00); + /* Set edid word address 0x00/0x80. */ hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c index ca01234c037c..221e72e71432 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c @@ -53,64 +53,12 @@ rockchip_fb_alloc(struct drm_device *dev, const struct drm_mode_fb_cmd2 *mode_cm return fb; } -static struct drm_framebuffer * -rockchip_user_fb_create(struct drm_device *dev, struct drm_file *file_priv, - const struct drm_mode_fb_cmd2 *mode_cmd) -{ - const struct drm_format_info *info = drm_get_format_info(dev, - mode_cmd); - struct drm_framebuffer *fb; - struct drm_gem_object *objs[ROCKCHIP_MAX_FB_BUFFER]; - struct drm_gem_object *obj; - int num_planes = min_t(int, info->num_planes, ROCKCHIP_MAX_FB_BUFFER); - int ret; - int i; - - for (i = 0; i < num_planes; i++) { - unsigned int width = mode_cmd->width / (i ? info->hsub : 1); - unsigned int height = mode_cmd->height / (i ? info->vsub : 1); - unsigned int min_size; - - obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[i]); - if (!obj) { - DRM_DEV_ERROR(dev->dev, - "Failed to lookup GEM object\n"); - ret = -ENXIO; - goto err_gem_object_unreference; - } - - min_size = (height - 1) * mode_cmd->pitches[i] + - mode_cmd->offsets[i] + - width * info->cpp[i]; - - if (obj->size < min_size) { - drm_gem_object_put_unlocked(obj); - ret = -EINVAL; - goto err_gem_object_unreference; - } - objs[i] = obj; - } - - fb = rockchip_fb_alloc(dev, mode_cmd, objs, i); - if (IS_ERR(fb)) { - ret = PTR_ERR(fb); - goto err_gem_object_unreference; - } - - return fb; - -err_gem_object_unreference: - for (i--; i >= 0; i--) - drm_gem_object_put_unlocked(objs[i]); - return ERR_PTR(ret); -} - static const struct drm_mode_config_helper_funcs rockchip_mode_config_helpers = { .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, }; static const struct drm_mode_config_funcs rockchip_drm_mode_config_funcs = { - .fb_create = rockchip_user_fb_create, + .fb_create = drm_gem_fb_create_with_dirty, .output_poll_changed = drm_fb_helper_output_poll_changed, .atomic_check = drm_atomic_helper_check, .atomic_commit = drm_atomic_helper_commit, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c index 02be6c5ff857..521fe42ac5e2 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c @@ -27,7 +27,7 @@ static int rockchip_fbdev_mmap(struct fb_info *info, return rockchip_gem_mmap_buf(private->fbdev_bo, vma); } -static struct fb_ops rockchip_drm_fbdev_ops = { +static const struct fb_ops rockchip_drm_fbdev_ops = { .owner = THIS_MODULE, DRM_FB_HELPER_DEFAULT_OPS, .fb_mmap = rockchip_fbdev_mmap, diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c index 8a4c9af0ba73..f25a36743cbd 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.c +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c @@ -10,6 +10,7 @@ #include <linux/component.h> #include <linux/mfd/syscon.h> #include <linux/of_graph.h> +#include <linux/phy/phy.h> #include <linux/pinctrl/devinfo.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> @@ -31,6 +32,8 @@ #define DISPLAY_OUTPUT_LVDS 1 #define DISPLAY_OUTPUT_DUAL_LVDS 2 +struct rockchip_lvds; + #define connector_to_lvds(c) \ container_of(c, struct rockchip_lvds, connector) @@ -39,16 +42,12 @@ /** * rockchip_lvds_soc_data - rockchip lvds Soc private data - * @ch1_offset: lvds channel 1 registe offset - * grf_soc_con6: general registe offset for LVDS contrl - * grf_soc_con7: general registe offset for LVDS contrl - * has_vop_sel: to indicate whether need to choose from different VOP. + * @probe: LVDS platform probe function + * @helper_funcs: LVDS connector helper functions */ struct rockchip_lvds_soc_data { - u32 ch1_offset; - int grf_soc_con6; - int grf_soc_con7; - bool has_vop_sel; + int (*probe)(struct platform_device *pdev, struct rockchip_lvds *lvds); + const struct drm_encoder_helper_funcs *helper_funcs; }; struct rockchip_lvds { @@ -56,6 +55,7 @@ struct rockchip_lvds { void __iomem *regs; struct regmap *grf; struct clk *pclk; + struct phy *dphy; const struct rockchip_lvds_soc_data *soc_data; int output; /* rgb lvds or dual lvds output */ int format; /* vesa or jeida format */ @@ -67,15 +67,16 @@ struct rockchip_lvds { struct dev_pin_info *pins; }; -static inline void lvds_writel(struct rockchip_lvds *lvds, u32 offset, u32 val) +static inline void rk3288_writel(struct rockchip_lvds *lvds, u32 offset, + u32 val) { writel_relaxed(val, lvds->regs + offset); if (lvds->output == DISPLAY_OUTPUT_LVDS) return; - writel_relaxed(val, lvds->regs + offset + lvds->soc_data->ch1_offset); + writel_relaxed(val, lvds->regs + offset + RK3288_LVDS_CH1_OFFSET); } -static inline int lvds_name_to_format(const char *s) +static inline int rockchip_lvds_name_to_format(const char *s) { if (strncmp(s, "jeida-18", 8) == 0) return LVDS_JEIDA_18; @@ -87,7 +88,7 @@ static inline int lvds_name_to_format(const char *s) return -EINVAL; } -static inline int lvds_name_to_output(const char *s) +static inline int rockchip_lvds_name_to_output(const char *s) { if (strncmp(s, "rgb", 3) == 0) return DISPLAY_OUTPUT_RGB; @@ -99,7 +100,41 @@ static inline int lvds_name_to_output(const char *s) return -EINVAL; } -static int rockchip_lvds_poweron(struct rockchip_lvds *lvds) +static const struct drm_connector_funcs rockchip_lvds_connector_funcs = { + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = drm_connector_cleanup, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static int rockchip_lvds_connector_get_modes(struct drm_connector *connector) +{ + struct rockchip_lvds *lvds = connector_to_lvds(connector); + struct drm_panel *panel = lvds->panel; + + return drm_panel_get_modes(panel, connector); +} + +static const +struct drm_connector_helper_funcs rockchip_lvds_connector_helper_funcs = { + .get_modes = rockchip_lvds_connector_get_modes, +}; + +static int +rockchip_lvds_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); + + s->output_mode = ROCKCHIP_OUT_MODE_P888; + s->output_type = DRM_MODE_CONNECTOR_LVDS; + + return 0; +} + +static int rk3288_lvds_poweron(struct rockchip_lvds *lvds) { int ret; u32 val; @@ -121,66 +156,73 @@ static int rockchip_lvds_poweron(struct rockchip_lvds *lvds) if (lvds->output == DISPLAY_OUTPUT_RGB) { val |= RK3288_LVDS_CH0_REG0_TTL_EN | RK3288_LVDS_CH0_REG0_LANECK_EN; - lvds_writel(lvds, RK3288_LVDS_CH0_REG0, val); - lvds_writel(lvds, RK3288_LVDS_CH0_REG2, - RK3288_LVDS_PLL_FBDIV_REG2(0x46)); - lvds_writel(lvds, RK3288_LVDS_CH0_REG4, - RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE | - RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE | - RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE | - RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE | - RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE | - RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE); - lvds_writel(lvds, RK3288_LVDS_CH0_REG5, - RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA | - RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA | - RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA | - RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA | - RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA | - RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA); + rk3288_writel(lvds, RK3288_LVDS_CH0_REG0, val); + rk3288_writel(lvds, RK3288_LVDS_CH0_REG2, + RK3288_LVDS_PLL_FBDIV_REG2(0x46)); + rk3288_writel(lvds, RK3288_LVDS_CH0_REG4, + RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE | + RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE | + RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE | + RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE | + RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE | + RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE); + rk3288_writel(lvds, RK3288_LVDS_CH0_REG5, + RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA | + RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA | + RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA | + RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA | + RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA | + RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA); } else { val |= RK3288_LVDS_CH0_REG0_LVDS_EN | RK3288_LVDS_CH0_REG0_LANECK_EN; - lvds_writel(lvds, RK3288_LVDS_CH0_REG0, val); - lvds_writel(lvds, RK3288_LVDS_CH0_REG1, - RK3288_LVDS_CH0_REG1_LANECK_BIAS | - RK3288_LVDS_CH0_REG1_LANE4_BIAS | - RK3288_LVDS_CH0_REG1_LANE3_BIAS | - RK3288_LVDS_CH0_REG1_LANE2_BIAS | - RK3288_LVDS_CH0_REG1_LANE1_BIAS | - RK3288_LVDS_CH0_REG1_LANE0_BIAS); - lvds_writel(lvds, RK3288_LVDS_CH0_REG2, - RK3288_LVDS_CH0_REG2_RESERVE_ON | - RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE | - RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE | - RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE | - RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE | - RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE | - RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE | - RK3288_LVDS_PLL_FBDIV_REG2(0x46)); - lvds_writel(lvds, RK3288_LVDS_CH0_REG4, 0x00); - lvds_writel(lvds, RK3288_LVDS_CH0_REG5, 0x00); + rk3288_writel(lvds, RK3288_LVDS_CH0_REG0, val); + rk3288_writel(lvds, RK3288_LVDS_CH0_REG1, + RK3288_LVDS_CH0_REG1_LANECK_BIAS | + RK3288_LVDS_CH0_REG1_LANE4_BIAS | + RK3288_LVDS_CH0_REG1_LANE3_BIAS | + RK3288_LVDS_CH0_REG1_LANE2_BIAS | + RK3288_LVDS_CH0_REG1_LANE1_BIAS | + RK3288_LVDS_CH0_REG1_LANE0_BIAS); + rk3288_writel(lvds, RK3288_LVDS_CH0_REG2, + RK3288_LVDS_CH0_REG2_RESERVE_ON | + RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE | + RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE | + RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE | + RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE | + RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE | + RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE | + RK3288_LVDS_PLL_FBDIV_REG2(0x46)); + rk3288_writel(lvds, RK3288_LVDS_CH0_REG4, 0x00); + rk3288_writel(lvds, RK3288_LVDS_CH0_REG5, 0x00); } - lvds_writel(lvds, RK3288_LVDS_CH0_REG3, RK3288_LVDS_PLL_FBDIV_REG3(0x46)); - lvds_writel(lvds, RK3288_LVDS_CH0_REGD, RK3288_LVDS_PLL_PREDIV_REGD(0x0a)); - lvds_writel(lvds, RK3288_LVDS_CH0_REG20, RK3288_LVDS_CH0_REG20_LSB); - - lvds_writel(lvds, RK3288_LVDS_CFG_REGC, RK3288_LVDS_CFG_REGC_PLL_ENABLE); - lvds_writel(lvds, RK3288_LVDS_CFG_REG21, RK3288_LVDS_CFG_REG21_TX_ENABLE); + rk3288_writel(lvds, RK3288_LVDS_CH0_REG3, + RK3288_LVDS_PLL_FBDIV_REG3(0x46)); + rk3288_writel(lvds, RK3288_LVDS_CH0_REGD, + RK3288_LVDS_PLL_PREDIV_REGD(0x0a)); + rk3288_writel(lvds, RK3288_LVDS_CH0_REG20, + RK3288_LVDS_CH0_REG20_LSB); + + rk3288_writel(lvds, RK3288_LVDS_CFG_REGC, + RK3288_LVDS_CFG_REGC_PLL_ENABLE); + rk3288_writel(lvds, RK3288_LVDS_CFG_REG21, + RK3288_LVDS_CFG_REG21_TX_ENABLE); return 0; } -static void rockchip_lvds_poweroff(struct rockchip_lvds *lvds) +static void rk3288_lvds_poweroff(struct rockchip_lvds *lvds) { int ret; u32 val; - lvds_writel(lvds, RK3288_LVDS_CFG_REG21, RK3288_LVDS_CFG_REG21_TX_ENABLE); - lvds_writel(lvds, RK3288_LVDS_CFG_REGC, RK3288_LVDS_CFG_REGC_PLL_ENABLE); + rk3288_writel(lvds, RK3288_LVDS_CFG_REG21, + RK3288_LVDS_CFG_REG21_TX_ENABLE); + rk3288_writel(lvds, RK3288_LVDS_CFG_REGC, + RK3288_LVDS_CFG_REGC_PLL_ENABLE); val = LVDS_DUAL | LVDS_TTL_EN | LVDS_CH0_EN | LVDS_CH1_EN | LVDS_PWRDN; val |= val << 16; - ret = regmap_write(lvds->grf, lvds->soc_data->grf_soc_con7, val); + ret = regmap_write(lvds->grf, RK3288_LVDS_GRF_SOC_CON7, val); if (ret != 0) DRM_DEV_ERROR(lvds->dev, "Could not write to GRF: %d\n", ret); @@ -188,29 +230,8 @@ static void rockchip_lvds_poweroff(struct rockchip_lvds *lvds) clk_disable(lvds->pclk); } -static const struct drm_connector_funcs rockchip_lvds_connector_funcs = { - .fill_modes = drm_helper_probe_single_connector_modes, - .destroy = drm_connector_cleanup, - .reset = drm_atomic_helper_connector_reset, - .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -}; - -static int rockchip_lvds_connector_get_modes(struct drm_connector *connector) -{ - struct rockchip_lvds *lvds = connector_to_lvds(connector); - struct drm_panel *panel = lvds->panel; - - return drm_panel_get_modes(panel); -} - -static const -struct drm_connector_helper_funcs rockchip_lvds_connector_helper_funcs = { - .get_modes = rockchip_lvds_connector_get_modes, -}; - -static void rockchip_lvds_grf_config(struct drm_encoder *encoder, - struct drm_display_mode *mode) +static int rk3288_lvds_grf_config(struct drm_encoder *encoder, + struct drm_display_mode *mode) { struct rockchip_lvds *lvds = encoder_to_lvds(encoder); u8 pin_hsync = (mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1 : 0; @@ -234,22 +255,19 @@ static void rockchip_lvds_grf_config(struct drm_encoder *encoder, val |= (pin_dclk << 8) | (pin_hsync << 9); val |= (0xffff << 16); - ret = regmap_write(lvds->grf, lvds->soc_data->grf_soc_con7, val); - if (ret != 0) { + ret = regmap_write(lvds->grf, RK3288_LVDS_GRF_SOC_CON7, val); + if (ret) DRM_DEV_ERROR(lvds->dev, "Could not write to GRF: %d\n", ret); - return; - } + + return ret; } -static int rockchip_lvds_set_vop_source(struct rockchip_lvds *lvds, - struct drm_encoder *encoder) +static int rk3288_lvds_set_vop_source(struct rockchip_lvds *lvds, + struct drm_encoder *encoder) { u32 val; int ret; - if (!lvds->soc_data->has_vop_sel) - return 0; - ret = drm_of_encoder_active_endpoint_id(lvds->dev->of_node, encoder); if (ret < 0) return ret; @@ -258,56 +276,162 @@ static int rockchip_lvds_set_vop_source(struct rockchip_lvds *lvds, if (ret) val |= RK3288_LVDS_SOC_CON6_SEL_VOP_LIT; - ret = regmap_write(lvds->grf, lvds->soc_data->grf_soc_con6, val); + ret = regmap_write(lvds->grf, RK3288_LVDS_GRF_SOC_CON6, val); if (ret < 0) return ret; return 0; } -static int -rockchip_lvds_encoder_atomic_check(struct drm_encoder *encoder, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) +static void rk3288_lvds_encoder_enable(struct drm_encoder *encoder) { - struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); + struct rockchip_lvds *lvds = encoder_to_lvds(encoder); + struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; + int ret; - s->output_mode = ROCKCHIP_OUT_MODE_P888; - s->output_type = DRM_MODE_CONNECTOR_LVDS; + drm_panel_prepare(lvds->panel); - return 0; + ret = rk3288_lvds_poweron(lvds); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to power on LVDS: %d\n", ret); + drm_panel_unprepare(lvds->panel); + return; + } + + ret = rk3288_lvds_grf_config(encoder, mode); + if (ret) { + DRM_DEV_ERROR(lvds->dev, "failed to configure LVDS: %d\n", ret); + drm_panel_unprepare(lvds->panel); + return; + } + + ret = rk3288_lvds_set_vop_source(lvds, encoder); + if (ret) { + DRM_DEV_ERROR(lvds->dev, "failed to set VOP source: %d\n", ret); + drm_panel_unprepare(lvds->panel); + return; + } + + drm_panel_enable(lvds->panel); +} + +static void rk3288_lvds_encoder_disable(struct drm_encoder *encoder) +{ + struct rockchip_lvds *lvds = encoder_to_lvds(encoder); + + drm_panel_disable(lvds->panel); + rk3288_lvds_poweroff(lvds); + drm_panel_unprepare(lvds->panel); +} + +static int px30_lvds_poweron(struct rockchip_lvds *lvds) +{ + int ret; + + ret = pm_runtime_get_sync(lvds->dev); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); + return ret; + } + + /* Enable LVDS mode */ + return regmap_update_bits(lvds->grf, PX30_LVDS_GRF_PD_VO_CON1, + PX30_LVDS_MODE_EN(1) | PX30_LVDS_P2S_EN(1), + PX30_LVDS_MODE_EN(1) | PX30_LVDS_P2S_EN(1)); +} + +static void px30_lvds_poweroff(struct rockchip_lvds *lvds) +{ + regmap_update_bits(lvds->grf, PX30_LVDS_GRF_PD_VO_CON1, + PX30_LVDS_MODE_EN(1) | PX30_LVDS_P2S_EN(1), + PX30_LVDS_MODE_EN(0) | PX30_LVDS_P2S_EN(0)); + + pm_runtime_put(lvds->dev); +} + +static int px30_lvds_grf_config(struct drm_encoder *encoder, + struct drm_display_mode *mode) +{ + struct rockchip_lvds *lvds = encoder_to_lvds(encoder); + + if (lvds->output != DISPLAY_OUTPUT_LVDS) { + DRM_DEV_ERROR(lvds->dev, "Unsupported display output %d\n", + lvds->output); + return -EINVAL; + } + + /* Set format */ + return regmap_update_bits(lvds->grf, PX30_LVDS_GRF_PD_VO_CON1, + PX30_LVDS_FORMAT(lvds->format), + PX30_LVDS_FORMAT(lvds->format)); +} + +static int px30_lvds_set_vop_source(struct rockchip_lvds *lvds, + struct drm_encoder *encoder) +{ + int vop; + + vop = drm_of_encoder_active_endpoint_id(lvds->dev->of_node, encoder); + if (vop < 0) + return vop; + + return regmap_update_bits(lvds->grf, PX30_LVDS_GRF_PD_VO_CON1, + PX30_LVDS_VOP_SEL(1), + PX30_LVDS_VOP_SEL(vop)); } -static void rockchip_lvds_encoder_enable(struct drm_encoder *encoder) +static void px30_lvds_encoder_enable(struct drm_encoder *encoder) { struct rockchip_lvds *lvds = encoder_to_lvds(encoder); struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; int ret; drm_panel_prepare(lvds->panel); - ret = rockchip_lvds_poweron(lvds); - if (ret < 0) { - DRM_DEV_ERROR(lvds->dev, "failed to power on lvds: %d\n", ret); + + ret = px30_lvds_poweron(lvds); + if (ret) { + DRM_DEV_ERROR(lvds->dev, "failed to power on LVDS: %d\n", ret); drm_panel_unprepare(lvds->panel); + return; + } + + ret = px30_lvds_grf_config(encoder, mode); + if (ret) { + DRM_DEV_ERROR(lvds->dev, "failed to configure LVDS: %d\n", ret); + drm_panel_unprepare(lvds->panel); + return; } - rockchip_lvds_grf_config(encoder, mode); - rockchip_lvds_set_vop_source(lvds, encoder); + + ret = px30_lvds_set_vop_source(lvds, encoder); + if (ret) { + DRM_DEV_ERROR(lvds->dev, "failed to set VOP source: %d\n", ret); + drm_panel_unprepare(lvds->panel); + return; + } + drm_panel_enable(lvds->panel); } -static void rockchip_lvds_encoder_disable(struct drm_encoder *encoder) +static void px30_lvds_encoder_disable(struct drm_encoder *encoder) { struct rockchip_lvds *lvds = encoder_to_lvds(encoder); drm_panel_disable(lvds->panel); - rockchip_lvds_poweroff(lvds); + px30_lvds_poweroff(lvds); drm_panel_unprepare(lvds->panel); } static const -struct drm_encoder_helper_funcs rockchip_lvds_encoder_helper_funcs = { - .enable = rockchip_lvds_encoder_enable, - .disable = rockchip_lvds_encoder_disable, +struct drm_encoder_helper_funcs rk3288_lvds_encoder_helper_funcs = { + .enable = rk3288_lvds_encoder_enable, + .disable = rk3288_lvds_encoder_disable, + .atomic_check = rockchip_lvds_encoder_atomic_check, +}; + +static const +struct drm_encoder_helper_funcs px30_lvds_encoder_helper_funcs = { + .enable = px30_lvds_encoder_enable, + .disable = px30_lvds_encoder_disable, .atomic_check = rockchip_lvds_encoder_atomic_check, }; @@ -315,11 +439,88 @@ static const struct drm_encoder_funcs rockchip_lvds_encoder_funcs = { .destroy = drm_encoder_cleanup, }; +static int rk3288_lvds_probe(struct platform_device *pdev, + struct rockchip_lvds *lvds) +{ + struct resource *res; + int ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + lvds->regs = devm_ioremap_resource(lvds->dev, res); + if (IS_ERR(lvds->regs)) + return PTR_ERR(lvds->regs); + + lvds->pclk = devm_clk_get(lvds->dev, "pclk_lvds"); + if (IS_ERR(lvds->pclk)) { + DRM_DEV_ERROR(lvds->dev, "could not get pclk_lvds\n"); + return PTR_ERR(lvds->pclk); + } + + lvds->pins = devm_kzalloc(lvds->dev, sizeof(*lvds->pins), + GFP_KERNEL); + if (!lvds->pins) + return -ENOMEM; + + lvds->pins->p = devm_pinctrl_get(lvds->dev); + if (IS_ERR(lvds->pins->p)) { + DRM_DEV_ERROR(lvds->dev, "no pinctrl handle\n"); + devm_kfree(lvds->dev, lvds->pins); + lvds->pins = NULL; + } else { + lvds->pins->default_state = + pinctrl_lookup_state(lvds->pins->p, "lcdc"); + if (IS_ERR(lvds->pins->default_state)) { + DRM_DEV_ERROR(lvds->dev, "no default pinctrl state\n"); + devm_kfree(lvds->dev, lvds->pins); + lvds->pins = NULL; + } + } + + ret = clk_prepare(lvds->pclk); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to prepare pclk_lvds\n"); + return ret; + } + + return 0; +} + +static int px30_lvds_probe(struct platform_device *pdev, + struct rockchip_lvds *lvds) +{ + int ret; + + /* MSB */ + ret = regmap_update_bits(lvds->grf, PX30_LVDS_GRF_PD_VO_CON1, + PX30_LVDS_MSBSEL(1), + PX30_LVDS_MSBSEL(1)); + if (ret) + return ret; + + /* PHY */ + lvds->dphy = devm_phy_get(&pdev->dev, "dphy"); + if (IS_ERR(lvds->dphy)) + return PTR_ERR(lvds->dphy); + + phy_init(lvds->dphy); + if (ret) + return ret; + + phy_set_mode(lvds->dphy, PHY_MODE_LVDS); + if (ret) + return ret; + + return phy_power_on(lvds->dphy); +} + static const struct rockchip_lvds_soc_data rk3288_lvds_data = { - .ch1_offset = 0x100, - .grf_soc_con6 = 0x025c, - .grf_soc_con7 = 0x0260, - .has_vop_sel = true, + .probe = rk3288_lvds_probe, + .helper_funcs = &rk3288_lvds_encoder_helper_funcs, +}; + +static const struct rockchip_lvds_soc_data px30_lvds_data = { + .probe = px30_lvds_probe, + .helper_funcs = &px30_lvds_encoder_helper_funcs, }; static const struct of_device_id rockchip_lvds_dt_ids[] = { @@ -327,6 +528,10 @@ static const struct of_device_id rockchip_lvds_dt_ids[] = { .compatible = "rockchip,rk3288-lvds", .data = &rk3288_lvds_data }, + { + .compatible = "rockchip,px30-lvds", + .data = &px30_lvds_data + }, {} }; MODULE_DEVICE_TABLE(of, rockchip_lvds_dt_ids); @@ -378,7 +583,7 @@ static int rockchip_lvds_bind(struct device *dev, struct device *master, /* default set it as output rgb */ lvds->output = DISPLAY_OUTPUT_RGB; else - lvds->output = lvds_name_to_output(name); + lvds->output = rockchip_lvds_name_to_output(name); if (lvds->output < 0) { DRM_DEV_ERROR(dev, "invalid output type [%s]\n", name); @@ -390,7 +595,7 @@ static int rockchip_lvds_bind(struct device *dev, struct device *master, /* default set it as format vesa 18 */ lvds->format = LVDS_VESA_18; else - lvds->format = lvds_name_to_format(name); + lvds->format = rockchip_lvds_name_to_format(name); if (lvds->format < 0) { DRM_DEV_ERROR(dev, "invalid data-mapping format [%s]\n", name); @@ -410,7 +615,7 @@ static int rockchip_lvds_bind(struct device *dev, struct device *master, goto err_put_remote; } - drm_encoder_helper_add(encoder, &rockchip_lvds_encoder_helper_funcs); + drm_encoder_helper_add(encoder, lvds->soc_data->helper_funcs); if (lvds->panel) { connector = &lvds->connector; @@ -471,8 +676,10 @@ static void rockchip_lvds_unbind(struct device *dev, struct device *master, void *data) { struct rockchip_lvds *lvds = dev_get_drvdata(dev); + const struct drm_encoder_helper_funcs *encoder_funcs; - rockchip_lvds_encoder_disable(&lvds->encoder); + encoder_funcs = lvds->soc_data->helper_funcs; + encoder_funcs->disable(&lvds->encoder); if (lvds->panel) drm_panel_detach(lvds->panel); pm_runtime_disable(dev); @@ -490,7 +697,6 @@ static int rockchip_lvds_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct rockchip_lvds *lvds; const struct of_device_id *match; - struct resource *res; int ret; if (!dev->of_node) @@ -506,37 +712,6 @@ static int rockchip_lvds_probe(struct platform_device *pdev) return -ENODEV; lvds->soc_data = match->data; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - lvds->regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(lvds->regs)) - return PTR_ERR(lvds->regs); - - lvds->pclk = devm_clk_get(&pdev->dev, "pclk_lvds"); - if (IS_ERR(lvds->pclk)) { - DRM_DEV_ERROR(dev, "could not get pclk_lvds\n"); - return PTR_ERR(lvds->pclk); - } - - lvds->pins = devm_kzalloc(lvds->dev, sizeof(*lvds->pins), - GFP_KERNEL); - if (!lvds->pins) - return -ENOMEM; - - lvds->pins->p = devm_pinctrl_get(lvds->dev); - if (IS_ERR(lvds->pins->p)) { - DRM_DEV_ERROR(dev, "no pinctrl handle\n"); - devm_kfree(lvds->dev, lvds->pins); - lvds->pins = NULL; - } else { - lvds->pins->default_state = - pinctrl_lookup_state(lvds->pins->p, "lcdc"); - if (IS_ERR(lvds->pins->default_state)) { - DRM_DEV_ERROR(dev, "no default pinctrl state\n"); - devm_kfree(lvds->dev, lvds->pins); - lvds->pins = NULL; - } - } - lvds->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); if (IS_ERR(lvds->grf)) { @@ -544,13 +719,14 @@ static int rockchip_lvds_probe(struct platform_device *pdev) return PTR_ERR(lvds->grf); } - dev_set_drvdata(dev, lvds); - - ret = clk_prepare(lvds->pclk); - if (ret < 0) { - DRM_DEV_ERROR(dev, "failed to prepare pclk_lvds\n"); + ret = lvds->soc_data->probe(pdev, lvds); + if (ret) { + DRM_DEV_ERROR(dev, "Platform initialization failed\n"); return ret; } + + dev_set_drvdata(dev, lvds); + ret = component_add(&pdev->dev, &rockchip_lvds_component_ops); if (ret < 0) { DRM_DEV_ERROR(dev, "failed to add component\n"); diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.h b/drivers/gpu/drm/rockchip/rockchip_lvds.h index 029bad8e1a14..4ce967d23813 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.h +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.h @@ -70,7 +70,10 @@ #define RK3288_LVDS_CFG_REG21 0x84 #define RK3288_LVDS_CFG_REG21_TX_ENABLE 0x92 #define RK3288_LVDS_CFG_REG21_TX_DISABLE 0x00 -#define RK3288_LVDS_CH1_OFFSET 0x100 +#define RK3288_LVDS_CH1_OFFSET 0x100 + +#define RK3288_LVDS_GRF_SOC_CON6 0x025C +#define RK3288_LVDS_GRF_SOC_CON7 0x0260 /* fbdiv value is split over 2 registers, with bit8 in reg2 */ #define RK3288_LVDS_PLL_FBDIV_REG2(_fbd) \ @@ -103,4 +106,18 @@ #define LVDS_VESA_18 2 #define LVDS_JEIDA_18 3 +#define HIWORD_UPDATE(v, h, l) ((GENMASK(h, l) << 16) | ((v) << (l))) + +#define PX30_LVDS_GRF_PD_VO_CON0 0x434 +#define PX30_LVDS_TIE_CLKS(val) HIWORD_UPDATE(val, 8, 8) +#define PX30_LVDS_INVERT_CLKS(val) HIWORD_UPDATE(val, 9, 9) +#define PX30_LVDS_INVERT_DCLK(val) HIWORD_UPDATE(val, 5, 5) + +#define PX30_LVDS_GRF_PD_VO_CON1 0x438 +#define PX30_LVDS_FORMAT(val) HIWORD_UPDATE(val, 14, 13) +#define PX30_LVDS_MODE_EN(val) HIWORD_UPDATE(val, 12, 12) +#define PX30_LVDS_MSBSEL(val) HIWORD_UPDATE(val, 11, 11) +#define PX30_LVDS_P2S_EN(val) HIWORD_UPDATE(val, 6, 6) +#define PX30_LVDS_VOP_SEL(val) HIWORD_UPDATE(val, 1, 1) + #endif /* _ROCKCHIP_LVDS_ */ |