diff options
Diffstat (limited to 'drivers/media/dvb-frontends')
166 files changed, 2920 insertions, 2586 deletions
diff --git a/drivers/media/dvb-frontends/Makefile b/drivers/media/dvb-frontends/Makefile index d025eb373842..4be59fed4536 100644 --- a/drivers/media/dvb-frontends/Makefile +++ b/drivers/media/dvb-frontends/Makefile @@ -3,7 +3,6 @@ # Makefile for the kernel DVB frontend device drivers. # -ccflags-y += -I$(srctree)/drivers/media/dvb-core/ ccflags-y += -I$(srctree)/drivers/media/tuners/ # FIXME: RTL2832 SDR driver uses power management directly from USB IF driver diff --git a/drivers/media/dvb-frontends/a8293.h b/drivers/media/dvb-frontends/a8293.h index 7b90a03fcd0a..bc6f74f10f32 100644 --- a/drivers/media/dvb-frontends/a8293.h +++ b/drivers/media/dvb-frontends/a8293.h @@ -17,7 +17,7 @@ #ifndef A8293_H #define A8293_H -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> /* * I2C address diff --git a/drivers/media/dvb-frontends/af9013.h b/drivers/media/dvb-frontends/af9013.h index 353274524f1b..a290722c04fd 100644 --- a/drivers/media/dvb-frontends/af9013.h +++ b/drivers/media/dvb-frontends/af9013.h @@ -38,6 +38,13 @@ * @api_version: Firmware API version. * @gpio: GPIOs. * @get_dvb_frontend: Get DVB frontend callback. + * + * AF9013/5 GPIOs (mostly guessed): + * * demod#1-gpio#0 - set demod#2 i2c-addr for dual devices + * * demod#1-gpio#1 - xtal setting (?) + * * demod#1-gpio#3 - tuner#1 + * * demod#2-gpio#0 - tuner#2 + * * demod#2-gpio#1 - xtal setting (?) */ struct af9013_platform_data { /* @@ -89,16 +96,15 @@ struct af9013_platform_data { #define AF9013_TS_PARALLEL AF9013_TS_MODE_PARALLEL #define AF9013_TS_SERIAL AF9013_TS_MODE_SERIAL -/* - * AF9013/5 GPIOs (mostly guessed) - * demod#1-gpio#0 - set demod#2 i2c-addr for dual devices - * demod#1-gpio#1 - xtal setting (?) - * demod#1-gpio#3 - tuner#1 - * demod#2-gpio#0 - tuner#2 - * demod#2-gpio#1 - xtal setting (?) - */ - #if IS_REACHABLE(CONFIG_DVB_AF9013) +/** + * Attach an af9013 demod + * + * @config: pointer to &struct af9013_config with demod configuration. + * @i2c: i2c adapter to use. + * + * return: FE pointer on success, NULL on failure. + */ extern struct dvb_frontend *af9013_attach(const struct af9013_config *config, struct i2c_adapter *i2c); #else diff --git a/drivers/media/dvb-frontends/af9013_priv.h b/drivers/media/dvb-frontends/af9013_priv.h index 35ca5c9bcacd..688fc3472cf6 100644 --- a/drivers/media/dvb-frontends/af9013_priv.h +++ b/drivers/media/dvb-frontends/af9013_priv.h @@ -21,7 +21,7 @@ #ifndef AF9013_PRIV_H #define AF9013_PRIV_H -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "af9013.h" #include <linux/firmware.h> #include <linux/math64.h> diff --git a/drivers/media/dvb-frontends/af9033_priv.h b/drivers/media/dvb-frontends/af9033_priv.h index 8799cda1ae14..f269abf609f0 100644 --- a/drivers/media/dvb-frontends/af9033_priv.h +++ b/drivers/media/dvb-frontends/af9033_priv.h @@ -18,12 +18,12 @@ #ifndef AF9033_PRIV_H #define AF9033_PRIV_H -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "af9033.h" #include <linux/math64.h> #include <linux/regmap.h> #include <linux/kernel.h> -#include "dvb_math.h" +#include <media/dvb_math.h> struct reg_val { u32 reg; diff --git a/drivers/media/dvb-frontends/as102_fe.c b/drivers/media/dvb-frontends/as102_fe.c index b1c84ee914f0..9b2f2da1d989 100644 --- a/drivers/media/dvb-frontends/as102_fe.c +++ b/drivers/media/dvb-frontends/as102_fe.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include <dvb_frontend.h> +#include <media/dvb_frontend.h> #include "as102_fe.h" diff --git a/drivers/media/dvb-frontends/ascot2e.c b/drivers/media/dvb-frontends/ascot2e.c index 0ee0df53b91b..9746c6dd7fb8 100644 --- a/drivers/media/dvb-frontends/ascot2e.c +++ b/drivers/media/dvb-frontends/ascot2e.c @@ -24,7 +24,7 @@ #include <linux/dvb/frontend.h> #include <linux/types.h> #include "ascot2e.h" -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #define MAX_WRITE_REGSIZE 10 @@ -155,7 +155,9 @@ static int ascot2e_write_regs(struct ascot2e_priv *priv, static int ascot2e_write_reg(struct ascot2e_priv *priv, u8 reg, u8 val) { - return ascot2e_write_regs(priv, reg, &val, 1); + u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ + + return ascot2e_write_regs(priv, reg, &tmp, 1); } static int ascot2e_read_regs(struct ascot2e_priv *priv, diff --git a/drivers/media/dvb-frontends/ascot2e.h b/drivers/media/dvb-frontends/ascot2e.h index dc61bf7d1b09..418c565baf83 100644 --- a/drivers/media/dvb-frontends/ascot2e.h +++ b/drivers/media/dvb-frontends/ascot2e.h @@ -41,6 +41,15 @@ struct ascot2e_config { }; #if IS_REACHABLE(CONFIG_DVB_ASCOT2E) +/** + * Attach an ascot2e tuner + * + * @fe: frontend to be attached + * @config: pointer to &struct ascot2e_config with tuner configuration. + * @i2c: i2c adapter to use. + * + * return: FE pointer on success, NULL on failure. + */ extern struct dvb_frontend *ascot2e_attach(struct dvb_frontend *fe, const struct ascot2e_config *config, struct i2c_adapter *i2c); diff --git a/drivers/media/dvb-frontends/atbm8830.c b/drivers/media/dvb-frontends/atbm8830.c index 05850b32d6c6..7b0f3239dbba 100644 --- a/drivers/media/dvb-frontends/atbm8830.c +++ b/drivers/media/dvb-frontends/atbm8830.c @@ -16,7 +16,7 @@ */ #include <asm/div64.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "atbm8830.h" #include "atbm8830_priv.h" diff --git a/drivers/media/dvb-frontends/au8522_common.c b/drivers/media/dvb-frontends/au8522_common.c index 6722838c3707..56605de9923b 100644 --- a/drivers/media/dvb-frontends/au8522_common.c +++ b/drivers/media/dvb-frontends/au8522_common.c @@ -23,7 +23,7 @@ */ #include <linux/i2c.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "au8522_priv.h" static int debug; diff --git a/drivers/media/dvb-frontends/au8522_dig.c b/drivers/media/dvb-frontends/au8522_dig.c index 3f3635f5a06a..8f659bd1c79e 100644 --- a/drivers/media/dvb-frontends/au8522_dig.c +++ b/drivers/media/dvb-frontends/au8522_dig.c @@ -24,7 +24,7 @@ #include <linux/module.h> #include <linux/string.h> #include <linux/delay.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "au8522.h" #include "au8522_priv.h" diff --git a/drivers/media/dvb-frontends/au8522_priv.h b/drivers/media/dvb-frontends/au8522_priv.h index f5a9438f6ce5..2043c1744753 100644 --- a/drivers/media/dvb-frontends/au8522_priv.h +++ b/drivers/media/dvb-frontends/au8522_priv.h @@ -32,7 +32,7 @@ #include <media/v4l2-ctrls.h> #include <media/v4l2-mc.h> #include <linux/i2c.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "au8522.h" #include "tuner-i2c.h" @@ -99,7 +99,7 @@ int au8522_led_ctrl(struct au8522_state *state, int led); #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H 0x0A5 #define AU8522_AGC_CONTROL_RANGE_REG0A6H 0x0A6 #define AU8522_SYSTEM_GAIN_CONTROL_REG0A7H 0x0A7 -#define AU8522_TUNER_AGC_RF_STOP_REG0A8H 0x0A8 +#define AU8522_TUNER_AGC_RF_STOP_REG0A8H 0x0A8 #define AU8522_TUNER_AGC_RF_START_REG0A9H 0x0A9 #define AU8522_TUNER_RF_AGC_DEFAULT_REG0AAH 0x0AA #define AU8522_TUNER_AGC_IF_STOP_REG0ABH 0x0AB @@ -110,18 +110,18 @@ int au8522_led_ctrl(struct au8522_state *state, int led); /* Receiver registers */ #define AU8522_FRMREGTHRD1_REG0B0H 0x0B0 -#define AU8522_FRMREGAGC1H_REG0B1H 0x0B1 -#define AU8522_FRMREGSHIFT1_REG0B2H 0x0B2 -#define AU8522_TOREGAGC1_REG0B3H 0x0B3 -#define AU8522_TOREGASHIFT1_REG0B4H 0x0B4 +#define AU8522_FRMREGAGC1H_REG0B1H 0x0B1 +#define AU8522_FRMREGSHIFT1_REG0B2H 0x0B2 +#define AU8522_TOREGAGC1_REG0B3H 0x0B3 +#define AU8522_TOREGASHIFT1_REG0B4H 0x0B4 #define AU8522_FRMREGBBH_REG0B5H 0x0B5 -#define AU8522_FRMREGBBM_REG0B6H 0x0B6 -#define AU8522_FRMREGBBL_REG0B7H 0x0B7 +#define AU8522_FRMREGBBM_REG0B6H 0x0B6 +#define AU8522_FRMREGBBL_REG0B7H 0x0B7 /* 0xB8 TO 0xD7 are the filter coefficients */ -#define AU8522_FRMREGTHRD2_REG0D8H 0x0D8 -#define AU8522_FRMREGAGC2H_REG0D9H 0x0D9 -#define AU8522_TOREGAGC2_REG0DAH 0x0DA -#define AU8522_TOREGSHIFT2_REG0DBH 0x0DB +#define AU8522_FRMREGTHRD2_REG0D8H 0x0D8 +#define AU8522_FRMREGAGC2H_REG0D9H 0x0D9 +#define AU8522_TOREGAGC2_REG0DAH 0x0DA +#define AU8522_TOREGSHIFT2_REG0DBH 0x0DB #define AU8522_FRMREGPILOTH_REG0DCH 0x0DC #define AU8522_FRMREGPILOTM_REG0DDH 0x0DD #define AU8522_FRMREGPILOTL_REG0DEH 0x0DE @@ -134,9 +134,9 @@ int au8522_led_ctrl(struct au8522_state *state, int led); #define AU8522_CHIP_MODE_REG0FEH 0x0FE /* I2C bus control registers */ -#define AU8522_I2C_CONTROL_REG0_REG090H 0x090 -#define AU8522_I2C_CONTROL_REG1_REG091H 0x091 -#define AU8522_I2C_STATUS_REG092H 0x092 +#define AU8522_I2C_CONTROL_REG0_REG090H 0x090 +#define AU8522_I2C_CONTROL_REG1_REG091H 0x091 +#define AU8522_I2C_STATUS_REG092H 0x092 #define AU8522_I2C_WR_DATA0_REG093H 0x093 #define AU8522_I2C_WR_DATA1_REG094H 0x094 #define AU8522_I2C_WR_DATA2_REG095H 0x095 @@ -156,48 +156,48 @@ int au8522_led_ctrl(struct au8522_state *state, int led); #define AU8522_ENA_USB_REG101H 0x101 -#define AU8522_I2S_CTRL_0_REG110H 0x110 -#define AU8522_I2S_CTRL_1_REG111H 0x111 -#define AU8522_I2S_CTRL_2_REG112H 0x112 +#define AU8522_I2S_CTRL_0_REG110H 0x110 +#define AU8522_I2S_CTRL_1_REG111H 0x111 +#define AU8522_I2S_CTRL_2_REG112H 0x112 -#define AU8522_FRMREGFFECONTROL_REG121H 0x121 -#define AU8522_FRMREGDFECONTROL_REG122H 0x122 +#define AU8522_FRMREGFFECONTROL_REG121H 0x121 +#define AU8522_FRMREGDFECONTROL_REG122H 0x122 -#define AU8522_CARRFREQOFFSET0_REG201H 0x201 +#define AU8522_CARRFREQOFFSET0_REG201H 0x201 #define AU8522_CARRFREQOFFSET1_REG202H 0x202 #define AU8522_DECIMATION_GAIN_REG21AH 0x21A -#define AU8522_FRMREGIFSLP_REG21BH 0x21B -#define AU8522_FRMREGTHRDL2_REG21CH 0x21C -#define AU8522_FRMREGSTEP3DB_REG21DH 0x21D +#define AU8522_FRMREGIFSLP_REG21BH 0x21B +#define AU8522_FRMREGTHRDL2_REG21CH 0x21C +#define AU8522_FRMREGSTEP3DB_REG21DH 0x21D #define AU8522_DAGC_GAIN_ADJUSTMENT_REG21EH 0x21E -#define AU8522_FRMREGPLLMODE_REG21FH 0x21F -#define AU8522_FRMREGCSTHRD_REG220H 0x220 -#define AU8522_FRMREGCRLOCKDMAX_REG221H 0x221 -#define AU8522_FRMREGCRPERIODMASK_REG222H 0x222 -#define AU8522_FRMREGCRLOCK0THH_REG223H 0x223 -#define AU8522_FRMREGCRLOCK1THH_REG224H 0x224 -#define AU8522_FRMREGCRLOCK0THL_REG225H 0x225 -#define AU8522_FRMREGCRLOCK1THL_REG226H 0x226 +#define AU8522_FRMREGPLLMODE_REG21FH 0x21F +#define AU8522_FRMREGCSTHRD_REG220H 0x220 +#define AU8522_FRMREGCRLOCKDMAX_REG221H 0x221 +#define AU8522_FRMREGCRPERIODMASK_REG222H 0x222 +#define AU8522_FRMREGCRLOCK0THH_REG223H 0x223 +#define AU8522_FRMREGCRLOCK1THH_REG224H 0x224 +#define AU8522_FRMREGCRLOCK0THL_REG225H 0x225 +#define AU8522_FRMREGCRLOCK1THL_REG226H 0x226 #define AU_FRMREGPLLACQPHASESCL_REG227H 0x227 -#define AU8522_FRMREGFREQFBCTRL_REG228H 0x228 +#define AU8522_FRMREGFREQFBCTRL_REG228H 0x228 /* Analog TV Decoder */ #define AU8522_TVDEC_STATUS_REG000H 0x000 #define AU8522_TVDEC_INT_STATUS_REG001H 0x001 -#define AU8522_TVDEC_MACROVISION_STATUS_REG002H 0x002 +#define AU8522_TVDEC_MACROVISION_STATUS_REG002H 0x002 #define AU8522_TVDEC_SHARPNESSREG009H 0x009 #define AU8522_TVDEC_BRIGHTNESS_REG00AH 0x00A #define AU8522_TVDEC_CONTRAST_REG00BH 0x00B #define AU8522_TVDEC_SATURATION_CB_REG00CH 0x00C #define AU8522_TVDEC_SATURATION_CR_REG00DH 0x00D #define AU8522_TVDEC_HUE_H_REG00EH 0x00E -#define AU8522_TVDEC_HUE_L_REG00FH 0x00F +#define AU8522_TVDEC_HUE_L_REG00FH 0x00F #define AU8522_TVDEC_INT_MASK_REG010H 0x010 #define AU8522_VIDEO_MODE_REG011H 0x011 #define AU8522_TVDEC_PGA_REG012H 0x012 #define AU8522_TVDEC_COMB_MODE_REG015H 0x015 -#define AU8522_REG016H 0x016 +#define AU8522_REG016H 0x016 #define AU8522_TVDED_DBG_MODE_REG060H 0x060 #define AU8522_TVDEC_FORMAT_CTRL1_REG061H 0x061 #define AU8522_TVDEC_FORMAT_CTRL2_REG062H 0x062 @@ -207,13 +207,13 @@ int au8522_led_ctrl(struct au8522_state *state, int led); #define AU8522_TVDEC_COMB_VDIF_THR2_REG066H 0x066 #define AU8522_TVDEC_COMB_VDIF_THR3_REG067H 0x067 #define AU8522_TVDEC_COMB_NOTCH_THR_REG068H 0x068 -#define AU8522_TVDEC_COMB_HDIF_THR1_REG069H 0x069 +#define AU8522_TVDEC_COMB_HDIF_THR1_REG069H 0x069 #define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH 0x06A -#define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH 0x06B -#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH 0x06C -#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH 0x06D -#define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH 0x06E -#define AU8522_TVDEC_UV_SEP_THR_REG06FH 0x06F +#define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH 0x06B +#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH 0x06C +#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH 0x06D +#define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH 0x06E +#define AU8522_TVDEC_UV_SEP_THR_REG06FH 0x06F #define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H 0x070 #define AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H 0x073 #define AU8522_TVDEC_DCAGC_CTRL_REG077H 0x077 @@ -229,42 +229,42 @@ int au8522_led_ctrl(struct au8522_state *state, int led); #define AU8522_TVDEC_CHROMA_AGC_REG401H 0x401 #define AU8522_TVDEC_CHROMA_SFT_REG402H 0x402 -#define AU8522_FILTER_COEF_R410 0x410 -#define AU8522_FILTER_COEF_R411 0x411 -#define AU8522_FILTER_COEF_R412 0x412 -#define AU8522_FILTER_COEF_R413 0x413 -#define AU8522_FILTER_COEF_R414 0x414 -#define AU8522_FILTER_COEF_R415 0x415 -#define AU8522_FILTER_COEF_R416 0x416 -#define AU8522_FILTER_COEF_R417 0x417 -#define AU8522_FILTER_COEF_R418 0x418 -#define AU8522_FILTER_COEF_R419 0x419 -#define AU8522_FILTER_COEF_R41A 0x41A -#define AU8522_FILTER_COEF_R41B 0x41B -#define AU8522_FILTER_COEF_R41C 0x41C -#define AU8522_FILTER_COEF_R41D 0x41D -#define AU8522_FILTER_COEF_R41E 0x41E -#define AU8522_FILTER_COEF_R41F 0x41F -#define AU8522_FILTER_COEF_R420 0x420 -#define AU8522_FILTER_COEF_R421 0x421 -#define AU8522_FILTER_COEF_R422 0x422 -#define AU8522_FILTER_COEF_R423 0x423 -#define AU8522_FILTER_COEF_R424 0x424 -#define AU8522_FILTER_COEF_R425 0x425 -#define AU8522_FILTER_COEF_R426 0x426 -#define AU8522_FILTER_COEF_R427 0x427 -#define AU8522_FILTER_COEF_R428 0x428 -#define AU8522_FILTER_COEF_R429 0x429 -#define AU8522_FILTER_COEF_R42A 0x42A -#define AU8522_FILTER_COEF_R42B 0x42B -#define AU8522_FILTER_COEF_R42C 0x42C -#define AU8522_FILTER_COEF_R42D 0x42D +#define AU8522_FILTER_COEF_R410 0x410 +#define AU8522_FILTER_COEF_R411 0x411 +#define AU8522_FILTER_COEF_R412 0x412 +#define AU8522_FILTER_COEF_R413 0x413 +#define AU8522_FILTER_COEF_R414 0x414 +#define AU8522_FILTER_COEF_R415 0x415 +#define AU8522_FILTER_COEF_R416 0x416 +#define AU8522_FILTER_COEF_R417 0x417 +#define AU8522_FILTER_COEF_R418 0x418 +#define AU8522_FILTER_COEF_R419 0x419 +#define AU8522_FILTER_COEF_R41A 0x41A +#define AU8522_FILTER_COEF_R41B 0x41B +#define AU8522_FILTER_COEF_R41C 0x41C +#define AU8522_FILTER_COEF_R41D 0x41D +#define AU8522_FILTER_COEF_R41E 0x41E +#define AU8522_FILTER_COEF_R41F 0x41F +#define AU8522_FILTER_COEF_R420 0x420 +#define AU8522_FILTER_COEF_R421 0x421 +#define AU8522_FILTER_COEF_R422 0x422 +#define AU8522_FILTER_COEF_R423 0x423 +#define AU8522_FILTER_COEF_R424 0x424 +#define AU8522_FILTER_COEF_R425 0x425 +#define AU8522_FILTER_COEF_R426 0x426 +#define AU8522_FILTER_COEF_R427 0x427 +#define AU8522_FILTER_COEF_R428 0x428 +#define AU8522_FILTER_COEF_R429 0x429 +#define AU8522_FILTER_COEF_R42A 0x42A +#define AU8522_FILTER_COEF_R42B 0x42B +#define AU8522_FILTER_COEF_R42C 0x42C +#define AU8522_FILTER_COEF_R42D 0x42D /* VBI Control Registers */ -#define AU8522_TVDEC_VBI_RX_FIFO_CONTAIN_REG004H 0x004 -#define AU8522_TVDEC_VBI_TX_FIFO_CONTAIN_REG005H 0x005 -#define AU8522_TVDEC_VBI_RX_FIFO_READ_REG006H 0x006 -#define AU8522_TVDEC_VBI_FIFO_STATUS_REG007H 0x007 +#define AU8522_TVDEC_VBI_RX_FIFO_CONTAIN_REG004H 0x004 +#define AU8522_TVDEC_VBI_TX_FIFO_CONTAIN_REG005H 0x005 +#define AU8522_TVDEC_VBI_RX_FIFO_READ_REG006H 0x006 +#define AU8522_TVDEC_VBI_FIFO_STATUS_REG007H 0x007 #define AU8522_TVDEC_VBI_CTRL_H_REG017H 0x017 #define AU8522_TVDEC_VBI_CTRL_L_REG018H 0x018 #define AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H 0x019 @@ -272,10 +272,10 @@ int au8522_led_ctrl(struct au8522_state *state, int led); #define AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH 0x01B #define AU8522_TVDEC_VBI_USER_THRESH1_REG01CH 0x01C #define AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH 0x01E -#define AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH 0x01F -#define AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H 0x020 -#define AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H 0x021 -#define AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H 0x022 +#define AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH 0x01F +#define AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H 0x020 +#define AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H 0x021 +#define AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H 0x022 #define AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H 0x023 #define AU8522_REG071H 0x071 @@ -315,17 +315,17 @@ int au8522_led_ctrl(struct au8522_state *state, int led); #define AU8522_GPIO_DATA_REG0E2H 0x0E2 /* Audio Control Registers */ -#define AU8522_AUDIOAGC_REG0EEH 0x0EE -#define AU8522_AUDIO_STATUS_REG0F0H 0x0F0 -#define AU8522_AUDIO_MODE_REG0F1H 0x0F1 -#define AU8522_AUDIO_VOLUME_L_REG0F2H 0x0F2 -#define AU8522_AUDIO_VOLUME_R_REG0F3H 0x0F3 -#define AU8522_AUDIO_VOLUME_REG0F4H 0x0F4 -#define AU8522_FRMREGAUPHASE_REG0F7H 0x0F7 +#define AU8522_AUDIOAGC_REG0EEH 0x0EE +#define AU8522_AUDIO_STATUS_REG0F0H 0x0F0 +#define AU8522_AUDIO_MODE_REG0F1H 0x0F1 +#define AU8522_AUDIO_VOLUME_L_REG0F2H 0x0F2 +#define AU8522_AUDIO_VOLUME_R_REG0F3H 0x0F3 +#define AU8522_AUDIO_VOLUME_REG0F4H 0x0F4 +#define AU8522_FRMREGAUPHASE_REG0F7H 0x0F7 #define AU8522_REG0F9H 0x0F9 -#define AU8522_AUDIOAGC2_REG605H 0x605 -#define AU8522_AUDIOFREQ_REG606H 0x606 +#define AU8522_AUDIOAGC2_REG605H 0x605 +#define AU8522_AUDIOFREQ_REG606H 0x606 /**************************************************************/ @@ -356,53 +356,53 @@ int au8522_led_ctrl(struct au8522_state *state, int led); #define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_PAL_M 0x02 -#define AU8522_INPUT_CONTROL_REG081H_ATSC 0xC4 +#define AU8522_INPUT_CONTROL_REG081H_ATSC 0xC4 #define AU8522_INPUT_CONTROL_REG081H_ATVRF 0xC4 #define AU8522_INPUT_CONTROL_REG081H_ATVRF13 0xC4 -#define AU8522_INPUT_CONTROL_REG081H_J83B64 0xC4 -#define AU8522_INPUT_CONTROL_REG081H_J83B256 0xC4 -#define AU8522_INPUT_CONTROL_REG081H_CVBS 0x20 +#define AU8522_INPUT_CONTROL_REG081H_J83B64 0xC4 +#define AU8522_INPUT_CONTROL_REG081H_J83B256 0xC4 +#define AU8522_INPUT_CONTROL_REG081H_CVBS 0x20 #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH1 0xA2 #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH2 0xA0 #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH3 0x69 #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4 0x68 -#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF 0x28 +#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF 0x28 /* CH1 AS Y,CH3 AS C */ -#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 0x23 +#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 0x23 /* CH2 AS Y,CH4 AS C */ -#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24 0x20 -#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATSC 0x0C -#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B64 0x09 -#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B256 0x09 -#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS 0x12 -#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF 0x1A +#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24 0x20 +#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATSC 0x0C +#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B64 0x09 +#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B256 0x09 +#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS 0x12 +#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF 0x1A #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF13 0x1A #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO 0x02 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CLEAR 0x00 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO 0x9C -#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS 0x9D +#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS 0x9D #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATSC 0xE8 -#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B256 0xCA -#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B64 0xCA -#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF 0xDD +#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B256 0xCA +#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B64 0xCA +#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF 0xDD #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF13 0xDD #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_PAL 0xDD #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_FM 0xDD #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATSC 0x80 -#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B256 0x80 -#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B64 0x80 +#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B256 0x80 +#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B64 0x80 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_ATSC 0x40 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B256 0x40 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B64 0x40 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_CLEAR 0x00 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF 0x01 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF13 0x01 -#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_SVIDEO 0x04 +#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_SVIDEO 0x04 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_CVBS 0x01 -#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PWM 0x03 -#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_IIS 0x09 +#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PWM 0x03 +#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_IIS 0x09 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PAL 0x01 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_FM 0x01 diff --git a/drivers/media/dvb-frontends/bcm3510.c b/drivers/media/dvb-frontends/bcm3510.c index ba63ad170d3c..05df133dc5be 100644 --- a/drivers/media/dvb-frontends/bcm3510.c +++ b/drivers/media/dvb-frontends/bcm3510.c @@ -40,7 +40,7 @@ #include <linux/slab.h> #include <linux/mutex.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "bcm3510.h" #include "bcm3510_priv.h" diff --git a/drivers/media/dvb-frontends/cx22700.c b/drivers/media/dvb-frontends/cx22700.c index 2b629e23ceeb..9ffd2c7ac74a 100644 --- a/drivers/media/dvb-frontends/cx22700.c +++ b/drivers/media/dvb-frontends/cx22700.c @@ -25,7 +25,7 @@ #include <linux/module.h> #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "cx22700.h" diff --git a/drivers/media/dvb-frontends/cx22702.c b/drivers/media/dvb-frontends/cx22702.c index c0e54c59cccf..e8b1e6b7e7e5 100644 --- a/drivers/media/dvb-frontends/cx22702.c +++ b/drivers/media/dvb-frontends/cx22702.c @@ -31,7 +31,7 @@ #include <linux/string.h> #include <linux/slab.h> #include <linux/delay.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "cx22702.h" struct cx22702_state { diff --git a/drivers/media/dvb-frontends/cx24110.c b/drivers/media/dvb-frontends/cx24110.c index cf1bc99d1f32..2f3a1c237489 100644 --- a/drivers/media/dvb-frontends/cx24110.c +++ b/drivers/media/dvb-frontends/cx24110.c @@ -27,7 +27,7 @@ #include <linux/module.h> #include <linux/init.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "cx24110.h" diff --git a/drivers/media/dvb-frontends/cx24113.c b/drivers/media/dvb-frontends/cx24113.c index ee1f704f81f2..037db3e9d2dd 100644 --- a/drivers/media/dvb-frontends/cx24113.c +++ b/drivers/media/dvb-frontends/cx24113.c @@ -22,7 +22,7 @@ #include <linux/module.h> #include <linux/init.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "cx24113.h" static int debug; diff --git a/drivers/media/dvb-frontends/cx24116.c b/drivers/media/dvb-frontends/cx24116.c index 8fb3f095e21c..786c56a4ef76 100644 --- a/drivers/media/dvb-frontends/cx24116.c +++ b/drivers/media/dvb-frontends/cx24116.c @@ -41,7 +41,7 @@ #include <linux/init.h> #include <linux/firmware.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "cx24116.h" static int debug; @@ -963,7 +963,7 @@ static int cx24116_send_diseqc_msg(struct dvb_frontend *fe, /* Validate length */ if (d->msg_len > sizeof(d->msg)) - return -EINVAL; + return -EINVAL; /* Dump DiSEqC message */ if (debug) { diff --git a/drivers/media/dvb-frontends/cx24117.c b/drivers/media/dvb-frontends/cx24117.c index d37cb7762bd6..8935114b75f3 100644 --- a/drivers/media/dvb-frontends/cx24117.c +++ b/drivers/media/dvb-frontends/cx24117.c @@ -32,7 +32,7 @@ #include <linux/firmware.h> #include "tuner-i2c.h" -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "cx24117.h" diff --git a/drivers/media/dvb-frontends/cx24120.c b/drivers/media/dvb-frontends/cx24120.c index 7f11dcc94d85..810f68acd69b 100644 --- a/drivers/media/dvb-frontends/cx24120.c +++ b/drivers/media/dvb-frontends/cx24120.c @@ -29,7 +29,7 @@ #include <linux/moduleparam.h> #include <linux/init.h> #include <linux/firmware.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "cx24120.h" #define CX24120_SEARCH_RANGE_KHZ 5000 diff --git a/drivers/media/dvb-frontends/cx24123.c b/drivers/media/dvb-frontends/cx24123.c index 1d59d1d3bd82..228ba1f4bf63 100644 --- a/drivers/media/dvb-frontends/cx24123.c +++ b/drivers/media/dvb-frontends/cx24123.c @@ -24,7 +24,7 @@ #include <linux/init.h> #include <asm/div64.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "cx24123.h" #define XTAL 10111000 diff --git a/drivers/media/dvb-frontends/cxd2820r.h b/drivers/media/dvb-frontends/cxd2820r.h index f3ff8f6eb3bb..a49400c0e28e 100644 --- a/drivers/media/dvb-frontends/cxd2820r.h +++ b/drivers/media/dvb-frontends/cxd2820r.h @@ -49,7 +49,6 @@ * @gpio_chip_base: GPIO. * @get_dvb_frontend: Get DVB frontend. */ - struct cxd2820r_platform_data { u8 ts_mode; bool ts_clk_inv; @@ -62,6 +61,17 @@ struct cxd2820r_platform_data { bool attach_in_use; }; +/** + * struct cxd2820r_config - configuration for cxd2020r demod + * + * @i2c_address: Demodulator I2C address. Driver determines DVB-C slave I2C + * address automatically from master address. + * Default: none, must set. Values: 0x6c, 0x6d. + * @ts_mode: TS output mode. Default: none, must set. Values: FIXME? + * @ts_clock_inv: TS clock inverted. Default: 0. Values: 0, 1. + * @if_agc_polarity: Default: 0. Values: 0, 1 + * @spec_inv: Spectrum inversion. Default: 0. Values: 0, 1. + */ struct cxd2820r_config { /* Demodulator I2C address. * Driver determines DVB-C slave I2C address automatically from master @@ -98,6 +108,18 @@ struct cxd2820r_config { #if IS_REACHABLE(CONFIG_DVB_CXD2820R) +/** + * Attach a cxd2820r demod + * + * @config: pointer to &struct cxd2820r_config with demod configuration. + * @i2c: i2c adapter to use. + * @gpio_chip_base: if zero, disables GPIO setting. Otherwise, if + * CONFIG_GPIOLIB is set dynamically allocate + * gpio base; if is not set, use its value to + * setup the GPIO pins. + * + * return: FE pointer on success, NULL on failure. + */ extern struct dvb_frontend *cxd2820r_attach( const struct cxd2820r_config *config, struct i2c_adapter *i2c, diff --git a/drivers/media/dvb-frontends/cxd2820r_priv.h b/drivers/media/dvb-frontends/cxd2820r_priv.h index 0d096206ac66..61adde4b4b2f 100644 --- a/drivers/media/dvb-frontends/cxd2820r_priv.h +++ b/drivers/media/dvb-frontends/cxd2820r_priv.h @@ -23,8 +23,8 @@ #define CXD2820R_PRIV_H #include <linux/dvb/version.h> -#include "dvb_frontend.h" -#include "dvb_math.h" +#include <media/dvb_frontend.h> +#include <media/dvb_math.h> #include "cxd2820r.h" #include <linux/gpio.h> #include <linux/math64.h> diff --git a/drivers/media/dvb-frontends/cxd2841er.c b/drivers/media/dvb-frontends/cxd2841er.c index 48ee9bc00c06..85905d3503ff 100644 --- a/drivers/media/dvb-frontends/cxd2841er.c +++ b/drivers/media/dvb-frontends/cxd2841er.c @@ -29,9 +29,10 @@ #include <linux/math64.h> #include <linux/log2.h> #include <linux/dynamic_debug.h> +#include <linux/kernel.h> -#include "dvb_math.h" -#include "dvb_frontend.h" +#include <media/dvb_math.h> +#include <media/dvb_frontend.h> #include "cxd2841er.h" #include "cxd2841er_priv.h" @@ -257,7 +258,9 @@ static int cxd2841er_write_regs(struct cxd2841er_priv *priv, static int cxd2841er_write_reg(struct cxd2841er_priv *priv, u8 addr, u8 reg, u8 val) { - return cxd2841er_write_regs(priv, addr, reg, &val, 1); + u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ + + return cxd2841er_write_regs(priv, addr, reg, &tmp, 1); } static int cxd2841er_read_regs(struct cxd2841er_priv *priv, @@ -1696,12 +1699,10 @@ static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv, min_index = 0; if (delsys == SYS_DVBS) { cn_data = s_cn_data; - max_index = sizeof(s_cn_data) / - sizeof(s_cn_data[0]) - 1; + max_index = ARRAY_SIZE(s_cn_data) - 1; } else { cn_data = s2_cn_data; - max_index = sizeof(s2_cn_data) / - sizeof(s2_cn_data[0]) - 1; + max_index = ARRAY_SIZE(s2_cn_data) - 1; } if (value >= cn_data[min_index].value) { res = cn_data[min_index].cnr_x1000; @@ -3340,13 +3341,17 @@ static int cxd2841er_set_frontend_s(struct dvb_frontend *fe) cxd2841er_tune_done(priv); timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150; - for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) { + + i = 0; + do { usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000, (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000); cxd2841er_read_status_s(fe, &status); if (status & FE_HAS_LOCK) break; - } + i++; + } while (i < timeout / CXD2841ER_DVBS_POLLING_INVL); + if (status & FE_HAS_LOCK) { if (cxd2841er_get_carrier_offset_s_s2( priv, &carr_offset)) { diff --git a/drivers/media/dvb-frontends/dib0070.c b/drivers/media/dvb-frontends/dib0070.c index d7614b8b8782..932d235118e2 100644 --- a/drivers/media/dvb-frontends/dib0070.c +++ b/drivers/media/dvb-frontends/dib0070.c @@ -27,7 +27,7 @@ #include <linux/i2c.h> #include <linux/mutex.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "dib0070.h" #include "dibx000_common.h" diff --git a/drivers/media/dvb-frontends/dib0090.c b/drivers/media/dvb-frontends/dib0090.c index d9d730dfe0b1..64f49c8eb1fb 100644 --- a/drivers/media/dvb-frontends/dib0090.c +++ b/drivers/media/dvb-frontends/dib0090.c @@ -27,7 +27,7 @@ #include <linux/i2c.h> #include <linux/mutex.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "dib0090.h" #include "dibx000_common.h" diff --git a/drivers/media/dvb-frontends/dib3000mb.c b/drivers/media/dvb-frontends/dib3000mb.c index 068bec104e29..de3ce2786c72 100644 --- a/drivers/media/dvb-frontends/dib3000mb.c +++ b/drivers/media/dvb-frontends/dib3000mb.c @@ -30,7 +30,7 @@ #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "dib3000.h" #include "dib3000mb_priv.h" diff --git a/drivers/media/dvb-frontends/dib3000mc.c b/drivers/media/dvb-frontends/dib3000mc.c index 4d086a7248e9..7e5d474806a5 100644 --- a/drivers/media/dvb-frontends/dib3000mc.c +++ b/drivers/media/dvb-frontends/dib3000mc.c @@ -17,7 +17,7 @@ #include <linux/slab.h> #include <linux/i2c.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "dib3000mc.h" diff --git a/drivers/media/dvb-frontends/dib7000m.c b/drivers/media/dvb-frontends/dib7000m.c index 5ce9f93a65c3..6a1d357d0c7c 100644 --- a/drivers/media/dvb-frontends/dib7000m.c +++ b/drivers/media/dvb-frontends/dib7000m.c @@ -16,7 +16,7 @@ #include <linux/i2c.h> #include <linux/mutex.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "dib7000m.h" diff --git a/drivers/media/dvb-frontends/dib7000p.c b/drivers/media/dvb-frontends/dib7000p.c index 0fbaabe43682..90ace707a80d 100644 --- a/drivers/media/dvb-frontends/dib7000p.c +++ b/drivers/media/dvb-frontends/dib7000p.c @@ -16,8 +16,8 @@ #include <linux/mutex.h> #include <asm/div64.h> -#include "dvb_math.h" -#include "dvb_frontend.h" +#include <media/dvb_math.h> +#include <media/dvb_frontend.h> #include "dib7000p.h" diff --git a/drivers/media/dvb-frontends/dib8000.c b/drivers/media/dvb-frontends/dib8000.c index 5d9381509b07..e64014f338fb 100644 --- a/drivers/media/dvb-frontends/dib8000.c +++ b/drivers/media/dvb-frontends/dib8000.c @@ -16,9 +16,9 @@ #include <linux/mutex.h> #include <asm/div64.h> -#include "dvb_math.h" +#include <media/dvb_math.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "dib8000.h" diff --git a/drivers/media/dvb-frontends/dib9000.c b/drivers/media/dvb-frontends/dib9000.c index 1b7a4331af05..f9289f488de7 100644 --- a/drivers/media/dvb-frontends/dib9000.c +++ b/drivers/media/dvb-frontends/dib9000.c @@ -14,8 +14,8 @@ #include <linux/i2c.h> #include <linux/mutex.h> -#include "dvb_math.h" -#include "dvb_frontend.h" +#include <media/dvb_math.h> +#include <media/dvb_frontend.h> #include "dib9000.h" #include "dibx000_common.h" diff --git a/drivers/media/dvb-frontends/dibx000_common.c b/drivers/media/dvb-frontends/dibx000_common.c index bc28184c7fb0..d981233e458f 100644 --- a/drivers/media/dvb-frontends/dibx000_common.c +++ b/drivers/media/dvb-frontends/dibx000_common.c @@ -288,8 +288,8 @@ static int dibx000_i2c_gated_gpio67_xfer(struct i2c_adapter *i2c_adap, int ret; if (num > 32) { - dprintk("%s: too much I2C message to be transmitted (%i).\ - Maximum is 32", __func__, num); + dprintk("%s: too much I2C message to be transmitted (%i). Maximum is 32", + __func__, num); return -ENOMEM; } @@ -335,8 +335,8 @@ static int dibx000_i2c_gated_tuner_xfer(struct i2c_adapter *i2c_adap, int ret; if (num > 32) { - dprintk("%s: too much I2C message to be transmitted (%i).\ - Maximum is 32", __func__, num); + dprintk("%s: too much I2C message to be transmitted (%i). Maximum is 32", + __func__, num); return -ENOMEM; } diff --git a/drivers/media/dvb-frontends/drx39xyj/Makefile b/drivers/media/dvb-frontends/drx39xyj/Makefile index 672e07774955..87f6eddcf657 100644 --- a/drivers/media/dvb-frontends/drx39xyj/Makefile +++ b/drivers/media/dvb-frontends/drx39xyj/Makefile @@ -2,5 +2,4 @@ drx39xyj-objs := drxj.o obj-$(CONFIG_DVB_DRX39XYJ) += drx39xyj.o -ccflags-y += -I$(srctree)/drivers/media/dvb-core/ ccflags-y += -I$(srctree)/drivers/media/tuners/ diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h index 5b5421f70388..2b3af247a1f1 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h @@ -52,7 +52,7 @@ struct i2c_device_addr { }; -/** +/* * \def IS_I2C_10BIT( addr ) * \brief Determine if I2C address 'addr' is a 10 bits address or not. * \param addr The I2C address. @@ -67,7 +67,7 @@ struct i2c_device_addr { Exported FUNCTIONS ------------------------------------------------------------------------------*/ -/** +/* * \fn drxbsp_i2c_init() * \brief Initialize I2C communication module. * \return drx_status_t Return status. @@ -76,7 +76,7 @@ Exported FUNCTIONS */ drx_status_t drxbsp_i2c_init(void); -/** +/* * \fn drxbsp_i2c_term() * \brief Terminate I2C communication module. * \return drx_status_t Return status. @@ -85,7 +85,7 @@ Exported FUNCTIONS */ drx_status_t drxbsp_i2c_term(void); -/** +/* * \fn drx_status_t drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr, * u16 w_count, * u8 *wData, @@ -121,7 +121,7 @@ Exported FUNCTIONS struct i2c_device_addr *r_dev_addr, u16 r_count, u8 *r_data); -/** +/* * \fn drxbsp_i2c_error_text() * \brief Returns a human readable error. * Counter part of numerical drx_i2c_error_g. @@ -130,7 +130,7 @@ Exported FUNCTIONS */ char *drxbsp_i2c_error_text(void); -/** +/* * \var drx_i2c_error_g; * \brief I2C specific error codes, platform dependent. */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h index 11e1ddeeef0a..c0c66ed65b6e 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h @@ -19,7 +19,7 @@ #define DRX39XXJ_H #include <linux/dvb/frontend.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "drx_driver.h" struct drx39xxj_state { diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index cd69e187ba7a..1ec20eecc433 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -46,7 +46,7 @@ struct i2c_device_addr { void *user_data; /* User data pointer */ }; -/** +/* * \def IS_I2C_10BIT( addr ) * \brief Determine if I2C address 'addr' is a 10 bits address or not. * \param addr The I2C address. @@ -61,7 +61,7 @@ struct i2c_device_addr { Exported FUNCTIONS ------------------------------------------------------------------------------*/ -/** +/* * \fn drxbsp_i2c_init() * \brief Initialize I2C communication module. * \return int Return status. @@ -70,7 +70,7 @@ Exported FUNCTIONS */ int drxbsp_i2c_init(void); -/** +/* * \fn drxbsp_i2c_term() * \brief Terminate I2C communication module. * \return int Return status. @@ -79,7 +79,7 @@ int drxbsp_i2c_init(void); */ int drxbsp_i2c_term(void); -/** +/* * \fn int drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr, * u16 w_count, * u8 * wData, @@ -115,7 +115,7 @@ int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, struct i2c_device_addr *r_dev_addr, u16 r_count, u8 *r_data); -/** +/* * \fn drxbsp_i2c_error_text() * \brief Returns a human readable error. * Counter part of numerical drx_i2c_error_g. @@ -124,7 +124,7 @@ int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, */ char *drxbsp_i2c_error_text(void); -/** +/* * \var drx_i2c_error_g; * \brief I2C specific error codes, platform dependent. */ @@ -241,13 +241,13 @@ int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, struct i2c_device_addr *r_dev_addr, u16 r_count, u8 *r_data); -/************** +/************* * * This section configures the DRX Data Access Protocols (DAPs). * **************/ -/** +/* * \def DRXDAP_SINGLE_MASTER * \brief Enable I2C single or I2C multimaster mode on host. * @@ -262,7 +262,7 @@ int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, #define DRXDAP_SINGLE_MASTER 1 #endif -/** +/* * \def DRXDAP_MAX_WCHUNKSIZE * \brief Defines maximum chunksize of an i2c write action by host. * @@ -282,7 +282,7 @@ int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, #define DRXDAP_MAX_WCHUNKSIZE 60 #endif -/** +/* * \def DRXDAP_MAX_RCHUNKSIZE * \brief Defines maximum chunksize of an i2c read action by host. * @@ -297,13 +297,13 @@ int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, #define DRXDAP_MAX_RCHUNKSIZE 60 #endif -/************** +/************* * * This section describes drxdriver defines. * **************/ -/** +/* * \def DRX_UNKNOWN * \brief Generic UNKNOWN value for DRX enumerated types. * @@ -313,7 +313,7 @@ int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, #define DRX_UNKNOWN (254) #endif -/** +/* * \def DRX_AUTO * \brief Generic AUTO value for DRX enumerated types. * @@ -324,104 +324,104 @@ int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, #define DRX_AUTO (255) #endif -/************** +/************* * * This section describes flag definitions for the device capbilities. * **************/ -/** +/* * \brief LNA capability flag * * Device has a Low Noise Amplifier * */ #define DRX_CAPABILITY_HAS_LNA (1UL << 0) -/** +/* * \brief OOB-RX capability flag * * Device has OOB-RX * */ #define DRX_CAPABILITY_HAS_OOBRX (1UL << 1) -/** +/* * \brief ATV capability flag * * Device has ATV * */ #define DRX_CAPABILITY_HAS_ATV (1UL << 2) -/** +/* * \brief DVB-T capability flag * * Device has DVB-T * */ #define DRX_CAPABILITY_HAS_DVBT (1UL << 3) -/** +/* * \brief ITU-B capability flag * * Device has ITU-B * */ #define DRX_CAPABILITY_HAS_ITUB (1UL << 4) -/** +/* * \brief Audio capability flag * * Device has Audio * */ #define DRX_CAPABILITY_HAS_AUD (1UL << 5) -/** +/* * \brief SAW switch capability flag * * Device has SAW switch * */ #define DRX_CAPABILITY_HAS_SAWSW (1UL << 6) -/** +/* * \brief GPIO1 capability flag * * Device has GPIO1 * */ #define DRX_CAPABILITY_HAS_GPIO1 (1UL << 7) -/** +/* * \brief GPIO2 capability flag * * Device has GPIO2 * */ #define DRX_CAPABILITY_HAS_GPIO2 (1UL << 8) -/** +/* * \brief IRQN capability flag * * Device has IRQN * */ #define DRX_CAPABILITY_HAS_IRQN (1UL << 9) -/** +/* * \brief 8VSB capability flag * * Device has 8VSB * */ #define DRX_CAPABILITY_HAS_8VSB (1UL << 10) -/** +/* * \brief SMA-TX capability flag * * Device has SMATX * */ #define DRX_CAPABILITY_HAS_SMATX (1UL << 11) -/** +/* * \brief SMA-RX capability flag * * Device has SMARX * */ #define DRX_CAPABILITY_HAS_SMARX (1UL << 12) -/** +/* * \brief ITU-A/C capability flag * * Device has ITU-A/C @@ -439,7 +439,7 @@ MACROS DRX_VERSIONSTRING_HELP(PATCH) #define DRX_VERSIONSTRING_HELP(NUM) #NUM -/** +/* * \brief Macro to create byte array elements from 16 bit integers. * This macro is used to create byte arrays for block writes. * Block writes speed up I2C traffic between host and demod. @@ -449,7 +449,7 @@ MACROS #define DRX_16TO8(x) ((u8) (((u16)x) & 0xFF)), \ ((u8)((((u16)x)>>8)&0xFF)) -/** +/* * \brief Macro to convert 16 bit register value to a s32 */ #define DRX_U16TODRXFREQ(x) ((x & 0x8000) ? \ @@ -461,191 +461,191 @@ MACROS ENUM -------------------------------------------------------------------------*/ -/** +/* * \enum enum drx_standard * \brief Modulation standards. */ enum drx_standard { - DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */ - DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */ - DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */ + DRX_STANDARD_DVBT = 0, /*< Terrestrial DVB-T. */ + DRX_STANDARD_8VSB, /*< Terrestrial 8VSB. */ + DRX_STANDARD_NTSC, /*< Terrestrial\Cable analog NTSC. */ DRX_STANDARD_PAL_SECAM_BG, - /**< Terrestrial analog PAL/SECAM B/G */ + /*< Terrestrial analog PAL/SECAM B/G */ DRX_STANDARD_PAL_SECAM_DK, - /**< Terrestrial analog PAL/SECAM D/K */ + /*< Terrestrial analog PAL/SECAM D/K */ DRX_STANDARD_PAL_SECAM_I, - /**< Terrestrial analog PAL/SECAM I */ + /*< Terrestrial analog PAL/SECAM I */ DRX_STANDARD_PAL_SECAM_L, - /**< Terrestrial analog PAL/SECAM L + /*< Terrestrial analog PAL/SECAM L with negative modulation */ DRX_STANDARD_PAL_SECAM_LP, - /**< Terrestrial analog PAL/SECAM L + /*< Terrestrial analog PAL/SECAM L with positive modulation */ - DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */ - DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */ - DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */ - DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */ - DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */ - DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/ + DRX_STANDARD_ITU_A, /*< Cable ITU ANNEX A. */ + DRX_STANDARD_ITU_B, /*< Cable ITU ANNEX B. */ + DRX_STANDARD_ITU_C, /*< Cable ITU ANNEX C. */ + DRX_STANDARD_ITU_D, /*< Cable ITU ANNEX D. */ + DRX_STANDARD_FM, /*< Terrestrial\Cable FM radio */ + DRX_STANDARD_DTMB, /*< Terrestrial DTMB standard (China)*/ DRX_STANDARD_UNKNOWN = DRX_UNKNOWN, - /**< Standard unknown. */ + /*< Standard unknown. */ DRX_STANDARD_AUTO = DRX_AUTO - /**< Autodetect standard. */ + /*< Autodetect standard. */ }; -/** +/* * \enum enum drx_standard * \brief Modulation sub-standards. */ enum drx_substandard { - DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */ + DRX_SUBSTANDARD_MAIN = 0, /*< Main subvariant of standard */ DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA, DRX_SUBSTANDARD_ATV_DK_POLAND, DRX_SUBSTANDARD_ATV_DK_CHINA, DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN, - /**< Sub-standard unknown. */ + /*< Sub-standard unknown. */ DRX_SUBSTANDARD_AUTO = DRX_AUTO - /**< Auto (default) sub-standard */ + /*< Auto (default) sub-standard */ }; -/** +/* * \enum enum drx_bandwidth * \brief Channel bandwidth or channel spacing. */ enum drx_bandwidth { - DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */ - DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */ - DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */ + DRX_BANDWIDTH_8MHZ = 0, /*< Bandwidth 8 MHz. */ + DRX_BANDWIDTH_7MHZ, /*< Bandwidth 7 MHz. */ + DRX_BANDWIDTH_6MHZ, /*< Bandwidth 6 MHz. */ DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN, - /**< Bandwidth unknown. */ + /*< Bandwidth unknown. */ DRX_BANDWIDTH_AUTO = DRX_AUTO - /**< Auto Set Bandwidth */ + /*< Auto Set Bandwidth */ }; -/** +/* * \enum enum drx_mirror * \brief Indicate if channel spectrum is mirrored or not. */ enum drx_mirror { - DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */ - DRX_MIRROR_YES, /**< Spectrum is mirrored. */ + DRX_MIRROR_NO = 0, /*< Spectrum is not mirrored. */ + DRX_MIRROR_YES, /*< Spectrum is mirrored. */ DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, - /**< Unknown if spectrum is mirrored. */ + /*< Unknown if spectrum is mirrored. */ DRX_MIRROR_AUTO = DRX_AUTO - /**< Autodetect if spectrum is mirrored. */ + /*< Autodetect if spectrum is mirrored. */ }; -/** +/* * \enum enum drx_modulation * \brief Constellation type of the channel. */ enum drx_modulation { - DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */ - DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */ - DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */ - DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */ - DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */ - DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */ - DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */ - DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */ - DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */ - DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */ - DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */ + DRX_CONSTELLATION_BPSK = 0, /*< Modulation is BPSK. */ + DRX_CONSTELLATION_QPSK, /*< Constellation is QPSK. */ + DRX_CONSTELLATION_PSK8, /*< Constellation is PSK8. */ + DRX_CONSTELLATION_QAM16, /*< Constellation is QAM16. */ + DRX_CONSTELLATION_QAM32, /*< Constellation is QAM32. */ + DRX_CONSTELLATION_QAM64, /*< Constellation is QAM64. */ + DRX_CONSTELLATION_QAM128, /*< Constellation is QAM128. */ + DRX_CONSTELLATION_QAM256, /*< Constellation is QAM256. */ + DRX_CONSTELLATION_QAM512, /*< Constellation is QAM512. */ + DRX_CONSTELLATION_QAM1024, /*< Constellation is QAM1024. */ + DRX_CONSTELLATION_QPSK_NR, /*< Constellation is QPSK_NR */ DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, - /**< Constellation unknown. */ + /*< Constellation unknown. */ DRX_CONSTELLATION_AUTO = DRX_AUTO - /**< Autodetect constellation. */ + /*< Autodetect constellation. */ }; -/** +/* * \enum enum drx_hierarchy * \brief Hierarchy of the channel. */ enum drx_hierarchy { - DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */ - DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */ - DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */ - DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */ + DRX_HIERARCHY_NONE = 0, /*< None hierarchical channel. */ + DRX_HIERARCHY_ALPHA1, /*< Hierarchical channel, alpha=1. */ + DRX_HIERARCHY_ALPHA2, /*< Hierarchical channel, alpha=2. */ + DRX_HIERARCHY_ALPHA4, /*< Hierarchical channel, alpha=4. */ DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN, - /**< Hierarchy unknown. */ + /*< Hierarchy unknown. */ DRX_HIERARCHY_AUTO = DRX_AUTO - /**< Autodetect hierarchy. */ + /*< Autodetect hierarchy. */ }; -/** +/* * \enum enum drx_priority * \brief Channel priority in case of hierarchical transmission. */ enum drx_priority { - DRX_PRIORITY_LOW = 0, /**< Low priority channel. */ - DRX_PRIORITY_HIGH, /**< High priority channel. */ + DRX_PRIORITY_LOW = 0, /*< Low priority channel. */ + DRX_PRIORITY_HIGH, /*< High priority channel. */ DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN - /**< Priority unknown. */ + /*< Priority unknown. */ }; -/** +/* * \enum enum drx_coderate * \brief Channel priority in case of hierarchical transmission. */ enum drx_coderate { - DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */ - DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */ - DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */ - DRX_CODERATE_5DIV6, /**< Code rate 5/6nd. */ - DRX_CODERATE_7DIV8, /**< Code rate 7/8nd. */ + DRX_CODERATE_1DIV2 = 0, /*< Code rate 1/2nd. */ + DRX_CODERATE_2DIV3, /*< Code rate 2/3nd. */ + DRX_CODERATE_3DIV4, /*< Code rate 3/4nd. */ + DRX_CODERATE_5DIV6, /*< Code rate 5/6nd. */ + DRX_CODERATE_7DIV8, /*< Code rate 7/8nd. */ DRX_CODERATE_UNKNOWN = DRX_UNKNOWN, - /**< Code rate unknown. */ + /*< Code rate unknown. */ DRX_CODERATE_AUTO = DRX_AUTO - /**< Autodetect code rate. */ + /*< Autodetect code rate. */ }; -/** +/* * \enum enum drx_guard * \brief Guard interval of a channel. */ enum drx_guard { - DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */ - DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */ - DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */ - DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */ + DRX_GUARD_1DIV32 = 0, /*< Guard interval 1/32nd. */ + DRX_GUARD_1DIV16, /*< Guard interval 1/16th. */ + DRX_GUARD_1DIV8, /*< Guard interval 1/8th. */ + DRX_GUARD_1DIV4, /*< Guard interval 1/4th. */ DRX_GUARD_UNKNOWN = DRX_UNKNOWN, - /**< Guard interval unknown. */ + /*< Guard interval unknown. */ DRX_GUARD_AUTO = DRX_AUTO - /**< Autodetect guard interval. */ + /*< Autodetect guard interval. */ }; -/** +/* * \enum enum drx_fft_mode * \brief FFT mode. */ enum drx_fft_mode { - DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */ - DRX_FFTMODE_4K, /**< 4K FFT mode. */ - DRX_FFTMODE_8K, /**< 8K FFT mode. */ + DRX_FFTMODE_2K = 0, /*< 2K FFT mode. */ + DRX_FFTMODE_4K, /*< 4K FFT mode. */ + DRX_FFTMODE_8K, /*< 8K FFT mode. */ DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, - /**< FFT mode unknown. */ + /*< FFT mode unknown. */ DRX_FFTMODE_AUTO = DRX_AUTO - /**< Autodetect FFT mode. */ + /*< Autodetect FFT mode. */ }; -/** +/* * \enum enum drx_classification * \brief Channel classification. */ enum drx_classification { - DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */ - DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */ - DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */ - DRX_CLASSIFICATION_STATIC, /**< Static echo. */ - DRX_CLASSIFICATION_MOVING, /**< Moving echo. */ - DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */ + DRX_CLASSIFICATION_GAUSS = 0, /*< Gaussion noise. */ + DRX_CLASSIFICATION_HVY_GAUSS, /*< Heavy Gaussion noise. */ + DRX_CLASSIFICATION_COCHANNEL, /*< Co-channel. */ + DRX_CLASSIFICATION_STATIC, /*< Static echo. */ + DRX_CLASSIFICATION_MOVING, /*< Moving echo. */ + DRX_CLASSIFICATION_ZERODB, /*< Zero dB echo. */ DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN, - /**< Unknown classification */ + /*< Unknown classification */ DRX_CLASSIFICATION_AUTO = DRX_AUTO - /**< Autodetect classification. */ + /*< Autodetect classification. */ }; -/** +/* * /enum enum drx_interleave_mode * /brief Interleave modes */ @@ -673,80 +673,80 @@ enum drx_interleave_mode { DRX_INTERLEAVEMODE_B52_M48, DRX_INTERLEAVEMODE_B52_M0, DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN, - /**< Unknown interleave mode */ + /*< Unknown interleave mode */ DRX_INTERLEAVEMODE_AUTO = DRX_AUTO - /**< Autodetect interleave mode */ + /*< Autodetect interleave mode */ }; -/** +/* * \enum enum drx_carrier_mode * \brief Channel Carrier Mode. */ enum drx_carrier_mode { - DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */ - DRX_CARRIER_SINGLE, /**< Single carrier mode */ + DRX_CARRIER_MULTI = 0, /*< Multi carrier mode */ + DRX_CARRIER_SINGLE, /*< Single carrier mode */ DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, - /**< Carrier mode unknown. */ - DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */ + /*< Carrier mode unknown. */ + DRX_CARRIER_AUTO = DRX_AUTO /*< Autodetect carrier mode */ }; -/** +/* * \enum enum drx_frame_mode * \brief Channel Frame Mode. */ enum drx_frame_mode { - DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */ - DRX_FRAMEMODE_595, /**< 595 */ - DRX_FRAMEMODE_945, /**< 945 with variable PN */ + DRX_FRAMEMODE_420 = 0, /*< 420 with variable PN */ + DRX_FRAMEMODE_595, /*< 595 */ + DRX_FRAMEMODE_945, /*< 945 with variable PN */ DRX_FRAMEMODE_420_FIXED_PN, - /**< 420 with fixed PN */ + /*< 420 with fixed PN */ DRX_FRAMEMODE_945_FIXED_PN, - /**< 945 with fixed PN */ + /*< 945 with fixed PN */ DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN, - /**< Frame mode unknown. */ + /*< Frame mode unknown. */ DRX_FRAMEMODE_AUTO = DRX_AUTO - /**< Autodetect frame mode */ + /*< Autodetect frame mode */ }; -/** +/* * \enum enum drx_tps_frame * \brief Frame number in current super-frame. */ enum drx_tps_frame { - DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */ - DRX_TPS_FRAME2, /**< TPS frame 2. */ - DRX_TPS_FRAME3, /**< TPS frame 3. */ - DRX_TPS_FRAME4, /**< TPS frame 4. */ + DRX_TPS_FRAME1 = 0, /*< TPS frame 1. */ + DRX_TPS_FRAME2, /*< TPS frame 2. */ + DRX_TPS_FRAME3, /*< TPS frame 3. */ + DRX_TPS_FRAME4, /*< TPS frame 4. */ DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN - /**< TPS frame unknown. */ + /*< TPS frame unknown. */ }; -/** +/* * \enum enum drx_ldpc * \brief TPS LDPC . */ enum drx_ldpc { - DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */ - DRX_LDPC_0_6, /**< LDPC 0.6 */ - DRX_LDPC_0_8, /**< LDPC 0.8 */ + DRX_LDPC_0_4 = 0, /*< LDPC 0.4 */ + DRX_LDPC_0_6, /*< LDPC 0.6 */ + DRX_LDPC_0_8, /*< LDPC 0.8 */ DRX_LDPC_UNKNOWN = DRX_UNKNOWN, - /**< LDPC unknown. */ - DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */ + /*< LDPC unknown. */ + DRX_LDPC_AUTO = DRX_AUTO /*< Autodetect LDPC */ }; -/** +/* * \enum enum drx_pilot_mode * \brief Pilot modes in DTMB. */ enum drx_pilot_mode { - DRX_PILOT_ON = 0, /**< Pilot On */ - DRX_PILOT_OFF, /**< Pilot Off */ + DRX_PILOT_ON = 0, /*< Pilot On */ + DRX_PILOT_OFF, /*< Pilot Off */ DRX_PILOT_UNKNOWN = DRX_UNKNOWN, - /**< Pilot unknown. */ - DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */ + /*< Pilot unknown. */ + DRX_PILOT_AUTO = DRX_AUTO /*< Autodetect Pilot */ }; -/** +/* * enum drxu_code_action - indicate if firmware has to be uploaded or verified. * @UCODE_UPLOAD: Upload the microcode image to device * @UCODE_VERIFY: Compare microcode image with code on device @@ -756,7 +756,7 @@ enum drxu_code_action { UCODE_VERIFY }; -/** +/* * \enum enum drx_lock_status * \brief Used to reflect current lock status of demodulator. * * The generic lock states have device dependent semantics. @@ -801,7 +801,7 @@ enum drx_lock_status { DRX_LOCKED }; -/** +/* * \enum enum drx_uio* \brief Used to address a User IO (UIO). */ enum drx_uio { @@ -840,7 +840,7 @@ enum drx_uio { DRX_UIO_MAX = DRX_UIO32 }; -/** +/* * \enum enum drxuio_mode * \brief Used to configure the modus oprandi of a UIO. * * DRX_UIO_MODE_FIRMWARE is an old uio mode. @@ -850,37 +850,37 @@ enum drx_uio { */ enum drxuio_mode { DRX_UIO_MODE_DISABLE = 0x01, - /**< not used, pin is configured as input */ + /*< not used, pin is configured as input */ DRX_UIO_MODE_READWRITE = 0x02, - /**< used for read/write by application */ + /*< used for read/write by application */ DRX_UIO_MODE_FIRMWARE = 0x04, - /**< controlled by firmware, function 0 */ + /*< controlled by firmware, function 0 */ DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE, - /**< same as above */ + /*< same as above */ DRX_UIO_MODE_FIRMWARE1 = 0x08, - /**< controlled by firmware, function 1 */ + /*< controlled by firmware, function 1 */ DRX_UIO_MODE_FIRMWARE2 = 0x10, - /**< controlled by firmware, function 2 */ + /*< controlled by firmware, function 2 */ DRX_UIO_MODE_FIRMWARE3 = 0x20, - /**< controlled by firmware, function 3 */ + /*< controlled by firmware, function 3 */ DRX_UIO_MODE_FIRMWARE4 = 0x40, - /**< controlled by firmware, function 4 */ + /*< controlled by firmware, function 4 */ DRX_UIO_MODE_FIRMWARE5 = 0x80 - /**< controlled by firmware, function 5 */ + /*< controlled by firmware, function 5 */ }; -/** +/* * \enum enum drxoob_downstream_standard * \brief Used to select OOB standard. * * Based on ANSI 55-1 and 55-2 */ enum drxoob_downstream_standard { DRX_OOB_MODE_A = 0, - /**< ANSI 55-1 */ + /*< ANSI 55-1 */ DRX_OOB_MODE_B_GRADE_A, - /**< ANSI 55-2 A */ + /*< ANSI 55-2 A */ DRX_OOB_MODE_B_GRADE_B - /**< ANSI 55-2 B */ + /*< ANSI 55-2 B */ }; /*------------------------------------------------------------------------- @@ -924,7 +924,7 @@ STRUCTS /*============================================================================*/ /*============================================================================*/ -/** +/* * struct drxu_code_info Parameters for microcode upload and verfiy. * * @mc_file: microcode file name @@ -932,10 +932,10 @@ STRUCTS * Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE */ struct drxu_code_info { - char *mc_file; + char *mc_file; }; -/** +/* * \struct drx_mc_version_rec_t * \brief Microcode version record * Version numbers are stored in BCD format, as usual: @@ -963,7 +963,7 @@ struct drx_mc_version_rec { /*========================================*/ -/** +/* * \struct drx_filter_info_t * \brief Parameters for loading filter coefficients * @@ -971,18 +971,18 @@ struct drx_mc_version_rec { */ struct drx_filter_info { u8 *data_re; - /**< pointer to coefficients for RE */ + /*< pointer to coefficients for RE */ u8 *data_im; - /**< pointer to coefficients for IM */ + /*< pointer to coefficients for IM */ u16 size_re; - /**< size of coefficients for RE */ + /*< size of coefficients for RE */ u16 size_im; - /**< size of coefficients for IM */ + /*< size of coefficients for IM */ }; /*========================================*/ -/** +/* * \struct struct drx_channel * \brief The set of parameters describing a single channel. * * Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL. @@ -991,29 +991,29 @@ struct drx_filter_info { */ struct drx_channel { s32 frequency; - /**< frequency in kHz */ + /*< frequency in kHz */ enum drx_bandwidth bandwidth; - /**< bandwidth */ - enum drx_mirror mirror; /**< mirrored or not on RF */ + /*< bandwidth */ + enum drx_mirror mirror; /*< mirrored or not on RF */ enum drx_modulation constellation; - /**< constellation */ + /*< constellation */ enum drx_hierarchy hierarchy; - /**< hierarchy */ - enum drx_priority priority; /**< priority */ - enum drx_coderate coderate; /**< coderate */ - enum drx_guard guard; /**< guard interval */ - enum drx_fft_mode fftmode; /**< fftmode */ + /*< hierarchy */ + enum drx_priority priority; /*< priority */ + enum drx_coderate coderate; /*< coderate */ + enum drx_guard guard; /*< guard interval */ + enum drx_fft_mode fftmode; /*< fftmode */ enum drx_classification classification; - /**< classification */ + /*< classification */ u32 symbolrate; - /**< symbolrate in symbols/sec */ + /*< symbolrate in symbols/sec */ enum drx_interleave_mode interleavemode; - /**< interleaveMode QAM */ - enum drx_ldpc ldpc; /**< ldpc */ - enum drx_carrier_mode carrier; /**< carrier */ + /*< interleaveMode QAM */ + enum drx_ldpc ldpc; /*< ldpc */ + enum drx_carrier_mode carrier; /*< carrier */ enum drx_frame_mode framemode; - /**< frame mode */ - enum drx_pilot_mode pilot; /**< pilot mode */ + /*< frame mode */ + enum drx_pilot_mode pilot; /*< pilot mode */ }; /*========================================*/ @@ -1027,74 +1027,74 @@ enum drx_cfg_sqi_speed { /*========================================*/ -/** +/* * \struct struct drx_complex * A complex number. * * Used by DRX_CTRL_CONSTEL. */ struct drx_complex { s16 im; - /**< Imaginary part. */ + /*< Imaginary part. */ s16 re; - /**< Real part. */ + /*< Real part. */ }; /*========================================*/ -/** +/* * \struct struct drx_frequency_plan * Array element of a frequency plan. * * Used by DRX_CTRL_SCAN_INIT. */ struct drx_frequency_plan { s32 first; - /**< First centre frequency in this band */ + /*< First centre frequency in this band */ s32 last; - /**< Last centre frequency in this band */ + /*< Last centre frequency in this band */ s32 step; - /**< Stepping frequency in this band */ + /*< Stepping frequency in this band */ enum drx_bandwidth bandwidth; - /**< Bandwidth within this frequency band */ + /*< Bandwidth within this frequency band */ u16 ch_number; - /**< First channel number in this band, or first + /*< First channel number in this band, or first index in ch_names */ char **ch_names; - /**< Optional list of channel names in this + /*< Optional list of channel names in this band */ }; /*========================================*/ -/** +/* * \struct struct drx_scan_param * Parameters for channel scan. * * Used by DRX_CTRL_SCAN_INIT. */ struct drx_scan_param { struct drx_frequency_plan *frequency_plan; - /**< Frequency plan (array)*/ - u16 frequency_plan_size; /**< Number of bands */ - u32 num_tries; /**< Max channels tried */ - s32 skip; /**< Minimum frequency step to take + /*< Frequency plan (array)*/ + u16 frequency_plan_size; /*< Number of bands */ + u32 num_tries; /*< Max channels tried */ + s32 skip; /*< Minimum frequency step to take after a channel is found */ - void *ext_params; /**< Standard specific params */ + void *ext_params; /*< Standard specific params */ }; /*========================================*/ -/** +/* * \brief Scan commands. * Used by scanning algorithms. */ enum drx_scan_command { - DRX_SCAN_COMMAND_INIT = 0,/**< Initialize scanning */ - DRX_SCAN_COMMAND_NEXT, /**< Next scan */ - DRX_SCAN_COMMAND_STOP /**< Stop scanning */ + DRX_SCAN_COMMAND_INIT = 0,/*< Initialize scanning */ + DRX_SCAN_COMMAND_NEXT, /*< Next scan */ + DRX_SCAN_COMMAND_STOP /*< Stop scanning */ }; /*========================================*/ -/** +/* * \brief Inner scan function prototype. */ typedef int(*drx_scan_func_t) (void *scan_context, @@ -1104,77 +1104,77 @@ typedef int(*drx_scan_func_t) (void *scan_context, /*========================================*/ -/** +/* * \struct struct drxtps_info * TPS information, DVB-T specific. * * Used by DRX_CTRL_TPS_INFO. */ struct drxtps_info { - enum drx_fft_mode fftmode; /**< Fft mode */ - enum drx_guard guard; /**< Guard interval */ + enum drx_fft_mode fftmode; /*< Fft mode */ + enum drx_guard guard; /*< Guard interval */ enum drx_modulation constellation; - /**< Constellation */ + /*< Constellation */ enum drx_hierarchy hierarchy; - /**< Hierarchy */ + /*< Hierarchy */ enum drx_coderate high_coderate; - /**< High code rate */ + /*< High code rate */ enum drx_coderate low_coderate; - /**< Low cod rate */ - enum drx_tps_frame frame; /**< Tps frame */ - u8 length; /**< Length */ - u16 cell_id; /**< Cell id */ + /*< Low cod rate */ + enum drx_tps_frame frame; /*< Tps frame */ + u8 length; /*< Length */ + u16 cell_id; /*< Cell id */ }; /*========================================*/ -/** +/* * \brief Power mode of device. * * Used by DRX_CTRL_SET_POWER_MODE. */ enum drx_power_mode { DRX_POWER_UP = 0, - /**< Generic , Power Up Mode */ + /*< Generic , Power Up Mode */ DRX_POWER_MODE_1, - /**< Device specific , Power Up Mode */ + /*< Device specific , Power Up Mode */ DRX_POWER_MODE_2, - /**< Device specific , Power Up Mode */ + /*< Device specific , Power Up Mode */ DRX_POWER_MODE_3, - /**< Device specific , Power Up Mode */ + /*< Device specific , Power Up Mode */ DRX_POWER_MODE_4, - /**< Device specific , Power Up Mode */ + /*< Device specific , Power Up Mode */ DRX_POWER_MODE_5, - /**< Device specific , Power Up Mode */ + /*< Device specific , Power Up Mode */ DRX_POWER_MODE_6, - /**< Device specific , Power Up Mode */ + /*< Device specific , Power Up Mode */ DRX_POWER_MODE_7, - /**< Device specific , Power Up Mode */ + /*< Device specific , Power Up Mode */ DRX_POWER_MODE_8, - /**< Device specific , Power Up Mode */ + /*< Device specific , Power Up Mode */ DRX_POWER_MODE_9, - /**< Device specific , Power Down Mode */ + /*< Device specific , Power Down Mode */ DRX_POWER_MODE_10, - /**< Device specific , Power Down Mode */ + /*< Device specific , Power Down Mode */ DRX_POWER_MODE_11, - /**< Device specific , Power Down Mode */ + /*< Device specific , Power Down Mode */ DRX_POWER_MODE_12, - /**< Device specific , Power Down Mode */ + /*< Device specific , Power Down Mode */ DRX_POWER_MODE_13, - /**< Device specific , Power Down Mode */ + /*< Device specific , Power Down Mode */ DRX_POWER_MODE_14, - /**< Device specific , Power Down Mode */ + /*< Device specific , Power Down Mode */ DRX_POWER_MODE_15, - /**< Device specific , Power Down Mode */ + /*< Device specific , Power Down Mode */ DRX_POWER_MODE_16, - /**< Device specific , Power Down Mode */ + /*< Device specific , Power Down Mode */ DRX_POWER_DOWN = 255 - /**< Generic , Power Down Mode */ + /*< Generic , Power Down Mode */ }; /*========================================*/ -/** +/* * \enum enum drx_module * \brief Software module identification. * * Used by DRX_CTRL_VERSION. @@ -1191,93 +1191,93 @@ typedef int(*drx_scan_func_t) (void *scan_context, DRX_MODULE_UNKNOWN }; -/** +/* * \enum struct drx_version * \brief Version information of one software module. * * Used by DRX_CTRL_VERSION. */ struct drx_version { enum drx_module module_type; - /**< Type identifier of the module */ + /*< Type identifier of the module */ char *module_name; - /**< Name or description of module */ - u16 v_major; /**< Major version number */ - u16 v_minor; /**< Minor version number */ - u16 v_patch; /**< Patch version number */ - char *v_string; /**< Version as text string */ + /*< Name or description of module */ + u16 v_major; /*< Major version number */ + u16 v_minor; /*< Minor version number */ + u16 v_patch; /*< Patch version number */ + char *v_string; /*< Version as text string */ }; -/** +/* * \enum struct drx_version_list * \brief List element of NULL terminated, linked list for version information. * * Used by DRX_CTRL_VERSION. */ struct drx_version_list { - struct drx_version *version;/**< Version information */ + struct drx_version *version;/*< Version information */ struct drx_version_list *next; - /**< Next list element */ + /*< Next list element */ }; /*========================================*/ -/** +/* * \brief Parameters needed to confiugure a UIO. * * Used by DRX_CTRL_UIO_CFG. */ struct drxuio_cfg { enum drx_uio uio; - /**< UIO identifier */ + /*< UIO identifier */ enum drxuio_mode mode; - /**< UIO operational mode */ + /*< UIO operational mode */ }; /*========================================*/ -/** +/* * \brief Parameters needed to read from or write to a UIO. * * Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE. */ struct drxuio_data { enum drx_uio uio; - /**< UIO identifier */ + /*< UIO identifier */ bool value; - /**< UIO value (true=1, false=0) */ + /*< UIO value (true=1, false=0) */ }; /*========================================*/ -/** +/* * \brief Parameters needed to configure OOB. * * Used by DRX_CTRL_SET_OOB. */ struct drxoob { - s32 frequency; /**< Frequency in kHz */ + s32 frequency; /*< Frequency in kHz */ enum drxoob_downstream_standard standard; - /**< OOB standard */ - bool spectrum_inverted; /**< If true, then spectrum + /*< OOB standard */ + bool spectrum_inverted; /*< If true, then spectrum is inverted */ }; /*========================================*/ -/** +/* * \brief Metrics from OOB. * * Used by DRX_CTRL_GET_OOB. */ struct drxoob_status { - s32 frequency; /**< Frequency in Khz */ - enum drx_lock_status lock; /**< Lock status */ - u32 mer; /**< MER */ - s32 symbol_rate_offset; /**< Symbolrate offset in ppm */ + s32 frequency; /*< Frequency in Khz */ + enum drx_lock_status lock; /*< Lock status */ + u32 mer; /*< MER */ + s32 symbol_rate_offset; /*< Symbolrate offset in ppm */ }; /*========================================*/ -/** +/* * \brief Device dependent configuration data. * * Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG. @@ -1285,14 +1285,14 @@ struct drx_version_list { */ struct drx_cfg { u32 cfg_type; - /**< Function identifier */ + /*< Function identifier */ void *cfg_data; - /**< Function data */ + /*< Function data */ }; /*========================================*/ -/** +/* * /struct DRXMpegStartWidth_t * MStart width [nr MCLK cycles] for serial MPEG output. */ @@ -1303,7 +1303,7 @@ struct drx_version_list { }; /* CTRL CFG MPEG output */ -/** +/* * \struct struct drx_cfg_mpeg_output * \brief Configuration parameters for MPEG output control. * * Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and @@ -1311,29 +1311,29 @@ struct drx_version_list { */ struct drx_cfg_mpeg_output { - bool enable_mpeg_output;/**< If true, enable MPEG output */ - bool insert_rs_byte; /**< If true, insert RS byte */ - bool enable_parallel; /**< If true, parallel out otherwise + bool enable_mpeg_output;/*< If true, enable MPEG output */ + bool insert_rs_byte; /*< If true, insert RS byte */ + bool enable_parallel; /*< If true, parallel out otherwise serial */ - bool invert_data; /**< If true, invert DATA signals */ - bool invert_err; /**< If true, invert ERR signal */ - bool invert_str; /**< If true, invert STR signals */ - bool invert_val; /**< If true, invert VAL signals */ - bool invert_clk; /**< If true, invert CLK signals */ - bool static_clk; /**< If true, static MPEG clockrate + bool invert_data; /*< If true, invert DATA signals */ + bool invert_err; /*< If true, invert ERR signal */ + bool invert_str; /*< If true, invert STR signals */ + bool invert_val; /*< If true, invert VAL signals */ + bool invert_clk; /*< If true, invert CLK signals */ + bool static_clk; /*< If true, static MPEG clockrate will be used, otherwise clockrate will adapt to the bitrate of the TS */ - u32 bitrate; /**< Maximum bitrate in b/s in case + u32 bitrate; /*< Maximum bitrate in b/s in case static clockrate is selected */ enum drxmpeg_str_width width_str; - /**< MPEG start width */ + /*< MPEG start width */ }; /*========================================*/ -/** +/* * \struct struct drxi2c_data * \brief Data for I2C via 2nd or 3rd or etc I2C port. * * Used by DRX_CTRL_I2C_READWRITE. @@ -1341,187 +1341,187 @@ struct drx_version_list { * */ struct drxi2c_data { - u16 port_nr; /**< I2C port number */ + u16 port_nr; /*< I2C port number */ struct i2c_device_addr *w_dev_addr; - /**< Write device address */ - u16 w_count; /**< Size of write data in bytes */ - u8 *wData; /**< Pointer to write data */ + /*< Write device address */ + u16 w_count; /*< Size of write data in bytes */ + u8 *wData; /*< Pointer to write data */ struct i2c_device_addr *r_dev_addr; - /**< Read device address */ - u16 r_count; /**< Size of data to read in bytes */ - u8 *r_data; /**< Pointer to read buffer */ + /*< Read device address */ + u16 r_count; /*< Size of data to read in bytes */ + u8 *r_data; /*< Pointer to read buffer */ }; /*========================================*/ -/** +/* * \enum enum drx_aud_standard * \brief Audio standard identifier. * * Used by DRX_CTRL_SET_AUD. */ enum drx_aud_standard { - DRX_AUD_STANDARD_BTSC, /**< set BTSC standard (USA) */ - DRX_AUD_STANDARD_A2, /**< set A2-Korea FM Stereo */ - DRX_AUD_STANDARD_EIAJ, /**< set to Japanese FM Stereo */ - DRX_AUD_STANDARD_FM_STEREO,/**< set to FM-Stereo Radio */ - DRX_AUD_STANDARD_M_MONO, /**< for 4.5 MHz mono detected */ - DRX_AUD_STANDARD_D_K_MONO, /**< for 6.5 MHz mono detected */ - DRX_AUD_STANDARD_BG_FM, /**< set BG_FM standard */ - DRX_AUD_STANDARD_D_K1, /**< set D_K1 standard */ - DRX_AUD_STANDARD_D_K2, /**< set D_K2 standard */ - DRX_AUD_STANDARD_D_K3, /**< set D_K3 standard */ + DRX_AUD_STANDARD_BTSC, /*< set BTSC standard (USA) */ + DRX_AUD_STANDARD_A2, /*< set A2-Korea FM Stereo */ + DRX_AUD_STANDARD_EIAJ, /*< set to Japanese FM Stereo */ + DRX_AUD_STANDARD_FM_STEREO,/*< set to FM-Stereo Radio */ + DRX_AUD_STANDARD_M_MONO, /*< for 4.5 MHz mono detected */ + DRX_AUD_STANDARD_D_K_MONO, /*< for 6.5 MHz mono detected */ + DRX_AUD_STANDARD_BG_FM, /*< set BG_FM standard */ + DRX_AUD_STANDARD_D_K1, /*< set D_K1 standard */ + DRX_AUD_STANDARD_D_K2, /*< set D_K2 standard */ + DRX_AUD_STANDARD_D_K3, /*< set D_K3 standard */ DRX_AUD_STANDARD_BG_NICAM_FM, - /**< set BG_NICAM_FM standard */ + /*< set BG_NICAM_FM standard */ DRX_AUD_STANDARD_L_NICAM_AM, - /**< set L_NICAM_AM standard */ + /*< set L_NICAM_AM standard */ DRX_AUD_STANDARD_I_NICAM_FM, - /**< set I_NICAM_FM standard */ + /*< set I_NICAM_FM standard */ DRX_AUD_STANDARD_D_K_NICAM_FM, - /**< set D_K_NICAM_FM standard */ - DRX_AUD_STANDARD_NOT_READY,/**< used to detect audio standard */ + /*< set D_K_NICAM_FM standard */ + DRX_AUD_STANDARD_NOT_READY,/*< used to detect audio standard */ DRX_AUD_STANDARD_AUTO = DRX_AUTO, - /**< Automatic Standard Detection */ + /*< Automatic Standard Detection */ DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN - /**< used as auto and for readback */ + /*< used as auto and for readback */ }; /* CTRL_AUD_GET_STATUS - struct drx_aud_status */ -/** +/* * \enum enum drx_aud_nicam_status * \brief Status of NICAM carrier. */ enum drx_aud_nicam_status { DRX_AUD_NICAM_DETECTED = 0, - /**< NICAM carrier detected */ + /*< NICAM carrier detected */ DRX_AUD_NICAM_NOT_DETECTED, - /**< NICAM carrier not detected */ - DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */ + /*< NICAM carrier not detected */ + DRX_AUD_NICAM_BAD /*< NICAM carrier bad quality */ }; -/** +/* * \struct struct drx_aud_status * \brief Audio status characteristics. */ struct drx_aud_status { - bool stereo; /**< stereo detection */ - bool carrier_a; /**< carrier A detected */ - bool carrier_b; /**< carrier B detected */ - bool sap; /**< sap / bilingual detection */ - bool rds; /**< RDS data array present */ + bool stereo; /*< stereo detection */ + bool carrier_a; /*< carrier A detected */ + bool carrier_b; /*< carrier B detected */ + bool sap; /*< sap / bilingual detection */ + bool rds; /*< RDS data array present */ enum drx_aud_nicam_status nicam_status; - /**< status of NICAM carrier */ - s8 fm_ident; /**< FM Identification value */ + /*< status of NICAM carrier */ + s8 fm_ident; /*< FM Identification value */ }; /* CTRL_AUD_READ_RDS - DRXRDSdata_t */ -/** +/* * \struct DRXRDSdata_t * \brief Raw RDS data array. */ struct drx_cfg_aud_rds { - bool valid; /**< RDS data validation */ - u16 data[18]; /**< data from one RDS data array */ + bool valid; /*< RDS data validation */ + u16 data[18]; /*< data from one RDS data array */ }; /* DRX_CFG_AUD_VOLUME - struct drx_cfg_aud_volume - set/get */ -/** +/* * \enum DRXAudAVCDecayTime_t * \brief Automatic volume control configuration. */ enum drx_aud_avc_mode { - DRX_AUD_AVC_OFF, /**< Automatic volume control off */ - DRX_AUD_AVC_DECAYTIME_8S, /**< level volume in 8 seconds */ - DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */ - DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */ - DRX_AUD_AVC_DECAYTIME_20MS/**< level volume in 20 millisec */ + DRX_AUD_AVC_OFF, /*< Automatic volume control off */ + DRX_AUD_AVC_DECAYTIME_8S, /*< level volume in 8 seconds */ + DRX_AUD_AVC_DECAYTIME_4S, /*< level volume in 4 seconds */ + DRX_AUD_AVC_DECAYTIME_2S, /*< level volume in 2 seconds */ + DRX_AUD_AVC_DECAYTIME_20MS/*< level volume in 20 millisec */ }; -/** +/* * /enum DRXAudMaxAVCGain_t * /brief Automatic volume control max gain in audio baseband. */ enum drx_aud_avc_max_gain { - DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */ - DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */ - DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */ + DRX_AUD_AVC_MAX_GAIN_0DB, /*< maximum AVC gain 0 dB */ + DRX_AUD_AVC_MAX_GAIN_6DB, /*< maximum AVC gain 6 dB */ + DRX_AUD_AVC_MAX_GAIN_12DB /*< maximum AVC gain 12 dB */ }; -/** +/* * /enum DRXAudMaxAVCAtten_t * /brief Automatic volume control max attenuation in audio baseband. */ enum drx_aud_avc_max_atten { DRX_AUD_AVC_MAX_ATTEN_12DB, - /**< maximum AVC attenuation 12 dB */ + /*< maximum AVC attenuation 12 dB */ DRX_AUD_AVC_MAX_ATTEN_18DB, - /**< maximum AVC attenuation 18 dB */ - DRX_AUD_AVC_MAX_ATTEN_24DB/**< maximum AVC attenuation 24 dB */ + /*< maximum AVC attenuation 18 dB */ + DRX_AUD_AVC_MAX_ATTEN_24DB/*< maximum AVC attenuation 24 dB */ }; -/** +/* * \struct struct drx_cfg_aud_volume * \brief Audio volume configuration. */ struct drx_cfg_aud_volume { - bool mute; /**< mute overrides volume setting */ - s16 volume; /**< volume, range -114 to 12 dB */ - enum drx_aud_avc_mode avc_mode; /**< AVC auto volume control mode */ - u16 avc_ref_level; /**< AVC reference level */ + bool mute; /*< mute overrides volume setting */ + s16 volume; /*< volume, range -114 to 12 dB */ + enum drx_aud_avc_mode avc_mode; /*< AVC auto volume control mode */ + u16 avc_ref_level; /*< AVC reference level */ enum drx_aud_avc_max_gain avc_max_gain; - /**< AVC max gain selection */ + /*< AVC max gain selection */ enum drx_aud_avc_max_atten avc_max_atten; - /**< AVC max attenuation selection */ - s16 strength_left; /**< quasi-peak, left speaker */ - s16 strength_right; /**< quasi-peak, right speaker */ + /*< AVC max attenuation selection */ + s16 strength_left; /*< quasi-peak, left speaker */ + s16 strength_right; /*< quasi-peak, right speaker */ }; /* DRX_CFG_I2S_OUTPUT - struct drx_cfg_i2s_output - set/get */ -/** +/* * \enum enum drxi2s_mode * \brief I2S output mode. */ enum drxi2s_mode { - DRX_I2S_MODE_MASTER, /**< I2S is in master mode */ - DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */ + DRX_I2S_MODE_MASTER, /*< I2S is in master mode */ + DRX_I2S_MODE_SLAVE /*< I2S is in slave mode */ }; -/** +/* * \enum enum drxi2s_word_length * \brief Width of I2S data. */ enum drxi2s_word_length { - DRX_I2S_WORDLENGTH_32 = 0,/**< I2S data is 32 bit wide */ - DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */ + DRX_I2S_WORDLENGTH_32 = 0,/*< I2S data is 32 bit wide */ + DRX_I2S_WORDLENGTH_16 = 1 /*< I2S data is 16 bit wide */ }; -/** +/* * \enum enum drxi2s_format * \brief Data wordstrobe alignment for I2S. */ enum drxi2s_format { DRX_I2S_FORMAT_WS_WITH_DATA, - /**< I2S data and wordstrobe are aligned */ + /*< I2S data and wordstrobe are aligned */ DRX_I2S_FORMAT_WS_ADVANCED - /**< I2S data one cycle after wordstrobe */ + /*< I2S data one cycle after wordstrobe */ }; -/** +/* * \enum enum drxi2s_polarity * \brief Polarity of I2S data. */ enum drxi2s_polarity { - DRX_I2S_POLARITY_RIGHT,/**< wordstrobe - right high, left low */ - DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */ + DRX_I2S_POLARITY_RIGHT,/*< wordstrobe - right high, left low */ + DRX_I2S_POLARITY_LEFT /*< wordstrobe - right low, left high */ }; -/** +/* * \struct struct drx_cfg_i2s_output * \brief I2S output configuration. */ struct drx_cfg_i2s_output { - bool output_enable; /**< I2S output enable */ - u32 frequency; /**< range from 8000-48000 Hz */ - enum drxi2s_mode mode; /**< I2S mode, master or slave */ + bool output_enable; /*< I2S output enable */ + u32 frequency; /*< range from 8000-48000 Hz */ + enum drxi2s_mode mode; /*< I2S mode, master or slave */ enum drxi2s_word_length word_length; - /**< I2S wordlength, 16 or 32 bits */ - enum drxi2s_polarity polarity;/**< I2S wordstrobe polarity */ - enum drxi2s_format format; /**< I2S wordstrobe delay to data */ + /*< I2S wordlength, 16 or 32 bits */ + enum drxi2s_polarity polarity;/*< I2S wordstrobe polarity */ + enum drxi2s_format format; /*< I2S wordstrobe delay to data */ }; /* ------------------------------expert interface-----------------------------*/ -/** +/* * /enum enum drx_aud_fm_deemphasis * setting for FM-Deemphasis in audio demodulator. * */ @@ -1531,7 +1531,7 @@ struct drx_version_list { DRX_AUD_FM_DEEMPH_OFF }; -/** +/* * /enum DRXAudDeviation_t * setting for deviation mode in audio demodulator. * @@ -1541,7 +1541,7 @@ struct drx_version_list { DRX_AUD_DEVIATION_HIGH }; -/** +/* * /enum enum drx_no_carrier_option * setting for carrier, mute/noise. * */ @@ -1550,7 +1550,7 @@ struct drx_version_list { DRX_NO_CARRIER_NOISE }; -/** +/* * \enum DRXAudAutoSound_t * \brief Automatic Sound */ @@ -1560,7 +1560,7 @@ struct drx_version_list { DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF }; -/** +/* * \enum DRXAudASSThres_t * \brief Automatic Sound Select Thresholds */ @@ -1570,7 +1570,7 @@ struct drx_version_list { u16 nicam; /* Nicam Threshold for ASS configuration */ }; -/** +/* * \struct struct drx_aud_carrier * \brief Carrier detection related parameters */ struct drx_aud_carrier { @@ -1580,7 +1580,7 @@ struct drx_version_list { s32 dco; /* frequency adjustment (A) */ }; -/** +/* * \struct struct drx_cfg_aud_carriers * \brief combining carrier A & B to one struct */ struct drx_cfg_aud_carriers { @@ -1588,7 +1588,7 @@ struct drx_version_list { struct drx_aud_carrier b; }; -/** +/* * /enum enum drx_aud_i2s_src * Selection of audio source */ enum drx_aud_i2s_src { @@ -1597,19 +1597,19 @@ struct drx_version_list { DRX_AUD_SRC_STEREO_OR_A, DRX_AUD_SRC_STEREO_OR_B}; -/** +/* * \enum enum drx_aud_i2s_matrix * \brief Used for selecting I2S output. */ enum drx_aud_i2s_matrix { DRX_AUD_I2S_MATRIX_A_MONO, - /**< A sound only, stereo or mono */ + /*< A sound only, stereo or mono */ DRX_AUD_I2S_MATRIX_B_MONO, - /**< B sound only, stereo or mono */ + /*< B sound only, stereo or mono */ DRX_AUD_I2S_MATRIX_STEREO, - /**< A+B sound, transparant */ - DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */}; + /*< A+B sound, transparant */ + DRX_AUD_I2S_MATRIX_MONO /*< A+B mixed to mono sum, (L+R)/2 */}; -/** +/* * /enum enum drx_aud_fm_matrix * setting for FM-Matrix in audio demodulator. * */ @@ -1620,7 +1620,7 @@ struct drx_version_list { DRX_AUD_FM_MATRIX_SOUND_A, DRX_AUD_FM_MATRIX_SOUND_B}; -/** +/* * \struct DRXAudMatrices_t * \brief Mixer settings */ @@ -1630,22 +1630,22 @@ struct drx_cfg_aud_mixer { enum drx_aud_fm_matrix matrix_fm; }; -/** +/* * \enum DRXI2SVidSync_t * \brief Audio/video synchronization, interacts with I2S mode. * AUTO_1 and AUTO_2 are for automatic video standard detection with preference * for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz) */ enum drx_cfg_aud_av_sync { - DRX_AUD_AVSYNC_OFF,/**< audio/video synchronization is off */ + DRX_AUD_AVSYNC_OFF,/*< audio/video synchronization is off */ DRX_AUD_AVSYNC_NTSC, - /**< it is an NTSC system */ + /*< it is an NTSC system */ DRX_AUD_AVSYNC_MONOCHROME, - /**< it is a MONOCHROME system */ + /*< it is a MONOCHROME system */ DRX_AUD_AVSYNC_PAL_SECAM - /**< it is a PAL/SECAM system */}; + /*< it is a PAL/SECAM system */}; -/** +/* * \struct struct drx_cfg_aud_prescale * \brief Prescalers */ struct drx_cfg_aud_prescale { @@ -1653,7 +1653,7 @@ struct drx_cfg_aud_prescale { s16 nicam_gain; }; -/** +/* * \struct struct drx_aud_beep * \brief Beep */ struct drx_aud_beep { @@ -1662,14 +1662,14 @@ struct drx_aud_beep { bool mute; }; -/** +/* * \enum enum drx_aud_btsc_detect * \brief BTSC detetcion mode */ enum drx_aud_btsc_detect { DRX_BTSC_STEREO, DRX_BTSC_MONO_AND_SAP}; -/** +/* * \struct struct drx_aud_data * \brief Audio data structure */ struct drx_aud_data { @@ -1692,7 +1692,7 @@ struct drx_aud_data { bool rds_data_present; }; -/** +/* * \enum enum drx_qam_lock_range * \brief QAM lock range mode */ enum drx_qam_lock_range { @@ -1782,7 +1782,7 @@ struct drx_aud_data { u32 wdata, /* data to write */ u32 *rdata); /* data to read */ -/** +/* * \struct struct drx_access_func * \brief Interface to an access protocol. */ struct drx_access_func { @@ -1811,85 +1811,85 @@ struct drx_reg_dump { /*============================================================================*/ /*============================================================================*/ -/** +/* * \struct struct drx_common_attr * \brief Set of common attributes, shared by all DRX devices. */ struct drx_common_attr { /* Microcode (firmware) attributes */ - char *microcode_file; /**< microcode filename */ + char *microcode_file; /*< microcode filename */ bool verify_microcode; - /**< Use microcode verify or not. */ + /*< Use microcode verify or not. */ struct drx_mc_version_rec mcversion; - /**< Version record of microcode from file */ + /*< Version record of microcode from file */ /* Clocks and tuner attributes */ s32 intermediate_freq; - /**< IF,if tuner instance not used. (kHz)*/ + /*< IF,if tuner instance not used. (kHz)*/ s32 sys_clock_freq; - /**< Systemclock frequency. (kHz) */ + /*< Systemclock frequency. (kHz) */ s32 osc_clock_freq; - /**< Oscillator clock frequency. (kHz) */ + /*< Oscillator clock frequency. (kHz) */ s16 osc_clock_deviation; - /**< Oscillator clock deviation. (ppm) */ + /*< Oscillator clock deviation. (ppm) */ bool mirror_freq_spect; - /**< Mirror IF frequency spectrum or not.*/ + /*< Mirror IF frequency spectrum or not.*/ /* Initial MPEG output attributes */ struct drx_cfg_mpeg_output mpeg_cfg; - /**< MPEG configuration */ + /*< MPEG configuration */ - bool is_opened; /**< if true instance is already opened. */ + bool is_opened; /*< if true instance is already opened. */ /* Channel scan */ struct drx_scan_param *scan_param; - /**< scan parameters */ + /*< scan parameters */ u16 scan_freq_plan_index; - /**< next index in freq plan */ + /*< next index in freq plan */ s32 scan_next_frequency; - /**< next freq to scan */ - bool scan_ready; /**< scan ready flag */ - u32 scan_max_channels;/**< number of channels in freqplan */ + /*< next freq to scan */ + bool scan_ready; /*< scan ready flag */ + u32 scan_max_channels;/*< number of channels in freqplan */ u32 scan_channels_scanned; - /**< number of channels scanned */ + /*< number of channels scanned */ /* Channel scan - inner loop: demod related */ drx_scan_func_t scan_function; - /**< function to check channel */ + /*< function to check channel */ /* Channel scan - inner loop: SYSObj related */ - void *scan_context; /**< Context Pointer of SYSObj */ + void *scan_context; /*< Context Pointer of SYSObj */ /* Channel scan - parameters for default DTV scan function in core driver */ u16 scan_demod_lock_timeout; - /**< millisecs to wait for lock */ + /*< millisecs to wait for lock */ enum drx_lock_status scan_desired_lock; - /**< lock requirement for channel found */ + /*< lock requirement for channel found */ /* scan_active can be used by SetChannel to decide how to program the tuner, fast or slow (but stable). Usually fast during scan. */ - bool scan_active; /**< true when scan routines are active */ + bool scan_active; /*< true when scan routines are active */ /* Power management */ enum drx_power_mode current_power_mode; - /**< current power management mode */ + /*< current power management mode */ /* Tuner */ - u8 tuner_port_nr; /**< nr of I2C port to wich tuner is */ + u8 tuner_port_nr; /*< nr of I2C port to wich tuner is */ s32 tuner_min_freq_rf; - /**< minimum RF input frequency, in kHz */ + /*< minimum RF input frequency, in kHz */ s32 tuner_max_freq_rf; - /**< maximum RF input frequency, in kHz */ - bool tuner_rf_agc_pol; /**< if true invert RF AGC polarity */ - bool tuner_if_agc_pol; /**< if true invert IF AGC polarity */ - bool tuner_slow_mode; /**< if true invert IF AGC polarity */ + /*< maximum RF input frequency, in kHz */ + bool tuner_rf_agc_pol; /*< if true invert RF AGC polarity */ + bool tuner_if_agc_pol; /*< if true invert IF AGC polarity */ + bool tuner_slow_mode; /*< if true invert IF AGC polarity */ struct drx_channel current_channel; - /**< current channel parameters */ + /*< current channel parameters */ enum drx_standard current_standard; - /**< current standard selection */ + /*< current standard selection */ enum drx_standard prev_standard; - /**< previous standard selection */ + /*< previous standard selection */ enum drx_standard di_cache_standard; - /**< standard in DI cache if available */ - bool use_bootloader; /**< use bootloader in open */ - u32 capabilities; /**< capabilities flags */ - u32 product_id; /**< product ID inc. metal fix number */}; + /*< standard in DI cache if available */ + bool use_bootloader; /*< use bootloader in open */ + u32 capabilities; /*< capabilities flags */ + u32 product_id; /*< product ID inc. metal fix number */}; /* * Generic functions for DRX devices. @@ -1897,16 +1897,16 @@ struct drx_reg_dump { struct drx_demod_instance; -/** +/* * \struct struct drx_demod_instance * \brief Top structure of demodulator instance. */ struct drx_demod_instance { - /**< data access protocol functions */ + /*< data access protocol functions */ struct i2c_device_addr *my_i2c_dev_addr; - /**< i2c address and device identifier */ + /*< i2c address and device identifier */ struct drx_common_attr *my_common_attr; - /**< common DRX attributes */ - void *my_ext_attr; /**< device specific attributes */ + /*< common DRX attributes */ + void *my_ext_attr; /*< device specific attributes */ /* generic demodulator data */ struct i2c_adapter *i2c; @@ -2195,7 +2195,7 @@ Conversion from enum values to human readable form. Access macros -------------------------------------------------------------------------*/ -/** +/* * \brief Create a compilable reference to the microcode attribute * \param d pointer to demod instance * @@ -2229,7 +2229,7 @@ Access macros #define DRX_ATTR_I2CDEVID(d) ((d)->my_i2c_dev_addr->i2c_dev_id) #define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD) -/**************************/ +/*************************/ /* Macros with device-specific handling are converted to CFG functions */ @@ -2285,7 +2285,7 @@ Access macros #define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET((d), (x), \ DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range, DRX_UNKNOWN) -/** +/* * \brief Macro to check if std is an ATV standard * \retval true std is an ATV standard * \retval false std is an ATV standard @@ -2298,7 +2298,7 @@ Access macros ((std) == DRX_STANDARD_NTSC) || \ ((std) == DRX_STANDARD_FM)) -/** +/* * \brief Macro to check if std is an QAM standard * \retval true std is an QAM standards * \retval false std is an QAM standards @@ -2308,14 +2308,14 @@ Access macros ((std) == DRX_STANDARD_ITU_C) || \ ((std) == DRX_STANDARD_ITU_D)) -/** +/* * \brief Macro to check if std is VSB standard * \retval true std is VSB standard * \retval false std is not VSB standard */ #define DRX_ISVSBSTD(std) ((std) == DRX_STANDARD_8VSB) -/** +/* * \brief Macro to check if std is DVBT standard * \retval true std is DVBT standard * \retval false std is not DVBT standard diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 499ccff557bf..5706898e84cc 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -61,7 +61,7 @@ INCLUDE FILES #include <linux/slab.h> #include <asm/div64.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "drx39xxj.h" #include "drxj.h" @@ -73,7 +73,7 @@ INCLUDE FILES #define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw" -/** +/* * \brief Maximum u32 value. */ #ifndef MAX_U32 @@ -100,8 +100,8 @@ INCLUDE FILES #ifndef OOB_DRX_DRIVE_STRENGTH #define OOB_DRX_DRIVE_STRENGTH 0x02 #endif -/**** START DJCOMBO patches to DRXJ registermap constants *********************/ -/**** registermap 200706071303 from drxj **************************************/ +/*** START DJCOMBO patches to DRXJ registermap constants *********************/ +/*** registermap 200706071303 from drxj **************************************/ #define ATV_TOP_CR_AMP_TH_FM 0x0 #define ATV_TOP_CR_AMP_TH_L 0xA #define ATV_TOP_CR_AMP_TH_LP 0xA @@ -188,7 +188,7 @@ INCLUDE FILES #define IQM_RC_ADJ_SEL_B_OFF 0x0 #define IQM_RC_ADJ_SEL_B_QAM 0x1 #define IQM_RC_ADJ_SEL_B_VSB 0x2 -/**** END DJCOMBO patches to DRXJ registermap *********************************/ +/*** END DJCOMBO patches to DRXJ registermap *********************************/ #include "drx_driver_version.h" @@ -208,25 +208,25 @@ DEFINES #define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr) #endif -/** +/* * \def DRXJ_DEF_I2C_ADDR * \brief Default I2C address of a demodulator instance. */ #define DRXJ_DEF_I2C_ADDR (0x52) -/** +/* * \def DRXJ_DEF_DEMOD_DEV_ID * \brief Default device identifier of a demodultor instance. */ #define DRXJ_DEF_DEMOD_DEV_ID (1) -/** +/* * \def DRXJ_SCAN_TIMEOUT * \brief Timeout value for waiting on demod lock during channel scan (millisec). */ #define DRXJ_SCAN_TIMEOUT 1000 -/** +/* * \def HI_I2C_DELAY * \brief HI timing delay for I2C timing (in nano seconds) * @@ -234,7 +234,7 @@ DEFINES */ #define HI_I2C_DELAY 42 -/** +/* * \def HI_I2C_BRIDGE_DELAY * \brief HI timing delay for I2C timing (in nano seconds) * @@ -242,13 +242,13 @@ DEFINES */ #define HI_I2C_BRIDGE_DELAY 750 -/** +/* * \brief Time Window for MER and SER Measurement in Units of Segment duration. */ #define VSB_TOP_MEASUREMENT_PERIOD 64 #define SYMBOLS_PER_SEGMENT 832 -/** +/* * \brief bit rate and segment rate constants used for SER and BER. */ /* values taken from the QAM microcode */ @@ -260,21 +260,21 @@ DEFINES #define DRXJ_QAM_SL_SIG_POWER_QAM64 43008 #define DRXJ_QAM_SL_SIG_POWER_QAM128 20992 #define DRXJ_QAM_SL_SIG_POWER_QAM256 43520 -/** +/* * \brief Min supported symbolrates. */ #ifndef DRXJ_QAM_SYMBOLRATE_MIN #define DRXJ_QAM_SYMBOLRATE_MIN (520000) #endif -/** +/* * \brief Max supported symbolrates. */ #ifndef DRXJ_QAM_SYMBOLRATE_MAX #define DRXJ_QAM_SYMBOLRATE_MAX (7233000) #endif -/** +/* * \def DRXJ_QAM_MAX_WAITTIME * \brief Maximal wait time for QAM auto constellation in ms */ @@ -290,7 +290,7 @@ DEFINES #define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 200 #endif -/** +/* * \def SCU status and results * \brief SCU */ @@ -299,7 +299,7 @@ DEFINES #define FEC_RS_MEASUREMENT_PERIOD 12894 /* 1 sec */ #define FEC_RS_MEASUREMENT_PRESCALE 1 /* n sec */ -/** +/* * \def DRX_AUD_MAX_DEVIATION * \brief Needed for calculation of prescale feature in AUD */ @@ -307,14 +307,14 @@ DEFINES #define DRXJ_AUD_MAX_FM_DEVIATION 100 /* kHz */ #endif -/** +/* * \brief Needed for calculation of NICAM prescale feature in AUD */ #ifndef DRXJ_AUD_MAX_NICAM_PRESCALE #define DRXJ_AUD_MAX_NICAM_PRESCALE (9) /* dB */ #endif -/** +/* * \brief Needed for calculation of NICAM prescale feature in AUD */ #ifndef DRXJ_AUD_MAX_WAITTIME @@ -371,21 +371,21 @@ DEFINES /*============================================================================*/ /*=== GLOBAL VARIABLEs =======================================================*/ /*============================================================================*/ -/** +/* */ -/** +/* * \brief Temporary register definitions. * (register definitions that are not yet available in register master) */ -/******************************************************************************/ +/*****************************************************************************/ /* Audio block 0x103 is write only. To avoid shadowing in driver accessing */ /* RAM adresses directly. This must be READ ONLY to avoid problems. */ /* Writing to the interface adresses is more than only writing the RAM */ /* locations */ -/******************************************************************************/ -/** +/*****************************************************************************/ +/* * \brief RAM location of MODUS registers */ #define AUD_DEM_RAM_MODUS_HI__A 0x10204A3 @@ -394,13 +394,13 @@ DEFINES #define AUD_DEM_RAM_MODUS_LO__A 0x10204A4 #define AUD_DEM_RAM_MODUS_LO__M 0x0FFF -/** +/* * \brief RAM location of I2S config registers */ #define AUD_DEM_RAM_I2S_CONFIG1__A 0x10204B1 #define AUD_DEM_RAM_I2S_CONFIG2__A 0x10204B2 -/** +/* * \brief RAM location of DCO config registers */ #define AUD_DEM_RAM_DCO_B_HI__A 0x1020461 @@ -408,20 +408,20 @@ DEFINES #define AUD_DEM_RAM_DCO_A_HI__A 0x1020463 #define AUD_DEM_RAM_DCO_A_LO__A 0x1020464 -/** +/* * \brief RAM location of Threshold registers */ #define AUD_DEM_RAM_NICAM_THRSHLD__A 0x102045A #define AUD_DEM_RAM_A2_THRSHLD__A 0x10204BB #define AUD_DEM_RAM_BTSC_THRSHLD__A 0x10204A6 -/** +/* * \brief RAM location of Carrier Threshold registers */ #define AUD_DEM_RAM_CM_A_THRSHLD__A 0x10204AF #define AUD_DEM_RAM_CM_B_THRSHLD__A 0x10204B0 -/** +/* * \brief FM Matrix register fix */ #ifdef AUD_DEM_WR_FM_MATRIX__A @@ -430,7 +430,7 @@ DEFINES #define AUD_DEM_WR_FM_MATRIX__A 0x105006F /*============================================================================*/ -/** +/* * \brief Defines required for audio */ #define AUD_VOLUME_ZERO_DB 115 @@ -443,14 +443,14 @@ DEFINES #define AUD_I2S_FREQUENCY_MIN 12000UL #define AUD_RDS_ARRAY_SIZE 18 -/** +/* * \brief Needed for calculation of prescale feature in AUD */ #ifndef DRX_AUD_MAX_FM_DEVIATION #define DRX_AUD_MAX_FM_DEVIATION (100) /* kHz */ #endif -/** +/* * \brief Needed for calculation of NICAM prescale feature in AUD */ #ifndef DRX_AUD_MAX_NICAM_PRESCALE @@ -478,7 +478,7 @@ DEFINES /*=== REGISTER ACCESS MACROS =================================================*/ /*============================================================================*/ -/** +/* * This macro is used to create byte arrays for block writes. * Block writes speed up I2C traffic between host and demod. * The macro takes care of the required byte order in a 16 bits word. @@ -486,7 +486,7 @@ DEFINES */ #define DRXJ_16TO8(x) ((u8) (((u16)x) & 0xFF)), \ ((u8)((((u16)x)>>8)&0xFF)) -/** +/* * This macro is used to convert byte array to 16 bit register value for block read. * Block read speed up I2C traffic between host and demod. * The macro takes care of the required byte order in a 16 bits word. @@ -501,7 +501,7 @@ DEFINES /*=== HI COMMAND RELATED DEFINES =============================================*/ /*============================================================================*/ -/** +/* * \brief General maximum number of retries for ucode command interfaces */ #define DRXJ_MAX_RETRIES (100) @@ -807,7 +807,7 @@ static struct drxj_data drxj_data_g = { }, }; -/** +/* * \var drxj_default_addr_g * \brief Default I2C address and device identifier. */ @@ -816,7 +816,7 @@ static struct i2c_device_addr drxj_default_addr_g = { DRXJ_DEF_DEMOD_DEV_ID /* device id */ }; -/** +/* * \var drxj_default_comm_attr_g * \brief Default common attributes of a drxj demodulator instance. */ @@ -887,7 +887,7 @@ static struct drx_common_attr drxj_default_comm_attr_g = { 0 /* mfx */ }; -/** +/* * \var drxj_default_demod_g * \brief Default drxj demodulator instance. */ @@ -897,7 +897,7 @@ static struct drx_demod_instance drxj_default_demod_g = { &drxj_data_g /* demod device specific attributes */ }; -/** +/* * \brief Default audio data structure for DRK demodulator instance. * * This structure is DRXK specific. @@ -997,7 +997,7 @@ struct drxj_hi_cmd { /*=== MICROCODE RELATED STRUCTURES ===========================================*/ /*============================================================================*/ -/** +/* * struct drxu_code_block_hdr - Structure of the microcode block headers * * @addr: Destination address of the data in this block @@ -1086,7 +1086,7 @@ static u32 frac28(u32 N, u32 D) return Q1; } -/** +/* * \fn u32 log1_times100( u32 x) * \brief Compute: 100*log10(x) * \param x 32 bits @@ -1198,7 +1198,7 @@ static u32 log1_times100(u32 x) } -/** +/* * \fn u32 frac_times1e6( u16 N, u32 D) * \brief Compute: (N/D) * 1000000. * \param N nominator 16-bits. @@ -1235,7 +1235,7 @@ static u32 frac_times1e6(u32 N, u32 D) /*============================================================================*/ -/** +/* * \brief Values for NICAM prescaler gain. Computed from dB to integer * and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20). * @@ -1280,7 +1280,7 @@ static const u16 nicam_presc_table_val[43] = { #define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */ /*============================================================================*/ -/** +/* * \fn bool is_handled_by_aud_tr_if( u32 addr ) * \brief Check if this address is handled by the audio token ring interface. * \param addr @@ -1386,7 +1386,7 @@ int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, /*============================================================================*/ -/****************************** +/***************************** * * int drxdap_fasi_read_block ( * struct i2c_device_addr *dev_addr, -- address of I2C device @@ -1498,7 +1498,7 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, } -/****************************** +/***************************** * * int drxdap_fasi_read_reg16 ( * struct i2c_device_addr *dev_addr, -- address of I2C device @@ -1531,7 +1531,7 @@ static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, return rc; } -/****************************** +/***************************** * * int drxdap_fasi_read_reg32 ( * struct i2c_device_addr *dev_addr, -- address of I2C device @@ -1566,7 +1566,7 @@ static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, return rc; } -/****************************** +/***************************** * * int drxdap_fasi_write_block ( * struct i2c_device_addr *dev_addr, -- address of I2C device @@ -1705,7 +1705,7 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, return first_err; } -/****************************** +/***************************** * * int drxdap_fasi_write_reg16 ( * struct i2c_device_addr *dev_addr, -- address of I2C device @@ -1734,7 +1734,7 @@ static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr, return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags); } -/****************************** +/***************************** * * int drxdap_fasi_read_modify_write_reg16 ( * struct i2c_device_addr *dev_addr, -- address of I2C device @@ -1778,7 +1778,7 @@ static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, return rc; } -/****************************** +/***************************** * * int drxdap_fasi_write_reg32 ( * struct i2c_device_addr *dev_addr, -- address of I2C device @@ -1811,7 +1811,7 @@ static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, /*============================================================================*/ -/** +/* * \fn int drxj_dap_rm_write_reg16short * \brief Read modify write 16 bits audio register using short format only. * \param dev_addr @@ -1890,7 +1890,7 @@ static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr, /*============================================================================*/ -/** +/* * \fn int drxj_dap_read_aud_reg16 * \brief Read 16 bits audio register * \param dev_addr @@ -1997,7 +1997,7 @@ static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr, } /*============================================================================*/ -/** +/* * \fn int drxj_dap_write_aud_reg16 * \brief Write 16 bits audio register * \param dev_addr @@ -2086,7 +2086,7 @@ static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr, #define DRXJ_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ #define DRXJ_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE -/** +/* * \fn int drxj_dap_atomic_read_write_block() * \brief Basic access routine for atomic read or write access * \param dev_addr pointer to i2c dev address @@ -2151,9 +2151,13 @@ int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, if (read_flag) { /* read data from buffer */ for (i = 0; i < (datasize / 2); i++) { - drxj_dap_read_reg16(dev_addr, - (DRXJ_HI_ATOMIC_BUF_START + i), - &word, 0); + rc = drxj_dap_read_reg16(dev_addr, + (DRXJ_HI_ATOMIC_BUF_START + i), + &word, 0); + if (rc) { + pr_err("error %d\n", rc); + goto rw_error; + } data[2 * i] = (u8) (word & 0xFF); data[(2 * i) + 1] = (u8) (word >> 8); } @@ -2168,7 +2172,7 @@ rw_error: /*============================================================================*/ -/** +/* * \fn int drxj_dap_atomic_read_reg32() * \brief Atomic read of 32 bits words */ @@ -2215,7 +2219,7 @@ int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr, /*============================================================================*/ /*============================================================================*/ -/** +/* * \fn int hi_cfg_command() * \brief Configure HI with settings stored in the demod structure. * \param demod Demodulator. @@ -2258,7 +2262,7 @@ rw_error: return rc; } -/** +/* * \fn int hi_command() * \brief Configure HI with settings stored in the demod structure. * \param dev_addr I2C address. @@ -2369,7 +2373,7 @@ rw_error: return rc; } -/** +/* * \fn int init_hi( const struct drx_demod_instance *demod ) * \brief Initialise and configurate HI. * \param demod pointer to demod data. @@ -2450,7 +2454,7 @@ rw_error: /*============================================================================*/ /*============================================================================*/ -/** +/* * \fn int get_device_capabilities() * \brief Get and store device capabilities. * \param demod Pointer to demodulator instance. @@ -2656,7 +2660,7 @@ rw_error: return rc; } -/** +/* * \fn int power_up_device() * \brief Power up device. * \param demod Pointer to demodulator instance. @@ -2710,7 +2714,7 @@ static int power_up_device(struct drx_demod_instance *demod) /*----------------------------------------------------------------------------*/ /* MPEG Output Configuration Functions - begin */ /*----------------------------------------------------------------------------*/ -/** +/* * \fn int ctrl_set_cfg_mpeg_output() * \brief Set MPEG output configuration of the device. * \param devmod Pointer to demodulator instance. @@ -3356,7 +3360,7 @@ rw_error: /* miscellaneous configurations - begin */ /*----------------------------------------------------------------------------*/ -/** +/* * \fn int set_mpegtei_handling() * \brief Activate MPEG TEI handling settings. * \param devmod Pointer to demodulator instance. @@ -3429,7 +3433,7 @@ rw_error: } /*----------------------------------------------------------------------------*/ -/** +/* * \fn int bit_reverse_mpeg_output() * \brief Set MPEG output bit-endian settings. * \param devmod Pointer to demodulator instance. @@ -3472,7 +3476,7 @@ rw_error: } /*----------------------------------------------------------------------------*/ -/** +/* * \fn int set_mpeg_start_width() * \brief Set MPEG start width. * \param devmod Pointer to demodulator instance. @@ -3522,7 +3526,7 @@ rw_error: /*----------------------------------------------------------------------------*/ /* UIO Configuration Functions - begin */ /*----------------------------------------------------------------------------*/ -/** +/* * \fn int ctrl_set_uio_cfg() * \brief Configure modus oprandi UIO. * \param demod Pointer to demodulator instance. @@ -3659,7 +3663,7 @@ rw_error: return rc; } -/** +/* * \fn int ctrl_uio_write() * \brief Write to a UIO. * \param demod Pointer to demodulator instance. @@ -3868,7 +3872,7 @@ rw_error: /*----------------------------------------------------------------------------*/ /* I2C Bridge Functions - begin */ /*----------------------------------------------------------------------------*/ -/** +/* * \fn int ctrl_i2c_bridge() * \brief Open or close the I2C switch to tuner. * \param demod Pointer to demodulator instance. @@ -3903,7 +3907,7 @@ ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed) /*----------------------------------------------------------------------------*/ /* Smart antenna Functions - begin */ /*----------------------------------------------------------------------------*/ -/** +/* * \fn int smart_ant_init() * \brief Initialize Smart Antenna. * \param pointer to struct drx_demod_instance. @@ -4116,7 +4120,7 @@ rw_error: return rc; } -/** +/* * \fn int DRXJ_DAP_SCUAtomicReadWriteBlock() * \brief Basic access routine for SCU atomic read or write access * \param dev_addr pointer to i2c dev address @@ -4188,7 +4192,7 @@ rw_error: /*============================================================================*/ -/** +/* * \fn int DRXJ_DAP_AtomicReadReg16() * \brief Atomic read of 16 bits words */ @@ -4216,7 +4220,7 @@ int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr, } /*============================================================================*/ -/** +/* * \fn int drxj_dap_scu_atomic_write_reg16() * \brief Atomic read of 16 bits words */ @@ -4237,7 +4241,7 @@ int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr, } /* -------------------------------------------------------------------------- */ -/** +/* * \brief Measure result of ADC synchronisation * \param demod demod instance * \param count (returned) count @@ -4297,7 +4301,7 @@ rw_error: return rc; } -/** +/* * \brief Synchronize analog and digital clock domains * \param demod demod instance * \return int. @@ -4365,7 +4369,7 @@ rw_error: /*== 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/ /*============================================================================*/ /*============================================================================*/ -/** +/* * \fn int init_agc () * \brief Initialize AGC for all standards. * \param demod instance of demodulator. @@ -4741,7 +4745,7 @@ rw_error: return rc; } -/** +/* * \fn int set_frequency () * \brief Set frequency shift. * \param demod instance of demodulator. @@ -4839,7 +4843,7 @@ rw_error: return rc; } -/** +/* * \fn int get_acc_pkt_err() * \brief Retrieve signal strength for VSB and QAM. * \param demod Pointer to demod instance @@ -4891,7 +4895,7 @@ rw_error: /*============================================================================*/ -/** +/* * \fn int set_agc_rf () * \brief Configure RF AGC * \param demod instance of demodulator. @@ -5105,7 +5109,7 @@ rw_error: return rc; } -/** +/* * \fn int set_agc_if () * \brief Configure If AGC * \param demod instance of demodulator. @@ -5334,7 +5338,7 @@ rw_error: return rc; } -/** +/* * \fn int set_iqm_af () * \brief Configure IQM AF registers * \param demod instance of demodulator. @@ -5380,7 +5384,7 @@ rw_error: /*============================================================================*/ /*============================================================================*/ -/** +/* * \fn int power_down_vsb () * \brief Powr down QAM related blocks. * \param demod instance of demodulator. @@ -5478,7 +5482,7 @@ rw_error: return rc; } -/** +/* * \fn int set_vsb_leak_n_gain () * \brief Set ATSC demod. * \param demod instance of demodulator. @@ -5694,7 +5698,7 @@ rw_error: return rc; } -/** +/* * \fn int set_vsb() * \brief Set 8VSB demod. * \param demod instance of demodulator. @@ -6200,7 +6204,7 @@ rw_error: return rc; } -/** +/* * \fn static short get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *PckErrs) * \brief Get the values of packet error in 8VSB mode * \return Error code @@ -6239,7 +6243,7 @@ rw_error: return rc; } -/** +/* * \fn static short GetVSBBer(struct i2c_device_addr *dev_addr, u32 *ber) * \brief Get the values of ber in VSB mode * \return Error code @@ -6284,7 +6288,7 @@ rw_error: return rc; } -/** +/* * \fn static short get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) * \brief Get the values of ber in VSB mode * \return Error code @@ -6306,7 +6310,7 @@ static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, return 0; } -/** +/* * \fn static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) * \brief Get the values of MER * \return Error code @@ -6340,7 +6344,7 @@ rw_error: /*============================================================================*/ /*============================================================================*/ -/** +/* * \fn int power_down_qam () * \brief Powr down QAM related blocks. * \param demod instance of demodulator. @@ -6444,7 +6448,7 @@ rw_error: /*============================================================================*/ -/** +/* * \fn int set_qam_measurement () * \brief Setup of the QAM Measuremnt intervals for signal quality * \param demod instance of demod. @@ -6656,7 +6660,7 @@ rw_error: /*============================================================================*/ -/** +/* * \fn int set_qam16 () * \brief QAM16 specific setup * \param demod instance of demod. @@ -6891,7 +6895,7 @@ rw_error: /*============================================================================*/ -/** +/* * \fn int set_qam32 () * \brief QAM32 specific setup * \param demod instance of demod. @@ -7126,7 +7130,7 @@ rw_error: /*============================================================================*/ -/** +/* * \fn int set_qam64 () * \brief QAM64 specific setup * \param demod instance of demod. @@ -7362,7 +7366,7 @@ rw_error: /*============================================================================*/ -/** +/* * \fn int set_qam128 () * \brief QAM128 specific setup * \param demod: instance of demod. @@ -7597,7 +7601,7 @@ rw_error: /*============================================================================*/ -/** +/* * \fn int set_qam256 () * \brief QAM256 specific setup * \param demod: instance of demod. @@ -7835,7 +7839,7 @@ rw_error: #define QAM_SET_OP_CONSTELLATION 0x2 #define QAM_SET_OP_SPECTRUM 0X4 -/** +/* * \fn int set_qam () * \brief Set QAM demod. * \param demod: instance of demod. @@ -8845,7 +8849,7 @@ rw_error: #define DEMOD_LOCKED 0x1 #define SYNC_FLIPPED 0x2 #define SPEC_MIRRORED 0x4 -/** +/* * \fn int qam64auto () * \brief auto do sync pattern switching and mirroring. * \param demod: instance of demod. @@ -8993,7 +8997,7 @@ rw_error: return rc; } -/** +/* * \fn int qam256auto () * \brief auto do sync pattern switching and mirroring. * \param demod: instance of demod. @@ -9077,7 +9081,7 @@ rw_error: return rc; } -/** +/* * \fn int set_qam_channel () * \brief Set QAM channel according to the requested constellation. * \param demod: instance of demod. @@ -9284,7 +9288,7 @@ rw_error: /*============================================================================*/ -/** +/* * \fn static short get_qamrs_err_count(struct i2c_device_addr *dev_addr) * \brief Get RS error count in QAM mode (used for post RS BER calculation) * \return Error code @@ -9355,7 +9359,7 @@ rw_error: /*============================================================================*/ -/** +/* * \fn int get_sig_strength() * \brief Retrieve signal strength for VSB and QAM. * \param demod Pointer to demod instance @@ -9435,7 +9439,7 @@ rw_error: return rc; } -/** +/* * \fn int ctrl_get_qam_sig_quality() * \brief Retrieve QAM signal quality from device. * \param devmod Pointer to demodulator instance. @@ -9721,7 +9725,7 @@ rw_error: */ /* -------------------------------------------------------------------------- */ -/** +/* * \fn int power_down_atv () * \brief Power down ATV. * \param demod instance of demodulator @@ -9822,7 +9826,7 @@ rw_error: /*============================================================================*/ -/** +/* * \brief Power up AUD. * \param demod instance of demodulator * \return int. @@ -9850,7 +9854,7 @@ rw_error: return rc; } -/** +/* * \fn int set_orx_nsu_aox() * \brief Configure OrxNsuAox for OOB * \param demod instance of demodulator. @@ -9884,7 +9888,7 @@ rw_error: return rc; } -/** +/* * \fn int ctrl_set_oob() * \brief Set OOB channel to be used. * \param demod instance of demodulator @@ -9986,9 +9990,9 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par 20; } - /*********/ + /********/ /* Stop */ - /*********/ + /********/ rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); @@ -10004,9 +10008,9 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par pr_err("error %d\n", rc); goto rw_error; } - /*********/ + /********/ /* Reset */ - /*********/ + /********/ scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB | SCU_RAM_COMMAND_CMD_DEMOD_RESET; scu_cmd.parameter_len = 0; @@ -10017,9 +10021,9 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par pr_err("error %d\n", rc); goto rw_error; } - /***********/ + /**********/ /* SET_ENV */ - /***********/ + /**********/ /* set frequency, spectrum inversion and data rate */ scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; @@ -10376,9 +10380,9 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par pr_err("error %d\n", rc); goto rw_error; } - /*********/ + /********/ /* Start */ - /*********/ + /********/ scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB | SCU_RAM_COMMAND_CMD_DEMOD_START; scu_cmd.parameter_len = 0; @@ -10419,7 +10423,7 @@ rw_error: /*============================================================================= ===== ctrl_set_channel() ========================================================== ===========================================================================*/ -/** +/* * \fn int ctrl_set_channel() * \brief Select a new transmission channel. * \param demod instance of demod. @@ -10652,7 +10656,7 @@ rw_error: ===== SigQuality() ========================================================== ===========================================================================*/ -/** +/* * \fn int ctrl_sig_quality() * \brief Retrieve signal quality form device. * \param devmod Pointer to demodulator instance. @@ -10768,7 +10772,7 @@ rw_error: /*============================================================================*/ -/** +/* * \fn int ctrl_lock_status() * \brief Retrieve lock status . * \param dev_addr Pointer to demodulator device address. @@ -10856,7 +10860,7 @@ rw_error: /*============================================================================*/ -/** +/* * \fn int ctrl_set_standard() * \brief Set modulation standard to be used. * \param standard Modulation standard. @@ -11012,7 +11016,7 @@ static void drxj_reset_mode(struct drxj_data *ext_attr) ext_attr->vsb_pre_saw_cfg.use_pre_saw = true; } -/** +/* * \fn int ctrl_power_mode() * \brief Set the power mode of the device to the specified power mode * \param demod Pointer to demodulator instance. @@ -11074,7 +11078,7 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) } } - if ((*mode == DRX_POWER_UP)) { + if (*mode == DRX_POWER_UP) { /* Restore analog & pin configuration */ /* Initialize default AFE configuration for VSB */ @@ -11171,7 +11175,7 @@ rw_error: /*== CTRL Set/Get Config related functions ===================================*/ /*============================================================================*/ -/** +/* * \fn int ctrl_set_cfg_pre_saw() * \brief Set Pre-saw reference. * \param demod demod instance @@ -11234,7 +11238,7 @@ rw_error: /*============================================================================*/ -/** +/* * \fn int ctrl_set_cfg_afe_gain() * \brief Set AFE Gain. * \param demod demod instance @@ -11324,7 +11328,7 @@ static int drx_ctrl_u_code(struct drx_demod_instance *demod, enum drxu_code_action action); static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state); -/** +/* * \fn drxj_open() * \brief Open the demod instance, configure device, configure drxdriver * \return Status_t Return status. @@ -11543,7 +11547,7 @@ rw_error: } /*============================================================================*/ -/** +/* * \fn drxj_close() * \brief Close the demod instance, power down the device * \return Status_t Return status. @@ -11594,7 +11598,7 @@ rw_error: * Microcode related functions */ -/** +/* * drx_u_code_compute_crc - Compute CRC of block of microcode data. * @block_data: Pointer to microcode data. * @nr_words: Size of microcode block (number of 16 bits words). @@ -11622,7 +11626,7 @@ static u16 drx_u_code_compute_crc(u8 *block_data, u16 nr_words) return (u16)(crc_word >> 16); } -/** +/* * drx_check_firmware - checks if the loaded firmware is valid * * @demod: demod structure @@ -11708,7 +11712,7 @@ eof: return -EINVAL; } -/** +/* * drx_ctrl_u_code - Handle microcode upload or verify. * @dev_addr: Address of device. * @mc_info: Pointer to information about microcode data. @@ -11723,7 +11727,7 @@ eof: * - In case of UCODE_UPLOAD: I2C error. * - In case of UCODE_VERIFY: I2C error or image on device * is not equal to image provided to this control function. - * -EINVAL: + * -EINVAL: * - Invalid arguments. * - Provided image is corrupt */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h index 6c5b8f78f9f6..d3ee1c23bb2f 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -69,15 +69,15 @@ TYPEDEFS struct drxjscu_cmd { u16 command; - /**< Command number */ + /*< Command number */ u16 parameter_len; - /**< Data length in byte */ + /*< Data length in byte */ u16 result_len; - /**< result length in byte */ + /*< result length in byte */ u16 *parameter; - /**< General purpous param */ + /*< General purpous param */ u16 *result; - /**< General purpous param */}; + /*< General purpous param */}; /*============================================================================*/ /*============================================================================*/ @@ -130,7 +130,7 @@ TYPEDEFS DRXJ_CFG_MAX /* dummy, never to be used */}; -/** +/* * /struct enum drxj_cfg_smart_ant_io * smart antenna i/o. */ enum drxj_cfg_smart_ant_io { @@ -138,7 +138,7 @@ enum drxj_cfg_smart_ant_io { DRXJ_SMT_ANT_INPUT }; -/** +/* * /struct struct drxj_cfg_smart_ant * Set smart antenna. */ struct drxj_cfg_smart_ant { @@ -146,7 +146,7 @@ enum drxj_cfg_smart_ant_io { u16 ctrl_data; }; -/** +/* * /struct DRXJAGCSTATUS_t * AGC status information from the DRXJ-IQM-AF. */ @@ -158,7 +158,7 @@ struct drxj_agc_status { /* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */ -/** +/* * /struct enum drxj_agc_ctrl_mode * Available AGCs modes in the DRXJ. */ enum drxj_agc_ctrl_mode { @@ -166,7 +166,7 @@ struct drxj_agc_status { DRX_AGC_CTRL_USER, DRX_AGC_CTRL_OFF}; -/** +/* * /struct struct drxj_cfg_agc * Generic interface for all AGCs present on the DRXJ. */ struct drxj_cfg_agc { @@ -182,7 +182,7 @@ struct drxj_agc_status { /* DRXJ_CFG_PRE_SAW */ -/** +/* * /struct struct drxj_cfg_pre_saw * Interface to configure pre SAW sense. */ struct drxj_cfg_pre_saw { @@ -192,14 +192,14 @@ struct drxj_agc_status { /* DRXJ_CFG_AFE_GAIN */ -/** +/* * /struct struct drxj_cfg_afe_gain * Interface to configure gain of AFE (LNA + PGA). */ struct drxj_cfg_afe_gain { enum drx_standard standard; /* standard to which these settings apply */ u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */}; -/** +/* * /struct drxjrs_errors * Available failure information in DRXJ_FEC_RS. * @@ -208,25 +208,25 @@ struct drxj_agc_status { */ struct drxjrs_errors { u16 nr_bit_errors; - /**< no of pre RS bit errors */ + /*< no of pre RS bit errors */ u16 nr_symbol_errors; - /**< no of pre RS symbol errors */ + /*< no of pre RS symbol errors */ u16 nr_packet_errors; - /**< no of pre RS packet errors */ + /*< no of pre RS packet errors */ u16 nr_failures; - /**< no of post RS failures to decode */ + /*< no of post RS failures to decode */ u16 nr_snc_par_fail_count; - /**< no of post RS bit erros */ + /*< no of post RS bit erros */ }; -/** +/* * /struct struct drxj_cfg_vsb_misc * symbol error rate */ struct drxj_cfg_vsb_misc { u32 symb_error; - /**< symbol error rate sps */}; + /*< symbol error rate sps */}; -/** +/* * /enum enum drxj_mpeg_output_clock_rate * Mpeg output clock rate. * */ @@ -234,7 +234,7 @@ struct drxj_agc_status { DRXJ_MPEG_START_WIDTH_1CLKCYC, DRXJ_MPEG_START_WIDTH_8CLKCYC}; -/** +/* * /enum enum drxj_mpeg_output_clock_rate * Mpeg output clock rate. * */ @@ -247,20 +247,20 @@ struct drxj_agc_status { DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K, DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K}; -/** +/* * /struct DRXJCfgMisc_t * Change TEI bit of MPEG output * reverse MPEG output bit order * set MPEG output clock rate */ struct drxj_cfg_mpeg_output_misc { - bool disable_tei_handling; /**< if true pass (not change) TEI bit */ - bool bit_reverse_mpeg_outout; /**< if true, parallel: msb on MD0; serial: lsb out first */ + bool disable_tei_handling; /*< if true pass (not change) TEI bit */ + bool bit_reverse_mpeg_outout; /*< if true, parallel: msb on MD0; serial: lsb out first */ enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate; - /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */ - enum drxj_mpeg_start_width mpeg_start_width; /**< set MPEG output start width */}; + /*< set MPEG output clock rate that overwirtes the derived one from symbol rate */ + enum drxj_mpeg_start_width mpeg_start_width; /*< set MPEG output start width */}; -/** +/* * /enum enum drxj_xtal_freq * Supported external crystal reference frequency. */ enum drxj_xtal_freq { @@ -269,21 +269,21 @@ struct drxj_agc_status { DRXJ_XTAL_FREQ_20P25MHZ, DRXJ_XTAL_FREQ_4MHZ}; -/** +/* * /enum enum drxj_xtal_freq * Supported external crystal reference frequency. */ enum drxji2c_speed { DRXJ_I2C_SPEED_400KBPS, DRXJ_I2C_SPEED_100KBPS}; -/** +/* * /struct struct drxj_cfg_hw_cfg * Get hw configuration, such as crystal reference frequency, I2C speed, etc... */ struct drxj_cfg_hw_cfg { enum drxj_xtal_freq xtal_freq; - /**< crystal reference frequency */ + /*< crystal reference frequency */ enum drxji2c_speed i2c_speed; - /**< 100 or 400 kbps */}; + /*< 100 or 400 kbps */}; /* * DRXJ_CFG_ATV_MISC @@ -352,7 +352,7 @@ struct drxj_cfg_oob_misc { * DRXJ_CFG_ATV_OUTPUT */ -/** +/* * /enum DRXJAttenuation_t * Attenuation setting for SIF AGC. * @@ -363,7 +363,7 @@ struct drxj_cfg_oob_misc { DRXJ_SIF_ATTENUATION_6DB, DRXJ_SIF_ATTENUATION_9DB}; -/** +/* * /struct struct drxj_cfg_atv_output * SIF attenuation setting. * */ @@ -398,7 +398,7 @@ struct drxj_cfg_atv_output { /*============================================================================*/ /*========================================*/ -/** +/* * /struct struct drxj_data * DRXJ specific attributes. * * Global data container for DRXJ specific data. @@ -406,93 +406,93 @@ struct drxj_cfg_atv_output { */ struct drxj_data { /* device capabilties (determined during drx_open()) */ - bool has_lna; /**< true if LNA (aka PGA) present */ - bool has_oob; /**< true if OOB supported */ - bool has_ntsc; /**< true if NTSC supported */ - bool has_btsc; /**< true if BTSC supported */ - bool has_smatx; /**< true if mat_tx is available */ - bool has_smarx; /**< true if mat_rx is available */ - bool has_gpio; /**< true if GPIO is available */ - bool has_irqn; /**< true if IRQN is available */ + bool has_lna; /*< true if LNA (aka PGA) present */ + bool has_oob; /*< true if OOB supported */ + bool has_ntsc; /*< true if NTSC supported */ + bool has_btsc; /*< true if BTSC supported */ + bool has_smatx; /*< true if mat_tx is available */ + bool has_smarx; /*< true if mat_rx is available */ + bool has_gpio; /*< true if GPIO is available */ + bool has_irqn; /*< true if IRQN is available */ /* A1/A2/A... */ - u8 mfx; /**< metal fix */ + u8 mfx; /*< metal fix */ /* tuner settings */ - bool mirror_freq_spect_oob;/**< tuner inversion (true = tuner mirrors the signal */ + bool mirror_freq_spect_oob;/*< tuner inversion (true = tuner mirrors the signal */ /* standard/channel settings */ - enum drx_standard standard; /**< current standard information */ + enum drx_standard standard; /*< current standard information */ enum drx_modulation constellation; - /**< current constellation */ - s32 frequency; /**< center signal frequency in KHz */ + /*< current constellation */ + s32 frequency; /*< center signal frequency in KHz */ enum drx_bandwidth curr_bandwidth; - /**< current channel bandwidth */ - enum drx_mirror mirror; /**< current channel mirror */ + /*< current channel bandwidth */ + enum drx_mirror mirror; /*< current channel mirror */ /* signal quality information */ - u32 fec_bits_desired; /**< BER accounting period */ - u16 fec_vd_plen; /**< no of trellis symbols: VD SER measurement period */ - u16 qam_vd_prescale; /**< Viterbi Measurement Prescale */ - u16 qam_vd_period; /**< Viterbi Measurement period */ - u16 fec_rs_plen; /**< defines RS BER measurement period */ - u16 fec_rs_prescale; /**< ReedSolomon Measurement Prescale */ - u16 fec_rs_period; /**< ReedSolomon Measurement period */ - bool reset_pkt_err_acc; /**< Set a flag to reset accumulated packet error */ - u16 pkt_err_acc_start; /**< Set a flag to reset accumulated packet error */ + u32 fec_bits_desired; /*< BER accounting period */ + u16 fec_vd_plen; /*< no of trellis symbols: VD SER measurement period */ + u16 qam_vd_prescale; /*< Viterbi Measurement Prescale */ + u16 qam_vd_period; /*< Viterbi Measurement period */ + u16 fec_rs_plen; /*< defines RS BER measurement period */ + u16 fec_rs_prescale; /*< ReedSolomon Measurement Prescale */ + u16 fec_rs_period; /*< ReedSolomon Measurement period */ + bool reset_pkt_err_acc; /*< Set a flag to reset accumulated packet error */ + u16 pkt_err_acc_start; /*< Set a flag to reset accumulated packet error */ /* HI configuration */ - u16 hi_cfg_timing_div; /**< HI Configure() parameter 2 */ - u16 hi_cfg_bridge_delay; /**< HI Configure() parameter 3 */ - u16 hi_cfg_wake_up_key; /**< HI Configure() parameter 4 */ - u16 hi_cfg_ctrl; /**< HI Configure() parameter 5 */ - u16 hi_cfg_transmit; /**< HI Configure() parameter 6 */ + u16 hi_cfg_timing_div; /*< HI Configure() parameter 2 */ + u16 hi_cfg_bridge_delay; /*< HI Configure() parameter 3 */ + u16 hi_cfg_wake_up_key; /*< HI Configure() parameter 4 */ + u16 hi_cfg_ctrl; /*< HI Configure() parameter 5 */ + u16 hi_cfg_transmit; /*< HI Configure() parameter 6 */ /* UIO configuration */ - enum drxuio_mode uio_sma_rx_mode;/**< current mode of SmaRx pin */ - enum drxuio_mode uio_sma_tx_mode;/**< current mode of SmaTx pin */ - enum drxuio_mode uio_gpio_mode; /**< current mode of ASEL pin */ - enum drxuio_mode uio_irqn_mode; /**< current mode of IRQN pin */ + enum drxuio_mode uio_sma_rx_mode;/*< current mode of SmaRx pin */ + enum drxuio_mode uio_sma_tx_mode;/*< current mode of SmaTx pin */ + enum drxuio_mode uio_gpio_mode; /*< current mode of ASEL pin */ + enum drxuio_mode uio_irqn_mode; /*< current mode of IRQN pin */ /* IQM fs frequecy shift and inversion */ - u32 iqm_fs_rate_ofs; /**< frequency shifter setting after setchannel */ - bool pos_image; /**< Ture: positive image */ + u32 iqm_fs_rate_ofs; /*< frequency shifter setting after setchannel */ + bool pos_image; /*< Ture: positive image */ /* IQM RC frequecy shift */ - u32 iqm_rc_rate_ofs; /**< frequency shifter setting after setchannel */ + u32 iqm_rc_rate_ofs; /*< frequency shifter setting after setchannel */ /* ATV configuration */ - u32 atv_cfg_changed_flags; /**< flag: flags cfg changes */ - s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */ - s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */ - s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */ - s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */ - bool phase_correction_bypass;/**< flag: true=bypass */ - s16 atv_top_vid_peak; /**< shadow of ATV_TOP_VID_PEAK__A */ - u16 atv_top_noise_th; /**< shadow of ATV_TOP_NOISE_TH__A */ - bool enable_cvbs_output; /**< flag CVBS ouput enable */ - bool enable_sif_output; /**< flag SIF ouput enable */ + u32 atv_cfg_changed_flags; /*< flag: flags cfg changes */ + s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU0__A */ + s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU1__A */ + s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU2__A */ + s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU3__A */ + bool phase_correction_bypass;/*< flag: true=bypass */ + s16 atv_top_vid_peak; /*< shadow of ATV_TOP_VID_PEAK__A */ + u16 atv_top_noise_th; /*< shadow of ATV_TOP_NOISE_TH__A */ + bool enable_cvbs_output; /*< flag CVBS ouput enable */ + bool enable_sif_output; /*< flag SIF ouput enable */ enum drxjsif_attenuation sif_attenuation; - /**< current SIF att setting */ + /*< current SIF att setting */ /* Agc configuration for QAM and VSB */ - struct drxj_cfg_agc qam_rf_agc_cfg; /**< qam RF AGC config */ - struct drxj_cfg_agc qam_if_agc_cfg; /**< qam IF AGC config */ - struct drxj_cfg_agc vsb_rf_agc_cfg; /**< vsb RF AGC config */ - struct drxj_cfg_agc vsb_if_agc_cfg; /**< vsb IF AGC config */ + struct drxj_cfg_agc qam_rf_agc_cfg; /*< qam RF AGC config */ + struct drxj_cfg_agc qam_if_agc_cfg; /*< qam IF AGC config */ + struct drxj_cfg_agc vsb_rf_agc_cfg; /*< vsb RF AGC config */ + struct drxj_cfg_agc vsb_if_agc_cfg; /*< vsb IF AGC config */ /* PGA gain configuration for QAM and VSB */ - u16 qam_pga_cfg; /**< qam PGA config */ - u16 vsb_pga_cfg; /**< vsb PGA config */ + u16 qam_pga_cfg; /*< qam PGA config */ + u16 vsb_pga_cfg; /*< vsb PGA config */ /* Pre SAW configuration for QAM and VSB */ struct drxj_cfg_pre_saw qam_pre_saw_cfg; - /**< qam pre SAW config */ + /*< qam pre SAW config */ struct drxj_cfg_pre_saw vsb_pre_saw_cfg; - /**< qam pre SAW config */ + /*< qam pre SAW config */ /* Version information */ - char v_text[2][12]; /**< allocated text versions */ - struct drx_version v_version[2]; /**< allocated versions structs */ + char v_text[2][12]; /*< allocated text versions */ + struct drx_version v_version[2]; /*< allocated versions structs */ struct drx_version_list v_list_elements[2]; - /**< allocated version list */ + /*< allocated version list */ /* smart antenna configuration */ bool smart_ant_inverted; @@ -502,25 +502,25 @@ struct drxj_cfg_atv_output { bool oob_power_on; /* MPEG static bitrate setting */ - u32 mpeg_ts_static_bitrate; /**< bitrate static MPEG output */ - bool disable_te_ihandling; /**< MPEG TS TEI handling */ - bool bit_reverse_mpeg_outout;/**< MPEG output bit order */ + u32 mpeg_ts_static_bitrate; /*< bitrate static MPEG output */ + bool disable_te_ihandling; /*< MPEG TS TEI handling */ + bool bit_reverse_mpeg_outout;/*< MPEG output bit order */ enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate; - /**< MPEG output clock rate */ + /*< MPEG output clock rate */ enum drxj_mpeg_start_width mpeg_start_width; - /**< MPEG Start width */ + /*< MPEG Start width */ /* Pre SAW & Agc configuration for ATV */ struct drxj_cfg_pre_saw atv_pre_saw_cfg; - /**< atv pre SAW config */ - struct drxj_cfg_agc atv_rf_agc_cfg; /**< atv RF AGC config */ - struct drxj_cfg_agc atv_if_agc_cfg; /**< atv IF AGC config */ - u16 atv_pga_cfg; /**< atv pga config */ + /*< atv pre SAW config */ + struct drxj_cfg_agc atv_rf_agc_cfg; /*< atv RF AGC config */ + struct drxj_cfg_agc atv_if_agc_cfg; /*< atv IF AGC config */ + u16 atv_pga_cfg; /*< atv pga config */ u32 curr_symbol_rate; /* pin-safe mode */ - bool pdr_safe_mode; /**< PDR safe mode activated */ + bool pdr_safe_mode; /*< PDR safe mode activated */ u16 pdr_safe_restore_val_gpio; u16 pdr_safe_restore_val_v_sync; u16 pdr_safe_restore_val_sma_rx; @@ -531,12 +531,12 @@ struct drxj_cfg_atv_output { enum drxj_cfg_oob_lo_power oob_lo_pow; struct drx_aud_data aud_data; - /**< audio storage */}; + /*< audio storage */}; /*------------------------------------------------------------------------- Access MACROS -------------------------------------------------------------------------*/ -/** +/* * \brief Compilable references to attributes * \param d pointer to demod instance * @@ -554,7 +554,7 @@ Access MACROS DEFINES -------------------------------------------------------------------------*/ -/** +/* * \def DRXJ_NTSC_CARRIER_FREQ_OFFSET * \brief Offset from picture carrier to centre frequency in kHz, in RF domain * @@ -569,7 +569,7 @@ DEFINES */ #define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((s32)(1750)) -/** +/* * \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET * \brief Offset from picture carrier to centre frequency in kHz, in RF domain * @@ -585,7 +585,7 @@ DEFINES */ #define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((s32)(2375)) -/** +/* * \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET * \brief Offset from picture carrier to centre frequency in kHz, in RF domain * @@ -601,7 +601,7 @@ DEFINES */ #define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((s32)(2775)) -/** +/* * \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET * \brief Offset from picture carrier to centre frequency in kHz, in RF domain * @@ -616,7 +616,7 @@ DEFINES */ #define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((s32)(-3255)) -/** +/* * \def DRXJ_FM_CARRIER_FREQ_OFFSET * \brief Offset from sound carrier to centre frequency in kHz, in RF domain * diff --git a/drivers/media/dvb-frontends/drxd_hard.c b/drivers/media/dvb-frontends/drxd_hard.c index 0696bc62dcc9..3b7d31a22d82 100644 --- a/drivers/media/dvb-frontends/drxd_hard.c +++ b/drivers/media/dvb-frontends/drxd_hard.c @@ -26,7 +26,7 @@ #include <linux/i2c.h> #include <asm/div64.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "drxd.h" #include "drxd_firm.h" @@ -972,7 +972,6 @@ static int DownloadMicrocode(struct drxd_state *state, static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult) { u32 nrRetries = 0; - u16 waitCmd; int status; status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0); @@ -985,8 +984,8 @@ static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult) status = -1; break; } - status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0); - } while (waitCmd != 0); + status = Read16(state, HI_RA_RAM_SRV_CMD__A, NULL, 0); + } while (status != 0); if (status >= 0) status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0); @@ -1298,12 +1297,11 @@ static int InitFT(struct drxd_state *state) static int SC_WaitForReady(struct drxd_state *state) { - u16 curCmd; int i; for (i = 0; i < DRXD_MAX_RETRIES; i += 1) { - int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0); - if (status == 0 || curCmd == 0) + int status = Read16(state, SC_RA_RAM_CMD__A, NULL, 0); + if (status == 0) return status; } return -1; @@ -1311,15 +1309,15 @@ static int SC_WaitForReady(struct drxd_state *state) static int SC_SendCommand(struct drxd_state *state, u16 cmd) { - int status = 0; + int status = 0, ret; u16 errCode; Write16(state, SC_RA_RAM_CMD__A, cmd, 0); SC_WaitForReady(state); - Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0); + ret = Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0); - if (errCode == 0xFFFF) { + if (ret < 0 || errCode == 0xFFFF) { printk(KERN_ERR "Command Error\n"); status = -1; } @@ -1330,13 +1328,13 @@ static int SC_SendCommand(struct drxd_state *state, u16 cmd) static int SC_ProcStartCommand(struct drxd_state *state, u16 subCmd, u16 param0, u16 param1) { - int status = 0; + int ret, status = 0; u16 scExec; mutex_lock(&state->mutex); do { - Read16(state, SC_COMM_EXEC__A, &scExec, 0); - if (scExec != 1) { + ret = Read16(state, SC_COMM_EXEC__A, &scExec, 0); + if (ret < 0 || scExec != 1) { status = -1; break; } @@ -2140,7 +2138,6 @@ static int DRX_Start(struct drxd_state *state, s32 off) } break; } - status = status; if (status < 0) break; @@ -2251,7 +2248,6 @@ static int DRX_Start(struct drxd_state *state, s32 off) break; } - status = status; if (status < 0) break; @@ -2318,7 +2314,6 @@ static int DRX_Start(struct drxd_state *state, s32 off) } break; } - status = status; if (status < 0) break; diff --git a/drivers/media/dvb-frontends/drxk.h b/drivers/media/dvb-frontends/drxk.h index eb9bdc9f59c4..76466f7ec3a0 100644 --- a/drivers/media/dvb-frontends/drxk.h +++ b/drivers/media/dvb-frontends/drxk.h @@ -10,7 +10,7 @@ * * @adr: I2C address of the DRX-K * @parallel_ts: True means that the device uses parallel TS, - * Serial otherwise. + * Serial otherwise. * @dynamic_clk: True means that the clock will be dynamically * adjusted. Static clock otherwise. * @enable_merr_cfg: Enable SIO_PDR_PERR_CFG/SIO_PDR_MVAL_CFG. @@ -20,17 +20,18 @@ * @antenna_dvbt: GPIO bit for changing antenna to DVB-C. A value of 1 * means that 1=DVBC, 0 = DVBT. Zero means the opposite. * @mpeg_out_clk_strength: DRXK Mpeg output clock drive strength. + * @chunk_size: maximum size for I2C messages * @microcode_name: Name of the firmware file with the microcode * @qam_demod_parameter_count: The number of parameters used for the command * to set the demodulator parameters. All * firmwares are using the 2-parameter commmand. - * An exception is the "drxk_a3.mc" firmware, + * An exception is the ``drxk_a3.mc`` firmware, * which uses the 4-parameter command. * A value of 0 (default) or lower indicates that * the correct number of parameters will be * automatically detected. * - * On the *_gpio vars, bit 0 is UIO-1, bit 1 is UIO-2 and bit 2 is + * On the ``*_gpio`` vars, bit 0 is UIO-1, bit 1 is UIO-2 and bit 2 is * UIO-3. */ struct drxk_config { @@ -52,14 +53,22 @@ struct drxk_config { }; #if IS_REACHABLE(CONFIG_DVB_DRXK) +/** + * Attach a drxk demod + * + * @config: pointer to &struct drxk_config with demod configuration. + * @i2c: i2c adapter to use. + * + * return: FE pointer on success, NULL on failure. + */ extern struct dvb_frontend *drxk_attach(const struct drxk_config *config, struct i2c_adapter *i2c); #else static inline struct dvb_frontend *drxk_attach(const struct drxk_config *config, struct i2c_adapter *i2c) { - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); - return NULL; + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; } #endif diff --git a/drivers/media/dvb-frontends/drxk_hard.c b/drivers/media/dvb-frontends/drxk_hard.c index 48a8aad47a74..5a26ad93be10 100644 --- a/drivers/media/dvb-frontends/drxk_hard.c +++ b/drivers/media/dvb-frontends/drxk_hard.c @@ -29,10 +29,10 @@ #include <linux/hardirq.h> #include <asm/div64.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "drxk.h" #include "drxk_hard.h" -#include "dvb_math.h" +#include <media/dvb_math.h> static int power_down_dvbt(struct drxk_state *state, bool set_power_mode); static int power_down_qam(struct drxk_state *state); @@ -207,9 +207,9 @@ static inline u32 log10times100(u32 value) return (100L * intlog10(value)) >> 24; } -/****************************************************************************/ +/***************************************************************************/ /* I2C **********************************************************************/ -/****************************************************************************/ +/***************************************************************************/ static int drxk_i2c_lock(struct drxk_state *state) { @@ -3444,7 +3444,7 @@ error: /*============================================================================*/ -/** +/* * \brief Activate DVBT specific presets * \param demod instance of demodulator. * \return DRXStatus_t. @@ -3484,7 +3484,7 @@ error: /*============================================================================*/ -/** +/* * \brief Initialize channelswitch-independent settings for DVBT. * \param demod instance of demodulator. * \return DRXStatus_t. @@ -3696,7 +3696,7 @@ error: } /*============================================================================*/ -/** +/* * \brief start dvbt demodulating for channel. * \param demod instance of demodulator. * \return DRXStatus_t. @@ -3732,7 +3732,7 @@ error: /*============================================================================*/ -/** +/* * \brief Set up dvbt demodulator for channel. * \param demod instance of demodulator. * \return DRXStatus_t. @@ -4086,7 +4086,7 @@ error: /*============================================================================*/ -/** +/* * \brief Retrieve lock status . * \param demod Pointer to demodulator instance. * \param lockStat Pointer to lock status structure. @@ -4148,7 +4148,7 @@ static int power_up_qam(struct drxk_state *state) } -/** Power Down QAM */ +/* Power Down QAM */ static int power_down_qam(struct drxk_state *state) { u16 data = 0; @@ -4186,7 +4186,7 @@ error: /*============================================================================*/ -/** +/* * \brief Setup of the QAM Measurement intervals for signal quality * \param demod instance of demod. * \param modulation current modulation. @@ -4461,7 +4461,7 @@ error: /*============================================================================*/ -/** +/* * \brief QAM32 specific setup * \param demod instance of demod. * \return DRXStatus_t. @@ -4657,7 +4657,7 @@ error: /*============================================================================*/ -/** +/* * \brief QAM64 specific setup * \param demod instance of demod. * \return DRXStatus_t. @@ -4852,7 +4852,7 @@ error: /*============================================================================*/ -/** +/* * \brief QAM128 specific setup * \param demod: instance of demod. * \return DRXStatus_t. @@ -5049,7 +5049,7 @@ error: /*============================================================================*/ -/** +/* * \brief QAM256 specific setup * \param demod: instance of demod. * \return DRXStatus_t. @@ -5244,7 +5244,7 @@ error: /*============================================================================*/ -/** +/* * \brief Reset QAM block. * \param demod: instance of demod. * \param channel: pointer to channel data. @@ -5272,7 +5272,7 @@ error: /*============================================================================*/ -/** +/* * \brief Set QAM symbolrate. * \param demod: instance of demod. * \param channel: pointer to channel data. @@ -5341,7 +5341,7 @@ error: /*============================================================================*/ -/** +/* * \brief Get QAM lock status. * \param demod: instance of demod. * \param channel: pointer to channel data. @@ -6062,7 +6062,7 @@ static int init_drxk(struct drxk_state *state) u16 driver_version; dprintk(1, "\n"); - if ((state->m_drxk_state == DRXK_UNINITIALIZED)) { + if (state->m_drxk_state == DRXK_UNINITIALIZED) { drxk_i2c_lock(state); status = power_up_device(state); if (status < 0) diff --git a/drivers/media/dvb-frontends/ds3000.c b/drivers/media/dvb-frontends/ds3000.c index bd4f8278c906..2ff90e5eabce 100644 --- a/drivers/media/dvb-frontends/ds3000.c +++ b/drivers/media/dvb-frontends/ds3000.c @@ -26,7 +26,7 @@ #include <linux/init.h> #include <linux/firmware.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "ts2020.h" #include "ds3000.h" diff --git a/drivers/media/dvb-frontends/dvb-pll.h b/drivers/media/dvb-frontends/dvb-pll.h index 6aaa9c6bff9c..ca885e71d2f0 100644 --- a/drivers/media/dvb-frontends/dvb-pll.h +++ b/drivers/media/dvb-frontends/dvb-pll.h @@ -7,7 +7,7 @@ #define __DVB_PLL_H__ #include <linux/i2c.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #define DVB_PLL_UNDEFINED 0 #define DVB_PLL_THOMSON_DTT7579 1 @@ -30,16 +30,17 @@ #define DVB_PLL_TDEE4 18 #define DVB_PLL_THOMSON_DTT7520X 19 +#if IS_REACHABLE(CONFIG_DVB_PLL) /** * Attach a dvb-pll to the supplied frontend structure. * - * @param fe Frontend to attach to. - * @param pll_addr i2c address of the PLL (if used). - * @param i2c i2c adapter to use (set to NULL if not used). - * @param pll_desc_id dvb_pll_desc to use. - * @return Frontend pointer on success, NULL on failure + * @fe: Frontend to attach to. + * @pll_addr: i2c address of the PLL (if used). + * @i2c: i2c adapter to use (set to NULL if not used). + * @pll_desc_id: dvb_pll_desc to use. + * + * return: Frontend pointer on success, NULL on failure */ -#if IS_REACHABLE(CONFIG_DVB_PLL) extern struct dvb_frontend *dvb_pll_attach(struct dvb_frontend *fe, int pll_addr, struct i2c_adapter *i2c, diff --git a/drivers/media/dvb-frontends/dvb_dummy_fe.c b/drivers/media/dvb-frontends/dvb_dummy_fe.c index 50b2b666ef6c..6650d4f61ef2 100644 --- a/drivers/media/dvb-frontends/dvb_dummy_fe.c +++ b/drivers/media/dvb-frontends/dvb_dummy_fe.c @@ -20,7 +20,7 @@ #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "dvb_dummy_fe.h" diff --git a/drivers/media/dvb-frontends/dvb_dummy_fe.h b/drivers/media/dvb-frontends/dvb_dummy_fe.h index 86dd7b9d1e57..7aacef4b7c80 100644 --- a/drivers/media/dvb-frontends/dvb_dummy_fe.h +++ b/drivers/media/dvb-frontends/dvb_dummy_fe.h @@ -19,7 +19,7 @@ #define DVB_DUMMY_FE_H #include <linux/dvb/frontend.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #if IS_REACHABLE(CONFIG_DVB_DUMMY_FE) extern struct dvb_frontend* dvb_dummy_fe_ofdm_attach(void); diff --git a/drivers/media/dvb-frontends/ec100.c b/drivers/media/dvb-frontends/ec100.c index fa2a96d5f94e..c2575fdcc811 100644 --- a/drivers/media/dvb-frontends/ec100.c +++ b/drivers/media/dvb-frontends/ec100.c @@ -15,7 +15,7 @@ * */ -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "ec100.h" struct ec100_state { diff --git a/drivers/media/dvb-frontends/gp8psk-fe.c b/drivers/media/dvb-frontends/gp8psk-fe.c index efe015df7f1d..a772ef8bfe1c 100644 --- a/drivers/media/dvb-frontends/gp8psk-fe.c +++ b/drivers/media/dvb-frontends/gp8psk-fe.c @@ -16,7 +16,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include "gp8psk-fe.h" -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> static int debug; module_param(debug, int, 0644); diff --git a/drivers/media/dvb-frontends/helene.c b/drivers/media/dvb-frontends/helene.c index 4bf5a551ba40..a0d0b53c91d7 100644 --- a/drivers/media/dvb-frontends/helene.c +++ b/drivers/media/dvb-frontends/helene.c @@ -23,7 +23,7 @@ #include <linux/dvb/frontend.h> #include <linux/types.h> #include "helene.h" -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #define MAX_WRITE_REGSIZE 20 @@ -331,7 +331,9 @@ static int helene_write_regs(struct helene_priv *priv, static int helene_write_reg(struct helene_priv *priv, u8 reg, u8 val) { - return helene_write_regs(priv, reg, &val, 1); + u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ + + return helene_write_regs(priv, reg, &tmp, 1); } static int helene_read_regs(struct helene_priv *priv, diff --git a/drivers/media/dvb-frontends/helene.h b/drivers/media/dvb-frontends/helene.h index 333615491d9e..c9fc81c7e4e7 100644 --- a/drivers/media/dvb-frontends/helene.h +++ b/drivers/media/dvb-frontends/helene.h @@ -38,6 +38,7 @@ enum helene_xtal { * @set_tuner_priv: Callback function private context * @set_tuner_callback: Callback function that notifies the parent driver * which tuner is active now + * @xtal: Cristal frequency as described by &enum helene_xtal */ struct helene_config { u8 i2c_address; @@ -48,9 +49,31 @@ struct helene_config { }; #if IS_REACHABLE(CONFIG_DVB_HELENE) +/** + * Attach a helene tuner (terrestrial and cable standards) + * + * @fe: frontend to be attached + * @config: pointer to &struct helene_config with tuner configuration. + * @i2c: i2c adapter to use. + * + * return: FE pointer on success, NULL on failure. + */ extern struct dvb_frontend *helene_attach(struct dvb_frontend *fe, const struct helene_config *config, struct i2c_adapter *i2c); + +/** + * Attach a helene tuner (satellite standards) + * + * @fe: frontend to be attached + * @config: pointer to &struct helene_config with tuner configuration. + * @i2c: i2c adapter to use. + * + * return: FE pointer on success, NULL on failure. + */ +extern struct dvb_frontend *helene_attach_s(struct dvb_frontend *fe, + const struct helene_config *config, + struct i2c_adapter *i2c); #else static inline struct dvb_frontend *helene_attach(struct dvb_frontend *fe, const struct helene_config *config, @@ -59,13 +82,6 @@ static inline struct dvb_frontend *helene_attach(struct dvb_frontend *fe, pr_warn("%s: driver disabled by Kconfig\n", __func__); return NULL; } -#endif - -#if IS_REACHABLE(CONFIG_DVB_HELENE) -extern struct dvb_frontend *helene_attach_s(struct dvb_frontend *fe, - const struct helene_config *config, - struct i2c_adapter *i2c); -#else static inline struct dvb_frontend *helene_attach_s(struct dvb_frontend *fe, const struct helene_config *config, struct i2c_adapter *i2c) diff --git a/drivers/media/dvb-frontends/horus3a.c b/drivers/media/dvb-frontends/horus3a.c index 68d759c4c52e..5e7e265a52e6 100644 --- a/drivers/media/dvb-frontends/horus3a.c +++ b/drivers/media/dvb-frontends/horus3a.c @@ -24,7 +24,7 @@ #include <linux/dvb/frontend.h> #include <linux/types.h> #include "horus3a.h" -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #define MAX_WRITE_REGSIZE 5 @@ -89,7 +89,9 @@ static int horus3a_write_regs(struct horus3a_priv *priv, static int horus3a_write_reg(struct horus3a_priv *priv, u8 reg, u8 val) { - return horus3a_write_regs(priv, reg, &val, 1); + u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ + + return horus3a_write_regs(priv, reg, &tmp, 1); } static int horus3a_enter_power_save(struct horus3a_priv *priv) diff --git a/drivers/media/dvb-frontends/horus3a.h b/drivers/media/dvb-frontends/horus3a.h index 672a556df71a..9157fd037e2f 100644 --- a/drivers/media/dvb-frontends/horus3a.h +++ b/drivers/media/dvb-frontends/horus3a.h @@ -41,6 +41,15 @@ struct horus3a_config { }; #if IS_REACHABLE(CONFIG_DVB_HORUS3A) +/** + * Attach a horus3a tuner + * + * @fe: frontend to be attached + * @config: pointer to &struct helene_config with tuner configuration. + * @i2c: i2c adapter to use. + * + * return: FE pointer on success, NULL on failure. + */ extern struct dvb_frontend *horus3a_attach(struct dvb_frontend *fe, const struct horus3a_config *config, struct i2c_adapter *i2c); diff --git a/drivers/media/dvb-frontends/isl6405.c b/drivers/media/dvb-frontends/isl6405.c index 2fc8d3c72c11..3bc78f8ffc00 100644 --- a/drivers/media/dvb-frontends/isl6405.c +++ b/drivers/media/dvb-frontends/isl6405.c @@ -29,7 +29,7 @@ #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "isl6405.h" struct isl6405 { diff --git a/drivers/media/dvb-frontends/isl6421.c b/drivers/media/dvb-frontends/isl6421.c index 3f3487887672..ae8ec59b665c 100644 --- a/drivers/media/dvb-frontends/isl6421.c +++ b/drivers/media/dvb-frontends/isl6421.c @@ -29,7 +29,7 @@ #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "isl6421.h" struct isl6421 { diff --git a/drivers/media/dvb-frontends/isl6423.c b/drivers/media/dvb-frontends/isl6423.c index dca5bebfeeb5..3dd2465d17cf 100644 --- a/drivers/media/dvb-frontends/isl6423.c +++ b/drivers/media/dvb-frontends/isl6423.c @@ -26,7 +26,7 @@ #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "isl6423.h" static unsigned int verbose; diff --git a/drivers/media/dvb-frontends/itd1000.c b/drivers/media/dvb-frontends/itd1000.c index 5bb1e73a10b4..04f7f6854f73 100644 --- a/drivers/media/dvb-frontends/itd1000.c +++ b/drivers/media/dvb-frontends/itd1000.c @@ -22,7 +22,7 @@ #include <linux/i2c.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "itd1000.h" #include "itd1000_priv.h" @@ -95,8 +95,9 @@ static int itd1000_read_reg(struct itd1000_state *state, u8 reg) static inline int itd1000_write_reg(struct itd1000_state *state, u8 r, u8 v) { - int ret = itd1000_write_regs(state, r, &v, 1); - state->shadow[r] = v; + u8 tmp = v; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ + int ret = itd1000_write_regs(state, r, &tmp, 1); + state->shadow[r] = tmp; return ret; } diff --git a/drivers/media/dvb-frontends/ix2505v.c b/drivers/media/dvb-frontends/ix2505v.c index 534b24fa2b95..965012ad5c59 100644 --- a/drivers/media/dvb-frontends/ix2505v.c +++ b/drivers/media/dvb-frontends/ix2505v.c @@ -1,4 +1,4 @@ -/** +/* * Driver for Sharp IX2505V (marked B0017) DVB-S silicon tuner * * Copyright (C) 2010 Malcolm Priestley @@ -36,7 +36,7 @@ struct ix2505v_state { u32 frequency; }; -/** +/* * Data read format of the Sharp IX2505V B0017 * * byte1: 1 | 1 | 0 | 0 | 0 | MA1 | MA0 | 1 @@ -99,7 +99,7 @@ static void ix2505v_release(struct dvb_frontend *fe) } -/** +/* * Data write format of the Sharp IX2505V B0017 * * byte1: 1 | 1 | 0 | 0 | 0 | 0(MA1)| 0(MA0)| 0 diff --git a/drivers/media/dvb-frontends/ix2505v.h b/drivers/media/dvb-frontends/ix2505v.h index 0b0a431c74f6..20b1eb3dda1a 100644 --- a/drivers/media/dvb-frontends/ix2505v.h +++ b/drivers/media/dvb-frontends/ix2505v.h @@ -17,34 +17,36 @@ #define DVB_IX2505V_H #include <linux/i2c.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> /** - * Attach a ix2505v tuner to the supplied frontend structure. + * struct ix2505v_config - ix2505 attachment configuration * - * @param fe Frontend to attach to. - * @param config ix2505v_config structure - * @return FE pointer on success, NULL on failure. + * @tuner_address: tuner address + * @tuner_gain: Baseband AMP gain control 0/1=0dB(default) 2=-2bB 3=-4dB + * @tuner_chargepump: Charge pump output +/- 0=120 1=260 2=555 3=1200(default) + * @min_delay_ms: delay after tune + * @tuner_write_only: disables reads */ - struct ix2505v_config { u8 tuner_address; - - /*Baseband AMP gain control 0/1=0dB(default) 2=-2bB 3=-4dB */ u8 tuner_gain; - - /*Charge pump output +/- 0=120 1=260 2=555 3=1200(default) */ u8 tuner_chargepump; - - /* delay after tune */ int min_delay_ms; - - /* disables reads*/ u8 tuner_write_only; }; #if IS_REACHABLE(CONFIG_DVB_IX2505V) +/** + * Attach a ix2505v tuner to the supplied frontend structure. + * + * @fe: Frontend to attach to. + * @config: pointer to &struct ix2505v_config + * @i2c: pointer to &struct i2c_adapter. + * + * return: FE pointer on success, NULL on failure. + */ extern struct dvb_frontend *ix2505v_attach(struct dvb_frontend *fe, const struct ix2505v_config *config, struct i2c_adapter *i2c); #else diff --git a/drivers/media/dvb-frontends/l64781.c b/drivers/media/dvb-frontends/l64781.c index 68923c84679a..e056f36e6f0c 100644 --- a/drivers/media/dvb-frontends/l64781.c +++ b/drivers/media/dvb-frontends/l64781.c @@ -25,7 +25,7 @@ #include <linux/module.h> #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "l64781.h" @@ -517,7 +517,7 @@ struct dvb_frontend* l64781_attach(const struct l64781_config* config, state->i2c = i2c; state->first = 1; - /** + /* * the L64781 won't show up before we send the reset_and_configure() * broadcast. If nothing responds there is no L64781 on the bus... */ diff --git a/drivers/media/dvb-frontends/lg2160.h b/drivers/media/dvb-frontends/lg2160.h index ba99125deac0..df817aec29e2 100644 --- a/drivers/media/dvb-frontends/lg2160.h +++ b/drivers/media/dvb-frontends/lg2160.h @@ -19,7 +19,7 @@ #define _LG2160_H_ #include <linux/i2c.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> enum lg_chip_type { LG2160 = 0, diff --git a/drivers/media/dvb-frontends/lgdt3305.c b/drivers/media/dvb-frontends/lgdt3305.c index 0af4d9104761..735d73060265 100644 --- a/drivers/media/dvb-frontends/lgdt3305.c +++ b/drivers/media/dvb-frontends/lgdt3305.c @@ -20,7 +20,7 @@ #include <asm/div64.h> #include <linux/dvb/frontend.h> #include <linux/slab.h> -#include "dvb_math.h" +#include <media/dvb_math.h> #include "lgdt3305.h" static int debug; diff --git a/drivers/media/dvb-frontends/lgdt3305.h b/drivers/media/dvb-frontends/lgdt3305.h index 2fb60d91f7b4..a54daaee823a 100644 --- a/drivers/media/dvb-frontends/lgdt3305.h +++ b/drivers/media/dvb-frontends/lgdt3305.h @@ -19,7 +19,7 @@ #define _LGDT3305_H_ #include <linux/i2c.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> enum lgdt3305_mpeg_mode { diff --git a/drivers/media/dvb-frontends/lgdt3306a.c b/drivers/media/dvb-frontends/lgdt3306a.c index 724e9aac0f11..6356815cf3e1 100644 --- a/drivers/media/dvb-frontends/lgdt3306a.c +++ b/drivers/media/dvb-frontends/lgdt3306a.c @@ -21,7 +21,7 @@ #include <asm/div64.h> #include <linux/kernel.h> #include <linux/dvb/frontend.h> -#include "dvb_math.h" +#include <media/dvb_math.h> #include "lgdt3306a.h" #include <linux/i2c-mux.h> diff --git a/drivers/media/dvb-frontends/lgdt3306a.h b/drivers/media/dvb-frontends/lgdt3306a.h index 6ce337ec5272..8b53044f5bdb 100644 --- a/drivers/media/dvb-frontends/lgdt3306a.h +++ b/drivers/media/dvb-frontends/lgdt3306a.h @@ -19,7 +19,7 @@ #define _LGDT3306A_H_ #include <linux/i2c.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> enum lgdt3306a_mpeg_mode { diff --git a/drivers/media/dvb-frontends/lgdt330x.c b/drivers/media/dvb-frontends/lgdt330x.c index 06f47dc8cd3d..8ad03bd81af5 100644 --- a/drivers/media/dvb-frontends/lgdt330x.c +++ b/drivers/media/dvb-frontends/lgdt330x.c @@ -37,8 +37,8 @@ #include <linux/slab.h> #include <asm/byteorder.h> -#include "dvb_frontend.h" -#include "dvb_math.h" +#include <media/dvb_frontend.h> +#include <media/dvb_math.h> #include "lgdt330x_priv.h" #include "lgdt330x.h" diff --git a/drivers/media/dvb-frontends/lgs8gl5.c b/drivers/media/dvb-frontends/lgs8gl5.c index 970e42fdbc1b..f47e5a1af16d 100644 --- a/drivers/media/dvb-frontends/lgs8gl5.c +++ b/drivers/media/dvb-frontends/lgs8gl5.c @@ -25,7 +25,7 @@ #include <linux/module.h> #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "lgs8gl5.h" diff --git a/drivers/media/dvb-frontends/lgs8gxx.c b/drivers/media/dvb-frontends/lgs8gxx.c index e6bf60e1138c..84af8a12f26a 100644 --- a/drivers/media/dvb-frontends/lgs8gxx.c +++ b/drivers/media/dvb-frontends/lgs8gxx.c @@ -22,7 +22,7 @@ #include <asm/div64.h> #include <linux/firmware.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "lgs8gxx.h" #include "lgs8gxx_priv.h" diff --git a/drivers/media/dvb-frontends/lnbh25.c b/drivers/media/dvb-frontends/lnbh25.c index cb486e879fdd..0b388502c298 100644 --- a/drivers/media/dvb-frontends/lnbh25.c +++ b/drivers/media/dvb-frontends/lnbh25.c @@ -23,7 +23,7 @@ #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "lnbh25.h" /** diff --git a/drivers/media/dvb-frontends/lnbp21.c b/drivers/media/dvb-frontends/lnbp21.c index 392d7be93774..d9966a338a72 100644 --- a/drivers/media/dvb-frontends/lnbp21.c +++ b/drivers/media/dvb-frontends/lnbp21.c @@ -29,7 +29,7 @@ #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "lnbp21.h" #include "lnbh24.h" diff --git a/drivers/media/dvb-frontends/lnbp22.c b/drivers/media/dvb-frontends/lnbp22.c index 39326a2ebab2..a62e82bf46f5 100644 --- a/drivers/media/dvb-frontends/lnbp22.c +++ b/drivers/media/dvb-frontends/lnbp22.c @@ -30,7 +30,7 @@ #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "lnbp22.h" static int debug; diff --git a/drivers/media/dvb-frontends/m88ds3103.c b/drivers/media/dvb-frontends/m88ds3103.c index 50bce68ffd66..65d157fe76d1 100644 --- a/drivers/media/dvb-frontends/m88ds3103.c +++ b/drivers/media/dvb-frontends/m88ds3103.c @@ -1262,11 +1262,12 @@ static int m88ds3103_select(struct i2c_mux_core *muxc, u32 chan) * New users must use I2C client binding directly! */ struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg, - struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter) + struct i2c_adapter *i2c, + struct i2c_adapter **tuner_i2c_adapter) { struct i2c_client *client; struct i2c_board_info board_info; - struct m88ds3103_platform_data pdata; + struct m88ds3103_platform_data pdata = {}; pdata.clk = cfg->clock; pdata.i2c_wr_max = cfg->i2c_wr_max; @@ -1409,6 +1410,8 @@ static int m88ds3103_probe(struct i2c_client *client, case M88DS3103_CHIP_ID: break; default: + ret = -ENODEV; + dev_err(&client->dev, "Unknown device. Chip_id=%02x\n", dev->chip_id); goto err_kfree; } diff --git a/drivers/media/dvb-frontends/m88ds3103.h b/drivers/media/dvb-frontends/m88ds3103.h index 04b355a005fb..1a8964a2265d 100644 --- a/drivers/media/dvb-frontends/m88ds3103.h +++ b/drivers/media/dvb-frontends/m88ds3103.h @@ -25,6 +25,34 @@ */ /** + * enum m88ds3103_ts_mode - TS connection mode + * @M88DS3103_TS_SERIAL: TS output pin D0, normal + * @M88DS3103_TS_SERIAL_D7: TS output pin D7 + * @M88DS3103_TS_PARALLEL: TS Parallel mode + * @M88DS3103_TS_CI: TS CI Mode + */ +enum m88ds3103_ts_mode { + M88DS3103_TS_SERIAL, + M88DS3103_TS_SERIAL_D7, + M88DS3103_TS_PARALLEL, + M88DS3103_TS_CI +}; + +/** + * enum m88ds3103_clock_out + * @M88DS3103_CLOCK_OUT_DISABLED: Clock output is disabled + * @M88DS3103_CLOCK_OUT_ENABLED: Clock output is enabled with crystal + * clock. + * @M88DS3103_CLOCK_OUT_ENABLED_DIV2: Clock output is enabled with half + * crystal clock. + */ +enum m88ds3103_clock_out { + M88DS3103_CLOCK_OUT_DISABLED, + M88DS3103_CLOCK_OUT_ENABLED, + M88DS3103_CLOCK_OUT_ENABLED_DIV2 +}; + +/** * struct m88ds3103_platform_data - Platform data for the m88ds3103 driver * @clk: Clock frequency. * @i2c_wr_max: Max bytes I2C adapter can write at once. @@ -44,24 +72,16 @@ * @get_dvb_frontend: Get DVB frontend. * @get_i2c_adapter: Get I2C adapter. */ - struct m88ds3103_platform_data { u32 clk; u16 i2c_wr_max; -#define M88DS3103_TS_SERIAL 0 /* TS output pin D0, normal */ -#define M88DS3103_TS_SERIAL_D7 1 /* TS output pin D7 */ -#define M88DS3103_TS_PARALLEL 2 /* TS Parallel mode */ -#define M88DS3103_TS_CI 3 /* TS CI Mode */ - u8 ts_mode:2; + enum m88ds3103_ts_mode ts_mode; u32 ts_clk; + enum m88ds3103_clock_out clk_out; u8 ts_clk_pol:1; u8 spec_inv:1; u8 agc; u8 agc_inv:1; -#define M88DS3103_CLOCK_OUT_DISABLED 0 -#define M88DS3103_CLOCK_OUT_ENABLED 1 -#define M88DS3103_CLOCK_OUT_ENABLED_DIV2 2 - u8 clk_out:2; u8 envelope_mode:1; u8 lnb_hv_pol:1; u8 lnb_en_pol:1; @@ -73,105 +93,60 @@ struct m88ds3103_platform_data { u8 attach_in_use:1; }; -/* - * Do not add new m88ds3103_attach() users! Use I2C bindings instead. +/** + * struct m88ds3103_config - m88ds3102 configuration + * + * @i2c_addr: I2C address. Default: none, must set. Example: 0x68, ... + * @clock: Device's clock. Default: none, must set. Example: 27000000 + * @i2c_wr_max: Max bytes I2C provider is asked to write at once. + * Default: none, must set. Example: 33, 65, ... + * @ts_mode: TS output mode, as defined by &enum m88ds3103_ts_mode. + * Default: M88DS3103_TS_SERIAL. + * @ts_clk: TS clk in KHz. Default: 0. + * @ts_clk_pol: TS clk polarity.Default: 0. + * 1-active at falling edge; 0-active at rising edge. + * @spec_inv: Spectrum inversion. Default: 0. + * @agc_inv: AGC polarity. Default: 0. + * @clock_out: Clock output, as defined by &enum m88ds3103_clock_out. + * Default: M88DS3103_CLOCK_OUT_DISABLED. + * @envelope_mode: DiSEqC envelope mode. Default: 0. + * @agc: AGC configuration. Default: none, must set. + * @lnb_hv_pol: LNB H/V pin polarity. Default: 0. Values: + * 1: pin high set to VOLTAGE_13, pin low to set VOLTAGE_18; + * 0: pin high set to VOLTAGE_18, pin low to set VOLTAGE_13. + * @lnb_en_pol: LNB enable pin polarity. Default: 0. Values: + * 1: pin high to enable, pin low to disable; + * 0: pin high to disable, pin low to enable. */ struct m88ds3103_config { - /* - * I2C address - * Default: none, must set - * 0x68, ... - */ u8 i2c_addr; - - /* - * clock - * Default: none, must set - * 27000000 - */ u32 clock; - - /* - * max bytes I2C provider is asked to write at once - * Default: none, must set - * 33, 65, ... - */ u16 i2c_wr_max; - - /* - * TS output mode - * Default: M88DS3103_TS_SERIAL - */ -#define M88DS3103_TS_SERIAL 0 /* TS output pin D0, normal */ -#define M88DS3103_TS_SERIAL_D7 1 /* TS output pin D7 */ -#define M88DS3103_TS_PARALLEL 2 /* TS Parallel mode */ -#define M88DS3103_TS_CI 3 /* TS CI Mode */ u8 ts_mode; - - /* - * TS clk in KHz - * Default: 0. - */ u32 ts_clk; - - /* - * TS clk polarity. - * Default: 0. 1-active at falling edge; 0-active at rising edge. - */ u8 ts_clk_pol:1; - - /* - * spectrum inversion - * Default: 0 - */ u8 spec_inv:1; - - /* - * AGC polarity - * Default: 0 - */ u8 agc_inv:1; - - /* - * clock output - * Default: M88DS3103_CLOCK_OUT_DISABLED - */ -#define M88DS3103_CLOCK_OUT_DISABLED 0 -#define M88DS3103_CLOCK_OUT_ENABLED 1 -#define M88DS3103_CLOCK_OUT_ENABLED_DIV2 2 u8 clock_out; - - /* - * DiSEqC envelope mode - * Default: 0 - */ u8 envelope_mode:1; - - /* - * AGC configuration - * Default: none, must set - */ u8 agc; - - /* - * LNB H/V pin polarity - * Default: 0. - * 1: pin high set to VOLTAGE_13, pin low to set VOLTAGE_18. - * 0: pin high set to VOLTAGE_18, pin low to set VOLTAGE_13. - */ u8 lnb_hv_pol:1; - - /* - * LNB enable pin polarity - * Default: 0. - * 1: pin high to enable, pin low to disable. - * 0: pin high to disable, pin low to enable. - */ u8 lnb_en_pol:1; }; #if defined(CONFIG_DVB_M88DS3103) || \ (defined(CONFIG_DVB_M88DS3103_MODULE) && defined(MODULE)) +/** + * Attach a m88ds3103 demod + * + * @config: pointer to &struct m88ds3103_config with demod configuration. + * @i2c: i2c adapter to use. + * @tuner_i2c: on success, returns the I2C adapter associated with + * m88ds3103 tuner. + * + * return: FE pointer on success, NULL on failure. + * Note: Do not add new m88ds3103_attach() users! Use I2C bindings instead. + */ extern struct dvb_frontend *m88ds3103_attach( const struct m88ds3103_config *config, struct i2c_adapter *i2c, diff --git a/drivers/media/dvb-frontends/m88ds3103_priv.h b/drivers/media/dvb-frontends/m88ds3103_priv.h index 07f20c269c67..1ba0b79df311 100644 --- a/drivers/media/dvb-frontends/m88ds3103_priv.h +++ b/drivers/media/dvb-frontends/m88ds3103_priv.h @@ -17,9 +17,9 @@ #ifndef M88DS3103_PRIV_H #define M88DS3103_PRIV_H -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "m88ds3103.h" -#include "dvb_math.h" +#include <media/dvb_math.h> #include <linux/firmware.h> #include <linux/i2c-mux.h> #include <linux/regmap.h> diff --git a/drivers/media/dvb-frontends/m88rs2000.c b/drivers/media/dvb-frontends/m88rs2000.c index ce6c21d405ee..496ce27fa63a 100644 --- a/drivers/media/dvb-frontends/m88rs2000.c +++ b/drivers/media/dvb-frontends/m88rs2000.c @@ -31,7 +31,7 @@ #include <linux/types.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "m88rs2000.h" struct m88rs2000_state { @@ -630,13 +630,16 @@ static int m88rs2000_set_frontend(struct dvb_frontend *fe) if (ret < 0) return -ENODEV; - if (fe->ops.tuner_ops.get_frequency) + if (fe->ops.tuner_ops.get_frequency) { ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_freq); - if (ret < 0) - return -ENODEV; + if (ret < 0) + return -ENODEV; - offset = (s16)((s32)tuner_freq - c->frequency); + offset = (s16)((s32)tuner_freq - c->frequency); + } else { + offset = 0; + } /* default mclk value 96.4285 * 2 * 1000 = 192857 */ if (((c->frequency % 192857) >= (192857 - 3000)) || diff --git a/drivers/media/dvb-frontends/m88rs2000.h b/drivers/media/dvb-frontends/m88rs2000.h index 1a313b0f5875..b015872c4ff4 100644 --- a/drivers/media/dvb-frontends/m88rs2000.h +++ b/drivers/media/dvb-frontends/m88rs2000.h @@ -21,7 +21,7 @@ #define M88RS2000_H #include <linux/dvb/frontend.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> struct m88rs2000_config { /* Demodulator i2c address */ diff --git a/drivers/media/dvb-frontends/mb86a16.c b/drivers/media/dvb-frontends/mb86a16.c index dfe322eccaa1..2969ba6ed9e1 100644 --- a/drivers/media/dvb-frontends/mb86a16.c +++ b/drivers/media/dvb-frontends/mb86a16.c @@ -24,7 +24,7 @@ #include <linux/moduleparam.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "mb86a16.h" #include "mb86a16_priv.h" @@ -635,6 +635,7 @@ static int sync_chk(struct mb86a16_state *state, return sync; err: dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + *VIRM = 0; return -EREMOTEIO; } @@ -1676,15 +1677,15 @@ static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber) * the deinterleaver output. * monitored BER is expressed as a 20 bit output in total */ - ber_rst = ber_mon >> 3; + ber_rst = (ber_mon >> 3) & 0x03; *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb; if (ber_rst == 0) timer = 12500000; - if (ber_rst == 1) + else if (ber_rst == 1) timer = 25000000; - if (ber_rst == 2) + else if (ber_rst == 2) timer = 50000000; - if (ber_rst == 3) + else /* ber_rst == 3 */ timer = 100000000; *ber /= timer; @@ -1696,11 +1697,11 @@ static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber) * QPSK demodulator output. * monitored BER is expressed as a 24 bit output in total */ - ber_tim = ber_mon >> 1; + ber_tim = (ber_mon >> 1) & 0x01; *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb; if (ber_tim == 0) timer = 16; - if (ber_tim == 1) + else /* ber_tim == 1 */ timer = 24; *ber /= 2 ^ timer; diff --git a/drivers/media/dvb-frontends/mb86a16.h b/drivers/media/dvb-frontends/mb86a16.h index dbd5f43fa128..f13820bc7a21 100644 --- a/drivers/media/dvb-frontends/mb86a16.h +++ b/drivers/media/dvb-frontends/mb86a16.h @@ -22,7 +22,7 @@ #define __MB86A16_H #include <linux/dvb/frontend.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> struct mb86a16_config { diff --git a/drivers/media/dvb-frontends/mb86a20s.c b/drivers/media/dvb-frontends/mb86a20s.c index bdaf9d235fed..36e95196dff4 100644 --- a/drivers/media/dvb-frontends/mb86a20s.c +++ b/drivers/media/dvb-frontends/mb86a20s.c @@ -17,7 +17,7 @@ #include <linux/kernel.h> #include <asm/div64.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "mb86a20s.h" #define NUM_LAYERS 3 @@ -2057,7 +2057,7 @@ static void mb86a20s_release(struct dvb_frontend *fe) static int mb86a20s_get_frontend_algo(struct dvb_frontend *fe) { - return DVBFE_ALGO_HW; + return DVBFE_ALGO_HW; } static const struct dvb_frontend_ops mb86a20s_ops; diff --git a/drivers/media/dvb-frontends/mb86a20s.h b/drivers/media/dvb-frontends/mb86a20s.h index dfb02db2126c..05c9725d1c5f 100644 --- a/drivers/media/dvb-frontends/mb86a20s.h +++ b/drivers/media/dvb-frontends/mb86a20s.h @@ -26,7 +26,6 @@ * @demod_address: the demodulator's i2c address * @is_serial: if true, TS is serial. Otherwise, TS is parallel */ - struct mb86a20s_config { u32 fclk; u8 demod_address; @@ -34,9 +33,17 @@ struct mb86a20s_config { }; #if IS_REACHABLE(CONFIG_DVB_MB86A20S) +/** + * Attach a mb86a20s demod + * + * @config: pointer to &struct mb86a20s_config with demod configuration. + * @i2c: i2c adapter to use. + * + * return: FE pointer on success, NULL on failure. + */ extern struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config, struct i2c_adapter *i2c); -extern struct i2c_adapter *mb86a20s_get_tuner_i2c_adapter(struct dvb_frontend *); + #else static inline struct dvb_frontend *mb86a20s_attach( const struct mb86a20s_config *config, struct i2c_adapter *i2c) @@ -44,12 +51,6 @@ static inline struct dvb_frontend *mb86a20s_attach( printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); return NULL; } -static inline struct i2c_adapter * - mb86a20s_get_tuner_i2c_adapter(struct dvb_frontend *fe) -{ - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); - return NULL; -} #endif #endif /* MB86A20S */ diff --git a/drivers/media/dvb-frontends/mn88472.h b/drivers/media/dvb-frontends/mn88472.h index 323632523876..8cd5ef61903b 100644 --- a/drivers/media/dvb-frontends/mn88472.h +++ b/drivers/media/dvb-frontends/mn88472.h @@ -19,21 +19,21 @@ #include <linux/dvb/frontend.h> +/* Define old names for backward compatibility */ +#define VARIABLE_TS_CLOCK MN88472_TS_CLK_VARIABLE +#define FIXED_TS_CLOCK MN88472_TS_CLK_FIXED +#define SERIAL_TS_MODE MN88472_TS_MODE_SERIAL +#define PARALLEL_TS_MODE MN88472_TS_MODE_PARALLEL + /** * struct mn88472_config - Platform data for the mn88472 driver * @xtal: Clock frequency. * @ts_mode: TS mode. * @ts_clock: TS clock config. * @i2c_wr_max: Max number of bytes driver writes to I2C at once. - * @get_dvb_frontend: Get DVB frontend. + * @fe: pointer to a frontend pointer + * @get_dvb_frontend: Get DVB frontend callback. */ - -/* Define old names for backward compatibility */ -#define VARIABLE_TS_CLOCK MN88472_TS_CLK_VARIABLE -#define FIXED_TS_CLOCK MN88472_TS_CLK_FIXED -#define SERIAL_TS_MODE MN88472_TS_MODE_SERIAL -#define PARALLEL_TS_MODE MN88472_TS_MODE_PARALLEL - struct mn88472_config { unsigned int xtal; diff --git a/drivers/media/dvb-frontends/mn88472_priv.h b/drivers/media/dvb-frontends/mn88472_priv.h index fb50f56ba30b..2ec126a42527 100644 --- a/drivers/media/dvb-frontends/mn88472_priv.h +++ b/drivers/media/dvb-frontends/mn88472_priv.h @@ -17,8 +17,8 @@ #ifndef MN88472_PRIV_H #define MN88472_PRIV_H -#include "dvb_frontend.h" -#include "dvb_math.h" +#include <media/dvb_frontend.h> +#include <media/dvb_math.h> #include "mn88472.h" #include <linux/firmware.h> #include <linux/regmap.h> diff --git a/drivers/media/dvb-frontends/mn88473.c b/drivers/media/dvb-frontends/mn88473.c index 58247432a628..ca722084e534 100644 --- a/drivers/media/dvb-frontends/mn88473.c +++ b/drivers/media/dvb-frontends/mn88473.c @@ -764,7 +764,7 @@ MODULE_DEVICE_TABLE(i2c, mn88473_id_table); static struct i2c_driver mn88473_driver = { .driver = { - .name = "mn88473", + .name = "mn88473", .suppress_bind_attrs = true, }, .probe = mn88473_probe, diff --git a/drivers/media/dvb-frontends/mn88473_priv.h b/drivers/media/dvb-frontends/mn88473_priv.h index 5fc463d147c8..d89a86320263 100644 --- a/drivers/media/dvb-frontends/mn88473_priv.h +++ b/drivers/media/dvb-frontends/mn88473_priv.h @@ -17,8 +17,8 @@ #ifndef MN88473_PRIV_H #define MN88473_PRIV_H -#include "dvb_frontend.h" -#include "dvb_math.h" +#include <media/dvb_frontend.h> +#include <media/dvb_math.h> #include "mn88473.h" #include <linux/math64.h> #include <linux/firmware.h> diff --git a/drivers/media/dvb-frontends/mt312.c b/drivers/media/dvb-frontends/mt312.c index 961b9a2508e0..e2a3fc521620 100644 --- a/drivers/media/dvb-frontends/mt312.c +++ b/drivers/media/dvb-frontends/mt312.c @@ -32,7 +32,7 @@ #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "mt312_priv.h" #include "mt312.h" @@ -142,7 +142,10 @@ static inline int mt312_readreg(struct mt312_state *state, static inline int mt312_writereg(struct mt312_state *state, const enum mt312_reg_addr reg, const u8 val) { - return mt312_write(state, reg, &val, 1); + u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ + + + return mt312_write(state, reg, &tmp, 1); } static inline u32 mt312_div(u32 a, u32 b) diff --git a/drivers/media/dvb-frontends/mt352.c b/drivers/media/dvb-frontends/mt352.c index d5fa96f0a6cd..a440b76444d3 100644 --- a/drivers/media/dvb-frontends/mt352.c +++ b/drivers/media/dvb-frontends/mt352.c @@ -33,7 +33,7 @@ #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "mt352_priv.h" #include "mt352.h" diff --git a/drivers/media/dvb-frontends/mxl5xx.c b/drivers/media/dvb-frontends/mxl5xx.c index 53064e11f5f1..e899821018a0 100644 --- a/drivers/media/dvb-frontends/mxl5xx.c +++ b/drivers/media/dvb-frontends/mxl5xx.c @@ -33,7 +33,7 @@ #include <asm/div64.h> #include <asm/unaligned.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "mxl5xx.h" #include "mxl5xx_regs.h" #include "mxl5xx_defs.h" @@ -636,16 +636,9 @@ static int tune(struct dvb_frontend *fe, bool re_tune, if (r) return r; state->tune_time = jiffies; - return 0; } - if (*status & FE_HAS_LOCK) - return 0; - r = read_status(fe, status); - if (r) - return r; - - return 0; + return read_status(fe, status); } static enum fe_code_rate conv_fec(enum MXL_HYDRA_FEC_E fec) diff --git a/drivers/media/dvb-frontends/mxl5xx.h b/drivers/media/dvb-frontends/mxl5xx.h index 532e08111537..ad4c21846800 100644 --- a/drivers/media/dvb-frontends/mxl5xx.h +++ b/drivers/media/dvb-frontends/mxl5xx.h @@ -4,7 +4,7 @@ #include <linux/types.h> #include <linux/i2c.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> struct mxl5xx_cfg { u8 adr; diff --git a/drivers/media/dvb-frontends/nxt200x.c b/drivers/media/dvb-frontends/nxt200x.c index bf6e5cd572c5..7aa74403648e 100644 --- a/drivers/media/dvb-frontends/nxt200x.c +++ b/drivers/media/dvb-frontends/nxt200x.c @@ -48,7 +48,7 @@ #include <linux/slab.h> #include <linux/string.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "nxt200x.h" struct nxt200x_state { diff --git a/drivers/media/dvb-frontends/nxt6000.c b/drivers/media/dvb-frontends/nxt6000.c index 1ce5ea28489b..109a635d166a 100644 --- a/drivers/media/dvb-frontends/nxt6000.c +++ b/drivers/media/dvb-frontends/nxt6000.c @@ -27,7 +27,7 @@ #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "nxt6000_priv.h" #include "nxt6000.h" diff --git a/drivers/media/dvb-frontends/or51132.c b/drivers/media/dvb-frontends/or51132.c index 5f2549c48eb0..b4c9aadcb552 100644 --- a/drivers/media/dvb-frontends/or51132.c +++ b/drivers/media/dvb-frontends/or51132.c @@ -38,8 +38,8 @@ #include <linux/slab.h> #include <asm/byteorder.h> -#include "dvb_math.h" -#include "dvb_frontend.h" +#include <media/dvb_math.h> +#include <media/dvb_frontend.h> #include "or51132.h" static int debug; diff --git a/drivers/media/dvb-frontends/or51211.c b/drivers/media/dvb-frontends/or51211.c index d14fa9736ae5..a1b7c301828f 100644 --- a/drivers/media/dvb-frontends/or51211.c +++ b/drivers/media/dvb-frontends/or51211.c @@ -36,8 +36,8 @@ #include <linux/slab.h> #include <asm/byteorder.h> -#include "dvb_math.h" -#include "dvb_frontend.h" +#include <media/dvb_math.h> +#include <media/dvb_frontend.h> #include "or51211.h" static int debug; diff --git a/drivers/media/dvb-frontends/rtl2830.h b/drivers/media/dvb-frontends/rtl2830.h index 0cde151e6608..458ac94e8a8b 100644 --- a/drivers/media/dvb-frontends/rtl2830.h +++ b/drivers/media/dvb-frontends/rtl2830.h @@ -32,7 +32,6 @@ * @pid_filter: Set PID to PID filter. * @pid_filter_ctrl: Control PID filter. */ - struct rtl2830_platform_data { u32 clk; bool spec_inv; diff --git a/drivers/media/dvb-frontends/rtl2830_priv.h b/drivers/media/dvb-frontends/rtl2830_priv.h index 8ec4721d79ac..72d3f3546ff2 100644 --- a/drivers/media/dvb-frontends/rtl2830_priv.h +++ b/drivers/media/dvb-frontends/rtl2830_priv.h @@ -18,8 +18,8 @@ #ifndef RTL2830_PRIV_H #define RTL2830_PRIV_H -#include "dvb_frontend.h" -#include "dvb_math.h" +#include <media/dvb_frontend.h> +#include <media/dvb_math.h> #include "rtl2830.h" #include <linux/i2c-mux.h> #include <linux/math64.h> diff --git a/drivers/media/dvb-frontends/rtl2832.h b/drivers/media/dvb-frontends/rtl2832.h index 03c0de039fa9..6a124ff71c2b 100644 --- a/drivers/media/dvb-frontends/rtl2832.h +++ b/drivers/media/dvb-frontends/rtl2832.h @@ -35,7 +35,6 @@ * @pid_filter: Set PID to PID filter. * @pid_filter_ctrl: Control PID filter. */ - struct rtl2832_platform_data { u32 clk; /* diff --git a/drivers/media/dvb-frontends/rtl2832_priv.h b/drivers/media/dvb-frontends/rtl2832_priv.h index 9a6d01a9c690..bd13d9ad9ab7 100644 --- a/drivers/media/dvb-frontends/rtl2832_priv.h +++ b/drivers/media/dvb-frontends/rtl2832_priv.h @@ -26,8 +26,8 @@ #include <linux/math64.h> #include <linux/bitops.h> -#include "dvb_frontend.h" -#include "dvb_math.h" +#include <media/dvb_frontend.h> +#include <media/dvb_math.h> #include "rtl2832.h" struct rtl2832_dev { diff --git a/drivers/media/dvb-frontends/rtl2832_sdr.h b/drivers/media/dvb-frontends/rtl2832_sdr.h index d8fc7e7212e3..d28735c1cb0c 100644 --- a/drivers/media/dvb-frontends/rtl2832_sdr.h +++ b/drivers/media/dvb-frontends/rtl2832_sdr.h @@ -27,21 +27,17 @@ #include <linux/i2c.h> #include <media/v4l2-subdev.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> /** * struct rtl2832_sdr_platform_data - Platform data for the rtl2832_sdr driver * @clk: Clock frequency (4000000, 16000000, 25000000, 28800000). * @tuner: Used tuner model. - * @i2c_client: rtl2832 demod driver I2C client. - * @bulk_read: rtl2832 driver private I/O interface. - * @bulk_write: rtl2832 driver private I/O interface. - * @update_bits: rtl2832 driver private I/O interface. + * @regmap: pointer to &struct regmap. * @dvb_frontend: rtl2832 DVB frontend. * @v4l2_subdev: Tuner v4l2 controls. * @dvb_usb_device: DVB USB interface for USB streaming. */ - struct rtl2832_sdr_platform_data { u32 clk; /* diff --git a/drivers/media/dvb-frontends/s5h1409.c b/drivers/media/dvb-frontends/s5h1409.c index f370c6df0a8b..aced6a956ec5 100644 --- a/drivers/media/dvb-frontends/s5h1409.c +++ b/drivers/media/dvb-frontends/s5h1409.c @@ -25,7 +25,7 @@ #include <linux/string.h> #include <linux/slab.h> #include <linux/delay.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "s5h1409.h" struct s5h1409_state { diff --git a/drivers/media/dvb-frontends/s5h1411.c b/drivers/media/dvb-frontends/s5h1411.c index dd09336a135b..c4b1e9725f3e 100644 --- a/drivers/media/dvb-frontends/s5h1411.c +++ b/drivers/media/dvb-frontends/s5h1411.c @@ -25,7 +25,7 @@ #include <linux/string.h> #include <linux/slab.h> #include <linux/delay.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "s5h1411.h" struct s5h1411_state { diff --git a/drivers/media/dvb-frontends/s5h1420.c b/drivers/media/dvb-frontends/s5h1420.c index fd427a29c001..8b2222530227 100644 --- a/drivers/media/dvb-frontends/s5h1420.c +++ b/drivers/media/dvb-frontends/s5h1420.c @@ -30,7 +30,7 @@ #include <linux/i2c.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "s5h1420.h" #include "s5h1420_priv.h" diff --git a/drivers/media/dvb-frontends/s5h1432.c b/drivers/media/dvb-frontends/s5h1432.c index 4de50fe0c638..740a60df0455 100644 --- a/drivers/media/dvb-frontends/s5h1432.c +++ b/drivers/media/dvb-frontends/s5h1432.c @@ -20,7 +20,7 @@ #include <linux/string.h> #include <linux/slab.h> #include <linux/delay.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "s5h1432.h" struct s5h1432_state { diff --git a/drivers/media/dvb-frontends/s921.c b/drivers/media/dvb-frontends/s921.c index 274544a3ae0e..2d75ede77aca 100644 --- a/drivers/media/dvb-frontends/s921.c +++ b/drivers/media/dvb-frontends/s921.c @@ -25,7 +25,7 @@ #include <linux/kernel.h> #include <asm/div64.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "s921.h" static int debug = 1; diff --git a/drivers/media/dvb-frontends/si2165.c b/drivers/media/dvb-frontends/si2165.c index 528b82a5dd46..2dd336f95cbf 100644 --- a/drivers/media/dvb-frontends/si2165.c +++ b/drivers/media/dvb-frontends/si2165.c @@ -1,7 +1,7 @@ /* * Driver for Silicon Labs Si2161 DVB-T and Si2165 DVB-C/-T Demodulator * - * Copyright (C) 2013-2014 Matthias Schwarzott <zzam@gentoo.org> + * Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,8 +27,8 @@ #include <linux/firmware.h> #include <linux/regmap.h> -#include "dvb_frontend.h" -#include "dvb_math.h" +#include <media/dvb_frontend.h> +#include <media/dvb_math.h> #include "si2165_priv.h" #include "si2165.h" @@ -57,63 +57,21 @@ struct si2165_state { u32 sys_clk; u32 adc_clk; + /* DVBv3 stats */ + u64 ber_prev; + bool has_dvbc; bool has_dvbt; bool firmware_loaded; }; -#define DEBUG_OTHER 0x01 -#define DEBUG_I2C_WRITE 0x02 -#define DEBUG_I2C_READ 0x04 -#define DEBUG_REG_READ 0x08 -#define DEBUG_REG_WRITE 0x10 -#define DEBUG_FW_LOAD 0x20 - -static int debug = 0x00; - -#define dprintk(args...) \ - do { \ - if (debug & DEBUG_OTHER) \ - printk(KERN_DEBUG "si2165: " args); \ - } while (0) - -#define deb_i2c_write(args...) \ - do { \ - if (debug & DEBUG_I2C_WRITE) \ - printk(KERN_DEBUG "si2165: i2c write: " args); \ - } while (0) - -#define deb_i2c_read(args...) \ - do { \ - if (debug & DEBUG_I2C_READ) \ - printk(KERN_DEBUG "si2165: i2c read: " args); \ - } while (0) - -#define deb_readreg(args...) \ - do { \ - if (debug & DEBUG_REG_READ) \ - printk(KERN_DEBUG "si2165: reg read: " args); \ - } while (0) - -#define deb_writereg(args...) \ - do { \ - if (debug & DEBUG_REG_WRITE) \ - printk(KERN_DEBUG "si2165: reg write: " args); \ - } while (0) - -#define deb_fw_load(args...) \ - do { \ - if (debug & DEBUG_FW_LOAD) \ - printk(KERN_DEBUG "si2165: fw load: " args); \ - } while (0) - static int si2165_write(struct si2165_state *state, const u16 reg, - const u8 *src, const int count) + const u8 *src, const int count) { int ret; - if (debug & DEBUG_I2C_WRITE) - deb_i2c_write("reg: 0x%04x, data: %*ph\n", reg, count, src); + dev_dbg(&state->client->dev, "i2c write: reg: 0x%04x, data: %*ph\n", + reg, count, src); ret = regmap_bulk_write(state->regmap, reg, src, count); @@ -134,30 +92,41 @@ static int si2165_read(struct si2165_state *state, return ret; } - if (debug & DEBUG_I2C_READ) - deb_i2c_read("reg: 0x%04x, data: %*ph\n", reg, count, val); + dev_dbg(&state->client->dev, "i2c read: reg: 0x%04x, data: %*ph\n", + reg, count, val); return 0; } static int si2165_readreg8(struct si2165_state *state, - const u16 reg, u8 *val) + const u16 reg, u8 *val) { unsigned int val_tmp; int ret = regmap_read(state->regmap, reg, &val_tmp); *val = (u8)val_tmp; - deb_readreg("R(0x%04x)=0x%02x\n", reg, *val); + dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%02x\n", reg, *val); return ret; } static int si2165_readreg16(struct si2165_state *state, - const u16 reg, u16 *val) + const u16 reg, u16 *val) { u8 buf[2]; int ret = si2165_read(state, reg, buf, 2); *val = buf[0] | buf[1] << 8; - deb_readreg("R(0x%04x)=0x%04x\n", reg, *val); + dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%04x\n", reg, *val); + return ret; +} + +static int si2165_readreg24(struct si2165_state *state, + const u16 reg, u32 *val) +{ + u8 buf[3]; + + int ret = si2165_read(state, reg, buf, 3); + *val = buf[0] | buf[1] << 8 | buf[2] << 16; + dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%06x\n", reg, *val); return ret; } @@ -208,7 +177,9 @@ static int si2165_writereg_mask8(struct si2165_state *state, const u16 reg, return si2165_writereg8(state, reg, val); } -#define REG16(reg, val) { (reg), (val) & 0xff }, { (reg)+1, (val)>>8 & 0xff } +#define REG16(reg, val) \ + { (reg), (val) & 0xff }, \ + { (reg) + 1, (val) >> 8 & 0xff } struct si2165_reg_value_pair { u16 reg; u8 val; @@ -238,7 +209,7 @@ static int si2165_get_tune_settings(struct dvb_frontend *fe, static int si2165_init_pll(struct si2165_state *state) { - u32 ref_freq_Hz = state->config.ref_freq_Hz; + u32 ref_freq_hz = state->config.ref_freq_hz; u8 divr = 1; /* 1..7 */ u8 divp = 1; /* only 1 or 4 */ u8 divn = 56; /* 1..63 */ @@ -250,7 +221,7 @@ static int si2165_init_pll(struct si2165_state *state) * hardcoded values can be deleted if calculation is verified * or it yields the same values as the windows driver */ - switch (ref_freq_Hz) { + switch (ref_freq_hz) { case 16000000u: divn = 56; break; @@ -261,39 +232,39 @@ static int si2165_init_pll(struct si2165_state *state) break; default: /* ref_freq / divr must be between 4 and 16 MHz */ - if (ref_freq_Hz > 16000000u) + if (ref_freq_hz > 16000000u) divr = 2; /* * now select divn and divp such that * fvco is in 1624..1824 MHz */ - if (1624000000u * divr > ref_freq_Hz * 2u * 63u) + if (1624000000u * divr > ref_freq_hz * 2u * 63u) divp = 4; /* is this already correct regarding rounding? */ - divn = 1624000000u * divr / (ref_freq_Hz * 2u * divp); + divn = 1624000000u * divr / (ref_freq_hz * 2u * divp); break; } /* adc_clk and sys_clk depend on xtal and pll settings */ - state->fvco_hz = ref_freq_Hz / divr + state->fvco_hz = ref_freq_hz / divr * 2u * divn * divp; state->adc_clk = state->fvco_hz / (divm * 4u); state->sys_clk = state->fvco_hz / (divl * 2u); - /* write pll registers 0x00a0..0x00a3 at once */ + /* write all 4 pll registers 0x00a0..0x00a3 at once */ buf[0] = divl; buf[1] = divm; buf[2] = (divn & 0x3f) | ((divp == 1) ? 0x40 : 0x00) | 0x80; buf[3] = divr; - return si2165_write(state, 0x00a0, buf, 4); + return si2165_write(state, REG_PLL_DIVL, buf, 4); } static int si2165_adjust_pll_divl(struct si2165_state *state, u8 divl) { state->sys_clk = state->fvco_hz / (divl * 2u); - return si2165_writereg8(state, 0x00a0, divl); /* pll_divl */ + return si2165_writereg8(state, REG_PLL_DIVL, divl); } static u32 si2165_get_fe_clk(struct si2165_state *state) @@ -309,18 +280,18 @@ static int si2165_wait_init_done(struct si2165_state *state) int i; for (i = 0; i < 3; ++i) { - si2165_readreg8(state, 0x0054, &val); + si2165_readreg8(state, REG_INIT_DONE, &val); if (val == 0x01) return 0; usleep_range(1000, 50000); } - dev_err(&state->client->dev, "%s: init_done was not set\n", - KBUILD_MODNAME); + dev_err(&state->client->dev, "init_done was not set\n"); return ret; } static int si2165_upload_firmware_block(struct si2165_state *state, - const u8 *data, u32 len, u32 *poffset, u32 block_count) + const u8 *data, u32 len, u32 *poffset, + u32 block_count) { int ret; u8 buf_ctrl[4] = { 0x00, 0x00, 0x00, 0xc0 }; @@ -333,42 +304,43 @@ static int si2165_upload_firmware_block(struct si2165_state *state, if (len % 4 != 0) return -EINVAL; - deb_fw_load( - "si2165_upload_firmware_block called with len=0x%x offset=0x%x blockcount=0x%x\n", - len, offset, block_count); - while (offset+12 <= len && cur_block < block_count) { - deb_fw_load( - "si2165_upload_firmware_block in while len=0x%x offset=0x%x cur_block=0x%x blockcount=0x%x\n", - len, offset, cur_block, block_count); + dev_dbg(&state->client->dev, + "fw load: %s: called with len=0x%x offset=0x%x blockcount=0x%x\n", + __func__, len, offset, block_count); + while (offset + 12 <= len && cur_block < block_count) { + dev_dbg(&state->client->dev, + "fw load: %s: in while len=0x%x offset=0x%x cur_block=0x%x blockcount=0x%x\n", + __func__, len, offset, cur_block, block_count); wordcount = data[offset]; - if (wordcount < 1 || data[offset+1] || - data[offset+2] || data[offset+3]) { + if (wordcount < 1 || data[offset + 1] || + data[offset + 2] || data[offset + 3]) { dev_warn(&state->client->dev, - "%s: bad fw data[0..3] = %*ph\n", - KBUILD_MODNAME, 4, data); + "bad fw data[0..3] = %*ph\n", + 4, data); return -EINVAL; } if (offset + 8 + wordcount * 4 > len) { dev_warn(&state->client->dev, - "%s: len is too small for block len=%d, wordcount=%d\n", - KBUILD_MODNAME, len, wordcount); + "len is too small for block len=%d, wordcount=%d\n", + len, wordcount); return -EINVAL; } buf_ctrl[0] = wordcount - 1; - ret = si2165_write(state, 0x0364, buf_ctrl, 4); + ret = si2165_write(state, REG_DCOM_CONTROL_BYTE, buf_ctrl, 4); if (ret < 0) goto error; - ret = si2165_write(state, 0x0368, data+offset+4, 4); + ret = si2165_write(state, REG_DCOM_ADDR, data + offset + 4, 4); if (ret < 0) goto error; offset += 8; while (wordcount > 0) { - ret = si2165_write(state, 0x36c, data+offset, 4); + ret = si2165_write(state, REG_DCOM_DATA, + data + offset, 4); if (ret < 0) goto error; wordcount--; @@ -377,15 +349,16 @@ static int si2165_upload_firmware_block(struct si2165_state *state, cur_block++; } - deb_fw_load( - "si2165_upload_firmware_block after while len=0x%x offset=0x%x cur_block=0x%x blockcount=0x%x\n", - len, offset, cur_block, block_count); + dev_dbg(&state->client->dev, + "fw load: %s: after while len=0x%x offset=0x%x cur_block=0x%x blockcount=0x%x\n", + __func__, len, offset, cur_block, block_count); if (poffset) *poffset = offset; - deb_fw_load("si2165_upload_firmware_block returned offset=0x%x\n", - offset); + dev_dbg(&state->client->dev, + "fw load: %s: returned offset=0x%x\n", + __func__, offset); return 0; error: @@ -413,43 +386,40 @@ static int si2165_upload_firmware(struct si2165_state *state) fw_file = SI2165_FIRMWARE_REV_D; break; default: - dev_info(&state->client->dev, "%s: no firmware file for revision=%d\n", - KBUILD_MODNAME, state->chip_revcode); + dev_info(&state->client->dev, "no firmware file for revision=%d\n", + state->chip_revcode); return 0; } /* request the firmware, this will block and timeout */ ret = request_firmware(&fw, fw_file, &state->client->dev); if (ret) { - dev_warn(&state->client->dev, "%s: firmware file '%s' not found\n", - KBUILD_MODNAME, fw_file); + dev_warn(&state->client->dev, "firmware file '%s' not found\n", + fw_file); goto error; } data = fw->data; len = fw->size; - dev_info(&state->client->dev, "%s: downloading firmware from file '%s' size=%d\n", - KBUILD_MODNAME, fw_file, len); + dev_info(&state->client->dev, "downloading firmware from file '%s' size=%d\n", + fw_file, len); if (len % 4 != 0) { - dev_warn(&state->client->dev, "%s: firmware size is not multiple of 4\n", - KBUILD_MODNAME); + dev_warn(&state->client->dev, "firmware size is not multiple of 4\n"); ret = -EINVAL; goto error; } /* check header (8 bytes) */ if (len < 8) { - dev_warn(&state->client->dev, "%s: firmware header is missing\n", - KBUILD_MODNAME); + dev_warn(&state->client->dev, "firmware header is missing\n"); ret = -EINVAL; goto error; } if (data[0] != 1 || data[1] != 0) { - dev_warn(&state->client->dev, "%s: firmware file version is wrong\n", - KBUILD_MODNAME); + dev_warn(&state->client->dev, "firmware file version is wrong\n"); ret = -EINVAL; goto error; } @@ -460,45 +430,45 @@ static int si2165_upload_firmware(struct si2165_state *state) /* start uploading fw */ /* boot/wdog status */ - ret = si2165_writereg8(state, 0x0341, 0x00); + ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00); if (ret < 0) goto error; /* reset */ - ret = si2165_writereg8(state, 0x00c0, 0x00); + ret = si2165_writereg8(state, REG_RST_ALL, 0x00); if (ret < 0) goto error; /* boot/wdog status */ - ret = si2165_readreg8(state, 0x0341, val); + ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val); if (ret < 0) goto error; /* enable reset on error */ - ret = si2165_readreg8(state, 0x035c, val); + ret = si2165_readreg8(state, REG_EN_RST_ERROR, val); if (ret < 0) goto error; - ret = si2165_readreg8(state, 0x035c, val); + ret = si2165_readreg8(state, REG_EN_RST_ERROR, val); if (ret < 0) goto error; - ret = si2165_writereg8(state, 0x035c, 0x02); + ret = si2165_writereg8(state, REG_EN_RST_ERROR, 0x02); if (ret < 0) goto error; /* start right after the header */ offset = 8; - dev_info(&state->client->dev, "%s: si2165_upload_firmware extracted patch_version=0x%02x, block_count=0x%02x, crc_expected=0x%04x\n", - KBUILD_MODNAME, patch_version, block_count, crc_expected); + dev_info(&state->client->dev, "%s: extracted patch_version=0x%02x, block_count=0x%02x, crc_expected=0x%04x\n", + __func__, patch_version, block_count, crc_expected); ret = si2165_upload_firmware_block(state, data, len, &offset, 1); if (ret < 0) goto error; - ret = si2165_writereg8(state, 0x0344, patch_version); + ret = si2165_writereg8(state, REG_PATCH_VERSION, patch_version); if (ret < 0) goto error; /* reset crc */ - ret = si2165_writereg8(state, 0x0379, 0x01); + ret = si2165_writereg8(state, REG_RST_CRC, 0x01); if (ret) goto error; @@ -506,20 +476,19 @@ static int si2165_upload_firmware(struct si2165_state *state) &offset, block_count); if (ret < 0) { dev_err(&state->client->dev, - "%s: firmware could not be uploaded\n", - KBUILD_MODNAME); + "firmware could not be uploaded\n"); goto error; } /* read crc */ - ret = si2165_readreg16(state, 0x037a, &val16); + ret = si2165_readreg16(state, REG_CRC, &val16); if (ret) goto error; if (val16 != crc_expected) { dev_err(&state->client->dev, - "%s: firmware crc mismatch %04x != %04x\n", - KBUILD_MODNAME, val16, crc_expected); + "firmware crc mismatch %04x != %04x\n", + val16, crc_expected); ret = -EINVAL; goto error; } @@ -530,23 +499,23 @@ static int si2165_upload_firmware(struct si2165_state *state) if (len != offset) { dev_err(&state->client->dev, - "%s: firmware len mismatch %04x != %04x\n", - KBUILD_MODNAME, len, offset); + "firmware len mismatch %04x != %04x\n", + len, offset); ret = -EINVAL; goto error; } /* reset watchdog error register */ - ret = si2165_writereg_mask8(state, 0x0341, 0x02, 0x02); + ret = si2165_writereg_mask8(state, REG_WDOG_AND_BOOT, 0x02, 0x02); if (ret < 0) goto error; /* enable reset on error */ - ret = si2165_writereg_mask8(state, 0x035c, 0x01, 0x01); + ret = si2165_writereg_mask8(state, REG_EN_RST_ERROR, 0x01, 0x01); if (ret < 0) goto error; - dev_info(&state->client->dev, "%s: fw load finished\n", KBUILD_MODNAME); + dev_info(&state->client->dev, "fw load finished\n"); ret = 0; state->firmware_loaded = true; @@ -563,46 +532,47 @@ static int si2165_init(struct dvb_frontend *fe) { int ret = 0; struct si2165_state *state = fe->demodulator_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; u8 val; u8 patch_version = 0x00; - dprintk("%s: called\n", __func__); + dev_dbg(&state->client->dev, "%s: called\n", __func__); /* powerup */ - ret = si2165_writereg8(state, 0x0000, state->config.chip_mode); + ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode); if (ret < 0) goto error; /* dsp_clock_enable */ - ret = si2165_writereg8(state, 0x0104, 0x01); + ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x01); if (ret < 0) goto error; - ret = si2165_readreg8(state, 0x0000, &val); /* verify chip_mode */ + /* verify chip_mode */ + ret = si2165_readreg8(state, REG_CHIP_MODE, &val); if (ret < 0) goto error; if (val != state->config.chip_mode) { - dev_err(&state->client->dev, "%s: could not set chip_mode\n", - KBUILD_MODNAME); + dev_err(&state->client->dev, "could not set chip_mode\n"); return -EINVAL; } /* agc */ - ret = si2165_writereg8(state, 0x018b, 0x00); + ret = si2165_writereg8(state, REG_AGC_IF_TRI, 0x00); if (ret < 0) goto error; - ret = si2165_writereg8(state, 0x0190, 0x01); + ret = si2165_writereg8(state, REG_AGC_IF_SLR, 0x01); if (ret < 0) goto error; - ret = si2165_writereg8(state, 0x0170, 0x00); + ret = si2165_writereg8(state, REG_AGC2_OUTPUT, 0x00); if (ret < 0) goto error; - ret = si2165_writereg8(state, 0x0171, 0x07); + ret = si2165_writereg8(state, REG_AGC2_CLKDIV, 0x07); if (ret < 0) goto error; /* rssi pad */ - ret = si2165_writereg8(state, 0x0646, 0x00); + ret = si2165_writereg8(state, REG_RSSI_PAD_CTRL, 0x00); if (ret < 0) goto error; - ret = si2165_writereg8(state, 0x0641, 0x00); + ret = si2165_writereg8(state, REG_RSSI_ENABLE, 0x00); if (ret < 0) goto error; @@ -611,11 +581,11 @@ static int si2165_init(struct dvb_frontend *fe) goto error; /* enable chip_init */ - ret = si2165_writereg8(state, 0x0050, 0x01); + ret = si2165_writereg8(state, REG_CHIP_INIT, 0x01); if (ret < 0) goto error; /* set start_init */ - ret = si2165_writereg8(state, 0x0096, 0x01); + ret = si2165_writereg8(state, REG_START_INIT, 0x01); if (ret < 0) goto error; ret = si2165_wait_init_done(state); @@ -623,29 +593,30 @@ static int si2165_init(struct dvb_frontend *fe) goto error; /* disable chip_init */ - ret = si2165_writereg8(state, 0x0050, 0x00); + ret = si2165_writereg8(state, REG_CHIP_INIT, 0x00); if (ret < 0) goto error; - /* ber_pkt */ - ret = si2165_writereg16(state, 0x0470, 0x7530); + /* ber_pkt - default 65535 */ + ret = si2165_writereg16(state, REG_BER_PKT, + STATISTICS_PERIOD_PKT_COUNT); if (ret < 0) goto error; - ret = si2165_readreg8(state, 0x0344, &patch_version); + ret = si2165_readreg8(state, REG_PATCH_VERSION, &patch_version); if (ret < 0) goto error; - ret = si2165_writereg8(state, 0x00cb, 0x00); + ret = si2165_writereg8(state, REG_AUTO_RESET, 0x00); if (ret < 0) goto error; /* dsp_addr_jump */ - ret = si2165_writereg32(state, 0x0348, 0xf4000000); + ret = si2165_writereg32(state, REG_ADDR_JUMP, 0xf4000000); if (ret < 0) goto error; /* boot/wdog status */ - ret = si2165_readreg8(state, 0x0341, &val); + ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, &val); if (ret < 0) goto error; @@ -656,19 +627,30 @@ static int si2165_init(struct dvb_frontend *fe) } /* ts output config */ - ret = si2165_writereg8(state, 0x04e4, 0x20); + ret = si2165_writereg8(state, REG_TS_DATA_MODE, 0x20); + if (ret < 0) + return ret; + ret = si2165_writereg16(state, REG_TS_TRI, 0x00fe); if (ret < 0) return ret; - ret = si2165_writereg16(state, 0x04ef, 0x00fe); + ret = si2165_writereg24(state, REG_TS_SLR, 0x555555); if (ret < 0) return ret; - ret = si2165_writereg24(state, 0x04f4, 0x555555); + ret = si2165_writereg8(state, REG_TS_CLK_MODE, 0x01); if (ret < 0) return ret; - ret = si2165_writereg8(state, 0x04e5, 0x01); + ret = si2165_writereg8(state, REG_TS_PARALLEL_MODE, 0x00); if (ret < 0) return ret; + c = &state->fe.dtv_property_cache; + c->cnr.len = 1; + c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + c->post_bit_error.len = 1; + c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + c->post_bit_count.len = 1; + c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + return 0; error: return ret; @@ -680,11 +662,11 @@ static int si2165_sleep(struct dvb_frontend *fe) struct si2165_state *state = fe->demodulator_priv; /* dsp clock disable */ - ret = si2165_writereg8(state, 0x0104, 0x00); + ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x00); if (ret < 0) return ret; /* chip mode */ - ret = si2165_writereg8(state, 0x0000, SI2165_MODE_OFF); + ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF); if (ret < 0) return ret; return 0; @@ -693,18 +675,48 @@ static int si2165_sleep(struct dvb_frontend *fe) static int si2165_read_status(struct dvb_frontend *fe, enum fe_status *status) { int ret; - u8 fec_lock = 0; + u8 u8tmp; + u32 u32tmp; struct si2165_state *state = fe->demodulator_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + u32 delsys = c->delivery_system; - if (!state->has_dvbt) - return -EINVAL; + *status = 0; + + switch (delsys) { + case SYS_DVBT: + /* check fast signal type */ + ret = si2165_readreg8(state, REG_CHECK_SIGNAL, &u8tmp); + if (ret < 0) + return ret; + switch (u8tmp & 0x3) { + case 0: /* searching */ + case 1: /* nothing */ + break; + case 2: /* digital signal */ + *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER; + break; + } + break; + case SYS_DVBC_ANNEX_A: + /* check packet sync lock */ + ret = si2165_readreg8(state, REG_PS_LOCK, &u8tmp); + if (ret < 0) + return ret; + if (u8tmp & 0x01) { + *status |= FE_HAS_SIGNAL; + *status |= FE_HAS_CARRIER; + *status |= FE_HAS_VITERBI; + *status |= FE_HAS_SYNC; + } + break; + } /* check fec_lock */ - ret = si2165_readreg8(state, 0x4e0, &fec_lock); + ret = si2165_readreg8(state, REG_FEC_LOCK, &u8tmp); if (ret < 0) return ret; - *status = 0; - if (fec_lock & 0x01) { + if (u8tmp & 0x01) { *status |= FE_HAS_SIGNAL; *status |= FE_HAS_CARRIER; *status |= FE_HAS_VITERBI; @@ -712,6 +724,109 @@ static int si2165_read_status(struct dvb_frontend *fe, enum fe_status *status) *status |= FE_HAS_LOCK; } + /* CNR */ + if (delsys == SYS_DVBC_ANNEX_A && *status & FE_HAS_VITERBI) { + ret = si2165_readreg24(state, REG_C_N, &u32tmp); + if (ret < 0) + return ret; + /* + * svalue = + * 1000 * c_n/dB = + * 1000 * 10 * log10(2^24 / regval) = + * 1000 * 10 * (log10(2^24) - log10(regval)) = + * 1000 * 10 * (intlog10(2^24) - intlog10(regval)) / 2^24 + * + * intlog10(x) = log10(x) * 2^24 + * intlog10(2^24) = log10(2^24) * 2^24 = 121210686 + */ + u32tmp = (1000 * 10 * (121210686 - (u64)intlog10(u32tmp))) + >> 24; + c->cnr.stat[0].scale = FE_SCALE_DECIBEL; + c->cnr.stat[0].svalue = u32tmp; + } else + c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + + /* BER */ + if (*status & FE_HAS_VITERBI) { + if (c->post_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { + /* start new sampling period to get rid of old data*/ + ret = si2165_writereg8(state, REG_BER_RST, 0x01); + if (ret < 0) + return ret; + + /* set scale to enter read code on next call */ + c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; + c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; + c->post_bit_error.stat[0].uvalue = 0; + c->post_bit_count.stat[0].uvalue = 0; + + /* + * reset DVBv3 value to deliver a good result + * for the first call + */ + state->ber_prev = 0; + + } else { + ret = si2165_readreg8(state, REG_BER_AVAIL, &u8tmp); + if (ret < 0) + return ret; + + if (u8tmp & 1) { + u32 biterrcnt; + + ret = si2165_readreg24(state, REG_BER_BIT, + &biterrcnt); + if (ret < 0) + return ret; + + c->post_bit_error.stat[0].uvalue += + biterrcnt; + c->post_bit_count.stat[0].uvalue += + STATISTICS_PERIOD_BIT_COUNT; + + /* start new sampling period */ + ret = si2165_writereg8(state, + REG_BER_RST, 0x01); + if (ret < 0) + return ret; + + dev_dbg(&state->client->dev, + "post_bit_error=%u post_bit_count=%u\n", + biterrcnt, STATISTICS_PERIOD_BIT_COUNT); + } + } + } else { + c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } + + return 0; +} + +static int si2165_read_snr(struct dvb_frontend *fe, u16 *snr) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + + if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL) + *snr = div_s64(c->cnr.stat[0].svalue, 100); + else + *snr = 0; + return 0; +} + +static int si2165_read_ber(struct dvb_frontend *fe, u32 *ber) +{ + struct si2165_state *state = fe->demodulator_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + + if (c->post_bit_error.stat[0].scale != FE_SCALE_COUNTER) { + *ber = 0; + return 0; + } + + *ber = c->post_bit_error.stat[0].uvalue - state->ber_prev; + state->ber_prev = c->post_bit_error.stat[0].uvalue; + return 0; } @@ -728,8 +843,8 @@ static int si2165_set_oversamp(struct si2165_state *state, u32 dvb_rate) do_div(oversamp, dvb_rate); reg_value = oversamp & 0x3fffffff; - dprintk("%s: Write oversamp=%#x\n", __func__, reg_value); - return si2165_writereg32(state, 0x00e4, reg_value); + dev_dbg(&state->client->dev, "Write oversamp=%#x\n", reg_value); + return si2165_writereg32(state, REG_OVERSAMP, reg_value); } static int si2165_set_if_freq_shift(struct si2165_state *state) @@ -742,8 +857,7 @@ static int si2165_set_if_freq_shift(struct si2165_state *state) if (!fe->ops.tuner_ops.get_if_frequency) { dev_err(&state->client->dev, - "%s: Error: get_if_frequency() not defined at tuner. Can't work without it!\n", - KBUILD_MODNAME); + "Error: get_if_frequency() not defined at tuner. Can't work without it!\n"); return -EINVAL; } @@ -763,30 +877,29 @@ static int si2165_set_if_freq_shift(struct si2165_state *state) reg_value = reg_value & 0x1fffffff; /* if_freq_shift, usbdump contained 0x023ee08f; */ - return si2165_writereg32(state, 0x00e8, reg_value); + return si2165_writereg32(state, REG_IF_FREQ_SHIFT, reg_value); } static const struct si2165_reg_value_pair dvbt_regs[] = { /* standard = DVB-T */ - { 0x00ec, 0x01 }, - { 0x08f8, 0x00 }, + { REG_DVB_STANDARD, 0x01 }, /* impulsive_noise_remover */ - { 0x031c, 0x01 }, - { 0x00cb, 0x00 }, + { REG_IMPULSIVE_NOISE_REM, 0x01 }, + { REG_AUTO_RESET, 0x00 }, /* agc2 */ - { 0x016e, 0x41 }, - { 0x016c, 0x0e }, - { 0x016d, 0x10 }, + { REG_AGC2_MIN, 0x41 }, + { REG_AGC2_KACQ, 0x0e }, + { REG_AGC2_KLOC, 0x10 }, /* agc */ - { 0x015b, 0x03 }, - { 0x0150, 0x78 }, + { REG_AGC_UNFREEZE_THR, 0x03 }, + { REG_AGC_CRESTF_DBX8, 0x78 }, /* agc */ - { 0x01a0, 0x78 }, - { 0x01c8, 0x68 }, + { REG_AAF_CRESTF_DBX8, 0x78 }, + { REG_ACI_CRESTF_DBX8, 0x68 }, /* freq_sync_range */ - REG16(0x030c, 0x0064), + REG16(REG_FREQ_SYNC_RANGE, 0x0064), /* gp_reg0 */ - { 0x0387, 0x00 } + { REG_GP_REG0_MSB, 0x00 } }; static int si2165_set_frontend_dvbt(struct dvb_frontend *fe) @@ -798,7 +911,7 @@ static int si2165_set_frontend_dvbt(struct dvb_frontend *fe) u16 bw10k; u32 bw_hz = p->bandwidth_hz; - dprintk("%s: called\n", __func__); + dev_dbg(&state->client->dev, "%s: called\n", __func__); if (!state->has_dvbt) return -EINVAL; @@ -815,7 +928,7 @@ static int si2165_set_frontend_dvbt(struct dvb_frontend *fe) return ret; /* bandwidth in 10KHz steps */ - ret = si2165_writereg16(state, 0x0308, bw10k); + ret = si2165_writereg16(state, REG_T_BANDWIDTH, bw10k); if (ret < 0) return ret; ret = si2165_set_oversamp(state, dvb_rate); @@ -831,33 +944,30 @@ static int si2165_set_frontend_dvbt(struct dvb_frontend *fe) static const struct si2165_reg_value_pair dvbc_regs[] = { /* standard = DVB-C */ - { 0x00ec, 0x05 }, - { 0x08f8, 0x00 }, + { REG_DVB_STANDARD, 0x05 }, /* agc2 */ - { 0x016e, 0x50 }, - { 0x016c, 0x0e }, - { 0x016d, 0x10 }, + { REG_AGC2_MIN, 0x50 }, + { REG_AGC2_KACQ, 0x0e }, + { REG_AGC2_KLOC, 0x10 }, /* agc */ - { 0x015b, 0x03 }, - { 0x0150, 0x68 }, + { REG_AGC_UNFREEZE_THR, 0x03 }, + { REG_AGC_CRESTF_DBX8, 0x68 }, /* agc */ - { 0x01a0, 0x68 }, - { 0x01c8, 0x50 }, - - { 0x0278, 0x0d }, - - { 0x023a, 0x05 }, - { 0x0261, 0x09 }, - REG16(0x0350, 0x3e80), - { 0x02f4, 0x00 }, - - { 0x00cb, 0x01 }, - REG16(0x024c, 0x0000), - REG16(0x027c, 0x0000), - { 0x0232, 0x03 }, - { 0x02f4, 0x0b }, - { 0x018b, 0x00 }, + { REG_AAF_CRESTF_DBX8, 0x68 }, + { REG_ACI_CRESTF_DBX8, 0x50 }, + + { REG_EQ_AUTO_CONTROL, 0x0d }, + + { REG_KP_LOCK, 0x05 }, + { REG_CENTRAL_TAP, 0x09 }, + REG16(REG_UNKNOWN_350, 0x3e80), + + { REG_AUTO_RESET, 0x01 }, + REG16(REG_UNKNOWN_24C, 0x0000), + REG16(REG_UNKNOWN_27C, 0x0000), + { REG_SWEEP_STEP, 0x03 }, + { REG_AGC_IF_TRI, 0x00 }, }; static int si2165_set_frontend_dvbc(struct dvb_frontend *fe) @@ -866,7 +976,7 @@ static int si2165_set_frontend_dvbc(struct dvb_frontend *fe) int ret; struct dtv_frontend_properties *p = &fe->dtv_property_cache; const u32 dvb_rate = p->symbol_rate; - const u32 bw_hz = p->bandwidth_hz; + u8 u8tmp; if (!state->has_dvbc) return -EINVAL; @@ -883,7 +993,32 @@ static int si2165_set_frontend_dvbc(struct dvb_frontend *fe) if (ret < 0) return ret; - ret = si2165_writereg32(state, 0x00c4, bw_hz); + switch (p->modulation) { + case QPSK: + u8tmp = 0x3; + break; + case QAM_16: + u8tmp = 0x7; + break; + case QAM_32: + u8tmp = 0x8; + break; + case QAM_64: + u8tmp = 0x9; + break; + case QAM_128: + u8tmp = 0xa; + break; + case QAM_256: + default: + u8tmp = 0xb; + break; + } + ret = si2165_writereg8(state, REG_REQ_CONSTELLATION, u8tmp); + if (ret < 0) + return ret; + + ret = si2165_writereg32(state, REG_LOCK_TIMEOUT, 0x007a1200); if (ret < 0) return ret; @@ -894,12 +1029,12 @@ static int si2165_set_frontend_dvbc(struct dvb_frontend *fe) return 0; } -static const struct si2165_reg_value_pair agc_rewrite[] = { - { 0x012a, 0x46 }, - { 0x012c, 0x00 }, - { 0x012e, 0x0a }, - { 0x012f, 0xff }, - { 0x0123, 0x70 } +static const struct si2165_reg_value_pair adc_rewrite[] = { + { REG_ADC_RI1, 0x46 }, + { REG_ADC_RI3, 0x00 }, + { REG_ADC_RI5, 0x0a }, + { REG_ADC_RI6, 0xff }, + { REG_ADC_RI8, 0x70 } }; static int si2165_set_frontend(struct dvb_frontend *fe) @@ -931,7 +1066,7 @@ static int si2165_set_frontend(struct dvb_frontend *fe) } /* dsp_addr_jump */ - ret = si2165_writereg32(state, 0x0348, 0xf4000000); + ret = si2165_writereg32(state, REG_ADDR_JUMP, 0xf4000000); if (ret < 0) return ret; @@ -944,34 +1079,34 @@ static int si2165_set_frontend(struct dvb_frontend *fe) return ret; /* boot/wdog status */ - ret = si2165_readreg8(state, 0x0341, val); + ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val); if (ret < 0) return ret; - ret = si2165_writereg8(state, 0x0341, 0x00); + ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00); if (ret < 0) return ret; /* reset all */ - ret = si2165_writereg8(state, 0x00c0, 0x00); + ret = si2165_writereg8(state, REG_RST_ALL, 0x00); if (ret < 0) return ret; /* gp_reg0 */ - ret = si2165_writereg32(state, 0x0384, 0x00000000); + ret = si2165_writereg32(state, REG_GP_REG0_LSB, 0x00000000); if (ret < 0) return ret; /* write adc values after each reset*/ - ret = si2165_write_reg_list(state, agc_rewrite, - ARRAY_SIZE(agc_rewrite)); + ret = si2165_write_reg_list(state, adc_rewrite, + ARRAY_SIZE(adc_rewrite)); if (ret < 0) return ret; /* start_synchro */ - ret = si2165_writereg8(state, 0x02e0, 0x01); + ret = si2165_writereg8(state, REG_START_SYNCHRO, 0x01); if (ret < 0) return ret; /* boot/wdog status */ - ret = si2165_readreg8(state, 0x0341, val); + ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val); if (ret < 0) return ret; @@ -998,7 +1133,6 @@ static const struct dvb_frontend_ops si2165_ops = { FE_CAN_QAM_64 | FE_CAN_QAM_128 | FE_CAN_QAM_256 | - FE_CAN_QAM_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | FE_CAN_MUTE_TS | @@ -1013,10 +1147,12 @@ static const struct dvb_frontend_ops si2165_ops = { .set_frontend = si2165_set_frontend, .read_status = si2165_read_status, + .read_snr = si2165_read_snr, + .read_ber = si2165_read_ber, }; static int si2165_probe(struct i2c_client *client, - const struct i2c_device_id *id) + const struct i2c_device_id *id) { struct si2165_state *state = NULL; struct si2165_platform_data *pdata = client->dev.platform_data; @@ -1032,8 +1168,8 @@ static int si2165_probe(struct i2c_client *client, }; /* allocate memory for the internal state */ - state = kzalloc(sizeof(struct si2165_state), GFP_KERNEL); - if (state == NULL) { + state = kzalloc(sizeof(*state), GFP_KERNEL); + if (!state) { ret = -ENOMEM; goto error; } @@ -1049,45 +1185,45 @@ static int si2165_probe(struct i2c_client *client, state->client = client; state->config.i2c_addr = client->addr; state->config.chip_mode = pdata->chip_mode; - state->config.ref_freq_Hz = pdata->ref_freq_Hz; + state->config.ref_freq_hz = pdata->ref_freq_hz; state->config.inversion = pdata->inversion; - if (state->config.ref_freq_Hz < 4000000 - || state->config.ref_freq_Hz > 27000000) { - dev_err(&state->client->dev, "%s: ref_freq of %d Hz not supported by this driver\n", - KBUILD_MODNAME, state->config.ref_freq_Hz); + if (state->config.ref_freq_hz < 4000000 || + state->config.ref_freq_hz > 27000000) { + dev_err(&state->client->dev, "ref_freq of %d Hz not supported by this driver\n", + state->config.ref_freq_hz); ret = -EINVAL; goto error; } /* create dvb_frontend */ memcpy(&state->fe.ops, &si2165_ops, - sizeof(struct dvb_frontend_ops)); + sizeof(struct dvb_frontend_ops)); state->fe.ops.release = NULL; state->fe.demodulator_priv = state; i2c_set_clientdata(client, state); /* powerup */ - ret = si2165_writereg8(state, 0x0000, state->config.chip_mode); + ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode); if (ret < 0) goto nodev_error; - ret = si2165_readreg8(state, 0x0000, &val); + ret = si2165_readreg8(state, REG_CHIP_MODE, &val); if (ret < 0) goto nodev_error; if (val != state->config.chip_mode) goto nodev_error; - ret = si2165_readreg8(state, 0x0023, &state->chip_revcode); + ret = si2165_readreg8(state, REG_CHIP_REVCODE, &state->chip_revcode); if (ret < 0) goto nodev_error; - ret = si2165_readreg8(state, 0x0118, &state->chip_type); + ret = si2165_readreg8(state, REV_CHIP_TYPE, &state->chip_type); if (ret < 0) goto nodev_error; /* powerdown */ - ret = si2165_writereg8(state, 0x0000, SI2165_MODE_OFF); + ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF); if (ret < 0) goto nodev_error; @@ -1107,18 +1243,18 @@ static int si2165_probe(struct i2c_client *client, state->has_dvbc = true; break; default: - dev_err(&state->client->dev, "%s: Unsupported Silicon Labs chip (type %d, rev %d)\n", - KBUILD_MODNAME, state->chip_type, state->chip_revcode); + dev_err(&state->client->dev, "Unsupported Silicon Labs chip (type %d, rev %d)\n", + state->chip_type, state->chip_revcode); goto nodev_error; } dev_info(&state->client->dev, - "%s: Detected Silicon Labs %s-%c (type %d, rev %d)\n", - KBUILD_MODNAME, chip_name, rev_char, state->chip_type, + "Detected Silicon Labs %s-%c (type %d, rev %d)\n", + chip_name, rev_char, state->chip_type, state->chip_revcode); strlcat(state->fe.ops.info.name, chip_name, - sizeof(state->fe.ops.info.name)); + sizeof(state->fe.ops.info.name)); n = 0; if (state->has_dvbt) { @@ -1173,9 +1309,6 @@ static struct i2c_driver si2165_driver = { module_i2c_driver(si2165_driver); -module_param(debug, int, 0644); -MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); - MODULE_DESCRIPTION("Silicon Labs Si2165 DVB-C/-T Demodulator driver"); MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>"); MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb-frontends/si2165.h b/drivers/media/dvb-frontends/si2165.h index 76c2ca7d7edb..74a57b7ecd26 100644 --- a/drivers/media/dvb-frontends/si2165.h +++ b/drivers/media/dvb-frontends/si2165.h @@ -1,21 +1,22 @@ /* - Driver for Silicon Labs SI2165 DVB-C/-T Demodulator - - Copyright (C) 2013-2014 Matthias Schwarzott <zzam@gentoo.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - References: - http://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf -*/ + * Driver for Silicon Labs SI2165 DVB-C/-T Demodulator + * + * Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * References: + * http://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf + * + */ #ifndef _DVB_SI2165_H #define _DVB_SI2165_H @@ -44,7 +45,7 @@ struct si2165_platform_data { /* frequency of external clock or xtal in Hz * possible values: 4000000, 16000000, 20000000, 240000000, 27000000 */ - u32 ref_freq_Hz; + u32 ref_freq_hz; /* invert the spectrum */ bool inversion; diff --git a/drivers/media/dvb-frontends/si2165_priv.h b/drivers/media/dvb-frontends/si2165_priv.h index e5932118834b..8c6fbfe441ff 100644 --- a/drivers/media/dvb-frontends/si2165_priv.h +++ b/drivers/media/dvb-frontends/si2165_priv.h @@ -1,19 +1,19 @@ /* - Driver for Silicon Labs SI2165 DVB-C/-T Demodulator - - Copyright (C) 2013-2014 Matthias Schwarzott <zzam@gentoo.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - -*/ + * Driver for Silicon Labs SI2165 DVB-C/-T Demodulator + * + * Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ #ifndef _DVB_SI2165_PRIV #define _DVB_SI2165_PRIV @@ -22,7 +22,8 @@ struct si2165_config { /* i2c addr - * possible values: 0x64,0x65,0x66,0x67 */ + * possible values: 0x64,0x65,0x66,0x67 + */ u8 i2c_addr; /* external clock or XTAL */ @@ -31,10 +32,89 @@ struct si2165_config { /* frequency of external clock or xtal in Hz * possible values: 4000000, 16000000, 20000000, 240000000, 27000000 */ - u32 ref_freq_Hz; + u32 ref_freq_hz; /* invert the spectrum */ bool inversion; }; +#define STATISTICS_PERIOD_PKT_COUNT 30000u +#define STATISTICS_PERIOD_BIT_COUNT (STATISTICS_PERIOD_PKT_COUNT * 204 * 8) + +#define REG_CHIP_MODE 0x0000 +#define REG_CHIP_REVCODE 0x0023 +#define REV_CHIP_TYPE 0x0118 +#define REG_CHIP_INIT 0x0050 +#define REG_INIT_DONE 0x0054 +#define REG_START_INIT 0x0096 +#define REG_PLL_DIVL 0x00a0 +#define REG_RST_ALL 0x00c0 +#define REG_LOCK_TIMEOUT 0x00c4 +#define REG_AUTO_RESET 0x00cb +#define REG_OVERSAMP 0x00e4 +#define REG_IF_FREQ_SHIFT 0x00e8 +#define REG_DVB_STANDARD 0x00ec +#define REG_DSP_CLOCK 0x0104 +#define REG_ADC_RI8 0x0123 +#define REG_ADC_RI1 0x012a +#define REG_ADC_RI2 0x012b +#define REG_ADC_RI3 0x012c +#define REG_ADC_RI4 0x012d +#define REG_ADC_RI5 0x012e +#define REG_ADC_RI6 0x012f +#define REG_AGC_CRESTF_DBX8 0x0150 +#define REG_AGC_UNFREEZE_THR 0x015b +#define REG_AGC2_MIN 0x016e +#define REG_AGC2_KACQ 0x016c +#define REG_AGC2_KLOC 0x016d +#define REG_AGC2_OUTPUT 0x0170 +#define REG_AGC2_CLKDIV 0x0171 +#define REG_AGC_IF_TRI 0x018b +#define REG_AGC_IF_SLR 0x0190 +#define REG_AAF_CRESTF_DBX8 0x01a0 +#define REG_ACI_CRESTF_DBX8 0x01c8 +#define REG_SWEEP_STEP 0x0232 +#define REG_KP_LOCK 0x023a +#define REG_UNKNOWN_24C 0x024c +#define REG_CENTRAL_TAP 0x0261 +#define REG_C_N 0x026c +#define REG_EQ_AUTO_CONTROL 0x0278 +#define REG_UNKNOWN_27C 0x027c +#define REG_START_SYNCHRO 0x02e0 +#define REG_REQ_CONSTELLATION 0x02f4 +#define REG_T_BANDWIDTH 0x0308 +#define REG_FREQ_SYNC_RANGE 0x030c +#define REG_IMPULSIVE_NOISE_REM 0x031c +#define REG_WDOG_AND_BOOT 0x0341 +#define REG_PATCH_VERSION 0x0344 +#define REG_ADDR_JUMP 0x0348 +#define REG_UNKNOWN_350 0x0350 +#define REG_EN_RST_ERROR 0x035c +#define REG_DCOM_CONTROL_BYTE 0x0364 +#define REG_DCOM_ADDR 0x0368 +#define REG_DCOM_DATA 0x036c +#define REG_RST_CRC 0x0379 +#define REG_GP_REG0_LSB 0x0384 +#define REG_GP_REG0_MSB 0x0387 +#define REG_CRC 0x037a +#define REG_CHECK_SIGNAL 0x03a8 +#define REG_CBER_RST 0x0424 +#define REG_CBER_BIT 0x0428 +#define REG_CBER_ERR 0x0430 +#define REG_CBER_AVAIL 0x0434 +#define REG_PS_LOCK 0x0440 +#define REG_UNCOR_CNT 0x0468 +#define REG_BER_RST 0x046c +#define REG_BER_PKT 0x0470 +#define REG_BER_BIT 0x0478 +#define REG_BER_AVAIL 0x047c +#define REG_FEC_LOCK 0x04e0 +#define REG_TS_DATA_MODE 0x04e4 +#define REG_TS_CLK_MODE 0x04e5 +#define REG_TS_TRI 0x04ef +#define REG_TS_SLR 0x04f4 +#define REG_RSSI_ENABLE 0x0641 +#define REG_RSSI_PAD_CTRL 0x0646 +#define REG_TS_PARALLEL_MODE 0x08f8 + #endif /* _DVB_SI2165_PRIV */ diff --git a/drivers/media/dvb-frontends/si2168.c b/drivers/media/dvb-frontends/si2168.c index 41d9c513b7e8..539399dac551 100644 --- a/drivers/media/dvb-frontends/si2168.c +++ b/drivers/media/dvb-frontends/si2168.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <linux/delay.h> + #include "si2168_priv.h" static const struct dvb_frontend_ops si2168_ops; @@ -435,6 +437,7 @@ static int si2168_init(struct dvb_frontend *fe) if (ret) goto err; + udelay(100); memcpy(cmd.args, "\x85", 1); cmd.wlen = 1; cmd.rlen = 1; diff --git a/drivers/media/dvb-frontends/si2168_priv.h b/drivers/media/dvb-frontends/si2168_priv.h index 737cf416fbb2..3c8746a20038 100644 --- a/drivers/media/dvb-frontends/si2168_priv.h +++ b/drivers/media/dvb-frontends/si2168_priv.h @@ -18,7 +18,7 @@ #define SI2168_PRIV_H #include "si2168.h" -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include <linux/firmware.h> #include <linux/i2c-mux.h> #include <linux/kernel.h> diff --git a/drivers/media/dvb-frontends/si21xx.c b/drivers/media/dvb-frontends/si21xx.c index 4e8c3ac4303f..9b32a1b3205e 100644 --- a/drivers/media/dvb-frontends/si21xx.c +++ b/drivers/media/dvb-frontends/si21xx.c @@ -16,7 +16,7 @@ #include <linux/jiffies.h> #include <asm/div64.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "si21xx.h" #define REVISION_REG 0x00 diff --git a/drivers/media/dvb-frontends/si21xx.h b/drivers/media/dvb-frontends/si21xx.h index 43d480bb6ea2..12fa1d579820 100644 --- a/drivers/media/dvb-frontends/si21xx.h +++ b/drivers/media/dvb-frontends/si21xx.h @@ -3,7 +3,7 @@ #define SI21XX_H #include <linux/dvb/frontend.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> struct si21xx_config { /* the demodulator's i2c address */ diff --git a/drivers/media/dvb-frontends/sp2.h b/drivers/media/dvb-frontends/sp2.h index 3901cd74b3f7..1bf60b80566f 100644 --- a/drivers/media/dvb-frontends/sp2.h +++ b/drivers/media/dvb-frontends/sp2.h @@ -17,7 +17,7 @@ #ifndef SP2_H #define SP2_H -#include "dvb_ca_en50221.h" +#include <media/dvb_ca_en50221.h> /* * I2C address diff --git a/drivers/media/dvb-frontends/sp2_priv.h b/drivers/media/dvb-frontends/sp2_priv.h index 37fef7bcd63f..c9ee53073ec0 100644 --- a/drivers/media/dvb-frontends/sp2_priv.h +++ b/drivers/media/dvb-frontends/sp2_priv.h @@ -18,7 +18,7 @@ #define SP2_PRIV_H #include "sp2.h" -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> /* state struct */ struct sp2 { diff --git a/drivers/media/dvb-frontends/sp8870.c b/drivers/media/dvb-frontends/sp8870.c index 04454cb78467..9a726f3a4896 100644 --- a/drivers/media/dvb-frontends/sp8870.c +++ b/drivers/media/dvb-frontends/sp8870.c @@ -35,7 +35,7 @@ #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "sp8870.h" diff --git a/drivers/media/dvb-frontends/sp887x.c b/drivers/media/dvb-frontends/sp887x.c index 7c511c3cd4ca..572a297811fe 100644 --- a/drivers/media/dvb-frontends/sp887x.c +++ b/drivers/media/dvb-frontends/sp887x.c @@ -17,7 +17,7 @@ #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "sp887x.h" @@ -57,7 +57,7 @@ static int sp887x_writereg (struct sp887x_state* state, u16 reg, u16 data) int ret; if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1) { - /** + /* * in case of soft reset we ignore ACK errors... */ if (!(reg == 0xf1a && data == 0x000 && @@ -130,7 +130,7 @@ static void sp887x_setup_agc (struct sp887x_state* state) #define BLOCKSIZE 30 #define FW_SIZE 0x4000 -/** +/* * load firmware and setup MPEG interface... */ static int sp887x_initial_setup (struct dvb_frontend* fe, const struct firmware *fw) @@ -279,7 +279,7 @@ static int configure_reg0xc05(struct dtv_frontend_properties *p, u16 *reg0xc05) return 0; } -/** +/* * estimates division of two 24bit numbers, * derived from the ves1820/stv0299 driver code */ diff --git a/drivers/media/dvb-frontends/stb0899_algo.c b/drivers/media/dvb-frontends/stb0899_algo.c index 3012f196e9bd..bd2defde7a77 100644 --- a/drivers/media/dvb-frontends/stb0899_algo.c +++ b/drivers/media/dvb-frontends/stb0899_algo.c @@ -925,8 +925,7 @@ static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state) wn = (4 * zeta * zeta) + 1000000; wn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn; /*wn =wn 10^-8*/ - k_indirect = (wn * wn) / K; - k_indirect = k_indirect; /*kindirect = kindirect 10^-6*/ + k_indirect = (wn * wn) / K; /*kindirect = kindirect 10^-6*/ k_direct = (2 * wn * zeta) / K; /*kDirect = kDirect 10^-2*/ k_direct *= 100; diff --git a/drivers/media/dvb-frontends/stb0899_drv.c b/drivers/media/dvb-frontends/stb0899_drv.c index 02347598277a..3c654ae16e78 100644 --- a/drivers/media/dvb-frontends/stb0899_drv.c +++ b/drivers/media/dvb-frontends/stb0899_drv.c @@ -27,7 +27,7 @@ #include <linux/string.h> #include <linux/dvb/frontend.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "stb0899_drv.h" #include "stb0899_priv.h" @@ -539,7 +539,8 @@ int stb0899_write_regs(struct stb0899_state *state, unsigned int reg, u8 *data, int stb0899_write_reg(struct stb0899_state *state, unsigned int reg, u8 data) { - return stb0899_write_regs(state, reg, &data, 1); + u8 tmp = data; + return stb0899_write_regs(state, reg, &tmp, 1); } /* @@ -1582,15 +1583,15 @@ static enum dvbfe_algo stb0899_frontend_algo(struct dvb_frontend *fe) static const struct dvb_frontend_ops stb0899_ops = { .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS }, .info = { - .name = "STB0899 Multistandard", + .name = "STB0899 Multistandard", .frequency_min = 950000, - .frequency_max = 2150000, + .frequency_max = 2150000, .frequency_stepsize = 0, .frequency_tolerance = 0, - .symbol_rate_min = 5000000, - .symbol_rate_max = 45000000, + .symbol_rate_min = 5000000, + .symbol_rate_max = 45000000, - .caps = FE_CAN_INVERSION_AUTO | + .caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO | FE_CAN_2G_MODULATION | FE_CAN_QPSK diff --git a/drivers/media/dvb-frontends/stb0899_drv.h b/drivers/media/dvb-frontends/stb0899_drv.h index 0a72131a57db..f65f9a8266f8 100644 --- a/drivers/media/dvb-frontends/stb0899_drv.h +++ b/drivers/media/dvb-frontends/stb0899_drv.h @@ -25,7 +25,7 @@ #include <linux/kernel.h> #include <linux/module.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #define STB0899_TSMODE_SERIAL 1 #define STB0899_CLKPOL_FALLING 2 @@ -82,7 +82,7 @@ enum stb0899_inversion { * 1. POWER ON/OFF (index 0) * 2. FE_HAS_LOCK/LOCK_LOSS (index 1) * - * @gpio = one of the above listed GPIO's + * @gpio = one of the above listed GPIO's * @level = output state: pulled up or low */ struct stb0899_postproc { diff --git a/drivers/media/dvb-frontends/stb0899_priv.h b/drivers/media/dvb-frontends/stb0899_priv.h index 82395b912815..3285cd1ba60a 100644 --- a/drivers/media/dvb-frontends/stb0899_priv.h +++ b/drivers/media/dvb-frontends/stb0899_priv.h @@ -22,7 +22,7 @@ #ifndef __STB0899_PRIV_H #define __STB0899_PRIV_H -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "stb0899_drv.h" #define FE_ERROR 0 @@ -252,7 +252,7 @@ extern int stb0899_write_s2reg(struct stb0899_state *state, extern int stb0899_i2c_gate_ctrl(struct dvb_frontend *fe, int enable); -#define STB0899_READ_S2REG(DEVICE, REG) (_stb0899_read_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG)) +#define STB0899_READ_S2REG(DEVICE, REG) (_stb0899_read_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG)) //#define STB0899_WRITE_S2REG(DEVICE, REG, DATA) (_stb0899_write_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG, DATA)) /* stb0899_algo.c */ diff --git a/drivers/media/dvb-frontends/stb6000.h b/drivers/media/dvb-frontends/stb6000.h index 78e75dfc317f..1adda72379ff 100644 --- a/drivers/media/dvb-frontends/stb6000.h +++ b/drivers/media/dvb-frontends/stb6000.h @@ -24,17 +24,18 @@ #define __DVB_STB6000_H__ #include <linux/i2c.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> +#if IS_REACHABLE(CONFIG_DVB_STB6000) /** * Attach a stb6000 tuner to the supplied frontend structure. * - * @param fe Frontend to attach to. - * @param addr i2c address of the tuner. - * @param i2c i2c adapter to use. - * @return FE pointer on success, NULL on failure. + * @fe: Frontend to attach to. + * @addr: i2c address of the tuner. + * @i2c: i2c adapter to use. + * + * return: FE pointer on success, NULL on failure. */ -#if IS_REACHABLE(CONFIG_DVB_STB6000) extern struct dvb_frontend *stb6000_attach(struct dvb_frontend *fe, int addr, struct i2c_adapter *i2c); #else diff --git a/drivers/media/dvb-frontends/stb6100.c b/drivers/media/dvb-frontends/stb6100.c index 17a955d0031b..3a851f524b16 100644 --- a/drivers/media/dvb-frontends/stb6100.c +++ b/drivers/media/dvb-frontends/stb6100.c @@ -25,7 +25,7 @@ #include <linux/slab.h> #include <linux/string.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "stb6100.h" static unsigned int verbose; @@ -226,12 +226,14 @@ static int stb6100_write_reg_range(struct stb6100_state *state, u8 buf[], int st static int stb6100_write_reg(struct stb6100_state *state, u8 reg, u8 data) { + u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ + if (unlikely(reg >= STB6100_NUMREGS)) { dprintk(verbose, FE_ERROR, 1, "Invalid register offset 0x%x", reg); return -EREMOTEIO; } - data = (data & stb6100_template[reg].mask) | stb6100_template[reg].set; - return stb6100_write_reg_range(state, &data, reg, 1); + tmp = (tmp & stb6100_template[reg].mask) | stb6100_template[reg].set; + return stb6100_write_reg_range(state, &tmp, reg, 1); } diff --git a/drivers/media/dvb-frontends/stb6100.h b/drivers/media/dvb-frontends/stb6100.h index f7b468b6dc26..6cdae688a23e 100644 --- a/drivers/media/dvb-frontends/stb6100.h +++ b/drivers/media/dvb-frontends/stb6100.h @@ -23,7 +23,7 @@ #define __STB_6100_REG_H #include <linux/dvb/frontend.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #define STB6100_LD 0x00 #define STB6100_LD_LOCK (1 << 0) diff --git a/drivers/media/dvb-frontends/stb6100_cfg.h b/drivers/media/dvb-frontends/stb6100_cfg.h index 2ef67aa768b9..203f9b36c0eb 100644 --- a/drivers/media/dvb-frontends/stb6100_cfg.h +++ b/drivers/media/dvb-frontends/stb6100_cfg.h @@ -20,7 +20,7 @@ */ #include <linux/dvb/frontend.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> static int stb6100_get_frequency(struct dvb_frontend *fe, u32 *frequency) { diff --git a/drivers/media/dvb-frontends/stb6100_proc.h b/drivers/media/dvb-frontends/stb6100_proc.h index 50ffa21e3871..fad877b2fc7d 100644 --- a/drivers/media/dvb-frontends/stb6100_proc.h +++ b/drivers/media/dvb-frontends/stb6100_proc.h @@ -18,7 +18,7 @@ */ #include <linux/dvb/frontend.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> static int stb6100_get_freq(struct dvb_frontend *fe, u32 *frequency) { diff --git a/drivers/media/dvb-frontends/stv0288.c b/drivers/media/dvb-frontends/stv0288.c index 67f91814b9f7..f947ed947aae 100644 --- a/drivers/media/dvb-frontends/stv0288.c +++ b/drivers/media/dvb-frontends/stv0288.c @@ -33,7 +33,7 @@ #include <linux/jiffies.h> #include <asm/div64.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "stv0288.h" struct stv0288_state { diff --git a/drivers/media/dvb-frontends/stv0288.h b/drivers/media/dvb-frontends/stv0288.h index 803acb917282..c10227aaa62c 100644 --- a/drivers/media/dvb-frontends/stv0288.h +++ b/drivers/media/dvb-frontends/stv0288.h @@ -28,7 +28,7 @@ #define STV0288_H #include <linux/dvb/frontend.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> struct stv0288_config { /* the demodulator's i2c address */ diff --git a/drivers/media/dvb-frontends/stv0297.c b/drivers/media/dvb-frontends/stv0297.c index db94d4d109f9..b823c04e24d3 100644 --- a/drivers/media/dvb-frontends/stv0297.c +++ b/drivers/media/dvb-frontends/stv0297.c @@ -27,7 +27,7 @@ #include <linux/jiffies.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "stv0297.h" struct stv0297_state { diff --git a/drivers/media/dvb-frontends/stv0297.h b/drivers/media/dvb-frontends/stv0297.h index b30632a67333..8fa5ac700fc3 100644 --- a/drivers/media/dvb-frontends/stv0297.h +++ b/drivers/media/dvb-frontends/stv0297.h @@ -22,7 +22,7 @@ #define STV0297_H #include <linux/dvb/frontend.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> struct stv0297_config { diff --git a/drivers/media/dvb-frontends/stv0299.c b/drivers/media/dvb-frontends/stv0299.c index b36b21a13201..633b90e6fe86 100644 --- a/drivers/media/dvb-frontends/stv0299.c +++ b/drivers/media/dvb-frontends/stv0299.c @@ -51,7 +51,7 @@ #include <linux/jiffies.h> #include <asm/div64.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "stv0299.h" struct stv0299_state { @@ -368,7 +368,7 @@ static int stv0299_set_voltage(struct dvb_frontend *fe, reg0x08 = stv0299_readreg (state, 0x08); reg0x0c = stv0299_readreg (state, 0x0c); - /** + /* * H/V switching over OP0, OP1 and OP2 are LNB power enable bits */ reg0x0c &= 0x0f; diff --git a/drivers/media/dvb-frontends/stv0299.h b/drivers/media/dvb-frontends/stv0299.h index 0aca30a8ec25..700c124a1699 100644 --- a/drivers/media/dvb-frontends/stv0299.h +++ b/drivers/media/dvb-frontends/stv0299.h @@ -46,7 +46,7 @@ #define STV0299_H #include <linux/dvb/frontend.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #define STV0299_LOCKOUTPUT_0 0 #define STV0299_LOCKOUTPUT_1 1 diff --git a/drivers/media/dvb-frontends/stv0367.c b/drivers/media/dvb-frontends/stv0367.c index f3529df8211d..5435c908e298 100644 --- a/drivers/media/dvb-frontends/stv0367.c +++ b/drivers/media/dvb-frontends/stv0367.c @@ -25,7 +25,7 @@ #include <linux/slab.h> #include <linux/i2c.h> -#include "dvb_math.h" +#include <media/dvb_math.h> #include "stv0367.h" #include "stv0367_defs.h" @@ -166,7 +166,9 @@ int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len) static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data) { - return stv0367_writeregs(state, reg, &data, 1); + u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ + + return stv0367_writeregs(state, reg, &tmp, 1); } static u8 stv0367_readreg(struct stv0367_state *state, u16 reg) @@ -1547,7 +1549,6 @@ static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber) } else if (abc == 0x7) { if (Errors <= 4) { temporary = (Errors * 1000000000) / (8 * (1 << 14)); - temporary = temporary; } else if (Errors <= 42) { temporary = (Errors * 100000000) / (8 * (1 << 14)); temporary = temporary * 10; @@ -1625,7 +1626,6 @@ static u32 stv0367ter_get_per(struct stv0367_state *state) else if (abc == 0x9) { if (Errors <= 4) { temporary = (Errors * 1000000000) / (8 * (1 << 8)); - temporary = temporary; } else if (Errors <= 42) { temporary = (Errors * 100000000) / (8 * (1 << 8)); temporary = temporary * 10; diff --git a/drivers/media/dvb-frontends/stv0367.h b/drivers/media/dvb-frontends/stv0367.h index 8f7a31481744..14a50ecef6dd 100644 --- a/drivers/media/dvb-frontends/stv0367.h +++ b/drivers/media/dvb-frontends/stv0367.h @@ -23,7 +23,7 @@ #define STV0367_H #include <linux/dvb/frontend.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #define STV0367_ICSPEED_53125 53125000 #define STV0367_ICSPEED_58000 58000000 diff --git a/drivers/media/dvb-frontends/stv0900.h b/drivers/media/dvb-frontends/stv0900.h index 1571a465e05c..5dbe1e550fe5 100644 --- a/drivers/media/dvb-frontends/stv0900.h +++ b/drivers/media/dvb-frontends/stv0900.h @@ -23,7 +23,7 @@ #define STV0900_H #include <linux/dvb/frontend.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> struct stv0900_reg { u16 addr; diff --git a/drivers/media/dvb-frontends/stv0900_core.c b/drivers/media/dvb-frontends/stv0900_core.c index 0b739725e3c0..72f17b97ca04 100644 --- a/drivers/media/dvb-frontends/stv0900_core.c +++ b/drivers/media/dvb-frontends/stv0900_core.c @@ -1929,7 +1929,7 @@ struct dvb_frontend *stv0900_attach(const struct stv0900_config *config, switch (demod) { case 0: case 1: - init_params.dmd_ref_clk = config->xtal; + init_params.dmd_ref_clk = config->xtal; init_params.demod_mode = config->demod_mode; init_params.rolloff = STV0900_35; init_params.path1_ts_clock = config->path1_mode; diff --git a/drivers/media/dvb-frontends/stv0900_init.h b/drivers/media/dvb-frontends/stv0900_init.h index 411941442086..550ef4a0f654 100644 --- a/drivers/media/dvb-frontends/stv0900_init.h +++ b/drivers/media/dvb-frontends/stv0900_init.h @@ -148,8 +148,8 @@ struct stv0900_short_frames_car_loop_optim_vs_mod { /* Cut 1.x Tracking carrier loop carrier QPSK 1/2 to 8PSK 9/10 long Frame */ static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoop[14] = { - /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon - 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ + /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon + 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ { STV0900_QPSK_12, 0x1C, 0x0D, 0x1B, 0x2C, 0x3A, 0x1C, 0x2A, 0x3B, 0x2A, 0x1B }, { STV0900_QPSK_35, 0x2C, 0x0D, 0x2B, 0x2C, 0x3A, @@ -176,15 +176,15 @@ static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoop[14] = { 0x0B, 0x39, 0x1A, 0x19, 0x0A }, { STV0900_8PSK_89, 0x3B, 0x3B, 0x0B, 0x2B, 0x2A, 0x0B, 0x39, 0x1A, 0x29, 0x39 }, - { STV0900_8PSK_910, 0x3B, 0x3B, 0x0B, 0x2B, 0x2A, + { STV0900_8PSK_910, 0x3B, 0x3B, 0x0B, 0x2B, 0x2A, 0x0B, 0x39, 0x1A, 0x29, 0x39 } }; /* Cut 2.0 Tracking carrier loop carrier QPSK 1/2 to 8PSK 9/10 long Frame */ static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut20[14] = { - /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon - 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ + /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon + 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ { STV0900_QPSK_12, 0x1F, 0x3F, 0x1E, 0x3F, 0x3D, 0x1F, 0x3D, 0x3E, 0x3D, 0x1E }, { STV0900_QPSK_35, 0x2F, 0x3F, 0x2E, 0x2F, 0x3D, @@ -211,7 +211,7 @@ static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut20[14] = { 0x1e, 0x3c, 0x2d, 0x2c, 0x1d }, { STV0900_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d }, - { STV0900_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, + { STV0900_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }, }; @@ -219,8 +219,8 @@ static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut20[14] = { /* Cut 2.0 Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame */ static const struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut20[11] = { - /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon - 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ + /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon + 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ { STV0900_16APSK_23, 0x0C, 0x0C, 0x0C, 0x0C, 0x1D, 0x0C, 0x3C, 0x0C, 0x2C, 0x0C }, { STV0900_16APSK_34, 0x0C, 0x0C, 0x0C, 0x0C, 0x0E, @@ -248,8 +248,8 @@ static const struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut20[11] = { /* Cut 2.0 Tracking carrier loop carrier QPSK 1/4 to QPSK 2/5 long Frame */ static const struct stv0900_car_loop_optim FE_STV0900_S2LowQPCarLoopCut20[3] = { - /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon - 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ + /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon + 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ { STV0900_QPSK_14, 0x0F, 0x3F, 0x0E, 0x3F, 0x2D, 0x2F, 0x2D, 0x1F, 0x3D, 0x3E }, { STV0900_QPSK_13, 0x0F, 0x3F, 0x0E, 0x3F, 0x2D, @@ -275,10 +275,10 @@ struct stv0900_short_frames_car_loop_optim FE_STV0900_S2ShortCarLoop[4] = { }; static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut30[14] = { - /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon - 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ + /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon + 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ { STV0900_QPSK_12, 0x3C, 0x2C, 0x0C, 0x2C, 0x1B, - 0x2C, 0x1B, 0x1C, 0x0B, 0x3B }, + 0x2C, 0x1B, 0x1C, 0x0B, 0x3B }, { STV0900_QPSK_35, 0x0D, 0x0D, 0x0C, 0x0D, 0x1B, 0x3C, 0x1B, 0x1C, 0x0B, 0x3B }, { STV0900_QPSK_23, 0x1D, 0x0D, 0x0C, 0x1D, 0x2B, @@ -309,8 +309,8 @@ static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut30[14] = { static const struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut30[11] = { - /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon - 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ + /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon + 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ { STV0900_16APSK_23, 0x0A, 0x0A, 0x0A, 0x0A, 0x1A, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A }, { STV0900_16APSK_34, 0x0A, 0x0A, 0x0A, 0x0A, 0x0B, @@ -337,8 +337,8 @@ struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut30[11] = { static const struct stv0900_car_loop_optim FE_STV0900_S2LowQPCarLoopCut30[3] = { - /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon - 10MPoff 20MPon 20MPoff 30MPon 30MPoff*/ + /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon + 10MPoff 20MPon 20MPoff 30MPon 30MPoff*/ { STV0900_QPSK_14, 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x2A, 0x1C, 0x3A, 0x3B }, { STV0900_QPSK_13, 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, diff --git a/drivers/media/dvb-frontends/stv0900_priv.h b/drivers/media/dvb-frontends/stv0900_priv.h index 7a95f955627b..d1fc06ff27d3 100644 --- a/drivers/media/dvb-frontends/stv0900_priv.h +++ b/drivers/media/dvb-frontends/stv0900_priv.h @@ -243,7 +243,7 @@ struct stv0900_init_params{ u8 tun1_maddress; int tuner1_adc; - int tuner1_type; + int tuner1_type; /* IQ from the tuner1 to the demod */ enum stv0900_iq_inversion tun1_iq_inv; diff --git a/drivers/media/dvb-frontends/stv090x.c b/drivers/media/dvb-frontends/stv090x.c index 7ef469c0c866..9133f65d4623 100644 --- a/drivers/media/dvb-frontends/stv090x.c +++ b/drivers/media/dvb-frontends/stv090x.c @@ -27,7 +27,7 @@ #include <linux/mutex.h> #include <linux/dvb/frontend.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "stv6110x.h" /* for demodulator internal modes */ @@ -677,7 +677,7 @@ static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = { /* Cut 3.0 Short Frame Tracking CR Loop */ static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = { - /* MODCOD 2M 5M 10M 20M 30M */ + /* MODCOD 2M 5M 10M 20M 30M */ { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A }, { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 }, { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }, @@ -701,7 +701,7 @@ static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg) u8 buf; struct i2c_msg msg[] = { - { .addr = config->address, .flags = 0, .buf = b0, .len = 2 }, + { .addr = config->address, .flags = 0, .buf = b0, .len = 2 }, { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 } }; @@ -755,7 +755,9 @@ static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data) { - return stv090x_write_regs(state, reg, &data, 1); + u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ + + return stv090x_write_regs(state, reg, &tmp, 1); } static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable) @@ -2215,13 +2217,12 @@ static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd) if (state->config->tuner_get_status) { if (state->config->tuner_get_status(fe, ®) < 0) goto err_gateoff; + if (reg) + dprintk(FE_DEBUG, 1, "Tuner phase locked"); + else + dprintk(FE_DEBUG, 1, "Tuner unlocked"); } - if (reg) - dprintk(FE_DEBUG, 1, "Tuner phase locked"); - else - dprintk(FE_DEBUG, 1, "Tuner unlocked"); - if (stv090x_i2c_gate_ctrl(state, 0) < 0) goto err; @@ -3429,6 +3430,21 @@ err: return -1; } +static int stv090x_set_pls(struct stv090x_state *state, u32 pls_code) +{ + dprintk(FE_DEBUG, 1, "Set Gold PLS code %d", pls_code); + if (STV090x_WRITE_DEMOD(state, PLROOT0, pls_code & 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, PLROOT1, (pls_code >> 8) & 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, PLROOT2, 0x04 | (pls_code >> 16)) < 0) + goto err; + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + static int stv090x_set_mis(struct stv090x_state *state, int mis) { u32 reg; @@ -3491,6 +3507,7 @@ static enum dvbfe_search stv090x_search(struct dvb_frontend *fe) state->search_range = 5000000; } + stv090x_set_pls(state, props->scrambling_sequence_index); stv090x_set_mis(state, props->stream_id); if (stv090x_algo(state) == STV090x_RANGEOK) { @@ -4889,11 +4906,11 @@ static const struct dvb_frontend_ops stv090x_ops = { .info = { .name = "STV090x Multistandard", .frequency_min = 950000, - .frequency_max = 2150000, + .frequency_max = 2150000, .frequency_stepsize = 0, .frequency_tolerance = 0, - .symbol_rate_min = 1000000, - .symbol_rate_max = 45000000, + .symbol_rate_min = 1000000, + .symbol_rate_max = 45000000, .caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO | FE_CAN_QPSK | @@ -4936,7 +4953,7 @@ struct dvb_frontend *stv090x_attach(struct stv090x_config *config, state->frontend.ops = stv090x_ops; state->frontend.demodulator_priv = state; state->demod = demod; - state->demod_mode = config->demod_mode; /* Single or Dual mode */ + state->demod_mode = config->demod_mode; /* Single or Dual mode */ state->device = config->device; state->rolloff = STV090x_RO_35; /* default */ diff --git a/drivers/media/dvb-frontends/stv090x_priv.h b/drivers/media/dvb-frontends/stv090x_priv.h index 5b780c80d496..fdda2185db9d 100644 --- a/drivers/media/dvb-frontends/stv090x_priv.h +++ b/drivers/media/dvb-frontends/stv090x_priv.h @@ -22,7 +22,7 @@ #ifndef __STV090x_PRIV_H #define __STV090x_PRIV_H -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #define FE_ERROR 0 #define FE_NOTICE 1 @@ -231,7 +231,7 @@ struct stv090x_tab { }; struct stv090x_internal { - struct i2c_adapter *i2c_adap; + struct i2c_adapter *i2c_adap; u8 i2c_addr; struct mutex demod_lock; /* Lock access to shared register */ diff --git a/drivers/media/dvb-frontends/stv0910.c b/drivers/media/dvb-frontends/stv0910.c index 8bf855c301f5..a2f7c0c1587f 100644 --- a/drivers/media/dvb-frontends/stv0910.c +++ b/drivers/media/dvb-frontends/stv0910.c @@ -24,8 +24,7 @@ #include <linux/i2c.h> #include <asm/div64.h> -#include "dvb_math.h" -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "stv0910.h" #include "stv0910_regs.h" @@ -138,33 +137,21 @@ struct slookup { u32 reg_value; }; -static inline int i2c_write(struct i2c_adapter *adap, u8 adr, - u8 *data, int len) +static int write_reg(struct stv *state, u16 reg, u8 val) { - struct i2c_msg msg = {.addr = adr, .flags = 0, - .buf = data, .len = len}; + struct i2c_adapter *adap = state->base->i2c; + u8 data[3] = {reg >> 8, reg & 0xff, val}; + struct i2c_msg msg = {.addr = state->base->adr, .flags = 0, + .buf = data, .len = 3}; if (i2c_transfer(adap, &msg, 1) != 1) { dev_warn(&adap->dev, "i2c write error ([%02x] %04x: %02x)\n", - adr, (data[0] << 8) | data[1], - (len > 2 ? data[2] : 0)); - return -EREMOTEIO; + state->base->adr, reg, val); + return -EIO; } return 0; } -static int i2c_write_reg16(struct i2c_adapter *adap, u8 adr, u16 reg, u8 val) -{ - u8 msg[3] = {reg >> 8, reg & 0xff, val}; - - return i2c_write(adap, adr, msg, 3); -} - -static int write_reg(struct stv *state, u16 reg, u8 val) -{ - return i2c_write_reg16(state->base->i2c, state->base->adr, reg, val); -} - static inline int i2c_read_regs16(struct i2c_adapter *adapter, u8 adr, u16 reg, u8 *val, int count) { @@ -177,7 +164,7 @@ static inline int i2c_read_regs16(struct i2c_adapter *adapter, u8 adr, if (i2c_transfer(adapter, msgs, 2) != 2) { dev_warn(&adapter->dev, "i2c read error ([%02x] %04x)\n", adr, reg); - return -EREMOTEIO; + return -EIO; } return 0; } @@ -207,6 +194,34 @@ static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val) return status; } +static int write_field(struct stv *state, u32 field, u8 val) +{ + int status; + u8 shift, mask, old, new; + + status = read_reg(state, field >> 16, &old); + if (status) + return status; + mask = field & 0xff; + shift = (field >> 12) & 0xf; + new = ((val << shift) & mask) | (old & ~mask); + if (new == old) + return 0; + return write_reg(state, field >> 16, new); +} + +#define SET_FIELD(_reg, _val) \ + write_field(state, state->nr ? FSTV0910_P2_##_reg : \ + FSTV0910_P1_##_reg, _val) + +#define SET_REG(_reg, _val) \ + write_reg(state, state->nr ? RSTV0910_P2_##_reg : \ + RSTV0910_P1_##_reg, _val) + +#define GET_REG(_reg, _val) \ + read_reg(state, state->nr ? RSTV0910_P2_##_reg : \ + RSTV0910_P1_##_reg, _val) + static const struct slookup s1_sn_lookup[] = { { 0, 9242 }, /* C/N= 0dB */ { 5, 9105 }, /* C/N= 0.5dB */ @@ -533,10 +548,8 @@ static int get_signal_parameters(struct stv *state) static int tracking_optimization(struct stv *state) { - u32 symbol_rate = 0; u8 tmp; - get_cur_symbol_rate(state, &symbol_rate); read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp); tmp &= ~0xC0; @@ -867,71 +880,90 @@ static int stop(struct stv *state) return 0; } -static int init_search_param(struct stv *state) +static void set_pls(struct stv *state, u32 pls_code) { - u8 tmp; - - read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp); - tmp |= 0x20; /* Filter_en (no effect if SIS=non-MIS */ - write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp); - - read_reg(state, RSTV0910_P2_PDELCTRL2 + state->regoff, &tmp); - tmp &= ~0x02; /* frame mode = 0 */ - write_reg(state, RSTV0910_P2_PDELCTRL2 + state->regoff, tmp); - - write_reg(state, RSTV0910_P2_UPLCCST0 + state->regoff, 0xe0); - write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0x00); - - read_reg(state, RSTV0910_P2_TSSTATEM + state->regoff, &tmp); - tmp &= ~0x01; /* nosync = 0, in case next signal is standard TS */ - write_reg(state, RSTV0910_P2_TSSTATEM + state->regoff, tmp); - - read_reg(state, RSTV0910_P2_TSCFGL + state->regoff, &tmp); - tmp &= ~0x04; /* embindvb = 0 */ - write_reg(state, RSTV0910_P2_TSCFGL + state->regoff, tmp); - - read_reg(state, RSTV0910_P2_TSINSDELH + state->regoff, &tmp); - tmp &= ~0x80; /* syncbyte = 0 */ - write_reg(state, RSTV0910_P2_TSINSDELH + state->regoff, tmp); - - read_reg(state, RSTV0910_P2_TSINSDELM + state->regoff, &tmp); - tmp &= ~0x08; /* token = 0 */ - write_reg(state, RSTV0910_P2_TSINSDELM + state->regoff, tmp); + if (pls_code == state->cur_scrambling_code) + return; + + /* PLROOT2 bit 2 = gold code */ + write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff, + pls_code & 0xff); + write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff, + (pls_code >> 8) & 0xff); + write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff, + 0x04 | ((pls_code >> 16) & 0x03)); + state->cur_scrambling_code = pls_code; +} - read_reg(state, RSTV0910_P2_TSDLYSET2 + state->regoff, &tmp); - tmp &= ~0x30; /* hysteresis threshold = 0 */ - write_reg(state, RSTV0910_P2_TSDLYSET2 + state->regoff, tmp); +static void set_isi(struct stv *state, u32 isi) +{ + if (isi == NO_STREAM_ID_FILTER) + return; + if (isi == 0x80000000) { + SET_FIELD(FORCE_CONTINUOUS, 1); + SET_FIELD(TSOUT_NOSYNC, 1); + } else { + SET_FIELD(FILTER_EN, 1); + write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff, + isi & 0xff); + write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff); + } + SET_FIELD(ALGOSWRST, 1); + SET_FIELD(ALGOSWRST, 0); +} - read_reg(state, RSTV0910_P2_PDELCTRL0 + state->regoff, &tmp); - tmp = (tmp & ~0x30) | 0x10; /* isi obs mode = 1, observe min ISI */ - write_reg(state, RSTV0910_P2_PDELCTRL0 + state->regoff, tmp); +static void set_stream_modes(struct stv *state, + struct dtv_frontend_properties *p) +{ + set_isi(state, p->stream_id); + set_pls(state, p->scrambling_sequence_index); +} +static int init_search_param(struct stv *state, + struct dtv_frontend_properties *p) +{ + SET_FIELD(FORCE_CONTINUOUS, 0); + SET_FIELD(FRAME_MODE, 0); + SET_FIELD(FILTER_EN, 0); + SET_FIELD(TSOUT_NOSYNC, 0); + SET_FIELD(TSFIFO_EMBINDVB, 0); + SET_FIELD(TSDEL_SYNCBYTE, 0); + SET_REG(UPLCCST0, 0xe0); + SET_FIELD(TSINS_TOKEN, 0); + SET_FIELD(HYSTERESIS_THRESHOLD, 0); + SET_FIELD(ISIOBS_MODE, 1); + + set_stream_modes(state, p); return 0; } static int enable_puncture_rate(struct stv *state, enum fe_code_rate rate) { + u8 val; + switch (rate) { case FEC_1_2: - return write_reg(state, - RSTV0910_P2_PRVIT + state->regoff, 0x01); + val = 0x01; + break; case FEC_2_3: - return write_reg(state, - RSTV0910_P2_PRVIT + state->regoff, 0x02); + val = 0x02; + break; case FEC_3_4: - return write_reg(state, - RSTV0910_P2_PRVIT + state->regoff, 0x04); + val = 0x04; + break; case FEC_5_6: - return write_reg(state, - RSTV0910_P2_PRVIT + state->regoff, 0x08); + val = 0x08; + break; case FEC_7_8: - return write_reg(state, - RSTV0910_P2_PRVIT + state->regoff, 0x20); + val = 0x20; + break; case FEC_NONE: default: - return write_reg(state, - RSTV0910_P2_PRVIT + state->regoff, 0x2f); + val = 0x2f; + break; } + + return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val); } static int set_vth_default(struct stv *state) @@ -988,7 +1020,6 @@ static int start(struct stv *state, struct dtv_frontend_properties *p) s32 freq; u8 reg_dmdcfgmd; u16 symb; - u32 scrambling_code = 1; if (p->symbol_rate < 100000 || p->symbol_rate > 70000000) return -EINVAL; @@ -1000,30 +1031,7 @@ static int start(struct stv *state, struct dtv_frontend_properties *p) if (state->started) write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C); - init_search_param(state); - - if (p->stream_id != NO_STREAM_ID_FILTER) { - /* - * Backwards compatibility to "crazy" API. - * PRBS X root cannot be 0, so this should always work. - */ - if (p->stream_id & 0xffffff00) - scrambling_code = p->stream_id >> 8; - write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff, - p->stream_id & 0xff); - write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, - 0xff); - } - - if (scrambling_code != state->cur_scrambling_code) { - write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff, - scrambling_code & 0xff); - write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff, - (scrambling_code >> 8) & 0xff); - write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff, - (scrambling_code >> 16) & 0x0f); - state->cur_scrambling_code = scrambling_code; - } + init_search_param(state, p); if (p->symbol_rate <= 1000000) { /* SR <=1Msps */ state->demod_timeout = 3000; @@ -1241,7 +1249,8 @@ static int gate_ctrl(struct dvb_frontend *fe, int enable) if (write_reg(state, state->nr ? RSTV0910_P2_I2CRPT : RSTV0910_P1_I2CRPT, i2crpt) < 0) { /* don't hold the I2C bus lock on failure */ - mutex_unlock(&state->base->i2c_lock); + if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock))) + mutex_unlock(&state->base->i2c_lock); dev_err(&state->base->i2c->dev, "%s() write_reg failure (enable=%d)\n", __func__, enable); @@ -1251,7 +1260,8 @@ static int gate_ctrl(struct dvb_frontend *fe, int enable) state->i2crpt = i2crpt; if (!enable) - mutex_unlock(&state->base->i2c_lock); + if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock))) + mutex_unlock(&state->base->i2c_lock); return 0; } @@ -1271,14 +1281,11 @@ static int set_parameters(struct dvb_frontend *fe) { int stat = 0; struct stv *state = fe->demodulator_priv; - u32 iffreq; struct dtv_frontend_properties *p = &fe->dtv_property_cache; stop(state); if (fe->ops.tuner_ops.set_params) fe->ops.tuner_ops.set_params(fe); - if (fe->ops.tuner_ops.get_if_frequency) - fe->ops.tuner_ops.get_if_frequency(fe, &iffreq); state->symbol_rate = p->symbol_rate; stat = start(state, p); return stat; @@ -1498,6 +1505,19 @@ static int read_status(struct dvb_frontend *fe, enum fe_status *status) enable_puncture_rate(state, state->puncture_rate); } + + /* Use highest signaled ModCod for quality */ + if (state->is_vcm) { + u8 tmp; + enum fe_stv0910_mod_cod mod_cod; + + read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, + &tmp); + mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2); + + if (mod_cod > state->mod_cod) + state->mod_cod = mod_cod; + } } /* read signal statistics */ @@ -1527,6 +1547,7 @@ static int get_frontend(struct dvb_frontend *fe, { struct stv *state = fe->demodulator_priv; u8 tmp; + u32 symbolrate; if (state->receive_mode == RCVMODE_DVBS2) { u32 mc; @@ -1580,6 +1601,10 @@ static int get_frontend(struct dvb_frontend *fe, p->rolloff = ROLLOFF_35; } + if (state->receive_mode != RCVMODE_NONE) { + get_cur_symbol_rate(state, &symbolrate); + p->symbol_rate = symbolrate; + } return 0; } diff --git a/drivers/media/dvb-frontends/stv0910_regs.h b/drivers/media/dvb-frontends/stv0910_regs.h index 32ced4eaf296..f0eb915090bd 100644 --- a/drivers/media/dvb-frontends/stv0910_regs.h +++ b/drivers/media/dvb-frontends/stv0910_regs.h @@ -7,15 +7,15 @@ * Registers Declaration (Internal ST, All Applications ) * ------------------------- * Each register (RSTV0910__XXXXX) is defined by its address (2 bytes). - * - * Each field (FSTV0910__XXXXX)is defined as follow: - * [register address -- 2bytes][field sign -- 1byte][field mask -- 1byte] - * ====================================================================== + * Each field (FSTV0910__XXXXX) is defined as follow: + * [register address -- 2bytes][field offset -- 4 bits][unused -- 3 bits] + * [field sign -- 1 bit][field mask -- 1byte] + * ======================================================================= */ /* MID */ #define RSTV0910_MID 0xf100 -#define FSTV0910_MCHIP_IDENT 0xf10000f0 +#define FSTV0910_MCHIP_IDENT 0xf10040f0 #define FSTV0910_MRELEASE 0xf100000f /* DID */ @@ -24,7 +24,7 @@ /* DACR1 */ #define RSTV0910_DACR1 0xf113 -#define FSTV0910_DAC_MODE 0xf11300e0 +#define FSTV0910_DAC_MODE 0xf11350e0 #define FSTV0910_DAC_VALUE1 0xf113000f /* DACR2 */ @@ -33,283 +33,283 @@ /* PADCFG */ #define RSTV0910_PADCFG 0xf11a -#define FSTV0910_AGCRF2_OPD 0xf11a0008 -#define FSTV0910_AGCRF2_XOR 0xf11a0004 -#define FSTV0910_AGCRF1_OPD 0xf11a0002 +#define FSTV0910_AGCRF2_OPD 0xf11a3008 +#define FSTV0910_AGCRF2_XOR 0xf11a2004 +#define FSTV0910_AGCRF1_OPD 0xf11a1002 #define FSTV0910_AGCRF1_XOR 0xf11a0001 /* OUTCFG2 */ #define RSTV0910_OUTCFG2 0xf11b -#define FSTV0910_TS2_ERROR_XOR 0xf11b0080 -#define FSTV0910_TS2_DPN_XOR 0xf11b0040 -#define FSTV0910_TS2_STROUT_XOR 0xf11b0020 -#define FSTV0910_TS2_CLOCKOUT_XOR 0xf11b0010 -#define FSTV0910_TS1_ERROR_XOR 0xf11b0008 -#define FSTV0910_TS1_DPN_XOR 0xf11b0004 -#define FSTV0910_TS1_STROUT_XOR 0xf11b0002 +#define FSTV0910_TS2_ERROR_XOR 0xf11b7080 +#define FSTV0910_TS2_DPN_XOR 0xf11b6040 +#define FSTV0910_TS2_STROUT_XOR 0xf11b5020 +#define FSTV0910_TS2_CLOCKOUT_XOR 0xf11b4010 +#define FSTV0910_TS1_ERROR_XOR 0xf11b3008 +#define FSTV0910_TS1_DPN_XOR 0xf11b2004 +#define FSTV0910_TS1_STROUT_XOR 0xf11b1002 #define FSTV0910_TS1_CLOCKOUT_XOR 0xf11b0001 /* OUTCFG */ #define RSTV0910_OUTCFG 0xf11c -#define FSTV0910_TS2_OUTSER_HZ 0xf11c0020 -#define FSTV0910_TS1_OUTSER_HZ 0xf11c0010 -#define FSTV0910_TS2_OUTPAR_HZ 0xf11c0008 -#define FSTV0910_TS1_OUTPAR_HZ 0xf11c0004 -#define FSTV0910_TS_SERDATA0 0xf11c0002 +#define FSTV0910_TS2_OUTSER_HZ 0xf11c5020 +#define FSTV0910_TS1_OUTSER_HZ 0xf11c4010 +#define FSTV0910_TS2_OUTPAR_HZ 0xf11c3008 +#define FSTV0910_TS1_OUTPAR_HZ 0xf11c2004 +#define FSTV0910_TS_SERDATA0 0xf11c1002 /* IRQSTATUS3 */ #define RSTV0910_IRQSTATUS3 0xf120 -#define FSTV0910_SPLL_LOCK 0xf1200020 -#define FSTV0910_SSTREAM_LCK_1 0xf1200010 -#define FSTV0910_SSTREAM_LCK_2 0xf1200008 -#define FSTV0910_SDVBS1_PRF_2 0xf1200002 +#define FSTV0910_SPLL_LOCK 0xf1205020 +#define FSTV0910_SSTREAM_LCK_1 0xf1204010 +#define FSTV0910_SSTREAM_LCK_2 0xf1203008 +#define FSTV0910_SDVBS1_PRF_2 0xf1201002 #define FSTV0910_SDVBS1_PRF_1 0xf1200001 /* IRQSTATUS2 */ #define RSTV0910_IRQSTATUS2 0xf121 -#define FSTV0910_SSPY_ENDSIM_1 0xf1210080 -#define FSTV0910_SSPY_ENDSIM_2 0xf1210040 -#define FSTV0910_SPKTDEL_ERROR_2 0xf1210010 -#define FSTV0910_SPKTDEL_LOCKB_2 0xf1210008 -#define FSTV0910_SPKTDEL_LOCK_2 0xf1210004 -#define FSTV0910_SPKTDEL_ERROR_1 0xf1210002 +#define FSTV0910_SSPY_ENDSIM_1 0xf1217080 +#define FSTV0910_SSPY_ENDSIM_2 0xf1216040 +#define FSTV0910_SPKTDEL_ERROR_2 0xf1214010 +#define FSTV0910_SPKTDEL_LOCKB_2 0xf1213008 +#define FSTV0910_SPKTDEL_LOCK_2 0xf1212004 +#define FSTV0910_SPKTDEL_ERROR_1 0xf1211002 #define FSTV0910_SPKTDEL_LOCKB_1 0xf1210001 /* IRQSTATUS1 */ #define RSTV0910_IRQSTATUS1 0xf122 -#define FSTV0910_SPKTDEL_LOCK_1 0xf1220080 -#define FSTV0910_SFEC_LOCKB_2 0xf1220040 -#define FSTV0910_SFEC_LOCK_2 0xf1220020 -#define FSTV0910_SFEC_LOCKB_1 0xf1220010 -#define FSTV0910_SFEC_LOCK_1 0xf1220008 -#define FSTV0910_SDEMOD_LOCKB_2 0xf1220004 -#define FSTV0910_SDEMOD_LOCK_2 0xf1220002 +#define FSTV0910_SPKTDEL_LOCK_1 0xf1227080 +#define FSTV0910_SFEC_LOCKB_2 0xf1226040 +#define FSTV0910_SFEC_LOCK_2 0xf1225020 +#define FSTV0910_SFEC_LOCKB_1 0xf1224010 +#define FSTV0910_SFEC_LOCK_1 0xf1223008 +#define FSTV0910_SDEMOD_LOCKB_2 0xf1222004 +#define FSTV0910_SDEMOD_LOCK_2 0xf1221002 #define FSTV0910_SDEMOD_IRQ_2 0xf1220001 /* IRQSTATUS0 */ #define RSTV0910_IRQSTATUS0 0xf123 -#define FSTV0910_SDEMOD_LOCKB_1 0xf1230080 -#define FSTV0910_SDEMOD_LOCK_1 0xf1230040 -#define FSTV0910_SDEMOD_IRQ_1 0xf1230020 -#define FSTV0910_SBCH_ERRFLAG 0xf1230010 -#define FSTV0910_SDISEQC2_IRQ 0xf1230004 +#define FSTV0910_SDEMOD_LOCKB_1 0xf1237080 +#define FSTV0910_SDEMOD_LOCK_1 0xf1236040 +#define FSTV0910_SDEMOD_IRQ_1 0xf1235020 +#define FSTV0910_SBCH_ERRFLAG 0xf1234010 +#define FSTV0910_SDISEQC2_IRQ 0xf1232004 #define FSTV0910_SDISEQC1_IRQ 0xf1230001 /* IRQMASK3 */ #define RSTV0910_IRQMASK3 0xf124 -#define FSTV0910_MPLL_LOCK 0xf1240020 -#define FSTV0910_MSTREAM_LCK_1 0xf1240010 -#define FSTV0910_MSTREAM_LCK_2 0xf1240008 -#define FSTV0910_MDVBS1_PRF_2 0xf1240002 +#define FSTV0910_MPLL_LOCK 0xf1245020 +#define FSTV0910_MSTREAM_LCK_1 0xf1244010 +#define FSTV0910_MSTREAM_LCK_2 0xf1243008 +#define FSTV0910_MDVBS1_PRF_2 0xf1241002 #define FSTV0910_MDVBS1_PRF_1 0xf1240001 /* IRQMASK2 */ #define RSTV0910_IRQMASK2 0xf125 -#define FSTV0910_MSPY_ENDSIM_1 0xf1250080 -#define FSTV0910_MSPY_ENDSIM_2 0xf1250040 -#define FSTV0910_MPKTDEL_ERROR_2 0xf1250010 -#define FSTV0910_MPKTDEL_LOCKB_2 0xf1250008 -#define FSTV0910_MPKTDEL_LOCK_2 0xf1250004 -#define FSTV0910_MPKTDEL_ERROR_1 0xf1250002 +#define FSTV0910_MSPY_ENDSIM_1 0xf1257080 +#define FSTV0910_MSPY_ENDSIM_2 0xf1256040 +#define FSTV0910_MPKTDEL_ERROR_2 0xf1254010 +#define FSTV0910_MPKTDEL_LOCKB_2 0xf1253008 +#define FSTV0910_MPKTDEL_LOCK_2 0xf1252004 +#define FSTV0910_MPKTDEL_ERROR_1 0xf1251002 #define FSTV0910_MPKTDEL_LOCKB_1 0xf1250001 /* IRQMASK1 */ #define RSTV0910_IRQMASK1 0xf126 -#define FSTV0910_MPKTDEL_LOCK_1 0xf1260080 -#define FSTV0910_MFEC_LOCKB_2 0xf1260040 -#define FSTV0910_MFEC_LOCK_2 0xf1260020 -#define FSTV0910_MFEC_LOCKB_1 0xf1260010 -#define FSTV0910_MFEC_LOCK_1 0xf1260008 -#define FSTV0910_MDEMOD_LOCKB_2 0xf1260004 -#define FSTV0910_MDEMOD_LOCK_2 0xf1260002 +#define FSTV0910_MPKTDEL_LOCK_1 0xf1267080 +#define FSTV0910_MFEC_LOCKB_2 0xf1266040 +#define FSTV0910_MFEC_LOCK_2 0xf1265020 +#define FSTV0910_MFEC_LOCKB_1 0xf1264010 +#define FSTV0910_MFEC_LOCK_1 0xf1263008 +#define FSTV0910_MDEMOD_LOCKB_2 0xf1262004 +#define FSTV0910_MDEMOD_LOCK_2 0xf1261002 #define FSTV0910_MDEMOD_IRQ_2 0xf1260001 /* IRQMASK0 */ #define RSTV0910_IRQMASK0 0xf127 -#define FSTV0910_MDEMOD_LOCKB_1 0xf1270080 -#define FSTV0910_MDEMOD_LOCK_1 0xf1270040 -#define FSTV0910_MDEMOD_IRQ_1 0xf1270020 -#define FSTV0910_MBCH_ERRFLAG 0xf1270010 -#define FSTV0910_MDISEQC2_IRQ 0xf1270004 +#define FSTV0910_MDEMOD_LOCKB_1 0xf1277080 +#define FSTV0910_MDEMOD_LOCK_1 0xf1276040 +#define FSTV0910_MDEMOD_IRQ_1 0xf1275020 +#define FSTV0910_MBCH_ERRFLAG 0xf1274010 +#define FSTV0910_MDISEQC2_IRQ 0xf1272004 #define FSTV0910_MDISEQC1_IRQ 0xf1270001 /* I2CCFG */ #define RSTV0910_I2CCFG 0xf129 -#define FSTV0910_I2C_FASTMODE 0xf1290008 +#define FSTV0910_I2C_FASTMODE 0xf1293008 #define FSTV0910_I2CADDR_INC 0xf1290003 /* P1_I2CRPT */ #define RSTV0910_P1_I2CRPT 0xf12a -#define FSTV0910_P1_I2CT_ON 0xf12a0080 -#define FSTV0910_P1_ENARPT_LEVEL 0xf12a0070 -#define FSTV0910_P1_SCLT_DELAY 0xf12a0008 -#define FSTV0910_P1_STOP_ENABLE 0xf12a0004 -#define FSTV0910_P1_STOP_SDAT2SDA 0xf12a0002 +#define FSTV0910_P1_I2CT_ON 0xf12a7080 +#define FSTV0910_P1_ENARPT_LEVEL 0xf12a4070 +#define FSTV0910_P1_SCLT_DELAY 0xf12a3008 +#define FSTV0910_P1_STOP_ENABLE 0xf12a2004 +#define FSTV0910_P1_STOP_SDAT2SDA 0xf12a1002 /* P2_I2CRPT */ #define RSTV0910_P2_I2CRPT 0xf12b -#define FSTV0910_P2_I2CT_ON 0xf12b0080 -#define FSTV0910_P2_ENARPT_LEVEL 0xf12b0070 -#define FSTV0910_P2_SCLT_DELAY 0xf12b0008 -#define FSTV0910_P2_STOP_ENABLE 0xf12b0004 -#define FSTV0910_P2_STOP_SDAT2SDA 0xf12b0002 +#define FSTV0910_P2_I2CT_ON 0xf12b7080 +#define FSTV0910_P2_ENARPT_LEVEL 0xf12b4070 +#define FSTV0910_P2_SCLT_DELAY 0xf12b3008 +#define FSTV0910_P2_STOP_ENABLE 0xf12b2004 +#define FSTV0910_P2_STOP_SDAT2SDA 0xf12b1002 /* GPIO0CFG */ #define RSTV0910_GPIO0CFG 0xf140 -#define FSTV0910_GPIO0_OPD 0xf1400080 -#define FSTV0910_GPIO0_CONFIG 0xf140007e +#define FSTV0910_GPIO0_OPD 0xf1407080 +#define FSTV0910_GPIO0_CONFIG 0xf140107e #define FSTV0910_GPIO0_XOR 0xf1400001 /* GPIO1CFG */ #define RSTV0910_GPIO1CFG 0xf141 -#define FSTV0910_GPIO1_OPD 0xf1410080 -#define FSTV0910_GPIO1_CONFIG 0xf141007e +#define FSTV0910_GPIO1_OPD 0xf1417080 +#define FSTV0910_GPIO1_CONFIG 0xf141107e #define FSTV0910_GPIO1_XOR 0xf1410001 /* GPIO2CFG */ #define RSTV0910_GPIO2CFG 0xf142 -#define FSTV0910_GPIO2_OPD 0xf1420080 -#define FSTV0910_GPIO2_CONFIG 0xf142007e +#define FSTV0910_GPIO2_OPD 0xf1427080 +#define FSTV0910_GPIO2_CONFIG 0xf142107e #define FSTV0910_GPIO2_XOR 0xf1420001 /* GPIO3CFG */ #define RSTV0910_GPIO3CFG 0xf143 -#define FSTV0910_GPIO3_OPD 0xf1430080 -#define FSTV0910_GPIO3_CONFIG 0xf143007e +#define FSTV0910_GPIO3_OPD 0xf1437080 +#define FSTV0910_GPIO3_CONFIG 0xf143107e #define FSTV0910_GPIO3_XOR 0xf1430001 /* GPIO4CFG */ #define RSTV0910_GPIO4CFG 0xf144 -#define FSTV0910_GPIO4_OPD 0xf1440080 -#define FSTV0910_GPIO4_CONFIG 0xf144007e +#define FSTV0910_GPIO4_OPD 0xf1447080 +#define FSTV0910_GPIO4_CONFIG 0xf144107e #define FSTV0910_GPIO4_XOR 0xf1440001 /* GPIO5CFG */ #define RSTV0910_GPIO5CFG 0xf145 -#define FSTV0910_GPIO5_OPD 0xf1450080 -#define FSTV0910_GPIO5_CONFIG 0xf145007e +#define FSTV0910_GPIO5_OPD 0xf1457080 +#define FSTV0910_GPIO5_CONFIG 0xf145107e #define FSTV0910_GPIO5_XOR 0xf1450001 /* GPIO6CFG */ #define RSTV0910_GPIO6CFG 0xf146 -#define FSTV0910_GPIO6_OPD 0xf1460080 -#define FSTV0910_GPIO6_CONFIG 0xf146007e +#define FSTV0910_GPIO6_OPD 0xf1467080 +#define FSTV0910_GPIO6_CONFIG 0xf146107e #define FSTV0910_GPIO6_XOR 0xf1460001 /* GPIO7CFG */ #define RSTV0910_GPIO7CFG 0xf147 -#define FSTV0910_GPIO7_OPD 0xf1470080 -#define FSTV0910_GPIO7_CONFIG 0xf147007e +#define FSTV0910_GPIO7_OPD 0xf1477080 +#define FSTV0910_GPIO7_CONFIG 0xf147107e #define FSTV0910_GPIO7_XOR 0xf1470001 /* GPIO8CFG */ #define RSTV0910_GPIO8CFG 0xf148 -#define FSTV0910_GPIO8_OPD 0xf1480080 -#define FSTV0910_GPIO8_CONFIG 0xf148007e +#define FSTV0910_GPIO8_OPD 0xf1487080 +#define FSTV0910_GPIO8_CONFIG 0xf148107e #define FSTV0910_GPIO8_XOR 0xf1480001 /* GPIO9CFG */ #define RSTV0910_GPIO9CFG 0xf149 -#define FSTV0910_GPIO9_OPD 0xf1490080 -#define FSTV0910_GPIO9_CONFIG 0xf149007e +#define FSTV0910_GPIO9_OPD 0xf1497080 +#define FSTV0910_GPIO9_CONFIG 0xf149107e #define FSTV0910_GPIO9_XOR 0xf1490001 /* GPIO10CFG */ #define RSTV0910_GPIO10CFG 0xf14a -#define FSTV0910_GPIO10_OPD 0xf14a0080 -#define FSTV0910_GPIO10_CONFIG 0xf14a007e +#define FSTV0910_GPIO10_OPD 0xf14a7080 +#define FSTV0910_GPIO10_CONFIG 0xf14a107e #define FSTV0910_GPIO10_XOR 0xf14a0001 /* GPIO11CFG */ #define RSTV0910_GPIO11CFG 0xf14b -#define FSTV0910_GPIO11_OPD 0xf14b0080 -#define FSTV0910_GPIO11_CONFIG 0xf14b007e +#define FSTV0910_GPIO11_OPD 0xf14b7080 +#define FSTV0910_GPIO11_CONFIG 0xf14b107e #define FSTV0910_GPIO11_XOR 0xf14b0001 /* GPIO12CFG */ #define RSTV0910_GPIO12CFG 0xf14c -#define FSTV0910_GPIO12_OPD 0xf14c0080 -#define FSTV0910_GPIO12_CONFIG 0xf14c007e +#define FSTV0910_GPIO12_OPD 0xf14c7080 +#define FSTV0910_GPIO12_CONFIG 0xf14c107e #define FSTV0910_GPIO12_XOR 0xf14c0001 /* GPIO13CFG */ #define RSTV0910_GPIO13CFG 0xf14d -#define FSTV0910_GPIO13_OPD 0xf14d0080 -#define FSTV0910_GPIO13_CONFIG 0xf14d007e +#define FSTV0910_GPIO13_OPD 0xf14d7080 +#define FSTV0910_GPIO13_CONFIG 0xf14d107e #define FSTV0910_GPIO13_XOR 0xf14d0001 /* GPIO14CFG */ #define RSTV0910_GPIO14CFG 0xf14e -#define FSTV0910_GPIO14_OPD 0xf14e0080 -#define FSTV0910_GPIO14_CONFIG 0xf14e007e +#define FSTV0910_GPIO14_OPD 0xf14e7080 +#define FSTV0910_GPIO14_CONFIG 0xf14e107e #define FSTV0910_GPIO14_XOR 0xf14e0001 /* GPIO15CFG */ #define RSTV0910_GPIO15CFG 0xf14f -#define FSTV0910_GPIO15_OPD 0xf14f0080 -#define FSTV0910_GPIO15_CONFIG 0xf14f007e +#define FSTV0910_GPIO15_OPD 0xf14f7080 +#define FSTV0910_GPIO15_CONFIG 0xf14f107e #define FSTV0910_GPIO15_XOR 0xf14f0001 /* GPIO16CFG */ #define RSTV0910_GPIO16CFG 0xf150 -#define FSTV0910_GPIO16_OPD 0xf1500080 -#define FSTV0910_GPIO16_CONFIG 0xf150007e +#define FSTV0910_GPIO16_OPD 0xf1507080 +#define FSTV0910_GPIO16_CONFIG 0xf150107e #define FSTV0910_GPIO16_XOR 0xf1500001 /* GPIO17CFG */ #define RSTV0910_GPIO17CFG 0xf151 -#define FSTV0910_GPIO17_OPD 0xf1510080 -#define FSTV0910_GPIO17_CONFIG 0xf151007e +#define FSTV0910_GPIO17_OPD 0xf1517080 +#define FSTV0910_GPIO17_CONFIG 0xf151107e #define FSTV0910_GPIO17_XOR 0xf1510001 /* GPIO18CFG */ #define RSTV0910_GPIO18CFG 0xf152 -#define FSTV0910_GPIO18_OPD 0xf1520080 -#define FSTV0910_GPIO18_CONFIG 0xf152007e +#define FSTV0910_GPIO18_OPD 0xf1527080 +#define FSTV0910_GPIO18_CONFIG 0xf152107e #define FSTV0910_GPIO18_XOR 0xf1520001 /* GPIO19CFG */ #define RSTV0910_GPIO19CFG 0xf153 -#define FSTV0910_GPIO19_OPD 0xf1530080 -#define FSTV0910_GPIO19_CONFIG 0xf153007e +#define FSTV0910_GPIO19_OPD 0xf1537080 +#define FSTV0910_GPIO19_CONFIG 0xf153107e #define FSTV0910_GPIO19_XOR 0xf1530001 /* GPIO20CFG */ #define RSTV0910_GPIO20CFG 0xf154 -#define FSTV0910_GPIO20_OPD 0xf1540080 -#define FSTV0910_GPIO20_CONFIG 0xf154007e +#define FSTV0910_GPIO20_OPD 0xf1547080 +#define FSTV0910_GPIO20_CONFIG 0xf154107e #define FSTV0910_GPIO20_XOR 0xf1540001 /* GPIO21CFG */ #define RSTV0910_GPIO21CFG 0xf155 -#define FSTV0910_GPIO21_OPD 0xf1550080 -#define FSTV0910_GPIO21_CONFIG 0xf155007e +#define FSTV0910_GPIO21_OPD 0xf1557080 +#define FSTV0910_GPIO21_CONFIG 0xf155107e #define FSTV0910_GPIO21_XOR 0xf1550001 /* GPIO22CFG */ #define RSTV0910_GPIO22CFG 0xf156 -#define FSTV0910_GPIO22_OPD 0xf1560080 -#define FSTV0910_GPIO22_CONFIG 0xf156007e +#define FSTV0910_GPIO22_OPD 0xf1567080 +#define FSTV0910_GPIO22_CONFIG 0xf156107e #define FSTV0910_GPIO22_XOR 0xf1560001 /* STRSTATUS1 */ #define RSTV0910_STRSTATUS1 0xf16a -#define FSTV0910_STRSTATUS_SEL2 0xf16a00f0 +#define FSTV0910_STRSTATUS_SEL2 0xf16a40f0 #define FSTV0910_STRSTATUS_SEL1 0xf16a000f /* STRSTATUS2 */ #define RSTV0910_STRSTATUS2 0xf16b -#define FSTV0910_STRSTATUS_SEL4 0xf16b00f0 +#define FSTV0910_STRSTATUS_SEL4 0xf16b40f0 #define FSTV0910_STRSTATUS_SEL3 0xf16b000f /* STRSTATUS3 */ #define RSTV0910_STRSTATUS3 0xf16c -#define FSTV0910_STRSTATUS_SEL6 0xf16c00f0 +#define FSTV0910_STRSTATUS_SEL6 0xf16c40f0 #define FSTV0910_STRSTATUS_SEL5 0xf16c000f /* FSKTFC2 */ #define RSTV0910_FSKTFC2 0xf170 -#define FSTV0910_FSKT_KMOD 0xf17000fc +#define FSTV0910_FSKT_KMOD 0xf17020fc #define FSTV0910_FSKT_CAR2 0xf1700003 /* FSKTFC1 */ @@ -330,17 +330,17 @@ /* FSKTCTRL */ #define RSTV0910_FSKTCTRL 0xf175 -#define FSTV0910_FSKT_PINSEL 0xf1750080 -#define FSTV0910_FSKT_EN_SGN 0xf1750040 -#define FSTV0910_FSKT_MOD_SGN 0xf1750020 -#define FSTV0910_FSKT_MOD_EN 0xf175001c +#define FSTV0910_FSKT_PINSEL 0xf1757080 +#define FSTV0910_FSKT_EN_SGN 0xf1756040 +#define FSTV0910_FSKT_MOD_SGN 0xf1755020 +#define FSTV0910_FSKT_MOD_EN 0xf175201c #define FSTV0910_FSKT_DACMODE 0xf1750003 /* FSKRFC2 */ #define RSTV0910_FSKRFC2 0xf176 -#define FSTV0910_FSKR_DETSGN 0xf1760040 -#define FSTV0910_FSKR_OUTSGN 0xf1760020 -#define FSTV0910_FSKR_KAGC 0xf176001c +#define FSTV0910_FSKR_DETSGN 0xf1766040 +#define FSTV0910_FSKR_OUTSGN 0xf1765020 +#define FSTV0910_FSKR_KAGC 0xf176201c #define FSTV0910_FSKR_CAR2 0xf1760003 /* FSKRFC1 */ @@ -353,17 +353,17 @@ /* FSKRK1 */ #define RSTV0910_FSKRK1 0xf179 -#define FSTV0910_FSKR_K1_EXP 0xf17900e0 +#define FSTV0910_FSKR_K1_EXP 0xf17950e0 #define FSTV0910_FSKR_K1_MANT 0xf179001f /* FSKRK2 */ #define RSTV0910_FSKRK2 0xf17a -#define FSTV0910_FSKR_K2_EXP 0xf17a00e0 +#define FSTV0910_FSKR_K2_EXP 0xf17a50e0 #define FSTV0910_FSKR_K2_MANT 0xf17a001f /* FSKRAGCR */ #define RSTV0910_FSKRAGCR 0xf17b -#define FSTV0910_FSKR_OUTCTL 0xf17b00c0 +#define FSTV0910_FSKR_OUTCTL 0xf17b60c0 #define FSTV0910_FSKR_AGC_REF 0xf17b003f /* FSKRAGC */ @@ -372,12 +372,12 @@ /* FSKRALPHA */ #define RSTV0910_FSKRALPHA 0xf17d -#define FSTV0910_FSKR_ALPHA_EXP 0xf17d001c +#define FSTV0910_FSKR_ALPHA_EXP 0xf17d201c #define FSTV0910_FSKR_ALPHA_M 0xf17d0003 /* FSKRPLTH1 */ #define RSTV0910_FSKRPLTH1 0xf17e -#define FSTV0910_FSKR_BETA 0xf17e00f0 +#define FSTV0910_FSKR_BETA 0xf17e40f0 #define FSTV0910_FSKR_PLL_TRESH1 0xf17e000f /* FSKRPLTH0 */ @@ -386,8 +386,8 @@ /* FSKRDF1 */ #define RSTV0910_FSKRDF1 0xf180 -#define FSTV0910_FSKR_OUT 0xf1800080 -#define FSTV0910_FSKR_STATE 0xf1800060 +#define FSTV0910_FSKR_OUT 0xf1807080 +#define FSTV0910_FSKR_STATE 0xf1805060 #define FSTV0910_FSKR_DELTAF1 0xf180001f /* FSKRDF0 */ @@ -404,7 +404,7 @@ /* FSKRDET1 */ #define RSTV0910_FSKRDET1 0xf184 -#define FSTV0910_FSKR_DETECT 0xf1840080 +#define FSTV0910_FSKR_DETECT 0xf1847080 #define FSTV0910_FSKR_CARDET_ACCU1 0xf184000f /* FSKRDET0 */ @@ -413,7 +413,7 @@ /* FSKRDTH1 */ #define RSTV0910_FSKRDTH1 0xf186 -#define FSTV0910_FSKR_CARLOSS_THRESH1 0xf18600f0 +#define FSTV0910_FSKR_CARLOSS_THRESH1 0xf18640f0 #define FSTV0910_FSKR_CARDET_THRESH1 0xf186000f /* FSKRDTH0 */ @@ -426,7 +426,7 @@ /* NCOARSE */ #define RSTV0910_NCOARSE 0xf1b3 -#define FSTV0910_CP 0xf1b300f8 +#define FSTV0910_CP 0xf1b330f8 #define FSTV0910_IDF 0xf1b30007 /* NCOARSE1 */ @@ -439,14 +439,14 @@ /* SYNTCTRL */ #define RSTV0910_SYNTCTRL 0xf1b6 -#define FSTV0910_STANDBY 0xf1b60080 -#define FSTV0910_BYPASSPLLCORE 0xf1b60040 -#define FSTV0910_STOP_PLL 0xf1b60008 -#define FSTV0910_OSCI_E 0xf1b60002 +#define FSTV0910_STANDBY 0xf1b67080 +#define FSTV0910_BYPASSPLLCORE 0xf1b66040 +#define FSTV0910_STOP_PLL 0xf1b63008 +#define FSTV0910_OSCI_E 0xf1b61002 /* FILTCTRL */ #define RSTV0910_FILTCTRL 0xf1b7 -#define FSTV0910_INV_CLKFSK 0xf1b70002 +#define FSTV0910_INV_CLKFSK 0xf1b71002 #define FSTV0910_BYPASS_APPLI 0xf1b70001 /* PLLSTAT */ @@ -455,48 +455,48 @@ /* STOPCLK1 */ #define RSTV0910_STOPCLK1 0xf1c2 -#define FSTV0910_INV_CLKADCI2 0xf1c20004 +#define FSTV0910_INV_CLKADCI2 0xf1c22004 #define FSTV0910_INV_CLKADCI1 0xf1c20001 /* STOPCLK2 */ #define RSTV0910_STOPCLK2 0xf1c3 -#define FSTV0910_STOP_DVBS2FEC2 0xf1c30020 -#define FSTV0910_STOP_DVBS2FEC 0xf1c30010 -#define FSTV0910_STOP_DVBS1FEC2 0xf1c30008 -#define FSTV0910_STOP_DVBS1FEC 0xf1c30004 -#define FSTV0910_STOP_DEMOD2 0xf1c30002 +#define FSTV0910_STOP_DVBS2FEC2 0xf1c35020 +#define FSTV0910_STOP_DVBS2FEC 0xf1c34010 +#define FSTV0910_STOP_DVBS1FEC2 0xf1c33008 +#define FSTV0910_STOP_DVBS1FEC 0xf1c32004 +#define FSTV0910_STOP_DEMOD2 0xf1c31002 #define FSTV0910_STOP_DEMOD 0xf1c30001 /* PREGCTL */ #define RSTV0910_PREGCTL 0xf1c8 -#define FSTV0910_REG3V3TO2V5_POFF 0xf1c80080 +#define FSTV0910_REG3V3TO2V5_POFF 0xf1c87080 /* TSTTNR0 */ #define RSTV0910_TSTTNR0 0xf1df -#define FSTV0910_FSK_PON 0xf1df0004 +#define FSTV0910_FSK_PON 0xf1df2004 /* TSTTNR1 */ #define RSTV0910_TSTTNR1 0xf1e0 -#define FSTV0910_ADC1_PON 0xf1e00002 +#define FSTV0910_ADC1_PON 0xf1e01002 /* TSTTNR2 */ #define RSTV0910_TSTTNR2 0xf1e1 -#define FSTV0910_I2C_DISEQC_PON 0xf1e10020 +#define FSTV0910_I2C_DISEQC_PON 0xf1e15020 #define FSTV0910_DISEQC_CLKDIV 0xf1e1000f /* TSTTNR3 */ #define RSTV0910_TSTTNR3 0xf1e2 -#define FSTV0910_ADC2_PON 0xf1e20002 +#define FSTV0910_ADC2_PON 0xf1e21002 /* P2_IQCONST */ #define RSTV0910_P2_IQCONST 0xf200 -#define FSTV0910_P2_CONSTEL_SELECT 0xf2000060 +#define FSTV0910_P2_CONSTEL_SELECT 0xf2005060 #define FSTV0910_P2_IQSYMB_SEL 0xf200001f /* P2_NOSCFG */ #define RSTV0910_P2_NOSCFG 0xf201 -#define FSTV0910_P2_DUMMYPL_NOSDATA 0xf2010020 -#define FSTV0910_P2_NOSPLH_BETA 0xf2010018 +#define FSTV0910_P2_DUMMYPL_NOSDATA 0xf2015020 +#define FSTV0910_P2_NOSPLH_BETA 0xf2013018 #define FSTV0910_P2_NOSDATA_BETA 0xf2010007 /* P2_ISYMB */ @@ -509,18 +509,18 @@ /* P2_AGC1CFG */ #define RSTV0910_P2_AGC1CFG 0xf204 -#define FSTV0910_P2_DC_FROZEN 0xf2040080 -#define FSTV0910_P2_DC_CORRECT 0xf2040040 -#define FSTV0910_P2_AMM_FROZEN 0xf2040020 -#define FSTV0910_P2_AMM_CORRECT 0xf2040010 -#define FSTV0910_P2_QUAD_FROZEN 0xf2040008 -#define FSTV0910_P2_QUAD_CORRECT 0xf2040004 +#define FSTV0910_P2_DC_FROZEN 0xf2047080 +#define FSTV0910_P2_DC_CORRECT 0xf2046040 +#define FSTV0910_P2_AMM_FROZEN 0xf2045020 +#define FSTV0910_P2_AMM_CORRECT 0xf2044010 +#define FSTV0910_P2_QUAD_FROZEN 0xf2043008 +#define FSTV0910_P2_QUAD_CORRECT 0xf2042004 /* P2_AGC1CN */ #define RSTV0910_P2_AGC1CN 0xf206 -#define FSTV0910_P2_AGC1_LOCKED 0xf2060080 -#define FSTV0910_P2_AGC1_MINPOWER 0xf2060010 -#define FSTV0910_P2_AGCOUT_FAST 0xf2060008 +#define FSTV0910_P2_AGC1_LOCKED 0xf2067080 +#define FSTV0910_P2_AGC1_MINPOWER 0xf2064010 +#define FSTV0910_P2_AGCOUT_FAST 0xf2063008 #define FSTV0910_P2_AGCIQ_BETA 0xf2060007 /* P2_AGC1REF */ @@ -561,50 +561,50 @@ /* P2_DEMOD */ #define RSTV0910_P2_DEMOD 0xf210 -#define FSTV0910_P2_MANUALS2_ROLLOFF 0xf2100080 -#define FSTV0910_P2_SPECINV_CONTROL 0xf2100030 -#define FSTV0910_P2_MANUALSX_ROLLOFF 0xf2100004 +#define FSTV0910_P2_MANUALS2_ROLLOFF 0xf2107080 +#define FSTV0910_P2_SPECINV_CONTROL 0xf2104030 +#define FSTV0910_P2_MANUALSX_ROLLOFF 0xf2102004 #define FSTV0910_P2_ROLLOFF_CONTROL 0xf2100003 /* P2_DMDMODCOD */ #define RSTV0910_P2_DMDMODCOD 0xf211 -#define FSTV0910_P2_MANUAL_MODCOD 0xf2110080 -#define FSTV0910_P2_DEMOD_MODCOD 0xf211007c +#define FSTV0910_P2_MANUAL_MODCOD 0xf2117080 +#define FSTV0910_P2_DEMOD_MODCOD 0xf211207c #define FSTV0910_P2_DEMOD_TYPE 0xf2110003 /* P2_DSTATUS */ #define RSTV0910_P2_DSTATUS 0xf212 -#define FSTV0910_P2_CAR_LOCK 0xf2120080 -#define FSTV0910_P2_TMGLOCK_QUALITY 0xf2120060 -#define FSTV0910_P2_LOCK_DEFINITIF 0xf2120008 +#define FSTV0910_P2_CAR_LOCK 0xf2127080 +#define FSTV0910_P2_TMGLOCK_QUALITY 0xf2125060 +#define FSTV0910_P2_LOCK_DEFINITIF 0xf2123008 #define FSTV0910_P2_OVADC_DETECT 0xf2120001 /* P2_DSTATUS2 */ #define RSTV0910_P2_DSTATUS2 0xf213 -#define FSTV0910_P2_DEMOD_DELOCK 0xf2130080 -#define FSTV0910_P2_MODCODRQ_SYNCTAG 0xf2130020 -#define FSTV0910_P2_POLYPH_SATEVENT 0xf2130010 -#define FSTV0910_P2_AGC1_NOSIGNALACK 0xf2130008 -#define FSTV0910_P2_AGC2_OVERFLOW 0xf2130004 -#define FSTV0910_P2_CFR_OVERFLOW 0xf2130002 +#define FSTV0910_P2_DEMOD_DELOCK 0xf2137080 +#define FSTV0910_P2_MODCODRQ_SYNCTAG 0xf2135020 +#define FSTV0910_P2_POLYPH_SATEVENT 0xf2134010 +#define FSTV0910_P2_AGC1_NOSIGNALACK 0xf2133008 +#define FSTV0910_P2_AGC2_OVERFLOW 0xf2132004 +#define FSTV0910_P2_CFR_OVERFLOW 0xf2131002 #define FSTV0910_P2_GAMMA_OVERUNDER 0xf2130001 /* P2_DMDCFGMD */ #define RSTV0910_P2_DMDCFGMD 0xf214 -#define FSTV0910_P2_DVBS2_ENABLE 0xf2140080 -#define FSTV0910_P2_DVBS1_ENABLE 0xf2140040 -#define FSTV0910_P2_SCAN_ENABLE 0xf2140010 -#define FSTV0910_P2_CFR_AUTOSCAN 0xf2140008 +#define FSTV0910_P2_DVBS2_ENABLE 0xf2147080 +#define FSTV0910_P2_DVBS1_ENABLE 0xf2146040 +#define FSTV0910_P2_SCAN_ENABLE 0xf2144010 +#define FSTV0910_P2_CFR_AUTOSCAN 0xf2143008 #define FSTV0910_P2_TUN_RNG 0xf2140003 /* P2_DMDCFG2 */ #define RSTV0910_P2_DMDCFG2 0xf215 -#define FSTV0910_P2_S1S2_SEQUENTIAL 0xf2150040 -#define FSTV0910_P2_INFINITE_RELOCK 0xf2150010 +#define FSTV0910_P2_S1S2_SEQUENTIAL 0xf2156040 +#define FSTV0910_P2_INFINITE_RELOCK 0xf2154010 /* P2_DMDISTATE */ #define RSTV0910_P2_DMDISTATE 0xf216 -#define FSTV0910_P2_I2C_NORESETDMODE 0xf2160080 +#define FSTV0910_P2_I2C_NORESETDMODE 0xf2167080 #define FSTV0910_P2_I2C_DEMOD_MODE 0xf216001f /* P2_DMDT0M */ @@ -613,27 +613,27 @@ /* P2_DMDSTATE */ #define RSTV0910_P2_DMDSTATE 0xf21b -#define FSTV0910_P2_HEADER_MODE 0xf21b0060 +#define FSTV0910_P2_HEADER_MODE 0xf21b5060 /* P2_DMDFLYW */ #define RSTV0910_P2_DMDFLYW 0xf21c -#define FSTV0910_P2_I2C_IRQVAL 0xf21c00f0 +#define FSTV0910_P2_I2C_IRQVAL 0xf21c40f0 #define FSTV0910_P2_FLYWHEEL_CPT 0xf21c000f /* P2_DSTATUS3 */ #define RSTV0910_P2_DSTATUS3 0xf21d -#define FSTV0910_P2_CFR_ZIGZAG 0xf21d0080 -#define FSTV0910_P2_DEMOD_CFGMODE 0xf21d0060 -#define FSTV0910_P2_GAMMA_LOWBAUDRATE 0xf21d0010 +#define FSTV0910_P2_CFR_ZIGZAG 0xf21d7080 +#define FSTV0910_P2_DEMOD_CFGMODE 0xf21d5060 +#define FSTV0910_P2_GAMMA_LOWBAUDRATE 0xf21d4010 /* P2_DMDCFG3 */ #define RSTV0910_P2_DMDCFG3 0xf21e -#define FSTV0910_P2_NOSTOP_FIFOFULL 0xf21e0008 +#define FSTV0910_P2_NOSTOP_FIFOFULL 0xf21e3008 /* P2_DMDCFG4 */ #define RSTV0910_P2_DMDCFG4 0xf21f -#define FSTV0910_P2_DIS_VITLOCK 0xf21f0080 -#define FSTV0910_P2_DIS_CLKENABLE 0xf21f0004 +#define FSTV0910_P2_DIS_VITLOCK 0xf21f7080 +#define FSTV0910_P2_DIS_CLKENABLE 0xf21f2004 /* P2_CORRELMANT */ #define RSTV0910_P2_CORRELMANT 0xf220 @@ -645,13 +645,13 @@ /* P2_CORRELEXP */ #define RSTV0910_P2_CORRELEXP 0xf222 -#define FSTV0910_P2_CORREL_ABSEXP 0xf22200f0 +#define FSTV0910_P2_CORREL_ABSEXP 0xf22240f0 #define FSTV0910_P2_CORREL_EXP 0xf222000f /* P2_PLHMODCOD */ #define RSTV0910_P2_PLHMODCOD 0xf224 -#define FSTV0910_P2_SPECINV_DEMOD 0xf2240080 -#define FSTV0910_P2_PLH_MODCOD 0xf224007c +#define FSTV0910_P2_SPECINV_DEMOD 0xf2247080 +#define FSTV0910_P2_PLH_MODCOD 0xf224207c #define FSTV0910_P2_PLH_TYPE 0xf2240003 /* P2_DMDREG */ @@ -660,19 +660,19 @@ /* P2_AGCNADJ */ #define RSTV0910_P2_AGCNADJ 0xf226 -#define FSTV0910_P2_RADJOFF_AGC2 0xf2260080 -#define FSTV0910_P2_RADJOFF_AGC1 0xf2260040 +#define FSTV0910_P2_RADJOFF_AGC2 0xf2267080 +#define FSTV0910_P2_RADJOFF_AGC1 0xf2266040 #define FSTV0910_P2_AGC_NADJ 0xf226013f /* P2_AGCKS */ #define RSTV0910_P2_AGCKS 0xf227 -#define FSTV0910_P2_RSADJ_MANUALCFG 0xf2270080 -#define FSTV0910_P2_RSADJ_CCMMODE 0xf2270040 +#define FSTV0910_P2_RSADJ_MANUALCFG 0xf2277080 +#define FSTV0910_P2_RSADJ_CCMMODE 0xf2276040 #define FSTV0910_P2_RADJ_SPSK 0xf227013f /* P2_AGCKQ */ #define RSTV0910_P2_AGCKQ 0xf228 -#define FSTV0910_P2_RADJON_DVBS1 0xf2280040 +#define FSTV0910_P2_RADJON_DVBS1 0xf2286040 #define FSTV0910_P2_RADJ_QPSK 0xf228013f /* P2_AGCK8 */ @@ -681,20 +681,20 @@ /* P2_AGCK16 */ #define RSTV0910_P2_AGCK16 0xf22a -#define FSTV0910_P2_R2ADJOFF_16APSK 0xf22a0040 -#define FSTV0910_P2_R1ADJOFF_16APSK 0xf22a0020 +#define FSTV0910_P2_R2ADJOFF_16APSK 0xf22a6040 +#define FSTV0910_P2_R1ADJOFF_16APSK 0xf22a5020 #define FSTV0910_P2_RADJ_16APSK 0xf22a011f /* P2_AGCK32 */ #define RSTV0910_P2_AGCK32 0xf22b -#define FSTV0910_P2_R3ADJOFF_32APSK 0xf22b0080 -#define FSTV0910_P2_R2ADJOFF_32APSK 0xf22b0040 -#define FSTV0910_P2_R1ADJOFF_32APSK 0xf22b0020 +#define FSTV0910_P2_R3ADJOFF_32APSK 0xf22b7080 +#define FSTV0910_P2_R2ADJOFF_32APSK 0xf22b6040 +#define FSTV0910_P2_R1ADJOFF_32APSK 0xf22b5020 #define FSTV0910_P2_RADJ_32APSK 0xf22b011f /* P2_AGC2O */ #define RSTV0910_P2_AGC2O 0xf22c -#define FSTV0910_P2_CSTENV_MODE 0xf22c00c0 +#define FSTV0910_P2_CSTENV_MODE 0xf22c60c0 #define FSTV0910_P2_AGC2_COEF 0xf22c0007 /* P2_AGC2REF */ @@ -743,32 +743,32 @@ /* P2_CARCFG */ #define RSTV0910_P2_CARCFG 0xf238 -#define FSTV0910_P2_ROTAON 0xf2380004 +#define FSTV0910_P2_ROTAON 0xf2382004 #define FSTV0910_P2_PH_DET_ALGO 0xf2380003 /* P2_ACLC */ #define RSTV0910_P2_ACLC 0xf239 -#define FSTV0910_P2_CAR_ALPHA_MANT 0xf2390030 +#define FSTV0910_P2_CAR_ALPHA_MANT 0xf2394030 #define FSTV0910_P2_CAR_ALPHA_EXP 0xf239000f /* P2_BCLC */ #define RSTV0910_P2_BCLC 0xf23a -#define FSTV0910_P2_CAR_BETA_MANT 0xf23a0030 +#define FSTV0910_P2_CAR_BETA_MANT 0xf23a4030 #define FSTV0910_P2_CAR_BETA_EXP 0xf23a000f /* P2_ACLCS2 */ #define RSTV0910_P2_ACLCS2 0xf23b -#define FSTV0910_P2_CARS2_APLHA_MANTISSE 0xf23b0030 +#define FSTV0910_P2_CARS2_APLHA_MANTISSE 0xf23b4030 #define FSTV0910_P2_CARS2_ALPHA_EXP 0xf23b000f /* P2_BCLCS2 */ #define RSTV0910_P2_BCLCS2 0xf23c -#define FSTV0910_P2_CARS2_BETA_MANTISSE 0xf23c0030 +#define FSTV0910_P2_CARS2_BETA_MANTISSE 0xf23c4030 #define FSTV0910_P2_CARS2_BETA_EXP 0xf23c000f /* P2_CARFREQ */ #define RSTV0910_P2_CARFREQ 0xf23d -#define FSTV0910_P2_KC_COARSE_EXP 0xf23d00f0 +#define FSTV0910_P2_KC_COARSE_EXP 0xf23d40f0 #define FSTV0910_P2_BETA_FREQ 0xf23d000f /* P2_CARHDR */ @@ -821,7 +821,7 @@ /* P2_CFRINC1 */ #define RSTV0910_P2_CFRINC1 0xf24a -#define FSTV0910_P2_MANUAL_CFRINC 0xf24a0080 +#define FSTV0910_P2_MANUAL_CFRINC 0xf24a7080 #define FSTV0910_P2_CFR_INC1 0xf24a003f /* P2_CFRINC0 */ @@ -846,18 +846,18 @@ /* P2_TMGCFG */ #define RSTV0910_P2_TMGCFG 0xf250 -#define FSTV0910_P2_TMGLOCK_BETA 0xf25000c0 -#define FSTV0910_P2_DO_TIMING_CORR 0xf2500010 +#define FSTV0910_P2_TMGLOCK_BETA 0xf25060c0 +#define FSTV0910_P2_DO_TIMING_CORR 0xf2504010 #define FSTV0910_P2_TMG_MINFREQ 0xf2500003 /* P2_RTC */ #define RSTV0910_P2_RTC 0xf251 -#define FSTV0910_P2_TMGALPHA_EXP 0xf25100f0 +#define FSTV0910_P2_TMGALPHA_EXP 0xf25140f0 #define FSTV0910_P2_TMGBETA_EXP 0xf251000f /* P2_RTCS2 */ #define RSTV0910_P2_RTCS2 0xf252 -#define FSTV0910_P2_TMGALPHAS2_EXP 0xf25200f0 +#define FSTV0910_P2_TMGALPHAS2_EXP 0xf25240f0 #define FSTV0910_P2_TMGBETAS2_EXP 0xf252000f /* P2_TMGTHRISE */ @@ -878,7 +878,7 @@ /* P2_KTTMG */ #define RSTV0910_P2_KTTMG 0xf257 -#define FSTV0910_P2_KT_TMG_EXP 0xf25700f0 +#define FSTV0910_P2_KT_TMG_EXP 0xf25740f0 /* P2_KREFTMG */ #define RSTV0910_P2_KREFTMG 0xf258 @@ -886,12 +886,12 @@ /* P2_SFRSTEP */ #define RSTV0910_P2_SFRSTEP 0xf259 -#define FSTV0910_P2_SFR_SCANSTEP 0xf25900f0 +#define FSTV0910_P2_SFR_SCANSTEP 0xf25940f0 #define FSTV0910_P2_SFR_CENTERSTEP 0xf259000f /* P2_TMGCFG2 */ #define RSTV0910_P2_TMGCFG2 0xf25a -#define FSTV0910_P2_DIS_AUTOSAMP 0xf25a0008 +#define FSTV0910_P2_DIS_AUTOSAMP 0xf25a3008 #define FSTV0910_P2_SFRRATIO_FINE 0xf25a0001 /* P2_KREFTMG2 */ @@ -900,9 +900,9 @@ /* P2_TMGCFG3 */ #define RSTV0910_P2_TMGCFG3 0xf25d -#define FSTV0910_P2_CONT_TMGCENTER 0xf25d0008 -#define FSTV0910_P2_AUTO_GUP 0xf25d0004 -#define FSTV0910_P2_AUTO_GLOW 0xf25d0002 +#define FSTV0910_P2_CONT_TMGCENTER 0xf25d3008 +#define FSTV0910_P2_AUTO_GUP 0xf25d2004 +#define FSTV0910_P2_AUTO_GLOW 0xf25d1002 /* P2_SFRINIT1 */ #define RSTV0910_P2_SFRINIT1 0xf25e @@ -966,11 +966,11 @@ /* P2_TMGOBS */ #define RSTV0910_P2_TMGOBS 0xf26d -#define FSTV0910_P2_ROLLOFF_STATUS 0xf26d00c0 +#define FSTV0910_P2_ROLLOFF_STATUS 0xf26d60c0 /* P2_EQUALCFG */ #define RSTV0910_P2_EQUALCFG 0xf26f -#define FSTV0910_P2_EQUAL_ON 0xf26f0040 +#define FSTV0910_P2_EQUAL_ON 0xf26f6040 #define FSTV0910_P2_MU_EQUALDFE 0xf26f0007 /* P2_EQUAI1 */ @@ -1095,33 +1095,33 @@ /* P2_NOSCFGF1 */ #define RSTV0910_P2_NOSCFGF1 0xf28e -#define FSTV0910_P2_LOWNOISE_MESURE 0xf28e0080 -#define FSTV0910_P2_NOS_DELFRAME 0xf28e0040 -#define FSTV0910_P2_NOSDATA_MODE 0xf28e0030 -#define FSTV0910_P2_FRAMESEL_TYPESEL 0xf28e000c +#define FSTV0910_P2_LOWNOISE_MESURE 0xf28e7080 +#define FSTV0910_P2_NOS_DELFRAME 0xf28e6040 +#define FSTV0910_P2_NOSDATA_MODE 0xf28e4030 +#define FSTV0910_P2_FRAMESEL_TYPESEL 0xf28e200c #define FSTV0910_P2_FRAMESEL_TYPE 0xf28e0003 /* P2_NOSCFGF2 */ #define RSTV0910_P2_NOSCFGF2 0xf28f -#define FSTV0910_P2_DIS_NOSPILOTS 0xf28f0080 -#define FSTV0910_P2_FRAMESEL_MODCODSEL 0xf28f0060 +#define FSTV0910_P2_DIS_NOSPILOTS 0xf28f7080 +#define FSTV0910_P2_FRAMESEL_MODCODSEL 0xf28f5060 #define FSTV0910_P2_FRAMESEL_MODCOD 0xf28f001f /* P2_CAR2CFG */ #define RSTV0910_P2_CAR2CFG 0xf290 -#define FSTV0910_P2_ROTA2ON 0xf2900004 +#define FSTV0910_P2_ROTA2ON 0xf2902004 #define FSTV0910_P2_PH_DET_ALGO2 0xf2900003 /* P2_CFR2CFR1 */ #define RSTV0910_P2_CFR2CFR1 0xf291 -#define FSTV0910_P2_EN_S2CAR2CENTER 0xf2910020 +#define FSTV0910_P2_EN_S2CAR2CENTER 0xf2915020 #define FSTV0910_P2_CFR2TOCFR1_BETA 0xf2910007 /* P2_CAR3CFG */ #define RSTV0910_P2_CAR3CFG 0xf292 -#define FSTV0910_P2_CARRIER23_MODE 0xf29200c0 -#define FSTV0910_P2_CAR3INTERM_DVBS1 0xf2920020 -#define FSTV0910_P2_ABAMPLIF_MODE 0xf2920018 +#define FSTV0910_P2_CARRIER23_MODE 0xf29260c0 +#define FSTV0910_P2_CAR3INTERM_DVBS1 0xf2925020 +#define FSTV0910_P2_ABAMPLIF_MODE 0xf2923018 #define FSTV0910_P2_CARRIER3_ALPHA3DL 0xf2920007 /* P2_CFR22 */ @@ -1138,50 +1138,50 @@ /* P2_ACLC2S2Q */ #define RSTV0910_P2_ACLC2S2Q 0xf297 -#define FSTV0910_P2_ENAB_SPSKSYMB 0xf2970080 -#define FSTV0910_P2_CAR2S2_Q_ALPH_M 0xf2970030 +#define FSTV0910_P2_ENAB_SPSKSYMB 0xf2977080 +#define FSTV0910_P2_CAR2S2_Q_ALPH_M 0xf2974030 #define FSTV0910_P2_CAR2S2_Q_ALPH_E 0xf297000f /* P2_ACLC2S28 */ #define RSTV0910_P2_ACLC2S28 0xf298 -#define FSTV0910_P2_CAR2S2_8_ALPH_M 0xf2980030 +#define FSTV0910_P2_CAR2S2_8_ALPH_M 0xf2984030 #define FSTV0910_P2_CAR2S2_8_ALPH_E 0xf298000f /* P2_ACLC2S216A */ #define RSTV0910_P2_ACLC2S216A 0xf299 -#define FSTV0910_P2_CAR2S2_16A_ALPH_M 0xf2990030 +#define FSTV0910_P2_CAR2S2_16A_ALPH_M 0xf2994030 #define FSTV0910_P2_CAR2S2_16A_ALPH_E 0xf299000f /* P2_ACLC2S232A */ #define RSTV0910_P2_ACLC2S232A 0xf29a -#define FSTV0910_P2_CAR2S2_32A_ALPH_M 0xf29a0030 +#define FSTV0910_P2_CAR2S2_32A_ALPH_M 0xf29a4030 #define FSTV0910_P2_CAR2S2_32A_ALPH_E 0xf29a000f /* P2_BCLC2S2Q */ #define RSTV0910_P2_BCLC2S2Q 0xf29c -#define FSTV0910_P2_CAR2S2_Q_BETA_M 0xf29c0030 +#define FSTV0910_P2_CAR2S2_Q_BETA_M 0xf29c4030 #define FSTV0910_P2_CAR2S2_Q_BETA_E 0xf29c000f /* P2_BCLC2S28 */ #define RSTV0910_P2_BCLC2S28 0xf29d -#define FSTV0910_P2_CAR2S2_8_BETA_M 0xf29d0030 +#define FSTV0910_P2_CAR2S2_8_BETA_M 0xf29d4030 #define FSTV0910_P2_CAR2S2_8_BETA_E 0xf29d000f /* P2_BCLC2S216A */ #define RSTV0910_P2_BCLC2S216A 0xf29e -#define FSTV0910_P2_DVBS2S216A_NIP 0xf29e0080 -#define FSTV0910_P2_CAR2S2_16A_BETA_M 0xf29e0030 +#define FSTV0910_P2_DVBS2S216A_NIP 0xf29e7080 +#define FSTV0910_P2_CAR2S2_16A_BETA_M 0xf29e4030 #define FSTV0910_P2_CAR2S2_16A_BETA_E 0xf29e000f /* P2_BCLC2S232A */ #define RSTV0910_P2_BCLC2S232A 0xf29f -#define FSTV0910_P2_DVBS2S232A_NIP 0xf29f0080 -#define FSTV0910_P2_CAR2S2_32A_BETA_M 0xf29f0030 +#define FSTV0910_P2_DVBS2S232A_NIP 0xf29f7080 +#define FSTV0910_P2_CAR2S2_32A_BETA_M 0xf29f4030 #define FSTV0910_P2_CAR2S2_32A_BETA_E 0xf29f000f /* P2_PLROOT2 */ #define RSTV0910_P2_PLROOT2 0xf2ac -#define FSTV0910_P2_PLSCRAMB_MODE 0xf2ac000c +#define FSTV0910_P2_PLSCRAMB_MODE 0xf2ac200c #define FSTV0910_P2_PLSCRAMB_ROOT2 0xf2ac0003 /* P2_PLROOT1 */ @@ -1198,100 +1198,100 @@ /* P2_MODCODLST1 */ #define RSTV0910_P2_MODCODLST1 0xf2b1 -#define FSTV0910_P2_SYMBRATE_FILTER 0xf2b10008 -#define FSTV0910_P2_NRESET_MODCODLST 0xf2b10004 +#define FSTV0910_P2_SYMBRATE_FILTER 0xf2b13008 +#define FSTV0910_P2_NRESET_MODCODLST 0xf2b12004 #define FSTV0910_P2_DIS_32PSK_9_10 0xf2b10003 /* P2_MODCODLST2 */ #define RSTV0910_P2_MODCODLST2 0xf2b2 -#define FSTV0910_P2_DIS_32PSK_8_9 0xf2b200f0 +#define FSTV0910_P2_DIS_32PSK_8_9 0xf2b240f0 #define FSTV0910_P2_DIS_32PSK_5_6 0xf2b2000f /* P2_MODCODLST3 */ #define RSTV0910_P2_MODCODLST3 0xf2b3 -#define FSTV0910_P2_DIS_32PSK_4_5 0xf2b300f0 +#define FSTV0910_P2_DIS_32PSK_4_5 0xf2b340f0 #define FSTV0910_P2_DIS_32PSK_3_4 0xf2b3000f /* P2_MODCODLST4 */ #define RSTV0910_P2_MODCODLST4 0xf2b4 -#define FSTV0910_P2_DUMMYPL_PILOT 0xf2b40080 -#define FSTV0910_P2_DUMMYPL_NOPILOT 0xf2b40040 -#define FSTV0910_P2_DIS_16PSK_9_10 0xf2b40030 +#define FSTV0910_P2_DUMMYPL_PILOT 0xf2b47080 +#define FSTV0910_P2_DUMMYPL_NOPILOT 0xf2b46040 +#define FSTV0910_P2_DIS_16PSK_9_10 0xf2b44030 #define FSTV0910_P2_DIS_16PSK_8_9 0xf2b4000f /* P2_MODCODLST5 */ #define RSTV0910_P2_MODCODLST5 0xf2b5 -#define FSTV0910_P2_DIS_16PSK_5_6 0xf2b500f0 +#define FSTV0910_P2_DIS_16PSK_5_6 0xf2b540f0 #define FSTV0910_P2_DIS_16PSK_4_5 0xf2b5000f /* P2_MODCODLST6 */ #define RSTV0910_P2_MODCODLST6 0xf2b6 -#define FSTV0910_P2_DIS_16PSK_3_4 0xf2b600f0 +#define FSTV0910_P2_DIS_16PSK_3_4 0xf2b640f0 #define FSTV0910_P2_DIS_16PSK_2_3 0xf2b6000f /* P2_MODCODLST7 */ #define RSTV0910_P2_MODCODLST7 0xf2b7 -#define FSTV0910_P2_MODCOD_NNOSFILTER 0xf2b70080 -#define FSTV0910_P2_DIS_8PSK_9_10 0xf2b70030 +#define FSTV0910_P2_MODCOD_NNOSFILTER 0xf2b77080 +#define FSTV0910_P2_DIS_8PSK_9_10 0xf2b74030 #define FSTV0910_P2_DIS_8PSK_8_9 0xf2b7000f /* P2_MODCODLST8 */ #define RSTV0910_P2_MODCODLST8 0xf2b8 -#define FSTV0910_P2_DIS_8PSK_5_6 0xf2b800f0 +#define FSTV0910_P2_DIS_8PSK_5_6 0xf2b840f0 #define FSTV0910_P2_DIS_8PSK_3_4 0xf2b8000f /* P2_MODCODLST9 */ #define RSTV0910_P2_MODCODLST9 0xf2b9 -#define FSTV0910_P2_DIS_8PSK_2_3 0xf2b900f0 +#define FSTV0910_P2_DIS_8PSK_2_3 0xf2b940f0 #define FSTV0910_P2_DIS_8PSK_3_5 0xf2b9000f /* P2_MODCODLSTA */ #define RSTV0910_P2_MODCODLSTA 0xf2ba -#define FSTV0910_P2_NOSFILTER_LIMITE 0xf2ba0080 -#define FSTV0910_P2_DIS_QPSK_9_10 0xf2ba0030 +#define FSTV0910_P2_NOSFILTER_LIMITE 0xf2ba7080 +#define FSTV0910_P2_DIS_QPSK_9_10 0xf2ba4030 #define FSTV0910_P2_DIS_QPSK_8_9 0xf2ba000f /* P2_MODCODLSTB */ #define RSTV0910_P2_MODCODLSTB 0xf2bb -#define FSTV0910_P2_DIS_QPSK_5_6 0xf2bb00f0 +#define FSTV0910_P2_DIS_QPSK_5_6 0xf2bb40f0 #define FSTV0910_P2_DIS_QPSK_4_5 0xf2bb000f /* P2_MODCODLSTC */ #define RSTV0910_P2_MODCODLSTC 0xf2bc -#define FSTV0910_P2_DIS_QPSK_3_4 0xf2bc00f0 +#define FSTV0910_P2_DIS_QPSK_3_4 0xf2bc40f0 #define FSTV0910_P2_DIS_QPSK_2_3 0xf2bc000f /* P2_MODCODLSTD */ #define RSTV0910_P2_MODCODLSTD 0xf2bd -#define FSTV0910_P2_DIS_QPSK_3_5 0xf2bd00f0 +#define FSTV0910_P2_DIS_QPSK_3_5 0xf2bd40f0 #define FSTV0910_P2_DIS_QPSK_1_2 0xf2bd000f /* P2_MODCODLSTE */ #define RSTV0910_P2_MODCODLSTE 0xf2be -#define FSTV0910_P2_DIS_QPSK_2_5 0xf2be00f0 +#define FSTV0910_P2_DIS_QPSK_2_5 0xf2be40f0 #define FSTV0910_P2_DIS_QPSK_1_3 0xf2be000f /* P2_MODCODLSTF */ #define RSTV0910_P2_MODCODLSTF 0xf2bf -#define FSTV0910_P2_DIS_QPSK_1_4 0xf2bf00f0 -#define FSTV0910_P2_DEMOD_INVMODLST 0xf2bf0008 -#define FSTV0910_P2_DEMODOUT_ENABLE 0xf2bf0004 -#define FSTV0910_P2_DDEMOD_NSET 0xf2bf0002 +#define FSTV0910_P2_DIS_QPSK_1_4 0xf2bf40f0 +#define FSTV0910_P2_DEMOD_INVMODLST 0xf2bf3008 +#define FSTV0910_P2_DEMODOUT_ENABLE 0xf2bf2004 +#define FSTV0910_P2_DDEMOD_NSET 0xf2bf1002 #define FSTV0910_P2_MODCOD_NSTOCK 0xf2bf0001 /* P2_GAUSSR0 */ #define RSTV0910_P2_GAUSSR0 0xf2c0 -#define FSTV0910_P2_EN_CCIMODE 0xf2c00080 +#define FSTV0910_P2_EN_CCIMODE 0xf2c07080 #define FSTV0910_P2_R0_GAUSSIEN 0xf2c0007f /* P2_CCIR0 */ #define RSTV0910_P2_CCIR0 0xf2c1 -#define FSTV0910_P2_CCIDETECT_PLHONLY 0xf2c10080 +#define FSTV0910_P2_CCIDETECT_PLHONLY 0xf2c17080 #define FSTV0910_P2_R0_CCI 0xf2c1007f /* P2_CCIQUANT */ #define RSTV0910_P2_CCIQUANT 0xf2c2 -#define FSTV0910_P2_CCI_BETA 0xf2c200e0 +#define FSTV0910_P2_CCI_BETA 0xf2c250e0 #define FSTV0910_P2_CCI_QUANT 0xf2c2001f /* P2_CCITHRES */ @@ -1304,24 +1304,24 @@ /* P2_DSTATUS4 */ #define RSTV0910_P2_DSTATUS4 0xf2c5 -#define FSTV0910_P2_RAINFADE_DETECT 0xf2c50080 -#define FSTV0910_P2_NOTHRES2_FAIL 0xf2c50040 -#define FSTV0910_P2_NOTHRES1_FAIL 0xf2c50020 -#define FSTV0910_P2_DMDPROG_ERROR 0xf2c50004 -#define FSTV0910_P2_CSTENV_DETECT 0xf2c50002 +#define FSTV0910_P2_RAINFADE_DETECT 0xf2c57080 +#define FSTV0910_P2_NOTHRES2_FAIL 0xf2c56040 +#define FSTV0910_P2_NOTHRES1_FAIL 0xf2c55020 +#define FSTV0910_P2_DMDPROG_ERROR 0xf2c52004 +#define FSTV0910_P2_CSTENV_DETECT 0xf2c51002 #define FSTV0910_P2_DETECTION_TRIAX 0xf2c50001 /* P2_DMDRESCFG */ #define RSTV0910_P2_DMDRESCFG 0xf2c6 -#define FSTV0910_P2_DMDRES_RESET 0xf2c60080 -#define FSTV0910_P2_DMDRES_STRALL 0xf2c60008 -#define FSTV0910_P2_DMDRES_NEWONLY 0xf2c60004 -#define FSTV0910_P2_DMDRES_NOSTORE 0xf2c60002 +#define FSTV0910_P2_DMDRES_RESET 0xf2c67080 +#define FSTV0910_P2_DMDRES_STRALL 0xf2c63008 +#define FSTV0910_P2_DMDRES_NEWONLY 0xf2c62004 +#define FSTV0910_P2_DMDRES_NOSTORE 0xf2c61002 /* P2_DMDRESADR */ #define RSTV0910_P2_DMDRESADR 0xf2c7 -#define FSTV0910_P2_DMDRES_VALIDCFR 0xf2c70040 -#define FSTV0910_P2_DMDRES_MEMFULL 0xf2c70030 +#define FSTV0910_P2_DMDRES_VALIDCFR 0xf2c76040 +#define FSTV0910_P2_DMDRES_MEMFULL 0xf2c74030 #define FSTV0910_P2_DMDRES_RESNBR 0xf2c7000f /* P2_DMDRESDATA7 */ @@ -1390,29 +1390,29 @@ /* P2_FFECFG */ #define RSTV0910_P2_FFECFG 0xf2d8 -#define FSTV0910_P2_EQUALFFE_ON 0xf2d80040 -#define FSTV0910_P2_EQUAL_USEDSYMB 0xf2d80030 +#define FSTV0910_P2_EQUALFFE_ON 0xf2d86040 +#define FSTV0910_P2_EQUAL_USEDSYMB 0xf2d84030 #define FSTV0910_P2_MU_EQUALFFE 0xf2d80007 /* P2_TNRCFG2 */ #define RSTV0910_P2_TNRCFG2 0xf2e1 -#define FSTV0910_P2_TUN_IQSWAP 0xf2e10080 +#define FSTV0910_P2_TUN_IQSWAP 0xf2e17080 /* P2_SMAPCOEF7 */ #define RSTV0910_P2_SMAPCOEF7 0xf300 -#define FSTV0910_P2_DIS_QSCALE 0xf3000080 +#define FSTV0910_P2_DIS_QSCALE 0xf3007080 #define FSTV0910_P2_SMAPCOEF_Q_LLR12 0xf300017f /* P2_SMAPCOEF6 */ #define RSTV0910_P2_SMAPCOEF6 0xf301 -#define FSTV0910_P2_DIS_AGC2SCALE 0xf3010080 -#define FSTV0910_P2_ADJ_8PSKLLR1 0xf3010004 -#define FSTV0910_P2_OLD_8PSKLLR1 0xf3010002 +#define FSTV0910_P2_DIS_AGC2SCALE 0xf3017080 +#define FSTV0910_P2_ADJ_8PSKLLR1 0xf3012004 +#define FSTV0910_P2_OLD_8PSKLLR1 0xf3011002 #define FSTV0910_P2_DIS_AB8PSK 0xf3010001 /* P2_SMAPCOEF5 */ #define RSTV0910_P2_SMAPCOEF5 0xf302 -#define FSTV0910_P2_DIS_8SCALE 0xf3020080 +#define FSTV0910_P2_DIS_8SCALE 0xf3027080 #define FSTV0910_P2_SMAPCOEF_8P_LLR23 0xf302017f /* P2_SMAPCOEF4 */ @@ -1425,17 +1425,17 @@ /* P2_SMAPCOEF2 */ #define RSTV0910_P2_SMAPCOEF2 0xf305 -#define FSTV0910_P2_SMAPCOEF_32APSK_R2R3 0xf30501f0 +#define FSTV0910_P2_SMAPCOEF_32APSK_R2R3 0xf30541f0 #define FSTV0910_P2_SMAPCOEF_32APSK_LLR2 0xf305010f /* P2_SMAPCOEF1 */ #define RSTV0910_P2_SMAPCOEF1 0xf306 -#define FSTV0910_P2_DIS_16SCALE 0xf3060080 +#define FSTV0910_P2_DIS_16SCALE 0xf3067080 #define FSTV0910_P2_SMAPCOEF_32_LLR34 0xf306017f /* P2_SMAPCOEF0 */ #define RSTV0910_P2_SMAPCOEF0 0xf307 -#define FSTV0910_P2_DIS_32SCALE 0xf3070080 +#define FSTV0910_P2_DIS_32SCALE 0xf3077080 #define FSTV0910_P2_SMAPCOEF_32_LLR15 0xf307017f /* P2_NOSTHRES1 */ @@ -1452,20 +1452,20 @@ /* P2_RAINFADE */ #define RSTV0910_P2_RAINFADE 0xf30c -#define FSTV0910_P2_NOSTHRES_DATAT 0xf30c0080 -#define FSTV0910_P2_RAINFADE_CNLIMIT 0xf30c0070 +#define FSTV0910_P2_NOSTHRES_DATAT 0xf30c7080 +#define FSTV0910_P2_RAINFADE_CNLIMIT 0xf30c4070 #define FSTV0910_P2_RAINFADE_TIMEOUT 0xf30c0007 /* P2_NOSRAMCFG */ #define RSTV0910_P2_NOSRAMCFG 0xf30d -#define FSTV0910_P2_NOSRAM_ACTIVATION 0xf30d0030 -#define FSTV0910_P2_NOSRAM_CNRONLY 0xf30d0008 +#define FSTV0910_P2_NOSRAM_ACTIVATION 0xf30d4030 +#define FSTV0910_P2_NOSRAM_CNRONLY 0xf30d3008 #define FSTV0910_P2_NOSRAM_LGNCNR1 0xf30d0007 /* P2_NOSRAMPOS */ #define RSTV0910_P2_NOSRAMPOS 0xf30e -#define FSTV0910_P2_NOSRAM_LGNCNR0 0xf30e00f0 -#define FSTV0910_P2_NOSRAM_VALIDE 0xf30e0004 +#define FSTV0910_P2_NOSRAM_LGNCNR0 0xf30e40f0 +#define FSTV0910_P2_NOSRAM_VALIDE 0xf30e2004 #define FSTV0910_P2_NOSRAM_CNRVAL1 0xf30e0003 /* P2_NOSRAMVAL */ @@ -1494,16 +1494,16 @@ /* P2_VITSCALE */ #define RSTV0910_P2_VITSCALE 0xf332 -#define FSTV0910_P2_NVTH_NOSRANGE 0xf3320080 -#define FSTV0910_P2_VERROR_MAXMODE 0xf3320040 -#define FSTV0910_P2_NSLOWSN_LOCKED 0xf3320008 -#define FSTV0910_P2_DIS_RSFLOCK 0xf3320002 +#define FSTV0910_P2_NVTH_NOSRANGE 0xf3327080 +#define FSTV0910_P2_VERROR_MAXMODE 0xf3326040 +#define FSTV0910_P2_NSLOWSN_LOCKED 0xf3323008 +#define FSTV0910_P2_DIS_RSFLOCK 0xf3321002 /* P2_FECM */ #define RSTV0910_P2_FECM 0xf333 -#define FSTV0910_P2_DSS_DVB 0xf3330080 -#define FSTV0910_P2_DSS_SRCH 0xf3330010 -#define FSTV0910_P2_SYNCVIT 0xf3330002 +#define FSTV0910_P2_DSS_DVB 0xf3337080 +#define FSTV0910_P2_DSS_SRCH 0xf3334010 +#define FSTV0910_P2_SYNCVIT 0xf3331002 #define FSTV0910_P2_IQINV 0xf3330001 /* P2_VTH12 */ @@ -1540,26 +1540,26 @@ /* P2_PRVIT */ #define RSTV0910_P2_PRVIT 0xf33c -#define FSTV0910_P2_DIS_VTHLOCK 0xf33c0040 -#define FSTV0910_P2_E7_8VIT 0xf33c0020 -#define FSTV0910_P2_E6_7VIT 0xf33c0010 -#define FSTV0910_P2_E5_6VIT 0xf33c0008 -#define FSTV0910_P2_E3_4VIT 0xf33c0004 -#define FSTV0910_P2_E2_3VIT 0xf33c0002 +#define FSTV0910_P2_DIS_VTHLOCK 0xf33c6040 +#define FSTV0910_P2_E7_8VIT 0xf33c5020 +#define FSTV0910_P2_E6_7VIT 0xf33c4010 +#define FSTV0910_P2_E5_6VIT 0xf33c3008 +#define FSTV0910_P2_E3_4VIT 0xf33c2004 +#define FSTV0910_P2_E2_3VIT 0xf33c1002 #define FSTV0910_P2_E1_2VIT 0xf33c0001 /* P2_VAVSRVIT */ #define RSTV0910_P2_VAVSRVIT 0xf33d -#define FSTV0910_P2_AMVIT 0xf33d0080 -#define FSTV0910_P2_FROZENVIT 0xf33d0040 -#define FSTV0910_P2_SNVIT 0xf33d0030 -#define FSTV0910_P2_TOVVIT 0xf33d000c +#define FSTV0910_P2_AMVIT 0xf33d7080 +#define FSTV0910_P2_FROZENVIT 0xf33d6040 +#define FSTV0910_P2_SNVIT 0xf33d4030 +#define FSTV0910_P2_TOVVIT 0xf33d200c #define FSTV0910_P2_HYPVIT 0xf33d0003 /* P2_VSTATUSVIT */ #define RSTV0910_P2_VSTATUSVIT 0xf33e -#define FSTV0910_P2_PRFVIT 0xf33e0010 -#define FSTV0910_P2_LOCKEDVIT 0xf33e0008 +#define FSTV0910_P2_PRFVIT 0xf33e4010 +#define FSTV0910_P2_LOCKEDVIT 0xf33e3008 /* P2_VTHINUSE */ #define RSTV0910_P2_VTHINUSE 0xf33f @@ -1599,32 +1599,32 @@ /* P2_PDELCTRL0 */ #define RSTV0910_P2_PDELCTRL0 0xf34f -#define FSTV0910_P2_ISIOBS_MODE 0xf34f0030 +#define FSTV0910_P2_ISIOBS_MODE 0xf34f4030 /* P2_PDELCTRL1 */ #define RSTV0910_P2_PDELCTRL1 0xf350 -#define FSTV0910_P2_INV_MISMASK 0xf3500080 -#define FSTV0910_P2_FILTER_EN 0xf3500020 -#define FSTV0910_P2_HYSTEN 0xf3500008 -#define FSTV0910_P2_HYSTSWRST 0xf3500004 -#define FSTV0910_P2_EN_MIS00 0xf3500002 +#define FSTV0910_P2_INV_MISMASK 0xf3507080 +#define FSTV0910_P2_FILTER_EN 0xf3505020 +#define FSTV0910_P2_HYSTEN 0xf3503008 +#define FSTV0910_P2_HYSTSWRST 0xf3502004 +#define FSTV0910_P2_EN_MIS00 0xf3501002 #define FSTV0910_P2_ALGOSWRST 0xf3500001 /* P2_PDELCTRL2 */ #define RSTV0910_P2_PDELCTRL2 0xf351 -#define FSTV0910_P2_FORCE_CONTINUOUS 0xf3510080 -#define FSTV0910_P2_RESET_UPKO_COUNT 0xf3510040 -#define FSTV0910_P2_USER_PKTDELIN_NB 0xf3510020 -#define FSTV0910_P2_FRAME_MODE 0xf3510002 +#define FSTV0910_P2_FORCE_CONTINUOUS 0xf3517080 +#define FSTV0910_P2_RESET_UPKO_COUNT 0xf3516040 +#define FSTV0910_P2_USER_PKTDELIN_NB 0xf3515020 +#define FSTV0910_P2_FRAME_MODE 0xf3511002 /* P2_HYSTTHRESH */ #define RSTV0910_P2_HYSTTHRESH 0xf354 -#define FSTV0910_P2_DELIN_LOCKTHRES 0xf35400f0 +#define FSTV0910_P2_DELIN_LOCKTHRES 0xf35440f0 #define FSTV0910_P2_DELIN_UNLOCKTHRES 0xf354000f /* P2_UPLCCST0 */ #define RSTV0910_P2_UPLCCST0 0xf358 -#define FSTV0910_P2_UPL_CST0 0xf35800f8 +#define FSTV0910_P2_UPL_CST0 0xf35830f8 #define FSTV0910_P2_UPL_MODE 0xf3580007 /* P2_ISIENTRY */ @@ -1673,16 +1673,16 @@ /* P2_PDELSTATUS1 */ #define RSTV0910_P2_PDELSTATUS1 0xf369 -#define FSTV0910_P2_PKTDELIN_DELOCK 0xf3690080 -#define FSTV0910_P2_SYNCDUPDFL_BADDFL 0xf3690040 -#define FSTV0910_P2_UNACCEPTED_STREAM 0xf3690010 -#define FSTV0910_P2_BCH_ERROR_FLAG 0xf3690008 -#define FSTV0910_P2_PKTDELIN_LOCK 0xf3690002 +#define FSTV0910_P2_PKTDELIN_DELOCK 0xf3697080 +#define FSTV0910_P2_SYNCDUPDFL_BADDFL 0xf3696040 +#define FSTV0910_P2_UNACCEPTED_STREAM 0xf3694010 +#define FSTV0910_P2_BCH_ERROR_FLAG 0xf3693008 +#define FSTV0910_P2_PKTDELIN_LOCK 0xf3691002 #define FSTV0910_P2_FIRST_LOCK 0xf3690001 /* P2_PDELSTATUS2 */ #define RSTV0910_P2_PDELSTATUS2 0xf36a -#define FSTV0910_P2_FRAME_MODCOD 0xf36a007c +#define FSTV0910_P2_FRAME_MODCOD 0xf36a207c #define FSTV0910_P2_FRAME_TYPE 0xf36a0003 /* P2_BBFCRCKO1 */ @@ -1703,92 +1703,92 @@ /* P2_PDELCTRL3 */ #define RSTV0910_P2_PDELCTRL3 0xf36f -#define FSTV0910_P2_NOFIFO_BCHERR 0xf36f0020 -#define FSTV0910_P2_PKTDELIN_DELACMERR 0xf36f0010 +#define FSTV0910_P2_NOFIFO_BCHERR 0xf36f5020 +#define FSTV0910_P2_PKTDELIN_DELACMERR 0xf36f4010 /* P2_TSSTATEM */ #define RSTV0910_P2_TSSTATEM 0xf370 -#define FSTV0910_P2_TSDIL_ON 0xf3700080 -#define FSTV0910_P2_TSRS_ON 0xf3700020 -#define FSTV0910_P2_TSDESCRAMB_ON 0xf3700010 -#define FSTV0910_P2_TSFRAME_MODE 0xf3700008 -#define FSTV0910_P2_TS_DISABLE 0xf3700004 -#define FSTV0910_P2_TSACM_MODE 0xf3700002 +#define FSTV0910_P2_TSDIL_ON 0xf3707080 +#define FSTV0910_P2_TSRS_ON 0xf3705020 +#define FSTV0910_P2_TSDESCRAMB_ON 0xf3704010 +#define FSTV0910_P2_TSFRAME_MODE 0xf3703008 +#define FSTV0910_P2_TS_DISABLE 0xf3702004 +#define FSTV0910_P2_TSACM_MODE 0xf3701002 #define FSTV0910_P2_TSOUT_NOSYNC 0xf3700001 /* P2_TSSTATEL */ #define RSTV0910_P2_TSSTATEL 0xf371 -#define FSTV0910_P2_TSNOSYNCBYTE 0xf3710080 -#define FSTV0910_P2_TSPARITY_ON 0xf3710040 -#define FSTV0910_P2_TSISSYI_ON 0xf3710008 -#define FSTV0910_P2_TSNPD_ON 0xf3710004 -#define FSTV0910_P2_TSCRC8_ON 0xf3710002 +#define FSTV0910_P2_TSNOSYNCBYTE 0xf3717080 +#define FSTV0910_P2_TSPARITY_ON 0xf3716040 +#define FSTV0910_P2_TSISSYI_ON 0xf3713008 +#define FSTV0910_P2_TSNPD_ON 0xf3712004 +#define FSTV0910_P2_TSCRC8_ON 0xf3711002 #define FSTV0910_P2_TSDSS_PACKET 0xf3710001 /* P2_TSCFGH */ #define RSTV0910_P2_TSCFGH 0xf372 -#define FSTV0910_P2_TSFIFO_DVBCI 0xf3720080 -#define FSTV0910_P2_TSFIFO_SERIAL 0xf3720040 -#define FSTV0910_P2_TSFIFO_TEIUPDATE 0xf3720020 -#define FSTV0910_P2_TSFIFO_DUTY50 0xf3720010 -#define FSTV0910_P2_TSFIFO_HSGNLOUT 0xf3720008 -#define FSTV0910_P2_TSFIFO_ERRMODE 0xf3720006 +#define FSTV0910_P2_TSFIFO_DVBCI 0xf3727080 +#define FSTV0910_P2_TSFIFO_SERIAL 0xf3726040 +#define FSTV0910_P2_TSFIFO_TEIUPDATE 0xf3725020 +#define FSTV0910_P2_TSFIFO_DUTY50 0xf3724010 +#define FSTV0910_P2_TSFIFO_HSGNLOUT 0xf3723008 +#define FSTV0910_P2_TSFIFO_ERRMODE 0xf3721006 #define FSTV0910_P2_RST_HWARE 0xf3720001 /* P2_TSCFGM */ #define RSTV0910_P2_TSCFGM 0xf373 -#define FSTV0910_P2_TSFIFO_MANSPEED 0xf37300c0 -#define FSTV0910_P2_TSFIFO_PERMDATA 0xf3730020 -#define FSTV0910_P2_TSFIFO_NONEWSGNL 0xf3730010 +#define FSTV0910_P2_TSFIFO_MANSPEED 0xf37360c0 +#define FSTV0910_P2_TSFIFO_PERMDATA 0xf3735020 +#define FSTV0910_P2_TSFIFO_NONEWSGNL 0xf3734010 #define FSTV0910_P2_TSFIFO_INVDATA 0xf3730001 /* P2_TSCFGL */ #define RSTV0910_P2_TSCFGL 0xf374 -#define FSTV0910_P2_TSFIFO_BCLKDEL1CK 0xf37400c0 -#define FSTV0910_P2_BCHERROR_MODE 0xf3740030 -#define FSTV0910_P2_TSFIFO_NSGNL2DATA 0xf3740008 -#define FSTV0910_P2_TSFIFO_EMBINDVB 0xf3740004 +#define FSTV0910_P2_TSFIFO_BCLKDEL1CK 0xf37460c0 +#define FSTV0910_P2_BCHERROR_MODE 0xf3744030 +#define FSTV0910_P2_TSFIFO_NSGNL2DATA 0xf3743008 +#define FSTV0910_P2_TSFIFO_EMBINDVB 0xf3742004 #define FSTV0910_P2_TSFIFO_BITSPEED 0xf3740003 /* P2_TSSYNC */ #define RSTV0910_P2_TSSYNC 0xf375 -#define FSTV0910_P2_TSFIFO_SYNCMODE 0xf3750018 +#define FSTV0910_P2_TSFIFO_SYNCMODE 0xf3753018 /* P2_TSINSDELH */ #define RSTV0910_P2_TSINSDELH 0xf376 -#define FSTV0910_P2_TSDEL_SYNCBYTE 0xf3760080 -#define FSTV0910_P2_TSDEL_XXHEADER 0xf3760040 -#define FSTV0910_P2_TSDEL_DATAFIELD 0xf3760010 -#define FSTV0910_P2_TSINSDEL_RSPARITY 0xf3760002 +#define FSTV0910_P2_TSDEL_SYNCBYTE 0xf3767080 +#define FSTV0910_P2_TSDEL_XXHEADER 0xf3766040 +#define FSTV0910_P2_TSDEL_DATAFIELD 0xf3764010 +#define FSTV0910_P2_TSINSDEL_RSPARITY 0xf3761002 #define FSTV0910_P2_TSINSDEL_CRC8 0xf3760001 /* P2_TSINSDELM */ #define RSTV0910_P2_TSINSDELM 0xf377 -#define FSTV0910_P2_TSINS_EMODCOD 0xf3770010 -#define FSTV0910_P2_TSINS_TOKEN 0xf3770008 -#define FSTV0910_P2_TSINS_XXXERR 0xf3770004 -#define FSTV0910_P2_TSINS_MATYPE 0xf3770002 +#define FSTV0910_P2_TSINS_EMODCOD 0xf3774010 +#define FSTV0910_P2_TSINS_TOKEN 0xf3773008 +#define FSTV0910_P2_TSINS_XXXERR 0xf3772004 +#define FSTV0910_P2_TSINS_MATYPE 0xf3771002 #define FSTV0910_P2_TSINS_UPL 0xf3770001 /* P2_TSINSDELL */ #define RSTV0910_P2_TSINSDELL 0xf378 -#define FSTV0910_P2_TSINS_DFL 0xf3780080 -#define FSTV0910_P2_TSINS_SYNCD 0xf3780040 -#define FSTV0910_P2_TSINS_BLOCLEN 0xf3780020 -#define FSTV0910_P2_TSINS_SIGPCOUNT 0xf3780010 -#define FSTV0910_P2_TSINS_FIFO 0xf3780008 -#define FSTV0910_P2_TSINS_REALPACK 0xf3780004 -#define FSTV0910_P2_TSINS_TSCONFIG 0xf3780002 +#define FSTV0910_P2_TSINS_DFL 0xf3787080 +#define FSTV0910_P2_TSINS_SYNCD 0xf3786040 +#define FSTV0910_P2_TSINS_BLOCLEN 0xf3785020 +#define FSTV0910_P2_TSINS_SIGPCOUNT 0xf3784010 +#define FSTV0910_P2_TSINS_FIFO 0xf3783008 +#define FSTV0910_P2_TSINS_REALPACK 0xf3782004 +#define FSTV0910_P2_TSINS_TSCONFIG 0xf3781002 #define FSTV0910_P2_TSINS_LATENCY 0xf3780001 /* P2_TSDIVN */ #define RSTV0910_P2_TSDIVN 0xf379 -#define FSTV0910_P2_TSFIFO_SPEEDMODE 0xf37900c0 +#define FSTV0910_P2_TSFIFO_SPEEDMODE 0xf37960c0 #define FSTV0910_P2_TSFIFO_RISEOK 0xf3790007 /* P2_TSCFG4 */ #define RSTV0910_P2_TSCFG4 0xf37a -#define FSTV0910_P2_TSFIFO_TSSPEEDMODE 0xf37a00c0 +#define FSTV0910_P2_TSFIFO_TSSPEEDMODE 0xf37a60c0 /* P2_TSSPEED */ #define RSTV0910_P2_TSSPEED 0xf380 @@ -1796,18 +1796,18 @@ /* P2_TSSTATUS */ #define RSTV0910_P2_TSSTATUS 0xf381 -#define FSTV0910_P2_TSFIFO_LINEOK 0xf3810080 -#define FSTV0910_P2_TSFIFO_ERROR 0xf3810040 -#define FSTV0910_P2_TSFIFO_NOSYNC 0xf3810010 -#define FSTV0910_P2_TSREGUL_ERROR 0xf3810004 +#define FSTV0910_P2_TSFIFO_LINEOK 0xf3817080 +#define FSTV0910_P2_TSFIFO_ERROR 0xf3816040 +#define FSTV0910_P2_TSFIFO_NOSYNC 0xf3814010 +#define FSTV0910_P2_TSREGUL_ERROR 0xf3812004 #define FSTV0910_P2_DIL_READY 0xf3810001 /* P2_TSSTATUS2 */ #define RSTV0910_P2_TSSTATUS2 0xf382 -#define FSTV0910_P2_TSFIFO_DEMODSEL 0xf3820080 -#define FSTV0910_P2_TSFIFOSPEED_STORE 0xf3820040 -#define FSTV0910_P2_DILXX_RESET 0xf3820020 -#define FSTV0910_P2_SCRAMBDETECT 0xf3820002 +#define FSTV0910_P2_TSFIFO_DEMODSEL 0xf3827080 +#define FSTV0910_P2_TSFIFOSPEED_STORE 0xf3826040 +#define FSTV0910_P2_DILXX_RESET 0xf3825020 +#define FSTV0910_P2_SCRAMBDETECT 0xf3821002 /* P2_TSBITRATE1 */ #define RSTV0910_P2_TSBITRATE1 0xf383 @@ -1819,7 +1819,7 @@ /* P2_TSPACKLEN1 */ #define RSTV0910_P2_TSPACKLEN1 0xf385 -#define FSTV0910_P2_TSFIFO_PACKCPT 0xf38500e0 +#define FSTV0910_P2_TSFIFO_PACKCPT 0xf38550e0 /* P2_TSDLY2 */ #define RSTV0910_P2_TSDLY2 0xf389 @@ -1839,8 +1839,8 @@ /* P2_TSBUFSTAT2 */ #define RSTV0910_P2_TSBUFSTAT2 0xf38d -#define FSTV0910_P2_TSISCR_3BYTES 0xf38d0080 -#define FSTV0910_P2_TSISCR_NEWDATA 0xf38d0040 +#define FSTV0910_P2_TSISCR_3BYTES 0xf38d7080 +#define FSTV0910_P2_TSISCR_NEWDATA 0xf38d6040 #define FSTV0910_P2_TSISCR_BUFSTAT2 0xf38d003f /* P2_TSBUFSTAT1 */ @@ -1853,13 +1853,13 @@ /* P2_TSDEBUGL */ #define RSTV0910_P2_TSDEBUGL 0xf391 -#define FSTV0910_P2_TSFIFO_ERROR_EVNT 0xf3910004 +#define FSTV0910_P2_TSFIFO_ERROR_EVNT 0xf3912004 #define FSTV0910_P2_TSFIFO_OVERFLOWM 0xf3910001 /* P2_TSDLYSET2 */ #define RSTV0910_P2_TSDLYSET2 0xf392 -#define FSTV0910_P2_SOFFIFO_OFFSET 0xf39200c0 -#define FSTV0910_P2_HYSTERESIS_THRESHOLD 0xf3920030 +#define FSTV0910_P2_SOFFIFO_OFFSET 0xf39260c0 +#define FSTV0910_P2_HYSTERESIS_THRESHOLD 0xf3924030 #define FSTV0910_P2_SOFFIFO_SYMBOFFS2 0xf392000f /* P2_TSDLYSET1 */ @@ -1872,12 +1872,12 @@ /* P2_ERRCTRL1 */ #define RSTV0910_P2_ERRCTRL1 0xf398 -#define FSTV0910_P2_ERR_SOURCE1 0xf39800f0 +#define FSTV0910_P2_ERR_SOURCE1 0xf39840f0 #define FSTV0910_P2_NUM_EVENT1 0xf3980007 /* P2_ERRCNT12 */ #define RSTV0910_P2_ERRCNT12 0xf399 -#define FSTV0910_P2_ERRCNT1_OLDVALUE 0xf3990080 +#define FSTV0910_P2_ERRCNT1_OLDVALUE 0xf3997080 #define FSTV0910_P2_ERR_CNT12 0xf399007f /* P2_ERRCNT11 */ @@ -1890,12 +1890,12 @@ /* P2_ERRCTRL2 */ #define RSTV0910_P2_ERRCTRL2 0xf39c -#define FSTV0910_P2_ERR_SOURCE2 0xf39c00f0 +#define FSTV0910_P2_ERR_SOURCE2 0xf39c40f0 #define FSTV0910_P2_NUM_EVENT2 0xf39c0007 /* P2_ERRCNT22 */ #define RSTV0910_P2_ERRCNT22 0xf39d -#define FSTV0910_P2_ERRCNT2_OLDVALUE 0xf39d0080 +#define FSTV0910_P2_ERRCNT2_OLDVALUE 0xf39d7080 #define FSTV0910_P2_ERR_CNT22 0xf39d007f /* P2_ERRCNT21 */ @@ -1908,39 +1908,39 @@ /* P2_FECSPY */ #define RSTV0910_P2_FECSPY 0xf3a0 -#define FSTV0910_P2_SPY_ENABLE 0xf3a00080 -#define FSTV0910_P2_NO_SYNCBYTE 0xf3a00040 -#define FSTV0910_P2_SERIAL_MODE 0xf3a00020 -#define FSTV0910_P2_UNUSUAL_PACKET 0xf3a00010 -#define FSTV0910_P2_BERMETER_DATAMODE 0xf3a0000c -#define FSTV0910_P2_BERMETER_LMODE 0xf3a00002 +#define FSTV0910_P2_SPY_ENABLE 0xf3a07080 +#define FSTV0910_P2_NO_SYNCBYTE 0xf3a06040 +#define FSTV0910_P2_SERIAL_MODE 0xf3a05020 +#define FSTV0910_P2_UNUSUAL_PACKET 0xf3a04010 +#define FSTV0910_P2_BERMETER_DATAMODE 0xf3a0200c +#define FSTV0910_P2_BERMETER_LMODE 0xf3a01002 #define FSTV0910_P2_BERMETER_RESET 0xf3a00001 /* P2_FSPYCFG */ #define RSTV0910_P2_FSPYCFG 0xf3a1 -#define FSTV0910_P2_FECSPY_INPUT 0xf3a100c0 -#define FSTV0910_P2_RST_ON_ERROR 0xf3a10020 -#define FSTV0910_P2_ONE_SHOT 0xf3a10010 -#define FSTV0910_P2_I2C_MODE 0xf3a1000c +#define FSTV0910_P2_FECSPY_INPUT 0xf3a160c0 +#define FSTV0910_P2_RST_ON_ERROR 0xf3a15020 +#define FSTV0910_P2_ONE_SHOT 0xf3a14010 +#define FSTV0910_P2_I2C_MODE 0xf3a1200c #define FSTV0910_P2_SPY_HYSTERESIS 0xf3a10003 /* P2_FSPYDATA */ #define RSTV0910_P2_FSPYDATA 0xf3a2 -#define FSTV0910_P2_SPY_STUFFING 0xf3a20080 -#define FSTV0910_P2_SPY_CNULLPKT 0xf3a20020 +#define FSTV0910_P2_SPY_STUFFING 0xf3a27080 +#define FSTV0910_P2_SPY_CNULLPKT 0xf3a25020 #define FSTV0910_P2_SPY_OUTDATA_MODE 0xf3a2001f /* P2_FSPYOUT */ #define RSTV0910_P2_FSPYOUT 0xf3a3 -#define FSTV0910_P2_FSPY_DIRECT 0xf3a30080 +#define FSTV0910_P2_FSPY_DIRECT 0xf3a37080 #define FSTV0910_P2_STUFF_MODE 0xf3a30007 /* P2_FSTATUS */ #define RSTV0910_P2_FSTATUS 0xf3a4 -#define FSTV0910_P2_SPY_ENDSIM 0xf3a40080 -#define FSTV0910_P2_VALID_SIM 0xf3a40040 -#define FSTV0910_P2_FOUND_SIGNAL 0xf3a40020 -#define FSTV0910_P2_DSS_SYNCBYTE 0xf3a40010 +#define FSTV0910_P2_SPY_ENDSIM 0xf3a47080 +#define FSTV0910_P2_VALID_SIM 0xf3a46040 +#define FSTV0910_P2_FOUND_SIGNAL 0xf3a45020 +#define FSTV0910_P2_DSS_SYNCBYTE 0xf3a44010 #define FSTV0910_P2_RESULT_STATE 0xf3a4000f /* P2_FBERCPT4 */ @@ -1977,8 +1977,8 @@ /* P2_FSPYBER */ #define RSTV0910_P2_FSPYBER 0xf3b2 -#define FSTV0910_P2_FSPYBER_SYNCBYTE 0xf3b20010 -#define FSTV0910_P2_FSPYBER_UNSYNC 0xf3b20008 +#define FSTV0910_P2_FSPYBER_SYNCBYTE 0xf3b24010 +#define FSTV0910_P2_FSPYBER_UNSYNC 0xf3b23008 #define FSTV0910_P2_FSPYBER_CTIME 0xf3b20007 /* P2_SFERROR */ @@ -1987,60 +1987,60 @@ /* P2_SFECSTATUS */ #define RSTV0910_P2_SFECSTATUS 0xf3c3 -#define FSTV0910_P2_SFEC_ON 0xf3c30080 -#define FSTV0910_P2_SFEC_OFF 0xf3c30040 -#define FSTV0910_P2_LOCKEDSFEC 0xf3c30008 -#define FSTV0910_P2_SFEC_DELOCK 0xf3c30004 -#define FSTV0910_P2_SFEC_DEMODSEL 0xf3c30002 +#define FSTV0910_P2_SFEC_ON 0xf3c37080 +#define FSTV0910_P2_SFEC_OFF 0xf3c36040 +#define FSTV0910_P2_LOCKEDSFEC 0xf3c33008 +#define FSTV0910_P2_SFEC_DELOCK 0xf3c32004 +#define FSTV0910_P2_SFEC_DEMODSEL 0xf3c31002 #define FSTV0910_P2_SFEC_OVFON 0xf3c30001 /* P2_SFKDIV12 */ #define RSTV0910_P2_SFKDIV12 0xf3c4 -#define FSTV0910_P2_SFECKDIV12_MAN 0xf3c40080 +#define FSTV0910_P2_SFECKDIV12_MAN 0xf3c47080 /* P2_SFKDIV23 */ #define RSTV0910_P2_SFKDIV23 0xf3c5 -#define FSTV0910_P2_SFECKDIV23_MAN 0xf3c50080 +#define FSTV0910_P2_SFECKDIV23_MAN 0xf3c57080 /* P2_SFKDIV34 */ #define RSTV0910_P2_SFKDIV34 0xf3c6 -#define FSTV0910_P2_SFECKDIV34_MAN 0xf3c60080 +#define FSTV0910_P2_SFECKDIV34_MAN 0xf3c67080 /* P2_SFKDIV56 */ #define RSTV0910_P2_SFKDIV56 0xf3c7 -#define FSTV0910_P2_SFECKDIV56_MAN 0xf3c70080 +#define FSTV0910_P2_SFECKDIV56_MAN 0xf3c77080 /* P2_SFKDIV67 */ #define RSTV0910_P2_SFKDIV67 0xf3c8 -#define FSTV0910_P2_SFECKDIV67_MAN 0xf3c80080 +#define FSTV0910_P2_SFECKDIV67_MAN 0xf3c87080 /* P2_SFKDIV78 */ #define RSTV0910_P2_SFKDIV78 0xf3c9 -#define FSTV0910_P2_SFECKDIV78_MAN 0xf3c90080 +#define FSTV0910_P2_SFECKDIV78_MAN 0xf3c97080 /* P2_SFSTATUS */ #define RSTV0910_P2_SFSTATUS 0xf3cc -#define FSTV0910_P2_SFEC_LINEOK 0xf3cc0080 -#define FSTV0910_P2_SFEC_ERROR 0xf3cc0040 -#define FSTV0910_P2_SFEC_DATA7 0xf3cc0020 -#define FSTV0910_P2_SFEC_PKTDNBRFAIL 0xf3cc0010 -#define FSTV0910_P2_TSSFEC_DEMODSEL 0xf3cc0008 -#define FSTV0910_P2_SFEC_NOSYNC 0xf3cc0004 -#define FSTV0910_P2_SFEC_UNREGULA 0xf3cc0002 +#define FSTV0910_P2_SFEC_LINEOK 0xf3cc7080 +#define FSTV0910_P2_SFEC_ERROR 0xf3cc6040 +#define FSTV0910_P2_SFEC_DATA7 0xf3cc5020 +#define FSTV0910_P2_SFEC_PKTDNBRFAIL 0xf3cc4010 +#define FSTV0910_P2_TSSFEC_DEMODSEL 0xf3cc3008 +#define FSTV0910_P2_SFEC_NOSYNC 0xf3cc2004 +#define FSTV0910_P2_SFEC_UNREGULA 0xf3cc1002 #define FSTV0910_P2_SFEC_READY 0xf3cc0001 /* P2_SFDLYSET2 */ #define RSTV0910_P2_SFDLYSET2 0xf3d0 -#define FSTV0910_P2_SFEC_DISABLE 0xf3d00002 +#define FSTV0910_P2_SFEC_DISABLE 0xf3d01002 /* P2_SFERRCTRL */ #define RSTV0910_P2_SFERRCTRL 0xf3d8 -#define FSTV0910_P2_SFEC_ERR_SOURCE 0xf3d800f0 +#define FSTV0910_P2_SFEC_ERR_SOURCE 0xf3d840f0 #define FSTV0910_P2_SFEC_NUM_EVENT 0xf3d80007 /* P2_SFERRCNT2 */ #define RSTV0910_P2_SFERRCNT2 0xf3d9 -#define FSTV0910_P2_SFERRC_OLDVALUE 0xf3d90080 +#define FSTV0910_P2_SFERRC_OLDVALUE 0xf3d97080 #define FSTV0910_P2_SFEC_ERR_CNT2 0xf3d9007f /* P2_SFERRCNT1 */ @@ -2053,13 +2053,13 @@ /* P1_IQCONST */ #define RSTV0910_P1_IQCONST 0xf400 -#define FSTV0910_P1_CONSTEL_SELECT 0xf4000060 +#define FSTV0910_P1_CONSTEL_SELECT 0xf4005060 #define FSTV0910_P1_IQSYMB_SEL 0xf400001f /* P1_NOSCFG */ #define RSTV0910_P1_NOSCFG 0xf401 -#define FSTV0910_P1_DUMMYPL_NOSDATA 0xf4010020 -#define FSTV0910_P1_NOSPLH_BETA 0xf4010018 +#define FSTV0910_P1_DUMMYPL_NOSDATA 0xf4015020 +#define FSTV0910_P1_NOSPLH_BETA 0xf4013018 #define FSTV0910_P1_NOSDATA_BETA 0xf4010007 /* P1_ISYMB */ @@ -2072,18 +2072,18 @@ /* P1_AGC1CFG */ #define RSTV0910_P1_AGC1CFG 0xf404 -#define FSTV0910_P1_DC_FROZEN 0xf4040080 -#define FSTV0910_P1_DC_CORRECT 0xf4040040 -#define FSTV0910_P1_AMM_FROZEN 0xf4040020 -#define FSTV0910_P1_AMM_CORRECT 0xf4040010 -#define FSTV0910_P1_QUAD_FROZEN 0xf4040008 -#define FSTV0910_P1_QUAD_CORRECT 0xf4040004 +#define FSTV0910_P1_DC_FROZEN 0xf4047080 +#define FSTV0910_P1_DC_CORRECT 0xf4046040 +#define FSTV0910_P1_AMM_FROZEN 0xf4045020 +#define FSTV0910_P1_AMM_CORRECT 0xf4044010 +#define FSTV0910_P1_QUAD_FROZEN 0xf4043008 +#define FSTV0910_P1_QUAD_CORRECT 0xf4042004 /* P1_AGC1CN */ #define RSTV0910_P1_AGC1CN 0xf406 -#define FSTV0910_P1_AGC1_LOCKED 0xf4060080 -#define FSTV0910_P1_AGC1_MINPOWER 0xf4060010 -#define FSTV0910_P1_AGCOUT_FAST 0xf4060008 +#define FSTV0910_P1_AGC1_LOCKED 0xf4067080 +#define FSTV0910_P1_AGC1_MINPOWER 0xf4064010 +#define FSTV0910_P1_AGCOUT_FAST 0xf4063008 #define FSTV0910_P1_AGCIQ_BETA 0xf4060007 /* P1_AGC1REF */ @@ -2124,50 +2124,50 @@ /* P1_DEMOD */ #define RSTV0910_P1_DEMOD 0xf410 -#define FSTV0910_P1_MANUALS2_ROLLOFF 0xf4100080 -#define FSTV0910_P1_SPECINV_CONTROL 0xf4100030 -#define FSTV0910_P1_MANUALSX_ROLLOFF 0xf4100004 +#define FSTV0910_P1_MANUALS2_ROLLOFF 0xf4107080 +#define FSTV0910_P1_SPECINV_CONTROL 0xf4104030 +#define FSTV0910_P1_MANUALSX_ROLLOFF 0xf4102004 #define FSTV0910_P1_ROLLOFF_CONTROL 0xf4100003 /* P1_DMDMODCOD */ #define RSTV0910_P1_DMDMODCOD 0xf411 -#define FSTV0910_P1_MANUAL_MODCOD 0xf4110080 -#define FSTV0910_P1_DEMOD_MODCOD 0xf411007c +#define FSTV0910_P1_MANUAL_MODCOD 0xf4117080 +#define FSTV0910_P1_DEMOD_MODCOD 0xf411207c #define FSTV0910_P1_DEMOD_TYPE 0xf4110003 /* P1_DSTATUS */ #define RSTV0910_P1_DSTATUS 0xf412 -#define FSTV0910_P1_CAR_LOCK 0xf4120080 -#define FSTV0910_P1_TMGLOCK_QUALITY 0xf4120060 -#define FSTV0910_P1_LOCK_DEFINITIF 0xf4120008 +#define FSTV0910_P1_CAR_LOCK 0xf4127080 +#define FSTV0910_P1_TMGLOCK_QUALITY 0xf4125060 +#define FSTV0910_P1_LOCK_DEFINITIF 0xf4123008 #define FSTV0910_P1_OVADC_DETECT 0xf4120001 /* P1_DSTATUS2 */ #define RSTV0910_P1_DSTATUS2 0xf413 -#define FSTV0910_P1_DEMOD_DELOCK 0xf4130080 -#define FSTV0910_P1_MODCODRQ_SYNCTAG 0xf4130020 -#define FSTV0910_P1_POLYPH_SATEVENT 0xf4130010 -#define FSTV0910_P1_AGC1_NOSIGNALACK 0xf4130008 -#define FSTV0910_P1_AGC2_OVERFLOW 0xf4130004 -#define FSTV0910_P1_CFR_OVERFLOW 0xf4130002 +#define FSTV0910_P1_DEMOD_DELOCK 0xf4137080 +#define FSTV0910_P1_MODCODRQ_SYNCTAG 0xf4135020 +#define FSTV0910_P1_POLYPH_SATEVENT 0xf4134010 +#define FSTV0910_P1_AGC1_NOSIGNALACK 0xf4133008 +#define FSTV0910_P1_AGC2_OVERFLOW 0xf4132004 +#define FSTV0910_P1_CFR_OVERFLOW 0xf4131002 #define FSTV0910_P1_GAMMA_OVERUNDER 0xf4130001 /* P1_DMDCFGMD */ #define RSTV0910_P1_DMDCFGMD 0xf414 -#define FSTV0910_P1_DVBS2_ENABLE 0xf4140080 -#define FSTV0910_P1_DVBS1_ENABLE 0xf4140040 -#define FSTV0910_P1_SCAN_ENABLE 0xf4140010 -#define FSTV0910_P1_CFR_AUTOSCAN 0xf4140008 +#define FSTV0910_P1_DVBS2_ENABLE 0xf4147080 +#define FSTV0910_P1_DVBS1_ENABLE 0xf4146040 +#define FSTV0910_P1_SCAN_ENABLE 0xf4144010 +#define FSTV0910_P1_CFR_AUTOSCAN 0xf4143008 #define FSTV0910_P1_TUN_RNG 0xf4140003 /* P1_DMDCFG2 */ #define RSTV0910_P1_DMDCFG2 0xf415 -#define FSTV0910_P1_S1S2_SEQUENTIAL 0xf4150040 -#define FSTV0910_P1_INFINITE_RELOCK 0xf4150010 +#define FSTV0910_P1_S1S2_SEQUENTIAL 0xf4156040 +#define FSTV0910_P1_INFINITE_RELOCK 0xf4154010 /* P1_DMDISTATE */ #define RSTV0910_P1_DMDISTATE 0xf416 -#define FSTV0910_P1_I2C_NORESETDMODE 0xf4160080 +#define FSTV0910_P1_I2C_NORESETDMODE 0xf4167080 #define FSTV0910_P1_I2C_DEMOD_MODE 0xf416001f /* P1_DMDT0M */ @@ -2176,27 +2176,27 @@ /* P1_DMDSTATE */ #define RSTV0910_P1_DMDSTATE 0xf41b -#define FSTV0910_P1_HEADER_MODE 0xf41b0060 +#define FSTV0910_P1_HEADER_MODE 0xf41b5060 /* P1_DMDFLYW */ #define RSTV0910_P1_DMDFLYW 0xf41c -#define FSTV0910_P1_I2C_IRQVAL 0xf41c00f0 +#define FSTV0910_P1_I2C_IRQVAL 0xf41c40f0 #define FSTV0910_P1_FLYWHEEL_CPT 0xf41c000f /* P1_DSTATUS3 */ #define RSTV0910_P1_DSTATUS3 0xf41d -#define FSTV0910_P1_CFR_ZIGZAG 0xf41d0080 -#define FSTV0910_P1_DEMOD_CFGMODE 0xf41d0060 -#define FSTV0910_P1_GAMMA_LOWBAUDRATE 0xf41d0010 +#define FSTV0910_P1_CFR_ZIGZAG 0xf41d7080 +#define FSTV0910_P1_DEMOD_CFGMODE 0xf41d5060 +#define FSTV0910_P1_GAMMA_LOWBAUDRATE 0xf41d4010 /* P1_DMDCFG3 */ #define RSTV0910_P1_DMDCFG3 0xf41e -#define FSTV0910_P1_NOSTOP_FIFOFULL 0xf41e0008 +#define FSTV0910_P1_NOSTOP_FIFOFULL 0xf41e3008 /* P1_DMDCFG4 */ #define RSTV0910_P1_DMDCFG4 0xf41f -#define FSTV0910_P1_DIS_VITLOCK 0xf41f0080 -#define FSTV0910_P1_DIS_CLKENABLE 0xf41f0004 +#define FSTV0910_P1_DIS_VITLOCK 0xf41f7080 +#define FSTV0910_P1_DIS_CLKENABLE 0xf41f2004 /* P1_CORRELMANT */ #define RSTV0910_P1_CORRELMANT 0xf420 @@ -2208,13 +2208,13 @@ /* P1_CORRELEXP */ #define RSTV0910_P1_CORRELEXP 0xf422 -#define FSTV0910_P1_CORREL_ABSEXP 0xf42200f0 +#define FSTV0910_P1_CORREL_ABSEXP 0xf42240f0 #define FSTV0910_P1_CORREL_EXP 0xf422000f /* P1_PLHMODCOD */ #define RSTV0910_P1_PLHMODCOD 0xf424 -#define FSTV0910_P1_SPECINV_DEMOD 0xf4240080 -#define FSTV0910_P1_PLH_MODCOD 0xf424007c +#define FSTV0910_P1_SPECINV_DEMOD 0xf4247080 +#define FSTV0910_P1_PLH_MODCOD 0xf424207c #define FSTV0910_P1_PLH_TYPE 0xf4240003 /* P1_DMDREG */ @@ -2223,19 +2223,19 @@ /* P1_AGCNADJ */ #define RSTV0910_P1_AGCNADJ 0xf426 -#define FSTV0910_P1_RADJOFF_AGC2 0xf4260080 -#define FSTV0910_P1_RADJOFF_AGC1 0xf4260040 +#define FSTV0910_P1_RADJOFF_AGC2 0xf4267080 +#define FSTV0910_P1_RADJOFF_AGC1 0xf4266040 #define FSTV0910_P1_AGC_NADJ 0xf426013f /* P1_AGCKS */ #define RSTV0910_P1_AGCKS 0xf427 -#define FSTV0910_P1_RSADJ_MANUALCFG 0xf4270080 -#define FSTV0910_P1_RSADJ_CCMMODE 0xf4270040 +#define FSTV0910_P1_RSADJ_MANUALCFG 0xf4277080 +#define FSTV0910_P1_RSADJ_CCMMODE 0xf4276040 #define FSTV0910_P1_RADJ_SPSK 0xf427013f /* P1_AGCKQ */ #define RSTV0910_P1_AGCKQ 0xf428 -#define FSTV0910_P1_RADJON_DVBS1 0xf4280040 +#define FSTV0910_P1_RADJON_DVBS1 0xf4286040 #define FSTV0910_P1_RADJ_QPSK 0xf428013f /* P1_AGCK8 */ @@ -2244,20 +2244,20 @@ /* P1_AGCK16 */ #define RSTV0910_P1_AGCK16 0xf42a -#define FSTV0910_P1_R2ADJOFF_16APSK 0xf42a0040 -#define FSTV0910_P1_R1ADJOFF_16APSK 0xf42a0020 +#define FSTV0910_P1_R2ADJOFF_16APSK 0xf42a6040 +#define FSTV0910_P1_R1ADJOFF_16APSK 0xf42a5020 #define FSTV0910_P1_RADJ_16APSK 0xf42a011f /* P1_AGCK32 */ #define RSTV0910_P1_AGCK32 0xf42b -#define FSTV0910_P1_R3ADJOFF_32APSK 0xf42b0080 -#define FSTV0910_P1_R2ADJOFF_32APSK 0xf42b0040 -#define FSTV0910_P1_R1ADJOFF_32APSK 0xf42b0020 +#define FSTV0910_P1_R3ADJOFF_32APSK 0xf42b7080 +#define FSTV0910_P1_R2ADJOFF_32APSK 0xf42b6040 +#define FSTV0910_P1_R1ADJOFF_32APSK 0xf42b5020 #define FSTV0910_P1_RADJ_32APSK 0xf42b011f /* P1_AGC2O */ #define RSTV0910_P1_AGC2O 0xf42c -#define FSTV0910_P1_CSTENV_MODE 0xf42c00c0 +#define FSTV0910_P1_CSTENV_MODE 0xf42c60c0 #define FSTV0910_P1_AGC2_COEF 0xf42c0007 /* P1_AGC2REF */ @@ -2306,32 +2306,32 @@ /* P1_CARCFG */ #define RSTV0910_P1_CARCFG 0xf438 -#define FSTV0910_P1_ROTAON 0xf4380004 +#define FSTV0910_P1_ROTAON 0xf4382004 #define FSTV0910_P1_PH_DET_ALGO 0xf4380003 /* P1_ACLC */ #define RSTV0910_P1_ACLC 0xf439 -#define FSTV0910_P1_CAR_ALPHA_MANT 0xf4390030 +#define FSTV0910_P1_CAR_ALPHA_MANT 0xf4394030 #define FSTV0910_P1_CAR_ALPHA_EXP 0xf439000f /* P1_BCLC */ #define RSTV0910_P1_BCLC 0xf43a -#define FSTV0910_P1_CAR_BETA_MANT 0xf43a0030 +#define FSTV0910_P1_CAR_BETA_MANT 0xf43a4030 #define FSTV0910_P1_CAR_BETA_EXP 0xf43a000f /* P1_ACLCS2 */ #define RSTV0910_P1_ACLCS2 0xf43b -#define FSTV0910_P1_CARS2_APLHA_MANTISSE 0xf43b0030 +#define FSTV0910_P1_CARS2_APLHA_MANTISSE 0xf43b4030 #define FSTV0910_P1_CARS2_ALPHA_EXP 0xf43b000f /* P1_BCLCS2 */ #define RSTV0910_P1_BCLCS2 0xf43c -#define FSTV0910_P1_CARS2_BETA_MANTISSE 0xf43c0030 +#define FSTV0910_P1_CARS2_BETA_MANTISSE 0xf43c4030 #define FSTV0910_P1_CARS2_BETA_EXP 0xf43c000f /* P1_CARFREQ */ #define RSTV0910_P1_CARFREQ 0xf43d -#define FSTV0910_P1_KC_COARSE_EXP 0xf43d00f0 +#define FSTV0910_P1_KC_COARSE_EXP 0xf43d40f0 #define FSTV0910_P1_BETA_FREQ 0xf43d000f /* P1_CARHDR */ @@ -2384,7 +2384,7 @@ /* P1_CFRINC1 */ #define RSTV0910_P1_CFRINC1 0xf44a -#define FSTV0910_P1_MANUAL_CFRINC 0xf44a0080 +#define FSTV0910_P1_MANUAL_CFRINC 0xf44a7080 #define FSTV0910_P1_CFR_INC1 0xf44a003f /* P1_CFRINC0 */ @@ -2409,18 +2409,18 @@ /* P1_TMGCFG */ #define RSTV0910_P1_TMGCFG 0xf450 -#define FSTV0910_P1_TMGLOCK_BETA 0xf45000c0 -#define FSTV0910_P1_DO_TIMING_CORR 0xf4500010 +#define FSTV0910_P1_TMGLOCK_BETA 0xf45060c0 +#define FSTV0910_P1_DO_TIMING_CORR 0xf4504010 #define FSTV0910_P1_TMG_MINFREQ 0xf4500003 /* P1_RTC */ #define RSTV0910_P1_RTC 0xf451 -#define FSTV0910_P1_TMGALPHA_EXP 0xf45100f0 +#define FSTV0910_P1_TMGALPHA_EXP 0xf45140f0 #define FSTV0910_P1_TMGBETA_EXP 0xf451000f /* P1_RTCS2 */ #define RSTV0910_P1_RTCS2 0xf452 -#define FSTV0910_P1_TMGALPHAS2_EXP 0xf45200f0 +#define FSTV0910_P1_TMGALPHAS2_EXP 0xf45240f0 #define FSTV0910_P1_TMGBETAS2_EXP 0xf452000f /* P1_TMGTHRISE */ @@ -2441,7 +2441,7 @@ /* P1_KTTMG */ #define RSTV0910_P1_KTTMG 0xf457 -#define FSTV0910_P1_KT_TMG_EXP 0xf45700f0 +#define FSTV0910_P1_KT_TMG_EXP 0xf45740f0 /* P1_KREFTMG */ #define RSTV0910_P1_KREFTMG 0xf458 @@ -2449,12 +2449,12 @@ /* P1_SFRSTEP */ #define RSTV0910_P1_SFRSTEP 0xf459 -#define FSTV0910_P1_SFR_SCANSTEP 0xf45900f0 +#define FSTV0910_P1_SFR_SCANSTEP 0xf45940f0 #define FSTV0910_P1_SFR_CENTERSTEP 0xf459000f /* P1_TMGCFG2 */ #define RSTV0910_P1_TMGCFG2 0xf45a -#define FSTV0910_P1_DIS_AUTOSAMP 0xf45a0008 +#define FSTV0910_P1_DIS_AUTOSAMP 0xf45a3008 #define FSTV0910_P1_SFRRATIO_FINE 0xf45a0001 /* P1_KREFTMG2 */ @@ -2463,9 +2463,9 @@ /* P1_TMGCFG3 */ #define RSTV0910_P1_TMGCFG3 0xf45d -#define FSTV0910_P1_CONT_TMGCENTER 0xf45d0008 -#define FSTV0910_P1_AUTO_GUP 0xf45d0004 -#define FSTV0910_P1_AUTO_GLOW 0xf45d0002 +#define FSTV0910_P1_CONT_TMGCENTER 0xf45d3008 +#define FSTV0910_P1_AUTO_GUP 0xf45d2004 +#define FSTV0910_P1_AUTO_GLOW 0xf45d1002 /* P1_SFRINIT1 */ #define RSTV0910_P1_SFRINIT1 0xf45e @@ -2529,11 +2529,11 @@ /* P1_TMGOBS */ #define RSTV0910_P1_TMGOBS 0xf46d -#define FSTV0910_P1_ROLLOFF_STATUS 0xf46d00c0 +#define FSTV0910_P1_ROLLOFF_STATUS 0xf46d60c0 /* P1_EQUALCFG */ #define RSTV0910_P1_EQUALCFG 0xf46f -#define FSTV0910_P1_EQUAL_ON 0xf46f0040 +#define FSTV0910_P1_EQUAL_ON 0xf46f6040 #define FSTV0910_P1_MU_EQUALDFE 0xf46f0007 /* P1_EQUAI1 */ @@ -2658,33 +2658,33 @@ /* P1_NOSCFGF1 */ #define RSTV0910_P1_NOSCFGF1 0xf48e -#define FSTV0910_P1_LOWNOISE_MESURE 0xf48e0080 -#define FSTV0910_P1_NOS_DELFRAME 0xf48e0040 -#define FSTV0910_P1_NOSDATA_MODE 0xf48e0030 -#define FSTV0910_P1_FRAMESEL_TYPESEL 0xf48e000c +#define FSTV0910_P1_LOWNOISE_MESURE 0xf48e7080 +#define FSTV0910_P1_NOS_DELFRAME 0xf48e6040 +#define FSTV0910_P1_NOSDATA_MODE 0xf48e4030 +#define FSTV0910_P1_FRAMESEL_TYPESEL 0xf48e200c #define FSTV0910_P1_FRAMESEL_TYPE 0xf48e0003 /* P1_NOSCFGF2 */ #define RSTV0910_P1_NOSCFGF2 0xf48f -#define FSTV0910_P1_DIS_NOSPILOTS 0xf48f0080 -#define FSTV0910_P1_FRAMESEL_MODCODSEL 0xf48f0060 +#define FSTV0910_P1_DIS_NOSPILOTS 0xf48f7080 +#define FSTV0910_P1_FRAMESEL_MODCODSEL 0xf48f5060 #define FSTV0910_P1_FRAMESEL_MODCOD 0xf48f001f /* P1_CAR2CFG */ #define RSTV0910_P1_CAR2CFG 0xf490 -#define FSTV0910_P1_ROTA2ON 0xf4900004 +#define FSTV0910_P1_ROTA2ON 0xf4902004 #define FSTV0910_P1_PH_DET_ALGO2 0xf4900003 /* P1_CFR2CFR1 */ #define RSTV0910_P1_CFR2CFR1 0xf491 -#define FSTV0910_P1_EN_S2CAR2CENTER 0xf4910020 +#define FSTV0910_P1_EN_S2CAR2CENTER 0xf4915020 #define FSTV0910_P1_CFR2TOCFR1_BETA 0xf4910007 /* P1_CAR3CFG */ #define RSTV0910_P1_CAR3CFG 0xf492 -#define FSTV0910_P1_CARRIER23_MODE 0xf49200c0 -#define FSTV0910_P1_CAR3INTERM_DVBS1 0xf4920020 -#define FSTV0910_P1_ABAMPLIF_MODE 0xf4920018 +#define FSTV0910_P1_CARRIER23_MODE 0xf49260c0 +#define FSTV0910_P1_CAR3INTERM_DVBS1 0xf4925020 +#define FSTV0910_P1_ABAMPLIF_MODE 0xf4923018 #define FSTV0910_P1_CARRIER3_ALPHA3DL 0xf4920007 /* P1_CFR22 */ @@ -2701,50 +2701,50 @@ /* P1_ACLC2S2Q */ #define RSTV0910_P1_ACLC2S2Q 0xf497 -#define FSTV0910_P1_ENAB_SPSKSYMB 0xf4970080 -#define FSTV0910_P1_CAR2S2_Q_ALPH_M 0xf4970030 +#define FSTV0910_P1_ENAB_SPSKSYMB 0xf4977080 +#define FSTV0910_P1_CAR2S2_Q_ALPH_M 0xf4974030 #define FSTV0910_P1_CAR2S2_Q_ALPH_E 0xf497000f /* P1_ACLC2S28 */ #define RSTV0910_P1_ACLC2S28 0xf498 -#define FSTV0910_P1_CAR2S2_8_ALPH_M 0xf4980030 +#define FSTV0910_P1_CAR2S2_8_ALPH_M 0xf4984030 #define FSTV0910_P1_CAR2S2_8_ALPH_E 0xf498000f /* P1_ACLC2S216A */ #define RSTV0910_P1_ACLC2S216A 0xf499 -#define FSTV0910_P1_CAR2S2_16A_ALPH_M 0xf4990030 +#define FSTV0910_P1_CAR2S2_16A_ALPH_M 0xf4994030 #define FSTV0910_P1_CAR2S2_16A_ALPH_E 0xf499000f /* P1_ACLC2S232A */ #define RSTV0910_P1_ACLC2S232A 0xf49a -#define FSTV0910_P1_CAR2S2_32A_ALPH_M 0xf49a0030 +#define FSTV0910_P1_CAR2S2_32A_ALPH_M 0xf49a4030 #define FSTV0910_P1_CAR2S2_32A_ALPH_E 0xf49a000f /* P1_BCLC2S2Q */ #define RSTV0910_P1_BCLC2S2Q 0xf49c -#define FSTV0910_P1_CAR2S2_Q_BETA_M 0xf49c0030 +#define FSTV0910_P1_CAR2S2_Q_BETA_M 0xf49c4030 #define FSTV0910_P1_CAR2S2_Q_BETA_E 0xf49c000f /* P1_BCLC2S28 */ #define RSTV0910_P1_BCLC2S28 0xf49d -#define FSTV0910_P1_CAR2S2_8_BETA_M 0xf49d0030 +#define FSTV0910_P1_CAR2S2_8_BETA_M 0xf49d4030 #define FSTV0910_P1_CAR2S2_8_BETA_E 0xf49d000f /* P1_BCLC2S216A */ #define RSTV0910_P1_BCLC2S216A 0xf49e -#define FSTV0910_P1_DVBS2S216A_NIP 0xf49e0080 -#define FSTV0910_P1_CAR2S2_16A_BETA_M 0xf49e0030 +#define FSTV0910_P1_DVBS2S216A_NIP 0xf49e7080 +#define FSTV0910_P1_CAR2S2_16A_BETA_M 0xf49e4030 #define FSTV0910_P1_CAR2S2_16A_BETA_E 0xf49e000f /* P1_BCLC2S232A */ #define RSTV0910_P1_BCLC2S232A 0xf49f -#define FSTV0910_P1_DVBS2S232A_NIP 0xf49f0080 -#define FSTV0910_P1_CAR2S2_32A_BETA_M 0xf49f0030 +#define FSTV0910_P1_DVBS2S232A_NIP 0xf49f7080 +#define FSTV0910_P1_CAR2S2_32A_BETA_M 0xf49f4030 #define FSTV0910_P1_CAR2S2_32A_BETA_E 0xf49f000f /* P1_PLROOT2 */ #define RSTV0910_P1_PLROOT2 0xf4ac -#define FSTV0910_P1_PLSCRAMB_MODE 0xf4ac000c +#define FSTV0910_P1_PLSCRAMB_MODE 0xf4ac200c #define FSTV0910_P1_PLSCRAMB_ROOT2 0xf4ac0003 /* P1_PLROOT1 */ @@ -2761,100 +2761,100 @@ /* P1_MODCODLST1 */ #define RSTV0910_P1_MODCODLST1 0xf4b1 -#define FSTV0910_P1_SYMBRATE_FILTER 0xf4b10008 -#define FSTV0910_P1_NRESET_MODCODLST 0xf4b10004 +#define FSTV0910_P1_SYMBRATE_FILTER 0xf4b13008 +#define FSTV0910_P1_NRESET_MODCODLST 0xf4b12004 #define FSTV0910_P1_DIS_32PSK_9_10 0xf4b10003 /* P1_MODCODLST2 */ #define RSTV0910_P1_MODCODLST2 0xf4b2 -#define FSTV0910_P1_DIS_32PSK_8_9 0xf4b200f0 +#define FSTV0910_P1_DIS_32PSK_8_9 0xf4b240f0 #define FSTV0910_P1_DIS_32PSK_5_6 0xf4b2000f /* P1_MODCODLST3 */ #define RSTV0910_P1_MODCODLST3 0xf4b3 -#define FSTV0910_P1_DIS_32PSK_4_5 0xf4b300f0 +#define FSTV0910_P1_DIS_32PSK_4_5 0xf4b340f0 #define FSTV0910_P1_DIS_32PSK_3_4 0xf4b3000f /* P1_MODCODLST4 */ #define RSTV0910_P1_MODCODLST4 0xf4b4 -#define FSTV0910_P1_DUMMYPL_PILOT 0xf4b40080 -#define FSTV0910_P1_DUMMYPL_NOPILOT 0xf4b40040 -#define FSTV0910_P1_DIS_16PSK_9_10 0xf4b40030 +#define FSTV0910_P1_DUMMYPL_PILOT 0xf4b47080 +#define FSTV0910_P1_DUMMYPL_NOPILOT 0xf4b46040 +#define FSTV0910_P1_DIS_16PSK_9_10 0xf4b44030 #define FSTV0910_P1_DIS_16PSK_8_9 0xf4b4000f /* P1_MODCODLST5 */ #define RSTV0910_P1_MODCODLST5 0xf4b5 -#define FSTV0910_P1_DIS_16PSK_5_6 0xf4b500f0 +#define FSTV0910_P1_DIS_16PSK_5_6 0xf4b540f0 #define FSTV0910_P1_DIS_16PSK_4_5 0xf4b5000f /* P1_MODCODLST6 */ #define RSTV0910_P1_MODCODLST6 0xf4b6 -#define FSTV0910_P1_DIS_16PSK_3_4 0xf4b600f0 +#define FSTV0910_P1_DIS_16PSK_3_4 0xf4b640f0 #define FSTV0910_P1_DIS_16PSK_2_3 0xf4b6000f /* P1_MODCODLST7 */ #define RSTV0910_P1_MODCODLST7 0xf4b7 -#define FSTV0910_P1_MODCOD_NNOSFILTER 0xf4b70080 -#define FSTV0910_P1_DIS_8PSK_9_10 0xf4b70030 +#define FSTV0910_P1_MODCOD_NNOSFILTER 0xf4b77080 +#define FSTV0910_P1_DIS_8PSK_9_10 0xf4b74030 #define FSTV0910_P1_DIS_8PSK_8_9 0xf4b7000f /* P1_MODCODLST8 */ #define RSTV0910_P1_MODCODLST8 0xf4b8 -#define FSTV0910_P1_DIS_8PSK_5_6 0xf4b800f0 +#define FSTV0910_P1_DIS_8PSK_5_6 0xf4b840f0 #define FSTV0910_P1_DIS_8PSK_3_4 0xf4b8000f /* P1_MODCODLST9 */ #define RSTV0910_P1_MODCODLST9 0xf4b9 -#define FSTV0910_P1_DIS_8PSK_2_3 0xf4b900f0 +#define FSTV0910_P1_DIS_8PSK_2_3 0xf4b940f0 #define FSTV0910_P1_DIS_8PSK_3_5 0xf4b9000f /* P1_MODCODLSTA */ #define RSTV0910_P1_MODCODLSTA 0xf4ba -#define FSTV0910_P1_NOSFILTER_LIMITE 0xf4ba0080 -#define FSTV0910_P1_DIS_QPSK_9_10 0xf4ba0030 +#define FSTV0910_P1_NOSFILTER_LIMITE 0xf4ba7080 +#define FSTV0910_P1_DIS_QPSK_9_10 0xf4ba4030 #define FSTV0910_P1_DIS_QPSK_8_9 0xf4ba000f /* P1_MODCODLSTB */ #define RSTV0910_P1_MODCODLSTB 0xf4bb -#define FSTV0910_P1_DIS_QPSK_5_6 0xf4bb00f0 +#define FSTV0910_P1_DIS_QPSK_5_6 0xf4bb40f0 #define FSTV0910_P1_DIS_QPSK_4_5 0xf4bb000f /* P1_MODCODLSTC */ #define RSTV0910_P1_MODCODLSTC 0xf4bc -#define FSTV0910_P1_DIS_QPSK_3_4 0xf4bc00f0 +#define FSTV0910_P1_DIS_QPSK_3_4 0xf4bc40f0 #define FSTV0910_P1_DIS_QPSK_2_3 0xf4bc000f /* P1_MODCODLSTD */ #define RSTV0910_P1_MODCODLSTD 0xf4bd -#define FSTV0910_P1_DIS_QPSK_3_5 0xf4bd00f0 +#define FSTV0910_P1_DIS_QPSK_3_5 0xf4bd40f0 #define FSTV0910_P1_DIS_QPSK_1_2 0xf4bd000f /* P1_MODCODLSTE */ #define RSTV0910_P1_MODCODLSTE 0xf4be -#define FSTV0910_P1_DIS_QPSK_2_5 0xf4be00f0 +#define FSTV0910_P1_DIS_QPSK_2_5 0xf4be40f0 #define FSTV0910_P1_DIS_QPSK_1_3 0xf4be000f /* P1_MODCODLSTF */ #define RSTV0910_P1_MODCODLSTF 0xf4bf -#define FSTV0910_P1_DIS_QPSK_1_4 0xf4bf00f0 -#define FSTV0910_P1_DEMOD_INVMODLST 0xf4bf0008 -#define FSTV0910_P1_DEMODOUT_ENABLE 0xf4bf0004 -#define FSTV0910_P1_DDEMOD_NSET 0xf4bf0002 +#define FSTV0910_P1_DIS_QPSK_1_4 0xf4bf40f0 +#define FSTV0910_P1_DEMOD_INVMODLST 0xf4bf3008 +#define FSTV0910_P1_DEMODOUT_ENABLE 0xf4bf2004 +#define FSTV0910_P1_DDEMOD_NSET 0xf4bf1002 #define FSTV0910_P1_MODCOD_NSTOCK 0xf4bf0001 /* P1_GAUSSR0 */ #define RSTV0910_P1_GAUSSR0 0xf4c0 -#define FSTV0910_P1_EN_CCIMODE 0xf4c00080 +#define FSTV0910_P1_EN_CCIMODE 0xf4c07080 #define FSTV0910_P1_R0_GAUSSIEN 0xf4c0007f /* P1_CCIR0 */ #define RSTV0910_P1_CCIR0 0xf4c1 -#define FSTV0910_P1_CCIDETECT_PLHONLY 0xf4c10080 +#define FSTV0910_P1_CCIDETECT_PLHONLY 0xf4c17080 #define FSTV0910_P1_R0_CCI 0xf4c1007f /* P1_CCIQUANT */ #define RSTV0910_P1_CCIQUANT 0xf4c2 -#define FSTV0910_P1_CCI_BETA 0xf4c200e0 +#define FSTV0910_P1_CCI_BETA 0xf4c250e0 #define FSTV0910_P1_CCI_QUANT 0xf4c2001f /* P1_CCITHRES */ @@ -2867,24 +2867,24 @@ /* P1_DSTATUS4 */ #define RSTV0910_P1_DSTATUS4 0xf4c5 -#define FSTV0910_P1_RAINFADE_DETECT 0xf4c50080 -#define FSTV0910_P1_NOTHRES2_FAIL 0xf4c50040 -#define FSTV0910_P1_NOTHRES1_FAIL 0xf4c50020 -#define FSTV0910_P1_DMDPROG_ERROR 0xf4c50004 -#define FSTV0910_P1_CSTENV_DETECT 0xf4c50002 +#define FSTV0910_P1_RAINFADE_DETECT 0xf4c57080 +#define FSTV0910_P1_NOTHRES2_FAIL 0xf4c56040 +#define FSTV0910_P1_NOTHRES1_FAIL 0xf4c55020 +#define FSTV0910_P1_DMDPROG_ERROR 0xf4c52004 +#define FSTV0910_P1_CSTENV_DETECT 0xf4c51002 #define FSTV0910_P1_DETECTION_TRIAX 0xf4c50001 /* P1_DMDRESCFG */ #define RSTV0910_P1_DMDRESCFG 0xf4c6 -#define FSTV0910_P1_DMDRES_RESET 0xf4c60080 -#define FSTV0910_P1_DMDRES_STRALL 0xf4c60008 -#define FSTV0910_P1_DMDRES_NEWONLY 0xf4c60004 -#define FSTV0910_P1_DMDRES_NOSTORE 0xf4c60002 +#define FSTV0910_P1_DMDRES_RESET 0xf4c67080 +#define FSTV0910_P1_DMDRES_STRALL 0xf4c63008 +#define FSTV0910_P1_DMDRES_NEWONLY 0xf4c62004 +#define FSTV0910_P1_DMDRES_NOSTORE 0xf4c61002 /* P1_DMDRESADR */ #define RSTV0910_P1_DMDRESADR 0xf4c7 -#define FSTV0910_P1_DMDRES_VALIDCFR 0xf4c70040 -#define FSTV0910_P1_DMDRES_MEMFULL 0xf4c70030 +#define FSTV0910_P1_DMDRES_VALIDCFR 0xf4c76040 +#define FSTV0910_P1_DMDRES_MEMFULL 0xf4c74030 #define FSTV0910_P1_DMDRES_RESNBR 0xf4c7000f /* P1_DMDRESDATA7 */ @@ -2953,29 +2953,29 @@ /* P1_FFECFG */ #define RSTV0910_P1_FFECFG 0xf4d8 -#define FSTV0910_P1_EQUALFFE_ON 0xf4d80040 -#define FSTV0910_P1_EQUAL_USEDSYMB 0xf4d80030 +#define FSTV0910_P1_EQUALFFE_ON 0xf4d86040 +#define FSTV0910_P1_EQUAL_USEDSYMB 0xf4d84030 #define FSTV0910_P1_MU_EQUALFFE 0xf4d80007 /* P1_TNRCFG2 */ #define RSTV0910_P1_TNRCFG2 0xf4e1 -#define FSTV0910_P1_TUN_IQSWAP 0xf4e10080 +#define FSTV0910_P1_TUN_IQSWAP 0xf4e17080 /* P1_SMAPCOEF7 */ #define RSTV0910_P1_SMAPCOEF7 0xf500 -#define FSTV0910_P1_DIS_QSCALE 0xf5000080 +#define FSTV0910_P1_DIS_QSCALE 0xf5007080 #define FSTV0910_P1_SMAPCOEF_Q_LLR12 0xf500017f /* P1_SMAPCOEF6 */ #define RSTV0910_P1_SMAPCOEF6 0xf501 -#define FSTV0910_P1_DIS_AGC2SCALE 0xf5010080 -#define FSTV0910_P1_ADJ_8PSKLLR1 0xf5010004 -#define FSTV0910_P1_OLD_8PSKLLR1 0xf5010002 +#define FSTV0910_P1_DIS_AGC2SCALE 0xf5017080 +#define FSTV0910_P1_ADJ_8PSKLLR1 0xf5012004 +#define FSTV0910_P1_OLD_8PSKLLR1 0xf5011002 #define FSTV0910_P1_DIS_AB8PSK 0xf5010001 /* P1_SMAPCOEF5 */ #define RSTV0910_P1_SMAPCOEF5 0xf502 -#define FSTV0910_P1_DIS_8SCALE 0xf5020080 +#define FSTV0910_P1_DIS_8SCALE 0xf5027080 #define FSTV0910_P1_SMAPCOEF_8P_LLR23 0xf502017f /* P1_SMAPCOEF4 */ @@ -2988,17 +2988,17 @@ /* P1_SMAPCOEF2 */ #define RSTV0910_P1_SMAPCOEF2 0xf505 -#define FSTV0910_P1_SMAPCOEF_32APSK_R2R3 0xf50501f0 +#define FSTV0910_P1_SMAPCOEF_32APSK_R2R3 0xf50541f0 #define FSTV0910_P1_SMAPCOEF_32APSK_LLR2 0xf505010f /* P1_SMAPCOEF1 */ #define RSTV0910_P1_SMAPCOEF1 0xf506 -#define FSTV0910_P1_DIS_16SCALE 0xf5060080 +#define FSTV0910_P1_DIS_16SCALE 0xf5067080 #define FSTV0910_P1_SMAPCOEF_32_LLR34 0xf506017f /* P1_SMAPCOEF0 */ #define RSTV0910_P1_SMAPCOEF0 0xf507 -#define FSTV0910_P1_DIS_32SCALE 0xf5070080 +#define FSTV0910_P1_DIS_32SCALE 0xf5077080 #define FSTV0910_P1_SMAPCOEF_32_LLR15 0xf507017f /* P1_NOSTHRES1 */ @@ -3015,20 +3015,20 @@ /* P1_RAINFADE */ #define RSTV0910_P1_RAINFADE 0xf50c -#define FSTV0910_P1_NOSTHRES_DATAT 0xf50c0080 -#define FSTV0910_P1_RAINFADE_CNLIMIT 0xf50c0070 +#define FSTV0910_P1_NOSTHRES_DATAT 0xf50c7080 +#define FSTV0910_P1_RAINFADE_CNLIMIT 0xf50c4070 #define FSTV0910_P1_RAINFADE_TIMEOUT 0xf50c0007 /* P1_NOSRAMCFG */ #define RSTV0910_P1_NOSRAMCFG 0xf50d -#define FSTV0910_P1_NOSRAM_ACTIVATION 0xf50d0030 -#define FSTV0910_P1_NOSRAM_CNRONLY 0xf50d0008 +#define FSTV0910_P1_NOSRAM_ACTIVATION 0xf50d4030 +#define FSTV0910_P1_NOSRAM_CNRONLY 0xf50d3008 #define FSTV0910_P1_NOSRAM_LGNCNR1 0xf50d0007 /* P1_NOSRAMPOS */ #define RSTV0910_P1_NOSRAMPOS 0xf50e -#define FSTV0910_P1_NOSRAM_LGNCNR0 0xf50e00f0 -#define FSTV0910_P1_NOSRAM_VALIDE 0xf50e0004 +#define FSTV0910_P1_NOSRAM_LGNCNR0 0xf50e40f0 +#define FSTV0910_P1_NOSRAM_VALIDE 0xf50e2004 #define FSTV0910_P1_NOSRAM_CNRVAL1 0xf50e0003 /* P1_NOSRAMVAL */ @@ -3057,16 +3057,16 @@ /* P1_VITSCALE */ #define RSTV0910_P1_VITSCALE 0xf532 -#define FSTV0910_P1_NVTH_NOSRANGE 0xf5320080 -#define FSTV0910_P1_VERROR_MAXMODE 0xf5320040 -#define FSTV0910_P1_NSLOWSN_LOCKED 0xf5320008 -#define FSTV0910_P1_DIS_RSFLOCK 0xf5320002 +#define FSTV0910_P1_NVTH_NOSRANGE 0xf5327080 +#define FSTV0910_P1_VERROR_MAXMODE 0xf5326040 +#define FSTV0910_P1_NSLOWSN_LOCKED 0xf5323008 +#define FSTV0910_P1_DIS_RSFLOCK 0xf5321002 /* P1_FECM */ #define RSTV0910_P1_FECM 0xf533 -#define FSTV0910_P1_DSS_DVB 0xf5330080 -#define FSTV0910_P1_DSS_SRCH 0xf5330010 -#define FSTV0910_P1_SYNCVIT 0xf5330002 +#define FSTV0910_P1_DSS_DVB 0xf5337080 +#define FSTV0910_P1_DSS_SRCH 0xf5334010 +#define FSTV0910_P1_SYNCVIT 0xf5331002 #define FSTV0910_P1_IQINV 0xf5330001 /* P1_VTH12 */ @@ -3103,26 +3103,26 @@ /* P1_PRVIT */ #define RSTV0910_P1_PRVIT 0xf53c -#define FSTV0910_P1_DIS_VTHLOCK 0xf53c0040 -#define FSTV0910_P1_E7_8VIT 0xf53c0020 -#define FSTV0910_P1_E6_7VIT 0xf53c0010 -#define FSTV0910_P1_E5_6VIT 0xf53c0008 -#define FSTV0910_P1_E3_4VIT 0xf53c0004 -#define FSTV0910_P1_E2_3VIT 0xf53c0002 +#define FSTV0910_P1_DIS_VTHLOCK 0xf53c6040 +#define FSTV0910_P1_E7_8VIT 0xf53c5020 +#define FSTV0910_P1_E6_7VIT 0xf53c4010 +#define FSTV0910_P1_E5_6VIT 0xf53c3008 +#define FSTV0910_P1_E3_4VIT 0xf53c2004 +#define FSTV0910_P1_E2_3VIT 0xf53c1002 #define FSTV0910_P1_E1_2VIT 0xf53c0001 /* P1_VAVSRVIT */ #define RSTV0910_P1_VAVSRVIT 0xf53d -#define FSTV0910_P1_AMVIT 0xf53d0080 -#define FSTV0910_P1_FROZENVIT 0xf53d0040 -#define FSTV0910_P1_SNVIT 0xf53d0030 -#define FSTV0910_P1_TOVVIT 0xf53d000c +#define FSTV0910_P1_AMVIT 0xf53d7080 +#define FSTV0910_P1_FROZENVIT 0xf53d6040 +#define FSTV0910_P1_SNVIT 0xf53d4030 +#define FSTV0910_P1_TOVVIT 0xf53d200c #define FSTV0910_P1_HYPVIT 0xf53d0003 /* P1_VSTATUSVIT */ #define RSTV0910_P1_VSTATUSVIT 0xf53e -#define FSTV0910_P1_PRFVIT 0xf53e0010 -#define FSTV0910_P1_LOCKEDVIT 0xf53e0008 +#define FSTV0910_P1_PRFVIT 0xf53e4010 +#define FSTV0910_P1_LOCKEDVIT 0xf53e3008 /* P1_VTHINUSE */ #define RSTV0910_P1_VTHINUSE 0xf53f @@ -3162,32 +3162,32 @@ /* P1_PDELCTRL0 */ #define RSTV0910_P1_PDELCTRL0 0xf54f -#define FSTV0910_P1_ISIOBS_MODE 0xf54f0030 +#define FSTV0910_P1_ISIOBS_MODE 0xf54f4030 /* P1_PDELCTRL1 */ #define RSTV0910_P1_PDELCTRL1 0xf550 -#define FSTV0910_P1_INV_MISMASK 0xf5500080 -#define FSTV0910_P1_FILTER_EN 0xf5500020 -#define FSTV0910_P1_HYSTEN 0xf5500008 -#define FSTV0910_P1_HYSTSWRST 0xf5500004 -#define FSTV0910_P1_EN_MIS00 0xf5500002 +#define FSTV0910_P1_INV_MISMASK 0xf5507080 +#define FSTV0910_P1_FILTER_EN 0xf5505020 +#define FSTV0910_P1_HYSTEN 0xf5503008 +#define FSTV0910_P1_HYSTSWRST 0xf5502004 +#define FSTV0910_P1_EN_MIS00 0xf5501002 #define FSTV0910_P1_ALGOSWRST 0xf5500001 /* P1_PDELCTRL2 */ #define RSTV0910_P1_PDELCTRL2 0xf551 -#define FSTV0910_P1_FORCE_CONTINUOUS 0xf5510080 -#define FSTV0910_P1_RESET_UPKO_COUNT 0xf5510040 -#define FSTV0910_P1_USER_PKTDELIN_NB 0xf5510020 -#define FSTV0910_P1_FRAME_MODE 0xf5510002 +#define FSTV0910_P1_FORCE_CONTINUOUS 0xf5517080 +#define FSTV0910_P1_RESET_UPKO_COUNT 0xf5516040 +#define FSTV0910_P1_USER_PKTDELIN_NB 0xf5515020 +#define FSTV0910_P1_FRAME_MODE 0xf5511002 /* P1_HYSTTHRESH */ #define RSTV0910_P1_HYSTTHRESH 0xf554 -#define FSTV0910_P1_DELIN_LOCKTHRES 0xf55400f0 +#define FSTV0910_P1_DELIN_LOCKTHRES 0xf55440f0 #define FSTV0910_P1_DELIN_UNLOCKTHRES 0xf554000f /* P1_UPLCCST0 */ #define RSTV0910_P1_UPLCCST0 0xf558 -#define FSTV0910_P1_UPL_CST0 0xf55800f8 +#define FSTV0910_P1_UPL_CST0 0xf55830f8 #define FSTV0910_P1_UPL_MODE 0xf5580007 /* P1_ISIENTRY */ @@ -3236,16 +3236,16 @@ /* P1_PDELSTATUS1 */ #define RSTV0910_P1_PDELSTATUS1 0xf569 -#define FSTV0910_P1_PKTDELIN_DELOCK 0xf5690080 -#define FSTV0910_P1_SYNCDUPDFL_BADDFL 0xf5690040 -#define FSTV0910_P1_UNACCEPTED_STREAM 0xf5690010 -#define FSTV0910_P1_BCH_ERROR_FLAG 0xf5690008 -#define FSTV0910_P1_PKTDELIN_LOCK 0xf5690002 +#define FSTV0910_P1_PKTDELIN_DELOCK 0xf5697080 +#define FSTV0910_P1_SYNCDUPDFL_BADDFL 0xf5696040 +#define FSTV0910_P1_UNACCEPTED_STREAM 0xf5694010 +#define FSTV0910_P1_BCH_ERROR_FLAG 0xf5693008 +#define FSTV0910_P1_PKTDELIN_LOCK 0xf5691002 #define FSTV0910_P1_FIRST_LOCK 0xf5690001 /* P1_PDELSTATUS2 */ #define RSTV0910_P1_PDELSTATUS2 0xf56a -#define FSTV0910_P1_FRAME_MODCOD 0xf56a007c +#define FSTV0910_P1_FRAME_MODCOD 0xf56a207c #define FSTV0910_P1_FRAME_TYPE 0xf56a0003 /* P1_BBFCRCKO1 */ @@ -3266,92 +3266,92 @@ /* P1_PDELCTRL3 */ #define RSTV0910_P1_PDELCTRL3 0xf56f -#define FSTV0910_P1_NOFIFO_BCHERR 0xf56f0020 -#define FSTV0910_P1_PKTDELIN_DELACMERR 0xf56f0010 +#define FSTV0910_P1_NOFIFO_BCHERR 0xf56f5020 +#define FSTV0910_P1_PKTDELIN_DELACMERR 0xf56f4010 /* P1_TSSTATEM */ #define RSTV0910_P1_TSSTATEM 0xf570 -#define FSTV0910_P1_TSDIL_ON 0xf5700080 -#define FSTV0910_P1_TSRS_ON 0xf5700020 -#define FSTV0910_P1_TSDESCRAMB_ON 0xf5700010 -#define FSTV0910_P1_TSFRAME_MODE 0xf5700008 -#define FSTV0910_P1_TS_DISABLE 0xf5700004 -#define FSTV0910_P1_TSACM_MODE 0xf5700002 +#define FSTV0910_P1_TSDIL_ON 0xf5707080 +#define FSTV0910_P1_TSRS_ON 0xf5705020 +#define FSTV0910_P1_TSDESCRAMB_ON 0xf5704010 +#define FSTV0910_P1_TSFRAME_MODE 0xf5703008 +#define FSTV0910_P1_TS_DISABLE 0xf5702004 +#define FSTV0910_P1_TSACM_MODE 0xf5701002 #define FSTV0910_P1_TSOUT_NOSYNC 0xf5700001 /* P1_TSSTATEL */ #define RSTV0910_P1_TSSTATEL 0xf571 -#define FSTV0910_P1_TSNOSYNCBYTE 0xf5710080 -#define FSTV0910_P1_TSPARITY_ON 0xf5710040 -#define FSTV0910_P1_TSISSYI_ON 0xf5710008 -#define FSTV0910_P1_TSNPD_ON 0xf5710004 -#define FSTV0910_P1_TSCRC8_ON 0xf5710002 +#define FSTV0910_P1_TSNOSYNCBYTE 0xf5717080 +#define FSTV0910_P1_TSPARITY_ON 0xf5716040 +#define FSTV0910_P1_TSISSYI_ON 0xf5713008 +#define FSTV0910_P1_TSNPD_ON 0xf5712004 +#define FSTV0910_P1_TSCRC8_ON 0xf5711002 #define FSTV0910_P1_TSDSS_PACKET 0xf5710001 /* P1_TSCFGH */ #define RSTV0910_P1_TSCFGH 0xf572 -#define FSTV0910_P1_TSFIFO_DVBCI 0xf5720080 -#define FSTV0910_P1_TSFIFO_SERIAL 0xf5720040 -#define FSTV0910_P1_TSFIFO_TEIUPDATE 0xf5720020 -#define FSTV0910_P1_TSFIFO_DUTY50 0xf5720010 -#define FSTV0910_P1_TSFIFO_HSGNLOUT 0xf5720008 -#define FSTV0910_P1_TSFIFO_ERRMODE 0xf5720006 +#define FSTV0910_P1_TSFIFO_DVBCI 0xf5727080 +#define FSTV0910_P1_TSFIFO_SERIAL 0xf5726040 +#define FSTV0910_P1_TSFIFO_TEIUPDATE 0xf5725020 +#define FSTV0910_P1_TSFIFO_DUTY50 0xf5724010 +#define FSTV0910_P1_TSFIFO_HSGNLOUT 0xf5723008 +#define FSTV0910_P1_TSFIFO_ERRMODE 0xf5721006 #define FSTV0910_P1_RST_HWARE 0xf5720001 /* P1_TSCFGM */ #define RSTV0910_P1_TSCFGM 0xf573 -#define FSTV0910_P1_TSFIFO_MANSPEED 0xf57300c0 -#define FSTV0910_P1_TSFIFO_PERMDATA 0xf5730020 -#define FSTV0910_P1_TSFIFO_NONEWSGNL 0xf5730010 +#define FSTV0910_P1_TSFIFO_MANSPEED 0xf57360c0 +#define FSTV0910_P1_TSFIFO_PERMDATA 0xf5735020 +#define FSTV0910_P1_TSFIFO_NONEWSGNL 0xf5734010 #define FSTV0910_P1_TSFIFO_INVDATA 0xf5730001 /* P1_TSCFGL */ #define RSTV0910_P1_TSCFGL 0xf574 -#define FSTV0910_P1_TSFIFO_BCLKDEL1CK 0xf57400c0 -#define FSTV0910_P1_BCHERROR_MODE 0xf5740030 -#define FSTV0910_P1_TSFIFO_NSGNL2DATA 0xf5740008 -#define FSTV0910_P1_TSFIFO_EMBINDVB 0xf5740004 +#define FSTV0910_P1_TSFIFO_BCLKDEL1CK 0xf57460c0 +#define FSTV0910_P1_BCHERROR_MODE 0xf5744030 +#define FSTV0910_P1_TSFIFO_NSGNL2DATA 0xf5743008 +#define FSTV0910_P1_TSFIFO_EMBINDVB 0xf5742004 #define FSTV0910_P1_TSFIFO_BITSPEED 0xf5740003 /* P1_TSSYNC */ #define RSTV0910_P1_TSSYNC 0xf575 -#define FSTV0910_P1_TSFIFO_SYNCMODE 0xf5750018 +#define FSTV0910_P1_TSFIFO_SYNCMODE 0xf5753018 /* P1_TSINSDELH */ #define RSTV0910_P1_TSINSDELH 0xf576 -#define FSTV0910_P1_TSDEL_SYNCBYTE 0xf5760080 -#define FSTV0910_P1_TSDEL_XXHEADER 0xf5760040 -#define FSTV0910_P1_TSDEL_DATAFIELD 0xf5760010 -#define FSTV0910_P1_TSINSDEL_RSPARITY 0xf5760002 +#define FSTV0910_P1_TSDEL_SYNCBYTE 0xf5767080 +#define FSTV0910_P1_TSDEL_XXHEADER 0xf5766040 +#define FSTV0910_P1_TSDEL_DATAFIELD 0xf5764010 +#define FSTV0910_P1_TSINSDEL_RSPARITY 0xf5761002 #define FSTV0910_P1_TSINSDEL_CRC8 0xf5760001 /* P1_TSINSDELM */ #define RSTV0910_P1_TSINSDELM 0xf577 -#define FSTV0910_P1_TSINS_EMODCOD 0xf5770010 -#define FSTV0910_P1_TSINS_TOKEN 0xf5770008 -#define FSTV0910_P1_TSINS_XXXERR 0xf5770004 -#define FSTV0910_P1_TSINS_MATYPE 0xf5770002 +#define FSTV0910_P1_TSINS_EMODCOD 0xf5774010 +#define FSTV0910_P1_TSINS_TOKEN 0xf5773008 +#define FSTV0910_P1_TSINS_XXXERR 0xf5772004 +#define FSTV0910_P1_TSINS_MATYPE 0xf5771002 #define FSTV0910_P1_TSINS_UPL 0xf5770001 /* P1_TSINSDELL */ #define RSTV0910_P1_TSINSDELL 0xf578 -#define FSTV0910_P1_TSINS_DFL 0xf5780080 -#define FSTV0910_P1_TSINS_SYNCD 0xf5780040 -#define FSTV0910_P1_TSINS_BLOCLEN 0xf5780020 -#define FSTV0910_P1_TSINS_SIGPCOUNT 0xf5780010 -#define FSTV0910_P1_TSINS_FIFO 0xf5780008 -#define FSTV0910_P1_TSINS_REALPACK 0xf5780004 -#define FSTV0910_P1_TSINS_TSCONFIG 0xf5780002 +#define FSTV0910_P1_TSINS_DFL 0xf5787080 +#define FSTV0910_P1_TSINS_SYNCD 0xf5786040 +#define FSTV0910_P1_TSINS_BLOCLEN 0xf5785020 +#define FSTV0910_P1_TSINS_SIGPCOUNT 0xf5784010 +#define FSTV0910_P1_TSINS_FIFO 0xf5783008 +#define FSTV0910_P1_TSINS_REALPACK 0xf5782004 +#define FSTV0910_P1_TSINS_TSCONFIG 0xf5781002 #define FSTV0910_P1_TSINS_LATENCY 0xf5780001 /* P1_TSDIVN */ #define RSTV0910_P1_TSDIVN 0xf579 -#define FSTV0910_P1_TSFIFO_SPEEDMODE 0xf57900c0 +#define FSTV0910_P1_TSFIFO_SPEEDMODE 0xf57960c0 #define FSTV0910_P1_TSFIFO_RISEOK 0xf5790007 /* P1_TSCFG4 */ #define RSTV0910_P1_TSCFG4 0xf57a -#define FSTV0910_P1_TSFIFO_TSSPEEDMODE 0xf57a00c0 +#define FSTV0910_P1_TSFIFO_TSSPEEDMODE 0xf57a60c0 /* P1_TSSPEED */ #define RSTV0910_P1_TSSPEED 0xf580 @@ -3359,18 +3359,18 @@ /* P1_TSSTATUS */ #define RSTV0910_P1_TSSTATUS 0xf581 -#define FSTV0910_P1_TSFIFO_LINEOK 0xf5810080 -#define FSTV0910_P1_TSFIFO_ERROR 0xf5810040 -#define FSTV0910_P1_TSFIFO_NOSYNC 0xf5810010 -#define FSTV0910_P1_TSREGUL_ERROR 0xf5810004 +#define FSTV0910_P1_TSFIFO_LINEOK 0xf5817080 +#define FSTV0910_P1_TSFIFO_ERROR 0xf5816040 +#define FSTV0910_P1_TSFIFO_NOSYNC 0xf5814010 +#define FSTV0910_P1_TSREGUL_ERROR 0xf5812004 #define FSTV0910_P1_DIL_READY 0xf5810001 /* P1_TSSTATUS2 */ #define RSTV0910_P1_TSSTATUS2 0xf582 -#define FSTV0910_P1_TSFIFO_DEMODSEL 0xf5820080 -#define FSTV0910_P1_TSFIFOSPEED_STORE 0xf5820040 -#define FSTV0910_P1_DILXX_RESET 0xf5820020 -#define FSTV0910_P1_SCRAMBDETECT 0xf5820002 +#define FSTV0910_P1_TSFIFO_DEMODSEL 0xf5827080 +#define FSTV0910_P1_TSFIFOSPEED_STORE 0xf5826040 +#define FSTV0910_P1_DILXX_RESET 0xf5825020 +#define FSTV0910_P1_SCRAMBDETECT 0xf5821002 /* P1_TSBITRATE1 */ #define RSTV0910_P1_TSBITRATE1 0xf583 @@ -3382,7 +3382,7 @@ /* P1_TSPACKLEN1 */ #define RSTV0910_P1_TSPACKLEN1 0xf585 -#define FSTV0910_P1_TSFIFO_PACKCPT 0xf58500e0 +#define FSTV0910_P1_TSFIFO_PACKCPT 0xf58550e0 /* P1_TSDLY2 */ #define RSTV0910_P1_TSDLY2 0xf589 @@ -3402,8 +3402,8 @@ /* P1_TSBUFSTAT2 */ #define RSTV0910_P1_TSBUFSTAT2 0xf58d -#define FSTV0910_P1_TSISCR_3BYTES 0xf58d0080 -#define FSTV0910_P1_TSISCR_NEWDATA 0xf58d0040 +#define FSTV0910_P1_TSISCR_3BYTES 0xf58d7080 +#define FSTV0910_P1_TSISCR_NEWDATA 0xf58d6040 #define FSTV0910_P1_TSISCR_BUFSTAT2 0xf58d003f /* P1_TSBUFSTAT1 */ @@ -3416,13 +3416,13 @@ /* P1_TSDEBUGL */ #define RSTV0910_P1_TSDEBUGL 0xf591 -#define FSTV0910_P1_TSFIFO_ERROR_EVNT 0xf5910004 +#define FSTV0910_P1_TSFIFO_ERROR_EVNT 0xf5912004 #define FSTV0910_P1_TSFIFO_OVERFLOWM 0xf5910001 /* P1_TSDLYSET2 */ #define RSTV0910_P1_TSDLYSET2 0xf592 -#define FSTV0910_P1_SOFFIFO_OFFSET 0xf59200c0 -#define FSTV0910_P1_HYSTERESIS_THRESHOLD 0xf5920030 +#define FSTV0910_P1_SOFFIFO_OFFSET 0xf59260c0 +#define FSTV0910_P1_HYSTERESIS_THRESHOLD 0xf5924030 #define FSTV0910_P1_SOFFIFO_SYMBOFFS2 0xf592000f /* P1_TSDLYSET1 */ @@ -3435,12 +3435,12 @@ /* P1_ERRCTRL1 */ #define RSTV0910_P1_ERRCTRL1 0xf598 -#define FSTV0910_P1_ERR_SOURCE1 0xf59800f0 +#define FSTV0910_P1_ERR_SOURCE1 0xf59840f0 #define FSTV0910_P1_NUM_EVENT1 0xf5980007 /* P1_ERRCNT12 */ #define RSTV0910_P1_ERRCNT12 0xf599 -#define FSTV0910_P1_ERRCNT1_OLDVALUE 0xf5990080 +#define FSTV0910_P1_ERRCNT1_OLDVALUE 0xf5997080 #define FSTV0910_P1_ERR_CNT12 0xf599007f /* P1_ERRCNT11 */ @@ -3453,12 +3453,12 @@ /* P1_ERRCTRL2 */ #define RSTV0910_P1_ERRCTRL2 0xf59c -#define FSTV0910_P1_ERR_SOURCE2 0xf59c00f0 +#define FSTV0910_P1_ERR_SOURCE2 0xf59c40f0 #define FSTV0910_P1_NUM_EVENT2 0xf59c0007 /* P1_ERRCNT22 */ #define RSTV0910_P1_ERRCNT22 0xf59d -#define FSTV0910_P1_ERRCNT2_OLDVALUE 0xf59d0080 +#define FSTV0910_P1_ERRCNT2_OLDVALUE 0xf59d7080 #define FSTV0910_P1_ERR_CNT22 0xf59d007f /* P1_ERRCNT21 */ @@ -3471,39 +3471,39 @@ /* P1_FECSPY */ #define RSTV0910_P1_FECSPY 0xf5a0 -#define FSTV0910_P1_SPY_ENABLE 0xf5a00080 -#define FSTV0910_P1_NO_SYNCBYTE 0xf5a00040 -#define FSTV0910_P1_SERIAL_MODE 0xf5a00020 -#define FSTV0910_P1_UNUSUAL_PACKET 0xf5a00010 -#define FSTV0910_P1_BERMETER_DATAMODE 0xf5a0000c -#define FSTV0910_P1_BERMETER_LMODE 0xf5a00002 +#define FSTV0910_P1_SPY_ENABLE 0xf5a07080 +#define FSTV0910_P1_NO_SYNCBYTE 0xf5a06040 +#define FSTV0910_P1_SERIAL_MODE 0xf5a05020 +#define FSTV0910_P1_UNUSUAL_PACKET 0xf5a04010 +#define FSTV0910_P1_BERMETER_DATAMODE 0xf5a0200c +#define FSTV0910_P1_BERMETER_LMODE 0xf5a01002 #define FSTV0910_P1_BERMETER_RESET 0xf5a00001 /* P1_FSPYCFG */ #define RSTV0910_P1_FSPYCFG 0xf5a1 -#define FSTV0910_P1_FECSPY_INPUT 0xf5a100c0 -#define FSTV0910_P1_RST_ON_ERROR 0xf5a10020 -#define FSTV0910_P1_ONE_SHOT 0xf5a10010 -#define FSTV0910_P1_I2C_MODE 0xf5a1000c +#define FSTV0910_P1_FECSPY_INPUT 0xf5a160c0 +#define FSTV0910_P1_RST_ON_ERROR 0xf5a15020 +#define FSTV0910_P1_ONE_SHOT 0xf5a14010 +#define FSTV0910_P1_I2C_MODE 0xf5a1200c #define FSTV0910_P1_SPY_HYSTERESIS 0xf5a10003 /* P1_FSPYDATA */ #define RSTV0910_P1_FSPYDATA 0xf5a2 -#define FSTV0910_P1_SPY_STUFFING 0xf5a20080 -#define FSTV0910_P1_SPY_CNULLPKT 0xf5a20020 +#define FSTV0910_P1_SPY_STUFFING 0xf5a27080 +#define FSTV0910_P1_SPY_CNULLPKT 0xf5a25020 #define FSTV0910_P1_SPY_OUTDATA_MODE 0xf5a2001f /* P1_FSPYOUT */ #define RSTV0910_P1_FSPYOUT 0xf5a3 -#define FSTV0910_P1_FSPY_DIRECT 0xf5a30080 +#define FSTV0910_P1_FSPY_DIRECT 0xf5a37080 #define FSTV0910_P1_STUFF_MODE 0xf5a30007 /* P1_FSTATUS */ #define RSTV0910_P1_FSTATUS 0xf5a4 -#define FSTV0910_P1_SPY_ENDSIM 0xf5a40080 -#define FSTV0910_P1_VALID_SIM 0xf5a40040 -#define FSTV0910_P1_FOUND_SIGNAL 0xf5a40020 -#define FSTV0910_P1_DSS_SYNCBYTE 0xf5a40010 +#define FSTV0910_P1_SPY_ENDSIM 0xf5a47080 +#define FSTV0910_P1_VALID_SIM 0xf5a46040 +#define FSTV0910_P1_FOUND_SIGNAL 0xf5a45020 +#define FSTV0910_P1_DSS_SYNCBYTE 0xf5a44010 #define FSTV0910_P1_RESULT_STATE 0xf5a4000f /* P1_FBERCPT4 */ @@ -3540,8 +3540,8 @@ /* P1_FSPYBER */ #define RSTV0910_P1_FSPYBER 0xf5b2 -#define FSTV0910_P1_FSPYBER_SYNCBYTE 0xf5b20010 -#define FSTV0910_P1_FSPYBER_UNSYNC 0xf5b20008 +#define FSTV0910_P1_FSPYBER_SYNCBYTE 0xf5b24010 +#define FSTV0910_P1_FSPYBER_UNSYNC 0xf5b23008 #define FSTV0910_P1_FSPYBER_CTIME 0xf5b20007 /* P1_SFERROR */ @@ -3550,60 +3550,60 @@ /* P1_SFECSTATUS */ #define RSTV0910_P1_SFECSTATUS 0xf5c3 -#define FSTV0910_P1_SFEC_ON 0xf5c30080 -#define FSTV0910_P1_SFEC_OFF 0xf5c30040 -#define FSTV0910_P1_LOCKEDSFEC 0xf5c30008 -#define FSTV0910_P1_SFEC_DELOCK 0xf5c30004 -#define FSTV0910_P1_SFEC_DEMODSEL 0xf5c30002 +#define FSTV0910_P1_SFEC_ON 0xf5c37080 +#define FSTV0910_P1_SFEC_OFF 0xf5c36040 +#define FSTV0910_P1_LOCKEDSFEC 0xf5c33008 +#define FSTV0910_P1_SFEC_DELOCK 0xf5c32004 +#define FSTV0910_P1_SFEC_DEMODSEL 0xf5c31002 #define FSTV0910_P1_SFEC_OVFON 0xf5c30001 /* P1_SFKDIV12 */ #define RSTV0910_P1_SFKDIV12 0xf5c4 -#define FSTV0910_P1_SFECKDIV12_MAN 0xf5c40080 +#define FSTV0910_P1_SFECKDIV12_MAN 0xf5c47080 /* P1_SFKDIV23 */ #define RSTV0910_P1_SFKDIV23 0xf5c5 -#define FSTV0910_P1_SFECKDIV23_MAN 0xf5c50080 +#define FSTV0910_P1_SFECKDIV23_MAN 0xf5c57080 /* P1_SFKDIV34 */ #define RSTV0910_P1_SFKDIV34 0xf5c6 -#define FSTV0910_P1_SFECKDIV34_MAN 0xf5c60080 +#define FSTV0910_P1_SFECKDIV34_MAN 0xf5c67080 /* P1_SFKDIV56 */ #define RSTV0910_P1_SFKDIV56 0xf5c7 -#define FSTV0910_P1_SFECKDIV56_MAN 0xf5c70080 +#define FSTV0910_P1_SFECKDIV56_MAN 0xf5c77080 /* P1_SFKDIV67 */ #define RSTV0910_P1_SFKDIV67 0xf5c8 -#define FSTV0910_P1_SFECKDIV67_MAN 0xf5c80080 +#define FSTV0910_P1_SFECKDIV67_MAN 0xf5c87080 /* P1_SFKDIV78 */ #define RSTV0910_P1_SFKDIV78 0xf5c9 -#define FSTV0910_P1_SFECKDIV78_MAN 0xf5c90080 +#define FSTV0910_P1_SFECKDIV78_MAN 0xf5c97080 /* P1_SFSTATUS */ #define RSTV0910_P1_SFSTATUS 0xf5cc -#define FSTV0910_P1_SFEC_LINEOK 0xf5cc0080 -#define FSTV0910_P1_SFEC_ERROR 0xf5cc0040 -#define FSTV0910_P1_SFEC_DATA7 0xf5cc0020 -#define FSTV0910_P1_SFEC_PKTDNBRFAIL 0xf5cc0010 -#define FSTV0910_P1_TSSFEC_DEMODSEL 0xf5cc0008 -#define FSTV0910_P1_SFEC_NOSYNC 0xf5cc0004 -#define FSTV0910_P1_SFEC_UNREGULA 0xf5cc0002 +#define FSTV0910_P1_SFEC_LINEOK 0xf5cc7080 +#define FSTV0910_P1_SFEC_ERROR 0xf5cc6040 +#define FSTV0910_P1_SFEC_DATA7 0xf5cc5020 +#define FSTV0910_P1_SFEC_PKTDNBRFAIL 0xf5cc4010 +#define FSTV0910_P1_TSSFEC_DEMODSEL 0xf5cc3008 +#define FSTV0910_P1_SFEC_NOSYNC 0xf5cc2004 +#define FSTV0910_P1_SFEC_UNREGULA 0xf5cc1002 #define FSTV0910_P1_SFEC_READY 0xf5cc0001 /* P1_SFDLYSET2 */ #define RSTV0910_P1_SFDLYSET2 0xf5d0 -#define FSTV0910_P1_SFEC_DISABLE 0xf5d00002 +#define FSTV0910_P1_SFEC_DISABLE 0xf5d01002 /* P1_SFERRCTRL */ #define RSTV0910_P1_SFERRCTRL 0xf5d8 -#define FSTV0910_P1_SFEC_ERR_SOURCE 0xf5d800f0 +#define FSTV0910_P1_SFEC_ERR_SOURCE 0xf5d840f0 #define FSTV0910_P1_SFEC_NUM_EVENT 0xf5d80007 /* P1_SFERRCNT2 */ #define RSTV0910_P1_SFERRCNT2 0xf5d9 -#define FSTV0910_P1_SFERRC_OLDVALUE 0xf5d90080 +#define FSTV0910_P1_SFERRC_OLDVALUE 0xf5d97080 #define FSTV0910_P1_SFEC_ERR_CNT2 0xf5d9007f /* P1_SFERRCNT1 */ @@ -3616,66 +3616,66 @@ /* RCCFG2 */ #define RSTV0910_RCCFG2 0xf600 -#define FSTV0910_TSRCFIFO_DVBCI 0xf6000080 -#define FSTV0910_TSRCFIFO_SERIAL 0xf6000040 -#define FSTV0910_TSRCFIFO_DISABLE 0xf6000020 -#define FSTV0910_TSFIFO_2TORC 0xf6000010 -#define FSTV0910_TSRCFIFO_HSGNLOUT 0xf6000008 -#define FSTV0910_TSRCFIFO_ERRMODE 0xf6000006 +#define FSTV0910_TSRCFIFO_DVBCI 0xf6007080 +#define FSTV0910_TSRCFIFO_SERIAL 0xf6006040 +#define FSTV0910_TSRCFIFO_DISABLE 0xf6005020 +#define FSTV0910_TSFIFO_2TORC 0xf6004010 +#define FSTV0910_TSRCFIFO_HSGNLOUT 0xf6003008 +#define FSTV0910_TSRCFIFO_ERRMODE 0xf6001006 /* RCCFG1 */ #define RSTV0910_RCCFG1 0xf601 -#define FSTV0910_TSRCFIFO_MANSPEED 0xf60100c0 -#define FSTV0910_TSRCFIFO_PERMDATA 0xf6010020 -#define FSTV0910_TSRCFIFO_NONEWSGNL 0xf6010010 +#define FSTV0910_TSRCFIFO_MANSPEED 0xf60160c0 +#define FSTV0910_TSRCFIFO_PERMDATA 0xf6015020 +#define FSTV0910_TSRCFIFO_NONEWSGNL 0xf6014010 #define FSTV0910_TSRCFIFO_INVDATA 0xf6010001 /* RCCFG0 */ #define RSTV0910_RCCFG0 0xf602 -#define FSTV0910_TSRCFIFO_BCLKDEL1CK 0xf60200c0 -#define FSTV0910_TSRCFIFO_DUTY50 0xf6020010 -#define FSTV0910_TSRCFIFO_NSGNL2DATA 0xf6020008 -#define FSTV0910_TSRCFIFO_NPDSGNL 0xf6020004 +#define FSTV0910_TSRCFIFO_BCLKDEL1CK 0xf60260c0 +#define FSTV0910_TSRCFIFO_DUTY50 0xf6024010 +#define FSTV0910_TSRCFIFO_NSGNL2DATA 0xf6023008 +#define FSTV0910_TSRCFIFO_NPDSGNL 0xf6022004 /* RCINSDEL2 */ #define RSTV0910_RCINSDEL2 0xf603 -#define FSTV0910_TSRCDEL_SYNCBYTE 0xf6030080 -#define FSTV0910_TSRCDEL_XXHEADER 0xf6030040 -#define FSTV0910_TSRCDEL_BBHEADER 0xf6030020 -#define FSTV0910_TSRCDEL_DATAFIELD 0xf6030010 -#define FSTV0910_TSRCINSDEL_ISCR 0xf6030008 -#define FSTV0910_TSRCINSDEL_NPD 0xf6030004 -#define FSTV0910_TSRCINSDEL_RSPARITY 0xf6030002 +#define FSTV0910_TSRCDEL_SYNCBYTE 0xf6037080 +#define FSTV0910_TSRCDEL_XXHEADER 0xf6036040 +#define FSTV0910_TSRCDEL_BBHEADER 0xf6035020 +#define FSTV0910_TSRCDEL_DATAFIELD 0xf6034010 +#define FSTV0910_TSRCINSDEL_ISCR 0xf6033008 +#define FSTV0910_TSRCINSDEL_NPD 0xf6032004 +#define FSTV0910_TSRCINSDEL_RSPARITY 0xf6031002 #define FSTV0910_TSRCINSDEL_CRC8 0xf6030001 /* RCINSDEL1 */ #define RSTV0910_RCINSDEL1 0xf604 -#define FSTV0910_TSRCINS_BBPADDING 0xf6040080 -#define FSTV0910_TSRCINS_BCHFEC 0xf6040040 -#define FSTV0910_TSRCINS_EMODCOD 0xf6040010 -#define FSTV0910_TSRCINS_TOKEN 0xf6040008 -#define FSTV0910_TSRCINS_XXXERR 0xf6040004 -#define FSTV0910_TSRCINS_MATYPE 0xf6040002 +#define FSTV0910_TSRCINS_BBPADDING 0xf6047080 +#define FSTV0910_TSRCINS_BCHFEC 0xf6046040 +#define FSTV0910_TSRCINS_EMODCOD 0xf6044010 +#define FSTV0910_TSRCINS_TOKEN 0xf6043008 +#define FSTV0910_TSRCINS_XXXERR 0xf6042004 +#define FSTV0910_TSRCINS_MATYPE 0xf6041002 #define FSTV0910_TSRCINS_UPL 0xf6040001 /* RCINSDEL0 */ #define RSTV0910_RCINSDEL0 0xf605 -#define FSTV0910_TSRCINS_DFL 0xf6050080 -#define FSTV0910_TSRCINS_SYNCD 0xf6050040 -#define FSTV0910_TSRCINS_BLOCLEN 0xf6050020 -#define FSTV0910_TSRCINS_SIGPCOUNT 0xf6050010 -#define FSTV0910_TSRCINS_FIFO 0xf6050008 -#define FSTV0910_TSRCINS_REALPACK 0xf6050004 -#define FSTV0910_TSRCINS_TSCONFIG 0xf6050002 +#define FSTV0910_TSRCINS_DFL 0xf6057080 +#define FSTV0910_TSRCINS_SYNCD 0xf6056040 +#define FSTV0910_TSRCINS_BLOCLEN 0xf6055020 +#define FSTV0910_TSRCINS_SIGPCOUNT 0xf6054010 +#define FSTV0910_TSRCINS_FIFO 0xf6053008 +#define FSTV0910_TSRCINS_REALPACK 0xf6052004 +#define FSTV0910_TSRCINS_TSCONFIG 0xf6051002 #define FSTV0910_TSRCINS_LATENCY 0xf6050001 /* RCSTATUS */ #define RSTV0910_RCSTATUS 0xf606 -#define FSTV0910_TSRCFIFO_LINEOK 0xf6060080 -#define FSTV0910_TSRCFIFO_ERROR 0xf6060040 -#define FSTV0910_TSRCREGUL_ERROR 0xf6060010 -#define FSTV0910_TSRCFIFO_DEMODSEL 0xf6060008 -#define FSTV0910_TSRCFIFOSPEED_STORE 0xf6060004 +#define FSTV0910_TSRCFIFO_LINEOK 0xf6067080 +#define FSTV0910_TSRCFIFO_ERROR 0xf6066040 +#define FSTV0910_TSRCREGUL_ERROR 0xf6064010 +#define FSTV0910_TSRCFIFO_DEMODSEL 0xf6063008 +#define FSTV0910_TSRCFIFOSPEED_STORE 0xf6062004 #define FSTV0910_TSRCSPEED_IMPOSSIBLE 0xf6060001 /* RCSPEED */ @@ -3684,47 +3684,47 @@ /* TSGENERAL */ #define RSTV0910_TSGENERAL 0xf630 -#define FSTV0910_TSFIFO_DISTS2PAR 0xf6300040 -#define FSTV0910_MUXSTREAM_OUTMODE 0xf6300008 -#define FSTV0910_TSFIFO_PERMPARAL 0xf6300006 +#define FSTV0910_TSFIFO_DISTS2PAR 0xf6306040 +#define FSTV0910_MUXSTREAM_OUTMODE 0xf6303008 +#define FSTV0910_TSFIFO_PERMPARAL 0xf6301006 /* P1_DISIRQCFG */ #define RSTV0910_P1_DISIRQCFG 0xf700 -#define FSTV0910_P1_ENRXEND 0xf7000040 -#define FSTV0910_P1_ENRXFIFO8B 0xf7000020 -#define FSTV0910_P1_ENTRFINISH 0xf7000010 -#define FSTV0910_P1_ENTIMEOUT 0xf7000008 -#define FSTV0910_P1_ENTXEND 0xf7000004 -#define FSTV0910_P1_ENTXFIFO64B 0xf7000002 +#define FSTV0910_P1_ENRXEND 0xf7006040 +#define FSTV0910_P1_ENRXFIFO8B 0xf7005020 +#define FSTV0910_P1_ENTRFINISH 0xf7004010 +#define FSTV0910_P1_ENTIMEOUT 0xf7003008 +#define FSTV0910_P1_ENTXEND 0xf7002004 +#define FSTV0910_P1_ENTXFIFO64B 0xf7001002 #define FSTV0910_P1_ENGAPBURST 0xf7000001 /* P1_DISIRQSTAT */ #define RSTV0910_P1_DISIRQSTAT 0xf701 -#define FSTV0910_P1_IRQRXEND 0xf7010040 -#define FSTV0910_P1_IRQRXFIFO8B 0xf7010020 -#define FSTV0910_P1_IRQTRFINISH 0xf7010010 -#define FSTV0910_P1_IRQTIMEOUT 0xf7010008 -#define FSTV0910_P1_IRQTXEND 0xf7010004 -#define FSTV0910_P1_IRQTXFIFO64B 0xf7010002 +#define FSTV0910_P1_IRQRXEND 0xf7016040 +#define FSTV0910_P1_IRQRXFIFO8B 0xf7015020 +#define FSTV0910_P1_IRQTRFINISH 0xf7014010 +#define FSTV0910_P1_IRQTIMEOUT 0xf7013008 +#define FSTV0910_P1_IRQTXEND 0xf7012004 +#define FSTV0910_P1_IRQTXFIFO64B 0xf7011002 #define FSTV0910_P1_IRQGAPBURST 0xf7010001 /* P1_DISTXCFG */ #define RSTV0910_P1_DISTXCFG 0xf702 -#define FSTV0910_P1_DISTX_RESET 0xf7020080 -#define FSTV0910_P1_TIM_OFF 0xf7020040 -#define FSTV0910_P1_TIM_CMD 0xf7020030 -#define FSTV0910_P1_ENVELOP 0xf7020008 -#define FSTV0910_P1_DIS_PRECHARGE 0xf7020004 +#define FSTV0910_P1_DISTX_RESET 0xf7027080 +#define FSTV0910_P1_TIM_OFF 0xf7026040 +#define FSTV0910_P1_TIM_CMD 0xf7024030 +#define FSTV0910_P1_ENVELOP 0xf7023008 +#define FSTV0910_P1_DIS_PRECHARGE 0xf7022004 #define FSTV0910_P1_DISEQC_MODE 0xf7020003 /* P1_DISTXSTATUS */ #define RSTV0910_P1_DISTXSTATUS 0xf703 -#define FSTV0910_P1_TX_FIFO_FULL 0xf7030040 -#define FSTV0910_P1_TX_IDLE 0xf7030020 -#define FSTV0910_P1_GAP_BURST 0xf7030010 -#define FSTV0910_P1_TX_FIFO64B 0xf7030008 -#define FSTV0910_P1_TX_END 0xf7030004 -#define FSTV0910_P1_TR_TIMEOUT 0xf7030002 +#define FSTV0910_P1_TX_FIFO_FULL 0xf7036040 +#define FSTV0910_P1_TX_IDLE 0xf7035020 +#define FSTV0910_P1_GAP_BURST 0xf7034010 +#define FSTV0910_P1_TX_FIFO64B 0xf7033008 +#define FSTV0910_P1_TX_END 0xf7032004 +#define FSTV0910_P1_TR_TIMEOUT 0xf7031002 #define FSTV0910_P1_TR_FINISH 0xf7030001 /* P1_DISTXBYTES */ @@ -3741,7 +3741,7 @@ /* P1_DISTIMEOCFG */ #define RSTV0910_P1_DISTIMEOCFG 0xf708 -#define FSTV0910_P1_RXCHOICE 0xf7080006 +#define FSTV0910_P1_RXCHOICE 0xf7081006 #define FSTV0910_P1_TIMEOUT_OFF 0xf7080001 /* P1_DISTIMEOUT */ @@ -3750,30 +3750,30 @@ /* P1_DISRXCFG */ #define RSTV0910_P1_DISRXCFG 0xf70a -#define FSTV0910_P1_DISRX_RESET 0xf70a0080 -#define FSTV0910_P1_EXTENVELOP 0xf70a0040 -#define FSTV0910_P1_PINSELECT 0xf70a0038 -#define FSTV0910_P1_IGNORE_SHORT22K 0xf70a0004 -#define FSTV0910_P1_SIGNED_RXIN 0xf70a0002 +#define FSTV0910_P1_DISRX_RESET 0xf70a7080 +#define FSTV0910_P1_EXTENVELOP 0xf70a6040 +#define FSTV0910_P1_PINSELECT 0xf70a3038 +#define FSTV0910_P1_IGNORE_SHORT22K 0xf70a2004 +#define FSTV0910_P1_SIGNED_RXIN 0xf70a1002 #define FSTV0910_P1_DISRX_ON 0xf70a0001 /* P1_DISRXSTAT1 */ #define RSTV0910_P1_DISRXSTAT1 0xf70b -#define FSTV0910_P1_RXEND 0xf70b0080 -#define FSTV0910_P1_RXACTIVE 0xf70b0040 -#define FSTV0910_P1_RXDETECT 0xf70b0020 -#define FSTV0910_P1_CONTTONE 0xf70b0010 -#define FSTV0910_P1_8BFIFOREADY 0xf70b0008 -#define FSTV0910_P1_FIFOEMPTY 0xf70b0004 +#define FSTV0910_P1_RXEND 0xf70b7080 +#define FSTV0910_P1_RXACTIVE 0xf70b6040 +#define FSTV0910_P1_RXDETECT 0xf70b5020 +#define FSTV0910_P1_CONTTONE 0xf70b4010 +#define FSTV0910_P1_8BFIFOREADY 0xf70b3008 +#define FSTV0910_P1_FIFOEMPTY 0xf70b2004 /* P1_DISRXSTAT0 */ #define RSTV0910_P1_DISRXSTAT0 0xf70c -#define FSTV0910_P1_RXFAIL 0xf70c0080 -#define FSTV0910_P1_FIFOPFAIL 0xf70c0040 -#define FSTV0910_P1_RXNONBYTE 0xf70c0020 -#define FSTV0910_P1_FIFOOVF 0xf70c0010 -#define FSTV0910_P1_SHORT22K 0xf70c0008 -#define FSTV0910_P1_RXMSGLOST 0xf70c0004 +#define FSTV0910_P1_RXFAIL 0xf70c7080 +#define FSTV0910_P1_FIFOPFAIL 0xf70c6040 +#define FSTV0910_P1_RXNONBYTE 0xf70c5020 +#define FSTV0910_P1_FIFOOVF 0xf70c4010 +#define FSTV0910_P1_SHORT22K 0xf70c3008 +#define FSTV0910_P1_RXMSGLOST 0xf70c2004 /* P1_DISRXBYTES */ #define RSTV0910_P1_DISRXBYTES 0xf70d @@ -3825,41 +3825,41 @@ /* P2_DISIRQCFG */ #define RSTV0910_P2_DISIRQCFG 0xf740 -#define FSTV0910_P2_ENRXEND 0xf7400040 -#define FSTV0910_P2_ENRXFIFO8B 0xf7400020 -#define FSTV0910_P2_ENTRFINISH 0xf7400010 -#define FSTV0910_P2_ENTIMEOUT 0xf7400008 -#define FSTV0910_P2_ENTXEND 0xf7400004 -#define FSTV0910_P2_ENTXFIFO64B 0xf7400002 +#define FSTV0910_P2_ENRXEND 0xf7406040 +#define FSTV0910_P2_ENRXFIFO8B 0xf7405020 +#define FSTV0910_P2_ENTRFINISH 0xf7404010 +#define FSTV0910_P2_ENTIMEOUT 0xf7403008 +#define FSTV0910_P2_ENTXEND 0xf7402004 +#define FSTV0910_P2_ENTXFIFO64B 0xf7401002 #define FSTV0910_P2_ENGAPBURST 0xf7400001 /* P2_DISIRQSTAT */ #define RSTV0910_P2_DISIRQSTAT 0xf741 -#define FSTV0910_P2_IRQRXEND 0xf7410040 -#define FSTV0910_P2_IRQRXFIFO8B 0xf7410020 -#define FSTV0910_P2_IRQTRFINISH 0xf7410010 -#define FSTV0910_P2_IRQTIMEOUT 0xf7410008 -#define FSTV0910_P2_IRQTXEND 0xf7410004 -#define FSTV0910_P2_IRQTXFIFO64B 0xf7410002 +#define FSTV0910_P2_IRQRXEND 0xf7416040 +#define FSTV0910_P2_IRQRXFIFO8B 0xf7415020 +#define FSTV0910_P2_IRQTRFINISH 0xf7414010 +#define FSTV0910_P2_IRQTIMEOUT 0xf7413008 +#define FSTV0910_P2_IRQTXEND 0xf7412004 +#define FSTV0910_P2_IRQTXFIFO64B 0xf7411002 #define FSTV0910_P2_IRQGAPBURST 0xf7410001 /* P2_DISTXCFG */ #define RSTV0910_P2_DISTXCFG 0xf742 -#define FSTV0910_P2_DISTX_RESET 0xf7420080 -#define FSTV0910_P2_TIM_OFF 0xf7420040 -#define FSTV0910_P2_TIM_CMD 0xf7420030 -#define FSTV0910_P2_ENVELOP 0xf7420008 -#define FSTV0910_P2_DIS_PRECHARGE 0xf7420004 +#define FSTV0910_P2_DISTX_RESET 0xf7427080 +#define FSTV0910_P2_TIM_OFF 0xf7426040 +#define FSTV0910_P2_TIM_CMD 0xf7424030 +#define FSTV0910_P2_ENVELOP 0xf7423008 +#define FSTV0910_P2_DIS_PRECHARGE 0xf7422004 #define FSTV0910_P2_DISEQC_MODE 0xf7420003 /* P2_DISTXSTATUS */ #define RSTV0910_P2_DISTXSTATUS 0xf743 -#define FSTV0910_P2_TX_FIFO_FULL 0xf7430040 -#define FSTV0910_P2_TX_IDLE 0xf7430020 -#define FSTV0910_P2_GAP_BURST 0xf7430010 -#define FSTV0910_P2_TX_FIFO64B 0xf7430008 -#define FSTV0910_P2_TX_END 0xf7430004 -#define FSTV0910_P2_TR_TIMEOUT 0xf7430002 +#define FSTV0910_P2_TX_FIFO_FULL 0xf7436040 +#define FSTV0910_P2_TX_IDLE 0xf7435020 +#define FSTV0910_P2_GAP_BURST 0xf7434010 +#define FSTV0910_P2_TX_FIFO64B 0xf7433008 +#define FSTV0910_P2_TX_END 0xf7432004 +#define FSTV0910_P2_TR_TIMEOUT 0xf7431002 #define FSTV0910_P2_TR_FINISH 0xf7430001 /* P2_DISTXBYTES */ @@ -3876,7 +3876,7 @@ /* P2_DISTIMEOCFG */ #define RSTV0910_P2_DISTIMEOCFG 0xf748 -#define FSTV0910_P2_RXCHOICE 0xf7480006 +#define FSTV0910_P2_RXCHOICE 0xf7481006 #define FSTV0910_P2_TIMEOUT_OFF 0xf7480001 /* P2_DISTIMEOUT */ @@ -3885,30 +3885,30 @@ /* P2_DISRXCFG */ #define RSTV0910_P2_DISRXCFG 0xf74a -#define FSTV0910_P2_DISRX_RESET 0xf74a0080 -#define FSTV0910_P2_EXTENVELOP 0xf74a0040 -#define FSTV0910_P2_PINSELECT 0xf74a0038 -#define FSTV0910_P2_IGNORE_SHORT22K 0xf74a0004 -#define FSTV0910_P2_SIGNED_RXIN 0xf74a0002 +#define FSTV0910_P2_DISRX_RESET 0xf74a7080 +#define FSTV0910_P2_EXTENVELOP 0xf74a6040 +#define FSTV0910_P2_PINSELECT 0xf74a3038 +#define FSTV0910_P2_IGNORE_SHORT22K 0xf74a2004 +#define FSTV0910_P2_SIGNED_RXIN 0xf74a1002 #define FSTV0910_P2_DISRX_ON 0xf74a0001 /* P2_DISRXSTAT1 */ #define RSTV0910_P2_DISRXSTAT1 0xf74b -#define FSTV0910_P2_RXEND 0xf74b0080 -#define FSTV0910_P2_RXACTIVE 0xf74b0040 -#define FSTV0910_P2_RXDETECT 0xf74b0020 -#define FSTV0910_P2_CONTTONE 0xf74b0010 -#define FSTV0910_P2_8BFIFOREADY 0xf74b0008 -#define FSTV0910_P2_FIFOEMPTY 0xf74b0004 +#define FSTV0910_P2_RXEND 0xf74b7080 +#define FSTV0910_P2_RXACTIVE 0xf74b6040 +#define FSTV0910_P2_RXDETECT 0xf74b5020 +#define FSTV0910_P2_CONTTONE 0xf74b4010 +#define FSTV0910_P2_8BFIFOREADY 0xf74b3008 +#define FSTV0910_P2_FIFOEMPTY 0xf74b2004 /* P2_DISRXSTAT0 */ #define RSTV0910_P2_DISRXSTAT0 0xf74c -#define FSTV0910_P2_RXFAIL 0xf74c0080 -#define FSTV0910_P2_FIFOPFAIL 0xf74c0040 -#define FSTV0910_P2_RXNONBYTE 0xf74c0020 -#define FSTV0910_P2_FIFOOVF 0xf74c0010 -#define FSTV0910_P2_SHORT22K 0xf74c0008 -#define FSTV0910_P2_RXMSGLOST 0xf74c0004 +#define FSTV0910_P2_RXFAIL 0xf74c7080 +#define FSTV0910_P2_FIFOPFAIL 0xf74c6040 +#define FSTV0910_P2_RXNONBYTE 0xf74c5020 +#define FSTV0910_P2_FIFOOVF 0xf74c4010 +#define FSTV0910_P2_SHORT22K 0xf74c3008 +#define FSTV0910_P2_RXMSGLOST 0xf74c2004 /* P2_DISRXBYTES */ #define RSTV0910_P2_DISRXBYTES 0xf74d @@ -4168,75 +4168,75 @@ /* SELSATUR6 */ #define RSTV0910_SELSATUR6 0xfa34 -#define FSTV0910_SSAT_SF27 0xfa340008 -#define FSTV0910_SSAT_SF26 0xfa340004 -#define FSTV0910_SSAT_SF25 0xfa340002 +#define FSTV0910_SSAT_SF27 0xfa343008 +#define FSTV0910_SSAT_SF26 0xfa342004 +#define FSTV0910_SSAT_SF25 0xfa341002 #define FSTV0910_SSAT_SF24 0xfa340001 /* SELSATUR5 */ #define RSTV0910_SELSATUR5 0xfa35 -#define FSTV0910_SSAT_SF22 0xfa350080 -#define FSTV0910_SSAT_SF21 0xfa350040 -#define FSTV0910_SSAT_SF20 0xfa350020 -#define FSTV0910_SSAT_SF19 0xfa350010 -#define FSTV0910_SSAT_SF18 0xfa350008 -#define FSTV0910_SSAT_SF16 0xfa350004 -#define FSTV0910_SSAT_SF15 0xfa350002 +#define FSTV0910_SSAT_SF22 0xfa357080 +#define FSTV0910_SSAT_SF21 0xfa356040 +#define FSTV0910_SSAT_SF20 0xfa355020 +#define FSTV0910_SSAT_SF19 0xfa354010 +#define FSTV0910_SSAT_SF18 0xfa353008 +#define FSTV0910_SSAT_SF16 0xfa352004 +#define FSTV0910_SSAT_SF15 0xfa351002 #define FSTV0910_SSAT_SF14 0xfa350001 /* SELSATUR4 */ #define RSTV0910_SELSATUR4 0xfa36 -#define FSTV0910_SSAT_SF13 0xfa360080 -#define FSTV0910_SSAT_SF12 0xfa360040 -#define FSTV0910_SSAT_SF10 0xfa360020 -#define FSTV0910_SSAT_SF9 0xfa360010 -#define FSTV0910_SSAT_SF8 0xfa360008 -#define FSTV0910_SSAT_SF7 0xfa360004 -#define FSTV0910_SSAT_SF6 0xfa360002 +#define FSTV0910_SSAT_SF13 0xfa367080 +#define FSTV0910_SSAT_SF12 0xfa366040 +#define FSTV0910_SSAT_SF10 0xfa365020 +#define FSTV0910_SSAT_SF9 0xfa364010 +#define FSTV0910_SSAT_SF8 0xfa363008 +#define FSTV0910_SSAT_SF7 0xfa362004 +#define FSTV0910_SSAT_SF6 0xfa361002 #define FSTV0910_SSAT_SF5 0xfa360001 /* SELSATUR3 */ #define RSTV0910_SELSATUR3 0xfa37 -#define FSTV0910_SSAT_SF4 0xfa370080 -#define FSTV0910_SSAT_SF3 0xfa370040 -#define FSTV0910_SSAT_SF2 0xfa370020 -#define FSTV0910_SSAT_SF1 0xfa370010 -#define FSTV0910_SSAT_NF28 0xfa370008 -#define FSTV0910_SSAT_NF27 0xfa370004 -#define FSTV0910_SSAT_NF26 0xfa370002 +#define FSTV0910_SSAT_SF4 0xfa377080 +#define FSTV0910_SSAT_SF3 0xfa376040 +#define FSTV0910_SSAT_SF2 0xfa375020 +#define FSTV0910_SSAT_SF1 0xfa374010 +#define FSTV0910_SSAT_NF28 0xfa373008 +#define FSTV0910_SSAT_NF27 0xfa372004 +#define FSTV0910_SSAT_NF26 0xfa371002 #define FSTV0910_SSAT_NF25 0xfa370001 /* SELSATUR2 */ #define RSTV0910_SELSATUR2 0xfa38 -#define FSTV0910_SSAT_NF24 0xfa380080 -#define FSTV0910_SSAT_NF23 0xfa380040 -#define FSTV0910_SSAT_NF22 0xfa380020 -#define FSTV0910_SSAT_NF21 0xfa380010 -#define FSTV0910_SSAT_NF20 0xfa380008 -#define FSTV0910_SSAT_NF19 0xfa380004 -#define FSTV0910_SSAT_NF18 0xfa380002 +#define FSTV0910_SSAT_NF24 0xfa387080 +#define FSTV0910_SSAT_NF23 0xfa386040 +#define FSTV0910_SSAT_NF22 0xfa385020 +#define FSTV0910_SSAT_NF21 0xfa384010 +#define FSTV0910_SSAT_NF20 0xfa383008 +#define FSTV0910_SSAT_NF19 0xfa382004 +#define FSTV0910_SSAT_NF18 0xfa381002 #define FSTV0910_SSAT_NF17 0xfa380001 /* SELSATUR1 */ #define RSTV0910_SELSATUR1 0xfa39 -#define FSTV0910_SSAT_NF16 0xfa390080 -#define FSTV0910_SSAT_NF15 0xfa390040 -#define FSTV0910_SSAT_NF14 0xfa390020 -#define FSTV0910_SSAT_NF13 0xfa390010 -#define FSTV0910_SSAT_NF12 0xfa390008 -#define FSTV0910_SSAT_NF11 0xfa390004 -#define FSTV0910_SSAT_NF10 0xfa390002 +#define FSTV0910_SSAT_NF16 0xfa397080 +#define FSTV0910_SSAT_NF15 0xfa396040 +#define FSTV0910_SSAT_NF14 0xfa395020 +#define FSTV0910_SSAT_NF13 0xfa394010 +#define FSTV0910_SSAT_NF12 0xfa393008 +#define FSTV0910_SSAT_NF11 0xfa392004 +#define FSTV0910_SSAT_NF10 0xfa391002 #define FSTV0910_SSAT_NF9 0xfa390001 /* SELSATUR0 */ #define RSTV0910_SELSATUR0 0xfa3a -#define FSTV0910_SSAT_NF8 0xfa3a0080 -#define FSTV0910_SSAT_NF7 0xfa3a0040 -#define FSTV0910_SSAT_NF6 0xfa3a0020 -#define FSTV0910_SSAT_NF5 0xfa3a0010 -#define FSTV0910_SSAT_NF4 0xfa3a0008 -#define FSTV0910_SSAT_NF3 0xfa3a0004 -#define FSTV0910_SSAT_NF2 0xfa3a0002 +#define FSTV0910_SSAT_NF8 0xfa3a7080 +#define FSTV0910_SSAT_NF7 0xfa3a6040 +#define FSTV0910_SSAT_NF6 0xfa3a5020 +#define FSTV0910_SSAT_NF5 0xfa3a4010 +#define FSTV0910_SSAT_NF4 0xfa3a3008 +#define FSTV0910_SSAT_NF3 0xfa3a2004 +#define FSTV0910_SSAT_NF2 0xfa3a1002 #define FSTV0910_SSAT_NF1 0xfa3a0001 /* GAINLLR_NF1 */ @@ -4449,14 +4449,14 @@ /* CFGEXT */ #define RSTV0910_CFGEXT 0xfa80 -#define FSTV0910_BYPBCH 0xfa800040 -#define FSTV0910_BYPLDPC 0xfa800020 -#define FSTV0910_SHORTMULT 0xfa800004 +#define FSTV0910_BYPBCH 0xfa806040 +#define FSTV0910_BYPLDPC 0xfa805020 +#define FSTV0910_SHORTMULT 0xfa802004 /* GENCFG */ #define RSTV0910_GENCFG 0xfa86 -#define FSTV0910_BROADCAST 0xfa860010 -#define FSTV0910_CROSSINPUT 0xfa860002 +#define FSTV0910_BROADCAST 0xfa864010 +#define FSTV0910_CROSSINPUT 0xfa861002 #define FSTV0910_DDEMOD 0xfa860001 /* LDPCERR1 */ @@ -4469,7 +4469,7 @@ /* BCHERR */ #define RSTV0910_BCHERR 0xfa98 -#define FSTV0910_ERRORFLAG 0xfa980010 +#define FSTV0910_ERRORFLAG 0xfa984010 #define FSTV0910_BCH_ERRORS_COUNTER 0xfa98000f /* P1_MAXEXTRAITER */ @@ -4706,22 +4706,22 @@ /* TSTRES0 */ #define RSTV0910_TSTRES0 0xff11 -#define FSTV0910_FRESFEC 0xff110080 -#define FSTV0910_FRESSYM1 0xff110008 -#define FSTV0910_FRESSYM2 0xff110004 +#define FSTV0910_FRESFEC 0xff117080 +#define FSTV0910_FRESSYM1 0xff113008 +#define FSTV0910_FRESSYM2 0xff112004 /* TSTOUT */ #define RSTV0910_TSTOUT 0xff12 -#define FSTV0910_TS 0xff12003e +#define FSTV0910_TS 0xff12103e #define FSTV0910_TEST_OUT 0xff120001 /* TSTIN */ #define RSTV0910_TSTIN 0xff13 -#define FSTV0910_TEST_IN 0xff130080 +#define FSTV0910_TEST_IN 0xff137080 /* P2_TSTDMD */ #define RSTV0910_P2_TSTDMD 0xff20 -#define FSTV0910_P2_CFRINIT_INVZIGZAG 0xff200008 +#define FSTV0910_P2_CFRINIT_INVZIGZAG 0xff203008 /* P2_TCTL1 */ #define RSTV0910_P2_TCTL1 0xff24 @@ -4729,15 +4729,15 @@ /* P2_TCTL4 */ #define RSTV0910_P2_TCTL4 0xff28 -#define FSTV0910_P2_CFR2TOCFR1_DVBS1 0xff2800c0 +#define FSTV0910_P2_CFR2TOCFR1_DVBS1 0xff2860c0 /* P2_TPKTDELIN */ #define RSTV0910_P2_TPKTDELIN 0xff37 -#define FSTV0910_P2_CFG_RSPARITYON 0xff370080 +#define FSTV0910_P2_CFG_RSPARITYON 0xff377080 /* P1_TSTDMD */ #define RSTV0910_P1_TSTDMD 0xff40 -#define FSTV0910_P1_CFRINIT_INVZIGZAG 0xff400008 +#define FSTV0910_P1_CFRINIT_INVZIGZAG 0xff403008 /* P1_TCTL1 */ #define RSTV0910_P1_TCTL1 0xff44 @@ -4745,16 +4745,16 @@ /* P1_TCTL4 */ #define RSTV0910_P1_TCTL4 0xff48 -#define FSTV0910_P1_CFR2TOCFR1_DVBS1 0xff4800c0 +#define FSTV0910_P1_CFR2TOCFR1_DVBS1 0xff4860c0 /* P1_TPKTDELIN */ #define RSTV0910_P1_TPKTDELIN 0xff57 -#define FSTV0910_P1_CFG_RSPARITYON 0xff570080 +#define FSTV0910_P1_CFG_RSPARITYON 0xff577080 /* TSTTSRS */ #define RSTV0910_TSTTSRS 0xff6d -#define FSTV0910_TSTRS_DISRS2 0xff6d0002 +#define FSTV0910_TSTRS_DISRS2 0xff6d1002 #define FSTV0910_TSTRS_DISRS1 0xff6d0001 -#define STV0910_NBREGS 975 -#define STV0910_NBFIELDS 1818 +#define STV0910_NBREGS 975 +#define STV0910_NBFIELDS 1818 diff --git a/drivers/media/dvb-frontends/stv6110.h b/drivers/media/dvb-frontends/stv6110.h index ab73124c0dec..ecfc1faba15c 100644 --- a/drivers/media/dvb-frontends/stv6110.h +++ b/drivers/media/dvb-frontends/stv6110.h @@ -22,7 +22,7 @@ #define __DVB_STV6110_H__ #include <linux/i2c.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> /* registers */ #define RSTV6110_CTRL1 0 diff --git a/drivers/media/dvb-frontends/stv6110x.c b/drivers/media/dvb-frontends/stv6110x.c index 66eba38f1014..d8950028d021 100644 --- a/drivers/media/dvb-frontends/stv6110x.c +++ b/drivers/media/dvb-frontends/stv6110x.c @@ -26,7 +26,7 @@ #include <linux/slab.h> #include <linux/string.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "stv6110x_reg.h" #include "stv6110x.h" @@ -46,7 +46,7 @@ static int stv6110x_read_reg(struct stv6110x_state *stv6110x, u8 reg, u8 *data) u8 b0[] = { reg }; u8 b1[] = { 0 }; struct i2c_msg msg[] = { - { .addr = config->addr, .flags = 0, .buf = b0, .len = 1 }, + { .addr = config->addr, .flags = 0, .buf = b0, .len = 1 }, { .addr = config->addr, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; @@ -97,7 +97,9 @@ static int stv6110x_write_regs(struct stv6110x_state *stv6110x, int start, u8 da static int stv6110x_write_reg(struct stv6110x_state *stv6110x, u8 reg, u8 data) { - return stv6110x_write_regs(stv6110x, reg, &data, 1); + u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ + + return stv6110x_write_regs(stv6110x, reg, &tmp, 1); } static int stv6110x_init(struct dvb_frontend *fe) diff --git a/drivers/media/dvb-frontends/stv6110x_priv.h b/drivers/media/dvb-frontends/stv6110x_priv.h index a993aba27b7e..109dfaf4ba42 100644 --- a/drivers/media/dvb-frontends/stv6110x_priv.h +++ b/drivers/media/dvb-frontends/stv6110x_priv.h @@ -48,11 +48,11 @@ #define STV6110x_SETFIELD(mask, bitf, val) \ (mask = (mask & (~(((1 << STV6110x_WIDTH_##bitf) - 1) << \ - STV6110x_OFFST_##bitf))) | \ + STV6110x_OFFST_##bitf))) | \ (val << STV6110x_OFFST_##bitf)) #define STV6110x_GETFIELD(bitf, val) \ - ((val >> STV6110x_OFFST_##bitf) & \ + ((val >> STV6110x_OFFST_##bitf) & \ ((1 << STV6110x_WIDTH_##bitf) - 1)) #define MAKEWORD16(a, b) (((a) << 8) | (b)) @@ -68,7 +68,7 @@ struct stv6110x_state { struct i2c_adapter *i2c; const struct stv6110x_config *config; - u8 regs[8]; + u8 regs[8]; const struct stv6110x_devctl *devctl; }; diff --git a/drivers/media/dvb-frontends/stv6111.c b/drivers/media/dvb-frontends/stv6111.c index e3e90070e293..9b715b6fe152 100644 --- a/drivers/media/dvb-frontends/stv6111.c +++ b/drivers/media/dvb-frontends/stv6111.c @@ -25,7 +25,7 @@ #include "stv6111.h" -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> struct stv { struct i2c_adapter *i2c; @@ -424,6 +424,7 @@ static int set_bandwidth(struct dvb_frontend *fe, u32 cutoff_frequency) { struct stv *state = fe->tuner_priv; u32 index = (cutoff_frequency + 999999) / 1000000; + int stat = 0; if (index < 6) index = 6; @@ -435,12 +436,14 @@ static int set_bandwidth(struct dvb_frontend *fe, u32 cutoff_frequency) state->reg[0x08] = (state->reg[0x08] & ~0xFC) | ((index - 6) << 2); state->reg[0x09] = (state->reg[0x09] & ~0x0C) | 0x08; if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - write_regs(state, 0x08, 2); - wait_for_call_done(state, 0x08); - if (fe->ops.i2c_gate_ctrl) + stat = fe->ops.i2c_gate_ctrl(fe, 1); + if (!stat) { + write_regs(state, 0x08, 2); + wait_for_call_done(state, 0x08); + } + if (fe->ops.i2c_gate_ctrl && !stat) fe->ops.i2c_gate_ctrl(fe, 0); - return 0; + return stat; } static int set_lof(struct stv *state, u32 local_frequency, u32 cutoff_frequency) @@ -518,6 +521,7 @@ static int set_params(struct dvb_frontend *fe) struct stv *state = fe->tuner_priv; struct dtv_frontend_properties *p = &fe->dtv_property_cache; u32 freq, cutoff; + int stat = 0; if (p->delivery_system != SYS_DVBS && p->delivery_system != SYS_DVBS2) return -EINVAL; @@ -526,9 +530,10 @@ static int set_params(struct dvb_frontend *fe) cutoff = 5000000 + muldiv32(p->symbol_rate, 135, 200); if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - set_lof(state, freq, cutoff); - if (fe->ops.i2c_gate_ctrl) + stat = fe->ops.i2c_gate_ctrl(fe, 1); + if (!stat) + set_lof(state, freq, cutoff); + if (fe->ops.i2c_gate_ctrl && !stat) fe->ops.i2c_gate_ctrl(fe, 0); return 0; } @@ -575,14 +580,17 @@ static int get_rf_strength(struct dvb_frontend *fe, u16 *st) if ((state->reg[0x03] & 0x60) == 0) { /* RF Mode, Read AGC ADC */ u8 reg = 0; + int stat = 0; if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - write_reg(state, 0x02, state->reg[0x02] | 0x20); - read_reg(state, 2, ®); - if (reg & 0x20) + stat = fe->ops.i2c_gate_ctrl(fe, 1); + if (!stat) { + write_reg(state, 0x02, state->reg[0x02] | 0x20); read_reg(state, 2, ®); - if (fe->ops.i2c_gate_ctrl) + if (reg & 0x20) + read_reg(state, 2, ®); + } + if (fe->ops.i2c_gate_ctrl && !stat) fe->ops.i2c_gate_ctrl(fe, 0); if ((state->reg[0x02] & 0x80) == 0) @@ -652,7 +660,8 @@ struct dvb_frontend *stv6111_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, u8 adr) { struct stv *state; - int stat; + int stat = -ENODEV; + int gatestat = 0; state = kzalloc(sizeof(*state), GFP_KERNEL); if (!state) @@ -663,9 +672,10 @@ struct dvb_frontend *stv6111_attach(struct dvb_frontend *fe, init_state(state); if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - stat = attach_init(state); - if (fe->ops.i2c_gate_ctrl) + gatestat = fe->ops.i2c_gate_ctrl(fe, 1); + if (!gatestat) + stat = attach_init(state); + if (fe->ops.i2c_gate_ctrl && !gatestat) fe->ops.i2c_gate_ctrl(fe, 0); if (stat < 0) { kfree(state); diff --git a/drivers/media/dvb-frontends/tc90522.c b/drivers/media/dvb-frontends/tc90522.c index 4687e1546af2..5572b39614d5 100644 --- a/drivers/media/dvb-frontends/tc90522.c +++ b/drivers/media/dvb-frontends/tc90522.c @@ -30,7 +30,7 @@ #include <linux/kernel.h> #include <linux/math64.h> #include <linux/dvb/frontend.h> -#include "dvb_math.h" +#include <media/dvb_math.h> #include "tc90522.h" #define TC90522_I2C_THRU_REG 0xfe diff --git a/drivers/media/dvb-frontends/tc90522.h b/drivers/media/dvb-frontends/tc90522.h index b1cbddfa6ee6..10e585f32499 100644 --- a/drivers/media/dvb-frontends/tc90522.h +++ b/drivers/media/dvb-frontends/tc90522.h @@ -25,7 +25,7 @@ #define TC90522_H #include <linux/i2c.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> /* I2C device types */ #define TC90522_I2C_DEV_SAT "tc90522sat" diff --git a/drivers/media/dvb-frontends/tda10021.c b/drivers/media/dvb-frontends/tda10021.c index 32ba8401e743..4f588ebde39d 100644 --- a/drivers/media/dvb-frontends/tda10021.c +++ b/drivers/media/dvb-frontends/tda10021.c @@ -29,7 +29,7 @@ #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "tda1002x.h" diff --git a/drivers/media/dvb-frontends/tda10023.c b/drivers/media/dvb-frontends/tda10023.c index 8028007c68eb..6c84916234e3 100644 --- a/drivers/media/dvb-frontends/tda10023.c +++ b/drivers/media/dvb-frontends/tda10023.c @@ -35,7 +35,7 @@ #include <asm/div64.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "tda1002x.h" #define REG0_INIT_VAL 0x23 @@ -211,7 +211,7 @@ static int tda10023_set_symbolrate (struct tda10023_state* state, u32 sr) BDRX=1<<(24+NDEC); BDRX*=sr; - do_div(BDRX, state->sysclk); /* BDRX/=SYSCLK; */ + do_div(BDRX, state->sysclk); /* BDRX/=SYSCLK; */ BDR=(s32)BDRX; } diff --git a/drivers/media/dvb-frontends/tda10048.c b/drivers/media/dvb-frontends/tda10048.c index 143b39b5f6c9..de82a2558e15 100644 --- a/drivers/media/dvb-frontends/tda10048.c +++ b/drivers/media/dvb-frontends/tda10048.c @@ -27,8 +27,8 @@ #include <linux/delay.h> #include <linux/math64.h> #include <asm/div64.h> -#include "dvb_frontend.h" -#include "dvb_math.h" +#include <media/dvb_frontend.h> +#include <media/dvb_math.h> #include "tda10048.h" #define TDA10048_DEFAULT_FIRMWARE "dvb-fe-tda10048-1.0.fw" diff --git a/drivers/media/dvb-frontends/tda1004x.c b/drivers/media/dvb-frontends/tda1004x.c index e674508c349c..58e3beff5adc 100644 --- a/drivers/media/dvb-frontends/tda1004x.c +++ b/drivers/media/dvb-frontends/tda1004x.c @@ -36,7 +36,7 @@ #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "tda1004x.h" static int debug; diff --git a/drivers/media/dvb-frontends/tda10071.h b/drivers/media/dvb-frontends/tda10071.h index 8f184026ee11..da1a87bc1603 100644 --- a/drivers/media/dvb-frontends/tda10071.h +++ b/drivers/media/dvb-frontends/tda10071.h @@ -38,7 +38,6 @@ * @tuner_i2c_addr: CX24118A tuner I2C address (0x14, 0x54, ...). * @get_dvb_frontend: Get DVB frontend. */ - struct tda10071_platform_data { u32 clk; u16 i2c_wr_max; diff --git a/drivers/media/dvb-frontends/tda10071_priv.h b/drivers/media/dvb-frontends/tda10071_priv.h index b9c3601802ba..67c46e8a7201 100644 --- a/drivers/media/dvb-frontends/tda10071_priv.h +++ b/drivers/media/dvb-frontends/tda10071_priv.h @@ -21,7 +21,7 @@ #ifndef TDA10071_PRIV #define TDA10071_PRIV -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "tda10071.h" #include <linux/firmware.h> #include <linux/regmap.h> diff --git a/drivers/media/dvb-frontends/tda10086.c b/drivers/media/dvb-frontends/tda10086.c index b6d16c05904d..1a95c521e97f 100644 --- a/drivers/media/dvb-frontends/tda10086.c +++ b/drivers/media/dvb-frontends/tda10086.c @@ -27,7 +27,7 @@ #include <linux/string.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "tda10086.h" #define SACLK 96000000 diff --git a/drivers/media/dvb-frontends/tda18271c2dd.c b/drivers/media/dvb-frontends/tda18271c2dd.c index 2d2778be2d2f..2e1d36ae943b 100644 --- a/drivers/media/dvb-frontends/tda18271c2dd.c +++ b/drivers/media/dvb-frontends/tda18271c2dd.c @@ -27,7 +27,7 @@ #include <linux/i2c.h> #include <asm/div64.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "tda18271c2dd.h" /* Max transfer size done by I2C transfer functions */ @@ -674,7 +674,6 @@ static int PowerScan(struct tda_state *state, Count = 200000; wait = true; } - status = status; if (status < 0) break; if (CID_Gain >= CID_Target) { diff --git a/drivers/media/dvb-frontends/tda18271c2dd.h b/drivers/media/dvb-frontends/tda18271c2dd.h index 289653db68e4..afeb9536e9c9 100644 --- a/drivers/media/dvb-frontends/tda18271c2dd.h +++ b/drivers/media/dvb-frontends/tda18271c2dd.h @@ -9,8 +9,8 @@ struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe, static inline struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, u8 adr) { - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); - return NULL; + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; } #endif diff --git a/drivers/media/dvb-frontends/tda665x.c b/drivers/media/dvb-frontends/tda665x.c index a63dec44295b..3ef7140ed7f3 100644 --- a/drivers/media/dvb-frontends/tda665x.c +++ b/drivers/media/dvb-frontends/tda665x.c @@ -22,7 +22,7 @@ #include <linux/module.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "tda665x.h" struct tda665x_state { diff --git a/drivers/media/dvb-frontends/tda8083.c b/drivers/media/dvb-frontends/tda8083.c index aa3200d3c352..29b4f64c030c 100644 --- a/drivers/media/dvb-frontends/tda8083.c +++ b/drivers/media/dvb-frontends/tda8083.c @@ -30,7 +30,7 @@ #include <linux/string.h> #include <linux/slab.h> #include <linux/jiffies.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "tda8083.h" diff --git a/drivers/media/dvb-frontends/tda8261.c b/drivers/media/dvb-frontends/tda8261.c index 4eb294f330bc..f72a54e7eb23 100644 --- a/drivers/media/dvb-frontends/tda8261.c +++ b/drivers/media/dvb-frontends/tda8261.c @@ -23,7 +23,7 @@ #include <linux/module.h> #include <linux/slab.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "tda8261.h" struct tda8261_state { diff --git a/drivers/media/dvb-frontends/tda826x.h b/drivers/media/dvb-frontends/tda826x.h index 81abe1aebe9f..0ef35ff3807f 100644 --- a/drivers/media/dvb-frontends/tda826x.h +++ b/drivers/media/dvb-frontends/tda826x.h @@ -24,16 +24,17 @@ #define __DVB_TDA826X_H__ #include <linux/i2c.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> /** * Attach a tda826x tuner to the supplied frontend structure. * - * @param fe Frontend to attach to. - * @param addr i2c address of the tuner. - * @param i2c i2c adapter to use. - * @param has_loopthrough Set to 1 if the card has a loopthrough RF connector. - * @return FE pointer on success, NULL on failure. + * @fe: Frontend to attach to. + * @addr: i2c address of the tuner. + * @i2c: i2c adapter to use. + * @has_loopthrough: Set to 1 if the card has a loopthrough RF connector. + * + * return: FE pointer on success, NULL on failure. */ #if IS_REACHABLE(CONFIG_DVB_TDA826X) extern struct dvb_frontend* tda826x_attach(struct dvb_frontend *fe, int addr, diff --git a/drivers/media/dvb-frontends/ts2020.c b/drivers/media/dvb-frontends/ts2020.c index 931e5c98da8a..c55882a8da06 100644 --- a/drivers/media/dvb-frontends/ts2020.c +++ b/drivers/media/dvb-frontends/ts2020.c @@ -19,7 +19,7 @@ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "ts2020.h" #include <linux/regmap.h> #include <linux/math64.h> @@ -368,7 +368,7 @@ static int ts2020_read_tuner_gain(struct dvb_frontend *fe, unsigned v_agc, gain2 = clamp_t(long, gain2, 0, 13); v_agc = clamp_t(long, v_agc, 400, 1100); - *_gain = -(gain1 * 2330 + + *_gain = -((__s64)gain1 * 2330 + gain2 * 3500 + v_agc * 24 / 10 * 10 + 10000); @@ -386,7 +386,7 @@ static int ts2020_read_tuner_gain(struct dvb_frontend *fe, unsigned v_agc, gain3 = clamp_t(long, gain3, 0, 6); v_agc = clamp_t(long, v_agc, 600, 1600); - *_gain = -(gain1 * 2650 + + *_gain = -((__s64)gain1 * 2650 + gain2 * 3380 + gain3 * 2850 + v_agc * 176 / 100 * 10 - diff --git a/drivers/media/dvb-frontends/tua6100.c b/drivers/media/dvb-frontends/tua6100.c index 18e6d4c5be21..1d41abd47f04 100644 --- a/drivers/media/dvb-frontends/tua6100.c +++ b/drivers/media/dvb-frontends/tua6100.c @@ -1,4 +1,4 @@ -/** +/* * Driver for Infineon tua6100 pll. * * (c) 2006 Andrew de Quincey diff --git a/drivers/media/dvb-frontends/tua6100.h b/drivers/media/dvb-frontends/tua6100.h index 9f15cbdfdeca..a342bd9c7fbf 100644 --- a/drivers/media/dvb-frontends/tua6100.h +++ b/drivers/media/dvb-frontends/tua6100.h @@ -1,4 +1,4 @@ -/** +/* * Driver for Infineon tua6100 PLL. * * (c) 2006 Andrew de Quincey @@ -28,7 +28,7 @@ #define __DVB_TUA6100_H__ #include <linux/i2c.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #if IS_REACHABLE(CONFIG_DVB_TUA6100) extern struct dvb_frontend *tua6100_attach(struct dvb_frontend *fe, int addr, struct i2c_adapter *i2c); diff --git a/drivers/media/dvb-frontends/ves1820.c b/drivers/media/dvb-frontends/ves1820.c index 178363704bd4..1d8979289915 100644 --- a/drivers/media/dvb-frontends/ves1820.c +++ b/drivers/media/dvb-frontends/ves1820.c @@ -27,7 +27,7 @@ #include <linux/slab.h> #include <asm/div64.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "ves1820.h" diff --git a/drivers/media/dvb-frontends/ves1x93.c b/drivers/media/dvb-frontends/ves1x93.c index d0ee52f66a8e..0c7b3286b04d 100644 --- a/drivers/media/dvb-frontends/ves1x93.c +++ b/drivers/media/dvb-frontends/ves1x93.c @@ -30,7 +30,7 @@ #include <linux/slab.h> #include <linux/delay.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "ves1x93.h" diff --git a/drivers/media/dvb-frontends/zd1301_demod.h b/drivers/media/dvb-frontends/zd1301_demod.h index ceb2e05e873c..63c13fa4a54b 100644 --- a/drivers/media/dvb-frontends/zd1301_demod.h +++ b/drivers/media/dvb-frontends/zd1301_demod.h @@ -19,7 +19,7 @@ #include <linux/platform_device.h> #include <linux/dvb/frontend.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> /** * struct zd1301_demod_platform_data - Platform data for the zd1301_demod driver @@ -27,7 +27,6 @@ * @reg_read: Register read callback. * @reg_write: Register write callback. */ - struct zd1301_demod_platform_data { void *reg_priv; int (*reg_read)(void *, u16, u8 *); @@ -41,8 +40,7 @@ struct zd1301_demod_platform_data { * * Return: Pointer to DVB frontend which given platform device owns. */ - -struct dvb_frontend *zd1301_demod_get_dvb_frontend(struct platform_device *); +struct dvb_frontend *zd1301_demod_get_dvb_frontend(struct platform_device *pdev); /** * zd1301_demod_get_i2c_adapter() - Get pointer to I2C adapter @@ -50,11 +48,16 @@ struct dvb_frontend *zd1301_demod_get_dvb_frontend(struct platform_device *); * * Return: Pointer to I2C adapter which given platform device owns. */ - -struct i2c_adapter *zd1301_demod_get_i2c_adapter(struct platform_device *); +struct i2c_adapter *zd1301_demod_get_i2c_adapter(struct platform_device *pdev); #else +/** + * zd1301_demod_get_dvb_frontend() - Attach a zd1301 frontend + * @dev: Pointer to platform device + * + * Return: Pointer to %struct dvb_frontend or NULL if attach fails. + */ static inline struct dvb_frontend *zd1301_demod_get_dvb_frontend(struct platform_device *dev) { printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); diff --git a/drivers/media/dvb-frontends/zl10036.c b/drivers/media/dvb-frontends/zl10036.c index 062282739ce5..89dd65ae88ad 100644 --- a/drivers/media/dvb-frontends/zl10036.c +++ b/drivers/media/dvb-frontends/zl10036.c @@ -1,4 +1,4 @@ -/** +/* * Driver for Zarlink zl10036 DVB-S silicon tuner * * Copyright (C) 2006 Tino Reichardt @@ -157,7 +157,7 @@ static int zl10036_sleep(struct dvb_frontend *fe) return ret; } -/** +/* * register map of the ZL10036/ZL10038 * * reg[default] content @@ -219,7 +219,7 @@ static int zl10036_set_bandwidth(struct zl10036_state *state, u32 fbw) if (fbw <= 28820) { br = _BR_MAXIMUM; } else { - /** + /* * f(bw)=34,6MHz f(xtal)=10.111MHz * br = (10111/34600) * 63 * 1/K = 14; */ @@ -315,7 +315,7 @@ static int zl10036_set_params(struct dvb_frontend *fe) || (frequency > fe->ops.info.frequency_max)) return -EINVAL; - /** + /* * alpha = 1.35 for dvb-s * fBW = (alpha*symbolrate)/(2*0.8) * 1.35 / (2*0.8) = 27 / 32 diff --git a/drivers/media/dvb-frontends/zl10036.h b/drivers/media/dvb-frontends/zl10036.h index 88751adfecf7..a1129ab74296 100644 --- a/drivers/media/dvb-frontends/zl10036.h +++ b/drivers/media/dvb-frontends/zl10036.h @@ -18,15 +18,7 @@ #define DVB_ZL10036_H #include <linux/i2c.h> -#include "dvb_frontend.h" - -/** - * Attach a zl10036 tuner to the supplied frontend structure. - * - * @param fe Frontend to attach to. - * @param config zl10036_config structure - * @return FE pointer on success, NULL on failure. - */ +#include <media/dvb_frontend.h> struct zl10036_config { u8 tuner_address; @@ -34,6 +26,14 @@ struct zl10036_config { }; #if IS_REACHABLE(CONFIG_DVB_ZL10036) +/** + * Attach a zl10036 tuner to the supplied frontend structure. + * + * @fe: Frontend to attach to. + * @config: zl10036_config structure. + * @i2c: pointer to struct i2c_adapter. + * return: FE pointer on success, NULL on failure. + */ extern struct dvb_frontend *zl10036_attach(struct dvb_frontend *fe, const struct zl10036_config *config, struct i2c_adapter *i2c); #else diff --git a/drivers/media/dvb-frontends/zl10039.c b/drivers/media/dvb-frontends/zl10039.c index 623355fc2666..6293bd920fa6 100644 --- a/drivers/media/dvb-frontends/zl10039.c +++ b/drivers/media/dvb-frontends/zl10039.c @@ -21,7 +21,7 @@ #include <linux/slab.h> #include <linux/dvb/frontend.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "zl10039.h" static int debug; @@ -134,7 +134,9 @@ static inline int zl10039_writereg(struct zl10039_state *state, const enum zl10039_reg_addr reg, const u8 val) { - return zl10039_write(state, reg, &val, 1); + const u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ + + return zl10039_write(state, reg, &tmp, 1); } static int zl10039_init(struct dvb_frontend *fe) diff --git a/drivers/media/dvb-frontends/zl10353.c b/drivers/media/dvb-frontends/zl10353.c index 1c689f7f4ab8..c9901f45deb7 100644 --- a/drivers/media/dvb-frontends/zl10353.c +++ b/drivers/media/dvb-frontends/zl10353.c @@ -23,7 +23,7 @@ #include <linux/slab.h> #include <asm/div64.h> -#include "dvb_frontend.h" +#include <media/dvb_frontend.h> #include "zl10353_priv.h" #include "zl10353.h" |