diff options
Diffstat (limited to 'drivers/misc/habanalabs/include/goya/asic_reg/mme4_rtr_regs.h')
| -rw-r--r-- | drivers/misc/habanalabs/include/goya/asic_reg/mme4_rtr_regs.h | 331 |
1 files changed, 331 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme4_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme4_rtr_regs.h new file mode 100644 index 000000000000..d9a4a02cefa3 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme4_rtr_regs.h @@ -0,0 +1,331 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME4_RTR_REGS_H_ +#define ASIC_REG_MME4_RTR_REGS_H_ + +/* + ***************************************** + * MME4_RTR (Prototype: MME_RTR) + ***************************************** + */ + +#define mmMME4_RTR_HBW_RD_RQ_E_ARB 0x100100 + +#define mmMME4_RTR_HBW_RD_RQ_W_ARB 0x100104 + +#define mmMME4_RTR_HBW_RD_RQ_N_ARB 0x100108 + +#define mmMME4_RTR_HBW_RD_RQ_S_ARB 0x10010C + +#define mmMME4_RTR_HBW_RD_RQ_L_ARB 0x100110 + +#define mmMME4_RTR_HBW_E_ARB_MAX 0x100120 + +#define mmMME4_RTR_HBW_W_ARB_MAX 0x100124 + +#define mmMME4_RTR_HBW_N_ARB_MAX 0x100128 + +#define mmMME4_RTR_HBW_S_ARB_MAX 0x10012C + +#define mmMME4_RTR_HBW_L_ARB_MAX 0x100130 + +#define mmMME4_RTR_HBW_RD_RS_MAX_CREDIT 0x100140 + +#define mmMME4_RTR_HBW_WR_RQ_MAX_CREDIT 0x100144 + +#define mmMME4_RTR_HBW_RD_RQ_MAX_CREDIT 0x100148 + +#define mmMME4_RTR_HBW_RD_RS_E_ARB 0x100150 + +#define mmMME4_RTR_HBW_RD_RS_W_ARB 0x100154 + +#define mmMME4_RTR_HBW_RD_RS_N_ARB 0x100158 + +#define mmMME4_RTR_HBW_RD_RS_S_ARB 0x10015C + +#define mmMME4_RTR_HBW_RD_RS_L_ARB 0x100160 + +#define mmMME4_RTR_HBW_WR_RQ_E_ARB 0x100170 + +#define mmMME4_RTR_HBW_WR_RQ_W_ARB 0x100174 + +#define mmMME4_RTR_HBW_WR_RQ_N_ARB 0x100178 + +#define mmMME4_RTR_HBW_WR_RQ_S_ARB 0x10017C + +#define mmMME4_RTR_HBW_WR_RQ_L_ARB 0x100180 + +#define mmMME4_RTR_HBW_WR_RS_E_ARB 0x100190 + +#define mmMME4_RTR_HBW_WR_RS_W_ARB 0x100194 + +#define mmMME4_RTR_HBW_WR_RS_N_ARB 0x100198 + +#define mmMME4_RTR_HBW_WR_RS_S_ARB 0x10019C + +#define mmMME4_RTR_HBW_WR_RS_L_ARB 0x1001A0 + +#define mmMME4_RTR_LBW_RD_RQ_E_ARB 0x100200 + +#define mmMME4_RTR_LBW_RD_RQ_W_ARB 0x100204 + +#define mmMME4_RTR_LBW_RD_RQ_N_ARB 0x100208 + +#define mmMME4_RTR_LBW_RD_RQ_S_ARB 0x10020C + +#define mmMME4_RTR_LBW_RD_RQ_L_ARB 0x100210 + +#define mmMME4_RTR_LBW_E_ARB_MAX 0x100220 + +#define mmMME4_RTR_LBW_W_ARB_MAX 0x100224 + +#define mmMME4_RTR_LBW_N_ARB_MAX 0x100228 + +#define mmMME4_RTR_LBW_S_ARB_MAX 0x10022C + +#define mmMME4_RTR_LBW_L_ARB_MAX 0x100230 + +#define mmMME4_RTR_LBW_SRAM_MAX_CREDIT 0x100240 + +#define mmMME4_RTR_LBW_RD_RS_E_ARB 0x100250 + +#define mmMME4_RTR_LBW_RD_RS_W_ARB 0x100254 + +#define mmMME4_RTR_LBW_RD_RS_N_ARB 0x100258 + +#define mmMME4_RTR_LBW_RD_RS_S_ARB 0x10025C + +#define mmMME4_RTR_LBW_RD_RS_L_ARB 0x100260 + +#define mmMME4_RTR_LBW_WR_RQ_E_ARB 0x100270 + +#define mmMME4_RTR_LBW_WR_RQ_W_ARB 0x100274 + +#define mmMME4_RTR_LBW_WR_RQ_N_ARB 0x100278 + +#define mmMME4_RTR_LBW_WR_RQ_S_ARB 0x10027C + +#define mmMME4_RTR_LBW_WR_RQ_L_ARB 0x100280 + +#define mmMME4_RTR_LBW_WR_RS_E_ARB 0x100290 + +#define mmMME4_RTR_LBW_WR_RS_W_ARB 0x100294 + +#define mmMME4_RTR_LBW_WR_RS_N_ARB 0x100298 + +#define mmMME4_RTR_LBW_WR_RS_S_ARB 0x10029C + +#define mmMME4_RTR_LBW_WR_RS_L_ARB 0x1002A0 + +#define mmMME4_RTR_DBG_E_ARB 0x100300 + +#define mmMME4_RTR_DBG_W_ARB 0x100304 + +#define mmMME4_RTR_DBG_N_ARB 0x100308 + +#define mmMME4_RTR_DBG_S_ARB 0x10030C + +#define mmMME4_RTR_DBG_L_ARB 0x100310 + +#define mmMME4_RTR_DBG_E_ARB_MAX 0x100320 + +#define mmMME4_RTR_DBG_W_ARB_MAX 0x100324 + +#define mmMME4_RTR_DBG_N_ARB_MAX 0x100328 + +#define mmMME4_RTR_DBG_S_ARB_MAX 0x10032C + +#define mmMME4_RTR_DBG_L_ARB_MAX 0x100330 + +#define mmMME4_RTR_SPLIT_COEF_0 0x100400 + +#define mmMME4_RTR_SPLIT_COEF_1 0x100404 + +#define mmMME4_RTR_SPLIT_COEF_2 0x100408 + +#define mmMME4_RTR_SPLIT_COEF_3 0x10040C + +#define mmMME4_RTR_SPLIT_COEF_4 0x100410 + +#define mmMME4_RTR_SPLIT_COEF_5 0x100414 + +#define mmMME4_RTR_SPLIT_COEF_6 0x100418 + +#define mmMME4_RTR_SPLIT_COEF_7 0x10041C + +#define mmMME4_RTR_SPLIT_COEF_8 0x100420 + +#define mmMME4_RTR_SPLIT_COEF_9 0x100424 + +#define mmMME4_RTR_SPLIT_CFG 0x100440 + +#define mmMME4_RTR_SPLIT_RD_SAT 0x100444 + +#define mmMME4_RTR_SPLIT_RD_RST_TOKEN 0x100448 + +#define mmMME4_RTR_SPLIT_RD_TIMEOUT_0 0x10044C + +#define mmMME4_RTR_SPLIT_RD_TIMEOUT_1 0x100450 + +#define mmMME4_RTR_SPLIT_WR_SAT 0x100454 + +#define mmMME4_RTR_WPLIT_WR_TST_TOLEN 0x100458 + +#define mmMME4_RTR_SPLIT_WR_TIMEOUT_0 0x10045C + +#define mmMME4_RTR_SPLIT_WR_TIMEOUT_1 0x100460 + +#define mmMME4_RTR_HBW_RANGE_HIT 0x100470 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_0 0x100480 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_1 0x100484 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_2 0x100488 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_3 0x10048C + +#define mmMME4_RTR_HBW_RANGE_MASK_L_4 0x100490 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_5 0x100494 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_6 0x100498 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_7 0x10049C + +#define mmMME4_RTR_HBW_RANGE_MASK_H_0 0x1004A0 + +#define mmMME4_RTR_HBW_RANGE_MASK_H_1 0x1004A4 + +#define mmMME4_RTR_HBW_RANGE_MASK_H_2 0x1004A8 + +#define mmMME4_RTR_HBW_RANGE_MASK_H_3 0x1004AC + +#define mmMME4_RTR_HBW_RANGE_MASK_H_4 0x1004B0 + +#define mmMME4_RTR_HBW_RANGE_MASK_H_5 0x1004B4 + +#define mmMME4_RTR_HBW_RANGE_MASK_H_6 0x1004B8 + +#define mmMME4_RTR_HBW_RANGE_MASK_H_7 0x1004BC + +#define mmMME4_RTR_HBW_RANGE_BASE_L_0 0x1004C0 + +#define mmMME4_RTR_HBW_RANGE_BASE_L_1 0x1004C4 + +#define mmMME4_RTR_HBW_RANGE_BASE_L_2 0x1004C8 + +#define mmMME4_RTR_HBW_RANGE_BASE_L_3 0x1004CC + +#define mmMME4_RTR_HBW_RANGE_BASE_L_4 0x1004D0 + +#define mmMME4_RTR_HBW_RANGE_BASE_L_5 0x1004D4 + +#define mmMME4_RTR_HBW_RANGE_BASE_L_6 0x1004D8 + +#define mmMME4_RTR_HBW_RANGE_BASE_L_7 0x1004DC + +#define mmMME4_RTR_HBW_RANGE_BASE_H_0 0x1004E0 + +#define mmMME4_RTR_HBW_RANGE_BASE_H_1 0x1004E4 + +#define mmMME4_RTR_HBW_RANGE_BASE_H_2 0x1004E8 + +#define mmMME4_RTR_HBW_RANGE_BASE_H_3 0x1004EC + +#define mmMME4_RTR_HBW_RANGE_BASE_H_4 0x1004F0 + +#define mmMME4_RTR_HBW_RANGE_BASE_H_5 0x1004F4 + +#define mmMME4_RTR_HBW_RANGE_BASE_H_6 0x1004F8 + +#define mmMME4_RTR_HBW_RANGE_BASE_H_7 0x1004FC + +#define mmMME4_RTR_LBW_RANGE_HIT 0x100500 + +#define mmMME4_RTR_LBW_RANGE_MASK_0 0x100510 + +#define mmMME4_RTR_LBW_RANGE_MASK_1 0x100514 + +#define mmMME4_RTR_LBW_RANGE_MASK_2 0x100518 + +#define mmMME4_RTR_LBW_RANGE_MASK_3 0x10051C + +#define mmMME4_RTR_LBW_RANGE_MASK_4 0x100520 + +#define mmMME4_RTR_LBW_RANGE_MASK_5 0x100524 + +#define mmMME4_RTR_LBW_RANGE_MASK_6 0x100528 + +#define mmMME4_RTR_LBW_RANGE_MASK_7 0x10052C + +#define mmMME4_RTR_LBW_RANGE_MASK_8 0x100530 + +#define mmMME4_RTR_LBW_RANGE_MASK_9 0x100534 + +#define mmMME4_RTR_LBW_RANGE_MASK_10 0x100538 + +#define mmMME4_RTR_LBW_RANGE_MASK_11 0x10053C + +#define mmMME4_RTR_LBW_RANGE_MASK_12 0x100540 + +#define mmMME4_RTR_LBW_RANGE_MASK_13 0x100544 + +#define mmMME4_RTR_LBW_RANGE_MASK_14 0x100548 + +#define mmMME4_RTR_LBW_RANGE_MASK_15 0x10054C + +#define mmMME4_RTR_LBW_RANGE_BASE_0 0x100550 + +#define mmMME4_RTR_LBW_RANGE_BASE_1 0x100554 + +#define mmMME4_RTR_LBW_RANGE_BASE_2 0x100558 + +#define mmMME4_RTR_LBW_RANGE_BASE_3 0x10055C + +#define mmMME4_RTR_LBW_RANGE_BASE_4 0x100560 + +#define mmMME4_RTR_LBW_RANGE_BASE_5 0x100564 + +#define mmMME4_RTR_LBW_RANGE_BASE_6 0x100568 + +#define mmMME4_RTR_LBW_RANGE_BASE_7 0x10056C + +#define mmMME4_RTR_LBW_RANGE_BASE_8 0x100570 + +#define mmMME4_RTR_LBW_RANGE_BASE_9 0x100574 + +#define mmMME4_RTR_LBW_RANGE_BASE_10 0x100578 + +#define mmMME4_RTR_LBW_RANGE_BASE_11 0x10057C + +#define mmMME4_RTR_LBW_RANGE_BASE_12 0x100580 + +#define mmMME4_RTR_LBW_RANGE_BASE_13 0x100584 + +#define mmMME4_RTR_LBW_RANGE_BASE_14 0x100588 + +#define mmMME4_RTR_LBW_RANGE_BASE_15 0x10058C + +#define mmMME4_RTR_RGLTR 0x100590 + +#define mmMME4_RTR_RGLTR_WR_RESULT 0x100594 + +#define mmMME4_RTR_RGLTR_RD_RESULT 0x100598 + +#define mmMME4_RTR_SCRAMB_EN 0x100600 + +#define mmMME4_RTR_NON_LIN_SCRAMB 0x100604 + +#endif /* ASIC_REG_MME4_RTR_REGS_H_ */ + |