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path: root/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cmdq_regs.h
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Diffstat (limited to 'drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cmdq_regs.h')
-rw-r--r--drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cmdq_regs.h139
1 files changed, 139 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cmdq_regs.h
new file mode 100644
index 000000000000..fbca6b47284e
--- /dev/null
+++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cmdq_regs.h
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC6_CMDQ_REGS_H_
+#define ASIC_REG_TPC6_CMDQ_REGS_H_
+
+/*
+ *****************************************
+ * TPC6_CMDQ (Prototype: CMDQ)
+ *****************************************
+ */
+
+#define mmTPC6_CMDQ_GLBL_CFG0 0xF89000
+
+#define mmTPC6_CMDQ_GLBL_CFG1 0xF89004
+
+#define mmTPC6_CMDQ_GLBL_PROT 0xF89008
+
+#define mmTPC6_CMDQ_GLBL_ERR_CFG 0xF8900C
+
+#define mmTPC6_CMDQ_GLBL_ERR_ADDR_LO 0xF89010
+
+#define mmTPC6_CMDQ_GLBL_ERR_ADDR_HI 0xF89014
+
+#define mmTPC6_CMDQ_GLBL_ERR_WDATA 0xF89018
+
+#define mmTPC6_CMDQ_GLBL_SECURE_PROPS 0xF8901C
+
+#define mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS 0xF89020
+
+#define mmTPC6_CMDQ_GLBL_STS0 0xF89024
+
+#define mmTPC6_CMDQ_GLBL_STS1 0xF89028
+
+#define mmTPC6_CMDQ_CQ_CFG0 0xF890B0
+
+#define mmTPC6_CMDQ_CQ_CFG1 0xF890B4
+
+#define mmTPC6_CMDQ_CQ_ARUSER 0xF890B8
+
+#define mmTPC6_CMDQ_CQ_PTR_LO 0xF890C0
+
+#define mmTPC6_CMDQ_CQ_PTR_HI 0xF890C4
+
+#define mmTPC6_CMDQ_CQ_TSIZE 0xF890C8
+
+#define mmTPC6_CMDQ_CQ_CTL 0xF890CC
+
+#define mmTPC6_CMDQ_CQ_PTR_LO_STS 0xF890D4
+
+#define mmTPC6_CMDQ_CQ_PTR_HI_STS 0xF890D8
+
+#define mmTPC6_CMDQ_CQ_TSIZE_STS 0xF890DC
+
+#define mmTPC6_CMDQ_CQ_CTL_STS 0xF890E0
+
+#define mmTPC6_CMDQ_CQ_STS0 0xF890E4
+
+#define mmTPC6_CMDQ_CQ_STS1 0xF890E8
+
+#define mmTPC6_CMDQ_CQ_RD_RATE_LIM_EN 0xF890F0
+
+#define mmTPC6_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xF890F4
+
+#define mmTPC6_CMDQ_CQ_RD_RATE_LIM_SAT 0xF890F8
+
+#define mmTPC6_CMDQ_CQ_RD_RATE_LIM_TOUT 0xF890FC
+
+#define mmTPC6_CMDQ_CQ_IFIFO_CNT 0xF89108
+
+#define mmTPC6_CMDQ_CP_MSG_BASE0_ADDR_LO 0xF89120
+
+#define mmTPC6_CMDQ_CP_MSG_BASE0_ADDR_HI 0xF89124
+
+#define mmTPC6_CMDQ_CP_MSG_BASE1_ADDR_LO 0xF89128
+
+#define mmTPC6_CMDQ_CP_MSG_BASE1_ADDR_HI 0xF8912C
+
+#define mmTPC6_CMDQ_CP_MSG_BASE2_ADDR_LO 0xF89130
+
+#define mmTPC6_CMDQ_CP_MSG_BASE2_ADDR_HI 0xF89134
+
+#define mmTPC6_CMDQ_CP_MSG_BASE3_ADDR_LO 0xF89138
+
+#define mmTPC6_CMDQ_CP_MSG_BASE3_ADDR_HI 0xF8913C
+
+#define mmTPC6_CMDQ_CP_LDMA_TSIZE_OFFSET 0xF89140
+
+#define mmTPC6_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xF89144
+
+#define mmTPC6_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xF89148
+
+#define mmTPC6_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xF8914C
+
+#define mmTPC6_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xF89150
+
+#define mmTPC6_CMDQ_CP_LDMA_COMMIT_OFFSET 0xF89154
+
+#define mmTPC6_CMDQ_CP_FENCE0_RDATA 0xF89158
+
+#define mmTPC6_CMDQ_CP_FENCE1_RDATA 0xF8915C
+
+#define mmTPC6_CMDQ_CP_FENCE2_RDATA 0xF89160
+
+#define mmTPC6_CMDQ_CP_FENCE3_RDATA 0xF89164
+
+#define mmTPC6_CMDQ_CP_FENCE0_CNT 0xF89168
+
+#define mmTPC6_CMDQ_CP_FENCE1_CNT 0xF8916C
+
+#define mmTPC6_CMDQ_CP_FENCE2_CNT 0xF89170
+
+#define mmTPC6_CMDQ_CP_FENCE3_CNT 0xF89174
+
+#define mmTPC6_CMDQ_CP_STS 0xF89178
+
+#define mmTPC6_CMDQ_CP_CURRENT_INST_LO 0xF8917C
+
+#define mmTPC6_CMDQ_CP_CURRENT_INST_HI 0xF89180
+
+#define mmTPC6_CMDQ_CP_BARRIER_CFG 0xF89184
+
+#define mmTPC6_CMDQ_CP_DBG_0 0xF89188
+
+#define mmTPC6_CMDQ_CQ_BUF_ADDR 0xF89308
+
+#define mmTPC6_CMDQ_CQ_BUF_RDATA 0xF8930C
+
+#endif /* ASIC_REG_TPC6_CMDQ_REGS_H_ */
+