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path: root/drivers/misc/pci_endpoint_test.c
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Diffstat (limited to 'drivers/misc/pci_endpoint_test.c')
-rw-r--r--drivers/misc/pci_endpoint_test.c132
1 files changed, 109 insertions, 23 deletions
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 09c10f426b64..deb203026496 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -72,6 +72,11 @@ static DEFINE_IDA(pci_endpoint_test_ida);
#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
miscdev)
+
+static bool no_msi;
+module_param(no_msi, bool, 0444);
+MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
+
enum pci_barno {
BAR_0,
BAR_1,
@@ -90,9 +95,15 @@ struct pci_endpoint_test {
/* mutex to protect the ioctls */
struct mutex mutex;
struct miscdevice miscdev;
+ enum pci_barno test_reg_bar;
+ size_t alignment;
};
-static int bar_size[] = { 4, 512, 1024, 16384, 131072, 1048576 };
+struct pci_endpoint_test_data {
+ enum pci_barno test_reg_bar;
+ size_t alignment;
+ bool no_msi;
+};
static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
u32 offset)
@@ -141,11 +152,15 @@ static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
int j;
u32 val;
int size;
+ struct pci_dev *pdev = test->pdev;
if (!test->bar[barno])
return false;
- size = bar_size[barno];
+ size = pci_resource_len(pdev, barno);
+
+ if (barno == test->test_reg_bar)
+ size = 0x4;
for (j = 0; j < size; j += 4)
pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
@@ -202,16 +217,32 @@ static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size)
dma_addr_t dst_phys_addr;
struct pci_dev *pdev = test->pdev;
struct device *dev = &pdev->dev;
+ void *orig_src_addr;
+ dma_addr_t orig_src_phys_addr;
+ void *orig_dst_addr;
+ dma_addr_t orig_dst_phys_addr;
+ size_t offset;
+ size_t alignment = test->alignment;
u32 src_crc32;
u32 dst_crc32;
- src_addr = dma_alloc_coherent(dev, size, &src_phys_addr, GFP_KERNEL);
- if (!src_addr) {
+ orig_src_addr = dma_alloc_coherent(dev, size + alignment,
+ &orig_src_phys_addr, GFP_KERNEL);
+ if (!orig_src_addr) {
dev_err(dev, "failed to allocate source buffer\n");
ret = false;
goto err;
}
+ if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) {
+ src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment);
+ offset = src_phys_addr - orig_src_phys_addr;
+ src_addr = orig_src_addr + offset;
+ } else {
+ src_phys_addr = orig_src_phys_addr;
+ src_addr = orig_src_addr;
+ }
+
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
lower_32_bits(src_phys_addr));
@@ -221,11 +252,21 @@ static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size)
get_random_bytes(src_addr, size);
src_crc32 = crc32_le(~0, src_addr, size);
- dst_addr = dma_alloc_coherent(dev, size, &dst_phys_addr, GFP_KERNEL);
- if (!dst_addr) {
+ orig_dst_addr = dma_alloc_coherent(dev, size + alignment,
+ &orig_dst_phys_addr, GFP_KERNEL);
+ if (!orig_dst_addr) {
dev_err(dev, "failed to allocate destination address\n");
ret = false;
- goto err_src_addr;
+ goto err_orig_src_addr;
+ }
+
+ if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) {
+ dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment);
+ offset = dst_phys_addr - orig_dst_phys_addr;
+ dst_addr = orig_dst_addr + offset;
+ } else {
+ dst_phys_addr = orig_dst_phys_addr;
+ dst_addr = orig_dst_addr;
}
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
@@ -245,10 +286,12 @@ static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size)
if (dst_crc32 == src_crc32)
ret = true;
- dma_free_coherent(dev, size, dst_addr, dst_phys_addr);
+ dma_free_coherent(dev, size + alignment, orig_dst_addr,
+ orig_dst_phys_addr);
-err_src_addr:
- dma_free_coherent(dev, size, src_addr, src_phys_addr);
+err_orig_src_addr:
+ dma_free_coherent(dev, size + alignment, orig_src_addr,
+ orig_src_phys_addr);
err:
return ret;
@@ -262,15 +305,29 @@ static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size)
dma_addr_t phys_addr;
struct pci_dev *pdev = test->pdev;
struct device *dev = &pdev->dev;
+ void *orig_addr;
+ dma_addr_t orig_phys_addr;
+ size_t offset;
+ size_t alignment = test->alignment;
u32 crc32;
- addr = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL);
- if (!addr) {
+ orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
+ GFP_KERNEL);
+ if (!orig_addr) {
dev_err(dev, "failed to allocate address\n");
ret = false;
goto err;
}
+ if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
+ phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
+ offset = phys_addr - orig_phys_addr;
+ addr = orig_addr + offset;
+ } else {
+ phys_addr = orig_phys_addr;
+ addr = orig_addr;
+ }
+
get_random_bytes(addr, size);
crc32 = crc32_le(~0, addr, size);
@@ -293,7 +350,7 @@ static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size)
if (reg & STATUS_READ_SUCCESS)
ret = true;
- dma_free_coherent(dev, size, addr, phys_addr);
+ dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr);
err:
return ret;
@@ -306,15 +363,29 @@ static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size)
dma_addr_t phys_addr;
struct pci_dev *pdev = test->pdev;
struct device *dev = &pdev->dev;
+ void *orig_addr;
+ dma_addr_t orig_phys_addr;
+ size_t offset;
+ size_t alignment = test->alignment;
u32 crc32;
- addr = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL);
- if (!addr) {
+ orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
+ GFP_KERNEL);
+ if (!orig_addr) {
dev_err(dev, "failed to allocate destination address\n");
ret = false;
goto err;
}
+ if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
+ phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
+ offset = phys_addr - orig_phys_addr;
+ addr = orig_addr + offset;
+ } else {
+ phys_addr = orig_phys_addr;
+ addr = orig_addr;
+ }
+
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
lower_32_bits(phys_addr));
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
@@ -331,7 +402,7 @@ static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size)
if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
ret = true;
- dma_free_coherent(dev, size, addr, phys_addr);
+ dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr);
err:
return ret;
}
@@ -383,13 +454,15 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev,
{
int i;
int err;
- int irq;
+ int irq = 0;
int id;
char name[20];
enum pci_barno bar;
void __iomem *base;
struct device *dev = &pdev->dev;
struct pci_endpoint_test *test;
+ struct pci_endpoint_test_data *data;
+ enum pci_barno test_reg_bar = BAR_0;
struct miscdevice *misc_device;
if (pci_is_bridge(pdev))
@@ -399,7 +472,17 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev,
if (!test)
return -ENOMEM;
+ test->test_reg_bar = 0;
+ test->alignment = 0;
test->pdev = pdev;
+
+ data = (struct pci_endpoint_test_data *)ent->driver_data;
+ if (data) {
+ test_reg_bar = data->test_reg_bar;
+ test->alignment = data->alignment;
+ no_msi = data->no_msi;
+ }
+
init_completion(&test->irq_raised);
mutex_init(&test->mutex);
@@ -417,9 +500,11 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev,
pci_set_master(pdev);
- irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
- if (irq < 0)
- dev_err(dev, "failed to get MSI interrupts\n");
+ if (!no_msi) {
+ irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
+ if (irq < 0)
+ dev_err(dev, "failed to get MSI interrupts\n");
+ }
err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
IRQF_SHARED, DRV_MODULE_NAME, test);
@@ -441,14 +526,15 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev,
base = pci_ioremap_bar(pdev, bar);
if (!base) {
dev_err(dev, "failed to read BAR%d\n", bar);
- WARN_ON(bar == BAR_0);
+ WARN_ON(bar == test_reg_bar);
}
test->bar[bar] = base;
}
- test->base = test->bar[0];
+ test->base = test->bar[test_reg_bar];
if (!test->base) {
- dev_err(dev, "Cannot perform PCI test without BAR0\n");
+ dev_err(dev, "Cannot perform PCI test without BAR%d\n",
+ test_reg_bar);
goto err_iounmap;
}
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.