diff options
Diffstat (limited to 'drivers/net/ethernet/apm/xgene/xgene_enet_hw.h')
| -rw-r--r-- | drivers/net/ethernet/apm/xgene/xgene_enet_hw.h | 34 |
1 files changed, 11 insertions, 23 deletions
diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h index 371e7a5b2507..38558584080e 100644 --- a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h @@ -42,6 +42,12 @@ static inline u32 xgene_get_bits(u32 val, u32 start, u32 end) return (val & GENMASK(end, start)) >> start; } +enum xgene_enet_rm { + RM0, + RM1, + RM3 = 3 +}; + #define CSR_RING_ID 0x0008 #define OVERWRITE BIT(31) #define IS_BUFFER_POOL BIT(20) @@ -52,7 +58,6 @@ static inline u32 xgene_get_bits(u32 val, u32 start, u32 end) #define CSR_RING_WR_BASE 0x0070 #define NUM_RING_CONFIG 5 #define BUFPOOL_MODE 3 -#define RM3 3 #define INC_DEC_CMD_ADDR 0x002c #define UDP_HDR_SIZE 2 #define BUF_LEN_CODE_2K 0x5000 @@ -94,11 +99,9 @@ static inline u32 xgene_get_bits(u32 val, u32 start, u32 end) #define BLOCK_ETH_CSR_OFFSET 0x2000 #define BLOCK_ETH_RING_IF_OFFSET 0x9000 -#define BLOCK_ETH_CLKRST_CSR_OFFSET 0xC000 #define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000 #define BLOCK_ETH_MAC_OFFSET 0x0000 -#define BLOCK_ETH_STATS_OFFSET 0x0014 #define BLOCK_ETH_MAC_CSR_OFFSET 0x2800 #define MAC_ADDR_REG_OFFSET 0x00 @@ -107,12 +110,6 @@ static inline u32 xgene_get_bits(u32 val, u32 start, u32 end) #define MAC_READ_REG_OFFSET 0x0c #define MAC_COMMAND_DONE_REG_OFFSET 0x10 -#define STAT_ADDR_REG_OFFSET 0x00 -#define STAT_COMMAND_REG_OFFSET 0x04 -#define STAT_WRITE_REG_OFFSET 0x08 -#define STAT_READ_REG_OFFSET 0x0c -#define STAT_COMMAND_DONE_REG_OFFSET 0x10 - #define MII_MGMT_CONFIG_ADDR 0x20 #define MII_MGMT_COMMAND_ADDR 0x24 #define MII_MGMT_ADDRESS_ADDR 0x28 @@ -147,6 +144,8 @@ static inline u32 xgene_get_bits(u32 val, u32 start, u32 end) #define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4) #define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2) #define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16) +#define CFG_CLE_DSTQID0(val) (val & GENMASK(11, 0)) +#define CFG_CLE_FPSEL0(val) ((val << 16) & GENMASK(19, 16)) #define ICM_CONFIG0_REG_0_ADDR 0x0400 #define ICM_CONFIG2_REG_0_ADDR 0x0410 #define RX_DV_GATE_REG_0_ADDR 0x05fc @@ -183,7 +182,6 @@ static inline u32 xgene_get_bits(u32 val, u32 start, u32 end) #define TUND_ADDR 0x4a #define TSO_IPPROTO_TCP 1 -#define FULL_DUPLEX 2 #define USERINFO_POS 0 #define USERINFO_LEN 32 @@ -318,20 +316,10 @@ void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring, struct xgene_enet_pdata *pdata, enum xgene_enet_err_code status); -void xgene_enet_reset(struct xgene_enet_pdata *priv); -void xgene_gmac_reset(struct xgene_enet_pdata *priv); -void xgene_gmac_init(struct xgene_enet_pdata *priv, int speed); -void xgene_gmac_tx_enable(struct xgene_enet_pdata *priv); -void xgene_gmac_rx_enable(struct xgene_enet_pdata *priv); -void xgene_gmac_tx_disable(struct xgene_enet_pdata *priv); -void xgene_gmac_rx_disable(struct xgene_enet_pdata *priv); -void xgene_gmac_set_mac_addr(struct xgene_enet_pdata *pdata); -void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata, - u32 dst_ring_num, u16 bufpool_id); -void xgene_gport_shutdown(struct xgene_enet_pdata *priv); -void xgene_gmac_get_tx_stats(struct xgene_enet_pdata *pdata); - int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata); void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata); +extern struct xgene_mac_ops xgene_gmac_ops; +extern struct xgene_port_ops xgene_gport_ops; + #endif /* __XGENE_ENET_HW_H__ */ |