diff options
Diffstat (limited to 'drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c')
| -rw-r--r-- | drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c | 506 |
1 files changed, 239 insertions, 267 deletions
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c index e4a22ce7bf09..819f6bcf9b4e 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c @@ -12,83 +12,89 @@ #include "../aq_hw.h" #include "../aq_hw_utils.h" #include "../aq_ring.h" +#include "../aq_nic.h" #include "hw_atl_b0.h" #include "hw_atl_utils.h" #include "hw_atl_llh.h" #include "hw_atl_b0_internal.h" #include "hw_atl_llh_internal.h" -static int hw_atl_b0_get_hw_caps(struct aq_hw_s *self, - struct aq_hw_caps_s *aq_hw_caps, - unsigned short device, - unsigned short subsystem_device) -{ - memcpy(aq_hw_caps, &hw_atl_b0_hw_caps_, sizeof(*aq_hw_caps)); - - if (device == HW_ATL_DEVICE_ID_D108 && subsystem_device == 0x0001) - aq_hw_caps->link_speed_msk &= ~HW_ATL_B0_RATE_10G; - - if (device == HW_ATL_DEVICE_ID_D109 && subsystem_device == 0x0001) { - aq_hw_caps->link_speed_msk &= ~HW_ATL_B0_RATE_10G; - aq_hw_caps->link_speed_msk &= ~HW_ATL_B0_RATE_5G; - } - - return 0; -} - -static struct aq_hw_s *hw_atl_b0_create(struct aq_pci_func_s *aq_pci_func, - unsigned int port, - struct aq_hw_ops *ops) -{ - struct hw_atl_s *self = NULL; - - self = kzalloc(sizeof(*self), GFP_KERNEL); - if (!self) - goto err_exit; - - self->base.aq_pci_func = aq_pci_func; +#define DEFAULT_B0_BOARD_BASIC_CAPABILITIES \ + .is_64_dma = true, \ + .msix_irqs = 4U, \ + .irq_mask = ~0U, \ + .vecs = HW_ATL_B0_RSS_MAX, \ + .tcs = HW_ATL_B0_TC_MAX, \ + .rxd_alignment = 1U, \ + .rxd_size = HW_ATL_B0_RXD_SIZE, \ + .rxds = 4U * 1024U, \ + .txd_alignment = 1U, \ + .txd_size = HW_ATL_B0_TXD_SIZE, \ + .txds = 8U * 1024U, \ + .txhwb_alignment = 4096U, \ + .tx_rings = HW_ATL_B0_TX_RINGS, \ + .rx_rings = HW_ATL_B0_RX_RINGS, \ + .hw_features = NETIF_F_HW_CSUM | \ + NETIF_F_RXCSUM | \ + NETIF_F_RXHASH | \ + NETIF_F_SG | \ + NETIF_F_TSO | \ + NETIF_F_LRO, \ + .hw_priv_flags = IFF_UNICAST_FLT, \ + .flow_control = true, \ + .mtu = HW_ATL_B0_MTU_JUMBO, \ + .mac_regs_count = 88, \ + .hw_alive_check_addr = 0x10U + +const struct aq_hw_caps_s hw_atl_b0_caps_aqc100 = { + DEFAULT_B0_BOARD_BASIC_CAPABILITIES, + .media_type = AQ_HW_MEDIA_TYPE_FIBRE, + .link_speed_msk = HW_ATL_B0_RATE_10G | + HW_ATL_B0_RATE_5G | + HW_ATL_B0_RATE_2G5 | + HW_ATL_B0_RATE_1G | + HW_ATL_B0_RATE_100M, +}; - self->base.not_ff_addr = 0x10U; +const struct aq_hw_caps_s hw_atl_b0_caps_aqc107 = { + DEFAULT_B0_BOARD_BASIC_CAPABILITIES, + .media_type = AQ_HW_MEDIA_TYPE_TP, + .link_speed_msk = HW_ATL_B0_RATE_10G | + HW_ATL_B0_RATE_5G | + HW_ATL_B0_RATE_2G5 | + HW_ATL_B0_RATE_1G | + HW_ATL_B0_RATE_100M, +}; -err_exit: - return (struct aq_hw_s *)self; -} +const struct aq_hw_caps_s hw_atl_b0_caps_aqc108 = { + DEFAULT_B0_BOARD_BASIC_CAPABILITIES, + .media_type = AQ_HW_MEDIA_TYPE_TP, + .link_speed_msk = HW_ATL_B0_RATE_5G | + HW_ATL_B0_RATE_2G5 | + HW_ATL_B0_RATE_1G | + HW_ATL_B0_RATE_100M, +}; -static void hw_atl_b0_destroy(struct aq_hw_s *self) -{ - kfree(self); -} +const struct aq_hw_caps_s hw_atl_b0_caps_aqc109 = { + DEFAULT_B0_BOARD_BASIC_CAPABILITIES, + .media_type = AQ_HW_MEDIA_TYPE_TP, + .link_speed_msk = HW_ATL_B0_RATE_2G5 | + HW_ATL_B0_RATE_1G | + HW_ATL_B0_RATE_100M, +}; static int hw_atl_b0_hw_reset(struct aq_hw_s *self) { int err = 0; - glb_glb_reg_res_dis_set(self, 1U); - pci_pci_reg_res_dis_set(self, 0U); - rx_rx_reg_res_dis_set(self, 0U); - tx_tx_reg_res_dis_set(self, 0U); - - HW_ATL_FLUSH(); - glb_soft_res_set(self, 1); - - /* check 10 times by 1ms */ - AQ_HW_WAIT_FOR(glb_soft_res_get(self) == 0, 1000U, 10U); - if (err < 0) - goto err_exit; - - itr_irq_reg_res_dis_set(self, 0U); - itr_res_irq_set(self, 1U); - - /* check 10 times by 1ms */ - AQ_HW_WAIT_FOR(itr_res_irq_get(self) == 0, 1000U, 10U); - if (err < 0) - goto err_exit; + err = hw_atl_utils_soft_reset(self); + if (err) + return err; - hw_atl_utils_mpi_set(self, MPI_RESET, 0x0U); + self->aq_fw_ops->set_state(self, MPI_RESET); err = aq_hw_err_from_flags(self); -err_exit: return err; } @@ -100,51 +106,53 @@ static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self) bool is_rx_flow_control = false; /* TPS Descriptor rate init */ - tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U); - tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA); + hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U); + hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA); /* TPS VM init */ - tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U); + hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U); /* TPS TC credits init */ - tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U); - tps_tx_pkt_shed_data_arb_mode_set(self, 0U); + hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U); + hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U); - tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U); - tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U); - tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U); - tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U); + hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U); + hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U); + hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U); + hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U); /* Tx buf size */ buff_size = HW_ATL_B0_TXBUF_MAX; - tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc); - tpb_tx_buff_hi_threshold_per_tc_set(self, - (buff_size * (1024 / 32U) * 66U) / - 100U, tc); - tpb_tx_buff_lo_threshold_per_tc_set(self, - (buff_size * (1024 / 32U) * 50U) / - 100U, tc); + hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc); + hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self, + (buff_size * + (1024 / 32U) * 66U) / + 100U, tc); + hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self, + (buff_size * + (1024 / 32U) * 50U) / + 100U, tc); /* QoS Rx buf size per TC */ tc = 0; is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control); buff_size = HW_ATL_B0_RXBUF_MAX; - rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc); - rpb_rx_buff_hi_threshold_per_tc_set(self, - (buff_size * - (1024U / 32U) * 66U) / - 100U, tc); - rpb_rx_buff_lo_threshold_per_tc_set(self, - (buff_size * - (1024U / 32U) * 50U) / - 100U, tc); - rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc); + hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc); + hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self, + (buff_size * + (1024U / 32U) * 66U) / + 100U, tc); + hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self, + (buff_size * + (1024U / 32U) * 50U) / + 100U, tc); + hw_atl_rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc); /* QoS 802.1p priority -> TC mapping */ for (i_priority = 8U; i_priority--;) - rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U); + hw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U); return aq_hw_err_from_flags(self); } @@ -152,20 +160,19 @@ static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self) static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self, struct aq_rss_parameters *rss_params) { - struct aq_nic_cfg_s *cfg = NULL; + struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; int err = 0; unsigned int i = 0U; unsigned int addr = 0U; - cfg = self->aq_nic_cfg; - for (i = 10, addr = 0U; i--; ++addr) { u32 key_data = cfg->is_rss ? __swab32(rss_params->hash_secret_key[i]) : 0U; - rpf_rss_key_wr_data_set(self, key_data); - rpf_rss_key_addr_set(self, addr); - rpf_rss_key_wr_en_set(self, 1U); - AQ_HW_WAIT_FOR(rpf_rss_key_wr_en_get(self) == 0, 1000U, 10U); + hw_atl_rpf_rss_key_wr_data_set(self, key_data); + hw_atl_rpf_rss_key_addr_set(self, addr); + hw_atl_rpf_rss_key_wr_en_set(self, 1U); + AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0, + 1000U, 10U); if (err < 0) goto err_exit; } @@ -194,11 +201,12 @@ static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self, ((i * 3U) & 0xFU)); } - for (i = AQ_DIMOF(bitary); i--;) { - rpf_rss_redir_tbl_wr_data_set(self, bitary[i]); - rpf_rss_redir_tbl_addr_set(self, i); - rpf_rss_redir_wr_en_set(self, 1U); - AQ_HW_WAIT_FOR(rpf_rss_redir_wr_en_get(self) == 0, 1000U, 10U); + for (i = ARRAY_SIZE(bitary); i--;) { + hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]); + hw_atl_rpf_rss_redir_tbl_addr_set(self, i); + hw_atl_rpf_rss_redir_wr_en_set(self, 1U); + AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0, + 1000U, 10U); if (err < 0) goto err_exit; } @@ -215,15 +223,15 @@ static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self, unsigned int i; /* TX checksums offloads*/ - tpo_ipv4header_crc_offload_en_set(self, 1); - tpo_tcp_udp_crc_offload_en_set(self, 1); + hw_atl_tpo_ipv4header_crc_offload_en_set(self, 1); + hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1); /* RX checksums offloads*/ - rpo_ipv4header_crc_offload_en_set(self, 1); - rpo_tcp_udp_crc_offload_en_set(self, 1); + hw_atl_rpo_ipv4header_crc_offload_en_set(self, 1); + hw_atl_rpo_tcp_udp_crc_offload_en_set(self, 1); /* LSO offloads*/ - tdm_large_send_offload_en_set(self, 0xFFFFFFFFU); + hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU); /* LRO offloads */ { @@ -232,43 +240,44 @@ static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self, ((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0)); for (i = 0; i < HW_ATL_B0_RINGS_MAX; i++) - rpo_lro_max_num_of_descriptors_set(self, val, i); + hw_atl_rpo_lro_max_num_of_descriptors_set(self, val, i); - rpo_lro_time_base_divider_set(self, 0x61AU); - rpo_lro_inactive_interval_set(self, 0); - rpo_lro_max_coalescing_interval_set(self, 2); + hw_atl_rpo_lro_time_base_divider_set(self, 0x61AU); + hw_atl_rpo_lro_inactive_interval_set(self, 0); + hw_atl_rpo_lro_max_coalescing_interval_set(self, 2); - rpo_lro_qsessions_lim_set(self, 1U); + hw_atl_rpo_lro_qsessions_lim_set(self, 1U); - rpo_lro_total_desc_lim_set(self, 2U); + hw_atl_rpo_lro_total_desc_lim_set(self, 2U); - rpo_lro_patch_optimization_en_set(self, 0U); + hw_atl_rpo_lro_patch_optimization_en_set(self, 0U); - rpo_lro_min_pay_of_first_pkt_set(self, 10U); + hw_atl_rpo_lro_min_pay_of_first_pkt_set(self, 10U); - rpo_lro_pkt_lim_set(self, 1U); + hw_atl_rpo_lro_pkt_lim_set(self, 1U); - rpo_lro_en_set(self, aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U); + hw_atl_rpo_lro_en_set(self, + aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U); } return aq_hw_err_from_flags(self); } static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self) { - thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U); - thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U); - thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU); + hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U); + hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U); + hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU); /* Tx interrupts */ - tdm_tx_desc_wr_wb_irq_en_set(self, 1U); + hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U); /* misc */ aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ? 0x00010000U : 0x00000000U); - tdm_tx_dca_en_set(self, 0U); - tdm_tx_dca_mode_set(self, 0U); + hw_atl_tdm_tx_dca_en_set(self, 0U); + hw_atl_tdm_tx_dca_mode_set(self, 0U); - tpb_tx_path_scp_ins_en_set(self, 1U); + hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U); return aq_hw_err_from_flags(self); } @@ -279,55 +288,55 @@ static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self) int i; /* Rx TC/RSS number config */ - rpb_rpf_rx_traf_class_mode_set(self, 1U); + hw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U); /* Rx flow control */ - rpb_rx_flow_ctl_mode_set(self, 1U); + hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U); /* RSS Ring selection */ - reg_rx_flr_rss_control1set(self, cfg->is_rss ? + hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ? 0xB3333333U : 0x00000000U); /* Multicast filters */ for (i = HW_ATL_B0_MAC_MAX; i--;) { - rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i); - rpfl2unicast_flr_act_set(self, 1U, i); + hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i); + hw_atl_rpfl2unicast_flr_act_set(self, 1U, i); } - reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U); - reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U); + hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U); + hw_atl_reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U); /* Vlan filters */ - rpf_vlan_outer_etht_set(self, 0x88A8U); - rpf_vlan_inner_etht_set(self, 0x8100U); + hw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U); + hw_atl_rpf_vlan_inner_etht_set(self, 0x8100U); if (cfg->vlan_id) { - rpf_vlan_flr_act_set(self, 1U, 0U); - rpf_vlan_id_flr_set(self, 0U, 0U); - rpf_vlan_flr_en_set(self, 0U, 0U); + hw_atl_rpf_vlan_flr_act_set(self, 1U, 0U); + hw_atl_rpf_vlan_id_flr_set(self, 0U, 0U); + hw_atl_rpf_vlan_flr_en_set(self, 0U, 0U); - rpf_vlan_accept_untagged_packets_set(self, 1U); - rpf_vlan_untagged_act_set(self, 1U); + hw_atl_rpf_vlan_accept_untagged_packets_set(self, 1U); + hw_atl_rpf_vlan_untagged_act_set(self, 1U); - rpf_vlan_flr_act_set(self, 1U, 1U); - rpf_vlan_id_flr_set(self, cfg->vlan_id, 0U); - rpf_vlan_flr_en_set(self, 1U, 1U); + hw_atl_rpf_vlan_flr_act_set(self, 1U, 1U); + hw_atl_rpf_vlan_id_flr_set(self, cfg->vlan_id, 0U); + hw_atl_rpf_vlan_flr_en_set(self, 1U, 1U); } else { - rpf_vlan_prom_mode_en_set(self, 1); + hw_atl_rpf_vlan_prom_mode_en_set(self, 1); } /* Rx Interrupts */ - rdm_rx_desc_wr_wb_irq_en_set(self, 1U); + hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U); /* misc */ aq_hw_write_reg(self, 0x00005040U, IS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U); - rpfl2broadcast_flr_act_set(self, 1U); - rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U)); + hw_atl_rpfl2broadcast_flr_act_set(self, 1U); + hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U)); - rdm_rx_dca_en_set(self, 0U); - rdm_rx_dca_mode_set(self, 0U); + hw_atl_rdm_rx_dca_en_set(self, 0U); + hw_atl_rdm_rx_dca_mode_set(self, 0U); return aq_hw_err_from_flags(self); } @@ -346,10 +355,10 @@ static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr) l = (mac_addr[2] << 24) | (mac_addr[3] << 16) | (mac_addr[4] << 8) | mac_addr[5]; - rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC); - rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC); - rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC); - rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC); + hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC); + hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC); + hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC); + hw_atl_rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC); err = aq_hw_err_from_flags(self); @@ -357,9 +366,7 @@ err_exit: return err; } -static int hw_atl_b0_hw_init(struct aq_hw_s *self, - struct aq_nic_cfg_s *aq_nic_cfg, - u8 *mac_addr) +static int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr) { static u32 aq_hw_atl_igcr_table_[4][2] = { { 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */ @@ -371,51 +378,50 @@ static int hw_atl_b0_hw_init(struct aq_hw_s *self, int err = 0; u32 val; - self->aq_nic_cfg = aq_nic_cfg; - - hw_atl_utils_hw_chip_features_init(self, - &PHAL_ATLANTIC_B0->chip_features); + struct aq_nic_cfg_s *aq_nic_cfg = self->aq_nic_cfg; hw_atl_b0_hw_init_tx_path(self); hw_atl_b0_hw_init_rx_path(self); hw_atl_b0_hw_mac_addr_set(self, mac_addr); - hw_atl_utils_mpi_set(self, MPI_INIT, aq_nic_cfg->link_speed_msk); + self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk); + self->aq_fw_ops->set_state(self, MPI_INIT); hw_atl_b0_hw_qos_set(self); hw_atl_b0_hw_rss_set(self, &aq_nic_cfg->aq_rss); hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss); /* Force limit MRRS on RDM/TDM to 2K */ - val = aq_hw_read_reg(self, pci_reg_control6_adr); - aq_hw_write_reg(self, pci_reg_control6_adr, (val & ~0x707) | 0x404); + val = aq_hw_read_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR); + aq_hw_write_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR, + (val & ~0x707) | 0x404); /* TX DMA total request limit. B0 hardware is not capable to * handle more than (8K-MRRS) incoming DMA data. * Value 24 in 256byte units */ - aq_hw_write_reg(self, tx_dma_total_req_limit_adr, 24); + aq_hw_write_reg(self, HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR, 24); /* Reset link status and read out initial hardware counters */ self->aq_link_status.mbps = 0; - hw_atl_utils_update_stats(self); + self->aq_fw_ops->update_stats(self); err = aq_hw_err_from_flags(self); if (err < 0) goto err_exit; /* Interrupts */ - reg_irq_glb_ctl_set(self, - aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type] + hw_atl_reg_irq_glb_ctl_set(self, + aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type] [(aq_nic_cfg->vecs > 1U) ? 1 : 0]); - itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask); + hw_atl_itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask); /* Interrupts */ - reg_gen_irq_map_set(self, - ((HW_ATL_B0_ERR_INT << 0x18) | (1U << 0x1F)) | + hw_atl_reg_gen_irq_map_set(self, + ((HW_ATL_B0_ERR_INT << 0x18) | (1U << 0x1F)) | ((HW_ATL_B0_ERR_INT << 0x10) | (1U << 0x17)), 0U); hw_atl_b0_hw_offload_set(self, aq_nic_cfg); @@ -427,28 +433,28 @@ err_exit: static int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self, struct aq_ring_s *ring) { - tdm_tx_desc_en_set(self, 1, ring->idx); + hw_atl_tdm_tx_desc_en_set(self, 1, ring->idx); return aq_hw_err_from_flags(self); } static int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self, struct aq_ring_s *ring) { - rdm_rx_desc_en_set(self, 1, ring->idx); + hw_atl_rdm_rx_desc_en_set(self, 1, ring->idx); return aq_hw_err_from_flags(self); } static int hw_atl_b0_hw_start(struct aq_hw_s *self) { - tpb_tx_buff_en_set(self, 1); - rpb_rx_buff_en_set(self, 1); + hw_atl_tpb_tx_buff_en_set(self, 1); + hw_atl_rpb_rx_buff_en_set(self, 1); return aq_hw_err_from_flags(self); } static int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self, struct aq_ring_s *ring) { - reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx); + hw_atl_reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx); return 0; } @@ -534,36 +540,36 @@ static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa; u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32); - rdm_rx_desc_en_set(self, false, aq_ring->idx); + hw_atl_rdm_rx_desc_en_set(self, false, aq_ring->idx); - rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx); + hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx); - reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw, - aq_ring->idx); + hw_atl_reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw, + aq_ring->idx); - reg_rx_dma_desc_base_addressmswset(self, - dma_desc_addr_msw, aq_ring->idx); + hw_atl_reg_rx_dma_desc_base_addressmswset(self, + dma_desc_addr_msw, aq_ring->idx); - rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx); + hw_atl_rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx); - rdm_rx_desc_data_buff_size_set(self, - AQ_CFG_RX_FRAME_MAX / 1024U, + hw_atl_rdm_rx_desc_data_buff_size_set(self, + AQ_CFG_RX_FRAME_MAX / 1024U, aq_ring->idx); - rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx); - rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx); - rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx); + hw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx); + hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx); + hw_atl_rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx); /* Rx ring set mode */ /* Mapping interrupt vector */ - itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx); - itr_irq_map_en_rx_set(self, true, aq_ring->idx); + hw_atl_itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx); + hw_atl_itr_irq_map_en_rx_set(self, true, aq_ring->idx); - rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx); - rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx); - rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx); - rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx); + hw_atl_rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx); + hw_atl_rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx); + hw_atl_rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx); + hw_atl_rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx); return aq_hw_err_from_flags(self); } @@ -575,25 +581,25 @@ static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa; u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32); - reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr, - aq_ring->idx); + hw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr, + aq_ring->idx); - reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr, - aq_ring->idx); + hw_atl_reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr, + aq_ring->idx); - tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx); + hw_atl_tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx); hw_atl_b0_hw_tx_ring_tail_update(self, aq_ring); /* Set Tx threshold */ - tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx); + hw_atl_tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx); /* Mapping interrupt vector */ - itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx); - itr_irq_map_en_tx_set(self, true, aq_ring->idx); + hw_atl_itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx); + hw_atl_itr_irq_map_en_tx_set(self, true, aq_ring->idx); - tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx); - tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx); + hw_atl_tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx); + hw_atl_tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx); return aq_hw_err_from_flags(self); } @@ -614,7 +620,7 @@ static int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self, rxd->hdr_addr = 0U; } - reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx); + hw_atl_reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx); return aq_hw_err_from_flags(self); } @@ -623,9 +629,9 @@ static int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self, struct aq_ring_s *ring) { int err = 0; - unsigned int hw_head_ = tdm_tx_desc_head_ptr_get(self, ring->idx); + unsigned int hw_head_ = hw_atl_tdm_tx_desc_head_ptr_get(self, ring->idx); - if (aq_utils_obj_test(&self->header.flags, AQ_HW_FLAG_ERR_UNPLUG)) { + if (aq_utils_obj_test(&self->flags, AQ_HW_FLAG_ERR_UNPLUG)) { err = -ENXIO; goto err_exit; } @@ -728,22 +734,22 @@ static int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self, static int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask) { - itr_irq_msk_setlsw_set(self, LODWORD(mask)); + hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask)); return aq_hw_err_from_flags(self); } static int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask) { - itr_irq_msk_clearlsw_set(self, LODWORD(mask)); - itr_irq_status_clearlsw_set(self, LODWORD(mask)); + hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask)); + hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask)); - atomic_inc(&PHAL_ATLANTIC_B0->dpc); + atomic_inc(&self->dpc); return aq_hw_err_from_flags(self); } static int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask) { - *mask = itr_irq_statuslsw_get(self); + *mask = hw_atl_itr_irq_statuslsw_get(self); return aq_hw_err_from_flags(self); } @@ -754,20 +760,20 @@ static int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self, { unsigned int i = 0U; - rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC)); - rpfl2multicast_flr_en_set(self, - IS_FILTER_ENABLED(IFF_MULTICAST), 0); + hw_atl_rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC)); + hw_atl_rpfl2multicast_flr_en_set(self, + IS_FILTER_ENABLED(IFF_MULTICAST), 0); - rpfl2_accept_all_mc_packets_set(self, - IS_FILTER_ENABLED(IFF_ALLMULTI)); + hw_atl_rpfl2_accept_all_mc_packets_set(self, + IS_FILTER_ENABLED(IFF_ALLMULTI)); - rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST)); + hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST)); self->aq_nic_cfg->is_mc_list_enabled = IS_FILTER_ENABLED(IFF_MULTICAST); for (i = HW_ATL_B0_MAC_MIN; i < HW_ATL_B0_MAC_MAX; ++i) - rpfl2_uc_flr_en_set(self, - (self->aq_nic_cfg->is_mc_list_enabled && + hw_atl_rpfl2_uc_flr_en_set(self, + (self->aq_nic_cfg->is_mc_list_enabled && (i <= self->aq_nic_cfg->mc_list_count)) ? 1U : 0U, i); @@ -796,16 +802,16 @@ static int hw_atl_b0_hw_multicast_list_set(struct aq_hw_s *self, u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) | (ar_mac[i][4] << 8) | ar_mac[i][5]; - rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC_MIN + i); + hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC_MIN + i); - rpfl2unicast_dest_addresslsw_set(self, - l, HW_ATL_B0_MAC_MIN + i); + hw_atl_rpfl2unicast_dest_addresslsw_set(self, + l, HW_ATL_B0_MAC_MIN + i); - rpfl2unicast_dest_addressmsw_set(self, - h, HW_ATL_B0_MAC_MIN + i); + hw_atl_rpfl2unicast_dest_addressmsw_set(self, + h, HW_ATL_B0_MAC_MIN + i); - rpfl2_uc_flr_en_set(self, - (self->aq_nic_cfg->is_mc_list_enabled), + hw_atl_rpfl2_uc_flr_en_set(self, + (self->aq_nic_cfg->is_mc_list_enabled), HW_ATL_B0_MAC_MIN + i); } @@ -824,10 +830,10 @@ static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self) switch (self->aq_nic_cfg->itr) { case AQ_CFG_INTERRUPT_MODERATION_ON: case AQ_CFG_INTERRUPT_MODERATION_AUTO: - tdm_tx_desc_wr_wb_irq_en_set(self, 0U); - tdm_tdm_intr_moder_en_set(self, 1U); - rdm_rx_desc_wr_wb_irq_en_set(self, 0U); - rdm_rdm_intr_moder_en_set(self, 1U); + hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 0U); + hw_atl_tdm_tdm_intr_moder_en_set(self, 1U); + hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 0U); + hw_atl_rdm_rdm_intr_moder_en_set(self, 1U); if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) { /* HW timers are in 2us units */ @@ -887,18 +893,18 @@ static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self) } break; case AQ_CFG_INTERRUPT_MODERATION_OFF: - tdm_tx_desc_wr_wb_irq_en_set(self, 1U); - tdm_tdm_intr_moder_en_set(self, 0U); - rdm_rx_desc_wr_wb_irq_en_set(self, 1U); - rdm_rdm_intr_moder_en_set(self, 0U); + hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U); + hw_atl_tdm_tdm_intr_moder_en_set(self, 0U); + hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U); + hw_atl_rdm_rdm_intr_moder_en_set(self, 0U); itr_tx = 0U; itr_rx = 0U; break; } for (i = HW_ATL_B0_RINGS_MAX; i--;) { - reg_tx_intr_moder_ctrl_set(self, itr_tx, i); - reg_rx_intr_moder_ctrl_set(self, itr_rx, i); + hw_atl_reg_tx_intr_moder_ctrl_set(self, itr_tx, i); + hw_atl_reg_rx_intr_moder_ctrl_set(self, itr_rx, i); } return aq_hw_err_from_flags(self); @@ -913,38 +919,19 @@ static int hw_atl_b0_hw_stop(struct aq_hw_s *self) static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, struct aq_ring_s *ring) { - tdm_tx_desc_en_set(self, 0U, ring->idx); + hw_atl_tdm_tx_desc_en_set(self, 0U, ring->idx); return aq_hw_err_from_flags(self); } static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, struct aq_ring_s *ring) { - rdm_rx_desc_en_set(self, 0U, ring->idx); + hw_atl_rdm_rx_desc_en_set(self, 0U, ring->idx); return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_set_speed(struct aq_hw_s *self, u32 speed) -{ - int err = 0; - - err = hw_atl_utils_mpi_set_speed(self, speed, MPI_INIT); - if (err < 0) - goto err_exit; - -err_exit: - return err; -} - -static struct aq_hw_ops hw_atl_ops_ = { - .create = hw_atl_b0_create, - .destroy = hw_atl_b0_destroy, - .get_hw_caps = hw_atl_b0_get_hw_caps, - - .hw_get_mac_permanent = hw_atl_utils_get_mac_permanent, +const struct aq_hw_ops hw_atl_ops_b0 = { .hw_set_mac_address = hw_atl_b0_hw_mac_addr_set, - .hw_get_link_status = hw_atl_utils_mpi_get_link_status, - .hw_set_link_speed = hw_atl_b0_hw_set_speed, .hw_init = hw_atl_b0_hw_init, .hw_deinit = hw_atl_utils_hw_deinit, .hw_set_power = hw_atl_utils_hw_set_power, @@ -974,21 +961,6 @@ static struct aq_hw_ops hw_atl_ops_ = { .hw_rss_set = hw_atl_b0_hw_rss_set, .hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set, .hw_get_regs = hw_atl_utils_hw_get_regs, - .hw_update_stats = hw_atl_utils_update_stats, .hw_get_hw_stats = hw_atl_utils_get_hw_stats, .hw_get_fw_version = hw_atl_utils_get_fw_version, }; - -struct aq_hw_ops *hw_atl_b0_get_ops_by_id(struct pci_dev *pdev) -{ - bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA); - bool is_did_ok = ((pdev->device == HW_ATL_DEVICE_ID_0001) || - (pdev->device == HW_ATL_DEVICE_ID_D100) || - (pdev->device == HW_ATL_DEVICE_ID_D107) || - (pdev->device == HW_ATL_DEVICE_ID_D108) || - (pdev->device == HW_ATL_DEVICE_ID_D109)); - - bool is_rev_ok = (pdev->revision == 2U); - - return (is_vid_ok && is_did_ok && is_rev_ok) ? &hw_atl_ops_ : NULL; -} |