diff options
Diffstat (limited to 'drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h')
| -rw-r--r-- | drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h | 619 |
1 files changed, 260 insertions, 359 deletions
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h index bb6b60814762..f43331224851 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h @@ -24,192 +24,186 @@ #define TX_DESC_SIZE_RTL8192S (16 * 4) #define TX_CMDDESC_SIZE_RTL8192S (16 * 4) -/* Define a macro that takes a le32 word, converts it to host ordering, - * right shifts by a specified count, creates a mask of the specified - * bit count, and extracts that number of bits. - */ - -#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \ - ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \ - BIT_LEN_MASK_32(__mask)) - -/* Define a macro that clears a bit field in an le32 word and - * sets the specified value into that bit field. The resulting - * value remains in le32 ordering; however, it is properly converted - * to host ordering for the clear and set operations before conversion - * back to le32. - */ - -#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \ - (*(__le32 *)(__pdesc) = \ - (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \ - (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \ - (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift))))); - /* macros to read/write various fields in RX or TX descriptors */ /* Dword 0 */ -#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val) -#define SET_TX_DESC_OFFSET(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val) -#define SET_TX_DESC_TYPE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val) -#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val) -#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val) -#define SET_TX_DESC_LINIP(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val) -#define SET_TX_DESC_AMSDU(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val) -#define SET_TX_DESC_GREEN_FIELD(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val) -#define SET_TX_DESC_OWN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val) - -#define GET_TX_DESC_OWN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 31, 1) +static inline void set_tx_desc_pkt_size(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits(__pdesc, __val, GENMASK(15, 0)); +} + +static inline void set_tx_desc_offset(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits(__pdesc, __val, GENMASK(23, 16)); +} + +static inline void set_tx_desc_last_seg(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits(__pdesc, __val, BIT(26)); +} + +static inline void set_tx_desc_first_seg(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits(__pdesc, __val, BIT(27)); +} + +static inline void set_tx_desc_linip(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits(__pdesc, __val, BIT(28)); +} + +static inline void set_tx_desc_own(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits(__pdesc, __val, BIT(31)); +} + +static inline u32 get_tx_desc_own(__le32 *__pdesc) +{ + return le32_get_bits(*(__pdesc), BIT(31)); +} /* Dword 1 */ -#define SET_TX_DESC_MACID(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val) -#define SET_TX_DESC_MORE_DATA(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 5, 1, __val) -#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 6, 1, __val) -#define SET_TX_DESC_PIFS(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 7, 1, __val) -#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 8, 5, __val) -#define SET_TX_DESC_ACK_POLICY(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 13, 2, __val) -#define SET_TX_DESC_NO_ACM(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val) -#define SET_TX_DESC_NON_QOS(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 16, 1, __val) -#define SET_TX_DESC_KEY_ID(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 17, 2, __val) -#define SET_TX_DESC_OUI(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 19, 1, __val) -#define SET_TX_DESC_PKT_TYPE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 20, 1, __val) -#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 21, 1, __val) -#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 22, 2, __val) -#define SET_TX_DESC_WDS(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val) -#define SET_TX_DESC_HTC(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val) -#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 26, 5, __val) -#define SET_TX_DESC_HWPC(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val) +static inline void set_tx_desc_macid(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 1), __val, GENMASK(4, 0)); +} + +static inline void set_tx_desc_queue_sel(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8)); +} + +static inline void set_tx_desc_non_qos(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 1), __val, BIT(16)); +} + +static inline void set_tx_desc_sec_type(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22)); +} /* Dword 2 */ -#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 8, 0, 6, __val) -#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 8, 6, 1, __val) -#define SET_TX_DESC_TSFL(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 8, 7, 5, __val) -#define SET_TX_DESC_RTS_RETRY_COUNT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 8, 12, 6, __val) -#define SET_TX_DESC_DATA_RETRY_COUNT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 8, 18, 6, __val) -#define SET_TX_DESC_RSVD_MACID(__pdesc, __val) \ - SET_BITS_OFFSET_LE(((__pdesc) + 8), 24, 5, __val) -#define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 8, 29, 1, __val) -#define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val) -#define SET_TX_DESC_OWN_MAC(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 8, 31, 1, __val) +static inline void set_tx_desc_rsvd_macid(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 2), __val, GENMASK(28, 24)); +} + +static inline void set_tx_desc_agg_enable(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 2), __val, BIT(29)); +} /* Dword 3 */ -#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 12, 0, 8, __val) -#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 12, 8, 8, __val) -#define SET_TX_DESC_SEQ(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 12, 16, 12, __val) -#define SET_TX_DESC_FRAG(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 12, 28, 4, __val) +static inline void set_tx_desc_seq(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 3), __val, GENMASK(27, 16)); +} /* Dword 4 */ -#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 0, 6, __val) -#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 6, 1, __val) -#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 7, 4, __val) -#define SET_TX_DESC_CTS_ENABLE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 11, 1, __val) -#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 12, 1, __val) -#define SET_TX_DESC_RA_BRSR_ID(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 13, 3, __val) -#define SET_TX_DESC_TXHT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 16, 1, __val) -#define SET_TX_DESC_TX_SHORT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 17, 1, __val) -#define SET_TX_DESC_TX_BANDWIDTH(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 18, 1, __val) -#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 19, 2, __val) -#define SET_TX_DESC_TX_STBC(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 21, 2, __val) -#define SET_TX_DESC_TX_REVERSE_DIRECTION(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 23, 1, __val) -#define SET_TX_DESC_RTS_HT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 24, 1, __val) -#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 25, 1, __val) -#define SET_TX_DESC_RTS_BANDWIDTH(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 26, 1, __val) -#define SET_TX_DESC_RTS_SUB_CARRIER(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 27, 2, __val) -#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 29, 2, __val) -#define SET_TX_DESC_USER_RATE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 31, 1, __val) +static inline void set_tx_desc_rts_rate(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 4), __val, GENMASK(5, 0)); +} + +static inline void set_tx_desc_cts_enable(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 4), __val, BIT(11)); +} + +static inline void set_tx_desc_rts_enable(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 4), __val, BIT(12)); +} + +static inline void set_tx_desc_ra_brsr_id(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 4), __val, GENMASK(15, 13)); +} + +static inline void set_tx_desc_txht(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 4), __val, BIT(16)); +} + +static inline void set_tx_desc_tx_short(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 4), __val, BIT(17)); +} + +static inline void set_tx_desc_tx_bandwidth(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 4), __val, BIT(18)); +} + +static inline void set_tx_desc_tx_sub_carrier(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 4), __val, GENMASK(20, 19)); +} + +static inline void set_tx_desc_rts_short(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 4), __val, BIT(25)); +} + +static inline void set_tx_desc_rts_bandwidth(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 4), __val, BIT(26)); +} + +static inline void set_tx_desc_rts_sub_carrier(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 4), __val, GENMASK(28, 27)); +} + +static inline void set_tx_desc_rts_stbc(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 4), __val, GENMASK(30, 29)); +} + +static inline void set_tx_desc_user_rate(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 4), __val, BIT(31)); +} /* Dword 5 */ -#define SET_TX_DESC_PACKET_ID(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 20, 0, 9, __val) -#define SET_TX_DESC_TX_RATE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 20, 9, 6, __val) -#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 20, 15, 1, __val) -#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 20, 16, 5, __val) -#define SET_TX_DESC_TX_AGC(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 20, 21, 11, __val) - -/* Dword 6 */ -#define SET_TX_DESC_IP_CHECK_SUM(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 24, 0, 16, __val) -#define SET_TX_DESC_TCP_CHECK_SUM(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 24, 16, 16, __val) +static inline void set_tx_desc_packet_id(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 5), __val, GENMASK(8, 0)); +} + +static inline void set_tx_desc_tx_rate(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 5), __val, GENMASK(14, 9)); +} + +static inline void set_tx_desc_data_rate_fb_limit(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 5), __val, GENMASK(20, 16)); +} /* Dword 7 */ -#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 28, 0, 16, __val) -#define SET_TX_DESC_IP_HEADER_OFFSET(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 28, 16, 8, __val) -#define SET_TX_DESC_TCP_ENABLE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 28, 31, 1, __val) +static inline void set_tx_desc_tx_buffer_size(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0)); +} /* Dword 8 */ -#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 32, 0, 32, __val) -#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 32, 0, 32) +static inline void set_tx_desc_tx_buffer_address(__le32 *__pdesc, u32 __val) +{ + *(__pdesc + 8) = cpu_to_le32(__val); +} + +static inline u32 get_tx_desc_tx_buffer_address(__le32 *__pdesc) +{ + return le32_to_cpu(*((__pdesc + 8))); +} /* Dword 9 */ -#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 36, 0, 32, __val) +static inline void set_tx_desc_next_desc_address(__le32 *__pdesc, u32 __val) +{ + *(__pdesc + 9) = cpu_to_le32(__val); +} /* Because the PCI Tx descriptors are chaied at the * initialization and all the NextDescAddresses in @@ -226,208 +220,115 @@ #define RX_DRV_INFO_SIZE_UNIT 8 /* DWORD 0 */ -#define SET_RX_STATUS_DESC_PKT_LEN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val) -#define SET_RX_STATUS_DESC_CRC32(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 14, 1, __val) -#define SET_RX_STATUS_DESC_ICV(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 15, 1, __val) -#define SET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 16, 4, __val) -#define SET_RX_STATUS_DESC_SECURITY(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 20, 3, __val) -#define SET_RX_STATUS_DESC_QOS(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 23, 1, __val) -#define SET_RX_STATUS_DESC_SHIFT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val) -#define SET_RX_STATUS_DESC_PHY_STATUS(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val) -#define SET_RX_STATUS_DESC_SWDEC(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val) -#define SET_RX_STATUS_DESC_LAST_SEG(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val) -#define SET_RX_STATUS_DESC_FIRST_SEG(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val) -#define SET_RX_STATUS_DESC_EOR(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val) -#define SET_RX_STATUS_DESC_OWN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val) - -#define GET_RX_STATUS_DESC_PKT_LEN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 0, 14) -#define GET_RX_STATUS_DESC_CRC32(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 14, 1) -#define GET_RX_STATUS_DESC_ICV(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 15, 1) -#define GET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 16, 4) -#define GET_RX_STATUS_DESC_SECURITY(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 20, 3) -#define GET_RX_STATUS_DESC_QOS(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 23, 1) -#define GET_RX_STATUS_DESC_SHIFT(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 24, 2) -#define GET_RX_STATUS_DESC_PHY_STATUS(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 26, 1) -#define GET_RX_STATUS_DESC_SWDEC(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 27, 1) -#define GET_RX_STATUS_DESC_LAST_SEG(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 28, 1) -#define GET_RX_STATUS_DESC_FIRST_SEG(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 29, 1) -#define GET_RX_STATUS_DESC_EOR(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 30, 1) -#define GET_RX_STATUS_DESC_OWN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 31, 1) +static inline void set_rx_status_desc_pkt_len(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits(__pdesc, __val, GENMASK(13, 0)); +} + +static inline void set_rx_status_desc_eor(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits(__pdesc, __val, BIT(30)); +} + +static inline void set_rx_status_desc_own(__le32 *__pdesc, u32 __val) +{ + le32p_replace_bits(__pdesc, __val, BIT(31)); +} + +static inline u32 get_rx_status_desc_pkt_len(__le32 *__pdesc) +{ + return le32_get_bits(*(__pdesc), GENMASK(13, 0)); +} + +static inline u32 get_rx_status_desc_crc32(__le32 *__pdesc) +{ + return le32_get_bits(*(__pdesc), BIT(14)); +} + +static inline u32 get_rx_status_desc_icv(__le32 *__pdesc) +{ + return le32_get_bits(*(__pdesc), BIT(15)); +} + +static inline u32 get_rx_status_desc_drvinfo_size(__le32 *__pdesc) +{ + return le32_get_bits(*(__pdesc), GENMASK(19, 16)); +} + +static inline u32 get_rx_status_desc_shift(__le32 *__pdesc) +{ + return le32_get_bits(*(__pdesc), GENMASK(25, 24)); +} + +static inline u32 get_rx_status_desc_phy_status(__le32 *__pdesc) +{ + return le32_get_bits(*(__pdesc), BIT(26)); +} + +static inline u32 get_rx_status_desc_swdec(__le32 *__pdesc) +{ + return le32_get_bits(*(__pdesc), BIT(27)); +} + +static inline u32 get_rx_status_desc_own(__le32 *__pdesc) +{ + return le32_get_bits(*(__pdesc), BIT(31)); +} /* DWORD 1 */ -#define SET_RX_STATUS_DESC_MACID(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val) -#define SET_RX_STATUS_DESC_TID(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 5, 4, __val) -#define SET_RX_STATUS_DESC_PAGGR(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 14, 1, __val) -#define SET_RX_STATUS_DESC_FAGGR(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val) -#define SET_RX_STATUS_DESC_A1_FIT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 16, 4, __val) -#define SET_RX_STATUS_DESC_A2_FIT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 20, 4, __val) -#define SET_RX_STATUS_DESC_PAM(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val) -#define SET_RX_STATUS_DESC_PWR(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val) -#define SET_RX_STATUS_DESC_MOREDATA(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 26, 1, __val) -#define SET_RX_STATUS_DESC_MOREFRAG(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val) -#define SET_RX_STATUS_DESC_TYPE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 28, 2, __val) -#define SET_RX_STATUS_DESC_MC(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 30, 1, __val) -#define SET_RX_STATUS_DESC_BC(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 4, 31, 1, __val) - -#define GET_RX_STATUS_DEC_MACID(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 4, 0, 5) -#define GET_RX_STATUS_DESC_TID(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 4, 5, 4) -#define GET_RX_STATUS_DESC_PAGGR(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 4, 14, 1) -#define GET_RX_STATUS_DESC_FAGGR(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 4, 15, 1) -#define GET_RX_STATUS_DESC_A1_FIT(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 4, 16, 4) -#define GET_RX_STATUS_DESC_A2_FIT(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 4, 20, 4) -#define GET_RX_STATUS_DESC_PAM(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 4, 24, 1) -#define GET_RX_STATUS_DESC_PWR(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 4, 25, 1) -#define GET_RX_STATUS_DESC_MORE_DATA(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 4, 26, 1) -#define GET_RX_STATUS_DESC_MORE_FRAG(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 4, 27, 1) -#define GET_RX_STATUS_DESC_TYPE(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 4, 28, 2) -#define GET_RX_STATUS_DESC_MC(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 4, 30, 1) -#define GET_RX_STATUS_DESC_BC(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 4, 31, 1) - -/* DWORD 2 */ -#define SET_RX_STATUS_DESC_SEQ(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 8, 0, 12, __val) -#define SET_RX_STATUS_DESC_FRAG(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 8, 12, 4, __val) -#define SET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 8, 16, 8, __val) -#define SET_RX_STATUS_DESC_NEXT_IND(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val) - -#define GET_RX_STATUS_DESC_SEQ(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 8, 0, 12) -#define GET_RX_STATUS_DESC_FRAG(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 8, 12, 4) -#define GET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 8, 16, 8) -#define GET_RX_STATUS_DESC_NEXT_IND(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 8, 30, 1) +static inline u32 get_rx_status_desc_paggr(__le32 *__pdesc) +{ + return le32_get_bits(*(__pdesc + 1), BIT(14)); +} + +static inline u32 get_rx_status_desc_faggr(__le32 *__pdesc) +{ + return le32_get_bits(*(__pdesc + 1), BIT(15)); +} /* DWORD 3 */ -#define SET_RX_STATUS_DESC_RX_MCS(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 12, 0, 6, __val) -#define SET_RX_STATUS_DESC_RX_HT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 12, 6, 1, __val) -#define SET_RX_STATUS_DESC_AMSDU(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 12, 7, 1, __val) -#define SET_RX_STATUS_DESC_SPLCP(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 12, 8, 1, __val) -#define SET_RX_STATUS_DESC_BW(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 12, 9, 1, __val) -#define SET_RX_STATUS_DESC_HTC(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 12, 10, 1, __val) -#define SET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 12, 11, 1, __val) -#define SET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 12, 12, 1, __val) -#define SET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 12, 13, 1, __val) -#define SET_RX_STATUS_DESC_HWPC_ERR(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 12, 14, 1, __val) -#define SET_RX_STATUS_DESC_HWPC_IND(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 12, 15, 1, __val) -#define SET_RX_STATUS_DESC_IV0(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 12, 16, 16, __val) - -#define GET_RX_STATUS_DESC_RX_MCS(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 12, 0, 6) -#define GET_RX_STATUS_DESC_RX_HT(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 12, 6, 1) -#define GET_RX_STATUS_DESC_AMSDU(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 12, 7, 1) -#define GET_RX_STATUS_DESC_SPLCP(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 12, 8, 1) -#define GET_RX_STATUS_DESC_BW(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 12, 9, 1) -#define GET_RX_STATUS_DESC_HTC(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 12, 10, 1) -#define GET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 12, 11, 1) -#define GET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 12, 12, 1) -#define GET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 12, 13, 1) -#define GET_RX_STATUS_DESC_HWPC_ERR(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 12, 14, 1) -#define GET_RX_STATUS_DESC_HWPC_IND(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 12, 15, 1) -#define GET_RX_STATUS_DESC_IV0(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 12, 16, 16) - -/* DWORD 4 */ -#define SET_RX_STATUS_DESC_IV1(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 16, 0, 32, __val) -#define GET_RX_STATUS_DESC_IV1(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 16, 0, 32) +static inline u32 get_rx_status_desc_rx_mcs(__le32 *__pdesc) +{ + return le32_get_bits(*(__pdesc + 3), GENMASK(5, 0)); +} + +static inline u32 get_rx_status_desc_rx_ht(__le32 *__pdesc) +{ + return le32_get_bits(*(__pdesc + 3), BIT(6)); +} + +static inline u32 get_rx_status_desc_splcp(__le32 *__pdesc) +{ + return le32_get_bits(*(__pdesc + 3), BIT(8)); +} + +static inline u32 get_rx_status_desc_bw(__le32 *__pdesc) +{ + return le32_get_bits(*(__pdesc + 3), BIT(9)); +} /* DWORD 5 */ -#define SET_RX_STATUS_DESC_TSFL(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 20, 0, 32, __val) -#define GET_RX_STATUS_DESC_TSFL(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 20, 0, 32) +static inline u32 get_rx_status_desc_tsfl(__le32 *__pdesc) +{ + return le32_to_cpu(*((__pdesc + 5))); +} /* DWORD 6 */ -#define SET_RX_STATUS__DESC_BUFF_ADDR(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc + 24, 0, 32, __val) -#define GET_RX_STATUS_DESC_BUFF_ADDR(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc + 24, 0, 32) +static inline void set_rx_status__desc_buff_addr(__le32 *__pdesc, u32 __val) +{ + *(__pdesc + 6) = cpu_to_le32(__val); +} + +static inline u32 get_rx_status_desc_buff_addr(__le32 *__pdesc) +{ + return le32_to_cpu(*(__pdesc + 6)); +} #define SE_RX_HAL_IS_CCK_RATE(_pdesc)\ - (GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE1M || \ - GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE2M || \ - GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE5_5M ||\ - GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE11M) + (get_rx_status_desc_rx_mcs(_pdesc) == DESC_RATE1M || \ + get_rx_status_desc_rx_mcs(_pdesc) == DESC_RATE2M || \ + get_rx_status_desc_rx_mcs(_pdesc) == DESC_RATE5_5M ||\ + get_rx_status_desc_rx_mcs(_pdesc) == DESC_RATE11M) enum rf_optype { RF_OP_BY_SW_3WIRE = 0, |