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path: root/drivers/net/wireless/realtek/rtw88/rtw8822c.c
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Diffstat (limited to 'drivers/net/wireless/realtek/rtw88/rtw8822c.c')
-rw-r--r--drivers/net/wireless/realtek/rtw88/rtw8822c.c136
1 files changed, 80 insertions, 56 deletions
diff --git a/drivers/net/wireless/realtek/rtw88/rtw8822c.c b/drivers/net/wireless/realtek/rtw88/rtw8822c.c
index e37300e98517..dd560c28abb2 100644
--- a/drivers/net/wireless/realtek/rtw88/rtw8822c.c
+++ b/drivers/net/wireless/realtek/rtw88/rtw8822c.c
@@ -18,6 +18,8 @@
#include "bf.h"
#include "efuse.h"
+#define IQK_DONE_8822C 0xaa
+
static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
u8 rx_path, bool is_tx2_path);
@@ -2110,20 +2112,17 @@ static void rtw8822c_do_iqk(struct rtw_dev *rtwdev)
{
struct rtw_iqk_para para = {0};
u8 iqk_chk;
- int counter;
+ int ret;
para.clear = 1;
rtw_fw_do_iqk(rtwdev, &para);
- for (counter = 0; counter < 300; counter++) {
- iqk_chk = rtw_read8(rtwdev, REG_RPT_CIP);
- if (iqk_chk == 0xaa)
- break;
- msleep(20);
- }
- rtw_write8(rtwdev, REG_IQKSTAT, 0x0);
+ ret = read_poll_timeout(rtw_read8, iqk_chk, iqk_chk == IQK_DONE_8822C,
+ 20000, 300000, false, rtwdev, REG_RPT_CIP);
+ if (ret)
+ rtw_warn(rtwdev, "failed to poll iqk status bit\n");
- rtw_dbg(rtwdev, RTW_DBG_RFK, "iqk counter=%d\n", counter);
+ rtw_write8(rtwdev, REG_IQKSTAT, 0x0);
}
/* for coex */
@@ -2132,28 +2131,28 @@ static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev)
/* enable TBTT nterrupt */
rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
- /* BT report packet sample rate */
+ /* BT report packet sample rate */
/* 0x790[5:0]=0x5 */
- rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05);
+ rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
/* enable BT counter statistics */
rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
/* enable PTA (3-wire function form BT side) */
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
- rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3);
+ rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
/* enable PTA (tx/rx signal form WiFi side) */
rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
/* wl tx signal to PTA not case EDCCA */
rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
/* GNT_BT=1 while select both */
- rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
- /* BT_CCA = ~GNT_WL_BB, (not or GNT_BT_BB, LTE_Rx */
+ rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
+ /* BT_CCA = ~GNT_WL_BB, not or GNT_BT_BB, LTE_Rx */
rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL);
/* to avoid RF parameter error */
- rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, 0x40000);
+ rtw_write_rf(rtwdev, RF_PATH_B, RF_MODOPT, 0xfffff, 0x40000);
}
static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
@@ -2190,10 +2189,10 @@ static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
* disable WL-S1 BB chage RF mode if GNT_BT
* since RF TRx mask can do it
*/
- rtw_write8_mask(rtwdev, 0x1c32, BIT(6), 1);
- rtw_write8_mask(rtwdev, 0x1c39, BIT(4), 0);
- rtw_write8_mask(rtwdev, 0x1c3b, BIT(4), 1);
- rtw_write8_mask(rtwdev, 0x4160, BIT(3), 1);
+ rtw_write8_mask(rtwdev, REG_ANAPAR + 2, BIT_ANAPAR_BTPS >> 16, 1);
+ rtw_write8_mask(rtwdev, REG_RSTB_SEL + 1, BIT_DAC_OFF_ENABLE, 0);
+ rtw_write8_mask(rtwdev, REG_RSTB_SEL + 3, BIT_DAC_OFF_ENABLE, 1);
+ rtw_write8_mask(rtwdev, REG_IGN_GNTBT4, BIT_PI_IGNORE_GNT_BT, 1);
/* disable WL-S0 BB chage RF mode if wifi is at 5G,
* or antenna path is separated
@@ -2201,26 +2200,32 @@ static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
if (coex_stat->wl_coex_mode == COEX_WLINK_5G ||
coex->under_5g || !efuse->share_ant) {
if (coex_stat->kt_ver >= 3) {
- rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0);
- rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 1);
+ rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
+ BIT_PI_IGNORE_GNT_BT, 0);
+ rtw_write8_mask(rtwdev, REG_NOMASK_TXBT,
+ BIT_NOMASK_TXBT_ENABLE, 1);
} else {
- rtw_write8_mask(rtwdev, 0x1860, BIT(3), 1);
+ rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
+ BIT_PI_IGNORE_GNT_BT, 1);
}
} else {
/* shared-antenna */
- rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0);
- if (coex_stat->kt_ver >= 3)
- rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 0);
+ rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
+ BIT_PI_IGNORE_GNT_BT, 0);
+ if (coex_stat->kt_ver >= 3) {
+ rtw_write8_mask(rtwdev, REG_NOMASK_TXBT,
+ BIT_NOMASK_TXBT_ENABLE, 0);
+ }
}
}
static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
{
- rtw_write8_mask(rtwdev, 0x66, BIT(4), 0);
- rtw_write8_mask(rtwdev, 0x67, BIT(0), 0);
- rtw_write8_mask(rtwdev, 0x42, BIT(3), 0);
- rtw_write8_mask(rtwdev, 0x65, BIT(7), 0);
- rtw_write8_mask(rtwdev, 0x73, BIT(3), 0);
+ rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0);
+ rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0);
+ rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0);
+ rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0);
+ rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0);
}
static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
@@ -2241,9 +2246,9 @@ static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
coex_rfe->wlg_at_btg = false;
/* disable LTE coex in wifi side */
- rtw_coex_write_indirect_reg(rtwdev, 0x38, BIT_LTE_COEX_EN, 0x0);
- rtw_coex_write_indirect_reg(rtwdev, 0xa0, MASKLWORD, 0xffff);
- rtw_coex_write_indirect_reg(rtwdev, 0xa4, MASKLWORD, 0xffff);
+ rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0);
+ rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
+ rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
}
static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
@@ -2268,16 +2273,22 @@ static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
coex_dm->cur_wl_rx_low_gain_en = low_gain;
if (coex_dm->cur_wl_rx_low_gain_en) {
+ rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n");
+
/* set Rx filter corner RCK offset */
- rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x22);
- rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x36);
- rtw_write_rf(rtwdev, RF_PATH_B, 0xde, 0xfffff, 0x22);
- rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x36);
+ rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x22);
+ rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x36);
+ rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x22);
+ rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x36);
+
} else {
+ rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n");
+
/* set Rx filter corner RCK offset */
- rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x20);
- rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x0);
- rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x0);
+ rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x20);
+ rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x0);
+ rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x20);
+ rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x0);
}
}
@@ -2442,7 +2453,7 @@ static void rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev *rtwdev, u8 path)
static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path)
{
u16 dc_i, dc_q;
- u8 corr_val, corr_idx;
+ u8 corr_idx;
rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0);
dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
@@ -2455,7 +2466,7 @@ static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path)
rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0));
- corr_val = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8));
+ rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8));
if (dc_i > 200 || dc_q > 200 || corr_idx < 40 || corr_idx > 65)
return 1;
@@ -3442,6 +3453,10 @@ rtw8822c_phy_cck_pd_set_reg(struct rtw_dev *rtwdev,
rtw8822c_cck_pd_reg[bw][nrx].reg_cs,
rtw8822c_cck_pd_reg[bw][nrx].mask_cs,
cs);
+
+ rtw_dbg(rtwdev, RTW_DBG_PHY,
+ "is_linked=%d, bw=%d, nrx=%d, cs_ratio=0x%x, pd_th=0x%x\n",
+ rtw_is_assoc(rtwdev), bw, nrx, cs, pd);
}
static void rtw8822c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
@@ -3455,6 +3470,10 @@ static void rtw8822c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000);
bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc);
+ rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d) bw=%d nr=%d cck_fa_avg=%d\n",
+ dm_info->cck_pd_lv[bw][nrx], new_lvl, bw, nrx,
+ dm_info->cck_fa_avg);
+
if (dm_info->cck_pd_lv[bw][nrx] == new_lvl)
return;
@@ -3983,14 +4002,14 @@ static const struct coex_table_para table_sant_8822c[] = {
{0xaaaaaaaa, 0xaaaaaaaa},
{0x5a5a5a5a, 0x5a5a5a5a},
{0xfafafafa, 0xfafafafa}, /* case-5 */
- {0x6a5a6a5a, 0xaaaaaaaa},
+ {0x6a5a5555, 0xaaaaaaaa},
{0x6a5a56aa, 0x6a5a56aa},
{0x6a5a5a5a, 0x6a5a5a5a},
{0x66555555, 0x5a5a5a5a},
{0x66555555, 0x6a5a5a5a}, /* case-10 */
- {0x66555555, 0xfafafafa},
+ {0x66555555, 0x6a5a5aaa},
{0x66555555, 0x5a5a5aaa},
- {0x66555555, 0x5aaa5aaa},
+ {0x66555555, 0x6aaa5aaa},
{0x66555555, 0xaaaa5aaa},
{0x66555555, 0xaaaaaaaa}, /* case-15 */
{0xffff55ff, 0xfafafafa},
@@ -4000,13 +4019,16 @@ static const struct coex_table_para table_sant_8822c[] = {
{0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
{0xaa5555aa, 0xaaaaaaaa},
{0xffffffff, 0x5a5a5a5a},
- {0xffffffff, 0x6a5a5a5a},
+ {0xffffffff, 0x5a5a5a5a},
{0xffffffff, 0x55555555},
- {0xffffffff, 0x6a5a5aaa}, /* case-25 */
+ {0xffffffff, 0x5a5a5aaa}, /* case-25 */
{0x55555555, 0x5a5a5a5a},
{0x55555555, 0xaaaaaaaa},
{0x55555555, 0x6a5a6a5a},
- {0x66556655, 0x66556655}
+ {0x66556655, 0x66556655},
+ {0x66556aaa, 0x6a5a6aaa}, /*case-30*/
+ {0xffffffff, 0x5aaa5aaa},
+ {0x56555555, 0x5a5a5aaa},
};
/* Non-Shared-Antenna Coex Table */
@@ -4026,12 +4048,12 @@ static const struct coex_table_para table_nsant_8822c[] = {
{0xffff55ff, 0xfafafafa},
{0xffff55ff, 0x5afa5afa},
{0xffff55ff, 0xaaaaaaaa},
- {0xaaffffaa, 0xfafafafa}, /* case-115 */
+ {0xffff55ff, 0xffff55ff}, /* case-115 */
{0xaaffffaa, 0x5afa5afa},
{0xaaffffaa, 0xaaaaaaaa},
{0xffffffff, 0xfafafafa},
{0xffffffff, 0x5afa5afa},
- {0xffffffff, 0xaaaaaaaa},/* case-120 */
+ {0xffffffff, 0xaaaaaaaa}, /* case-120 */
{0x55ff55ff, 0x5afa5afa},
{0x55ff55ff, 0xaaaaaaaa},
{0x55ff55ff, 0x55ff55ff}
@@ -4040,7 +4062,7 @@ static const struct coex_table_para table_nsant_8822c[] = {
/* Shared-Antenna TDMA */
static const struct coex_tdma_para tdma_sant_8822c[] = {
{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
- { {0x61, 0x45, 0x03, 0x11, 0x11} },
+ { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
{ {0x61, 0x3a, 0x03, 0x11, 0x11} },
{ {0x61, 0x30, 0x03, 0x11, 0x11} },
{ {0x61, 0x20, 0x03, 0x11, 0x11} },
@@ -4055,7 +4077,7 @@ static const struct coex_tdma_para tdma_sant_8822c[] = {
{ {0x51, 0x08, 0x03, 0x10, 0x54} },
{ {0x51, 0x08, 0x03, 0x10, 0x55} },
{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
- { {0x51, 0x45, 0x03, 0x10, 0x10} },
+ { {0x51, 0x45, 0x03, 0x10, 0x50} },
{ {0x51, 0x3a, 0x03, 0x10, 0x50} },
{ {0x51, 0x30, 0x03, 0x10, 0x50} },
{ {0x51, 0x20, 0x03, 0x10, 0x50} },
@@ -4063,7 +4085,7 @@ static const struct coex_tdma_para tdma_sant_8822c[] = {
{ {0x51, 0x4a, 0x03, 0x10, 0x50} },
{ {0x51, 0x0c, 0x03, 0x10, 0x54} },
{ {0x55, 0x08, 0x03, 0x10, 0x54} },
- { {0x65, 0x10, 0x03, 0x11, 0x11} },
+ { {0x65, 0x10, 0x03, 0x11, 0x10} },
{ {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
{ {0x51, 0x08, 0x03, 0x10, 0x50} },
{ {0x61, 0x08, 0x03, 0x11, 0x11} }
@@ -4091,7 +4113,8 @@ static const struct coex_tdma_para tdma_nsant_8822c[] = {
{ {0x51, 0x3a, 0x03, 0x10, 0x50} },
{ {0x51, 0x30, 0x03, 0x10, 0x50} },
{ {0x51, 0x20, 0x03, 0x10, 0x50} },
- { {0x51, 0x10, 0x03, 0x10, 0x50} } /* case-120 */
+ { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
+ { {0x51, 0x08, 0x03, 0x10, 0x50} }
};
/* rssi in percentage % (dbm = % - 100) */
@@ -4337,10 +4360,11 @@ struct rtw_chip_info rtw8822c_hw_spec = {
.wowlan_stub = &rtw_wowlan_stub_8822c,
.max_sched_scan_ssids = 4,
#endif
- .coex_para_ver = 0x20070217,
- .bt_desired_ver = 0x17,
+ .coex_para_ver = 0x201029,
+ .bt_desired_ver = 0x1c,
.scbd_support = true,
.new_scbd10_def = true,
+ .ble_hid_profile_support = true,
.pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
.bt_rssi_type = COEX_BTRSSI_DBM,
.ant_isolation = 15,
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.