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path: root/drivers/pci/probe.c
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Diffstat (limited to 'drivers/pci/probe.c')
-rw-r--r--drivers/pci/probe.c133
1 files changed, 85 insertions, 48 deletions
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 4c62d966d545..2c673a65d5b0 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -257,7 +257,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
sz64 = pci_size(l64, sz64, mask64);
if (!sz64) {
- dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
+ pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
pos);
goto fail;
}
@@ -268,7 +268,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
res->start = 0;
res->end = 0;
- dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
+ pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
pos, (unsigned long long)sz64);
goto out;
}
@@ -278,7 +278,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
res->flags |= IORESOURCE_UNSET;
res->start = 0;
res->end = sz64;
- dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
+ pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
pos, (unsigned long long)l64);
goto out;
}
@@ -305,7 +305,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
res->flags |= IORESOURCE_UNSET;
res->start = 0;
res->end = region.end - region.start;
- dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
+ pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
pos, (unsigned long long)region.start);
}
@@ -316,7 +316,7 @@ fail:
res->flags = 0;
out:
if (res->flags)
- dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
+ pci_printk(KERN_DEBUG, dev, "reg 0x%x: %pR\n", pos, res);
return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
}
@@ -379,7 +379,7 @@ static void pci_read_bridge_io(struct pci_bus *child)
region.start = base;
region.end = limit + io_granularity - 1;
pcibios_bus_to_resource(dev->bus, res, &region);
- dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
+ pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res);
}
}
@@ -401,7 +401,7 @@ static void pci_read_bridge_mmio(struct pci_bus *child)
region.start = base;
region.end = limit + 0xfffff;
pcibios_bus_to_resource(dev->bus, res, &region);
- dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
+ pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res);
}
}
@@ -441,7 +441,7 @@ static void pci_read_bridge_mmio_pref(struct pci_bus *child)
limit = (pci_bus_addr_t) limit64;
if (base != base64) {
- dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
+ pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
(unsigned long long) base64);
return;
}
@@ -454,7 +454,7 @@ static void pci_read_bridge_mmio_pref(struct pci_bus *child)
region.start = base;
region.end = limit + 0xfffff;
pcibios_bus_to_resource(dev->bus, res, &region);
- dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
+ pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res);
}
}
@@ -467,7 +467,7 @@ void pci_read_bridge_bases(struct pci_bus *child)
if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
return;
- dev_info(&dev->dev, "PCI bridge to %pR%s\n",
+ pci_info(dev, "PCI bridge to %pR%s\n",
&child->busn_res,
dev->transparent ? " (subtractive decode)" : "");
@@ -484,7 +484,7 @@ void pci_read_bridge_bases(struct pci_bus *child)
if (res && res->flags) {
pci_bus_add_resource(child, res,
PCI_SUBTRACTIVE_DECODE);
- dev_printk(KERN_DEBUG, &dev->dev,
+ pci_printk(KERN_DEBUG, dev,
" bridge window %pR (subtractive decode)\n",
res);
}
@@ -1005,11 +1005,11 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
secondary = (buses >> 8) & 0xFF;
subordinate = (buses >> 16) & 0xFF;
- dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
+ pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
secondary, subordinate, pass);
if (!primary && (primary != bus->number) && secondary && subordinate) {
- dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
+ pci_warn(dev, "Primary bus is hard wired to 0\n");
primary = bus->number;
}
@@ -1017,7 +1017,7 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
if (!pass &&
(primary != bus->number || secondary <= bus->number ||
secondary > subordinate)) {
- dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
+ pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
secondary, subordinate);
broken = 1;
}
@@ -1061,7 +1061,7 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
cmax = pci_scan_child_bus(child);
if (cmax > subordinate)
- dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
+ pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
subordinate, cmax);
/* Subordinate should equal child->busn_res.end */
@@ -1480,7 +1480,7 @@ int pci_setup_device(struct pci_dev *dev)
dev->revision = class & 0xff;
dev->class = class >> 8; /* upper 3 bytes */
- dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
+ pci_printk(KERN_DEBUG, dev, "[%04x:%04x] type %02x class %#08x\n",
dev->vendor, dev->device, dev->hdr_type, dev->class);
/* Need to have dev->class ready */
@@ -1501,7 +1501,7 @@ int pci_setup_device(struct pci_dev *dev)
if (dev->non_compliant_bars) {
pci_read_config_word(dev, PCI_COMMAND, &cmd);
if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
- dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
+ pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
cmd &= ~PCI_COMMAND_IO;
cmd &= ~PCI_COMMAND_MEMORY;
pci_write_config_word(dev, PCI_COMMAND, cmd);
@@ -1534,14 +1534,14 @@ int pci_setup_device(struct pci_dev *dev)
res = &dev->resource[0];
res->flags = LEGACY_IO_RESOURCE;
pcibios_bus_to_resource(dev->bus, res, &region);
- dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
+ pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
res);
region.start = 0x3F6;
region.end = 0x3F6;
res = &dev->resource[1];
res->flags = LEGACY_IO_RESOURCE;
pcibios_bus_to_resource(dev->bus, res, &region);
- dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
+ pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
res);
}
if ((progif & 4) == 0) {
@@ -1550,14 +1550,14 @@ int pci_setup_device(struct pci_dev *dev)
res = &dev->resource[2];
res->flags = LEGACY_IO_RESOURCE;
pcibios_bus_to_resource(dev->bus, res, &region);
- dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
+ pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
res);
region.start = 0x376;
region.end = 0x376;
res = &dev->resource[3];
res->flags = LEGACY_IO_RESOURCE;
pcibios_bus_to_resource(dev->bus, res, &region);
- dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
+ pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
res);
}
}
@@ -1593,12 +1593,12 @@ int pci_setup_device(struct pci_dev *dev)
break;
default: /* unknown header */
- dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
+ pci_err(dev, "unknown header type %02x, ignoring device\n",
dev->hdr_type);
return -EIO;
bad:
- dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
+ pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
dev->class, dev->hdr_type);
dev->class = PCI_CLASS_NOT_DEFINED << 8;
}
@@ -1622,7 +1622,7 @@ static void pci_configure_mps(struct pci_dev *dev)
return;
if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
- dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
+ pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
mps, pci_name(bridge), p_mps);
return;
}
@@ -1636,12 +1636,12 @@ static void pci_configure_mps(struct pci_dev *dev)
rc = pcie_set_mps(dev, p_mps);
if (rc) {
- dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
+ pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
p_mps);
return;
}
- dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
+ pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
p_mps, mps, 128 << dev->pcie_mpss);
}
@@ -1661,8 +1661,7 @@ static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
hpp = &pci_default_type0;
if (hpp->revision > 1) {
- dev_warn(&dev->dev,
- "PCI settings rev %d not supported; using defaults\n",
+ pci_warn(dev, "PCI settings rev %d not supported; using defaults\n",
hpp->revision);
hpp = &pci_default_type0;
}
@@ -1700,7 +1699,7 @@ static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
if (!pos)
return;
- dev_warn(&dev->dev, "PCI-X settings not supported\n");
+ pci_warn(dev, "PCI-X settings not supported\n");
}
static bool pcie_root_rcb_set(struct pci_dev *dev)
@@ -1730,7 +1729,7 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
return;
if (hpp->revision > 1) {
- dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
+ pci_warn(dev, "PCIe settings rev %d not supported\n",
hpp->revision);
return;
}
@@ -1835,7 +1834,7 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
*/
if (host->no_ext_tags) {
if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
- dev_info(&dev->dev, "disabling Extended Tags\n");
+ pci_info(dev, "disabling Extended Tags\n");
pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
PCI_EXP_DEVCTL_EXT_TAG);
}
@@ -1843,7 +1842,7 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
}
if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
- dev_info(&dev->dev, "enabling Extended Tags\n");
+ pci_info(dev, "enabling Extended Tags\n");
pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
PCI_EXP_DEVCTL_EXT_TAG);
}
@@ -1888,10 +1887,42 @@ static void pci_configure_relaxed_ordering(struct pci_dev *dev)
if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
PCI_EXP_DEVCTL_RELAX_EN);
- dev_info(&dev->dev, "Disable Relaxed Ordering because the Root Port didn't support it\n");
+ pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
}
}
+static void pci_configure_ltr(struct pci_dev *dev)
+{
+#ifdef CONFIG_PCIEASPM
+ u32 cap;
+ struct pci_dev *bridge;
+
+ if (!pci_is_pcie(dev))
+ return;
+
+ pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
+ if (!(cap & PCI_EXP_DEVCAP2_LTR))
+ return;
+
+ /*
+ * Software must not enable LTR in an Endpoint unless the Root
+ * Complex and all intermediate Switches indicate support for LTR.
+ * PCIe r3.1, sec 6.18.
+ */
+ if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
+ dev->ltr_path = 1;
+ else {
+ bridge = pci_upstream_bridge(dev);
+ if (bridge && bridge->ltr_path)
+ dev->ltr_path = 1;
+ }
+
+ if (dev->ltr_path)
+ pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
+ PCI_EXP_DEVCTL2_LTR_EN);
+#endif
+}
+
static void pci_configure_device(struct pci_dev *dev)
{
struct hotplug_params hpp;
@@ -1900,6 +1931,7 @@ static void pci_configure_device(struct pci_dev *dev)
pci_configure_mps(dev);
pci_configure_extended_tags(dev, NULL);
pci_configure_relaxed_ordering(dev);
+ pci_configure_ltr(dev);
memset(&hpp, 0, sizeof(hpp));
ret = pci_get_hp_params(dev, &hpp);
@@ -2233,22 +2265,27 @@ static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
static int only_one_child(struct pci_bus *bus)
{
- struct pci_dev *parent = bus->self;
+ struct pci_dev *bridge = bus->self;
- if (!parent || !pci_is_pcie(parent))
+ /*
+ * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
+ * we scan for all possible devices, not just Device 0.
+ */
+ if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
return 0;
- if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
- return 1;
/*
- * PCIe downstream ports are bridges that normally lead to only a
- * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
- * possible devices, not just device 0. See PCIe spec r3.0,
- * sec 7.3.1.
+ * A PCIe Downstream Port normally leads to a Link with only Device
+ * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
+ * only for Device 0 in that situation.
+ *
+ * Checking has_secondary_link is a hack to identify Downstream
+ * Ports because sometimes Switches are configured such that the
+ * PCIe Port Type labels are backwards.
*/
- if (parent->has_secondary_link &&
- !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
+ if (bridge && pci_is_pcie(bridge) && bridge->has_secondary_link)
return 1;
+
return 0;
}
@@ -2354,7 +2391,7 @@ static void pcie_write_mps(struct pci_dev *dev, int mps)
rc = pcie_set_mps(dev, mps);
if (rc)
- dev_err(&dev->dev, "Failed attempting to set the MPS\n");
+ pci_err(dev, "Failed attempting to set the MPS\n");
}
static void pcie_write_mrrs(struct pci_dev *dev)
@@ -2387,12 +2424,12 @@ static void pcie_write_mrrs(struct pci_dev *dev)
if (!rc)
break;
- dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
+ pci_warn(dev, "Failed attempting to set the MRRS\n");
mrrs /= 2;
}
if (mrrs < 128)
- dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
+ pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
}
static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
@@ -2412,7 +2449,7 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
pcie_write_mps(dev, mps);
pcie_write_mrrs(dev);
- dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
+ pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
pcie_get_mps(dev), 128 << dev->pcie_mpss,
orig_mps, pcie_get_readrq(dev));
@@ -2901,7 +2938,7 @@ int pci_hp_add_bridge(struct pci_dev *dev)
break;
}
if (busnr-- > end) {
- dev_err(&dev->dev, "No bus number available for hot-added bridge\n");
+ pci_err(dev, "No bus number available for hot-added bridge\n");
return -1;
}
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.