diff options
Diffstat (limited to 'drivers/pinctrl/aspeed')
| -rw-r--r-- | drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 70 | ||||
| -rw-r--r-- | drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 64 | ||||
| -rw-r--r-- | drivers/pinctrl/aspeed/pinctrl-aspeed.c | 21 | ||||
| -rw-r--r-- | drivers/pinctrl/aspeed/pinctrl-aspeed.h | 1 |
4 files changed, 143 insertions, 13 deletions
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c index cf3106cec048..05b153034517 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -1006,15 +1006,23 @@ SS_PIN_DECL(H3, GPIOQ5, SDA14); FUNC_GROUP_DECL(I2C14, H4, H3); -#define DASH9028_DESC SIG_DESC_SET(SCU90, 28) +/* + * There are several opportunities to document USB port 4 in the datasheet, but + * it is only mentioned in one location. Particularly, the Multi-function Pins + * Mapping and Control table in the datasheet elides the signal names, + * suggesting that port 4 may not actually be functional. As such we define the + * signal names and control bit, but don't export the capability's function or + * group. + */ +#define USB11H3_DESC SIG_DESC_SET(SCU90, 28) #define H2 134 -SIG_EXPR_LIST_DECL_SINGLE(DASHH2, DASHH2, DASH9028_DESC); -SS_PIN_DECL(H2, GPIOQ6, DASHH2); +SIG_EXPR_LIST_DECL_SINGLE(USB11HDP3, USB11H3, USB11H3_DESC); +SS_PIN_DECL(H2, GPIOQ6, USB11HDP3); #define H1 135 -SIG_EXPR_LIST_DECL_SINGLE(DASHH1, DASHH1, DASH9028_DESC); -SS_PIN_DECL(H1, GPIOQ7, DASHH1); +SIG_EXPR_LIST_DECL_SINGLE(USB11HDN3, USB11H3, USB11H3_DESC); +SS_PIN_DECL(H1, GPIOQ7, USB11HDN3); #define V20 136 SSSF_PIN_DECL(V20, GPIOR0, ROMCS1, SIG_DESC_SET(SCU88, 24)); @@ -1706,10 +1714,42 @@ FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20, R22, P18, P19, P20, P21, P22, M19, FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22, R22, P18, P19, P20, P21, P22, M19, M20, M21, M22, L18, L19); +#define USB11H2_DESC SIG_DESC_SET(SCU90, 3) +#define USB11D1_DESC SIG_DESC_BIT(SCU90, 3, 0) + +#define K4 220 +SIG_EXPR_LIST_DECL_SINGLE(USB11HDP2, USB11H2, USB11H2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(USB11DP1, USB11D1, USB11D1_DESC); +MS_PIN_DECL_(K4, SIG_EXPR_LIST_PTR(USB11HDP2), SIG_EXPR_LIST_PTR(USB11DP1)); + +#define K3 221 +SIG_EXPR_LIST_DECL_SINGLE(USB11HDN1, USB11H2, USB11H2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(USB11DDN1, USB11D1, USB11D1_DESC); +MS_PIN_DECL_(K3, SIG_EXPR_LIST_PTR(USB11HDN1), SIG_EXPR_LIST_PTR(USB11DDN1)); + +FUNC_GROUP_DECL(USB11H2, K4, K3); +FUNC_GROUP_DECL(USB11D1, K4, K3); + +#define USB2H1_DESC SIG_DESC_SET(SCU90, 29) +#define USB2D1_DESC SIG_DESC_BIT(SCU90, 29, 0) + +#define AB21 222 +SIG_EXPR_LIST_DECL_SINGLE(USB2HDP1, USB2H1, USB2H1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(USB2DDP1, USB2D1, USB2D1_DESC); +MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(USB2HDP1), SIG_EXPR_LIST_PTR(USB2DDP1)); + +#define AB20 223 +SIG_EXPR_LIST_DECL_SINGLE(USB2HDN1, USB2H1, USB2H1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(USB2DDN1, USB2D1, USB2D1_DESC); +MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(USB2HDN1), SIG_EXPR_LIST_PTR(USB2DDN1)); + +FUNC_GROUP_DECL(USB2H1, AB21, AB20); +FUNC_GROUP_DECL(USB2D1, AB21, AB20); + /* Note we account for GPIOY4-GPIOY7 even though they're not valid, thus 216 - * pins becomes 220. + * pins becomes 220. Four additional non-GPIO-capable pins are present for USB. */ -#define ASPEED_G4_NR_PINS 220 +#define ASPEED_G4_NR_PINS 224 /* Pins, groups and functions are sort(1):ed alphabetically for sanity */ @@ -1749,6 +1789,8 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = { ASPEED_PINCTRL_PIN(AB5), ASPEED_PINCTRL_PIN(AB6), ASPEED_PINCTRL_PIN(AB7), + ASPEED_PINCTRL_PIN(AB20), + ASPEED_PINCTRL_PIN(AB21), ASPEED_PINCTRL_PIN(B1), ASPEED_PINCTRL_PIN(B10), ASPEED_PINCTRL_PIN(B11), @@ -1848,6 +1890,8 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = { ASPEED_PINCTRL_PIN(J5), ASPEED_PINCTRL_PIN(K18), ASPEED_PINCTRL_PIN(K20), + ASPEED_PINCTRL_PIN(K3), + ASPEED_PINCTRL_PIN(K4), ASPEED_PINCTRL_PIN(K5), ASPEED_PINCTRL_PIN(L1), ASPEED_PINCTRL_PIN(L18), @@ -2070,6 +2114,10 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = { ASPEED_PINCTRL_GROUP(TXD3), ASPEED_PINCTRL_GROUP(TXD4), ASPEED_PINCTRL_GROUP(UART6), + ASPEED_PINCTRL_GROUP(USB11D1), + ASPEED_PINCTRL_GROUP(USB11H2), + ASPEED_PINCTRL_GROUP(USB2D1), + ASPEED_PINCTRL_GROUP(USB2H1), ASPEED_PINCTRL_GROUP(USBCKI), ASPEED_PINCTRL_GROUP(VGABIOS_ROM), ASPEED_PINCTRL_GROUP(VGAHS), @@ -2221,6 +2269,10 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = { ASPEED_PINCTRL_FUNC(TXD3), ASPEED_PINCTRL_FUNC(TXD4), ASPEED_PINCTRL_FUNC(UART6), + ASPEED_PINCTRL_FUNC(USB11D1), + ASPEED_PINCTRL_FUNC(USB11H2), + ASPEED_PINCTRL_FUNC(USB2D1), + ASPEED_PINCTRL_FUNC(USB2H1), ASPEED_PINCTRL_FUNC(USBCKI), ASPEED_PINCTRL_FUNC(VGABIOS_ROM), ASPEED_PINCTRL_FUNC(VGAHS), @@ -2349,7 +2401,7 @@ static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = { .nconfigs = ARRAY_SIZE(aspeed_g4_configs), }; -static struct pinmux_ops aspeed_g4_pinmux_ops = { +static const struct pinmux_ops aspeed_g4_pinmux_ops = { .get_functions_count = aspeed_pinmux_get_fn_count, .get_function_name = aspeed_pinmux_get_fn_name, .get_function_groups = aspeed_pinmux_get_fn_groups, @@ -2358,7 +2410,7 @@ static struct pinmux_ops aspeed_g4_pinmux_ops = { .strict = true, }; -static struct pinctrl_ops aspeed_g4_pinctrl_ops = { +static const struct pinctrl_ops aspeed_g4_pinctrl_ops = { .get_groups_count = aspeed_pinctrl_get_groups_count, .get_group_name = aspeed_pinctrl_get_group_name, .get_group_pins = aspeed_pinctrl_get_group_pins, diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index 68aa04664a62..187abd7693cf 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -25,7 +25,7 @@ #include "../pinctrl-utils.h" #include "pinctrl-aspeed.h" -#define ASPEED_G5_NR_PINS 232 +#define ASPEED_G5_NR_PINS 236 #define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 } #define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } @@ -1724,6 +1724,48 @@ FUNC_GROUP_DECL(LPCRST, G22); FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22); +#define A7 232 +SIG_EXPR_LIST_DECL_SINGLE(USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29)); +SIG_EXPR_LIST_DECL_SINGLE(USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0)); +MS_PIN_DECL_(A7, SIG_EXPR_LIST_PTR(USB2AHDP), SIG_EXPR_LIST_PTR(USB2ADDP)); + +#define A8 233 +SIG_EXPR_LIST_DECL_SINGLE(USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29)); +SIG_EXPR_LIST_DECL_SINGLE(USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0)); +MS_PIN_DECL_(A8, SIG_EXPR_LIST_PTR(USB2AHDN), SIG_EXPR_LIST_PTR(USB2ADDN)); + +FUNC_GROUP_DECL(USB2AH, A7, A8); +FUNC_GROUP_DECL(USB2AD, A7, A8); + +#define USB11BHID_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 0, 0 } +#define USB2BD_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 1, 0 } +#define USB2BH1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 2, 0 } +#define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 } + +#define B6 234 +SIG_EXPR_LIST_DECL_SINGLE(USB11BDP, USB11BHID, USB11BHID_DESC); +SIG_EXPR_LIST_DECL_SINGLE(USB2BDDP, USB2BD, USB2BD_DESC); +SIG_EXPR_DECL(USB2BHDP1, USB2BH, USB2BH1_DESC); +SIG_EXPR_DECL(USB2BHDP2, USB2BH, USB2BH2_DESC); +SIG_EXPR_LIST_DECL(USB2BHDP, SIG_EXPR_PTR(USB2BHDP1, USB2BH), + SIG_EXPR_PTR(USB2BHDP2, USB2BH)); +MS_PIN_DECL_(B6, SIG_EXPR_LIST_PTR(USB11BDP), SIG_EXPR_LIST_PTR(USB2BDDP), + SIG_EXPR_LIST_PTR(USB2BHDP)); + +#define A6 235 +SIG_EXPR_LIST_DECL_SINGLE(USB11BDN, USB11BHID, USB11BHID_DESC); +SIG_EXPR_LIST_DECL_SINGLE(USB2BDN, USB2BD, USB2BD_DESC); +SIG_EXPR_DECL(USB2BHDN1, USB2BH, USB2BH1_DESC); +SIG_EXPR_DECL(USB2BHDN2, USB2BH, USB2BH2_DESC); +SIG_EXPR_LIST_DECL(USB2BHDN, SIG_EXPR_PTR(USB2BHDN1, USB2BH), + SIG_EXPR_PTR(USB2BHDN2, USB2BH)); +MS_PIN_DECL_(A6, SIG_EXPR_LIST_PTR(USB11BDN), SIG_EXPR_LIST_PTR(USB2BDN), + SIG_EXPR_LIST_PTR(USB2BHDN)); + +FUNC_GROUP_DECL(USB11BHID, B6, A6); +FUNC_GROUP_DECL(USB2BD, B6, A6); +FUNC_GROUP_DECL(USB2BH, B6, A6); + /* Pins, groups and functions are sort(1):ed alphabetically for sanity */ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { @@ -1743,6 +1785,9 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { ASPEED_PINCTRL_PIN(A3), ASPEED_PINCTRL_PIN(A4), ASPEED_PINCTRL_PIN(A5), + ASPEED_PINCTRL_PIN(A6), + ASPEED_PINCTRL_PIN(A7), + ASPEED_PINCTRL_PIN(A8), ASPEED_PINCTRL_PIN(A9), ASPEED_PINCTRL_PIN(AA1), ASPEED_PINCTRL_PIN(AA19), @@ -1777,6 +1822,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { ASPEED_PINCTRL_PIN(B3), ASPEED_PINCTRL_PIN(B4), ASPEED_PINCTRL_PIN(B5), + ASPEED_PINCTRL_PIN(B6), ASPEED_PINCTRL_PIN(B9), ASPEED_PINCTRL_PIN(C1), ASPEED_PINCTRL_PIN(C11), @@ -2111,6 +2157,11 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = { ASPEED_PINCTRL_GROUP(TXD3), ASPEED_PINCTRL_GROUP(TXD4), ASPEED_PINCTRL_GROUP(UART6), + ASPEED_PINCTRL_GROUP(USB11BHID), + ASPEED_PINCTRL_GROUP(USB2AD), + ASPEED_PINCTRL_GROUP(USB2AH), + ASPEED_PINCTRL_GROUP(USB2BD), + ASPEED_PINCTRL_GROUP(USB2BH), ASPEED_PINCTRL_GROUP(USBCKI), ASPEED_PINCTRL_GROUP(VGABIOSROM), ASPEED_PINCTRL_GROUP(VGAHS), @@ -2275,6 +2326,11 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = { ASPEED_PINCTRL_FUNC(TXD3), ASPEED_PINCTRL_FUNC(TXD4), ASPEED_PINCTRL_FUNC(UART6), + ASPEED_PINCTRL_FUNC(USB11BHID), + ASPEED_PINCTRL_FUNC(USB2AD), + ASPEED_PINCTRL_FUNC(USB2AH), + ASPEED_PINCTRL_FUNC(USB2BD), + ASPEED_PINCTRL_FUNC(USB2BH), ASPEED_PINCTRL_FUNC(USBCKI), ASPEED_PINCTRL_FUNC(VGABIOSROM), ASPEED_PINCTRL_FUNC(VGAHS), @@ -2436,7 +2492,7 @@ static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = { .nconfigs = ARRAY_SIZE(aspeed_g5_configs), }; -static struct pinmux_ops aspeed_g5_pinmux_ops = { +static const struct pinmux_ops aspeed_g5_pinmux_ops = { .get_functions_count = aspeed_pinmux_get_fn_count, .get_function_name = aspeed_pinmux_get_fn_name, .get_function_groups = aspeed_pinmux_get_fn_groups, @@ -2445,7 +2501,7 @@ static struct pinmux_ops aspeed_g5_pinmux_ops = { .strict = true, }; -static struct pinctrl_ops aspeed_g5_pinctrl_ops = { +static const struct pinctrl_ops aspeed_g5_pinctrl_ops = { .get_groups_count = aspeed_pinctrl_get_groups_count, .get_group_name = aspeed_pinctrl_get_group_name, .get_group_pins = aspeed_pinctrl_get_group_pins, @@ -2454,7 +2510,7 @@ static struct pinctrl_ops aspeed_g5_pinctrl_ops = { .dt_free_map = pinctrl_utils_free_map, }; -static struct pinconf_ops aspeed_g5_conf_ops = { +static const struct pinconf_ops aspeed_g5_conf_ops = { .is_generic = true, .pin_config_get = aspeed_pin_config_get, .pin_config_set = aspeed_pin_config_set, diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index a86a4d66099c..7f13ce8450a3 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c @@ -213,6 +213,27 @@ static int aspeed_sig_expr_set(const struct aspeed_sig_expr *expr, if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2) continue; + /* On AST2500, Set bits in SCU7C are cleared from SCU70 */ + if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1) { + unsigned int rev_id; + + ret = regmap_read(maps[ASPEED_IP_SCU], + HW_REVISION_ID, &rev_id); + if (ret < 0) + return ret; + + if (0x04 == (rev_id >> 24)) { + u32 value = ~val & desc->mask; + + if (value) { + ret = regmap_write(maps[desc->ip], + HW_REVISION_ID, value); + if (ret < 0) + return ret; + } + } + } + ret = regmap_update_bits(maps[desc->ip], desc->reg, desc->mask, val); diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h index fa125db828f5..d4d7f032c1da 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h @@ -251,6 +251,7 @@ #define SCU3C 0x3C /* System Reset Control/Status Register */ #define SCU48 0x48 /* MAC Interface Clock Delay Setting */ #define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */ +#define HW_REVISION_ID 0x7C /* Silicon revision ID register */ #define SCU80 0x80 /* Multi-function Pin Control #1 */ #define SCU84 0x84 /* Multi-function Pin Control #2 */ #define SCU88 0x88 /* Multi-function Pin Control #3 */ |