diff options
Diffstat (limited to 'drivers/pinctrl/sh-pfc/pfc-r8a7795.c')
| -rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 915 |
1 files changed, 630 insertions, 285 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index ce4f5cdb0579..5979dabc02fa 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -189,8 +189,8 @@ #define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4) #define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0) #define GPSR6_2 F_(SSI_SDATA0, IP13_31_28) -#define GPSR6_1 F_(SSI_WS0129, IP13_27_24) -#define GPSR6_0 F_(SSI_SCK0129, IP13_23_20) +#define GPSR6_1 F_(SSI_WS01239, IP13_27_24) +#define GPSR6_0 F_(SSI_SCK01239, IP13_23_20) /* GPSR7 */ #define GPSR7_3 FM(HDMI1_CEC) @@ -315,8 +315,8 @@ #define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP13_23_20 FM(SSI_SCK0129) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP13_27_24 FM(SSI_WS0129) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -478,7 +478,6 @@ FM(IP16_31_28) IP16_31_28 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) -#define MOD_SEL2_2_1 FM(SEL_VSP_0) FM(SEL_VSP_1) FM(SEL_VSP_2) FM(SEL_VSP_3) #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) #define PINMUX_MOD_SELS\ @@ -512,7 +511,7 @@ MOD_SEL0_7_6 \ MOD_SEL0_5_4 MOD_SEL1_5 \ MOD_SEL1_4 \ MOD_SEL0_3 MOD_SEL1_3 \ -MOD_SEL0_2_1 MOD_SEL1_2 MOD_SEL2_2_1 \ +MOD_SEL0_2_1 MOD_SEL1_2 \ MOD_SEL1_1 \ MOD_SEL1_0 MOD_SEL2_0 @@ -569,18 +568,18 @@ static const u16 pinmux_data[] = { PINMUX_SINGLE(SSI_WS5), /* IPSR0 */ - PINMUX_IPSR_DATA(IP0_3_0, AVB_MDC), + PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), - PINMUX_IPSR_DATA(IP0_7_4, AVB_MAGIC), + PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), - PINMUX_IPSR_DATA(IP0_11_8, AVB_PHY_INT), + PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), - PINMUX_IPSR_DATA(IP0_15_12, AVB_LINK), + PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), @@ -592,126 +591,126 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0), - PINMUX_IPSR_DATA(IP0_27_24, IRQ0), - PINMUX_IPSR_DATA(IP0_27_24, QPOLB), - PINMUX_IPSR_DATA(IP0_27_24, DU_CDE), + PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), + PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), + PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), - PINMUX_IPSR_DATA(IP0_31_28, IRQ1), - PINMUX_IPSR_DATA(IP0_31_28, QPOLA), - PINMUX_IPSR_DATA(IP0_31_28, DU_DISP), + PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), + PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), + PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), /* IPSR1 */ - PINMUX_IPSR_DATA(IP1_3_0, IRQ2), - PINMUX_IPSR_DATA(IP1_3_0, QCPV_QDE), - PINMUX_IPSR_DATA(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), + PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), + PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), + PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), - PINMUX_IPSR_DATA(IP1_7_4, IRQ3), - PINMUX_IPSR_DATA(IP1_7_4, QSTVB_QVE), - PINMUX_IPSR_DATA(IP1_7_4, A25), - PINMUX_IPSR_DATA(IP1_7_4, DU_DOTCLKOUT1), + PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), + PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), + PINMUX_IPSR_GPSR(IP1_7_4, A25), + PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), - PINMUX_IPSR_DATA(IP1_11_8, IRQ4), - PINMUX_IPSR_DATA(IP1_11_8, QSTH_QHS), - PINMUX_IPSR_DATA(IP1_11_8, A24), - PINMUX_IPSR_DATA(IP1_11_8, DU_EXHSYNC_DU_HSYNC), + PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), + PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), + PINMUX_IPSR_GPSR(IP1_11_8, A24), + PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), - PINMUX_IPSR_DATA(IP1_15_12, IRQ5), - PINMUX_IPSR_DATA(IP1_15_12, QSTB_QHE), - PINMUX_IPSR_DATA(IP1_15_12, A23), - PINMUX_IPSR_DATA(IP1_15_12, DU_EXVSYNC_DU_VSYNC), + PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), + PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), + PINMUX_IPSR_GPSR(IP1_15_12, A23), + PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), - PINMUX_IPSR_DATA(IP1_19_16, PWM0), - PINMUX_IPSR_DATA(IP1_19_16, AVB_AVTP_PPS), - PINMUX_IPSR_DATA(IP1_19_16, A22), + PINMUX_IPSR_GPSR(IP1_19_16, PWM0), + PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), + PINMUX_IPSR_GPSR(IP1_19_16, A22), PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), - PINMUX_IPSR_DATA(IP1_23_20, A21), + PINMUX_IPSR_GPSR(IP1_23_20, A21), PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), - PINMUX_IPSR_DATA(IP1_27_24, A20), + PINMUX_IPSR_GPSR(IP1_27_24, A20), PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), - PINMUX_IPSR_DATA(IP1_31_28, A0), - PINMUX_IPSR_DATA(IP1_31_28, LCDOUT16), + PINMUX_IPSR_GPSR(IP1_31_28, A0), + PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), - PINMUX_IPSR_DATA(IP1_31_28, VI4_DATA8), - PINMUX_IPSR_DATA(IP1_31_28, DU_DB0), + PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), + PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), /* IPSR2 */ - PINMUX_IPSR_DATA(IP2_3_0, A1), - PINMUX_IPSR_DATA(IP2_3_0, LCDOUT17), + PINMUX_IPSR_GPSR(IP2_3_0, A1), + PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), - PINMUX_IPSR_DATA(IP2_3_0, VI4_DATA9), - PINMUX_IPSR_DATA(IP2_3_0, DU_DB1), + PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), + PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), - PINMUX_IPSR_DATA(IP2_7_4, A2), - PINMUX_IPSR_DATA(IP2_7_4, LCDOUT18), + PINMUX_IPSR_GPSR(IP2_7_4, A2), + PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), - PINMUX_IPSR_DATA(IP2_7_4, VI4_DATA10), - PINMUX_IPSR_DATA(IP2_7_4, DU_DB2), + PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), + PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), - PINMUX_IPSR_DATA(IP2_11_8, A3), - PINMUX_IPSR_DATA(IP2_11_8, LCDOUT19), + PINMUX_IPSR_GPSR(IP2_11_8, A3), + PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), - PINMUX_IPSR_DATA(IP2_11_8, VI4_DATA11), - PINMUX_IPSR_DATA(IP2_11_8, DU_DB3), + PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), + PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), - PINMUX_IPSR_DATA(IP2_15_12, A4), - PINMUX_IPSR_DATA(IP2_15_12, LCDOUT20), + PINMUX_IPSR_GPSR(IP2_15_12, A4), + PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), - PINMUX_IPSR_DATA(IP2_15_12, VI4_DATA12), - PINMUX_IPSR_DATA(IP2_15_12, VI5_DATA12), - PINMUX_IPSR_DATA(IP2_15_12, DU_DB4), + PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), + PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), + PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), - PINMUX_IPSR_DATA(IP2_19_16, A5), - PINMUX_IPSR_DATA(IP2_19_16, LCDOUT21), + PINMUX_IPSR_GPSR(IP2_19_16, A5), + PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), - PINMUX_IPSR_DATA(IP2_19_16, VI4_DATA13), - PINMUX_IPSR_DATA(IP2_19_16, VI5_DATA13), - PINMUX_IPSR_DATA(IP2_19_16, DU_DB5), + PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), + PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), + PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), - PINMUX_IPSR_DATA(IP2_23_20, A6), - PINMUX_IPSR_DATA(IP2_23_20, LCDOUT22), + PINMUX_IPSR_GPSR(IP2_23_20, A6), + PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), - PINMUX_IPSR_DATA(IP2_23_20, VI4_DATA14), - PINMUX_IPSR_DATA(IP2_23_20, VI5_DATA14), - PINMUX_IPSR_DATA(IP2_23_20, DU_DB6), + PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), + PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), + PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), - PINMUX_IPSR_DATA(IP2_27_24, A7), - PINMUX_IPSR_DATA(IP2_27_24, LCDOUT23), + PINMUX_IPSR_GPSR(IP2_27_24, A7), + PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), - PINMUX_IPSR_DATA(IP2_27_24, VI4_DATA15), - PINMUX_IPSR_DATA(IP2_27_24, VI5_DATA15), - PINMUX_IPSR_DATA(IP2_27_24, DU_DB7), + PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), + PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), + PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), - PINMUX_IPSR_DATA(IP2_31_28, A8), + PINMUX_IPSR_GPSR(IP2_31_28, A8), PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), @@ -720,99 +719,99 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), /* IPSR3 */ - PINMUX_IPSR_DATA(IP3_3_0, A9), + PINMUX_IPSR_GPSR(IP3_3_0, A9), PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), - PINMUX_IPSR_DATA(IP3_3_0, VI5_VSYNC_N), + PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), - PINMUX_IPSR_DATA(IP3_7_4, A10), + PINMUX_IPSR_GPSR(IP3_7_4, A10), PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1), - PINMUX_IPSR_DATA(IP3_7_4, VI5_HSYNC_N), + PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), - PINMUX_IPSR_DATA(IP3_11_8, A11), + PINMUX_IPSR_GPSR(IP3_11_8, A11), PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), - PINMUX_IPSR_DATA(IP3_11_8, HSCK4), - PINMUX_IPSR_DATA(IP3_11_8, VI5_FIELD), + PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), + PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), - PINMUX_IPSR_DATA(IP3_15_12, A12), - PINMUX_IPSR_DATA(IP3_15_12, LCDOUT12), + PINMUX_IPSR_GPSR(IP3_15_12, A12), + PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), - PINMUX_IPSR_DATA(IP3_15_12, VI5_DATA8), - PINMUX_IPSR_DATA(IP3_15_12, DU_DG4), + PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), + PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), - PINMUX_IPSR_DATA(IP3_19_16, A13), - PINMUX_IPSR_DATA(IP3_19_16, LCDOUT13), + PINMUX_IPSR_GPSR(IP3_19_16, A13), + PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), - PINMUX_IPSR_DATA(IP3_19_16, VI5_DATA9), - PINMUX_IPSR_DATA(IP3_19_16, DU_DG5), + PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), + PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), - PINMUX_IPSR_DATA(IP3_23_20, A14), - PINMUX_IPSR_DATA(IP3_23_20, LCDOUT14), + PINMUX_IPSR_GPSR(IP3_23_20, A14), + PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), - PINMUX_IPSR_DATA(IP3_23_20, HCTS4_N), - PINMUX_IPSR_DATA(IP3_23_20, VI5_DATA10), - PINMUX_IPSR_DATA(IP3_23_20, DU_DG6), + PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), + PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), + PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), - PINMUX_IPSR_DATA(IP3_27_24, A15), - PINMUX_IPSR_DATA(IP3_27_24, LCDOUT15), + PINMUX_IPSR_GPSR(IP3_27_24, A15), + PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), - PINMUX_IPSR_DATA(IP3_27_24, HRTS4_N), - PINMUX_IPSR_DATA(IP3_27_24, VI5_DATA11), - PINMUX_IPSR_DATA(IP3_27_24, DU_DG7), + PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), + PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), + PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), - PINMUX_IPSR_DATA(IP3_31_28, A16), - PINMUX_IPSR_DATA(IP3_31_28, LCDOUT8), - PINMUX_IPSR_DATA(IP3_31_28, VI4_FIELD), - PINMUX_IPSR_DATA(IP3_31_28, DU_DG0), + PINMUX_IPSR_GPSR(IP3_31_28, A16), + PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), + PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), + PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), /* IPSR4 */ - PINMUX_IPSR_DATA(IP4_3_0, A17), - PINMUX_IPSR_DATA(IP4_3_0, LCDOUT9), - PINMUX_IPSR_DATA(IP4_3_0, VI4_VSYNC_N), - PINMUX_IPSR_DATA(IP4_3_0, DU_DG1), - - PINMUX_IPSR_DATA(IP4_7_4, A18), - PINMUX_IPSR_DATA(IP4_7_4, LCDOUT10), - PINMUX_IPSR_DATA(IP4_7_4, VI4_HSYNC_N), - PINMUX_IPSR_DATA(IP4_7_4, DU_DG2), - - PINMUX_IPSR_DATA(IP4_11_8, A19), - PINMUX_IPSR_DATA(IP4_11_8, LCDOUT11), - PINMUX_IPSR_DATA(IP4_11_8, VI4_CLKENB), - PINMUX_IPSR_DATA(IP4_11_8, DU_DG3), - - PINMUX_IPSR_DATA(IP4_15_12, CS0_N), - PINMUX_IPSR_DATA(IP4_15_12, VI5_CLKENB), - - PINMUX_IPSR_DATA(IP4_19_16, CS1_N_A26), - PINMUX_IPSR_DATA(IP4_19_16, VI5_CLK), + PINMUX_IPSR_GPSR(IP4_3_0, A17), + PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), + PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), + PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), + + PINMUX_IPSR_GPSR(IP4_7_4, A18), + PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), + PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), + PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), + + PINMUX_IPSR_GPSR(IP4_11_8, A19), + PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), + PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), + PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), + + PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), + PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), + + PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26), + PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), - PINMUX_IPSR_DATA(IP4_23_20, BS_N), - PINMUX_IPSR_DATA(IP4_23_20, QSTVA_QVS), + PINMUX_IPSR_GPSR(IP4_23_20, BS_N), + PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), - PINMUX_IPSR_DATA(IP4_23_20, SCK3), - PINMUX_IPSR_DATA(IP4_23_20, HSCK3), - PINMUX_IPSR_DATA(IP4_23_20, CAN1_TX), - PINMUX_IPSR_DATA(IP4_23_20, CANFD1_TX), + PINMUX_IPSR_GPSR(IP4_23_20, SCK3), + PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), + PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), + PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), - PINMUX_IPSR_DATA(IP4_27_24, RD_N), + PINMUX_IPSR_GPSR(IP4_27_24, RD_N), PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), - PINMUX_IPSR_DATA(IP4_31_28, RD_WR_N), + PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), @@ -820,236 +819,236 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), /* IPSR5 */ - PINMUX_IPSR_DATA(IP5_3_0, WE0_N), + PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), - PINMUX_IPSR_DATA(IP5_3_0, CTS3_N), - PINMUX_IPSR_DATA(IP5_3_0, HCTS3_N), + PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), + PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), - PINMUX_IPSR_DATA(IP5_3_0, CAN_CLK), + PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), - PINMUX_IPSR_DATA(IP5_7_4, WE1_N), + PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), - PINMUX_IPSR_DATA(IP5_7_4, RTS3_N_TANS), - PINMUX_IPSR_DATA(IP5_7_4, HRTS3_N), + PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS), + PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), - PINMUX_IPSR_DATA(IP5_7_4, CAN1_RX), - PINMUX_IPSR_DATA(IP5_7_4, CANFD1_RX), + PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), + PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), - PINMUX_IPSR_DATA(IP5_11_8, QCLK), - PINMUX_IPSR_DATA(IP5_11_8, VI4_CLK), - PINMUX_IPSR_DATA(IP5_11_8, DU_DOTCLKOUT0), + PINMUX_IPSR_GPSR(IP5_11_8, QCLK), + PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), + PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), - PINMUX_IPSR_DATA(IP5_15_12, D0), + PINMUX_IPSR_GPSR(IP5_15_12, D0), PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), - PINMUX_IPSR_DATA(IP5_15_12, VI4_DATA16), - PINMUX_IPSR_DATA(IP5_15_12, VI5_DATA0), + PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), + PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), - PINMUX_IPSR_DATA(IP5_19_16, D1), + PINMUX_IPSR_GPSR(IP5_19_16, D1), PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), - PINMUX_IPSR_DATA(IP5_19_16, VI4_DATA17), - PINMUX_IPSR_DATA(IP5_19_16, VI5_DATA1), + PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), + PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), - PINMUX_IPSR_DATA(IP5_23_20, D2), + PINMUX_IPSR_GPSR(IP5_23_20, D2), PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), - PINMUX_IPSR_DATA(IP5_23_20, VI4_DATA18), - PINMUX_IPSR_DATA(IP5_23_20, VI5_DATA2), + PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), + PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), - PINMUX_IPSR_DATA(IP5_27_24, D3), + PINMUX_IPSR_GPSR(IP5_27_24, D3), PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), - PINMUX_IPSR_DATA(IP5_27_24, VI4_DATA19), - PINMUX_IPSR_DATA(IP5_27_24, VI5_DATA3), + PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), + PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), - PINMUX_IPSR_DATA(IP5_31_28, D4), + PINMUX_IPSR_GPSR(IP5_31_28, D4), PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), - PINMUX_IPSR_DATA(IP5_31_28, VI4_DATA20), - PINMUX_IPSR_DATA(IP5_31_28, VI5_DATA4), + PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), + PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), /* IPSR6 */ - PINMUX_IPSR_DATA(IP6_3_0, D5), + PINMUX_IPSR_GPSR(IP6_3_0, D5), PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), - PINMUX_IPSR_DATA(IP6_3_0, VI4_DATA21), - PINMUX_IPSR_DATA(IP6_3_0, VI5_DATA5), + PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), + PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), - PINMUX_IPSR_DATA(IP6_7_4, D6), + PINMUX_IPSR_GPSR(IP6_7_4, D6), PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), - PINMUX_IPSR_DATA(IP6_7_4, VI4_DATA22), - PINMUX_IPSR_DATA(IP6_7_4, VI5_DATA6), + PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), + PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), - PINMUX_IPSR_DATA(IP6_11_8, D7), + PINMUX_IPSR_GPSR(IP6_11_8, D7), PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), - PINMUX_IPSR_DATA(IP6_11_8, VI4_DATA23), - PINMUX_IPSR_DATA(IP6_11_8, VI5_DATA7), + PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), + PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), - PINMUX_IPSR_DATA(IP6_15_12, D8), - PINMUX_IPSR_DATA(IP6_15_12, LCDOUT0), + PINMUX_IPSR_GPSR(IP6_15_12, D8), + PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), - PINMUX_IPSR_DATA(IP6_15_12, DU_DR0), + PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), - PINMUX_IPSR_DATA(IP6_19_16, D9), - PINMUX_IPSR_DATA(IP6_19_16, LCDOUT1), + PINMUX_IPSR_GPSR(IP6_19_16, D9), + PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), - PINMUX_IPSR_DATA(IP6_19_16, DU_DR1), + PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), - PINMUX_IPSR_DATA(IP6_23_20, D10), - PINMUX_IPSR_DATA(IP6_23_20, LCDOUT2), + PINMUX_IPSR_GPSR(IP6_23_20, D10), + PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), - PINMUX_IPSR_DATA(IP6_23_20, DU_DR2), + PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), - PINMUX_IPSR_DATA(IP6_27_24, D11), - PINMUX_IPSR_DATA(IP6_27_24, LCDOUT3), + PINMUX_IPSR_GPSR(IP6_27_24, D11), + PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), - PINMUX_IPSR_DATA(IP6_27_24, DU_DR3), + PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), - PINMUX_IPSR_DATA(IP6_31_28, D12), - PINMUX_IPSR_DATA(IP6_31_28, LCDOUT4), + PINMUX_IPSR_GPSR(IP6_31_28, D12), + PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), - PINMUX_IPSR_DATA(IP6_31_28, DU_DR4), + PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), /* IPSR7 */ - PINMUX_IPSR_DATA(IP7_3_0, D13), - PINMUX_IPSR_DATA(IP7_3_0, LCDOUT5), + PINMUX_IPSR_GPSR(IP7_3_0, D13), + PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), - PINMUX_IPSR_DATA(IP7_3_0, DU_DR5), + PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), - PINMUX_IPSR_DATA(IP7_7_4, D14), - PINMUX_IPSR_DATA(IP7_7_4, LCDOUT6), + PINMUX_IPSR_GPSR(IP7_7_4, D14), + PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), - PINMUX_IPSR_DATA(IP7_7_4, DU_DR6), + PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), - PINMUX_IPSR_DATA(IP7_11_8, D15), - PINMUX_IPSR_DATA(IP7_11_8, LCDOUT7), + PINMUX_IPSR_GPSR(IP7_11_8, D15), + PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), - PINMUX_IPSR_DATA(IP7_11_8, DU_DR7), + PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), - PINMUX_IPSR_DATA(IP7_15_12, FSCLKST), + PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST), - PINMUX_IPSR_DATA(IP7_19_16, SD0_CLK), + PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), - PINMUX_IPSR_DATA(IP7_23_20, SD0_CMD), + PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), - PINMUX_IPSR_DATA(IP7_27_24, SD0_DAT0), + PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), - PINMUX_IPSR_DATA(IP7_31_28, SD0_DAT1), + PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), /* IPSR8 */ - PINMUX_IPSR_DATA(IP8_3_0, SD0_DAT2), + PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), - PINMUX_IPSR_DATA(IP8_7_4, SD0_DAT3), + PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), - PINMUX_IPSR_DATA(IP8_11_8, SD1_CLK), + PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), - PINMUX_IPSR_DATA(IP8_15_12, SD1_CMD), + PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), - PINMUX_IPSR_DATA(IP8_19_16, SD1_DAT0), - PINMUX_IPSR_DATA(IP8_19_16, SD2_DAT4), + PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), + PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), - PINMUX_IPSR_DATA(IP8_23_20, SD1_DAT1), - PINMUX_IPSR_DATA(IP8_23_20, SD2_DAT5), + PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), + PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), - PINMUX_IPSR_DATA(IP8_27_24, SD1_DAT2), - PINMUX_IPSR_DATA(IP8_27_24, SD2_DAT6), + PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), + PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), - PINMUX_IPSR_DATA(IP8_31_28, SD1_DAT3), - PINMUX_IPSR_DATA(IP8_31_28, SD2_DAT7), + PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), + PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), /* IPSR9 */ - PINMUX_IPSR_DATA(IP9_3_0, SD2_CLK), + PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), - PINMUX_IPSR_DATA(IP9_7_4, SD2_DAT0), + PINMUX_IPSR_GPSR(IP9_7_4, SD2_DAT0), - PINMUX_IPSR_DATA(IP9_11_8, SD2_DAT1), + PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT1), - PINMUX_IPSR_DATA(IP9_15_12, SD2_DAT2), + PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT2), - PINMUX_IPSR_DATA(IP9_19_16, SD2_DAT3), + PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT3), - PINMUX_IPSR_DATA(IP9_23_20, SD2_DS), + PINMUX_IPSR_GPSR(IP9_23_20, SD2_DS), PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1), - PINMUX_IPSR_DATA(IP9_27_24, SD3_DAT4), + PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT4), PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0), - PINMUX_IPSR_DATA(IP9_31_28, SD3_DAT5), + PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT5), PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0), /* IPSR10 */ - PINMUX_IPSR_DATA(IP10_3_0, SD3_DAT6), - PINMUX_IPSR_DATA(IP10_3_0, SD3_CD), + PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT6), + PINMUX_IPSR_GPSR(IP10_3_0, SD3_CD), - PINMUX_IPSR_DATA(IP10_7_4, SD3_DAT7), - PINMUX_IPSR_DATA(IP10_7_4, SD3_WP), + PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT7), + PINMUX_IPSR_GPSR(IP10_7_4, SD3_WP), - PINMUX_IPSR_DATA(IP10_11_8, SD0_CD), + PINMUX_IPSR_GPSR(IP10_11_8, SD0_CD), PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0), - PINMUX_IPSR_DATA(IP10_15_12, SD0_WP), + PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP), PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1), - PINMUX_IPSR_DATA(IP10_19_16, SD1_CD), + PINMUX_IPSR_GPSR(IP10_19_16, SD1_CD), PINMUX_IPSR_MSEL(IP10_19_16, SIM0_CLK_B, SEL_SIMCARD_1), - PINMUX_IPSR_DATA(IP10_23_20, SD1_WP), + PINMUX_IPSR_GPSR(IP10_23_20, SD1_WP), PINMUX_IPSR_MSEL(IP10_23_20, SIM0_D_B, SEL_SIMCARD_1), - PINMUX_IPSR_DATA(IP10_27_24, SCK0), + PINMUX_IPSR_GPSR(IP10_27_24, SCK0), PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1), @@ -1057,38 +1056,38 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1), PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1), - PINMUX_IPSR_DATA(IP10_27_24, ADICHS2), + PINMUX_IPSR_GPSR(IP10_27_24, ADICHS2), - PINMUX_IPSR_DATA(IP10_31_28, RX0), + PINMUX_IPSR_GPSR(IP10_31_28, RX0), PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2), PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1), /* IPSR11 */ - PINMUX_IPSR_DATA(IP11_3_0, TX0), + PINMUX_IPSR_GPSR(IP11_3_0, TX0), PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1), - PINMUX_IPSR_DATA(IP11_7_4, CTS0_N), + PINMUX_IPSR_GPSR(IP11_7_4, CTS0_N), PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1), PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2), - PINMUX_IPSR_DATA(IP11_7_4, ADICS_SAMP), + PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP), - PINMUX_IPSR_DATA(IP11_11_8, RTS0_N_TANS), + PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N_TANS), PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1), PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1), - PINMUX_IPSR_DATA(IP11_11_8, ADICHS1), + PINMUX_IPSR_GPSR(IP11_11_8, ADICHS1), PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0), PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0), @@ -1102,29 +1101,29 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2), - PINMUX_IPSR_DATA(IP11_23_20, CTS1_N), + PINMUX_IPSR_GPSR(IP11_23_20, CTS1_N), PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0), PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2), PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1), - PINMUX_IPSR_DATA(IP11_23_20, ADIDATA), + PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA), - PINMUX_IPSR_DATA(IP11_27_24, RTS1_N_TANS), + PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS), PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0), PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2), PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2), PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1), - PINMUX_IPSR_DATA(IP11_27_24, ADICHS0), + PINMUX_IPSR_GPSR(IP11_27_24, ADICHS0), - PINMUX_IPSR_DATA(IP11_31_28, SCK2), + PINMUX_IPSR_GPSR(IP11_31_28, SCK2), PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1), PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2), PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1), - PINMUX_IPSR_DATA(IP11_31_28, ADICLK), + PINMUX_IPSR_GPSR(IP11_31_28, ADICLK), /* IPSR12 */ PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0), @@ -1141,7 +1140,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2), PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1), - PINMUX_IPSR_DATA(IP12_11_8, HSCK0), + PINMUX_IPSR_GPSR(IP12_11_8, HSCK0), PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0), PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1), @@ -1149,21 +1148,21 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2), - PINMUX_IPSR_DATA(IP12_15_12, HRX0), + PINMUX_IPSR_GPSR(IP12_15_12, HRX0), PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1), PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2), - PINMUX_IPSR_DATA(IP12_19_16, HTX0), + PINMUX_IPSR_GPSR(IP12_19_16, HTX0), PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1), PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3), PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2), - PINMUX_IPSR_DATA(IP12_23_20, HCTS0_N), + PINMUX_IPSR_GPSR(IP12_23_20, HCTS0_N), PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1), PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0), @@ -1172,7 +1171,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2), PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0), - PINMUX_IPSR_DATA(IP12_27_24, HRTS0_N), + PINMUX_IPSR_GPSR(IP12_27_24, HRTS0_N), PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1), PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0), @@ -1180,20 +1179,20 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0), PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0), - PINMUX_IPSR_DATA(IP12_31_28, MSIOF0_SYNC), + PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC), PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0), /* IPSR13 */ - PINMUX_IPSR_DATA(IP13_3_0, MSIOF0_SS1), - PINMUX_IPSR_DATA(IP13_3_0, RX5), + PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1), + PINMUX_IPSR_GPSR(IP13_3_0, RX5), PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2), PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0), PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0), PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1), - PINMUX_IPSR_DATA(IP13_7_4, MSIOF0_SS2), - PINMUX_IPSR_DATA(IP13_7_4, TX5), + PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2), + PINMUX_IPSR_GPSR(IP13_7_4, TX5), PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0), PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0), @@ -1201,26 +1200,26 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3), PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), - PINMUX_IPSR_DATA(IP13_11_8, MLB_CLK), + PINMUX_IPSR_GPSR(IP13_11_8, MLB_CLK), PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1), - PINMUX_IPSR_DATA(IP13_15_12, MLB_SIG), + PINMUX_IPSR_GPSR(IP13_15_12, MLB_SIG), PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1), PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1), - PINMUX_IPSR_DATA(IP13_19_16, MLB_DAT), + PINMUX_IPSR_GPSR(IP13_19_16, MLB_DAT), PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1), PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), - PINMUX_IPSR_DATA(IP13_23_20, SSI_SCK0129), + PINMUX_IPSR_GPSR(IP13_23_20, SSI_SCK01239), PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), - PINMUX_IPSR_DATA(IP13_27_24, SSI_WS0129), + PINMUX_IPSR_GPSR(IP13_27_24, SSI_WS01239), PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), - PINMUX_IPSR_DATA(IP13_31_28, SSI_SDATA0), + PINMUX_IPSR_GPSR(IP13_31_28, SSI_SDATA0), PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), /* IPSR14 */ @@ -1229,16 +1228,16 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0), PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1), - PINMUX_IPSR_DATA(IP14_11_8, SSI_SCK34), + PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK34), PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), - PINMUX_IPSR_DATA(IP14_15_12, SSI_WS34), + PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS34), PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0), PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), - PINMUX_IPSR_DATA(IP14_19_16, SSI_SDATA3), + PINMUX_IPSR_GPSR(IP14_19_16, SSI_SDATA3), PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0), PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0), @@ -1246,7 +1245,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0), PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0), - PINMUX_IPSR_DATA(IP14_23_20, SSI_SCK4), + PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK4), PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0), PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0), @@ -1254,7 +1253,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0), PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0), - PINMUX_IPSR_DATA(IP14_27_24, SSI_WS4), + PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS4), PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0), PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0), @@ -1262,7 +1261,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0), PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0), - PINMUX_IPSR_DATA(IP14_31_28, SSI_SDATA4), + PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA4), PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0), PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), @@ -1271,19 +1270,19 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0), /* IPSR15 */ - PINMUX_IPSR_DATA(IP15_3_0, SSI_SCK6), - PINMUX_IPSR_DATA(IP15_3_0, USB2_PWEN), + PINMUX_IPSR_GPSR(IP15_3_0, SSI_SCK6), + PINMUX_IPSR_GPSR(IP15_3_0, USB2_PWEN), PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3), - PINMUX_IPSR_DATA(IP15_7_4, SSI_WS6), - PINMUX_IPSR_DATA(IP15_7_4, USB2_OVC), + PINMUX_IPSR_GPSR(IP15_7_4, SSI_WS6), + PINMUX_IPSR_GPSR(IP15_7_4, USB2_OVC), PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3), - PINMUX_IPSR_DATA(IP15_11_8, SSI_SDATA6), + PINMUX_IPSR_GPSR(IP15_11_8, SSI_SDATA6), PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3), PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0), - PINMUX_IPSR_DATA(IP15_15_12, SSI_SCK78), + PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK78), PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1), PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0), @@ -1291,7 +1290,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0), PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0), - PINMUX_IPSR_DATA(IP15_19_16, SSI_WS78), + PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS78), PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1), PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0), @@ -1299,7 +1298,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0), PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0), - PINMUX_IPSR_DATA(IP15_23_20, SSI_SDATA7), + PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA7), PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1), PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0), @@ -1308,7 +1307,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0), PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0), - PINMUX_IPSR_DATA(IP15_27_24, SSI_SDATA8), + PINMUX_IPSR_GPSR(IP15_27_24, SSI_SDATA8), PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1), PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), @@ -1321,13 +1320,13 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0), PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1), - PINMUX_IPSR_DATA(IP15_31_28, SCK1), + PINMUX_IPSR_GPSR(IP15_31_28, SCK1), PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), - PINMUX_IPSR_DATA(IP15_31_28, SCK5), + PINMUX_IPSR_GPSR(IP15_31_28, SCK5), /* IPSR16 */ PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0), - PINMUX_IPSR_DATA(IP16_3_0, CC5_OSCOUT), + PINMUX_IPSR_GPSR(IP16_3_0, CC5_OSCOUT), PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1), PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0), @@ -1335,20 +1334,20 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0), PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0), - PINMUX_IPSR_DATA(IP16_11_8, USB0_PWEN), + PINMUX_IPSR_GPSR(IP16_11_8, USB0_PWEN), PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2), PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3), PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1), PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1), - PINMUX_IPSR_DATA(IP16_15_12, USB0_OVC), + PINMUX_IPSR_GPSR(IP16_15_12, USB0_OVC), PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2), PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3), PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1), - PINMUX_IPSR_DATA(IP16_19_16, USB1_PWEN), + PINMUX_IPSR_GPSR(IP16_19_16, USB1_PWEN), PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2), PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0), PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4), @@ -1357,7 +1356,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1), PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), - PINMUX_IPSR_DATA(IP16_23_20, USB1_OVC), + PINMUX_IPSR_GPSR(IP16_23_20, USB1_OVC), PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0), PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4), @@ -1366,7 +1365,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1), PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1), - PINMUX_IPSR_DATA(IP16_27_24, USB30_PWEN), + PINMUX_IPSR_GPSR(IP16_27_24, USB30_PWEN), PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1), PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1), PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3), @@ -1374,9 +1373,9 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1), PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1), - PINMUX_IPSR_DATA(IP16_27_24, TPU0TO0), + PINMUX_IPSR_GPSR(IP16_27_24, TPU0TO0), - PINMUX_IPSR_DATA(IP16_31_28, USB30_OVC), + PINMUX_IPSR_GPSR(IP16_31_28, USB30_OVC), PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1), PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1), PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), @@ -1384,24 +1383,24 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1), PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1), - PINMUX_IPSR_DATA(IP16_31_28, TPU0TO1), + PINMUX_IPSR_GPSR(IP16_31_28, TPU0TO1), /* IPSR17 */ - PINMUX_IPSR_DATA(IP17_3_0, USB31_PWEN), + PINMUX_IPSR_GPSR(IP17_3_0, USB31_PWEN), PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1), PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1), PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4), PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1), - PINMUX_IPSR_DATA(IP17_3_0, TPU0TO2), + PINMUX_IPSR_GPSR(IP17_3_0, TPU0TO2), - PINMUX_IPSR_DATA(IP17_7_4, USB31_OVC), + PINMUX_IPSR_GPSR(IP17_7_4, USB31_OVC), PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1), PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1), PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1), - PINMUX_IPSR_DATA(IP17_7_4, TPU0TO3), + PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3), /* I2C */ PINMUX_IPSR_NOGP(0, I2C_SEL_0_1), @@ -1600,6 +1599,61 @@ static const unsigned int avb_avtp_capture_b_mux[] = { AVB_AVTP_CAPTURE_B_MARK, }; +/* - CAN ------------------------------------------------------------------ */ +static const unsigned int can0_data_a_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +}; +static const unsigned int can0_data_a_mux[] = { + CAN0_TX_A_MARK, CAN0_RX_A_MARK, +}; +static const unsigned int can0_data_b_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +}; +static const unsigned int can0_data_b_mux[] = { + CAN0_TX_B_MARK, CAN0_RX_B_MARK, +}; +static const unsigned int can1_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), +}; +static const unsigned int can1_data_mux[] = { + CAN1_TX_MARK, CAN1_RX_MARK, +}; + +/* - CAN Clock -------------------------------------------------------------- */ +static const unsigned int can_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int can_clk_mux[] = { + CAN_CLK_MARK, +}; + +/* - CAN FD --------------------------------------------------------------- */ +static const unsigned int canfd0_data_a_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +}; +static const unsigned int canfd0_data_a_mux[] = { + CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, +}; +static const unsigned int canfd0_data_b_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +}; +static const unsigned int canfd0_data_b_mux[] = { + CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, +}; +static const unsigned int canfd1_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), +}; +static const unsigned int canfd1_data_mux[] = { + CANFD1_TX_MARK, CANFD1_RX_MARK, +}; + /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { /* RX, TX */ @@ -1836,6 +1890,50 @@ static const unsigned int i2c6_c_mux[] = { SDA6_C_MARK, SCL6_C_MARK, }; +/* - INTC-EX ---------------------------------------------------------------- */ +static const unsigned int intc_ex_irq0_pins[] = { + /* IRQ0 */ + RCAR_GP_PIN(2, 0), +}; +static const unsigned int intc_ex_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_ex_irq1_pins[] = { + /* IRQ1 */ + RCAR_GP_PIN(2, 1), +}; +static const unsigned int intc_ex_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_ex_irq2_pins[] = { + /* IRQ2 */ + RCAR_GP_PIN(2, 2), +}; +static const unsigned int intc_ex_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_ex_irq3_pins[] = { + /* IRQ3 */ + RCAR_GP_PIN(2, 3), +}; +static const unsigned int intc_ex_irq3_mux[] = { + IRQ3_MARK, +}; +static const unsigned int intc_ex_irq4_pins[] = { + /* IRQ4 */ + RCAR_GP_PIN(2, 4), +}; +static const unsigned int intc_ex_irq4_mux[] = { + IRQ4_MARK, +}; +static const unsigned int intc_ex_irq5_pins[] = { + /* IRQ5 */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int intc_ex_irq5_mux[] = { + IRQ5_MARK, +}; + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -2492,6 +2590,105 @@ static const unsigned int msiof3_rxd_d_mux[] = { MSIOF3_RXD_D_MARK, }; +/* - PWM0 --------------------------------------------------------------------*/ +static const unsigned int pwm0_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 6), +}; +static const unsigned int pwm0_mux[] = { + PWM0_MARK, +}; +/* - PWM1 --------------------------------------------------------------------*/ +static const unsigned int pwm1_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 7), +}; +static const unsigned int pwm1_a_mux[] = { + PWM1_A_MARK, +}; +static const unsigned int pwm1_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 8), +}; +static const unsigned int pwm1_b_mux[] = { + PWM1_B_MARK, +}; +/* - PWM2 --------------------------------------------------------------------*/ +static const unsigned int pwm2_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 8), +}; +static const unsigned int pwm2_a_mux[] = { + PWM2_A_MARK, +}; +static const unsigned int pwm2_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 11), +}; +static const unsigned int pwm2_b_mux[] = { + PWM2_B_MARK, +}; +/* - PWM3 --------------------------------------------------------------------*/ +static const unsigned int pwm3_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 0), +}; +static const unsigned int pwm3_a_mux[] = { + PWM3_A_MARK, +}; +static const unsigned int pwm3_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 2), +}; +static const unsigned int pwm3_b_mux[] = { + PWM3_B_MARK, +}; +/* - PWM4 --------------------------------------------------------------------*/ +static const unsigned int pwm4_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 1), +}; +static const unsigned int pwm4_a_mux[] = { + PWM4_A_MARK, +}; +static const unsigned int pwm4_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 3), +}; +static const unsigned int pwm4_b_mux[] = { + PWM4_B_MARK, +}; +/* - PWM5 --------------------------------------------------------------------*/ +static const unsigned int pwm5_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 2), +}; +static const unsigned int pwm5_a_mux[] = { + PWM5_A_MARK, +}; +static const unsigned int pwm5_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 4), +}; +static const unsigned int pwm5_b_mux[] = { + PWM5_B_MARK, +}; +/* - PWM6 --------------------------------------------------------------------*/ +static const unsigned int pwm6_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 3), +}; +static const unsigned int pwm6_a_mux[] = { + PWM6_A_MARK, +}; +static const unsigned int pwm6_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int pwm6_b_mux[] = { + PWM6_B_MARK, +}; + /* - SATA --------------------------------------------------------------------*/ static const unsigned int sata0_devslp_a_pins[] = { /* DEVSLP */ @@ -2926,7 +3123,7 @@ static const unsigned int ssi01239_ctrl_pins[] = { RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), }; static const unsigned int ssi01239_ctrl_mux[] = { - SSI_SCK0129_MARK, SSI_WS0129_MARK, + SSI_SCK01239_MARK, SSI_WS01239_MARK, }; static const unsigned int ssi1_data_a_pins[] = { /* SDATA */ @@ -3090,6 +3287,31 @@ static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; +/* - USB0 ------------------------------------------------------------------- */ +static const unsigned int usb0_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), +}; +static const unsigned int usb0_mux[] = { + USB0_PWEN_MARK, USB0_OVC_MARK, +}; +/* - USB1 ------------------------------------------------------------------- */ +static const unsigned int usb1_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), +}; +static const unsigned int usb1_mux[] = { + USB1_PWEN_MARK, USB1_OVC_MARK, +}; +/* - USB2 ------------------------------------------------------------------- */ +static const unsigned int usb2_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), +}; +static const unsigned int usb2_mux[] = { + USB2_PWEN_MARK, USB2_OVC_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(audio_clk_a_a), SH_PFC_PIN_GROUP(audio_clk_a_b), @@ -3117,6 +3339,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_avtp_capture_a), SH_PFC_PIN_GROUP(avb_avtp_match_b), SH_PFC_PIN_GROUP(avb_avtp_capture_b), + SH_PFC_PIN_GROUP(can0_data_a), + SH_PFC_PIN_GROUP(can0_data_b), + SH_PFC_PIN_GROUP(can1_data), + SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(canfd0_data_a), + SH_PFC_PIN_GROUP(canfd0_data_b), + SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), @@ -3149,6 +3378,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), + SH_PFC_PIN_GROUP(intc_ex_irq0), + SH_PFC_PIN_GROUP(intc_ex_irq1), + SH_PFC_PIN_GROUP(intc_ex_irq2), + SH_PFC_PIN_GROUP(intc_ex_irq3), + SH_PFC_PIN_GROUP(intc_ex_irq4), + SH_PFC_PIN_GROUP(intc_ex_irq5), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -3242,6 +3477,19 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof3_ss1_d), SH_PFC_PIN_GROUP(msiof3_txd_d), SH_PFC_PIN_GROUP(msiof3_rxd_d), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm1_a), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2_a), + SH_PFC_PIN_GROUP(pwm2_b), + SH_PFC_PIN_GROUP(pwm3_a), + SH_PFC_PIN_GROUP(pwm3_b), + SH_PFC_PIN_GROUP(pwm4_a), + SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(pwm5_a), + SH_PFC_PIN_GROUP(pwm5_b), + SH_PFC_PIN_GROUP(pwm6_a), + SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data), @@ -3322,6 +3570,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(ssi9_data_b), SH_PFC_PIN_GROUP(ssi9_ctrl_a), SH_PFC_PIN_GROUP(ssi9_ctrl_b), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb2), }; static const char * const audio_clk_groups[] = { @@ -3356,6 +3607,28 @@ static const char * const avb_groups[] = { "avb_avtp_capture_b", }; +static const char * const can0_groups[] = { + "can0_data_a", + "can0_data_b", +}; + +static const char * const can1_groups[] = { + "can1_data", +}; + +static const char * const can_clk_groups[] = { + "can_clk", +}; + +static const char * const canfd0_groups[] = { + "canfd0_data_a", + "canfd0_data_b", +}; + +static const char * const canfd1_groups[] = { + "canfd1_data", +}; + static const char * const hscif0_groups[] = { "hscif0_data", "hscif0_clk", @@ -3412,6 +3685,15 @@ static const char * const i2c6_groups[] = { "i2c6_c", }; +static const char * const intc_ex_groups[] = { + "intc_ex_irq0", + "intc_ex_irq1", + "intc_ex_irq2", + "intc_ex_irq3", + "intc_ex_irq4", + "intc_ex_irq5", +}; + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -3517,6 +3799,40 @@ static const char * const msiof3_groups[] = { "msiof3_rxd_d", }; +static const char * const pwm0_groups[] = { + "pwm0", +}; + +static const char * const pwm1_groups[] = { + "pwm1_a", + "pwm1_b", +}; + +static const char * const pwm2_groups[] = { + "pwm2_a", + "pwm2_b", +}; + +static const char * const pwm3_groups[] = { + "pwm3_a", + "pwm3_b", +}; + +static const char * const pwm4_groups[] = { + "pwm4_a", + "pwm4_b", +}; + +static const char * const pwm5_groups[] = { + "pwm5_a", + "pwm5_b", +}; + +static const char * const pwm6_groups[] = { + "pwm6_a", + "pwm6_b", +}; + static const char * const sata0_groups[] = { "sata0_devslp_a", "sata0_devslp_b", @@ -3636,9 +3952,26 @@ static const char * const ssi_groups[] = { "ssi9_ctrl_b", }; +static const char * const usb0_groups[] = { + "usb0", +}; + +static const char * const usb1_groups[] = { + "usb1", +}; + +static const char * const usb2_groups[] = { + "usb2", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), @@ -3647,10 +3980,18 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c6), + SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), SH_PFC_FUNCTION(sata0), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), @@ -3664,6 +4005,9 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(usb2), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -4213,7 +4557,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 3 */ 0, 0, - MOD_SEL2_2_1 + /* RESERVED 2, 1 */ + 0, 0, 0, 0, MOD_SEL2_0 } }, { }, |