diff options
Diffstat (limited to 'drivers/pinctrl')
31 files changed, 1957 insertions, 414 deletions
diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c index 6f7d3a2f2e97..f50833e6650a 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -858,7 +858,7 @@ static int iproc_gpio_probe(struct platform_device *pdev) struct gpio_irq_chip *girq; irqc = &chip->irqchip; - irqc->name = "bcm-iproc-gpio"; + irqc->name = dev_name(dev); irqc->irq_ack = iproc_gpio_irq_ack; irqc->irq_mask = iproc_gpio_irq_mask; irqc->irq_unmask = iproc_gpio_irq_unmask; diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c index 5d6d8b1e9062..1a300374a16d 100644 --- a/drivers/pinctrl/devicetree.c +++ b/drivers/pinctrl/devicetree.c @@ -29,6 +29,13 @@ struct pinctrl_dt_map { static void dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map, unsigned num_maps) { + int i; + + for (i = 0; i < num_maps; ++i) { + kfree_const(map[i].dev_name); + map[i].dev_name = NULL; + } + if (pctldev) { const struct pinctrl_ops *ops = pctldev->desc->pctlops; if (ops->dt_free_map) @@ -63,7 +70,13 @@ static int dt_remember_or_free_map(struct pinctrl *p, const char *statename, /* Initialize common mapping table entry fields */ for (i = 0; i < num_maps; i++) { - map[i].dev_name = dev_name(p->dev); + const char *devname; + + devname = kstrdup_const(dev_name(p->dev), GFP_KERNEL); + if (!devname) + goto err_free_map; + + map[i].dev_name = devname; map[i].name = statename; if (pctldev) map[i].ctrl_dev_name = dev_name(pctldev->dev); @@ -71,10 +84,8 @@ static int dt_remember_or_free_map(struct pinctrl *p, const char *statename, /* Remember the converted mapping table entries */ dt_map = kzalloc(sizeof(*dt_map), GFP_KERNEL); - if (!dt_map) { - dt_free_map(pctldev, map, num_maps); - return -ENOMEM; - } + if (!dt_map) + goto err_free_map; dt_map->pctldev = pctldev; dt_map->map = map; @@ -82,6 +93,10 @@ static int dt_remember_or_free_map(struct pinctrl *p, const char *statename, list_add_tail(&dt_map->node, &p->dt_maps); return pinctrl_register_map(map, num_maps, false); + +err_free_map: + dt_free_map(pctldev, map, num_maps); + return -ENOMEM; } struct pinctrl_dev *of_pinctrl_get(struct device_node *np) @@ -166,21 +181,6 @@ static int dt_remember_dummy_state(struct pinctrl *p, const char *statename) return dt_remember_or_free_map(p, statename, NULL, map, 1); } -bool pinctrl_dt_has_hogs(struct pinctrl_dev *pctldev) -{ - struct device_node *np; - struct property *prop; - int size; - - np = pctldev->dev->of_node; - if (!np) - return false; - - prop = of_find_property(np, "pinctrl-0", &size); - - return prop ? true : false; -} - int pinctrl_dt_to_map(struct pinctrl *p, struct pinctrl_dev *pctldev) { struct device_node *np = p->dev->of_node; diff --git a/drivers/pinctrl/devicetree.h b/drivers/pinctrl/devicetree.h index 00e645d7fac7..efa80779de4f 100644 --- a/drivers/pinctrl/devicetree.h +++ b/drivers/pinctrl/devicetree.h @@ -9,8 +9,6 @@ struct of_phandle_args; #ifdef CONFIG_OF -bool pinctrl_dt_has_hogs(struct pinctrl_dev *pctldev); - void pinctrl_dt_free_maps(struct pinctrl *p); int pinctrl_dt_to_map(struct pinctrl *p, struct pinctrl_dev *pctldev); @@ -23,11 +21,6 @@ int pinctrl_parse_index_with_args(const struct device_node *np, #else -static inline bool pinctrl_dt_has_hogs(struct pinctrl_dev *pctldev) -{ - return false; -} - static inline int pinctrl_dt_to_map(struct pinctrl *p, struct pinctrl_dev *pctldev) { diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 53f52b9a0acd..67f8444f7a0c 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -982,7 +982,6 @@ static const struct mtk_eint_xt mtk_eint_xt = { static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; - struct resource *res; if (!of_property_read_bool(np, "interrupt-controller")) return -ENODEV; @@ -991,8 +990,7 @@ static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev) if (!pctl->eint) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pctl->eint->base = devm_ioremap_resource(&pdev->dev, res); + pctl->eint->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pctl->eint->base)) return PTR_ERR(pctl->eint->base); diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 6462d3ca7ceb..952cf4e87e82 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -722,6 +722,8 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, struct device_node *np = info->dev->of_node; struct gpio_chip *gc = &info->gpio_chip; struct irq_chip *irqchip = &info->irq_chip; + struct gpio_irq_chip *girq = &gc->irq; + struct device *dev = &pdev->dev; struct resource res; int ret = -ENODEV, i, nr_irq_parent; @@ -732,19 +734,21 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, break; } }; - if (ret) + if (ret) { + dev_err(dev, "no gpio-controller child node\n"); return ret; + } nr_irq_parent = of_irq_count(np); spin_lock_init(&info->irq_lock); if (!nr_irq_parent) { - dev_err(&pdev->dev, "Invalid or no IRQ\n"); + dev_err(dev, "invalid or no IRQ\n"); return 0; } if (of_address_to_resource(info->dev->of_node, 1, &res)) { - dev_err(info->dev, "cannot find IO resource\n"); + dev_err(dev, "cannot find IO resource\n"); return -ENOENT; } @@ -759,27 +763,27 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, irqchip->irq_set_type = armada_37xx_irq_set_type; irqchip->irq_startup = armada_37xx_irq_startup; irqchip->name = info->data->name; - ret = gpiochip_irqchip_add(gc, irqchip, 0, - handle_edge_irq, IRQ_TYPE_NONE); - if (ret) { - dev_info(&pdev->dev, "could not add irqchip\n"); - return ret; - } - + girq->chip = irqchip; + girq->parent_handler = armada_37xx_irq_handler; /* * Many interrupts are connected to the parent interrupt * controller. But we do not take advantage of this and use * the chained irq with all of them. */ + girq->num_parents = nr_irq_parent; + girq->parents = devm_kcalloc(&pdev->dev, nr_irq_parent, + sizeof(*girq->parents), GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; for (i = 0; i < nr_irq_parent; i++) { int irq = irq_of_parse_and_map(np, i); if (irq < 0) continue; - - gpiochip_set_chained_irqchip(gc, irqchip, irq, - armada_37xx_irq_handler); + girq->parents[i] = irq; } + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_edge_irq; return 0; } @@ -809,10 +813,10 @@ static int armada_37xx_gpiochip_register(struct platform_device *pdev, gc->of_node = np; gc->label = info->data->name; - ret = devm_gpiochip_add_data(&pdev->dev, gc, info); + ret = armada_37xx_irqchip_register(pdev, info); if (ret) return ret; - ret = armada_37xx_irqchip_register(pdev, info); + ret = devm_gpiochip_add_data(&pdev->dev, gc, info); if (ret) return ret; diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index 00cfaf2c9d4a..a1f93859e7ca 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -759,12 +759,10 @@ int mvebu_pinctrl_simple_mmio_probe(struct platform_device *pdev) { struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev); struct mvebu_mpp_ctrl_data *mpp_data; - struct resource *res; void __iomem *base; int i; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, res); + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); diff --git a/drivers/pinctrl/mvebu/pinctrl-orion.c b/drivers/pinctrl/mvebu/pinctrl-orion.c index 29bb9d8cbbb5..cc97d270be61 100644 --- a/drivers/pinctrl/mvebu/pinctrl-orion.c +++ b/drivers/pinctrl/mvebu/pinctrl-orion.c @@ -220,17 +220,14 @@ static int orion_pinctrl_probe(struct platform_device *pdev) { const struct of_device_id *match = of_match_device(orion_pinctrl_of_match, &pdev->dev); - struct resource *res; pdev->dev.platform_data = (void*)match->data; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - mpp_base = devm_ioremap_resource(&pdev->dev, res); + mpp_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(mpp_base)) return PTR_ERR(mpp_base); - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - high_mpp_base = devm_ioremap_resource(&pdev->dev, res); + high_mpp_base = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(high_mpp_base)) return PTR_ERR(high_mpp_base); diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index 2a8190b11d10..95f864dfdef4 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -248,9 +248,6 @@ struct nmk_gpio_chip { void __iomem *addr; struct clk *clk; unsigned int bank; - unsigned int parent_irq; - int latent_parent_irq; - u32 (*get_latent_status)(unsigned int bank); void (*set_ioforce)(bool enable); spinlock_t lock; bool sleepmode; @@ -802,13 +799,19 @@ static void nmk_gpio_irq_shutdown(struct irq_data *d) clk_disable(nmk_chip->clk); } -static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status) +static void nmk_gpio_irq_handler(struct irq_desc *desc) { struct irq_chip *host_chip = irq_desc_get_chip(desc); struct gpio_chip *chip = irq_desc_get_handler_data(desc); + struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); + u32 status; chained_irq_enter(host_chip, desc); + clk_enable(nmk_chip->clk); + status = readl(nmk_chip->addr + NMK_GPIO_IS); + clk_disable(nmk_chip->clk); + while (status) { int bit = __ffs(status); @@ -819,28 +822,6 @@ static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status) chained_irq_exit(host_chip, desc); } -static void nmk_gpio_irq_handler(struct irq_desc *desc) -{ - struct gpio_chip *chip = irq_desc_get_handler_data(desc); - struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); - u32 status; - - clk_enable(nmk_chip->clk); - status = readl(nmk_chip->addr + NMK_GPIO_IS); - clk_disable(nmk_chip->clk); - - __nmk_gpio_irq_handler(desc, status); -} - -static void nmk_gpio_latent_irq_handler(struct irq_desc *desc) -{ - struct gpio_chip *chip = irq_desc_get_handler_data(desc); - struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); - u32 status = nmk_chip->get_latent_status(nmk_chip->bank); - - __nmk_gpio_irq_handler(desc, status); -} - /* I/O Functions */ static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset) @@ -1103,8 +1084,8 @@ static int nmk_gpio_probe(struct platform_device *dev) struct device_node *np = dev->dev.of_node; struct nmk_gpio_chip *nmk_chip; struct gpio_chip *chip; + struct gpio_irq_chip *girq; struct irq_chip *irqchip; - int latent_irq; bool supports_sleepmode; int irq; int ret; @@ -1125,15 +1106,10 @@ static int nmk_gpio_probe(struct platform_device *dev) if (irq < 0) return irq; - /* It's OK for this IRQ not to be present */ - latent_irq = platform_get_irq(dev, 1); - /* * The virt address in nmk_chip->addr is in the nomadik register space, * so we can simply convert the resource address, without remapping */ - nmk_chip->parent_irq = irq; - nmk_chip->latent_parent_irq = latent_irq; nmk_chip->sleepmode = supports_sleepmode; spin_lock_init(&nmk_chip->lock); @@ -1163,6 +1139,19 @@ static int nmk_gpio_probe(struct platform_device *dev) chip->base, chip->base + chip->ngpio - 1); + girq = &chip->irq; + girq->chip = irqchip; + girq->parent_handler = nmk_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&dev->dev, 1, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_edge_irq; + clk_enable(nmk_chip->clk); nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); clk_disable(nmk_chip->clk); @@ -1174,33 +1163,7 @@ static int nmk_gpio_probe(struct platform_device *dev) platform_set_drvdata(dev, nmk_chip); - /* - * Let the generic code handle this edge IRQ, the the chained - * handler will perform the actual work of handling the parent - * interrupt. - */ - ret = gpiochip_irqchip_add(chip, - irqchip, - 0, - handle_edge_irq, - IRQ_TYPE_NONE); - if (ret) { - dev_err(&dev->dev, "could not add irqchip\n"); - gpiochip_remove(&nmk_chip->chip); - return -ENODEV; - } - /* Then register the chain on the parent IRQ */ - gpiochip_set_chained_irqchip(chip, - irqchip, - nmk_chip->parent_irq, - nmk_gpio_irq_handler); - if (nmk_chip->latent_parent_irq > 0) - gpiochip_set_chained_irqchip(chip, - irqchip, - nmk_chip->latent_parent_irq, - nmk_gpio_latent_irq_handler); - - dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); + dev_info(&dev->dev, "chip registered\n"); return 0; } diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c index 17f909d8b63a..22077cbe6880 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -1954,6 +1954,22 @@ static int npcm7xx_gpio_register(struct npcm7xx_pinctrl *pctrl) int ret, id; for (id = 0 ; id < pctrl->bank_num ; id++) { + struct gpio_irq_chip *girq; + + girq = &pctrl->gpio_bank[id].gc.irq; + girq->chip = &pctrl->gpio_bank[id].irq_chip; + girq->parent_handler = npcmgpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(pctrl->dev, 1, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) { + ret = -ENOMEM; + goto err_register; + } + girq->parents[0] = pctrl->gpio_bank[id].irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->gpio_bank[id].gc, &pctrl->gpio_bank[id]); @@ -1972,22 +1988,6 @@ static int npcm7xx_gpio_register(struct npcm7xx_pinctrl *pctrl) gpiochip_remove(&pctrl->gpio_bank[id].gc); goto err_register; } - - ret = gpiochip_irqchip_add(&pctrl->gpio_bank[id].gc, - &pctrl->gpio_bank[id].irq_chip, - 0, handle_level_irq, - IRQ_TYPE_NONE); - if (ret < 0) { - dev_err(pctrl->dev, - "Failed to add IRQ chip %u\n", id); - gpiochip_remove(&pctrl->gpio_bank[id].gc); - goto err_register; - } - - gpiochip_set_chained_irqchip(&pctrl->gpio_bank[id].gc, - &pctrl->gpio_bank[id].irq_chip, - pctrl->gpio_bank[id].irq, - npcmgpio_irq_handler); } return 0; diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index d6de4d360cd4..e380202eb86a 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -328,6 +328,33 @@ static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset) return !!(reg & BIT(pin->line)); } +static int atmel_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, + unsigned long *bits) +{ + struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); + unsigned int bank; + + bitmap_zero(bits, atmel_pioctrl->npins); + + for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) { + unsigned int word = bank; + unsigned int offset = 0; + unsigned int reg; + +#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG + word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK); + offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG; +#endif + if (!mask[word]) + continue; + + reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR); + bits[word] |= mask[word] & (reg << offset); + } + + return 0; +} + static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) { @@ -358,11 +385,46 @@ static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val) BIT(pin->line)); } +static void atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, + unsigned long *bits) +{ + struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); + unsigned int bank; + + for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) { + unsigned int bitmask; + unsigned int word = bank; + +/* + * On a 64-bit platform, BITS_PER_LONG is 64 so it is necessary to iterate over + * two 32bit words to handle the whole bitmask + */ +#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG + word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK); +#endif + if (!mask[word]) + continue; + + bitmask = mask[word] & bits[word]; + atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask); + + bitmask = mask[word] & ~bits[word]; + atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask); + +#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG + mask[word] >>= ATMEL_PIO_NPINS_PER_BANK; + bits[word] >>= ATMEL_PIO_NPINS_PER_BANK; +#endif + } +} + static struct gpio_chip atmel_gpio_chip = { .direction_input = atmel_gpio_direction_input, .get = atmel_gpio_get, + .get_multiple = atmel_gpio_get_multiple, .direction_output = atmel_gpio_direction_output, .set = atmel_gpio_set, + .set_multiple = atmel_gpio_set_multiple, .to_irq = atmel_gpio_to_irq, .base = 0, }; diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index d6e7e9f0ddec..117075b5798f 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1723,9 +1723,11 @@ static int at91_gpio_of_irq_setup(struct platform_device *pdev, struct at91_gpio_chip *prev = NULL; struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); struct irq_chip *gpio_irqchip; - int ret, i; + struct gpio_irq_chip *girq; + int i; - gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip), GFP_KERNEL); + gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip), + GFP_KERNEL); if (!gpio_irqchip) return -ENOMEM; @@ -1747,33 +1749,30 @@ static int at91_gpio_of_irq_setup(struct platform_device *pdev, * handler will perform the actual work of handling the parent * interrupt. */ - ret = gpiochip_irqchip_add(&at91_gpio->chip, - gpio_irqchip, - 0, - handle_edge_irq, - IRQ_TYPE_NONE); - if (ret) { - dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n", - at91_gpio->pioc_idx); - return ret; - } + girq = &at91_gpio->chip.irq; + girq->chip = gpio_irqchip; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_edge_irq; - /* The top level handler handles one bank of GPIOs, except + /* + * The top level handler handles one bank of GPIOs, except * on some SoC it can handle up to three... * We only set up the handler for the first of the list. */ gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq); if (!gpiochip_prev) { - /* Then register the chain on the parent IRQ */ - gpiochip_set_chained_irqchip(&at91_gpio->chip, - gpio_irqchip, - at91_gpio->pioc_virq, - gpio_irq_handler); + girq->parent_handler = gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&pdev->dev, 1, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = at91_gpio->pioc_virq; return 0; } prev = gpiochip_get_data(gpiochip_prev); - /* we can only have 2 banks before */ for (i = 0; i < 2; i++) { if (prev->next) { @@ -1903,6 +1902,10 @@ static int at91_gpio_probe(struct platform_device *pdev) range->npins = chip->ngpio; range->gc = chip; + ret = at91_gpio_of_irq_setup(pdev, at91_chip); + if (ret) + goto gpiochip_add_err; + ret = gpiochip_add_data(chip, at91_chip); if (ret) goto gpiochip_add_err; @@ -1910,16 +1913,10 @@ static int at91_gpio_probe(struct platform_device *pdev) gpio_chips[alias_idx] = at91_chip; gpio_banks = max(gpio_banks, alias_idx + 1); - ret = at91_gpio_of_irq_setup(pdev, at91_chip); - if (ret) - goto irq_setup_err; - dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); return 0; -irq_setup_err: - gpiochip_remove(chip); gpiochip_add_err: clk_enable_err: clk_disable_unprepare(at91_chip->clock); diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c index 08b9e909e917..063a629be9b2 100644 --- a/drivers/pinctrl/pinctrl-coh901.c +++ b/drivers/pinctrl/pinctrl-coh901.c @@ -616,6 +616,7 @@ static int __init u300_gpio_probe(struct platform_device *pdev) { struct u300_gpio *gpio; struct resource *memres; + struct gpio_irq_chip *girq; int err = 0; int portno; u32 val; @@ -672,26 +673,17 @@ static int __init u300_gpio_probe(struct platform_device *pdev) gpio->base + U300_GPIO_CR); u300_gpio_init_coh901571(gpio); -#ifdef CONFIG_OF_GPIO - gpio->chip.of_node = pdev->dev.of_node; -#endif - err = gpiochip_add_data(&gpio->chip, gpio); - if (err) { - dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); - goto err_no_chip; - } - - err = gpiochip_irqchip_add(&gpio->chip, - &u300_gpio_irqchip, - 0, - handle_simple_irq, - IRQ_TYPE_EDGE_FALLING); - if (err) { - dev_err(gpio->dev, "no GPIO irqchip\n"); - goto err_no_irqchip; + girq = &gpio->chip.irq; + girq->chip = &u300_gpio_irqchip; + girq->parent_handler = u300_gpio_irq_handler; + girq->num_parents = U300_GPIO_NUM_PORTS; + girq->parents = devm_kcalloc(gpio->dev, U300_GPIO_NUM_PORTS, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) { + err = -ENOMEM; + goto err_dis_clk; } - - /* Add each port with its IRQ separately */ for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) { struct u300_gpio_port *port = &gpio->ports[portno]; @@ -700,16 +692,21 @@ static int __init u300_gpio_probe(struct platform_device *pdev) port->gpio = gpio; port->irq = platform_get_irq(pdev, portno); - - gpiochip_set_chained_irqchip(&gpio->chip, - &u300_gpio_irqchip, - port->irq, - u300_gpio_irq_handler); + girq->parents[portno] = port->irq; /* Turns off irq force (test register) for this port */ writel(0x0, gpio->base + portno * gpio->stride + ifr); } - dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno); + girq->default_type = IRQ_TYPE_EDGE_FALLING; + girq->handler = handle_simple_irq; +#ifdef CONFIG_OF_GPIO + gpio->chip.of_node = pdev->dev.of_node; +#endif + err = gpiochip_add_data(&gpio->chip, gpio); + if (err) { + dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); + goto err_dis_clk; + } /* * Add pinctrl pin ranges, the pin controller must be registered @@ -729,9 +726,8 @@ static int __init u300_gpio_probe(struct platform_device *pdev) return 0; err_no_range: -err_no_irqchip: gpiochip_remove(&gpio->chip); -err_no_chip: +err_dis_clk: clk_disable_unprepare(gpio->clk); dev_err(&pdev->dev, "module ERROR:%d\n", err); return err; diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 6e2683016c1f..06cae38f6daf 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -1940,6 +1940,7 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, { struct ingenic_gpio_chip *jzgc; struct device *dev = jzpc->dev; + struct gpio_irq_chip *girq; unsigned int bank; int err; @@ -1982,10 +1983,6 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, jzgc->gc.free = gpiochip_generic_free; } - err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc); - if (err) - return err; - jzgc->irq = irq_of_parse_and_map(node, 0); if (!jzgc->irq) return -EINVAL; @@ -2000,13 +1997,22 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake; jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; - err = gpiochip_irqchip_add(&jzgc->gc, &jzgc->irq_chip, 0, - handle_level_irq, IRQ_TYPE_NONE); + girq = &jzgc->gc.irq; + girq->chip = &jzgc->irq_chip; + girq->parent_handler = ingenic_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = jzgc->irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + + err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc); if (err) return err; - gpiochip_set_chained_irqchip(&jzgc->gc, &jzgc->irq_chip, - jzgc->irq, ingenic_gpio_irq_handler); return 0; } diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index fb76fb2e9ea5..eb3dd0d46d6c 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -736,6 +736,7 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, struct ocelot_pinctrl *info) { struct gpio_chip *gc; + struct gpio_irq_chip *girq; int ret, irq; info->gpio_chip = ocelot_gpiolib_chip; @@ -747,22 +748,26 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, gc->of_node = info->dev->of_node; gc->label = "ocelot-gpio"; - ret = devm_gpiochip_add_data(&pdev->dev, gc, info); - if (ret) - return ret; - irq = irq_of_parse_and_map(pdev->dev.of_node, 0); if (irq <= 0) return irq; - ret = gpiochip_irqchip_add(gc, &ocelot_irqchip, 0, handle_edge_irq, - IRQ_TYPE_NONE); + girq = &gc->irq; + girq->chip = &ocelot_irqchip; + girq->parent_handler = ocelot_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_edge_irq; + + ret = devm_gpiochip_add_data(&pdev->dev, gc, info); if (ret) return ret; - gpiochip_set_chained_irqchip(gc, &ocelot_irqchip, irq, - ocelot_irq_handler); - return 0; } diff --git a/drivers/pinctrl/pinctrl-oxnas.c b/drivers/pinctrl/pinctrl-oxnas.c index 55488ca246f1..40dc1251432a 100644 --- a/drivers/pinctrl/pinctrl-oxnas.c +++ b/drivers/pinctrl/pinctrl-oxnas.c @@ -1197,6 +1197,7 @@ static int oxnas_gpio_probe(struct platform_device *pdev) unsigned int id, ngpios; int irq, ret; struct resource *res; + struct gpio_irq_chip *girq; if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &pinspec)) { @@ -1232,6 +1233,18 @@ static int oxnas_gpio_probe(struct platform_device *pdev) bank->gpio_chip.parent = &pdev->dev; bank->gpio_chip.of_node = np; bank->gpio_chip.ngpio = ngpios; + girq = &bank->gpio_chip.irq; + girq->chip = &bank->irq_chip; + girq->parent_handler = oxnas_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + ret = gpiochip_add_data(&bank->gpio_chip, bank); if (ret < 0) { dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n", @@ -1239,18 +1252,6 @@ static int oxnas_gpio_probe(struct platform_device *pdev) return ret; } - ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip, - 0, handle_level_irq, IRQ_TYPE_NONE); - if (ret < 0) { - dev_err(&pdev->dev, "Failed to add IRQ chip %u: %d\n", - id, ret); - gpiochip_remove(&bank->gpio_chip); - return ret; - } - - gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip, - irq, oxnas_gpio_irq_handler); - return 0; } diff --git a/drivers/pinctrl/pinctrl-pic32.c b/drivers/pinctrl/pinctrl-pic32.c index e7f6dd5ab578..7e4c5a08a932 100644 --- a/drivers/pinctrl/pinctrl-pic32.c +++ b/drivers/pinctrl/pinctrl-pic32.c @@ -2203,6 +2203,7 @@ static int pic32_gpio_probe(struct platform_device *pdev) u32 id; int irq, ret; struct resource *res; + struct gpio_irq_chip *girq; if (of_property_read_u32(np, "microchip,gpio-bank", &id)) { dev_err(&pdev->dev, "microchip,gpio-bank property not found\n"); @@ -2240,25 +2241,23 @@ static int pic32_gpio_probe(struct platform_device *pdev) bank->gpio_chip.parent = &pdev->dev; bank->gpio_chip.of_node = np; + girq = &bank->gpio_chip.irq; + girq->chip = &bank->irq_chip; + girq->parent_handler = pic32_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + girq->parents[0] = irq; ret = gpiochip_add_data(&bank->gpio_chip, bank); if (ret < 0) { dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n", id, ret); return ret; } - - ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip, - 0, handle_level_irq, IRQ_TYPE_NONE); - if (ret < 0) { - dev_err(&pdev->dev, "Failed to add IRQ chip %u: %d\n", - id, ret); - gpiochip_remove(&bank->gpio_chip); - return ret; - } - - gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip, - irq, pic32_gpio_irq_handler); - return 0; } diff --git a/drivers/pinctrl/pinctrl-pistachio.c b/drivers/pinctrl/pinctrl-pistachio.c index 379e9a6a6d89..eb40ae9f8639 100644 --- a/drivers/pinctrl/pinctrl-pistachio.c +++ b/drivers/pinctrl/pinctrl-pistachio.c @@ -1352,6 +1352,7 @@ static int pistachio_gpio_register(struct pistachio_pinctrl *pctl) for (i = 0; i < pctl->nbanks; i++) { char child_name[sizeof("gpioXX")]; struct device_node *child; + struct gpio_irq_chip *girq; snprintf(child_name, sizeof(child_name), "gpio%d", i); child = of_get_child_by_name(node, child_name); @@ -1383,23 +1384,28 @@ static int pistachio_gpio_register(struct pistachio_pinctrl *pctl) bank->gpio_chip.parent = pctl->dev; bank->gpio_chip.of_node = child; - ret = gpiochip_add_data(&bank->gpio_chip, bank); - if (ret < 0) { - dev_err(pctl->dev, "Failed to add GPIO chip %u: %d\n", - i, ret); + + girq = &bank->gpio_chip.irq; + girq->chip = &bank->irq_chip; + girq->parent_handler = pistachio_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(pctl->dev, 1, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) { + ret = -ENOMEM; goto err; } + girq->parents[0] = irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; - ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip, - 0, handle_level_irq, IRQ_TYPE_NONE); + ret = gpiochip_add_data(&bank->gpio_chip, bank); if (ret < 0) { - dev_err(pctl->dev, "Failed to add IRQ chip %u: %d\n", + dev_err(pctl->dev, "Failed to add GPIO chip %u: %d\n", i, ret); - gpiochip_remove(&bank->gpio_chip); goto err; } - gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip, - irq, pistachio_gpio_irq_handler); ret = gpiochip_add_pin_range(&bank->gpio_chip, dev_name(pctl->dev), 0, diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index dc0bbf198cbc..fc9a2a9959d9 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -58,6 +58,7 @@ enum rockchip_pinctrl_type { RK3128, RK3188, RK3288, + RK3308, RK3368, RK3399, }; @@ -70,6 +71,7 @@ enum rockchip_pinctrl_type { #define IOMUX_SOURCE_PMU BIT(2) #define IOMUX_UNROUTED BIT(3) #define IOMUX_WIDTH_3BIT BIT(4) +#define IOMUX_WIDTH_2BIT BIT(5) /** * @type: iomux variant using IOMUX_* constants @@ -656,6 +658,100 @@ static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { }, }; +static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { + { + .num = 1, + .pin = 14, + .reg = 0x28, + .bit = 12, + .mask = 0xf + }, { + .num = 1, + .pin = 15, + .reg = 0x2c, + .bit = 0, + .mask = 0x3 + }, { + .num = 1, + .pin = 18, + .reg = 0x30, + .bit = 4, + .mask = 0xf + }, { + .num = 1, + .pin = 19, + .reg = 0x30, + .bit = 8, + .mask = 0xf + }, { + .num = 1, + .pin = 20, + .reg = 0x30, + .bit = 12, + .mask = 0xf + }, { + .num = 1, + .pin = 21, + .reg = 0x34, + .bit = 0, + .mask = 0xf + }, { + .num = 1, + .pin = 22, + .reg = 0x34, + .bit = 4, + .mask = 0xf + }, { + .num = 1, + .pin = 23, + .reg = 0x34, + .bit = 8, + .mask = 0xf + }, { + .num = 3, + .pin = 12, + .reg = 0x68, + .bit = 8, + .mask = 0xf + }, { + .num = 3, + .pin = 13, + .reg = 0x68, + .bit = 12, + .mask = 0xf + }, { + .num = 2, + .pin = 2, + .reg = 0x608, + .bit = 0, + .mask = 0x7 + }, { + .num = 2, + .pin = 3, + .reg = 0x608, + .bit = 4, + .mask = 0x7 + }, { + .num = 2, + .pin = 16, + .reg = 0x610, + .bit = 8, + .mask = 0x7 + }, { + .num = 3, + .pin = 10, + .reg = 0x610, + .bit = 0, + .mask = 0x7 + }, { + .num = 3, + .pin = 11, + .reg = 0x610, + .bit = 4, + .mask = 0x7 + }, +}; + static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { { .num = 2, @@ -982,6 +1078,192 @@ static struct rockchip_mux_route_data rk3288_mux_route_data[] = { }, }; +static struct rockchip_mux_route_data rk3308_mux_route_data[] = { + { + /* rtc_clk */ + .bank_num = 0, + .pin = 19, + .func = 1, + .route_offset = 0x314, + .route_val = BIT(16 + 0) | BIT(0), + }, { + /* uart2_rxm0 */ + .bank_num = 1, + .pin = 22, + .func = 2, + .route_offset = 0x314, + .route_val = BIT(16 + 2) | BIT(16 + 3), + }, { + /* uart2_rxm1 */ + .bank_num = 4, + .pin = 26, + .func = 2, + .route_offset = 0x314, + .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), + }, { + /* i2c3_sdam0 */ + .bank_num = 0, + .pin = 15, + .func = 2, + .route_offset = 0x608, + .route_val = BIT(16 + 8) | BIT(16 + 9), + }, { + /* i2c3_sdam1 */ + .bank_num = 3, + .pin = 12, + .func = 2, + .route_offset = 0x608, + .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), + }, { + /* i2c3_sdam2 */ + .bank_num = 2, + .pin = 0, + .func = 3, + .route_offset = 0x608, + .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), + }, { + /* i2s-8ch-1-sclktxm0 */ + .bank_num = 1, + .pin = 3, + .func = 2, + .route_offset = 0x308, + .route_val = BIT(16 + 3), + }, { + /* i2s-8ch-1-sclkrxm0 */ + .bank_num = 1, + .pin = 4, + .func = 2, + .route_offset = 0x308, + .route_val = BIT(16 + 3), + }, { + /* i2s-8ch-1-sclktxm1 */ + .bank_num = 1, + .pin = 13, + .func = 2, + .route_offset = 0x308, + .route_val = BIT(16 + 3) | BIT(3), + }, { + /* i2s-8ch-1-sclkrxm1 */ + .bank_num = 1, + .pin = 14, + .func = 2, + .route_offset = 0x308, + .route_val = BIT(16 + 3) | BIT(3), + }, { + /* pdm-clkm0 */ + .bank_num = 1, + .pin = 4, + .func = 3, + .route_offset = 0x308, + .route_val = BIT(16 + 12) | BIT(16 + 13), + }, { + /* pdm-clkm1 */ + .bank_num = 1, + .pin = 14, + .func = 4, + .route_offset = 0x308, + .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), + }, { + /* pdm-clkm2 */ + .bank_num = 2, + .pin = 6, + .func = 2, + .route_offset = 0x308, + .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), + }, { + /* pdm-clkm-m2 */ + .bank_num = 2, + .pin = 4, + .func = 3, + .route_offset = 0x600, + .route_val = BIT(16 + 2) | BIT(2), + }, { + /* spi1_miso */ + .bank_num = 3, + .pin = 10, + .func = 3, + .route_offset = 0x314, + .route_val = BIT(16 + 9), + }, { + /* spi1_miso_m1 */ + .bank_num = 2, + .pin = 4, + .func = 2, + .route_offset = 0x314, + .route_val = BIT(16 + 9) | BIT(9), + }, { + /* owire_m0 */ + .bank_num = 0, + .pin = 11, + .func = 3, + .route_offset = 0x314, + .route_val = BIT(16 + 10) | BIT(16 + 11), + }, { + /* owire_m1 */ + .bank_num = 1, + .pin = 22, + .func = 7, + .route_offset = 0x314, + .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), + }, { + /* owire_m2 */ + .bank_num = 2, + .pin = 2, + .func = 5, + .route_offset = 0x314, + .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), + }, { + /* can_rxd_m0 */ + .bank_num = 0, + .pin = 11, + .func = 2, + .route_offset = 0x314, + .route_val = BIT(16 + 12) | BIT(16 + 13), + }, { + /* can_rxd_m1 */ + .bank_num = 1, + .pin = 22, + .func = 5, + .route_offset = 0x314, + .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), + }, { + /* can_rxd_m2 */ + .bank_num = 2, + .pin = 2, + .func = 4, + .route_offset = 0x314, + .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), + }, { + /* mac_rxd0_m0 */ + .bank_num = 1, + .pin = 20, + .func = 3, + .route_offset = 0x314, + .route_val = BIT(16 + 14), + }, { + /* mac_rxd0_m1 */ + .bank_num = 4, + .pin = 2, + .func = 2, + .route_offset = 0x314, + .route_val = BIT(16 + 14) | BIT(14), + }, { + /* uart3_rx */ + .bank_num = 3, + .pin = 12, + .func = 4, + .route_offset = 0x314, + .route_val = BIT(16 + 15), + }, { + /* uart3_rx_m1 */ + .bank_num = 0, + .pin = 17, + .func = 3, + .route_offset = 0x314, + .route_val = BIT(16 + 15) | BIT(15), + }, +}; + static struct rockchip_mux_route_data rk3328_mux_route_data[] = { { /* uart2dbg_rxm0 */ @@ -1475,6 +1757,26 @@ static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, return 0; } +#define RK3308_SCHMITT_PINS_PER_REG 8 +#define RK3308_SCHMITT_BANK_STRIDE 16 +#define RK3308_SCHMITT_GRF_OFFSET 0x1a0 + +static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + *reg = RK3308_SCHMITT_GRF_OFFSET; + + *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; + *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); + *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; + + return 0; +} + #define RK2928_PULL_OFFSET 0x118 #define RK2928_PULL_PINS_PER_REG 16 #define RK2928_PULL_BANK_STRIDE 8 @@ -1646,6 +1948,40 @@ static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, *bit *= RK3288_DRV_BITS_PER_PIN; } +#define RK3308_PULL_OFFSET 0xa0 + +static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + *reg = RK3308_PULL_OFFSET; + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % RK3188_PULL_PINS_PER_REG); + *bit *= RK3188_PULL_BITS_PER_PIN; +} + +#define RK3308_DRV_GRF_OFFSET 0x100 + +static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + *reg = RK3308_DRV_GRF_OFFSET; + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); + + *bit = (pin_num % RK3288_DRV_PINS_PER_REG); + *bit *= RK3288_DRV_BITS_PER_PIN; +} + #define RK3368_PULL_GRF_OFFSET 0x100 #define RK3368_PULL_PMU_OFFSET 0x10 @@ -1986,6 +2322,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) case RV1108: case RK3188: case RK3288: + case RK3308: case RK3368: case RK3399: pull_type = bank->pull_type[pin_num / 8]; @@ -2030,6 +2367,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, case RV1108: case RK3188: case RK3288: + case RK3308: case RK3368: case RK3399: pull_type = bank->pull_type[pin_num / 8]; @@ -2293,6 +2631,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, case RV1108: case RK3188: case RK3288: + case RK3308: case RK3368: case RK3399: return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); @@ -3303,7 +3642,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( * 4bit iomux'es are spread over two registers. */ inc = (iom->type & (IOMUX_WIDTH_4BIT | - IOMUX_WIDTH_3BIT)) ? 8 : 4; + IOMUX_WIDTH_3BIT | + IOMUX_WIDTH_2BIT)) ? 8 : 4; if (iom->type & IOMUX_SOURCE_PMU) pmu_offs += inc; else @@ -3709,6 +4049,44 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = { .drv_calc_reg = rk3288_calc_drv_reg_and_bit, }; +static struct rockchip_pin_bank rk3308_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, + IOMUX_WIDTH_2BIT, + IOMUX_WIDTH_2BIT, + IOMUX_WIDTH_2BIT), + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, + IOMUX_WIDTH_2BIT, + IOMUX_WIDTH_2BIT, + IOMUX_WIDTH_2BIT), + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, + IOMUX_WIDTH_2BIT, + IOMUX_WIDTH_2BIT, + IOMUX_WIDTH_2BIT), + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, + IOMUX_WIDTH_2BIT, + IOMUX_WIDTH_2BIT, + IOMUX_WIDTH_2BIT), + PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, + IOMUX_WIDTH_2BIT, + IOMUX_WIDTH_2BIT, + IOMUX_WIDTH_2BIT), +}; + +static struct rockchip_pin_ctrl rk3308_pin_ctrl = { + .pin_banks = rk3308_pin_banks, + .nr_banks = ARRAY_SIZE(rk3308_pin_banks), + .label = "RK3308-GPIO", + .type = RK3308, + .grf_mux_offset = 0x0, + .iomux_recalced = rk3308_mux_recalced_data, + .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), + .iomux_routes = rk3308_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), + .pull_calc_reg = rk3308_calc_pull_reg_and_bit, + .drv_calc_reg = rk3308_calc_drv_reg_and_bit, + .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, +}; + static struct rockchip_pin_bank rk3328_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), @@ -3849,6 +4227,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = &rk3228_pin_ctrl }, { .compatible = "rockchip,rk3288-pinctrl", .data = &rk3288_pin_ctrl }, + { .compatible = "rockchip,rk3308-pinctrl", + .data = &rk3308_pin_ctrl }, { .compatible = "rockchip,rk3328-pinctrl", .data = &rk3328_pin_ctrl }, { .compatible = "rockchip,rk3368-pinctrl", diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 00db8b9efb2c..4f39a7945d01 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1477,7 +1477,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, struct device *dev = info->dev; int bank_num = of_alias_get_id(np, "gpio"); struct resource res, irq_res; - int gpio_irq = 0, err; + int err; if (of_address_to_resource(np, 0, &res)) return -ENODEV; @@ -1500,12 +1500,6 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; range->npins = bank->gpio_chip.ngpio; range->gc = &bank->gpio_chip; - err = gpiochip_add_data(&bank->gpio_chip, bank); - if (err) { - dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num); - return err; - } - dev_info(dev, "%s bank added.\n", range->name); /** * GPIO bank can have one of the two possible types of @@ -1527,23 +1521,40 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, */ if (of_irq_to_resource(np, 0, &irq_res) > 0) { - gpio_irq = irq_res.start; - gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip, - gpio_irq, st_gpio_irq_handler); - } + struct gpio_irq_chip *girq; + int gpio_irq = irq_res.start; - if (info->irqmux_base || gpio_irq > 0) { - err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip, - 0, handle_simple_irq, - IRQ_TYPE_NONE); - if (err) { - gpiochip_remove(&bank->gpio_chip); - dev_info(dev, "could not add irqchip\n"); - return err; + /* This is not a valid IRQ */ + if (gpio_irq <= 0) { + dev_err(dev, "invalid IRQ for %pOF bank\n", np); + goto skip_irq; } - } else { - dev_info(dev, "No IRQ support for %pOF bank\n", np); + /* We need to have a mux as well */ + if (!info->irqmux_base) { + dev_err(dev, "no irqmux for %pOF bank\n", np); + goto skip_irq; + } + + girq = &bank->gpio_chip.irq; + girq->chip = &st_gpio_irqchip; + girq->parent_handler = st_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = gpio_irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_simple_irq; + } + +skip_irq: + err = gpiochip_add_data(&bank->gpio_chip, bank); + if (err) { + dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num); + return err; } + dev_info(dev, "%s bank added.\n", range->name); return 0; } diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index 974973777395..e6f76d2f18ab 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -505,6 +505,25 @@ static void stmfx_pinctrl_irq_bus_sync_unlock(struct irq_data *data) mutex_unlock(&pctl->lock); } +static int stmfx_gpio_irq_request_resources(struct irq_data *data) +{ + struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); + int ret; + + ret = stmfx_gpio_direction_input(gpio_chip, data->hwirq); + if (ret) + return ret; + + return gpiochip_reqres_irq(gpio_chip, data->hwirq); +} + +static void stmfx_gpio_irq_release_resources(struct irq_data *data) +{ + struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); + + return gpiochip_relres_irq(gpio_chip, data->hwirq); +} + static void stmfx_pinctrl_irq_toggle_trigger(struct stmfx_pinctrl *pctl, unsigned int offset) { @@ -678,6 +697,8 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev) pctl->irq_chip.irq_set_type = stmfx_pinctrl_irq_set_type; pctl->irq_chip.irq_bus_lock = stmfx_pinctrl_irq_bus_lock; pctl->irq_chip.irq_bus_sync_unlock = stmfx_pinctrl_irq_bus_sync_unlock; + pctl->irq_chip.irq_request_resources = stmfx_gpio_irq_request_resources; + pctl->irq_chip.irq_release_resources = stmfx_gpio_irq_release_resources; ret = gpiochip_irqchip_add_nested(&pctl->gpio_chip, &pctl->irq_chip, 0, handle_bad_irq, IRQ_TYPE_NONE); diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 32fc2458b8eb..4f5645245b06 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -90,6 +90,16 @@ config PINCTRL_MSM8916 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found on the Qualcomm 8916 platform. +config PINCTRL_MSM8976 + tristate "Qualcomm 8976 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found on the Qualcomm MSM8976 platform. + The Qualcomm MSM8956, APQ8056, APQ8076 platforms are also + supported by this driver. + config PINCTRL_MSM8994 tristate "Qualcomm 8994 pin controller driver" depends on GPIOLIB && OF @@ -152,6 +162,7 @@ config PINCTRL_QCOM_SSBI_PMIC select PINMUX select PINCONF select GENERIC_PINCONF + select GPIOLIB_IRQCHIP select IRQ_DOMAIN_HIERARCHY help This is the pinctrl, pinmux, pinconf and gpiolib driver for the diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index f8bb0c265381..c2c2f9ad6827 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o +obj-$(CONFIG_PINCTRL_MSM8976) += pinctrl-msm8976.o obj-$(CONFIG_PINCTRL_MSM8994) += pinctrl-msm8994.o obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o obj-$(CONFIG_PINCTRL_MSM8998) += pinctrl-msm8998.o diff --git a/drivers/pinctrl/qcom/pinctrl-msm8976.c b/drivers/pinctrl/qcom/pinctrl-msm8976.c new file mode 100644 index 000000000000..e1259ce27396 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8976.c @@ -0,0 +1,1127 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2016, AngeloGioacchino Del Regno <kholk11@gmail.com> + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_BASE 0x0 +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_BASE + REG_SIZE * id, \ + .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ + .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc msm8976_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "SDC1_CLK"), + PINCTRL_PIN(146, "SDC1_CMD"), + PINCTRL_PIN(147, "SDC1_DATA"), + PINCTRL_PIN(148, "SDC1_RCLK"), + PINCTRL_PIN(149, "SDC2_CLK"), + PINCTRL_PIN(150, "SDC2_CMD"), + PINCTRL_PIN(151, "SDC2_DATA"), + PINCTRL_PIN(152, "QDSD_CLK"), + PINCTRL_PIN(153, "QDSD_CMD"), + PINCTRL_PIN(154, "QDSD_DATA0"), + PINCTRL_PIN(155, "QDSD_DATA1"), + PINCTRL_PIN(156, "QDSD_DATA2"), + PINCTRL_PIN(157, "QDSD_DATA3"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); + +static const unsigned int sdc1_clk_pins[] = { 145 }; +static const unsigned int sdc1_cmd_pins[] = { 146 }; +static const unsigned int sdc1_data_pins[] = { 147 }; +static const unsigned int sdc1_rclk_pins[] = { 148 }; +static const unsigned int sdc2_clk_pins[] = { 149 }; +static const unsigned int sdc2_cmd_pins[] = { 150 }; +static const unsigned int sdc2_data_pins[] = { 151 }; +static const unsigned int qdsd_clk_pins[] = { 152 }; +static const unsigned int qdsd_cmd_pins[] = { 153 }; +static const unsigned int qdsd_data0_pins[] = { 154 }; +static const unsigned int qdsd_data1_pins[] = { 155 }; +static const unsigned int qdsd_data2_pins[] = { 156 }; +static const unsigned int qdsd_data3_pins[] = { 157 }; + +enum msm8976_functions { + msm_mux_gpio, + msm_mux_blsp_uart1, + msm_mux_blsp_spi1, + msm_mux_smb_int, + msm_mux_blsp_i2c1, + msm_mux_blsp_spi2, + msm_mux_blsp_uart2, + msm_mux_blsp_i2c2, + msm_mux_gcc_gp1_clk_b, + msm_mux_blsp_spi3, + msm_mux_qdss_tracedata_b, + msm_mux_blsp_i2c3, + msm_mux_gcc_gp2_clk_b, + msm_mux_gcc_gp3_clk_b, + msm_mux_blsp_spi4, + msm_mux_cap_int, + msm_mux_blsp_i2c4, + msm_mux_blsp_spi5, + msm_mux_blsp_uart5, + msm_mux_qdss_traceclk_a, + msm_mux_m_voc, + msm_mux_blsp_i2c5, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracedata_a, + msm_mux_blsp_spi6, + msm_mux_blsp_uart6, + msm_mux_qdss_tracectl_b, + msm_mux_blsp_i2c6, + msm_mux_qdss_traceclk_b, + msm_mux_mdp_vsync, + msm_mux_pri_mi2s_mclk_a, + msm_mux_sec_mi2s_mclk_a, + msm_mux_cam_mclk, + msm_mux_cci0_i2c, + msm_mux_cci1_i2c, + msm_mux_blsp1_spi, + msm_mux_blsp3_spi, + msm_mux_gcc_gp1_clk_a, + msm_mux_gcc_gp2_clk_a, + msm_mux_gcc_gp3_clk_a, + msm_mux_uim_batt, + msm_mux_sd_write, + msm_mux_uim1_data, + msm_mux_uim1_clk, + msm_mux_uim1_reset, + msm_mux_uim1_present, + msm_mux_uim2_data, + msm_mux_uim2_clk, + msm_mux_uim2_reset, + msm_mux_uim2_present, + msm_mux_ts_xvdd, + msm_mux_mipi_dsi0, + msm_mux_us_euro, + msm_mux_ts_resout, + msm_mux_ts_sample, + msm_mux_sec_mi2s_mclk_b, + msm_mux_pri_mi2s, + msm_mux_codec_reset, + msm_mux_cdc_pdm0, + msm_mux_us_emitter, + msm_mux_pri_mi2s_mclk_b, + msm_mux_pri_mi2s_mclk_c, + msm_mux_lpass_slimbus, + msm_mux_lpass_slimbus0, + msm_mux_lpass_slimbus1, + msm_mux_codec_int1, + msm_mux_codec_int2, + msm_mux_wcss_bt, + msm_mux_sdc3, + msm_mux_wcss_wlan2, + msm_mux_wcss_wlan1, + msm_mux_wcss_wlan0, + msm_mux_wcss_wlan, + msm_mux_wcss_fm, + msm_mux_key_volp, + msm_mux_key_snapshot, + msm_mux_key_focus, + msm_mux_key_home, + msm_mux_pwr_down, + msm_mux_dmic0_clk, + msm_mux_hdmi_int, + msm_mux_dmic0_data, + msm_mux_wsa_vi, + msm_mux_wsa_en, + msm_mux_blsp_spi8, + msm_mux_wsa_irq, + msm_mux_blsp_i2c8, + msm_mux_pa_indicator, + msm_mux_modem_tsync, + msm_mux_ssbi_wtr1, + msm_mux_gsm1_tx, + msm_mux_gsm0_tx, + msm_mux_sdcard_det, + msm_mux_sec_mi2s, + msm_mux_ss_switch, + msm_mux_NA, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", +}; +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const smb_int_groups[] = { + "gpio1", +}; +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3", +}; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7", +}; +static const char * const gcc_gp1_clk_b_groups[] = { + "gpio105", +}; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const qdss_tracedata_b_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", + "gpio31", "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", + "gpio116", "gpio126", "gpio128", "gpio129", +}; +static const char * const blsp_i2c3_groups[] = { + "gpio10", "gpio11", +}; +static const char * const gcc_gp2_clk_b_groups[] = { + "gpio12", +}; +static const char * const gcc_gp3_clk_b_groups[] = { + "gpio13", +}; +static const char * const blsp_spi4_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const cap_int_groups[] = { + "gpio13", +}; +static const char * const blsp_i2c4_groups[] = { + "gpio14", "gpio15", +}; +static const char * const blsp_spi5_groups[] = { + "gpio134", "gpio135", "gpio136", "gpio137", +}; +static const char * const blsp_uart5_groups[] = { + "gpio134", "gpio135", "gpio136", "gpio137", +}; +static const char * const qdss_traceclk_a_groups[] = { + "gpio46", +}; +const char * const m_voc_groups[] = { + "gpio123", "gpio124", +}; +static const char * const blsp_i2c5_groups[] = { + "gpio136", "gpio137", +}; +static const char * const qdss_tracectl_a_groups[] = { + "gpio45", +}; +static const char * const qdss_tracedata_a_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio47", "gpio48", "gpio62", "gpio69", "gpio120", + "gpio121", "gpio130", "gpio131", +}; +static const char * const blsp_spi6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char * const blsp_uart6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char * const qdss_tracectl_b_groups[] = { + "gpio5", +}; +static const char * const blsp_i2c6_groups[] = { + "gpio22", "gpio23", +}; +static const char * const qdss_traceclk_b_groups[] = { + "gpio5", +}; +static const char * const mdp_vsync_groups[] = { + "gpio24", "gpio25", +}; +static const char * const pri_mi2s_mclk_a_groups[] = { + "gpio126", +}; +static const char * const sec_mi2s_mclk_a_groups[] = { + "gpio62", +}; +static const char * const cam_mclk_groups[] = { + "gpio26", "gpio27", "gpio28", +}; +static const char * const cci0_i2c_groups[] = { + "gpio30", "gpio29", +}; +static const char * const cci1_i2c_groups[] = { + "gpio104", "gpio103", +}; +static const char * const blsp1_spi_groups[] = { + "gpio101", +}; +static const char * const blsp3_spi_groups[] = { + "gpio106", "gpio107", +}; +static const char * const gcc_gp1_clk_a_groups[] = { + "gpio49", +}; +static const char * const gcc_gp2_clk_a_groups[] = { + "gpio50", +}; +static const char * const gcc_gp3_clk_a_groups[] = { + "gpio51", +}; +static const char * const uim_batt_groups[] = { + "gpio61", +}; +static const char * const sd_write_groups[] = { + "gpio50", +}; +static const char * const uim2_data_groups[] = { + "gpio51", +}; +static const char * const uim2_clk_groups[] = { + "gpio52", +}; +static const char * const uim2_reset_groups[] = { + "gpio53", +}; +static const char * const uim2_present_groups[] = { + "gpio54", +}; +static const char * const uim1_data_groups[] = { + "gpio55", +}; +static const char * const uim1_clk_groups[] = { + "gpio56", +}; +static const char * const uim1_reset_groups[] = { + "gpio57", +}; +static const char * const uim1_present_groups[] = { + "gpio58", +}; +static const char * const ts_xvdd_groups[] = { + "gpio60", +}; +static const char * const mipi_dsi0_groups[] = { + "gpio61", +}; +static const char * const us_euro_groups[] = { + "gpio63", +}; +static const char * const ts_resout_groups[] = { + "gpio64", +}; +static const char * const ts_sample_groups[] = { + "gpio65", +}; +static const char * const sec_mi2s_mclk_b_groups[] = { + "gpio66", +}; +static const char * const pri_mi2s_groups[] = { + "gpio122", "gpio123", "gpio124", "gpio125", "gpio127", +}; +static const char * const codec_reset_groups[] = { + "gpio67", +}; +static const char * const cdc_pdm0_groups[] = { + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", +}; +static const char * const us_emitter_groups[] = { + "gpio68", +}; +static const char * const pri_mi2s_mclk_b_groups[] = { + "gpio62", +}; +static const char * const pri_mi2s_mclk_c_groups[] = { + "gpio116", +}; +static const char * const lpass_slimbus_groups[] = { + "gpio117", +}; +static const char * const lpass_slimbus0_groups[] = { + "gpio118", +}; +static const char * const lpass_slimbus1_groups[] = { + "gpio119", +}; +static const char * const codec_int1_groups[] = { + "gpio73", +}; +static const char * const codec_int2_groups[] = { + "gpio74", +}; +static const char * const wcss_bt_groups[] = { + "gpio39", "gpio47", "gpio88", +}; +static const char * const sdc3_groups[] = { + "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", +}; +static const char * const wcss_wlan2_groups[] = { + "gpio40", +}; +static const char * const wcss_wlan1_groups[] = { + "gpio41", +}; +static const char * const wcss_wlan0_groups[] = { + "gpio42", +}; +static const char * const wcss_wlan_groups[] = { + "gpio43", "gpio44", +}; +static const char * const wcss_fm_groups[] = { + "gpio45", "gpio46", +}; +static const char * const key_volp_groups[] = { + "gpio85", +}; +static const char * const key_snapshot_groups[] = { + "gpio86", +}; +static const char * const key_focus_groups[] = { + "gpio87", +}; +static const char * const key_home_groups[] = { + "gpio88", +}; +static const char * const pwr_down_groups[] = { + "gpio89", +}; +static const char * const dmic0_clk_groups[] = { + "gpio66", +}; +static const char * const hdmi_int_groups[] = { + "gpio90", +}; +static const char * const dmic0_data_groups[] = { + "gpio67", +}; +static const char * const wsa_vi_groups[] = { + "gpio108", "gpio109", +}; +static const char * const wsa_en_groups[] = { + "gpio96", +}; +static const char * const blsp_spi8_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const wsa_irq_groups[] = { + "gpio97", +}; +static const char * const blsp_i2c8_groups[] = { + "gpio18", "gpio19", +}; +static const char * const pa_indicator_groups[] = { + "gpio92", +}; +static const char * const modem_tsync_groups[] = { + "gpio93", +}; +static const char * const nav_tsync_groups[] = { + "gpio93", +}; +static const char * const ssbi_wtr1_groups[] = { + "gpio79", "gpio94", +}; +static const char * const gsm1_tx_groups[] = { + "gpio95", +}; +static const char * const gsm0_tx_groups[] = { + "gpio99", +}; +static const char * const sdcard_det_groups[] = { + "gpio133", +}; +static const char * const sec_mi2s_groups[] = { + "gpio102", "gpio105", "gpio134", "gpio135", +}; + +static const char * const ss_switch_groups[] = { + "gpio139", +}; + +static const struct msm_function msm8976_functions[] = { + FUNCTION(gpio), + FUNCTION(blsp_spi1), + FUNCTION(smb_int), + FUNCTION(blsp_i2c1), + FUNCTION(blsp_spi2), + FUNCTION(blsp_uart1), + FUNCTION(blsp_uart2), + FUNCTION(blsp_i2c2), + FUNCTION(gcc_gp1_clk_b), + FUNCTION(blsp_spi3), + FUNCTION(qdss_tracedata_b), + FUNCTION(blsp_i2c3), + FUNCTION(gcc_gp2_clk_b), + FUNCTION(gcc_gp3_clk_b), + FUNCTION(blsp_spi4), + FUNCTION(cap_int), + FUNCTION(blsp_i2c4), + FUNCTION(blsp_spi5), + FUNCTION(blsp_uart5), + FUNCTION(qdss_traceclk_a), + FUNCTION(m_voc), + FUNCTION(blsp_i2c5), + FUNCTION(qdss_tracectl_a), + FUNCTION(qdss_tracedata_a), + FUNCTION(blsp_spi6), + FUNCTION(blsp_uart6), + FUNCTION(qdss_tracectl_b), + FUNCTION(blsp_i2c6), + FUNCTION(qdss_traceclk_b), + FUNCTION(mdp_vsync), + FUNCTION(pri_mi2s_mclk_a), + FUNCTION(sec_mi2s_mclk_a), + FUNCTION(cam_mclk), + FUNCTION(cci0_i2c), + FUNCTION(cci1_i2c), + FUNCTION(blsp1_spi), + FUNCTION(blsp3_spi), + FUNCTION(gcc_gp1_clk_a), + FUNCTION(gcc_gp2_clk_a), + FUNCTION(gcc_gp3_clk_a), + FUNCTION(uim_batt), + FUNCTION(sd_write), + FUNCTION(uim1_data), + FUNCTION(uim1_clk), + FUNCTION(uim1_reset), + FUNCTION(uim1_present), + FUNCTION(uim2_data), + FUNCTION(uim2_clk), + FUNCTION(uim2_reset), + FUNCTION(uim2_present), + FUNCTION(ts_xvdd), + FUNCTION(mipi_dsi0), + FUNCTION(us_euro), + FUNCTION(ts_resout), + FUNCTION(ts_sample), + FUNCTION(sec_mi2s_mclk_b), + FUNCTION(pri_mi2s), + FUNCTION(codec_reset), + FUNCTION(cdc_pdm0), + FUNCTION(us_emitter), + FUNCTION(pri_mi2s_mclk_b), + FUNCTION(pri_mi2s_mclk_c), + FUNCTION(lpass_slimbus), + FUNCTION(lpass_slimbus0), + FUNCTION(lpass_slimbus1), + FUNCTION(codec_int1), + FUNCTION(codec_int2), + FUNCTION(wcss_bt), + FUNCTION(sdc3), + FUNCTION(wcss_wlan2), + FUNCTION(wcss_wlan1), + FUNCTION(wcss_wlan0), + FUNCTION(wcss_wlan), + FUNCTION(wcss_fm), + FUNCTION(key_volp), + FUNCTION(key_snapshot), + FUNCTION(key_focus), + FUNCTION(key_home), + FUNCTION(pwr_down), + FUNCTION(dmic0_clk), + FUNCTION(hdmi_int), + FUNCTION(dmic0_data), + FUNCTION(wsa_vi), + FUNCTION(wsa_en), + FUNCTION(blsp_spi8), + FUNCTION(wsa_irq), + FUNCTION(blsp_i2c8), + FUNCTION(pa_indicator), + FUNCTION(modem_tsync), + FUNCTION(ssbi_wtr1), + FUNCTION(gsm1_tx), + FUNCTION(gsm0_tx), + FUNCTION(sdcard_det), + FUNCTION(sec_mi2s), + FUNCTION(ss_switch), +}; + +static const struct msm_pingroup msm8976_groups[] = { + PINGROUP(0, blsp_spi1, blsp_uart1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA), + PINGROUP(4, blsp_spi2, blsp_uart2, NA, NA, NA, qdss_tracectl_b, NA, NA, NA), + PINGROUP(5, blsp_spi2, blsp_uart2, NA, NA, NA, qdss_traceclk_b, NA, NA, NA), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA, NA, NA), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA, NA, NA), + PINGROUP(8, blsp_spi3, NA, NA, NA, NA, qdss_tracedata_a, NA, NA, NA), + PINGROUP(9, blsp_spi3, NA, NA, NA, qdss_tracedata_a, NA, NA, NA, NA), + PINGROUP(10, blsp_spi3, NA, blsp_i2c3, NA, NA, qdss_tracedata_a, NA, NA, NA), + PINGROUP(11, blsp_spi3, NA, blsp_i2c3, NA, NA, NA, NA, NA, NA), + PINGROUP(12, blsp_spi4, NA, gcc_gp2_clk_b, NA, NA, NA, NA, NA, NA), + PINGROUP(13, blsp_spi4, NA, gcc_gp3_clk_b, NA, NA, NA, NA, NA, NA), + PINGROUP(14, blsp_spi4, NA, blsp_i2c4, NA, NA, NA, NA, NA, NA), + PINGROUP(15, blsp_spi4, NA, blsp_i2c4, NA, NA, NA, NA, NA, NA), + PINGROUP(16, blsp_spi8, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(17, blsp_spi8, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, blsp_spi8, NA, blsp_i2c8, NA, NA, NA, NA, NA, NA), + PINGROUP(19, blsp_spi8, NA, blsp_i2c8, NA, NA, NA, NA, NA, NA), + PINGROUP(20, blsp_spi6, blsp_uart6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, blsp_spi6, blsp_uart6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA, NA, NA), + PINGROUP(23, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA, NA, NA), + PINGROUP(24, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(26, cam_mclk, NA, NA, NA, NA, qdss_tracedata_b, NA, NA, NA), + PINGROUP(27, cam_mclk, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA), + PINGROUP(28, cam_mclk, NA, NA, NA, NA, qdss_tracedata_b, NA, NA, NA), + PINGROUP(29, cci0_i2c, NA, NA, NA, NA, qdss_tracedata_b, NA, NA, NA), + PINGROUP(30, cci0_i2c, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA), + PINGROUP(31, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA), + PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA), + PINGROUP(34, NA, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), + PINGROUP(35, NA, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), + PINGROUP(36, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA), + PINGROUP(37, NA, NA, NA, qdss_tracedata_b, NA, NA, NA, NA, NA), + PINGROUP(38, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA), + PINGROUP(39, wcss_bt, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA), + PINGROUP(40, wcss_wlan, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA), + PINGROUP(41, wcss_wlan, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA), + PINGROUP(42, wcss_wlan, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA), + PINGROUP(43, wcss_wlan, sdc3, NA, NA, qdss_tracedata_a, NA, NA, NA, NA), + PINGROUP(44, wcss_wlan, sdc3, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, wcss_fm, NA, qdss_tracectl_a, NA, NA, NA, NA, NA, NA), + PINGROUP(46, wcss_fm, NA, NA, qdss_traceclk_a, NA, NA, NA, NA, NA), + PINGROUP(47, wcss_bt, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), + PINGROUP(48, wcss_bt, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), + PINGROUP(49, NA, NA, gcc_gp1_clk_a, NA, NA, NA, NA, NA, NA), + PINGROUP(50, NA, sd_write, gcc_gp2_clk_a, NA, NA, NA, NA, NA, NA), + PINGROUP(51, uim2_data, gcc_gp3_clk_a, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, uim2_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, uim2_reset, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, uim2_present, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, uim1_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, uim1_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, uim1_reset, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, uim1_present, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, sec_mi2s_mclk_a, pri_mi2s_mclk_b, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), + PINGROUP(63, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, dmic0_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, dmic0_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, NA, ssbi_wtr1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(90, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(91, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(92, NA, NA, pa_indicator, NA, NA, NA, NA, NA, NA), + PINGROUP(93, NA, modem_tsync, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(94, NA, ssbi_wtr1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(95, NA, gsm1_tx, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(98, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(99, gsm0_tx, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(101, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(102, sec_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(103, cci1_i2c, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, cci1_i2c, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, sec_mi2s, gcc_gp1_clk_b, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, wsa_vi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, wsa_vi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(111, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(112, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(113, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(114, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(115, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(116, pri_mi2s_mclk_c, cdc_pdm0, NA, NA, NA, qdss_tracedata_b, NA, NA, NA), + PINGROUP(117, lpass_slimbus, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(118, lpass_slimbus0, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(119, lpass_slimbus1, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(120, cdc_pdm0, NA, NA, NA, NA, NA, NA, qdss_tracedata_a, NA), + PINGROUP(121, cdc_pdm0, NA, NA, NA, NA, NA, NA, qdss_tracedata_a, NA), + PINGROUP(122, pri_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(123, pri_mi2s, m_voc, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(124, pri_mi2s, m_voc, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(125, pri_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(126, pri_mi2s_mclk_a, sec_mi2s_mclk_b, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), + PINGROUP(127, pri_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(128, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA), + PINGROUP(129, qdss_tracedata_b, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(130, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(131, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(132, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(133, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(134, blsp_spi5, blsp_uart5, sec_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(135, blsp_spi5, blsp_uart5, sec_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(136, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA, NA, NA), + PINGROUP(137, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA, NA, NA), + PINGROUP(138, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(139, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(140, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(141, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(142, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(143, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(144, NA, NA, NA, NA, NA, NA, NA, NA, NA), + SDC_QDSD_PINGROUP(sdc1_clk, 0x10a000, 13, 6), + SDC_QDSD_PINGROUP(sdc1_cmd, 0x10a000, 11, 3), + SDC_QDSD_PINGROUP(sdc1_data, 0x10a000, 9, 0), + SDC_QDSD_PINGROUP(sdc1_rclk, 0x10a000, 15, 0), + SDC_QDSD_PINGROUP(sdc2_clk, 0x109000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x109000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x109000, 9, 0), + SDC_QDSD_PINGROUP(qdsd_clk, 0x19c000, 3, 0), + SDC_QDSD_PINGROUP(qdsd_cmd, 0x19c000, 8, 5), + SDC_QDSD_PINGROUP(qdsd_data0, 0x19c000, 13, 10), + SDC_QDSD_PINGROUP(qdsd_data1, 0x19c000, 18, 15), + SDC_QDSD_PINGROUP(qdsd_data2, 0x19c000, 23, 20), + SDC_QDSD_PINGROUP(qdsd_data3, 0x19c000, 28, 25), +}; + +static const struct msm_pinctrl_soc_data msm8976_pinctrl = { + .pins = msm8976_pins, + .npins = ARRAY_SIZE(msm8976_pins), + .functions = msm8976_functions, + .nfunctions = ARRAY_SIZE(msm8976_functions), + .groups = msm8976_groups, + .ngroups = ARRAY_SIZE(msm8976_groups), + .ngpios = 145, +}; + +static int msm8976_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8976_pinctrl); +} + +static const struct of_device_id msm8976_pinctrl_of_match[] = { + { .compatible = "qcom,msm8976-pinctrl", }, + { }, +}; + +static struct platform_driver msm8976_pinctrl_driver = { + .driver = { + .name = "msm8976-pinctrl", + .of_match_table = msm8976_pinctrl_of_match, + }, + .probe = msm8976_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8976_pinctrl_init(void) +{ + return platform_driver_register(&msm8976_pinctrl_driver); +} +arch_initcall(msm8976_pinctrl_init); + +static void __exit msm8976_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8976_pinctrl_driver); +} +module_exit(msm8976_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm msm8976 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8976_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index f1fece5b9c06..387917c517d3 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1121,6 +1121,8 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 }, /* pm8150l has 12 GPIOs with holes on 7 */ { .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 }, + { .compatible = "qcom,pm6150-gpio", .data = (void *) 10 }, + { .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 }, { }, }; diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index c1f7d0799ebe..dca86886b1f9 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -56,7 +56,6 @@ /** * struct pm8xxx_pin_data - dynamic configuration for a pin * @reg: address of the control register - * @irq: IRQ from the PMIC interrupt controller * @power_source: logical selected voltage source, mapping in static data * is used translate to register values * @mode: operating mode for the pin (input/output) @@ -72,7 +71,6 @@ */ struct pm8xxx_pin_data { unsigned reg; - int irq; u8 power_source; u8 mode; bool open_drain; @@ -93,9 +91,6 @@ struct pm8xxx_gpio { struct pinctrl_desc desc; unsigned npins; - - struct fwnode_handle *fwnode; - struct irq_domain *domain; }; static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = { @@ -491,13 +486,16 @@ static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset) { struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + int ret, irq; bool state; - int ret; - if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) { - ret = pin->output_value; - } else if (pin->irq >= 0) { - ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state); + if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) + return pin->output_value; + + irq = chip->to_irq(chip, offset); + if (irq >= 0) { + ret = irq_get_irqchip_state(irq, IRQCHIP_STATE_LINE_LEVEL, + &state); if (!ret) ret = !!state; } else @@ -535,37 +533,6 @@ static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip, } -static int pm8xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); - struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; - struct irq_fwspec fwspec; - int ret; - - fwspec.fwnode = pctrl->fwnode; - fwspec.param_count = 2; - fwspec.param[0] = offset + PM8XXX_GPIO_PHYSICAL_OFFSET; - fwspec.param[1] = IRQ_TYPE_EDGE_RISING; - - ret = irq_create_fwspec_mapping(&fwspec); - - /* - * Cache the IRQ since pm8xxx_gpio_get() needs this to get determine the - * line level. - */ - pin->irq = ret; - - return ret; -} - -static void pm8xxx_gpio_free(struct gpio_chip *chip, unsigned int offset) -{ - struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); - struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; - - pin->irq = -1; -} - #ifdef CONFIG_DEBUG_FS #include <linux/seq_file.h> @@ -624,13 +591,11 @@ static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) #endif static const struct gpio_chip pm8xxx_gpio_template = { - .free = pm8xxx_gpio_free, .direction_input = pm8xxx_gpio_direction_input, .direction_output = pm8xxx_gpio_direction_output, .get = pm8xxx_gpio_get, .set = pm8xxx_gpio_set, .of_xlate = pm8xxx_gpio_of_xlate, - .to_irq = pm8xxx_gpio_to_irq, .dbg_show = pm8xxx_gpio_dbg_show, .owner = THIS_MODULE, }; @@ -712,43 +677,24 @@ static int pm8xxx_domain_translate(struct irq_domain *domain, return 0; } -static int pm8xxx_domain_alloc(struct irq_domain *domain, unsigned int virq, - unsigned int nr_irqs, void *data) +static unsigned int pm8xxx_child_offset_to_irq(struct gpio_chip *chip, + unsigned int offset) { - struct pm8xxx_gpio *pctrl = container_of(domain->host_data, - struct pm8xxx_gpio, chip); - struct irq_fwspec *fwspec = data; - struct irq_fwspec parent_fwspec; - irq_hw_number_t hwirq; - unsigned int type; - int ret, i; - - ret = pm8xxx_domain_translate(domain, fwspec, &hwirq, &type); - if (ret) - return ret; - - for (i = 0; i < nr_irqs; i++) - irq_domain_set_info(domain, virq + i, hwirq + i, - &pm8xxx_irq_chip, pctrl, handle_level_irq, - NULL, NULL); + return offset + PM8XXX_GPIO_PHYSICAL_OFFSET; +} - parent_fwspec.fwnode = domain->parent->fwnode; - parent_fwspec.param_count = 2; - parent_fwspec.param[0] = hwirq + 0xc0; - parent_fwspec.param[1] = fwspec->param[1]; +static int pm8xxx_child_to_parent_hwirq(struct gpio_chip *chip, + unsigned int child_hwirq, + unsigned int child_type, + unsigned int *parent_hwirq, + unsigned int *parent_type) +{ + *parent_hwirq = child_hwirq + 0xc0; + *parent_type = child_type; - return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, - &parent_fwspec); + return 0; } -static const struct irq_domain_ops pm8xxx_domain_ops = { - .activate = gpiochip_irq_domain_activate, - .alloc = pm8xxx_domain_alloc, - .deactivate = gpiochip_irq_domain_deactivate, - .free = irq_domain_free_irqs_common, - .translate = pm8xxx_domain_translate, -}; - static const struct of_device_id pm8xxx_gpio_of_match[] = { { .compatible = "qcom,pm8018-gpio", .data = (void *) 6 }, { .compatible = "qcom,pm8038-gpio", .data = (void *) 12 }, @@ -765,6 +711,7 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev) struct irq_domain *parent_domain; struct device_node *parent_node; struct pinctrl_pin_desc *pins; + struct gpio_irq_chip *girq; struct pm8xxx_gpio *pctrl; int ret, i; @@ -800,7 +747,6 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev) for (i = 0; i < pctrl->desc.npins; i++) { pin_data[i].reg = SSBI_REG_ADDR_GPIO(i); - pin_data[i].irq = -1; ret = pm8xxx_pin_populate(pctrl, &pin_data[i]); if (ret) @@ -841,19 +787,21 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev) if (!parent_domain) return -ENXIO; - pctrl->fwnode = of_node_to_fwnode(pctrl->dev->of_node); - pctrl->domain = irq_domain_create_hierarchy(parent_domain, 0, - pctrl->chip.ngpio, - pctrl->fwnode, - &pm8xxx_domain_ops, - &pctrl->chip); - if (!pctrl->domain) - return -ENODEV; + girq = &pctrl->chip.irq; + girq->chip = &pm8xxx_irq_chip; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + girq->fwnode = of_node_to_fwnode(pctrl->dev->of_node); + girq->parent_domain = parent_domain; + girq->child_to_parent_hwirq = pm8xxx_child_to_parent_hwirq; + girq->populate_parent_fwspec = gpiochip_populate_parent_fwspec_fourcell; + girq->child_offset_to_irq = pm8xxx_child_offset_to_irq; + girq->child_irq_domain_ops.translate = pm8xxx_domain_translate; ret = gpiochip_add_data(&pctrl->chip, pctrl); if (ret) { dev_err(&pdev->dev, "failed register gpiochip\n"); - goto err_chip_add_data; + return ret; } /* @@ -883,8 +831,6 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev) unregister_gpiochip: gpiochip_remove(&pctrl->chip); -err_chip_add_data: - irq_domain_remove(pctrl->domain); return ret; } @@ -894,7 +840,6 @@ static int pm8xxx_gpio_remove(struct platform_device *pdev) struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev); gpiochip_remove(&pctrl->chip); - irq_domain_remove(pctrl->domain); return 0; } diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c index 924080362bf7..b1a9611f46b3 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -5996,6 +5996,7 @@ static int atlas7_gpio_probe(struct platform_device *pdev) struct gpio_chip *chip; u32 nbank; int ret, idx; + struct gpio_irq_chip *girq; ret = of_property_read_u32(np, "gpio-banks", &nbank); if (ret) { @@ -6048,24 +6049,15 @@ static int atlas7_gpio_probe(struct platform_device *pdev) chip->of_gpio_n_cells = 2; chip->parent = &pdev->dev; - /* Add gpio chip to system */ - ret = gpiochip_add_data(chip, a7gc); - if (ret) { - dev_err(&pdev->dev, - "%pOF: error in probe function with status %d\n", - np, ret); - goto failed; - } - - /* Add gpio chip to irq subsystem */ - ret = gpiochip_irqchip_add(chip, &atlas7_gpio_irq_chip, - 0, handle_level_irq, IRQ_TYPE_NONE); - if (ret) { - dev_err(&pdev->dev, - "could not connect irqchip to gpiochip\n"); - goto failed; - } - + girq = &chip->irq; + girq->chip = &atlas7_gpio_irq_chip; + girq->parent_handler = atlas7_gpio_handle_irq; + girq->num_parents = nbank; + girq->parents = devm_kcalloc(&pdev->dev, nbank, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; for (idx = 0; idx < nbank; idx++) { struct atlas7_gpio_bank *bank; @@ -6084,9 +6076,18 @@ static int atlas7_gpio_probe(struct platform_device *pdev) goto failed; } bank->irq = ret; + girq->parents[idx] = ret; + } + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; - gpiochip_set_chained_irqchip(chip, &atlas7_gpio_irq_chip, - bank->irq, atlas7_gpio_handle_irq); + /* Add gpio chip to system */ + ret = gpiochip_add_data(chip, a7gc); + if (ret) { + dev_err(&pdev->dev, + "%pOF: error in probe function with status %d\n", + np, ret); + goto failed; } platform_set_drvdata(pdev, a7gc); diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 780c31bb4009..1ebcb957c654 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -785,6 +785,7 @@ static int sirfsoc_gpio_probe(struct device_node *np) struct sirfsoc_gpio_bank *bank; void __iomem *regs; struct platform_device *pdev; + struct gpio_irq_chip *girq; u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS]; @@ -816,36 +817,33 @@ static int sirfsoc_gpio_probe(struct device_node *np) sgpio->chip.gc.parent = &pdev->dev; sgpio->chip.regs = regs; - err = gpiochip_add_data(&sgpio->chip.gc, sgpio); - if (err) { - dev_err(&pdev->dev, "%pOF: error in probe function with status %d\n", - np, err); - goto out; - } - - err = gpiochip_irqchip_add(&sgpio->chip.gc, - &sirfsoc_irq_chip, - 0, handle_level_irq, - IRQ_TYPE_NONE); - if (err) { - dev_err(&pdev->dev, - "could not connect irqchip to gpiochip\n"); - goto out_banks; - } - + girq = &sgpio->chip.gc.irq; + girq->chip = &sirfsoc_irq_chip; + girq->parent_handler = sirfsoc_gpio_handle_irq; + girq->num_parents = SIRFSOC_GPIO_NO_OF_BANKS; + girq->parents = devm_kcalloc(&pdev->dev, SIRFSOC_GPIO_NO_OF_BANKS, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { bank = &sgpio->sgpio_bank[i]; spin_lock_init(&bank->lock); bank->parent_irq = platform_get_irq(pdev, i); if (bank->parent_irq < 0) { err = bank->parent_irq; - goto out_banks; + goto out; } + girq->parents[i] = bank->parent_irq; + } + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; - gpiochip_set_chained_irqchip(&sgpio->chip.gc, - &sirfsoc_irq_chip, - bank->parent_irq, - sirfsoc_gpio_handle_irq); + err = gpiochip_add_data(&sgpio->chip.gc, sgpio); + if (err) { + dev_err(&pdev->dev, "%pOF: error in probe function with status %d\n", + np, err); + goto out; } err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev), @@ -867,7 +865,6 @@ static int sirfsoc_gpio_probe(struct device_node *np) return 0; out_no_range: -out_banks: gpiochip_remove(&sgpio->chip.gc); out: iounmap(regs); diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c index 9d906474f3e4..c4c9a2971445 100644 --- a/drivers/pinctrl/spear/pinctrl-plgpio.c +++ b/drivers/pinctrl/spear/pinctrl-plgpio.c @@ -569,40 +569,35 @@ static int plgpio_probe(struct platform_device *pdev) } } - ret = gpiochip_add_data(&plgpio->chip, plgpio); - if (ret) { - dev_err(&pdev->dev, "unable to add gpio chip\n"); - goto unprepare_clk; - } - irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_info(&pdev->dev, "PLGPIO registered without IRQs\n"); - return 0; + if (irq > 0) { + struct gpio_irq_chip *girq; + + girq = &plgpio->chip.irq; + girq->chip = &plgpio_irqchip; + girq->parent_handler = plgpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&pdev->dev, 1, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_simple_irq; + dev_info(&pdev->dev, "PLGPIO registering with IRQs\n"); + } else { + dev_info(&pdev->dev, "PLGPIO registering without IRQs\n"); } - ret = gpiochip_irqchip_add(&plgpio->chip, - &plgpio_irqchip, - 0, - handle_simple_irq, - IRQ_TYPE_NONE); + ret = gpiochip_add_data(&plgpio->chip, plgpio); if (ret) { - dev_err(&pdev->dev, "failed to add irqchip to gpiochip\n"); - goto remove_gpiochip; + dev_err(&pdev->dev, "unable to add gpio chip\n"); + goto unprepare_clk; } - gpiochip_set_chained_irqchip(&plgpio->chip, - &plgpio_irqchip, - irq, - plgpio_irq_handler); - - dev_info(&pdev->dev, "PLGPIO registered with IRQs\n"); - return 0; -remove_gpiochip: - dev_info(&pdev->dev, "Remove gpiochip\n"); - gpiochip_remove(&plgpio->chip); unprepare_clk: if (!IS_ERR(plgpio->clk)) clk_unprepare(plgpio->clk); diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c index 7b95bf5a82a9..157712ab05a8 100644 --- a/drivers/pinctrl/sprd/pinctrl-sprd.c +++ b/drivers/pinctrl/sprd/pinctrl-sprd.c @@ -41,7 +41,8 @@ #define PUBCP_SLEEP_MODE BIT(14) #define TGLDSP_SLEEP_MODE BIT(15) #define AGDSP_SLEEP_MODE BIT(16) -#define SLEEP_MODE_MASK GENMASK(3, 0) +#define CM4_SLEEP_MODE BIT(17) +#define SLEEP_MODE_MASK GENMASK(5, 0) #define SLEEP_MODE_SHIFT 13 #define SLEEP_INPUT BIT(1) @@ -81,6 +82,7 @@ enum pin_sleep_mode { PUBCP_SLEEP = BIT(1), TGLDSP_SLEEP = BIT(2), AGDSP_SLEEP = BIT(3), + CM4_SLEEP = BIT(4), }; enum pin_func_sel { @@ -484,6 +486,13 @@ static int sprd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id, SLEEP_PULL_UP_MASK) << 16; arg |= (reg >> PULL_UP_SHIFT) & PULL_UP_MASK; break; + case PIN_CONFIG_BIAS_DISABLE: + if ((reg & (SLEEP_PULL_DOWN | SLEEP_PULL_UP)) || + (reg & (PULL_DOWN | PULL_UP_4_7K | PULL_UP_20K))) + return -EINVAL; + + arg = 1; + break; case PIN_CONFIG_SLEEP_HARDWARE_STATE: arg = 0; break; @@ -609,6 +618,8 @@ static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id, val |= TGLDSP_SLEEP_MODE; if (arg & AGDSP_SLEEP) val |= AGDSP_SLEEP_MODE; + if (arg & CM4_SLEEP) + val |= CM4_SLEEP_MODE; mask = SLEEP_MODE_MASK; shift = SLEEP_MODE_SHIFT; @@ -674,6 +685,16 @@ static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id, shift = PULL_UP_SHIFT; } break; + case PIN_CONFIG_BIAS_DISABLE: + if (is_sleep_config == true) { + val = shift = 0; + mask = SLEEP_PULL_DOWN | SLEEP_PULL_UP; + } else { + val = shift = 0; + mask = PULL_DOWN | PULL_UP_20K | + PULL_UP_4_7K; + } + break; case PIN_CONFIG_SLEEP_HARDWARE_STATE: continue; default: diff --git a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c index 95002e3ecaff..f2fa1f76ebb7 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c @@ -885,6 +885,12 @@ int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev) mutex_init(&padctl->lock); padctl->dev = &pdev->dev; + /* + * Note that we can't replace this by of_device_get_match_data() + * because we need the separate matching table for this legacy code on + * Tegra124. of_device_get_match_data() would attempt to use the table + * from the updated driver and fail. + */ match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node); padctl->soc = match->data; diff --git a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c index e5e7f1f22813..b522ca010332 100644 --- a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c +++ b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c @@ -496,7 +496,7 @@ static int ti_iodelay_dt_node_to_map(struct pinctrl_dev *pctldev, return -EINVAL; rows = pinctrl_count_index_with_args(np, name); - if (rows == -EINVAL) + if (rows < 0) return rows; *map = devm_kzalloc(iod->dev, sizeof(**map), GFP_KERNEL); |