diff options
Diffstat (limited to 'drivers/pinctrl')
29 files changed, 7715 insertions, 48 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 6ca1a6fc9756..815095326e2d 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -208,10 +208,12 @@ config PINCTRL_OXNAS config PINCTRL_ROCKCHIP bool + depends on OF select PINMUX select GENERIC_PINCONF select GENERIC_IRQ_CHIP select MFD_SYSCON + select OF_GPIO config PINCTRL_SINGLE tristate "One-register-per-pin type device tree based pinctrl driver" @@ -397,6 +399,7 @@ source "drivers/pinctrl/mediatek/Kconfig" source "drivers/pinctrl/zte/Kconfig" source "drivers/pinctrl/meson/Kconfig" source "drivers/pinctrl/cirrus/Kconfig" +source "drivers/pinctrl/visconti/Kconfig" config PINCTRL_XWAY bool diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 113be648658f..f53933b2ff02 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -71,3 +71,4 @@ obj-$(CONFIG_ARCH_VT8500) += vt8500/ obj-y += mediatek/ obj-$(CONFIG_PINCTRL_ZX) += zte/ obj-y += cirrus/ +obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/ diff --git a/drivers/pinctrl/actions/Kconfig b/drivers/pinctrl/actions/Kconfig index 966f1c2c89d6..a1d16e8280e5 100644 --- a/drivers/pinctrl/actions/Kconfig +++ b/drivers/pinctrl/actions/Kconfig @@ -10,6 +10,12 @@ config PINCTRL_OWL help Say Y here to enable Actions Semi OWL pinctrl driver +config PINCTRL_S500 + bool "Actions Semi S500 pinctrl driver" + depends on PINCTRL_OWL + help + Say Y here to enable Actions Semi S500 pinctrl driver + config PINCTRL_S700 bool "Actions Semi S700 pinctrl driver" depends on PINCTRL_OWL diff --git a/drivers/pinctrl/actions/Makefile b/drivers/pinctrl/actions/Makefile index 61aa9107a43a..b9e2c527c9d3 100644 --- a/drivers/pinctrl/actions/Makefile +++ b/drivers/pinctrl/actions/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_PINCTRL_OWL) += pinctrl-owl.o +obj-$(CONFIG_PINCTRL_S500) += pinctrl-s500.o obj-$(CONFIG_PINCTRL_S700) += pinctrl-s700.o obj-$(CONFIG_PINCTRL_S900) += pinctrl-s900.o diff --git a/drivers/pinctrl/actions/pinctrl-owl.c b/drivers/pinctrl/actions/pinctrl-owl.c index 7efdfb4f3e9b..903a4baf3846 100644 --- a/drivers/pinctrl/actions/pinctrl-owl.c +++ b/drivers/pinctrl/actions/pinctrl-owl.c @@ -125,7 +125,7 @@ static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev, seq_printf(s, "%s", dev_name(pctrl->dev)); } -static struct pinctrl_ops owl_pinctrl_ops = { +static const struct pinctrl_ops owl_pinctrl_ops = { .get_groups_count = owl_get_groups_count, .get_group_name = owl_get_group_name, .get_group_pins = owl_get_group_pins, @@ -212,7 +212,7 @@ static int owl_set_mux(struct pinctrl_dev *pctrldev, return 0; } -static struct pinmux_ops owl_pinmux_ops = { +static const struct pinmux_ops owl_pinmux_ops = { .get_functions_count = owl_get_funcs_count, .get_function_name = owl_get_func_name, .get_function_groups = owl_get_func_groups, diff --git a/drivers/pinctrl/actions/pinctrl-s500.c b/drivers/pinctrl/actions/pinctrl-s500.c new file mode 100644 index 000000000000..38e30914af6e --- /dev/null +++ b/drivers/pinctrl/actions/pinctrl-s500.c @@ -0,0 +1,1727 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Actions Semi S500 SoC Pinctrl driver + * + * Copyright (c) 2014 Actions Semi Inc. + * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com> + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include "pinctrl-owl.h" + +/* Pinctrl registers offset */ +#define MFCTL0 (0x0040) +#define MFCTL1 (0x0044) +#define MFCTL2 (0x0048) +#define MFCTL3 (0x004C) +#define PAD_PULLCTL0 (0x0060) +#define PAD_PULLCTL1 (0x0064) +#define PAD_PULLCTL2 (0x0068) +#define PAD_ST0 (0x006C) +#define PAD_ST1 (0x0070) +#define PAD_CTL (0x0074) +#define PAD_DRV0 (0x0080) +#define PAD_DRV1 (0x0084) +#define PAD_DRV2 (0x0088) + +#define _GPIOA(offset) (offset) +#define _GPIOB(offset) (32 + (offset)) +#define _GPIOC(offset) (64 + (offset)) +#define _GPIOD(offset) (96 + (offset)) +#define _GPIOE(offset) (128 + (offset)) + +#define NUM_GPIOS (_GPIOE(3) + 1) +#define _PIN(offset) (NUM_GPIOS + (offset)) + +#define DNAND_DQS _GPIOA(12) +#define DNAND_DQSN _GPIOA(13) +#define ETH_TXD0 _GPIOA(14) +#define ETH_TXD1 _GPIOA(15) +#define ETH_TXEN _GPIOA(16) +#define ETH_RXER _GPIOA(17) +#define ETH_CRS_DV _GPIOA(18) +#define ETH_RXD1 _GPIOA(19) +#define ETH_RXD0 _GPIOA(20) +#define ETH_REF_CLK _GPIOA(21) +#define ETH_MDC _GPIOA(22) +#define ETH_MDIO _GPIOA(23) +#define SIRQ0 _GPIOA(24) +#define SIRQ1 _GPIOA(25) +#define SIRQ2 _GPIOA(26) +#define I2S_D0 _GPIOA(27) +#define I2S_BCLK0 _GPIOA(28) +#define I2S_LRCLK0 _GPIOA(29) +#define I2S_MCLK0 _GPIOA(30) +#define I2S_D1 _GPIOA(31) + +#define I2S_BCLK1 _GPIOB(0) +#define I2S_LRCLK1 _GPIOB(1) +#define I2S_MCLK1 _GPIOB(2) +#define KS_IN0 _GPIOB(3) +#define KS_IN1 _GPIOB(4) +#define KS_IN2 _GPIOB(5) +#define KS_IN3 _GPIOB(6) +#define KS_OUT0 _GPIOB(7) +#define KS_OUT1 _GPIOB(8) +#define KS_OUT2 _GPIOB(9) +#define LVDS_OEP _GPIOB(10) +#define LVDS_OEN _GPIOB(11) +#define LVDS_ODP _GPIOB(12) +#define LVDS_ODN _GPIOB(13) +#define LVDS_OCP _GPIOB(14) +#define LVDS_OCN _GPIOB(15) +#define LVDS_OBP _GPIOB(16) +#define LVDS_OBN _GPIOB(17) +#define LVDS_OAP _GPIOB(18) +#define LVDS_OAN _GPIOB(19) +#define LVDS_EEP _GPIOB(20) +#define LVDS_EEN _GPIOB(21) +#define LVDS_EDP _GPIOB(22) +#define LVDS_EDN _GPIOB(23) +#define LVDS_ECP _GPIOB(24) +#define LVDS_ECN _GPIOB(25) +#define LVDS_EBP _GPIOB(26) +#define LVDS_EBN _GPIOB(27) +#define LVDS_EAP _GPIOB(28) +#define LVDS_EAN _GPIOB(29) +#define LCD0_D18 _GPIOB(30) +#define LCD0_D17 _GPIOB(31) + +#define DSI_DP3 _GPIOC(0) +#define DSI_DN3 _GPIOC(1) +#define DSI_DP1 _GPIOC(2) +#define DSI_DN1 _GPIOC(3) +#define DSI_CP _GPIOC(4) +#define DSI_CN _GPIOC(5) +#define DSI_DP0 _GPIOC(6) +#define DSI_DN0 _GPIOC(7) +#define DSI_DP2 _GPIOC(8) +#define DSI_DN2 _GPIOC(9) +#define SD0_D0 _GPIOC(10) +#define SD0_D1 _GPIOC(11) +#define SD0_D2 _GPIOC(12) +#define SD0_D3 _GPIOC(13) +#define SD1_D0 _GPIOC(14) /* SD0_D4 */ +#define SD1_D1 _GPIOC(15) /* SD0_D5 */ +#define SD1_D2 _GPIOC(16) /* SD0_D6 */ +#define SD1_D3 _GPIOC(17) /* SD0_D7 */ +#define SD0_CMD _GPIOC(18) +#define SD0_CLK _GPIOC(19) +#define SD1_CMD _GPIOC(20) +#define SD1_CLK _GPIOC(21) +#define SPI0_SCLK _GPIOC(22) +#define SPI0_SS _GPIOC(23) +#define SPI0_MISO _GPIOC(24) +#define SPI0_MOSI _GPIOC(25) +#define UART0_RX _GPIOC(26) +#define UART0_TX _GPIOC(27) +#define I2C0_SCLK _GPIOC(28) +#define I2C0_SDATA _GPIOC(29) +#define SENSOR0_PCLK _GPIOC(31) + +#define SENSOR0_CKOUT _GPIOD(10) +#define DNAND_ALE _GPIOD(12) +#define DNAND_CLE _GPIOD(13) +#define DNAND_CEB0 _GPIOD(14) +#define DNAND_CEB1 _GPIOD(15) +#define DNAND_CEB2 _GPIOD(16) +#define DNAND_CEB3 _GPIOD(17) +#define UART2_RX _GPIOD(18) +#define UART2_TX _GPIOD(19) +#define UART2_RTSB _GPIOD(20) +#define UART2_CTSB _GPIOD(21) +#define UART3_RX _GPIOD(22) +#define UART3_TX _GPIOD(23) +#define UART3_RTSB _GPIOD(24) +#define UART3_CTSB _GPIOD(25) +#define PCM1_IN _GPIOD(28) +#define PCM1_CLK _GPIOD(29) +#define PCM1_SYNC _GPIOD(30) +#define PCM1_OUT _GPIOD(31) + +#define I2C1_SCLK _GPIOE(0) +#define I2C1_SDATA _GPIOE(1) +#define I2C2_SCLK _GPIOE(2) +#define I2C2_SDATA _GPIOE(3) + +#define CSI_DN0 _PIN(0) +#define CSI_DP0 _PIN(1) +#define CSI_DN1 _PIN(2) +#define CSI_DP1 _PIN(3) +#define CSI_CN _PIN(4) +#define CSI_CP _PIN(5) +#define CSI_DN2 _PIN(6) +#define CSI_DP2 _PIN(7) +#define CSI_DN3 _PIN(8) +#define CSI_DP3 _PIN(9) + +#define DNAND_D0 _PIN(10) +#define DNAND_D1 _PIN(11) +#define DNAND_D2 _PIN(12) +#define DNAND_D3 _PIN(13) +#define DNAND_D4 _PIN(14) +#define DNAND_D5 _PIN(15) +#define DNAND_D6 _PIN(16) +#define DNAND_D7 _PIN(17) +#define DNAND_WRB _PIN(18) +#define DNAND_RDB _PIN(19) +#define DNAND_RDBN _PIN(20) +#define DNAND_RB _PIN(21) + +#define PORB _PIN(22) +#define CLKO_25M _PIN(23) +#define BSEL _PIN(24) +#define PKG0 _PIN(25) +#define PKG1 _PIN(26) +#define PKG2 _PIN(27) +#define PKG3 _PIN(28) + +#define _FIRSTPAD _GPIOA(0) +#define _LASTPAD PKG3 +#define NUM_PADS (_PIN(28) + 1) + +static const struct pinctrl_pin_desc s500_pads[] = { + PINCTRL_PIN(DNAND_DQS, "dnand_dqs"), + PINCTRL_PIN(DNAND_DQSN, "dnand_dqsn"), + PINCTRL_PIN(ETH_TXD0, "eth_txd0"), + PINCTRL_PIN(ETH_TXD1, "eth_txd1"), + PINCTRL_PIN(ETH_TXEN, "eth_txen"), + PINCTRL_PIN(ETH_RXER, "eth_rxer"), + PINCTRL_PIN(ETH_CRS_DV, "eth_crs_dv"), + PINCTRL_PIN(ETH_RXD1, "eth_rxd1"), + PINCTRL_PIN(ETH_RXD0, "eth_rxd0"), + PINCTRL_PIN(ETH_REF_CLK, "eth_ref_clk"), + PINCTRL_PIN(ETH_MDC, "eth_mdc"), + PINCTRL_PIN(ETH_MDIO, "eth_mdio"), + PINCTRL_PIN(SIRQ0, "sirq0"), + PINCTRL_PIN(SIRQ1, "sirq1"), + PINCTRL_PIN(SIRQ2, "sirq2"), + PINCTRL_PIN(I2S_D0, "i2s_d0"), + PINCTRL_PIN(I2S_BCLK0, "i2s_bclk0"), + PINCTRL_PIN(I2S_LRCLK0, "i2s_lrclk0"), + PINCTRL_PIN(I2S_MCLK0, "i2s_mclk0"), + PINCTRL_PIN(I2S_D1, "i2s_d1"), + PINCTRL_PIN(I2S_BCLK1, "i2s_bclk1"), + PINCTRL_PIN(I2S_LRCLK1, "i2s_lrclk1"), + PINCTRL_PIN(I2S_MCLK1, "i2s_mclk1"), + PINCTRL_PIN(KS_IN0, "ks_in0"), + PINCTRL_PIN(KS_IN1, "ks_in1"), + PINCTRL_PIN(KS_IN2, "ks_in2"), + PINCTRL_PIN(KS_IN3, "ks_in3"), + PINCTRL_PIN(KS_OUT0, "ks_out0"), + PINCTRL_PIN(KS_OUT1, "ks_out1"), + PINCTRL_PIN(KS_OUT2, "ks_out2"), + PINCTRL_PIN(LVDS_OEP, "lvds_oep"), + PINCTRL_PIN(LVDS_OEN, "lvds_oen"), + PINCTRL_PIN(LVDS_ODP, "lvds_odp"), + PINCTRL_PIN(LVDS_ODN, "lvds_odn"), + PINCTRL_PIN(LVDS_OCP, "lvds_ocp"), + PINCTRL_PIN(LVDS_OCN, "lvds_ocn"), + PINCTRL_PIN(LVDS_OBP, "lvds_obp"), + PINCTRL_PIN(LVDS_OBN, "lvds_obn"), + PINCTRL_PIN(LVDS_OAP, "lvds_oap"), + PINCTRL_PIN(LVDS_OAN, "lvds_oan"), + PINCTRL_PIN(LVDS_EEP, "lvds_eep"), + PINCTRL_PIN(LVDS_EEN, "lvds_een"), + PINCTRL_PIN(LVDS_EDP, "lvds_edp"), + PINCTRL_PIN(LVDS_EDN, "lvds_edn"), + PINCTRL_PIN(LVDS_ECP, "lvds_ecp"), + PINCTRL_PIN(LVDS_ECN, "lvds_ecn"), + PINCTRL_PIN(LVDS_EBP, "lvds_ebp"), + PINCTRL_PIN(LVDS_EBN, "lvds_ebn"), + PINCTRL_PIN(LVDS_EAP, "lvds_eap"), + PINCTRL_PIN(LVDS_EAN, "lvds_ean"), + PINCTRL_PIN(LCD0_D18, "lcd0_d18"), + PINCTRL_PIN(LCD0_D17, "lcd0_d17"), + PINCTRL_PIN(DSI_DP3, "dsi_dp3"), + PINCTRL_PIN(DSI_DN3, "dsi_dn3"), + PINCTRL_PIN(DSI_DP1, "dsi_dp1"), + PINCTRL_PIN(DSI_DN1, "dsi_dn1"), + PINCTRL_PIN(DSI_CP, "dsi_cp"), + PINCTRL_PIN(DSI_CN, "dsi_cn"), + PINCTRL_PIN(DSI_DP0, "dsi_dp0"), + PINCTRL_PIN(DSI_DN0, "dsi_dn0"), + PINCTRL_PIN(DSI_DP2, "dsi_dp2"), + PINCTRL_PIN(DSI_DN2, "dsi_dn2"), + PINCTRL_PIN(SD0_D0, "sd0_d0"), + PINCTRL_PIN(SD0_D1, "sd0_d1"), + PINCTRL_PIN(SD0_D2, "sd0_d2"), + PINCTRL_PIN(SD0_D3, "sd0_d3"), + PINCTRL_PIN(SD1_D0, "sd1_d0"), + PINCTRL_PIN(SD1_D1, "sd1_d1"), + PINCTRL_PIN(SD1_D2, "sd1_d2"), + PINCTRL_PIN(SD1_D3, "sd1_d3"), + PINCTRL_PIN(SD0_CMD, "sd0_cmd"), + PINCTRL_PIN(SD0_CLK, "sd0_clk"), + PINCTRL_PIN(SD1_CMD, "sd1_cmd"), + PINCTRL_PIN(SD1_CLK, "sd1_clk"), + PINCTRL_PIN(SPI0_SCLK, "spi0_sclk"), + PINCTRL_PIN(SPI0_SS, "spi0_ss"), + PINCTRL_PIN(SPI0_MISO, "spi0_miso"), + PINCTRL_PIN(SPI0_MOSI, "spi0_mosi"), + PINCTRL_PIN(UART0_RX, "uart0_rx"), + PINCTRL_PIN(UART0_TX, "uart0_tx"), + PINCTRL_PIN(I2C0_SCLK, "i2c0_sclk"), + PINCTRL_PIN(I2C0_SDATA, "i2c0_sdata"), + PINCTRL_PIN(SENSOR0_PCLK, "sensor0_pclk"), + PINCTRL_PIN(SENSOR0_CKOUT, "sensor0_ckout"), + PINCTRL_PIN(DNAND_ALE, "dnand_ale"), + PINCTRL_PIN(DNAND_CLE, "dnand_cle"), + PINCTRL_PIN(DNAND_CEB0, "dnand_ceb0"), + PINCTRL_PIN(DNAND_CEB1, "dnand_ceb1"), + PINCTRL_PIN(DNAND_CEB2, "dnand_ceb2"), + PINCTRL_PIN(DNAND_CEB3, "dnand_ceb3"), + PINCTRL_PIN(UART2_RX, "uart2_rx"), + PINCTRL_PIN(UART2_TX, "uart2_tx"), + PINCTRL_PIN(UART2_RTSB, "uart2_rtsb"), + PINCTRL_PIN(UART2_CTSB, "uart2_ctsb"), + PINCTRL_PIN(UART3_RX, "uart3_rx"), + PINCTRL_PIN(UART3_TX, "uart3_tx"), + PINCTRL_PIN(UART3_RTSB, "uart3_rtsb"), + PINCTRL_PIN(UART3_CTSB, "uart3_ctsb"), + PINCTRL_PIN(PCM1_IN, "pcm1_in"), + PINCTRL_PIN(PCM1_CLK, "pcm1_clk"), + PINCTRL_PIN(PCM1_SYNC, "pcm1_sync"), + PINCTRL_PIN(PCM1_OUT, "pcm1_out"), + PINCTRL_PIN(I2C1_SCLK, "i2c1_sclk"), + PINCTRL_PIN(I2C1_SDATA, "i2c1_sdata"), + PINCTRL_PIN(I2C2_SCLK, "i2c2_sclk"), + PINCTRL_PIN(I2C2_SDATA, "i2c2_sdata"), + PINCTRL_PIN(CSI_DN0, "csi_dn0"), + PINCTRL_PIN(CSI_DP0, "csi_dp0"), + PINCTRL_PIN(CSI_DN1, "csi_dn1"), + PINCTRL_PIN(CSI_DP1, "csi_dp1"), + PINCTRL_PIN(CSI_DN2, "csi_dn2"), + PINCTRL_PIN(CSI_DP2, "csi_dp2"), + PINCTRL_PIN(CSI_DN3, "csi_dn3"), + PINCTRL_PIN(CSI_DP3, "csi_dp3"), + PINCTRL_PIN(CSI_CN, "csi_cn"), + PINCTRL_PIN(CSI_CP, "csi_cp"), + PINCTRL_PIN(DNAND_D0, "dnand_d0"), + PINCTRL_PIN(DNAND_D1, "dnand_d1"), + PINCTRL_PIN(DNAND_D2, "dnand_d2"), + PINCTRL_PIN(DNAND_D3, "dnand_d3"), + PINCTRL_PIN(DNAND_D4, "dnand_d4"), + PINCTRL_PIN(DNAND_D5, "dnand_d5"), + PINCTRL_PIN(DNAND_D6, "dnand_d6"), + PINCTRL_PIN(DNAND_D7, "dnand_d7"), + PINCTRL_PIN(DNAND_RB, "dnand_rb"), + PINCTRL_PIN(DNAND_RDB, "dnand_rdb"), + PINCTRL_PIN(DNAND_RDBN, "dnand_rdbn"), + PINCTRL_PIN(DNAND_WRB, "dnand_wrb"), + PINCTRL_PIN(PORB, "porb"), + PINCTRL_PIN(CLKO_25M, "clko_25m"), + PINCTRL_PIN(BSEL, "bsel"), + PINCTRL_PIN(PKG0, "pkg0"), + PINCTRL_PIN(PKG1, "pkg1"), + PINCTRL_PIN(PKG2, "pkg2"), + PINCTRL_PIN(PKG3, "pkg3"), +}; + +enum s500_pinmux_functions { + S500_MUX_NOR, + S500_MUX_ETH_RMII, + S500_MUX_ETH_SMII, + S500_MUX_SPI0, + S500_MUX_SPI1, + S500_MUX_SPI2, + S500_MUX_SPI3, + S500_MUX_SENS0, + S500_MUX_SENS1, + S500_MUX_UART0, + S500_MUX_UART1, + S500_MUX_UART2, + S500_MUX_UART3, + S500_MUX_UART4, + S500_MUX_UART5, + S500_MUX_UART6, + S500_MUX_I2S0, + S500_MUX_I2S1, + S500_MUX_PCM1, + S500_MUX_PCM0, + S500_MUX_KS, + S500_MUX_JTAG, + S500_MUX_PWM0, + S500_MUX_PWM1, + S500_MUX_PWM2, + S500_MUX_PWM3, + S500_MUX_PWM4, + S500_MUX_PWM5, + S500_MUX_P0, + S500_MUX_SD0, + S500_MUX_SD1, + S500_MUX_SD2, + S500_MUX_I2C0, + S500_MUX_I2C1, + /*S500_MUX_I2C2,*/ + S500_MUX_I2C3, + S500_MUX_DSI, + S500_MUX_LVDS, + S500_MUX_USB30, + S500_MUX_CLKO_25M, + S500_MUX_MIPI_CSI, + S500_MUX_NAND, + S500_MUX_SPDIF, + /*S500_MUX_SIRQ0,*/ + /*S500_MUX_SIRQ1,*/ + /*S500_MUX_SIRQ2,*/ + S500_MUX_TS, + S500_MUX_LCD0, + S500_MUX_RESERVED, +}; + +/* MFPCTL group data */ +/* mfp0_31_26 reserved */ +/* mfp0_25_23 */ +static unsigned int lcd0_d18_mfp_pads[] = { LCD0_D18 }; +static unsigned int lcd0_d18_mfp_funcs[] = { S500_MUX_NOR, + S500_MUX_SENS1, + S500_MUX_PWM2, + S500_MUX_PWM4, + S500_MUX_LCD0 }; +/* mfp0_22_20 */ +static unsigned int rmii_crs_dv_mfp_pads[] = { ETH_CRS_DV }; +static unsigned int rmii_crs_dv_mfp_funcs[] = { S500_MUX_ETH_RMII, + S500_MUX_ETH_SMII, + S500_MUX_SPI2, + S500_MUX_UART4, + S500_MUX_PWM4 }; +/* mfp0_18_16_eth_txd0 */ +static unsigned int rmii_txd0_mfp_pads[] = { ETH_TXD0 }; +static unsigned int rmii_txd0_mfp_funcs[] = { S500_MUX_ETH_RMII, + S500_MUX_ETH_SMII, + S500_MUX_SPI2, + S500_MUX_UART6, + S500_MUX_PWM4 }; +/* mfp0_18_16_eth_txd1 */ +static unsigned int rmii_txd1_mfp_pads[] = { ETH_TXD1 }; +static unsigned int rmii_txd1_mfp_funcs[] = { S500_MUX_ETH_RMII, + S500_MUX_ETH_SMII, + S500_MUX_SPI2, + S500_MUX_UART6, + S500_MUX_PWM5 }; +/* mfp0_15_13_rmii_txen */ +static unsigned int rmii_txen_mfp_pads[] = { ETH_TXEN }; +static unsigned int rmii_txen_mfp_funcs[] = { S500_MUX_ETH_RMII, + S500_MUX_UART2, + S500_MUX_SPI3, + S500_MUX_PWM0 }; +/* mfp0_15_13_rmii_rxen */ +static unsigned int rmii_rxen_mfp_pads[] = { ETH_RXER }; +static unsigned int rmii_rxen_mfp_funcs[] = { S500_MUX_ETH_RMII, + S500_MUX_UART2, + S500_MUX_SPI3, + S500_MUX_PWM1 }; +/* mfp0_12_11 reserved */ + +/* mfp0_10_8_rmii_rxd1 */ +static unsigned int rmii_rxd1_mfp_pads[] = { ETH_RXD1 }; +static unsigned int rmii_rxd1_mfp_funcs[] = { S500_MUX_ETH_RMII, + S500_MUX_UART2, + S500_MUX_SPI3, + S500_MUX_PWM2, + S500_MUX_UART5 }; +/* mfp0_10_8_rmii_rxd0 */ +static unsigned int rmii_rxd0_mfp_pads[] = { ETH_RXD0 }; +static unsigned int rmii_rxd0_mfp_funcs[] = { S500_MUX_ETH_RMII, + S500_MUX_UART2, + S500_MUX_SPI3, + S500_MUX_PWM3, + S500_MUX_UART5 }; +/* mfp0_7_6 */ +static unsigned int rmii_ref_clk_mfp_pads[] = { ETH_REF_CLK }; +static unsigned int rmii_ref_clk_mfp_funcs[] = { S500_MUX_ETH_RMII, + S500_MUX_UART4, + S500_MUX_SPI2, + S500_MUX_RESERVED, + S500_MUX_ETH_SMII }; +/* mfp0_5 */ +static unsigned int i2s_d0_mfp_pads[] = { I2S_D0 }; +static unsigned int i2s_d0_mfp_funcs[] = { S500_MUX_I2S0, + S500_MUX_NOR }; +/* mfp0_4_3 */ +static unsigned int i2s_pcm1_mfp_pads[] = { I2S_LRCLK0, I2S_MCLK0 }; +static unsigned int i2s_pcm1_mfp_funcs[] = { S500_MUX_I2S0, + S500_MUX_NOR, + S500_MUX_PCM1 }; +/* mfp0_2_1_i2s0 */ +static unsigned int i2s0_pcm0_mfp_pads[] = { I2S_BCLK0 }; +static unsigned int i2s0_pcm0_mfp_funcs[] = { S500_MUX_I2S0, + S500_MUX_NOR, + S500_MUX_PCM0 }; +/* mfp0_2_1_i2s1 */ +static unsigned int i2s1_pcm0_mfp_pads[] = { I2S_BCLK1, I2S_LRCLK1, + I2S_MCLK1 }; +static unsigned int i2s1_pcm0_mfp_funcs[] = { S500_MUX_I2S1, + S500_MUX_NOR, + S500_MUX_PCM0 }; +/* mfp0_0 */ +static unsigned int i2s_d1_mfp_pads[] = { I2S_D1 }; +static unsigned int i2s_d1_mfp_funcs[] = { S500_MUX_I2S1, + S500_MUX_NOR }; +/* mfp1_31_29_ks_in0 */ +static unsigned int ks_in0_mfp_pads[] = { KS_IN0 }; +static unsigned int ks_in0_mfp_funcs[] = { S500_MUX_KS, + S500_MUX_JTAG, + S500_MUX_NOR, + S500_MUX_PWM0, + S500_MUX_PWM4, + S500_MUX_SENS1, + S500_MUX_PWM4, + S500_MUX_P0 }; +/* mfp1_31_29_ks_in1 */ +static unsigned int ks_in1_mfp_pads[] = { KS_IN1 }; +static unsigned int ks_in1_mfp_funcs[] = { S500_MUX_KS, + S500_MUX_JTAG, + S500_MUX_NOR, + S500_MUX_PWM1, + S500_MUX_PWM5, + S500_MUX_SENS1, + S500_MUX_PWM1, + S500_MUX_USB30 }; +/* mfp1_31_29_ks_in2 */ +static unsigned int ks_in2_mfp_pads[] = { KS_IN2 }; +static unsigned int ks_in2_mfp_funcs[] = { S500_MUX_KS, + S500_MUX_JTAG, + S500_MUX_NOR, + S500_MUX_PWM0, + S500_MUX_PWM0, + S500_MUX_SENS1, + S500_MUX_PWM0, + S500_MUX_P0 }; +/* mfp1_28_26_ks_in3 */ +static unsigned int ks_in3_mfp_pads[] = { KS_IN3 }; +static unsigned int ks_in3_mfp_funcs[] = { S500_MUX_KS, + S500_MUX_JTAG, + S500_MUX_NOR, + S500_MUX_PWM1, + S500_MUX_RESERVED, + S500_MUX_SENS1 }; +/* mfp1_28_26_ks_out0 */ +static unsigned int ks_out0_mfp_pads[] = { KS_OUT0 }; +static unsigned int ks_out0_mfp_funcs[] = { S500_MUX_KS, + S500_MUX_UART5, + S500_MUX_NOR, + S500_MUX_PWM2, + S500_MUX_RESERVED, + S500_MUX_SENS1, + S500_MUX_SD0 }; +/* mfp1_28_26_ks_out1 */ +static unsigned int ks_out1_mfp_pads[] = { KS_OUT1 }; +static unsigned int ks_out1_mfp_funcs[] = { S500_MUX_KS, + S500_MUX_JTAG, + S500_MUX_NOR, + S500_MUX_PWM3, + S500_MUX_RESERVED, + S500_MUX_SENS1, + S500_MUX_SD0 }; +/* mfp1_25_23 */ +static unsigned int ks_out2_mfp_pads[] = { KS_OUT2 }; +static unsigned int ks_out2_mfp_funcs[] = { S500_MUX_SD0, + S500_MUX_KS, + S500_MUX_NOR, + S500_MUX_PWM2, + S500_MUX_UART5, + S500_MUX_SENS1 }; +/* mfp1_22_21 */ +static unsigned int lvds_o_pn_mfp_pads[] = { LVDS_OEP, LVDS_OEN, + LVDS_ODP, LVDS_ODN, + LVDS_OCP, LVDS_OCN, + LVDS_OBP, LVDS_OBN, + LVDS_OAP, LVDS_OAN }; +static unsigned int lvds_o_pn_mfp_funcs[] = { S500_MUX_LVDS, + S500_MUX_TS, + S500_MUX_LCD0 }; +/* mfp1_20_19 */ +static unsigned int dsi_dn0_mfp_pads[] = { DSI_DN0 }; +static unsigned int dsi_dn0_mfp_funcs[] = { S500_MUX_DSI, + S500_MUX_UART2, + S500_MUX_SPI0 }; +/* mfp1_18_17 */ +static unsigned int dsi_dp2_mfp_pads[] = { DSI_DP2 }; +static unsigned int dsi_dp2_mfp_funcs[] = { S500_MUX_DSI, + S500_MUX_UART2, + S500_MUX_SPI0, + S500_MUX_SD1 }; +/* mfp1_16_14 */ +static unsigned int lcd0_d17_mfp_pads[] = { LCD0_D17 }; +static unsigned int lcd0_d17_mfp_funcs[] = { S500_MUX_NOR, + S500_MUX_SD0, + S500_MUX_SD1, + S500_MUX_PWM3, + S500_MUX_LCD0 }; +/* mfp1_13_12 */ +static unsigned int dsi_dp3_mfp_pads[] = { DSI_DP3 }; +static unsigned int dsi_dp3_mfp_funcs[] = { S500_MUX_DSI, + S500_MUX_SD0, + S500_MUX_SD1, + S500_MUX_LCD0 }; +/* mfp1_11_10 */ +static unsigned int dsi_dn3_mfp_pads[] = { DSI_DN3 }; +static unsigned int dsi_dn3_mfp_funcs[] = { S500_MUX_DSI, + S500_MUX_RESERVED, + S500_MUX_SD1, + S500_MUX_LCD0 }; +/* mfp1_9_7 */ +static unsigned int dsi_dp0_mfp_pads[] = { DSI_DP0 }; +static unsigned int dsi_dp0_mfp_funcs[] = { S500_MUX_DSI, + S500_MUX_RESERVED, + S500_MUX_SD0, + S500_MUX_UART2, + S500_MUX_SPI0 }; +/* mfp1_6_5 */ +static unsigned int lvds_ee_pn_mfp_pads[] = { LVDS_EEP, LVDS_EEN }; +static unsigned int lvds_ee_pn_mfp_funcs[] = { S500_MUX_LVDS, + S500_MUX_NOR, + S500_MUX_TS, + S500_MUX_LCD0 }; +/* mfp1_4_3 */ +static unsigned int spi0_i2c_pcm_mfp_pads[] = { SPI0_SCLK, SPI0_MOSI }; +static unsigned int spi0_i2c_pcm_mfp_funcs[] = { S500_MUX_SPI0, + S500_MUX_NOR, + S500_MUX_I2C3, + S500_MUX_PCM0 }; +/* mfp1_2_0 */ +static unsigned int spi0_i2s_pcm_mfp_pads[] = { SPI0_SS, SPI0_MISO }; +static unsigned int spi0_i2s_pcm_mfp_funcs[] = { S500_MUX_SPI0, + S500_MUX_NOR, + S500_MUX_I2S1, + S500_MUX_PCM1, + S500_MUX_PCM0 }; +/* mfp2_31 reserved */ +/* mfp2_30_29 */ +static unsigned int dsi_dnp1_cp_mfp_pads[] = { DSI_DP1, DSI_CP, DSI_CN }; +static unsigned int dsi_dnp1_cp_mfp_funcs[] = { S500_MUX_DSI, + S500_MUX_SD1, + S500_MUX_LCD0 }; +/* mfp2_28_27 */ +static unsigned int lvds_e_pn_mfp_pads[] = { LVDS_EDP, LVDS_EDN, + LVDS_ECP, LVDS_ECN, + LVDS_EBP, LVDS_EBN, + LVDS_EAP, LVDS_EAN }; +static unsigned int lvds_e_pn_mfp_funcs[] = { S500_MUX_LVDS, + S500_MUX_NOR, + S500_MUX_LCD0 }; +/* mfp2_26_24 */ +static unsigned int dsi_dn2_mfp_pads[] = { DSI_DN2 }; +static unsigned int dsi_dn2_mfp_funcs[] = { S500_MUX_DSI, + S500_MUX_RESERVED, + S500_MUX_SD1, + S500_MUX_UART2, + S500_MUX_SPI0 }; +/* mfp2_23 */ +static unsigned int uart2_rtsb_mfp_pads[] = { UART2_RTSB }; +static unsigned int uart2_rtsb_mfp_funcs[] = { S500_MUX_UART2, + S500_MUX_UART0 }; +/* mfp2_22 */ +static unsigned int uart2_ctsb_mfp_pads[] = { UART2_CTSB }; +static unsigned int uart2_ctsb_mfp_funcs[] = { S500_MUX_UART2, + S500_MUX_UART0 }; +/* mfp2_21 */ +static unsigned int uart3_rtsb_mfp_pads[] = { UART3_RTSB }; +static unsigned int uart3_rtsb_mfp_funcs[] = { S500_MUX_UART3, + S500_MUX_UART5 }; +/* mfp2_20 */ +static unsigned int uart3_ctsb_mfp_pads[] = { UART3_CTSB }; +static unsigned int uart3_ctsb_mfp_funcs[] = { S500_MUX_UART3, + S500_MUX_UART5 }; +/* mfp2_19_17 */ +static unsigned int sd0_d0_mfp_pads[] = { SD0_D0 }; +static unsigned int sd0_d0_mfp_funcs[] = { S500_MUX_SD0, + S500_MUX_NOR, + S500_MUX_RESERVED, + S500_MUX_JTAG, + S500_MUX_UART2, + S500_MUX_UART5 }; +/* mfp2_16_14 */ +static unsigned int sd0_d1_mfp_pads[] = { SD0_D1 }; +static unsigned int sd0_d1_mfp_funcs[] = { S500_MUX_SD0, + S500_MUX_NOR, + S500_MUX_RESERVED, + S500_MUX_RESERVED, + S500_MUX_UART2, + S500_MUX_UART5 }; +/* mfp2_13_11 */ +static unsigned int sd0_d2_d3_mfp_pads[] = { SD0_D2, SD0_D3 }; +static unsigned int sd0_d2_d3_mfp_funcs[] = { S500_MUX_SD0, + S500_MUX_NOR, + S500_MUX_RESERVED, + S500_MUX_JTAG, + S500_MUX_UART2, + S500_MUX_UART1 }; +/* mfp2_10_9 */ +static unsigned int sd1_d0_d3_mfp_pads[] = { SD1_D0, SD1_D1, + SD1_D2, SD1_D3 }; +static unsigned int sd1_d0_d3_mfp_funcs[] = { S500_MUX_SD0, + S500_MUX_NOR, + S500_MUX_RESERVED, + S500_MUX_SD1 }; +/* mfp2_8_7 */ +static unsigned int sd0_cmd_mfp_pads[] = { SD0_CMD }; +static unsigned int sd0_cmd_mfp_funcs[] = { S500_MUX_SD0, + S500_MUX_NOR, + S500_MUX_RESERVED, + S500_MUX_JTAG }; +/* mfp2_6_5 */ +static unsigned int sd0_clk_mfp_pads[] = { SD0_CLK }; +static unsigned int sd0_clk_mfp_funcs[] = { S500_MUX_SD0, + S500_MUX_RESERVED, + S500_MUX_JTAG }; +/* mfp2_4_3 */ +static unsigned int sd1_cmd_mfp_pads[] = { SD1_CMD }; +static unsigned int sd1_cmd_mfp_funcs[] = { S500_MUX_SD1, + S500_MUX_NOR }; +/* mfp2_2_0 */ +static unsigned int uart0_rx_mfp_pads[] = { UART0_RX }; +static unsigned int uart0_rx_mfp_funcs[] = { S500_MUX_UART0, + S500_MUX_UART2, + S500_MUX_SPI1, + S500_MUX_I2C0, + S500_MUX_PCM1, + S500_MUX_I2S1 }; +/* mfp3_31 reserved */ +/* mfp3_30 */ +static unsigned int clko_25m_mfp_pads[] = { CLKO_25M }; +static unsigned int clko_25m_mfp_funcs[] = { S500_MUX_RESERVED, + S500_MUX_CLKO_25M }; +/* mfp3_29_28 */ +static unsigned int csi_cn_cp_mfp_pads[] = { CSI_CN, CSI_CP }; +static unsigned int csi_cn_cp_mfp_funcs[] = { S500_MUX_MIPI_CSI, + S500_MUX_SENS0 }; +/* mfp3_27_24 reserved */ +/* mfp3_23_22 */ +static unsigned int sens0_ckout_mfp_pads[] = { SENSOR0_CKOUT }; +static unsigned int sens0_ckout_mfp_funcs[] = { S500_MUX_SENS0, + S500_MUX_NOR, + S500_MUX_SENS1, + S500_MUX_PWM1 }; +/* mfp3_21_19 */ +static unsigned int uart0_tx_mfp_pads[] = { UART0_TX }; +static unsigned int uart0_tx_mfp_funcs[] = { S500_MUX_UART0, + S500_MUX_UART2, + S500_MUX_SPI1, + S500_MUX_I2C0, + S500_MUX_SPDIF, + S500_MUX_PCM1, + S500_MUX_I2S1 }; +/* mfp3_18_16 */ +static unsigned int i2c0_mfp_pads[] = { I2C0_SCLK, + I2C0_SDATA }; +static unsigned int i2c0_mfp_funcs[] = { S500_MUX_I2C0, + S500_MUX_UART2, + S500_MUX_I2C1, + S500_MUX_UART1, + S500_MUX_SPI1 }; +/* mfp3_15_14 */ +static unsigned int csi_dn_dp_mfp_pads[] = { CSI_DN0, CSI_DN1, + CSI_DN2, CSI_DN3, + CSI_DP0, CSI_DP1, + CSI_DP2, CSI_DP3 }; +static unsigned int csi_dn_dp_mfp_funcs[] = { S500_MUX_MIPI_CSI, + S500_MUX_SENS0 }; +/* mfp3_13_12 */ +static unsigned int sen0_pclk_mfp_pads[] = { SENSOR0_PCLK }; +static unsigned int sen0_pclk_mfp_funcs[] = { S500_MUX_SENS0, + S500_MUX_NOR, + S500_MUX_PWM0 }; +/* mfp3_11_10 */ +static unsigned int pcm1_in_mfp_pads[] = { PCM1_IN }; +static unsigned int pcm1_in_mfp_funcs[] = { S500_MUX_PCM1, + S500_MUX_SENS1, + S500_MUX_UART4, + S500_MUX_PWM4 }; +/* mfp3_9_8 */ +static unsigned int pcm1_clk_mfp_pads[] = { PCM1_CLK }; +static unsigned int pcm1_clk_mfp_funcs[] = { S500_MUX_PCM1, + S500_MUX_SENS1, + S500_MUX_UART4, + S500_MUX_PWM5 }; +/* mfp3_7_6 */ +static unsigned int pcm1_sync_mfp_pads[] = { PCM1_SYNC }; +static unsigned int pcm1_sync_mfp_funcs[] = { S500_MUX_PCM1, + S500_MUX_SENS1, + S500_MUX_UART6, + S500_MUX_I2C3 }; +/* mfp3_5_4 */ +static unsigned int pcm1_out_mfp_pads[] = { PCM1_OUT }; +static unsigned int pcm1_out_mfp_funcs[] = { S500_MUX_PCM1, + S500_MUX_SENS1, + S500_MUX_UART6, + S500_MUX_I2C3 }; +/* mfp3_3 */ +static unsigned int dnand_data_wr_mfp_pads[] = { DNAND_D0, DNAND_D1, + DNAND_D2, DNAND_D3, + DNAND_D4, DNAND_D5, + DNAND_D6, DNAND_D7, + DNAND_RDB, DNAND_RDBN }; +static unsigned int dnand_data_wr_mfp_funcs[] = { S500_MUX_NAND, + S500_MUX_SD2 }; +/* mfp3_2 */ +static unsigned int dnand_acle_ce0_mfp_pads[] = { DNAND_ALE, + DNAND_CLE, + DNAND_CEB0, + DNAND_CEB1 }; +static unsigned int dnand_acle_ce0_mfp_funcs[] = { S500_MUX_NAND, + S500_MUX_SPI2 }; +/* mfp3_1_0_nand_ceb2 */ +static unsigned int nand_ceb2_mfp_pads[] = { DNAND_CEB2 }; +static unsigned int nand_ceb2_mfp_funcs[] = { S500_MUX_NAND, + S500_MUX_PWM5 }; +/* mfp3_1_0_nand_ceb3 */ +static unsigned int nand_ceb3_mfp_pads[] = { DNAND_CEB3 }; +static unsigned int nand_ceb3_mfp_funcs[] = { S500_MUX_NAND, + S500_MUX_PWM4 }; + +/* PADDRV group data */ +/* paddrv0_29_28 */ +static unsigned int sirq_drv_pads[] = { SIRQ0, SIRQ1, SIRQ2 }; +/* paddrv0_23_22 */ +static unsigned int rmii_txd01_txen_drv_pads[] = { ETH_TXD0, ETH_TXD1, + ETH_TXEN }; +/* paddrv0_21_20 */ +static unsigned int rmii_rxer_drv_pads[] = { ETH_RXER }; +/* paddrv0_19_18 */ +static unsigned int rmii_crs_drv_pads[] = { ETH_CRS_DV }; +/* paddrv0_17_16 */ +static unsigned int rmii_rxd10_drv_pads[] = { ETH_RXD0, ETH_RXD1 }; +/* paddrv0_15_14 */ +static unsigned int rmii_ref_clk_drv_pads[] = { ETH_REF_CLK }; +/* paddrv0_13_12 */ +static unsigned int smi_mdc_mdio_drv_pads[] = { ETH_MDC, ETH_MDIO }; +/* paddrv0_11_10 */ +static unsigned int i2s_d0_drv_pads[] = { I2S_D0 }; +/* paddrv0_9_8 */ +static unsigned int i2s_bclk0_drv_pads[] = { I2S_BCLK0 }; +/* paddrv0_7_6 */ +static unsigned int i2s3_drv_pads[] = { I2S_LRCLK0, I2S_MCLK0, + I2S_D1 }; +/* paddrv0_5_4 */ +static unsigned int i2s13_drv_pads[] = { I2S_BCLK1, I2S_LRCLK1, + I2S_MCLK1 }; +/* paddrv0_3_2 */ +static unsigned int pcm1_drv_pads[] = { PCM1_IN, PCM1_CLK, + PCM1_SYNC, PCM1_OUT }; +/* paddrv0_1_0 */ +static unsigned int ks_in_drv_pads[] = { KS_IN0, KS_IN1, + KS_IN2, KS_IN3 }; +/* paddrv1_31_30 */ +static unsigned int ks_out_drv_pads[] = { KS_OUT0, KS_OUT1, KS_OUT2 }; +/* paddrv1_29_28 */ +static unsigned int lvds_all_drv_pads[] = { LVDS_OEP, LVDS_OEN, + LVDS_ODP, LVDS_ODN, + LVDS_OCP, LVDS_OCN, + LVDS_OBP, LVDS_OBN, + LVDS_OAP, LVDS_OAN, + LVDS_EEP, LVDS_EEN, + LVDS_EDP, LVDS_EDN, + LVDS_ECP, LVDS_ECN, + LVDS_EBP, LVDS_EBN, + LVDS_EAP, LVDS_EAN }; +/* paddrv1_27_26 */ +static unsigned int lcd_dsi_drv_pads[] = { DSI_DP3, DSI_DN3, DSI_DP1, + DSI_DN1, DSI_CP, DSI_CN }; +/* paddrv1_25_24 */ +static unsigned int dsi_drv_pads[] = { DSI_DP0, DSI_DN0, + DSI_DP2, DSI_DN2 }; +/* paddrv1_23_22 */ +static unsigned int sd0_d0_d3_drv_pads[] = { SD0_D0, SD0_D1, + SD0_D2, SD0_D3 }; +/* paddrv1_21_20 */ +static unsigned int sd1_d0_d3_drv_pads[] = { SD1_D0, SD1_D1, + SD1_D2, SD1_D3 }; +/* paddrv1_19_18 */ +static unsigned int sd0_cmd_drv_pads[] = { SD0_CMD }; +/* paddrv1_17_16 */ +static unsigned int sd0_clk_drv_pads[] = { SD0_CLK }; +/* paddrv1_15_14 */ +static unsigned int sd1_cmd_drv_pads[] = { SD1_CMD }; +/* paddrv1_13_12 */ +static unsigned int sd1_clk_drv_pads[] = { SD1_CLK }; +/* paddrv1_11_10 */ +static unsigned int spi0_all_drv_pads[] = { SPI0_SCLK, SPI0_SS, + SPI0_MISO, SPI0_MOSI }; +/* paddrv2_31_30 */ +static unsigned int uart0_rx_drv_pads[] = { UART0_RX }; +/* paddrv2_29_28 */ +static unsigned int uart0_tx_drv_pads[] = { UART0_TX }; +/* paddrv2_27_26 */ +static unsigned int uart2_all_drv_pads[] = { UART2_RX, UART2_TX, + UART2_RTSB, UART2_CTSB }; +/* paddrv2_24_23 */ +static unsigned int i2c0_all_drv_pads[] = { I2C0_SCLK, I2C0_SDATA }; +/* paddrv2_22_21 */ +static unsigned int i2c12_all_drv_pads[] = { I2C1_SCLK, I2C1_SDATA, + I2C2_SCLK, I2C2_SDATA }; +/* paddrv2_19_18 */ +static unsigned int sens0_pclk_drv_pads[] = { SENSOR0_PCLK }; +/* paddrv2_13_12 */ +static unsigned int sens0_ckout_drv_pads[] = { SENSOR0_CKOUT }; +/* paddrv2_3_2 */ +static unsigned int uart3_all_drv_pads[] = { UART3_RX, UART3_TX, + UART3_RTSB, UART3_CTSB }; + +/* Pinctrl groups */ +static const struct owl_pingroup s500_groups[] = { + MUX_PG(lcd0_d18_mfp, 0, 23, 3), + MUX_PG(rmii_crs_dv_mfp, 0, 20, 3), + MUX_PG(rmii_txd0_mfp, 0, 16, 3), + MUX_PG(rmii_txd1_mfp, 0, 16, 3), + MUX_PG(rmii_txen_mfp, 0, 13, 3), + MUX_PG(rmii_rxen_mfp, 0, 13, 3), + MUX_PG(rmii_rxd1_mfp, 0, 8, 3), + MUX_PG(rmii_rxd0_mfp, 0, 8, 3), + MUX_PG(rmii_ref_clk_mfp, 0, 6, 2), + MUX_PG(i2s_d0_mfp, 0, 5, 1), + MUX_PG(i2s_pcm1_mfp, 0, 3, 2), + MUX_PG(i2s0_pcm0_mfp, 0, 1, 2), + MUX_PG(i2s1_pcm0_mfp, 0, 1, 2), + MUX_PG(i2s_d1_mfp, 0, 0, 1), + MUX_PG(ks_in2_mfp, 1, 29, 3), + MUX_PG(ks_in1_mfp, 1, 29, 3), + MUX_PG(ks_in0_mfp, 1, 29, 3), + MUX_PG(ks_in3_mfp, 1, 26, 3), + MUX_PG(ks_out0_mfp, 1, 26, 3), + MUX_PG(ks_out1_mfp, 1, 26, 3), + MUX_PG(ks_out2_mfp, 1, 23, 3), + MUX_PG(lvds_o_pn_mfp, 1, 21, 2), + MUX_PG(dsi_dn0_mfp, 1, 19, 2), + MUX_PG(dsi_dp2_mfp, 1, 17, 2), + MUX_PG(lcd0_d17_mfp, 1, 14, 3), + MUX_PG(dsi_dp3_mfp, 1, 12, 2), + MUX_PG(dsi_dn3_mfp, 1, 10, 2), + MUX_PG(dsi_dp0_mfp, 1, 7, 3), + MUX_PG(lvds_ee_pn_mfp, 1, 5, 2), + MUX_PG(spi0_i2c_pcm_mfp, 1, 3, 2), + MUX_PG(spi0_i2s_pcm_mfp, 1, 0, 3), + MUX_PG(dsi_dnp1_cp_mfp, 2, 29, 2), + MUX_PG(lvds_e_pn_mfp, 2, 27, 2), + MUX_PG(dsi_dn2_mfp, 2, 24, 3), + MUX_PG(uart2_rtsb_mfp, 2, 23, 1), + MUX_PG(uart2_ctsb_mfp, 2, 22, 1), + MUX_PG(uart3_rtsb_mfp, 2, 21, 1), + MUX_PG(uart3_ctsb_mfp, 2, 20, 1), + MUX_PG(sd0_d0_mfp, 2, 17, 3), + MUX_PG(sd0_d1_mfp, 2, 14, 3), + MUX_PG(sd0_d2_d3_mfp, 2, 11, 3), + MUX_PG(sd1_d0_d3_mfp, 2, 9, 2), + MUX_PG(sd0_cmd_mfp, 2, 7, 2), + MUX_PG(sd0_clk_mfp, 2, 5, 2), + MUX_PG(sd1_cmd_mfp, 2, 3, 2), + MUX_PG(uart0_rx_mfp, 2, 0, 3), + MUX_PG(clko_25m_mfp, 3, 30, 1), + MUX_PG(csi_cn_cp_mfp, 3, 28, 2), + MUX_PG(sens0_ckout_mfp, 3, 22, 2), + MUX_PG(uart0_tx_mfp, 3, 19, 3), + MUX_PG(i2c0_mfp, 3, 16, 3), + MUX_PG(csi_dn_dp_mfp, 3, 14, 2), + MUX_PG(sen0_pclk_mfp, 3, 12, 2), + MUX_PG(pcm1_in_mfp, 3, 10, 2), + MUX_PG(pcm1_clk_mfp, 3, 8, 2), + MUX_PG(pcm1_sync_mfp, 3, 6, 2), + MUX_PG(pcm1_out_mfp, 3, 4, 2), + MUX_PG(dnand_data_wr_mfp, 3, 3, 1), + MUX_PG(dnand_acle_ce0_mfp, 3, 2, 1), + MUX_PG(nand_ceb2_mfp, 3, 0, 2), + MUX_PG(nand_ceb3_mfp, 3, 0, 2), + + DRV_PG(sirq_drv, 0, 28, 2), + DRV_PG(rmii_txd01_txen_drv, 0, 22, 2), + DRV_PG(rmii_rxer_drv, 0, 20, 2), + DRV_PG(rmii_crs_drv, 0, 18, 2), + DRV_PG(rmii_rxd10_drv, 0, 16, 2), + DRV_PG(rmii_ref_clk_drv, 0, 14, 2), + DRV_PG(smi_mdc_mdio_drv, 0, 12, 2), + DRV_PG(i2s_d0_drv, 0, 10, 2), + DRV_PG(i2s_bclk0_drv, 0, 8, 2), + DRV_PG(i2s3_drv, 0, 6, 2), + DRV_PG(i2s13_drv, 0, 4, 2), + DRV_PG(pcm1_drv, 0, 2, 2), + DRV_PG(ks_in_drv, 0, 0, 2), + DRV_PG(ks_out_drv, 1, 30, 2), + DRV_PG(lvds_all_drv, 1, 28, 2), + DRV_PG(lcd_dsi_drv, 1, 26, 2), + DRV_PG(dsi_drv, 1, 24, 2), + DRV_PG(sd0_d0_d3_drv, 1, 22, 2), + DRV_PG(sd1_d0_d3_drv, 1, 20, 2), + DRV_PG(sd0_cmd_drv, 1, 18, 2), + DRV_PG(sd0_clk_drv, 1, 16, 2), + DRV_PG(sd1_cmd_drv, 1, 14, 2), + DRV_PG(sd1_clk_drv, 1, 12, 2), + DRV_PG(spi0_all_drv, 1, 10, 2), + DRV_PG(uart0_rx_drv, 2, 30, 2), + DRV_PG(uart0_tx_drv, 2, 28, 2), + DRV_PG(uart2_all_drv, 2, 26, 2), + DRV_PG(i2c0_all_drv, 2, 23, 2), + DRV_PG(i2c12_all_drv, 2, 21, 2), + DRV_PG(sens0_pclk_drv, 2, 18, 2), + DRV_PG(sens0_ckout_drv, 2, 12, 2), + DRV_PG(uart3_all_drv, 2, 2, 2), +}; + +static const char * const nor_groups[] = { + "lcd0_d18_mfp", + "i2s_d0_mfp", + "i2s0_pcm0_mfp", + "i2s1_pcm0_mfp", + "i2s_d1_mfp", + "ks_in2_mfp", + "ks_in1_mfp", + "ks_in0_mfp", + "ks_in3_mfp", + "ks_out0_mfp", + "ks_out1_mfp", + "ks_out2_mfp", + "lcd0_d17_mfp", + "lvds_ee_pn_mfp", + "spi0_i2c_pcm_mfp", + "spi0_i2s_pcm_mfp", + "lvds_e_pn_mfp", + "sd0_d0_mfp", + "sd0_d1_mfp", + "sd0_d2_d3_mfp", + "sd1_d0_d3_mfp", + "sd0_cmd_mfp", + "sd1_cmd_mfp", + "sens0_ckout_mfp", + "sen0_pclk_mfp", +}; + +static const char * const eth_rmii_groups[] = { + "rmii_crs_dv_mfp", + "rmii_txd0_mfp", + "rmii_txd1_mfp", + "rmii_txen_mfp", + "rmii_rxen_mfp", + "rmii_rxd1_mfp", + "rmii_rxd0_mfp", + "rmii_ref_clk_mfp", +}; + +static const char * const eth_smii_groups[] = { + "rmii_crs_dv_mfp", + "rmii_txd0_mfp", + "rmii_txd1_mfp", + "rmii_ref_clk_mfp", +}; + +static const char * const spi0_groups[] = { + "dsi_dn0_mfp", + "dsi_dp2_mfp", + "dsi_dp0_mfp", + "spi0_i2c_pcm_mfp", + "spi0_i2s_pcm_mfp", + "dsi_dn2_mfp", +}; + +static const char * const spi1_groups[] = { + "uart0_rx_mfp", + "uart0_tx_mfp", + "i2c0_mfp", +}; + +static const char * const spi2_groups[] = { + "rmii_crs_dv_mfp", + "rmii_txd0_mfp", + "rmii_txd1_mfp", + "rmii_ref_clk_mfp", + "dnand_acle_ce0_mfp", +}; + +static const char * const spi3_groups[] = { + "rmii_txen_mfp", + "rmii_rxen_mfp", + "rmii_rxd1_mfp", + "rmii_rxd0_mfp", +}; + +static const char * const sens0_groups[] = { + "csi_cn_cp_mfp", + "sens0_ckout_mfp", + "csi_dn_dp_mfp", + "sen0_pclk_mfp", +}; + +static const char * const sens1_groups[] = { + "lcd0_d18_mfp", + "ks_in2_mfp", + "ks_in1_mfp", + "ks_in0_mfp", + "ks_in3_mfp", + "ks_out0_mfp", + "ks_out1_mfp", + "ks_out2_mfp", + "sens0_ckout_mfp", + "pcm1_in_mfp", + "pcm1_clk_mfp", + "pcm1_sync_mfp", + "pcm1_out_mfp", +}; + +static const char * const uart0_groups[] = { + "uart2_rtsb_mfp", + "uart2_ctsb_mfp", + "uart0_rx_mfp", + "uart0_tx_mfp", +}; + +static const char * const uart1_groups[] = { + "sd0_d2_d3_mfp", + "i2c0_mfp", +}; + +static const char * const uart2_groups[] = { + "rmii_txen_mfp", + "rmii_rxen_mfp", + "rmii_rxd1_mfp", + "rmii_rxd0_mfp", + "dsi_dn0_mfp", + "dsi_dp2_mfp", + "dsi_dp0_mfp", + "dsi_dn2_mfp", + "uart2_rtsb_mfp", + "uart2_ctsb_mfp", + "sd0_d0_mfp", + "sd0_d1_mfp", + "sd0_d2_d3_mfp", + "uart0_rx_mfp", + "uart0_tx_mfp", + "i2c0_mfp", +}; + +static const char * const uart3_groups[] = { + "uart3_rtsb_mfp", + "uart3_ctsb_mfp", +}; + +static const char * const uart4_groups[] = { + "rmii_crs_dv_mfp", + "rmii_ref_clk_mfp", + "pcm1_in_mfp", + "pcm1_clk_mfp", +}; + +static const char * const uart5_groups[] = { + "rmii_rxd1_mfp", + "rmii_rxd0_mfp", + "ks_out0_mfp", + "ks_out2_mfp", + "uart3_rtsb_mfp", + "uart3_ctsb_mfp", + "sd0_d0_mfp", + "sd0_d1_mfp", +}; + +static const char * const uart6_groups[] = { + "rmii_txd0_mfp", + "rmii_txd1_mfp", + "pcm1_sync_mfp", + "pcm1_out_mfp", +}; + +static const char * const i2s0_groups[] = { + "i2s_d0_mfp", + "i2s_pcm1_mfp", + "i2s0_pcm0_mfp", +}; + +static const char * const i2s1_groups[] = { + "i2s1_pcm0_mfp", + "i2s_d1_mfp", + "spi0_i2s_pcm_mfp", + "uart0_rx_mfp", + "uart0_tx_mfp", +}; + +static const char * const pcm1_groups[] = { + "i2s_pcm1_mfp", + "spi0_i2s_pcm_mfp", + "uart0_rx_mfp", + "uart0_tx_mfp", + "pcm1_in_mfp", + "pcm1_clk_mfp", + "pcm1_sync_mfp", + "pcm1_out_mfp", +}; + +static const char * const pcm0_groups[] = { + "i2s0_pcm0_mfp", + "i2s1_pcm0_mfp", + "spi0_i2c_pcm_mfp", + "spi0_i2s_pcm_mfp", +}; + +static const char * const ks_groups[] = { + "ks_in2_mfp", + "ks_in1_mfp", + "ks_in0_mfp", + "ks_in3_mfp", + "ks_out0_mfp", + "ks_out1_mfp", + "ks_out2_mfp", +}; + +static const char * const jtag_groups[] = { + "ks_in2_mfp", + "ks_in1_mfp", + "ks_in0_mfp", + "ks_in3_mfp", + "ks_out1_mfp", + "sd0_d0_mfp", + "sd0_d2_d3_mfp", + "sd0_cmd_mfp", + "sd0_clk_mfp", +}; + +static const char * const pwm0_groups[] = { + "ks_in2_mfp", + "ks_in0_mfp", + "rmii_txen_mfp", + "sen0_pclk_mfp", +}; + +static const char * const pwm1_groups[] = { + "rmii_rxen_mfp", + "ks_in1_mfp", + "ks_in3_mfp", + "sens0_ckout_mfp", +}; + +static const char * const pwm2_groups[] = { + "lcd0_d18_mfp", + "rmii_rxd1_mfp", + "ks_out0_mfp", + "ks_out2_mfp", +}; + +static const char * const pwm3_groups[] = { + "rmii_rxd0_mfp", + "ks_out1_mfp", + "lcd0_d17_mfp", +}; + +static const char * const pwm4_groups[] = { + "lcd0_d18_mfp", + "rmii_crs_dv_mfp", + "rmii_txd0_mfp", + "ks_in0_mfp", + "pcm1_in_mfp", + "nand_ceb3_mfp", +}; + +static const char * const pwm5_groups[] = { + "rmii_txd1_mfp", + "ks_in1_mfp", + "pcm1_clk_mfp", + "nand_ceb2_mfp", +}; + +static const char * const p0_groups[] = { + "ks_in2_mfp", + "ks_in0_mfp", +}; + +static const char * const sd0_groups[] = { + "ks_out0_mfp", + "ks_out1_mfp", + "ks_out2_mfp", + "lcd0_d17_mfp", + "dsi_dp3_mfp", + "dsi_dp0_mfp", + "sd0_d0_mfp", + "sd0_d1_mfp", + "sd0_d2_d3_mfp", + "sd1_d0_d3_mfp", + "sd0_cmd_mfp", + "sd0_clk_mfp", +}; + +static const char * const sd1_groups[] = { + "dsi_dp2_mfp", + "lcd0_d17_mfp", + "dsi_dp3_mfp", + "dsi_dn3_mfp", + "dsi_dnp1_cp_mfp", + "dsi_dn2_mfp", + "sd1_d0_d3_mfp", + "sd1_cmd_mfp", +}; + +static const char * const sd2_groups[] = { + "dnand_data_wr_mfp", +}; + +static const char * const i2c0_groups[] = { + "uart0_rx_mfp", + "uart0_tx_mfp", + "i2c0_mfp", +}; + +static const char * const i2c1_groups[] = { + "i2c0_mfp", +}; + +static const char * const i2c3_groups[] = { + "spi0_i2c_pcm_mfp", + "pcm1_sync_mfp", + "pcm1_out_mfp", +}; + +static const char * const lvds_groups[] = { + "lvds_o_pn_mfp", + "lvds_ee_pn_mfp", + "lvds_e_pn_mfp", +}; + +static const char * const ts_groups[] = { + "lvds_o_pn_mfp", + "lvds_ee_pn_mfp", +}; + +static const char * const lcd0_groups[] = { + "lcd0_d18_mfp", + "lcd0_d17_mfp", + "lvds_o_pn_mfp", + "dsi_dp3_mfp", + "dsi_dn3_mfp", + "lvds_ee_pn_mfp", + "dsi_dnp1_cp_mfp", + "lvds_e_pn_mfp", +}; + +static const char * const usb30_groups[] = { + "ks_in1_mfp", +}; + +static const char * const clko_25m_groups[] = { + "clko_25m_mfp", +}; + +static const char * const mipi_csi_groups[] = { + "csi_cn_cp_mfp", + "csi_dn_dp_mfp", +}; + +static const char * const dsi_groups[] = { + "dsi_dn0_mfp", + "dsi_dp2_mfp", + "dsi_dp3_mfp", + "dsi_dn3_mfp", + "dsi_dp0_mfp", + "dsi_dnp1_cp_mfp", + "dsi_dn2_mfp", +}; + +static const char * const nand_groups[] = { + "dnand_data_wr_mfp", + "dnand_acle_ce0_mfp", + "nand_ceb2_mfp", + "nand_ceb3_mfp", +}; + +static const char * const spdif_groups[] = { + "uart0_tx_mfp", +}; + +static const struct owl_pinmux_func s500_functions[] = { + [S500_MUX_NOR] = FUNCTION(nor), + [S500_MUX_ETH_RMII] = FUNCTION(eth_rmii), + [S500_MUX_ETH_SMII] = FUNCTION(eth_smii), + [S500_MUX_SPI0] = FUNCTION(spi0), + [S500_MUX_SPI1] = FUNCTION(spi1), + [S500_MUX_SPI2] = FUNCTION(spi2), + [S500_MUX_SPI3] = FUNCTION(spi3), + [S500_MUX_SENS0] = FUNCTION(sens0), + [S500_MUX_SENS1] = FUNCTION(sens1), + [S500_MUX_UART0] = FUNCTION(uart0), + [S500_MUX_UART1] = FUNCTION(uart1), + [S500_MUX_UART2] = FUNCTION(uart2), + [S500_MUX_UART3] = FUNCTION(uart3), + [S500_MUX_UART4] = FUNCTION(uart4), + [S500_MUX_UART5] = FUNCTION(uart5), + [S500_MUX_UART6] = FUNCTION(uart6), + [S500_MUX_I2S0] = FUNCTION(i2s0), + [S500_MUX_I2S1] = FUNCTION(i2s1), + [S500_MUX_PCM1] = FUNCTION(pcm1), + [S500_MUX_PCM0] = FUNCTION(pcm0), + [S500_MUX_KS] = FUNCTION(ks), + [S500_MUX_JTAG] = FUNCTION(jtag), + [S500_MUX_PWM0] = FUNCTION(pwm0), + [S500_MUX_PWM1] = FUNCTION(pwm1), + [S500_MUX_PWM2] = FUNCTION(pwm2), + [S500_MUX_PWM3] = FUNCTION(pwm3), + [S500_MUX_PWM4] = FUNCTION(pwm4), + [S500_MUX_PWM5] = FUNCTION(pwm5), + [S500_MUX_P0] = FUNCTION(p0), + [S500_MUX_SD0] = FUNCTION(sd0), + [S500_MUX_SD1] = FUNCTION(sd1), + [S500_MUX_SD2] = FUNCTION(sd2), + [S500_MUX_I2C0] = FUNCTION(i2c0), + [S500_MUX_I2C1] = FUNCTION(i2c1), + /*[S500_MUX_I2C2] = FUNCTION(i2c2),*/ + [S500_MUX_I2C3] = FUNCTION(i2c3), + [S500_MUX_DSI] = FUNCTION(dsi), + [S500_MUX_LVDS] = FUNCTION(lvds), + [S500_MUX_USB30] = FUNCTION(usb30), + [S500_MUX_CLKO_25M] = FUNCTION(clko_25m), + [S500_MUX_MIPI_CSI] = FUNCTION(mipi_csi), + [S500_MUX_NAND] = FUNCTION(nand), + [S500_MUX_SPDIF] = FUNCTION(spdif), + /*[S500_MUX_SIRQ0] = FUNCTION(sirq0),*/ + /*[S500_MUX_SIRQ1] = FUNCTION(sirq1),*/ + /*[S500_MUX_SIRQ2] = FUNCTION(sirq2),*/ + [S500_MUX_TS] = FUNCTION(ts), + [S500_MUX_LCD0] = FUNCTION(lcd0), +}; + +/* PAD_ST0 */ +static PAD_ST_CONF(I2C0_SDATA, 0, 30, 1); +static PAD_ST_CONF(UART0_RX, 0, 29, 1); +static PAD_ST_CONF(I2S_MCLK1, 0, 23, 1); +static PAD_ST_CONF(ETH_REF_CLK, 0, 22, 1); +static PAD_ST_CONF(ETH_TXEN, 0, 21, 1); +static PAD_ST_CONF(ETH_TXD0, 0, 20, 1); +static PAD_ST_CONF(I2S_LRCLK1, 0, 19, 1); +static PAD_ST_CONF(DSI_DP0, 0, 16, 1); +static PAD_ST_CONF(DSI_DN0, 0, 15, 1); +static PAD_ST_CONF(UART0_TX, 0, 14, 1); +static PAD_ST_CONF(SPI0_SCLK, 0, 13, 1); +static PAD_ST_CONF(SD0_CLK, 0, 12, 1); +static PAD_ST_CONF(KS_IN0, 0, 11, 1); +static PAD_ST_CONF(SENSOR0_PCLK, 0, 9, 1); +static PAD_ST_CONF(I2C0_SCLK, 0, 7, 1); +static PAD_ST_CONF(KS_OUT0, 0, 6, 1); +static PAD_ST_CONF(KS_OUT1, 0, 5, 1); +static PAD_ST_CONF(KS_OUT2, 0, 4, 1); + +/* PAD_ST1 */ +static PAD_ST_CONF(DSI_DP2, 1, 31, 1); +static PAD_ST_CONF(DSI_DN2, 1, 30, 1); +static PAD_ST_CONF(I2S_LRCLK0, 1, 29, 1); +static PAD_ST_CONF(UART3_CTSB, 1, 27, 1); +static PAD_ST_CONF(UART3_RTSB, 1, 26, 1); +static PAD_ST_CONF(UART3_RX, 1, 25, 1); +static PAD_ST_CONF(UART2_RTSB, 1, 24, 1); +static PAD_ST_CONF(UART2_CTSB, 1, 23, 1); +static PAD_ST_CONF(UART2_RX, 1, 22, 1); +static PAD_ST_CONF(ETH_RXD0, 1, 21, 1); +static PAD_ST_CONF(ETH_RXD1, 1, 20, 1); +static PAD_ST_CONF(ETH_CRS_DV, 1, 19, 1); +static PAD_ST_CONF(ETH_RXER, 1, 18, 1); +static PAD_ST_CONF(ETH_TXD1, 1, 17, 1); +static PAD_ST_CONF(LVDS_OAP, 1, 12, 1); +static PAD_ST_CONF(PCM1_CLK, 1, 11, 1); +static PAD_ST_CONF(PCM1_IN, 1, 10, 1); +static PAD_ST_CONF(PCM1_SYNC, 1, 9, 1); +static PAD_ST_CONF(I2C1_SCLK, 1, 8, 1); +static PAD_ST_CONF(I2C1_SDATA, 1, 7, 1); +static PAD_ST_CONF(I2C2_SCLK, 1, 6, 1); +static PAD_ST_CONF(I2C2_SDATA, 1, 5, 1); +static PAD_ST_CONF(SPI0_MOSI, 1, 4, 1); +static PAD_ST_CONF(SPI0_MISO, 1, 3, 1); +static PAD_ST_CONF(SPI0_SS, 1, 2, 1); +static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1); +static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1); + +/* PAD_PULLCTL0 */ +static PAD_PULLCTL_CONF(PCM1_SYNC, 0, 30, 1); +static PAD_PULLCTL_CONF(PCM1_OUT, 0, 29, 1); +static PAD_PULLCTL_CONF(KS_OUT2, 0, 28, 1); +static PAD_PULLCTL_CONF(LCD0_D17, 0, 27, 1); +static PAD_PULLCTL_CONF(DSI_DN3, 0, 26, 1); +static PAD_PULLCTL_CONF(ETH_RXER, 0, 16, 1); +static PAD_PULLCTL_CONF(SIRQ0, 0, 14, 2); +static PAD_PULLCTL_CONF(SIRQ1, 0, 12, 2); +static PAD_PULLCTL_CONF(SIRQ2, 0, 10, 2); +static PAD_PULLCTL_CONF(I2C0_SDATA, 0, 9, 1); +static PAD_PULLCTL_CONF(I2C0_SCLK, 0, 8, 1); +static PAD_PULLCTL_CONF(KS_IN0, 0, 7, 1); +static PAD_PULLCTL_CONF(KS_IN1, 0, 6, 1); +static PAD_PULLCTL_CONF(KS_IN2, 0, 5, 1); +static PAD_PULLCTL_CONF(KS_IN3, 0, 4, 1); +static PAD_PULLCTL_CONF(KS_OUT0, 0, 2, 1); +static PAD_PULLCTL_CONF(KS_OUT1, 0, 1, 1); +static PAD_PULLCTL_CONF(DSI_DP1, 0, 0, 1); + +/* PAD_PULLCTL1 */ +static PAD_PULLCTL_CONF(DSI_CP, 1, 31, 1); +static PAD_PULLCTL_CONF(DSI_CN, 1, 30, 1); +static PAD_PULLCTL_CONF(DSI_DN2, 1, 28, 1); +static PAD_PULLCTL_CONF(DNAND_RDBN, 1, 25, 1); +static PAD_PULLCTL_CONF(SD0_D0, 1, 17, 1); +static PAD_PULLCTL_CONF(SD0_D1, 1, 16, 1); +static PAD_PULLCTL_CONF(SD0_D2, 1, 15, 1); +static PAD_PULLCTL_CONF(SD0_D3, 1, 14, 1); +static PAD_PULLCTL_CONF(SD0_CMD, 1, 13, 1); +static PAD_PULLCTL_CONF(SD0_CLK, 1, 12, 1); +static PAD_PULLCTL_CONF(SD1_CMD, 1, 11, 1); +static PAD_PULLCTL_CONF(SD1_D0, 1, 6, 1); +static PAD_PULLCTL_CONF(SD1_D1, 1, 5, 1); +static PAD_PULLCTL_CONF(SD1_D2, 1, 4, 1); +static PAD_PULLCTL_CONF(SD1_D3, 1, 3, 1); +static PAD_PULLCTL_CONF(UART0_RX, 1, 2, 1); +static PAD_PULLCTL_CONF(UART0_TX, 1, 1, 1); +static PAD_PULLCTL_CONF(CLKO_25M, 1, 0, 1); + +/* PAD_PULLCTL2 */ +static PAD_PULLCTL_CONF(SPI0_SCLK, 2, 12, 1); +static PAD_PULLCTL_CONF(SPI0_MOSI, 2, 11, 1); +static PAD_PULLCTL_CONF(I2C1_SDATA, 2, 10, 1); +static PAD_PULLCTL_CONF(I2C1_SCLK, 2, 9, 1); +static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 8, 1); +static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 7, 1); +static PAD_PULLCTL_CONF(DNAND_DQSN, 2, 5, 2); +static PAD_PULLCTL_CONF(DNAND_DQS, 2, 3, 2); +static PAD_PULLCTL_CONF(DNAND_D0, 2, 2, 1); +static PAD_PULLCTL_CONF(DNAND_D1, 2, 2, 1); +static PAD_PULLCTL_CONF(DNAND_D2, 2, 2, 1); +static PAD_PULLCTL_CONF(DNAND_D3, 2, 2, 1); +static PAD_PULLCTL_CONF(DNAND_D4, 2, 2, 1); +static PAD_PULLCTL_CONF(DNAND_D5, 2, 2, 1); +static PAD_PULLCTL_CONF(DNAND_D6, 2, 2, 1); +static PAD_PULLCTL_CONF(DNAND_D7, 2, 2, 1); + +/* Pad info table */ +static struct owl_padinfo s500_padinfo[NUM_PADS] = { + [DNAND_DQS] = PAD_INFO_PULLCTL(DNAND_DQS), + [DNAND_DQSN] = PAD_INFO_PULLCTL(DNAND_DQSN), + [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0), + [ETH_TXD1] = PAD_INFO_ST(ETH_TXD1), + [ETH_TXEN] = PAD_INFO_ST(ETH_TXEN), + [ETH_RXER] = PAD_INFO_PULLCTL_ST(ETH_RXER), + [ETH_CRS_DV] = PAD_INFO_ST(ETH_CRS_DV), + [ETH_RXD1] = PAD_INFO_ST(ETH_RXD1), + [ETH_RXD0] = PAD_INFO_ST(ETH_RXD0), + [ETH_REF_CLK] = PAD_INFO_ST(ETH_REF_CLK), + [ETH_MDC] = PAD_INFO(ETH_MDC), + [ETH_MDIO] = PAD_INFO(ETH_MDIO), + [SIRQ0] = PAD_INFO_PULLCTL(SIRQ0), + [SIRQ1] = PAD_INFO_PULLCTL(SIRQ1), + [SIRQ2] = PAD_INFO_PULLCTL(SIRQ2), + [I2S_D0] = PAD_INFO(I2S_D0), + [I2S_BCLK0] = PAD_INFO_ST(I2S_BCLK0), + [I2S_LRCLK0] = PAD_INFO_ST(I2S_LRCLK0), + [I2S_MCLK0] = PAD_INFO_ST(I2S_MCLK0), + [I2S_D1] = PAD_INFO(I2S_D1), + [I2S_BCLK1] = PAD_INFO(I2S_BCLK1), + [I2S_LRCLK1] = PAD_INFO_ST(I2S_LRCLK1), + [I2S_MCLK1] = PAD_INFO_ST(I2S_MCLK1), + [KS_IN0] = PAD_INFO_PULLCTL_ST(KS_IN0), + [KS_IN1] = PAD_INFO_PULLCTL(KS_IN1), + [KS_IN2] = PAD_INFO_PULLCTL(KS_IN2), + [KS_IN3] = PAD_INFO_PULLCTL(KS_IN3), + [KS_OUT0] = PAD_INFO_PULLCTL_ST(KS_OUT0), + [KS_OUT1] = PAD_INFO_PULLCTL_ST(KS_OUT1), + [KS_OUT2] = PAD_INFO_PULLCTL_ST(KS_OUT2), + [LVDS_OEP] = PAD_INFO(LVDS_OEP), + [LVDS_OEN] = PAD_INFO(LVDS_OEN), + [LVDS_ODP] = PAD_INFO(LVDS_ODP), + [LVDS_ODN] = PAD_INFO(LVDS_ODN), + [LVDS_OCP] = PAD_INFO(LVDS_OCP), + [LVDS_OCN] = PAD_INFO(LVDS_OCN), + [LVDS_OBP] = PAD_INFO(LVDS_OBP), + [LVDS_OBN] = PAD_INFO(LVDS_OBN), + [LVDS_OAP] = PAD_INFO_ST(LVDS_OAP), + [LVDS_OAN] = PAD_INFO(LVDS_OAN), + [LVDS_EEP] = PAD_INFO(LVDS_EEP), + [LVDS_EEN] = PAD_INFO(LVDS_EEN), + [LVDS_EDP] = PAD_INFO(LVDS_EDP), + [LVDS_EDN] = PAD_INFO(LVDS_EDN), + [LVDS_ECP] = PAD_INFO(LVDS_ECP), + [LVDS_ECN] = PAD_INFO(LVDS_ECN), + [LVDS_EBP] = PAD_INFO(LVDS_EBP), + [LVDS_EBN] = PAD_INFO(LVDS_EBN), + [LVDS_EAP] = PAD_INFO(LVDS_EAP), + [LVDS_EAN] = PAD_INFO(LVDS_EAN), + [LCD0_D18] = PAD_INFO(LCD0_D18), + [LCD0_D17] = PAD_INFO_PULLCTL(LCD0_D17), + [DSI_DP3] = PAD_INFO(DSI_DP3), + [DSI_DN3] = PAD_INFO_PULLCTL(DSI_DN3), + [DSI_DP1] = PAD_INFO_PULLCTL(DSI_DP1), + [DSI_DN1] = PAD_INFO(DSI_DN1), + [DSI_CP] = PAD_INFO_PULLCTL(DSI_CP), + [DSI_CN] = PAD_INFO_PULLCTL(DSI_CN), + [DSI_DP0] = PAD_INFO_ST(DSI_DP0), + [DSI_DN0] = PAD_INFO_ST(DSI_DN0), + [DSI_DP2] = PAD_INFO_ST(DSI_DP2), + [DSI_DN2] = PAD_INFO_PULLCTL_ST(DSI_DN2), + [SD0_D0] = PAD_INFO_PULLCTL(SD0_D0), + [SD0_D1] = PAD_INFO_PULLCTL(SD0_D1), + [SD0_D2] = PAD_INFO_PULLCTL(SD0_D2), + [SD0_D3] = PAD_INFO_PULLCTL(SD0_D3), + [SD1_D0] = PAD_INFO_PULLCTL(SD1_D0), + [SD1_D1] = PAD_INFO_PULLCTL(SD1_D1), + [SD1_D2] = PAD_INFO_PULLCTL(SD1_D2), + [SD1_D3] = PAD_INFO_PULLCTL(SD1_D3), + [SD0_CMD] = PAD_INFO_PULLCTL(SD0_CMD), + [SD0_CLK] = PAD_INFO_PULLCTL_ST(SD0_CLK), + [SD1_CMD] = PAD_INFO_PULLCTL(SD1_CMD), + [SD1_CLK] = PAD_INFO(SD1_CLK), + [SPI0_SCLK] = PAD_INFO_PULLCTL_ST(SPI0_SCLK), + [SPI0_SS] = PAD_INFO_ST(SPI0_SS), + [SPI0_MISO] = PAD_INFO_ST(SPI0_MISO), + [SPI0_MOSI] = PAD_INFO_PULLCTL_ST(SPI0_MOSI), + [UART0_RX] = PAD_INFO_PULLCTL_ST(UART0_RX), + [UART0_TX] = PAD_INFO_PULLCTL_ST(UART0_TX), + [I2C0_SCLK] = PAD_INFO_PULLCTL_ST(I2C0_SCLK), + [I2C0_SDATA] = PAD_INFO_PULLCTL_ST(I2C0_SDATA), + [SENSOR0_PCLK] = PAD_INFO_ST(SENSOR0_PCLK), + [SENSOR0_CKOUT] = PAD_INFO(SENSOR0_CKOUT), + [DNAND_ALE] = PAD_INFO(DNAND_ALE), + [DNAND_CLE] = PAD_INFO(DNAND_CLE), + [DNAND_CEB0] = PAD_INFO(DNAND_CEB0), + [DNAND_CEB1] = PAD_INFO(DNAND_CEB1), + [DNAND_CEB2] = PAD_INFO(DNAND_CEB2), + [DNAND_CEB3] = PAD_INFO(DNAND_CEB3), + [UART2_RX] = PAD_INFO_ST(UART2_RX), + [UART2_TX] = PAD_INFO(UART2_TX), + [UART2_RTSB] = PAD_INFO_ST(UART2_RTSB), + [UART2_CTSB] = PAD_INFO_ST(UART2_CTSB), + [UART3_RX] = PAD_INFO_ST(UART3_RX), + [UART3_TX] = PAD_INFO(UART3_TX), + [UART3_RTSB] = PAD_INFO_ST(UART3_RTSB), + [UART3_CTSB] = PAD_INFO_ST(UART3_CTSB), + [PCM1_IN] = PAD_INFO_ST(PCM1_IN), + [PCM1_CLK] = PAD_INFO_ST(PCM1_CLK), + [PCM1_SYNC] = PAD_INFO_PULLCTL_ST(PCM1_SYNC), + [PCM1_OUT] = PAD_INFO_PULLCTL(PCM1_OUT), + [I2C1_SCLK] = PAD_INFO_PULLCTL_ST(I2C1_SCLK), + [I2C1_SDATA] = PAD_INFO_PULLCTL_ST(I2C1_SDATA), + [I2C2_SCLK] = PAD_INFO_PULLCTL_ST(I2C2_SCLK), + [I2C2_SDATA] = PAD_INFO_PULLCTL_ST(I2C2_SDATA), + [CSI_DN0] = PAD_INFO(CSI_DN0), + [CSI_DP0] = PAD_INFO(CSI_DP0), + [CSI_DN1] = PAD_INFO(CSI_DN1), + [CSI_DP1] = PAD_INFO(CSI_DP1), + [CSI_CN] = PAD_INFO(CSI_CN), + [CSI_CP] = PAD_INFO(CSI_CP), + [CSI_DN2] = PAD_INFO(CSI_DN2), + [CSI_DP2] = PAD_INFO(CSI_DP2), + [CSI_DN3] = PAD_INFO(CSI_DN3), + [CSI_DP3] = PAD_INFO(CSI_DP3), + [DNAND_D0] = PAD_INFO_PULLCTL(DNAND_D0), + [DNAND_D1] = PAD_INFO_PULLCTL(DNAND_D1), + [DNAND_D2] = PAD_INFO_PULLCTL(DNAND_D2), + [DNAND_D3] = PAD_INFO_PULLCTL(DNAND_D3), + [DNAND_D4] = PAD_INFO_PULLCTL(DNAND_D4), + [DNAND_D5] = PAD_INFO_PULLCTL(DNAND_D5), + [DNAND_D6] = PAD_INFO_PULLCTL(DNAND_D6), + [DNAND_D7] = PAD_INFO_PULLCTL(DNAND_D7), + [DNAND_WRB] = PAD_INFO(DNAND_WRB), + [DNAND_RDB] = PAD_INFO(DNAND_RDB), + [DNAND_RDBN] = PAD_INFO_PULLCTL(DNAND_RDBN), + [DNAND_RB] = PAD_INFO(DNAND_RB), + [PORB] = PAD_INFO(PORB), + [CLKO_25M] = PAD_INFO_PULLCTL(CLKO_25M), + [BSEL] = PAD_INFO(BSEL), + [PKG0] = PAD_INFO(PKG0), + [PKG1] = PAD_INFO(PKG1), + [PKG2] = PAD_INFO(PKG2), + [PKG3] = PAD_INFO(PKG3), +}; + +static const struct owl_gpio_port s500_gpio_ports[] = { + OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x230, 0), + OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x1F8, 0x204, 0x208, 0x22C, 1), + OWL_GPIO_PORT(C, 0x0018, 32, 0x0, 0x4, 0x8, 0x1EC, 0x200, 0x204, 0x228, 2), + OWL_GPIO_PORT(D, 0x0024, 32, 0x0, 0x4, 0x8, 0x1E0, 0x1FC, 0x200, 0x224, 3), + OWL_GPIO_PORT(E, 0x0030, 4, 0x0, 0x4, 0x8, 0x1D4, 0x1F8, 0x1FC, 0x220, 4), +}; + +enum s500_pinconf_pull { + OWL_PINCONF_PULL_DOWN, + OWL_PINCONF_PULL_UP, +}; + +static int s500_pad_pinconf_arg2val(const struct owl_padinfo *info, + unsigned int param, u32 *arg) +{ + switch (param) { + case PIN_CONFIG_BIAS_PULL_DOWN: + *arg = OWL_PINCONF_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_PULL_UP: + *arg = OWL_PINCONF_PULL_UP; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + *arg = (*arg >= 1 ? 1 : 0); + break; + default: + return -EOPNOTSUPP; + } + + return 0; +} + +static int s500_pad_pinconf_val2arg(const struct owl_padinfo *padinfo, + unsigned int param, u32 *arg) +{ + switch (param) { + case PIN_CONFIG_BIAS_PULL_DOWN: + *arg = *arg == OWL_PINCONF_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_PULL_UP: + *arg = *arg == OWL_PINCONF_PULL_UP; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + *arg = *arg == 1; + break; + default: + return -EOPNOTSUPP; + } + + return 0; +} + +static struct owl_pinctrl_soc_data s500_pinctrl_data = { + .padinfo = s500_padinfo, + .pins = (const struct pinctrl_pin_desc *)s500_pads, + .npins = ARRAY_SIZE(s500_pads), + .functions = s500_functions, + .nfunctions = ARRAY_SIZE(s500_functions), + .groups = s500_groups, + .ngroups = ARRAY_SIZE(s500_groups), + .ngpios = NUM_GPIOS, + .ports = s500_gpio_ports, + .nports = ARRAY_SIZE(s500_gpio_ports), + .padctl_arg2val = s500_pad_pinconf_arg2val, + .padctl_val2arg = s500_pad_pinconf_val2arg, +}; + +static int s500_pinctrl_probe(struct platform_device *pdev) +{ + return owl_pinctrl_probe(pdev, &s500_pinctrl_data); +} + +static const struct of_device_id s500_pinctrl_of_match[] = { + { .compatible = "actions,s500-pinctrl", }, + { } +}; + +static struct platform_driver s500_pinctrl_driver = { + .driver = { + .name = "pinctrl-s500", + .of_match_table = of_match_ptr(s500_pinctrl_of_match), + }, + .probe = s500_pinctrl_probe, +}; + +static int __init s500_pinctrl_init(void) +{ + return platform_driver_register(&s500_pinctrl_driver); +} +arch_initcall(s500_pinctrl_init); + +static void __exit s500_pinctrl_exit(void) +{ + platform_driver_unregister(&s500_pinctrl_driver); +} +module_exit(s500_pinctrl_exit); + +MODULE_AUTHOR("Actions Semi Inc."); +MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@gmail.com>"); +MODULE_DESCRIPTION("Actions Semi S500 SoC Pinctrl Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/actions/pinctrl-s700.c b/drivers/pinctrl/actions/pinctrl-s700.c index f579a6593f37..fd00940a5799 100644 --- a/drivers/pinctrl/actions/pinctrl-s700.c +++ b/drivers/pinctrl/actions/pinctrl-s700.c @@ -1685,7 +1685,7 @@ static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 8, 1); static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 7, 1); /* Pad info table for the pinmux subsystem */ -static struct owl_padinfo s700_padinfo[NUM_PADS] = { +static const struct owl_padinfo s700_padinfo[NUM_PADS] = { [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0), [ETH_TXD1] = PAD_INFO_ST(ETH_TXD1), [ETH_TXEN] = PAD_INFO_ST(ETH_TXEN), diff --git a/drivers/pinctrl/actions/pinctrl-s900.c b/drivers/pinctrl/actions/pinctrl-s900.c index 9492b86852e7..811249a8011e 100644 --- a/drivers/pinctrl/actions/pinctrl-s900.c +++ b/drivers/pinctrl/actions/pinctrl-s900.c @@ -1556,7 +1556,7 @@ static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1); static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1); /* Pad info table */ -static struct owl_padinfo s900_padinfo[NUM_PADS] = { +static const struct owl_padinfo s900_padinfo[NUM_PADS] = { [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0), [ETH_TXD1] = PAD_INFO_ST(ETH_TXD1), [ETH_TXEN] = PAD_INFO_ST(ETH_TXEN), diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c index 5eff8c296552..3fb238714718 100644 --- a/drivers/pinctrl/devicetree.c +++ b/drivers/pinctrl/devicetree.c @@ -130,9 +130,8 @@ static int dt_to_map_one_config(struct pinctrl *p, if (!np_pctldev || of_node_is_root(np_pctldev)) { of_node_put(np_pctldev); ret = driver_deferred_probe_check_state(p->dev); - /* keep deferring if modules are enabled unless we've timed out */ - if (IS_ENABLED(CONFIG_MODULES) && !allow_default && - (ret == -ENODEV)) + /* keep deferring if modules are enabled */ + if (IS_ENABLED(CONFIG_MODULES) && !allow_default && ret < 0) ret = -EPROBE_DEFER; return ret; } diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 1cedc5f2aadb..7d336370d767 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -133,6 +133,13 @@ config PINCTRL_MT8183 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS +config PINCTRL_MT8192 + bool "Mediatek MT8192 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_PARIS + config PINCTRL_MT8516 bool "Mediatek MT8516 pin control" depends on OF diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index b0b07c541d11..1966a5299da4 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -19,5 +19,6 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o +obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8192.c b/drivers/pinctrl/mediatek/pinctrl-mt8192.c new file mode 100644 index 000000000000..0c16b2c756bf --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c @@ -0,0 +1,1409 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Zhiyong Tao <zhiyong.tao@mediatek.com> + * + */ + +#include <linux/module.h> +#include "pinctrl-mtk-mt8192.h" +#include "pinctrl-paris.h" + +/* MT8192 have multiple bases to program pin configuration listed as the below: + * iocfg0:0x10005000, iocfg_rm:0x11C20000, iocfg_bm:0x11D10000, + * iocfg_bl:0x11D30000, iocfg_br:0x11D40000, iocfg_lm:0x11E20000, + * iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000, iocfg_lt:0x11F20000, + * iocfg_tl:0x11F30000 + * _i_based could be used to indicate what base the pin should be mapped into. + */ + +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 0) + +#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 1) + +static const struct mtk_pin_field_calc mt8192_pin_mode_range[] = { + PIN_FIELD(0, 228, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt8192_pin_dir_range[] = { + PIN_FIELD(0, 228, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_di_range[] = { + PIN_FIELD(0, 228, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_do_range[] = { + PIN_FIELD(0, 228, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, 4, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(1, 1, 4, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(2, 2, 4, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(3, 3, 4, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(4, 4, 4, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(5, 5, 4, 0x00f0, 0x10, 9, 1), + PIN_FIELD_BASE(6, 6, 4, 0x00f0, 0x10, 9, 1), + PIN_FIELD_BASE(7, 7, 4, 0x00f0, 0x10, 9, 1), + PIN_FIELD_BASE(8, 8, 4, 0x00f0, 0x10, 9, 1), + PIN_FIELD_BASE(9, 9, 4, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(10, 10, 6, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, 6, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(12, 12, 6, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(14, 14, 6, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(16, 16, 8, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(17, 17, 8, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(18, 18, 7, 0x0100, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, 7, 0x0100, 0x10, 4, 1), + PIN_FIELD_BASE(20, 20, 7, 0x0100, 0x10, 5, 1), + PIN_FIELD_BASE(21, 21, 7, 0x0100, 0x10, 5, 1), + PIN_FIELD_BASE(22, 22, 2, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(23, 23, 2, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(24, 24, 2, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(25, 25, 2, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(26, 26, 3, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(27, 27, 3, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(28, 28, 3, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(29, 29, 3, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(30, 30, 3, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(31, 31, 3, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(32, 32, 3, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(33, 33, 3, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(34, 34, 3, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(35, 35, 3, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(36, 36, 2, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(37, 37, 2, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(38, 38, 2, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(39, 39, 2, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(40, 40, 8, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 8, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 8, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, 7, 0x0100, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, 7, 0x0100, 0x10, 4, 1), + PIN_FIELD_BASE(45, 45, 1, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(46, 46, 1, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(47, 47, 1, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(48, 48, 1, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(49, 49, 1, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(50, 50, 1, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(51, 51, 1, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(52, 52, 1, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(53, 53, 1, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(54, 54, 1, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(55, 55, 1, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(56, 56, 1, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(57, 57, 3, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(58, 58, 3, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(59, 59, 3, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(60, 60, 3, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(61, 61, 3, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(62, 62, 3, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(63, 63, 3, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(64, 64, 3, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(65, 65, 3, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(66, 66, 3, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(67, 67, 3, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(68, 68, 3, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(69, 69, 3, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 3, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(71, 71, 3, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(72, 72, 3, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(73, 73, 3, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(74, 74, 3, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, 3, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(76, 76, 3, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(77, 77, 3, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(78, 78, 3, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(79, 79, 3, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(80, 80, 3, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(81, 81, 3, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(82, 82, 3, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(83, 83, 3, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(84, 84, 3, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(85, 85, 3, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(86, 86, 3, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(87, 87, 3, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(88, 88, 3, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(89, 89, 2, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(90, 90, 2, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(91, 91, 2, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(92, 92, 2, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(93, 93, 2, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(94, 94, 2, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(95, 95, 2, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(96, 96, 2, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(97, 97, 2, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(98, 98, 2, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(99, 99, 2, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(100, 100, 2, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(101, 101, 2, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(102, 102, 2, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(103, 103, 2, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(104, 104, 2, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(105, 105, 2, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(106, 106, 2, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(107, 107, 2, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(108, 108, 2, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(109, 109, 2, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(110, 110, 2, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(111, 111, 2, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, 2, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(113, 113, 2, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(114, 114, 2, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(115, 115, 2, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(116, 116, 2, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(117, 117, 2, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(118, 118, 4, 0x00f0, 0x10, 12, 1), + PIN_FIELD_BASE(119, 119, 4, 0x00f0, 0x10, 18, 1), + PIN_FIELD_BASE(120, 120, 4, 0x00f0, 0x10, 17, 1), + PIN_FIELD_BASE(121, 121, 4, 0x00f0, 0x10, 23, 1), + PIN_FIELD_BASE(122, 122, 4, 0x00f0, 0x10, 16, 1), + PIN_FIELD_BASE(123, 123, 4, 0x00f0, 0x10, 22, 1), + PIN_FIELD_BASE(124, 124, 4, 0x00f0, 0x10, 15, 1), + PIN_FIELD_BASE(125, 125, 4, 0x00f0, 0x10, 21, 1), + PIN_FIELD_BASE(126, 126, 4, 0x00f0, 0x10, 6, 1), + PIN_FIELD_BASE(127, 127, 4, 0x00f0, 0x10, 7, 1), + PIN_FIELD_BASE(128, 128, 4, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(129, 129, 4, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(130, 130, 4, 0x00f0, 0x10, 3, 1), + PIN_FIELD_BASE(131, 131, 4, 0x00f0, 0x10, 4, 1), + PIN_FIELD_BASE(132, 132, 4, 0x00f0, 0x10, 11, 1), + PIN_FIELD_BASE(133, 133, 4, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(134, 134, 4, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(135, 135, 4, 0x00f0, 0x10, 11, 1), + PIN_FIELD_BASE(136, 136, 4, 0x00f0, 0x10, 0, 1), + PIN_FIELD_BASE(137, 137, 4, 0x00f0, 0x10, 1, 1), + PIN_FIELD_BASE(138, 138, 4, 0x00f0, 0x10, 2, 1), + PIN_FIELD_BASE(139, 139, 4, 0x00f0, 0x10, 14, 1), + PIN_FIELD_BASE(140, 140, 4, 0x00f0, 0x10, 20, 1), + PIN_FIELD_BASE(141, 141, 4, 0x00f0, 0x10, 13, 1), + PIN_FIELD_BASE(142, 142, 4, 0x00f0, 0x10, 19, 1), + PIN_FIELD_BASE(143, 143, 1, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(144, 144, 1, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(145, 145, 1, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(146, 146, 1, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(147, 147, 1, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(148, 148, 1, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(149, 149, 1, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(150, 150, 1, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(151, 151, 1, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(152, 152, 7, 0x0100, 0x10, 6, 1), + PIN_FIELD_BASE(153, 153, 7, 0x0100, 0x10, 6, 1), + PIN_FIELD_BASE(154, 154, 7, 0x0100, 0x10, 6, 1), + PIN_FIELD_BASE(155, 155, 7, 0x0100, 0x10, 6, 1), + PIN_FIELD_BASE(156, 156, 7, 0x0100, 0x10, 7, 1), + PIN_FIELD_BASE(157, 157, 7, 0x0100, 0x10, 7, 1), + PIN_FIELD_BASE(158, 158, 7, 0x0100, 0x10, 7, 1), + PIN_FIELD_BASE(159, 159, 7, 0x0100, 0x10, 7, 1), + PIN_FIELD_BASE(160, 160, 7, 0x0100, 0x10, 12, 1), + PIN_FIELD_BASE(161, 161, 7, 0x0100, 0x10, 13, 1), + PIN_FIELD_BASE(162, 162, 7, 0x0100, 0x10, 0, 1), + PIN_FIELD_BASE(163, 163, 7, 0x0100, 0x10, 1, 1), + PIN_FIELD_BASE(164, 164, 7, 0x0100, 0x10, 8, 1), + PIN_FIELD_BASE(165, 165, 7, 0x0100, 0x10, 8, 1), + PIN_FIELD_BASE(166, 166, 7, 0x0100, 0x10, 8, 1), + PIN_FIELD_BASE(167, 167, 7, 0x0100, 0x10, 8, 1), + PIN_FIELD_BASE(168, 168, 7, 0x0100, 0x10, 2, 1), + PIN_FIELD_BASE(169, 169, 7, 0x0100, 0x10, 3, 1), + PIN_FIELD_BASE(170, 170, 7, 0x0100, 0x10, 8, 1), + PIN_FIELD_BASE(171, 171, 7, 0x0100, 0x10, 8, 1), + PIN_FIELD_BASE(172, 172, 7, 0x0100, 0x10, 9, 1), + PIN_FIELD_BASE(173, 173, 7, 0x0100, 0x10, 10, 1), + PIN_FIELD_BASE(174, 174, 7, 0x0100, 0x10, 9, 1), + PIN_FIELD_BASE(175, 175, 7, 0x0100, 0x10, 10, 1), + PIN_FIELD_BASE(176, 176, 7, 0x0100, 0x10, 9, 1), + PIN_FIELD_BASE(177, 177, 7, 0x0100, 0x10, 9, 1), + PIN_FIELD_BASE(178, 178, 7, 0x0100, 0x10, 10, 1), + PIN_FIELD_BASE(179, 179, 7, 0x0100, 0x10, 10, 1), + PIN_FIELD_BASE(180, 180, 7, 0x0100, 0x10, 11, 1), + PIN_FIELD_BASE(181, 181, 7, 0x0100, 0x10, 11, 1), + PIN_FIELD_BASE(182, 182, 7, 0x0100, 0x10, 11, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(195, 195, 5, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(196, 196, 5, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(197, 197, 5, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(198, 198, 5, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(199, 199, 5, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(206, 206, 5, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(207, 207, 5, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(208, 208, 5, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(209, 209, 5, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(210, 210, 5, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(211, 211, 5, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(212, 212, 5, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(213, 213, 5, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(214, 214, 5, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(215, 215, 5, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(216, 216, 5, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(217, 217, 5, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(218, 218, 5, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(219, 219, 5, 0x0080, 0x10, 4, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, 4, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(1, 1, 4, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, 4, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, 4, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(4, 4, 4, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(5, 5, 4, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(6, 6, 4, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(7, 7, 4, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(8, 8, 4, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(9, 9, 4, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(10, 10, 6, 0x0010, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, 6, 0x0010, 0x10, 1, 1), + PIN_FIELD_BASE(12, 12, 6, 0x0010, 0x10, 2, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0010, 0x10, 3, 1), + PIN_FIELD_BASE(14, 14, 6, 0x0010, 0x10, 4, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0010, 0x10, 5, 1), + PIN_FIELD_BASE(16, 16, 8, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(17, 17, 8, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(18, 18, 7, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(19, 19, 7, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(20, 20, 7, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(21, 21, 7, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(22, 22, 2, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(23, 23, 2, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(24, 24, 2, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(26, 26, 3, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(27, 27, 3, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, 3, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, 3, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, 3, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, 3, 0x0030, 0x10, 27, 1), + PIN_FIELD_BASE(32, 32, 3, 0x0030, 0x10, 24, 1), + PIN_FIELD_BASE(33, 33, 3, 0x0030, 0x10, 26, 1), + PIN_FIELD_BASE(34, 34, 3, 0x0030, 0x10, 23, 1), + PIN_FIELD_BASE(35, 35, 3, 0x0030, 0x10, 25, 1), + PIN_FIELD_BASE(36, 36, 2, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(37, 37, 2, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(38, 38, 2, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(39, 39, 2, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(40, 40, 8, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 8, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(42, 42, 8, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(43, 43, 7, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(44, 44, 7, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(45, 45, 1, 0x0030, 0x10, 18, 1), + PIN_FIELD_BASE(46, 46, 1, 0x0030, 0x10, 20, 1), + PIN_FIELD_BASE(47, 47, 1, 0x0030, 0x10, 19, 1), + PIN_FIELD_BASE(48, 48, 1, 0x0030, 0x10, 16, 1), + PIN_FIELD_BASE(49, 49, 1, 0x0030, 0x10, 17, 1), + PIN_FIELD_BASE(50, 50, 1, 0x0030, 0x10, 15, 1), + PIN_FIELD_BASE(51, 51, 1, 0x0030, 0x10, 9, 1), + PIN_FIELD_BASE(52, 52, 1, 0x0030, 0x10, 10, 1), + PIN_FIELD_BASE(53, 53, 1, 0x0030, 0x10, 14, 1), + PIN_FIELD_BASE(54, 54, 1, 0x0030, 0x10, 11, 1), + PIN_FIELD_BASE(55, 55, 1, 0x0030, 0x10, 13, 1), + PIN_FIELD_BASE(56, 56, 1, 0x0030, 0x10, 12, 1), + PIN_FIELD_BASE(57, 57, 3, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(58, 58, 3, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(59, 59, 3, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(60, 60, 3, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0030, 0x10, 28, 1), + PIN_FIELD_BASE(62, 62, 3, 0x0030, 0x10, 22, 1), + PIN_FIELD_BASE(63, 63, 3, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(64, 64, 3, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(65, 65, 3, 0x0030, 0x10, 12, 1), + PIN_FIELD_BASE(66, 66, 3, 0x0030, 0x10, 15, 1), + PIN_FIELD_BASE(67, 67, 3, 0x0030, 0x10, 16, 1), + PIN_FIELD_BASE(68, 68, 3, 0x0030, 0x10, 17, 1), + PIN_FIELD_BASE(69, 69, 3, 0x0030, 0x10, 18, 1), + PIN_FIELD_BASE(70, 70, 3, 0x0030, 0x10, 19, 1), + PIN_FIELD_BASE(71, 71, 3, 0x0030, 0x10, 20, 1), + PIN_FIELD_BASE(72, 72, 3, 0x0030, 0x10, 21, 1), + PIN_FIELD_BASE(73, 73, 3, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(74, 74, 3, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(75, 75, 3, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(76, 76, 3, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(77, 77, 3, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0030, 0x10, 9, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0030, 0x10, 10, 1), + PIN_FIELD_BASE(82, 82, 3, 0x0030, 0x10, 11, 1), + PIN_FIELD_BASE(83, 83, 3, 0x0030, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0030, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, 3, 0x0030, 0x10, 31, 1), + PIN_FIELD_BASE(86, 86, 3, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(87, 87, 3, 0x0030, 0x10, 29, 1), + PIN_FIELD_BASE(88, 88, 3, 0x0030, 0x10, 30, 1), + PIN_FIELD_BASE(89, 89, 2, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(90, 90, 2, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(91, 91, 2, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(92, 92, 2, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(93, 93, 2, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(94, 94, 2, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(95, 95, 2, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0050, 0x10, 31, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(98, 98, 2, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(99, 99, 2, 0x0050, 0x10, 27, 1), + PIN_FIELD_BASE(100, 100, 2, 0x0050, 0x10, 28, 1), + PIN_FIELD_BASE(101, 101, 2, 0x0050, 0x10, 29, 1), + PIN_FIELD_BASE(102, 102, 2, 0x0050, 0x10, 30, 1), + PIN_FIELD_BASE(103, 103, 2, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(104, 104, 2, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(105, 105, 2, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(106, 106, 2, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(107, 107, 2, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(108, 108, 2, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(109, 109, 2, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(110, 110, 2, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(111, 111, 2, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(112, 112, 2, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(113, 113, 2, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(114, 114, 2, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(115, 115, 2, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(116, 116, 2, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(117, 117, 2, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(118, 118, 4, 0x0070, 0x10, 23, 1), + PIN_FIELD_BASE(119, 119, 4, 0x0070, 0x10, 29, 1), + PIN_FIELD_BASE(120, 120, 4, 0x0070, 0x10, 28, 1), + PIN_FIELD_BASE(121, 121, 4, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(122, 122, 4, 0x0070, 0x10, 27, 1), + PIN_FIELD_BASE(123, 123, 4, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(124, 124, 4, 0x0070, 0x10, 26, 1), + PIN_FIELD_BASE(125, 125, 4, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(126, 126, 4, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(127, 127, 4, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(128, 128, 4, 0x0070, 0x10, 21, 1), + PIN_FIELD_BASE(129, 129, 4, 0x0070, 0x10, 22, 1), + PIN_FIELD_BASE(130, 130, 4, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(131, 131, 4, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(132, 132, 4, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(133, 133, 4, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(134, 134, 4, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(135, 135, 4, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(136, 136, 4, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(137, 137, 4, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(138, 138, 4, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(139, 139, 4, 0x0070, 0x10, 25, 1), + PIN_FIELD_BASE(140, 140, 4, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(141, 141, 4, 0x0070, 0x10, 24, 1), + PIN_FIELD_BASE(142, 142, 4, 0x0070, 0x10, 30, 1), + PIN_FIELD_BASE(143, 143, 1, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(144, 144, 1, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(145, 145, 1, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(146, 146, 1, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(147, 147, 1, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(148, 148, 1, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(149, 149, 1, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(150, 150, 1, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(151, 151, 1, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(152, 152, 7, 0x0050, 0x10, 30, 1), + PIN_FIELD_BASE(153, 153, 7, 0x0050, 0x10, 29, 1), + PIN_FIELD_BASE(154, 154, 7, 0x0050, 0x10, 27, 1), + PIN_FIELD_BASE(155, 155, 7, 0x0050, 0x10, 28, 1), + PIN_FIELD_BASE(156, 156, 7, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(157, 157, 7, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(158, 158, 7, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(159, 159, 7, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(160, 160, 7, 0x0050, 0x10, 31, 1), + PIN_FIELD_BASE(161, 161, 7, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(162, 162, 7, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(163, 163, 7, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(164, 164, 7, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(165, 165, 7, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(166, 166, 7, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(167, 167, 7, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(168, 168, 7, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(169, 169, 7, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(170, 170, 7, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(171, 171, 7, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(172, 172, 7, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(173, 173, 7, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(174, 174, 7, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(175, 175, 7, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(176, 176, 7, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(177, 177, 7, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(178, 178, 7, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(179, 179, 7, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(180, 180, 7, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(181, 181, 7, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(182, 182, 7, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0020, 0x10, 1, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0020, 0x10, 4, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0020, 0x10, 6, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0020, 0x10, 8, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0020, 0x10, 3, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0020, 0x10, 7, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0020, 0x10, 9, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0020, 0x10, 10, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0020, 0x10, 5, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0020, 0x10, 11, 1), + PIN_FIELD_BASE(195, 195, 5, 0x0030, 0x10, 16, 1), + PIN_FIELD_BASE(196, 196, 5, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(197, 197, 5, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(198, 198, 5, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(199, 199, 5, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0030, 0x10, 15, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0030, 0x10, 17, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(206, 206, 5, 0x0030, 0x10, 18, 1), + PIN_FIELD_BASE(207, 207, 5, 0x0030, 0x10, 19, 1), + PIN_FIELD_BASE(208, 208, 5, 0x0030, 0x10, 20, 1), + PIN_FIELD_BASE(209, 209, 5, 0x0030, 0x10, 12, 1), + PIN_FIELD_BASE(210, 210, 5, 0x0030, 0x10, 11, 1), + PIN_FIELD_BASE(211, 211, 5, 0x0030, 0x10, 13, 1), + PIN_FIELD_BASE(212, 212, 5, 0x0030, 0x10, 10, 1), + PIN_FIELD_BASE(213, 213, 5, 0x0030, 0x10, 14, 1), + PIN_FIELD_BASE(214, 214, 5, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(215, 215, 5, 0x0030, 0x10, 9, 1), + PIN_FIELD_BASE(216, 216, 5, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(217, 217, 5, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(218, 218, 5, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(219, 219, 5, 0x0030, 0x10, 2, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_pu_range[] = { + PIN_FIELD_BASE(0, 0, 4, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(1, 1, 4, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, 4, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, 4, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(4, 4, 4, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(5, 5, 4, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(6, 6, 4, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(7, 7, 4, 0x00b0, 0x10, 16, 1), + PIN_FIELD_BASE(8, 8, 4, 0x00b0, 0x10, 17, 1), + PIN_FIELD_BASE(9, 9, 4, 0x00b0, 0x10, 18, 1), + PIN_FIELD_BASE(16, 16, 8, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(17, 17, 8, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(18, 18, 7, 0x00a0, 0x10, 21, 1), + PIN_FIELD_BASE(19, 19, 7, 0x00a0, 0x10, 22, 1), + PIN_FIELD_BASE(20, 20, 7, 0x00a0, 0x10, 23, 1), + PIN_FIELD_BASE(21, 21, 7, 0x00a0, 0x10, 24, 1), + PIN_FIELD_BASE(22, 22, 2, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(23, 23, 2, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(24, 24, 2, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(26, 26, 3, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(27, 27, 3, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, 3, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, 3, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, 3, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, 3, 0x0070, 0x10, 27, 1), + PIN_FIELD_BASE(32, 32, 3, 0x0070, 0x10, 24, 1), + PIN_FIELD_BASE(33, 33, 3, 0x0070, 0x10, 26, 1), + PIN_FIELD_BASE(34, 34, 3, 0x0070, 0x10, 23, 1), + PIN_FIELD_BASE(35, 35, 3, 0x0070, 0x10, 25, 1), + PIN_FIELD_BASE(36, 36, 2, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(37, 37, 2, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(38, 38, 2, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(39, 39, 2, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(40, 40, 8, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 8, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(42, 42, 8, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(43, 43, 7, 0x00a0, 0x10, 25, 1), + PIN_FIELD_BASE(44, 44, 7, 0x00a0, 0x10, 26, 1), + PIN_FIELD_BASE(57, 57, 3, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(58, 58, 3, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(59, 59, 3, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(60, 60, 3, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0070, 0x10, 28, 1), + PIN_FIELD_BASE(62, 62, 3, 0x0070, 0x10, 22, 1), + PIN_FIELD_BASE(63, 63, 3, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(64, 64, 3, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(65, 65, 3, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(66, 66, 3, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(67, 67, 3, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(68, 68, 3, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(69, 69, 3, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(70, 70, 3, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(71, 71, 3, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(72, 72, 3, 0x0070, 0x10, 21, 1), + PIN_FIELD_BASE(73, 73, 3, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(74, 74, 3, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(75, 75, 3, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(76, 76, 3, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(77, 77, 3, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(82, 82, 3, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(83, 83, 3, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, 3, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(86, 86, 3, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(87, 87, 3, 0x0070, 0x10, 29, 1), + PIN_FIELD_BASE(88, 88, 3, 0x0070, 0x10, 30, 1), + PIN_FIELD_BASE(89, 89, 2, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(90, 90, 2, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(91, 91, 2, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(92, 92, 2, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(93, 93, 2, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(94, 94, 2, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(95, 95, 2, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0090, 0x10, 31, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(98, 98, 2, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(99, 99, 2, 0x0090, 0x10, 27, 1), + PIN_FIELD_BASE(100, 100, 2, 0x0090, 0x10, 28, 1), + PIN_FIELD_BASE(101, 101, 2, 0x0090, 0x10, 29, 1), + PIN_FIELD_BASE(102, 102, 2, 0x0090, 0x10, 30, 1), + PIN_FIELD_BASE(103, 103, 2, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(104, 104, 2, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(105, 105, 2, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(106, 106, 2, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(107, 107, 2, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(108, 108, 2, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(109, 109, 2, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(110, 110, 2, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(111, 111, 2, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(112, 112, 2, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(113, 113, 2, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(114, 114, 2, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(115, 115, 2, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(116, 116, 2, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(117, 117, 2, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(118, 118, 4, 0x00b0, 0x10, 23, 1), + PIN_FIELD_BASE(119, 119, 4, 0x00b0, 0x10, 29, 1), + PIN_FIELD_BASE(120, 120, 4, 0x00b0, 0x10, 28, 1), + PIN_FIELD_BASE(121, 121, 4, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(122, 122, 4, 0x00b0, 0x10, 27, 1), + PIN_FIELD_BASE(123, 123, 4, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(124, 124, 4, 0x00b0, 0x10, 26, 1), + PIN_FIELD_BASE(125, 125, 4, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(126, 126, 4, 0x00b0, 0x10, 19, 1), + PIN_FIELD_BASE(127, 127, 4, 0x00b0, 0x10, 20, 1), + PIN_FIELD_BASE(128, 128, 4, 0x00b0, 0x10, 21, 1), + PIN_FIELD_BASE(129, 129, 4, 0x00b0, 0x10, 22, 1), + PIN_FIELD_BASE(130, 130, 4, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(131, 131, 4, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(132, 132, 4, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(133, 133, 4, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(134, 134, 4, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(135, 135, 4, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(136, 136, 4, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(137, 137, 4, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(138, 138, 4, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(139, 139, 4, 0x00b0, 0x10, 25, 1), + PIN_FIELD_BASE(140, 140, 4, 0x00b0, 0x10, 31, 1), + PIN_FIELD_BASE(141, 141, 4, 0x00b0, 0x10, 24, 1), + PIN_FIELD_BASE(142, 142, 4, 0x00b0, 0x10, 30, 1), + PIN_FIELD_BASE(143, 143, 1, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(144, 144, 1, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(145, 145, 1, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(146, 146, 1, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(147, 147, 1, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(148, 148, 1, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(149, 149, 1, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(150, 150, 1, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(151, 151, 1, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(156, 156, 7, 0x00a0, 0x10, 29, 1), + PIN_FIELD_BASE(157, 157, 7, 0x00a0, 0x10, 30, 1), + PIN_FIELD_BASE(158, 158, 7, 0x00a0, 0x10, 31, 1), + PIN_FIELD_BASE(159, 159, 7, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(160, 160, 7, 0x00a0, 0x10, 27, 1), + PIN_FIELD_BASE(161, 161, 7, 0x00a0, 0x10, 28, 1), + PIN_FIELD_BASE(162, 162, 7, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(163, 163, 7, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(164, 164, 7, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(165, 165, 7, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(166, 166, 7, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(167, 167, 7, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(168, 168, 7, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(169, 169, 7, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(170, 170, 7, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(171, 171, 7, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(172, 172, 7, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(173, 173, 7, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(174, 174, 7, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(175, 175, 7, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(176, 176, 7, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(177, 177, 7, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(178, 178, 7, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(179, 179, 7, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(180, 180, 7, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(181, 181, 7, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(182, 182, 7, 0x00a0, 0x10, 20, 1), + PIN_FIELD_BASE(195, 195, 5, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(196, 196, 5, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(197, 197, 5, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(198, 198, 5, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(199, 199, 5, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(206, 206, 5, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(207, 207, 5, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(208, 208, 5, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(209, 209, 5, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(210, 210, 5, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(211, 211, 5, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(212, 212, 5, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(213, 213, 5, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(214, 214, 5, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(215, 215, 5, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(216, 216, 5, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(217, 217, 5, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(218, 218, 5, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(219, 219, 5, 0x0050, 0x10, 2, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_pd_range[] = { + PIN_FIELD_BASE(0, 0, 4, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(1, 1, 4, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, 4, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, 4, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(4, 4, 4, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(5, 5, 4, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(6, 6, 4, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(7, 7, 4, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(8, 8, 4, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(9, 9, 4, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(16, 16, 8, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(17, 17, 8, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(18, 18, 7, 0x0070, 0x10, 21, 1), + PIN_FIELD_BASE(19, 19, 7, 0x0070, 0x10, 22, 1), + PIN_FIELD_BASE(20, 20, 7, 0x0070, 0x10, 23, 1), + PIN_FIELD_BASE(21, 21, 7, 0x0070, 0x10, 24, 1), + PIN_FIELD_BASE(22, 22, 2, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(23, 23, 2, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(24, 24, 2, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(26, 26, 3, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(27, 27, 3, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, 3, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, 3, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, 3, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, 3, 0x0050, 0x10, 27, 1), + PIN_FIELD_BASE(32, 32, 3, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(33, 33, 3, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(34, 34, 3, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(35, 35, 3, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(36, 36, 2, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(37, 37, 2, 0x0070, 0x10, 21, 1), + PIN_FIELD_BASE(38, 38, 2, 0x0070, 0x10, 22, 1), + PIN_FIELD_BASE(39, 39, 2, 0x0070, 0x10, 23, 1), + PIN_FIELD_BASE(40, 40, 8, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 8, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(42, 42, 8, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(43, 43, 7, 0x0070, 0x10, 25, 1), + PIN_FIELD_BASE(44, 44, 7, 0x0070, 0x10, 26, 1), + PIN_FIELD_BASE(57, 57, 3, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(58, 58, 3, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(59, 59, 3, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(60, 60, 3, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0050, 0x10, 28, 1), + PIN_FIELD_BASE(62, 62, 3, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(63, 63, 3, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(64, 64, 3, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(65, 65, 3, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(66, 66, 3, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(67, 67, 3, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(68, 68, 3, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(69, 69, 3, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(70, 70, 3, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(71, 71, 3, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(72, 72, 3, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(73, 73, 3, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(74, 74, 3, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(75, 75, 3, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(76, 76, 3, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(77, 77, 3, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(82, 82, 3, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(83, 83, 3, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, 3, 0x0050, 0x10, 31, 1), + PIN_FIELD_BASE(86, 86, 3, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(87, 87, 3, 0x0050, 0x10, 29, 1), + PIN_FIELD_BASE(88, 88, 3, 0x0050, 0x10, 30, 1), + PIN_FIELD_BASE(89, 89, 2, 0x0070, 0x10, 24, 1), + PIN_FIELD_BASE(90, 90, 2, 0x0070, 0x10, 25, 1), + PIN_FIELD_BASE(91, 91, 2, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(92, 92, 2, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(93, 93, 2, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(94, 94, 2, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(95, 95, 2, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0070, 0x10, 26, 1), + PIN_FIELD_BASE(98, 98, 2, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(99, 99, 2, 0x0070, 0x10, 27, 1), + PIN_FIELD_BASE(100, 100, 2, 0x0070, 0x10, 28, 1), + PIN_FIELD_BASE(101, 101, 2, 0x0070, 0x10, 29, 1), + PIN_FIELD_BASE(102, 102, 2, 0x0070, 0x10, 30, 1), + PIN_FIELD_BASE(103, 103, 2, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(104, 104, 2, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(105, 105, 2, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(106, 106, 2, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(107, 107, 2, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(108, 108, 2, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(109, 109, 2, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(110, 110, 2, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(111, 111, 2, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(112, 112, 2, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(113, 113, 2, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(114, 114, 2, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(115, 115, 2, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(116, 116, 2, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(117, 117, 2, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(118, 118, 4, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(119, 119, 4, 0x0090, 0x10, 29, 1), + PIN_FIELD_BASE(120, 120, 4, 0x0090, 0x10, 28, 1), + PIN_FIELD_BASE(121, 121, 4, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(122, 122, 4, 0x0090, 0x10, 27, 1), + PIN_FIELD_BASE(123, 123, 4, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(124, 124, 4, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(125, 125, 4, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(126, 126, 4, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(127, 127, 4, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(128, 128, 4, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(129, 129, 4, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(130, 130, 4, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(131, 131, 4, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(132, 132, 4, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(133, 133, 4, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(134, 134, 4, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(135, 135, 4, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(136, 136, 4, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(137, 137, 4, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(138, 138, 4, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(139, 139, 4, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(140, 140, 4, 0x0090, 0x10, 31, 1), + PIN_FIELD_BASE(141, 141, 4, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(142, 142, 4, 0x0090, 0x10, 30, 1), + PIN_FIELD_BASE(143, 143, 1, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(144, 144, 1, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(145, 145, 1, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(146, 146, 1, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(147, 147, 1, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(148, 148, 1, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(149, 149, 1, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(150, 150, 1, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(151, 151, 1, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(156, 156, 7, 0x0070, 0x10, 29, 1), + PIN_FIELD_BASE(157, 157, 7, 0x0070, 0x10, 30, 1), + PIN_FIELD_BASE(158, 158, 7, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(159, 159, 7, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(160, 160, 7, 0x0070, 0x10, 27, 1), + PIN_FIELD_BASE(161, 161, 7, 0x0070, 0x10, 28, 1), + PIN_FIELD_BASE(162, 162, 7, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(163, 163, 7, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(164, 164, 7, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(165, 165, 7, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(166, 166, 7, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(167, 167, 7, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(168, 168, 7, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(169, 169, 7, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(170, 170, 7, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(171, 171, 7, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(172, 172, 7, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(173, 173, 7, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(174, 174, 7, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(175, 175, 7, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(176, 176, 7, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(177, 177, 7, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(178, 178, 7, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(179, 179, 7, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(180, 180, 7, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(181, 181, 7, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(182, 182, 7, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(195, 195, 5, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(196, 196, 5, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(197, 197, 5, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(198, 198, 5, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(199, 199, 5, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(206, 206, 5, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(207, 207, 5, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(208, 208, 5, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(209, 209, 5, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(210, 210, 5, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(211, 211, 5, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(212, 212, 5, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(213, 213, 5, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(214, 214, 5, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(215, 215, 5, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(216, 216, 5, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(217, 217, 5, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(218, 218, 5, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(219, 219, 5, 0x0040, 0x10, 2, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, 4, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(1, 1, 4, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(2, 2, 4, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(3, 3, 4, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(4, 4, 4, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(5, 5, 4, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(6, 6, 4, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(7, 7, 4, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(8, 8, 4, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(9, 9, 4, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(10, 10, 6, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(11, 11, 6, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(12, 12, 6, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(13, 13, 6, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(14, 14, 6, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(15, 15, 6, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(16, 16, 8, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(17, 17, 8, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(18, 18, 7, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(19, 19, 7, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(20, 20, 7, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(21, 21, 7, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(22, 22, 2, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(23, 23, 2, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(24, 24, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(25, 25, 2, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(26, 26, 3, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(27, 27, 3, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(28, 28, 3, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(29, 29, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(30, 30, 3, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(31, 31, 3, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(32, 32, 3, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(33, 33, 3, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(34, 34, 3, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(35, 35, 3, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(36, 36, 2, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(37, 37, 2, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(38, 38, 2, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(39, 39, 2, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(40, 40, 8, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(41, 41, 8, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(42, 42, 8, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(43, 43, 7, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(44, 44, 7, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(45, 45, 1, 0x0010, 0x10, 6, 2), + PIN_FIELD_BASE(46, 46, 1, 0x0010, 0x10, 6, 2), + PIN_FIELD_BASE(47, 47, 1, 0x0010, 0x10, 6, 2), + PIN_FIELD_BASE(48, 48, 1, 0x0010, 0x10, 8, 2), + PIN_FIELD_BASE(49, 49, 1, 0x0010, 0x10, 8, 2), + PIN_FIELD_BASE(50, 50, 1, 0x0010, 0x10, 8, 2), + PIN_FIELD_BASE(51, 51, 1, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(52, 52, 1, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(53, 53, 1, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(54, 54, 1, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(55, 55, 1, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(56, 56, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(57, 57, 3, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(58, 58, 3, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(59, 59, 3, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(60, 60, 3, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(61, 61, 3, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(62, 62, 3, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(63, 63, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(64, 64, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(65, 65, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(66, 66, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(67, 67, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(68, 68, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(69, 69, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(70, 70, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(71, 71, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(72, 72, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(73, 73, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(74, 74, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(75, 75, 3, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(76, 76, 3, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(77, 77, 3, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(78, 78, 3, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(79, 79, 3, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(80, 80, 3, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(81, 81, 3, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(82, 82, 3, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(83, 83, 3, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(84, 84, 3, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(85, 85, 3, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(86, 86, 3, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(87, 87, 3, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(88, 88, 3, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(89, 89, 2, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(90, 90, 2, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(91, 91, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(92, 92, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(93, 93, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(94, 94, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(95, 95, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(96, 96, 2, 0x0020, 0x10, 24, 3), + PIN_FIELD_BASE(97, 97, 2, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(98, 98, 2, 0x0020, 0x10, 27, 3), + PIN_FIELD_BASE(99, 99, 2, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(100, 100, 2, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(101, 101, 2, 0x0020, 0x10, 18, 3), + PIN_FIELD_BASE(102, 102, 2, 0x0020, 0x10, 21, 3), + PIN_FIELD_BASE(103, 103, 2, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(104, 104, 2, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(105, 105, 2, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(106, 106, 2, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(107, 107, 2, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(108, 108, 2, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(109, 109, 2, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(110, 110, 2, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(111, 111, 2, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(112, 112, 2, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(113, 113, 2, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(114, 114, 2, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(115, 115, 2, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(116, 116, 2, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(117, 117, 2, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(118, 118, 4, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(119, 119, 4, 0x0020, 0x10, 21, 3), + PIN_FIELD_BASE(120, 120, 4, 0x0020, 0x10, 18, 3), + PIN_FIELD_BASE(121, 121, 4, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(122, 122, 4, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(123, 123, 4, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(124, 124, 4, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(125, 125, 4, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(126, 126, 4, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(127, 127, 4, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(128, 128, 4, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(129, 129, 4, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(130, 130, 4, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(131, 131, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(132, 132, 4, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(133, 133, 4, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(134, 134, 4, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(135, 135, 4, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(136, 136, 4, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(137, 137, 4, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(138, 138, 4, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(139, 139, 4, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(140, 140, 4, 0x0020, 0x10, 27, 3), + PIN_FIELD_BASE(141, 141, 4, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(142, 142, 4, 0x0020, 0x10, 24, 3), + PIN_FIELD_BASE(143, 143, 1, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(144, 144, 1, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(145, 145, 1, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(146, 146, 1, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(147, 147, 1, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(148, 148, 1, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(149, 149, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(150, 150, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(151, 151, 1, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(152, 152, 7, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(153, 153, 7, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(154, 154, 7, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(155, 155, 7, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(156, 156, 7, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(157, 157, 7, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(158, 158, 7, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(159, 159, 7, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(160, 160, 7, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(161, 161, 7, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(162, 162, 7, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(163, 163, 7, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(164, 164, 7, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(165, 165, 7, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(166, 166, 7, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(167, 167, 7, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(168, 168, 7, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(169, 169, 7, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(170, 170, 7, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(171, 171, 7, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(172, 172, 7, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(173, 173, 7, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(174, 174, 7, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(175, 175, 7, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(176, 176, 7, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(177, 177, 7, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(178, 178, 7, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(179, 179, 7, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(180, 180, 7, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(181, 181, 7, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(182, 182, 7, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(183, 183, 9, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(184, 184, 9, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(185, 185, 9, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(186, 186, 9, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(187, 187, 9, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(188, 188, 9, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(189, 189, 9, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(190, 190, 9, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(191, 191, 9, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(192, 192, 9, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(193, 193, 9, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(194, 194, 9, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(195, 195, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(196, 196, 5, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(197, 197, 5, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(198, 198, 5, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(199, 199, 5, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(200, 200, 8, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(201, 201, 8, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(202, 202, 5, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(203, 203, 5, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(204, 204, 8, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(205, 205, 8, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(206, 206, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(207, 207, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(208, 208, 5, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(209, 209, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(210, 210, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(211, 211, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(212, 212, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(213, 213, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(214, 214, 5, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(215, 215, 5, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(216, 216, 5, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(217, 217, 5, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(218, 218, 5, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(219, 219, 5, 0x0000, 0x10, 6, 3), +}; + +static const struct mtk_pin_field_calc mt8192_pin_pupd_range[] = { + PIN_FIELD_BASE(10, 10, 6, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, 6, 0x0020, 0x10, 1, 1), + PIN_FIELD_BASE(12, 12, 6, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0020, 0x10, 3, 1), + PIN_FIELD_BASE(14, 14, 6, 0x0020, 0x10, 4, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0020, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, 1, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(46, 46, 1, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(47, 47, 1, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, 1, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, 1, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(50, 50, 1, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(51, 51, 1, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(52, 52, 1, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(53, 53, 1, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, 1, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(55, 55, 1, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(56, 56, 1, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(152, 152, 7, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(153, 153, 7, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(154, 154, 7, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(155, 155, 7, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 31, 1), + PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 31, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0030, 0x10, 9, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0030, 0x10, 10, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0030, 0x10, 11, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 31, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_r0_range[] = { + PIN_FIELD_BASE(10, 10, 6, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, 6, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(12, 12, 6, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(14, 14, 6, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, 1, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(46, 46, 1, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(47, 47, 1, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, 1, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, 1, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(50, 50, 1, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(51, 51, 1, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(52, 52, 1, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(53, 53, 1, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, 1, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(55, 55, 1, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(56, 56, 1, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 12, 1), + PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 22, 1), + PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 20, 1), + PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 18, 1), + PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 16, 1), + PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 14, 1), + PIN_FIELD_BASE(152, 152, 7, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(153, 153, 7, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(154, 154, 7, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(155, 155, 7, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 0, 1), + PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 2, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 4, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_r1_range[] = { + PIN_FIELD_BASE(10, 10, 6, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, 6, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(12, 12, 6, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(14, 14, 6, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, 1, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(46, 46, 1, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(47, 47, 1, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, 1, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, 1, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(50, 50, 1, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(51, 51, 1, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(52, 52, 1, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(53, 53, 1, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, 1, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(55, 55, 1, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(56, 56, 1, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 13, 1), + PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 23, 1), + PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 21, 1), + PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 19, 1), + PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 15, 1), + PIN_FIELD_BASE(152, 152, 7, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(153, 153, 7, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(154, 154, 7, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(155, 155, 7, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 1, 1), + PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 3, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_e1e0en_range[] = { + PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 27, 1), + PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 24, 1), + PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 21, 1), + PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 3, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 9, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 3, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 0, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 6, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_e0_range[] = { + PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 28, 1), + PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 25, 1), + PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 22, 1), + PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 4, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 10, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 1, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 4, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 1, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 7, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_e1_range[] = { + PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 29, 1), + PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 26, 1), + PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 23, 1), + PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 5, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 11, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 5, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 2, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 8, 1), +}; + + +static const char * const mt8192_pinctrl_register_base_names[] = { + "iocfg0", "iocfg_rm", "iocfg_bm", "iocfg_bl", "iocfg_br", + "iocfg_lm", "iocfg_lb", "iocfg_rt", "iocfg_lt", "iocfg_tl", +}; + +static const struct mtk_eint_hw mt8192_eint_hw = { + .port_mask = 7, + .ports = 7, + .ap_num = 224, + .db_cnt = 32, +}; + +static const struct mtk_pin_reg_calc mt8192_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8192_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8192_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8192_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8192_pin_do_range), + [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt8192_pin_dir_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8192_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8192_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8192_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8192_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8192_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8192_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8192_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8192_pin_r1_range), + [PINCTRL_PIN_REG_DRV_EN] = MTK_RANGE(mt8192_pin_e1e0en_range), + [PINCTRL_PIN_REG_DRV_E0] = MTK_RANGE(mt8192_pin_e0_range), + [PINCTRL_PIN_REG_DRV_E1] = MTK_RANGE(mt8192_pin_e1_range), +}; + +static const struct mtk_pin_soc mt8192_data = { + .reg_cal = mt8192_reg_cals, + .pins = mtk_pins_mt8192, + .npins = ARRAY_SIZE(mtk_pins_mt8192), + .ngrps = ARRAY_SIZE(mtk_pins_mt8192), + .base_names = mt8192_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt8192_pinctrl_register_base_names), + .eint_hw = &mt8192_eint_hw, + .nfuncs = 8, + .gpio_m = 0, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_raw, + .drive_get = mtk_pinconf_drive_get_raw, + .adv_pull_get = mtk_pinconf_adv_pull_get, + .adv_pull_set = mtk_pinconf_adv_pull_set, + .adv_drive_get = mtk_pinconf_adv_drive_get, + .adv_drive_set = mtk_pinconf_adv_drive_set, +}; + +static const struct of_device_id mt8192_pinctrl_of_match[] = { + { .compatible = "mediatek,mt8192-pinctrl", }, + { } +}; + +static int mt8192_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_paris_pinctrl_probe(pdev, &mt8192_data); +} + +static struct platform_driver mt8192_pinctrl_driver = { + .driver = { + .name = "mt8192-pinctrl", + .of_match_table = mt8192_pinctrl_of_match, + .pm = &mtk_paris_pinctrl_pm_ops, + }, + .probe = mt8192_pinctrl_probe, +}; + +static int __init mt8192_pinctrl_init(void) +{ + return platform_driver_register(&mt8192_pinctrl_driver); +} +arch_initcall(mt8192_pinctrl_init); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek MT8192 Pinctrl Driver"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8192.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8192.h new file mode 100644 index 000000000000..071162141376 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8192.h @@ -0,0 +1,2275 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Andy Teng <andy.teng@mediatek.com> + * + */ + +#ifndef __PINCTRL_MTK_MT8192_H +#define __PINCTRL_MTK_MT8192_H + +#include "pinctrl-paris.h" + +static const struct mtk_pin_desc mtk_pins_mt8192[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(0, 0), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "SPI6_CLK"), + MTK_FUNCTION(2, "I2S5_MCK"), + MTK_FUNCTION(3, "PWM_0"), + MTK_FUNCTION(4, "TDM_LRCK"), + MTK_FUNCTION(5, "TP_GPIO0_AO"), + MTK_FUNCTION(6, "MD_INT0") + ), + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(0, 1), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "SPI6_CSB"), + MTK_FUNCTION(2, "I2S5_BCK"), + MTK_FUNCTION(3, "PWM_1"), + MTK_FUNCTION(4, "TDM_BCK"), + MTK_FUNCTION(5, "TP_GPIO1_AO"), + MTK_FUNCTION(6, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(7, "DBG_MON_A9") + ), + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(0, 2), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "SPI6_MI"), + MTK_FUNCTION(2, "I2S5_LRCK"), + MTK_FUNCTION(3, "PWM_2"), + MTK_FUNCTION(4, "TDM_MCK"), + MTK_FUNCTION(5, "TP_GPIO2_AO"), + MTK_FUNCTION(6, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(7, "DBG_MON_A10") + ), + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(0, 3), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "SPI6_MO"), + MTK_FUNCTION(2, "I2S5_DO"), + MTK_FUNCTION(3, "PWM_3"), + MTK_FUNCTION(4, "TDM_DATA0"), + MTK_FUNCTION(5, "TP_GPIO3_AO"), + MTK_FUNCTION(6, "CLKM0"), + MTK_FUNCTION(7, "DBG_MON_A11") + ), + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(0, 4), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "SPI4_A_CLK"), + MTK_FUNCTION(2, "I2S2_MCK"), + MTK_FUNCTION(3, "DMIC1_CLK"), + MTK_FUNCTION(4, "TDM_DATA1"), + MTK_FUNCTION(5, "TP_GPIO4_AO"), + MTK_FUNCTION(6, "PCM1_DI"), + MTK_FUNCTION(7, "IDDIG") + ), + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(0, 5), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "SPI4_A_CSB"), + MTK_FUNCTION(2, "I2S2_BCK"), + MTK_FUNCTION(3, "DMIC1_DAT"), + MTK_FUNCTION(4, "TDM_DATA2"), + MTK_FUNCTION(5, "TP_GPIO5_AO"), + MTK_FUNCTION(6, "PCM1_CLK"), + MTK_FUNCTION(7, "USB_DRVVBUS") + ), + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(0, 6), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "SPI4_A_MI"), + MTK_FUNCTION(2, "I2S2_LRCK"), + MTK_FUNCTION(3, "DMIC_CLK"), + MTK_FUNCTION(4, "TDM_DATA3"), + MTK_FUNCTION(5, "TP_GPIO6_AO"), + MTK_FUNCTION(6, "PCM1_SYNC") + ), + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(0, 7), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "SPI4_A_MO"), + MTK_FUNCTION(2, "I2S2_DI"), + MTK_FUNCTION(3, "DMIC_DAT"), + MTK_FUNCTION(4, "WIFI_TXD"), + MTK_FUNCTION(5, "TP_GPIO7_AO"), + MTK_FUNCTION(6, "PCM1_DO0") + ), + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(0, 8), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "SRCLKENAI1"), + MTK_FUNCTION(2, "I2S2_DI2"), + MTK_FUNCTION(3, "KPCOL2"), + MTK_FUNCTION(4, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(5, "CLKM1"), + MTK_FUNCTION(6, "PCM1_DO1"), + MTK_FUNCTION(7, "DBG_MON_A12") + ), + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(0, 9), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "DVFSRC_EXT_REQ"), + MTK_FUNCTION(3, "KPROW2"), + MTK_FUNCTION(4, "CMMCLK4"), + MTK_FUNCTION(5, "CLKM3"), + MTK_FUNCTION(6, "PCM1_DO2"), + MTK_FUNCTION(7, "DBG_MON_A13") + ), + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(0, 10), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "MSDC2_CLK"), + MTK_FUNCTION(2, "SPI4_B_CLK"), + MTK_FUNCTION(3, "I2S8_MCK"), + MTK_FUNCTION(5, "MD_INT0"), + MTK_FUNCTION(6, "TP_GPIO8_AO") + ), + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(0, 11), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "MSDC2_CMD"), + MTK_FUNCTION(2, "SPI4_B_CSB"), + MTK_FUNCTION(3, "I2S8_BCK"), + MTK_FUNCTION(4, "PCIE_CLKREQ_N"), + MTK_FUNCTION(5, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(6, "TP_GPIO9_AO") + ), + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(0, 12), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "MSDC2_DAT3"), + MTK_FUNCTION(2, "SPI4_B_MI"), + MTK_FUNCTION(3, "I2S8_LRCK"), + MTK_FUNCTION(4, "DMIC1_CLK"), + MTK_FUNCTION(5, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(6, "TP_GPIO10_AO") + ), + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(0, 13), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "MSDC2_DAT0"), + MTK_FUNCTION(2, "SPI4_B_MO"), + MTK_FUNCTION(3, "I2S8_DI"), + MTK_FUNCTION(4, "DMIC1_DAT"), + MTK_FUNCTION(5, "ANT_SEL10"), + MTK_FUNCTION(6, "TP_GPIO11_AO") + ), + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(0, 14), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "MSDC2_DAT2"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "SCL_6306"), + MTK_FUNCTION(4, "PCIE_PERESET_N"), + MTK_FUNCTION(5, "ANT_SEL11"), + MTK_FUNCTION(6, "TP_GPIO12_AO") + ), + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(0, 15), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "MSDC2_DAT1"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(3, "SDA_6306"), + MTK_FUNCTION(4, "PCIE_WAKE_N"), + MTK_FUNCTION(5, "ANT_SEL12"), + MTK_FUNCTION(6, "TP_GPIO13_AO") + ), + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(0, 16), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "SRCLKENAI1"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "TP_GPIO14_AO"), + MTK_FUNCTION(4, "KPCOL2"), + MTK_FUNCTION(5, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(6, "SPI7_A_MI"), + MTK_FUNCTION(7, "DBG_MON_A0") + ), + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(0, 17), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(3, "TP_GPIO15_AO"), + MTK_FUNCTION(4, "KPROW2"), + MTK_FUNCTION(6, "SPI7_A_MO"), + MTK_FUNCTION(7, "DBG_MON_A1") + ), + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(0, 18), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "SPI4_C_MI"), + MTK_FUNCTION(3, "SPI1_B_MI"), + MTK_FUNCTION(4, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(5, "ANT_SEL10"), + MTK_FUNCTION(6, "MD_INT0"), + MTK_FUNCTION(7, "DBG_MON_B2") + ), + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(0, 19), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "SRCLKENAI1"), + MTK_FUNCTION(2, "SPI4_C_MO"), + MTK_FUNCTION(3, "SPI1_B_MO"), + MTK_FUNCTION(5, "ANT_SEL11"), + MTK_FUNCTION(6, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(7, "DBG_MON_B3") + ), + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(0, 20), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "SPI4_C_CLK"), + MTK_FUNCTION(3, "SPI1_B_CLK"), + MTK_FUNCTION(4, "PWM_3"), + MTK_FUNCTION(5, "ANT_SEL12"), + MTK_FUNCTION(6, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(7, "DBG_MON_B4") + ), + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(0, 21), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(2, "SPI4_C_CSB"), + MTK_FUNCTION(3, "SPI1_B_CSB"), + MTK_FUNCTION(6, "IDDIG"), + MTK_FUNCTION(7, "DBG_MON_B5") + ), + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(0, 22), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(2, "SPI0_C_CLK"), + MTK_FUNCTION(3, "SPI7_B_CLK"), + MTK_FUNCTION(4, "I2S7_BCK"), + MTK_FUNCTION(5, "I2S9_BCK"), + MTK_FUNCTION(6, "SCL_6306") + ), + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(0, 23), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(2, "SPI0_C_CSB"), + MTK_FUNCTION(3, "SPI7_B_CSB"), + MTK_FUNCTION(4, "I2S7_LRCK"), + MTK_FUNCTION(5, "I2S9_LRCK"), + MTK_FUNCTION(6, "SDA_6306") + ), + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(0, 24), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "SRCLKENAI1"), + MTK_FUNCTION(2, "SPI0_C_MI"), + MTK_FUNCTION(3, "SPI7_B_MI"), + MTK_FUNCTION(4, "I2S6_DI"), + MTK_FUNCTION(5, "I2S8_DI"), + MTK_FUNCTION(6, "SPINOR_CS") + ), + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(0, 25), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "SPI0_C_MO"), + MTK_FUNCTION(3, "SPI7_B_MO"), + MTK_FUNCTION(4, "I2S7_DO"), + MTK_FUNCTION(5, "I2S9_DO"), + MTK_FUNCTION(6, "SPINOR_CK") + ), + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(0, 26), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "PWM_2"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "USB_DRVVBUS"), + MTK_FUNCTION(4, "SPI5_C_MI"), + MTK_FUNCTION(5, "I2S9_BCK") + ), + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(0, 27), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "PWM_3"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(4, "SPI5_C_MO"), + MTK_FUNCTION(5, "I2S9_LRCK"), + MTK_FUNCTION(6, "SPINOR_IO0") + ), + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(0, 28), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "PWM_0"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(4, "SPI5_C_CSB"), + MTK_FUNCTION(5, "I2S9_MCK"), + MTK_FUNCTION(6, "SPINOR_IO1") + ), + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(0, 29), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "PWM_1"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(4, "SPI5_C_CLK"), + MTK_FUNCTION(5, "I2S9_DO"), + MTK_FUNCTION(6, "SPINOR_IO2") + ), + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(0, 30), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "PWM_2"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(4, "I2S7_MCK"), + MTK_FUNCTION(5, "I2S9_MCK"), + MTK_FUNCTION(6, "SPINOR_IO3") + ), + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(0, 31), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "I2S3_MCK"), + MTK_FUNCTION(2, "I2S1_MCK"), + MTK_FUNCTION(3, "I2S5_MCK"), + MTK_FUNCTION(4, "SRCLKENAI0"), + MTK_FUNCTION(5, "I2S0_MCK") + ), + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(0, 32), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "I2S3_BCK"), + MTK_FUNCTION(2, "I2S1_BCK"), + MTK_FUNCTION(3, "I2S5_BCK"), + MTK_FUNCTION(4, "PCM0_CLK"), + MTK_FUNCTION(5, "I2S0_BCK") + ), + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(0, 33), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "I2S3_LRCK"), + MTK_FUNCTION(2, "I2S1_LRCK"), + MTK_FUNCTION(3, "I2S5_LRCK"), + MTK_FUNCTION(4, "PCM0_SYNC"), + MTK_FUNCTION(5, "I2S0_LRCK") + ), + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(0, 34), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "I2S0_DI"), + MTK_FUNCTION(2, "I2S2_DI"), + MTK_FUNCTION(3, "I2S2_DI2"), + MTK_FUNCTION(4, "PCM0_DI"), + MTK_FUNCTION(5, "I2S0_DI") + ), + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(0, 35), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "I2S3_DO"), + MTK_FUNCTION(2, "I2S1_DO"), + MTK_FUNCTION(3, "I2S5_DO"), + MTK_FUNCTION(4, "PCM0_DO") + ), + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(0, 36), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "SPI5_A_CLK"), + MTK_FUNCTION(2, "DMIC1_CLK"), + MTK_FUNCTION(4, "MD_URXD0"), + MTK_FUNCTION(5, "UCTS0"), + MTK_FUNCTION(6, "URXD1") + ), + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(0, 37), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "SPI5_A_CSB"), + MTK_FUNCTION(2, "DMIC1_DAT"), + MTK_FUNCTION(4, "MD_UTXD0"), + MTK_FUNCTION(5, "URTS0"), + MTK_FUNCTION(6, "UTXD1") + ), + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(0, 38), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "SPI5_A_MI"), + MTK_FUNCTION(2, "DMIC_CLK"), + MTK_FUNCTION(4, "MD_URXD1"), + MTK_FUNCTION(5, "URXD0"), + MTK_FUNCTION(6, "UCTS1") + ), + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(0, 39), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "SPI5_A_MO"), + MTK_FUNCTION(2, "DMIC_DAT"), + MTK_FUNCTION(4, "MD_UTXD1"), + MTK_FUNCTION(5, "UTXD0"), + MTK_FUNCTION(6, "URTS1") + ), + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(0, 40), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(7, "DBG_MON_A6") + ), + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(0, 41), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "DSI_TE"), + MTK_FUNCTION(7, "DBG_MON_A7") + ), + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(0, 42), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "LCM_RST"), + MTK_FUNCTION(7, "DBG_MON_A8") + ), + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(0, 43), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(2, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(3, "SCL_6306"), + MTK_FUNCTION(4, "ADSP_URXD0"), + MTK_FUNCTION(5, "PTA_RXD"), + MTK_FUNCTION(6, "SSPM_URXD_AO"), + MTK_FUNCTION(7, "DBG_MON_B0") + ), + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(0, 44), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(2, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(3, "SDA_6306"), + MTK_FUNCTION(4, "ADSP_UTXD0"), + MTK_FUNCTION(5, "PTA_TXD"), + MTK_FUNCTION(6, "SSPM_UTXD_AO"), + MTK_FUNCTION(7, "DBG_MON_B1") + ), + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(0, 45), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "MD1_SIM2_SCLK"), + MTK_FUNCTION(2, "MD1_SIM1_SCLK"), + MTK_FUNCTION(3, "MCUPM_JTAG_TDI"), + MTK_FUNCTION(4, "APU_JTAG_TDI"), + MTK_FUNCTION(5, "CCU_JTAG_TDI"), + MTK_FUNCTION(6, "LVTS_SCK"), + MTK_FUNCTION(7, "CONN_DSP_JDI") + ), + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(0, 46), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "MD1_SIM2_SRST"), + MTK_FUNCTION(2, "MD1_SIM1_SRST"), + MTK_FUNCTION(3, "MCUPM_JTAG_TMS"), + MTK_FUNCTION(4, "APU_JTAG_TMS"), + MTK_FUNCTION(5, "CCU_JTAG_TMS"), + MTK_FUNCTION(6, "LVTS_SDI"), + MTK_FUNCTION(7, "CONN_DSP_JMS") + ), + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(0, 47), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "MD1_SIM2_SIO"), + MTK_FUNCTION(2, "MD1_SIM1_SIO"), + MTK_FUNCTION(3, "MCUPM_JTAG_TDO"), + MTK_FUNCTION(4, "APU_JTAG_TDO"), + MTK_FUNCTION(5, "CCU_JTAG_TDO"), + MTK_FUNCTION(6, "LVTS_SCF"), + MTK_FUNCTION(7, "CONN_DSP_JDO") + ), + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(0, 48), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "MD1_SIM1_SIO"), + MTK_FUNCTION(2, "MD1_SIM2_SIO"), + MTK_FUNCTION(3, "MCUPM_JTAG_TRSTN"), + MTK_FUNCTION(4, "APU_JTAG_TRST"), + MTK_FUNCTION(5, "CCU_JTAG_TRST"), + MTK_FUNCTION(6, "LVTS_FOUT"), + MTK_FUNCTION(7, "CONN_DSP_JINTP") + ), + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(0, 49), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "MD1_SIM1_SRST"), + MTK_FUNCTION(2, "MD1_SIM2_SRST"), + MTK_FUNCTION(3, "MCUPM_JTAG_TCK"), + MTK_FUNCTION(4, "APU_JTAG_TCK"), + MTK_FUNCTION(5, "CCU_JTAG_TCK"), + MTK_FUNCTION(6, "LVTS_SDO"), + MTK_FUNCTION(7, "CONN_DSP_JCK") + ), + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(0, 50), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "MD1_SIM1_SCLK"), + MTK_FUNCTION(2, "MD1_SIM2_SCLK"), + MTK_FUNCTION(6, "LVTS_26M") + ), + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(0, 51), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "PCM1_CLK"), + MTK_FUNCTION(3, "CONN_DSP_JCK"), + MTK_FUNCTION(4, "UDI_TCK"), + MTK_FUNCTION(5, "IPU_JTAG_TCK"), + MTK_FUNCTION(6, "SSPM_JTAG_TCK"), + MTK_FUNCTION(7, "JTCK_SEL3") + ), + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(0, 52), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(2, "PCM1_SYNC"), + MTK_FUNCTION(3, "CONN_DSP_JMS"), + MTK_FUNCTION(4, "UDI_TMS"), + MTK_FUNCTION(5, "IPU_JTAG_TMS"), + MTK_FUNCTION(6, "SSPM_JTAG_TMS"), + MTK_FUNCTION(7, "JTMS_SEL3") + ), + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(0, 53), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(2, "PCM1_DI"), + MTK_FUNCTION(3, "CONN_DSP_JINTP"), + MTK_FUNCTION(4, "CONN_MCU_AICE_TMSC") + ), + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(0, 54), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "PCM1_DO0"), + MTK_FUNCTION(3, "CONN_DSP_JDI"), + MTK_FUNCTION(4, "UDI_TDI"), + MTK_FUNCTION(5, "IPU_JTAG_TDI"), + MTK_FUNCTION(6, "SSPM_JTAG_TDI"), + MTK_FUNCTION(7, "JTDI_SEL3") + ), + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(0, 55), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "PCM1_DO2"), + MTK_FUNCTION(3, "CONN_MCU_AICE_TCKC"), + MTK_FUNCTION(4, "UDI_NTRST"), + MTK_FUNCTION(5, "IPU_JTAG_TRST"), + MTK_FUNCTION(6, "SSPM_JTAG_TRSTN"), + MTK_FUNCTION(7, "JTRSTN_SEL3") + ), + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(0, 56), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "PCM1_DO1"), + MTK_FUNCTION(3, "CONN_DSP_JDO"), + MTK_FUNCTION(4, "UDI_TDO"), + MTK_FUNCTION(5, "IPU_JTAG_TDO"), + MTK_FUNCTION(6, "SSPM_JTAG_TDO"), + MTK_FUNCTION(7, "JTDO_SEL3") + ), + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(0, 57), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "MIPI2_D_SCLK") + ), + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(0, 58), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "MIPI2_D_SDATA") + ), + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(0, 59), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "MIPI_M_SCLK") + ), + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(0, 60), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "MIPI_M_SDATA") + ), + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(0, 61), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "MD_UCNT_A_TGL") + ), + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(0, 62), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "DIGRF_IRQ") + ), + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(0, 63), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "BPI_BUS0"), + MTK_FUNCTION(3, "PCIE_WAKE_N") + ), + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(0, 64), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "BPI_BUS1"), + MTK_FUNCTION(3, "PCIE_PERESET_N") + ), + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(0, 65), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "BPI_BUS2"), + MTK_FUNCTION(3, "PCIE_CLKREQ_N") + ), + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(0, 66), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "BPI_BUS3") + ), + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(0, 67), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "BPI_BUS4") + ), + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(0, 68), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "BPI_BUS5") + ), + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(0, 69), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "BPI_BUS6"), + MTK_FUNCTION(2, "CONN_BPI_BUS6") + ), + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(0, 70), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "BPI_BUS7"), + MTK_FUNCTION(2, "CONN_BPI_BUS7") + ), + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(0, 71), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "BPI_BUS8"), + MTK_FUNCTION(2, "CONN_BPI_BUS8") + ), + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(0, 72), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "BPI_BUS9"), + MTK_FUNCTION(2, "CONN_BPI_BUS9") + ), + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(0, 73), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "BPI_BUS10"), + MTK_FUNCTION(2, "CONN_BPI_BUS10") + ), + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(0, 74), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "BPI_BUS11_OLAT0"), + MTK_FUNCTION(2, "CONN_BPI_BUS11_OLAT0") + ), + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(0, 75), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "BPI_BUS12_OLAT1"), + MTK_FUNCTION(2, "CONN_BPI_BUS12_OLAT1") + ), + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(0, 76), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "BPI_BUS13_OLAT2"), + MTK_FUNCTION(2, "CONN_BPI_BUS13_OLAT2") + ), + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(0, 77), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "BPI_BUS14_OLAT3"), + MTK_FUNCTION(2, "CONN_BPI_BUS14_OLAT3") + ), + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(0, 78), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "BPI_BUS15_OLAT4"), + MTK_FUNCTION(2, "CONN_BPI_BUS15_OLAT4") + ), + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(0, 79), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "BPI_BUS16_OLAT5"), + MTK_FUNCTION(2, "CONN_BPI_BUS16_OLAT5") + ), + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(0, 80), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "BPI_BUS17_ANT0"), + MTK_FUNCTION(2, "CONN_BPI_BUS17_ANT0"), + MTK_FUNCTION(3, "PCIE_WAKE_N") + ), + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(0, 81), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "BPI_BUS18_ANT1"), + MTK_FUNCTION(2, "CONN_BPI_BUS18_ANT1"), + MTK_FUNCTION(3, "PCIE_PERESET_N") + ), + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(0, 82), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "BPI_BUS19_ANT2"), + MTK_FUNCTION(2, "CONN_BPI_BUS19_ANT2"), + MTK_FUNCTION(3, "PCIE_CLKREQ_N") + ), + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(0, 83), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "BPI_BUS20_ANT3"), + MTK_FUNCTION(2, "CONN_BPI_BUS20_ANT3") + ), + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(0, 84), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "BPI_BUS21_ANT4"), + MTK_FUNCTION(2, "CONN_BPI_BUS21_ANT4") + ), + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(0, 85), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "MIPI1_D_SCLK"), + MTK_FUNCTION(2, "CONN_MIPI1_SCLK") + ), + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(0, 86), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "MIPI1_D_SDATA"), + MTK_FUNCTION(2, "CONN_MIPI1_SDATA") + ), + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(0, 87), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "MIPI0_D_SCLK"), + MTK_FUNCTION(2, "CONN_MIPI0_SCLK") + ), + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(0, 88), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "MIPI0_D_SDATA"), + MTK_FUNCTION(2, "CONN_MIPI0_SDATA") + ), + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(0, 89), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "SPMI_SCL"), + MTK_FUNCTION(2, "SCL10") + ), + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(0, 90), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "SPMI_SDA"), + MTK_FUNCTION(2, "SDA10") + ), + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(0, 91), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "AP_GOOD") + ), + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(0, 92), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "MD_URXD0"), + MTK_FUNCTION(3, "MD_URXD1"), + MTK_FUNCTION(4, "SSPM_URXD_AO"), + MTK_FUNCTION(5, "CONN_UART0_RXD") + ), + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(0, 93), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "MD_UTXD0"), + MTK_FUNCTION(3, "MD_UTXD1"), + MTK_FUNCTION(4, "SSPM_UTXD_AO"), + MTK_FUNCTION(5, "CONN_UART0_TXD"), + MTK_FUNCTION(6, "WIFI_TXD") + ), + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(0, 94), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "ADSP_URXD0"), + MTK_FUNCTION(3, "MD32_0_RXD"), + MTK_FUNCTION(4, "SSPM_URXD_AO"), + MTK_FUNCTION(5, "TP_URXD1_AO"), + MTK_FUNCTION(6, "TP_URXD2_AO"), + MTK_FUNCTION(7, "MBISTREADEN_TRIGGER") + ), + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(0, 95), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "ADSP_UTXD0"), + MTK_FUNCTION(3, "MD32_0_TXD"), + MTK_FUNCTION(4, "SSPM_UTXD_AO"), + MTK_FUNCTION(5, "TP_UTXD1_AO"), + MTK_FUNCTION(6, "TP_UTXD2_AO"), + MTK_FUNCTION(7, "MBISTWRITEEN_TRIGGER") + ), + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(0, 96), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "TDM_LRCK"), + MTK_FUNCTION(2, "I2S7_LRCK"), + MTK_FUNCTION(3, "I2S9_LRCK"), + MTK_FUNCTION(4, "DPI_D0"), + MTK_FUNCTION(5, "ADSP_JTAG0_TDI"), + MTK_FUNCTION(7, "IO_JTAG_TDI") + ), + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(0, 97), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "TDM_BCK"), + MTK_FUNCTION(2, "I2S7_BCK"), + MTK_FUNCTION(3, "I2S9_BCK"), + MTK_FUNCTION(4, "DPI_D1"), + MTK_FUNCTION(5, "ADSP_JTAG0_TRSTN"), + MTK_FUNCTION(7, "IO_JTAG_TRSTN") + ), + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(0, 98), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "TDM_MCK"), + MTK_FUNCTION(2, "I2S7_MCK"), + MTK_FUNCTION(3, "I2S9_MCK"), + MTK_FUNCTION(4, "DPI_D2"), + MTK_FUNCTION(5, "ADSP_JTAG0_TCK"), + MTK_FUNCTION(7, "IO_JTAG_TCK") + ), + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(0, 99), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "TDM_DATA0"), + MTK_FUNCTION(2, "I2S6_DI"), + MTK_FUNCTION(3, "I2S8_DI"), + MTK_FUNCTION(4, "DPI_D3"), + MTK_FUNCTION(5, "ADSP_JTAG0_TDO"), + MTK_FUNCTION(7, "IO_JTAG_TDO") + ), + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(0, 100), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "TDM_DATA1"), + MTK_FUNCTION(2, "I2S7_DO"), + MTK_FUNCTION(3, "I2S9_DO"), + MTK_FUNCTION(4, "DPI_D4"), + MTK_FUNCTION(5, "ADSP_JTAG0_TMS"), + MTK_FUNCTION(7, "IO_JTAG_TMS") + ), + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(0, 101), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "TDM_DATA2"), + MTK_FUNCTION(2, "DMIC1_CLK"), + MTK_FUNCTION(3, "SRCLKENAI0"), + MTK_FUNCTION(4, "DPI_D5"), + MTK_FUNCTION(5, "CLKM0"), + MTK_FUNCTION(7, "DAP_MD32_SWD") + ), + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(0, 102), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "TDM_DATA3"), + MTK_FUNCTION(2, "DMIC1_DAT"), + MTK_FUNCTION(3, "SRCLKENAI1"), + MTK_FUNCTION(4, "DPI_D6"), + MTK_FUNCTION(6, "DVFSRC_EXT_REQ"), + MTK_FUNCTION(7, "DAP_MD32_SWCK") + ), + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(0, 103), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "SPI0_A_MI"), + MTK_FUNCTION(2, "SCP_SPI0_MI"), + MTK_FUNCTION(4, "DPI_D7"), + MTK_FUNCTION(5, "DFD_TDO"), + MTK_FUNCTION(6, "SPM_JTAG_TDO"), + MTK_FUNCTION(7, "JTDO_SEL1") + ), + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(0, 104), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "SPI0_A_CSB"), + MTK_FUNCTION(2, "SCP_SPI0_CS"), + MTK_FUNCTION(4, "DPI_D8"), + MTK_FUNCTION(5, "DFD_TMS"), + MTK_FUNCTION(6, "SPM_JTAG_TMS"), + MTK_FUNCTION(7, "JTMS_SEL1") + ), + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(0, 105), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "SPI0_A_MO"), + MTK_FUNCTION(2, "SCP_SPI0_MO"), + MTK_FUNCTION(3, "SCP_SDA0"), + MTK_FUNCTION(4, "DPI_D9"), + MTK_FUNCTION(5, "DFD_TDI"), + MTK_FUNCTION(6, "SPM_JTAG_TDI"), + MTK_FUNCTION(7, "JTDI_SEL1") + ), + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(0, 106), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "SPI0_A_CLK"), + MTK_FUNCTION(2, "SCP_SPI0_CK"), + MTK_FUNCTION(3, "SCP_SCL0"), + MTK_FUNCTION(4, "DPI_D10"), + MTK_FUNCTION(5, "DFD_TCK_XI"), + MTK_FUNCTION(6, "SPM_JTAG_TCK"), + MTK_FUNCTION(7, "JTCK_SEL1") + ), + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(0, 107), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "DMIC_CLK"), + MTK_FUNCTION(2, "PWM_0"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(6, "SPM_JTAG_TRSTN"), + MTK_FUNCTION(7, "JTRSTN_SEL1") + ), + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(0, 108), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "DMIC_DAT"), + MTK_FUNCTION(2, "PWM_1"), + MTK_FUNCTION(3, "CLKM3"), + MTK_FUNCTION(7, "DAP_SONIC_SWD") + ), + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(0, 109), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "I2S1_MCK"), + MTK_FUNCTION(2, "I2S3_MCK"), + MTK_FUNCTION(3, "I2S2_MCK"), + MTK_FUNCTION(4, "DPI_DE"), + MTK_FUNCTION(5, "I2S2_MCK"), + MTK_FUNCTION(6, "SRCLKENAI0"), + MTK_FUNCTION(7, "DAP_SONIC_SWCK") + ), + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(0, 110), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "I2S1_BCK"), + MTK_FUNCTION(2, "I2S3_BCK"), + MTK_FUNCTION(3, "I2S2_BCK"), + MTK_FUNCTION(4, "DPI_D11"), + MTK_FUNCTION(5, "I2S2_BCK"), + MTK_FUNCTION(6, "CONN_MCU_TDO") + ), + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(0, 111), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "I2S1_LRCK"), + MTK_FUNCTION(2, "I2S3_LRCK"), + MTK_FUNCTION(3, "I2S2_LRCK"), + MTK_FUNCTION(4, "DPI_VSYNC"), + MTK_FUNCTION(5, "I2S2_LRCK"), + MTK_FUNCTION(6, "CONN_MCU_TDI") + ), + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(0, 112), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "I2S2_DI"), + MTK_FUNCTION(2, "I2S0_DI"), + MTK_FUNCTION(3, "I2S2_DI2"), + MTK_FUNCTION(4, "DPI_CK"), + MTK_FUNCTION(5, "I2S2_DI"), + MTK_FUNCTION(6, "CONN_MCU_TMS") + ), + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(0, 113), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "I2S1_DO"), + MTK_FUNCTION(2, "I2S3_DO"), + MTK_FUNCTION(3, "I2S5_DO"), + MTK_FUNCTION(4, "DPI_HSYNC"), + MTK_FUNCTION(5, "I2S2_DI2"), + MTK_FUNCTION(6, "CONN_MCU_TCK") + ), + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(0, 114), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "SPI2_MI"), + MTK_FUNCTION(2, "SCP_SPI2_MI"), + MTK_FUNCTION(4, "PCM0_DI"), + MTK_FUNCTION(6, "CONN_MCU_TRST_B") + ), + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(0, 115), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "SPI2_CSB"), + MTK_FUNCTION(2, "SCP_SPI2_CS"), + MTK_FUNCTION(4, "PCM0_SYNC"), + MTK_FUNCTION(6, "CONN_MCU_DBGI_N") + ), + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(0, 116), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "SPI2_MO"), + MTK_FUNCTION(2, "SCP_SPI2_MO"), + MTK_FUNCTION(3, "SCP_SDA1"), + MTK_FUNCTION(4, "PCM0_DO"), + MTK_FUNCTION(6, "CONN_MCU_DBGACK_N") + ), + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(0, 117), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "SPI2_CLK"), + MTK_FUNCTION(2, "SCP_SPI2_CK"), + MTK_FUNCTION(3, "SCP_SCL1"), + MTK_FUNCTION(4, "PCM0_CLK") + ), + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(0, 118), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "SCL1"), + MTK_FUNCTION(2, "SCP_SCL0"), + MTK_FUNCTION(3, "SCP_SCL1") + ), + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(0, 119), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(2, "SCP_SDA0"), + MTK_FUNCTION(3, "SCP_SDA1") + ), + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(0, 120), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "SCL9"), + MTK_FUNCTION(2, "SCP_SCL0") + ), + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(0, 121), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "SDA9"), + MTK_FUNCTION(2, "SCP_SDA0") + ), + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(0, 122), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "SCL8"), + MTK_FUNCTION(2, "SCP_SDA0") + ), + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(0, 123), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "SDA8"), + MTK_FUNCTION(2, "SCP_SCL0") + ), + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(0, 124), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "SCL7"), + MTK_FUNCTION(2, "DMIC1_CLK") + ), + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(0, 125), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "SDA7"), + MTK_FUNCTION(2, "DMIC1_DAT") + ), + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(0, 126), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "CMFLASH0"), + MTK_FUNCTION(2, "PWM_2"), + MTK_FUNCTION(3, "TP_UCTS1_AO"), + MTK_FUNCTION(4, "UCTS0"), + MTK_FUNCTION(5, "SCL11"), + MTK_FUNCTION(6, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(7, "DBG_MON_A14") + ), + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(0, 127), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "CMFLASH1"), + MTK_FUNCTION(2, "PWM_3"), + MTK_FUNCTION(3, "TP_URTS1_AO"), + MTK_FUNCTION(4, "URTS0"), + MTK_FUNCTION(5, "SDA11"), + MTK_FUNCTION(7, "DBG_MON_A15") + ), + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(0, 128), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "CMFLASH2"), + MTK_FUNCTION(2, "PWM_0"), + MTK_FUNCTION(3, "TP_UCTS2_AO"), + MTK_FUNCTION(4, "UCTS1"), + MTK_FUNCTION(5, "SCL_6306"), + MTK_FUNCTION(7, "DBG_MON_A16") + ), + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(0, 129), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "CMFLASH3"), + MTK_FUNCTION(2, "PWM_1"), + MTK_FUNCTION(3, "TP_URTS2_AO"), + MTK_FUNCTION(4, "URTS1"), + MTK_FUNCTION(5, "SDA_6306"), + MTK_FUNCTION(7, "DBG_MON_A17") + ), + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(0, 130), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "CMVREF0"), + MTK_FUNCTION(2, "ANT_SEL10"), + MTK_FUNCTION(3, "SCP_JTAG0_TDO"), + MTK_FUNCTION(4, "MD32_0_JTAG_TDO"), + MTK_FUNCTION(5, "SCL11"), + MTK_FUNCTION(6, "SPI5_B_CLK"), + MTK_FUNCTION(7, "DBG_MON_A22") + ), + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(0, 131), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "CMVREF1"), + MTK_FUNCTION(2, "ANT_SEL11"), + MTK_FUNCTION(3, "SCP_JTAG0_TDI"), + MTK_FUNCTION(4, "MD32_0_JTAG_TDI"), + MTK_FUNCTION(5, "SDA11"), + MTK_FUNCTION(6, "SPI5_B_MO"), + MTK_FUNCTION(7, "DBG_MON_A25") + ), + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(0, 132), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "CMVREF2"), + MTK_FUNCTION(2, "ANT_SEL12"), + MTK_FUNCTION(3, "SCP_JTAG0_TMS"), + MTK_FUNCTION(4, "MD32_0_JTAG_TMS"), + MTK_FUNCTION(7, "DBG_MON_A28") + ), + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(0, 133), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "CMVREF3"), + MTK_FUNCTION(2, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(3, "SCP_JTAG0_TCK"), + MTK_FUNCTION(4, "MD32_0_JTAG_TCK"), + MTK_FUNCTION(6, "SPI5_B_CSB"), + MTK_FUNCTION(7, "DBG_MON_A23") + ), + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(0, 134), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "CMVREF4"), + MTK_FUNCTION(3, "SCP_JTAG0_TRSTN"), + MTK_FUNCTION(4, "MD32_0_JTAG_TRST"), + MTK_FUNCTION(7, "DBG_MON_A26") + ), + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(0, 135), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "PWM_0"), + MTK_FUNCTION(2, "SRCLKENAI1"), + MTK_FUNCTION(3, "MD_URXD0"), + MTK_FUNCTION(4, "MD32_0_RXD"), + MTK_FUNCTION(5, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(7, "DBG_MON_A29") + ), + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(0, 136), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "CMMCLK3"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "MD_UTXD0"), + MTK_FUNCTION(4, "MD32_0_TXD"), + MTK_FUNCTION(6, "SPI5_B_MI"), + MTK_FUNCTION(7, "DBG_MON_A24") + ), + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(0, 137), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "CMMCLK4"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "MD_URXD1"), + MTK_FUNCTION(6, "CONN_UART0_RXD"), + MTK_FUNCTION(7, "DBG_MON_A27") + ), + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(0, 138), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "CMMCLK5"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "MD_UTXD1"), + MTK_FUNCTION(6, "CONN_UART0_TXD"), + MTK_FUNCTION(7, "DBG_MON_A30") + ), + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(0, 139), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "SCL4"), + MTK_FUNCTION(7, "DBG_MON_A21") + ), + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(0, 140), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "SDA4"), + MTK_FUNCTION(7, "DBG_MON_A20") + ), + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(0, 141), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(7, "DBG_MON_A18") + ), + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(0, 142), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(7, "DBG_MON_A19") + ), + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(0, 143), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "CMVREF0"), + MTK_FUNCTION(2, "SPI3_CLK"), + MTK_FUNCTION(3, "ADSP_JTAG1_TDO"), + MTK_FUNCTION(4, "SCP_JTAG1_TDO"), + MTK_FUNCTION(7, "DBG_MON_A31") + ), + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(0, 144), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "CMVREF1"), + MTK_FUNCTION(2, "SPI3_CSB"), + MTK_FUNCTION(3, "ADSP_JTAG1_TDI"), + MTK_FUNCTION(4, "SCP_JTAG1_TDI") + ), + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(0, 145), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "CMVREF2"), + MTK_FUNCTION(2, "SPI3_MI"), + MTK_FUNCTION(3, "ADSP_JTAG1_TMS"), + MTK_FUNCTION(4, "SCP_JTAG1_TMS") + ), + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(0, 146), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "CMVREF3"), + MTK_FUNCTION(2, "SPI3_MO"), + MTK_FUNCTION(3, "ADSP_JTAG1_TCK"), + MTK_FUNCTION(4, "SCP_JTAG1_TCK"), + MTK_FUNCTION(7, "DBG_MON_A32") + ), + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(0, 147), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "CMVREF4"), + MTK_FUNCTION(2, "EXT_FRAME_SYNC"), + MTK_FUNCTION(3, "ADSP_JTAG1_TRSTN"), + MTK_FUNCTION(4, "SCP_JTAG1_TRSTN") + ), + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(0, 148), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "PWM_1"), + MTK_FUNCTION(2, "AGPS_SYNC"), + MTK_FUNCTION(3, "CMMCLK5") + ), + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(0, 149), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "CMMCLK0"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "MD32_0_GPIO0") + ), + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(0, 150), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(1, "CMMCLK1"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "MD32_0_GPIO1"), + MTK_FUNCTION(7, "CONN_MCU_AICE_TMSC") + ), + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(0, 151), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "CMMCLK2"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "MD32_0_GPIO2"), + MTK_FUNCTION(7, "CONN_MCU_AICE_TCKC") + ), + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(0, 152), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(1, "KPROW1"), + MTK_FUNCTION(2, "PWM_2"), + MTK_FUNCTION(3, "IDDIG"), + MTK_FUNCTION(6, "MBISTREADEN_TRIGGER"), + MTK_FUNCTION(7, "DBG_MON_B9") + ), + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(0, 153), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "KPROW0"), + MTK_FUNCTION(7, "DBG_MON_B8") + ), + MTK_PIN( + 154, "GPIO154", + MTK_EINT_FUNCTION(0, 154), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(1, "KPCOL0"), + MTK_FUNCTION(7, "DBG_MON_B6") + ), + MTK_PIN( + 155, "GPIO155", + MTK_EINT_FUNCTION(0, 155), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO155"), + MTK_FUNCTION(1, "KPCOL1"), + MTK_FUNCTION(2, "PWM_3"), + MTK_FUNCTION(3, "USB_DRVVBUS"), + MTK_FUNCTION(4, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(6, "MBISTWRITEEN_TRIGGER"), + MTK_FUNCTION(7, "DBG_MON_B7") + ), + MTK_PIN( + 156, "GPIO156", + MTK_EINT_FUNCTION(0, 156), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO156"), + MTK_FUNCTION(1, "SPI1_A_CLK"), + MTK_FUNCTION(2, "SCP_SPI1_A_CK"), + MTK_FUNCTION(3, "MRG_CLK"), + MTK_FUNCTION(4, "AGPS_SYNC"), + MTK_FUNCTION(5, "MD_URXD0"), + MTK_FUNCTION(6, "UDI_TMS"), + MTK_FUNCTION(7, "DBG_MON_B10") + ), + MTK_PIN( + 157, "GPIO157", + MTK_EINT_FUNCTION(0, 157), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO157"), + MTK_FUNCTION(1, "SPI1_A_CSB"), + MTK_FUNCTION(2, "SCP_SPI1_A_CS"), + MTK_FUNCTION(3, "MRG_SYNC"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(5, "MD_UTXD0"), + MTK_FUNCTION(6, "UDI_TCK"), + MTK_FUNCTION(7, "DBG_MON_B11") + ), + MTK_PIN( + 158, "GPIO158", + MTK_EINT_FUNCTION(0, 158), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO158"), + MTK_FUNCTION(1, "SPI1_A_MI"), + MTK_FUNCTION(2, "SCP_SPI1_A_MI"), + MTK_FUNCTION(3, "MRG_DI"), + MTK_FUNCTION(4, "PTA_RXD"), + MTK_FUNCTION(5, "MD_URXD1"), + MTK_FUNCTION(6, "UDI_TDO"), + MTK_FUNCTION(7, "DBG_MON_B12") + ), + MTK_PIN( + 159, "GPIO159", + MTK_EINT_FUNCTION(0, 159), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO159"), + MTK_FUNCTION(1, "SPI1_A_MO"), + MTK_FUNCTION(2, "SCP_SPI1_A_MO"), + MTK_FUNCTION(3, "MRG_DO"), + MTK_FUNCTION(4, "PTA_TXD"), + MTK_FUNCTION(5, "MD_UTXD1"), + MTK_FUNCTION(6, "UDI_NTRST"), + MTK_FUNCTION(7, "DBG_MON_B13") + ), + MTK_PIN( + 160, "GPIO160", + MTK_EINT_FUNCTION(0, 160), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO160"), + MTK_FUNCTION(1, "SCL3"), + MTK_FUNCTION(3, "SCP_SCL1"), + MTK_FUNCTION(7, "DBG_MON_B14") + ), + MTK_PIN( + 161, "GPIO161", + MTK_EINT_FUNCTION(0, 161), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO161"), + MTK_FUNCTION(1, "SDA3"), + MTK_FUNCTION(3, "SCP_SDA1"), + MTK_FUNCTION(7, "DBG_MON_B15") + ), + MTK_PIN( + 162, "GPIO162", + MTK_EINT_FUNCTION(0, 162), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO162"), + MTK_FUNCTION(1, "ANT_SEL0"), + MTK_FUNCTION(2, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(6, "UDI_TDI"), + MTK_FUNCTION(7, "DBG_MON_B16") + ), + MTK_PIN( + 163, "GPIO163", + MTK_EINT_FUNCTION(0, 163), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO163"), + MTK_FUNCTION(1, "ANT_SEL1"), + MTK_FUNCTION(2, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(7, "DBG_MON_B17") + ), + MTK_PIN( + 164, "GPIO164", + MTK_EINT_FUNCTION(0, 164), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO164"), + MTK_FUNCTION(1, "ANT_SEL2"), + MTK_FUNCTION(2, "SCP_SPI1_B_CK"), + MTK_FUNCTION(3, "TP_URXD1_AO"), + MTK_FUNCTION(5, "UCTS0"), + MTK_FUNCTION(7, "DBG_MON_B18") + ), + MTK_PIN( + 165, "GPIO165", + MTK_EINT_FUNCTION(0, 165), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO165"), + MTK_FUNCTION(1, "ANT_SEL3"), + MTK_FUNCTION(2, "SCP_SPI1_B_CS"), + MTK_FUNCTION(3, "TP_UTXD1_AO"), + MTK_FUNCTION(4, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(5, "URTS0"), + MTK_FUNCTION(7, "DBG_MON_B19") + ), + MTK_PIN( + 166, "GPIO166", + MTK_EINT_FUNCTION(0, 166), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO166"), + MTK_FUNCTION(1, "ANT_SEL4"), + MTK_FUNCTION(2, "SCP_SPI1_B_MI"), + MTK_FUNCTION(3, "TP_URXD2_AO"), + MTK_FUNCTION(4, "SRCLKENAI1"), + MTK_FUNCTION(5, "UCTS1"), + MTK_FUNCTION(7, "DBG_MON_B20") + ), + MTK_PIN( + 167, "GPIO167", + MTK_EINT_FUNCTION(0, 167), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO167"), + MTK_FUNCTION(1, "ANT_SEL5"), + MTK_FUNCTION(2, "SCP_SPI1_B_MO"), + MTK_FUNCTION(3, "TP_UTXD2_AO"), + MTK_FUNCTION(4, "SRCLKENAI0"), + MTK_FUNCTION(5, "URTS1"), + MTK_FUNCTION(7, "DBG_MON_B21") + ), + MTK_PIN( + 168, "GPIO168", + MTK_EINT_FUNCTION(0, 168), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO168"), + MTK_FUNCTION(1, "ANT_SEL6"), + MTK_FUNCTION(2, "SPI0_B_CLK"), + MTK_FUNCTION(3, "TP_UCTS1_AO"), + MTK_FUNCTION(4, "KPCOL2"), + MTK_FUNCTION(5, "MD_UCTS0"), + MTK_FUNCTION(6, "SCL11"), + MTK_FUNCTION(7, "DBG_MON_B22") + ), + MTK_PIN( + 169, "GPIO169", + MTK_EINT_FUNCTION(0, 169), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO169"), + MTK_FUNCTION(1, "ANT_SEL7"), + MTK_FUNCTION(2, "SPI0_B_CSB"), + MTK_FUNCTION(3, "TP_URTS1_AO"), + MTK_FUNCTION(4, "KPROW2"), + MTK_FUNCTION(5, "MD_URTS0"), + MTK_FUNCTION(6, "SDA11"), + MTK_FUNCTION(7, "DBG_MON_B23") + ), + MTK_PIN( + 170, "GPIO170", + MTK_EINT_FUNCTION(0, 170), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO170"), + MTK_FUNCTION(1, "ANT_SEL8"), + MTK_FUNCTION(2, "SPI0_B_MI"), + MTK_FUNCTION(3, "TP_UCTS2_AO"), + MTK_FUNCTION(4, "SRCLKENAI1"), + MTK_FUNCTION(5, "MD_UCTS1"), + MTK_FUNCTION(7, "DBG_MON_B24") + ), + MTK_PIN( + 171, "GPIO171", + MTK_EINT_FUNCTION(0, 171), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO171"), + MTK_FUNCTION(1, "ANT_SEL9"), + MTK_FUNCTION(2, "SPI0_B_MO"), + MTK_FUNCTION(3, "TP_URTS2_AO"), + MTK_FUNCTION(4, "SRCLKENAI0"), + MTK_FUNCTION(5, "MD_URTS1"), + MTK_FUNCTION(7, "DBG_MON_B25") + ), + MTK_PIN( + 172, "GPIO172", + MTK_EINT_FUNCTION(0, 172), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO172"), + MTK_FUNCTION(1, "CONN_TOP_CLK"), + MTK_FUNCTION(2, "AUXIF_CLK0"), + MTK_FUNCTION(7, "DBG_MON_B29") + ), + MTK_PIN( + 173, "GPIO173", + MTK_EINT_FUNCTION(0, 173), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO173"), + MTK_FUNCTION(1, "CONN_TOP_DATA"), + MTK_FUNCTION(2, "AUXIF_ST0"), + MTK_FUNCTION(7, "DBG_MON_B30") + ), + MTK_PIN( + 174, "GPIO174", + MTK_EINT_FUNCTION(0, 174), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO174"), + MTK_FUNCTION(1, "CONN_HRST_B"), + MTK_FUNCTION(7, "DBG_MON_B28") + ), + MTK_PIN( + 175, "GPIO175", + MTK_EINT_FUNCTION(0, 175), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO175"), + MTK_FUNCTION(1, "CONN_WB_PTA"), + MTK_FUNCTION(7, "DBG_MON_B31") + ), + MTK_PIN( + 176, "GPIO176", + MTK_EINT_FUNCTION(0, 176), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO176"), + MTK_FUNCTION(1, "CONN_BT_CLK"), + MTK_FUNCTION(2, "AUXIF_CLK1"), + MTK_FUNCTION(7, "DBG_MON_B26") + ), + MTK_PIN( + 177, "GPIO177", + MTK_EINT_FUNCTION(0, 177), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO177"), + MTK_FUNCTION(1, "CONN_BT_DATA"), + MTK_FUNCTION(2, "AUXIF_ST1"), + MTK_FUNCTION(7, "DBG_MON_B27") + ), + MTK_PIN( + 178, "GPIO178", + MTK_EINT_FUNCTION(0, 178), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO178"), + MTK_FUNCTION(1, "CONN_WF_CTRL0") + ), + MTK_PIN( + 179, "GPIO179", + MTK_EINT_FUNCTION(0, 179), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO179"), + MTK_FUNCTION(1, "CONN_WF_CTRL1"), + MTK_FUNCTION(2, "UFS_MPHY_SCL") + ), + MTK_PIN( + 180, "GPIO180", + MTK_EINT_FUNCTION(0, 180), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO180"), + MTK_FUNCTION(1, "CONN_WF_CTRL2"), + MTK_FUNCTION(2, "UFS_MPHY_SDA") + ), + MTK_PIN( + 181, "GPIO181", + MTK_EINT_FUNCTION(0, 181), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO181"), + MTK_FUNCTION(1, "CONN_WF_CTRL3") + ), + MTK_PIN( + 182, "GPIO182", + MTK_EINT_FUNCTION(0, 182), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO182"), + MTK_FUNCTION(1, "CONN_WF_CTRL4") + ), + MTK_PIN( + 183, "GPIO183", + MTK_EINT_FUNCTION(0, 183), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO183"), + MTK_FUNCTION(1, "MSDC0_CMD") + ), + MTK_PIN( + 184, "GPIO184", + MTK_EINT_FUNCTION(0, 184), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO184"), + MTK_FUNCTION(1, "MSDC0_DAT0") + ), + MTK_PIN( + 185, "GPIO185", + MTK_EINT_FUNCTION(0, 185), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO185"), + MTK_FUNCTION(1, "MSDC0_DAT2") + ), + MTK_PIN( + 186, "GPIO186", + MTK_EINT_FUNCTION(0, 186), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO186"), + MTK_FUNCTION(1, "MSDC0_DAT4") + ), + MTK_PIN( + 187, "GPIO187", + MTK_EINT_FUNCTION(0, 187), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO187"), + MTK_FUNCTION(1, "MSDC0_DAT6") + ), + MTK_PIN( + 188, "GPIO188", + MTK_EINT_FUNCTION(0, 188), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO188"), + MTK_FUNCTION(1, "MSDC0_DAT1") + ), + MTK_PIN( + 189, "GPIO189", + MTK_EINT_FUNCTION(0, 189), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO189"), + MTK_FUNCTION(1, "MSDC0_DAT5") + ), + MTK_PIN( + 190, "GPIO190", + MTK_EINT_FUNCTION(0, 190), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO190"), + MTK_FUNCTION(1, "MSDC0_DAT7") + ), + MTK_PIN( + 191, "GPIO191", + MTK_EINT_FUNCTION(0, 191), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO191"), + MTK_FUNCTION(1, "MSDC0_DSL"), + MTK_FUNCTION(2, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(3, "IDDIG"), + MTK_FUNCTION(4, "DMIC_CLK") + ), + MTK_PIN( + 192, "GPIO192", + MTK_EINT_FUNCTION(0, 192), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO192"), + MTK_FUNCTION(1, "MSDC0_CLK"), + MTK_FUNCTION(3, "USB_DRVVBUS"), + MTK_FUNCTION(4, "DMIC_DAT") + ), + MTK_PIN( + 193, "GPIO193", + MTK_EINT_FUNCTION(0, 193), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO193"), + MTK_FUNCTION(1, "MSDC0_DAT3") + ), + MTK_PIN( + 194, "GPIO194", + MTK_EINT_FUNCTION(0, 194), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO194"), + MTK_FUNCTION(1, "MSDC0_RSTB") + ), + MTK_PIN( + 195, "GPIO195", + MTK_EINT_FUNCTION(0, 195), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO195"), + MTK_FUNCTION(1, "SCP_VREQ_VAO"), + MTK_FUNCTION(2, "DVFSRC_EXT_REQ") + ), + MTK_PIN( + 196, "GPIO196", + MTK_EINT_FUNCTION(0, 196), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO196"), + MTK_FUNCTION(1, "AUD_DAT_MOSI2") + ), + MTK_PIN( + 197, "GPIO197", + MTK_EINT_FUNCTION(0, 197), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO197"), + MTK_FUNCTION(1, "AUD_NLE_MOSI1"), + MTK_FUNCTION(2, "AUD_CLK_MISO"), + MTK_FUNCTION(3, "I2S2_MCK"), + MTK_FUNCTION(4, "I2S6_MCK"), + MTK_FUNCTION(5, "I2S8_MCK") + ), + MTK_PIN( + 198, "GPIO198", + MTK_EINT_FUNCTION(0, 198), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO198"), + MTK_FUNCTION(1, "AUD_NLE_MOSI0"), + MTK_FUNCTION(2, "AUD_SYNC_MISO"), + MTK_FUNCTION(3, "I2S2_BCK"), + MTK_FUNCTION(4, "I2S6_BCK"), + MTK_FUNCTION(5, "I2S8_BCK") + ), + MTK_PIN( + 199, "GPIO199", + MTK_EINT_FUNCTION(0, 199), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO199"), + MTK_FUNCTION(1, "AUD_DAT_MISO2"), + MTK_FUNCTION(3, "I2S2_DI2") + ), + MTK_PIN( + 200, "GPIO200", + MTK_EINT_FUNCTION(0, 200), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO200"), + MTK_FUNCTION(1, "SCL6"), + MTK_FUNCTION(3, "SCP_SCL1"), + MTK_FUNCTION(4, "SCL_6306"), + MTK_FUNCTION(7, "DBG_MON_A4") + ), + MTK_PIN( + 201, "GPIO201", + MTK_EINT_FUNCTION(0, 201), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO201"), + MTK_FUNCTION(1, "SDA6"), + MTK_FUNCTION(3, "SCP_SDA1"), + MTK_FUNCTION(4, "SDA_6306"), + MTK_FUNCTION(7, "DBG_MON_A5") + ), + MTK_PIN( + 202, "GPIO202", + MTK_EINT_FUNCTION(0, 202), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO202"), + MTK_FUNCTION(1, "SCL5") + ), + MTK_PIN( + 203, "GPIO203", + MTK_EINT_FUNCTION(0, 203), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO203"), + MTK_FUNCTION(1, "SDA5") + ), + MTK_PIN( + 204, "GPIO204", + MTK_EINT_FUNCTION(0, 204), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO204"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(6, "SPI7_A_CLK"), + MTK_FUNCTION(7, "DBG_MON_A2") + ), + MTK_PIN( + 205, "GPIO205", + MTK_EINT_FUNCTION(0, 205), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO205"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(6, "SPI7_A_CSB"), + MTK_FUNCTION(7, "DBG_MON_A3") + ), + MTK_PIN( + 206, "GPIO206", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO206"), + MTK_FUNCTION(1, "SRCLKENA0") + ), + MTK_PIN( + 207, "GPIO207", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO207"), + MTK_FUNCTION(1, "SRCLKENA1") + ), + MTK_PIN( + 208, "GPIO208", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO208"), + MTK_FUNCTION(1, "WATCHDOG") + ), + MTK_PIN( + 209, "GPIO209", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO209"), + MTK_FUNCTION(1, "PWRAP_SPI0_MI"), + MTK_FUNCTION(2, "PWRAP_SPI0_MO") + ), + MTK_PIN( + 210, "GPIO210", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO210"), + MTK_FUNCTION(1, "PWRAP_SPI0_CSN") + ), + MTK_PIN( + 211, "GPIO211", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO211"), + MTK_FUNCTION(1, "PWRAP_SPI0_MO"), + MTK_FUNCTION(2, "PWRAP_SPI0_MI") + ), + MTK_PIN( + 212, "GPIO212", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO212"), + MTK_FUNCTION(1, "PWRAP_SPI0_CK") + ), + MTK_PIN( + 213, "GPIO213", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO213"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN( + 214, "GPIO214", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO214"), + MTK_FUNCTION(1, "AUD_CLK_MOSI"), + MTK_FUNCTION(3, "I2S1_MCK"), + MTK_FUNCTION(4, "I2S7_MCK"), + MTK_FUNCTION(5, "I2S9_MCK") + ), + MTK_PIN( + 215, "GPIO215", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO215"), + MTK_FUNCTION(1, "AUD_SYNC_MOSI"), + MTK_FUNCTION(3, "I2S1_BCK"), + MTK_FUNCTION(4, "I2S7_BCK"), + MTK_FUNCTION(5, "I2S9_BCK") + ), + MTK_PIN( + 216, "GPIO216", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO216"), + MTK_FUNCTION(1, "AUD_DAT_MOSI0"), + MTK_FUNCTION(3, "I2S1_LRCK"), + MTK_FUNCTION(4, "I2S7_LRCK"), + MTK_FUNCTION(5, "I2S9_LRCK") + ), + MTK_PIN( + 217, "GPIO217", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO217"), + MTK_FUNCTION(1, "AUD_DAT_MOSI1"), + MTK_FUNCTION(3, "I2S1_DO"), + MTK_FUNCTION(4, "I2S7_DO"), + MTK_FUNCTION(5, "I2S9_DO") + ), + MTK_PIN( + 218, "GPIO218", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO218"), + MTK_FUNCTION(1, "AUD_DAT_MISO0"), + MTK_FUNCTION(2, "VOW_DAT_MISO"), + MTK_FUNCTION(3, "I2S2_LRCK"), + MTK_FUNCTION(4, "I2S6_LRCK"), + MTK_FUNCTION(5, "I2S8_LRCK") + ), + MTK_PIN( + 219, "GPIO219", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO219"), + MTK_FUNCTION(1, "AUD_DAT_MISO1"), + MTK_FUNCTION(2, "VOW_CLK_MISO"), + MTK_FUNCTION(3, "I2S2_DI"), + MTK_FUNCTION(4, "I2S6_DI"), + MTK_FUNCTION(5, "I2S8_DI") + ), + MTK_PIN( + 220, "GPIO220", + MTK_EINT_FUNCTION(0, 208), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO220") + ), + MTK_PIN( + 221, "GPIO221", + MTK_EINT_FUNCTION(0, 209), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO221") + ), + MTK_PIN( + 222, "GPIO222", + MTK_EINT_FUNCTION(0, 210), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO222") + ), + MTK_PIN( + 223, "GPIO223", + MTK_EINT_FUNCTION(0, 211), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO223") + ), + MTK_PIN( + 224, "GPIO224", + MTK_EINT_FUNCTION(0, 212), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO224") + ), + MTK_PIN( + 225, "GPIO225", + MTK_EINT_FUNCTION(0, 214), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO225") + ), + MTK_PIN( + 226, "GPIO226", + MTK_EINT_FUNCTION(0, 215), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO226") + ), + MTK_PIN( + 227, "GPIO227", + MTK_EINT_FUNCTION(0, 216), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO227") + ), +}; + +#endif /* __PINCTRL_MTK_MT8192_H */ diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 953126bf6657..68894e9e05d2 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -197,7 +197,7 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"), PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"), PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"), - PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), + PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */ PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"), PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"), PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"), diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index ba25c4654391..657e35a75d84 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -931,11 +931,6 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s, [NMK_GPIO_ALT_C+3] = "altC3", [NMK_GPIO_ALT_C+4] = "altC4", }; - const char *pulls[] = { - "none ", - "pull down", - "pull up ", - }; clk_enable(nmk_chip->clk); is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset)); @@ -946,7 +941,7 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s, mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); if (is_out) { - seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", + seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", gpio, label ?: "(none)", data_out ? "hi" : "lo", @@ -954,11 +949,12 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s, } else { int irq = chip->to_irq(chip, offset); struct irq_desc *desc = irq_to_desc(irq); - int pullidx = 0; + const int pullidx = pull ? 1 : 0; int val; - - if (pull) - pullidx = data_out ? 2 : 1; + static const char * const pulls[] = { + "none ", + "pull enabled", + }; seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s", gpio, diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index 42b12ea14d6b..ce2d8014b7e0 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -87,7 +87,7 @@ const struct regmap_config mcp23x08_regmap = { }; EXPORT_SYMBOL_GPL(mcp23x08_regmap); -static const struct reg_default mcp23x16_defaults[] = { +static const struct reg_default mcp23x17_defaults[] = { {.reg = MCP_IODIR << 1, .def = 0xffff}, {.reg = MCP_IPOL << 1, .def = 0x0000}, {.reg = MCP_GPINTEN << 1, .def = 0x0000}, @@ -98,23 +98,23 @@ static const struct reg_default mcp23x16_defaults[] = { {.reg = MCP_OLAT << 1, .def = 0x0000}, }; -static const struct regmap_range mcp23x16_volatile_range = { +static const struct regmap_range mcp23x17_volatile_range = { .range_min = MCP_INTF << 1, .range_max = MCP_GPIO << 1, }; -static const struct regmap_access_table mcp23x16_volatile_table = { - .yes_ranges = &mcp23x16_volatile_range, +static const struct regmap_access_table mcp23x17_volatile_table = { + .yes_ranges = &mcp23x17_volatile_range, .n_yes_ranges = 1, }; -static const struct regmap_range mcp23x16_precious_range = { - .range_min = MCP_GPIO << 1, +static const struct regmap_range mcp23x17_precious_range = { + .range_min = MCP_INTCAP << 1, .range_max = MCP_GPIO << 1, }; -static const struct regmap_access_table mcp23x16_precious_table = { - .yes_ranges = &mcp23x16_precious_range, +static const struct regmap_access_table mcp23x17_precious_table = { + .yes_ranges = &mcp23x17_precious_range, .n_yes_ranges = 1, }; @@ -124,10 +124,10 @@ const struct regmap_config mcp23x17_regmap = { .reg_stride = 2, .max_register = MCP_OLAT << 1, - .volatile_table = &mcp23x16_volatile_table, - .precious_table = &mcp23x16_precious_table, - .reg_defaults = mcp23x16_defaults, - .num_reg_defaults = ARRAY_SIZE(mcp23x16_defaults), + .volatile_table = &mcp23x17_volatile_table, + .precious_table = &mcp23x17_precious_table, + .reg_defaults = mcp23x17_defaults, + .num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults), .cache_type = REGCACHE_FLAT, .val_format_endian = REGMAP_ENDIAN_LITTLE, }; @@ -564,7 +564,7 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, ret = mcp_read(mcp, MCP_IOCON, &status); if (ret < 0) - goto fail; + return dev_err_probe(dev, ret, "can't identify chip %d\n", addr); mcp->irq_controller = device_property_read_bool(dev, "interrupt-controller"); @@ -598,7 +598,7 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, ret = mcp_write(mcp, MCP_IOCON, status); if (ret < 0) - goto fail; + return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr); } if (mcp->irq && mcp->irq_controller) { @@ -616,7 +616,7 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp); if (ret < 0) - goto fail; + return dev_err_probe(dev, ret, "can't add GPIO chip\n"); mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops; mcp->pinctrl_desc.confops = &mcp_pinconf_ops; @@ -628,18 +628,17 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, mcp->pinctrl_desc.owner = THIS_MODULE; mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp); - if (IS_ERR(mcp->pctldev)) { - ret = PTR_ERR(mcp->pctldev); - goto fail; - } + if (IS_ERR(mcp->pctldev)) + return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n"); - if (mcp->irq) + if (mcp->irq) { ret = mcp23s08_irq_setup(mcp); + if (ret) + return dev_err_probe(dev, ret, "can't setup IRQ\n"); + } -fail: - if (ret < 0) - dev_dbg(dev, "can't setup chip %d, --> %d\n", addr, ret); - return ret; + return 0; } EXPORT_SYMBOL_GPL(mcp23s08_probe_one); + MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index b325a136ac48..c110f780407b 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -1154,12 +1154,6 @@ static int sx150x_probe(struct i2c_client *client, return ret; } - ret = pinctrl_enable(pctl->pctldev); - if (ret) { - dev_err(dev, "Failed to enable pinctrl device\n"); - return ret; - } - /* Register GPIO controller */ pctl->gpio.base = -1; pctl->gpio.ngpio = pctl->data->npins; @@ -1238,6 +1232,17 @@ static int sx150x_probe(struct i2c_client *client, if (ret) return ret; + /* + * Pin control functions need to be enabled AFTER registering the + * GPIO chip because sx150x_pinconf_set() calls + * sx150x_gpio_direction_output(). + */ + ret = pinctrl_enable(pctl->pctldev); + if (ret) { + dev_err(dev, "Failed to enable pinctrl device\n"); + return ret; + } + ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev), 0, 0, pctl->data->npins); if (ret) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index f8ff30cdafa6..5fe7b8aaf69d 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -62,6 +62,15 @@ config PINCTRL_IPQ6018 Qualcomm Technologies Inc. IPQ6018 platform. Select this for IPQ6018. +config PINCTRL_MSM8226 + tristate "Qualcomm 8226 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc MSM8226 platform. + config PINCTRL_MSM8660 tristate "Qualcomm 8660 pin controller driver" depends on GPIOLIB && OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 061ec9fb659b..9e3d9c91a444 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o +obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o diff --git a/drivers/pinctrl/qcom/pinctrl-msm8226.c b/drivers/pinctrl/qcom/pinctrl-msm8226.c new file mode 100644 index 000000000000..98779e62e951 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8226.c @@ -0,0 +1,630 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc msm8226_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + + PINCTRL_PIN(117, "SDC1_CLK"), + PINCTRL_PIN(118, "SDC1_CMD"), + PINCTRL_PIN(119, "SDC1_DATA"), + PINCTRL_PIN(120, "SDC2_CLK"), + PINCTRL_PIN(121, "SDC2_CMD"), + PINCTRL_PIN(122, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); + +static const unsigned int sdc1_clk_pins[] = { 117 }; +static const unsigned int sdc1_cmd_pins[] = { 118 }; +static const unsigned int sdc1_data_pins[] = { 119 }; +static const unsigned int sdc2_clk_pins[] = { 120 }; +static const unsigned int sdc2_cmd_pins[] = { 121 }; +static const unsigned int sdc2_data_pins[] = { 122 }; + +#define FUNCTION(fname) \ + [MSM_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + MSM_MUX_gpio, \ + MSM_MUX_##f1, \ + MSM_MUX_##f2, \ + MSM_MUX_##f3, \ + MSM_MUX_##f4, \ + MSM_MUX_##f5, \ + MSM_MUX_##f6, \ + MSM_MUX_##f7 \ + }, \ + .nfuncs = 8, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x1008 + 0x10 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +/* + * TODO: Add the rest of the possible functions and fill out + * the pingroup table below. + */ +enum msm8226_functions { + MSM_MUX_gpio, + MSM_MUX_cci_i2c0, + MSM_MUX_blsp_i2c1, + MSM_MUX_blsp_i2c2, + MSM_MUX_blsp_i2c3, + MSM_MUX_blsp_i2c5, + MSM_MUX_blsp_spi1, + MSM_MUX_blsp_spi2, + MSM_MUX_blsp_spi3, + MSM_MUX_blsp_spi5, + MSM_MUX_blsp_uart1, + MSM_MUX_blsp_uart2, + MSM_MUX_blsp_uart3, + MSM_MUX_blsp_uart5, + MSM_MUX_blsp_uim1, + MSM_MUX_blsp_uim2, + MSM_MUX_blsp_uim3, + MSM_MUX_blsp_uim5, + MSM_MUX_cam_mclk0, + MSM_MUX_cam_mclk1, + MSM_MUX_wlan, + MSM_MUX_NA, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", +}; + +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; + +static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" }; +static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" }; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; + +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; + +static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" }; +static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" }; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; + +static const char * const blsp_uart3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; + +static const char * const blsp_uim3_groups[] = { "gpio8", "gpio9" }; +static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" }; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; + +static const char * const blsp_uart5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19" +}; + +static const char * const blsp_uim5_groups[] = { "gpio16", "gpio17" }; +static const char * const blsp_i2c5_groups[] = { "gpio18", "gpio19" }; +static const char * const blsp_spi5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19" +}; + +static const char * const cci_i2c0_groups[] = { "gpio29", "gpio30" }; + +static const char * const cam_mclk0_groups[] = { "gpio26" }; +static const char * const cam_mclk1_groups[] = { "gpio27" }; + +static const char * const wlan_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44" +}; + +static const struct msm_function msm8226_functions[] = { + FUNCTION(gpio), + FUNCTION(cci_i2c0), + FUNCTION(blsp_uim1), + FUNCTION(blsp_uim2), + FUNCTION(blsp_uim3), + FUNCTION(blsp_uim5), + FUNCTION(blsp_i2c1), + FUNCTION(blsp_i2c2), + FUNCTION(blsp_i2c3), + FUNCTION(blsp_i2c5), + FUNCTION(blsp_spi1), + FUNCTION(blsp_spi2), + FUNCTION(blsp_spi3), + FUNCTION(blsp_spi5), + FUNCTION(blsp_uart1), + FUNCTION(blsp_uart2), + FUNCTION(blsp_uart3), + FUNCTION(blsp_uart5), + FUNCTION(cam_mclk0), + FUNCTION(cam_mclk1), + FUNCTION(wlan), +}; + +static const struct msm_pingroup msm8226_groups[] = { + PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, NA, NA, NA, NA), + PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, NA, NA, NA, NA), + PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA), + PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA), + PINGROUP(12, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(13, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(14, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA), + PINGROUP(17, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA), + PINGROUP(18, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA), + PINGROUP(19, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA), + PINGROUP(20, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(23, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(24, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(26, cam_mclk0, NA, NA, NA, NA, NA, NA), + PINGROUP(27, cam_mclk1, NA, NA, NA, NA, NA, NA), + PINGROUP(28, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(29, cci_i2c0, NA, NA, NA, NA, NA, NA), + PINGROUP(30, cci_i2c0, NA, NA, NA, NA, NA, NA), + PINGROUP(31, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(32, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(35, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(38, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(40, wlan, NA, NA, NA, NA, NA, NA), + PINGROUP(41, wlan, NA, NA, NA, NA, NA, NA), + PINGROUP(42, wlan, NA, NA, NA, NA, NA, NA), + PINGROUP(43, wlan, NA, NA, NA, NA, NA, NA), + PINGROUP(44, wlan, NA, NA, NA, NA, NA, NA), + PINGROUP(45, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(46, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(47, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(48, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(49, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(51, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(90, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(91, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(92, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(93, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(94, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(95, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(96, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(98, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(99, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(101, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(102, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(103, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(111, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(112, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(113, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(114, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(115, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(116, NA, NA, NA, NA, NA, NA, NA), + SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3), + SDC_PINGROUP(sdc1_data, 0x2044, 9, 0), + SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6), + SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3), + SDC_PINGROUP(sdc2_data, 0x2048, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 117 + +static const struct msm_pinctrl_soc_data msm8226_pinctrl = { + .pins = msm8226_pins, + .npins = ARRAY_SIZE(msm8226_pins), + .functions = msm8226_functions, + .nfunctions = ARRAY_SIZE(msm8226_functions), + .groups = msm8226_groups, + .ngroups = ARRAY_SIZE(msm8226_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int msm8226_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8226_pinctrl); +} + +static const struct of_device_id msm8226_pinctrl_of_match[] = { + { .compatible = "qcom,msm8226-pinctrl", }, + { }, +}; + +static struct platform_driver msm8226_pinctrl_driver = { + .driver = { + .name = "msm8226-pinctrl", + .of_match_table = msm8226_pinctrl_of_match, + }, + .probe = msm8226_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8226_pinctrl_init(void) +{ + return platform_driver_register(&msm8226_pinctrl_driver); +} +arch_initcall(msm8226_pinctrl_init); + +static void __exit msm8226_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8226_pinctrl_driver); +} +module_exit(msm8226_pinctrl_exit); + +MODULE_AUTHOR("Bartosz Dudziak <bartosz.dudziak@snejp.pl>"); +MODULE_DESCRIPTION("Qualcomm MSM8226 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8226_pinctrl_of_match); diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index f7aae200ee15..593293584ecc 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -94,6 +94,16 @@ config PINCTRL_SUN50I_A64_R default ARM64 && ARCH_SUNXI select PINCTRL_SUNXI +config PINCTRL_SUN50I_A100 + bool "Support for the Allwinner A100 PIO" + default ARM64 && ARCH_SUNXI + select PINCTRL_SUNXI + +config PINCTRL_SUN50I_A100_R + bool "Support for the Allwinner A100 R-PIO" + default ARM64 && ARCH_SUNXI + select PINCTRL_SUNXI + config PINCTRL_SUN50I_H5 bool "Support for the Allwinner H5 PIO" default ARM64 && ARCH_SUNXI diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index fafcdae8134f..8b7ff0dc3bdf 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -13,6 +13,8 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o obj-$(CONFIG_PINCTRL_SUN50I_A64_R) += pinctrl-sun50i-a64-r.o +obj-$(CONFIG_PINCTRL_SUN50I_A100) += pinctrl-sun50i-a100.o +obj-$(CONFIG_PINCTRL_SUN50I_A100_R) += pinctrl-sun50i-a100-r.o obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c new file mode 100644 index 000000000000..21054fcacd34 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> + * + * Based on: + * huangshuosheng <huangshuosheng@allwinnertech.com> + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin a100_r_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2c0"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2c0"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_uart0"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2c1"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2c1"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_pwm"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_cir"), /* IN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), +}; + +static const struct sunxi_pinctrl_desc a100_r_pinctrl_data = { + .pins = a100_r_pins, + .npins = ARRAY_SIZE(a100_r_pins), + .pin_base = PL_BASE, + .irq_banks = 1, +}; + +static int a100_r_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, &a100_r_pinctrl_data); +} + +static const struct of_device_id a100_r_pinctrl_match[] = { + { .compatible = "allwinner,sun50i-a100-r-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, a100_r_pinctrl_match); + +static struct platform_driver a100_r_pinctrl_driver = { + .probe = a100_r_pinctrl_probe, + .driver = { + .name = "sun50iw10p1-r-pinctrl", + .of_match_table = a100_r_pinctrl_match, + }, +}; +module_platform_driver(a100_r_pinctrl_driver); diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c new file mode 100644 index 000000000000..19cfd1e76ee2 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c @@ -0,0 +1,708 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> + * + * Based on: + * huangshuosheng <huangshuosheng@allwinnertech.com> + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin a100_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ + SUNXI_FUNCTION(0x3, "spi2"), /* CS */ + SUNXI_FUNCTION(0x4, "jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ + SUNXI_FUNCTION(0x3, "spi2"), /* CLK */ + SUNXI_FUNCTION(0x4, "jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ + SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */ + SUNXI_FUNCTION(0x4, "jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ + SUNXI_FUNCTION(0x3, "spi2"), /* MISO */ + SUNXI_FUNCTION(0x4, "jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ + SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */ + SUNXI_FUNCTION(0x4, "jtag_gpu"), /* MS_GPU */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ + SUNXI_FUNCTION(0x3, "i2s0"), /* BCLK */ + SUNXI_FUNCTION(0x4, "jtag_gpu"), /* CK_GPU */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2s0"), /* LRCK */ + SUNXI_FUNCTION(0x4, "jtag_gpu"), /* DO_GPU */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spdif"), /* DIN */ + SUNXI_FUNCTION(0x3, "i2s0_dout0"), /* DOUT0 */ + SUNXI_FUNCTION(0x4, "i2s0_din1"), /* DIN1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spdif"), /* DOUT */ + SUNXI_FUNCTION(0x3, "i2s0_din0"), /* DIN0 */ + SUNXI_FUNCTION(0x4, "i2s0_dout1"), /* DOUT1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x4, "jtag_gpu"), /* DI_GPU */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x4, "pwm1"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), + /* HOLE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* WE */ + SUNXI_FUNCTION(0x3, "mmc2"), /* DS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ + SUNXI_FUNCTION(0x3, "mmc2"), /* RST */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ + SUNXI_FUNCTION(0x4, "spi0"), /* MOSI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */ + SUNXI_FUNCTION(0x4, "spi0"), /* CS0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */ + SUNXI_FUNCTION(0x4, "spi0"), /* MISO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RE */ + SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */ + SUNXI_FUNCTION(0x4, "spi0"), /* CS1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ + SUNXI_FUNCTION(0x4, "spi0"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */ + SUNXI_FUNCTION(0x4, "spi0"), /* WP */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */ + SUNXI_FUNCTION(0x4, "spi0"), /* HOLD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), + /* HOLE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* D0P */ + SUNXI_FUNCTION(0x4, "dsi0"), /* DP0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* D0N */ + SUNXI_FUNCTION(0x4, "dsi0"), /* DM0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* D1P */ + SUNXI_FUNCTION(0x4, "dsi0"), /* DP1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* D1N */ + SUNXI_FUNCTION(0x4, "dsi0"), /* DM1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* D2P */ + SUNXI_FUNCTION(0x4, "dsi0"), /* CKP */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* D2N */ + SUNXI_FUNCTION(0x4, "dsi0"), /* CKM */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* CKP */ + SUNXI_FUNCTION(0x4, "dsi0"), /* DP2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* CKN */ + SUNXI_FUNCTION(0x4, "dsi0"), /* DM2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x4, "dsi0"), /* DP3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x4, "dsi0"), /* DM3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ + SUNXI_FUNCTION(0x4, "spi1"), /* CS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ + SUNXI_FUNCTION(0x4, "spi1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x4, "spi1"), /* MISO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION(0x4, "uart3"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart4"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION(0x4, "uart4"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "pwm2"), + SUNXI_FUNCTION(0x4, "uart4"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 20)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "pwm3"), + SUNXI_FUNCTION(0x4, "uart4"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 21)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm1"), + SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 22)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm0"), + SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 23)), + /* HOLE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ + SUNXI_FUNCTION(0x3, "pll"), /* LOCK_DBG */ + SUNXI_FUNCTION(0x4, "i2s2"), /* MCLK */ + SUNXI_FUNCTION(0x5, "ledc"), /* LEDC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "bist0"), /* RESULT0 */ + SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SM_VS */ + SUNXI_FUNCTION(0x3, "bist0"), /* RESULT1 */ + SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */ + SUNXI_FUNCTION(0x5, "tcon0"), /* TRIG */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "bist0"), /* RESULT2 */ + SUNXI_FUNCTION(0x4, "i2s2"), /* DOUT0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "bist0"), /* RESULT3 */ + SUNXI_FUNCTION(0x4, "i2s2"), /* DIN0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), + /* HOLE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS1 */ + SUNXI_FUNCTION(0x4, "jtag_gpu"), /* MS_GPU */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x3, "jtag"), /* DI1 */ + SUNXI_FUNCTION(0x4, "jtag_gpu"), /* DI_GPU */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO */ + SUNXI_FUNCTION(0x4, "jtag_gpu"), /* DO_GPU */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart0"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK */ + SUNXI_FUNCTION(0x4, "jtag_gpu"), /* CK_GPU */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 6)), + /* HOLE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ + SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2s1_dout0"), /* DOUT0 */ + SUNXI_FUNCTION(0x4, "i2s1_din1"), /* DIN1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 12)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2s1_din0"), /* DIN0 */ + SUNXI_FUNCTION(0x4, "i2s1_dout1"), /* DOUT1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 13)), + /* HOLE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ + SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ + SUNXI_FUNCTION(0x3, "cir0"), /* OUT */ + SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart3"), /* TX */ + SUNXI_FUNCTION(0x3, "spi1"), /* CS */ + SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart3"), /* RX */ + SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x4, "ledc"), + SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart3"), /* RTS */ + SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart3"), /* CTS */ + SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x4, "spdif"), /* OUT */ + SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dmic"), /* CLK */ + SUNXI_FUNCTION(0x3, "spi2"), /* CS */ + SUNXI_FUNCTION(0x4, "i2s2"), /* MCLK */ + SUNXI_FUNCTION(0x5, "i2s2_din2"), /* DIN2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */ + SUNXI_FUNCTION(0x3, "spi2"), /* CLK */ + SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */ + SUNXI_FUNCTION(0x5, "emac0"), /* MDC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */ + SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */ + SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */ + SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dmic"), /* DATA2 */ + SUNXI_FUNCTION(0x3, "spi2"), /* MISO */ + SUNXI_FUNCTION(0x4, "i2s2_dout0"), /* DOUT0 */ + SUNXI_FUNCTION(0x5, "i2s2_din1"), /* DIN1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dmic"), /* DATA3 */ + SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */ + SUNXI_FUNCTION(0x4, "i2s2_din0"), /* DIN0 */ + SUNXI_FUNCTION(0x5, "i2s2_dout1"), /* DOUT1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 12)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */ + SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */ + SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */ + SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */ + SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */ + SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */ + SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */ + SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */ + SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "cir0"), /* OUT */ + SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */ + SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */ + SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "cir0"), /* IN */ + SUNXI_FUNCTION(0x3, "i2s3_dout3"), /* DOUT3 */ + SUNXI_FUNCTION(0x4, "i2s3_din3"), /* DIN3 */ + SUNXI_FUNCTION(0x5, "ledc"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 19)), +}; + +static const unsigned int a100_irq_bank_map[] = { 0, 1, 2, 3, 4, 5, 6}; + +static const struct sunxi_pinctrl_desc a100_pinctrl_data = { + .pins = a100_pins, + .npins = ARRAY_SIZE(a100_pins), + .irq_banks = 7, + .irq_bank_map = a100_irq_bank_map, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, +}; + +static int a100_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, &a100_pinctrl_data); +} + +static const struct of_device_id a100_pinctrl_match[] = { + { .compatible = "allwinner,sun50i-a100-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, a100_pinctrl_match); + +static struct platform_driver a100_pinctrl_driver = { + .probe = a100_pinctrl_probe, + .driver = { + .name = "sun50i-a100-pinctrl", + .of_match_table = a100_pinctrl_match, + }, +}; +module_platform_driver(a100_pinctrl_driver); diff --git a/drivers/pinctrl/visconti/Kconfig b/drivers/pinctrl/visconti/Kconfig new file mode 100644 index 000000000000..198ec33189cc --- /dev/null +++ b/drivers/pinctrl/visconti/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +config PINCTRL_VISCONTI + bool + select PINMUX + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + +config PINCTRL_TMPV7700 + bool "Toshiba Visconti TMPV7700 series pinctrl driver" + depends on OF + depends on ARM64 || COMPILE_TEST + select PINCTRL_VISCONTI + default ARM64 && ARCH_VISCONTI diff --git a/drivers/pinctrl/visconti/Makefile b/drivers/pinctrl/visconti/Makefile new file mode 100644 index 000000000000..43b2eb663bce --- /dev/null +++ b/drivers/pinctrl/visconti/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PINCTRL_VISCONTI) += pinctrl-common.o +obj-$(CONFIG_PINCTRL_TMPV7700) += pinctrl-tmpv7700.o diff --git a/drivers/pinctrl/visconti/pinctrl-common.c b/drivers/pinctrl/visconti/pinctrl-common.c new file mode 100644 index 000000000000..0cb10b7b4430 --- /dev/null +++ b/drivers/pinctrl/visconti/pinctrl-common.c @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 TOSHIBA CORPORATION + * Copyright (c) 2020 Toshiba Electronic Devices & Storage Corporation + * Copyright (c) 2020 Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + */ + +#include <linux/init.h> +#include <linux/of.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include "pinctrl-common.h" +#include "../core.h" +#include "../pinconf.h" +#include "../pinctrl-utils.h" + +#define DSEL_MASK GENMASK(3, 0) + +/* private data */ +struct visconti_pinctrl { + void __iomem *base; + struct device *dev; + struct pinctrl_dev *pctl; + struct pinctrl_desc pctl_desc; + + const struct visconti_pinctrl_devdata *devdata; + + spinlock_t lock; /* protect pinctrl register */ +}; + +/* pinconf */ +static int visconti_pin_config_set(struct pinctrl_dev *pctldev, + unsigned int _pin, + unsigned long *configs, + unsigned int num_configs) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + const struct visconti_desc_pin *pin = &priv->devdata->pins[_pin]; + enum pin_config_param param; + unsigned int arg; + int i, ret = 0; + unsigned int val, set_val, pude_val; + unsigned long flags; + + dev_dbg(priv->dev, "%s: pin = %d (%s)\n", __func__, _pin, pin->pin.name); + + spin_lock_irqsave(&priv->lock, flags); + + for (i = 0; i < num_configs; i++) { + set_val = 0; + pude_val = 0; + + param = pinconf_to_config_param(configs[i]); + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + set_val = 1; + fallthrough; + case PIN_CONFIG_BIAS_PULL_DOWN: + /* update pudsel setting */ + val = readl(priv->base + pin->pudsel_offset); + val &= ~BIT(pin->pud_shift); + val |= set_val << pin->pud_shift; + writel(val, priv->base + pin->pudsel_offset); + pude_val = 1; + fallthrough; + case PIN_CONFIG_BIAS_DISABLE: + /* update pude setting */ + val = readl(priv->base + pin->pude_offset); + val &= ~BIT(pin->pud_shift); + val |= pude_val << pin->pud_shift; + writel(val, priv->base + pin->pude_offset); + dev_dbg(priv->dev, "BIAS(%d): off = 0x%x val = 0x%x\n", + param, pin->pude_offset, val); + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + arg = pinconf_to_config_argument(configs[i]); + dev_dbg(priv->dev, "DRV_STR arg = %d\n", arg); + switch (arg) { + case 2: + case 4: + case 8: + case 16: + case 24: + case 32: + /* + * I/O drive capacity setting: + * 2mA: 0 + * 4mA: 1 + * 8mA: 3 + * 16mA: 7 + * 24mA: 11 + * 32mA: 15 + */ + set_val = DIV_ROUND_CLOSEST(arg, 2) - 1; + break; + default: + ret = -EINVAL; + goto err; + } + /* update drive setting */ + val = readl(priv->base + pin->dsel_offset); + val &= ~(DSEL_MASK << pin->dsel_shift); + val |= set_val << pin->dsel_shift; + writel(val, priv->base + pin->dsel_offset); + break; + + default: + ret = -EOPNOTSUPP; + goto err; + } + } +err: + spin_unlock_irqrestore(&priv->lock, flags); + return ret; +} + +static int visconti_pin_config_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *configs, + unsigned int num_configs) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + const unsigned int *pins; + unsigned int num_pins; + int i, ret; + + pins = priv->devdata->groups[selector].pins; + num_pins = priv->devdata->groups[selector].nr_pins; + + dev_dbg(priv->dev, "%s: select = %d, n_pin = %d, n_config = %d\n", + __func__, selector, num_pins, num_configs); + + for (i = 0; i < num_pins; i++) { + ret = visconti_pin_config_set(pctldev, pins[i], + configs, num_configs); + if (ret) + return ret; + } + + return 0; +} +static const struct pinconf_ops visconti_pinconf_ops = { + .is_generic = true, + .pin_config_set = visconti_pin_config_set, + .pin_config_group_set = visconti_pin_config_group_set, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + +/* pinctrl */ +static int visconti_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + return priv->devdata->nr_groups; +} + +static const char *visconti_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + return priv->devdata->groups[selector].name; +} + +static int visconti_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + *pins = priv->devdata->groups[selector].pins; + *num_pins = priv->devdata->groups[selector].nr_pins; + + return 0; +} + +static const struct pinctrl_ops visconti_pinctrl_ops = { + .get_groups_count = visconti_get_groups_count, + .get_group_name = visconti_get_group_name, + .get_group_pins = visconti_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_free_map, +}; + +/* pinmux */ +static int visconti_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + return priv->devdata->nr_functions; +} + +static const char *visconti_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + return priv->devdata->functions[selector].name; +} + +static int visconti_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned * const num_groups) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + *groups = priv->devdata->functions[selector].groups; + *num_groups = priv->devdata->functions[selector].nr_groups; + + return 0; +} + +static int visconti_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, unsigned int group) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + const struct visconti_pin_function *func = &priv->devdata->functions[function]; + const struct visconti_pin_group *grp = &priv->devdata->groups[group]; + const struct visconti_mux *mux = &grp->mux; + unsigned int val; + unsigned long flags; + + dev_dbg(priv->dev, "%s: function = %d(%s) group = %d(%s)\n", __func__, + function, func->name, group, grp->name); + + spin_lock_irqsave(&priv->lock, flags); + + /* update mux */ + val = readl(priv->base + mux->offset); + val &= ~mux->mask; + val |= mux->val; + writel(val, priv->base + mux->offset); + + spin_unlock_irqrestore(&priv->lock, flags); + + dev_dbg(priv->dev, "[%x]: 0x%x\n", mux->offset, val); + + return 0; +} + +static const struct pinmux_ops visconti_pinmux_ops = { + .get_functions_count = visconti_get_functions_count, + .get_function_name = visconti_get_function_name, + .get_function_groups = visconti_get_function_groups, + .set_mux = visconti_set_mux, + .strict = true, +}; + +int visconti_pinctrl_probe(struct platform_device *pdev, + const struct visconti_pinctrl_devdata *devdata) +{ + struct device *dev = &pdev->dev; + struct visconti_pinctrl *priv; + struct pinctrl_pin_desc *pins; + int i, ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + priv->devdata = devdata; + spin_lock_init(&priv->lock); + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) { + dev_err(dev, "unable to map I/O space\n"); + return PTR_ERR(priv->base); + } + + pins = devm_kcalloc(dev, devdata->nr_pins, + sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < devdata->nr_pins; i++) + pins[i] = devdata->pins[i].pin; + + priv->pctl_desc.name = dev_name(dev); + priv->pctl_desc.owner = THIS_MODULE; + priv->pctl_desc.pins = pins; + priv->pctl_desc.npins = devdata->nr_pins; + priv->pctl_desc.confops = &visconti_pinconf_ops; + priv->pctl_desc.pctlops = &visconti_pinctrl_ops; + priv->pctl_desc.pmxops = &visconti_pinmux_ops; + + ret = devm_pinctrl_register_and_init(dev, &priv->pctl_desc, + priv, &priv->pctl); + if (ret) { + dev_err(dev, "couldn't register pinctrl: %d\n", ret); + return ret; + } + + if (devdata->unlock) + devdata->unlock(priv->base); + + return pinctrl_enable(priv->pctl); +} diff --git a/drivers/pinctrl/visconti/pinctrl-common.h b/drivers/pinctrl/visconti/pinctrl-common.h new file mode 100644 index 000000000000..56a2eb0225fb --- /dev/null +++ b/drivers/pinctrl/visconti/pinctrl-common.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 TOSHIBA CORPORATION + * Copyright (c) 2020 Toshiba Electronic Devices & Storage Corporation + * Copyright (c) 2020 Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + */ + +#ifndef __VISCONTI_PINCTRL_COMMON_H__ +#define __VISCONTI_PINCTRL_COMMON_H__ + +struct pinctrl_pin_desc; + +/* PIN */ +#define VISCONTI_PINS(pins_name, ...) \ + static const unsigned int pins_name ## _pins[] = { __VA_ARGS__ } + +struct visconti_desc_pin { + struct pinctrl_pin_desc pin; + unsigned int dsel_offset; + unsigned int dsel_shift; + unsigned int pude_offset; + unsigned int pudsel_offset; + unsigned int pud_shift; +}; + +#define VISCONTI_PIN(_pin, dsel, d_sh, pude, pudsel, p_sh) \ +{ \ + .pin = _pin, \ + .dsel_offset = dsel, \ + .dsel_shift = d_sh, \ + .pude_offset = pude, \ + .pudsel_offset = pudsel, \ + .pud_shift = p_sh, \ +} + +/* Group */ +#define VISCONTI_GROUPS(groups_name, ...) \ + static const char * const groups_name ## _grps[] = { __VA_ARGS__ } + +struct visconti_mux { + unsigned int offset; + unsigned int mask; + unsigned int val; +}; + +struct visconti_pin_group { + const char *name; + const unsigned int *pins; + unsigned int nr_pins; + struct visconti_mux mux; +}; + +#define VISCONTI_PIN_GROUP(group_name, off, msk, v) \ +{ \ + .name = __stringify(group_name) "_grp", \ + .pins = group_name ## _pins, \ + .nr_pins = ARRAY_SIZE(group_name ## _pins), \ + .mux = { \ + .offset = off, \ + .mask = msk, \ + .val = v, \ + } \ +} + +/* MUX */ +struct visconti_pin_function { + const char *name; + const char * const *groups; + unsigned int nr_groups; +}; + +#define VISCONTI_PIN_FUNCTION(func) \ +{ \ + .name = #func, \ + .groups = func ## _grps, \ + .nr_groups = ARRAY_SIZE(func ## _grps), \ +} + +/* chip dependent data */ +struct visconti_pinctrl_devdata { + const struct visconti_desc_pin *pins; + unsigned int nr_pins; + const struct visconti_pin_group *groups; + unsigned int nr_groups; + const struct visconti_pin_function *functions; + unsigned int nr_functions; + + const struct visconti_mux *gpio_mux; + + void (*unlock)(void __iomem *base); +}; + +int visconti_pinctrl_probe(struct platform_device *pdev, + const struct visconti_pinctrl_devdata *devdata); + +#endif /* __VISCONTI_PINCTRL_COMMON_H__ */ diff --git a/drivers/pinctrl/visconti/pinctrl-tmpv7700.c b/drivers/pinctrl/visconti/pinctrl-tmpv7700.c new file mode 100644 index 000000000000..38a00d514f74 --- /dev/null +++ b/drivers/pinctrl/visconti/pinctrl-tmpv7700.c @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 TOSHIBA CORPORATION + * Copyright (c) 2020 Toshiba Electronic Devices & Storage Corporation + * Copyright (c) 2020 Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + */ + +#include <linux/init.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include "pinctrl-common.h" + +#define tmpv7700_MAGIC_NUM 0x4932f70e + +/* register offset */ +#define REG_KEY_CTRL 0x0000 +#define REG_KEY_CMD 0x0004 +#define REG_PINMUX1 0x3000 +#define REG_PINMUX2 0x3004 +#define REG_PINMUX3 0x3008 +#define REG_PINMUX4 0x300c +#define REG_PINMUX5 0x3010 +#define REG_IOSET 0x3014 +#define REG_IO_VSEL 0x3018 +#define REG_IO_DSEL1 0x301c +#define REG_IO_DSEL2 0x3020 +#define REG_IO_DSEL3 0x3024 +#define REG_IO_DSEL4 0x3028 +#define REG_IO_DSEL5 0x302c +#define REG_IO_DSEL6 0x3030 +#define REG_IO_DSEL7 0x3034 +#define REG_IO_DSEL8 0x3038 +#define REG_IO_PUDE1 0x303c +#define REG_IO_PUDE2 0x3040 +#define REG_IO_PUDSEL1 0x3044 +#define REG_IO_PUDSEL2 0x3048 + +/* PIN */ +static const struct visconti_desc_pin pins_tmpv7700[] = { + VISCONTI_PIN(PINCTRL_PIN(0, "gpio0"), REG_IO_DSEL4, 24, + REG_IO_PUDE1, REG_IO_PUDSEL1, 30), + VISCONTI_PIN(PINCTRL_PIN(1, "gpio1"), REG_IO_DSEL4, 28, + REG_IO_PUDE1, REG_IO_PUDSEL1, 31), + VISCONTI_PIN(PINCTRL_PIN(2, "gpio2"), REG_IO_DSEL5, 0, + REG_IO_PUDE2, REG_IO_PUDSEL2, 0), + VISCONTI_PIN(PINCTRL_PIN(3, "gpio3"), REG_IO_DSEL5, 4, + REG_IO_PUDE2, REG_IO_PUDSEL2, 1), + VISCONTI_PIN(PINCTRL_PIN(4, "gpio4"), REG_IO_DSEL5, 8, + REG_IO_PUDE2, REG_IO_PUDSEL2, 2), + VISCONTI_PIN(PINCTRL_PIN(5, "gpio5"), REG_IO_DSEL5, 12, + REG_IO_PUDE2, REG_IO_PUDSEL2, 3), + VISCONTI_PIN(PINCTRL_PIN(6, "gpio6"), REG_IO_DSEL5, 16, + REG_IO_PUDE2, REG_IO_PUDSEL2, 4), + VISCONTI_PIN(PINCTRL_PIN(7, "gpio7"), REG_IO_DSEL5, 20, + REG_IO_PUDE2, REG_IO_PUDSEL2, 5), + VISCONTI_PIN(PINCTRL_PIN(8, "gpio8"), REG_IO_DSEL5, 24, + REG_IO_PUDE2, REG_IO_PUDSEL2, 6), + VISCONTI_PIN(PINCTRL_PIN(9, "gpio9"), REG_IO_DSEL5, 28, + REG_IO_PUDE2, REG_IO_PUDSEL2, 7), + VISCONTI_PIN(PINCTRL_PIN(10, "gpio10"), REG_IO_DSEL6, 0, + REG_IO_PUDE2, REG_IO_PUDSEL2, 8), + VISCONTI_PIN(PINCTRL_PIN(11, "gpio11"), REG_IO_DSEL6, 4, + REG_IO_PUDE2, REG_IO_PUDSEL2, 9), + VISCONTI_PIN(PINCTRL_PIN(12, "gpio12"), REG_IO_DSEL6, 8, + REG_IO_PUDE2, REG_IO_PUDSEL2, 10), + VISCONTI_PIN(PINCTRL_PIN(13, "gpio13"), REG_IO_DSEL6, 12, + REG_IO_PUDE2, REG_IO_PUDSEL2, 11), + VISCONTI_PIN(PINCTRL_PIN(14, "gpio14"), REG_IO_DSEL6, 16, + REG_IO_PUDE2, REG_IO_PUDSEL2, 12), + VISCONTI_PIN(PINCTRL_PIN(15, "gpio15"), REG_IO_DSEL6, 20, + REG_IO_PUDE2, REG_IO_PUDSEL2, 13), + VISCONTI_PIN(PINCTRL_PIN(16, "gpio16"), REG_IO_DSEL6, 24, + REG_IO_PUDE2, REG_IO_PUDSEL2, 14), + VISCONTI_PIN(PINCTRL_PIN(17, "gpio17"), REG_IO_DSEL6, 28, + REG_IO_PUDE2, REG_IO_PUDSEL2, 15), + VISCONTI_PIN(PINCTRL_PIN(18, "gpio18"), REG_IO_DSEL7, 0, + REG_IO_PUDE2, REG_IO_PUDSEL2, 16), + VISCONTI_PIN(PINCTRL_PIN(19, "gpio19"), REG_IO_DSEL7, 4, + REG_IO_PUDE2, REG_IO_PUDSEL2, 17), + VISCONTI_PIN(PINCTRL_PIN(20, "gpio20"), REG_IO_DSEL7, 8, + REG_IO_PUDE2, REG_IO_PUDSEL2, 18), + VISCONTI_PIN(PINCTRL_PIN(21, "gpio21"), REG_IO_DSEL7, 12, + REG_IO_PUDE2, REG_IO_PUDSEL2, 19), + VISCONTI_PIN(PINCTRL_PIN(22, "gpio22"), REG_IO_DSEL7, 16, + REG_IO_PUDE2, REG_IO_PUDSEL2, 20), + VISCONTI_PIN(PINCTRL_PIN(23, "gpio23"), REG_IO_DSEL7, 20, + REG_IO_PUDE2, REG_IO_PUDSEL2, 21), + VISCONTI_PIN(PINCTRL_PIN(24, "gpio24"), REG_IO_DSEL7, 24, + REG_IO_PUDE2, REG_IO_PUDSEL2, 22), + VISCONTI_PIN(PINCTRL_PIN(25, "gpio25"), REG_IO_DSEL7, 28, + REG_IO_PUDE2, REG_IO_PUDSEL2, 23), + VISCONTI_PIN(PINCTRL_PIN(26, "gpio26"), REG_IO_DSEL8, 0, + REG_IO_PUDE2, REG_IO_PUDSEL2, 24), + VISCONTI_PIN(PINCTRL_PIN(27, "gpio27"), REG_IO_DSEL8, 4, + REG_IO_PUDE2, REG_IO_PUDSEL2, 25), + VISCONTI_PIN(PINCTRL_PIN(28, "gpio28"), REG_IO_DSEL8, 8, + REG_IO_PUDE2, REG_IO_PUDSEL2, 26), + VISCONTI_PIN(PINCTRL_PIN(29, "gpio29"), REG_IO_DSEL4, 8, + REG_IO_PUDE1, REG_IO_PUDSEL1, 26), + VISCONTI_PIN(PINCTRL_PIN(30, "gpio30"), REG_IO_DSEL4, 4, + REG_IO_PUDE1, REG_IO_PUDSEL1, 25), + VISCONTI_PIN(PINCTRL_PIN(31, "gpio31"), REG_IO_DSEL4, 0, + REG_IO_PUDE1, REG_IO_PUDSEL1, 24), + VISCONTI_PIN(PINCTRL_PIN(32, "spi_sck"), REG_IO_DSEL4, 12, + REG_IO_PUDE1, REG_IO_PUDSEL1, 27), + VISCONTI_PIN(PINCTRL_PIN(33, "spi_sdo"), REG_IO_DSEL4, 16, + REG_IO_PUDE1, REG_IO_PUDSEL1, 28), + VISCONTI_PIN(PINCTRL_PIN(34, "spi_sdi"), REG_IO_DSEL4, 20, + REG_IO_PUDE1, REG_IO_PUDSEL1, 29), +}; + +/* Group */ +VISCONTI_PINS(i2c0, 0, 1); +VISCONTI_PINS(i2c1, 2, 3); +VISCONTI_PINS(i2c2, 12, 13); +VISCONTI_PINS(i2c3, 14, 15); +VISCONTI_PINS(i2c4, 16, 17); +VISCONTI_PINS(i2c5, 18, 19); +VISCONTI_PINS(i2c6, 33, 34); +VISCONTI_PINS(i2c7, 29, 32); +VISCONTI_PINS(i2c8, 30, 31); +VISCONTI_PINS(spi0_cs0, 29); +VISCONTI_PINS(spi0_cs1, 30); +VISCONTI_PINS(spi0_cs2, 31); +VISCONTI_PINS(spi1_cs, 3); +VISCONTI_PINS(spi2_cs, 7); +VISCONTI_PINS(spi3_cs, 11); +VISCONTI_PINS(spi4_cs, 15); +VISCONTI_PINS(spi5_cs, 19); +VISCONTI_PINS(spi6_cs, 27); +VISCONTI_PINS(spi0, 32, 33, 34); +VISCONTI_PINS(spi1, 0, 1, 2); +VISCONTI_PINS(spi2, 4, 5, 6); +VISCONTI_PINS(spi3, 8, 9, 10); +VISCONTI_PINS(spi4, 12, 13, 14); +VISCONTI_PINS(spi5, 16, 17, 18); +VISCONTI_PINS(spi6, 24, 25, 26); +VISCONTI_PINS(uart0, 4, 5, 6, 7); +VISCONTI_PINS(uart1, 8, 9, 10, 11); +VISCONTI_PINS(uart2, 12, 13, 14, 15); +VISCONTI_PINS(uart3, 16, 17, 18, 19); +VISCONTI_PINS(pwm0_gpio4, 4); +VISCONTI_PINS(pwm1_gpio5, 5); +VISCONTI_PINS(pwm2_gpio6, 6); +VISCONTI_PINS(pwm3_gpio7, 7); +VISCONTI_PINS(pwm0_gpio8, 8); +VISCONTI_PINS(pwm1_gpio9, 9); +VISCONTI_PINS(pwm2_gpio10, 10); +VISCONTI_PINS(pwm3_gpio11, 11); +VISCONTI_PINS(pwm0_gpio12, 12); +VISCONTI_PINS(pwm1_gpio13, 13); +VISCONTI_PINS(pwm2_gpio14, 14); +VISCONTI_PINS(pwm3_gpio15, 15); +VISCONTI_PINS(pwm0_gpio16, 16); +VISCONTI_PINS(pwm1_gpio17, 17); +VISCONTI_PINS(pwm2_gpio18, 18); +VISCONTI_PINS(pwm3_gpio19, 19); +VISCONTI_PINS(pcmif_out, 20, 21, 22); +VISCONTI_PINS(pcmif_in, 24, 25, 26); + +static const struct visconti_pin_group groups_tmpv7700[] = { + VISCONTI_PIN_GROUP(i2c0, REG_PINMUX2, GENMASK(7, 0), 0x00000022), + VISCONTI_PIN_GROUP(i2c1, REG_PINMUX2, GENMASK(15, 8), 0x00002200), + VISCONTI_PIN_GROUP(i2c2, REG_PINMUX3, GENMASK(23, 16), 0x00770000), + VISCONTI_PIN_GROUP(i2c3, REG_PINMUX3, GENMASK(31, 24), 0x77000000), + VISCONTI_PIN_GROUP(i2c4, REG_PINMUX4, GENMASK(7, 0), 0x00000077), + VISCONTI_PIN_GROUP(i2c5, REG_PINMUX4, GENMASK(15, 8), 0x00007700), + VISCONTI_PIN_GROUP(i2c6, REG_PINMUX1, GENMASK(3, 0), 0x0000002), + VISCONTI_PIN_GROUP(i2c7, REG_PINMUX5, GENMASK(23, 20), 0x00200000), + VISCONTI_PIN_GROUP(i2c8, REG_PINMUX5, GENMASK(31, 24), 0x22000000), + VISCONTI_PIN_GROUP(spi0_cs0, REG_PINMUX5, GENMASK(23, 20), 0x00100000), + VISCONTI_PIN_GROUP(spi0_cs1, REG_PINMUX5, GENMASK(27, 24), 0x01000000), + VISCONTI_PIN_GROUP(spi0_cs2, REG_PINMUX5, GENMASK(31, 28), 0x10000000), + VISCONTI_PIN_GROUP(spi1_cs, REG_PINMUX2, GENMASK(15, 12), 0x00001000), + VISCONTI_PIN_GROUP(spi2_cs, REG_PINMUX2, GENMASK(31, 28), 0x10000000), + VISCONTI_PIN_GROUP(spi3_cs, REG_PINMUX3, GENMASK(15, 12), 0x00001000), + VISCONTI_PIN_GROUP(spi4_cs, REG_PINMUX4, GENMASK(31, 28), 0x10000000), + VISCONTI_PIN_GROUP(spi5_cs, REG_PINMUX4, GENMASK(15, 12), 0x00001000), + VISCONTI_PIN_GROUP(spi6_cs, REG_PINMUX5, GENMASK(15, 12), 0x00001000), + VISCONTI_PIN_GROUP(spi0, REG_PINMUX1, GENMASK(3, 0), 0x00000001), + VISCONTI_PIN_GROUP(spi1, REG_PINMUX2, GENMASK(11, 0), 0x00000111), + VISCONTI_PIN_GROUP(spi2, REG_PINMUX2, GENMASK(27, 16), 0x01110000), + VISCONTI_PIN_GROUP(spi3, REG_PINMUX3, GENMASK(11, 0), 0x00000111), + VISCONTI_PIN_GROUP(spi4, REG_PINMUX3, GENMASK(27, 16), 0x01110000), + VISCONTI_PIN_GROUP(spi5, REG_PINMUX4, GENMASK(11, 0), 0x00000111), + VISCONTI_PIN_GROUP(spi6, REG_PINMUX5, GENMASK(11, 0), 0x00000111), + VISCONTI_PIN_GROUP(uart0, REG_PINMUX2, GENMASK(31, 16), 0x22220000), + VISCONTI_PIN_GROUP(uart1, REG_PINMUX3, GENMASK(15, 0), 0x00002222), + VISCONTI_PIN_GROUP(uart2, REG_PINMUX3, GENMASK(31, 16), 0x22220000), + VISCONTI_PIN_GROUP(uart3, REG_PINMUX4, GENMASK(15, 0), 0x00002222), + VISCONTI_PIN_GROUP(pwm0_gpio4, REG_PINMUX2, GENMASK(19, 16), 0x00050000), + VISCONTI_PIN_GROUP(pwm1_gpio5, REG_PINMUX2, GENMASK(23, 20), 0x00500000), + VISCONTI_PIN_GROUP(pwm2_gpio6, REG_PINMUX2, GENMASK(27, 24), 0x05000000), + VISCONTI_PIN_GROUP(pwm3_gpio7, REG_PINMUX2, GENMASK(31, 28), 0x50000000), + VISCONTI_PIN_GROUP(pwm0_gpio8, REG_PINMUX3, GENMASK(3, 0), 0x00000005), + VISCONTI_PIN_GROUP(pwm1_gpio9, REG_PINMUX3, GENMASK(7, 4), 0x00000050), + VISCONTI_PIN_GROUP(pwm2_gpio10, REG_PINMUX3, GENMASK(11, 8), 0x00000500), + VISCONTI_PIN_GROUP(pwm3_gpio11, REG_PINMUX3, GENMASK(15, 12), 0x00005000), + VISCONTI_PIN_GROUP(pwm0_gpio12, REG_PINMUX3, GENMASK(19, 16), 0x00050000), + VISCONTI_PIN_GROUP(pwm1_gpio13, REG_PINMUX3, GENMASK(23, 20), 0x00500000), + VISCONTI_PIN_GROUP(pwm2_gpio14, REG_PINMUX3, GENMASK(27, 24), 0x05000000), + VISCONTI_PIN_GROUP(pwm3_gpio15, REG_PINMUX3, GENMASK(31, 28), 0x50000000), + VISCONTI_PIN_GROUP(pwm0_gpio16, REG_PINMUX4, GENMASK(3, 0), 0x00000005), + VISCONTI_PIN_GROUP(pwm1_gpio17, REG_PINMUX4, GENMASK(7, 4), 0x00000050), + VISCONTI_PIN_GROUP(pwm2_gpio18, REG_PINMUX4, GENMASK(11, 8), 0x00000500), + VISCONTI_PIN_GROUP(pwm3_gpio19, REG_PINMUX4, GENMASK(15, 12), 0x00005000), + VISCONTI_PIN_GROUP(pcmif_out, REG_PINMUX4, GENMASK(27, 16), 0x01110000), + VISCONTI_PIN_GROUP(pcmif_in, REG_PINMUX5, GENMASK(11, 0), 0x00000222), +}; + +/* MUX */ +VISCONTI_GROUPS(i2c0, "i2c0_grp"); +VISCONTI_GROUPS(i2c1, "i2c1_grp"); +VISCONTI_GROUPS(i2c2, "i2c2_grp"); +VISCONTI_GROUPS(i2c3, "i2c3_grp"); +VISCONTI_GROUPS(i2c4, "i2c4_grp"); +VISCONTI_GROUPS(i2c5, "i2c5_grp"); +VISCONTI_GROUPS(i2c6, "i2c6_grp"); +VISCONTI_GROUPS(i2c7, "i2c7_grp"); +VISCONTI_GROUPS(i2c8, "i2c8_grp"); +VISCONTI_GROUPS(spi0, "spi0_grp", "spi0_cs0_grp", + "spi0_cs1_grp", "spi0_cs2_grp"); +VISCONTI_GROUPS(spi1, "spi1_grp", "spi1_cs_grp"); +VISCONTI_GROUPS(spi2, "spi2_grp", "spi2_cs_grp"); +VISCONTI_GROUPS(spi3, "spi3_grp", "spi3_cs_grp"); +VISCONTI_GROUPS(spi4, "spi4_grp", "spi4_cs_grp"); +VISCONTI_GROUPS(spi5, "spi5_grp", "spi5_cs_grp"); +VISCONTI_GROUPS(spi6, "spi6_grp", "spi6_cs_grp"); +VISCONTI_GROUPS(uart0, "uart0_grp"); +VISCONTI_GROUPS(uart1, "uart1_grp"); +VISCONTI_GROUPS(uart2, "uart2_grp"); +VISCONTI_GROUPS(uart3, "uart3_grp"); +VISCONTI_GROUPS(pwm, "pwm0_gpio4_grp", "pwm0_gpio8_grp", + "pwm0_gpio12_grp", "pwm0_gpio16_grp", + "pwm1_gpio5_grp", "pwm1_gpio9_grp", + "pwm1_gpio13_grp", "pwm1_gpio17_grp", + "pwm2_gpio6_grp", "pwm2_gpio10_grp", + "pwm2_gpio14_grp", "pwm2_gpio18_grp", + "pwm3_gpio7_grp", "pwm3_gpio11_grp", + "pwm3_gpio15_grp", "pwm3_gpio19_grp"); +VISCONTI_GROUPS(pcmif_out, "pcmif_out_grp"); +VISCONTI_GROUPS(pcmif_in, "pcmif_in_grp"); + +static const struct visconti_pin_function functions_tmpv7700[] = { + VISCONTI_PIN_FUNCTION(i2c0), + VISCONTI_PIN_FUNCTION(i2c1), + VISCONTI_PIN_FUNCTION(i2c2), + VISCONTI_PIN_FUNCTION(i2c3), + VISCONTI_PIN_FUNCTION(i2c4), + VISCONTI_PIN_FUNCTION(i2c5), + VISCONTI_PIN_FUNCTION(i2c6), + VISCONTI_PIN_FUNCTION(i2c7), + VISCONTI_PIN_FUNCTION(i2c8), + VISCONTI_PIN_FUNCTION(spi0), + VISCONTI_PIN_FUNCTION(spi1), + VISCONTI_PIN_FUNCTION(spi2), + VISCONTI_PIN_FUNCTION(spi3), + VISCONTI_PIN_FUNCTION(spi4), + VISCONTI_PIN_FUNCTION(spi5), + VISCONTI_PIN_FUNCTION(spi6), + VISCONTI_PIN_FUNCTION(uart0), + VISCONTI_PIN_FUNCTION(uart1), + VISCONTI_PIN_FUNCTION(uart2), + VISCONTI_PIN_FUNCTION(uart3), + VISCONTI_PIN_FUNCTION(pwm), + VISCONTI_PIN_FUNCTION(pcmif_in), + VISCONTI_PIN_FUNCTION(pcmif_out), +}; + +/* GPIO MUX */ +#define tmpv7700_GPIO_MUX(off, msk) \ +{ \ + .offset = off, \ + .mask = msk, \ + .val = 0, \ +} + +static const struct visconti_mux gpio_mux_tmpv7700[] = { + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(3, 0)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(7, 4)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(11, 8)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(15, 12)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(19, 16)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(23, 20)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(27, 24)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(31, 28)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(3, 0)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(7, 4)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(11, 8)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(15, 12)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(19, 16)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(23, 20)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(27, 24)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(31, 28)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(3, 0)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(7, 4)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(11, 8)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(15, 12)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(19, 16)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(23, 20)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(27, 24)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(31, 28)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(3, 0)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(7, 4)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(11, 8)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(15, 12)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(19, 16)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(23, 20)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(27, 24)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(31, 28)), +}; + +static void tmpv7700_pinctrl_unlock(void __iomem *base) +{ + writel(1, base + REG_KEY_CTRL); + writel(tmpv7700_MAGIC_NUM, base + REG_KEY_CMD); +} + +/* chip dependent data */ +static const struct visconti_pinctrl_devdata tmpv7700_pinctrl_data = { + .pins = pins_tmpv7700, + .nr_pins = ARRAY_SIZE(pins_tmpv7700), + .groups = groups_tmpv7700, + .nr_groups = ARRAY_SIZE(groups_tmpv7700), + .functions = functions_tmpv7700, + .nr_functions = ARRAY_SIZE(functions_tmpv7700), + .gpio_mux = gpio_mux_tmpv7700, + .unlock = tmpv7700_pinctrl_unlock, +}; + +static int tmpv7700_pinctrl_probe(struct platform_device *pdev) +{ + return visconti_pinctrl_probe(pdev, &tmpv7700_pinctrl_data); +} + +static const struct of_device_id tmpv7700_pctrl_of_match[] = { + { .compatible = "toshiba,tmpv7708-pinctrl", }, + {}, +}; + +static struct platform_driver tmpv7700_pinctrl_driver = { + .probe = tmpv7700_pinctrl_probe, + .driver = { + .name = "tmpv7700-pinctrl", + .of_match_table = tmpv7700_pctrl_of_match, + }, +}; + +static int __init tmpv7700_pinctrl_init(void) +{ + return platform_driver_register(&tmpv7700_pinctrl_driver); +} +arch_initcall(tmpv7700_pinctrl_init); |