diff options
Diffstat (limited to 'drivers/ssb')
| -rw-r--r-- | drivers/ssb/Kconfig | 1 | ||||
| -rw-r--r-- | drivers/ssb/driver_chipcommon_pmu.c | 2 | ||||
| -rw-r--r-- | drivers/ssb/driver_mipscore.c | 2 | ||||
| -rw-r--r-- | drivers/ssb/driver_pcicore.c | 9 | ||||
| -rw-r--r-- | drivers/ssb/main.c | 2 |
5 files changed, 14 insertions, 2 deletions
diff --git a/drivers/ssb/Kconfig b/drivers/ssb/Kconfig index 75b3603906c1..f0d22cdb51cd 100644 --- a/drivers/ssb/Kconfig +++ b/drivers/ssb/Kconfig @@ -130,6 +130,7 @@ config SSB_DRIVER_MIPS bool "SSB Broadcom MIPS core driver" depends on SSB && MIPS select SSB_SERIAL + select SSB_SFLASH help Driver for the Sonics Silicon Backplane attached Broadcom MIPS core. diff --git a/drivers/ssb/driver_chipcommon_pmu.c b/drivers/ssb/driver_chipcommon_pmu.c index 1173a091b402..09428412139e 100644 --- a/drivers/ssb/driver_chipcommon_pmu.c +++ b/drivers/ssb/driver_chipcommon_pmu.c @@ -14,7 +14,7 @@ #include <linux/delay.h> #include <linux/export.h> #ifdef CONFIG_BCM47XX -#include <bcm47xx_nvram.h> +#include <linux/bcm47xx_nvram.h> #endif #include "ssb_private.h" diff --git a/drivers/ssb/driver_mipscore.c b/drivers/ssb/driver_mipscore.c index 7b986f9f213f..f87efef42252 100644 --- a/drivers/ssb/driver_mipscore.c +++ b/drivers/ssb/driver_mipscore.c @@ -16,7 +16,7 @@ #include <linux/serial_reg.h> #include <linux/time.h> #ifdef CONFIG_BCM47XX -#include <bcm47xx_nvram.h> +#include <linux/bcm47xx_nvram.h> #endif #include "ssb_private.h" diff --git a/drivers/ssb/driver_pcicore.c b/drivers/ssb/driver_pcicore.c index d75b72ba2672..15a7ee3859dd 100644 --- a/drivers/ssb/driver_pcicore.c +++ b/drivers/ssb/driver_pcicore.c @@ -357,6 +357,15 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA); + /* + * Accessing PCI config without a proper delay after devices reset (not + * GPIO reset) was causing reboots on WRT300N v1.0. + * Tested delay 850 us lowered reboot chance to 50-80%, 1000 us fixed it + * completely. Flushing all writes was also tested but with no luck. + */ + if (pc->dev->bus->chip_id == 0x4704) + usleep_range(1000, 2000); + /* Enable PCI bridge BAR0 prefetch and burst */ val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2); diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c index 1e180c400f17..a48a7439a206 100644 --- a/drivers/ssb/main.c +++ b/drivers/ssb/main.c @@ -1135,6 +1135,8 @@ static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev) case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */ case SSB_IDLOW_SSBREV_27: /* same here */ return SSB_TMSLOW_REJECT; /* this is a guess */ + case SSB_IDLOW_SSBREV: + break; default: WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev); } |