diff options
Diffstat (limited to 'drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw')
24 files changed, 26842 insertions, 0 deletions
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_ares_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_ares_reg.h new file mode 100644 index 000000000000..5970fa94d4d2 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_ares_reg.h @@ -0,0 +1,3291 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + +/* Copyright (C) 2009 Denali Software Inc. All rights reserved */ +/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */ + + +#ifndef _ANALOG_INTF_ARES_REG_REG_H_ +#define _ANALOG_INTF_ARES_REG_REG_H_ + + +/* macros for RXRF_BIAS1 */ +#define PHY_ANALOG_RXRF_BIAS1_ADDRESS 0x00000000 +#define PHY_ANALOG_RXRF_BIAS1_OFFSET 0x00000000 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_MSB 0 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_MASK 0x00000001 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_BIAS1_SPARE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MSB 3 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_LSB 1 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MASK 0x0000000e +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MSB 6 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_LSB 4 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MASK 0x00000070 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_GET(x) (((x) & 0x00000070) >> 4) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_SET(x) (((x) << 4) & 0x00000070) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MSB 9 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_LSB 7 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MASK 0x00000380 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MSB 12 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_LSB 10 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MASK 0x00001c00 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_GET(x) (((x) & 0x00001c00) >> 10) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_SET(x) (((x) << 10) & 0x00001c00) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MSB 15 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_LSB 13 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MASK 0x0000e000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MSB 18 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_LSB 16 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MASK 0x00070000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_SET(x) (((x) << 16) & 0x00070000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MSB 21 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_LSB 19 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MASK 0x00380000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MSB 24 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_LSB 22 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MASK 0x01c00000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_GET(x) (((x) & 0x01c00000) >> 22) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_SET(x) (((x) << 22) & 0x01c00000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MSB 27 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_LSB 25 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MASK 0x0e000000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_GET(x) (((x) & 0x0e000000) >> 25) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_SET(x) (((x) << 25) & 0x0e000000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MSB 30 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_LSB 28 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MASK 0x70000000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_GET(x) (((x) & 0x70000000) >> 28) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_SET(x) (((x) << 28) & 0x70000000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MSB 31 +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_LSB 31 +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MASK 0x80000000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000) + +/* macros for RXRF_BIAS2 */ +#define PHY_ANALOG_RXRF_BIAS2_ADDRESS 0x00000004 +#define PHY_ANALOG_RXRF_BIAS2_OFFSET 0x00000004 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_MSB 0 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_MASK 0x00000001 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_BIAS2_SPARE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_BIAS2_PKEN_MSB 3 +#define PHY_ANALOG_RXRF_BIAS2_PKEN_LSB 1 +#define PHY_ANALOG_RXRF_BIAS2_PKEN_MASK 0x0000000e +#define PHY_ANALOG_RXRF_BIAS2_PKEN_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_RXRF_BIAS2_PKEN_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MSB 6 +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_LSB 4 +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MASK 0x00000070 +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_GET(x) (((x) & 0x00000070) >> 4) +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_SET(x) (((x) << 4) & 0x00000070) +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MSB 7 +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_LSB 7 +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MASK 0x00000080 +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_MSB 10 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_LSB 8 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_MASK 0x00000700 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_MSB 13 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_LSB 11 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_MASK 0x00003800 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_MSB 16 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_LSB 14 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_MASK 0x0001c000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_MSB 19 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_LSB 17 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_MASK 0x000e0000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_MSB 22 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_LSB 20 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_MASK 0x00700000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_MSB 25 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_LSB 23 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_MASK 0x03800000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MSB 28 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_LSB 26 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MASK 0x1c000000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MSB 31 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_LSB 29 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MASK 0xe0000000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for RXRF_GAINSTAGES */ +#define PHY_ANALOG_RXRF_GAINSTAGES_ADDRESS 0x00000008 +#define PHY_ANALOG_RXRF_GAINSTAGES_OFFSET 0x00000008 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MSB 0 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MASK 0x00000001 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MSB 1 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_LSB 1 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MASK 0x00000002 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MSB 3 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_LSB 2 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MASK 0x0000000c +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MSB 5 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_LSB 4 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MASK 0x00000030 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_SET(x) (((x) << 4) & 0x00000030) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MSB 6 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_LSB 6 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MASK 0x00000040 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MSB 7 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_LSB 7 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MASK 0x00000080 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MSB 8 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_LSB 8 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MASK 0x00000100 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MSB 9 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_LSB 9 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MASK 0x00000200 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MSB 10 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_LSB 10 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MASK 0x00000400 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MSB 12 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_LSB 11 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MASK 0x00001800 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_GET(x) (((x) & 0x00001800) >> 11) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_SET(x) (((x) << 11) & 0x00001800) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MSB 13 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_LSB 13 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MASK 0x00002000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MSB 14 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_LSB 14 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MASK 0x00004000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MSB 15 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_LSB 15 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MASK 0x00008000 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MSB 16 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_LSB 16 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MASK 0x00010000 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MSB 17 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_LSB 17 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MASK 0x00020000 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MSB 19 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_LSB 18 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MASK 0x000c0000 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MSB 22 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_LSB 20 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MASK 0x00700000 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MSB 25 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_LSB 23 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MASK 0x03800000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MSB 27 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_LSB 26 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MASK 0x0c000000 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_GET(x) (((x) & 0x0c000000) >> 26) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_SET(x) (((x) << 26) & 0x0c000000) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MSB 30 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_LSB 28 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MASK 0x70000000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_GET(x) (((x) & 0x70000000) >> 28) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_SET(x) (((x) << 28) & 0x70000000) +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MSB 31 +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_LSB 31 +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MASK 0x80000000 +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for RXRF_AGC */ +#define PHY_ANALOG_RXRF_AGC_ADDRESS 0x0000000c +#define PHY_ANALOG_RXRF_AGC_OFFSET 0x0000000c +#define PHY_ANALOG_RXRF_AGC_SPARE_MSB 5 +#define PHY_ANALOG_RXRF_AGC_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_AGC_SPARE_MASK 0x0000003f +#define PHY_ANALOG_RXRF_AGC_SPARE_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_ANALOG_RXRF_AGC_SPARE_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MSB 8 +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_LSB 6 +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MASK 0x000001c0 +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_GET(x) (((x) & 0x000001c0) >> 6) +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_SET(x) (((x) << 6) & 0x000001c0) +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MSB 14 +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_LSB 9 +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MASK 0x00007e00 +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_GET(x) (((x) & 0x00007e00) >> 9) +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_SET(x) (((x) << 9) & 0x00007e00) +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MSB 18 +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_LSB 15 +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MASK 0x00078000 +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_GET(x) (((x) & 0x00078000) >> 15) +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_SET(x) (((x) << 15) & 0x00078000) +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MSB 24 +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_LSB 19 +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MASK 0x01f80000 +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_GET(x) (((x) & 0x01f80000) >> 19) +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_SET(x) (((x) << 19) & 0x01f80000) +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MSB 28 +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_LSB 25 +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MASK 0x1e000000 +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_GET(x) (((x) & 0x1e000000) >> 25) +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_SET(x) (((x) << 25) & 0x1e000000) +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MSB 29 +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_LSB 29 +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MASK 0x20000000 +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MSB 30 +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_LSB 30 +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MASK 0x40000000 +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MSB 31 +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_LSB 31 +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MASK 0x80000000 +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF1 */ +#define PHY_ANALOG_TXRF1_ADDRESS 0x00000040 +#define PHY_ANALOG_TXRF1_OFFSET 0x00000040 +#define PHY_ANALOG_TXRF1_DCAS2G_MSB 2 +#define PHY_ANALOG_TXRF1_DCAS2G_LSB 0 +#define PHY_ANALOG_TXRF1_DCAS2G_MASK 0x00000007 +#define PHY_ANALOG_TXRF1_DCAS2G_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_TXRF1_DCAS2G_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_TXRF1_OB2G_PALOFF_MSB 5 +#define PHY_ANALOG_TXRF1_OB2G_PALOFF_LSB 3 +#define PHY_ANALOG_TXRF1_OB2G_PALOFF_MASK 0x00000038 +#define PHY_ANALOG_TXRF1_OB2G_PALOFF_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_ANALOG_TXRF1_OB2G_PALOFF_SET(x) (((x) << 3) & 0x00000038) +#define PHY_ANALOG_TXRF1_OB2G_QAM_MSB 8 +#define PHY_ANALOG_TXRF1_OB2G_QAM_LSB 6 +#define PHY_ANALOG_TXRF1_OB2G_QAM_MASK 0x000001c0 +#define PHY_ANALOG_TXRF1_OB2G_QAM_GET(x) (((x) & 0x000001c0) >> 6) +#define PHY_ANALOG_TXRF1_OB2G_QAM_SET(x) (((x) << 6) & 0x000001c0) +#define PHY_ANALOG_TXRF1_OB2G_PSK_MSB 11 +#define PHY_ANALOG_TXRF1_OB2G_PSK_LSB 9 +#define PHY_ANALOG_TXRF1_OB2G_PSK_MASK 0x00000e00 +#define PHY_ANALOG_TXRF1_OB2G_PSK_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_ANALOG_TXRF1_OB2G_PSK_SET(x) (((x) << 9) & 0x00000e00) +#define PHY_ANALOG_TXRF1_OB2G_CCK_MSB 14 +#define PHY_ANALOG_TXRF1_OB2G_CCK_LSB 12 +#define PHY_ANALOG_TXRF1_OB2G_CCK_MASK 0x00007000 +#define PHY_ANALOG_TXRF1_OB2G_CCK_GET(x) (((x) & 0x00007000) >> 12) +#define PHY_ANALOG_TXRF1_OB2G_CCK_SET(x) (((x) << 12) & 0x00007000) +#define PHY_ANALOG_TXRF1_DB2G_MSB 17 +#define PHY_ANALOG_TXRF1_DB2G_LSB 15 +#define PHY_ANALOG_TXRF1_DB2G_MASK 0x00038000 +#define PHY_ANALOG_TXRF1_DB2G_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_TXRF1_DB2G_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_TXRF1_PDOUT2G_MSB 18 +#define PHY_ANALOG_TXRF1_PDOUT2G_LSB 18 +#define PHY_ANALOG_TXRF1_PDOUT2G_MASK 0x00040000 +#define PHY_ANALOG_TXRF1_PDOUT2G_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_TXRF1_PDOUT2G_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_TXRF1_PDDR2G_MSB 19 +#define PHY_ANALOG_TXRF1_PDDR2G_LSB 19 +#define PHY_ANALOG_TXRF1_PDDR2G_MASK 0x00080000 +#define PHY_ANALOG_TXRF1_PDDR2G_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_TXRF1_PDDR2G_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_TXRF1_PDMXR2G_MSB 20 +#define PHY_ANALOG_TXRF1_PDMXR2G_LSB 20 +#define PHY_ANALOG_TXRF1_PDMXR2G_MASK 0x00100000 +#define PHY_ANALOG_TXRF1_PDMXR2G_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TXRF1_PDMXR2G_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TXRF1_PDLO2G_MSB 21 +#define PHY_ANALOG_TXRF1_PDLO2G_LSB 21 +#define PHY_ANALOG_TXRF1_PDLO2G_MASK 0x00200000 +#define PHY_ANALOG_TXRF1_PDLO2G_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_TXRF1_PDLO2G_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MSB 22 +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_LSB 22 +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MASK 0x00400000 +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MSB 23 +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_LSB 23 +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MASK 0x00800000 +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_TXRF1_PADRVGN2G_MSB 30 +#define PHY_ANALOG_TXRF1_PADRVGN2G_LSB 24 +#define PHY_ANALOG_TXRF1_PADRVGN2G_MASK 0x7f000000 +#define PHY_ANALOG_TXRF1_PADRVGN2G_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TXRF1_PADRVGN2G_SET(x) (((x) << 24) & 0x7f000000) +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MSB 31 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_LSB 31 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MASK 0x80000000 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF2 */ +#define PHY_ANALOG_TXRF2_ADDRESS 0x00000044 +#define PHY_ANALOG_TXRF2_OFFSET 0x00000044 +#define PHY_ANALOG_TXRF2_SPARE2_MSB 0 +#define PHY_ANALOG_TXRF2_SPARE2_LSB 0 +#define PHY_ANALOG_TXRF2_SPARE2_MASK 0x00000001 +#define PHY_ANALOG_TXRF2_SPARE2_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TXRF2_SPARE2_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TXRF2_D3B5G_MSB 3 +#define PHY_ANALOG_TXRF2_D3B5G_LSB 1 +#define PHY_ANALOG_TXRF2_D3B5G_MASK 0x0000000e +#define PHY_ANALOG_TXRF2_D3B5G_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_TXRF2_D3B5G_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_TXRF2_D4B5G_MSB 6 +#define PHY_ANALOG_TXRF2_D4B5G_LSB 4 +#define PHY_ANALOG_TXRF2_D4B5G_MASK 0x00000070 +#define PHY_ANALOG_TXRF2_D4B5G_GET(x) (((x) & 0x00000070) >> 4) +#define PHY_ANALOG_TXRF2_D4B5G_SET(x) (((x) << 4) & 0x00000070) +#define PHY_ANALOG_TXRF2_PDOUT5G_MSB 10 +#define PHY_ANALOG_TXRF2_PDOUT5G_LSB 7 +#define PHY_ANALOG_TXRF2_PDOUT5G_MASK 0x00000780 +#define PHY_ANALOG_TXRF2_PDOUT5G_GET(x) (((x) & 0x00000780) >> 7) +#define PHY_ANALOG_TXRF2_PDOUT5G_SET(x) (((x) << 7) & 0x00000780) +#define PHY_ANALOG_TXRF2_PDMXR5G_MSB 11 +#define PHY_ANALOG_TXRF2_PDMXR5G_LSB 11 +#define PHY_ANALOG_TXRF2_PDMXR5G_MASK 0x00000800 +#define PHY_ANALOG_TXRF2_PDMXR5G_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_TXRF2_PDMXR5G_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_TXRF2_PDLOBUF5G_MSB 12 +#define PHY_ANALOG_TXRF2_PDLOBUF5G_LSB 12 +#define PHY_ANALOG_TXRF2_PDLOBUF5G_MASK 0x00001000 +#define PHY_ANALOG_TXRF2_PDLOBUF5G_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_TXRF2_PDLOBUF5G_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_TXRF2_PDLODIV5G_MSB 13 +#define PHY_ANALOG_TXRF2_PDLODIV5G_LSB 13 +#define PHY_ANALOG_TXRF2_PDLODIV5G_MASK 0x00002000 +#define PHY_ANALOG_TXRF2_PDLODIV5G_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_TXRF2_PDLODIV5G_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_MSB 14 +#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_LSB 14 +#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_MASK 0x00004000 +#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_TXRF2_LODIV5GFORCED_MSB 15 +#define PHY_ANALOG_TXRF2_LODIV5GFORCED_LSB 15 +#define PHY_ANALOG_TXRF2_LODIV5GFORCED_MASK 0x00008000 +#define PHY_ANALOG_TXRF2_LODIV5GFORCED_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_TXRF2_LODIV5GFORCED_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_TXRF2_PADRV2GN5G_MSB 19 +#define PHY_ANALOG_TXRF2_PADRV2GN5G_LSB 16 +#define PHY_ANALOG_TXRF2_PADRV2GN5G_MASK 0x000f0000 +#define PHY_ANALOG_TXRF2_PADRV2GN5G_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_TXRF2_PADRV2GN5G_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_ANALOG_TXRF2_PADRV3GN5G_MSB 23 +#define PHY_ANALOG_TXRF2_PADRV3GN5G_LSB 20 +#define PHY_ANALOG_TXRF2_PADRV3GN5G_MASK 0x00f00000 +#define PHY_ANALOG_TXRF2_PADRV3GN5G_GET(x) (((x) & 0x00f00000) >> 20) +#define PHY_ANALOG_TXRF2_PADRV3GN5G_SET(x) (((x) << 20) & 0x00f00000) +#define PHY_ANALOG_TXRF2_PADRV4GN5G_MSB 27 +#define PHY_ANALOG_TXRF2_PADRV4GN5G_LSB 24 +#define PHY_ANALOG_TXRF2_PADRV4GN5G_MASK 0x0f000000 +#define PHY_ANALOG_TXRF2_PADRV4GN5G_GET(x) (((x) & 0x0f000000) >> 24) +#define PHY_ANALOG_TXRF2_PADRV4GN5G_SET(x) (((x) << 24) & 0x0f000000) +#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_MSB 28 +#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_LSB 28 +#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_MASK 0x10000000 +#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_TXRF2_OCAS2G_MSB 31 +#define PHY_ANALOG_TXRF2_OCAS2G_LSB 29 +#define PHY_ANALOG_TXRF2_OCAS2G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF2_OCAS2G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF2_OCAS2G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF3 */ +#define PHY_ANALOG_TXRF3_ADDRESS 0x00000048 +#define PHY_ANALOG_TXRF3_OFFSET 0x00000048 +#define PHY_ANALOG_TXRF3_SPARE3_MSB 22 +#define PHY_ANALOG_TXRF3_SPARE3_LSB 0 +#define PHY_ANALOG_TXRF3_SPARE3_MASK 0x007fffff +#define PHY_ANALOG_TXRF3_SPARE3_GET(x) (((x) & 0x007fffff) >> 0) +#define PHY_ANALOG_TXRF3_SPARE3_SET(x) (((x) << 0) & 0x007fffff) +#define PHY_ANALOG_TXRF3_CAS5G_MSB 25 +#define PHY_ANALOG_TXRF3_CAS5G_LSB 23 +#define PHY_ANALOG_TXRF3_CAS5G_MASK 0x03800000 +#define PHY_ANALOG_TXRF3_CAS5G_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF3_CAS5G_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF3_OB5G_MSB 28 +#define PHY_ANALOG_TXRF3_OB5G_LSB 26 +#define PHY_ANALOG_TXRF3_OB5G_MASK 0x1c000000 +#define PHY_ANALOG_TXRF3_OB5G_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF3_OB5G_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF3_D2B5G_MSB 31 +#define PHY_ANALOG_TXRF3_D2B5G_LSB 29 +#define PHY_ANALOG_TXRF3_D2B5G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF3_D2B5G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF3_D2B5G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF4 */ +#define PHY_ANALOG_TXRF4_ADDRESS 0x0000004c +#define PHY_ANALOG_TXRF4_OFFSET 0x0000004c +#define PHY_ANALOG_TXRF4_COMP2G_PSK_MSB 2 +#define PHY_ANALOG_TXRF4_COMP2G_PSK_LSB 0 +#define PHY_ANALOG_TXRF4_COMP2G_PSK_MASK 0x00000007 +#define PHY_ANALOG_TXRF4_COMP2G_PSK_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_TXRF4_COMP2G_PSK_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_TXRF4_COMP2G_CCK_MSB 5 +#define PHY_ANALOG_TXRF4_COMP2G_CCK_LSB 3 +#define PHY_ANALOG_TXRF4_COMP2G_CCK_MASK 0x00000038 +#define PHY_ANALOG_TXRF4_COMP2G_CCK_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_ANALOG_TXRF4_COMP2G_CCK_SET(x) (((x) << 3) & 0x00000038) +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MSB 8 +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_LSB 6 +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MASK 0x000001c0 +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_GET(x) (((x) & 0x000001c0) >> 6) +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_SET(x) (((x) << 6) & 0x000001c0) +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MSB 11 +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_LSB 9 +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MASK 0x00000e00 +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_SET(x) (((x) << 9) & 0x00000e00) +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MSB 14 +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_LSB 12 +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MASK 0x00007000 +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_GET(x) (((x) & 0x00007000) >> 12) +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_SET(x) (((x) << 12) & 0x00007000) +#define PHY_ANALOG_TXRF4_AMP2CAS2G_MSB 17 +#define PHY_ANALOG_TXRF4_AMP2CAS2G_LSB 15 +#define PHY_ANALOG_TXRF4_AMP2CAS2G_MASK 0x00038000 +#define PHY_ANALOG_TXRF4_AMP2CAS2G_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_TXRF4_AMP2CAS2G_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_TXRF4_FILTR2G_MSB 19 +#define PHY_ANALOG_TXRF4_FILTR2G_LSB 18 +#define PHY_ANALOG_TXRF4_FILTR2G_MASK 0x000c0000 +#define PHY_ANALOG_TXRF4_FILTR2G_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_ANALOG_TXRF4_FILTR2G_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_ANALOG_TXRF4_PWDFB2_2G_MSB 20 +#define PHY_ANALOG_TXRF4_PWDFB2_2G_LSB 20 +#define PHY_ANALOG_TXRF4_PWDFB2_2G_MASK 0x00100000 +#define PHY_ANALOG_TXRF4_PWDFB2_2G_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TXRF4_PWDFB2_2G_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TXRF4_PWDFB1_2G_MSB 21 +#define PHY_ANALOG_TXRF4_PWDFB1_2G_LSB 21 +#define PHY_ANALOG_TXRF4_PWDFB1_2G_MASK 0x00200000 +#define PHY_ANALOG_TXRF4_PWDFB1_2G_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_TXRF4_PWDFB1_2G_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_TXRF4_PDFB2G_MSB 22 +#define PHY_ANALOG_TXRF4_PDFB2G_LSB 22 +#define PHY_ANALOG_TXRF4_PDFB2G_MASK 0x00400000 +#define PHY_ANALOG_TXRF4_PDFB2G_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_TXRF4_PDFB2G_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_TXRF4_RDIV5G_MSB 24 +#define PHY_ANALOG_TXRF4_RDIV5G_LSB 23 +#define PHY_ANALOG_TXRF4_RDIV5G_MASK 0x01800000 +#define PHY_ANALOG_TXRF4_RDIV5G_GET(x) (((x) & 0x01800000) >> 23) +#define PHY_ANALOG_TXRF4_RDIV5G_SET(x) (((x) << 23) & 0x01800000) +#define PHY_ANALOG_TXRF4_CAPDIV5G_MSB 27 +#define PHY_ANALOG_TXRF4_CAPDIV5G_LSB 25 +#define PHY_ANALOG_TXRF4_CAPDIV5G_MASK 0x0e000000 +#define PHY_ANALOG_TXRF4_CAPDIV5G_GET(x) (((x) & 0x0e000000) >> 25) +#define PHY_ANALOG_TXRF4_CAPDIV5G_SET(x) (((x) << 25) & 0x0e000000) +#define PHY_ANALOG_TXRF4_PDPREDIST5G_MSB 28 +#define PHY_ANALOG_TXRF4_PDPREDIST5G_LSB 28 +#define PHY_ANALOG_TXRF4_PDPREDIST5G_MASK 0x10000000 +#define PHY_ANALOG_TXRF4_PDPREDIST5G_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_TXRF4_PDPREDIST5G_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_TXRF4_RDIV2G_MSB 30 +#define PHY_ANALOG_TXRF4_RDIV2G_LSB 29 +#define PHY_ANALOG_TXRF4_RDIV2G_MASK 0x60000000 +#define PHY_ANALOG_TXRF4_RDIV2G_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_ANALOG_TXRF4_RDIV2G_SET(x) (((x) << 29) & 0x60000000) +#define PHY_ANALOG_TXRF4_PDPREDIST2G_MSB 31 +#define PHY_ANALOG_TXRF4_PDPREDIST2G_LSB 31 +#define PHY_ANALOG_TXRF4_PDPREDIST2G_MASK 0x80000000 +#define PHY_ANALOG_TXRF4_PDPREDIST2G_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF4_PDPREDIST2G_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF5 */ +#define PHY_ANALOG_TXRF5_ADDRESS 0x00000050 +#define PHY_ANALOG_TXRF5_OFFSET 0x00000050 +#define PHY_ANALOG_TXRF5_FBHI2G_MSB 0 +#define PHY_ANALOG_TXRF5_FBHI2G_LSB 0 +#define PHY_ANALOG_TXRF5_FBHI2G_MASK 0x00000001 +#define PHY_ANALOG_TXRF5_FBHI2G_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TXRF5_FBLO2G_MSB 1 +#define PHY_ANALOG_TXRF5_FBLO2G_LSB 1 +#define PHY_ANALOG_TXRF5_FBLO2G_MASK 0x00000002 +#define PHY_ANALOG_TXRF5_FBLO2G_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_TXRF5_REFHI2G_MSB 4 +#define PHY_ANALOG_TXRF5_REFHI2G_LSB 2 +#define PHY_ANALOG_TXRF5_REFHI2G_MASK 0x0000001c +#define PHY_ANALOG_TXRF5_REFHI2G_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_TXRF5_REFHI2G_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_TXRF5_REFLO2G_MSB 7 +#define PHY_ANALOG_TXRF5_REFLO2G_LSB 5 +#define PHY_ANALOG_TXRF5_REFLO2G_MASK 0x000000e0 +#define PHY_ANALOG_TXRF5_REFLO2G_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_TXRF5_REFLO2G_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MSB 9 +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_LSB 8 +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MASK 0x00000300 +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MSB 11 +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_LSB 10 +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MASK 0x00000c00 +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_GET(x) (((x) & 0x00000c00) >> 10) +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_SET(x) (((x) << 10) & 0x00000c00) +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MSB 13 +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_LSB 12 +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MASK 0x00003000 +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_GET(x) (((x) & 0x00003000) >> 12) +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_SET(x) (((x) << 12) & 0x00003000) +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MSB 15 +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_LSB 14 +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MASK 0x0000c000 +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MSB 17 +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_LSB 16 +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MASK 0x00030000 +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_GET(x) (((x) & 0x00030000) >> 16) +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_SET(x) (((x) << 16) & 0x00030000) +#define PHY_ANALOG_TXRF5_PK1B2G_CCK_MSB 19 +#define PHY_ANALOG_TXRF5_PK1B2G_CCK_LSB 18 +#define PHY_ANALOG_TXRF5_PK1B2G_CCK_MASK 0x000c0000 +#define PHY_ANALOG_TXRF5_PK1B2G_CCK_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_ANALOG_TXRF5_PK1B2G_CCK_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_ANALOG_TXRF5_MIOB2G_QAM_MSB 22 +#define PHY_ANALOG_TXRF5_MIOB2G_QAM_LSB 20 +#define PHY_ANALOG_TXRF5_MIOB2G_QAM_MASK 0x00700000 +#define PHY_ANALOG_TXRF5_MIOB2G_QAM_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF5_MIOB2G_QAM_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF5_MIOB2G_PSK_MSB 25 +#define PHY_ANALOG_TXRF5_MIOB2G_PSK_LSB 23 +#define PHY_ANALOG_TXRF5_MIOB2G_PSK_MASK 0x03800000 +#define PHY_ANALOG_TXRF5_MIOB2G_PSK_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF5_MIOB2G_PSK_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF5_MIOB2G_CCK_MSB 28 +#define PHY_ANALOG_TXRF5_MIOB2G_CCK_LSB 26 +#define PHY_ANALOG_TXRF5_MIOB2G_CCK_MASK 0x1c000000 +#define PHY_ANALOG_TXRF5_MIOB2G_CCK_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF5_MIOB2G_CCK_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF5_COMP2G_QAM_MSB 31 +#define PHY_ANALOG_TXRF5_COMP2G_QAM_LSB 29 +#define PHY_ANALOG_TXRF5_COMP2G_QAM_MASK 0xe0000000 +#define PHY_ANALOG_TXRF5_COMP2G_QAM_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF5_COMP2G_QAM_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF6 */ +#define PHY_ANALOG_TXRF6_ADDRESS 0x00000054 +#define PHY_ANALOG_TXRF6_OFFSET 0x00000054 +#define PHY_ANALOG_TXRF6_SPARE6_MSB 0 +#define PHY_ANALOG_TXRF6_SPARE6_LSB 0 +#define PHY_ANALOG_TXRF6_SPARE6_MASK 0x00000001 +#define PHY_ANALOG_TXRF6_SPARE6_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TXRF6_SPARE6_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TXRF6_PAL_LOCKED_MSB 1 +#define PHY_ANALOG_TXRF6_PAL_LOCKED_LSB 1 +#define PHY_ANALOG_TXRF6_PAL_LOCKED_MASK 0x00000002 +#define PHY_ANALOG_TXRF6_PAL_LOCKED_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_MSB 7 +#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_LSB 2 +#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_MASK 0x000000fc +#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF6_GAINSTEP2G_MSB 10 +#define PHY_ANALOG_TXRF6_GAINSTEP2G_LSB 8 +#define PHY_ANALOG_TXRF6_GAINSTEP2G_MASK 0x00000700 +#define PHY_ANALOG_TXRF6_GAINSTEP2G_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_TXRF6_GAINSTEP2G_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MSB 11 +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_LSB 11 +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MASK 0x00000800 +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MSB 15 +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_LSB 12 +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MASK 0x0000f000 +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MSB 18 +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_LSB 16 +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MASK 0x00070000 +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_SET(x) (((x) << 16) & 0x00070000) +#define PHY_ANALOG_TXRF6_CAPDIV2G_MSB 21 +#define PHY_ANALOG_TXRF6_CAPDIV2G_LSB 19 +#define PHY_ANALOG_TXRF6_CAPDIV2G_MASK 0x00380000 +#define PHY_ANALOG_TXRF6_CAPDIV2G_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_TXRF6_CAPDIV2G_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MSB 22 +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_LSB 22 +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MASK 0x00400000 +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_TXRF6_ENPACAL2G_MSB 23 +#define PHY_ANALOG_TXRF6_ENPACAL2G_LSB 23 +#define PHY_ANALOG_TXRF6_ENPACAL2G_MASK 0x00800000 +#define PHY_ANALOG_TXRF6_ENPACAL2G_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_TXRF6_ENPACAL2G_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_TXRF6_OFFSET2G_MSB 30 +#define PHY_ANALOG_TXRF6_OFFSET2G_LSB 24 +#define PHY_ANALOG_TXRF6_OFFSET2G_MASK 0x7f000000 +#define PHY_ANALOG_TXRF6_OFFSET2G_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TXRF6_OFFSET2G_SET(x) (((x) << 24) & 0x7f000000) +#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_MSB 31 +#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_LSB 31 +#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_MASK 0x80000000 +#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF7 */ +#define PHY_ANALOG_TXRF7_ADDRESS 0x00000058 +#define PHY_ANALOG_TXRF7_OFFSET 0x00000058 +#define PHY_ANALOG_TXRF7_SPARE7_MSB 1 +#define PHY_ANALOG_TXRF7_SPARE7_LSB 0 +#define PHY_ANALOG_TXRF7_SPARE7_MASK 0x00000003 +#define PHY_ANALOG_TXRF7_SPARE7_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF7_SPARE7_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MSB 7 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_LSB 2 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MASK 0x000000fc +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MSB 13 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_LSB 8 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MASK 0x00003f00 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MSB 19 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_LSB 14 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MASK 0x000fc000 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MSB 25 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_LSB 20 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MASK 0x03f00000 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MSB 31 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_LSB 26 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MASK 0xfc000000 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for TXRF8 */ +#define PHY_ANALOG_TXRF8_ADDRESS 0x0000005c +#define PHY_ANALOG_TXRF8_OFFSET 0x0000005c +#define PHY_ANALOG_TXRF8_SPARE8_MSB 1 +#define PHY_ANALOG_TXRF8_SPARE8_LSB 0 +#define PHY_ANALOG_TXRF8_SPARE8_MASK 0x00000003 +#define PHY_ANALOG_TXRF8_SPARE8_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF8_SPARE8_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MSB 7 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_LSB 2 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MASK 0x000000fc +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MSB 13 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_LSB 8 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MASK 0x00003f00 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MSB 19 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_LSB 14 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MASK 0x000fc000 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MSB 25 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_LSB 20 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MASK 0x03f00000 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MSB 31 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_LSB 26 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MASK 0xfc000000 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for TXRF9 */ +#define PHY_ANALOG_TXRF9_ADDRESS 0x00000060 +#define PHY_ANALOG_TXRF9_OFFSET 0x00000060 +#define PHY_ANALOG_TXRF9_SPARE9_MSB 1 +#define PHY_ANALOG_TXRF9_SPARE9_LSB 0 +#define PHY_ANALOG_TXRF9_SPARE9_MASK 0x00000003 +#define PHY_ANALOG_TXRF9_SPARE9_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF9_SPARE9_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MSB 7 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_LSB 2 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MASK 0x000000fc +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MSB 13 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_LSB 8 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MASK 0x00003f00 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MSB 19 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_LSB 14 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MASK 0x000fc000 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MSB 25 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_LSB 20 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MASK 0x03f00000 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MSB 31 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_LSB 26 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MASK 0xfc000000 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for TXRF10 */ +#define PHY_ANALOG_TXRF10_ADDRESS 0x00000064 +#define PHY_ANALOG_TXRF10_OFFSET 0x00000064 +#define PHY_ANALOG_TXRF10_SPARE10_MSB 12 +#define PHY_ANALOG_TXRF10_SPARE10_LSB 0 +#define PHY_ANALOG_TXRF10_SPARE10_MASK 0x00001fff +#define PHY_ANALOG_TXRF10_SPARE10_GET(x) (((x) & 0x00001fff) >> 0) +#define PHY_ANALOG_TXRF10_SPARE10_SET(x) (((x) << 0) & 0x00001fff) +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MSB 13 +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_LSB 13 +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MASK 0x00002000 +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_TXRF10_D3B5GCALTX_MSB 16 +#define PHY_ANALOG_TXRF10_D3B5GCALTX_LSB 14 +#define PHY_ANALOG_TXRF10_D3B5GCALTX_MASK 0x0001c000 +#define PHY_ANALOG_TXRF10_D3B5GCALTX_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF10_D3B5GCALTX_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF10_D4B5GCALTX_MSB 19 +#define PHY_ANALOG_TXRF10_D4B5GCALTX_LSB 17 +#define PHY_ANALOG_TXRF10_D4B5GCALTX_MASK 0x000e0000 +#define PHY_ANALOG_TXRF10_D4B5GCALTX_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF10_D4B5GCALTX_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MSB 26 +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_LSB 20 +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MASK 0x07f00000 +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_GET(x) (((x) & 0x07f00000) >> 20) +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_SET(x) (((x) << 20) & 0x07f00000) +#define PHY_ANALOG_TXRF10_DB2GCALTX_MSB 29 +#define PHY_ANALOG_TXRF10_DB2GCALTX_LSB 27 +#define PHY_ANALOG_TXRF10_DB2GCALTX_MASK 0x38000000 +#define PHY_ANALOG_TXRF10_DB2GCALTX_GET(x) (((x) & 0x38000000) >> 27) +#define PHY_ANALOG_TXRF10_DB2GCALTX_SET(x) (((x) << 27) & 0x38000000) +#define PHY_ANALOG_TXRF10_CALTXSHIFT_MSB 30 +#define PHY_ANALOG_TXRF10_CALTXSHIFT_LSB 30 +#define PHY_ANALOG_TXRF10_CALTXSHIFT_MASK 0x40000000 +#define PHY_ANALOG_TXRF10_CALTXSHIFT_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_TXRF10_CALTXSHIFT_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MSB 31 +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_LSB 31 +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MASK 0x80000000 +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF11 */ +#define PHY_ANALOG_TXRF11_ADDRESS 0x00000068 +#define PHY_ANALOG_TXRF11_OFFSET 0x00000068 +#define PHY_ANALOG_TXRF11_SPARE11_MSB 1 +#define PHY_ANALOG_TXRF11_SPARE11_LSB 0 +#define PHY_ANALOG_TXRF11_SPARE11_MASK 0x00000003 +#define PHY_ANALOG_TXRF11_SPARE11_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF11_SPARE11_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_MSB 4 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_LSB 2 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_MASK 0x0000001c +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MSB 7 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_LSB 5 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MASK 0x000000e0 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MSB 10 +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_LSB 8 +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MASK 0x00000700 +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MSB 13 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_LSB 11 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MASK 0x00003800 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MSB 16 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_LSB 14 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MASK 0x0001c000 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MSB 19 +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_LSB 17 +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MASK 0x000e0000 +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MSB 22 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_LSB 20 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MASK 0x00700000 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MSB 25 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_LSB 23 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MASK 0x03800000 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MSB 28 +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_LSB 26 +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MASK 0x1c000000 +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MSB 31 +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_LSB 29 +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF12 */ +#define PHY_ANALOG_TXRF12_ADDRESS 0x0000006c +#define PHY_ANALOG_TXRF12_OFFSET 0x0000006c +#define PHY_ANALOG_TXRF12_SPARE12_2_MSB 7 +#define PHY_ANALOG_TXRF12_SPARE12_2_LSB 0 +#define PHY_ANALOG_TXRF12_SPARE12_2_MASK 0x000000ff +#define PHY_ANALOG_TXRF12_SPARE12_2_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_ANALOG_TXRF12_SPARE12_1_MSB 15 +#define PHY_ANALOG_TXRF12_SPARE12_1_LSB 8 +#define PHY_ANALOG_TXRF12_SPARE12_1_MASK 0x0000ff00 +#define PHY_ANALOG_TXRF12_SPARE12_1_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_ANALOG_TXRF12_SPARE12_1_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_ANALOG_TXRF12_ATBSEL5G_MSB 19 +#define PHY_ANALOG_TXRF12_ATBSEL5G_LSB 16 +#define PHY_ANALOG_TXRF12_ATBSEL5G_MASK 0x000f0000 +#define PHY_ANALOG_TXRF12_ATBSEL5G_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_TXRF12_ATBSEL5G_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_ANALOG_TXRF12_ATBSEL2G_MSB 22 +#define PHY_ANALOG_TXRF12_ATBSEL2G_LSB 20 +#define PHY_ANALOG_TXRF12_ATBSEL2G_MASK 0x00700000 +#define PHY_ANALOG_TXRF12_ATBSEL2G_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF12_ATBSEL2G_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MSB 25 +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_LSB 23 +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MASK 0x03800000 +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MSB 28 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_LSB 26 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MASK 0x1c000000 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MSB 31 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_LSB 29 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MASK 0xe0000000 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for SYNTH1 */ +#define PHY_ANALOG_SYNTH1_ADDRESS 0x00000080 +#define PHY_ANALOG_SYNTH1_OFFSET 0x00000080 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MSB 2 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_LSB 0 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MASK 0x00000007 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MSB 5 +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_LSB 3 +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MASK 0x00000038 +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_SET(x) (((x) << 3) & 0x00000038) +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 6 +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 6 +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000040 +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MSB 7 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_LSB 7 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MASK 0x00000080 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MSB 8 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_LSB 8 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000100 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MSB 9 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_LSB 9 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000200 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_SYNTH1_MONITOR_REF_MSB 10 +#define PHY_ANALOG_SYNTH1_MONITOR_REF_LSB 10 +#define PHY_ANALOG_SYNTH1_MONITOR_REF_MASK 0x00000400 +#define PHY_ANALOG_SYNTH1_MONITOR_REF_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH1_MONITOR_REF_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_MSB 11 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_LSB 11 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_MASK 0x00000800 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MSB 12 +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_LSB 12 +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MASK 0x00001000 +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_SYNTH1_PWUP_PD_MSB 15 +#define PHY_ANALOG_SYNTH1_PWUP_PD_LSB 13 +#define PHY_ANALOG_SYNTH1_PWUP_PD_MASK 0x0000e000 +#define PHY_ANALOG_SYNTH1_PWUP_PD_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_SYNTH1_PWUP_PD_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MSB 16 +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_LSB 16 +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MASK 0x00010000 +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MSB 18 +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_LSB 17 +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MASK 0x00060000 +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_GET(x) (((x) & 0x00060000) >> 17) +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_SET(x) (((x) << 17) & 0x00060000) +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MSB 20 +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_LSB 19 +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MASK 0x00180000 +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_GET(x) (((x) & 0x00180000) >> 19) +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_SET(x) (((x) << 19) & 0x00180000) +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MSB 21 +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_LSB 21 +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MASK 0x00200000 +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MSB 22 +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_LSB 22 +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MASK 0x00400000 +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MSB 23 +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_LSB 23 +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MASK 0x00800000 +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_SYNTH1_PWD_LODIV_MSB 24 +#define PHY_ANALOG_SYNTH1_PWD_LODIV_LSB 24 +#define PHY_ANALOG_SYNTH1_PWD_LODIV_MASK 0x01000000 +#define PHY_ANALOG_SYNTH1_PWD_LODIV_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_SYNTH1_PWD_LODIV_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MSB 25 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_LSB 25 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MASK 0x02000000 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << 25) & 0x02000000) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MSB 26 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_LSB 26 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MASK 0x04000000 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_SYNTH1_PWD_PRESC_MSB 27 +#define PHY_ANALOG_SYNTH1_PWD_PRESC_LSB 27 +#define PHY_ANALOG_SYNTH1_PWD_PRESC_MASK 0x08000000 +#define PHY_ANALOG_SYNTH1_PWD_PRESC_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_SYNTH1_PWD_PRESC_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_SYNTH1_PWD_VCO_MSB 28 +#define PHY_ANALOG_SYNTH1_PWD_VCO_LSB 28 +#define PHY_ANALOG_SYNTH1_PWD_VCO_MASK 0x10000000 +#define PHY_ANALOG_SYNTH1_PWD_VCO_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_SYNTH1_PWD_VCO_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_SYNTH1_PWD_VCMON_MSB 29 +#define PHY_ANALOG_SYNTH1_PWD_VCMON_LSB 29 +#define PHY_ANALOG_SYNTH1_PWD_VCMON_MASK 0x20000000 +#define PHY_ANALOG_SYNTH1_PWD_VCMON_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_SYNTH1_PWD_VCMON_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_SYNTH1_PWD_CP_MSB 30 +#define PHY_ANALOG_SYNTH1_PWD_CP_LSB 30 +#define PHY_ANALOG_SYNTH1_PWD_CP_MASK 0x40000000 +#define PHY_ANALOG_SYNTH1_PWD_CP_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH1_PWD_CP_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH1_PWD_BIAS_MSB 31 +#define PHY_ANALOG_SYNTH1_PWD_BIAS_LSB 31 +#define PHY_ANALOG_SYNTH1_PWD_BIAS_MASK 0x80000000 +#define PHY_ANALOG_SYNTH1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH2 */ +#define PHY_ANALOG_SYNTH2_ADDRESS 0x00000084 +#define PHY_ANALOG_SYNTH2_OFFSET 0x00000084 +#define PHY_ANALOG_SYNTH2_CAPRANGE3_MSB 3 +#define PHY_ANALOG_SYNTH2_CAPRANGE3_LSB 0 +#define PHY_ANALOG_SYNTH2_CAPRANGE3_MASK 0x0000000f +#define PHY_ANALOG_SYNTH2_CAPRANGE3_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_SYNTH2_CAPRANGE3_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_ANALOG_SYNTH2_CAPRANGE2_MSB 7 +#define PHY_ANALOG_SYNTH2_CAPRANGE2_LSB 4 +#define PHY_ANALOG_SYNTH2_CAPRANGE2_MASK 0x000000f0 +#define PHY_ANALOG_SYNTH2_CAPRANGE2_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_SYNTH2_CAPRANGE2_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_SYNTH2_CAPRANGE1_MSB 11 +#define PHY_ANALOG_SYNTH2_CAPRANGE1_LSB 8 +#define PHY_ANALOG_SYNTH2_CAPRANGE1_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH2_CAPRANGE1_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH2_CAPRANGE1_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_MSB 15 +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_LSB 12 +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_MASK 0x0000f000 +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_ANALOG_SYNTH2_CPLOWLK_MSB 16 +#define PHY_ANALOG_SYNTH2_CPLOWLK_LSB 16 +#define PHY_ANALOG_SYNTH2_CPLOWLK_MASK 0x00010000 +#define PHY_ANALOG_SYNTH2_CPLOWLK_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_SYNTH2_CPLOWLK_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MSB 17 +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_LSB 17 +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MASK 0x00020000 +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_SYNTH2_CPBIAS_MSB 19 +#define PHY_ANALOG_SYNTH2_CPBIAS_LSB 18 +#define PHY_ANALOG_SYNTH2_CPBIAS_MASK 0x000c0000 +#define PHY_ANALOG_SYNTH2_CPBIAS_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_ANALOG_SYNTH2_CPBIAS_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MSB 22 +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_LSB 20 +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MASK 0x00700000 +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_SYNTH2_VC_MID_REF_MSB 25 +#define PHY_ANALOG_SYNTH2_VC_MID_REF_LSB 23 +#define PHY_ANALOG_SYNTH2_VC_MID_REF_MASK 0x03800000 +#define PHY_ANALOG_SYNTH2_VC_MID_REF_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_SYNTH2_VC_MID_REF_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_SYNTH2_VC_HI_REF_MSB 28 +#define PHY_ANALOG_SYNTH2_VC_HI_REF_LSB 26 +#define PHY_ANALOG_SYNTH2_VC_HI_REF_MASK 0x1c000000 +#define PHY_ANALOG_SYNTH2_VC_HI_REF_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_SYNTH2_VC_HI_REF_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MSB 31 +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_LSB 29 +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MASK 0xe0000000 +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for SYNTH3 */ +#define PHY_ANALOG_SYNTH3_ADDRESS 0x00000088 +#define PHY_ANALOG_SYNTH3_OFFSET 0x00000088 +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MSB 5 +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_LSB 0 +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MSB 11 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_LSB 6 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MSB 17 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_LSB 12 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MSB 23 +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_LSB 18 +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000 +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_SET(x) (((x) << 18) & 0x00fc0000) +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29 +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24 +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000 +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << 24) & 0x3f000000) +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MSB 30 +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_LSB 30 +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000 +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MSB 31 +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_LSB 31 +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000 +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH4 */ +#define PHY_ANALOG_SYNTH4_ADDRESS 0x0000008c +#define PHY_ANALOG_SYNTH4_OFFSET 0x0000008c +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MSB 0 +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_LSB 0 +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MASK 0x00000001 +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MSB 1 +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_LSB 1 +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MASK 0x00000002 +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MSB 3 +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_LSB 2 +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MASK 0x0000000c +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MSB 4 +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_LSB 4 +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MASK 0x00000010 +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MSB 5 +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_LSB 5 +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020 +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_SYNTH4_SDM_DITHER_MSB 7 +#define PHY_ANALOG_SYNTH4_SDM_DITHER_LSB 6 +#define PHY_ANALOG_SYNTH4_SDM_DITHER_MASK 0x000000c0 +#define PHY_ANALOG_SYNTH4_SDM_DITHER_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_ANALOG_SYNTH4_SDM_DITHER_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_ANALOG_SYNTH4_SDM_MODE_MSB 8 +#define PHY_ANALOG_SYNTH4_SDM_MODE_LSB 8 +#define PHY_ANALOG_SYNTH4_SDM_MODE_MASK 0x00000100 +#define PHY_ANALOG_SYNTH4_SDM_MODE_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_SYNTH4_SDM_MODE_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MSB 9 +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_LSB 9 +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MASK 0x00000200 +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_SYNTH4_RESET_PRESC_MSB 10 +#define PHY_ANALOG_SYNTH4_RESET_PRESC_LSB 10 +#define PHY_ANALOG_SYNTH4_RESET_PRESC_MASK 0x00000400 +#define PHY_ANALOG_SYNTH4_RESET_PRESC_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH4_RESET_PRESC_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH4_PRESCSEL_MSB 12 +#define PHY_ANALOG_SYNTH4_PRESCSEL_LSB 11 +#define PHY_ANALOG_SYNTH4_PRESCSEL_MASK 0x00001800 +#define PHY_ANALOG_SYNTH4_PRESCSEL_GET(x) (((x) & 0x00001800) >> 11) +#define PHY_ANALOG_SYNTH4_PRESCSEL_SET(x) (((x) << 11) & 0x00001800) +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MSB 13 +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_LSB 13 +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MASK 0x00002000 +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MSB 14 +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_LSB 14 +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MASK 0x00004000 +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MSB 15 +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_LSB 15 +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MASK 0x00008000 +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MSB 16 +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_LSB 16 +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MASK 0x00010000 +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MSB 17 +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_LSB 17 +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MASK 0x00020000 +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MSB 25 +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_LSB 18 +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000 +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_GET(x) (((x) & 0x03fc0000) >> 18) +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_SET(x) (((x) << 18) & 0x03fc0000) +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MSB 26 +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_LSB 26 +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MASK 0x04000000 +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MSB 27 +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_LSB 27 +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MASK 0x08000000 +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28 +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28 +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000 +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MSB 29 +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_LSB 29 +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000 +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MSB 30 +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_LSB 30 +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MASK 0x40000000 +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31 +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31 +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000 +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH5 */ +#define PHY_ANALOG_SYNTH5_ADDRESS 0x00000090 +#define PHY_ANALOG_SYNTH5_OFFSET 0x00000090 +#define PHY_ANALOG_SYNTH5_VCOBIAS_MSB 1 +#define PHY_ANALOG_SYNTH5_VCOBIAS_LSB 0 +#define PHY_ANALOG_SYNTH5_VCOBIAS_MASK 0x00000003 +#define PHY_ANALOG_SYNTH5_VCOBIAS_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_SYNTH5_VCOBIAS_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MSB 4 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_LSB 2 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MASK 0x0000001c +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MSB 7 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_LSB 5 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MASK 0x000000e0 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MSB 10 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_LSB 8 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MASK 0x00000700 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MSB 13 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_LSB 11 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MASK 0x00003800 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MSB 14 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_LSB 14 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MASK 0x00004000 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MSB 17 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_LSB 15 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MASK 0x00038000 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MSB 20 +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_LSB 18 +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MASK 0x001c0000 +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_GET(x) (((x) & 0x001c0000) >> 18) +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_SET(x) (((x) << 18) & 0x001c0000) +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MSB 23 +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_LSB 21 +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MASK 0x00e00000 +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_GET(x) (((x) & 0x00e00000) >> 21) +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_SET(x) (((x) << 21) & 0x00e00000) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MSB 26 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_LSB 24 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MASK 0x07000000 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_SET(x) (((x) << 24) & 0x07000000) +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MSB 29 +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_LSB 27 +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MASK 0x38000000 +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_GET(x) (((x) & 0x38000000) >> 27) +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_SET(x) (((x) << 27) & 0x38000000) +#define PHY_ANALOG_SYNTH5_SPARE5A_MSB 31 +#define PHY_ANALOG_SYNTH5_SPARE5A_LSB 30 +#define PHY_ANALOG_SYNTH5_SPARE5A_MASK 0xc0000000 +#define PHY_ANALOG_SYNTH5_SPARE5A_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_ANALOG_SYNTH5_SPARE5A_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for SYNTH6 */ +#define PHY_ANALOG_SYNTH6_ADDRESS 0x00000094 +#define PHY_ANALOG_SYNTH6_OFFSET 0x00000094 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MSB 1 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_LSB 0 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MASK 0x00000003 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_SYNTH6_LOOP_IP_MSB 8 +#define PHY_ANALOG_SYNTH6_LOOP_IP_LSB 2 +#define PHY_ANALOG_SYNTH6_LOOP_IP_MASK 0x000001fc +#define PHY_ANALOG_SYNTH6_LOOP_IP_GET(x) (((x) & 0x000001fc) >> 2) +#define PHY_ANALOG_SYNTH6_VC2LOW_MSB 9 +#define PHY_ANALOG_SYNTH6_VC2LOW_LSB 9 +#define PHY_ANALOG_SYNTH6_VC2LOW_MASK 0x00000200 +#define PHY_ANALOG_SYNTH6_VC2LOW_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_SYNTH6_VC2HIGH_MSB 10 +#define PHY_ANALOG_SYNTH6_VC2HIGH_LSB 10 +#define PHY_ANALOG_SYNTH6_VC2HIGH_MASK 0x00000400 +#define PHY_ANALOG_SYNTH6_VC2HIGH_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MSB 11 +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_LSB 11 +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MASK 0x00000800 +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MSB 12 +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_LSB 12 +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MASK 0x00001000 +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_SYNTH6_RESET_PFD_MSB 13 +#define PHY_ANALOG_SYNTH6_RESET_PFD_LSB 13 +#define PHY_ANALOG_SYNTH6_RESET_PFD_MASK 0x00002000 +#define PHY_ANALOG_SYNTH6_RESET_PFD_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_SYNTH6_RESET_RFD_MSB 14 +#define PHY_ANALOG_SYNTH6_RESET_RFD_LSB 14 +#define PHY_ANALOG_SYNTH6_RESET_RFD_MASK 0x00004000 +#define PHY_ANALOG_SYNTH6_RESET_RFD_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH6_SHORT_R_MSB 15 +#define PHY_ANALOG_SYNTH6_SHORT_R_LSB 15 +#define PHY_ANALOG_SYNTH6_SHORT_R_MASK 0x00008000 +#define PHY_ANALOG_SYNTH6_SHORT_R_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MSB 23 +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_LSB 16 +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MASK 0x00ff0000 +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_SYNTH6_PIN_VC_MSB 24 +#define PHY_ANALOG_SYNTH6_PIN_VC_LSB 24 +#define PHY_ANALOG_SYNTH6_PIN_VC_MASK 0x01000000 +#define PHY_ANALOG_SYNTH6_PIN_VC_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MSB 25 +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_LSB 25 +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MASK 0x02000000 +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MSB 26 +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_LSB 26 +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MASK 0x04000000 +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MSB 30 +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_LSB 27 +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MASK 0x78000000 +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_SYNTH6_SYNTH_ON_MSB 31 +#define PHY_ANALOG_SYNTH6_SYNTH_ON_LSB 31 +#define PHY_ANALOG_SYNTH6_SYNTH_ON_MASK 0x80000000 +#define PHY_ANALOG_SYNTH6_SYNTH_ON_GET(x) (((x) & 0x80000000) >> 31) + +/* macros for SYNTH7 */ +#define PHY_ANALOG_SYNTH7_ADDRESS 0x00000098 +#define PHY_ANALOG_SYNTH7_OFFSET 0x00000098 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MSB 0 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_LSB 0 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MASK 0x00000001 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MSB 1 +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_LSB 1 +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MASK 0x00000002 +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_SYNTH7_CHANFRAC_MSB 18 +#define PHY_ANALOG_SYNTH7_CHANFRAC_LSB 2 +#define PHY_ANALOG_SYNTH7_CHANFRAC_MASK 0x0007fffc +#define PHY_ANALOG_SYNTH7_CHANFRAC_GET(x) (((x) & 0x0007fffc) >> 2) +#define PHY_ANALOG_SYNTH7_CHANFRAC_SET(x) (((x) << 2) & 0x0007fffc) +#define PHY_ANALOG_SYNTH7_CHANSEL_MSB 27 +#define PHY_ANALOG_SYNTH7_CHANSEL_LSB 19 +#define PHY_ANALOG_SYNTH7_CHANSEL_MASK 0x0ff80000 +#define PHY_ANALOG_SYNTH7_CHANSEL_GET(x) (((x) & 0x0ff80000) >> 19) +#define PHY_ANALOG_SYNTH7_CHANSEL_SET(x) (((x) << 19) & 0x0ff80000) +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MSB 29 +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_LSB 28 +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MASK 0x30000000 +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_GET(x) (((x) & 0x30000000) >> 28) +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_SET(x) (((x) << 28) & 0x30000000) +#define PHY_ANALOG_SYNTH7_FRACMODE_MSB 30 +#define PHY_ANALOG_SYNTH7_FRACMODE_LSB 30 +#define PHY_ANALOG_SYNTH7_FRACMODE_MASK 0x40000000 +#define PHY_ANALOG_SYNTH7_FRACMODE_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH7_FRACMODE_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MSB 31 +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_LSB 31 +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MASK 0x80000000 +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH8 */ +#define PHY_ANALOG_SYNTH8_ADDRESS 0x0000009c +#define PHY_ANALOG_SYNTH8_OFFSET 0x0000009c +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MSB 0 +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_LSB 0 +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MASK 0x00000001 +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MSB 7 +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_LSB 1 +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MASK 0x000000fe +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_GET(x) (((x) & 0x000000fe) >> 1) +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_SET(x) (((x) << 1) & 0x000000fe) +#define PHY_ANALOG_SYNTH8_LOOP_CSB_MSB 11 +#define PHY_ANALOG_SYNTH8_LOOP_CSB_LSB 8 +#define PHY_ANALOG_SYNTH8_LOOP_CSB_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH8_LOOP_CSB_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH8_LOOP_CSB_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH8_LOOP_RSB_MSB 16 +#define PHY_ANALOG_SYNTH8_LOOP_RSB_LSB 12 +#define PHY_ANALOG_SYNTH8_LOOP_RSB_MASK 0x0001f000 +#define PHY_ANALOG_SYNTH8_LOOP_RSB_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_ANALOG_SYNTH8_LOOP_RSB_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_ANALOG_SYNTH8_LOOP_CPB_MSB 21 +#define PHY_ANALOG_SYNTH8_LOOP_CPB_LSB 17 +#define PHY_ANALOG_SYNTH8_LOOP_CPB_MASK 0x003e0000 +#define PHY_ANALOG_SYNTH8_LOOP_CPB_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_ANALOG_SYNTH8_LOOP_CPB_SET(x) (((x) << 17) & 0x003e0000) +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MSB 26 +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_LSB 22 +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH8_REFDIVB_MSB 31 +#define PHY_ANALOG_SYNTH8_REFDIVB_LSB 27 +#define PHY_ANALOG_SYNTH8_REFDIVB_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH8_REFDIVB_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH8_REFDIVB_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH9 */ +#define PHY_ANALOG_SYNTH9_ADDRESS 0x000000a0 +#define PHY_ANALOG_SYNTH9_OFFSET 0x000000a0 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MSB 0 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_LSB 0 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MASK 0x00000001 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MSB 3 +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_LSB 1 +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MASK 0x0000000e +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MSB 7 +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_LSB 4 +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MASK 0x000000f0 +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MSB 11 +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_LSB 8 +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MSB 16 +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_LSB 12 +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MASK 0x0001f000 +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MSB 21 +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_LSB 17 +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MASK 0x003e0000 +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_SET(x) (((x) << 17) & 0x003e0000) +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MSB 26 +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_LSB 22 +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH9_REFDIVA_MSB 31 +#define PHY_ANALOG_SYNTH9_REFDIVA_LSB 27 +#define PHY_ANALOG_SYNTH9_REFDIVA_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH9_REFDIVA_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH9_REFDIVA_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH10 */ +#define PHY_ANALOG_SYNTH10_ADDRESS 0x000000a4 +#define PHY_ANALOG_SYNTH10_OFFSET 0x000000a4 +#define PHY_ANALOG_SYNTH10_SPARE10A_MSB 0 +#define PHY_ANALOG_SYNTH10_SPARE10A_LSB 0 +#define PHY_ANALOG_SYNTH10_SPARE10A_MASK 0x00000001 +#define PHY_ANALOG_SYNTH10_SPARE10A_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH10_SPARE10A_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MSB 3 +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_LSB 1 +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MASK 0x0000000e +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_MSB 4 +#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_LSB 4 +#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_MASK 0x00000010 +#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MSB 7 +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_LSB 5 +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MASK 0x000000e0 +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MSB 10 +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_LSB 8 +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MASK 0x00000700 +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MSB 13 +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_LSB 11 +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MASK 0x00003800 +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MSB 17 +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_LSB 14 +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MASK 0x0003c000 +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_GET(x) (((x) & 0x0003c000) >> 14) +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_SET(x) (((x) << 14) & 0x0003c000) +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MSB 21 +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_LSB 18 +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MASK 0x003c0000 +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_GET(x) (((x) & 0x003c0000) >> 18) +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_SET(x) (((x) << 18) & 0x003c0000) +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MSB 26 +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_LSB 22 +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MSB 31 +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_LSB 27 +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH11 */ +#define PHY_ANALOG_SYNTH11_ADDRESS 0x000000a8 +#define PHY_ANALOG_SYNTH11_OFFSET 0x000000a8 +#define PHY_ANALOG_SYNTH11_SPARE11A_MSB 4 +#define PHY_ANALOG_SYNTH11_SPARE11A_LSB 0 +#define PHY_ANALOG_SYNTH11_SPARE11A_MASK 0x0000001f +#define PHY_ANALOG_SYNTH11_SPARE11A_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_SYNTH11_SPARE11A_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MSB 5 +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_LSB 5 +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MASK 0x00000020 +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_SYNTH11_LOREFSEL_MSB 7 +#define PHY_ANALOG_SYNTH11_LOREFSEL_LSB 6 +#define PHY_ANALOG_SYNTH11_LOREFSEL_MASK 0x000000c0 +#define PHY_ANALOG_SYNTH11_LOREFSEL_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_ANALOG_SYNTH11_LOREFSEL_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MSB 9 +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_LSB 8 +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MASK 0x00000300 +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MSB 10 +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_LSB 10 +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MASK 0x00000400 +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MSB 13 +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_LSB 11 +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MASK 0x00003800 +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MSB 17 +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_LSB 14 +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MASK 0x0003c000 +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_GET(x) (((x) & 0x0003c000) >> 14) +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_SET(x) (((x) << 14) & 0x0003c000) +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MSB 21 +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_LSB 18 +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MASK 0x003c0000 +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_GET(x) (((x) & 0x003c0000) >> 18) +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_SET(x) (((x) << 18) & 0x003c0000) +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MSB 26 +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_LSB 22 +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MSB 31 +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_LSB 27 +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH12 */ +#define PHY_ANALOG_SYNTH12_ADDRESS 0x000000ac +#define PHY_ANALOG_SYNTH12_OFFSET 0x000000ac +#define PHY_ANALOG_SYNTH12_SPARE12A_MSB 17 +#define PHY_ANALOG_SYNTH12_SPARE12A_LSB 0 +#define PHY_ANALOG_SYNTH12_SPARE12A_MASK 0x0003ffff +#define PHY_ANALOG_SYNTH12_SPARE12A_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_ANALOG_SYNTH12_SPARE12A_SET(x) (((x) << 0) & 0x0003ffff) +#define PHY_ANALOG_SYNTH12_STRCONT_MSB 18 +#define PHY_ANALOG_SYNTH12_STRCONT_LSB 18 +#define PHY_ANALOG_SYNTH12_STRCONT_MASK 0x00040000 +#define PHY_ANALOG_SYNTH12_STRCONT_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_SYNTH12_STRCONT_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_SYNTH12_VREFMUL3_MSB 22 +#define PHY_ANALOG_SYNTH12_VREFMUL3_LSB 19 +#define PHY_ANALOG_SYNTH12_VREFMUL3_MASK 0x00780000 +#define PHY_ANALOG_SYNTH12_VREFMUL3_GET(x) (((x) & 0x00780000) >> 19) +#define PHY_ANALOG_SYNTH12_VREFMUL3_SET(x) (((x) << 19) & 0x00780000) +#define PHY_ANALOG_SYNTH12_VREFMUL2_MSB 26 +#define PHY_ANALOG_SYNTH12_VREFMUL2_LSB 23 +#define PHY_ANALOG_SYNTH12_VREFMUL2_MASK 0x07800000 +#define PHY_ANALOG_SYNTH12_VREFMUL2_GET(x) (((x) & 0x07800000) >> 23) +#define PHY_ANALOG_SYNTH12_VREFMUL2_SET(x) (((x) << 23) & 0x07800000) +#define PHY_ANALOG_SYNTH12_VREFMUL1_MSB 30 +#define PHY_ANALOG_SYNTH12_VREFMUL1_LSB 27 +#define PHY_ANALOG_SYNTH12_VREFMUL1_MASK 0x78000000 +#define PHY_ANALOG_SYNTH12_VREFMUL1_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_SYNTH12_VREFMUL1_SET(x) (((x) << 27) & 0x78000000) +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MSB 31 +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_LSB 31 +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MASK 0x80000000 +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BIAS1 */ +#define PHY_ANALOG_BIAS1_ADDRESS 0x000000c0 +#define PHY_ANALOG_BIAS1_OFFSET 0x000000c0 +#define PHY_ANALOG_BIAS1_SPARE1_MSB 6 +#define PHY_ANALOG_BIAS1_SPARE1_LSB 0 +#define PHY_ANALOG_BIAS1_SPARE1_MASK 0x0000007f +#define PHY_ANALOG_BIAS1_SPARE1_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_BIAS1_SPARE1_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MSB 9 +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_LSB 7 +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MASK 0x00000380 +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MSB 12 +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_LSB 10 +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MASK 0x00001c00 +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_GET(x) (((x) & 0x00001c00) >> 10) +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_SET(x) (((x) << 10) & 0x00001c00) +#define PHY_ANALOG_BIAS1_PWD_IC25BB_MSB 15 +#define PHY_ANALOG_BIAS1_PWD_IC25BB_LSB 13 +#define PHY_ANALOG_BIAS1_PWD_IC25BB_MASK 0x0000e000 +#define PHY_ANALOG_BIAS1_PWD_IC25BB_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_BIAS1_PWD_IC25BB_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MSB 18 +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_LSB 16 +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MASK 0x00070000 +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_SET(x) (((x) << 16) & 0x00070000) +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MSB 21 +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_LSB 19 +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MASK 0x00380000 +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MSB 24 +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_LSB 22 +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MASK 0x01c00000 +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_GET(x) (((x) & 0x01c00000) >> 22) +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_SET(x) (((x) << 22) & 0x01c00000) +#define PHY_ANALOG_BIAS1_BIAS_SEL_MSB 31 +#define PHY_ANALOG_BIAS1_BIAS_SEL_LSB 25 +#define PHY_ANALOG_BIAS1_BIAS_SEL_MASK 0xfe000000 +#define PHY_ANALOG_BIAS1_BIAS_SEL_GET(x) (((x) & 0xfe000000) >> 25) +#define PHY_ANALOG_BIAS1_BIAS_SEL_SET(x) (((x) << 25) & 0xfe000000) + +/* macros for BIAS2 */ +#define PHY_ANALOG_BIAS2_ADDRESS 0x000000c4 +#define PHY_ANALOG_BIAS2_OFFSET 0x000000c4 +#define PHY_ANALOG_BIAS2_SPARE2_MSB 4 +#define PHY_ANALOG_BIAS2_SPARE2_LSB 0 +#define PHY_ANALOG_BIAS2_SPARE2_MASK 0x0000001f +#define PHY_ANALOG_BIAS2_SPARE2_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_BIAS2_SPARE2_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_MSB 7 +#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_LSB 5 +#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_MASK 0x000000e0 +#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MSB 10 +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_LSB 8 +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MASK 0x00000700 +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MSB 13 +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_LSB 11 +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MASK 0x00003800 +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MSB 16 +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_LSB 14 +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MASK 0x0001c000 +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_MSB 19 +#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_LSB 17 +#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_MASK 0x000e0000 +#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MSB 22 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_LSB 20 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MASK 0x00700000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MSB 25 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_LSB 23 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MASK 0x03800000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MSB 28 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_LSB 26 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MASK 0x1c000000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MSB 31 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_LSB 29 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MASK 0xe0000000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for BIAS3 */ +#define PHY_ANALOG_BIAS3_ADDRESS 0x000000c8 +#define PHY_ANALOG_BIAS3_OFFSET 0x000000c8 +#define PHY_ANALOG_BIAS3_SPARE3_MSB 1 +#define PHY_ANALOG_BIAS3_SPARE3_LSB 0 +#define PHY_ANALOG_BIAS3_SPARE3_MASK 0x00000003 +#define PHY_ANALOG_BIAS3_SPARE3_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_BIAS3_SPARE3_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_MSB 4 +#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_LSB 2 +#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_MASK 0x0000001c +#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MSB 7 +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_LSB 5 +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MASK 0x000000e0 +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MSB 10 +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_LSB 8 +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MASK 0x00000700 +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_MSB 13 +#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_LSB 11 +#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_MASK 0x00003800 +#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MSB 16 +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_LSB 14 +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MASK 0x0001c000 +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_BIAS3_PWD_IR25BB_MSB 19 +#define PHY_ANALOG_BIAS3_PWD_IR25BB_LSB 17 +#define PHY_ANALOG_BIAS3_PWD_IR25BB_MASK 0x000e0000 +#define PHY_ANALOG_BIAS3_PWD_IR25BB_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_BIAS3_PWD_IR25BB_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MSB 22 +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_LSB 20 +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MASK 0x00700000 +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MSB 25 +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_LSB 23 +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MASK 0x03800000 +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MSB 28 +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_LSB 26 +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MASK 0x1c000000 +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MSB 31 +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_LSB 29 +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MASK 0xe0000000 +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for BIAS4 */ +#define PHY_ANALOG_BIAS4_ADDRESS 0x000000cc +#define PHY_ANALOG_BIAS4_OFFSET 0x000000cc +#define PHY_ANALOG_BIAS4_SPARE4_MSB 13 +#define PHY_ANALOG_BIAS4_SPARE4_LSB 0 +#define PHY_ANALOG_BIAS4_SPARE4_MASK 0x00003fff +#define PHY_ANALOG_BIAS4_SPARE4_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_ANALOG_BIAS4_SPARE4_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MSB 16 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_LSB 14 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MASK 0x0001c000 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MSB 19 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_LSB 17 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MASK 0x000e0000 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_MSB 22 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_LSB 20 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_MASK 0x00700000 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MSB 25 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_LSB 23 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MASK 0x03800000 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MSB 28 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_LSB 26 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MASK 0x1c000000 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MSB 31 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_LSB 29 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MASK 0xe0000000 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for RXTX1 */ +#define PHY_ANALOG_RXTX1_ADDRESS 0x00000100 +#define PHY_ANALOG_RXTX1_OFFSET 0x00000100 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MSB 0 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_LSB 0 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MASK 0x00000001 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXTX1_MANRXGAIN_MSB 1 +#define PHY_ANALOG_RXTX1_MANRXGAIN_LSB 1 +#define PHY_ANALOG_RXTX1_MANRXGAIN_MASK 0x00000002 +#define PHY_ANALOG_RXTX1_MANRXGAIN_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXTX1_MANRXGAIN_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXTX1_AGC_DBDAC_MSB 5 +#define PHY_ANALOG_RXTX1_AGC_DBDAC_LSB 2 +#define PHY_ANALOG_RXTX1_AGC_DBDAC_MASK 0x0000003c +#define PHY_ANALOG_RXTX1_AGC_DBDAC_GET(x) (((x) & 0x0000003c) >> 2) +#define PHY_ANALOG_RXTX1_AGC_DBDAC_SET(x) (((x) << 2) & 0x0000003c) +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MSB 6 +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_LSB 6 +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MASK 0x00000040 +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_MSB 7 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_LSB 7 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_MASK 0x00000080 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MSB 8 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_LSB 8 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MASK 0x00000100 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MSB 11 +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_LSB 9 +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MASK 0x00000e00 +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_SET(x) (((x) << 9) & 0x00000e00) +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MSB 13 +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_LSB 12 +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MASK 0x00003000 +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_GET(x) (((x) & 0x00003000) >> 12) +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_SET(x) (((x) << 12) & 0x00003000) +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MSB 14 +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_LSB 14 +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MASK 0x00004000 +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RXTX1_PADRV2GN_MSB 18 +#define PHY_ANALOG_RXTX1_PADRV2GN_LSB 15 +#define PHY_ANALOG_RXTX1_PADRV2GN_MASK 0x00078000 +#define PHY_ANALOG_RXTX1_PADRV2GN_GET(x) (((x) & 0x00078000) >> 15) +#define PHY_ANALOG_RXTX1_PADRV2GN_SET(x) (((x) << 15) & 0x00078000) +#define PHY_ANALOG_RXTX1_PADRV3GN5G_MSB 22 +#define PHY_ANALOG_RXTX1_PADRV3GN5G_LSB 19 +#define PHY_ANALOG_RXTX1_PADRV3GN5G_MASK 0x00780000 +#define PHY_ANALOG_RXTX1_PADRV3GN5G_GET(x) (((x) & 0x00780000) >> 19) +#define PHY_ANALOG_RXTX1_PADRV3GN5G_SET(x) (((x) << 19) & 0x00780000) +#define PHY_ANALOG_RXTX1_PADRV4GN5G_MSB 26 +#define PHY_ANALOG_RXTX1_PADRV4GN5G_LSB 23 +#define PHY_ANALOG_RXTX1_PADRV4GN5G_MASK 0x07800000 +#define PHY_ANALOG_RXTX1_PADRV4GN5G_GET(x) (((x) & 0x07800000) >> 23) +#define PHY_ANALOG_RXTX1_PADRV4GN5G_SET(x) (((x) << 23) & 0x07800000) +#define PHY_ANALOG_RXTX1_TXBB_GC_MSB 30 +#define PHY_ANALOG_RXTX1_TXBB_GC_LSB 27 +#define PHY_ANALOG_RXTX1_TXBB_GC_MASK 0x78000000 +#define PHY_ANALOG_RXTX1_TXBB_GC_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_RXTX1_TXBB_GC_SET(x) (((x) << 27) & 0x78000000) +#define PHY_ANALOG_RXTX1_MANTXGAIN_MSB 31 +#define PHY_ANALOG_RXTX1_MANTXGAIN_LSB 31 +#define PHY_ANALOG_RXTX1_MANTXGAIN_MASK 0x80000000 +#define PHY_ANALOG_RXTX1_MANTXGAIN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXTX1_MANTXGAIN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for RXTX2 */ +#define PHY_ANALOG_RXTX2_ADDRESS 0x00000104 +#define PHY_ANALOG_RXTX2_OFFSET 0x00000104 +#define PHY_ANALOG_RXTX2_BMODE_MSB 0 +#define PHY_ANALOG_RXTX2_BMODE_LSB 0 +#define PHY_ANALOG_RXTX2_BMODE_MASK 0x00000001 +#define PHY_ANALOG_RXTX2_BMODE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXTX2_BMODE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXTX2_BMODE_OVR_MSB 1 +#define PHY_ANALOG_RXTX2_BMODE_OVR_LSB 1 +#define PHY_ANALOG_RXTX2_BMODE_OVR_MASK 0x00000002 +#define PHY_ANALOG_RXTX2_BMODE_OVR_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXTX2_BMODE_OVR_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXTX2_SYNTHON_MSB 2 +#define PHY_ANALOG_RXTX2_SYNTHON_LSB 2 +#define PHY_ANALOG_RXTX2_SYNTHON_MASK 0x00000004 +#define PHY_ANALOG_RXTX2_SYNTHON_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_RXTX2_SYNTHON_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MSB 3 +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_LSB 3 +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MASK 0x00000008 +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RXTX2_BW_ST_MSB 5 +#define PHY_ANALOG_RXTX2_BW_ST_LSB 4 +#define PHY_ANALOG_RXTX2_BW_ST_MASK 0x00000030 +#define PHY_ANALOG_RXTX2_BW_ST_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_ANALOG_RXTX2_BW_ST_SET(x) (((x) << 4) & 0x00000030) +#define PHY_ANALOG_RXTX2_BW_ST_OVR_MSB 6 +#define PHY_ANALOG_RXTX2_BW_ST_OVR_LSB 6 +#define PHY_ANALOG_RXTX2_BW_ST_OVR_MASK 0x00000040 +#define PHY_ANALOG_RXTX2_BW_ST_OVR_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXTX2_BW_ST_OVR_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXTX2_TXON_MSB 7 +#define PHY_ANALOG_RXTX2_TXON_LSB 7 +#define PHY_ANALOG_RXTX2_TXON_MASK 0x00000080 +#define PHY_ANALOG_RXTX2_TXON_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXTX2_TXON_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXTX2_TXON_OVR_MSB 8 +#define PHY_ANALOG_RXTX2_TXON_OVR_LSB 8 +#define PHY_ANALOG_RXTX2_TXON_OVR_MASK 0x00000100 +#define PHY_ANALOG_RXTX2_TXON_OVR_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXTX2_TXON_OVR_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXTX2_PAON_MSB 9 +#define PHY_ANALOG_RXTX2_PAON_LSB 9 +#define PHY_ANALOG_RXTX2_PAON_MASK 0x00000200 +#define PHY_ANALOG_RXTX2_PAON_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RXTX2_PAON_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RXTX2_PAON_OVR_MSB 10 +#define PHY_ANALOG_RXTX2_PAON_OVR_LSB 10 +#define PHY_ANALOG_RXTX2_PAON_OVR_MASK 0x00000400 +#define PHY_ANALOG_RXTX2_PAON_OVR_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RXTX2_PAON_OVR_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RXTX2_RXON_MSB 11 +#define PHY_ANALOG_RXTX2_RXON_LSB 11 +#define PHY_ANALOG_RXTX2_RXON_MASK 0x00000800 +#define PHY_ANALOG_RXTX2_RXON_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_RXTX2_RXON_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_RXTX2_RXON_OVR_MSB 12 +#define PHY_ANALOG_RXTX2_RXON_OVR_LSB 12 +#define PHY_ANALOG_RXTX2_RXON_OVR_MASK 0x00001000 +#define PHY_ANALOG_RXTX2_RXON_OVR_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_RXTX2_RXON_OVR_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_RXTX2_AGCON_MSB 13 +#define PHY_ANALOG_RXTX2_AGCON_LSB 13 +#define PHY_ANALOG_RXTX2_AGCON_MASK 0x00002000 +#define PHY_ANALOG_RXTX2_AGCON_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_RXTX2_AGCON_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_RXTX2_AGCON_OVR_MSB 14 +#define PHY_ANALOG_RXTX2_AGCON_OVR_LSB 14 +#define PHY_ANALOG_RXTX2_AGCON_OVR_MASK 0x00004000 +#define PHY_ANALOG_RXTX2_AGCON_OVR_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RXTX2_AGCON_OVR_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RXTX2_TXMOD_MSB 17 +#define PHY_ANALOG_RXTX2_TXMOD_LSB 15 +#define PHY_ANALOG_RXTX2_TXMOD_MASK 0x00038000 +#define PHY_ANALOG_RXTX2_TXMOD_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_RXTX2_TXMOD_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_RXTX2_TXMOD_OVR_MSB 18 +#define PHY_ANALOG_RXTX2_TXMOD_OVR_LSB 18 +#define PHY_ANALOG_RXTX2_TXMOD_OVR_MASK 0x00040000 +#define PHY_ANALOG_RXTX2_TXMOD_OVR_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_RXTX2_TXMOD_OVR_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MSB 21 +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_LSB 19 +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MASK 0x00380000 +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MSB 23 +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_LSB 22 +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MASK 0x00c00000 +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_ANALOG_RXTX2_MXRGAIN_MSB 25 +#define PHY_ANALOG_RXTX2_MXRGAIN_LSB 24 +#define PHY_ANALOG_RXTX2_MXRGAIN_MASK 0x03000000 +#define PHY_ANALOG_RXTX2_MXRGAIN_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_ANALOG_RXTX2_MXRGAIN_SET(x) (((x) << 24) & 0x03000000) +#define PHY_ANALOG_RXTX2_VGAGAIN_MSB 28 +#define PHY_ANALOG_RXTX2_VGAGAIN_LSB 26 +#define PHY_ANALOG_RXTX2_VGAGAIN_MASK 0x1c000000 +#define PHY_ANALOG_RXTX2_VGAGAIN_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_RXTX2_VGAGAIN_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_RXTX2_LNAGAIN_MSB 31 +#define PHY_ANALOG_RXTX2_LNAGAIN_LSB 29 +#define PHY_ANALOG_RXTX2_LNAGAIN_MASK 0xe0000000 +#define PHY_ANALOG_RXTX2_LNAGAIN_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_RXTX2_LNAGAIN_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for RXTX3 */ +#define PHY_ANALOG_RXTX3_ADDRESS 0x00000108 +#define PHY_ANALOG_RXTX3_OFFSET 0x00000108 +#define PHY_ANALOG_RXTX3_SPARE3_MSB 2 +#define PHY_ANALOG_RXTX3_SPARE3_LSB 0 +#define PHY_ANALOG_RXTX3_SPARE3_MASK 0x00000007 +#define PHY_ANALOG_RXTX3_SPARE3_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_RXTX3_SPARE3_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_RXTX3_DACFULLSCALE_MSB 3 +#define PHY_ANALOG_RXTX3_DACFULLSCALE_LSB 3 +#define PHY_ANALOG_RXTX3_DACFULLSCALE_MASK 0x00000008 +#define PHY_ANALOG_RXTX3_DACFULLSCALE_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RXTX3_DACFULLSCALE_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RXTX3_DACRSTB_MSB 4 +#define PHY_ANALOG_RXTX3_DACRSTB_LSB 4 +#define PHY_ANALOG_RXTX3_DACRSTB_MASK 0x00000010 +#define PHY_ANALOG_RXTX3_DACRSTB_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RXTX3_DACRSTB_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_MSB 5 +#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_LSB 5 +#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_MASK 0x00000020 +#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_RXTX3_ADCSHORT_MSB 6 +#define PHY_ANALOG_RXTX3_ADCSHORT_LSB 6 +#define PHY_ANALOG_RXTX3_ADCSHORT_MASK 0x00000040 +#define PHY_ANALOG_RXTX3_ADCSHORT_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXTX3_ADCSHORT_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXTX3_DACPWD_MSB 7 +#define PHY_ANALOG_RXTX3_DACPWD_LSB 7 +#define PHY_ANALOG_RXTX3_DACPWD_MASK 0x00000080 +#define PHY_ANALOG_RXTX3_DACPWD_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXTX3_DACPWD_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXTX3_DACPWD_OVR_MSB 8 +#define PHY_ANALOG_RXTX3_DACPWD_OVR_LSB 8 +#define PHY_ANALOG_RXTX3_DACPWD_OVR_MASK 0x00000100 +#define PHY_ANALOG_RXTX3_DACPWD_OVR_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXTX3_DACPWD_OVR_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXTX3_ADCPWD_MSB 9 +#define PHY_ANALOG_RXTX3_ADCPWD_LSB 9 +#define PHY_ANALOG_RXTX3_ADCPWD_MASK 0x00000200 +#define PHY_ANALOG_RXTX3_ADCPWD_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RXTX3_ADCPWD_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MSB 10 +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_LSB 10 +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MASK 0x00000400 +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RXTX3_AGC_CALDAC_MSB 16 +#define PHY_ANALOG_RXTX3_AGC_CALDAC_LSB 11 +#define PHY_ANALOG_RXTX3_AGC_CALDAC_MASK 0x0001f800 +#define PHY_ANALOG_RXTX3_AGC_CALDAC_GET(x) (((x) & 0x0001f800) >> 11) +#define PHY_ANALOG_RXTX3_AGC_CALDAC_SET(x) (((x) << 11) & 0x0001f800) +#define PHY_ANALOG_RXTX3_AGC_CAL_MSB 17 +#define PHY_ANALOG_RXTX3_AGC_CAL_LSB 17 +#define PHY_ANALOG_RXTX3_AGC_CAL_MASK 0x00020000 +#define PHY_ANALOG_RXTX3_AGC_CAL_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_RXTX3_AGC_CAL_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MSB 18 +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_LSB 18 +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MASK 0x00040000 +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_RXTX3_LOFORCEDON_MSB 19 +#define PHY_ANALOG_RXTX3_LOFORCEDON_LSB 19 +#define PHY_ANALOG_RXTX3_LOFORCEDON_MASK 0x00080000 +#define PHY_ANALOG_RXTX3_LOFORCEDON_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_RXTX3_LOFORCEDON_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_RXTX3_CALRESIDUE_MSB 20 +#define PHY_ANALOG_RXTX3_CALRESIDUE_LSB 20 +#define PHY_ANALOG_RXTX3_CALRESIDUE_MASK 0x00100000 +#define PHY_ANALOG_RXTX3_CALRESIDUE_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_RXTX3_CALRESIDUE_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MSB 21 +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_LSB 21 +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MASK 0x00200000 +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_RXTX3_CALFC_MSB 22 +#define PHY_ANALOG_RXTX3_CALFC_LSB 22 +#define PHY_ANALOG_RXTX3_CALFC_MASK 0x00400000 +#define PHY_ANALOG_RXTX3_CALFC_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_RXTX3_CALFC_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_RXTX3_CALFC_OVR_MSB 23 +#define PHY_ANALOG_RXTX3_CALFC_OVR_LSB 23 +#define PHY_ANALOG_RXTX3_CALFC_OVR_MASK 0x00800000 +#define PHY_ANALOG_RXTX3_CALFC_OVR_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_RXTX3_CALFC_OVR_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_RXTX3_CALTX_MSB 24 +#define PHY_ANALOG_RXTX3_CALTX_LSB 24 +#define PHY_ANALOG_RXTX3_CALTX_MASK 0x01000000 +#define PHY_ANALOG_RXTX3_CALTX_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_RXTX3_CALTX_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_RXTX3_CALTX_OVR_MSB 25 +#define PHY_ANALOG_RXTX3_CALTX_OVR_LSB 25 +#define PHY_ANALOG_RXTX3_CALTX_OVR_MASK 0x02000000 +#define PHY_ANALOG_RXTX3_CALTX_OVR_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_RXTX3_CALTX_OVR_SET(x) (((x) << 25) & 0x02000000) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_MSB 26 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_LSB 26 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_MASK 0x04000000 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MSB 27 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_LSB 27 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MASK 0x08000000 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_RXTX3_CALPA_MSB 28 +#define PHY_ANALOG_RXTX3_CALPA_LSB 28 +#define PHY_ANALOG_RXTX3_CALPA_MASK 0x10000000 +#define PHY_ANALOG_RXTX3_CALPA_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_RXTX3_CALPA_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_RXTX3_CALPA_OVR_MSB 29 +#define PHY_ANALOG_RXTX3_CALPA_OVR_LSB 29 +#define PHY_ANALOG_RXTX3_CALPA_OVR_MASK 0x20000000 +#define PHY_ANALOG_RXTX3_CALPA_OVR_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_RXTX3_CALPA_OVR_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_RXTX3_SPURON_MSB 30 +#define PHY_ANALOG_RXTX3_SPURON_LSB 30 +#define PHY_ANALOG_RXTX3_SPURON_MASK 0x40000000 +#define PHY_ANALOG_RXTX3_SPURON_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_RXTX3_SPURON_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_RXTX3_SPURON_OVR_MSB 31 +#define PHY_ANALOG_RXTX3_SPURON_OVR_LSB 31 +#define PHY_ANALOG_RXTX3_SPURON_OVR_MASK 0x80000000 +#define PHY_ANALOG_RXTX3_SPURON_OVR_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXTX3_SPURON_OVR_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB1 */ +#define PHY_ANALOG_BB1_ADDRESS 0x00000140 +#define PHY_ANALOG_BB1_OFFSET 0x00000140 +#define PHY_ANALOG_BB1_I2V_CURR2X_MSB 0 +#define PHY_ANALOG_BB1_I2V_CURR2X_LSB 0 +#define PHY_ANALOG_BB1_I2V_CURR2X_MASK 0x00000001 +#define PHY_ANALOG_BB1_I2V_CURR2X_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_BB1_I2V_CURR2X_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_BB1_ENABLE_LOQ_MSB 1 +#define PHY_ANALOG_BB1_ENABLE_LOQ_LSB 1 +#define PHY_ANALOG_BB1_ENABLE_LOQ_MASK 0x00000002 +#define PHY_ANALOG_BB1_ENABLE_LOQ_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_BB1_ENABLE_LOQ_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_BB1_FORCE_LOQ_MSB 2 +#define PHY_ANALOG_BB1_FORCE_LOQ_LSB 2 +#define PHY_ANALOG_BB1_FORCE_LOQ_MASK 0x00000004 +#define PHY_ANALOG_BB1_FORCE_LOQ_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_BB1_FORCE_LOQ_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_BB1_ENABLE_NOTCH_MSB 3 +#define PHY_ANALOG_BB1_ENABLE_NOTCH_LSB 3 +#define PHY_ANALOG_BB1_ENABLE_NOTCH_MASK 0x00000008 +#define PHY_ANALOG_BB1_ENABLE_NOTCH_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_BB1_ENABLE_NOTCH_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_BB1_FORCE_NOTCH_MSB 4 +#define PHY_ANALOG_BB1_FORCE_NOTCH_LSB 4 +#define PHY_ANALOG_BB1_FORCE_NOTCH_MASK 0x00000010 +#define PHY_ANALOG_BB1_FORCE_NOTCH_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_BB1_FORCE_NOTCH_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MSB 5 +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_LSB 5 +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MASK 0x00000020 +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_BB1_FORCE_BIQUAD_MSB 6 +#define PHY_ANALOG_BB1_FORCE_BIQUAD_LSB 6 +#define PHY_ANALOG_BB1_FORCE_BIQUAD_MASK 0x00000040 +#define PHY_ANALOG_BB1_FORCE_BIQUAD_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_BB1_FORCE_BIQUAD_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_BB1_ENABLE_OSDAC_MSB 7 +#define PHY_ANALOG_BB1_ENABLE_OSDAC_LSB 7 +#define PHY_ANALOG_BB1_ENABLE_OSDAC_MASK 0x00000080 +#define PHY_ANALOG_BB1_ENABLE_OSDAC_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_BB1_ENABLE_OSDAC_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_BB1_FORCE_OSDAC_MSB 8 +#define PHY_ANALOG_BB1_FORCE_OSDAC_LSB 8 +#define PHY_ANALOG_BB1_FORCE_OSDAC_MASK 0x00000100 +#define PHY_ANALOG_BB1_FORCE_OSDAC_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_BB1_FORCE_OSDAC_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_BB1_ENABLE_V2I_MSB 9 +#define PHY_ANALOG_BB1_ENABLE_V2I_LSB 9 +#define PHY_ANALOG_BB1_ENABLE_V2I_MASK 0x00000200 +#define PHY_ANALOG_BB1_ENABLE_V2I_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_BB1_ENABLE_V2I_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_BB1_FORCE_V2I_MSB 10 +#define PHY_ANALOG_BB1_FORCE_V2I_LSB 10 +#define PHY_ANALOG_BB1_FORCE_V2I_MASK 0x00000400 +#define PHY_ANALOG_BB1_FORCE_V2I_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_BB1_FORCE_V2I_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_BB1_ENABLE_I2V_MSB 11 +#define PHY_ANALOG_BB1_ENABLE_I2V_LSB 11 +#define PHY_ANALOG_BB1_ENABLE_I2V_MASK 0x00000800 +#define PHY_ANALOG_BB1_ENABLE_I2V_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_BB1_ENABLE_I2V_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_BB1_FORCE_I2V_MSB 12 +#define PHY_ANALOG_BB1_FORCE_I2V_LSB 12 +#define PHY_ANALOG_BB1_FORCE_I2V_MASK 0x00001000 +#define PHY_ANALOG_BB1_FORCE_I2V_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_BB1_FORCE_I2V_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_BB1_CMSEL_MSB 15 +#define PHY_ANALOG_BB1_CMSEL_LSB 13 +#define PHY_ANALOG_BB1_CMSEL_MASK 0x0000e000 +#define PHY_ANALOG_BB1_CMSEL_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_BB1_CMSEL_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_BB1_ATBSEL_MSB 17 +#define PHY_ANALOG_BB1_ATBSEL_LSB 16 +#define PHY_ANALOG_BB1_ATBSEL_MASK 0x00030000 +#define PHY_ANALOG_BB1_ATBSEL_GET(x) (((x) & 0x00030000) >> 16) +#define PHY_ANALOG_BB1_ATBSEL_SET(x) (((x) << 16) & 0x00030000) +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MSB 18 +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_LSB 18 +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MASK 0x00040000 +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MSB 23 +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_LSB 19 +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MASK 0x00f80000 +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_GET(x) (((x) & 0x00f80000) >> 19) +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_SET(x) (((x) << 19) & 0x00f80000) +#define PHY_ANALOG_BB1_OFSTCORRI2VI_MSB 28 +#define PHY_ANALOG_BB1_OFSTCORRI2VI_LSB 24 +#define PHY_ANALOG_BB1_OFSTCORRI2VI_MASK 0x1f000000 +#define PHY_ANALOG_BB1_OFSTCORRI2VI_GET(x) (((x) & 0x1f000000) >> 24) +#define PHY_ANALOG_BB1_OFSTCORRI2VI_SET(x) (((x) << 24) & 0x1f000000) +#define PHY_ANALOG_BB1_LOCALOFFSET_MSB 29 +#define PHY_ANALOG_BB1_LOCALOFFSET_LSB 29 +#define PHY_ANALOG_BB1_LOCALOFFSET_MASK 0x20000000 +#define PHY_ANALOG_BB1_LOCALOFFSET_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_BB1_LOCALOFFSET_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_BB1_RANGE_OSDAC_MSB 31 +#define PHY_ANALOG_BB1_RANGE_OSDAC_LSB 30 +#define PHY_ANALOG_BB1_RANGE_OSDAC_MASK 0xc0000000 +#define PHY_ANALOG_BB1_RANGE_OSDAC_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_ANALOG_BB1_RANGE_OSDAC_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for BB2 */ +#define PHY_ANALOG_BB2_ADDRESS 0x00000144 +#define PHY_ANALOG_BB2_OFFSET 0x00000144 +#define PHY_ANALOG_BB2_SPARE_MSB 6 +#define PHY_ANALOG_BB2_SPARE_LSB 0 +#define PHY_ANALOG_BB2_SPARE_MASK 0x0000007f +#define PHY_ANALOG_BB2_SPARE_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_BB2_SPARE_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_BB2_SEL_TEST_MSB 9 +#define PHY_ANALOG_BB2_SEL_TEST_LSB 7 +#define PHY_ANALOG_BB2_SEL_TEST_MASK 0x00000380 +#define PHY_ANALOG_BB2_SEL_TEST_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_BB2_SEL_TEST_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_BB2_SCFIR_CAP_MSB 14 +#define PHY_ANALOG_BB2_SCFIR_CAP_LSB 10 +#define PHY_ANALOG_BB2_SCFIR_CAP_MASK 0x00007c00 +#define PHY_ANALOG_BB2_SCFIR_CAP_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_ANALOG_BB2_SCFIR_CAP_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_MSB 15 +#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_LSB 15 +#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_MASK 0x00008000 +#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_BB2_FNOTCH_MSB 19 +#define PHY_ANALOG_BB2_FNOTCH_LSB 16 +#define PHY_ANALOG_BB2_FNOTCH_MASK 0x000f0000 +#define PHY_ANALOG_BB2_FNOTCH_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_BB2_FNOTCH_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MSB 20 +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_LSB 20 +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MASK 0x00100000 +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_BB2_FILTERFC_MSB 25 +#define PHY_ANALOG_BB2_FILTERFC_LSB 21 +#define PHY_ANALOG_BB2_FILTERFC_MASK 0x03e00000 +#define PHY_ANALOG_BB2_FILTERFC_GET(x) (((x) & 0x03e00000) >> 21) +#define PHY_ANALOG_BB2_FILTERFC_SET(x) (((x) << 21) & 0x03e00000) +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MSB 26 +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_LSB 26 +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MASK 0x04000000 +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MSB 27 +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_LSB 27 +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MASK 0x08000000 +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MSB 28 +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_LSB 28 +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MASK 0x10000000 +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_BB2_RXIN2I2V_EN_MSB 29 +#define PHY_ANALOG_BB2_RXIN2I2V_EN_LSB 29 +#define PHY_ANALOG_BB2_RXIN2I2V_EN_MASK 0x20000000 +#define PHY_ANALOG_BB2_RXIN2I2V_EN_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_BB2_RXIN2I2V_EN_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_BB2_RXIN2BQ_EN_MSB 30 +#define PHY_ANALOG_BB2_RXIN2BQ_EN_LSB 30 +#define PHY_ANALOG_BB2_RXIN2BQ_EN_MASK 0x40000000 +#define PHY_ANALOG_BB2_RXIN2BQ_EN_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_BB2_RXIN2BQ_EN_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MSB 31 +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_LSB 31 +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MASK 0x80000000 +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TOP1 */ +#define PHY_ANALOG_TOP1_ADDRESS 0x00000280 +#define PHY_ANALOG_TOP1_OFFSET 0x00000280 +#define PHY_ANALOG_TOP1_SEL_KVCO_MSB 1 +#define PHY_ANALOG_TOP1_SEL_KVCO_LSB 0 +#define PHY_ANALOG_TOP1_SEL_KVCO_MASK 0x00000003 +#define PHY_ANALOG_TOP1_SEL_KVCO_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TOP1_SEL_KVCO_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TOP1_PLLATB_MSB 3 +#define PHY_ANALOG_TOP1_PLLATB_LSB 2 +#define PHY_ANALOG_TOP1_PLLATB_MASK 0x0000000c +#define PHY_ANALOG_TOP1_PLLATB_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_ANALOG_TOP1_PLLATB_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_ANALOG_TOP1_PLL_SVREG_MSB 4 +#define PHY_ANALOG_TOP1_PLL_SVREG_LSB 4 +#define PHY_ANALOG_TOP1_PLL_SVREG_MASK 0x00000010 +#define PHY_ANALOG_TOP1_PLL_SVREG_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_TOP1_PLL_SVREG_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_TOP1_HI_FREQ_EN_MSB 5 +#define PHY_ANALOG_TOP1_HI_FREQ_EN_LSB 5 +#define PHY_ANALOG_TOP1_HI_FREQ_EN_MASK 0x00000020 +#define PHY_ANALOG_TOP1_HI_FREQ_EN_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_TOP1_HI_FREQ_EN_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_TOP1_PWDPLL_MSB 6 +#define PHY_ANALOG_TOP1_PWDPLL_LSB 6 +#define PHY_ANALOG_TOP1_PWDPLL_MASK 0x00000040 +#define PHY_ANALOG_TOP1_PWDPLL_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_TOP1_PWDPLL_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_MSB 7 +#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_LSB 7 +#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_MASK 0x00000080 +#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_TOP1_ADCPWD_PHASE_MSB 9 +#define PHY_ANALOG_TOP1_ADCPWD_PHASE_LSB 8 +#define PHY_ANALOG_TOP1_ADCPWD_PHASE_MASK 0x00000300 +#define PHY_ANALOG_TOP1_ADCPWD_PHASE_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_TOP1_ADCPWD_PHASE_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_TOP1_ADCCLK_PHASE_MSB 11 +#define PHY_ANALOG_TOP1_ADCCLK_PHASE_LSB 10 +#define PHY_ANALOG_TOP1_ADCCLK_PHASE_MASK 0x00000c00 +#define PHY_ANALOG_TOP1_ADCCLK_PHASE_GET(x) (((x) & 0x00000c00) >> 10) +#define PHY_ANALOG_TOP1_ADCCLK_PHASE_SET(x) (((x) << 10) & 0x00000c00) +#define PHY_ANALOG_TOP1_DAC_CLK_SEL_MSB 13 +#define PHY_ANALOG_TOP1_DAC_CLK_SEL_LSB 12 +#define PHY_ANALOG_TOP1_DAC_CLK_SEL_MASK 0x00003000 +#define PHY_ANALOG_TOP1_DAC_CLK_SEL_GET(x) (((x) & 0x00003000) >> 12) +#define PHY_ANALOG_TOP1_DAC_CLK_SEL_SET(x) (((x) << 12) & 0x00003000) +#define PHY_ANALOG_TOP1_ADC_CLK_SEL_MSB 15 +#define PHY_ANALOG_TOP1_ADC_CLK_SEL_LSB 14 +#define PHY_ANALOG_TOP1_ADC_CLK_SEL_MASK 0x0000c000 +#define PHY_ANALOG_TOP1_ADC_CLK_SEL_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_ANALOG_TOP1_ADC_CLK_SEL_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_ANALOG_TOP1_REFDIV_MSB 19 +#define PHY_ANALOG_TOP1_REFDIV_LSB 16 +#define PHY_ANALOG_TOP1_REFDIV_MASK 0x000f0000 +#define PHY_ANALOG_TOP1_REFDIV_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_TOP1_REFDIV_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_ANALOG_TOP1_DIV_MSB 29 +#define PHY_ANALOG_TOP1_DIV_LSB 20 +#define PHY_ANALOG_TOP1_DIV_MASK 0x3ff00000 +#define PHY_ANALOG_TOP1_DIV_GET(x) (((x) & 0x3ff00000) >> 20) +#define PHY_ANALOG_TOP1_DIV_SET(x) (((x) << 20) & 0x3ff00000) +#define PHY_ANALOG_TOP1_PLLBYPASS_MSB 30 +#define PHY_ANALOG_TOP1_PLLBYPASS_LSB 30 +#define PHY_ANALOG_TOP1_PLLBYPASS_MASK 0x40000000 +#define PHY_ANALOG_TOP1_PLLBYPASS_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_TOP1_PLLBYPASS_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_TOP1_CLKMOD_RSTB_MSB 31 +#define PHY_ANALOG_TOP1_CLKMOD_RSTB_LSB 31 +#define PHY_ANALOG_TOP1_CLKMOD_RSTB_MASK 0x80000000 +#define PHY_ANALOG_TOP1_CLKMOD_RSTB_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TOP1_CLKMOD_RSTB_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TOP2 */ +#define PHY_ANALOG_TOP2_ADDRESS 0x00000284 +#define PHY_ANALOG_TOP2_OFFSET 0x00000284 +#define PHY_ANALOG_TOP2_PLL_LOWLEAK_MSB 0 +#define PHY_ANALOG_TOP2_PLL_LOWLEAK_LSB 0 +#define PHY_ANALOG_TOP2_PLL_LOWLEAK_MASK 0x00000001 +#define PHY_ANALOG_TOP2_PLL_LOWLEAK_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TOP2_PLL_LOWLEAK_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TOP2_PLL_LEAK_MSB 4 +#define PHY_ANALOG_TOP2_PLL_LEAK_LSB 1 +#define PHY_ANALOG_TOP2_PLL_LEAK_MASK 0x0000001e +#define PHY_ANALOG_TOP2_PLL_LEAK_GET(x) (((x) & 0x0000001e) >> 1) +#define PHY_ANALOG_TOP2_PLL_LEAK_SET(x) (((x) << 1) & 0x0000001e) +#define PHY_ANALOG_TOP2_PLLFRAC_MSB 19 +#define PHY_ANALOG_TOP2_PLLFRAC_LSB 5 +#define PHY_ANALOG_TOP2_PLLFRAC_MASK 0x000fffe0 +#define PHY_ANALOG_TOP2_PLLFRAC_GET(x) (((x) & 0x000fffe0) >> 5) +#define PHY_ANALOG_TOP2_PLLFRAC_SET(x) (((x) << 5) & 0x000fffe0) +#define PHY_ANALOG_TOP2_PWD_PLLSDM_MSB 20 +#define PHY_ANALOG_TOP2_PWD_PLLSDM_LSB 20 +#define PHY_ANALOG_TOP2_PWD_PLLSDM_MASK 0x00100000 +#define PHY_ANALOG_TOP2_PWD_PLLSDM_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TOP2_PWD_PLLSDM_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TOP2_PLLICP_MSB 23 +#define PHY_ANALOG_TOP2_PLLICP_LSB 21 +#define PHY_ANALOG_TOP2_PLLICP_MASK 0x00e00000 +#define PHY_ANALOG_TOP2_PLLICP_GET(x) (((x) & 0x00e00000) >> 21) +#define PHY_ANALOG_TOP2_PLLICP_SET(x) (((x) << 21) & 0x00e00000) +#define PHY_ANALOG_TOP2_PLLFILTER_MSB 31 +#define PHY_ANALOG_TOP2_PLLFILTER_LSB 24 +#define PHY_ANALOG_TOP2_PLLFILTER_MASK 0xff000000 +#define PHY_ANALOG_TOP2_PLLFILTER_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_ANALOG_TOP2_PLLFILTER_SET(x) (((x) << 24) & 0xff000000) + +/* macros for TOP3 */ +#define PHY_ANALOG_TOP3_ADDRESS 0x00000288 +#define PHY_ANALOG_TOP3_OFFSET 0x00000288 +#define PHY_ANALOG_TOP3_INT2GND_MSB 0 +#define PHY_ANALOG_TOP3_INT2GND_LSB 0 +#define PHY_ANALOG_TOP3_INT2GND_MASK 0x00000001 +#define PHY_ANALOG_TOP3_INT2GND_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TOP3_INT2GND_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TOP3_PWDPALCLK_MSB 1 +#define PHY_ANALOG_TOP3_PWDPALCLK_LSB 1 +#define PHY_ANALOG_TOP3_PWDPALCLK_MASK 0x00000002 +#define PHY_ANALOG_TOP3_PWDPALCLK_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_TOP3_PWDPALCLK_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_TOP3_PWDAGCCLK_MSB 2 +#define PHY_ANALOG_TOP3_PWDAGCCLK_LSB 2 +#define PHY_ANALOG_TOP3_PWDAGCCLK_MASK 0x00000004 +#define PHY_ANALOG_TOP3_PWDAGCCLK_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_TOP3_PWDAGCCLK_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_TOP3_PWDV2I_MSB 3 +#define PHY_ANALOG_TOP3_PWDV2I_LSB 3 +#define PHY_ANALOG_TOP3_PWDV2I_MASK 0x00000008 +#define PHY_ANALOG_TOP3_PWDV2I_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_TOP3_PWDV2I_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_TOP3_PWDBIAS_MSB 4 +#define PHY_ANALOG_TOP3_PWDBIAS_LSB 4 +#define PHY_ANALOG_TOP3_PWDBIAS_MASK 0x00000010 +#define PHY_ANALOG_TOP3_PWDBIAS_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_TOP3_PWDBIAS_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_TOP3_PWDBG_MSB 5 +#define PHY_ANALOG_TOP3_PWDBG_LSB 5 +#define PHY_ANALOG_TOP3_PWDBG_MASK 0x00000020 +#define PHY_ANALOG_TOP3_PWDBG_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_TOP3_PWDBG_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_TOP3_XTAL_SELVREG_MSB 6 +#define PHY_ANALOG_TOP3_XTAL_SELVREG_LSB 6 +#define PHY_ANALOG_TOP3_XTAL_SELVREG_MASK 0x00000040 +#define PHY_ANALOG_TOP3_XTAL_SELVREG_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_TOP3_XTAL_SELVREG_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_TOP3_XTAL_PWDREG_MSB 7 +#define PHY_ANALOG_TOP3_XTAL_PWDREG_LSB 7 +#define PHY_ANALOG_TOP3_XTAL_PWDREG_MASK 0x00000080 +#define PHY_ANALOG_TOP3_XTAL_PWDREG_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_TOP3_XTAL_PWDREG_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_MSB 8 +#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_LSB 8 +#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_MASK 0x00000100 +#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_MSB 9 +#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_LSB 9 +#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_MASK 0x00000200 +#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_TOP3_XTAL_OSCON_MSB 10 +#define PHY_ANALOG_TOP3_XTAL_OSCON_LSB 10 +#define PHY_ANALOG_TOP3_XTAL_OSCON_MASK 0x00000400 +#define PHY_ANALOG_TOP3_XTAL_OSCON_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_TOP3_XTAL_OSCON_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_MSB 11 +#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_LSB 11 +#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_MASK 0x00000800 +#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_MSB 12 +#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_LSB 12 +#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_MASK 0x00001000 +#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_TOP3_XTAL_HIGHZ_MSB 13 +#define PHY_ANALOG_TOP3_XTAL_HIGHZ_LSB 13 +#define PHY_ANALOG_TOP3_XTAL_HIGHZ_MASK 0x00002000 +#define PHY_ANALOG_TOP3_XTAL_HIGHZ_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_TOP3_XTAL_HIGHZ_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_TOP3_XTAL_DRVPNR_MSB 15 +#define PHY_ANALOG_TOP3_XTAL_DRVPNR_LSB 14 +#define PHY_ANALOG_TOP3_XTAL_DRVPNR_MASK 0x0000c000 +#define PHY_ANALOG_TOP3_XTAL_DRVPNR_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_ANALOG_TOP3_XTAL_DRVPNR_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_MSB 22 +#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_LSB 16 +#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_MASK 0x007f0000 +#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_GET(x) (((x) & 0x007f0000) >> 16) +#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_SET(x) (((x) << 16) & 0x007f0000) +#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_MSB 29 +#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_LSB 23 +#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_MASK 0x3f800000 +#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_GET(x) (((x) & 0x3f800000) >> 23) +#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_SET(x) (((x) << 23) & 0x3f800000) +#define PHY_ANALOG_TOP3_XTAL_BIAS2X_MSB 30 +#define PHY_ANALOG_TOP3_XTAL_BIAS2X_LSB 30 +#define PHY_ANALOG_TOP3_XTAL_BIAS2X_MASK 0x40000000 +#define PHY_ANALOG_TOP3_XTAL_BIAS2X_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_TOP3_XTAL_BIAS2X_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_TOP3_TCXODET_MSB 31 +#define PHY_ANALOG_TOP3_TCXODET_LSB 31 +#define PHY_ANALOG_TOP3_TCXODET_MASK 0x80000000 +#define PHY_ANALOG_TOP3_TCXODET_GET(x) (((x) & 0x80000000) >> 31) + +/* macros for TOP4 */ +#define PHY_ANALOG_TOP4_ADDRESS 0x0000028c +#define PHY_ANALOG_TOP4_OFFSET 0x0000028c +#define PHY_ANALOG_TOP4_SPARE4_MSB 19 +#define PHY_ANALOG_TOP4_SPARE4_LSB 0 +#define PHY_ANALOG_TOP4_SPARE4_MASK 0x000fffff +#define PHY_ANALOG_TOP4_SPARE4_GET(x) (((x) & 0x000fffff) >> 0) +#define PHY_ANALOG_TOP4_SPARE4_SET(x) (((x) << 0) & 0x000fffff) +#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_MSB 20 +#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_LSB 20 +#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_MASK 0x00100000 +#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TOP4_ADCPWD_OVR_MSB 21 +#define PHY_ANALOG_TOP4_ADCPWD_OVR_LSB 21 +#define PHY_ANALOG_TOP4_ADCPWD_OVR_MASK 0x00200000 +#define PHY_ANALOG_TOP4_ADCPWD_OVR_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_TOP4_ADCPWD_OVR_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_TOP4_ADCPWD_INT_MSB 22 +#define PHY_ANALOG_TOP4_ADCPWD_INT_LSB 22 +#define PHY_ANALOG_TOP4_ADCPWD_INT_MASK 0x00400000 +#define PHY_ANALOG_TOP4_ADCPWD_INT_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_TOP4_ADCPWD_INT_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_TOP4_TESTIQ_OFF_MSB 23 +#define PHY_ANALOG_TOP4_TESTIQ_OFF_LSB 23 +#define PHY_ANALOG_TOP4_TESTIQ_OFF_MASK 0x00800000 +#define PHY_ANALOG_TOP4_TESTIQ_OFF_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_TOP4_TESTIQ_OFF_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_MSB 24 +#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_LSB 24 +#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_MASK 0x01000000 +#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_MSB 25 +#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_LSB 25 +#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_MASK 0x02000000 +#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_SET(x) (((x) << 25) & 0x02000000) +#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_MSB 26 +#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_LSB 26 +#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_MASK 0x04000000 +#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_TOP4_ENBTCLK_MSB 27 +#define PHY_ANALOG_TOP4_ENBTCLK_LSB 27 +#define PHY_ANALOG_TOP4_ENBTCLK_MASK 0x08000000 +#define PHY_ANALOG_TOP4_ENBTCLK_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_TOP4_ENBTCLK_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_TOP4_PAD2GND_MSB 28 +#define PHY_ANALOG_TOP4_PAD2GND_LSB 28 +#define PHY_ANALOG_TOP4_PAD2GND_MASK 0x10000000 +#define PHY_ANALOG_TOP4_PAD2GND_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_TOP4_PAD2GND_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_TOP4_INTH2PAD_MSB 29 +#define PHY_ANALOG_TOP4_INTH2PAD_LSB 29 +#define PHY_ANALOG_TOP4_INTH2PAD_MASK 0x20000000 +#define PHY_ANALOG_TOP4_INTH2PAD_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_TOP4_INTH2PAD_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_TOP4_INTH2GND_MSB 30 +#define PHY_ANALOG_TOP4_INTH2GND_LSB 30 +#define PHY_ANALOG_TOP4_INTH2GND_MASK 0x40000000 +#define PHY_ANALOG_TOP4_INTH2GND_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_TOP4_INTH2GND_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_TOP4_INT2PAD_MSB 31 +#define PHY_ANALOG_TOP4_INT2PAD_LSB 31 +#define PHY_ANALOG_TOP4_INT2PAD_MASK 0x80000000 +#define PHY_ANALOG_TOP4_INT2PAD_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TOP4_INT2PAD_SET(x) (((x) << 31) & 0x80000000) + +/* macros for rbist_cntrl */ +#define PHY_ANALOG_RBIST_CNTRL_ADDRESS 0x00000380 +#define PHY_ANALOG_RBIST_CNTRL_OFFSET 0x00000380 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MSB 0 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_LSB 0 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MASK 0x00000001 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MSB 1 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_LSB 1 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MASK 0x00000002 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MSB 2 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_LSB 2 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MASK 0x00000004 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MSB 3 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_LSB 3 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MASK 0x00000008 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MSB 4 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_LSB 4 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MASK 0x00000010 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MSB 5 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_LSB 5 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MASK 0x00000020 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MSB 6 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_LSB 6 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MASK 0x00000040 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MSB 7 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_LSB 7 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MASK 0x00000080 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MSB 8 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_LSB 8 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MASK 0x00000100 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MSB 9 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_LSB 9 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MASK 0x00000200 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MSB 10 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_LSB 10 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MASK 0x00000400 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MSB 11 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_LSB 11 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MASK 0x00000800 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MSB 12 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_LSB 12 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MASK 0x00001000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MSB 13 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_LSB 13 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MASK 0x00002000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MSB 14 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_LSB 14 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MASK 0x00004000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MSB 15 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_LSB 15 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MASK 0x00008000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MSB 16 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_LSB 16 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MASK 0x00010000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MSB 17 +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_LSB 17 +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MASK 0x00020000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_SET(x) (((x) << 17) & 0x00020000) + +/* macros for tx_dc_offset */ +#define PHY_ANALOG_TX_DC_OFFSET_ADDRESS 0x00000384 +#define PHY_ANALOG_TX_DC_OFFSET_OFFSET 0x00000384 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MSB 10 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_LSB 0 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MASK 0x000007ff +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MSB 26 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_LSB 16 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MASK 0x07ff0000 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_GET(x) (((x) & 0x07ff0000) >> 16) +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_SET(x) (((x) << 16) & 0x07ff0000) + +/* macros for tx_tonegen0 */ +#define PHY_ANALOG_TX_TONEGEN0_ADDRESS 0x00000388 +#define PHY_ANALOG_TX_TONEGEN0_OFFSET 0x00000388 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for tx_tonegen1 */ +#define PHY_ANALOG_TX_TONEGEN1_ADDRESS 0x0000038c +#define PHY_ANALOG_TX_TONEGEN1_OFFSET 0x0000038c +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MSB 6 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_LSB 0 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MSB 11 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_LSB 8 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MSB 23 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_LSB 16 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MSB 30 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_LSB 24 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for tx_lftonegen0 */ +#define PHY_ANALOG_TX_LFTONEGEN0_ADDRESS 0x00000390 +#define PHY_ANALOG_TX_LFTONEGEN0_OFFSET 0x00000390 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for tx_linear_ramp_i */ +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ADDRESS 0x00000394 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_OFFSET 0x00000394 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MSB 10 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_LSB 0 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MSB 21 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_LSB 12 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MSB 29 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_LSB 24 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for tx_linear_ramp_q */ +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ADDRESS 0x00000398 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_OFFSET 0x00000398 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MSB 10 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_LSB 0 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MSB 21 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_LSB 12 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MSB 29 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_LSB 24 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for tx_prbs_mag */ +#define PHY_ANALOG_TX_PRBS_MAG_ADDRESS 0x0000039c +#define PHY_ANALOG_TX_PRBS_MAG_OFFSET 0x0000039c +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MSB 9 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_LSB 0 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MASK 0x000003ff +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MSB 25 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_LSB 16 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MASK 0x03ff0000 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_GET(x) (((x) & 0x03ff0000) >> 16) +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_SET(x) (((x) << 16) & 0x03ff0000) + +/* macros for tx_prbs_seed_i */ +#define PHY_ANALOG_TX_PRBS_SEED_I_ADDRESS 0x000003a0 +#define PHY_ANALOG_TX_PRBS_SEED_I_OFFSET 0x000003a0 +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MSB 30 +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_LSB 0 +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0) +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff) + +/* macros for tx_prbs_seed_q */ +#define PHY_ANALOG_TX_PRBS_SEED_Q_ADDRESS 0x000003a4 +#define PHY_ANALOG_TX_PRBS_SEED_Q_OFFSET 0x000003a4 +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MSB 30 +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_LSB 0 +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0) +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff) + +/* macros for cmac_dc_cancel */ +#define PHY_ANALOG_CMAC_DC_CANCEL_ADDRESS 0x000003a8 +#define PHY_ANALOG_CMAC_DC_CANCEL_OFFSET 0x000003a8 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MSB 9 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_LSB 0 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MASK 0x000003ff +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MSB 25 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_LSB 16 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MASK 0x03ff0000 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_GET(x) (((x) & 0x03ff0000) >> 16) +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_SET(x) (((x) << 16) & 0x03ff0000) + +/* macros for cmac_dc_offset */ +#define PHY_ANALOG_CMAC_DC_OFFSET_ADDRESS 0x000003ac +#define PHY_ANALOG_CMAC_DC_OFFSET_OFFSET 0x000003ac +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_corr */ +#define PHY_ANALOG_CMAC_CORR_ADDRESS 0x000003b0 +#define PHY_ANALOG_CMAC_CORR_OFFSET 0x000003b0 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MSB 4 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MASK 0x0000001f +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MSB 13 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_LSB 8 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MASK 0x00003f00 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_SET(x) (((x) << 8) & 0x00003f00) + +/* macros for cmac_power */ +#define PHY_ANALOG_CMAC_POWER_ADDRESS 0x000003b4 +#define PHY_ANALOG_CMAC_POWER_OFFSET 0x000003b4 +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_cross_corr */ +#define PHY_ANALOG_CMAC_CROSS_CORR_ADDRESS 0x000003b8 +#define PHY_ANALOG_CMAC_CROSS_CORR_OFFSET 0x000003b8 +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_i2q2 */ +#define PHY_ANALOG_CMAC_I2Q2_ADDRESS 0x000003bc +#define PHY_ANALOG_CMAC_I2Q2_OFFSET 0x000003bc +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_power_hpf */ +#define PHY_ANALOG_CMAC_POWER_HPF_ADDRESS 0x000003c0 +#define PHY_ANALOG_CMAC_POWER_HPF_OFFSET 0x000003c0 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MSB 7 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_LSB 4 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MASK 0x000000f0 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_SET(x) (((x) << 4) & 0x000000f0) + +/* macros for rxdac_set1 */ +#define PHY_ANALOG_RXDAC_SET1_ADDRESS 0x000003c4 +#define PHY_ANALOG_RXDAC_SET1_OFFSET 0x000003c4 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MSB 1 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_LSB 0 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MASK 0x00000003 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MSB 4 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_LSB 4 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MASK 0x00000010 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MSB 13 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_LSB 8 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MASK 0x00003f00 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MSB 19 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_LSB 16 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MASK 0x000f0000 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_SET(x) (((x) << 16) & 0x000f0000) + +/* macros for rxdac_set2 */ +#define PHY_ANALOG_RXDAC_SET2_ADDRESS 0x000003c8 +#define PHY_ANALOG_RXDAC_SET2_OFFSET 0x000003c8 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MSB 4 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_LSB 0 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MASK 0x0000001f +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MSB 12 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_LSB 8 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MASK 0x00001f00 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_SET(x) (((x) << 8) & 0x00001f00) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MSB 20 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_LSB 16 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MASK 0x001f0000 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MSB 28 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_LSB 24 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MASK 0x1f000000 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_GET(x) (((x) & 0x1f000000) >> 24) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_SET(x) (((x) << 24) & 0x1f000000) + +/* macros for rxdac_long_shift */ +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ADDRESS 0x000003cc +#define PHY_ANALOG_RXDAC_LONG_SHIFT_OFFSET 0x000003cc +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MSB 4 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_LSB 0 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MASK 0x0000001f +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MSB 12 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_LSB 8 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MASK 0x00001f00 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_SET(x) (((x) << 8) & 0x00001f00) + +/* macros for cmac_results_i */ +#define PHY_ANALOG_CMAC_RESULTS_I_ADDRESS 0x000003d0 +#define PHY_ANALOG_CMAC_RESULTS_I_OFFSET 0x000003d0 +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MSB 31 +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_LSB 0 +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MASK 0xffffffff +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for cmac_results_q */ +#define PHY_ANALOG_CMAC_RESULTS_Q_ADDRESS 0x000003d4 +#define PHY_ANALOG_CMAC_RESULTS_Q_OFFSET 0x000003d4 +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MSB 31 +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_LSB 0 +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MASK 0xffffffff +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for PMU1 */ +#define PHY_ANALOG_PMU1_ADDRESS 0x00000740 +#define PHY_ANALOG_PMU1_OFFSET 0x00000740 +#define PHY_ANALOG_PMU1_SPARE_MSB 10 +#define PHY_ANALOG_PMU1_SPARE_LSB 0 +#define PHY_ANALOG_PMU1_SPARE_MASK 0x000007ff +#define PHY_ANALOG_PMU1_SPARE_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_PMU1_SPARE_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_PMU1_OTP_V25_PWD_MSB 11 +#define PHY_ANALOG_PMU1_OTP_V25_PWD_LSB 11 +#define PHY_ANALOG_PMU1_OTP_V25_PWD_MASK 0x00000800 +#define PHY_ANALOG_PMU1_OTP_V25_PWD_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_PMU1_OTP_V25_PWD_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_PMU1_PAREGON_MAN_MSB 12 +#define PHY_ANALOG_PMU1_PAREGON_MAN_LSB 12 +#define PHY_ANALOG_PMU1_PAREGON_MAN_MASK 0x00001000 +#define PHY_ANALOG_PMU1_PAREGON_MAN_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_PMU1_PAREGON_MAN_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_PMU1_OTPREGON_MAN_MSB 13 +#define PHY_ANALOG_PMU1_OTPREGON_MAN_LSB 13 +#define PHY_ANALOG_PMU1_OTPREGON_MAN_MASK 0x00002000 +#define PHY_ANALOG_PMU1_OTPREGON_MAN_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_PMU1_OTPREGON_MAN_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_PMU1_DREGON_MAN_MSB 14 +#define PHY_ANALOG_PMU1_DREGON_MAN_LSB 14 +#define PHY_ANALOG_PMU1_DREGON_MAN_MASK 0x00004000 +#define PHY_ANALOG_PMU1_DREGON_MAN_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_PMU1_DREGON_MAN_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_PMU1_DISCONTMODEEN_MSB 15 +#define PHY_ANALOG_PMU1_DISCONTMODEEN_LSB 15 +#define PHY_ANALOG_PMU1_DISCONTMODEEN_MASK 0x00008000 +#define PHY_ANALOG_PMU1_DISCONTMODEEN_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_PMU1_DISCONTMODEEN_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_PMU1_SWREGON_MAN_MSB 16 +#define PHY_ANALOG_PMU1_SWREGON_MAN_LSB 16 +#define PHY_ANALOG_PMU1_SWREGON_MAN_MASK 0x00010000 +#define PHY_ANALOG_PMU1_SWREGON_MAN_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_PMU1_SWREGON_MAN_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MSB 18 +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_LSB 17 +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MASK 0x00060000 +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_GET(x) (((x) & 0x00060000) >> 17) +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_SET(x) (((x) << 17) & 0x00060000) +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MSB 21 +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_LSB 19 +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MASK 0x00380000 +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MSB 23 +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_LSB 22 +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MASK 0x00c00000 +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_ANALOG_PMU1_SREG_LVLCTR_MSB 25 +#define PHY_ANALOG_PMU1_SREG_LVLCTR_LSB 24 +#define PHY_ANALOG_PMU1_SREG_LVLCTR_MASK 0x03000000 +#define PHY_ANALOG_PMU1_SREG_LVLCTR_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_ANALOG_PMU1_SREG_LVLCTR_SET(x) (((x) << 24) & 0x03000000) +#define PHY_ANALOG_PMU1_DREG_LVLCTR_MSB 27 +#define PHY_ANALOG_PMU1_DREG_LVLCTR_LSB 26 +#define PHY_ANALOG_PMU1_DREG_LVLCTR_MASK 0x0c000000 +#define PHY_ANALOG_PMU1_DREG_LVLCTR_GET(x) (((x) & 0x0c000000) >> 26) +#define PHY_ANALOG_PMU1_DREG_LVLCTR_SET(x) (((x) << 26) & 0x0c000000) +#define PHY_ANALOG_PMU1_PAREG_XPNP_MSB 28 +#define PHY_ANALOG_PMU1_PAREG_XPNP_LSB 28 +#define PHY_ANALOG_PMU1_PAREG_XPNP_MASK 0x10000000 +#define PHY_ANALOG_PMU1_PAREG_XPNP_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_PMU1_PAREG_XPNP_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MSB 31 +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_LSB 29 +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MASK 0xe0000000 +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for PMU2 */ +#define PHY_ANALOG_PMU2_ADDRESS 0x00000744 +#define PHY_ANALOG_PMU2_OFFSET 0x00000744 +#define PHY_ANALOG_PMU2_SPARE_MSB 7 +#define PHY_ANALOG_PMU2_SPARE_LSB 0 +#define PHY_ANALOG_PMU2_SPARE_MASK 0x000000ff +#define PHY_ANALOG_PMU2_SPARE_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_ANALOG_PMU2_SPARE_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MSB 8 +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_LSB 8 +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MASK 0x00000100 +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MSB 9 +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_LSB 9 +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MASK 0x00000200 +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MSB 10 +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_LSB 10 +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MASK 0x00000400 +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MSB 11 +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_LSB 11 +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MASK 0x00000800 +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MSB 12 +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_LSB 12 +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MASK 0x00001000 +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MSB 13 +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_LSB 13 +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MASK 0x00002000 +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MSB 14 +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_LSB 14 +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MASK 0x00004000 +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MSB 15 +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_LSB 15 +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MASK 0x00008000 +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MSB 16 +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_LSB 16 +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MASK 0x00010000 +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MSB 18 +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_LSB 17 +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MASK 0x00060000 +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_GET(x) (((x) & 0x00060000) >> 17) +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_SET(x) (((x) << 17) & 0x00060000) +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MSB 19 +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_LSB 19 +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MASK 0x00080000 +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MSB 21 +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_LSB 20 +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MASK 0x00300000 +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_GET(x) (((x) & 0x00300000) >> 20) +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_SET(x) (((x) << 20) & 0x00300000) +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MSB 22 +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_LSB 22 +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MASK 0x00400000 +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MSB 24 +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_LSB 23 +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MASK 0x01800000 +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_GET(x) (((x) & 0x01800000) >> 23) +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_SET(x) (((x) << 23) & 0x01800000) +#define PHY_ANALOG_PMU2_SWREG2ATB_MSB 27 +#define PHY_ANALOG_PMU2_SWREG2ATB_LSB 25 +#define PHY_ANALOG_PMU2_SWREG2ATB_MASK 0x0e000000 +#define PHY_ANALOG_PMU2_SWREG2ATB_GET(x) (((x) & 0x0e000000) >> 25) +#define PHY_ANALOG_PMU2_SWREG2ATB_SET(x) (((x) << 25) & 0x0e000000) +#define PHY_ANALOG_PMU2_OTPREG2ATB_MSB 28 +#define PHY_ANALOG_PMU2_OTPREG2ATB_LSB 28 +#define PHY_ANALOG_PMU2_OTPREG2ATB_MASK 0x10000000 +#define PHY_ANALOG_PMU2_OTPREG2ATB_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_PMU2_OTPREG2ATB_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MSB 30 +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_LSB 29 +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MASK 0x60000000 +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_SET(x) (((x) << 29) & 0x60000000) +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MSB 31 +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_LSB 31 +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MASK 0x80000000 +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_SET(x) (((x) << 31) & 0x80000000) + + +#ifndef __ASSEMBLER__ + +typedef struct analog_intf_ares_reg_reg_s { + volatile unsigned int RXRF_BIAS1; /* 0x0 - 0x4 */ + volatile unsigned int RXRF_BIAS2; /* 0x4 - 0x8 */ + volatile unsigned int RXRF_GAINSTAGES; /* 0x8 - 0xc */ + volatile unsigned int RXRF_AGC; /* 0xc - 0x10 */ + volatile char pad__0[0x30]; /* 0x10 - 0x40 */ + volatile unsigned int TXRF1; /* 0x40 - 0x44 */ + volatile unsigned int TXRF2; /* 0x44 - 0x48 */ + volatile unsigned int TXRF3; /* 0x48 - 0x4c */ + volatile unsigned int TXRF4; /* 0x4c - 0x50 */ + volatile unsigned int TXRF5; /* 0x50 - 0x54 */ + volatile unsigned int TXRF6; /* 0x54 - 0x58 */ + volatile unsigned int TXRF7; /* 0x58 - 0x5c */ + volatile unsigned int TXRF8; /* 0x5c - 0x60 */ + volatile unsigned int TXRF9; /* 0x60 - 0x64 */ + volatile unsigned int TXRF10; /* 0x64 - 0x68 */ + volatile unsigned int TXRF11; /* 0x68 - 0x6c */ + volatile unsigned int TXRF12; /* 0x6c - 0x70 */ + volatile char pad__1[0x10]; /* 0x70 - 0x80 */ + volatile unsigned int SYNTH1; /* 0x80 - 0x84 */ + volatile unsigned int SYNTH2; /* 0x84 - 0x88 */ + volatile unsigned int SYNTH3; /* 0x88 - 0x8c */ + volatile unsigned int SYNTH4; /* 0x8c - 0x90 */ + volatile unsigned int SYNTH5; /* 0x90 - 0x94 */ + volatile unsigned int SYNTH6; /* 0x94 - 0x98 */ + volatile unsigned int SYNTH7; /* 0x98 - 0x9c */ + volatile unsigned int SYNTH8; /* 0x9c - 0xa0 */ + volatile unsigned int SYNTH9; /* 0xa0 - 0xa4 */ + volatile unsigned int SYNTH10; /* 0xa4 - 0xa8 */ + volatile unsigned int SYNTH11; /* 0xa8 - 0xac */ + volatile unsigned int SYNTH12; /* 0xac - 0xb0 */ + volatile char pad__2[0x10]; /* 0xb0 - 0xc0 */ + volatile unsigned int BIAS1; /* 0xc0 - 0xc4 */ + volatile unsigned int BIAS2; /* 0xc4 - 0xc8 */ + volatile unsigned int BIAS3; /* 0xc8 - 0xcc */ + volatile unsigned int BIAS4; /* 0xcc - 0xd0 */ + volatile char pad__3[0x30]; /* 0xd0 - 0x100 */ + volatile unsigned int RXTX1; /* 0x100 - 0x104 */ + volatile unsigned int RXTX2; /* 0x104 - 0x108 */ + volatile unsigned int RXTX3; /* 0x108 - 0x10c */ + volatile char pad__4[0x34]; /* 0x10c - 0x140 */ + volatile unsigned int BB1; /* 0x140 - 0x144 */ + volatile unsigned int BB2; /* 0x144 - 0x148 */ + volatile char pad__5[0x138]; /* 0x148 - 0x280 */ + volatile unsigned int TOP1; /* 0x280 - 0x284 */ + volatile unsigned int TOP2; /* 0x284 - 0x288 */ + volatile unsigned int TOP3; /* 0x288 - 0x28c */ + volatile unsigned int TOP4; /* 0x28c - 0x290 */ + volatile char pad__6[0xf0]; /* 0x290 - 0x380 */ + volatile unsigned int rbist_cntrl; /* 0x380 - 0x384 */ + volatile unsigned int tx_dc_offset; /* 0x384 - 0x388 */ + volatile unsigned int tx_tonegen0; /* 0x388 - 0x38c */ + volatile unsigned int tx_tonegen1; /* 0x38c - 0x390 */ + volatile unsigned int tx_lftonegen0; /* 0x390 - 0x394 */ + volatile unsigned int tx_linear_ramp_i; /* 0x394 - 0x398 */ + volatile unsigned int tx_linear_ramp_q; /* 0x398 - 0x39c */ + volatile unsigned int tx_prbs_mag; /* 0x39c - 0x3a0 */ + volatile unsigned int tx_prbs_seed_i; /* 0x3a0 - 0x3a4 */ + volatile unsigned int tx_prbs_seed_q; /* 0x3a4 - 0x3a8 */ + volatile unsigned int cmac_dc_cancel; /* 0x3a8 - 0x3ac */ + volatile unsigned int cmac_dc_offset; /* 0x3ac - 0x3b0 */ + volatile unsigned int cmac_corr; /* 0x3b0 - 0x3b4 */ + volatile unsigned int cmac_power; /* 0x3b4 - 0x3b8 */ + volatile unsigned int cmac_cross_corr; /* 0x3b8 - 0x3bc */ + volatile unsigned int cmac_i2q2; /* 0x3bc - 0x3c0 */ + volatile unsigned int cmac_power_hpf; /* 0x3c0 - 0x3c4 */ + volatile unsigned int rxdac_set1; /* 0x3c4 - 0x3c8 */ + volatile unsigned int rxdac_set2; /* 0x3c8 - 0x3cc */ + volatile unsigned int rxdac_long_shift; /* 0x3cc - 0x3d0 */ + volatile unsigned int cmac_results_i; /* 0x3d0 - 0x3d4 */ + volatile unsigned int cmac_results_q; /* 0x3d4 - 0x3d8 */ + volatile char pad__7[0x368]; /* 0x3d8 - 0x740 */ + volatile unsigned int PMU1; /* 0x740 - 0x744 */ + volatile unsigned int PMU2; /* 0x744 - 0x748 */ +} analog_intf_ares_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _ANALOG_INTF_ARES_REG_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h new file mode 100644 index 000000000000..1c243fbbc810 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h @@ -0,0 +1,3674 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + +/* Copyright (C) 2009 Denali Software Inc. All rights reserved */ +/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */ + + +#ifndef _ANALOG_INTF_ATHR_WLAN_REG_REG_H_ +#define _ANALOG_INTF_ATHR_WLAN_REG_REG_H_ + + +/* macros for RXRF_BIAS1 */ +#define PHY_ANALOG_RXRF_BIAS1_ADDRESS 0x00000000 +#define PHY_ANALOG_RXRF_BIAS1_OFFSET 0x00000000 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_MSB 0 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_MASK 0x00000001 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_BIAS1_SPARE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MSB 3 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_LSB 1 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MASK 0x0000000e +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MSB 6 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_LSB 4 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MASK 0x00000070 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_GET(x) (((x) & 0x00000070) >> 4) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_SET(x) (((x) << 4) & 0x00000070) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MSB 9 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_LSB 7 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MASK 0x00000380 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MSB 12 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_LSB 10 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MASK 0x00001c00 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_GET(x) (((x) & 0x00001c00) >> 10) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_SET(x) (((x) << 10) & 0x00001c00) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MSB 15 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_LSB 13 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MASK 0x0000e000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MSB 18 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_LSB 16 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MASK 0x00070000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_SET(x) (((x) << 16) & 0x00070000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MSB 21 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_LSB 19 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MASK 0x00380000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MSB 24 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_LSB 22 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MASK 0x01c00000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_GET(x) (((x) & 0x01c00000) >> 22) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_SET(x) (((x) << 22) & 0x01c00000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MSB 27 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_LSB 25 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MASK 0x0e000000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_GET(x) (((x) & 0x0e000000) >> 25) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_SET(x) (((x) << 25) & 0x0e000000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MSB 30 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_LSB 28 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MASK 0x70000000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_GET(x) (((x) & 0x70000000) >> 28) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_SET(x) (((x) << 28) & 0x70000000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MSB 31 +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_LSB 31 +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MASK 0x80000000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000) + +/* macros for RXRF_BIAS2 */ +#define PHY_ANALOG_RXRF_BIAS2_ADDRESS 0x00000004 +#define PHY_ANALOG_RXRF_BIAS2_OFFSET 0x00000004 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_MSB 0 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_MASK 0x00000001 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_BIAS2_SPARE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_BIAS2_PKEN_MSB 3 +#define PHY_ANALOG_RXRF_BIAS2_PKEN_LSB 1 +#define PHY_ANALOG_RXRF_BIAS2_PKEN_MASK 0x0000000e +#define PHY_ANALOG_RXRF_BIAS2_PKEN_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_RXRF_BIAS2_PKEN_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MSB 6 +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_LSB 4 +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MASK 0x00000070 +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_GET(x) (((x) & 0x00000070) >> 4) +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_SET(x) (((x) << 4) & 0x00000070) +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MSB 7 +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_LSB 7 +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MASK 0x00000080 +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_MSB 10 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_LSB 8 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_MASK 0x00000700 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_MSB 13 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_LSB 11 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_MASK 0x00003800 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_MSB 16 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_LSB 14 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_MASK 0x0001c000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_MSB 19 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_LSB 17 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_MASK 0x000e0000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_MSB 22 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_LSB 20 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_MASK 0x00700000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_MSB 25 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_LSB 23 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_MASK 0x03800000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MSB 28 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_LSB 26 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MASK 0x1c000000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MSB 31 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_LSB 29 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MASK 0xe0000000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for RXRF_GAINSTAGES */ +#define PHY_ANALOG_RXRF_GAINSTAGES_ADDRESS 0x00000008 +#define PHY_ANALOG_RXRF_GAINSTAGES_OFFSET 0x00000008 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MSB 0 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MASK 0x00000001 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MSB 1 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_LSB 1 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MASK 0x00000002 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MSB 3 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_LSB 2 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MASK 0x0000000c +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MSB 5 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_LSB 4 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MASK 0x00000030 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_SET(x) (((x) << 4) & 0x00000030) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MSB 6 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_LSB 6 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MASK 0x00000040 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MSB 7 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_LSB 7 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MASK 0x00000080 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MSB 8 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_LSB 8 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MASK 0x00000100 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MSB 9 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_LSB 9 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MASK 0x00000200 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MSB 10 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_LSB 10 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MASK 0x00000400 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MSB 12 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_LSB 11 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MASK 0x00001800 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_GET(x) (((x) & 0x00001800) >> 11) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_SET(x) (((x) << 11) & 0x00001800) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MSB 13 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_LSB 13 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MASK 0x00002000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MSB 14 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_LSB 14 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MASK 0x00004000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MSB 15 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_LSB 15 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MASK 0x00008000 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MSB 16 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_LSB 16 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MASK 0x00010000 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MSB 17 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_LSB 17 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MASK 0x00020000 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MSB 19 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_LSB 18 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MASK 0x000c0000 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MSB 22 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_LSB 20 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MASK 0x00700000 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MSB 25 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_LSB 23 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MASK 0x03800000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MSB 27 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_LSB 26 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MASK 0x0c000000 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_GET(x) (((x) & 0x0c000000) >> 26) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_SET(x) (((x) << 26) & 0x0c000000) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MSB 30 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_LSB 28 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MASK 0x70000000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_GET(x) (((x) & 0x70000000) >> 28) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_SET(x) (((x) << 28) & 0x70000000) +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MSB 31 +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_LSB 31 +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MASK 0x80000000 +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for RXRF_AGC */ +#define PHY_ANALOG_RXRF_AGC_ADDRESS 0x0000000c +#define PHY_ANALOG_RXRF_AGC_OFFSET 0x0000000c +#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_MSB 0 +#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_LSB 0 +#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_MASK 0x00000001 +#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_MSB 1 +#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_LSB 1 +#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_MASK 0x00000002 +#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXRF_AGC_AGC_OUT_MSB 2 +#define PHY_ANALOG_RXRF_AGC_AGC_OUT_LSB 2 +#define PHY_ANALOG_RXRF_AGC_AGC_OUT_MASK 0x00000004 +#define PHY_ANALOG_RXRF_AGC_AGC_OUT_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_MSB 3 +#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_LSB 3 +#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_MASK 0x00000008 +#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_MSB 4 +#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_LSB 4 +#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_MASK 0x00000010 +#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_MSB 5 +#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_LSB 5 +#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_MASK 0x00000020 +#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MSB 8 +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_LSB 6 +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MASK 0x000001c0 +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_GET(x) (((x) & 0x000001c0) >> 6) +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_SET(x) (((x) << 6) & 0x000001c0) +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MSB 14 +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_LSB 9 +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MASK 0x00007e00 +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_GET(x) (((x) & 0x00007e00) >> 9) +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_SET(x) (((x) << 9) & 0x00007e00) +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MSB 18 +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_LSB 15 +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MASK 0x00078000 +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_GET(x) (((x) & 0x00078000) >> 15) +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_SET(x) (((x) << 15) & 0x00078000) +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MSB 24 +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_LSB 19 +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MASK 0x01f80000 +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_GET(x) (((x) & 0x01f80000) >> 19) +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_SET(x) (((x) << 19) & 0x01f80000) +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MSB 28 +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_LSB 25 +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MASK 0x1e000000 +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_GET(x) (((x) & 0x1e000000) >> 25) +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_SET(x) (((x) << 25) & 0x1e000000) +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MSB 29 +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_LSB 29 +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MASK 0x20000000 +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MSB 30 +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_LSB 30 +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MASK 0x40000000 +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MSB 31 +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_LSB 31 +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MASK 0x80000000 +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF1 */ +#define PHY_ANALOG_TXRF1_ADDRESS 0x00000040 +#define PHY_ANALOG_TXRF1_OFFSET 0x00000040 +#define PHY_ANALOG_TXRF1_PDLOBUF5G_MSB 0 +#define PHY_ANALOG_TXRF1_PDLOBUF5G_LSB 0 +#define PHY_ANALOG_TXRF1_PDLOBUF5G_MASK 0x00000001 +#define PHY_ANALOG_TXRF1_PDLOBUF5G_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TXRF1_PDLOBUF5G_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TXRF1_PDLODIV5G_MSB 1 +#define PHY_ANALOG_TXRF1_PDLODIV5G_LSB 1 +#define PHY_ANALOG_TXRF1_PDLODIV5G_MASK 0x00000002 +#define PHY_ANALOG_TXRF1_PDLODIV5G_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_TXRF1_PDLODIV5G_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_MSB 2 +#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_LSB 2 +#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_MASK 0x00000004 +#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_TXRF1_LODIV5GFORCED_MSB 3 +#define PHY_ANALOG_TXRF1_LODIV5GFORCED_LSB 3 +#define PHY_ANALOG_TXRF1_LODIV5GFORCED_MASK 0x00000008 +#define PHY_ANALOG_TXRF1_LODIV5GFORCED_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_TXRF1_LODIV5GFORCED_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_TXRF1_PADRV2GN5G_MSB 7 +#define PHY_ANALOG_TXRF1_PADRV2GN5G_LSB 4 +#define PHY_ANALOG_TXRF1_PADRV2GN5G_MASK 0x000000f0 +#define PHY_ANALOG_TXRF1_PADRV2GN5G_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_TXRF1_PADRV2GN5G_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_TXRF1_PADRV3GN5G_MSB 11 +#define PHY_ANALOG_TXRF1_PADRV3GN5G_LSB 8 +#define PHY_ANALOG_TXRF1_PADRV3GN5G_MASK 0x00000f00 +#define PHY_ANALOG_TXRF1_PADRV3GN5G_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TXRF1_PADRV3GN5G_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TXRF1_PADRV4GN5G_MSB 15 +#define PHY_ANALOG_TXRF1_PADRV4GN5G_LSB 12 +#define PHY_ANALOG_TXRF1_PADRV4GN5G_MASK 0x0000f000 +#define PHY_ANALOG_TXRF1_PADRV4GN5G_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_ANALOG_TXRF1_PADRV4GN5G_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_MSB 16 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_LSB 16 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_MASK 0x00010000 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_TXRF1_PDOUT2G_MSB 17 +#define PHY_ANALOG_TXRF1_PDOUT2G_LSB 17 +#define PHY_ANALOG_TXRF1_PDOUT2G_MASK 0x00020000 +#define PHY_ANALOG_TXRF1_PDOUT2G_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_TXRF1_PDOUT2G_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_TXRF1_PDDR2G_MSB 18 +#define PHY_ANALOG_TXRF1_PDDR2G_LSB 18 +#define PHY_ANALOG_TXRF1_PDDR2G_MASK 0x00040000 +#define PHY_ANALOG_TXRF1_PDDR2G_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_TXRF1_PDDR2G_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_TXRF1_PDMXR2G_MSB 19 +#define PHY_ANALOG_TXRF1_PDMXR2G_LSB 19 +#define PHY_ANALOG_TXRF1_PDMXR2G_MASK 0x00080000 +#define PHY_ANALOG_TXRF1_PDMXR2G_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_TXRF1_PDMXR2G_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_TXRF1_PDLOBUF2G_MSB 20 +#define PHY_ANALOG_TXRF1_PDLOBUF2G_LSB 20 +#define PHY_ANALOG_TXRF1_PDLOBUF2G_MASK 0x00100000 +#define PHY_ANALOG_TXRF1_PDLOBUF2G_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TXRF1_PDLOBUF2G_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TXRF1_PDLODIV2G_MSB 21 +#define PHY_ANALOG_TXRF1_PDLODIV2G_LSB 21 +#define PHY_ANALOG_TXRF1_PDLODIV2G_MASK 0x00200000 +#define PHY_ANALOG_TXRF1_PDLODIV2G_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_TXRF1_PDLODIV2G_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MSB 22 +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_LSB 22 +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MASK 0x00400000 +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MSB 23 +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_LSB 23 +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MASK 0x00800000 +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_TXRF1_PADRVGN2G_MSB 30 +#define PHY_ANALOG_TXRF1_PADRVGN2G_LSB 24 +#define PHY_ANALOG_TXRF1_PADRVGN2G_MASK 0x7f000000 +#define PHY_ANALOG_TXRF1_PADRVGN2G_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TXRF1_PADRVGN2G_SET(x) (((x) << 24) & 0x7f000000) +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MSB 31 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_LSB 31 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MASK 0x80000000 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF2 */ +#define PHY_ANALOG_TXRF2_ADDRESS 0x00000044 +#define PHY_ANALOG_TXRF2_OFFSET 0x00000044 +#define PHY_ANALOG_TXRF2_D3B5G_MSB 2 +#define PHY_ANALOG_TXRF2_D3B5G_LSB 0 +#define PHY_ANALOG_TXRF2_D3B5G_MASK 0x00000007 +#define PHY_ANALOG_TXRF2_D3B5G_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_TXRF2_D3B5G_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_TXRF2_D4B5G_MSB 5 +#define PHY_ANALOG_TXRF2_D4B5G_LSB 3 +#define PHY_ANALOG_TXRF2_D4B5G_MASK 0x00000038 +#define PHY_ANALOG_TXRF2_D4B5G_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_ANALOG_TXRF2_D4B5G_SET(x) (((x) << 3) & 0x00000038) +#define PHY_ANALOG_TXRF2_OCAS2G_MSB 8 +#define PHY_ANALOG_TXRF2_OCAS2G_LSB 6 +#define PHY_ANALOG_TXRF2_OCAS2G_MASK 0x000001c0 +#define PHY_ANALOG_TXRF2_OCAS2G_GET(x) (((x) & 0x000001c0) >> 6) +#define PHY_ANALOG_TXRF2_OCAS2G_SET(x) (((x) << 6) & 0x000001c0) +#define PHY_ANALOG_TXRF2_DCAS2G_MSB 11 +#define PHY_ANALOG_TXRF2_DCAS2G_LSB 9 +#define PHY_ANALOG_TXRF2_DCAS2G_MASK 0x00000e00 +#define PHY_ANALOG_TXRF2_DCAS2G_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_ANALOG_TXRF2_DCAS2G_SET(x) (((x) << 9) & 0x00000e00) +#define PHY_ANALOG_TXRF2_OB2G_PALOFF_MSB 14 +#define PHY_ANALOG_TXRF2_OB2G_PALOFF_LSB 12 +#define PHY_ANALOG_TXRF2_OB2G_PALOFF_MASK 0x00007000 +#define PHY_ANALOG_TXRF2_OB2G_PALOFF_GET(x) (((x) & 0x00007000) >> 12) +#define PHY_ANALOG_TXRF2_OB2G_PALOFF_SET(x) (((x) << 12) & 0x00007000) +#define PHY_ANALOG_TXRF2_OB2G_QAM_MSB 17 +#define PHY_ANALOG_TXRF2_OB2G_QAM_LSB 15 +#define PHY_ANALOG_TXRF2_OB2G_QAM_MASK 0x00038000 +#define PHY_ANALOG_TXRF2_OB2G_QAM_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_TXRF2_OB2G_QAM_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_TXRF2_OB2G_PSK_MSB 20 +#define PHY_ANALOG_TXRF2_OB2G_PSK_LSB 18 +#define PHY_ANALOG_TXRF2_OB2G_PSK_MASK 0x001c0000 +#define PHY_ANALOG_TXRF2_OB2G_PSK_GET(x) (((x) & 0x001c0000) >> 18) +#define PHY_ANALOG_TXRF2_OB2G_PSK_SET(x) (((x) << 18) & 0x001c0000) +#define PHY_ANALOG_TXRF2_OB2G_CCK_MSB 23 +#define PHY_ANALOG_TXRF2_OB2G_CCK_LSB 21 +#define PHY_ANALOG_TXRF2_OB2G_CCK_MASK 0x00e00000 +#define PHY_ANALOG_TXRF2_OB2G_CCK_GET(x) (((x) & 0x00e00000) >> 21) +#define PHY_ANALOG_TXRF2_OB2G_CCK_SET(x) (((x) << 21) & 0x00e00000) +#define PHY_ANALOG_TXRF2_DB2G_MSB 26 +#define PHY_ANALOG_TXRF2_DB2G_LSB 24 +#define PHY_ANALOG_TXRF2_DB2G_MASK 0x07000000 +#define PHY_ANALOG_TXRF2_DB2G_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_ANALOG_TXRF2_DB2G_SET(x) (((x) << 24) & 0x07000000) +#define PHY_ANALOG_TXRF2_PDOUT5G_MSB 30 +#define PHY_ANALOG_TXRF2_PDOUT5G_LSB 27 +#define PHY_ANALOG_TXRF2_PDOUT5G_MASK 0x78000000 +#define PHY_ANALOG_TXRF2_PDOUT5G_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_TXRF2_PDOUT5G_SET(x) (((x) << 27) & 0x78000000) +#define PHY_ANALOG_TXRF2_PDMXR5G_MSB 31 +#define PHY_ANALOG_TXRF2_PDMXR5G_LSB 31 +#define PHY_ANALOG_TXRF2_PDMXR5G_MASK 0x80000000 +#define PHY_ANALOG_TXRF2_PDMXR5G_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF2_PDMXR5G_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF3 */ +#define PHY_ANALOG_TXRF3_ADDRESS 0x00000048 +#define PHY_ANALOG_TXRF3_OFFSET 0x00000048 +#define PHY_ANALOG_TXRF3_FILTR2G_MSB 1 +#define PHY_ANALOG_TXRF3_FILTR2G_LSB 0 +#define PHY_ANALOG_TXRF3_FILTR2G_MASK 0x00000003 +#define PHY_ANALOG_TXRF3_FILTR2G_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF3_FILTR2G_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF3_PWDFB2_2G_MSB 2 +#define PHY_ANALOG_TXRF3_PWDFB2_2G_LSB 2 +#define PHY_ANALOG_TXRF3_PWDFB2_2G_MASK 0x00000004 +#define PHY_ANALOG_TXRF3_PWDFB2_2G_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_TXRF3_PWDFB2_2G_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_TXRF3_PWDFB1_2G_MSB 3 +#define PHY_ANALOG_TXRF3_PWDFB1_2G_LSB 3 +#define PHY_ANALOG_TXRF3_PWDFB1_2G_MASK 0x00000008 +#define PHY_ANALOG_TXRF3_PWDFB1_2G_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_TXRF3_PWDFB1_2G_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_TXRF3_PDFB2G_MSB 4 +#define PHY_ANALOG_TXRF3_PDFB2G_LSB 4 +#define PHY_ANALOG_TXRF3_PDFB2G_MASK 0x00000010 +#define PHY_ANALOG_TXRF3_PDFB2G_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_TXRF3_PDFB2G_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_TXRF3_RDIV5G_MSB 6 +#define PHY_ANALOG_TXRF3_RDIV5G_LSB 5 +#define PHY_ANALOG_TXRF3_RDIV5G_MASK 0x00000060 +#define PHY_ANALOG_TXRF3_RDIV5G_GET(x) (((x) & 0x00000060) >> 5) +#define PHY_ANALOG_TXRF3_RDIV5G_SET(x) (((x) << 5) & 0x00000060) +#define PHY_ANALOG_TXRF3_CAPDIV5G_MSB 9 +#define PHY_ANALOG_TXRF3_CAPDIV5G_LSB 7 +#define PHY_ANALOG_TXRF3_CAPDIV5G_MASK 0x00000380 +#define PHY_ANALOG_TXRF3_CAPDIV5G_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_TXRF3_CAPDIV5G_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_TXRF3_PDPREDIST5G_MSB 10 +#define PHY_ANALOG_TXRF3_PDPREDIST5G_LSB 10 +#define PHY_ANALOG_TXRF3_PDPREDIST5G_MASK 0x00000400 +#define PHY_ANALOG_TXRF3_PDPREDIST5G_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_TXRF3_PDPREDIST5G_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_TXRF3_RDIV2G_MSB 12 +#define PHY_ANALOG_TXRF3_RDIV2G_LSB 11 +#define PHY_ANALOG_TXRF3_RDIV2G_MASK 0x00001800 +#define PHY_ANALOG_TXRF3_RDIV2G_GET(x) (((x) & 0x00001800) >> 11) +#define PHY_ANALOG_TXRF3_RDIV2G_SET(x) (((x) << 11) & 0x00001800) +#define PHY_ANALOG_TXRF3_PDPREDIST2G_MSB 13 +#define PHY_ANALOG_TXRF3_PDPREDIST2G_LSB 13 +#define PHY_ANALOG_TXRF3_PDPREDIST2G_MASK 0x00002000 +#define PHY_ANALOG_TXRF3_PDPREDIST2G_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_TXRF3_PDPREDIST2G_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_TXRF3_OCAS5G_MSB 16 +#define PHY_ANALOG_TXRF3_OCAS5G_LSB 14 +#define PHY_ANALOG_TXRF3_OCAS5G_MASK 0x0001c000 +#define PHY_ANALOG_TXRF3_OCAS5G_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF3_OCAS5G_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF3_D2CAS5G_MSB 19 +#define PHY_ANALOG_TXRF3_D2CAS5G_LSB 17 +#define PHY_ANALOG_TXRF3_D2CAS5G_MASK 0x000e0000 +#define PHY_ANALOG_TXRF3_D2CAS5G_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF3_D2CAS5G_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF3_D3CAS5G_MSB 22 +#define PHY_ANALOG_TXRF3_D3CAS5G_LSB 20 +#define PHY_ANALOG_TXRF3_D3CAS5G_MASK 0x00700000 +#define PHY_ANALOG_TXRF3_D3CAS5G_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF3_D3CAS5G_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF3_D4CAS5G_MSB 25 +#define PHY_ANALOG_TXRF3_D4CAS5G_LSB 23 +#define PHY_ANALOG_TXRF3_D4CAS5G_MASK 0x03800000 +#define PHY_ANALOG_TXRF3_D4CAS5G_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF3_D4CAS5G_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF3_OB5G_MSB 28 +#define PHY_ANALOG_TXRF3_OB5G_LSB 26 +#define PHY_ANALOG_TXRF3_OB5G_MASK 0x1c000000 +#define PHY_ANALOG_TXRF3_OB5G_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF3_OB5G_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF3_D2B5G_MSB 31 +#define PHY_ANALOG_TXRF3_D2B5G_LSB 29 +#define PHY_ANALOG_TXRF3_D2B5G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF3_D2B5G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF3_D2B5G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF4 */ +#define PHY_ANALOG_TXRF4_ADDRESS 0x0000004c +#define PHY_ANALOG_TXRF4_OFFSET 0x0000004c +#define PHY_ANALOG_TXRF4_PK1B2G_CCK_MSB 1 +#define PHY_ANALOG_TXRF4_PK1B2G_CCK_LSB 0 +#define PHY_ANALOG_TXRF4_PK1B2G_CCK_MASK 0x00000003 +#define PHY_ANALOG_TXRF4_PK1B2G_CCK_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF4_PK1B2G_CCK_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF4_MIOB2G_QAM_MSB 4 +#define PHY_ANALOG_TXRF4_MIOB2G_QAM_LSB 2 +#define PHY_ANALOG_TXRF4_MIOB2G_QAM_MASK 0x0000001c +#define PHY_ANALOG_TXRF4_MIOB2G_QAM_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_TXRF4_MIOB2G_QAM_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_TXRF4_MIOB2G_PSK_MSB 7 +#define PHY_ANALOG_TXRF4_MIOB2G_PSK_LSB 5 +#define PHY_ANALOG_TXRF4_MIOB2G_PSK_MASK 0x000000e0 +#define PHY_ANALOG_TXRF4_MIOB2G_PSK_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_TXRF4_MIOB2G_PSK_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_TXRF4_MIOB2G_CCK_MSB 10 +#define PHY_ANALOG_TXRF4_MIOB2G_CCK_LSB 8 +#define PHY_ANALOG_TXRF4_MIOB2G_CCK_MASK 0x00000700 +#define PHY_ANALOG_TXRF4_MIOB2G_CCK_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_TXRF4_MIOB2G_CCK_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_TXRF4_COMP2G_QAM_MSB 13 +#define PHY_ANALOG_TXRF4_COMP2G_QAM_LSB 11 +#define PHY_ANALOG_TXRF4_COMP2G_QAM_MASK 0x00003800 +#define PHY_ANALOG_TXRF4_COMP2G_QAM_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_TXRF4_COMP2G_QAM_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_TXRF4_COMP2G_PSK_MSB 16 +#define PHY_ANALOG_TXRF4_COMP2G_PSK_LSB 14 +#define PHY_ANALOG_TXRF4_COMP2G_PSK_MASK 0x0001c000 +#define PHY_ANALOG_TXRF4_COMP2G_PSK_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF4_COMP2G_PSK_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF4_COMP2G_CCK_MSB 19 +#define PHY_ANALOG_TXRF4_COMP2G_CCK_LSB 17 +#define PHY_ANALOG_TXRF4_COMP2G_CCK_MASK 0x000e0000 +#define PHY_ANALOG_TXRF4_COMP2G_CCK_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF4_COMP2G_CCK_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MSB 22 +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_LSB 20 +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MASK 0x00700000 +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MSB 25 +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_LSB 23 +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MASK 0x03800000 +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MSB 28 +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_LSB 26 +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MASK 0x1c000000 +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF4_AMP2CAS2G_MSB 31 +#define PHY_ANALOG_TXRF4_AMP2CAS2G_LSB 29 +#define PHY_ANALOG_TXRF4_AMP2CAS2G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF4_AMP2CAS2G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF4_AMP2CAS2G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF5 */ +#define PHY_ANALOG_TXRF5_ADDRESS 0x00000050 +#define PHY_ANALOG_TXRF5_OFFSET 0x00000050 +#define PHY_ANALOG_TXRF5_SPARE5_MSB 0 +#define PHY_ANALOG_TXRF5_SPARE5_LSB 0 +#define PHY_ANALOG_TXRF5_SPARE5_MASK 0x00000001 +#define PHY_ANALOG_TXRF5_SPARE5_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TXRF5_SPARE5_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TXRF5_PAL_LOCKED_MSB 1 +#define PHY_ANALOG_TXRF5_PAL_LOCKED_LSB 1 +#define PHY_ANALOG_TXRF5_PAL_LOCKED_MASK 0x00000002 +#define PHY_ANALOG_TXRF5_PAL_LOCKED_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_TXRF5_FBHI2G_MSB 2 +#define PHY_ANALOG_TXRF5_FBHI2G_LSB 2 +#define PHY_ANALOG_TXRF5_FBHI2G_MASK 0x00000004 +#define PHY_ANALOG_TXRF5_FBHI2G_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_TXRF5_FBLO2G_MSB 3 +#define PHY_ANALOG_TXRF5_FBLO2G_LSB 3 +#define PHY_ANALOG_TXRF5_FBLO2G_MASK 0x00000008 +#define PHY_ANALOG_TXRF5_FBLO2G_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_TXRF5_NOPALGAIN2G_MSB 4 +#define PHY_ANALOG_TXRF5_NOPALGAIN2G_LSB 4 +#define PHY_ANALOG_TXRF5_NOPALGAIN2G_MASK 0x00000010 +#define PHY_ANALOG_TXRF5_NOPALGAIN2G_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_TXRF5_NOPALGAIN2G_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_TXRF5_ENPACAL2G_MSB 5 +#define PHY_ANALOG_TXRF5_ENPACAL2G_LSB 5 +#define PHY_ANALOG_TXRF5_ENPACAL2G_MASK 0x00000020 +#define PHY_ANALOG_TXRF5_ENPACAL2G_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_TXRF5_ENPACAL2G_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_TXRF5_OFFSET2G_MSB 12 +#define PHY_ANALOG_TXRF5_OFFSET2G_LSB 6 +#define PHY_ANALOG_TXRF5_OFFSET2G_MASK 0x00001fc0 +#define PHY_ANALOG_TXRF5_OFFSET2G_GET(x) (((x) & 0x00001fc0) >> 6) +#define PHY_ANALOG_TXRF5_OFFSET2G_SET(x) (((x) << 6) & 0x00001fc0) +#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_MSB 13 +#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_LSB 13 +#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_MASK 0x00002000 +#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_TXRF5_REFHI2G_MSB 16 +#define PHY_ANALOG_TXRF5_REFHI2G_LSB 14 +#define PHY_ANALOG_TXRF5_REFHI2G_MASK 0x0001c000 +#define PHY_ANALOG_TXRF5_REFHI2G_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF5_REFHI2G_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF5_REFLO2G_MSB 19 +#define PHY_ANALOG_TXRF5_REFLO2G_LSB 17 +#define PHY_ANALOG_TXRF5_REFLO2G_MASK 0x000e0000 +#define PHY_ANALOG_TXRF5_REFLO2G_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF5_REFLO2G_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF5_PALCLAMP2G_MSB 21 +#define PHY_ANALOG_TXRF5_PALCLAMP2G_LSB 20 +#define PHY_ANALOG_TXRF5_PALCLAMP2G_MASK 0x00300000 +#define PHY_ANALOG_TXRF5_PALCLAMP2G_GET(x) (((x) & 0x00300000) >> 20) +#define PHY_ANALOG_TXRF5_PALCLAMP2G_SET(x) (((x) << 20) & 0x00300000) +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MSB 23 +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_LSB 22 +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MASK 0x00c00000 +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MSB 25 +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_LSB 24 +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MASK 0x03000000 +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_SET(x) (((x) << 24) & 0x03000000) +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MSB 27 +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_LSB 26 +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MASK 0x0c000000 +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_GET(x) (((x) & 0x0c000000) >> 26) +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_SET(x) (((x) << 26) & 0x0c000000) +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MSB 29 +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_LSB 28 +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MASK 0x30000000 +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_GET(x) (((x) & 0x30000000) >> 28) +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_SET(x) (((x) << 28) & 0x30000000) +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MSB 31 +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_LSB 30 +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MASK 0xc0000000 +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for TXRF6 */ +#define PHY_ANALOG_TXRF6_ADDRESS 0x00000054 +#define PHY_ANALOG_TXRF6_OFFSET 0x00000054 +#define PHY_ANALOG_TXRF6_PALCLKGATE2G_MSB 0 +#define PHY_ANALOG_TXRF6_PALCLKGATE2G_LSB 0 +#define PHY_ANALOG_TXRF6_PALCLKGATE2G_MASK 0x00000001 +#define PHY_ANALOG_TXRF6_PALCLKGATE2G_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TXRF6_PALCLKGATE2G_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_MSB 8 +#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_LSB 1 +#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_MASK 0x000001fe +#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_GET(x) (((x) & 0x000001fe) >> 1) +#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_SET(x) (((x) << 1) & 0x000001fe) +#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_MSB 10 +#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_LSB 9 +#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_MASK 0x00000600 +#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_GET(x) (((x) & 0x00000600) >> 9) +#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_SET(x) (((x) << 9) & 0x00000600) +#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_MSB 11 +#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_LSB 11 +#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_MASK 0x00000800 +#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_TXRF6_GAINSTEP2G_MSB 14 +#define PHY_ANALOG_TXRF6_GAINSTEP2G_LSB 12 +#define PHY_ANALOG_TXRF6_GAINSTEP2G_MASK 0x00007000 +#define PHY_ANALOG_TXRF6_GAINSTEP2G_GET(x) (((x) & 0x00007000) >> 12) +#define PHY_ANALOG_TXRF6_GAINSTEP2G_SET(x) (((x) << 12) & 0x00007000) +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MSB 15 +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_LSB 15 +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MASK 0x00008000 +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_TXRF6_CAPDIV_I2G_MSB 19 +#define PHY_ANALOG_TXRF6_CAPDIV_I2G_LSB 16 +#define PHY_ANALOG_TXRF6_CAPDIV_I2G_MASK 0x000f0000 +#define PHY_ANALOG_TXRF6_CAPDIV_I2G_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_TXRF6_CAPDIV_I2G_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MSB 23 +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_LSB 20 +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MASK 0x00f00000 +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_GET(x) (((x) & 0x00f00000) >> 20) +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_SET(x) (((x) << 20) & 0x00f00000) +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MSB 26 +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_LSB 24 +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MASK 0x07000000 +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_SET(x) (((x) << 24) & 0x07000000) +#define PHY_ANALOG_TXRF6_CAPDIV2G_MSB 30 +#define PHY_ANALOG_TXRF6_CAPDIV2G_LSB 27 +#define PHY_ANALOG_TXRF6_CAPDIV2G_MASK 0x78000000 +#define PHY_ANALOG_TXRF6_CAPDIV2G_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_TXRF6_CAPDIV2G_SET(x) (((x) << 27) & 0x78000000) +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MSB 31 +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_LSB 31 +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MASK 0x80000000 +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF7 */ +#define PHY_ANALOG_TXRF7_ADDRESS 0x00000058 +#define PHY_ANALOG_TXRF7_OFFSET 0x00000058 +#define PHY_ANALOG_TXRF7_SPARE7_MSB 1 +#define PHY_ANALOG_TXRF7_SPARE7_LSB 0 +#define PHY_ANALOG_TXRF7_SPARE7_MASK 0x00000003 +#define PHY_ANALOG_TXRF7_SPARE7_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF7_SPARE7_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MSB 7 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_LSB 2 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MASK 0x000000fc +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MSB 13 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_LSB 8 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MASK 0x00003f00 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MSB 19 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_LSB 14 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MASK 0x000fc000 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MSB 25 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_LSB 20 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MASK 0x03f00000 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MSB 31 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_LSB 26 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MASK 0xfc000000 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for TXRF8 */ +#define PHY_ANALOG_TXRF8_ADDRESS 0x0000005c +#define PHY_ANALOG_TXRF8_OFFSET 0x0000005c +#define PHY_ANALOG_TXRF8_SPARE8_MSB 1 +#define PHY_ANALOG_TXRF8_SPARE8_LSB 0 +#define PHY_ANALOG_TXRF8_SPARE8_MASK 0x00000003 +#define PHY_ANALOG_TXRF8_SPARE8_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF8_SPARE8_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MSB 7 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_LSB 2 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MASK 0x000000fc +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MSB 13 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_LSB 8 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MASK 0x00003f00 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MSB 19 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_LSB 14 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MASK 0x000fc000 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MSB 25 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_LSB 20 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MASK 0x03f00000 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MSB 31 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_LSB 26 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MASK 0xfc000000 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for TXRF9 */ +#define PHY_ANALOG_TXRF9_ADDRESS 0x00000060 +#define PHY_ANALOG_TXRF9_OFFSET 0x00000060 +#define PHY_ANALOG_TXRF9_SPARE9_MSB 1 +#define PHY_ANALOG_TXRF9_SPARE9_LSB 0 +#define PHY_ANALOG_TXRF9_SPARE9_MASK 0x00000003 +#define PHY_ANALOG_TXRF9_SPARE9_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF9_SPARE9_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MSB 7 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_LSB 2 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MASK 0x000000fc +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MSB 13 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_LSB 8 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MASK 0x00003f00 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MSB 19 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_LSB 14 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MASK 0x000fc000 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MSB 25 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_LSB 20 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MASK 0x03f00000 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MSB 31 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_LSB 26 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MASK 0xfc000000 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for TXRF10 */ +#define PHY_ANALOG_TXRF10_ADDRESS 0x00000064 +#define PHY_ANALOG_TXRF10_OFFSET 0x00000064 +#define PHY_ANALOG_TXRF10_SPARE10_MSB 2 +#define PHY_ANALOG_TXRF10_SPARE10_LSB 0 +#define PHY_ANALOG_TXRF10_SPARE10_MASK 0x00000007 +#define PHY_ANALOG_TXRF10_SPARE10_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_TXRF10_SPARE10_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MSB 3 +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_LSB 3 +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MASK 0x00000008 +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_TXRF10_D3B5GCALTX_MSB 6 +#define PHY_ANALOG_TXRF10_D3B5GCALTX_LSB 4 +#define PHY_ANALOG_TXRF10_D3B5GCALTX_MASK 0x00000070 +#define PHY_ANALOG_TXRF10_D3B5GCALTX_GET(x) (((x) & 0x00000070) >> 4) +#define PHY_ANALOG_TXRF10_D3B5GCALTX_SET(x) (((x) << 4) & 0x00000070) +#define PHY_ANALOG_TXRF10_D4B5GCALTX_MSB 9 +#define PHY_ANALOG_TXRF10_D4B5GCALTX_LSB 7 +#define PHY_ANALOG_TXRF10_D4B5GCALTX_MASK 0x00000380 +#define PHY_ANALOG_TXRF10_D4B5GCALTX_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_TXRF10_D4B5GCALTX_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MSB 16 +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_LSB 10 +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MASK 0x0001fc00 +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_GET(x) (((x) & 0x0001fc00) >> 10) +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_SET(x) (((x) << 10) & 0x0001fc00) +#define PHY_ANALOG_TXRF10_DB2GCALTX_MSB 19 +#define PHY_ANALOG_TXRF10_DB2GCALTX_LSB 17 +#define PHY_ANALOG_TXRF10_DB2GCALTX_MASK 0x000e0000 +#define PHY_ANALOG_TXRF10_DB2GCALTX_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF10_DB2GCALTX_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF10_CALTXSHIFT_MSB 20 +#define PHY_ANALOG_TXRF10_CALTXSHIFT_LSB 20 +#define PHY_ANALOG_TXRF10_CALTXSHIFT_MASK 0x00100000 +#define PHY_ANALOG_TXRF10_CALTXSHIFT_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TXRF10_CALTXSHIFT_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MSB 21 +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_LSB 21 +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MASK 0x00200000 +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_MSB 27 +#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_LSB 22 +#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_MASK 0x0fc00000 +#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_GET(x) (((x) & 0x0fc00000) >> 22) +#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_MSB 31 +#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_LSB 28 +#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_MASK 0xf0000000 +#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_GET(x) (((x) & 0xf0000000) >> 28) + +/* macros for TXRF11 */ +#define PHY_ANALOG_TXRF11_ADDRESS 0x00000068 +#define PHY_ANALOG_TXRF11_OFFSET 0x00000068 +#define PHY_ANALOG_TXRF11_SPARE11_MSB 1 +#define PHY_ANALOG_TXRF11_SPARE11_LSB 0 +#define PHY_ANALOG_TXRF11_SPARE11_MASK 0x00000003 +#define PHY_ANALOG_TXRF11_SPARE11_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF11_SPARE11_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MSB 4 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_LSB 2 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MASK 0x0000001c +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MSB 7 +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_LSB 5 +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MASK 0x000000e0 +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MSB 10 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_LSB 8 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MASK 0x00000700 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MSB 13 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_LSB 11 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MASK 0x00003800 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MSB 16 +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_LSB 14 +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MASK 0x0001c000 +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_MSB 19 +#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_LSB 17 +#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_MASK 0x000e0000 +#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MSB 22 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_LSB 20 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MASK 0x00700000 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MSB 25 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_LSB 23 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MASK 0x03800000 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MSB 28 +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_LSB 26 +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MASK 0x1c000000 +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MSB 31 +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_LSB 29 +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF12 */ +#define PHY_ANALOG_TXRF12_ADDRESS 0x0000006c +#define PHY_ANALOG_TXRF12_OFFSET 0x0000006c +#define PHY_ANALOG_TXRF12_SPARE12_2_MSB 7 +#define PHY_ANALOG_TXRF12_SPARE12_2_LSB 0 +#define PHY_ANALOG_TXRF12_SPARE12_2_MASK 0x000000ff +#define PHY_ANALOG_TXRF12_SPARE12_2_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_ANALOG_TXRF12_SPARE12_1_MSB 9 +#define PHY_ANALOG_TXRF12_SPARE12_1_LSB 8 +#define PHY_ANALOG_TXRF12_SPARE12_1_MASK 0x00000300 +#define PHY_ANALOG_TXRF12_SPARE12_1_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_TXRF12_SPARE12_1_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_TXRF12_ATBSEL5G_MSB 13 +#define PHY_ANALOG_TXRF12_ATBSEL5G_LSB 10 +#define PHY_ANALOG_TXRF12_ATBSEL5G_MASK 0x00003c00 +#define PHY_ANALOG_TXRF12_ATBSEL5G_GET(x) (((x) & 0x00003c00) >> 10) +#define PHY_ANALOG_TXRF12_ATBSEL5G_SET(x) (((x) << 10) & 0x00003c00) +#define PHY_ANALOG_TXRF12_ATBSEL2G_MSB 16 +#define PHY_ANALOG_TXRF12_ATBSEL2G_LSB 14 +#define PHY_ANALOG_TXRF12_ATBSEL2G_MASK 0x0001c000 +#define PHY_ANALOG_TXRF12_ATBSEL2G_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF12_ATBSEL2G_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MSB 19 +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_LSB 17 +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MASK 0x000e0000 +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_MSB 22 +#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_LSB 20 +#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_MASK 0x00700000 +#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MSB 25 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_LSB 23 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MASK 0x03800000 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MSB 28 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_LSB 26 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MASK 0x1c000000 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_MSB 31 +#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_LSB 29 +#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for SYNTH1 */ +#define PHY_ANALOG_SYNTH1_ADDRESS 0x00000080 +#define PHY_ANALOG_SYNTH1_OFFSET 0x00000080 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MSB 2 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_LSB 0 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MASK 0x00000007 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MSB 5 +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_LSB 3 +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MASK 0x00000038 +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_SET(x) (((x) << 3) & 0x00000038) +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 6 +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 6 +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000040 +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MSB 7 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_LSB 7 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MASK 0x00000080 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MSB 8 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_LSB 8 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000100 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MSB 9 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_LSB 9 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000200 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_SYNTH1_MONITOR_REF_MSB 10 +#define PHY_ANALOG_SYNTH1_MONITOR_REF_LSB 10 +#define PHY_ANALOG_SYNTH1_MONITOR_REF_MASK 0x00000400 +#define PHY_ANALOG_SYNTH1_MONITOR_REF_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH1_MONITOR_REF_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_MSB 11 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_LSB 11 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_MASK 0x00000800 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MSB 12 +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_LSB 12 +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MASK 0x00001000 +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_SYNTH1_PWUP_PD_MSB 15 +#define PHY_ANALOG_SYNTH1_PWUP_PD_LSB 13 +#define PHY_ANALOG_SYNTH1_PWUP_PD_MASK 0x0000e000 +#define PHY_ANALOG_SYNTH1_PWUP_PD_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_SYNTH1_PWUP_PD_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MSB 16 +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_LSB 16 +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MASK 0x00010000 +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MSB 18 +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_LSB 17 +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MASK 0x00060000 +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_GET(x) (((x) & 0x00060000) >> 17) +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_SET(x) (((x) << 17) & 0x00060000) +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MSB 20 +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_LSB 19 +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MASK 0x00180000 +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_GET(x) (((x) & 0x00180000) >> 19) +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_SET(x) (((x) << 19) & 0x00180000) +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MSB 21 +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_LSB 21 +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MASK 0x00200000 +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MSB 22 +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_LSB 22 +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MASK 0x00400000 +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MSB 23 +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_LSB 23 +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MASK 0x00800000 +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_SYNTH1_PWD_LODIV_MSB 24 +#define PHY_ANALOG_SYNTH1_PWD_LODIV_LSB 24 +#define PHY_ANALOG_SYNTH1_PWD_LODIV_MASK 0x01000000 +#define PHY_ANALOG_SYNTH1_PWD_LODIV_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_SYNTH1_PWD_LODIV_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MSB 25 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_LSB 25 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MASK 0x02000000 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << 25) & 0x02000000) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MSB 26 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_LSB 26 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MASK 0x04000000 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_SYNTH1_PWD_PRESC_MSB 27 +#define PHY_ANALOG_SYNTH1_PWD_PRESC_LSB 27 +#define PHY_ANALOG_SYNTH1_PWD_PRESC_MASK 0x08000000 +#define PHY_ANALOG_SYNTH1_PWD_PRESC_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_SYNTH1_PWD_PRESC_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_SYNTH1_PWD_VCO_MSB 28 +#define PHY_ANALOG_SYNTH1_PWD_VCO_LSB 28 +#define PHY_ANALOG_SYNTH1_PWD_VCO_MASK 0x10000000 +#define PHY_ANALOG_SYNTH1_PWD_VCO_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_SYNTH1_PWD_VCO_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_SYNTH1_PWD_VCMON_MSB 29 +#define PHY_ANALOG_SYNTH1_PWD_VCMON_LSB 29 +#define PHY_ANALOG_SYNTH1_PWD_VCMON_MASK 0x20000000 +#define PHY_ANALOG_SYNTH1_PWD_VCMON_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_SYNTH1_PWD_VCMON_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_SYNTH1_PWD_CP_MSB 30 +#define PHY_ANALOG_SYNTH1_PWD_CP_LSB 30 +#define PHY_ANALOG_SYNTH1_PWD_CP_MASK 0x40000000 +#define PHY_ANALOG_SYNTH1_PWD_CP_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH1_PWD_CP_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH1_PWD_BIAS_MSB 31 +#define PHY_ANALOG_SYNTH1_PWD_BIAS_LSB 31 +#define PHY_ANALOG_SYNTH1_PWD_BIAS_MASK 0x80000000 +#define PHY_ANALOG_SYNTH1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH2 */ +#define PHY_ANALOG_SYNTH2_ADDRESS 0x00000084 +#define PHY_ANALOG_SYNTH2_OFFSET 0x00000084 +#define PHY_ANALOG_SYNTH2_CAPRANGE3_MSB 3 +#define PHY_ANALOG_SYNTH2_CAPRANGE3_LSB 0 +#define PHY_ANALOG_SYNTH2_CAPRANGE3_MASK 0x0000000f +#define PHY_ANALOG_SYNTH2_CAPRANGE3_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_SYNTH2_CAPRANGE3_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_ANALOG_SYNTH2_CAPRANGE2_MSB 7 +#define PHY_ANALOG_SYNTH2_CAPRANGE2_LSB 4 +#define PHY_ANALOG_SYNTH2_CAPRANGE2_MASK 0x000000f0 +#define PHY_ANALOG_SYNTH2_CAPRANGE2_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_SYNTH2_CAPRANGE2_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_SYNTH2_CAPRANGE1_MSB 11 +#define PHY_ANALOG_SYNTH2_CAPRANGE1_LSB 8 +#define PHY_ANALOG_SYNTH2_CAPRANGE1_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH2_CAPRANGE1_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH2_CAPRANGE1_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_MSB 15 +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_LSB 12 +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_MASK 0x0000f000 +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_MSB 16 +#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_LSB 16 +#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_MASK 0x00010000 +#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MSB 17 +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_LSB 17 +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MASK 0x00020000 +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_MSB 19 +#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_LSB 18 +#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_MASK 0x000c0000 +#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MSB 22 +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_LSB 20 +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MASK 0x00700000 +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_SYNTH2_VC_MID_REF_MSB 25 +#define PHY_ANALOG_SYNTH2_VC_MID_REF_LSB 23 +#define PHY_ANALOG_SYNTH2_VC_MID_REF_MASK 0x03800000 +#define PHY_ANALOG_SYNTH2_VC_MID_REF_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_SYNTH2_VC_MID_REF_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_SYNTH2_VC_HI_REF_MSB 28 +#define PHY_ANALOG_SYNTH2_VC_HI_REF_LSB 26 +#define PHY_ANALOG_SYNTH2_VC_HI_REF_MASK 0x1c000000 +#define PHY_ANALOG_SYNTH2_VC_HI_REF_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_SYNTH2_VC_HI_REF_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MSB 31 +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_LSB 29 +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MASK 0xe0000000 +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for SYNTH3 */ +#define PHY_ANALOG_SYNTH3_ADDRESS 0x00000088 +#define PHY_ANALOG_SYNTH3_OFFSET 0x00000088 +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MSB 5 +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_LSB 0 +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MSB 11 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_LSB 6 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MSB 17 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_LSB 12 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MSB 23 +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_LSB 18 +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000 +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_SET(x) (((x) << 18) & 0x00fc0000) +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29 +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24 +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000 +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << 24) & 0x3f000000) +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MSB 30 +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_LSB 30 +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000 +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MSB 31 +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_LSB 31 +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000 +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH4 */ +#define PHY_ANALOG_SYNTH4_ADDRESS 0x0000008c +#define PHY_ANALOG_SYNTH4_OFFSET 0x0000008c +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MSB 0 +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_LSB 0 +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MASK 0x00000001 +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MSB 1 +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_LSB 1 +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MASK 0x00000002 +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MSB 3 +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_LSB 2 +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MASK 0x0000000c +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MSB 4 +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_LSB 4 +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MASK 0x00000010 +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MSB 5 +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_LSB 5 +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020 +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_SYNTH4_SDM_DITHER1_MSB 7 +#define PHY_ANALOG_SYNTH4_SDM_DITHER1_LSB 6 +#define PHY_ANALOG_SYNTH4_SDM_DITHER1_MASK 0x000000c0 +#define PHY_ANALOG_SYNTH4_SDM_DITHER1_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_ANALOG_SYNTH4_SDM_DITHER1_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_ANALOG_SYNTH4_SDM_MODE_MSB 8 +#define PHY_ANALOG_SYNTH4_SDM_MODE_LSB 8 +#define PHY_ANALOG_SYNTH4_SDM_MODE_MASK 0x00000100 +#define PHY_ANALOG_SYNTH4_SDM_MODE_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_SYNTH4_SDM_MODE_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MSB 9 +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_LSB 9 +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MASK 0x00000200 +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_SYNTH4_RESET_PRESC_MSB 10 +#define PHY_ANALOG_SYNTH4_RESET_PRESC_LSB 10 +#define PHY_ANALOG_SYNTH4_RESET_PRESC_MASK 0x00000400 +#define PHY_ANALOG_SYNTH4_RESET_PRESC_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH4_RESET_PRESC_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH4_PRESCSEL_MSB 12 +#define PHY_ANALOG_SYNTH4_PRESCSEL_LSB 11 +#define PHY_ANALOG_SYNTH4_PRESCSEL_MASK 0x00001800 +#define PHY_ANALOG_SYNTH4_PRESCSEL_GET(x) (((x) & 0x00001800) >> 11) +#define PHY_ANALOG_SYNTH4_PRESCSEL_SET(x) (((x) << 11) & 0x00001800) +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MSB 13 +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_LSB 13 +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MASK 0x00002000 +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MSB 14 +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_LSB 14 +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MASK 0x00004000 +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MSB 15 +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_LSB 15 +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MASK 0x00008000 +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MSB 16 +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_LSB 16 +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MASK 0x00010000 +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MSB 17 +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_LSB 17 +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MASK 0x00020000 +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MSB 25 +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_LSB 18 +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000 +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_GET(x) (((x) & 0x03fc0000) >> 18) +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_SET(x) (((x) << 18) & 0x03fc0000) +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MSB 26 +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_LSB 26 +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MASK 0x04000000 +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MSB 27 +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_LSB 27 +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MASK 0x08000000 +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28 +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28 +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000 +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MSB 29 +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_LSB 29 +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000 +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MSB 30 +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_LSB 30 +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MASK 0x40000000 +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31 +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31 +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000 +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH5 */ +#define PHY_ANALOG_SYNTH5_ADDRESS 0x00000090 +#define PHY_ANALOG_SYNTH5_OFFSET 0x00000090 +#define PHY_ANALOG_SYNTH5_VCOBIAS_MSB 1 +#define PHY_ANALOG_SYNTH5_VCOBIAS_LSB 0 +#define PHY_ANALOG_SYNTH5_VCOBIAS_MASK 0x00000003 +#define PHY_ANALOG_SYNTH5_VCOBIAS_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_SYNTH5_VCOBIAS_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MSB 4 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_LSB 2 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MASK 0x0000001c +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MSB 7 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_LSB 5 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MASK 0x000000e0 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MSB 10 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_LSB 8 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MASK 0x00000700 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MSB 13 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_LSB 11 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MASK 0x00003800 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MSB 14 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_LSB 14 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MASK 0x00004000 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MSB 17 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_LSB 15 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MASK 0x00038000 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MSB 20 +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_LSB 18 +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MASK 0x001c0000 +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_GET(x) (((x) & 0x001c0000) >> 18) +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_SET(x) (((x) << 18) & 0x001c0000) +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MSB 23 +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_LSB 21 +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MASK 0x00e00000 +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_GET(x) (((x) & 0x00e00000) >> 21) +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_SET(x) (((x) << 21) & 0x00e00000) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MSB 26 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_LSB 24 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MASK 0x07000000 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_SET(x) (((x) << 24) & 0x07000000) +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MSB 29 +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_LSB 27 +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MASK 0x38000000 +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_GET(x) (((x) & 0x38000000) >> 27) +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_SET(x) (((x) << 27) & 0x38000000) +#define PHY_ANALOG_SYNTH5_SDM_DITHER2_MSB 31 +#define PHY_ANALOG_SYNTH5_SDM_DITHER2_LSB 30 +#define PHY_ANALOG_SYNTH5_SDM_DITHER2_MASK 0xc0000000 +#define PHY_ANALOG_SYNTH5_SDM_DITHER2_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_ANALOG_SYNTH5_SDM_DITHER2_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for SYNTH6 */ +#define PHY_ANALOG_SYNTH6_ADDRESS 0x00000094 +#define PHY_ANALOG_SYNTH6_OFFSET 0x00000094 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MSB 1 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_LSB 0 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MASK 0x00000003 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_SYNTH6_LOOP_IP_MSB 8 +#define PHY_ANALOG_SYNTH6_LOOP_IP_LSB 2 +#define PHY_ANALOG_SYNTH6_LOOP_IP_MASK 0x000001fc +#define PHY_ANALOG_SYNTH6_LOOP_IP_GET(x) (((x) & 0x000001fc) >> 2) +#define PHY_ANALOG_SYNTH6_VC2LOW_MSB 9 +#define PHY_ANALOG_SYNTH6_VC2LOW_LSB 9 +#define PHY_ANALOG_SYNTH6_VC2LOW_MASK 0x00000200 +#define PHY_ANALOG_SYNTH6_VC2LOW_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_SYNTH6_VC2HIGH_MSB 10 +#define PHY_ANALOG_SYNTH6_VC2HIGH_LSB 10 +#define PHY_ANALOG_SYNTH6_VC2HIGH_MASK 0x00000400 +#define PHY_ANALOG_SYNTH6_VC2HIGH_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MSB 11 +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_LSB 11 +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MASK 0x00000800 +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MSB 12 +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_LSB 12 +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MASK 0x00001000 +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_SYNTH6_RESET_PFD_MSB 13 +#define PHY_ANALOG_SYNTH6_RESET_PFD_LSB 13 +#define PHY_ANALOG_SYNTH6_RESET_PFD_MASK 0x00002000 +#define PHY_ANALOG_SYNTH6_RESET_PFD_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_SYNTH6_RESET_RFD_MSB 14 +#define PHY_ANALOG_SYNTH6_RESET_RFD_LSB 14 +#define PHY_ANALOG_SYNTH6_RESET_RFD_MASK 0x00004000 +#define PHY_ANALOG_SYNTH6_RESET_RFD_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH6_SHORT_R_MSB 15 +#define PHY_ANALOG_SYNTH6_SHORT_R_LSB 15 +#define PHY_ANALOG_SYNTH6_SHORT_R_MASK 0x00008000 +#define PHY_ANALOG_SYNTH6_SHORT_R_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MSB 23 +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_LSB 16 +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MASK 0x00ff0000 +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_SYNTH6_PIN_VC_MSB 24 +#define PHY_ANALOG_SYNTH6_PIN_VC_LSB 24 +#define PHY_ANALOG_SYNTH6_PIN_VC_MASK 0x01000000 +#define PHY_ANALOG_SYNTH6_PIN_VC_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MSB 25 +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_LSB 25 +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MASK 0x02000000 +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MSB 26 +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_LSB 26 +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MASK 0x04000000 +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MSB 30 +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_LSB 27 +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MASK 0x78000000 +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_SYNTH6_SYNTH_ON_MSB 31 +#define PHY_ANALOG_SYNTH6_SYNTH_ON_LSB 31 +#define PHY_ANALOG_SYNTH6_SYNTH_ON_MASK 0x80000000 +#define PHY_ANALOG_SYNTH6_SYNTH_ON_GET(x) (((x) & 0x80000000) >> 31) + +/* macros for SYNTH7 */ +#define PHY_ANALOG_SYNTH7_ADDRESS 0x00000098 +#define PHY_ANALOG_SYNTH7_OFFSET 0x00000098 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MSB 0 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_LSB 0 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MASK 0x00000001 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MSB 1 +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_LSB 1 +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MASK 0x00000002 +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_SYNTH7_CHANFRAC_MSB 18 +#define PHY_ANALOG_SYNTH7_CHANFRAC_LSB 2 +#define PHY_ANALOG_SYNTH7_CHANFRAC_MASK 0x0007fffc +#define PHY_ANALOG_SYNTH7_CHANFRAC_GET(x) (((x) & 0x0007fffc) >> 2) +#define PHY_ANALOG_SYNTH7_CHANFRAC_SET(x) (((x) << 2) & 0x0007fffc) +#define PHY_ANALOG_SYNTH7_CHANSEL_MSB 27 +#define PHY_ANALOG_SYNTH7_CHANSEL_LSB 19 +#define PHY_ANALOG_SYNTH7_CHANSEL_MASK 0x0ff80000 +#define PHY_ANALOG_SYNTH7_CHANSEL_GET(x) (((x) & 0x0ff80000) >> 19) +#define PHY_ANALOG_SYNTH7_CHANSEL_SET(x) (((x) << 19) & 0x0ff80000) +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MSB 29 +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_LSB 28 +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MASK 0x30000000 +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_GET(x) (((x) & 0x30000000) >> 28) +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_SET(x) (((x) << 28) & 0x30000000) +#define PHY_ANALOG_SYNTH7_FRACMODE_MSB 30 +#define PHY_ANALOG_SYNTH7_FRACMODE_LSB 30 +#define PHY_ANALOG_SYNTH7_FRACMODE_MASK 0x40000000 +#define PHY_ANALOG_SYNTH7_FRACMODE_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH7_FRACMODE_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MSB 31 +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_LSB 31 +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MASK 0x80000000 +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH8 */ +#define PHY_ANALOG_SYNTH8_ADDRESS 0x0000009c +#define PHY_ANALOG_SYNTH8_OFFSET 0x0000009c +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MSB 0 +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_LSB 0 +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MASK 0x00000001 +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MSB 7 +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_LSB 1 +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MASK 0x000000fe +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_GET(x) (((x) & 0x000000fe) >> 1) +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_SET(x) (((x) << 1) & 0x000000fe) +#define PHY_ANALOG_SYNTH8_LOOP_CSB_MSB 11 +#define PHY_ANALOG_SYNTH8_LOOP_CSB_LSB 8 +#define PHY_ANALOG_SYNTH8_LOOP_CSB_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH8_LOOP_CSB_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH8_LOOP_CSB_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH8_LOOP_RSB_MSB 16 +#define PHY_ANALOG_SYNTH8_LOOP_RSB_LSB 12 +#define PHY_ANALOG_SYNTH8_LOOP_RSB_MASK 0x0001f000 +#define PHY_ANALOG_SYNTH8_LOOP_RSB_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_ANALOG_SYNTH8_LOOP_RSB_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_ANALOG_SYNTH8_LOOP_CPB_MSB 21 +#define PHY_ANALOG_SYNTH8_LOOP_CPB_LSB 17 +#define PHY_ANALOG_SYNTH8_LOOP_CPB_MASK 0x003e0000 +#define PHY_ANALOG_SYNTH8_LOOP_CPB_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_ANALOG_SYNTH8_LOOP_CPB_SET(x) (((x) << 17) & 0x003e0000) +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MSB 26 +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_LSB 22 +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH8_REFDIVB_MSB 31 +#define PHY_ANALOG_SYNTH8_REFDIVB_LSB 27 +#define PHY_ANALOG_SYNTH8_REFDIVB_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH8_REFDIVB_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH8_REFDIVB_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH9 */ +#define PHY_ANALOG_SYNTH9_ADDRESS 0x000000a0 +#define PHY_ANALOG_SYNTH9_OFFSET 0x000000a0 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MSB 0 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_LSB 0 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MASK 0x00000001 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MSB 3 +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_LSB 1 +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MASK 0x0000000e +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MSB 7 +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_LSB 4 +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MASK 0x000000f0 +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MSB 11 +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_LSB 8 +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MSB 16 +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_LSB 12 +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MASK 0x0001f000 +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MSB 21 +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_LSB 17 +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MASK 0x003e0000 +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_SET(x) (((x) << 17) & 0x003e0000) +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MSB 26 +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_LSB 22 +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH9_REFDIVA_MSB 31 +#define PHY_ANALOG_SYNTH9_REFDIVA_LSB 27 +#define PHY_ANALOG_SYNTH9_REFDIVA_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH9_REFDIVA_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH9_REFDIVA_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH10 */ +#define PHY_ANALOG_SYNTH10_ADDRESS 0x000000a4 +#define PHY_ANALOG_SYNTH10_OFFSET 0x000000a4 +#define PHY_ANALOG_SYNTH10_SPARE10A_MSB 1 +#define PHY_ANALOG_SYNTH10_SPARE10A_LSB 0 +#define PHY_ANALOG_SYNTH10_SPARE10A_MASK 0x00000003 +#define PHY_ANALOG_SYNTH10_SPARE10A_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_SYNTH10_SPARE10A_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MSB 4 +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_LSB 2 +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MASK 0x0000001c +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MSB 7 +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_LSB 5 +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MASK 0x000000e0 +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MSB 10 +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_LSB 8 +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MASK 0x00000700 +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MSB 13 +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_LSB 11 +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MASK 0x00003800 +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MSB 17 +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_LSB 14 +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MASK 0x0003c000 +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_GET(x) (((x) & 0x0003c000) >> 14) +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_SET(x) (((x) << 14) & 0x0003c000) +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MSB 21 +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_LSB 18 +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MASK 0x003c0000 +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_GET(x) (((x) & 0x003c0000) >> 18) +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_SET(x) (((x) << 18) & 0x003c0000) +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MSB 26 +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_LSB 22 +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MSB 31 +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_LSB 27 +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH11 */ +#define PHY_ANALOG_SYNTH11_ADDRESS 0x000000a8 +#define PHY_ANALOG_SYNTH11_OFFSET 0x000000a8 +#define PHY_ANALOG_SYNTH11_SPARE11A_MSB 4 +#define PHY_ANALOG_SYNTH11_SPARE11A_LSB 0 +#define PHY_ANALOG_SYNTH11_SPARE11A_MASK 0x0000001f +#define PHY_ANALOG_SYNTH11_SPARE11A_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_SYNTH11_SPARE11A_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MSB 5 +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_LSB 5 +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MASK 0x00000020 +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_SYNTH11_LOREFSEL_MSB 7 +#define PHY_ANALOG_SYNTH11_LOREFSEL_LSB 6 +#define PHY_ANALOG_SYNTH11_LOREFSEL_MASK 0x000000c0 +#define PHY_ANALOG_SYNTH11_LOREFSEL_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_ANALOG_SYNTH11_LOREFSEL_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MSB 9 +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_LSB 8 +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MASK 0x00000300 +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MSB 10 +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_LSB 10 +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MASK 0x00000400 +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MSB 13 +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_LSB 11 +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MASK 0x00003800 +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MSB 17 +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_LSB 14 +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MASK 0x0003c000 +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_GET(x) (((x) & 0x0003c000) >> 14) +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_SET(x) (((x) << 14) & 0x0003c000) +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MSB 21 +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_LSB 18 +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MASK 0x003c0000 +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_GET(x) (((x) & 0x003c0000) >> 18) +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_SET(x) (((x) << 18) & 0x003c0000) +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MSB 26 +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_LSB 22 +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MSB 31 +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_LSB 27 +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH12 */ +#define PHY_ANALOG_SYNTH12_ADDRESS 0x000000ac +#define PHY_ANALOG_SYNTH12_OFFSET 0x000000ac +#define PHY_ANALOG_SYNTH12_SPARE12A_MSB 9 +#define PHY_ANALOG_SYNTH12_SPARE12A_LSB 0 +#define PHY_ANALOG_SYNTH12_SPARE12A_MASK 0x000003ff +#define PHY_ANALOG_SYNTH12_SPARE12A_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_ANALOG_SYNTH12_SPARE12A_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_MSB 13 +#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_LSB 10 +#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_MASK 0x00003c00 +#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_GET(x) (((x) & 0x00003c00) >> 10) +#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_SET(x) (((x) << 10) & 0x00003c00) +#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_MSB 14 +#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_LSB 14 +#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_MASK 0x00004000 +#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_MSB 16 +#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_LSB 15 +#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_MASK 0x00018000 +#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_GET(x) (((x) & 0x00018000) >> 15) +#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_SET(x) (((x) << 15) & 0x00018000) +#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_MSB 17 +#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_LSB 17 +#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_MASK 0x00020000 +#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_SYNTH12_STRCONT_MSB 18 +#define PHY_ANALOG_SYNTH12_STRCONT_LSB 18 +#define PHY_ANALOG_SYNTH12_STRCONT_MASK 0x00040000 +#define PHY_ANALOG_SYNTH12_STRCONT_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_SYNTH12_STRCONT_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_SYNTH12_VREFMUL3_MSB 22 +#define PHY_ANALOG_SYNTH12_VREFMUL3_LSB 19 +#define PHY_ANALOG_SYNTH12_VREFMUL3_MASK 0x00780000 +#define PHY_ANALOG_SYNTH12_VREFMUL3_GET(x) (((x) & 0x00780000) >> 19) +#define PHY_ANALOG_SYNTH12_VREFMUL3_SET(x) (((x) << 19) & 0x00780000) +#define PHY_ANALOG_SYNTH12_VREFMUL2_MSB 26 +#define PHY_ANALOG_SYNTH12_VREFMUL2_LSB 23 +#define PHY_ANALOG_SYNTH12_VREFMUL2_MASK 0x07800000 +#define PHY_ANALOG_SYNTH12_VREFMUL2_GET(x) (((x) & 0x07800000) >> 23) +#define PHY_ANALOG_SYNTH12_VREFMUL2_SET(x) (((x) << 23) & 0x07800000) +#define PHY_ANALOG_SYNTH12_VREFMUL1_MSB 30 +#define PHY_ANALOG_SYNTH12_VREFMUL1_LSB 27 +#define PHY_ANALOG_SYNTH12_VREFMUL1_MASK 0x78000000 +#define PHY_ANALOG_SYNTH12_VREFMUL1_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_SYNTH12_VREFMUL1_SET(x) (((x) << 27) & 0x78000000) +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MSB 31 +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_LSB 31 +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MASK 0x80000000 +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH13 */ +#define PHY_ANALOG_SYNTH13_ADDRESS 0x000000b0 +#define PHY_ANALOG_SYNTH13_OFFSET 0x000000b0 +#define PHY_ANALOG_SYNTH13_SPARE13A_MSB 0 +#define PHY_ANALOG_SYNTH13_SPARE13A_LSB 0 +#define PHY_ANALOG_SYNTH13_SPARE13A_MASK 0x00000001 +#define PHY_ANALOG_SYNTH13_SPARE13A_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH13_SPARE13A_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_MSB 3 +#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_LSB 1 +#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_MASK 0x0000000e +#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_MSB 7 +#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_LSB 4 +#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_MASK 0x000000f0 +#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_MSB 11 +#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_LSB 8 +#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_MSB 16 +#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_LSB 12 +#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_MASK 0x0001f000 +#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_MSB 21 +#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_LSB 17 +#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_MASK 0x003e0000 +#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_SET(x) (((x) << 17) & 0x003e0000) +#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_MSB 26 +#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_LSB 22 +#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_MSB 31 +#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_LSB 27 +#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH14 */ +#define PHY_ANALOG_SYNTH14_ADDRESS 0x000000b4 +#define PHY_ANALOG_SYNTH14_OFFSET 0x000000b4 +#define PHY_ANALOG_SYNTH14_SPARE14A_MSB 1 +#define PHY_ANALOG_SYNTH14_SPARE14A_LSB 0 +#define PHY_ANALOG_SYNTH14_SPARE14A_MASK 0x00000003 +#define PHY_ANALOG_SYNTH14_SPARE14A_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_SYNTH14_SPARE14A_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_MSB 3 +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_LSB 2 +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_MASK 0x0000000c +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_MSB 5 +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_LSB 4 +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_MASK 0x00000030 +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_SET(x) (((x) << 4) & 0x00000030) +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_MSB 7 +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_LSB 6 +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_MASK 0x000000c0 +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_MSB 9 +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_LSB 8 +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_MASK 0x00000300 +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_MSB 10 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_LSB 10 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_MASK 0x00000400 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_MSB 11 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_LSB 11 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_MASK 0x00000800 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_MSB 12 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_LSB 12 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_MASK 0x00001000 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_MSB 13 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_LSB 13 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_MASK 0x00002000 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_MSB 16 +#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_LSB 14 +#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_MASK 0x0001c000 +#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_MSB 19 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_LSB 17 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_MASK 0x000e0000 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_MSB 22 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_LSB 20 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_MASK 0x00700000 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_MSB 25 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_LSB 23 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_MASK 0x03800000 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_MSB 28 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_LSB 26 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_MASK 0x1c000000 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_MSB 31 +#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_LSB 29 +#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_MASK 0xe0000000 +#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for BIAS1 */ +#define PHY_ANALOG_BIAS1_ADDRESS 0x000000c0 +#define PHY_ANALOG_BIAS1_OFFSET 0x000000c0 +#define PHY_ANALOG_BIAS1_SPARE1_MSB 6 +#define PHY_ANALOG_BIAS1_SPARE1_LSB 0 +#define PHY_ANALOG_BIAS1_SPARE1_MASK 0x0000007f +#define PHY_ANALOG_BIAS1_SPARE1_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_BIAS1_SPARE1_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MSB 9 +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_LSB 7 +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MASK 0x00000380 +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MSB 12 +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_LSB 10 +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MASK 0x00001c00 +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_GET(x) (((x) & 0x00001c00) >> 10) +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_SET(x) (((x) << 10) & 0x00001c00) +#define PHY_ANALOG_BIAS1_PWD_IC25BB_MSB 15 +#define PHY_ANALOG_BIAS1_PWD_IC25BB_LSB 13 +#define PHY_ANALOG_BIAS1_PWD_IC25BB_MASK 0x0000e000 +#define PHY_ANALOG_BIAS1_PWD_IC25BB_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_BIAS1_PWD_IC25BB_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MSB 18 +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_LSB 16 +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MASK 0x00070000 +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_SET(x) (((x) << 16) & 0x00070000) +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MSB 21 +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_LSB 19 +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MASK 0x00380000 +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MSB 24 +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_LSB 22 +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MASK 0x01c00000 +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_GET(x) (((x) & 0x01c00000) >> 22) +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_SET(x) (((x) << 22) & 0x01c00000) +#define PHY_ANALOG_BIAS1_BIAS_SEL_MSB 31 +#define PHY_ANALOG_BIAS1_BIAS_SEL_LSB 25 +#define PHY_ANALOG_BIAS1_BIAS_SEL_MASK 0xfe000000 +#define PHY_ANALOG_BIAS1_BIAS_SEL_GET(x) (((x) & 0xfe000000) >> 25) +#define PHY_ANALOG_BIAS1_BIAS_SEL_SET(x) (((x) << 25) & 0xfe000000) + +/* macros for BIAS2 */ +#define PHY_ANALOG_BIAS2_ADDRESS 0x000000c4 +#define PHY_ANALOG_BIAS2_OFFSET 0x000000c4 +#define PHY_ANALOG_BIAS2_SPARE2_MSB 4 +#define PHY_ANALOG_BIAS2_SPARE2_LSB 0 +#define PHY_ANALOG_BIAS2_SPARE2_MASK 0x0000001f +#define PHY_ANALOG_BIAS2_SPARE2_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_BIAS2_SPARE2_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_BIAS2_PWD_IC25XPA_MSB 7 +#define PHY_ANALOG_BIAS2_PWD_IC25XPA_LSB 5 +#define PHY_ANALOG_BIAS2_PWD_IC25XPA_MASK 0x000000e0 +#define PHY_ANALOG_BIAS2_PWD_IC25XPA_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_BIAS2_PWD_IC25XPA_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MSB 10 +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_LSB 8 +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MASK 0x00000700 +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MSB 13 +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_LSB 11 +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MASK 0x00003800 +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MSB 16 +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_LSB 14 +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MASK 0x0001c000 +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_MSB 19 +#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_LSB 17 +#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_MASK 0x000e0000 +#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MSB 22 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_LSB 20 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MASK 0x00700000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MSB 25 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_LSB 23 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MASK 0x03800000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MSB 28 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_LSB 26 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MASK 0x1c000000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MSB 31 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_LSB 29 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MASK 0xe0000000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for BIAS3 */ +#define PHY_ANALOG_BIAS3_ADDRESS 0x000000c8 +#define PHY_ANALOG_BIAS3_OFFSET 0x000000c8 +#define PHY_ANALOG_BIAS3_SPARE3_MSB 1 +#define PHY_ANALOG_BIAS3_SPARE3_LSB 0 +#define PHY_ANALOG_BIAS3_SPARE3_MASK 0x00000003 +#define PHY_ANALOG_BIAS3_SPARE3_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_BIAS3_SPARE3_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_BIAS3_PWD_IR25SAR_MSB 4 +#define PHY_ANALOG_BIAS3_PWD_IR25SAR_LSB 2 +#define PHY_ANALOG_BIAS3_PWD_IR25SAR_MASK 0x0000001c +#define PHY_ANALOG_BIAS3_PWD_IR25SAR_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_BIAS3_PWD_IR25SAR_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MSB 7 +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_LSB 5 +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MASK 0x000000e0 +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MSB 10 +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_LSB 8 +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MASK 0x00000700 +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_MSB 13 +#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_LSB 11 +#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_MASK 0x00003800 +#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MSB 16 +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_LSB 14 +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MASK 0x0001c000 +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_BIAS3_PWD_IR25BB_MSB 19 +#define PHY_ANALOG_BIAS3_PWD_IR25BB_LSB 17 +#define PHY_ANALOG_BIAS3_PWD_IR25BB_MASK 0x000e0000 +#define PHY_ANALOG_BIAS3_PWD_IR25BB_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_BIAS3_PWD_IR25BB_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MSB 22 +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_LSB 20 +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MASK 0x00700000 +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MSB 25 +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_LSB 23 +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MASK 0x03800000 +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MSB 28 +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_LSB 26 +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MASK 0x1c000000 +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MSB 31 +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_LSB 29 +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MASK 0xe0000000 +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for BIAS4 */ +#define PHY_ANALOG_BIAS4_ADDRESS 0x000000cc +#define PHY_ANALOG_BIAS4_OFFSET 0x000000cc +#define PHY_ANALOG_BIAS4_SPARE4_MSB 10 +#define PHY_ANALOG_BIAS4_SPARE4_LSB 0 +#define PHY_ANALOG_BIAS4_SPARE4_MASK 0x000007ff +#define PHY_ANALOG_BIAS4_SPARE4_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_BIAS4_SPARE4_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_MSB 13 +#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_LSB 11 +#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_MASK 0x00003800 +#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MSB 16 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_LSB 14 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MASK 0x0001c000 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MSB 19 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_LSB 17 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MASK 0x000e0000 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_BIAS4_PWD_IR25XPA_MSB 22 +#define PHY_ANALOG_BIAS4_PWD_IR25XPA_LSB 20 +#define PHY_ANALOG_BIAS4_PWD_IR25XPA_MASK 0x00700000 +#define PHY_ANALOG_BIAS4_PWD_IR25XPA_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_BIAS4_PWD_IR25XPA_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MSB 25 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_LSB 23 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MASK 0x03800000 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MSB 28 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_LSB 26 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MASK 0x1c000000 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MSB 31 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_LSB 29 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MASK 0xe0000000 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for RXTX1 */ +#define PHY_ANALOG_RXTX1_ADDRESS 0x00000100 +#define PHY_ANALOG_RXTX1_OFFSET 0x00000100 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MSB 0 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_LSB 0 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MASK 0x00000001 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXTX1_MANRXGAIN_MSB 1 +#define PHY_ANALOG_RXTX1_MANRXGAIN_LSB 1 +#define PHY_ANALOG_RXTX1_MANRXGAIN_MASK 0x00000002 +#define PHY_ANALOG_RXTX1_MANRXGAIN_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXTX1_MANRXGAIN_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXTX1_AGC_DBDAC_MSB 5 +#define PHY_ANALOG_RXTX1_AGC_DBDAC_LSB 2 +#define PHY_ANALOG_RXTX1_AGC_DBDAC_MASK 0x0000003c +#define PHY_ANALOG_RXTX1_AGC_DBDAC_GET(x) (((x) & 0x0000003c) >> 2) +#define PHY_ANALOG_RXTX1_AGC_DBDAC_SET(x) (((x) << 2) & 0x0000003c) +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MSB 6 +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_LSB 6 +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MASK 0x00000040 +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_MSB 7 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_LSB 7 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_MASK 0x00000080 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MSB 8 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_LSB 8 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MASK 0x00000100 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MSB 11 +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_LSB 9 +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MASK 0x00000e00 +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_SET(x) (((x) << 9) & 0x00000e00) +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MSB 13 +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_LSB 12 +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MASK 0x00003000 +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_GET(x) (((x) & 0x00003000) >> 12) +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_SET(x) (((x) << 12) & 0x00003000) +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MSB 14 +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_LSB 14 +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MASK 0x00004000 +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RXTX1_PADRV2GN_MSB 18 +#define PHY_ANALOG_RXTX1_PADRV2GN_LSB 15 +#define PHY_ANALOG_RXTX1_PADRV2GN_MASK 0x00078000 +#define PHY_ANALOG_RXTX1_PADRV2GN_GET(x) (((x) & 0x00078000) >> 15) +#define PHY_ANALOG_RXTX1_PADRV2GN_SET(x) (((x) << 15) & 0x00078000) +#define PHY_ANALOG_RXTX1_PADRV3GN5G_MSB 22 +#define PHY_ANALOG_RXTX1_PADRV3GN5G_LSB 19 +#define PHY_ANALOG_RXTX1_PADRV3GN5G_MASK 0x00780000 +#define PHY_ANALOG_RXTX1_PADRV3GN5G_GET(x) (((x) & 0x00780000) >> 19) +#define PHY_ANALOG_RXTX1_PADRV3GN5G_SET(x) (((x) << 19) & 0x00780000) +#define PHY_ANALOG_RXTX1_PADRV4GN5G_MSB 26 +#define PHY_ANALOG_RXTX1_PADRV4GN5G_LSB 23 +#define PHY_ANALOG_RXTX1_PADRV4GN5G_MASK 0x07800000 +#define PHY_ANALOG_RXTX1_PADRV4GN5G_GET(x) (((x) & 0x07800000) >> 23) +#define PHY_ANALOG_RXTX1_PADRV4GN5G_SET(x) (((x) << 23) & 0x07800000) +#define PHY_ANALOG_RXTX1_TXBB_GC_MSB 30 +#define PHY_ANALOG_RXTX1_TXBB_GC_LSB 27 +#define PHY_ANALOG_RXTX1_TXBB_GC_MASK 0x78000000 +#define PHY_ANALOG_RXTX1_TXBB_GC_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_RXTX1_TXBB_GC_SET(x) (((x) << 27) & 0x78000000) +#define PHY_ANALOG_RXTX1_MANTXGAIN_MSB 31 +#define PHY_ANALOG_RXTX1_MANTXGAIN_LSB 31 +#define PHY_ANALOG_RXTX1_MANTXGAIN_MASK 0x80000000 +#define PHY_ANALOG_RXTX1_MANTXGAIN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXTX1_MANTXGAIN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for RXTX2 */ +#define PHY_ANALOG_RXTX2_ADDRESS 0x00000104 +#define PHY_ANALOG_RXTX2_OFFSET 0x00000104 +#define PHY_ANALOG_RXTX2_BMODE_MSB 0 +#define PHY_ANALOG_RXTX2_BMODE_LSB 0 +#define PHY_ANALOG_RXTX2_BMODE_MASK 0x00000001 +#define PHY_ANALOG_RXTX2_BMODE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXTX2_BMODE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXTX2_BMODE_OVR_MSB 1 +#define PHY_ANALOG_RXTX2_BMODE_OVR_LSB 1 +#define PHY_ANALOG_RXTX2_BMODE_OVR_MASK 0x00000002 +#define PHY_ANALOG_RXTX2_BMODE_OVR_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXTX2_BMODE_OVR_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXTX2_SYNTHON_MSB 2 +#define PHY_ANALOG_RXTX2_SYNTHON_LSB 2 +#define PHY_ANALOG_RXTX2_SYNTHON_MASK 0x00000004 +#define PHY_ANALOG_RXTX2_SYNTHON_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_RXTX2_SYNTHON_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MSB 3 +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_LSB 3 +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MASK 0x00000008 +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RXTX2_BW_ST_MSB 5 +#define PHY_ANALOG_RXTX2_BW_ST_LSB 4 +#define PHY_ANALOG_RXTX2_BW_ST_MASK 0x00000030 +#define PHY_ANALOG_RXTX2_BW_ST_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_ANALOG_RXTX2_BW_ST_SET(x) (((x) << 4) & 0x00000030) +#define PHY_ANALOG_RXTX2_BW_ST_OVR_MSB 6 +#define PHY_ANALOG_RXTX2_BW_ST_OVR_LSB 6 +#define PHY_ANALOG_RXTX2_BW_ST_OVR_MASK 0x00000040 +#define PHY_ANALOG_RXTX2_BW_ST_OVR_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXTX2_BW_ST_OVR_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXTX2_TXON_MSB 7 +#define PHY_ANALOG_RXTX2_TXON_LSB 7 +#define PHY_ANALOG_RXTX2_TXON_MASK 0x00000080 +#define PHY_ANALOG_RXTX2_TXON_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXTX2_TXON_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXTX2_TXON_OVR_MSB 8 +#define PHY_ANALOG_RXTX2_TXON_OVR_LSB 8 +#define PHY_ANALOG_RXTX2_TXON_OVR_MASK 0x00000100 +#define PHY_ANALOG_RXTX2_TXON_OVR_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXTX2_TXON_OVR_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXTX2_PAON_MSB 9 +#define PHY_ANALOG_RXTX2_PAON_LSB 9 +#define PHY_ANALOG_RXTX2_PAON_MASK 0x00000200 +#define PHY_ANALOG_RXTX2_PAON_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RXTX2_PAON_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RXTX2_PAON_OVR_MSB 10 +#define PHY_ANALOG_RXTX2_PAON_OVR_LSB 10 +#define PHY_ANALOG_RXTX2_PAON_OVR_MASK 0x00000400 +#define PHY_ANALOG_RXTX2_PAON_OVR_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RXTX2_PAON_OVR_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RXTX2_RXON_MSB 11 +#define PHY_ANALOG_RXTX2_RXON_LSB 11 +#define PHY_ANALOG_RXTX2_RXON_MASK 0x00000800 +#define PHY_ANALOG_RXTX2_RXON_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_RXTX2_RXON_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_RXTX2_RXON_OVR_MSB 12 +#define PHY_ANALOG_RXTX2_RXON_OVR_LSB 12 +#define PHY_ANALOG_RXTX2_RXON_OVR_MASK 0x00001000 +#define PHY_ANALOG_RXTX2_RXON_OVR_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_RXTX2_RXON_OVR_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_RXTX2_AGCON_MSB 13 +#define PHY_ANALOG_RXTX2_AGCON_LSB 13 +#define PHY_ANALOG_RXTX2_AGCON_MASK 0x00002000 +#define PHY_ANALOG_RXTX2_AGCON_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_RXTX2_AGCON_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_RXTX2_AGCON_OVR_MSB 14 +#define PHY_ANALOG_RXTX2_AGCON_OVR_LSB 14 +#define PHY_ANALOG_RXTX2_AGCON_OVR_MASK 0x00004000 +#define PHY_ANALOG_RXTX2_AGCON_OVR_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RXTX2_AGCON_OVR_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RXTX2_TXMOD_MSB 17 +#define PHY_ANALOG_RXTX2_TXMOD_LSB 15 +#define PHY_ANALOG_RXTX2_TXMOD_MASK 0x00038000 +#define PHY_ANALOG_RXTX2_TXMOD_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_RXTX2_TXMOD_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_RXTX2_TXMOD_OVR_MSB 18 +#define PHY_ANALOG_RXTX2_TXMOD_OVR_LSB 18 +#define PHY_ANALOG_RXTX2_TXMOD_OVR_MASK 0x00040000 +#define PHY_ANALOG_RXTX2_TXMOD_OVR_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_RXTX2_TXMOD_OVR_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MSB 21 +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_LSB 19 +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MASK 0x00380000 +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MSB 23 +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_LSB 22 +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MASK 0x00c00000 +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_ANALOG_RXTX2_MXRGAIN_MSB 25 +#define PHY_ANALOG_RXTX2_MXRGAIN_LSB 24 +#define PHY_ANALOG_RXTX2_MXRGAIN_MASK 0x03000000 +#define PHY_ANALOG_RXTX2_MXRGAIN_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_ANALOG_RXTX2_MXRGAIN_SET(x) (((x) << 24) & 0x03000000) +#define PHY_ANALOG_RXTX2_VGAGAIN_MSB 28 +#define PHY_ANALOG_RXTX2_VGAGAIN_LSB 26 +#define PHY_ANALOG_RXTX2_VGAGAIN_MASK 0x1c000000 +#define PHY_ANALOG_RXTX2_VGAGAIN_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_RXTX2_VGAGAIN_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_RXTX2_LNAGAIN_MSB 31 +#define PHY_ANALOG_RXTX2_LNAGAIN_LSB 29 +#define PHY_ANALOG_RXTX2_LNAGAIN_MASK 0xe0000000 +#define PHY_ANALOG_RXTX2_LNAGAIN_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_RXTX2_LNAGAIN_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for RXTX3 */ +#define PHY_ANALOG_RXTX3_ADDRESS 0x00000108 +#define PHY_ANALOG_RXTX3_OFFSET 0x00000108 +#define PHY_ANALOG_RXTX3_SPARE3_MSB 2 +#define PHY_ANALOG_RXTX3_SPARE3_LSB 0 +#define PHY_ANALOG_RXTX3_SPARE3_MASK 0x00000007 +#define PHY_ANALOG_RXTX3_SPARE3_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_RXTX3_SPARE3_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_RXTX3_SPURON_MSB 3 +#define PHY_ANALOG_RXTX3_SPURON_LSB 3 +#define PHY_ANALOG_RXTX3_SPURON_MASK 0x00000008 +#define PHY_ANALOG_RXTX3_SPURON_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RXTX3_SPURON_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_MSB 4 +#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_LSB 4 +#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_MASK 0x00000010 +#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RXTX3_DACFULLSCALE_MSB 5 +#define PHY_ANALOG_RXTX3_DACFULLSCALE_LSB 5 +#define PHY_ANALOG_RXTX3_DACFULLSCALE_MASK 0x00000020 +#define PHY_ANALOG_RXTX3_DACFULLSCALE_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_RXTX3_DACFULLSCALE_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_RXTX3_ADCSHORT_MSB 6 +#define PHY_ANALOG_RXTX3_ADCSHORT_LSB 6 +#define PHY_ANALOG_RXTX3_ADCSHORT_MASK 0x00000040 +#define PHY_ANALOG_RXTX3_ADCSHORT_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXTX3_ADCSHORT_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXTX3_DACPWD_MSB 7 +#define PHY_ANALOG_RXTX3_DACPWD_LSB 7 +#define PHY_ANALOG_RXTX3_DACPWD_MASK 0x00000080 +#define PHY_ANALOG_RXTX3_DACPWD_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXTX3_DACPWD_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXTX3_DACPWD_OVR_MSB 8 +#define PHY_ANALOG_RXTX3_DACPWD_OVR_LSB 8 +#define PHY_ANALOG_RXTX3_DACPWD_OVR_MASK 0x00000100 +#define PHY_ANALOG_RXTX3_DACPWD_OVR_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXTX3_DACPWD_OVR_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXTX3_ADCPWD_MSB 9 +#define PHY_ANALOG_RXTX3_ADCPWD_LSB 9 +#define PHY_ANALOG_RXTX3_ADCPWD_MASK 0x00000200 +#define PHY_ANALOG_RXTX3_ADCPWD_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RXTX3_ADCPWD_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MSB 10 +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_LSB 10 +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MASK 0x00000400 +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RXTX3_AGC_CALDAC_MSB 16 +#define PHY_ANALOG_RXTX3_AGC_CALDAC_LSB 11 +#define PHY_ANALOG_RXTX3_AGC_CALDAC_MASK 0x0001f800 +#define PHY_ANALOG_RXTX3_AGC_CALDAC_GET(x) (((x) & 0x0001f800) >> 11) +#define PHY_ANALOG_RXTX3_AGC_CALDAC_SET(x) (((x) << 11) & 0x0001f800) +#define PHY_ANALOG_RXTX3_AGC_CAL_MSB 17 +#define PHY_ANALOG_RXTX3_AGC_CAL_LSB 17 +#define PHY_ANALOG_RXTX3_AGC_CAL_MASK 0x00020000 +#define PHY_ANALOG_RXTX3_AGC_CAL_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_RXTX3_AGC_CAL_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MSB 18 +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_LSB 18 +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MASK 0x00040000 +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_RXTX3_LOFORCEDON_MSB 19 +#define PHY_ANALOG_RXTX3_LOFORCEDON_LSB 19 +#define PHY_ANALOG_RXTX3_LOFORCEDON_MASK 0x00080000 +#define PHY_ANALOG_RXTX3_LOFORCEDON_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_RXTX3_LOFORCEDON_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_RXTX3_CALRESIDUE_MSB 20 +#define PHY_ANALOG_RXTX3_CALRESIDUE_LSB 20 +#define PHY_ANALOG_RXTX3_CALRESIDUE_MASK 0x00100000 +#define PHY_ANALOG_RXTX3_CALRESIDUE_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_RXTX3_CALRESIDUE_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MSB 21 +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_LSB 21 +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MASK 0x00200000 +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_RXTX3_CALFC_MSB 22 +#define PHY_ANALOG_RXTX3_CALFC_LSB 22 +#define PHY_ANALOG_RXTX3_CALFC_MASK 0x00400000 +#define PHY_ANALOG_RXTX3_CALFC_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_RXTX3_CALFC_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_RXTX3_CALFC_OVR_MSB 23 +#define PHY_ANALOG_RXTX3_CALFC_OVR_LSB 23 +#define PHY_ANALOG_RXTX3_CALFC_OVR_MASK 0x00800000 +#define PHY_ANALOG_RXTX3_CALFC_OVR_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_RXTX3_CALFC_OVR_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_RXTX3_CALTX_MSB 24 +#define PHY_ANALOG_RXTX3_CALTX_LSB 24 +#define PHY_ANALOG_RXTX3_CALTX_MASK 0x01000000 +#define PHY_ANALOG_RXTX3_CALTX_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_RXTX3_CALTX_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_RXTX3_CALTX_OVR_MSB 25 +#define PHY_ANALOG_RXTX3_CALTX_OVR_LSB 25 +#define PHY_ANALOG_RXTX3_CALTX_OVR_MASK 0x02000000 +#define PHY_ANALOG_RXTX3_CALTX_OVR_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_RXTX3_CALTX_OVR_SET(x) (((x) << 25) & 0x02000000) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_MSB 26 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_LSB 26 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_MASK 0x04000000 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MSB 27 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_LSB 27 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MASK 0x08000000 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_RXTX3_CALPA_MSB 28 +#define PHY_ANALOG_RXTX3_CALPA_LSB 28 +#define PHY_ANALOG_RXTX3_CALPA_MASK 0x10000000 +#define PHY_ANALOG_RXTX3_CALPA_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_RXTX3_CALPA_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_RXTX3_CALPA_OVR_MSB 29 +#define PHY_ANALOG_RXTX3_CALPA_OVR_LSB 29 +#define PHY_ANALOG_RXTX3_CALPA_OVR_MASK 0x20000000 +#define PHY_ANALOG_RXTX3_CALPA_OVR_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_RXTX3_CALPA_OVR_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_RXTX3_TURBOADC_MSB 30 +#define PHY_ANALOG_RXTX3_TURBOADC_LSB 30 +#define PHY_ANALOG_RXTX3_TURBOADC_MASK 0x40000000 +#define PHY_ANALOG_RXTX3_TURBOADC_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_RXTX3_TURBOADC_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_RXTX3_TURBOADC_OVR_MSB 31 +#define PHY_ANALOG_RXTX3_TURBOADC_OVR_LSB 31 +#define PHY_ANALOG_RXTX3_TURBOADC_OVR_MASK 0x80000000 +#define PHY_ANALOG_RXTX3_TURBOADC_OVR_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXTX3_TURBOADC_OVR_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB1 */ +#define PHY_ANALOG_BB1_ADDRESS 0x00000140 +#define PHY_ANALOG_BB1_OFFSET 0x00000140 +#define PHY_ANALOG_BB1_I2V_CURR2X_MSB 0 +#define PHY_ANALOG_BB1_I2V_CURR2X_LSB 0 +#define PHY_ANALOG_BB1_I2V_CURR2X_MASK 0x00000001 +#define PHY_ANALOG_BB1_I2V_CURR2X_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_BB1_I2V_CURR2X_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_BB1_ENABLE_LOQ_MSB 1 +#define PHY_ANALOG_BB1_ENABLE_LOQ_LSB 1 +#define PHY_ANALOG_BB1_ENABLE_LOQ_MASK 0x00000002 +#define PHY_ANALOG_BB1_ENABLE_LOQ_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_BB1_ENABLE_LOQ_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_BB1_FORCE_LOQ_MSB 2 +#define PHY_ANALOG_BB1_FORCE_LOQ_LSB 2 +#define PHY_ANALOG_BB1_FORCE_LOQ_MASK 0x00000004 +#define PHY_ANALOG_BB1_FORCE_LOQ_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_BB1_FORCE_LOQ_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_BB1_ENABLE_NOTCH_MSB 3 +#define PHY_ANALOG_BB1_ENABLE_NOTCH_LSB 3 +#define PHY_ANALOG_BB1_ENABLE_NOTCH_MASK 0x00000008 +#define PHY_ANALOG_BB1_ENABLE_NOTCH_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_BB1_ENABLE_NOTCH_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_BB1_FORCE_NOTCH_MSB 4 +#define PHY_ANALOG_BB1_FORCE_NOTCH_LSB 4 +#define PHY_ANALOG_BB1_FORCE_NOTCH_MASK 0x00000010 +#define PHY_ANALOG_BB1_FORCE_NOTCH_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_BB1_FORCE_NOTCH_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MSB 5 +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_LSB 5 +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MASK 0x00000020 +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_BB1_FORCE_BIQUAD_MSB 6 +#define PHY_ANALOG_BB1_FORCE_BIQUAD_LSB 6 +#define PHY_ANALOG_BB1_FORCE_BIQUAD_MASK 0x00000040 +#define PHY_ANALOG_BB1_FORCE_BIQUAD_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_BB1_FORCE_BIQUAD_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_BB1_ENABLE_OSDAC_MSB 7 +#define PHY_ANALOG_BB1_ENABLE_OSDAC_LSB 7 +#define PHY_ANALOG_BB1_ENABLE_OSDAC_MASK 0x00000080 +#define PHY_ANALOG_BB1_ENABLE_OSDAC_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_BB1_ENABLE_OSDAC_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_BB1_FORCE_OSDAC_MSB 8 +#define PHY_ANALOG_BB1_FORCE_OSDAC_LSB 8 +#define PHY_ANALOG_BB1_FORCE_OSDAC_MASK 0x00000100 +#define PHY_ANALOG_BB1_FORCE_OSDAC_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_BB1_FORCE_OSDAC_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_BB1_ENABLE_V2I_MSB 9 +#define PHY_ANALOG_BB1_ENABLE_V2I_LSB 9 +#define PHY_ANALOG_BB1_ENABLE_V2I_MASK 0x00000200 +#define PHY_ANALOG_BB1_ENABLE_V2I_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_BB1_ENABLE_V2I_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_BB1_FORCE_V2I_MSB 10 +#define PHY_ANALOG_BB1_FORCE_V2I_LSB 10 +#define PHY_ANALOG_BB1_FORCE_V2I_MASK 0x00000400 +#define PHY_ANALOG_BB1_FORCE_V2I_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_BB1_FORCE_V2I_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_BB1_ENABLE_I2V_MSB 11 +#define PHY_ANALOG_BB1_ENABLE_I2V_LSB 11 +#define PHY_ANALOG_BB1_ENABLE_I2V_MASK 0x00000800 +#define PHY_ANALOG_BB1_ENABLE_I2V_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_BB1_ENABLE_I2V_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_BB1_FORCE_I2V_MSB 12 +#define PHY_ANALOG_BB1_FORCE_I2V_LSB 12 +#define PHY_ANALOG_BB1_FORCE_I2V_MASK 0x00001000 +#define PHY_ANALOG_BB1_FORCE_I2V_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_BB1_FORCE_I2V_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_BB1_CMSEL_MSB 15 +#define PHY_ANALOG_BB1_CMSEL_LSB 13 +#define PHY_ANALOG_BB1_CMSEL_MASK 0x0000e000 +#define PHY_ANALOG_BB1_CMSEL_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_BB1_CMSEL_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_BB1_ATBSEL_MSB 17 +#define PHY_ANALOG_BB1_ATBSEL_LSB 16 +#define PHY_ANALOG_BB1_ATBSEL_MASK 0x00030000 +#define PHY_ANALOG_BB1_ATBSEL_GET(x) (((x) & 0x00030000) >> 16) +#define PHY_ANALOG_BB1_ATBSEL_SET(x) (((x) << 16) & 0x00030000) +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MSB 18 +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_LSB 18 +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MASK 0x00040000 +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MSB 23 +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_LSB 19 +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MASK 0x00f80000 +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_GET(x) (((x) & 0x00f80000) >> 19) +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_SET(x) (((x) << 19) & 0x00f80000) +#define PHY_ANALOG_BB1_OFSTCORRI2VI_MSB 28 +#define PHY_ANALOG_BB1_OFSTCORRI2VI_LSB 24 +#define PHY_ANALOG_BB1_OFSTCORRI2VI_MASK 0x1f000000 +#define PHY_ANALOG_BB1_OFSTCORRI2VI_GET(x) (((x) & 0x1f000000) >> 24) +#define PHY_ANALOG_BB1_OFSTCORRI2VI_SET(x) (((x) << 24) & 0x1f000000) +#define PHY_ANALOG_BB1_LOCALOFFSET_MSB 29 +#define PHY_ANALOG_BB1_LOCALOFFSET_LSB 29 +#define PHY_ANALOG_BB1_LOCALOFFSET_MASK 0x20000000 +#define PHY_ANALOG_BB1_LOCALOFFSET_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_BB1_LOCALOFFSET_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_BB1_RANGE_OSDAC_MSB 31 +#define PHY_ANALOG_BB1_RANGE_OSDAC_LSB 30 +#define PHY_ANALOG_BB1_RANGE_OSDAC_MASK 0xc0000000 +#define PHY_ANALOG_BB1_RANGE_OSDAC_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_ANALOG_BB1_RANGE_OSDAC_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for BB2 */ +#define PHY_ANALOG_BB2_ADDRESS 0x00000144 +#define PHY_ANALOG_BB2_OFFSET 0x00000144 +#define PHY_ANALOG_BB2_SPARE_MSB 3 +#define PHY_ANALOG_BB2_SPARE_LSB 0 +#define PHY_ANALOG_BB2_SPARE_MASK 0x0000000f +#define PHY_ANALOG_BB2_SPARE_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_BB2_SPARE_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_MSB 7 +#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_LSB 4 +#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_MASK 0x000000f0 +#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_BB2_SEL_TEST_MSB 9 +#define PHY_ANALOG_BB2_SEL_TEST_LSB 8 +#define PHY_ANALOG_BB2_SEL_TEST_MASK 0x00000300 +#define PHY_ANALOG_BB2_SEL_TEST_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_BB2_SEL_TEST_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_BB2_RCFILTER_CAP_MSB 14 +#define PHY_ANALOG_BB2_RCFILTER_CAP_LSB 10 +#define PHY_ANALOG_BB2_RCFILTER_CAP_MASK 0x00007c00 +#define PHY_ANALOG_BB2_RCFILTER_CAP_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_ANALOG_BB2_RCFILTER_CAP_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_MSB 15 +#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_LSB 15 +#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_MASK 0x00008000 +#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_BB2_FNOTCH_MSB 19 +#define PHY_ANALOG_BB2_FNOTCH_LSB 16 +#define PHY_ANALOG_BB2_FNOTCH_MASK 0x000f0000 +#define PHY_ANALOG_BB2_FNOTCH_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_BB2_FNOTCH_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MSB 20 +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_LSB 20 +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MASK 0x00100000 +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_BB2_FILTERFC_MSB 25 +#define PHY_ANALOG_BB2_FILTERFC_LSB 21 +#define PHY_ANALOG_BB2_FILTERFC_MASK 0x03e00000 +#define PHY_ANALOG_BB2_FILTERFC_GET(x) (((x) & 0x03e00000) >> 21) +#define PHY_ANALOG_BB2_FILTERFC_SET(x) (((x) << 21) & 0x03e00000) +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MSB 26 +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_LSB 26 +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MASK 0x04000000 +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MSB 27 +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_LSB 27 +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MASK 0x08000000 +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MSB 28 +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_LSB 28 +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MASK 0x10000000 +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_BB2_RXIN2I2V_EN_MSB 29 +#define PHY_ANALOG_BB2_RXIN2I2V_EN_LSB 29 +#define PHY_ANALOG_BB2_RXIN2I2V_EN_MASK 0x20000000 +#define PHY_ANALOG_BB2_RXIN2I2V_EN_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_BB2_RXIN2I2V_EN_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_BB2_RXIN2BQ_EN_MSB 30 +#define PHY_ANALOG_BB2_RXIN2BQ_EN_LSB 30 +#define PHY_ANALOG_BB2_RXIN2BQ_EN_MASK 0x40000000 +#define PHY_ANALOG_BB2_RXIN2BQ_EN_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_BB2_RXIN2BQ_EN_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MSB 31 +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_LSB 31 +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MASK 0x80000000 +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB3 */ +#define PHY_ANALOG_BB3_ADDRESS 0x00000148 +#define PHY_ANALOG_BB3_OFFSET 0x00000148 +#define PHY_ANALOG_BB3_SPARE_MSB 15 +#define PHY_ANALOG_BB3_SPARE_LSB 0 +#define PHY_ANALOG_BB3_SPARE_MASK 0x0000ffff +#define PHY_ANALOG_BB3_SPARE_GET(x) (((x) & 0x0000ffff) >> 0) +#define PHY_ANALOG_BB3_SPARE_SET(x) (((x) << 0) & 0x0000ffff) +#define PHY_ANALOG_BB3_FILTERFC_MSB 20 +#define PHY_ANALOG_BB3_FILTERFC_LSB 16 +#define PHY_ANALOG_BB3_FILTERFC_MASK 0x001f0000 +#define PHY_ANALOG_BB3_FILTERFC_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_ANALOG_BB3_OFSTCORRI2VQ_MSB 25 +#define PHY_ANALOG_BB3_OFSTCORRI2VQ_LSB 21 +#define PHY_ANALOG_BB3_OFSTCORRI2VQ_MASK 0x03e00000 +#define PHY_ANALOG_BB3_OFSTCORRI2VQ_GET(x) (((x) & 0x03e00000) >> 21) +#define PHY_ANALOG_BB3_OFSTCORRI2VI_MSB 30 +#define PHY_ANALOG_BB3_OFSTCORRI2VI_LSB 26 +#define PHY_ANALOG_BB3_OFSTCORRI2VI_MASK 0x7c000000 +#define PHY_ANALOG_BB3_OFSTCORRI2VI_GET(x) (((x) & 0x7c000000) >> 26) +#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_MSB 31 +#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_LSB 31 +#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_MASK 0x80000000 +#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_SET(x) (((x) << 31) & 0x80000000) + +/* macros for PLLCLKMODA */ +#define PHY_ANALOG_PLLCLKMODA_ADDRESS 0x00000280 +#define PHY_ANALOG_PLLCLKMODA_OFFSET 0x00000280 +#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_MSB 0 +#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_LSB 0 +#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_MASK 0x00000001 +#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_PLLCLKMODA_PWDPLL_MSB 1 +#define PHY_ANALOG_PLLCLKMODA_PWDPLL_LSB 1 +#define PHY_ANALOG_PLLCLKMODA_PWDPLL_MASK 0x00000002 +#define PHY_ANALOG_PLLCLKMODA_PWDPLL_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_PLLCLKMODA_PWDPLL_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_MSB 16 +#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_LSB 2 +#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_MASK 0x0001fffc +#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_GET(x) (((x) & 0x0001fffc) >> 2) +#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_SET(x) (((x) << 2) & 0x0001fffc) +#define PHY_ANALOG_PLLCLKMODA_REFDIV_MSB 20 +#define PHY_ANALOG_PLLCLKMODA_REFDIV_LSB 17 +#define PHY_ANALOG_PLLCLKMODA_REFDIV_MASK 0x001e0000 +#define PHY_ANALOG_PLLCLKMODA_REFDIV_GET(x) (((x) & 0x001e0000) >> 17) +#define PHY_ANALOG_PLLCLKMODA_REFDIV_SET(x) (((x) << 17) & 0x001e0000) +#define PHY_ANALOG_PLLCLKMODA_DIV_MSB 30 +#define PHY_ANALOG_PLLCLKMODA_DIV_LSB 21 +#define PHY_ANALOG_PLLCLKMODA_DIV_MASK 0x7fe00000 +#define PHY_ANALOG_PLLCLKMODA_DIV_GET(x) (((x) & 0x7fe00000) >> 21) +#define PHY_ANALOG_PLLCLKMODA_DIV_SET(x) (((x) << 21) & 0x7fe00000) +#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_MSB 31 +#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_LSB 31 +#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_MASK 0x80000000 +#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_SET(x) (((x) << 31) & 0x80000000) + +/* macros for PLLCLKMODA2 */ +#define PHY_ANALOG_PLLCLKMODA2_ADDRESS 0x00000284 +#define PHY_ANALOG_PLLCLKMODA2_OFFSET 0x00000284 +#define PHY_ANALOG_PLLCLKMODA2_SPARE_MSB 3 +#define PHY_ANALOG_PLLCLKMODA2_SPARE_LSB 0 +#define PHY_ANALOG_PLLCLKMODA2_SPARE_MASK 0x0000000f +#define PHY_ANALOG_PLLCLKMODA2_SPARE_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_PLLCLKMODA2_SPARE_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_ANALOG_PLLCLKMODA2_DACPWD_MSB 4 +#define PHY_ANALOG_PLLCLKMODA2_DACPWD_LSB 4 +#define PHY_ANALOG_PLLCLKMODA2_DACPWD_MASK 0x00000010 +#define PHY_ANALOG_PLLCLKMODA2_DACPWD_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_PLLCLKMODA2_DACPWD_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_MSB 5 +#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_LSB 5 +#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_MASK 0x00000020 +#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_MSB 6 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_LSB 6 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_MASK 0x00000040 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_MSB 8 +#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_LSB 7 +#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_MASK 0x00000180 +#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_GET(x) (((x) & 0x00000180) >> 7) +#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_SET(x) (((x) << 7) & 0x00000180) +#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_MSB 12 +#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_LSB 9 +#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_MASK 0x00001e00 +#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_GET(x) (((x) & 0x00001e00) >> 9) +#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_SET(x) (((x) << 9) & 0x00001e00) +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_MSB 13 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_LSB 13 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_MASK 0x00002000 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_MSB 14 +#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_LSB 14 +#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_MASK 0x00004000 +#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_MSB 15 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_LSB 15 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_MASK 0x00008000 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_PLLCLKMODA2_PLLATB_MSB 17 +#define PHY_ANALOG_PLLCLKMODA2_PLLATB_LSB 16 +#define PHY_ANALOG_PLLCLKMODA2_PLLATB_MASK 0x00030000 +#define PHY_ANALOG_PLLCLKMODA2_PLLATB_GET(x) (((x) & 0x00030000) >> 16) +#define PHY_ANALOG_PLLCLKMODA2_PLLATB_SET(x) (((x) << 16) & 0x00030000) +#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_MSB 18 +#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_LSB 18 +#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_MASK 0x00040000 +#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_MSB 19 +#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_LSB 19 +#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_MASK 0x00080000 +#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_MSB 20 +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_LSB 20 +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_MASK 0x00100000 +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_MSB 21 +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_LSB 21 +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_MASK 0x00200000 +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_MSB 23 +#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_LSB 22 +#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_MASK 0x00c00000 +#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_ANALOG_PLLCLKMODA2_PLLICP_MSB 26 +#define PHY_ANALOG_PLLCLKMODA2_PLLICP_LSB 24 +#define PHY_ANALOG_PLLCLKMODA2_PLLICP_MASK 0x07000000 +#define PHY_ANALOG_PLLCLKMODA2_PLLICP_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_ANALOG_PLLCLKMODA2_PLLICP_SET(x) (((x) << 24) & 0x07000000) +#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_MSB 31 +#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_LSB 27 +#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_MASK 0xf8000000 +#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for TOP */ +#define PHY_ANALOG_TOP_ADDRESS 0x00000288 +#define PHY_ANALOG_TOP_OFFSET 0x00000288 +#define PHY_ANALOG_TOP_SPARE_MSB 2 +#define PHY_ANALOG_TOP_SPARE_LSB 0 +#define PHY_ANALOG_TOP_SPARE_MASK 0x00000007 +#define PHY_ANALOG_TOP_SPARE_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_TOP_SPARE_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_TOP_PWDBIAS_MSB 3 +#define PHY_ANALOG_TOP_PWDBIAS_LSB 3 +#define PHY_ANALOG_TOP_PWDBIAS_MASK 0x00000008 +#define PHY_ANALOG_TOP_PWDBIAS_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_TOP_PWDBIAS_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_TOP_FLIP_XPABIAS_MSB 4 +#define PHY_ANALOG_TOP_FLIP_XPABIAS_LSB 4 +#define PHY_ANALOG_TOP_FLIP_XPABIAS_MASK 0x00000010 +#define PHY_ANALOG_TOP_FLIP_XPABIAS_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_TOP_FLIP_XPABIAS_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_TOP_XPAON2_MSB 5 +#define PHY_ANALOG_TOP_XPAON2_LSB 5 +#define PHY_ANALOG_TOP_XPAON2_MASK 0x00000020 +#define PHY_ANALOG_TOP_XPAON2_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_TOP_XPAON2_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_TOP_XPAON5_MSB 6 +#define PHY_ANALOG_TOP_XPAON5_LSB 6 +#define PHY_ANALOG_TOP_XPAON5_MASK 0x00000040 +#define PHY_ANALOG_TOP_XPAON5_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_TOP_XPAON5_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_TOP_XPASHORT2GND_MSB 7 +#define PHY_ANALOG_TOP_XPASHORT2GND_LSB 7 +#define PHY_ANALOG_TOP_XPASHORT2GND_MASK 0x00000080 +#define PHY_ANALOG_TOP_XPASHORT2GND_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_TOP_XPASHORT2GND_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_TOP_XPABIASLVL_MSB 11 +#define PHY_ANALOG_TOP_XPABIASLVL_LSB 8 +#define PHY_ANALOG_TOP_XPABIASLVL_MASK 0x00000f00 +#define PHY_ANALOG_TOP_XPABIASLVL_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TOP_XPABIASLVL_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TOP_XPABIAS_EN_MSB 12 +#define PHY_ANALOG_TOP_XPABIAS_EN_LSB 12 +#define PHY_ANALOG_TOP_XPABIAS_EN_MASK 0x00001000 +#define PHY_ANALOG_TOP_XPABIAS_EN_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_TOP_XPABIAS_EN_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_TOP_ATBSELECT_MSB 13 +#define PHY_ANALOG_TOP_ATBSELECT_LSB 13 +#define PHY_ANALOG_TOP_ATBSELECT_MASK 0x00002000 +#define PHY_ANALOG_TOP_ATBSELECT_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_TOP_ATBSELECT_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_TOP_LOCAL_XPA_MSB 14 +#define PHY_ANALOG_TOP_LOCAL_XPA_LSB 14 +#define PHY_ANALOG_TOP_LOCAL_XPA_MASK 0x00004000 +#define PHY_ANALOG_TOP_LOCAL_XPA_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_TOP_LOCAL_XPA_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_TOP_XPABIAS_BYPASS_MSB 15 +#define PHY_ANALOG_TOP_XPABIAS_BYPASS_LSB 15 +#define PHY_ANALOG_TOP_XPABIAS_BYPASS_MASK 0x00008000 +#define PHY_ANALOG_TOP_XPABIAS_BYPASS_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_TOP_XPABIAS_BYPASS_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_TOP_TEST_PADQ_EN_MSB 16 +#define PHY_ANALOG_TOP_TEST_PADQ_EN_LSB 16 +#define PHY_ANALOG_TOP_TEST_PADQ_EN_MASK 0x00010000 +#define PHY_ANALOG_TOP_TEST_PADQ_EN_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_TOP_TEST_PADQ_EN_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_TOP_TEST_PADI_EN_MSB 17 +#define PHY_ANALOG_TOP_TEST_PADI_EN_LSB 17 +#define PHY_ANALOG_TOP_TEST_PADI_EN_MASK 0x00020000 +#define PHY_ANALOG_TOP_TEST_PADI_EN_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_TOP_TEST_PADI_EN_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_TOP_TESTIQ_RSEL_MSB 18 +#define PHY_ANALOG_TOP_TESTIQ_RSEL_LSB 18 +#define PHY_ANALOG_TOP_TESTIQ_RSEL_MASK 0x00040000 +#define PHY_ANALOG_TOP_TESTIQ_RSEL_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_TOP_TESTIQ_RSEL_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_TOP_TESTIQ_BUFEN_MSB 19 +#define PHY_ANALOG_TOP_TESTIQ_BUFEN_LSB 19 +#define PHY_ANALOG_TOP_TESTIQ_BUFEN_MASK 0x00080000 +#define PHY_ANALOG_TOP_TESTIQ_BUFEN_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_TOP_TESTIQ_BUFEN_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_TOP_PAD2GND_MSB 20 +#define PHY_ANALOG_TOP_PAD2GND_LSB 20 +#define PHY_ANALOG_TOP_PAD2GND_MASK 0x00100000 +#define PHY_ANALOG_TOP_PAD2GND_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TOP_PAD2GND_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TOP_INTH2PAD_MSB 21 +#define PHY_ANALOG_TOP_INTH2PAD_LSB 21 +#define PHY_ANALOG_TOP_INTH2PAD_MASK 0x00200000 +#define PHY_ANALOG_TOP_INTH2PAD_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_TOP_INTH2PAD_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_TOP_INTH2GND_MSB 22 +#define PHY_ANALOG_TOP_INTH2GND_LSB 22 +#define PHY_ANALOG_TOP_INTH2GND_MASK 0x00400000 +#define PHY_ANALOG_TOP_INTH2GND_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_TOP_INTH2GND_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_TOP_INT2PAD_MSB 23 +#define PHY_ANALOG_TOP_INT2PAD_LSB 23 +#define PHY_ANALOG_TOP_INT2PAD_MASK 0x00800000 +#define PHY_ANALOG_TOP_INT2PAD_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_TOP_INT2PAD_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_TOP_INT2GND_MSB 24 +#define PHY_ANALOG_TOP_INT2GND_LSB 24 +#define PHY_ANALOG_TOP_INT2GND_MASK 0x01000000 +#define PHY_ANALOG_TOP_INT2GND_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_TOP_INT2GND_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_TOP_PWDPALCLK_MSB 25 +#define PHY_ANALOG_TOP_PWDPALCLK_LSB 25 +#define PHY_ANALOG_TOP_PWDPALCLK_MASK 0x02000000 +#define PHY_ANALOG_TOP_PWDPALCLK_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_TOP_PWDPALCLK_SET(x) (((x) << 25) & 0x02000000) +#define PHY_ANALOG_TOP_INV_CLK320_ADC_MSB 26 +#define PHY_ANALOG_TOP_INV_CLK320_ADC_LSB 26 +#define PHY_ANALOG_TOP_INV_CLK320_ADC_MASK 0x04000000 +#define PHY_ANALOG_TOP_INV_CLK320_ADC_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_TOP_INV_CLK320_ADC_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_TOP_FLIP_REFCLK40_MSB 27 +#define PHY_ANALOG_TOP_FLIP_REFCLK40_LSB 27 +#define PHY_ANALOG_TOP_FLIP_REFCLK40_MASK 0x08000000 +#define PHY_ANALOG_TOP_FLIP_REFCLK40_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_TOP_FLIP_REFCLK40_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_TOP_FLIP_PLLCLK320_MSB 28 +#define PHY_ANALOG_TOP_FLIP_PLLCLK320_LSB 28 +#define PHY_ANALOG_TOP_FLIP_PLLCLK320_MASK 0x10000000 +#define PHY_ANALOG_TOP_FLIP_PLLCLK320_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_TOP_FLIP_PLLCLK320_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_TOP_FLIP_PLLCLK160_MSB 29 +#define PHY_ANALOG_TOP_FLIP_PLLCLK160_LSB 29 +#define PHY_ANALOG_TOP_FLIP_PLLCLK160_MASK 0x20000000 +#define PHY_ANALOG_TOP_FLIP_PLLCLK160_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_TOP_FLIP_PLLCLK160_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_TOP_CLK_SEL_MSB 31 +#define PHY_ANALOG_TOP_CLK_SEL_LSB 30 +#define PHY_ANALOG_TOP_CLK_SEL_MASK 0xc0000000 +#define PHY_ANALOG_TOP_CLK_SEL_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_ANALOG_TOP_CLK_SEL_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for THERM */ +#define PHY_ANALOG_THERM_ADDRESS 0x0000028c +#define PHY_ANALOG_THERM_OFFSET 0x0000028c +#define PHY_ANALOG_THERM_LOREG_LVL_MSB 2 +#define PHY_ANALOG_THERM_LOREG_LVL_LSB 0 +#define PHY_ANALOG_THERM_LOREG_LVL_MASK 0x00000007 +#define PHY_ANALOG_THERM_LOREG_LVL_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_THERM_LOREG_LVL_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_THERM_RFREG_LVL_MSB 5 +#define PHY_ANALOG_THERM_RFREG_LVL_LSB 3 +#define PHY_ANALOG_THERM_RFREG_LVL_MASK 0x00000038 +#define PHY_ANALOG_THERM_RFREG_LVL_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_ANALOG_THERM_RFREG_LVL_SET(x) (((x) << 3) & 0x00000038) +#define PHY_ANALOG_THERM_SAR_ADC_DONE_MSB 6 +#define PHY_ANALOG_THERM_SAR_ADC_DONE_LSB 6 +#define PHY_ANALOG_THERM_SAR_ADC_DONE_MASK 0x00000040 +#define PHY_ANALOG_THERM_SAR_ADC_DONE_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_THERM_SAR_ADC_OUT_MSB 14 +#define PHY_ANALOG_THERM_SAR_ADC_OUT_LSB 7 +#define PHY_ANALOG_THERM_SAR_ADC_OUT_MASK 0x00007f80 +#define PHY_ANALOG_THERM_SAR_ADC_OUT_GET(x) (((x) & 0x00007f80) >> 7) +#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_MSB 22 +#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_LSB 15 +#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_MASK 0x007f8000 +#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_GET(x) (((x) & 0x007f8000) >> 15) +#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_SET(x) (((x) << 15) & 0x007f8000) +#define PHY_ANALOG_THERM_SAR_DACTEST_EN_MSB 23 +#define PHY_ANALOG_THERM_SAR_DACTEST_EN_LSB 23 +#define PHY_ANALOG_THERM_SAR_DACTEST_EN_MASK 0x00800000 +#define PHY_ANALOG_THERM_SAR_DACTEST_EN_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_THERM_SAR_DACTEST_EN_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_MSB 24 +#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_LSB 24 +#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_MASK 0x01000000 +#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_THERM_THERMSEL_MSB 26 +#define PHY_ANALOG_THERM_THERMSEL_LSB 25 +#define PHY_ANALOG_THERM_THERMSEL_MASK 0x06000000 +#define PHY_ANALOG_THERM_THERMSEL_GET(x) (((x) & 0x06000000) >> 25) +#define PHY_ANALOG_THERM_THERMSEL_SET(x) (((x) << 25) & 0x06000000) +#define PHY_ANALOG_THERM_SAR_SLOW_EN_MSB 27 +#define PHY_ANALOG_THERM_SAR_SLOW_EN_LSB 27 +#define PHY_ANALOG_THERM_SAR_SLOW_EN_MASK 0x08000000 +#define PHY_ANALOG_THERM_SAR_SLOW_EN_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_THERM_SAR_SLOW_EN_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_THERM_THERMSTART_MSB 28 +#define PHY_ANALOG_THERM_THERMSTART_LSB 28 +#define PHY_ANALOG_THERM_THERMSTART_MASK 0x10000000 +#define PHY_ANALOG_THERM_THERMSTART_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_THERM_THERMSTART_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_MSB 29 +#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_LSB 29 +#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_MASK 0x20000000 +#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_THERM_THERMON_MSB 30 +#define PHY_ANALOG_THERM_THERMON_LSB 30 +#define PHY_ANALOG_THERM_THERMON_MASK 0x40000000 +#define PHY_ANALOG_THERM_THERMON_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_THERM_THERMON_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_THERM_LOCAL_THERM_MSB 31 +#define PHY_ANALOG_THERM_LOCAL_THERM_LSB 31 +#define PHY_ANALOG_THERM_LOCAL_THERM_MASK 0x80000000 +#define PHY_ANALOG_THERM_LOCAL_THERM_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_THERM_LOCAL_THERM_SET(x) (((x) << 31) & 0x80000000) + +/* macros for XTAL */ +#define PHY_ANALOG_XTAL_ADDRESS 0x00000290 +#define PHY_ANALOG_XTAL_OFFSET 0x00000290 +#define PHY_ANALOG_XTAL_SPARE_MSB 5 +#define PHY_ANALOG_XTAL_SPARE_LSB 0 +#define PHY_ANALOG_XTAL_SPARE_MASK 0x0000003f +#define PHY_ANALOG_XTAL_SPARE_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_ANALOG_XTAL_SPARE_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_MSB 6 +#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_LSB 6 +#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_MASK 0x00000040 +#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_XTAL_LOCALBIAS2X_MSB 7 +#define PHY_ANALOG_XTAL_LOCALBIAS2X_LSB 7 +#define PHY_ANALOG_XTAL_LOCALBIAS2X_MASK 0x00000080 +#define PHY_ANALOG_XTAL_LOCALBIAS2X_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_XTAL_LOCALBIAS2X_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_XTAL_LOCAL_XTAL_MSB 8 +#define PHY_ANALOG_XTAL_LOCAL_XTAL_LSB 8 +#define PHY_ANALOG_XTAL_LOCAL_XTAL_MASK 0x00000100 +#define PHY_ANALOG_XTAL_LOCAL_XTAL_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_XTAL_LOCAL_XTAL_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_MSB 9 +#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_LSB 9 +#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_MASK 0x00000200 +#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_XTAL_XTAL_OSCON_MSB 10 +#define PHY_ANALOG_XTAL_XTAL_OSCON_LSB 10 +#define PHY_ANALOG_XTAL_XTAL_OSCON_MASK 0x00000400 +#define PHY_ANALOG_XTAL_XTAL_OSCON_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_XTAL_XTAL_OSCON_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_MSB 11 +#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_LSB 11 +#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_MASK 0x00000800 +#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_MSB 12 +#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_LSB 12 +#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_MASK 0x00001000 +#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_MSB 13 +#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_LSB 13 +#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_MASK 0x00002000 +#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_XTAL_XTAL_DRVSTR_MSB 15 +#define PHY_ANALOG_XTAL_XTAL_DRVSTR_LSB 14 +#define PHY_ANALOG_XTAL_XTAL_DRVSTR_MASK 0x0000c000 +#define PHY_ANALOG_XTAL_XTAL_DRVSTR_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_ANALOG_XTAL_XTAL_DRVSTR_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_MSB 22 +#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_LSB 16 +#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_MASK 0x007f0000 +#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_GET(x) (((x) & 0x007f0000) >> 16) +#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_SET(x) (((x) << 16) & 0x007f0000) +#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_MSB 29 +#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_LSB 23 +#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_MASK 0x3f800000 +#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_GET(x) (((x) & 0x3f800000) >> 23) +#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_SET(x) (((x) << 23) & 0x3f800000) +#define PHY_ANALOG_XTAL_XTAL_BIAS2X_MSB 30 +#define PHY_ANALOG_XTAL_XTAL_BIAS2X_LSB 30 +#define PHY_ANALOG_XTAL_XTAL_BIAS2X_MASK 0x40000000 +#define PHY_ANALOG_XTAL_XTAL_BIAS2X_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_XTAL_XTAL_BIAS2X_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_XTAL_TCXODET_MSB 31 +#define PHY_ANALOG_XTAL_TCXODET_LSB 31 +#define PHY_ANALOG_XTAL_TCXODET_MASK 0x80000000 +#define PHY_ANALOG_XTAL_TCXODET_GET(x) (((x) & 0x80000000) >> 31) + +/* macros for rbist_cntrl */ +#define PHY_ANALOG_RBIST_CNTRL_ADDRESS 0x00000380 +#define PHY_ANALOG_RBIST_CNTRL_OFFSET 0x00000380 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MSB 0 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_LSB 0 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MASK 0x00000001 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MSB 1 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_LSB 1 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MASK 0x00000002 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MSB 2 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_LSB 2 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MASK 0x00000004 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MSB 3 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_LSB 3 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MASK 0x00000008 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MSB 4 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_LSB 4 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MASK 0x00000010 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MSB 5 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_LSB 5 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MASK 0x00000020 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MSB 6 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_LSB 6 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MASK 0x00000040 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MSB 7 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_LSB 7 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MASK 0x00000080 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MSB 8 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_LSB 8 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MASK 0x00000100 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MSB 9 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_LSB 9 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MASK 0x00000200 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MSB 10 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_LSB 10 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MASK 0x00000400 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MSB 11 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_LSB 11 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MASK 0x00000800 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MSB 12 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_LSB 12 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MASK 0x00001000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MSB 13 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_LSB 13 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MASK 0x00002000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MSB 14 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_LSB 14 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MASK 0x00004000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MSB 15 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_LSB 15 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MASK 0x00008000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MSB 16 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_LSB 16 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MASK 0x00010000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MSB 17 +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_LSB 17 +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MASK 0x00020000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_SET(x) (((x) << 17) & 0x00020000) + +/* macros for tx_dc_offset */ +#define PHY_ANALOG_TX_DC_OFFSET_ADDRESS 0x00000384 +#define PHY_ANALOG_TX_DC_OFFSET_OFFSET 0x00000384 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MSB 10 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_LSB 0 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MASK 0x000007ff +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MSB 26 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_LSB 16 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MASK 0x07ff0000 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_GET(x) (((x) & 0x07ff0000) >> 16) +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_SET(x) (((x) << 16) & 0x07ff0000) + +/* macros for tx_tonegen0 */ +#define PHY_ANALOG_TX_TONEGEN0_ADDRESS 0x00000388 +#define PHY_ANALOG_TX_TONEGEN0_OFFSET 0x00000388 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for tx_tonegen1 */ +#define PHY_ANALOG_TX_TONEGEN1_ADDRESS 0x0000038c +#define PHY_ANALOG_TX_TONEGEN1_OFFSET 0x0000038c +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MSB 6 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_LSB 0 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MSB 11 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_LSB 8 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MSB 23 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_LSB 16 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MSB 30 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_LSB 24 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for tx_lftonegen0 */ +#define PHY_ANALOG_TX_LFTONEGEN0_ADDRESS 0x00000390 +#define PHY_ANALOG_TX_LFTONEGEN0_OFFSET 0x00000390 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for tx_linear_ramp_i */ +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ADDRESS 0x00000394 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_OFFSET 0x00000394 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MSB 10 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_LSB 0 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MSB 21 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_LSB 12 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MSB 29 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_LSB 24 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for tx_linear_ramp_q */ +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ADDRESS 0x00000398 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_OFFSET 0x00000398 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MSB 10 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_LSB 0 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MSB 21 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_LSB 12 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MSB 29 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_LSB 24 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for tx_prbs_mag */ +#define PHY_ANALOG_TX_PRBS_MAG_ADDRESS 0x0000039c +#define PHY_ANALOG_TX_PRBS_MAG_OFFSET 0x0000039c +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MSB 9 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_LSB 0 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MASK 0x000003ff +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MSB 25 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_LSB 16 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MASK 0x03ff0000 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_GET(x) (((x) & 0x03ff0000) >> 16) +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_SET(x) (((x) << 16) & 0x03ff0000) + +/* macros for tx_prbs_seed_i */ +#define PHY_ANALOG_TX_PRBS_SEED_I_ADDRESS 0x000003a0 +#define PHY_ANALOG_TX_PRBS_SEED_I_OFFSET 0x000003a0 +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MSB 30 +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_LSB 0 +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0) +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff) + +/* macros for tx_prbs_seed_q */ +#define PHY_ANALOG_TX_PRBS_SEED_Q_ADDRESS 0x000003a4 +#define PHY_ANALOG_TX_PRBS_SEED_Q_OFFSET 0x000003a4 +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MSB 30 +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_LSB 0 +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0) +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff) + +/* macros for cmac_dc_cancel */ +#define PHY_ANALOG_CMAC_DC_CANCEL_ADDRESS 0x000003a8 +#define PHY_ANALOG_CMAC_DC_CANCEL_OFFSET 0x000003a8 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MSB 9 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_LSB 0 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MASK 0x000003ff +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MSB 25 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_LSB 16 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MASK 0x03ff0000 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_GET(x) (((x) & 0x03ff0000) >> 16) +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_SET(x) (((x) << 16) & 0x03ff0000) + +/* macros for cmac_dc_offset */ +#define PHY_ANALOG_CMAC_DC_OFFSET_ADDRESS 0x000003ac +#define PHY_ANALOG_CMAC_DC_OFFSET_OFFSET 0x000003ac +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_corr */ +#define PHY_ANALOG_CMAC_CORR_ADDRESS 0x000003b0 +#define PHY_ANALOG_CMAC_CORR_OFFSET 0x000003b0 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MSB 4 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MASK 0x0000001f +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MSB 13 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_LSB 8 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MASK 0x00003f00 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_SET(x) (((x) << 8) & 0x00003f00) + +/* macros for cmac_power */ +#define PHY_ANALOG_CMAC_POWER_ADDRESS 0x000003b4 +#define PHY_ANALOG_CMAC_POWER_OFFSET 0x000003b4 +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_cross_corr */ +#define PHY_ANALOG_CMAC_CROSS_CORR_ADDRESS 0x000003b8 +#define PHY_ANALOG_CMAC_CROSS_CORR_OFFSET 0x000003b8 +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_i2q2 */ +#define PHY_ANALOG_CMAC_I2Q2_ADDRESS 0x000003bc +#define PHY_ANALOG_CMAC_I2Q2_OFFSET 0x000003bc +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_power_hpf */ +#define PHY_ANALOG_CMAC_POWER_HPF_ADDRESS 0x000003c0 +#define PHY_ANALOG_CMAC_POWER_HPF_OFFSET 0x000003c0 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MSB 7 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_LSB 4 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MASK 0x000000f0 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_SET(x) (((x) << 4) & 0x000000f0) + +/* macros for rxdac_set1 */ +#define PHY_ANALOG_RXDAC_SET1_ADDRESS 0x000003c4 +#define PHY_ANALOG_RXDAC_SET1_OFFSET 0x000003c4 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MSB 1 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_LSB 0 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MASK 0x00000003 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MSB 4 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_LSB 4 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MASK 0x00000010 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MSB 13 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_LSB 8 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MASK 0x00003f00 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MSB 19 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_LSB 16 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MASK 0x000f0000 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_SET(x) (((x) << 16) & 0x000f0000) + +/* macros for rxdac_set2 */ +#define PHY_ANALOG_RXDAC_SET2_ADDRESS 0x000003c8 +#define PHY_ANALOG_RXDAC_SET2_OFFSET 0x000003c8 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MSB 4 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_LSB 0 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MASK 0x0000001f +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MSB 12 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_LSB 8 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MASK 0x00001f00 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_SET(x) (((x) << 8) & 0x00001f00) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MSB 20 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_LSB 16 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MASK 0x001f0000 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MSB 28 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_LSB 24 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MASK 0x1f000000 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_GET(x) (((x) & 0x1f000000) >> 24) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_SET(x) (((x) << 24) & 0x1f000000) + +/* macros for rxdac_long_shift */ +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ADDRESS 0x000003cc +#define PHY_ANALOG_RXDAC_LONG_SHIFT_OFFSET 0x000003cc +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MSB 4 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_LSB 0 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MASK 0x0000001f +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MSB 12 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_LSB 8 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MASK 0x00001f00 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_SET(x) (((x) << 8) & 0x00001f00) + +/* macros for cmac_results_i */ +#define PHY_ANALOG_CMAC_RESULTS_I_ADDRESS 0x000003d0 +#define PHY_ANALOG_CMAC_RESULTS_I_OFFSET 0x000003d0 +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MSB 31 +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_LSB 0 +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MASK 0xffffffff +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for cmac_results_q */ +#define PHY_ANALOG_CMAC_RESULTS_Q_ADDRESS 0x000003d4 +#define PHY_ANALOG_CMAC_RESULTS_Q_OFFSET 0x000003d4 +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MSB 31 +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_LSB 0 +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MASK 0xffffffff +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for PMU1 */ +#define PHY_ANALOG_PMU1_ADDRESS 0x00000740 +#define PHY_ANALOG_PMU1_OFFSET 0x00000740 +#define PHY_ANALOG_PMU1_SPARE_MSB 10 +#define PHY_ANALOG_PMU1_SPARE_LSB 0 +#define PHY_ANALOG_PMU1_SPARE_MASK 0x000007ff +#define PHY_ANALOG_PMU1_SPARE_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_PMU1_SPARE_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_PMU1_OTP_V25_PWD_MSB 11 +#define PHY_ANALOG_PMU1_OTP_V25_PWD_LSB 11 +#define PHY_ANALOG_PMU1_OTP_V25_PWD_MASK 0x00000800 +#define PHY_ANALOG_PMU1_OTP_V25_PWD_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_PMU1_OTP_V25_PWD_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_PMU1_PAREGON_MAN_MSB 12 +#define PHY_ANALOG_PMU1_PAREGON_MAN_LSB 12 +#define PHY_ANALOG_PMU1_PAREGON_MAN_MASK 0x00001000 +#define PHY_ANALOG_PMU1_PAREGON_MAN_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_PMU1_PAREGON_MAN_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_PMU1_OTPREGON_MAN_MSB 13 +#define PHY_ANALOG_PMU1_OTPREGON_MAN_LSB 13 +#define PHY_ANALOG_PMU1_OTPREGON_MAN_MASK 0x00002000 +#define PHY_ANALOG_PMU1_OTPREGON_MAN_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_PMU1_OTPREGON_MAN_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_PMU1_DREGON_MAN_MSB 14 +#define PHY_ANALOG_PMU1_DREGON_MAN_LSB 14 +#define PHY_ANALOG_PMU1_DREGON_MAN_MASK 0x00004000 +#define PHY_ANALOG_PMU1_DREGON_MAN_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_PMU1_DREGON_MAN_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_PMU1_DISCONTMODEEN_MSB 15 +#define PHY_ANALOG_PMU1_DISCONTMODEEN_LSB 15 +#define PHY_ANALOG_PMU1_DISCONTMODEEN_MASK 0x00008000 +#define PHY_ANALOG_PMU1_DISCONTMODEEN_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_PMU1_DISCONTMODEEN_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_PMU1_SWREGON_MAN_MSB 16 +#define PHY_ANALOG_PMU1_SWREGON_MAN_LSB 16 +#define PHY_ANALOG_PMU1_SWREGON_MAN_MASK 0x00010000 +#define PHY_ANALOG_PMU1_SWREGON_MAN_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_PMU1_SWREGON_MAN_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MSB 18 +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_LSB 17 +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MASK 0x00060000 +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_GET(x) (((x) & 0x00060000) >> 17) +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_SET(x) (((x) << 17) & 0x00060000) +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MSB 21 +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_LSB 19 +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MASK 0x00380000 +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MSB 23 +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_LSB 22 +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MASK 0x00c00000 +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_ANALOG_PMU1_SREG_LVLCTR_MSB 25 +#define PHY_ANALOG_PMU1_SREG_LVLCTR_LSB 24 +#define PHY_ANALOG_PMU1_SREG_LVLCTR_MASK 0x03000000 +#define PHY_ANALOG_PMU1_SREG_LVLCTR_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_ANALOG_PMU1_SREG_LVLCTR_SET(x) (((x) << 24) & 0x03000000) +#define PHY_ANALOG_PMU1_DREG_LVLCTR_MSB 27 +#define PHY_ANALOG_PMU1_DREG_LVLCTR_LSB 26 +#define PHY_ANALOG_PMU1_DREG_LVLCTR_MASK 0x0c000000 +#define PHY_ANALOG_PMU1_DREG_LVLCTR_GET(x) (((x) & 0x0c000000) >> 26) +#define PHY_ANALOG_PMU1_DREG_LVLCTR_SET(x) (((x) << 26) & 0x0c000000) +#define PHY_ANALOG_PMU1_PAREG_XPNP_MSB 28 +#define PHY_ANALOG_PMU1_PAREG_XPNP_LSB 28 +#define PHY_ANALOG_PMU1_PAREG_XPNP_MASK 0x10000000 +#define PHY_ANALOG_PMU1_PAREG_XPNP_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_PMU1_PAREG_XPNP_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MSB 31 +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_LSB 29 +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MASK 0xe0000000 +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for PMU2 */ +#define PHY_ANALOG_PMU2_ADDRESS 0x00000744 +#define PHY_ANALOG_PMU2_OFFSET 0x00000744 +#define PHY_ANALOG_PMU2_SPARE_MSB 7 +#define PHY_ANALOG_PMU2_SPARE_LSB 0 +#define PHY_ANALOG_PMU2_SPARE_MASK 0x000000ff +#define PHY_ANALOG_PMU2_SPARE_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_ANALOG_PMU2_SPARE_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MSB 8 +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_LSB 8 +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MASK 0x00000100 +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MSB 9 +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_LSB 9 +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MASK 0x00000200 +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MSB 10 +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_LSB 10 +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MASK 0x00000400 +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MSB 11 +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_LSB 11 +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MASK 0x00000800 +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MSB 12 +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_LSB 12 +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MASK 0x00001000 +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MSB 13 +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_LSB 13 +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MASK 0x00002000 +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MSB 14 +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_LSB 14 +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MASK 0x00004000 +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MSB 15 +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_LSB 15 +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MASK 0x00008000 +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MSB 16 +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_LSB 16 +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MASK 0x00010000 +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MSB 18 +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_LSB 17 +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MASK 0x00060000 +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_GET(x) (((x) & 0x00060000) >> 17) +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_SET(x) (((x) << 17) & 0x00060000) +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MSB 19 +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_LSB 19 +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MASK 0x00080000 +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MSB 21 +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_LSB 20 +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MASK 0x00300000 +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_GET(x) (((x) & 0x00300000) >> 20) +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_SET(x) (((x) << 20) & 0x00300000) +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MSB 22 +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_LSB 22 +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MASK 0x00400000 +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MSB 24 +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_LSB 23 +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MASK 0x01800000 +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_GET(x) (((x) & 0x01800000) >> 23) +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_SET(x) (((x) << 23) & 0x01800000) +#define PHY_ANALOG_PMU2_SWREG2ATB_MSB 27 +#define PHY_ANALOG_PMU2_SWREG2ATB_LSB 25 +#define PHY_ANALOG_PMU2_SWREG2ATB_MASK 0x0e000000 +#define PHY_ANALOG_PMU2_SWREG2ATB_GET(x) (((x) & 0x0e000000) >> 25) +#define PHY_ANALOG_PMU2_SWREG2ATB_SET(x) (((x) << 25) & 0x0e000000) +#define PHY_ANALOG_PMU2_OTPREG2ATB_MSB 28 +#define PHY_ANALOG_PMU2_OTPREG2ATB_LSB 28 +#define PHY_ANALOG_PMU2_OTPREG2ATB_MASK 0x10000000 +#define PHY_ANALOG_PMU2_OTPREG2ATB_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_PMU2_OTPREG2ATB_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MSB 30 +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_LSB 29 +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MASK 0x60000000 +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_SET(x) (((x) << 29) & 0x60000000) +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MSB 31 +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_LSB 31 +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MASK 0x80000000 +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_SET(x) (((x) << 31) & 0x80000000) + + +#ifndef __ASSEMBLER__ + +typedef struct analog_intf_athr_wlan_reg_reg_s { + volatile unsigned int RXRF_BIAS1; /* 0x0 - 0x4 */ + volatile unsigned int RXRF_BIAS2; /* 0x4 - 0x8 */ + volatile unsigned int RXRF_GAINSTAGES; /* 0x8 - 0xc */ + volatile unsigned int RXRF_AGC; /* 0xc - 0x10 */ + volatile char pad__0[0x30]; /* 0x10 - 0x40 */ + volatile unsigned int TXRF1; /* 0x40 - 0x44 */ + volatile unsigned int TXRF2; /* 0x44 - 0x48 */ + volatile unsigned int TXRF3; /* 0x48 - 0x4c */ + volatile unsigned int TXRF4; /* 0x4c - 0x50 */ + volatile unsigned int TXRF5; /* 0x50 - 0x54 */ + volatile unsigned int TXRF6; /* 0x54 - 0x58 */ + volatile unsigned int TXRF7; /* 0x58 - 0x5c */ + volatile unsigned int TXRF8; /* 0x5c - 0x60 */ + volatile unsigned int TXRF9; /* 0x60 - 0x64 */ + volatile unsigned int TXRF10; /* 0x64 - 0x68 */ + volatile unsigned int TXRF11; /* 0x68 - 0x6c */ + volatile unsigned int TXRF12; /* 0x6c - 0x70 */ + volatile char pad__1[0x10]; /* 0x70 - 0x80 */ + volatile unsigned int SYNTH1; /* 0x80 - 0x84 */ + volatile unsigned int SYNTH2; /* 0x84 - 0x88 */ + volatile unsigned int SYNTH3; /* 0x88 - 0x8c */ + volatile unsigned int SYNTH4; /* 0x8c - 0x90 */ + volatile unsigned int SYNTH5; /* 0x90 - 0x94 */ + volatile unsigned int SYNTH6; /* 0x94 - 0x98 */ + volatile unsigned int SYNTH7; /* 0x98 - 0x9c */ + volatile unsigned int SYNTH8; /* 0x9c - 0xa0 */ + volatile unsigned int SYNTH9; /* 0xa0 - 0xa4 */ + volatile unsigned int SYNTH10; /* 0xa4 - 0xa8 */ + volatile unsigned int SYNTH11; /* 0xa8 - 0xac */ + volatile unsigned int SYNTH12; /* 0xac - 0xb0 */ + volatile unsigned int SYNTH13; /* 0xb0 - 0xb4 */ + volatile unsigned int SYNTH14; /* 0xb4 - 0xb8 */ + volatile char pad__2[0x8]; /* 0xb8 - 0xc0 */ + volatile unsigned int BIAS1; /* 0xc0 - 0xc4 */ + volatile unsigned int BIAS2; /* 0xc4 - 0xc8 */ + volatile unsigned int BIAS3; /* 0xc8 - 0xcc */ + volatile unsigned int BIAS4; /* 0xcc - 0xd0 */ + volatile char pad__3[0x30]; /* 0xd0 - 0x100 */ + volatile unsigned int RXTX1; /* 0x100 - 0x104 */ + volatile unsigned int RXTX2; /* 0x104 - 0x108 */ + volatile unsigned int RXTX3; /* 0x108 - 0x10c */ + volatile char pad__4[0x34]; /* 0x10c - 0x140 */ + volatile unsigned int BB1; /* 0x140 - 0x144 */ + volatile unsigned int BB2; /* 0x144 - 0x148 */ + volatile unsigned int BB3; /* 0x148 - 0x14c */ + volatile char pad__5[0x134]; /* 0x14c - 0x280 */ + volatile unsigned int PLLCLKMODA; /* 0x280 - 0x284 */ + volatile unsigned int PLLCLKMODA2; /* 0x284 - 0x288 */ + volatile unsigned int TOP; /* 0x288 - 0x28c */ + volatile unsigned int THERM; /* 0x28c - 0x290 */ + volatile unsigned int XTAL; /* 0x290 - 0x294 */ + volatile char pad__6[0xec]; /* 0x294 - 0x380 */ + volatile unsigned int rbist_cntrl; /* 0x380 - 0x384 */ + volatile unsigned int tx_dc_offset; /* 0x384 - 0x388 */ + volatile unsigned int tx_tonegen0; /* 0x388 - 0x38c */ + volatile unsigned int tx_tonegen1; /* 0x38c - 0x390 */ + volatile unsigned int tx_lftonegen0; /* 0x390 - 0x394 */ + volatile unsigned int tx_linear_ramp_i; /* 0x394 - 0x398 */ + volatile unsigned int tx_linear_ramp_q; /* 0x398 - 0x39c */ + volatile unsigned int tx_prbs_mag; /* 0x39c - 0x3a0 */ + volatile unsigned int tx_prbs_seed_i; /* 0x3a0 - 0x3a4 */ + volatile unsigned int tx_prbs_seed_q; /* 0x3a4 - 0x3a8 */ + volatile unsigned int cmac_dc_cancel; /* 0x3a8 - 0x3ac */ + volatile unsigned int cmac_dc_offset; /* 0x3ac - 0x3b0 */ + volatile unsigned int cmac_corr; /* 0x3b0 - 0x3b4 */ + volatile unsigned int cmac_power; /* 0x3b4 - 0x3b8 */ + volatile unsigned int cmac_cross_corr; /* 0x3b8 - 0x3bc */ + volatile unsigned int cmac_i2q2; /* 0x3bc - 0x3c0 */ + volatile unsigned int cmac_power_hpf; /* 0x3c0 - 0x3c4 */ + volatile unsigned int rxdac_set1; /* 0x3c4 - 0x3c8 */ + volatile unsigned int rxdac_set2; /* 0x3c8 - 0x3cc */ + volatile unsigned int rxdac_long_shift; /* 0x3cc - 0x3d0 */ + volatile unsigned int cmac_results_i; /* 0x3d0 - 0x3d4 */ + volatile unsigned int cmac_results_q; /* 0x3d4 - 0x3d8 */ + volatile char pad__7[0x368]; /* 0x3d8 - 0x740 */ + volatile unsigned int PMU1; /* 0x740 - 0x744 */ + volatile unsigned int PMU2; /* 0x744 - 0x748 */ +} analog_intf_athr_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _ANALOG_INTF_ATHR_WLAN_REG_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_reg.h new file mode 100644 index 000000000000..01b9eb54a43c --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_reg.h @@ -0,0 +1,37 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "analog_intf_athr_wlan_reg.h" + + +#ifndef BT_HEADERS + + + +#endif +#endif + + + diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_athr_wlan_map.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_athr_wlan_map.h new file mode 100644 index 000000000000..609eb9841f59 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_athr_wlan_map.h @@ -0,0 +1,40 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _APB_ATHR_WLAN_MAP_H_ +#define _APB_ATHR_WLAN_MAP_H_ + +#define WLAN_RTC_BASE_ADDRESS 0x00004000 +#define WLAN_VMC_BASE_ADDRESS 0x00008000 +#define WLAN_UART_BASE_ADDRESS 0x0000c000 +#define WLAN_DBG_UART_BASE_ADDRESS 0x0000d000 +#define WLAN_UMBOX_BASE_ADDRESS 0x0000e000 +#define WLAN_SI_BASE_ADDRESS 0x00010000 +#define WLAN_GPIO_BASE_ADDRESS 0x00014000 +#define WLAN_MBOX_BASE_ADDRESS 0x00018000 +#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 +#define WLAN_MAC_BASE_ADDRESS 0x00020000 +#define WLAN_RDMA_BASE_ADDRESS 0x00030100 +#define EFUSE_BASE_ADDRESS 0x00031000 + +#endif /* _APB_ATHR_WLAN_MAP_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_map.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_map.h new file mode 100644 index 000000000000..e4d2d62f0bb4 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_map.h @@ -0,0 +1,48 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "apb_athr_wlan_map.h" + + +#ifndef BT_HEADERS + +#define RTC_BASE_ADDRESS WLAN_RTC_BASE_ADDRESS +#define VMC_BASE_ADDRESS WLAN_VMC_BASE_ADDRESS +#define UART_BASE_ADDRESS WLAN_UART_BASE_ADDRESS +#define DBG_UART_BASE_ADDRESS WLAN_DBG_UART_BASE_ADDRESS +#define UMBOX_BASE_ADDRESS WLAN_UMBOX_BASE_ADDRESS +#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS +#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS +#define MBOX_BASE_ADDRESS WLAN_MBOX_BASE_ADDRESS +#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS +#define MAC_BASE_ADDRESS WLAN_MAC_BASE_ADDRESS +#define RDMA_BASE_ADDRESS WLAN_RDMA_BASE_ADDRESS + + +#endif +#endif + + + diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/bb_lc_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/bb_lc_reg.h new file mode 100644 index 000000000000..271192953162 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/bb_lc_reg.h @@ -0,0 +1,7076 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + +/* Copyright (C) 2009 Denali Software Inc. All rights reserved */ +/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */ + + +#ifndef _BB_LC_REG_REG_H_ +#define _BB_LC_REG_REG_H_ + + +/* macros for BB_test_controls */ +#define PHY_BB_TEST_CONTROLS_ADDRESS 0x00009800 +#define PHY_BB_TEST_CONTROLS_OFFSET 0x00009800 +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MSB 3 +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_LSB 0 +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MASK 0x0000000f +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MSB 4 +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_LSB 4 +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MASK 0x00000010 +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MSB 6 +#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_LSB 5 +#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MASK 0x00000060 +#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_GET(x) (((x) & 0x00000060) >> 5) +#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_SET(x) (((x) << 5) & 0x00000060) +#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MSB 9 +#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_LSB 8 +#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MASK 0x00000300 +#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_SET(x) (((x) << 8) & 0x00000300) +#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MSB 10 +#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_LSB 10 +#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MASK 0x00000400 +#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MSB 13 +#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_LSB 13 +#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MASK 0x00002000 +#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MSB 15 +#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_LSB 15 +#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MASK 0x00008000 +#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_MSB 17 +#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_LSB 17 +#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_MASK 0x00020000 +#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MSB 18 +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_LSB 18 +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MASK 0x00040000 +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_SET(x) (((x) << 18) & 0x00040000) +#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MSB 22 +#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_LSB 19 +#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MASK 0x00780000 +#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_GET(x) (((x) & 0x00780000) >> 19) +#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_SET(x) (((x) << 19) & 0x00780000) +#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MSB 23 +#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_LSB 23 +#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MASK 0x00800000 +#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_SET(x) (((x) << 23) & 0x00800000) +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MSB 24 +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_LSB 24 +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MASK 0x01000000 +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_SET(x) (((x) << 24) & 0x01000000) +#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MSB 28 +#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_LSB 28 +#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MASK 0x10000000 +#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MSB 31 +#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_LSB 30 +#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MASK 0xc0000000 +#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for BB_gen_controls */ +#define PHY_BB_GEN_CONTROLS_ADDRESS 0x00009804 +#define PHY_BB_GEN_CONTROLS_OFFSET 0x00009804 +#define PHY_BB_GEN_CONTROLS_TURBO_MSB 0 +#define PHY_BB_GEN_CONTROLS_TURBO_LSB 0 +#define PHY_BB_GEN_CONTROLS_TURBO_MASK 0x00000001 +#define PHY_BB_GEN_CONTROLS_TURBO_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_GEN_CONTROLS_TURBO_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_GEN_CONTROLS_CF_SHORT20_MSB 1 +#define PHY_BB_GEN_CONTROLS_CF_SHORT20_LSB 1 +#define PHY_BB_GEN_CONTROLS_CF_SHORT20_MASK 0x00000002 +#define PHY_BB_GEN_CONTROLS_CF_SHORT20_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_GEN_CONTROLS_CF_SHORT20_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_MSB 2 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_LSB 2 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_MASK 0x00000004 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_MSB 3 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_LSB 3 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_MASK 0x00000008 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_MSB 4 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_LSB 4 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_MASK 0x00000010 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_MSB 5 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_LSB 5 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_MASK 0x00000020 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_SET(x) (((x) << 5) & 0x00000020) +#define PHY_BB_GEN_CONTROLS_HT_ENABLE_MSB 6 +#define PHY_BB_GEN_CONTROLS_HT_ENABLE_LSB 6 +#define PHY_BB_GEN_CONTROLS_HT_ENABLE_MASK 0x00000040 +#define PHY_BB_GEN_CONTROLS_HT_ENABLE_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_GEN_CONTROLS_HT_ENABLE_SET(x) (((x) << 6) & 0x00000040) +#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MSB 7 +#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_LSB 7 +#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MASK 0x00000080 +#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_SET(x) (((x) << 7) & 0x00000080) +#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_MSB 8 +#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_LSB 8 +#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_MASK 0x00000100 +#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_MSB 9 +#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_LSB 9 +#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_MASK 0x00000200 +#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_GEN_CONTROLS_GF_ENABLE_MSB 10 +#define PHY_BB_GEN_CONTROLS_GF_ENABLE_LSB 10 +#define PHY_BB_GEN_CONTROLS_GF_ENABLE_MASK 0x00000400 +#define PHY_BB_GEN_CONTROLS_GF_ENABLE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_GEN_CONTROLS_GF_ENABLE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_MSB 11 +#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_LSB 11 +#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_MASK 0x00000800 +#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_SET(x) (((x) << 11) & 0x00000800) + +/* macros for BB_test_controls_status */ +#define PHY_BB_TEST_CONTROLS_STATUS_ADDRESS 0x00009808 +#define PHY_BB_TEST_CONTROLS_STATUS_OFFSET 0x00009808 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MSB 0 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_LSB 0 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MASK 0x00000001 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MSB 1 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_LSB 1 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MASK 0x00000002 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MSB 4 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_LSB 2 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MASK 0x0000001c +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MSB 6 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_LSB 5 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MASK 0x00000060 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_GET(x) (((x) & 0x00000060) >> 5) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_SET(x) (((x) << 5) & 0x00000060) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MSB 7 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_LSB 7 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MASK 0x00000080 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_SET(x) (((x) << 7) & 0x00000080) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MSB 8 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_LSB 8 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MASK 0x00000100 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MSB 9 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_LSB 9 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MASK 0x00000200 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MSB 13 +#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_LSB 10 +#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MASK 0x00003c00 +#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_GET(x) (((x) & 0x00003c00) >> 10) +#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_SET(x) (((x) << 10) & 0x00003c00) +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MSB 14 +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_LSB 14 +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MASK 0x00004000 +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MSB 15 +#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_LSB 15 +#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MASK 0x00008000 +#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MSB 18 +#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_LSB 16 +#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MASK 0x00070000 +#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_SET(x) (((x) << 16) & 0x00070000) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MSB 19 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_LSB 19 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MASK 0x00080000 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_SET(x) (((x) << 19) & 0x00080000) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MSB 23 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_LSB 23 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MASK 0x00800000 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_SET(x) (((x) << 23) & 0x00800000) +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MSB 27 +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_LSB 27 +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MASK 0x08000000 +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_SET(x) (((x) << 27) & 0x08000000) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MSB 28 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_LSB 28 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MASK 0x10000000 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MSB 30 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_LSB 29 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MASK 0x60000000 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_SET(x) (((x) << 29) & 0x60000000) + +/* macros for BB_timing_controls_1 */ +#define PHY_BB_TIMING_CONTROLS_1_ADDRESS 0x0000980c +#define PHY_BB_TIMING_CONTROLS_1_OFFSET 0x0000980c +#define PHY_BB_TIMING_CONTROLS_1_STE_THR_MSB 6 +#define PHY_BB_TIMING_CONTROLS_1_STE_THR_LSB 0 +#define PHY_BB_TIMING_CONTROLS_1_STE_THR_MASK 0x0000007f +#define PHY_BB_TIMING_CONTROLS_1_STE_THR_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_TIMING_CONTROLS_1_STE_THR_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MSB 12 +#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_LSB 7 +#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MASK 0x00001f80 +#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_GET(x) (((x) & 0x00001f80) >> 7) +#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_SET(x) (((x) << 7) & 0x00001f80) +#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_MSB 16 +#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_LSB 13 +#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_MASK 0x0001e000 +#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_GET(x) (((x) & 0x0001e000) >> 13) +#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_SET(x) (((x) << 13) & 0x0001e000) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_MSB 17 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_LSB 17 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_MASK 0x00020000 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MSB 19 +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_LSB 18 +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MASK 0x000c0000 +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MSB 21 +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_LSB 20 +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MASK 0x00300000 +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_GET(x) (((x) & 0x00300000) >> 20) +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_SET(x) (((x) << 20) & 0x00300000) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MSB 22 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_LSB 22 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MASK 0x00400000 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MSB 23 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_LSB 23 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MASK 0x00800000 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_SET(x) (((x) << 23) & 0x00800000) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MSB 24 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_LSB 24 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MASK 0x01000000 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_SET(x) (((x) << 24) & 0x01000000) +#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MSB 26 +#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_LSB 25 +#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MASK 0x06000000 +#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_GET(x) (((x) & 0x06000000) >> 25) +#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_SET(x) (((x) << 25) & 0x06000000) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MSB 27 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_LSB 27 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MASK 0x08000000 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_SET(x) (((x) << 27) & 0x08000000) +#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MSB 28 +#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_LSB 28 +#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MASK 0x10000000 +#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MSB 30 +#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_LSB 29 +#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MASK 0x60000000 +#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_SET(x) (((x) << 29) & 0x60000000) +#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MSB 31 +#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_LSB 31 +#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MASK 0x80000000 +#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_timing_controls_2 */ +#define PHY_BB_TIMING_CONTROLS_2_ADDRESS 0x00009810 +#define PHY_BB_TIMING_CONTROLS_2_OFFSET 0x00009810 +#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MSB 11 +#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_LSB 0 +#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MASK 0x00000fff +#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_SET(x) (((x) << 0) & 0x00000fff) +#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MSB 12 +#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_LSB 12 +#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MASK 0x00001000 +#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MSB 13 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_LSB 13 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MASK 0x00002000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_MSB 14 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_LSB 14 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_MASK 0x00004000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MSB 15 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_LSB 15 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MASK 0x00008000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MSB 22 +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_LSB 16 +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MASK 0x007f0000 +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_GET(x) (((x) & 0x007f0000) >> 16) +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_SET(x) (((x) << 16) & 0x007f0000) +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MSB 26 +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_LSB 24 +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MASK 0x07000000 +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_SET(x) (((x) << 24) & 0x07000000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MSB 27 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_LSB 27 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MASK 0x08000000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_SET(x) (((x) << 27) & 0x08000000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MSB 28 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_LSB 28 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MASK 0x10000000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MSB 29 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_LSB 29 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MASK 0x20000000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MSB 30 +#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_LSB 30 +#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MASK 0x40000000 +#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MSB 31 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_LSB 31 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MASK 0x80000000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_timing_controls_3 */ +#define PHY_BB_TIMING_CONTROLS_3_ADDRESS 0x00009814 +#define PHY_BB_TIMING_CONTROLS_3_OFFSET 0x00009814 +#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MSB 7 +#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_LSB 0 +#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MASK 0x000000ff +#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MSB 8 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_LSB 8 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MASK 0x00000100 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MSB 9 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_LSB 9 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MASK 0x00000200 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MSB 10 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_LSB 10 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MASK 0x00000400 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MSB 11 +#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_LSB 11 +#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MASK 0x00000800 +#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_SET(x) (((x) << 11) & 0x00000800) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MSB 12 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_LSB 12 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MASK 0x00001000 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MSB 16 +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_LSB 13 +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MASK 0x0001e000 +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_GET(x) (((x) & 0x0001e000) >> 13) +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_SET(x) (((x) << 13) & 0x0001e000) +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MSB 31 +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_LSB 17 +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MASK 0xfffe0000 +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_GET(x) (((x) & 0xfffe0000) >> 17) +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_SET(x) (((x) << 17) & 0xfffe0000) + +/* macros for BB_D2_chip_id */ +#define PHY_BB_D2_CHIP_ID_ADDRESS 0x00009818 +#define PHY_BB_D2_CHIP_ID_OFFSET 0x00009818 +#define PHY_BB_D2_CHIP_ID_OLD_ID_MSB 7 +#define PHY_BB_D2_CHIP_ID_OLD_ID_LSB 0 +#define PHY_BB_D2_CHIP_ID_OLD_ID_MASK 0x000000ff +#define PHY_BB_D2_CHIP_ID_OLD_ID_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_D2_CHIP_ID_ID_MSB 31 +#define PHY_BB_D2_CHIP_ID_ID_LSB 8 +#define PHY_BB_D2_CHIP_ID_ID_MASK 0xffffff00 +#define PHY_BB_D2_CHIP_ID_ID_GET(x) (((x) & 0xffffff00) >> 8) + +/* macros for BB_active */ +#define PHY_BB_ACTIVE_ADDRESS 0x0000981c +#define PHY_BB_ACTIVE_OFFSET 0x0000981c +#define PHY_BB_ACTIVE_CF_ACTIVE_MSB 0 +#define PHY_BB_ACTIVE_CF_ACTIVE_LSB 0 +#define PHY_BB_ACTIVE_CF_ACTIVE_MASK 0x00000001 +#define PHY_BB_ACTIVE_CF_ACTIVE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_ACTIVE_CF_ACTIVE_SET(x) (((x) << 0) & 0x00000001) + +/* macros for BB_tx_timing_1 */ +#define PHY_BB_TX_TIMING_1_ADDRESS 0x00009820 +#define PHY_BB_TX_TIMING_1_OFFSET 0x00009820 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MSB 7 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_LSB 0 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MASK 0x000000ff +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MSB 15 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_LSB 8 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MASK 0x0000ff00 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MSB 23 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_LSB 16 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MASK 0x00ff0000 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MSB 31 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_LSB 24 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MASK 0xff000000 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_tx_timing_2 */ +#define PHY_BB_TX_TIMING_2_ADDRESS 0x00009824 +#define PHY_BB_TX_TIMING_2_OFFSET 0x00009824 +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MSB 7 +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_LSB 0 +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MASK 0x000000ff +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MSB 15 +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_LSB 8 +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MASK 0x0000ff00 +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MSB 23 +#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_LSB 16 +#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MASK 0x00ff0000 +#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MSB 31 +#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_LSB 24 +#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MASK 0xff000000 +#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_tx_timing_3 */ +#define PHY_BB_TX_TIMING_3_ADDRESS 0x00009828 +#define PHY_BB_TX_TIMING_3_OFFSET 0x00009828 +#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MSB 7 +#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_LSB 0 +#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MASK 0x000000ff +#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MSB 15 +#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_LSB 8 +#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MASK 0x0000ff00 +#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MSB 23 +#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_LSB 16 +#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MASK 0x00ff0000 +#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MSB 31 +#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_LSB 24 +#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MASK 0xff000000 +#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_addac_parallel_control */ +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ADDRESS 0x0000982c +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFFSET 0x0000982c +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MSB 12 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_LSB 12 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MASK 0x00001000 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MSB 13 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_LSB 13 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MASK 0x00002000 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MSB 15 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_LSB 15 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MASK 0x00008000 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MSB 28 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_LSB 28 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MASK 0x10000000 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MSB 29 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_LSB 29 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MASK 0x20000000 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MSB 31 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_LSB 31 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MASK 0x80000000 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_xpa_timing_control */ +#define PHY_BB_XPA_TIMING_CONTROL_ADDRESS 0x00009834 +#define PHY_BB_XPA_TIMING_CONTROL_OFFSET 0x00009834 +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MSB 7 +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_LSB 0 +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MASK 0x000000ff +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MSB 15 +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_LSB 8 +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MASK 0x0000ff00 +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MSB 23 +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_LSB 16 +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MASK 0x00ff0000 +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MSB 31 +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_LSB 24 +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MASK 0xff000000 +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_misc_pa_control */ +#define PHY_BB_MISC_PA_CONTROL_ADDRESS 0x00009838 +#define PHY_BB_MISC_PA_CONTROL_OFFSET 0x00009838 +#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MSB 0 +#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_LSB 0 +#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MASK 0x00000001 +#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MSB 1 +#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_LSB 1 +#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MASK 0x00000002 +#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MSB 2 +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_LSB 2 +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MASK 0x00000004 +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MSB 3 +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_LSB 3 +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MASK 0x00000008 +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_SET(x) (((x) << 3) & 0x00000008) + +/* macros for BB_tstdac_constant */ +#define PHY_BB_TSTDAC_CONSTANT_ADDRESS 0x0000983c +#define PHY_BB_TSTDAC_CONSTANT_OFFSET 0x0000983c +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MSB 10 +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_LSB 0 +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MASK 0x000007ff +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MSB 21 +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_LSB 11 +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MASK 0x003ff800 +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_GET(x) (((x) & 0x003ff800) >> 11) +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_SET(x) (((x) << 11) & 0x003ff800) + +/* macros for BB_find_signal_low */ +#define PHY_BB_FIND_SIGNAL_LOW_ADDRESS 0x00009840 +#define PHY_BB_FIND_SIGNAL_LOW_OFFSET 0x00009840 +#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MSB 5 +#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_LSB 0 +#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MASK 0x0000003f +#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MSB 11 +#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_LSB 6 +#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MASK 0x00000fc0 +#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MSB 19 +#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_LSB 12 +#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MASK 0x000ff000 +#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_GET(x) (((x) & 0x000ff000) >> 12) +#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_SET(x) (((x) << 12) & 0x000ff000) +#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MSB 23 +#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_LSB 20 +#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MASK 0x00f00000 +#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_GET(x) (((x) & 0x00f00000) >> 20) +#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_SET(x) (((x) << 20) & 0x00f00000) +#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MSB 30 +#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_LSB 24 +#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MASK 0x7f000000 +#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for BB_settling_time */ +#define PHY_BB_SETTLING_TIME_ADDRESS 0x00009844 +#define PHY_BB_SETTLING_TIME_OFFSET 0x00009844 +#define PHY_BB_SETTLING_TIME_AGC_SETTLING_MSB 6 +#define PHY_BB_SETTLING_TIME_AGC_SETTLING_LSB 0 +#define PHY_BB_SETTLING_TIME_AGC_SETTLING_MASK 0x0000007f +#define PHY_BB_SETTLING_TIME_AGC_SETTLING_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_SETTLING_TIME_AGC_SETTLING_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_MSB 13 +#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_LSB 7 +#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_MASK 0x00003f80 +#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_GET(x) (((x) & 0x00003f80) >> 7) +#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_SET(x) (((x) << 7) & 0x00003f80) +#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_MSB 19 +#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_LSB 14 +#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_MASK 0x000fc000 +#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_MSB 25 +#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_LSB 20 +#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_MASK 0x03f00000 +#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_MSB 29 +#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_LSB 26 +#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_MASK 0x3c000000 +#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_GET(x) (((x) & 0x3c000000) >> 26) +#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_SET(x) (((x) << 26) & 0x3c000000) + +/* macros for BB_gain_force_max_gains_b0 */ +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ADDRESS 0x00009848 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_OFFSET 0x00009848 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_MSB 13 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_LSB 7 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_MASK 0x00003f80 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_GET(x) (((x) & 0x00003f80) >> 7) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_SET(x) (((x) << 7) & 0x00003f80) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_MSB 20 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_LSB 14 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_MASK 0x001fc000 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_GET(x) (((x) & 0x001fc000) >> 14) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_SET(x) (((x) << 14) & 0x001fc000) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_MSB 21 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_LSB 21 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_MASK 0x00200000 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_SET(x) (((x) << 21) & 0x00200000) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_MSB 31 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_LSB 31 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_MASK 0x80000000 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_gains_min_offsets_b0 */ +#define PHY_BB_GAINS_MIN_OFFSETS_B0_ADDRESS 0x0000984c +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSET 0x0000984c +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_MSB 6 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_LSB 0 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_MASK 0x0000007f +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_MSB 11 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_LSB 7 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_MASK 0x00000f80 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_GET(x) (((x) & 0x00000f80) >> 7) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_SET(x) (((x) << 7) & 0x00000f80) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_MSB 16 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_LSB 12 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_MASK 0x0001f000 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_MSB 24 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_LSB 17 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_MASK 0x01fe0000 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_GET(x) (((x) & 0x01fe0000) >> 17) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_SET(x) (((x) << 17) & 0x01fe0000) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_MSB 25 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_LSB 25 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_MASK 0x02000000 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_SET(x) (((x) << 25) & 0x02000000) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_MSB 26 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_LSB 26 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_MASK 0x04000000 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_SET(x) (((x) << 26) & 0x04000000) + +/* macros for BB_desired_sigsize */ +#define PHY_BB_DESIRED_SIGSIZE_ADDRESS 0x00009850 +#define PHY_BB_DESIRED_SIGSIZE_OFFSET 0x00009850 +#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_MSB 7 +#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_LSB 0 +#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_MASK 0x000000ff +#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_MSB 27 +#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_LSB 20 +#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_MASK 0x0ff00000 +#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_GET(x) (((x) & 0x0ff00000) >> 20) +#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_SET(x) (((x) << 20) & 0x0ff00000) +#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_MSB 29 +#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_LSB 28 +#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_MASK 0x30000000 +#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_GET(x) (((x) & 0x30000000) >> 28) +#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_SET(x) (((x) << 28) & 0x30000000) +#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_MSB 30 +#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_LSB 30 +#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_MASK 0x40000000 +#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_MSB 31 +#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_LSB 31 +#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_MASK 0x80000000 +#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_timing_control_3a */ +#define PHY_BB_TIMING_CONTROL_3A_ADDRESS 0x00009854 +#define PHY_BB_TIMING_CONTROL_3A_OFFSET 0x00009854 +#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_MSB 6 +#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_LSB 0 +#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_MASK 0x0000007f +#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_SET(x) (((x) << 0) & 0x0000007f) + +/* macros for BB_find_signal */ +#define PHY_BB_FIND_SIGNAL_ADDRESS 0x00009858 +#define PHY_BB_FIND_SIGNAL_OFFSET 0x00009858 +#define PHY_BB_FIND_SIGNAL_RELSTEP_MSB 5 +#define PHY_BB_FIND_SIGNAL_RELSTEP_LSB 0 +#define PHY_BB_FIND_SIGNAL_RELSTEP_MASK 0x0000003f +#define PHY_BB_FIND_SIGNAL_RELSTEP_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_FIND_SIGNAL_RELSTEP_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_FIND_SIGNAL_RELPWR_MSB 11 +#define PHY_BB_FIND_SIGNAL_RELPWR_LSB 6 +#define PHY_BB_FIND_SIGNAL_RELPWR_MASK 0x00000fc0 +#define PHY_BB_FIND_SIGNAL_RELPWR_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_FIND_SIGNAL_RELPWR_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_FIND_SIGNAL_FIRSTEP_MSB 17 +#define PHY_BB_FIND_SIGNAL_FIRSTEP_LSB 12 +#define PHY_BB_FIND_SIGNAL_FIRSTEP_MASK 0x0003f000 +#define PHY_BB_FIND_SIGNAL_FIRSTEP_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_FIND_SIGNAL_FIRSTEP_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_FIND_SIGNAL_FIRPWR_MSB 25 +#define PHY_BB_FIND_SIGNAL_FIRPWR_LSB 18 +#define PHY_BB_FIND_SIGNAL_FIRPWR_MASK 0x03fc0000 +#define PHY_BB_FIND_SIGNAL_FIRPWR_GET(x) (((x) & 0x03fc0000) >> 18) +#define PHY_BB_FIND_SIGNAL_FIRPWR_SET(x) (((x) << 18) & 0x03fc0000) +#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_MSB 31 +#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_LSB 26 +#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_MASK 0xfc000000 +#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for BB_agc */ +#define PHY_BB_AGC_ADDRESS 0x0000985c +#define PHY_BB_AGC_OFFSET 0x0000985c +#define PHY_BB_AGC_COARSEPWR_CONST_MSB 6 +#define PHY_BB_AGC_COARSEPWR_CONST_LSB 0 +#define PHY_BB_AGC_COARSEPWR_CONST_MASK 0x0000007f +#define PHY_BB_AGC_COARSEPWR_CONST_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_AGC_COARSEPWR_CONST_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_BB_AGC_COARSE_LOW_MSB 14 +#define PHY_BB_AGC_COARSE_LOW_LSB 7 +#define PHY_BB_AGC_COARSE_LOW_MASK 0x00007f80 +#define PHY_BB_AGC_COARSE_LOW_GET(x) (((x) & 0x00007f80) >> 7) +#define PHY_BB_AGC_COARSE_LOW_SET(x) (((x) << 7) & 0x00007f80) +#define PHY_BB_AGC_COARSE_HIGH_MSB 21 +#define PHY_BB_AGC_COARSE_HIGH_LSB 15 +#define PHY_BB_AGC_COARSE_HIGH_MASK 0x003f8000 +#define PHY_BB_AGC_COARSE_HIGH_GET(x) (((x) & 0x003f8000) >> 15) +#define PHY_BB_AGC_COARSE_HIGH_SET(x) (((x) << 15) & 0x003f8000) +#define PHY_BB_AGC_QUICK_DROP_MSB 29 +#define PHY_BB_AGC_QUICK_DROP_LSB 22 +#define PHY_BB_AGC_QUICK_DROP_MASK 0x3fc00000 +#define PHY_BB_AGC_QUICK_DROP_GET(x) (((x) & 0x3fc00000) >> 22) +#define PHY_BB_AGC_QUICK_DROP_SET(x) (((x) << 22) & 0x3fc00000) +#define PHY_BB_AGC_RSSI_OUT_SELECT_MSB 31 +#define PHY_BB_AGC_RSSI_OUT_SELECT_LSB 30 +#define PHY_BB_AGC_RSSI_OUT_SELECT_MASK 0xc0000000 +#define PHY_BB_AGC_RSSI_OUT_SELECT_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_BB_AGC_RSSI_OUT_SELECT_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for BB_agc_control */ +#define PHY_BB_AGC_CONTROL_ADDRESS 0x00009860 +#define PHY_BB_AGC_CONTROL_OFFSET 0x00009860 +#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_MSB 0 +#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_LSB 0 +#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_MASK 0x00000001 +#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MSB 1 +#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_LSB 1 +#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MASK 0x00000002 +#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MSB 5 +#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_LSB 3 +#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MASK 0x00000038 +#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_SET(x) (((x) << 3) & 0x00000038) +#define PHY_BB_AGC_CONTROL_YCOK_MAX_MSB 9 +#define PHY_BB_AGC_CONTROL_YCOK_MAX_LSB 6 +#define PHY_BB_AGC_CONTROL_YCOK_MAX_MASK 0x000003c0 +#define PHY_BB_AGC_CONTROL_YCOK_MAX_GET(x) (((x) & 0x000003c0) >> 6) +#define PHY_BB_AGC_CONTROL_YCOK_MAX_SET(x) (((x) << 6) & 0x000003c0) +#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MSB 10 +#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_LSB 10 +#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MASK 0x00000400 +#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_AGC_CONTROL_CAL_ENABLE_MSB 11 +#define PHY_BB_AGC_CONTROL_CAL_ENABLE_LSB 11 +#define PHY_BB_AGC_CONTROL_CAL_ENABLE_MASK 0x00000800 +#define PHY_BB_AGC_CONTROL_CAL_ENABLE_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_BB_AGC_CONTROL_CAL_ENABLE_SET(x) (((x) << 11) & 0x00000800) +#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_MSB 12 +#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_LSB 12 +#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_MASK 0x00001000 +#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_MSB 13 +#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_LSB 13 +#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_MASK 0x00002000 +#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MSB 15 +#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_LSB 15 +#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MASK 0x00008000 +#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MSB 16 +#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_LSB 16 +#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MASK 0x00010000 +#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MSB 17 +#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_LSB 17 +#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MASK 0x00020000 +#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MSB 18 +#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_LSB 18 +#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MASK 0x00040000 +#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_SET(x) (((x) << 18) & 0x00040000) +#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_MSB 19 +#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_LSB 19 +#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_MASK 0x00080000 +#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MSB 20 +#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_LSB 20 +#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MASK 0x00100000 +#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_SET(x) (((x) << 20) & 0x00100000) + +/* macros for BB_cca_b0 */ +#define PHY_BB_CCA_B0_ADDRESS 0x00009864 +#define PHY_BB_CCA_B0_OFFSET 0x00009864 +#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_MSB 8 +#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_LSB 0 +#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_MASK 0x000001ff +#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_GET(x) (((x) & 0x000001ff) >> 0) +#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_SET(x) (((x) << 0) & 0x000001ff) +#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_MSB 11 +#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_LSB 9 +#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_MASK 0x00000e00 +#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_SET(x) (((x) << 9) & 0x00000e00) +#define PHY_BB_CCA_B0_CF_THRESH62_MSB 19 +#define PHY_BB_CCA_B0_CF_THRESH62_LSB 12 +#define PHY_BB_CCA_B0_CF_THRESH62_MASK 0x000ff000 +#define PHY_BB_CCA_B0_CF_THRESH62_GET(x) (((x) & 0x000ff000) >> 12) +#define PHY_BB_CCA_B0_CF_THRESH62_SET(x) (((x) << 12) & 0x000ff000) +#define PHY_BB_CCA_B0_MINCCAPWR_0_MSB 28 +#define PHY_BB_CCA_B0_MINCCAPWR_0_LSB 20 +#define PHY_BB_CCA_B0_MINCCAPWR_0_MASK 0x1ff00000 +#define PHY_BB_CCA_B0_MINCCAPWR_0_GET(x) (((x) & 0x1ff00000) >> 20) + +/* macros for BB_sfcorr */ +#define PHY_BB_SFCORR_ADDRESS 0x00009868 +#define PHY_BB_SFCORR_OFFSET 0x00009868 +#define PHY_BB_SFCORR_M2COUNT_THR_MSB 4 +#define PHY_BB_SFCORR_M2COUNT_THR_LSB 0 +#define PHY_BB_SFCORR_M2COUNT_THR_MASK 0x0000001f +#define PHY_BB_SFCORR_M2COUNT_THR_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_SFCORR_M2COUNT_THR_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_SFCORR_ADCSAT_THRESH_MSB 10 +#define PHY_BB_SFCORR_ADCSAT_THRESH_LSB 5 +#define PHY_BB_SFCORR_ADCSAT_THRESH_MASK 0x000007e0 +#define PHY_BB_SFCORR_ADCSAT_THRESH_GET(x) (((x) & 0x000007e0) >> 5) +#define PHY_BB_SFCORR_ADCSAT_THRESH_SET(x) (((x) << 5) & 0x000007e0) +#define PHY_BB_SFCORR_ADCSAT_ICOUNT_MSB 16 +#define PHY_BB_SFCORR_ADCSAT_ICOUNT_LSB 11 +#define PHY_BB_SFCORR_ADCSAT_ICOUNT_MASK 0x0001f800 +#define PHY_BB_SFCORR_ADCSAT_ICOUNT_GET(x) (((x) & 0x0001f800) >> 11) +#define PHY_BB_SFCORR_ADCSAT_ICOUNT_SET(x) (((x) << 11) & 0x0001f800) +#define PHY_BB_SFCORR_M1_THRES_MSB 23 +#define PHY_BB_SFCORR_M1_THRES_LSB 17 +#define PHY_BB_SFCORR_M1_THRES_MASK 0x00fe0000 +#define PHY_BB_SFCORR_M1_THRES_GET(x) (((x) & 0x00fe0000) >> 17) +#define PHY_BB_SFCORR_M1_THRES_SET(x) (((x) << 17) & 0x00fe0000) +#define PHY_BB_SFCORR_M2_THRES_MSB 30 +#define PHY_BB_SFCORR_M2_THRES_LSB 24 +#define PHY_BB_SFCORR_M2_THRES_MASK 0x7f000000 +#define PHY_BB_SFCORR_M2_THRES_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_BB_SFCORR_M2_THRES_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for BB_self_corr_low */ +#define PHY_BB_SELF_CORR_LOW_ADDRESS 0x0000986c +#define PHY_BB_SELF_CORR_LOW_OFFSET 0x0000986c +#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MSB 0 +#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_LSB 0 +#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MASK 0x00000001 +#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MSB 7 +#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_LSB 1 +#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MASK 0x000000fe +#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_GET(x) (((x) & 0x000000fe) >> 1) +#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_SET(x) (((x) << 1) & 0x000000fe) +#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MSB 13 +#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_LSB 8 +#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MASK 0x00003f00 +#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MSB 20 +#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_LSB 14 +#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MASK 0x001fc000 +#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_GET(x) (((x) & 0x001fc000) >> 14) +#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_SET(x) (((x) << 14) & 0x001fc000) +#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MSB 27 +#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_LSB 21 +#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MASK 0x0fe00000 +#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_GET(x) (((x) & 0x0fe00000) >> 21) +#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_SET(x) (((x) << 21) & 0x0fe00000) + +/* macros for BB_synth_control */ +#define PHY_BB_SYNTH_CONTROL_ADDRESS 0x00009874 +#define PHY_BB_SYNTH_CONTROL_OFFSET 0x00009874 +#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MSB 16 +#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_LSB 0 +#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MASK 0x0001ffff +#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_GET(x) (((x) & 0x0001ffff) >> 0) +#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_SET(x) (((x) << 0) & 0x0001ffff) +#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_MSB 25 +#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_LSB 17 +#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_MASK 0x03fe0000 +#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_GET(x) (((x) & 0x03fe0000) >> 17) +#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_SET(x) (((x) << 17) & 0x03fe0000) +#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MSB 27 +#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_LSB 26 +#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MASK 0x0c000000 +#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_GET(x) (((x) & 0x0c000000) >> 26) +#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_SET(x) (((x) << 26) & 0x0c000000) +#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_MSB 28 +#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_LSB 28 +#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_MASK 0x10000000 +#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_SYNTH_CONTROL_RFBMODE_MSB 29 +#define PHY_BB_SYNTH_CONTROL_RFBMODE_LSB 29 +#define PHY_BB_SYNTH_CONTROL_RFBMODE_MASK 0x20000000 +#define PHY_BB_SYNTH_CONTROL_RFBMODE_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_SYNTH_CONTROL_RFBMODE_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MSB 30 +#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_LSB 30 +#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MASK 0x40000000 +#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_SET(x) (((x) << 30) & 0x40000000) + +/* macros for BB_addac_clk_select */ +#define PHY_BB_ADDAC_CLK_SELECT_ADDRESS 0x00009878 +#define PHY_BB_ADDAC_CLK_SELECT_OFFSET 0x00009878 +#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MSB 3 +#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_LSB 2 +#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MASK 0x0000000c +#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_MSB 5 +#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_LSB 4 +#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_MASK 0x00000030 +#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_SET(x) (((x) << 4) & 0x00000030) + +/* macros for BB_pll_cntl */ +#define PHY_BB_PLL_CNTL_ADDRESS 0x0000987c +#define PHY_BB_PLL_CNTL_OFFSET 0x0000987c +#define PHY_BB_PLL_CNTL_BB_PLL_DIV_MSB 9 +#define PHY_BB_PLL_CNTL_BB_PLL_DIV_LSB 0 +#define PHY_BB_PLL_CNTL_BB_PLL_DIV_MASK 0x000003ff +#define PHY_BB_PLL_CNTL_BB_PLL_DIV_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_PLL_CNTL_BB_PLL_DIV_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MSB 13 +#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_LSB 10 +#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MASK 0x00003c00 +#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_GET(x) (((x) & 0x00003c00) >> 10) +#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_SET(x) (((x) << 10) & 0x00003c00) +#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MSB 15 +#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_LSB 14 +#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MASK 0x0000c000 +#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_MSB 16 +#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_LSB 16 +#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_MASK 0x00010000 +#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MSB 27 +#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_LSB 17 +#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MASK 0x0ffe0000 +#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_GET(x) (((x) & 0x0ffe0000) >> 17) +#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_SET(x) (((x) << 17) & 0x0ffe0000) + +/* macros for BB_vit_spur_mask_A */ +#define PHY_BB_VIT_SPUR_MASK_A_ADDRESS 0x00009900 +#define PHY_BB_VIT_SPUR_MASK_A_OFFSET 0x00009900 +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_MSB 9 +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_LSB 0 +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_MASK 0x000003ff +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_MSB 16 +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_LSB 10 +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_MASK 0x0001fc00 +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_GET(x) (((x) & 0x0001fc00) >> 10) +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_SET(x) (((x) << 10) & 0x0001fc00) + +/* macros for BB_vit_spur_mask_B */ +#define PHY_BB_VIT_SPUR_MASK_B_ADDRESS 0x00009904 +#define PHY_BB_VIT_SPUR_MASK_B_OFFSET 0x00009904 +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_MSB 9 +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_LSB 0 +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_MASK 0x000003ff +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_MSB 16 +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_LSB 10 +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_MASK 0x0001fc00 +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_GET(x) (((x) & 0x0001fc00) >> 10) +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_SET(x) (((x) << 10) & 0x0001fc00) + +/* macros for BB_pilot_spur_mask */ +#define PHY_BB_PILOT_SPUR_MASK_ADDRESS 0x00009908 +#define PHY_BB_PILOT_SPUR_MASK_OFFSET 0x00009908 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_MSB 4 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_LSB 0 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_MASK 0x0000001f +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_MSB 11 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_LSB 5 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_MASK 0x00000fe0 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_GET(x) (((x) & 0x00000fe0) >> 5) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_SET(x) (((x) << 5) & 0x00000fe0) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_MSB 16 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_LSB 12 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_MASK 0x0001f000 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_MSB 23 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_LSB 17 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_MASK 0x00fe0000 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_GET(x) (((x) & 0x00fe0000) >> 17) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_SET(x) (((x) << 17) & 0x00fe0000) + +/* macros for BB_chan_spur_mask */ +#define PHY_BB_CHAN_SPUR_MASK_ADDRESS 0x0000990c +#define PHY_BB_CHAN_SPUR_MASK_OFFSET 0x0000990c +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_MSB 4 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_LSB 0 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_MASK 0x0000001f +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_MSB 11 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_LSB 5 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_MASK 0x00000fe0 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_GET(x) (((x) & 0x00000fe0) >> 5) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_SET(x) (((x) << 5) & 0x00000fe0) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_MSB 16 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_LSB 12 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_MASK 0x0001f000 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_MSB 23 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_LSB 17 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_MASK 0x00fe0000 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_GET(x) (((x) & 0x00fe0000) >> 17) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_SET(x) (((x) << 17) & 0x00fe0000) + +/* macros for BB_spectral_scan */ +#define PHY_BB_SPECTRAL_SCAN_ADDRESS 0x00009910 +#define PHY_BB_SPECTRAL_SCAN_OFFSET 0x00009910 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MSB 0 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_LSB 0 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MASK 0x00000001 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MSB 1 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_LSB 1 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MASK 0x00000002 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_MSB 2 +#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_LSB 2 +#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_MASK 0x00000004 +#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_MSB 3 +#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_LSB 3 +#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_MASK 0x00000008 +#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_MSB 7 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_LSB 4 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_MASK 0x000000f0 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MSB 15 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_LSB 8 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MASK 0x0000ff00 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MSB 27 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_LSB 16 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MASK 0x0fff0000 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_GET(x) (((x) & 0x0fff0000) >> 16) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_SET(x) (((x) << 16) & 0x0fff0000) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_MSB 28 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_LSB 28 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_MASK 0x10000000 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MSB 29 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_LSB 29 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MASK 0x20000000 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_MSB 30 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_LSB 30 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_MASK 0x40000000 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_SET(x) (((x) << 30) & 0x40000000) + +/* macros for BB_analog_power_on_time */ +#define PHY_BB_ANALOG_POWER_ON_TIME_ADDRESS 0x00009914 +#define PHY_BB_ANALOG_POWER_ON_TIME_OFFSET 0x00009914 +#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MSB 13 +#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_LSB 0 +#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MASK 0x00003fff +#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_SET(x) (((x) << 0) & 0x00003fff) + +/* macros for BB_search_start_delay */ +#define PHY_BB_SEARCH_START_DELAY_ADDRESS 0x00009918 +#define PHY_BB_SEARCH_START_DELAY_OFFSET 0x00009918 +#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_MSB 11 +#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_LSB 0 +#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_MASK 0x00000fff +#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_SET(x) (((x) << 0) & 0x00000fff) +#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_MSB 12 +#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_LSB 12 +#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_MASK 0x00001000 +#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_MSB 13 +#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_LSB 13 +#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_MASK 0x00002000 +#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_SET(x) (((x) << 13) & 0x00002000) + +/* macros for BB_max_rx_length */ +#define PHY_BB_MAX_RX_LENGTH_ADDRESS 0x0000991c +#define PHY_BB_MAX_RX_LENGTH_OFFSET 0x0000991c +#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MSB 11 +#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_LSB 0 +#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MASK 0x00000fff +#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_SET(x) (((x) << 0) & 0x00000fff) +#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MSB 29 +#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_LSB 12 +#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MASK 0x3ffff000 +#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_GET(x) (((x) & 0x3ffff000) >> 12) +#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_SET(x) (((x) << 12) & 0x3ffff000) + +/* macros for BB_timing_control_4 */ +#define PHY_BB_TIMING_CONTROL_4_ADDRESS 0x00009920 +#define PHY_BB_TIMING_CONTROL_4_OFFSET 0x00009920 +#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MSB 15 +#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_LSB 12 +#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MASK 0x0000f000 +#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MSB 16 +#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_LSB 16 +#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MASK 0x00010000 +#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MSB 20 +#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_LSB 17 +#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MASK 0x001e0000 +#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_GET(x) (((x) & 0x001e0000) >> 17) +#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_SET(x) (((x) << 17) & 0x001e0000) +#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MSB 27 +#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_LSB 21 +#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MASK 0x0fe00000 +#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_GET(x) (((x) & 0x0fe00000) >> 21) +#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_SET(x) (((x) << 21) & 0x0fe00000) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MSB 28 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_LSB 28 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MASK 0x10000000 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MSB 29 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_LSB 29 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MASK 0x20000000 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_MSB 30 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_LSB 30 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_MASK 0x40000000 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MSB 31 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_LSB 31 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MASK 0x80000000 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_timing_control_5 */ +#define PHY_BB_TIMING_CONTROL_5_ADDRESS 0x00009924 +#define PHY_BB_TIMING_CONTROL_5_OFFSET 0x00009924 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MSB 0 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_LSB 0 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MASK 0x00000001 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MSB 7 +#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_LSB 1 +#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MASK 0x000000fe +#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_GET(x) (((x) & 0x000000fe) >> 1) +#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_SET(x) (((x) << 1) & 0x000000fe) +#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MSB 15 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_LSB 15 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MASK 0x00008000 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MSB 22 +#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_LSB 16 +#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MASK 0x007f0000 +#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_GET(x) (((x) & 0x007f0000) >> 16) +#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_SET(x) (((x) << 16) & 0x007f0000) +#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MSB 29 +#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_LSB 23 +#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MASK 0x3f800000 +#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_GET(x) (((x) & 0x3f800000) >> 23) +#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_SET(x) (((x) << 23) & 0x3f800000) +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_MSB 30 +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_LSB 30 +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_MASK 0x40000000 +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_MSB 31 +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_LSB 31 +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_MASK 0x80000000 +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_phyonly_warm_reset */ +#define PHY_BB_PHYONLY_WARM_RESET_ADDRESS 0x00009928 +#define PHY_BB_PHYONLY_WARM_RESET_OFFSET 0x00009928 +#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_MSB 0 +#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_LSB 0 +#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_MASK 0x00000001 +#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_SET(x) (((x) << 0) & 0x00000001) + +/* macros for BB_phyonly_control */ +#define PHY_BB_PHYONLY_CONTROL_ADDRESS 0x0000992c +#define PHY_BB_PHYONLY_CONTROL_OFFSET 0x0000992c +#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MSB 0 +#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_LSB 0 +#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MASK 0x00000001 +#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MSB 1 +#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_LSB 1 +#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MASK 0x00000002 +#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_MSB 2 +#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_LSB 2 +#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_MASK 0x00000004 +#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MSB 3 +#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_LSB 3 +#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MASK 0x00000008 +#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MSB 4 +#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_LSB 4 +#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MASK 0x00000010 +#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MSB 5 +#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_LSB 5 +#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MASK 0x00000020 +#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_SET(x) (((x) << 5) & 0x00000020) +#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MSB 6 +#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_LSB 6 +#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MASK 0x00000040 +#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_SET(x) (((x) << 6) & 0x00000040) +#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MSB 7 +#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_LSB 7 +#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MASK 0x00000080 +#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_SET(x) (((x) << 7) & 0x00000080) + +/* macros for BB_powertx_rate1 */ +#define PHY_BB_POWERTX_RATE1_ADDRESS 0x00009934 +#define PHY_BB_POWERTX_RATE1_OFFSET 0x00009934 +#define PHY_BB_POWERTX_RATE1_POWERTX_0_MSB 5 +#define PHY_BB_POWERTX_RATE1_POWERTX_0_LSB 0 +#define PHY_BB_POWERTX_RATE1_POWERTX_0_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE1_POWERTX_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE1_POWERTX_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE1_POWERTX_1_MSB 13 +#define PHY_BB_POWERTX_RATE1_POWERTX_1_LSB 8 +#define PHY_BB_POWERTX_RATE1_POWERTX_1_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE1_POWERTX_1_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE1_POWERTX_1_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE1_POWERTX_2_MSB 21 +#define PHY_BB_POWERTX_RATE1_POWERTX_2_LSB 16 +#define PHY_BB_POWERTX_RATE1_POWERTX_2_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE1_POWERTX_2_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE1_POWERTX_2_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE1_POWERTX_3_MSB 29 +#define PHY_BB_POWERTX_RATE1_POWERTX_3_LSB 24 +#define PHY_BB_POWERTX_RATE1_POWERTX_3_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE1_POWERTX_3_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE1_POWERTX_3_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate2 */ +#define PHY_BB_POWERTX_RATE2_ADDRESS 0x00009938 +#define PHY_BB_POWERTX_RATE2_OFFSET 0x00009938 +#define PHY_BB_POWERTX_RATE2_POWERTX_4_MSB 5 +#define PHY_BB_POWERTX_RATE2_POWERTX_4_LSB 0 +#define PHY_BB_POWERTX_RATE2_POWERTX_4_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE2_POWERTX_4_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE2_POWERTX_4_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE2_POWERTX_5_MSB 13 +#define PHY_BB_POWERTX_RATE2_POWERTX_5_LSB 8 +#define PHY_BB_POWERTX_RATE2_POWERTX_5_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE2_POWERTX_5_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE2_POWERTX_5_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE2_POWERTX_6_MSB 21 +#define PHY_BB_POWERTX_RATE2_POWERTX_6_LSB 16 +#define PHY_BB_POWERTX_RATE2_POWERTX_6_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE2_POWERTX_6_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE2_POWERTX_6_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE2_POWERTX_7_MSB 29 +#define PHY_BB_POWERTX_RATE2_POWERTX_7_LSB 24 +#define PHY_BB_POWERTX_RATE2_POWERTX_7_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE2_POWERTX_7_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE2_POWERTX_7_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_max */ +#define PHY_BB_POWERTX_MAX_ADDRESS 0x0000993c +#define PHY_BB_POWERTX_MAX_OFFSET 0x0000993c +#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_MSB 6 +#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_LSB 6 +#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_MASK 0x00000040 +#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_SET(x) (((x) << 6) & 0x00000040) + +/* macros for BB_extension_radar */ +#define PHY_BB_EXTENSION_RADAR_ADDRESS 0x00009940 +#define PHY_BB_EXTENSION_RADAR_OFFSET 0x00009940 +#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_MSB 13 +#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_LSB 8 +#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_MASK 0x00003f00 +#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_MSB 14 +#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_LSB 14 +#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_MASK 0x00004000 +#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_MSB 22 +#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_LSB 15 +#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_MASK 0x007f8000 +#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_GET(x) (((x) & 0x007f8000) >> 15) +#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_SET(x) (((x) << 15) & 0x007f8000) +#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MSB 30 +#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_LSB 23 +#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MASK 0x7f800000 +#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_GET(x) (((x) & 0x7f800000) >> 23) +#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_SET(x) (((x) << 23) & 0x7f800000) +#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_MSB 31 +#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_LSB 31 +#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_MASK 0x80000000 +#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_frame_control */ +#define PHY_BB_FRAME_CONTROL_ADDRESS 0x00009944 +#define PHY_BB_FRAME_CONTROL_OFFSET 0x00009944 +#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MSB 1 +#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_LSB 0 +#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MASK 0x00000003 +#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_SET(x) (((x) << 0) & 0x00000003) +#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_MSB 2 +#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_LSB 2 +#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_MASK 0x00000004 +#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MSB 5 +#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_LSB 3 +#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MASK 0x00000038 +#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_SET(x) (((x) << 3) & 0x00000038) +#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MSB 7 +#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_LSB 6 +#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MASK 0x000000c0 +#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MSB 15 +#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_LSB 8 +#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MASK 0x0000ff00 +#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MSB 16 +#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_LSB 16 +#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MASK 0x00010000 +#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MSB 17 +#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_LSB 17 +#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MASK 0x00020000 +#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MSB 18 +#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_LSB 18 +#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MASK 0x00040000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_SET(x) (((x) << 18) & 0x00040000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_MSB 19 +#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_LSB 19 +#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_MASK 0x00080000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_SET(x) (((x) << 19) & 0x00080000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MSB 20 +#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_LSB 20 +#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MASK 0x00100000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_SET(x) (((x) << 20) & 0x00100000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MSB 21 +#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_LSB 21 +#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MASK 0x00200000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_SET(x) (((x) << 21) & 0x00200000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MSB 22 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_LSB 22 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MASK 0x00400000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MSB 23 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_LSB 23 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MASK 0x00800000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_SET(x) (((x) << 23) & 0x00800000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MSB 24 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_LSB 24 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MASK 0x01000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_SET(x) (((x) << 24) & 0x01000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MSB 25 +#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_LSB 25 +#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MASK 0x02000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_SET(x) (((x) << 25) & 0x02000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MSB 26 +#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_LSB 26 +#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MASK 0x04000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_SET(x) (((x) << 26) & 0x04000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MSB 27 +#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_LSB 27 +#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MASK 0x08000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_SET(x) (((x) << 27) & 0x08000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_MSB 28 +#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_LSB 28 +#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_MASK 0x10000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MSB 29 +#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_LSB 29 +#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MASK 0x20000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MSB 30 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_LSB 30 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MASK 0x40000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MSB 31 +#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_LSB 31 +#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MASK 0x80000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_timing_control_6 */ +#define PHY_BB_TIMING_CONTROL_6_ADDRESS 0x00009948 +#define PHY_BB_TIMING_CONTROL_6_OFFSET 0x00009948 +#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MSB 7 +#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_LSB 0 +#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MASK 0x000000ff +#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MSB 14 +#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_LSB 8 +#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MASK 0x00007f00 +#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_GET(x) (((x) & 0x00007f00) >> 8) +#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_SET(x) (((x) << 8) & 0x00007f00) +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MSB 20 +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_LSB 15 +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MASK 0x001f8000 +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_GET(x) (((x) & 0x001f8000) >> 15) +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_SET(x) (((x) << 15) & 0x001f8000) +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MSB 27 +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_LSB 21 +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MASK 0x0fe00000 +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_GET(x) (((x) & 0x0fe00000) >> 21) +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_SET(x) (((x) << 21) & 0x0fe00000) +#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_MSB 31 +#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_LSB 28 +#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_MASK 0xf0000000 +#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_GET(x) (((x) & 0xf0000000) >> 28) +#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_SET(x) (((x) << 28) & 0xf0000000) + +/* macros for BB_spur_mask_controls */ +#define PHY_BB_SPUR_MASK_CONTROLS_ADDRESS 0x0000994c +#define PHY_BB_SPUR_MASK_CONTROLS_OFFSET 0x0000994c +#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MSB 7 +#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_LSB 0 +#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MASK 0x000000ff +#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MSB 8 +#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_LSB 8 +#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MASK 0x00000100 +#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MSB 17 +#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_LSB 17 +#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MASK 0x00020000 +#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MSB 25 +#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_LSB 18 +#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MASK 0x03fc0000 +#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_GET(x) (((x) & 0x03fc0000) >> 18) +#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_SET(x) (((x) << 18) & 0x03fc0000) + +/* macros for BB_rx_iq_corr_b0 */ +#define PHY_BB_RX_IQ_CORR_B0_ADDRESS 0x00009950 +#define PHY_BB_RX_IQ_CORR_B0_OFFSET 0x00009950 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_MSB 6 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_LSB 0 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_MASK 0x0000007f +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_MSB 13 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_LSB 7 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_MASK 0x00003f80 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_GET(x) (((x) & 0x00003f80) >> 7) +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_SET(x) (((x) << 7) & 0x00003f80) +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MSB 14 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_LSB 14 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MASK 0x00004000 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MSB 21 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_LSB 15 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MASK 0x003f8000 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_GET(x) (((x) & 0x003f8000) >> 15) +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_SET(x) (((x) << 15) & 0x003f8000) +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MSB 28 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_LSB 22 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MASK 0x1fc00000 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_GET(x) (((x) & 0x1fc00000) >> 22) +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_SET(x) (((x) << 22) & 0x1fc00000) +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_MSB 29 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_LSB 29 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_MASK 0x20000000 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_SET(x) (((x) << 29) & 0x20000000) + +/* macros for BB_radar_detection */ +#define PHY_BB_RADAR_DETECTION_ADDRESS 0x00009954 +#define PHY_BB_RADAR_DETECTION_OFFSET 0x00009954 +#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MSB 0 +#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_LSB 0 +#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MASK 0x00000001 +#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_MSB 5 +#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_LSB 1 +#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_MASK 0x0000003e +#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_GET(x) (((x) & 0x0000003e) >> 1) +#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_SET(x) (((x) << 1) & 0x0000003e) +#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MSB 11 +#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_LSB 6 +#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MASK 0x00000fc0 +#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MSB 17 +#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_LSB 12 +#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MASK 0x0003f000 +#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_MSB 23 +#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_LSB 18 +#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_MASK 0x00fc0000 +#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_SET(x) (((x) << 18) & 0x00fc0000) +#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MSB 30 +#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_LSB 24 +#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MASK 0x7f000000 +#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_SET(x) (((x) << 24) & 0x7f000000) +#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_MSB 31 +#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_LSB 31 +#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_MASK 0x80000000 +#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_radar_detection_2 */ +#define PHY_BB_RADAR_DETECTION_2_ADDRESS 0x00009958 +#define PHY_BB_RADAR_DETECTION_2_OFFSET 0x00009958 +#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_MSB 7 +#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_LSB 0 +#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_MASK 0x000000ff +#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MSB 12 +#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_LSB 8 +#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MASK 0x00001f00 +#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_SET(x) (((x) << 8) & 0x00001f00) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MSB 13 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_LSB 13 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MASK 0x00002000 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_MSB 14 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_LSB 14 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_MASK 0x00004000 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_MSB 15 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_LSB 15 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_MASK 0x00008000 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_MSB 21 +#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_LSB 16 +#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_MASK 0x003f0000 +#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_MSB 22 +#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_LSB 22 +#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_MASK 0x00400000 +#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_MSB 23 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_LSB 23 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_MASK 0x00800000 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_SET(x) (((x) << 23) & 0x00800000) +#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_MSB 26 +#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_LSB 24 +#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_MASK 0x07000000 +#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_SET(x) (((x) << 24) & 0x07000000) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MSB 27 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_LSB 27 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MASK 0x08000000 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_SET(x) (((x) << 27) & 0x08000000) + +/* macros for BB_tx_phase_ramp_b0 */ +#define PHY_BB_TX_PHASE_RAMP_B0_ADDRESS 0x0000995c +#define PHY_BB_TX_PHASE_RAMP_B0_OFFSET 0x0000995c +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MSB 0 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_LSB 0 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MASK 0x00000001 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MSB 6 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_LSB 1 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MASK 0x0000007e +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_GET(x) (((x) & 0x0000007e) >> 1) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_SET(x) (((x) << 1) & 0x0000007e) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MSB 16 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_LSB 7 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MASK 0x0001ff80 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_GET(x) (((x) & 0x0001ff80) >> 7) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_SET(x) (((x) << 7) & 0x0001ff80) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MSB 24 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_LSB 17 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MASK 0x01fe0000 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_GET(x) (((x) & 0x01fe0000) >> 17) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_SET(x) (((x) << 17) & 0x01fe0000) + +/* macros for BB_switch_table_chn_b0 */ +#define PHY_BB_SWITCH_TABLE_CHN_B0_ADDRESS 0x00009960 +#define PHY_BB_SWITCH_TABLE_CHN_B0_OFFSET 0x00009960 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MSB 1 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_LSB 0 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MASK 0x00000003 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_SET(x) (((x) << 0) & 0x00000003) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MSB 3 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_LSB 2 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MASK 0x0000000c +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MSB 5 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_LSB 4 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MASK 0x00000030 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_SET(x) (((x) << 4) & 0x00000030) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MSB 7 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_LSB 6 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MASK 0x000000c0 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MSB 9 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_LSB 8 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MASK 0x00000300 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_SET(x) (((x) << 8) & 0x00000300) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MSB 11 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_LSB 10 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MASK 0x00000c00 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_GET(x) (((x) & 0x00000c00) >> 10) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_SET(x) (((x) << 10) & 0x00000c00) + +/* macros for BB_switch_table_com1 */ +#define PHY_BB_SWITCH_TABLE_COM1_ADDRESS 0x00009964 +#define PHY_BB_SWITCH_TABLE_COM1_OFFSET 0x00009964 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MSB 3 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_LSB 0 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MASK 0x0000000f +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MSB 7 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_LSB 4 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MASK 0x000000f0 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MSB 11 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_LSB 8 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MASK 0x00000f00 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MSB 15 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_LSB 12 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MASK 0x0000f000 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_SET(x) (((x) << 12) & 0x0000f000) + +/* macros for BB_cca_ctrl_2_b0 */ +#define PHY_BB_CCA_CTRL_2_B0_ADDRESS 0x00009968 +#define PHY_BB_CCA_CTRL_2_B0_OFFSET 0x00009968 +#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_MSB 8 +#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_LSB 0 +#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_MASK 0x000001ff +#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_GET(x) (((x) & 0x000001ff) >> 0) +#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_SET(x) (((x) << 0) & 0x000001ff) +#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_MSB 9 +#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_LSB 9 +#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_MASK 0x00000200 +#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_MSB 17 +#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_LSB 10 +#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_MASK 0x0003fc00 +#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_GET(x) (((x) & 0x0003fc00) >> 10) +#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_SET(x) (((x) << 10) & 0x0003fc00) +#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_MSB 18 +#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_LSB 18 +#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_MASK 0x00040000 +#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_SET(x) (((x) << 18) & 0x00040000) + +/* macros for BB_switch_table_com2 */ +#define PHY_BB_SWITCH_TABLE_COM2_ADDRESS 0x0000996c +#define PHY_BB_SWITCH_TABLE_COM2_OFFSET 0x0000996c +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_MSB 3 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_LSB 0 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_MASK 0x0000000f +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_MSB 7 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_LSB 4 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_MASK 0x000000f0 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_MSB 11 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_LSB 8 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_MASK 0x00000f00 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_MSB 15 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_LSB 12 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_MASK 0x0000f000 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_MSB 19 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_LSB 16 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_MASK 0x000f0000 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_MSB 23 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_LSB 20 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_MASK 0x00f00000 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_GET(x) (((x) & 0x00f00000) >> 20) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_SET(x) (((x) << 20) & 0x00f00000) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_MSB 27 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_LSB 24 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_MASK 0x0f000000 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_GET(x) (((x) & 0x0f000000) >> 24) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_SET(x) (((x) << 24) & 0x0f000000) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_MSB 31 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_LSB 28 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_MASK 0xf0000000 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_GET(x) (((x) & 0xf0000000) >> 28) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_SET(x) (((x) << 28) & 0xf0000000) + +/* macros for BB_restart */ +#define PHY_BB_RESTART_ADDRESS 0x00009970 +#define PHY_BB_RESTART_OFFSET 0x00009970 +#define PHY_BB_RESTART_ENABLE_RESTART_MSB 0 +#define PHY_BB_RESTART_ENABLE_RESTART_LSB 0 +#define PHY_BB_RESTART_ENABLE_RESTART_MASK 0x00000001 +#define PHY_BB_RESTART_ENABLE_RESTART_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_RESTART_ENABLE_RESTART_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_MSB 5 +#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_LSB 1 +#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_MASK 0x0000003e +#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_GET(x) (((x) & 0x0000003e) >> 1) +#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_SET(x) (((x) << 1) & 0x0000003e) +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_MSB 6 +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_LSB 6 +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_MASK 0x00000040 +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_SET(x) (((x) << 6) & 0x00000040) +#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_MSB 11 +#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_LSB 7 +#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_MASK 0x00000f80 +#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_GET(x) (((x) & 0x00000f80) >> 7) +#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_SET(x) (((x) << 7) & 0x00000f80) +#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_MSB 17 +#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_LSB 12 +#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_MASK 0x0003f000 +#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_MSB 20 +#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_LSB 18 +#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_MASK 0x001c0000 +#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_GET(x) (((x) & 0x001c0000) >> 18) +#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_SET(x) (((x) << 18) & 0x001c0000) +#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_MSB 21 +#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_LSB 21 +#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_MASK 0x00200000 +#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_SET(x) (((x) << 21) & 0x00200000) +#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_MSB 28 +#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_LSB 22 +#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_MASK 0x1fc00000 +#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_GET(x) (((x) & 0x1fc00000) >> 22) +#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_SET(x) (((x) << 22) & 0x1fc00000) +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_MSB 29 +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_LSB 29 +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_MASK 0x20000000 +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_RESTART_DISABLE_DC_RESTART_MSB 30 +#define PHY_BB_RESTART_DISABLE_DC_RESTART_LSB 30 +#define PHY_BB_RESTART_DISABLE_DC_RESTART_MASK 0x40000000 +#define PHY_BB_RESTART_DISABLE_DC_RESTART_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_RESTART_DISABLE_DC_RESTART_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_RESTART_RESTART_MODE_BW40_MSB 31 +#define PHY_BB_RESTART_RESTART_MODE_BW40_LSB 31 +#define PHY_BB_RESTART_RESTART_MODE_BW40_MASK 0x80000000 +#define PHY_BB_RESTART_RESTART_MODE_BW40_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_RESTART_RESTART_MODE_BW40_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_scrambler_seed */ +#define PHY_BB_SCRAMBLER_SEED_ADDRESS 0x00009978 +#define PHY_BB_SCRAMBLER_SEED_OFFSET 0x00009978 +#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MSB 6 +#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_LSB 0 +#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MASK 0x0000007f +#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_SET(x) (((x) << 0) & 0x0000007f) + +/* macros for BB_rfbus_request */ +#define PHY_BB_RFBUS_REQUEST_ADDRESS 0x0000997c +#define PHY_BB_RFBUS_REQUEST_OFFSET 0x0000997c +#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MSB 0 +#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_LSB 0 +#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MASK 0x00000001 +#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_SET(x) (((x) << 0) & 0x00000001) + +/* macros for BB_timing_control_11 */ +#define PHY_BB_TIMING_CONTROL_11_ADDRESS 0x000099a0 +#define PHY_BB_TIMING_CONTROL_11_OFFSET 0x000099a0 +#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_MSB 19 +#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_LSB 0 +#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_MASK 0x000fffff +#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_GET(x) (((x) & 0x000fffff) >> 0) +#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_SET(x) (((x) << 0) & 0x000fffff) +#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MSB 29 +#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_LSB 20 +#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MASK 0x3ff00000 +#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_GET(x) (((x) & 0x3ff00000) >> 20) +#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_SET(x) (((x) << 20) & 0x3ff00000) +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MSB 30 +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_LSB 30 +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MASK 0x40000000 +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MSB 31 +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_LSB 31 +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MASK 0x80000000 +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_multichain_enable */ +#define PHY_BB_MULTICHAIN_ENABLE_ADDRESS 0x000099a4 +#define PHY_BB_MULTICHAIN_ENABLE_OFFSET 0x000099a4 +#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MSB 2 +#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_LSB 0 +#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK 0x00000007 +#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_SET(x) (((x) << 0) & 0x00000007) + +/* macros for BB_multichain_control */ +#define PHY_BB_MULTICHAIN_CONTROL_ADDRESS 0x000099a8 +#define PHY_BB_MULTICHAIN_CONTROL_OFFSET 0x000099a8 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MSB 0 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_LSB 0 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MASK 0x00000001 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MSB 7 +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_LSB 1 +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MASK 0x000000fe +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_GET(x) (((x) & 0x000000fe) >> 1) +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_SET(x) (((x) << 1) & 0x000000fe) +#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MSB 8 +#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_LSB 8 +#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MASK 0x00000100 +#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MSB 9 +#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_LSB 9 +#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MASK 0x00000200 +#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MSB 20 +#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_LSB 10 +#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MASK 0x001ffc00 +#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_GET(x) (((x) & 0x001ffc00) >> 10) +#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_SET(x) (((x) << 10) & 0x001ffc00) +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MSB 28 +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_LSB 22 +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MASK 0x1fc00000 +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_GET(x) (((x) & 0x1fc00000) >> 22) +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_SET(x) (((x) << 22) & 0x1fc00000) +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MSB 29 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_LSB 29 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MASK 0x20000000 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_SET(x) (((x) << 29) & 0x20000000) + +/* macros for BB_multichain_gain_ctrl */ +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ADDRESS 0x000099ac +#define PHY_BB_MULTICHAIN_GAIN_CTRL_OFFSET 0x000099ac +#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_MSB 7 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_LSB 0 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_MASK 0x000000ff +#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_MSB 8 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_LSB 8 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_MASK 0x00000100 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_MSB 14 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_LSB 9 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_MASK 0x00007e00 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_GET(x) (((x) & 0x00007e00) >> 9) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_SET(x) (((x) << 9) & 0x00007e00) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_MSB 20 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_LSB 15 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_MASK 0x001f8000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_GET(x) (((x) & 0x001f8000) >> 15) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_SET(x) (((x) << 15) & 0x001f8000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_MSB 21 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_LSB 21 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_MASK 0x00200000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_SET(x) (((x) << 21) & 0x00200000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_MSB 22 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_LSB 22 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_MASK 0x00400000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_MSB 23 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_LSB 23 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_MASK 0x00800000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_SET(x) (((x) << 23) & 0x00800000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_MSB 24 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_LSB 24 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_MASK 0x01000000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_SET(x) (((x) << 24) & 0x01000000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_MSB 26 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_LSB 25 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_MASK 0x06000000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_GET(x) (((x) & 0x06000000) >> 25) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_SET(x) (((x) << 25) & 0x06000000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_MSB 28 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_LSB 27 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_MASK 0x18000000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_GET(x) (((x) & 0x18000000) >> 27) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_SET(x) (((x) << 27) & 0x18000000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_MSB 29 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_LSB 29 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_MASK 0x20000000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_MSB 30 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_LSB 30 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_MASK 0x40000000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_SET(x) (((x) << 30) & 0x40000000) + +/* macros for BB_adc_gain_dc_corr_b0 */ +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADDRESS 0x000099b4 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_OFFSET 0x000099b4 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MSB 5 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_LSB 0 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MASK 0x0000003f +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MSB 11 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_LSB 6 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MASK 0x00000fc0 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MSB 20 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_LSB 12 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MASK 0x001ff000 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_GET(x) (((x) & 0x001ff000) >> 12) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_SET(x) (((x) << 12) & 0x001ff000) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MSB 29 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_LSB 21 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MASK 0x3fe00000 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_GET(x) (((x) & 0x3fe00000) >> 21) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_SET(x) (((x) << 21) & 0x3fe00000) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_MSB 30 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_LSB 30 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_MASK 0x40000000 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_MSB 31 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_LSB 31 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_MASK 0x80000000 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_ext_chan_pwr_thr_1 */ +#define PHY_BB_EXT_CHAN_PWR_THR_1_ADDRESS 0x000099b8 +#define PHY_BB_EXT_CHAN_PWR_THR_1_OFFSET 0x000099b8 +#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_MSB 7 +#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_LSB 0 +#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_MASK 0x000000ff +#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_MSB 15 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_LSB 8 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_MASK 0x0000ff00 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_MSB 20 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_LSB 16 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_MASK 0x001f0000 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_MSB 26 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_LSB 21 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_MASK 0x07e00000 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_GET(x) (((x) & 0x07e00000) >> 21) +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_SET(x) (((x) << 21) & 0x07e00000) + +/* macros for BB_ext_chan_pwr_thr_2_b0 */ +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_ADDRESS 0x000099bc +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_OFFSET 0x000099bc +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_MSB 8 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_LSB 0 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_MASK 0x000001ff +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_GET(x) (((x) & 0x000001ff) >> 0) +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_SET(x) (((x) << 0) & 0x000001ff) +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_MSB 15 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_LSB 9 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_MASK 0x0000fe00 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_GET(x) (((x) & 0x0000fe00) >> 9) +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_SET(x) (((x) << 9) & 0x0000fe00) +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_MSB 24 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_LSB 16 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_MASK 0x01ff0000 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_GET(x) (((x) & 0x01ff0000) >> 16) + +/* macros for BB_ext_chan_scorr_thr */ +#define PHY_BB_EXT_CHAN_SCORR_THR_ADDRESS 0x000099c0 +#define PHY_BB_EXT_CHAN_SCORR_THR_OFFSET 0x000099c0 +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_MSB 6 +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_LSB 0 +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_MASK 0x0000007f +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_MSB 13 +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_LSB 7 +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_MASK 0x00003f80 +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_GET(x) (((x) & 0x00003f80) >> 7) +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_SET(x) (((x) << 7) & 0x00003f80) +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_MSB 20 +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_LSB 14 +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_MASK 0x001fc000 +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_GET(x) (((x) & 0x001fc000) >> 14) +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_SET(x) (((x) << 14) & 0x001fc000) +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_MSB 27 +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_LSB 21 +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_MASK 0x0fe00000 +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_GET(x) (((x) & 0x0fe00000) >> 21) +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_SET(x) (((x) << 21) & 0x0fe00000) +#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_MSB 28 +#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_LSB 28 +#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_MASK 0x10000000 +#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_SET(x) (((x) << 28) & 0x10000000) + +/* macros for BB_ext_chan_detect_win */ +#define PHY_BB_EXT_CHAN_DETECT_WIN_ADDRESS 0x000099c4 +#define PHY_BB_EXT_CHAN_DETECT_WIN_OFFSET 0x000099c4 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_MSB 3 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LSB 0 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_MASK 0x0000000f +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_MSB 7 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_LSB 4 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_MASK 0x000000f0 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_MSB 12 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_LSB 8 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_MASK 0x00001f00 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_SET(x) (((x) << 8) & 0x00001f00) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_MSB 15 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_LSB 13 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_MASK 0x0000e000 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_MSB 18 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_LSB 16 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_MASK 0x00070000 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_SET(x) (((x) << 16) & 0x00070000) +#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_MSB 24 +#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_LSB 19 +#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_MASK 0x01f80000 +#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_GET(x) (((x) & 0x01f80000) >> 19) +#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_SET(x) (((x) << 19) & 0x01f80000) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_MSB 28 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_LSB 25 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_MASK 0x1e000000 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_GET(x) (((x) & 0x1e000000) >> 25) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_SET(x) (((x) << 25) & 0x1e000000) + +/* macros for BB_pwr_thr_20_40_det */ +#define PHY_BB_PWR_THR_20_40_DET_ADDRESS 0x000099c8 +#define PHY_BB_PWR_THR_20_40_DET_OFFSET 0x000099c8 +#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_MSB 4 +#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_LSB 0 +#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_MASK 0x0000001f +#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_MSB 10 +#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_LSB 5 +#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_MASK 0x000007e0 +#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_GET(x) (((x) & 0x000007e0) >> 5) +#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_SET(x) (((x) << 5) & 0x000007e0) +#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_MSB 15 +#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_LSB 11 +#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_MASK 0x0000f800 +#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_GET(x) (((x) & 0x0000f800) >> 11) +#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_SET(x) (((x) << 11) & 0x0000f800) +#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_MSB 23 +#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_LSB 16 +#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_MASK 0x00ff0000 +#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_MSB 28 +#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_LSB 24 +#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_MASK 0x1f000000 +#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_GET(x) (((x) & 0x1f000000) >> 24) +#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_SET(x) (((x) << 24) & 0x1f000000) +#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_MSB 29 +#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_LSB 29 +#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_MASK 0x20000000 +#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_MSB 30 +#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_LSB 30 +#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_MASK 0x40000000 +#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_SET(x) (((x) << 30) & 0x40000000) + +/* macros for BB_short_gi_delta_slope */ +#define PHY_BB_SHORT_GI_DELTA_SLOPE_ADDRESS 0x000099d0 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_OFFSET 0x000099d0 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_MSB 3 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_LSB 0 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_MASK 0x0000000f +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_MSB 18 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_LSB 4 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_MASK 0x0007fff0 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_GET(x) (((x) & 0x0007fff0) >> 4) +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_SET(x) (((x) << 4) & 0x0007fff0) + +/* macros for BB_chaninfo_ctrl */ +#define PHY_BB_CHANINFO_CTRL_ADDRESS 0x000099dc +#define PHY_BB_CHANINFO_CTRL_OFFSET 0x000099dc +#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MSB 0 +#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_LSB 0 +#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MASK 0x00000001 +#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MSB 1 +#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_LSB 1 +#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MASK 0x00000002 +#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_SET(x) (((x) << 1) & 0x00000002) + +/* macros for BB_heavy_clip_ctrl */ +#define PHY_BB_HEAVY_CLIP_CTRL_ADDRESS 0x000099e0 +#define PHY_BB_HEAVY_CLIP_CTRL_OFFSET 0x000099e0 +#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_MSB 8 +#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_LSB 0 +#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_MASK 0x000001ff +#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_GET(x) (((x) & 0x000001ff) >> 0) +#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_SET(x) (((x) << 0) & 0x000001ff) +#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_MSB 9 +#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_LSB 9 +#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_MASK 0x00000200 +#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_SET(x) (((x) << 9) & 0x00000200) + +/* macros for BB_heavy_clip_20 */ +#define PHY_BB_HEAVY_CLIP_20_ADDRESS 0x000099e4 +#define PHY_BB_HEAVY_CLIP_20_OFFSET 0x000099e4 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_MSB 7 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_LSB 0 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_MASK 0x000000ff +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_MSB 15 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_LSB 8 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_MASK 0x0000ff00 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_MSB 23 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_LSB 16 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_MASK 0x00ff0000 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_MSB 31 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_LSB 24 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_MASK 0xff000000 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_heavy_clip_40 */ +#define PHY_BB_HEAVY_CLIP_40_ADDRESS 0x000099e8 +#define PHY_BB_HEAVY_CLIP_40_OFFSET 0x000099e8 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_MSB 7 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_LSB 0 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_MASK 0x000000ff +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_MSB 15 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_LSB 8 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_MASK 0x0000ff00 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_MSB 23 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_LSB 16 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_MASK 0x00ff0000 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_MSB 31 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_LSB 24 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_MASK 0xff000000 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_rifs_srch */ +#define PHY_BB_RIFS_SRCH_ADDRESS 0x000099ec +#define PHY_BB_RIFS_SRCH_OFFSET 0x000099ec +#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_MSB 7 +#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_LSB 0 +#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_MASK 0x000000ff +#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_MSB 15 +#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_LSB 8 +#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_MASK 0x0000ff00 +#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_MSB 25 +#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_LSB 16 +#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_MASK 0x03ff0000 +#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_GET(x) (((x) & 0x03ff0000) >> 16) +#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_SET(x) (((x) << 16) & 0x03ff0000) +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_MSB 26 +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_LSB 26 +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_MASK 0x04000000 +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_SET(x) (((x) << 26) & 0x04000000) +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_MSB 27 +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_LSB 27 +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_MASK 0x08000000 +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_SET(x) (((x) << 27) & 0x08000000) + +/* macros for BB_iq_adc_cal_mode */ +#define PHY_BB_IQ_ADC_CAL_MODE_ADDRESS 0x000099f0 +#define PHY_BB_IQ_ADC_CAL_MODE_OFFSET 0x000099f0 +#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MSB 1 +#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_LSB 0 +#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MASK 0x00000003 +#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_SET(x) (((x) << 0) & 0x00000003) +#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MSB 2 +#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_LSB 2 +#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MASK 0x00000004 +#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_SET(x) (((x) << 2) & 0x00000004) + +/* macros for BB_per_chain_csd */ +#define PHY_BB_PER_CHAIN_CSD_ADDRESS 0x000099fc +#define PHY_BB_PER_CHAIN_CSD_OFFSET 0x000099fc +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_MSB 4 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_LSB 0 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_MASK 0x0000001f +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_MSB 9 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_LSB 5 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_MASK 0x000003e0 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_MSB 14 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_LSB 10 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_MASK 0x00007c00 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_SET(x) (((x) << 10) & 0x00007c00) + +/* macros for BB_rx_ocgain */ +#define PHY_BB_RX_OCGAIN_ADDRESS 0x00009a00 +#define PHY_BB_RX_OCGAIN_OFFSET 0x00009a00 +#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_MSB 31 +#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_LSB 0 +#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_MASK 0xffffffff +#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_crc */ +#define PHY_BB_TX_CRC_ADDRESS 0x00009c00 +#define PHY_BB_TX_CRC_OFFSET 0x00009c00 +#define PHY_BB_TX_CRC_TX_CRC_MSB 15 +#define PHY_BB_TX_CRC_TX_CRC_LSB 0 +#define PHY_BB_TX_CRC_TX_CRC_MASK 0x0000ffff +#define PHY_BB_TX_CRC_TX_CRC_GET(x) (((x) & 0x0000ffff) >> 0) + +/* macros for BB_iq_adc_meas_0_b0 */ +#define PHY_BB_IQ_ADC_MEAS_0_B0_ADDRESS 0x00009c10 +#define PHY_BB_IQ_ADC_MEAS_0_B0_OFFSET 0x00009c10 +#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MSB 31 +#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_LSB 0 +#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MASK 0xffffffff +#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_GET(x) (((x) & 0xffffffff) >> 0) + +/* macros for BB_iq_adc_meas_1_b0 */ +#define PHY_BB_IQ_ADC_MEAS_1_B0_ADDRESS 0x00009c14 +#define PHY_BB_IQ_ADC_MEAS_1_B0_OFFSET 0x00009c14 +#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MSB 31 +#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_LSB 0 +#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MASK 0xffffffff +#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_GET(x) (((x) & 0xffffffff) >> 0) + +/* macros for BB_iq_adc_meas_2_b0 */ +#define PHY_BB_IQ_ADC_MEAS_2_B0_ADDRESS 0x00009c18 +#define PHY_BB_IQ_ADC_MEAS_2_B0_OFFSET 0x00009c18 +#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MSB 31 +#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_LSB 0 +#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MASK 0xffffffff +#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_GET(x) (((x) & 0xffffffff) >> 0) + +/* macros for BB_iq_adc_meas_3_b0 */ +#define PHY_BB_IQ_ADC_MEAS_3_B0_ADDRESS 0x00009c1c +#define PHY_BB_IQ_ADC_MEAS_3_B0_OFFSET 0x00009c1c +#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MSB 31 +#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_LSB 0 +#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MASK 0xffffffff +#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_GET(x) (((x) & 0xffffffff) >> 0) + +/* macros for BB_rfbus_grant */ +#define PHY_BB_RFBUS_GRANT_ADDRESS 0x00009c20 +#define PHY_BB_RFBUS_GRANT_OFFSET 0x00009c20 +#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MSB 0 +#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_LSB 0 +#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MASK 0x00000001 +#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_RFBUS_GRANT_BT_ANT_MSB 1 +#define PHY_BB_RFBUS_GRANT_BT_ANT_LSB 1 +#define PHY_BB_RFBUS_GRANT_BT_ANT_MASK 0x00000002 +#define PHY_BB_RFBUS_GRANT_BT_ANT_GET(x) (((x) & 0x00000002) >> 1) + +/* macros for BB_tstadc */ +#define PHY_BB_TSTADC_ADDRESS 0x00009c24 +#define PHY_BB_TSTADC_OFFSET 0x00009c24 +#define PHY_BB_TSTADC_TSTADC_OUT_Q_MSB 9 +#define PHY_BB_TSTADC_TSTADC_OUT_Q_LSB 0 +#define PHY_BB_TSTADC_TSTADC_OUT_Q_MASK 0x000003ff +#define PHY_BB_TSTADC_TSTADC_OUT_Q_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_TSTADC_TSTADC_OUT_I_MSB 19 +#define PHY_BB_TSTADC_TSTADC_OUT_I_LSB 10 +#define PHY_BB_TSTADC_TSTADC_OUT_I_MASK 0x000ffc00 +#define PHY_BB_TSTADC_TSTADC_OUT_I_GET(x) (((x) & 0x000ffc00) >> 10) + +/* macros for BB_tstdac */ +#define PHY_BB_TSTDAC_ADDRESS 0x00009c28 +#define PHY_BB_TSTDAC_OFFSET 0x00009c28 +#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_MSB 9 +#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_LSB 0 +#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_MASK 0x000003ff +#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_TSTDAC_TSTDAC_OUT_I_MSB 19 +#define PHY_BB_TSTDAC_TSTDAC_OUT_I_LSB 10 +#define PHY_BB_TSTDAC_TSTDAC_OUT_I_MASK 0x000ffc00 +#define PHY_BB_TSTDAC_TSTDAC_OUT_I_GET(x) (((x) & 0x000ffc00) >> 10) + +/* macros for BB_illegal_tx_rate */ +#define PHY_BB_ILLEGAL_TX_RATE_ADDRESS 0x00009c30 +#define PHY_BB_ILLEGAL_TX_RATE_OFFSET 0x00009c30 +#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_MSB 0 +#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_LSB 0 +#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_MASK 0x00000001 +#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_GET(x) (((x) & 0x00000001) >> 0) + +/* macros for BB_spur_report_b0 */ +#define PHY_BB_SPUR_REPORT_B0_ADDRESS 0x00009c34 +#define PHY_BB_SPUR_REPORT_B0_OFFSET 0x00009c34 +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MSB 7 +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_LSB 0 +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MASK 0x000000ff +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MSB 15 +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_LSB 8 +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MASK 0x0000ff00 +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MSB 31 +#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_LSB 16 +#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MASK 0xffff0000 +#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_GET(x) (((x) & 0xffff0000) >> 16) + +/* macros for BB_channel_status */ +#define PHY_BB_CHANNEL_STATUS_ADDRESS 0x00009c38 +#define PHY_BB_CHANNEL_STATUS_OFFSET 0x00009c38 +#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MSB 0 +#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_LSB 0 +#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MASK 0x00000001 +#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MSB 1 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_LSB 1 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MASK 0x00000002 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MSB 2 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_LSB 2 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MASK 0x00000004 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MSB 3 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_LSB 3 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MASK 0x00000008 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MSB 5 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_LSB 4 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MASK 0x00000030 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MSB 7 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_LSB 6 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MASK 0x000000c0 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MSB 9 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_LSB 8 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MASK 0x00000300 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MSB 13 +#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_LSB 10 +#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MASK 0x00003c00 +#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_GET(x) (((x) & 0x00003c00) >> 10) +#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MSB 16 +#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_LSB 14 +#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MASK 0x0001c000 +#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_GET(x) (((x) & 0x0001c000) >> 14) + +/* macros for BB_rssi_b0 */ +#define PHY_BB_RSSI_B0_ADDRESS 0x00009c3c +#define PHY_BB_RSSI_B0_OFFSET 0x00009c3c +#define PHY_BB_RSSI_B0_RSSI_0_MSB 7 +#define PHY_BB_RSSI_B0_RSSI_0_LSB 0 +#define PHY_BB_RSSI_B0_RSSI_0_MASK 0x000000ff +#define PHY_BB_RSSI_B0_RSSI_0_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_RSSI_B0_RSSI_EXT_0_MSB 15 +#define PHY_BB_RSSI_B0_RSSI_EXT_0_LSB 8 +#define PHY_BB_RSSI_B0_RSSI_EXT_0_MASK 0x0000ff00 +#define PHY_BB_RSSI_B0_RSSI_EXT_0_GET(x) (((x) & 0x0000ff00) >> 8) + +/* macros for BB_spur_est_cck_report_b0 */ +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_ADDRESS 0x00009c40 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_OFFSET 0x00009c40 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_MSB 7 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_LSB 0 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_MASK 0x000000ff +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_MSB 15 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_LSB 8 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_MASK 0x0000ff00 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_MSB 23 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_LSB 16 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_MASK 0x00ff0000 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_MSB 31 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_LSB 24 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_MASK 0xff000000 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_GET(x) (((x) & 0xff000000) >> 24) + +/* macros for BB_chan_info_noise_pwr */ +#define PHY_BB_CHAN_INFO_NOISE_PWR_ADDRESS 0x00009cac +#define PHY_BB_CHAN_INFO_NOISE_PWR_OFFSET 0x00009cac +#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_MSB 11 +#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_LSB 0 +#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_MASK 0x00000fff +#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_GET(x) (((x) & 0x00000fff) >> 0) + +/* macros for BB_chan_info_gain_diff */ +#define PHY_BB_CHAN_INFO_GAIN_DIFF_ADDRESS 0x00009cb0 +#define PHY_BB_CHAN_INFO_GAIN_DIFF_OFFSET 0x00009cb0 +#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_MSB 11 +#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_LSB 0 +#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_MASK 0x00000fff +#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_GET(x) (((x) & 0x00000fff) >> 0) + +/* macros for BB_chan_info_fine_timing */ +#define PHY_BB_CHAN_INFO_FINE_TIMING_ADDRESS 0x00009cb4 +#define PHY_BB_CHAN_INFO_FINE_TIMING_OFFSET 0x00009cb4 +#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MSB 11 +#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_LSB 0 +#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MASK 0x00000fff +#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MSB 21 +#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_LSB 12 +#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MASK 0x003ff000 +#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_GET(x) (((x) & 0x003ff000) >> 12) + +/* macros for BB_chan_info_gain_b0 */ +#define PHY_BB_CHAN_INFO_GAIN_B0_ADDRESS 0x00009cb8 +#define PHY_BB_CHAN_INFO_GAIN_B0_OFFSET 0x00009cb8 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MSB 7 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_LSB 0 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MASK 0x000000ff +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MSB 15 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_LSB 8 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MASK 0x0000ff00 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MSB 16 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_LSB 16 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MASK 0x00010000 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MSB 17 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_LSB 17 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MASK 0x00020000 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_GET(x) (((x) & 0x00020000) >> 17) + +/* macros for BB_chan_info_chan_tab_b0 */ +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_ADDRESS 0x00009cbc +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_OFFSET 0x00009cbc +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_MSB 5 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_LSB 0 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_MASK 0x0000003f +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_MSB 11 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_LSB 6 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_MASK 0x00000fc0 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_MSB 15 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_LSB 12 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_MASK 0x0000f000 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_MSB 21 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_LSB 16 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_MASK 0x003f0000 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_MSB 27 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_LSB 22 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_MASK 0x0fc00000 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_GET(x) (((x) & 0x0fc00000) >> 22) +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_MSB 31 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_LSB 28 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_MASK 0xf0000000 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_GET(x) (((x) & 0xf0000000) >> 28) + +/* macros for BB_paprd_am2am_mask */ +#define PHY_BB_PAPRD_AM2AM_MASK_ADDRESS 0x00009de4 +#define PHY_BB_PAPRD_AM2AM_MASK_OFFSET 0x00009de4 +#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MSB 24 +#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_LSB 0 +#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MASK 0x01ffffff +#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_GET(x) (((x) & 0x01ffffff) >> 0) +#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_SET(x) (((x) << 0) & 0x01ffffff) + +/* macros for BB_paprd_am2pm_mask */ +#define PHY_BB_PAPRD_AM2PM_MASK_ADDRESS 0x00009de8 +#define PHY_BB_PAPRD_AM2PM_MASK_OFFSET 0x00009de8 +#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MSB 24 +#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_LSB 0 +#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MASK 0x01ffffff +#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_GET(x) (((x) & 0x01ffffff) >> 0) +#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_SET(x) (((x) << 0) & 0x01ffffff) + +/* macros for BB_paprd_ht40_mask */ +#define PHY_BB_PAPRD_HT40_MASK_ADDRESS 0x00009dec +#define PHY_BB_PAPRD_HT40_MASK_OFFSET 0x00009dec +#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MSB 24 +#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_LSB 0 +#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MASK 0x01ffffff +#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_GET(x) (((x) & 0x01ffffff) >> 0) +#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_SET(x) (((x) << 0) & 0x01ffffff) + +/* macros for BB_paprd_ctrl0 */ +#define PHY_BB_PAPRD_CTRL0_ADDRESS 0x00009df0 +#define PHY_BB_PAPRD_CTRL0_OFFSET 0x00009df0 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_MSB 0 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_LSB 0 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_MASK 0x00000001 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_MSB 1 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_LSB 1 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_MASK 0x00000002 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_MSB 26 +#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_LSB 2 +#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_MASK 0x07fffffc +#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_GET(x) (((x) & 0x07fffffc) >> 2) +#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_SET(x) (((x) << 2) & 0x07fffffc) +#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_MSB 31 +#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_LSB 27 +#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_MASK 0xf8000000 +#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for BB_paprd_ctrl1 */ +#define PHY_BB_PAPRD_CTRL1_ADDRESS 0x00009df4 +#define PHY_BB_PAPRD_CTRL1_OFFSET 0x00009df4 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_MSB 0 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_LSB 0 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_MASK 0x00000001 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_MSB 1 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_LSB 1 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_MASK 0x00000002 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_MSB 2 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_LSB 2 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_MASK 0x00000004 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_MSB 8 +#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_LSB 3 +#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_MASK 0x000001f8 +#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_GET(x) (((x) & 0x000001f8) >> 3) +#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_SET(x) (((x) << 3) & 0x000001f8) +#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_MSB 16 +#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_LSB 9 +#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_MASK 0x0001fe00 +#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_GET(x) (((x) & 0x0001fe00) >> 9) +#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_SET(x) (((x) << 9) & 0x0001fe00) +#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_MSB 26 +#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_LSB 17 +#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_MASK 0x07fe0000 +#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_GET(x) (((x) & 0x07fe0000) >> 17) +#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_SET(x) (((x) << 17) & 0x07fe0000) +#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_MSB 27 +#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_LSB 27 +#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_MASK 0x08000000 +#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_SET(x) (((x) << 27) & 0x08000000) + +/* macros for BB_pa_gain123 */ +#define PHY_BB_PA_GAIN123_ADDRESS 0x00009df8 +#define PHY_BB_PA_GAIN123_OFFSET 0x00009df8 +#define PHY_BB_PA_GAIN123_PA_GAIN1_MSB 9 +#define PHY_BB_PA_GAIN123_PA_GAIN1_LSB 0 +#define PHY_BB_PA_GAIN123_PA_GAIN1_MASK 0x000003ff +#define PHY_BB_PA_GAIN123_PA_GAIN1_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_PA_GAIN123_PA_GAIN1_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_PA_GAIN123_PA_GAIN2_MSB 19 +#define PHY_BB_PA_GAIN123_PA_GAIN2_LSB 10 +#define PHY_BB_PA_GAIN123_PA_GAIN2_MASK 0x000ffc00 +#define PHY_BB_PA_GAIN123_PA_GAIN2_GET(x) (((x) & 0x000ffc00) >> 10) +#define PHY_BB_PA_GAIN123_PA_GAIN2_SET(x) (((x) << 10) & 0x000ffc00) +#define PHY_BB_PA_GAIN123_PA_GAIN3_MSB 29 +#define PHY_BB_PA_GAIN123_PA_GAIN3_LSB 20 +#define PHY_BB_PA_GAIN123_PA_GAIN3_MASK 0x3ff00000 +#define PHY_BB_PA_GAIN123_PA_GAIN3_GET(x) (((x) & 0x3ff00000) >> 20) +#define PHY_BB_PA_GAIN123_PA_GAIN3_SET(x) (((x) << 20) & 0x3ff00000) + +/* macros for BB_pa_gain45 */ +#define PHY_BB_PA_GAIN45_ADDRESS 0x00009dfc +#define PHY_BB_PA_GAIN45_OFFSET 0x00009dfc +#define PHY_BB_PA_GAIN45_PA_GAIN4_MSB 9 +#define PHY_BB_PA_GAIN45_PA_GAIN4_LSB 0 +#define PHY_BB_PA_GAIN45_PA_GAIN4_MASK 0x000003ff +#define PHY_BB_PA_GAIN45_PA_GAIN4_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_PA_GAIN45_PA_GAIN4_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_PA_GAIN45_PA_GAIN5_MSB 19 +#define PHY_BB_PA_GAIN45_PA_GAIN5_LSB 10 +#define PHY_BB_PA_GAIN45_PA_GAIN5_MASK 0x000ffc00 +#define PHY_BB_PA_GAIN45_PA_GAIN5_GET(x) (((x) & 0x000ffc00) >> 10) +#define PHY_BB_PA_GAIN45_PA_GAIN5_SET(x) (((x) << 10) & 0x000ffc00) +#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_MSB 24 +#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_LSB 20 +#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_MASK 0x01f00000 +#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_SET(x) (((x) << 20) & 0x01f00000) + +/* macros for BB_paprd_pre_post_scale_0 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_ADDRESS 0x00009e00 +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_OFFSET 0x00009e00 +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_1 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_ADDRESS 0x00009e04 +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_OFFSET 0x00009e04 +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_2 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_ADDRESS 0x00009e08 +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_OFFSET 0x00009e08 +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_3 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_ADDRESS 0x00009e0c +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_OFFSET 0x00009e0c +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_4 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_ADDRESS 0x00009e10 +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_OFFSET 0x00009e10 +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_5 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_ADDRESS 0x00009e14 +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_OFFSET 0x00009e14 +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_6 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_ADDRESS 0x00009e18 +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_OFFSET 0x00009e18 +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_7 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_ADDRESS 0x00009e1c +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_OFFSET 0x00009e1c +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_mem_tab */ +#define PHY_BB_PAPRD_MEM_TAB_ADDRESS 0x00009e20 +#define PHY_BB_PAPRD_MEM_TAB_OFFSET 0x00009e20 +#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_MSB 21 +#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_LSB 0 +#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_MASK 0x003fffff +#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_GET(x) (((x) & 0x003fffff) >> 0) +#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_SET(x) (((x) << 0) & 0x003fffff) + +/* macros for BB_peak_det_ctrl_1 */ +#define PHY_BB_PEAK_DET_CTRL_1_ADDRESS 0x0000a000 +#define PHY_BB_PEAK_DET_CTRL_1_OFFSET 0x0000a000 +#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_MSB 0 +#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_LSB 0 +#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_MASK 0x00000001 +#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_MSB 1 +#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_LSB 1 +#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_MASK 0x00000002 +#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_MSB 7 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_LSB 2 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_MASK 0x000000fc +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_MSB 12 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_LSB 8 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_MASK 0x00001f00 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_SET(x) (((x) << 8) & 0x00001f00) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_MSB 17 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_LSB 13 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_MASK 0x0003e000 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_GET(x) (((x) & 0x0003e000) >> 13) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_SET(x) (((x) << 13) & 0x0003e000) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_MSB 22 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_LSB 18 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_MASK 0x007c0000 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_GET(x) (((x) & 0x007c0000) >> 18) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_SET(x) (((x) << 18) & 0x007c0000) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_MSB 29 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_LSB 23 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_MASK 0x3f800000 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_GET(x) (((x) & 0x3f800000) >> 23) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_SET(x) (((x) << 23) & 0x3f800000) +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_MSB 30 +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_LSB 30 +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_MASK 0x40000000 +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_MSB 31 +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_LSB 31 +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_MASK 0x80000000 +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_peak_det_ctrl_2 */ +#define PHY_BB_PEAK_DET_CTRL_2_ADDRESS 0x0000a004 +#define PHY_BB_PEAK_DET_CTRL_2_OFFSET 0x0000a004 +#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_MSB 9 +#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_LSB 0 +#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_MASK 0x000003ff +#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_MSB 14 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_LSB 10 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_MASK 0x00007c00 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_MSB 19 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_LSB 15 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_MASK 0x000f8000 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_GET(x) (((x) & 0x000f8000) >> 15) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_SET(x) (((x) << 15) & 0x000f8000) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_MSB 24 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_LSB 20 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_MASK 0x01f00000 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_MSB 29 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_LSB 25 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_MASK 0x3e000000 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_rx_gain_bounds_1 */ +#define PHY_BB_RX_GAIN_BOUNDS_1_ADDRESS 0x0000a008 +#define PHY_BB_RX_GAIN_BOUNDS_1_OFFSET 0x0000a008 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_MSB 7 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_LSB 0 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_MASK 0x000000ff +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_MSB 15 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_LSB 8 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_MASK 0x0000ff00 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_MSB 23 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_LSB 16 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_MASK 0x00ff0000 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_MSB 24 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_LSB 24 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_MASK 0x01000000 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_SET(x) (((x) << 24) & 0x01000000) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_MSB 25 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_LSB 25 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_MASK 0x02000000 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_SET(x) (((x) << 25) & 0x02000000) + +/* macros for BB_rx_gain_bounds_2 */ +#define PHY_BB_RX_GAIN_BOUNDS_2_ADDRESS 0x0000a00c +#define PHY_BB_RX_GAIN_BOUNDS_2_OFFSET 0x0000a00c +#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_MSB 7 +#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_LSB 0 +#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_MASK 0x000000ff +#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_MSB 15 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_LSB 8 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_MASK 0x0000ff00 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_MSB 23 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_LSB 16 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_MASK 0x00ff0000 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_MSB 31 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_LSB 24 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_MASK 0xff000000 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_peak_det_cal_ctrl */ +#define PHY_BB_PEAK_DET_CAL_CTRL_ADDRESS 0x0000a010 +#define PHY_BB_PEAK_DET_CAL_CTRL_OFFSET 0x0000a010 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_MSB 5 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_LSB 0 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_MASK 0x0000003f +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_MSB 11 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_LSB 6 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_MASK 0x00000fc0 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_MSB 13 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_LSB 12 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_MASK 0x00003000 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_GET(x) (((x) & 0x00003000) >> 12) +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_SET(x) (((x) << 12) & 0x00003000) + +/* macros for BB_agc_dig_dc_ctrl */ +#define PHY_BB_AGC_DIG_DC_CTRL_ADDRESS 0x0000a014 +#define PHY_BB_AGC_DIG_DC_CTRL_OFFSET 0x0000a014 +#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_MSB 0 +#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_LSB 0 +#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_MASK 0x00000001 +#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_MSB 3 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_LSB 1 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_MASK 0x0000000e +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_MSB 9 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_LSB 4 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_MASK 0x000003f0 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_GET(x) (((x) & 0x000003f0) >> 4) +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_SET(x) (((x) << 4) & 0x000003f0) +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_MSB 31 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_LSB 16 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_MASK 0xffff0000 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_GET(x) (((x) & 0xffff0000) >> 16) +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_SET(x) (((x) << 16) & 0xffff0000) + +/* macros for BB_agc_dig_dc_status_i_b0 */ +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_ADDRESS 0x0000a018 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_OFFSET 0x0000a018 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_MSB 8 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_LSB 0 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_MASK 0x000001ff +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_GET(x) (((x) & 0x000001ff) >> 0) +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_MSB 17 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_LSB 9 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_MASK 0x0003fe00 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_GET(x) (((x) & 0x0003fe00) >> 9) +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_MSB 26 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_LSB 18 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_MASK 0x07fc0000 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_GET(x) (((x) & 0x07fc0000) >> 18) + +/* macros for BB_agc_dig_dc_status_q_b0 */ +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_ADDRESS 0x0000a01c +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_OFFSET 0x0000a01c +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_MSB 8 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_LSB 0 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_MASK 0x000001ff +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_GET(x) (((x) & 0x000001ff) >> 0) +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_MSB 17 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_LSB 9 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_MASK 0x0003fe00 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_GET(x) (((x) & 0x0003fe00) >> 9) +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_MSB 26 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_LSB 18 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_MASK 0x07fc0000 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_GET(x) (((x) & 0x07fc0000) >> 18) + +/* macros for BB_bbb_txfir_0 */ +#define PHY_BB_BBB_TXFIR_0_ADDRESS 0x0000a1f4 +#define PHY_BB_BBB_TXFIR_0_OFFSET 0x0000a1f4 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MSB 3 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_LSB 0 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MASK 0x0000000f +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MSB 11 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_LSB 8 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MASK 0x00000f00 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MSB 20 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_LSB 16 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MASK 0x001f0000 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MSB 28 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_LSB 24 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MASK 0x1f000000 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_GET(x) (((x) & 0x1f000000) >> 24) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_SET(x) (((x) << 24) & 0x1f000000) + +/* macros for BB_bbb_txfir_1 */ +#define PHY_BB_BBB_TXFIR_1_ADDRESS 0x0000a1f8 +#define PHY_BB_BBB_TXFIR_1_OFFSET 0x0000a1f8 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MSB 5 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_LSB 0 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MASK 0x0000003f +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MSB 13 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_LSB 8 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MASK 0x00003f00 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MSB 22 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_LSB 16 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MASK 0x007f0000 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_GET(x) (((x) & 0x007f0000) >> 16) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_SET(x) (((x) << 16) & 0x007f0000) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MSB 30 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_LSB 24 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MASK 0x7f000000 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for BB_bbb_txfir_2 */ +#define PHY_BB_BBB_TXFIR_2_ADDRESS 0x0000a1fc +#define PHY_BB_BBB_TXFIR_2_OFFSET 0x0000a1fc +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MSB 7 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_LSB 0 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MASK 0x000000ff +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MSB 15 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_LSB 8 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MASK 0x0000ff00 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MSB 23 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_LSB 16 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MASK 0x00ff0000 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MSB 31 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_LSB 24 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MASK 0xff000000 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_modes_select */ +#define PHY_BB_MODES_SELECT_ADDRESS 0x0000a200 +#define PHY_BB_MODES_SELECT_OFFSET 0x0000a200 +#define PHY_BB_MODES_SELECT_CCK_MODE_MSB 0 +#define PHY_BB_MODES_SELECT_CCK_MODE_LSB 0 +#define PHY_BB_MODES_SELECT_CCK_MODE_MASK 0x00000001 +#define PHY_BB_MODES_SELECT_CCK_MODE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_MODES_SELECT_CCK_MODE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MSB 2 +#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_LSB 2 +#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MASK 0x00000004 +#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_MSB 5 +#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_LSB 5 +#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_MASK 0x00000020 +#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_SET(x) (((x) << 5) & 0x00000020) +#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MSB 6 +#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_LSB 6 +#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MASK 0x00000040 +#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_SET(x) (((x) << 6) & 0x00000040) +#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_MSB 7 +#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_LSB 7 +#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_MASK 0x00000080 +#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_SET(x) (((x) << 7) & 0x00000080) +#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MSB 8 +#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_LSB 8 +#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MASK 0x00000100 +#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_SET(x) (((x) << 8) & 0x00000100) + +/* macros for BB_bbb_tx_ctrl */ +#define PHY_BB_BBB_TX_CTRL_ADDRESS 0x0000a204 +#define PHY_BB_BBB_TX_CTRL_OFFSET 0x0000a204 +#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MSB 0 +#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_LSB 0 +#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MASK 0x00000001 +#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MSB 1 +#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_LSB 1 +#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MASK 0x00000002 +#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MSB 3 +#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_LSB 2 +#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MASK 0x0000000c +#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MSB 4 +#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_LSB 4 +#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MASK 0x00000010 +#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MSB 5 +#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_LSB 5 +#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MASK 0x00000020 +#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_SET(x) (((x) << 5) & 0x00000020) +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MSB 8 +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_LSB 6 +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MASK 0x000001c0 +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_GET(x) (((x) & 0x000001c0) >> 6) +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_SET(x) (((x) << 6) & 0x000001c0) +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MSB 11 +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_LSB 9 +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MASK 0x00000e00 +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_SET(x) (((x) << 9) & 0x00000e00) + +/* macros for BB_bbb_sig_detect */ +#define PHY_BB_BBB_SIG_DETECT_ADDRESS 0x0000a208 +#define PHY_BB_BBB_SIG_DETECT_OFFSET 0x0000a208 +#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_MSB 5 +#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_LSB 0 +#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_MASK 0x0000003f +#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_MSB 12 +#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_LSB 6 +#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_MASK 0x00001fc0 +#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_GET(x) (((x) & 0x00001fc0) >> 6) +#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_SET(x) (((x) << 6) & 0x00001fc0) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_MSB 13 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_LSB 13 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_MASK 0x00002000 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_MSB 14 +#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_LSB 14 +#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_MASK 0x00004000 +#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_MSB 15 +#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_LSB 15 +#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_MASK 0x00008000 +#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_MSB 16 +#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_LSB 16 +#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_MASK 0x00010000 +#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_MSB 17 +#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_LSB 17 +#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_MASK 0x00020000 +#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_MSB 18 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_LSB 18 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_MASK 0x00040000 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_SET(x) (((x) << 18) & 0x00040000) +#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_MSB 19 +#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_LSB 19 +#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_MASK 0x00080000 +#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_SET(x) (((x) << 19) & 0x00080000) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_MSB 20 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_LSB 20 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_MASK 0x00100000 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_SET(x) (((x) << 20) & 0x00100000) +#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_MSB 21 +#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_LSB 21 +#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_MASK 0x00200000 +#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_SET(x) (((x) << 21) & 0x00200000) +#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_MSB 22 +#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_LSB 22 +#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_MASK 0x00400000 +#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_MSB 31 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_LSB 31 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_MASK 0x80000000 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_ext_atten_switch_ctl_b0 */ +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_ADDRESS 0x0000a20c +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_OFFSET 0x0000a20c +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_MSB 5 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_LSB 0 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_MASK 0x0000003f +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_MSB 11 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_LSB 6 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_MASK 0x00000fc0 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_MSB 16 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_LSB 12 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_MASK 0x0001f000 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_MSB 21 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_LSB 17 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_MASK 0x003e0000 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_SET(x) (((x) << 17) & 0x003e0000) + +/* macros for BB_bbb_rx_ctrl_1 */ +#define PHY_BB_BBB_RX_CTRL_1_ADDRESS 0x0000a210 +#define PHY_BB_BBB_RX_CTRL_1_OFFSET 0x0000a210 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_MSB 2 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_LSB 0 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_MASK 0x00000007 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_SET(x) (((x) << 0) & 0x00000007) +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_MSB 7 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_LSB 3 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_MASK 0x000000f8 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_GET(x) (((x) & 0x000000f8) >> 3) +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_SET(x) (((x) << 3) & 0x000000f8) +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_MSB 10 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_LSB 8 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_MASK 0x00000700 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_SET(x) (((x) << 8) & 0x00000700) +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_MSB 15 +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_LSB 11 +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_MASK 0x0000f800 +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_GET(x) (((x) & 0x0000f800) >> 11) +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_SET(x) (((x) << 11) & 0x0000f800) +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_MSB 20 +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_LSB 16 +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_MASK 0x001f0000 +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_MSB 23 +#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_LSB 21 +#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_MASK 0x00e00000 +#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_GET(x) (((x) & 0x00e00000) >> 21) +#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_SET(x) (((x) << 21) & 0x00e00000) +#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_MSB 30 +#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_LSB 24 +#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_MASK 0x7f000000 +#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_SET(x) (((x) << 24) & 0x7f000000) +#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_MSB 31 +#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_LSB 31 +#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_MASK 0x80000000 +#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_bbb_rx_ctrl_2 */ +#define PHY_BB_BBB_RX_CTRL_2_ADDRESS 0x0000a214 +#define PHY_BB_BBB_RX_CTRL_2_OFFSET 0x0000a214 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_MSB 5 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_LSB 0 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_MASK 0x0000003f +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_MSB 11 +#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_LSB 6 +#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_MASK 0x00000fc0 +#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_MSB 16 +#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_LSB 12 +#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_MASK 0x0001f000 +#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_MSB 21 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_LSB 17 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_MASK 0x003e0000 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_SET(x) (((x) << 17) & 0x003e0000) +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_MSB 25 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_LSB 22 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_MASK 0x03c00000 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_GET(x) (((x) & 0x03c00000) >> 22) +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_SET(x) (((x) << 22) & 0x03c00000) +#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_MSB 31 +#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_LSB 26 +#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_MASK 0xfc000000 +#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for BB_bbb_rx_ctrl_3 */ +#define PHY_BB_BBB_RX_CTRL_3_ADDRESS 0x0000a218 +#define PHY_BB_BBB_RX_CTRL_3_OFFSET 0x0000a218 +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_MSB 7 +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_LSB 0 +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_MASK 0x000000ff +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_MSB 15 +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_LSB 8 +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_MASK 0x0000ff00 +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_MSB 23 +#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_LSB 16 +#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_MASK 0x00ff0000 +#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_SET(x) (((x) << 16) & 0x00ff0000) + +/* macros for BB_bbb_rx_ctrl_4 */ +#define PHY_BB_BBB_RX_CTRL_4_ADDRESS 0x0000a21c +#define PHY_BB_BBB_RX_CTRL_4_OFFSET 0x0000a21c +#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_MSB 3 +#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_LSB 0 +#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_MASK 0x0000000f +#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_MSB 15 +#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_LSB 4 +#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_MASK 0x0000fff0 +#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_GET(x) (((x) & 0x0000fff0) >> 4) +#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_SET(x) (((x) << 4) & 0x0000fff0) +#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_MSB 16 +#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_LSB 16 +#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_MASK 0x00010000 +#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_MSB 17 +#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_LSB 17 +#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_MASK 0x00020000 +#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_MSB 18 +#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_LSB 18 +#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_MASK 0x00040000 +#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_SET(x) (((x) << 18) & 0x00040000) +#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_MSB 24 +#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_LSB 19 +#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_MASK 0x01f80000 +#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_GET(x) (((x) & 0x01f80000) >> 19) +#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_SET(x) (((x) << 19) & 0x01f80000) +#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_MSB 30 +#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_LSB 25 +#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_MASK 0x7e000000 +#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_GET(x) (((x) & 0x7e000000) >> 25) +#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_SET(x) (((x) << 25) & 0x7e000000) + +/* macros for BB_bbb_rx_ctrl_5 */ +#define PHY_BB_BBB_RX_CTRL_5_ADDRESS 0x0000a220 +#define PHY_BB_BBB_RX_CTRL_5_OFFSET 0x0000a220 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_MSB 4 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_LSB 0 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_MASK 0x0000001f +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_MSB 9 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_LSB 5 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_MASK 0x000003e0 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_MSB 15 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_LSB 10 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_MASK 0x0000fc00 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_GET(x) (((x) & 0x0000fc00) >> 10) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_SET(x) (((x) << 10) & 0x0000fc00) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_MSB 20 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_LSB 16 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_MASK 0x001f0000 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_MSB 26 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_LSB 21 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_MASK 0x07e00000 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_GET(x) (((x) & 0x07e00000) >> 21) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_SET(x) (((x) << 21) & 0x07e00000) + +/* macros for BB_bbb_rx_ctrl_6 */ +#define PHY_BB_BBB_RX_CTRL_6_ADDRESS 0x0000a224 +#define PHY_BB_BBB_RX_CTRL_6_OFFSET 0x0000a224 +#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_MSB 9 +#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_LSB 0 +#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_MASK 0x000003ff +#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_MSB 10 +#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_LSB 10 +#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_MASK 0x00000400 +#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_MSB 20 +#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_LSB 11 +#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_MASK 0x001ff800 +#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_GET(x) (((x) & 0x001ff800) >> 11) +#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_SET(x) (((x) << 11) & 0x001ff800) + +/* macros for BB_bbb_dagc_ctrl */ +#define PHY_BB_BBB_DAGC_CTRL_ADDRESS 0x0000a228 +#define PHY_BB_BBB_DAGC_CTRL_OFFSET 0x0000a228 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_MSB 0 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_LSB 0 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_MASK 0x00000001 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_MSB 8 +#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_LSB 1 +#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_MASK 0x000001fe +#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_GET(x) (((x) & 0x000001fe) >> 1) +#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_SET(x) (((x) << 1) & 0x000001fe) +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_MSB 9 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_LSB 9 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_MASK 0x00000200 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_MSB 16 +#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_LSB 10 +#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_MASK 0x0001fc00 +#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_GET(x) (((x) & 0x0001fc00) >> 10) +#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_SET(x) (((x) << 10) & 0x0001fc00) +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_MSB 17 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_LSB 17 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_MASK 0x00020000 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_MSB 23 +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_LSB 18 +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_MASK 0x00fc0000 +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_SET(x) (((x) << 18) & 0x00fc0000) +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_MSB 27 +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_LSB 24 +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_MASK 0x0f000000 +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_GET(x) (((x) & 0x0f000000) >> 24) +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_SET(x) (((x) << 24) & 0x0f000000) + +/* macros for BB_force_clken_cck */ +#define PHY_BB_FORCE_CLKEN_CCK_ADDRESS 0x0000a22c +#define PHY_BB_FORCE_CLKEN_CCK_OFFSET 0x0000a22c +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_MSB 0 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_LSB 0 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_MASK 0x00000001 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_MSB 1 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_LSB 1 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_MASK 0x00000002 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_MSB 2 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_LSB 2 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_MASK 0x00000004 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_MSB 3 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_LSB 3 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_MASK 0x00000008 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_MSB 4 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_LSB 4 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_MASK 0x00000010 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_MSB 5 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_LSB 5 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_MASK 0x00000020 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_SET(x) (((x) << 5) & 0x00000020) + +/* macros for BB_rx_clear_delay */ +#define PHY_BB_RX_CLEAR_DELAY_ADDRESS 0x0000a230 +#define PHY_BB_RX_CLEAR_DELAY_OFFSET 0x0000a230 +#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_MSB 9 +#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_LSB 0 +#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_MASK 0x000003ff +#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_SET(x) (((x) << 0) & 0x000003ff) + +/* macros for BB_powertx_rate3 */ +#define PHY_BB_POWERTX_RATE3_ADDRESS 0x0000a234 +#define PHY_BB_POWERTX_RATE3_OFFSET 0x0000a234 +#define PHY_BB_POWERTX_RATE3_POWERTX_1L_MSB 5 +#define PHY_BB_POWERTX_RATE3_POWERTX_1L_LSB 0 +#define PHY_BB_POWERTX_RATE3_POWERTX_1L_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE3_POWERTX_1L_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE3_POWERTX_1L_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE3_POWERTX_2L_MSB 21 +#define PHY_BB_POWERTX_RATE3_POWERTX_2L_LSB 16 +#define PHY_BB_POWERTX_RATE3_POWERTX_2L_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE3_POWERTX_2L_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE3_POWERTX_2L_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE3_POWERTX_2S_MSB 29 +#define PHY_BB_POWERTX_RATE3_POWERTX_2S_LSB 24 +#define PHY_BB_POWERTX_RATE3_POWERTX_2S_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE3_POWERTX_2S_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE3_POWERTX_2S_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate4 */ +#define PHY_BB_POWERTX_RATE4_ADDRESS 0x0000a238 +#define PHY_BB_POWERTX_RATE4_OFFSET 0x0000a238 +#define PHY_BB_POWERTX_RATE4_POWERTX_55L_MSB 5 +#define PHY_BB_POWERTX_RATE4_POWERTX_55L_LSB 0 +#define PHY_BB_POWERTX_RATE4_POWERTX_55L_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE4_POWERTX_55L_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE4_POWERTX_55L_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE4_POWERTX_55S_MSB 13 +#define PHY_BB_POWERTX_RATE4_POWERTX_55S_LSB 8 +#define PHY_BB_POWERTX_RATE4_POWERTX_55S_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE4_POWERTX_55S_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE4_POWERTX_55S_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE4_POWERTX_11L_MSB 21 +#define PHY_BB_POWERTX_RATE4_POWERTX_11L_LSB 16 +#define PHY_BB_POWERTX_RATE4_POWERTX_11L_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE4_POWERTX_11L_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE4_POWERTX_11L_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE4_POWERTX_11S_MSB 29 +#define PHY_BB_POWERTX_RATE4_POWERTX_11S_LSB 24 +#define PHY_BB_POWERTX_RATE4_POWERTX_11S_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE4_POWERTX_11S_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE4_POWERTX_11S_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_cck_spur_mit */ +#define PHY_BB_CCK_SPUR_MIT_ADDRESS 0x0000a240 +#define PHY_BB_CCK_SPUR_MIT_OFFSET 0x0000a240 +#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_MSB 0 +#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_LSB 0 +#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_MASK 0x00000001 +#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_MSB 8 +#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_LSB 1 +#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_MASK 0x000001fe +#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_GET(x) (((x) & 0x000001fe) >> 1) +#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_SET(x) (((x) << 1) & 0x000001fe) +#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_MSB 28 +#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_LSB 9 +#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_MASK 0x1ffffe00 +#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_GET(x) (((x) & 0x1ffffe00) >> 9) +#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_SET(x) (((x) << 9) & 0x1ffffe00) +#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_MSB 30 +#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_LSB 29 +#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_MASK 0x60000000 +#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_SET(x) (((x) << 29) & 0x60000000) + +/* macros for BB_panic_watchdog_status */ +#define PHY_BB_PANIC_WATCHDOG_STATUS_ADDRESS 0x0000a244 +#define PHY_BB_PANIC_WATCHDOG_STATUS_OFFSET 0x0000a244 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_MSB 2 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_LSB 0 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_MASK 0x00000007 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_SET(x) (((x) << 0) & 0x00000007) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_MSB 3 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_LSB 3 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_MASK 0x00000008 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_MSB 7 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_LSB 4 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_MASK 0x000000f0 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_MSB 11 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_LSB 8 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_MASK 0x00000f00 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_MSB 15 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_LSB 12 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_MASK 0x0000f000 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_MSB 19 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_LSB 16 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_MASK 0x000f0000 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_MSB 23 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_LSB 20 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_MASK 0x00f00000 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_GET(x) (((x) & 0x00f00000) >> 20) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_SET(x) (((x) << 20) & 0x00f00000) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_MSB 27 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_LSB 24 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_MASK 0x0f000000 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_GET(x) (((x) & 0x0f000000) >> 24) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_SET(x) (((x) << 24) & 0x0f000000) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_MSB 31 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_LSB 28 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_MASK 0xf0000000 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_GET(x) (((x) & 0xf0000000) >> 28) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_SET(x) (((x) << 28) & 0xf0000000) + +/* macros for BB_panic_watchdog_ctrl_1 */ +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ADDRESS 0x0000a248 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_OFFSET 0x0000a248 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_MSB 0 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_LSB 0 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_MASK 0x00000001 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_MSB 1 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_LSB 1 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_MASK 0x00000002 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_MSB 15 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_LSB 2 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_MASK 0x0000fffc +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_GET(x) (((x) & 0x0000fffc) >> 2) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_SET(x) (((x) << 2) & 0x0000fffc) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_MSB 31 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_LSB 16 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_MASK 0xffff0000 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_GET(x) (((x) & 0xffff0000) >> 16) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_SET(x) (((x) << 16) & 0xffff0000) + +/* macros for BB_panic_watchdog_ctrl_2 */ +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_ADDRESS 0x0000a24c +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_OFFSET 0x0000a24c +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MSB 0 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_LSB 0 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MASK 0x00000001 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_MSB 1 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_LSB 1 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_MASK 0x00000002 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_MSB 2 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_LSB 2 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_MASK 0x00000004 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_SET(x) (((x) << 2) & 0x00000004) + +/* macros for BB_iqcorr_ctrl_cck */ +#define PHY_BB_IQCORR_CTRL_CCK_ADDRESS 0x0000a250 +#define PHY_BB_IQCORR_CTRL_CCK_OFFSET 0x0000a250 +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_MSB 4 +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_LSB 0 +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_MASK 0x0000001f +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_MSB 10 +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_LSB 5 +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_MASK 0x000007e0 +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_GET(x) (((x) & 0x000007e0) >> 5) +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_SET(x) (((x) << 5) & 0x000007e0) +#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_MSB 11 +#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_LSB 11 +#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_MASK 0x00000800 +#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_SET(x) (((x) << 11) & 0x00000800) +#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_MSB 13 +#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_LSB 12 +#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_MASK 0x00003000 +#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_GET(x) (((x) & 0x00003000) >> 12) +#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_SET(x) (((x) << 12) & 0x00003000) +#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_MSB 15 +#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_LSB 14 +#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_MASK 0x0000c000 +#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_MSB 20 +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_LSB 16 +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_MASK 0x001f0000 +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_MSB 21 +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_LSB 21 +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_MASK 0x00200000 +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_SET(x) (((x) << 21) & 0x00200000) + +/* macros for BB_bluetooth_cntl */ +#define PHY_BB_BLUETOOTH_CNTL_ADDRESS 0x0000a254 +#define PHY_BB_BLUETOOTH_CNTL_OFFSET 0x0000a254 +#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MSB 0 +#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_LSB 0 +#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MASK 0x00000001 +#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MSB 1 +#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_LSB 1 +#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MASK 0x00000002 +#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_SET(x) (((x) << 1) & 0x00000002) + +/* macros for BB_tpc_1 */ +#define PHY_BB_TPC_1_ADDRESS 0x0000a258 +#define PHY_BB_TPC_1_OFFSET 0x0000a258 +#define PHY_BB_TPC_1_FORCE_DAC_GAIN_MSB 0 +#define PHY_BB_TPC_1_FORCE_DAC_GAIN_LSB 0 +#define PHY_BB_TPC_1_FORCE_DAC_GAIN_MASK 0x00000001 +#define PHY_BB_TPC_1_FORCE_DAC_GAIN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TPC_1_FORCE_DAC_GAIN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TPC_1_FORCED_DAC_GAIN_MSB 5 +#define PHY_BB_TPC_1_FORCED_DAC_GAIN_LSB 1 +#define PHY_BB_TPC_1_FORCED_DAC_GAIN_MASK 0x0000003e +#define PHY_BB_TPC_1_FORCED_DAC_GAIN_GET(x) (((x) & 0x0000003e) >> 1) +#define PHY_BB_TPC_1_FORCED_DAC_GAIN_SET(x) (((x) << 1) & 0x0000003e) +#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_MSB 13 +#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_LSB 6 +#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_MASK 0x00003fc0 +#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_GET(x) (((x) & 0x00003fc0) >> 6) +#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_SET(x) (((x) << 6) & 0x00003fc0) +#define PHY_BB_TPC_1_NUM_PD_GAIN_MSB 15 +#define PHY_BB_TPC_1_NUM_PD_GAIN_LSB 14 +#define PHY_BB_TPC_1_NUM_PD_GAIN_MASK 0x0000c000 +#define PHY_BB_TPC_1_NUM_PD_GAIN_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_BB_TPC_1_NUM_PD_GAIN_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_BB_TPC_1_PD_GAIN_SETTING1_MSB 17 +#define PHY_BB_TPC_1_PD_GAIN_SETTING1_LSB 16 +#define PHY_BB_TPC_1_PD_GAIN_SETTING1_MASK 0x00030000 +#define PHY_BB_TPC_1_PD_GAIN_SETTING1_GET(x) (((x) & 0x00030000) >> 16) +#define PHY_BB_TPC_1_PD_GAIN_SETTING1_SET(x) (((x) << 16) & 0x00030000) +#define PHY_BB_TPC_1_PD_GAIN_SETTING2_MSB 19 +#define PHY_BB_TPC_1_PD_GAIN_SETTING2_LSB 18 +#define PHY_BB_TPC_1_PD_GAIN_SETTING2_MASK 0x000c0000 +#define PHY_BB_TPC_1_PD_GAIN_SETTING2_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_BB_TPC_1_PD_GAIN_SETTING2_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_BB_TPC_1_PD_GAIN_SETTING3_MSB 21 +#define PHY_BB_TPC_1_PD_GAIN_SETTING3_LSB 20 +#define PHY_BB_TPC_1_PD_GAIN_SETTING3_MASK 0x00300000 +#define PHY_BB_TPC_1_PD_GAIN_SETTING3_GET(x) (((x) & 0x00300000) >> 20) +#define PHY_BB_TPC_1_PD_GAIN_SETTING3_SET(x) (((x) << 20) & 0x00300000) +#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_MSB 22 +#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_LSB 22 +#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_MASK 0x00400000 +#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_MSB 28 +#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_LSB 23 +#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_MASK 0x1f800000 +#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_GET(x) (((x) & 0x1f800000) >> 23) +#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_SET(x) (((x) << 23) & 0x1f800000) +#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_MSB 29 +#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_LSB 29 +#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_MASK 0x20000000 +#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_MSB 31 +#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_LSB 30 +#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_MASK 0xc0000000 +#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for BB_tpc_2 */ +#define PHY_BB_TPC_2_ADDRESS 0x0000a25c +#define PHY_BB_TPC_2_OFFSET 0x0000a25c +#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MSB 7 +#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_LSB 0 +#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MASK 0x000000ff +#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MSB 15 +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_LSB 8 +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MASK 0x0000ff00 +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MSB 23 +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_LSB 16 +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MASK 0x00ff0000 +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_SET(x) (((x) << 16) & 0x00ff0000) + +/* macros for BB_tpc_3 */ +#define PHY_BB_TPC_3_ADDRESS 0x0000a260 +#define PHY_BB_TPC_3_OFFSET 0x0000a260 +#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MSB 7 +#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_LSB 0 +#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MASK 0x000000ff +#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MSB 15 +#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_LSB 8 +#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MASK 0x0000ff00 +#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_MSB 18 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_LSB 16 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_MASK 0x00070000 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_SET(x) (((x) << 16) & 0x00070000) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_MSB 21 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_LSB 19 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_MASK 0x00380000 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_SET(x) (((x) << 19) & 0x00380000) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MSB 24 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_LSB 22 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MASK 0x01c00000 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_GET(x) (((x) & 0x01c00000) >> 22) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_SET(x) (((x) << 22) & 0x01c00000) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MSB 27 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_LSB 25 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MASK 0x0e000000 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_GET(x) (((x) & 0x0e000000) >> 25) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_SET(x) (((x) << 25) & 0x0e000000) +#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MSB 31 +#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_LSB 31 +#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MASK 0x80000000 +#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_tpc_4_b0 */ +#define PHY_BB_TPC_4_B0_ADDRESS 0x0000a264 +#define PHY_BB_TPC_4_B0_OFFSET 0x0000a264 +#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_MSB 0 +#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_LSB 0 +#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_MASK 0x00000001 +#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_MSB 8 +#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_LSB 1 +#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_MASK 0x000001fe +#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_GET(x) (((x) & 0x000001fe) >> 1) +#define PHY_BB_TPC_4_B0_DAC_GAIN_0_MSB 13 +#define PHY_BB_TPC_4_B0_DAC_GAIN_0_LSB 9 +#define PHY_BB_TPC_4_B0_DAC_GAIN_0_MASK 0x00003e00 +#define PHY_BB_TPC_4_B0_DAC_GAIN_0_GET(x) (((x) & 0x00003e00) >> 9) +#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_MSB 19 +#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_LSB 14 +#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_MASK 0x000fc000 +#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_BB_TPC_4_B0_RATE_SENT_0_MSB 24 +#define PHY_BB_TPC_4_B0_RATE_SENT_0_LSB 20 +#define PHY_BB_TPC_4_B0_RATE_SENT_0_MASK 0x01f00000 +#define PHY_BB_TPC_4_B0_RATE_SENT_0_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_MSB 30 +#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_LSB 25 +#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_MASK 0x7e000000 +#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_GET(x) (((x) & 0x7e000000) >> 25) +#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_SET(x) (((x) << 25) & 0x7e000000) + +/* macros for BB_analog_swap */ +#define PHY_BB_ANALOG_SWAP_ADDRESS 0x0000a268 +#define PHY_BB_ANALOG_SWAP_OFFSET 0x0000a268 +#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MSB 2 +#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_LSB 0 +#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MASK 0x00000007 +#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_SET(x) (((x) << 0) & 0x00000007) +#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MSB 5 +#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_LSB 3 +#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MASK 0x00000038 +#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_SET(x) (((x) << 3) & 0x00000038) +#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MSB 6 +#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_LSB 6 +#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MASK 0x00000040 +#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_SET(x) (((x) << 6) & 0x00000040) +#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MSB 7 +#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_LSB 7 +#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MASK 0x00000080 +#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_SET(x) (((x) << 7) & 0x00000080) +#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MSB 8 +#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_LSB 8 +#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MASK 0x00000100 +#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_SET(x) (((x) << 8) & 0x00000100) + +/* macros for BB_tpc_5_b0 */ +#define PHY_BB_TPC_5_B0_ADDRESS 0x0000a26c +#define PHY_BB_TPC_5_B0_OFFSET 0x0000a26c +#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_MSB 3 +#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_LSB 0 +#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_MASK 0x0000000f +#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_MSB 9 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_LSB 4 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_MASK 0x000003f0 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_GET(x) (((x) & 0x000003f0) >> 4) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_SET(x) (((x) << 4) & 0x000003f0) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_MSB 15 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_LSB 10 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_MASK 0x0000fc00 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_GET(x) (((x) & 0x0000fc00) >> 10) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_SET(x) (((x) << 10) & 0x0000fc00) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_MSB 21 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_LSB 16 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_MASK 0x003f0000 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_MSB 27 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_LSB 22 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_MASK 0x0fc00000 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_GET(x) (((x) & 0x0fc00000) >> 22) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_SET(x) (((x) << 22) & 0x0fc00000) + +/* macros for BB_tpc_6_b0 */ +#define PHY_BB_TPC_6_B0_ADDRESS 0x0000a270 +#define PHY_BB_TPC_6_B0_OFFSET 0x0000a270 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_MSB 5 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_LSB 0 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_MASK 0x0000003f +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_MSB 11 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_LSB 6 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_MASK 0x00000fc0 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_MSB 17 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_LSB 12 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_MASK 0x0003f000 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_MSB 23 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_LSB 18 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_MASK 0x00fc0000 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_SET(x) (((x) << 18) & 0x00fc0000) +#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_MSB 25 +#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_LSB 24 +#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_MASK 0x03000000 +#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_SET(x) (((x) << 24) & 0x03000000) +#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_MSB 28 +#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_LSB 26 +#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_MASK 0x1c000000 +#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_SET(x) (((x) << 26) & 0x1c000000) + +/* macros for BB_tpc_7 */ +#define PHY_BB_TPC_7_ADDRESS 0x0000a274 +#define PHY_BB_TPC_7_OFFSET 0x0000a274 +#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MSB 5 +#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_LSB 0 +#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MASK 0x0000003f +#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_MSB 11 +#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_LSB 6 +#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_MASK 0x00000fc0 +#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_MSB 12 +#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_LSB 12 +#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_MASK 0x00001000 +#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MSB 13 +#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_LSB 13 +#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MASK 0x00002000 +#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MSB 14 +#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_LSB 14 +#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MASK 0x00004000 +#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MSB 15 +#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_LSB 15 +#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MASK 0x00008000 +#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_SET(x) (((x) << 15) & 0x00008000) + +/* macros for BB_tpc_8 */ +#define PHY_BB_TPC_8_ADDRESS 0x0000a278 +#define PHY_BB_TPC_8_OFFSET 0x0000a278 +#define PHY_BB_TPC_8_DESIRED_SCALE_0_MSB 4 +#define PHY_BB_TPC_8_DESIRED_SCALE_0_LSB 0 +#define PHY_BB_TPC_8_DESIRED_SCALE_0_MASK 0x0000001f +#define PHY_BB_TPC_8_DESIRED_SCALE_0_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_8_DESIRED_SCALE_0_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_8_DESIRED_SCALE_1_MSB 9 +#define PHY_BB_TPC_8_DESIRED_SCALE_1_LSB 5 +#define PHY_BB_TPC_8_DESIRED_SCALE_1_MASK 0x000003e0 +#define PHY_BB_TPC_8_DESIRED_SCALE_1_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_8_DESIRED_SCALE_1_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_8_DESIRED_SCALE_2_MSB 14 +#define PHY_BB_TPC_8_DESIRED_SCALE_2_LSB 10 +#define PHY_BB_TPC_8_DESIRED_SCALE_2_MASK 0x00007c00 +#define PHY_BB_TPC_8_DESIRED_SCALE_2_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_TPC_8_DESIRED_SCALE_2_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_TPC_8_DESIRED_SCALE_3_MSB 19 +#define PHY_BB_TPC_8_DESIRED_SCALE_3_LSB 15 +#define PHY_BB_TPC_8_DESIRED_SCALE_3_MASK 0x000f8000 +#define PHY_BB_TPC_8_DESIRED_SCALE_3_GET(x) (((x) & 0x000f8000) >> 15) +#define PHY_BB_TPC_8_DESIRED_SCALE_3_SET(x) (((x) << 15) & 0x000f8000) +#define PHY_BB_TPC_8_DESIRED_SCALE_4_MSB 24 +#define PHY_BB_TPC_8_DESIRED_SCALE_4_LSB 20 +#define PHY_BB_TPC_8_DESIRED_SCALE_4_MASK 0x01f00000 +#define PHY_BB_TPC_8_DESIRED_SCALE_4_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_TPC_8_DESIRED_SCALE_4_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_TPC_8_DESIRED_SCALE_5_MSB 29 +#define PHY_BB_TPC_8_DESIRED_SCALE_5_LSB 25 +#define PHY_BB_TPC_8_DESIRED_SCALE_5_MASK 0x3e000000 +#define PHY_BB_TPC_8_DESIRED_SCALE_5_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_TPC_8_DESIRED_SCALE_5_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_tpc_9 */ +#define PHY_BB_TPC_9_ADDRESS 0x0000a27c +#define PHY_BB_TPC_9_OFFSET 0x0000a27c +#define PHY_BB_TPC_9_DESIRED_SCALE_6_MSB 4 +#define PHY_BB_TPC_9_DESIRED_SCALE_6_LSB 0 +#define PHY_BB_TPC_9_DESIRED_SCALE_6_MASK 0x0000001f +#define PHY_BB_TPC_9_DESIRED_SCALE_6_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_9_DESIRED_SCALE_6_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_9_DESIRED_SCALE_7_MSB 9 +#define PHY_BB_TPC_9_DESIRED_SCALE_7_LSB 5 +#define PHY_BB_TPC_9_DESIRED_SCALE_7_MASK 0x000003e0 +#define PHY_BB_TPC_9_DESIRED_SCALE_7_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_9_DESIRED_SCALE_7_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_MSB 14 +#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_LSB 10 +#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_MASK 0x00007c00 +#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_MSB 20 +#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_LSB 20 +#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_MASK 0x00100000 +#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_SET(x) (((x) << 20) & 0x00100000) +#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_MSB 26 +#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_LSB 21 +#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_MASK 0x07e00000 +#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_GET(x) (((x) & 0x07e00000) >> 21) +#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_SET(x) (((x) << 21) & 0x07e00000) +#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MSB 30 +#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_LSB 27 +#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MASK 0x78000000 +#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_SET(x) (((x) << 27) & 0x78000000) +#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_MSB 31 +#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_LSB 31 +#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_MASK 0x80000000 +#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_pdadc_tab_b0 */ +#define PHY_BB_PDADC_TAB_B0_ADDRESS 0x0000a280 +#define PHY_BB_PDADC_TAB_B0_OFFSET 0x0000a280 +#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_MSB 31 +#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_LSB 0 +#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_MASK 0xffffffff +#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_tab_b0 */ +#define PHY_BB_CL_TAB_B0_ADDRESS 0x0000a300 +#define PHY_BB_CL_TAB_B0_OFFSET 0x0000a300 +#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MSB 4 +#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_LSB 0 +#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MASK 0x0000001f +#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MSB 15 +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_LSB 5 +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MASK 0x0000ffe0 +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_GET(x) (((x) & 0x0000ffe0) >> 5) +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_SET(x) (((x) << 5) & 0x0000ffe0) +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MSB 26 +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_LSB 16 +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MASK 0x07ff0000 +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_GET(x) (((x) & 0x07ff0000) >> 16) +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_SET(x) (((x) << 16) & 0x07ff0000) +#define PHY_BB_CL_TAB_B0_BB_GAIN_MSB 30 +#define PHY_BB_CL_TAB_B0_BB_GAIN_LSB 27 +#define PHY_BB_CL_TAB_B0_BB_GAIN_MASK 0x78000000 +#define PHY_BB_CL_TAB_B0_BB_GAIN_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_BB_CL_TAB_B0_BB_GAIN_SET(x) (((x) << 27) & 0x78000000) + +/* macros for BB_cl_map_0_b0 */ +#define PHY_BB_CL_MAP_0_B0_ADDRESS 0x0000a340 +#define PHY_BB_CL_MAP_0_B0_OFFSET 0x0000a340 +#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_MSB 31 +#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_LSB 0 +#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_MASK 0xffffffff +#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_map_1_b0 */ +#define PHY_BB_CL_MAP_1_B0_ADDRESS 0x0000a344 +#define PHY_BB_CL_MAP_1_B0_OFFSET 0x0000a344 +#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_MSB 31 +#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_LSB 0 +#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_MASK 0xffffffff +#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_map_2_b0 */ +#define PHY_BB_CL_MAP_2_B0_ADDRESS 0x0000a348 +#define PHY_BB_CL_MAP_2_B0_OFFSET 0x0000a348 +#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_MSB 31 +#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_LSB 0 +#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_MASK 0xffffffff +#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_map_3_b0 */ +#define PHY_BB_CL_MAP_3_B0_ADDRESS 0x0000a34c +#define PHY_BB_CL_MAP_3_B0_OFFSET 0x0000a34c +#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_MSB 31 +#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_LSB 0 +#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_MASK 0xffffffff +#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_cal_ctrl */ +#define PHY_BB_CL_CAL_CTRL_ADDRESS 0x0000a358 +#define PHY_BB_CL_CAL_CTRL_OFFSET 0x0000a358 +#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MSB 0 +#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_LSB 0 +#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MASK 0x00000001 +#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MSB 1 +#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_LSB 1 +#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MASK 0x00000002 +#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MSB 3 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_LSB 2 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MASK 0x0000000c +#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MSB 7 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_LSB 4 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MASK 0x000000f0 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MSB 15 +#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_LSB 8 +#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MASK 0x0000ff00 +#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MSB 21 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_LSB 16 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MASK 0x003f0000 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MSB 29 +#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_LSB 22 +#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MASK 0x3fc00000 +#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_GET(x) (((x) & 0x3fc00000) >> 22) +#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_SET(x) (((x) << 22) & 0x3fc00000) +#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MSB 30 +#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_LSB 30 +#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MASK 0x40000000 +#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MSB 31 +#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_LSB 31 +#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MASK 0x80000000 +#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_cl_map_pal_0_b0 */ +#define PHY_BB_CL_MAP_PAL_0_B0_ADDRESS 0x0000a35c +#define PHY_BB_CL_MAP_PAL_0_B0_OFFSET 0x0000a35c +#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_MSB 31 +#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_LSB 0 +#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_MASK 0xffffffff +#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_map_pal_1_b0 */ +#define PHY_BB_CL_MAP_PAL_1_B0_ADDRESS 0x0000a360 +#define PHY_BB_CL_MAP_PAL_1_B0_OFFSET 0x0000a360 +#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_MSB 31 +#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_LSB 0 +#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_MASK 0xffffffff +#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_map_pal_2_b0 */ +#define PHY_BB_CL_MAP_PAL_2_B0_ADDRESS 0x0000a364 +#define PHY_BB_CL_MAP_PAL_2_B0_OFFSET 0x0000a364 +#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_MSB 31 +#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_LSB 0 +#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_MASK 0xffffffff +#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_map_pal_3_b0 */ +#define PHY_BB_CL_MAP_PAL_3_B0_ADDRESS 0x0000a368 +#define PHY_BB_CL_MAP_PAL_3_B0_OFFSET 0x0000a368 +#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_MSB 31 +#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_LSB 0 +#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_MASK 0xffffffff +#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_rifs */ +#define PHY_BB_RIFS_ADDRESS 0x0000a388 +#define PHY_BB_RIFS_OFFSET 0x0000a388 +#define PHY_BB_RIFS_DISABLE_FCC_FIX_MSB 25 +#define PHY_BB_RIFS_DISABLE_FCC_FIX_LSB 25 +#define PHY_BB_RIFS_DISABLE_FCC_FIX_MASK 0x02000000 +#define PHY_BB_RIFS_DISABLE_FCC_FIX_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_BB_RIFS_DISABLE_FCC_FIX_SET(x) (((x) << 25) & 0x02000000) +#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MSB 26 +#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_LSB 26 +#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MASK 0x04000000 +#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_SET(x) (((x) << 26) & 0x04000000) +#define PHY_BB_RIFS_DISABLE_FCC_FIX2_MSB 27 +#define PHY_BB_RIFS_DISABLE_FCC_FIX2_LSB 27 +#define PHY_BB_RIFS_DISABLE_FCC_FIX2_MASK 0x08000000 +#define PHY_BB_RIFS_DISABLE_FCC_FIX2_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_RIFS_DISABLE_FCC_FIX2_SET(x) (((x) << 27) & 0x08000000) +#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_MSB 28 +#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_LSB 28 +#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_MASK 0x10000000 +#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_MSB 29 +#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_LSB 29 +#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_MASK 0x20000000 +#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_MSB 30 +#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_LSB 30 +#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_MASK 0x40000000 +#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_SET(x) (((x) << 30) & 0x40000000) + +/* macros for BB_powertx_rate5 */ +#define PHY_BB_POWERTX_RATE5_ADDRESS 0x0000a38c +#define PHY_BB_POWERTX_RATE5_OFFSET 0x0000a38c +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_MSB 5 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_LSB 0 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_MSB 13 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_LSB 8 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_MSB 21 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_LSB 16 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_MSB 29 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_LSB 24 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate6 */ +#define PHY_BB_POWERTX_RATE6_ADDRESS 0x0000a390 +#define PHY_BB_POWERTX_RATE6_OFFSET 0x0000a390 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_MSB 5 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_LSB 0 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_MSB 13 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_LSB 8 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_MSB 21 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_LSB 16 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_MSB 29 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_LSB 24 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_tpc_10 */ +#define PHY_BB_TPC_10_ADDRESS 0x0000a394 +#define PHY_BB_TPC_10_OFFSET 0x0000a394 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_MSB 4 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_LSB 0 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_MASK 0x0000001f +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_MSB 9 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_LSB 5 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_MASK 0x000003e0 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_MSB 14 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_LSB 10 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_MASK 0x00007c00 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_MSB 19 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_LSB 15 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_MASK 0x000f8000 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_GET(x) (((x) & 0x000f8000) >> 15) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_SET(x) (((x) << 15) & 0x000f8000) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_MSB 24 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_LSB 20 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_MASK 0x01f00000 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_MSB 29 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_LSB 25 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_MASK 0x3e000000 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_tpc_11_b0 */ +#define PHY_BB_TPC_11_B0_ADDRESS 0x0000a398 +#define PHY_BB_TPC_11_B0_OFFSET 0x0000a398 +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_MSB 4 +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_LSB 0 +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_MASK 0x0000001f +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_MSB 9 +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_LSB 5 +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_MASK 0x000003e0 +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MSB 23 +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB 16 +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MASK 0x00ff0000 +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_MSB 31 +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_LSB 24 +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_MASK 0xff000000 +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_cal_chain_mask */ +#define PHY_BB_CAL_CHAIN_MASK_ADDRESS 0x0000a39c +#define PHY_BB_CAL_CHAIN_MASK_OFFSET 0x0000a39c +#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MSB 2 +#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_LSB 0 +#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MASK 0x00000007 +#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_SET(x) (((x) << 0) & 0x00000007) + +/* macros for BB_powertx_sub */ +#define PHY_BB_POWERTX_SUB_ADDRESS 0x0000a3bc +#define PHY_BB_POWERTX_SUB_OFFSET 0x0000a3bc +#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_MSB 5 +#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_LSB 0 +#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_MASK 0x0000003f +#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_SET(x) (((x) << 0) & 0x0000003f) + +/* macros for BB_powertx_rate7 */ +#define PHY_BB_POWERTX_RATE7_ADDRESS 0x0000a3c0 +#define PHY_BB_POWERTX_RATE7_OFFSET 0x0000a3c0 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_MSB 5 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_LSB 0 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_MSB 13 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_LSB 8 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_MSB 21 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_LSB 16 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_MSB 29 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_LSB 24 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate8 */ +#define PHY_BB_POWERTX_RATE8_ADDRESS 0x0000a3c4 +#define PHY_BB_POWERTX_RATE8_OFFSET 0x0000a3c4 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_MSB 5 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_LSB 0 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_MSB 13 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_LSB 8 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_MSB 21 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_LSB 16 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_MSB 29 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_LSB 24 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate9 */ +#define PHY_BB_POWERTX_RATE9_ADDRESS 0x0000a3c8 +#define PHY_BB_POWERTX_RATE9_OFFSET 0x0000a3c8 +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_MSB 5 +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_LSB 0 +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_MSB 13 +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_LSB 8 +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_MSB 21 +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_LSB 16 +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_MSB 29 +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_LSB 24 +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate10 */ +#define PHY_BB_POWERTX_RATE10_ADDRESS 0x0000a3cc +#define PHY_BB_POWERTX_RATE10_OFFSET 0x0000a3cc +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_MSB 5 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_LSB 0 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_MSB 13 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_LSB 8 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_MSB 21 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_LSB 16 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_MSB 29 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_LSB 24 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate11 */ +#define PHY_BB_POWERTX_RATE11_ADDRESS 0x0000a3d0 +#define PHY_BB_POWERTX_RATE11_OFFSET 0x0000a3d0 +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_MSB 5 +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_LSB 0 +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_MSB 13 +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_LSB 8 +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_MSB 21 +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_LSB 16 +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_MSB 29 +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_LSB 24 +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate12 */ +#define PHY_BB_POWERTX_RATE12_ADDRESS 0x0000a3d4 +#define PHY_BB_POWERTX_RATE12_OFFSET 0x0000a3d4 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_MSB 5 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_LSB 0 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_MSB 13 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_LSB 8 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_MSB 21 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_LSB 16 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_MSB 29 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_LSB 24 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_force_analog */ +#define PHY_BB_FORCE_ANALOG_ADDRESS 0x0000a3d8 +#define PHY_BB_FORCE_ANALOG_OFFSET 0x0000a3d8 +#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_MSB 0 +#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_LSB 0 +#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_MASK 0x00000001 +#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_MSB 3 +#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_LSB 1 +#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_MASK 0x0000000e +#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_MSB 4 +#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_LSB 4 +#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_MASK 0x00000010 +#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_MSB 7 +#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_LSB 5 +#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_MASK 0x000000e0 +#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_SET(x) (((x) << 5) & 0x000000e0) + +/* macros for BB_tpc_12 */ +#define PHY_BB_TPC_12_ADDRESS 0x0000a3dc +#define PHY_BB_TPC_12_OFFSET 0x0000a3dc +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_MSB 4 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_LSB 0 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_MASK 0x0000001f +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_MSB 9 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_LSB 5 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_MASK 0x000003e0 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_MSB 14 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_LSB 10 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_MASK 0x00007c00 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_MSB 19 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_LSB 15 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_MASK 0x000f8000 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_GET(x) (((x) & 0x000f8000) >> 15) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_SET(x) (((x) << 15) & 0x000f8000) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_MSB 24 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_LSB 20 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_MASK 0x01f00000 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_MSB 29 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_LSB 25 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_MASK 0x3e000000 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_tpc_13 */ +#define PHY_BB_TPC_13_ADDRESS 0x0000a3e0 +#define PHY_BB_TPC_13_OFFSET 0x0000a3e0 +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_MSB 4 +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_LSB 0 +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_MASK 0x0000001f +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_MSB 9 +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_LSB 5 +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_MASK 0x000003e0 +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_SET(x) (((x) << 5) & 0x000003e0) + +/* macros for BB_tpc_14 */ +#define PHY_BB_TPC_14_ADDRESS 0x0000a3e4 +#define PHY_BB_TPC_14_OFFSET 0x0000a3e4 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_MSB 4 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_LSB 0 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_MASK 0x0000001f +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_MSB 9 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_LSB 5 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_MASK 0x000003e0 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_MSB 14 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_LSB 10 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_MASK 0x00007c00 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_MSB 19 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_LSB 15 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_MASK 0x000f8000 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_GET(x) (((x) & 0x000f8000) >> 15) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_SET(x) (((x) << 15) & 0x000f8000) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_MSB 24 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_LSB 20 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_MASK 0x01f00000 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_MSB 29 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_LSB 25 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_MASK 0x3e000000 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_tpc_15 */ +#define PHY_BB_TPC_15_ADDRESS 0x0000a3e8 +#define PHY_BB_TPC_15_OFFSET 0x0000a3e8 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_MSB 4 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_LSB 0 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_MASK 0x0000001f +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_MSB 9 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_LSB 5 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_MASK 0x000003e0 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_MSB 14 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_LSB 10 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_MASK 0x00007c00 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_MSB 19 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_LSB 15 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_MASK 0x000f8000 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_GET(x) (((x) & 0x000f8000) >> 15) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_SET(x) (((x) << 15) & 0x000f8000) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_MSB 24 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_LSB 20 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_MASK 0x01f00000 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_MSB 29 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_LSB 25 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_MASK 0x3e000000 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_tpc_16 */ +#define PHY_BB_TPC_16_ADDRESS 0x0000a3ec +#define PHY_BB_TPC_16_OFFSET 0x0000a3ec +#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_MSB 13 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_LSB 8 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_MASK 0x00003f00 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_MSB 21 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_LSB 16 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_MASK 0x003f0000 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_MSB 29 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_LSB 24 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_MASK 0x3f000000 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_tpc_17 */ +#define PHY_BB_TPC_17_ADDRESS 0x0000a3f0 +#define PHY_BB_TPC_17_OFFSET 0x0000a3f0 +#define PHY_BB_TPC_17_ENABLE_PAL_MSB 0 +#define PHY_BB_TPC_17_ENABLE_PAL_LSB 0 +#define PHY_BB_TPC_17_ENABLE_PAL_MASK 0x00000001 +#define PHY_BB_TPC_17_ENABLE_PAL_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TPC_17_ENABLE_PAL_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TPC_17_ENABLE_PAL_CCK_MSB 1 +#define PHY_BB_TPC_17_ENABLE_PAL_CCK_LSB 1 +#define PHY_BB_TPC_17_ENABLE_PAL_CCK_MASK 0x00000002 +#define PHY_BB_TPC_17_ENABLE_PAL_CCK_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_TPC_17_ENABLE_PAL_CCK_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_MSB 2 +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_LSB 2 +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_MASK 0x00000004 +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_MSB 3 +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_LSB 3 +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_MASK 0x00000008 +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_MSB 9 +#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_LSB 4 +#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_MASK 0x000003f0 +#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_GET(x) (((x) & 0x000003f0) >> 4) +#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_SET(x) (((x) << 4) & 0x000003f0) +#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_MSB 10 +#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_LSB 10 +#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_MASK 0x00000400 +#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_MSB 16 +#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_LSB 11 +#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_MASK 0x0001f800 +#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_GET(x) (((x) & 0x0001f800) >> 11) +#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_SET(x) (((x) << 11) & 0x0001f800) + +/* macros for BB_tpc_18 */ +#define PHY_BB_TPC_18_ADDRESS 0x0000a3f4 +#define PHY_BB_TPC_18_OFFSET 0x0000a3f4 +#define PHY_BB_TPC_18_THERM_CAL_VALUE_MSB 7 +#define PHY_BB_TPC_18_THERM_CAL_VALUE_LSB 0 +#define PHY_BB_TPC_18_THERM_CAL_VALUE_MASK 0x000000ff +#define PHY_BB_TPC_18_THERM_CAL_VALUE_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TPC_18_THERM_CAL_VALUE_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TPC_18_VOLT_CAL_VALUE_MSB 15 +#define PHY_BB_TPC_18_VOLT_CAL_VALUE_LSB 8 +#define PHY_BB_TPC_18_VOLT_CAL_VALUE_MASK 0x0000ff00 +#define PHY_BB_TPC_18_VOLT_CAL_VALUE_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TPC_18_VOLT_CAL_VALUE_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TPC_18_USE_LEGACY_TPC_MSB 16 +#define PHY_BB_TPC_18_USE_LEGACY_TPC_LSB 16 +#define PHY_BB_TPC_18_USE_LEGACY_TPC_MASK 0x00010000 +#define PHY_BB_TPC_18_USE_LEGACY_TPC_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_TPC_18_USE_LEGACY_TPC_SET(x) (((x) << 16) & 0x00010000) + +/* macros for BB_tpc_19 */ +#define PHY_BB_TPC_19_ADDRESS 0x0000a3f8 +#define PHY_BB_TPC_19_OFFSET 0x0000a3f8 +#define PHY_BB_TPC_19_ALPHA_THERM_MSB 7 +#define PHY_BB_TPC_19_ALPHA_THERM_LSB 0 +#define PHY_BB_TPC_19_ALPHA_THERM_MASK 0x000000ff +#define PHY_BB_TPC_19_ALPHA_THERM_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TPC_19_ALPHA_THERM_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_MSB 15 +#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_LSB 8 +#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_MASK 0x0000ff00 +#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TPC_19_ALPHA_VOLT_MSB 20 +#define PHY_BB_TPC_19_ALPHA_VOLT_LSB 16 +#define PHY_BB_TPC_19_ALPHA_VOLT_MASK 0x001f0000 +#define PHY_BB_TPC_19_ALPHA_VOLT_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_TPC_19_ALPHA_VOLT_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_MSB 25 +#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_LSB 21 +#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_MASK 0x03e00000 +#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_GET(x) (((x) & 0x03e00000) >> 21) +#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_SET(x) (((x) << 21) & 0x03e00000) + +/* macros for BB_tpc_20 */ +#define PHY_BB_TPC_20_ADDRESS 0x0000a3fc +#define PHY_BB_TPC_20_OFFSET 0x0000a3fc +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_MSB 0 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_LSB 0 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_MASK 0x00000001 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_MSB 1 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_LSB 1 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_MASK 0x00000002 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_MSB 2 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_LSB 2 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_MASK 0x00000004 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_MSB 3 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_LSB 3 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_MASK 0x00000008 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_MSB 4 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_LSB 4 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_MASK 0x00000010 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_MSB 5 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_LSB 5 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_MASK 0x00000020 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_SET(x) (((x) << 5) & 0x00000020) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_MSB 6 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_LSB 6 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_MASK 0x00000040 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_SET(x) (((x) << 6) & 0x00000040) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_MSB 7 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_LSB 7 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_MASK 0x00000080 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_SET(x) (((x) << 7) & 0x00000080) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_MSB 8 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_LSB 8 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_MASK 0x00000100 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_MSB 9 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_LSB 9 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_MASK 0x00000200 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_MSB 10 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_LSB 10 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_MASK 0x00000400 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_MSB 11 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_LSB 11 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_MASK 0x00000800 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_SET(x) (((x) << 11) & 0x00000800) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_MSB 12 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_LSB 12 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_MASK 0x00001000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_MSB 13 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_LSB 13 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_MASK 0x00002000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_MSB 14 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_LSB 14 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_MASK 0x00004000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_MSB 15 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_LSB 15 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_MASK 0x00008000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_MSB 16 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_LSB 16 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_MASK 0x00010000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_MSB 17 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_LSB 17 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_MASK 0x00020000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_MSB 18 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_LSB 18 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_MASK 0x00040000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_SET(x) (((x) << 18) & 0x00040000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_MSB 19 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_LSB 19 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_MASK 0x00080000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_SET(x) (((x) << 19) & 0x00080000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_MSB 20 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_LSB 20 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_MASK 0x00100000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_SET(x) (((x) << 20) & 0x00100000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_MSB 21 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_LSB 21 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_MASK 0x00200000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_SET(x) (((x) << 21) & 0x00200000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_MSB 22 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_LSB 22 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_MASK 0x00400000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_MSB 23 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_LSB 23 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_MASK 0x00800000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_SET(x) (((x) << 23) & 0x00800000) + +/* macros for BB_tx_gain_tab_1 */ +#define PHY_BB_TX_GAIN_TAB_1_ADDRESS 0x0000a400 +#define PHY_BB_TX_GAIN_TAB_1_OFFSET 0x0000a400 +#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_MSB 31 +#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_LSB 0 +#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_2 */ +#define PHY_BB_TX_GAIN_TAB_2_ADDRESS 0x0000a404 +#define PHY_BB_TX_GAIN_TAB_2_OFFSET 0x0000a404 +#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_MSB 31 +#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_LSB 0 +#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_3 */ +#define PHY_BB_TX_GAIN_TAB_3_ADDRESS 0x0000a408 +#define PHY_BB_TX_GAIN_TAB_3_OFFSET 0x0000a408 +#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_MSB 31 +#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_LSB 0 +#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_4 */ +#define PHY_BB_TX_GAIN_TAB_4_ADDRESS 0x0000a40c +#define PHY_BB_TX_GAIN_TAB_4_OFFSET 0x0000a40c +#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_MSB 31 +#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_LSB 0 +#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_5 */ +#define PHY_BB_TX_GAIN_TAB_5_ADDRESS 0x0000a410 +#define PHY_BB_TX_GAIN_TAB_5_OFFSET 0x0000a410 +#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_MSB 31 +#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_LSB 0 +#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_6 */ +#define PHY_BB_TX_GAIN_TAB_6_ADDRESS 0x0000a414 +#define PHY_BB_TX_GAIN_TAB_6_OFFSET 0x0000a414 +#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_MSB 31 +#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_LSB 0 +#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_7 */ +#define PHY_BB_TX_GAIN_TAB_7_ADDRESS 0x0000a418 +#define PHY_BB_TX_GAIN_TAB_7_OFFSET 0x0000a418 +#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_MSB 31 +#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_LSB 0 +#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_8 */ +#define PHY_BB_TX_GAIN_TAB_8_ADDRESS 0x0000a41c +#define PHY_BB_TX_GAIN_TAB_8_OFFSET 0x0000a41c +#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_MSB 31 +#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_LSB 0 +#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_9 */ +#define PHY_BB_TX_GAIN_TAB_9_ADDRESS 0x0000a420 +#define PHY_BB_TX_GAIN_TAB_9_OFFSET 0x0000a420 +#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_MSB 31 +#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_LSB 0 +#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_10 */ +#define PHY_BB_TX_GAIN_TAB_10_ADDRESS 0x0000a424 +#define PHY_BB_TX_GAIN_TAB_10_OFFSET 0x0000a424 +#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_MSB 31 +#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_LSB 0 +#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_11 */ +#define PHY_BB_TX_GAIN_TAB_11_ADDRESS 0x0000a428 +#define PHY_BB_TX_GAIN_TAB_11_OFFSET 0x0000a428 +#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_MSB 31 +#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_LSB 0 +#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_12 */ +#define PHY_BB_TX_GAIN_TAB_12_ADDRESS 0x0000a42c +#define PHY_BB_TX_GAIN_TAB_12_OFFSET 0x0000a42c +#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_MSB 31 +#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_LSB 0 +#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_13 */ +#define PHY_BB_TX_GAIN_TAB_13_ADDRESS 0x0000a430 +#define PHY_BB_TX_GAIN_TAB_13_OFFSET 0x0000a430 +#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_MSB 31 +#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_LSB 0 +#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_14 */ +#define PHY_BB_TX_GAIN_TAB_14_ADDRESS 0x0000a434 +#define PHY_BB_TX_GAIN_TAB_14_OFFSET 0x0000a434 +#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_MSB 31 +#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_LSB 0 +#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_15 */ +#define PHY_BB_TX_GAIN_TAB_15_ADDRESS 0x0000a438 +#define PHY_BB_TX_GAIN_TAB_15_OFFSET 0x0000a438 +#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_MSB 31 +#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_LSB 0 +#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_16 */ +#define PHY_BB_TX_GAIN_TAB_16_ADDRESS 0x0000a43c +#define PHY_BB_TX_GAIN_TAB_16_OFFSET 0x0000a43c +#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_MSB 31 +#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_LSB 0 +#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_17 */ +#define PHY_BB_TX_GAIN_TAB_17_ADDRESS 0x0000a440 +#define PHY_BB_TX_GAIN_TAB_17_OFFSET 0x0000a440 +#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_MSB 31 +#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_LSB 0 +#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_18 */ +#define PHY_BB_TX_GAIN_TAB_18_ADDRESS 0x0000a444 +#define PHY_BB_TX_GAIN_TAB_18_OFFSET 0x0000a444 +#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_MSB 31 +#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_LSB 0 +#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_19 */ +#define PHY_BB_TX_GAIN_TAB_19_ADDRESS 0x0000a448 +#define PHY_BB_TX_GAIN_TAB_19_OFFSET 0x0000a448 +#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_MSB 31 +#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_LSB 0 +#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_20 */ +#define PHY_BB_TX_GAIN_TAB_20_ADDRESS 0x0000a44c +#define PHY_BB_TX_GAIN_TAB_20_OFFSET 0x0000a44c +#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_MSB 31 +#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_LSB 0 +#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_21 */ +#define PHY_BB_TX_GAIN_TAB_21_ADDRESS 0x0000a450 +#define PHY_BB_TX_GAIN_TAB_21_OFFSET 0x0000a450 +#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_MSB 31 +#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_LSB 0 +#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_22 */ +#define PHY_BB_TX_GAIN_TAB_22_ADDRESS 0x0000a454 +#define PHY_BB_TX_GAIN_TAB_22_OFFSET 0x0000a454 +#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_MSB 31 +#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_LSB 0 +#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_23 */ +#define PHY_BB_TX_GAIN_TAB_23_ADDRESS 0x0000a458 +#define PHY_BB_TX_GAIN_TAB_23_OFFSET 0x0000a458 +#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_MSB 31 +#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_LSB 0 +#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_24 */ +#define PHY_BB_TX_GAIN_TAB_24_ADDRESS 0x0000a45c +#define PHY_BB_TX_GAIN_TAB_24_OFFSET 0x0000a45c +#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_MSB 31 +#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_LSB 0 +#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_25 */ +#define PHY_BB_TX_GAIN_TAB_25_ADDRESS 0x0000a460 +#define PHY_BB_TX_GAIN_TAB_25_OFFSET 0x0000a460 +#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_MSB 31 +#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_LSB 0 +#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_26 */ +#define PHY_BB_TX_GAIN_TAB_26_ADDRESS 0x0000a464 +#define PHY_BB_TX_GAIN_TAB_26_OFFSET 0x0000a464 +#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_MSB 31 +#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_LSB 0 +#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_27 */ +#define PHY_BB_TX_GAIN_TAB_27_ADDRESS 0x0000a468 +#define PHY_BB_TX_GAIN_TAB_27_OFFSET 0x0000a468 +#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_MSB 31 +#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_LSB 0 +#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_28 */ +#define PHY_BB_TX_GAIN_TAB_28_ADDRESS 0x0000a46c +#define PHY_BB_TX_GAIN_TAB_28_OFFSET 0x0000a46c +#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_MSB 31 +#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_LSB 0 +#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_29 */ +#define PHY_BB_TX_GAIN_TAB_29_ADDRESS 0x0000a470 +#define PHY_BB_TX_GAIN_TAB_29_OFFSET 0x0000a470 +#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_MSB 31 +#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_LSB 0 +#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_30 */ +#define PHY_BB_TX_GAIN_TAB_30_ADDRESS 0x0000a474 +#define PHY_BB_TX_GAIN_TAB_30_OFFSET 0x0000a474 +#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_MSB 31 +#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_LSB 0 +#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_31 */ +#define PHY_BB_TX_GAIN_TAB_31_ADDRESS 0x0000a478 +#define PHY_BB_TX_GAIN_TAB_31_OFFSET 0x0000a478 +#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_MSB 31 +#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_LSB 0 +#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_32 */ +#define PHY_BB_TX_GAIN_TAB_32_ADDRESS 0x0000a47c +#define PHY_BB_TX_GAIN_TAB_32_OFFSET 0x0000a47c +#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_MSB 31 +#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_LSB 0 +#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_1 */ +#define PHY_BB_TX_GAIN_TAB_PAL_1_ADDRESS 0x0000a480 +#define PHY_BB_TX_GAIN_TAB_PAL_1_OFFSET 0x0000a480 +#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_2 */ +#define PHY_BB_TX_GAIN_TAB_PAL_2_ADDRESS 0x0000a484 +#define PHY_BB_TX_GAIN_TAB_PAL_2_OFFSET 0x0000a484 +#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_3 */ +#define PHY_BB_TX_GAIN_TAB_PAL_3_ADDRESS 0x0000a488 +#define PHY_BB_TX_GAIN_TAB_PAL_3_OFFSET 0x0000a488 +#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_4 */ +#define PHY_BB_TX_GAIN_TAB_PAL_4_ADDRESS 0x0000a48c +#define PHY_BB_TX_GAIN_TAB_PAL_4_OFFSET 0x0000a48c +#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_5 */ +#define PHY_BB_TX_GAIN_TAB_PAL_5_ADDRESS 0x0000a490 +#define PHY_BB_TX_GAIN_TAB_PAL_5_OFFSET 0x0000a490 +#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_6 */ +#define PHY_BB_TX_GAIN_TAB_PAL_6_ADDRESS 0x0000a494 +#define PHY_BB_TX_GAIN_TAB_PAL_6_OFFSET 0x0000a494 +#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_7 */ +#define PHY_BB_TX_GAIN_TAB_PAL_7_ADDRESS 0x0000a498 +#define PHY_BB_TX_GAIN_TAB_PAL_7_OFFSET 0x0000a498 +#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_8 */ +#define PHY_BB_TX_GAIN_TAB_PAL_8_ADDRESS 0x0000a49c +#define PHY_BB_TX_GAIN_TAB_PAL_8_OFFSET 0x0000a49c +#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_9 */ +#define PHY_BB_TX_GAIN_TAB_PAL_9_ADDRESS 0x0000a4a0 +#define PHY_BB_TX_GAIN_TAB_PAL_9_OFFSET 0x0000a4a0 +#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_10 */ +#define PHY_BB_TX_GAIN_TAB_PAL_10_ADDRESS 0x0000a4a4 +#define PHY_BB_TX_GAIN_TAB_PAL_10_OFFSET 0x0000a4a4 +#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_11 */ +#define PHY_BB_TX_GAIN_TAB_PAL_11_ADDRESS 0x0000a4a8 +#define PHY_BB_TX_GAIN_TAB_PAL_11_OFFSET 0x0000a4a8 +#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_12 */ +#define PHY_BB_TX_GAIN_TAB_PAL_12_ADDRESS 0x0000a4ac +#define PHY_BB_TX_GAIN_TAB_PAL_12_OFFSET 0x0000a4ac +#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_13 */ +#define PHY_BB_TX_GAIN_TAB_PAL_13_ADDRESS 0x0000a4b0 +#define PHY_BB_TX_GAIN_TAB_PAL_13_OFFSET 0x0000a4b0 +#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_14 */ +#define PHY_BB_TX_GAIN_TAB_PAL_14_ADDRESS 0x0000a4b4 +#define PHY_BB_TX_GAIN_TAB_PAL_14_OFFSET 0x0000a4b4 +#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_15 */ +#define PHY_BB_TX_GAIN_TAB_PAL_15_ADDRESS 0x0000a4b8 +#define PHY_BB_TX_GAIN_TAB_PAL_15_OFFSET 0x0000a4b8 +#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_16 */ +#define PHY_BB_TX_GAIN_TAB_PAL_16_ADDRESS 0x0000a4bc +#define PHY_BB_TX_GAIN_TAB_PAL_16_OFFSET 0x0000a4bc +#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_17 */ +#define PHY_BB_TX_GAIN_TAB_PAL_17_ADDRESS 0x0000a4c0 +#define PHY_BB_TX_GAIN_TAB_PAL_17_OFFSET 0x0000a4c0 +#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_18 */ +#define PHY_BB_TX_GAIN_TAB_PAL_18_ADDRESS 0x0000a4c4 +#define PHY_BB_TX_GAIN_TAB_PAL_18_OFFSET 0x0000a4c4 +#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_19 */ +#define PHY_BB_TX_GAIN_TAB_PAL_19_ADDRESS 0x0000a4c8 +#define PHY_BB_TX_GAIN_TAB_PAL_19_OFFSET 0x0000a4c8 +#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_20 */ +#define PHY_BB_TX_GAIN_TAB_PAL_20_ADDRESS 0x0000a4cc +#define PHY_BB_TX_GAIN_TAB_PAL_20_OFFSET 0x0000a4cc +#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_21 */ +#define PHY_BB_TX_GAIN_TAB_PAL_21_ADDRESS 0x0000a4d0 +#define PHY_BB_TX_GAIN_TAB_PAL_21_OFFSET 0x0000a4d0 +#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_22 */ +#define PHY_BB_TX_GAIN_TAB_PAL_22_ADDRESS 0x0000a4d4 +#define PHY_BB_TX_GAIN_TAB_PAL_22_OFFSET 0x0000a4d4 +#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_23 */ +#define PHY_BB_TX_GAIN_TAB_PAL_23_ADDRESS 0x0000a4d8 +#define PHY_BB_TX_GAIN_TAB_PAL_23_OFFSET 0x0000a4d8 +#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_24 */ +#define PHY_BB_TX_GAIN_TAB_PAL_24_ADDRESS 0x0000a4dc +#define PHY_BB_TX_GAIN_TAB_PAL_24_OFFSET 0x0000a4dc +#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_25 */ +#define PHY_BB_TX_GAIN_TAB_PAL_25_ADDRESS 0x0000a4e0 +#define PHY_BB_TX_GAIN_TAB_PAL_25_OFFSET 0x0000a4e0 +#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_26 */ +#define PHY_BB_TX_GAIN_TAB_PAL_26_ADDRESS 0x0000a4e4 +#define PHY_BB_TX_GAIN_TAB_PAL_26_OFFSET 0x0000a4e4 +#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_27 */ +#define PHY_BB_TX_GAIN_TAB_PAL_27_ADDRESS 0x0000a4e8 +#define PHY_BB_TX_GAIN_TAB_PAL_27_OFFSET 0x0000a4e8 +#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_28 */ +#define PHY_BB_TX_GAIN_TAB_PAL_28_ADDRESS 0x0000a4ec +#define PHY_BB_TX_GAIN_TAB_PAL_28_OFFSET 0x0000a4ec +#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_29 */ +#define PHY_BB_TX_GAIN_TAB_PAL_29_ADDRESS 0x0000a4f0 +#define PHY_BB_TX_GAIN_TAB_PAL_29_OFFSET 0x0000a4f0 +#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_30 */ +#define PHY_BB_TX_GAIN_TAB_PAL_30_ADDRESS 0x0000a4f4 +#define PHY_BB_TX_GAIN_TAB_PAL_30_OFFSET 0x0000a4f4 +#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_31 */ +#define PHY_BB_TX_GAIN_TAB_PAL_31_ADDRESS 0x0000a4f8 +#define PHY_BB_TX_GAIN_TAB_PAL_31_OFFSET 0x0000a4f8 +#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_32 */ +#define PHY_BB_TX_GAIN_TAB_PAL_32_ADDRESS 0x0000a4fc +#define PHY_BB_TX_GAIN_TAB_PAL_32_OFFSET 0x0000a4fc +#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_caltx_gain_set_0 */ +#define PHY_BB_CALTX_GAIN_SET_0_ADDRESS 0x0000a518 +#define PHY_BB_CALTX_GAIN_SET_0_OFFSET 0x0000a518 +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_2 */ +#define PHY_BB_CALTX_GAIN_SET_2_ADDRESS 0x0000a51c +#define PHY_BB_CALTX_GAIN_SET_2_OFFSET 0x0000a51c +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_4 */ +#define PHY_BB_CALTX_GAIN_SET_4_ADDRESS 0x0000a520 +#define PHY_BB_CALTX_GAIN_SET_4_OFFSET 0x0000a520 +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_6 */ +#define PHY_BB_CALTX_GAIN_SET_6_ADDRESS 0x0000a524 +#define PHY_BB_CALTX_GAIN_SET_6_OFFSET 0x0000a524 +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_8 */ +#define PHY_BB_CALTX_GAIN_SET_8_ADDRESS 0x0000a528 +#define PHY_BB_CALTX_GAIN_SET_8_OFFSET 0x0000a528 +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_10 */ +#define PHY_BB_CALTX_GAIN_SET_10_ADDRESS 0x0000a52c +#define PHY_BB_CALTX_GAIN_SET_10_OFFSET 0x0000a52c +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_12 */ +#define PHY_BB_CALTX_GAIN_SET_12_ADDRESS 0x0000a530 +#define PHY_BB_CALTX_GAIN_SET_12_OFFSET 0x0000a530 +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_14 */ +#define PHY_BB_CALTX_GAIN_SET_14_ADDRESS 0x0000a534 +#define PHY_BB_CALTX_GAIN_SET_14_OFFSET 0x0000a534 +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_16 */ +#define PHY_BB_CALTX_GAIN_SET_16_ADDRESS 0x0000a538 +#define PHY_BB_CALTX_GAIN_SET_16_OFFSET 0x0000a538 +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_18 */ +#define PHY_BB_CALTX_GAIN_SET_18_ADDRESS 0x0000a53c +#define PHY_BB_CALTX_GAIN_SET_18_OFFSET 0x0000a53c +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_20 */ +#define PHY_BB_CALTX_GAIN_SET_20_ADDRESS 0x0000a540 +#define PHY_BB_CALTX_GAIN_SET_20_OFFSET 0x0000a540 +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_22 */ +#define PHY_BB_CALTX_GAIN_SET_22_ADDRESS 0x0000a544 +#define PHY_BB_CALTX_GAIN_SET_22_OFFSET 0x0000a544 +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_24 */ +#define PHY_BB_CALTX_GAIN_SET_24_ADDRESS 0x0000a548 +#define PHY_BB_CALTX_GAIN_SET_24_OFFSET 0x0000a548 +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_26 */ +#define PHY_BB_CALTX_GAIN_SET_26_ADDRESS 0x0000a54c +#define PHY_BB_CALTX_GAIN_SET_26_OFFSET 0x0000a54c +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_28 */ +#define PHY_BB_CALTX_GAIN_SET_28_ADDRESS 0x0000a550 +#define PHY_BB_CALTX_GAIN_SET_28_OFFSET 0x0000a550 +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_30 */ +#define PHY_BB_CALTX_GAIN_SET_30_ADDRESS 0x0000a554 +#define PHY_BB_CALTX_GAIN_SET_30_OFFSET 0x0000a554 +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiqcal_meas_b0 */ +#define PHY_BB_TXIQCAL_MEAS_B0_ADDRESS 0x0000a558 +#define PHY_BB_TXIQCAL_MEAS_B0_OFFSET 0x0000a558 +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_MSB 11 +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_LSB 0 +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_MASK 0x00000fff +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_MSB 23 +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_LSB 12 +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_MASK 0x00fff000 +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_GET(x) (((x) & 0x00fff000) >> 12) + +/* macros for BB_txiqcal_start */ +#define PHY_BB_TXIQCAL_START_ADDRESS 0x0000a6d8 +#define PHY_BB_TXIQCAL_START_OFFSET 0x0000a6d8 +#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_MSB 0 +#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_LSB 0 +#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_MASK 0x00000001 +#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_SET(x) (((x) << 0) & 0x00000001) + +/* macros for BB_txiqcal_control_0 */ +#define PHY_BB_TXIQCAL_CONTROL_0_ADDRESS 0x0000a6dc +#define PHY_BB_TXIQCAL_CONTROL_0_OFFSET 0x0000a6dc +#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_MSB 0 +#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_LSB 0 +#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_MASK 0x00000001 +#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MSB 6 +#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_LSB 1 +#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MASK 0x0000007e +#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_GET(x) (((x) & 0x0000007e) >> 1) +#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_SET(x) (((x) << 1) & 0x0000007e) +#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MSB 12 +#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_LSB 7 +#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MASK 0x00001f80 +#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_GET(x) (((x) & 0x00001f80) >> 7) +#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_SET(x) (((x) << 7) & 0x00001f80) +#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MSB 18 +#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_LSB 13 +#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MASK 0x0007e000 +#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_GET(x) (((x) & 0x0007e000) >> 13) +#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_SET(x) (((x) << 13) & 0x0007e000) +#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MSB 22 +#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_LSB 19 +#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MASK 0x00780000 +#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_GET(x) (((x) & 0x00780000) >> 19) +#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_SET(x) (((x) << 19) & 0x00780000) +#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MSB 29 +#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_LSB 23 +#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MASK 0x3f800000 +#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_GET(x) (((x) & 0x3f800000) >> 23) +#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_SET(x) (((x) << 23) & 0x3f800000) + +/* macros for BB_txiqcal_control_1 */ +#define PHY_BB_TXIQCAL_CONTROL_1_ADDRESS 0x0000a6e0 +#define PHY_BB_TXIQCAL_CONTROL_1_OFFSET 0x0000a6e0 +#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MSB 5 +#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_LSB 0 +#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MASK 0x0000003f +#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MSB 11 +#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_LSB 6 +#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MASK 0x00000fc0 +#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MSB 17 +#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_LSB 12 +#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MASK 0x0003f000 +#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MSB 24 +#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_LSB 18 +#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MASK 0x01fc0000 +#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_GET(x) (((x) & 0x01fc0000) >> 18) +#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_SET(x) (((x) << 18) & 0x01fc0000) + +/* macros for BB_txiqcal_control_2 */ +#define PHY_BB_TXIQCAL_CONTROL_2_ADDRESS 0x0000a6e4 +#define PHY_BB_TXIQCAL_CONTROL_2_OFFSET 0x0000a6e4 +#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_MSB 3 +#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_LSB 0 +#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_MASK 0x0000000f +#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MSB 8 +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_LSB 4 +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MASK 0x000001f0 +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_GET(x) (((x) & 0x000001f0) >> 4) +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_SET(x) (((x) << 4) & 0x000001f0) +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MSB 13 +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_LSB 9 +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MASK 0x00003e00 +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_GET(x) (((x) & 0x00003e00) >> 9) +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_SET(x) (((x) << 9) & 0x00003e00) + +/* macros for BB_txiqcal_control_3 */ +#define PHY_BB_TXIQCAL_CONTROL_3_ADDRESS 0x0000a6e8 +#define PHY_BB_TXIQCAL_CONTROL_3_OFFSET 0x0000a6e8 +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MSB 5 +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_LSB 0 +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MASK 0x0000003f +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MSB 11 +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_LSB 6 +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MASK 0x00000fc0 +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MSB 21 +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_LSB 12 +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MASK 0x003ff000 +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_GET(x) (((x) & 0x003ff000) >> 12) +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_SET(x) (((x) << 12) & 0x003ff000) +#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MSB 23 +#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_LSB 22 +#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MASK 0x00c00000 +#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_MSB 24 +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_LSB 24 +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_MASK 0x01000000 +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_SET(x) (((x) << 24) & 0x01000000) +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_MSB 26 +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_LSB 25 +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_MASK 0x06000000 +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_GET(x) (((x) & 0x06000000) >> 25) +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_SET(x) (((x) << 25) & 0x06000000) +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_MSB 28 +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_LSB 27 +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_MASK 0x18000000 +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_GET(x) (((x) & 0x18000000) >> 27) +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_SET(x) (((x) << 27) & 0x18000000) +#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MSB 30 +#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_LSB 29 +#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MASK 0x60000000 +#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_SET(x) (((x) << 29) & 0x60000000) +#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MSB 31 +#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_LSB 31 +#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MASK 0x80000000 +#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_txiq_corr_coeff_01_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_ADDRESS 0x0000a6ec +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_OFFSET 0x0000a6ec +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_23_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_ADDRESS 0x0000a6f0 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_OFFSET 0x0000a6f0 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_45_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_ADDRESS 0x0000a6f4 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_OFFSET 0x0000a6f4 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_67_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_ADDRESS 0x0000a6f8 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_OFFSET 0x0000a6f8 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_89_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_ADDRESS 0x0000a6fc +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_OFFSET 0x0000a6fc +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_ab_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_ADDRESS 0x0000a700 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_OFFSET 0x0000a700 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_cd_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_ADDRESS 0x0000a704 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_OFFSET 0x0000a704 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_ef_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_ADDRESS 0x0000a708 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_OFFSET 0x0000a708 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_cal_rxbb_gain_tbl_0 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_ADDRESS 0x0000a70c +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_OFFSET 0x0000a70c +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MSB 11 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_LSB 6 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MASK 0x00000fc0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MSB 17 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_LSB 12 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MASK 0x0003f000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MSB 23 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_LSB 18 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MASK 0x00fc0000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_SET(x) (((x) << 18) & 0x00fc0000) + +/* macros for BB_cal_rxbb_gain_tbl_4 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_ADDRESS 0x0000a710 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_OFFSET 0x0000a710 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MSB 11 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_LSB 6 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MASK 0x00000fc0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MSB 17 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_LSB 12 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MASK 0x0003f000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MSB 23 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_LSB 18 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MASK 0x00fc0000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_SET(x) (((x) << 18) & 0x00fc0000) + +/* macros for BB_cal_rxbb_gain_tbl_8 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_ADDRESS 0x0000a714 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_OFFSET 0x0000a714 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MSB 11 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_LSB 6 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MASK 0x00000fc0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MSB 17 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_LSB 12 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MASK 0x0003f000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MSB 23 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_LSB 18 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MASK 0x00fc0000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_SET(x) (((x) << 18) & 0x00fc0000) + +/* macros for BB_cal_rxbb_gain_tbl_12 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_ADDRESS 0x0000a718 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_OFFSET 0x0000a718 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MSB 11 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_LSB 6 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MASK 0x00000fc0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MSB 17 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_LSB 12 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MASK 0x0003f000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MSB 23 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_LSB 18 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MASK 0x00fc0000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_SET(x) (((x) << 18) & 0x00fc0000) + +/* macros for BB_cal_rxbb_gain_tbl_16 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_ADDRESS 0x0000a71c +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_OFFSET 0x0000a71c +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MSB 11 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_LSB 6 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MASK 0x00000fc0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MSB 17 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_LSB 12 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MASK 0x0003f000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MSB 23 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_LSB 18 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MASK 0x00fc0000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_SET(x) (((x) << 18) & 0x00fc0000) + +/* macros for BB_cal_rxbb_gain_tbl_20 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_ADDRESS 0x0000a720 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_OFFSET 0x0000a720 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MSB 11 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_LSB 6 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MASK 0x00000fc0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MSB 17 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_LSB 12 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MASK 0x0003f000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MSB 23 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_LSB 18 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MASK 0x00fc0000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_SET(x) (((x) << 18) & 0x00fc0000) + +/* macros for BB_cal_rxbb_gain_tbl_24 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_ADDRESS 0x0000a724 +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_OFFSET 0x0000a724 +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_SET(x) (((x) << 0) & 0x0000003f) + +/* macros for BB_txiqcal_status_b0 */ +#define PHY_BB_TXIQCAL_STATUS_B0_ADDRESS 0x0000a728 +#define PHY_BB_TXIQCAL_STATUS_B0_OFFSET 0x0000a728 +#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MSB 0 +#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_LSB 0 +#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MASK 0x00000001 +#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MSB 5 +#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_LSB 1 +#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MASK 0x0000003e +#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_GET(x) (((x) & 0x0000003e) >> 1) +#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MSB 11 +#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_LSB 6 +#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MASK 0x00000fc0 +#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MSB 17 +#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_LSB 12 +#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MASK 0x0003f000 +#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MSB 24 +#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_LSB 18 +#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MASK 0x01fc0000 +#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_GET(x) (((x) & 0x01fc0000) >> 18) + +/* macros for BB_paprd_trainer_cntl1 */ +#define PHY_BB_PAPRD_TRAINER_CNTL1_ADDRESS 0x0000a72c +#define PHY_BB_PAPRD_TRAINER_CNTL1_OFFSET 0x0000a72c +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MSB 0 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_LSB 0 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MASK 0x00000001 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MSB 7 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_LSB 1 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MASK 0x000000fe +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_GET(x) (((x) & 0x000000fe) >> 1) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_SET(x) (((x) << 1) & 0x000000fe) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MSB 8 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_LSB 8 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MASK 0x00000100 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MSB 9 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_LSB 9 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MASK 0x00000200 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MSB 10 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_LSB 10 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MASK 0x00000400 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_MSB 11 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_LSB 11 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_MASK 0x00000800 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_SET(x) (((x) << 11) & 0x00000800) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_MSB 18 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_LSB 12 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_MASK 0x0007f000 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_GET(x) (((x) & 0x0007f000) >> 12) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_SET(x) (((x) << 12) & 0x0007f000) + +/* macros for BB_paprd_trainer_cntl2 */ +#define PHY_BB_PAPRD_TRAINER_CNTL2_ADDRESS 0x0000a730 +#define PHY_BB_PAPRD_TRAINER_CNTL2_OFFSET 0x0000a730 +#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MSB 31 +#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_LSB 0 +#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MASK 0xffffffff +#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_paprd_trainer_cntl3 */ +#define PHY_BB_PAPRD_TRAINER_CNTL3_ADDRESS 0x0000a734 +#define PHY_BB_PAPRD_TRAINER_CNTL3_OFFSET 0x0000a734 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_MSB 5 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_LSB 0 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_MASK 0x0000003f +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MSB 11 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_LSB 6 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MASK 0x00000fc0 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MSB 16 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_LSB 12 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MASK 0x0001f000 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MSB 19 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_LSB 17 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MASK 0x000e0000 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MSB 23 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_LSB 20 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MASK 0x00f00000 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_GET(x) (((x) & 0x00f00000) >> 20) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_SET(x) (((x) << 20) & 0x00f00000) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MSB 27 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_LSB 24 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MASK 0x0f000000 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_GET(x) (((x) & 0x0f000000) >> 24) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_SET(x) (((x) << 24) & 0x0f000000) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MSB 28 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_LSB 28 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MASK 0x10000000 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_SET(x) (((x) << 28) & 0x10000000) + +/* macros for BB_paprd_trainer_cntl4 */ +#define PHY_BB_PAPRD_TRAINER_CNTL4_ADDRESS 0x0000a738 +#define PHY_BB_PAPRD_TRAINER_CNTL4_OFFSET 0x0000a738 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MSB 11 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_LSB 0 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MASK 0x00000fff +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_SET(x) (((x) << 0) & 0x00000fff) +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MSB 15 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_LSB 12 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MASK 0x0000f000 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MSB 25 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_LSB 16 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MASK 0x03ff0000 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_GET(x) (((x) & 0x03ff0000) >> 16) +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_SET(x) (((x) << 16) & 0x03ff0000) + +/* macros for BB_paprd_trainer_stat1 */ +#define PHY_BB_PAPRD_TRAINER_STAT1_ADDRESS 0x0000a73c +#define PHY_BB_PAPRD_TRAINER_STAT1_OFFSET 0x0000a73c +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MSB 0 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_LSB 0 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MASK 0x00000001 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MSB 1 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_LSB 1 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MASK 0x00000002 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MSB 2 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_LSB 2 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MASK 0x00000004 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MSB 3 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_LSB 3 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MASK 0x00000008 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MSB 8 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_LSB 4 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MASK 0x000001f0 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_GET(x) (((x) & 0x000001f0) >> 4) +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MSB 16 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_LSB 9 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MASK 0x0001fe00 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_GET(x) (((x) & 0x0001fe00) >> 9) + +/* macros for BB_paprd_trainer_stat2 */ +#define PHY_BB_PAPRD_TRAINER_STAT2_ADDRESS 0x0000a740 +#define PHY_BB_PAPRD_TRAINER_STAT2_OFFSET 0x0000a740 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MSB 15 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_LSB 0 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MASK 0x0000ffff +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_GET(x) (((x) & 0x0000ffff) >> 0) +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MSB 20 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_LSB 16 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MASK 0x001f0000 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MSB 22 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_LSB 21 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MASK 0x00600000 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_GET(x) (((x) & 0x00600000) >> 21) + +/* macros for BB_paprd_trainer_stat3 */ +#define PHY_BB_PAPRD_TRAINER_STAT3_ADDRESS 0x0000a744 +#define PHY_BB_PAPRD_TRAINER_STAT3_OFFSET 0x0000a744 +#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MSB 19 +#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_LSB 0 +#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MASK 0x000fffff +#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_GET(x) (((x) & 0x000fffff) >> 0) + +/* macros for BB_fcal_1 */ +#define PHY_BB_FCAL_1_ADDRESS 0x0000a7d8 +#define PHY_BB_FCAL_1_OFFSET 0x0000a7d8 +#define PHY_BB_FCAL_1_FLC_PB_FSTEP_MSB 9 +#define PHY_BB_FCAL_1_FLC_PB_FSTEP_LSB 0 +#define PHY_BB_FCAL_1_FLC_PB_FSTEP_MASK 0x000003ff +#define PHY_BB_FCAL_1_FLC_PB_FSTEP_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_FCAL_1_FLC_PB_FSTEP_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_FCAL_1_FLC_SB_FSTEP_MSB 19 +#define PHY_BB_FCAL_1_FLC_SB_FSTEP_LSB 10 +#define PHY_BB_FCAL_1_FLC_SB_FSTEP_MASK 0x000ffc00 +#define PHY_BB_FCAL_1_FLC_SB_FSTEP_GET(x) (((x) & 0x000ffc00) >> 10) +#define PHY_BB_FCAL_1_FLC_SB_FSTEP_SET(x) (((x) << 10) & 0x000ffc00) +#define PHY_BB_FCAL_1_FLC_PB_ATTEN_MSB 24 +#define PHY_BB_FCAL_1_FLC_PB_ATTEN_LSB 20 +#define PHY_BB_FCAL_1_FLC_PB_ATTEN_MASK 0x01f00000 +#define PHY_BB_FCAL_1_FLC_PB_ATTEN_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_FCAL_1_FLC_PB_ATTEN_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_FCAL_1_FLC_SB_ATTEN_MSB 29 +#define PHY_BB_FCAL_1_FLC_SB_ATTEN_LSB 25 +#define PHY_BB_FCAL_1_FLC_SB_ATTEN_MASK 0x3e000000 +#define PHY_BB_FCAL_1_FLC_SB_ATTEN_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_FCAL_1_FLC_SB_ATTEN_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_fcal_2_b0 */ +#define PHY_BB_FCAL_2_B0_ADDRESS 0x0000a7dc +#define PHY_BB_FCAL_2_B0_OFFSET 0x0000a7dc +#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MSB 2 +#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_LSB 0 +#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MASK 0x00000007 +#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_SET(x) (((x) << 0) & 0x00000007) +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MSB 7 +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_LSB 3 +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MASK 0x000000f8 +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_GET(x) (((x) & 0x000000f8) >> 3) +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_SET(x) (((x) << 3) & 0x000000f8) +#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MSB 9 +#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_LSB 8 +#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MASK 0x00000300 +#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_SET(x) (((x) << 8) & 0x00000300) +#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MSB 12 +#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_LSB 10 +#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MASK 0x00001c00 +#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_GET(x) (((x) & 0x00001c00) >> 10) +#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_SET(x) (((x) << 10) & 0x00001c00) +#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MSB 14 +#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_LSB 13 +#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MASK 0x00006000 +#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_GET(x) (((x) & 0x00006000) >> 13) +#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_SET(x) (((x) << 13) & 0x00006000) +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MSB 15 +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_LSB 15 +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MASK 0x00008000 +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MSB 18 +#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_LSB 16 +#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MASK 0x00070000 +#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_SET(x) (((x) << 16) & 0x00070000) +#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MSB 24 +#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_LSB 20 +#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MASK 0x01f00000 +#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_GET(x) (((x) & 0x01f00000) >> 20) + +/* macros for BB_radar_bw_filter */ +#define PHY_BB_RADAR_BW_FILTER_ADDRESS 0x0000a7e0 +#define PHY_BB_RADAR_BW_FILTER_OFFSET 0x0000a7e0 +#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_MSB 0 +#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_LSB 0 +#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_MASK 0x00000001 +#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_MSB 1 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_LSB 1 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_MASK 0x00000002 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_MSB 3 +#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_LSB 2 +#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_MASK 0x0000000c +#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_MSB 5 +#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_LSB 4 +#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_MASK 0x00000030 +#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_SET(x) (((x) << 4) & 0x00000030) +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_MSB 14 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_LSB 8 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_MASK 0x00007f00 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_GET(x) (((x) & 0x00007f00) >> 8) +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_SET(x) (((x) << 8) & 0x00007f00) +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_MSB 20 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_LSB 15 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_MASK 0x001f8000 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_GET(x) (((x) & 0x001f8000) >> 15) +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_SET(x) (((x) << 15) & 0x001f8000) +#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_MSB 26 +#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_LSB 21 +#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_MASK 0x07e00000 +#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_GET(x) (((x) & 0x07e00000) >> 21) +#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_SET(x) (((x) << 21) & 0x07e00000) + +/* macros for BB_dft_tone_ctrl_b0 */ +#define PHY_BB_DFT_TONE_CTRL_B0_ADDRESS 0x0000a7e4 +#define PHY_BB_DFT_TONE_CTRL_B0_OFFSET 0x0000a7e4 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MSB 0 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_LSB 0 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MASK 0x00000001 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MSB 3 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_LSB 2 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MASK 0x0000000c +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MSB 12 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_LSB 4 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MASK 0x00001ff0 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_GET(x) (((x) & 0x00001ff0) >> 4) +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_SET(x) (((x) << 4) & 0x00001ff0) + +/* macros for BB_therm_adc_1 */ +#define PHY_BB_THERM_ADC_1_ADDRESS 0x0000a7e8 +#define PHY_BB_THERM_ADC_1_OFFSET 0x0000a7e8 +#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_MSB 7 +#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_LSB 0 +#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_MASK 0x000000ff +#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_MSB 15 +#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_LSB 8 +#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_MASK 0x0000ff00 +#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_MSB 23 +#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_LSB 16 +#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_MASK 0x00ff0000 +#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_MSB 25 +#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_LSB 24 +#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_MASK 0x03000000 +#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_SET(x) (((x) << 24) & 0x03000000) +#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MSB 26 +#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_LSB 26 +#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MASK 0x04000000 +#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_SET(x) (((x) << 26) & 0x04000000) +#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MSB 27 +#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_LSB 27 +#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MASK 0x08000000 +#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_SET(x) (((x) << 27) & 0x08000000) + +/* macros for BB_therm_adc_2 */ +#define PHY_BB_THERM_ADC_2_ADDRESS 0x0000a7ec +#define PHY_BB_THERM_ADC_2_OFFSET 0x0000a7ec +#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_MSB 11 +#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_LSB 0 +#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_MASK 0x00000fff +#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_SET(x) (((x) << 0) & 0x00000fff) +#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_MSB 21 +#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_LSB 12 +#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_MASK 0x003ff000 +#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_GET(x) (((x) & 0x003ff000) >> 12) +#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_SET(x) (((x) << 12) & 0x003ff000) +#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_MSB 31 +#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_LSB 22 +#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_MASK 0xffc00000 +#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_GET(x) (((x) & 0xffc00000) >> 22) +#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_SET(x) (((x) << 22) & 0xffc00000) + +/* macros for BB_therm_adc_3 */ +#define PHY_BB_THERM_ADC_3_ADDRESS 0x0000a7f0 +#define PHY_BB_THERM_ADC_3_OFFSET 0x0000a7f0 +#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_MSB 7 +#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_LSB 0 +#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_MASK 0x000000ff +#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_MSB 16 +#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_LSB 8 +#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_MASK 0x0001ff00 +#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_GET(x) (((x) & 0x0001ff00) >> 8) +#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_SET(x) (((x) << 8) & 0x0001ff00) +#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_MSB 29 +#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_LSB 17 +#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_MASK 0x3ffe0000 +#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_GET(x) (((x) & 0x3ffe0000) >> 17) +#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_SET(x) (((x) << 17) & 0x3ffe0000) + +/* macros for BB_therm_adc_4 */ +#define PHY_BB_THERM_ADC_4_ADDRESS 0x0000a7f4 +#define PHY_BB_THERM_ADC_4_OFFSET 0x0000a7f4 +#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_MSB 7 +#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_LSB 0 +#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_MASK 0x000000ff +#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_MSB 15 +#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_LSB 8 +#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_MASK 0x0000ff00 +#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_MSB 23 +#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_LSB 16 +#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_MASK 0x00ff0000 +#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_GET(x) (((x) & 0x00ff0000) >> 16) + +/* macros for BB_tx_forced_gain */ +#define PHY_BB_TX_FORCED_GAIN_ADDRESS 0x0000a7f8 +#define PHY_BB_TX_FORCED_GAIN_OFFSET 0x0000a7f8 +#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MSB 0 +#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_LSB 0 +#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MASK 0x00000001 +#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MSB 3 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_LSB 1 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MASK 0x0000000e +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MSB 5 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_LSB 4 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MASK 0x00000030 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_SET(x) (((x) << 4) & 0x00000030) +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MSB 9 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_LSB 6 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MASK 0x000003c0 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_GET(x) (((x) & 0x000003c0) >> 6) +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_SET(x) (((x) << 6) & 0x000003c0) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_MSB 13 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_LSB 10 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_MASK 0x00003c00 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_GET(x) (((x) & 0x00003c00) >> 10) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_SET(x) (((x) << 10) & 0x00003c00) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_MSB 17 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_LSB 14 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_MASK 0x0003c000 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_GET(x) (((x) & 0x0003c000) >> 14) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_SET(x) (((x) << 14) & 0x0003c000) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_MSB 21 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_LSB 18 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_MASK 0x003c0000 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_GET(x) (((x) & 0x003c0000) >> 18) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_SET(x) (((x) << 18) & 0x003c0000) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_MSB 23 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_LSB 22 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_MASK 0x00c00000 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MSB 24 +#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_LSB 24 +#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MASK 0x01000000 +#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_SET(x) (((x) << 24) & 0x01000000) + +/* macros for BB_eco_ctrl */ +#define PHY_BB_ECO_CTRL_ADDRESS 0x0000a7fc +#define PHY_BB_ECO_CTRL_OFFSET 0x0000a7fc +#define PHY_BB_ECO_CTRL_ECO_CTRL_MSB 7 +#define PHY_BB_ECO_CTRL_ECO_CTRL_LSB 0 +#define PHY_BB_ECO_CTRL_ECO_CTRL_MASK 0x000000ff +#define PHY_BB_ECO_CTRL_ECO_CTRL_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_ECO_CTRL_ECO_CTRL_SET(x) (((x) << 0) & 0x000000ff) + +/* macros for BB_gain_force_max_gains_b1 */ +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_ADDRESS 0x0000a848 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_OFFSET 0x0000a848 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_MSB 13 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_LSB 7 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_MASK 0x00003f80 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_GET(x) (((x) & 0x00003f80) >> 7) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_SET(x) (((x) << 7) & 0x00003f80) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_MSB 20 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_LSB 14 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_MASK 0x001fc000 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_GET(x) (((x) & 0x001fc000) >> 14) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_SET(x) (((x) << 14) & 0x001fc000) + +/* macros for BB_gains_min_offsets_b1 */ +#define PHY_BB_GAINS_MIN_OFFSETS_B1_ADDRESS 0x0000a84c +#define PHY_BB_GAINS_MIN_OFFSETS_B1_OFFSET 0x0000a84c +#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_MSB 24 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_LSB 17 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_MASK 0x01fe0000 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_GET(x) (((x) & 0x01fe0000) >> 17) +#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_SET(x) (((x) << 17) & 0x01fe0000) +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_MSB 25 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_LSB 25 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_MASK 0x02000000 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_SET(x) (((x) << 25) & 0x02000000) +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_MSB 26 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_LSB 26 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_MASK 0x04000000 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_SET(x) (((x) << 26) & 0x04000000) + +/* macros for BB_rx_ocgain2 */ +#define PHY_BB_RX_OCGAIN2_ADDRESS 0x0000aa00 +#define PHY_BB_RX_OCGAIN2_OFFSET 0x0000aa00 +#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_MSB 31 +#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_LSB 0 +#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_MASK 0xffffffff +#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_ext_atten_switch_ctl_b1 */ +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_ADDRESS 0x0000b20c +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_OFFSET 0x0000b20c +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_MSB 5 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_LSB 0 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_MASK 0x0000003f +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_MSB 11 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_LSB 6 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_MASK 0x00000fc0 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_MSB 16 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_LSB 12 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_MASK 0x0001f000 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_MSB 21 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_LSB 17 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_MASK 0x003e0000 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_SET(x) (((x) << 17) & 0x003e0000) + + +#ifndef __ASSEMBLER__ + +typedef struct bb_lc_reg_reg_s { + volatile char pad__0[0x9800]; /* 0x0 - 0x9800 */ + volatile unsigned int BB_test_controls; /* 0x9800 - 0x9804 */ + volatile unsigned int BB_gen_controls; /* 0x9804 - 0x9808 */ + volatile unsigned int BB_test_controls_status; /* 0x9808 - 0x980c */ + volatile unsigned int BB_timing_controls_1; /* 0x980c - 0x9810 */ + volatile unsigned int BB_timing_controls_2; /* 0x9810 - 0x9814 */ + volatile unsigned int BB_timing_controls_3; /* 0x9814 - 0x9818 */ + volatile unsigned int BB_D2_chip_id; /* 0x9818 - 0x981c */ + volatile unsigned int BB_active; /* 0x981c - 0x9820 */ + volatile unsigned int BB_tx_timing_1; /* 0x9820 - 0x9824 */ + volatile unsigned int BB_tx_timing_2; /* 0x9824 - 0x9828 */ + volatile unsigned int BB_tx_timing_3; /* 0x9828 - 0x982c */ + volatile unsigned int BB_addac_parallel_control; /* 0x982c - 0x9830 */ + volatile char pad__1[0x4]; /* 0x9830 - 0x9834 */ + volatile unsigned int BB_xpa_timing_control; /* 0x9834 - 0x9838 */ + volatile unsigned int BB_misc_pa_control; /* 0x9838 - 0x983c */ + volatile unsigned int BB_tstdac_constant; /* 0x983c - 0x9840 */ + volatile unsigned int BB_find_signal_low; /* 0x9840 - 0x9844 */ + volatile unsigned int BB_settling_time; /* 0x9844 - 0x9848 */ + volatile unsigned int BB_gain_force_max_gains_b0; /* 0x9848 - 0x984c */ + volatile unsigned int BB_gains_min_offsets_b0; /* 0x984c - 0x9850 */ + volatile unsigned int BB_desired_sigsize; /* 0x9850 - 0x9854 */ + volatile unsigned int BB_timing_control_3a; /* 0x9854 - 0x9858 */ + volatile unsigned int BB_find_signal; /* 0x9858 - 0x985c */ + volatile unsigned int BB_agc; /* 0x985c - 0x9860 */ + volatile unsigned int BB_agc_control; /* 0x9860 - 0x9864 */ + volatile unsigned int BB_cca_b0; /* 0x9864 - 0x9868 */ + volatile unsigned int BB_sfcorr; /* 0x9868 - 0x986c */ + volatile unsigned int BB_self_corr_low; /* 0x986c - 0x9870 */ + volatile char pad__2[0x4]; /* 0x9870 - 0x9874 */ + volatile unsigned int BB_synth_control; /* 0x9874 - 0x9878 */ + volatile unsigned int BB_addac_clk_select; /* 0x9878 - 0x987c */ + volatile unsigned int BB_pll_cntl; /* 0x987c - 0x9880 */ + volatile char pad__3[0x80]; /* 0x9880 - 0x9900 */ + volatile unsigned int BB_vit_spur_mask_A; /* 0x9900 - 0x9904 */ + volatile unsigned int BB_vit_spur_mask_B; /* 0x9904 - 0x9908 */ + volatile unsigned int BB_pilot_spur_mask; /* 0x9908 - 0x990c */ + volatile unsigned int BB_chan_spur_mask; /* 0x990c - 0x9910 */ + volatile unsigned int BB_spectral_scan; /* 0x9910 - 0x9914 */ + volatile unsigned int BB_analog_power_on_time; /* 0x9914 - 0x9918 */ + volatile unsigned int BB_search_start_delay; /* 0x9918 - 0x991c */ + volatile unsigned int BB_max_rx_length; /* 0x991c - 0x9920 */ + volatile unsigned int BB_timing_control_4; /* 0x9920 - 0x9924 */ + volatile unsigned int BB_timing_control_5; /* 0x9924 - 0x9928 */ + volatile unsigned int BB_phyonly_warm_reset; /* 0x9928 - 0x992c */ + volatile unsigned int BB_phyonly_control; /* 0x992c - 0x9930 */ + volatile char pad__4[0x4]; /* 0x9930 - 0x9934 */ + volatile unsigned int BB_powertx_rate1; /* 0x9934 - 0x9938 */ + volatile unsigned int BB_powertx_rate2; /* 0x9938 - 0x993c */ + volatile unsigned int BB_powertx_max; /* 0x993c - 0x9940 */ + volatile unsigned int BB_extension_radar; /* 0x9940 - 0x9944 */ + volatile unsigned int BB_frame_control; /* 0x9944 - 0x9948 */ + volatile unsigned int BB_timing_control_6; /* 0x9948 - 0x994c */ + volatile unsigned int BB_spur_mask_controls; /* 0x994c - 0x9950 */ + volatile unsigned int BB_rx_iq_corr_b0; /* 0x9950 - 0x9954 */ + volatile unsigned int BB_radar_detection; /* 0x9954 - 0x9958 */ + volatile unsigned int BB_radar_detection_2; /* 0x9958 - 0x995c */ + volatile unsigned int BB_tx_phase_ramp_b0; /* 0x995c - 0x9960 */ + volatile unsigned int BB_switch_table_chn_b0; /* 0x9960 - 0x9964 */ + volatile unsigned int BB_switch_table_com1; /* 0x9964 - 0x9968 */ + volatile unsigned int BB_cca_ctrl_2_b0; /* 0x9968 - 0x996c */ + volatile unsigned int BB_switch_table_com2; /* 0x996c - 0x9970 */ + volatile unsigned int BB_restart; /* 0x9970 - 0x9974 */ + volatile char pad__5[0x4]; /* 0x9974 - 0x9978 */ + volatile unsigned int BB_scrambler_seed; /* 0x9978 - 0x997c */ + volatile unsigned int BB_rfbus_request; /* 0x997c - 0x9980 */ + volatile char pad__6[0x20]; /* 0x9980 - 0x99a0 */ + volatile unsigned int BB_timing_control_11; /* 0x99a0 - 0x99a4 */ + volatile unsigned int BB_multichain_enable; /* 0x99a4 - 0x99a8 */ + volatile unsigned int BB_multichain_control; /* 0x99a8 - 0x99ac */ + volatile unsigned int BB_multichain_gain_ctrl; /* 0x99ac - 0x99b0 */ + volatile char pad__7[0x4]; /* 0x99b0 - 0x99b4 */ + volatile unsigned int BB_adc_gain_dc_corr_b0; /* 0x99b4 - 0x99b8 */ + volatile unsigned int BB_ext_chan_pwr_thr_1; /* 0x99b8 - 0x99bc */ + volatile unsigned int BB_ext_chan_pwr_thr_2_b0; /* 0x99bc - 0x99c0 */ + volatile unsigned int BB_ext_chan_scorr_thr; /* 0x99c0 - 0x99c4 */ + volatile unsigned int BB_ext_chan_detect_win; /* 0x99c4 - 0x99c8 */ + volatile unsigned int BB_pwr_thr_20_40_det; /* 0x99c8 - 0x99cc */ + volatile char pad__8[0x4]; /* 0x99cc - 0x99d0 */ + volatile unsigned int BB_short_gi_delta_slope; /* 0x99d0 - 0x99d4 */ + volatile char pad__9[0x8]; /* 0x99d4 - 0x99dc */ + volatile unsigned int BB_chaninfo_ctrl; /* 0x99dc - 0x99e0 */ + volatile unsigned int BB_heavy_clip_ctrl; /* 0x99e0 - 0x99e4 */ + volatile unsigned int BB_heavy_clip_20; /* 0x99e4 - 0x99e8 */ + volatile unsigned int BB_heavy_clip_40; /* 0x99e8 - 0x99ec */ + volatile unsigned int BB_rifs_srch; /* 0x99ec - 0x99f0 */ + volatile unsigned int BB_iq_adc_cal_mode; /* 0x99f0 - 0x99f4 */ + volatile char pad__10[0x8]; /* 0x99f4 - 0x99fc */ + volatile unsigned int BB_per_chain_csd; /* 0x99fc - 0x9a00 */ + volatile unsigned int BB_rx_ocgain[128]; /* 0x9a00 - 0x9c00 */ + volatile unsigned int BB_tx_crc; /* 0x9c00 - 0x9c04 */ + volatile char pad__11[0xc]; /* 0x9c04 - 0x9c10 */ + volatile unsigned int BB_iq_adc_meas_0_b0; /* 0x9c10 - 0x9c14 */ + volatile unsigned int BB_iq_adc_meas_1_b0; /* 0x9c14 - 0x9c18 */ + volatile unsigned int BB_iq_adc_meas_2_b0; /* 0x9c18 - 0x9c1c */ + volatile unsigned int BB_iq_adc_meas_3_b0; /* 0x9c1c - 0x9c20 */ + volatile unsigned int BB_rfbus_grant; /* 0x9c20 - 0x9c24 */ + volatile unsigned int BB_tstadc; /* 0x9c24 - 0x9c28 */ + volatile unsigned int BB_tstdac; /* 0x9c28 - 0x9c2c */ + volatile char pad__12[0x4]; /* 0x9c2c - 0x9c30 */ + volatile unsigned int BB_illegal_tx_rate; /* 0x9c30 - 0x9c34 */ + volatile unsigned int BB_spur_report_b0; /* 0x9c34 - 0x9c38 */ + volatile unsigned int BB_channel_status; /* 0x9c38 - 0x9c3c */ + volatile unsigned int BB_rssi_b0; /* 0x9c3c - 0x9c40 */ + volatile unsigned int BB_spur_est_cck_report_b0; /* 0x9c40 - 0x9c44 */ + volatile char pad__13[0x68]; /* 0x9c44 - 0x9cac */ + volatile unsigned int BB_chan_info_noise_pwr; /* 0x9cac - 0x9cb0 */ + volatile unsigned int BB_chan_info_gain_diff; /* 0x9cb0 - 0x9cb4 */ + volatile unsigned int BB_chan_info_fine_timing; /* 0x9cb4 - 0x9cb8 */ + volatile unsigned int BB_chan_info_gain_b0; /* 0x9cb8 - 0x9cbc */ + volatile unsigned int BB_chan_info_chan_tab_b0[60]; /* 0x9cbc - 0x9dac */ + volatile char pad__14[0x38]; /* 0x9dac - 0x9de4 */ + volatile unsigned int BB_paprd_am2am_mask; /* 0x9de4 - 0x9de8 */ + volatile unsigned int BB_paprd_am2pm_mask; /* 0x9de8 - 0x9dec */ + volatile unsigned int BB_paprd_ht40_mask; /* 0x9dec - 0x9df0 */ + volatile unsigned int BB_paprd_ctrl0; /* 0x9df0 - 0x9df4 */ + volatile unsigned int BB_paprd_ctrl1; /* 0x9df4 - 0x9df8 */ + volatile unsigned int BB_pa_gain123; /* 0x9df8 - 0x9dfc */ + volatile unsigned int BB_pa_gain45; /* 0x9dfc - 0x9e00 */ + volatile unsigned int BB_paprd_pre_post_scale_0; /* 0x9e00 - 0x9e04 */ + volatile unsigned int BB_paprd_pre_post_scale_1; /* 0x9e04 - 0x9e08 */ + volatile unsigned int BB_paprd_pre_post_scale_2; /* 0x9e08 - 0x9e0c */ + volatile unsigned int BB_paprd_pre_post_scale_3; /* 0x9e0c - 0x9e10 */ + volatile unsigned int BB_paprd_pre_post_scale_4; /* 0x9e10 - 0x9e14 */ + volatile unsigned int BB_paprd_pre_post_scale_5; /* 0x9e14 - 0x9e18 */ + volatile unsigned int BB_paprd_pre_post_scale_6; /* 0x9e18 - 0x9e1c */ + volatile unsigned int BB_paprd_pre_post_scale_7; /* 0x9e1c - 0x9e20 */ + volatile unsigned int BB_paprd_mem_tab[120]; /* 0x9e20 - 0xa000 */ + volatile unsigned int BB_peak_det_ctrl_1; /* 0xa000 - 0xa004 */ + volatile unsigned int BB_peak_det_ctrl_2; /* 0xa004 - 0xa008 */ + volatile unsigned int BB_rx_gain_bounds_1; /* 0xa008 - 0xa00c */ + volatile unsigned int BB_rx_gain_bounds_2; /* 0xa00c - 0xa010 */ + volatile unsigned int BB_peak_det_cal_ctrl; /* 0xa010 - 0xa014 */ + volatile unsigned int BB_agc_dig_dc_ctrl; /* 0xa014 - 0xa018 */ + volatile unsigned int BB_agc_dig_dc_status_i_b0; /* 0xa018 - 0xa01c */ + volatile unsigned int BB_agc_dig_dc_status_q_b0; /* 0xa01c - 0xa020 */ + volatile char pad__15[0x1d4]; /* 0xa020 - 0xa1f4 */ + volatile unsigned int BB_bbb_txfir_0; /* 0xa1f4 - 0xa1f8 */ + volatile unsigned int BB_bbb_txfir_1; /* 0xa1f8 - 0xa1fc */ + volatile unsigned int BB_bbb_txfir_2; /* 0xa1fc - 0xa200 */ + volatile unsigned int BB_modes_select; /* 0xa200 - 0xa204 */ + volatile unsigned int BB_bbb_tx_ctrl; /* 0xa204 - 0xa208 */ + volatile unsigned int BB_bbb_sig_detect; /* 0xa208 - 0xa20c */ + volatile unsigned int BB_ext_atten_switch_ctl_b0; /* 0xa20c - 0xa210 */ + volatile unsigned int BB_bbb_rx_ctrl_1; /* 0xa210 - 0xa214 */ + volatile unsigned int BB_bbb_rx_ctrl_2; /* 0xa214 - 0xa218 */ + volatile unsigned int BB_bbb_rx_ctrl_3; /* 0xa218 - 0xa21c */ + volatile unsigned int BB_bbb_rx_ctrl_4; /* 0xa21c - 0xa220 */ + volatile unsigned int BB_bbb_rx_ctrl_5; /* 0xa220 - 0xa224 */ + volatile unsigned int BB_bbb_rx_ctrl_6; /* 0xa224 - 0xa228 */ + volatile unsigned int BB_bbb_dagc_ctrl; /* 0xa228 - 0xa22c */ + volatile unsigned int BB_force_clken_cck; /* 0xa22c - 0xa230 */ + volatile unsigned int BB_rx_clear_delay; /* 0xa230 - 0xa234 */ + volatile unsigned int BB_powertx_rate3; /* 0xa234 - 0xa238 */ + volatile unsigned int BB_powertx_rate4; /* 0xa238 - 0xa23c */ + volatile char pad__16[0x4]; /* 0xa23c - 0xa240 */ + volatile unsigned int BB_cck_spur_mit; /* 0xa240 - 0xa244 */ + volatile unsigned int BB_panic_watchdog_status; /* 0xa244 - 0xa248 */ + volatile unsigned int BB_panic_watchdog_ctrl_1; /* 0xa248 - 0xa24c */ + volatile unsigned int BB_panic_watchdog_ctrl_2; /* 0xa24c - 0xa250 */ + volatile unsigned int BB_iqcorr_ctrl_cck; /* 0xa250 - 0xa254 */ + volatile unsigned int BB_bluetooth_cntl; /* 0xa254 - 0xa258 */ + volatile unsigned int BB_tpc_1; /* 0xa258 - 0xa25c */ + volatile unsigned int BB_tpc_2; /* 0xa25c - 0xa260 */ + volatile unsigned int BB_tpc_3; /* 0xa260 - 0xa264 */ + volatile unsigned int BB_tpc_4_b0; /* 0xa264 - 0xa268 */ + volatile unsigned int BB_analog_swap; /* 0xa268 - 0xa26c */ + volatile unsigned int BB_tpc_5_b0; /* 0xa26c - 0xa270 */ + volatile unsigned int BB_tpc_6_b0; /* 0xa270 - 0xa274 */ + volatile unsigned int BB_tpc_7; /* 0xa274 - 0xa278 */ + volatile unsigned int BB_tpc_8; /* 0xa278 - 0xa27c */ + volatile unsigned int BB_tpc_9; /* 0xa27c - 0xa280 */ + volatile unsigned int BB_pdadc_tab_b0[32]; /* 0xa280 - 0xa300 */ + volatile unsigned int BB_cl_tab_b0[16]; /* 0xa300 - 0xa340 */ + volatile unsigned int BB_cl_map_0_b0; /* 0xa340 - 0xa344 */ + volatile unsigned int BB_cl_map_1_b0; /* 0xa344 - 0xa348 */ + volatile unsigned int BB_cl_map_2_b0; /* 0xa348 - 0xa34c */ + volatile unsigned int BB_cl_map_3_b0; /* 0xa34c - 0xa350 */ + volatile char pad__17[0x8]; /* 0xa350 - 0xa358 */ + volatile unsigned int BB_cl_cal_ctrl; /* 0xa358 - 0xa35c */ + volatile unsigned int BB_cl_map_pal_0_b0; /* 0xa35c - 0xa360 */ + volatile unsigned int BB_cl_map_pal_1_b0; /* 0xa360 - 0xa364 */ + volatile unsigned int BB_cl_map_pal_2_b0; /* 0xa364 - 0xa368 */ + volatile unsigned int BB_cl_map_pal_3_b0; /* 0xa368 - 0xa36c */ + volatile char pad__18[0x1c]; /* 0xa36c - 0xa388 */ + volatile unsigned int BB_rifs; /* 0xa388 - 0xa38c */ + volatile unsigned int BB_powertx_rate5; /* 0xa38c - 0xa390 */ + volatile unsigned int BB_powertx_rate6; /* 0xa390 - 0xa394 */ + volatile unsigned int BB_tpc_10; /* 0xa394 - 0xa398 */ + volatile unsigned int BB_tpc_11_b0; /* 0xa398 - 0xa39c */ + volatile unsigned int BB_cal_chain_mask; /* 0xa39c - 0xa3a0 */ + volatile char pad__19[0x1c]; /* 0xa3a0 - 0xa3bc */ + volatile unsigned int BB_powertx_sub; /* 0xa3bc - 0xa3c0 */ + volatile unsigned int BB_powertx_rate7; /* 0xa3c0 - 0xa3c4 */ + volatile unsigned int BB_powertx_rate8; /* 0xa3c4 - 0xa3c8 */ + volatile unsigned int BB_powertx_rate9; /* 0xa3c8 - 0xa3cc */ + volatile unsigned int BB_powertx_rate10; /* 0xa3cc - 0xa3d0 */ + volatile unsigned int BB_powertx_rate11; /* 0xa3d0 - 0xa3d4 */ + volatile unsigned int BB_powertx_rate12; /* 0xa3d4 - 0xa3d8 */ + volatile unsigned int BB_force_analog; /* 0xa3d8 - 0xa3dc */ + volatile unsigned int BB_tpc_12; /* 0xa3dc - 0xa3e0 */ + volatile unsigned int BB_tpc_13; /* 0xa3e0 - 0xa3e4 */ + volatile unsigned int BB_tpc_14; /* 0xa3e4 - 0xa3e8 */ + volatile unsigned int BB_tpc_15; /* 0xa3e8 - 0xa3ec */ + volatile unsigned int BB_tpc_16; /* 0xa3ec - 0xa3f0 */ + volatile unsigned int BB_tpc_17; /* 0xa3f0 - 0xa3f4 */ + volatile unsigned int BB_tpc_18; /* 0xa3f4 - 0xa3f8 */ + volatile unsigned int BB_tpc_19; /* 0xa3f8 - 0xa3fc */ + volatile unsigned int BB_tpc_20; /* 0xa3fc - 0xa400 */ + volatile unsigned int BB_tx_gain_tab_1; /* 0xa400 - 0xa404 */ + volatile unsigned int BB_tx_gain_tab_2; /* 0xa404 - 0xa408 */ + volatile unsigned int BB_tx_gain_tab_3; /* 0xa408 - 0xa40c */ + volatile unsigned int BB_tx_gain_tab_4; /* 0xa40c - 0xa410 */ + volatile unsigned int BB_tx_gain_tab_5; /* 0xa410 - 0xa414 */ + volatile unsigned int BB_tx_gain_tab_6; /* 0xa414 - 0xa418 */ + volatile unsigned int BB_tx_gain_tab_7; /* 0xa418 - 0xa41c */ + volatile unsigned int BB_tx_gain_tab_8; /* 0xa41c - 0xa420 */ + volatile unsigned int BB_tx_gain_tab_9; /* 0xa420 - 0xa424 */ + volatile unsigned int BB_tx_gain_tab_10; /* 0xa424 - 0xa428 */ + volatile unsigned int BB_tx_gain_tab_11; /* 0xa428 - 0xa42c */ + volatile unsigned int BB_tx_gain_tab_12; /* 0xa42c - 0xa430 */ + volatile unsigned int BB_tx_gain_tab_13; /* 0xa430 - 0xa434 */ + volatile unsigned int BB_tx_gain_tab_14; /* 0xa434 - 0xa438 */ + volatile unsigned int BB_tx_gain_tab_15; /* 0xa438 - 0xa43c */ + volatile unsigned int BB_tx_gain_tab_16; /* 0xa43c - 0xa440 */ + volatile unsigned int BB_tx_gain_tab_17; /* 0xa440 - 0xa444 */ + volatile unsigned int BB_tx_gain_tab_18; /* 0xa444 - 0xa448 */ + volatile unsigned int BB_tx_gain_tab_19; /* 0xa448 - 0xa44c */ + volatile unsigned int BB_tx_gain_tab_20; /* 0xa44c - 0xa450 */ + volatile unsigned int BB_tx_gain_tab_21; /* 0xa450 - 0xa454 */ + volatile unsigned int BB_tx_gain_tab_22; /* 0xa454 - 0xa458 */ + volatile unsigned int BB_tx_gain_tab_23; /* 0xa458 - 0xa45c */ + volatile unsigned int BB_tx_gain_tab_24; /* 0xa45c - 0xa460 */ + volatile unsigned int BB_tx_gain_tab_25; /* 0xa460 - 0xa464 */ + volatile unsigned int BB_tx_gain_tab_26; /* 0xa464 - 0xa468 */ + volatile unsigned int BB_tx_gain_tab_27; /* 0xa468 - 0xa46c */ + volatile unsigned int BB_tx_gain_tab_28; /* 0xa46c - 0xa470 */ + volatile unsigned int BB_tx_gain_tab_29; /* 0xa470 - 0xa474 */ + volatile unsigned int BB_tx_gain_tab_30; /* 0xa474 - 0xa478 */ + volatile unsigned int BB_tx_gain_tab_31; /* 0xa478 - 0xa47c */ + volatile unsigned int BB_tx_gain_tab_32; /* 0xa47c - 0xa480 */ + volatile unsigned int BB_tx_gain_tab_pal_1; /* 0xa480 - 0xa484 */ + volatile unsigned int BB_tx_gain_tab_pal_2; /* 0xa484 - 0xa488 */ + volatile unsigned int BB_tx_gain_tab_pal_3; /* 0xa488 - 0xa48c */ + volatile unsigned int BB_tx_gain_tab_pal_4; /* 0xa48c - 0xa490 */ + volatile unsigned int BB_tx_gain_tab_pal_5; /* 0xa490 - 0xa494 */ + volatile unsigned int BB_tx_gain_tab_pal_6; /* 0xa494 - 0xa498 */ + volatile unsigned int BB_tx_gain_tab_pal_7; /* 0xa498 - 0xa49c */ + volatile unsigned int BB_tx_gain_tab_pal_8; /* 0xa49c - 0xa4a0 */ + volatile unsigned int BB_tx_gain_tab_pal_9; /* 0xa4a0 - 0xa4a4 */ + volatile unsigned int BB_tx_gain_tab_pal_10; /* 0xa4a4 - 0xa4a8 */ + volatile unsigned int BB_tx_gain_tab_pal_11; /* 0xa4a8 - 0xa4ac */ + volatile unsigned int BB_tx_gain_tab_pal_12; /* 0xa4ac - 0xa4b0 */ + volatile unsigned int BB_tx_gain_tab_pal_13; /* 0xa4b0 - 0xa4b4 */ + volatile unsigned int BB_tx_gain_tab_pal_14; /* 0xa4b4 - 0xa4b8 */ + volatile unsigned int BB_tx_gain_tab_pal_15; /* 0xa4b8 - 0xa4bc */ + volatile unsigned int BB_tx_gain_tab_pal_16; /* 0xa4bc - 0xa4c0 */ + volatile unsigned int BB_tx_gain_tab_pal_17; /* 0xa4c0 - 0xa4c4 */ + volatile unsigned int BB_tx_gain_tab_pal_18; /* 0xa4c4 - 0xa4c8 */ + volatile unsigned int BB_tx_gain_tab_pal_19; /* 0xa4c8 - 0xa4cc */ + volatile unsigned int BB_tx_gain_tab_pal_20; /* 0xa4cc - 0xa4d0 */ + volatile unsigned int BB_tx_gain_tab_pal_21; /* 0xa4d0 - 0xa4d4 */ + volatile unsigned int BB_tx_gain_tab_pal_22; /* 0xa4d4 - 0xa4d8 */ + volatile unsigned int BB_tx_gain_tab_pal_23; /* 0xa4d8 - 0xa4dc */ + volatile unsigned int BB_tx_gain_tab_pal_24; /* 0xa4dc - 0xa4e0 */ + volatile unsigned int BB_tx_gain_tab_pal_25; /* 0xa4e0 - 0xa4e4 */ + volatile unsigned int BB_tx_gain_tab_pal_26; /* 0xa4e4 - 0xa4e8 */ + volatile unsigned int BB_tx_gain_tab_pal_27; /* 0xa4e8 - 0xa4ec */ + volatile unsigned int BB_tx_gain_tab_pal_28; /* 0xa4ec - 0xa4f0 */ + volatile unsigned int BB_tx_gain_tab_pal_29; /* 0xa4f0 - 0xa4f4 */ + volatile unsigned int BB_tx_gain_tab_pal_30; /* 0xa4f4 - 0xa4f8 */ + volatile unsigned int BB_tx_gain_tab_pal_31; /* 0xa4f8 - 0xa4fc */ + volatile unsigned int BB_tx_gain_tab_pal_32; /* 0xa4fc - 0xa500 */ + volatile char pad__20[0x18]; /* 0xa500 - 0xa518 */ + volatile unsigned int BB_caltx_gain_set_0; /* 0xa518 - 0xa51c */ + volatile unsigned int BB_caltx_gain_set_2; /* 0xa51c - 0xa520 */ + volatile unsigned int BB_caltx_gain_set_4; /* 0xa520 - 0xa524 */ + volatile unsigned int BB_caltx_gain_set_6; /* 0xa524 - 0xa528 */ + volatile unsigned int BB_caltx_gain_set_8; /* 0xa528 - 0xa52c */ + volatile unsigned int BB_caltx_gain_set_10; /* 0xa52c - 0xa530 */ + volatile unsigned int BB_caltx_gain_set_12; /* 0xa530 - 0xa534 */ + volatile unsigned int BB_caltx_gain_set_14; /* 0xa534 - 0xa538 */ + volatile unsigned int BB_caltx_gain_set_16; /* 0xa538 - 0xa53c */ + volatile unsigned int BB_caltx_gain_set_18; /* 0xa53c - 0xa540 */ + volatile unsigned int BB_caltx_gain_set_20; /* 0xa540 - 0xa544 */ + volatile unsigned int BB_caltx_gain_set_22; /* 0xa544 - 0xa548 */ + volatile unsigned int BB_caltx_gain_set_24; /* 0xa548 - 0xa54c */ + volatile unsigned int BB_caltx_gain_set_26; /* 0xa54c - 0xa550 */ + volatile unsigned int BB_caltx_gain_set_28; /* 0xa550 - 0xa554 */ + volatile unsigned int BB_caltx_gain_set_30; /* 0xa554 - 0xa558 */ + volatile unsigned int BB_txiqcal_meas_b0[96]; /* 0xa558 - 0xa6d8 */ + volatile unsigned int BB_txiqcal_start; /* 0xa6d8 - 0xa6dc */ + volatile unsigned int BB_txiqcal_control_0; /* 0xa6dc - 0xa6e0 */ + volatile unsigned int BB_txiqcal_control_1; /* 0xa6e0 - 0xa6e4 */ + volatile unsigned int BB_txiqcal_control_2; /* 0xa6e4 - 0xa6e8 */ + volatile unsigned int BB_txiqcal_control_3; /* 0xa6e8 - 0xa6ec */ + volatile unsigned int BB_txiq_corr_coeff_01_b0; /* 0xa6ec - 0xa6f0 */ + volatile unsigned int BB_txiq_corr_coeff_23_b0; /* 0xa6f0 - 0xa6f4 */ + volatile unsigned int BB_txiq_corr_coeff_45_b0; /* 0xa6f4 - 0xa6f8 */ + volatile unsigned int BB_txiq_corr_coeff_67_b0; /* 0xa6f8 - 0xa6fc */ + volatile unsigned int BB_txiq_corr_coeff_89_b0; /* 0xa6fc - 0xa700 */ + volatile unsigned int BB_txiq_corr_coeff_ab_b0; /* 0xa700 - 0xa704 */ + volatile unsigned int BB_txiq_corr_coeff_cd_b0; /* 0xa704 - 0xa708 */ + volatile unsigned int BB_txiq_corr_coeff_ef_b0; /* 0xa708 - 0xa70c */ + volatile unsigned int BB_cal_rxbb_gain_tbl_0; /* 0xa70c - 0xa710 */ + volatile unsigned int BB_cal_rxbb_gain_tbl_4; /* 0xa710 - 0xa714 */ + volatile unsigned int BB_cal_rxbb_gain_tbl_8; /* 0xa714 - 0xa718 */ + volatile unsigned int BB_cal_rxbb_gain_tbl_12; /* 0xa718 - 0xa71c */ + volatile unsigned int BB_cal_rxbb_gain_tbl_16; /* 0xa71c - 0xa720 */ + volatile unsigned int BB_cal_rxbb_gain_tbl_20; /* 0xa720 - 0xa724 */ + volatile unsigned int BB_cal_rxbb_gain_tbl_24; /* 0xa724 - 0xa728 */ + volatile unsigned int BB_txiqcal_status_b0; /* 0xa728 - 0xa72c */ + volatile unsigned int BB_paprd_trainer_cntl1; /* 0xa72c - 0xa730 */ + volatile unsigned int BB_paprd_trainer_cntl2; /* 0xa730 - 0xa734 */ + volatile unsigned int BB_paprd_trainer_cntl3; /* 0xa734 - 0xa738 */ + volatile unsigned int BB_paprd_trainer_cntl4; /* 0xa738 - 0xa73c */ + volatile unsigned int BB_paprd_trainer_stat1; /* 0xa73c - 0xa740 */ + volatile unsigned int BB_paprd_trainer_stat2; /* 0xa740 - 0xa744 */ + volatile unsigned int BB_paprd_trainer_stat3; /* 0xa744 - 0xa748 */ + volatile char pad__21[0x90]; /* 0xa748 - 0xa7d8 */ + volatile unsigned int BB_fcal_1; /* 0xa7d8 - 0xa7dc */ + volatile unsigned int BB_fcal_2_b0; /* 0xa7dc - 0xa7e0 */ + volatile unsigned int BB_radar_bw_filter; /* 0xa7e0 - 0xa7e4 */ + volatile unsigned int BB_dft_tone_ctrl_b0; /* 0xa7e4 - 0xa7e8 */ + volatile unsigned int BB_therm_adc_1; /* 0xa7e8 - 0xa7ec */ + volatile unsigned int BB_therm_adc_2; /* 0xa7ec - 0xa7f0 */ + volatile unsigned int BB_therm_adc_3; /* 0xa7f0 - 0xa7f4 */ + volatile unsigned int BB_therm_adc_4; /* 0xa7f4 - 0xa7f8 */ + volatile unsigned int BB_tx_forced_gain; /* 0xa7f8 - 0xa7fc */ + volatile unsigned int BB_eco_ctrl; /* 0xa7fc - 0xa800 */ + volatile char pad__22[0x48]; /* 0xa800 - 0xa848 */ + volatile unsigned int BB_gain_force_max_gains_b1; /* 0xa848 - 0xa84c */ + volatile unsigned int BB_gains_min_offsets_b1; /* 0xa84c - 0xa850 */ + volatile char pad__23[0x1b0]; /* 0xa850 - 0xaa00 */ + volatile unsigned int BB_rx_ocgain2[128]; /* 0xaa00 - 0xac00 */ + volatile char pad__24[0x60c]; /* 0xac00 - 0xb20c */ + volatile unsigned int BB_ext_atten_switch_ctl_b1; /* 0xb20c - 0xb210 */ +} bb_lc_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _BB_LC_REG_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/efuse_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/efuse_reg.h new file mode 100644 index 000000000000..12cadb337482 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/efuse_reg.h @@ -0,0 +1,108 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _EFUSE_REG_REG_H_ +#define _EFUSE_REG_REG_H_ + +#define EFUSE_WR_ENABLE_REG_ADDRESS 0x00000000 +#define EFUSE_WR_ENABLE_REG_OFFSET 0x00000000 +#define EFUSE_WR_ENABLE_REG_V_MSB 0 +#define EFUSE_WR_ENABLE_REG_V_LSB 0 +#define EFUSE_WR_ENABLE_REG_V_MASK 0x00000001 +#define EFUSE_WR_ENABLE_REG_V_GET(x) (((x) & EFUSE_WR_ENABLE_REG_V_MASK) >> EFUSE_WR_ENABLE_REG_V_LSB) +#define EFUSE_WR_ENABLE_REG_V_SET(x) (((x) << EFUSE_WR_ENABLE_REG_V_LSB) & EFUSE_WR_ENABLE_REG_V_MASK) + +#define EFUSE_INT_ENABLE_REG_ADDRESS 0x00000004 +#define EFUSE_INT_ENABLE_REG_OFFSET 0x00000004 +#define EFUSE_INT_ENABLE_REG_V_MSB 0 +#define EFUSE_INT_ENABLE_REG_V_LSB 0 +#define EFUSE_INT_ENABLE_REG_V_MASK 0x00000001 +#define EFUSE_INT_ENABLE_REG_V_GET(x) (((x) & EFUSE_INT_ENABLE_REG_V_MASK) >> EFUSE_INT_ENABLE_REG_V_LSB) +#define EFUSE_INT_ENABLE_REG_V_SET(x) (((x) << EFUSE_INT_ENABLE_REG_V_LSB) & EFUSE_INT_ENABLE_REG_V_MASK) + +#define EFUSE_INT_STATUS_REG_ADDRESS 0x00000008 +#define EFUSE_INT_STATUS_REG_OFFSET 0x00000008 +#define EFUSE_INT_STATUS_REG_V_MSB 0 +#define EFUSE_INT_STATUS_REG_V_LSB 0 +#define EFUSE_INT_STATUS_REG_V_MASK 0x00000001 +#define EFUSE_INT_STATUS_REG_V_GET(x) (((x) & EFUSE_INT_STATUS_REG_V_MASK) >> EFUSE_INT_STATUS_REG_V_LSB) +#define EFUSE_INT_STATUS_REG_V_SET(x) (((x) << EFUSE_INT_STATUS_REG_V_LSB) & EFUSE_INT_STATUS_REG_V_MASK) + +#define BITMASK_WR_REG_ADDRESS 0x0000000c +#define BITMASK_WR_REG_OFFSET 0x0000000c +#define BITMASK_WR_REG_V_MSB 31 +#define BITMASK_WR_REG_V_LSB 0 +#define BITMASK_WR_REG_V_MASK 0xffffffff +#define BITMASK_WR_REG_V_GET(x) (((x) & BITMASK_WR_REG_V_MASK) >> BITMASK_WR_REG_V_LSB) +#define BITMASK_WR_REG_V_SET(x) (((x) << BITMASK_WR_REG_V_LSB) & BITMASK_WR_REG_V_MASK) + +#define VDDQ_SETTLE_TIME_REG_ADDRESS 0x00000010 +#define VDDQ_SETTLE_TIME_REG_OFFSET 0x00000010 +#define VDDQ_SETTLE_TIME_REG_V_MSB 31 +#define VDDQ_SETTLE_TIME_REG_V_LSB 0 +#define VDDQ_SETTLE_TIME_REG_V_MASK 0xffffffff +#define VDDQ_SETTLE_TIME_REG_V_GET(x) (((x) & VDDQ_SETTLE_TIME_REG_V_MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB) +#define VDDQ_SETTLE_TIME_REG_V_SET(x) (((x) << VDDQ_SETTLE_TIME_REG_V_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK) + +#define RD_STROBE_PW_REG_ADDRESS 0x00000014 +#define RD_STROBE_PW_REG_OFFSET 0x00000014 +#define RD_STROBE_PW_REG_V_MSB 31 +#define RD_STROBE_PW_REG_V_LSB 0 +#define RD_STROBE_PW_REG_V_MASK 0xffffffff +#define RD_STROBE_PW_REG_V_GET(x) (((x) & RD_STROBE_PW_REG_V_MASK) >> RD_STROBE_PW_REG_V_LSB) +#define RD_STROBE_PW_REG_V_SET(x) (((x) << RD_STROBE_PW_REG_V_LSB) & RD_STROBE_PW_REG_V_MASK) + +#define PG_STROBE_PW_REG_ADDRESS 0x00000018 +#define PG_STROBE_PW_REG_OFFSET 0x00000018 +#define PG_STROBE_PW_REG_V_MSB 31 +#define PG_STROBE_PW_REG_V_LSB 0 +#define PG_STROBE_PW_REG_V_MASK 0xffffffff +#define PG_STROBE_PW_REG_V_GET(x) (((x) & PG_STROBE_PW_REG_V_MASK) >> PG_STROBE_PW_REG_V_LSB) +#define PG_STROBE_PW_REG_V_SET(x) (((x) << PG_STROBE_PW_REG_V_LSB) & PG_STROBE_PW_REG_V_MASK) + +#define EFUSE_INTF_ADDRESS 0x00000800 +#define EFUSE_INTF_OFFSET 0x00000800 +#define EFUSE_INTF_R_MSB 31 +#define EFUSE_INTF_R_LSB 0 +#define EFUSE_INTF_R_MASK 0xffffffff +#define EFUSE_INTF_R_GET(x) (((x) & EFUSE_INTF_R_MASK) >> EFUSE_INTF_R_LSB) +#define EFUSE_INTF_R_SET(x) (((x) << EFUSE_INTF_R_LSB) & EFUSE_INTF_R_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct efuse_reg_reg_s { + volatile unsigned int efuse_wr_enable_reg; + volatile unsigned int efuse_int_enable_reg; + volatile unsigned int efuse_int_status_reg; + volatile unsigned int bitmask_wr_reg; + volatile unsigned int vddq_settle_time_reg; + volatile unsigned int rd_strobe_pw_reg; + volatile unsigned int pg_strobe_pw_reg; + unsigned char pad0[2020]; /* pad to 0x800 */ + volatile unsigned int efuse_intf[512]; +} efuse_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _EFUSE_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h new file mode 100644 index 000000000000..1adee707de7c --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h @@ -0,0 +1,1253 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _GPIO_ATHR_WLAN_REG_REG_H_ +#define _GPIO_ATHR_WLAN_REG_REG_H_ + +#define WLAN_GPIO_OUT_ADDRESS 0x00000000 +#define WLAN_GPIO_OUT_OFFSET 0x00000000 +#define WLAN_GPIO_OUT_DATA_MSB 25 +#define WLAN_GPIO_OUT_DATA_LSB 0 +#define WLAN_GPIO_OUT_DATA_MASK 0x03ffffff +#define WLAN_GPIO_OUT_DATA_GET(x) (((x) & WLAN_GPIO_OUT_DATA_MASK) >> WLAN_GPIO_OUT_DATA_LSB) +#define WLAN_GPIO_OUT_DATA_SET(x) (((x) << WLAN_GPIO_OUT_DATA_LSB) & WLAN_GPIO_OUT_DATA_MASK) + +#define WLAN_GPIO_OUT_W1TS_ADDRESS 0x00000004 +#define WLAN_GPIO_OUT_W1TS_OFFSET 0x00000004 +#define WLAN_GPIO_OUT_W1TS_DATA_MSB 25 +#define WLAN_GPIO_OUT_W1TS_DATA_LSB 0 +#define WLAN_GPIO_OUT_W1TS_DATA_MASK 0x03ffffff +#define WLAN_GPIO_OUT_W1TS_DATA_GET(x) (((x) & WLAN_GPIO_OUT_W1TS_DATA_MASK) >> WLAN_GPIO_OUT_W1TS_DATA_LSB) +#define WLAN_GPIO_OUT_W1TS_DATA_SET(x) (((x) << WLAN_GPIO_OUT_W1TS_DATA_LSB) & WLAN_GPIO_OUT_W1TS_DATA_MASK) + +#define WLAN_GPIO_OUT_W1TC_ADDRESS 0x00000008 +#define WLAN_GPIO_OUT_W1TC_OFFSET 0x00000008 +#define WLAN_GPIO_OUT_W1TC_DATA_MSB 25 +#define WLAN_GPIO_OUT_W1TC_DATA_LSB 0 +#define WLAN_GPIO_OUT_W1TC_DATA_MASK 0x03ffffff +#define WLAN_GPIO_OUT_W1TC_DATA_GET(x) (((x) & WLAN_GPIO_OUT_W1TC_DATA_MASK) >> WLAN_GPIO_OUT_W1TC_DATA_LSB) +#define WLAN_GPIO_OUT_W1TC_DATA_SET(x) (((x) << WLAN_GPIO_OUT_W1TC_DATA_LSB) & WLAN_GPIO_OUT_W1TC_DATA_MASK) + +#define WLAN_GPIO_ENABLE_ADDRESS 0x0000000c +#define WLAN_GPIO_ENABLE_OFFSET 0x0000000c +#define WLAN_GPIO_ENABLE_DATA_MSB 25 +#define WLAN_GPIO_ENABLE_DATA_LSB 0 +#define WLAN_GPIO_ENABLE_DATA_MASK 0x03ffffff +#define WLAN_GPIO_ENABLE_DATA_GET(x) (((x) & WLAN_GPIO_ENABLE_DATA_MASK) >> WLAN_GPIO_ENABLE_DATA_LSB) +#define WLAN_GPIO_ENABLE_DATA_SET(x) (((x) << WLAN_GPIO_ENABLE_DATA_LSB) & WLAN_GPIO_ENABLE_DATA_MASK) + +#define WLAN_GPIO_ENABLE_W1TS_ADDRESS 0x00000010 +#define WLAN_GPIO_ENABLE_W1TS_OFFSET 0x00000010 +#define WLAN_GPIO_ENABLE_W1TS_DATA_MSB 25 +#define WLAN_GPIO_ENABLE_W1TS_DATA_LSB 0 +#define WLAN_GPIO_ENABLE_W1TS_DATA_MASK 0x03ffffff +#define WLAN_GPIO_ENABLE_W1TS_DATA_GET(x) (((x) & WLAN_GPIO_ENABLE_W1TS_DATA_MASK) >> WLAN_GPIO_ENABLE_W1TS_DATA_LSB) +#define WLAN_GPIO_ENABLE_W1TS_DATA_SET(x) (((x) << WLAN_GPIO_ENABLE_W1TS_DATA_LSB) & WLAN_GPIO_ENABLE_W1TS_DATA_MASK) + +#define WLAN_GPIO_ENABLE_W1TC_ADDRESS 0x00000014 +#define WLAN_GPIO_ENABLE_W1TC_OFFSET 0x00000014 +#define WLAN_GPIO_ENABLE_W1TC_DATA_MSB 25 +#define WLAN_GPIO_ENABLE_W1TC_DATA_LSB 0 +#define WLAN_GPIO_ENABLE_W1TC_DATA_MASK 0x03ffffff +#define WLAN_GPIO_ENABLE_W1TC_DATA_GET(x) (((x) & WLAN_GPIO_ENABLE_W1TC_DATA_MASK) >> WLAN_GPIO_ENABLE_W1TC_DATA_LSB) +#define WLAN_GPIO_ENABLE_W1TC_DATA_SET(x) (((x) << WLAN_GPIO_ENABLE_W1TC_DATA_LSB) & WLAN_GPIO_ENABLE_W1TC_DATA_MASK) + +#define WLAN_GPIO_IN_ADDRESS 0x00000018 +#define WLAN_GPIO_IN_OFFSET 0x00000018 +#define WLAN_GPIO_IN_DATA_MSB 25 +#define WLAN_GPIO_IN_DATA_LSB 0 +#define WLAN_GPIO_IN_DATA_MASK 0x03ffffff +#define WLAN_GPIO_IN_DATA_GET(x) (((x) & WLAN_GPIO_IN_DATA_MASK) >> WLAN_GPIO_IN_DATA_LSB) +#define WLAN_GPIO_IN_DATA_SET(x) (((x) << WLAN_GPIO_IN_DATA_LSB) & WLAN_GPIO_IN_DATA_MASK) + +#define WLAN_GPIO_STATUS_ADDRESS 0x0000001c +#define WLAN_GPIO_STATUS_OFFSET 0x0000001c +#define WLAN_GPIO_STATUS_INTERRUPT_MSB 25 +#define WLAN_GPIO_STATUS_INTERRUPT_LSB 0 +#define WLAN_GPIO_STATUS_INTERRUPT_MASK 0x03ffffff +#define WLAN_GPIO_STATUS_INTERRUPT_GET(x) (((x) & WLAN_GPIO_STATUS_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_INTERRUPT_LSB) +#define WLAN_GPIO_STATUS_INTERRUPT_SET(x) (((x) << WLAN_GPIO_STATUS_INTERRUPT_LSB) & WLAN_GPIO_STATUS_INTERRUPT_MASK) + +#define WLAN_GPIO_STATUS_W1TS_ADDRESS 0x00000020 +#define WLAN_GPIO_STATUS_W1TS_OFFSET 0x00000020 +#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_MSB 25 +#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB 0 +#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK 0x03ffffff +#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_GET(x) (((x) & WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB) +#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_SET(x) (((x) << WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB) & WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK) + +#define WLAN_GPIO_STATUS_W1TC_ADDRESS 0x00000024 +#define WLAN_GPIO_STATUS_W1TC_OFFSET 0x00000024 +#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_MSB 25 +#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB 0 +#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK 0x03ffffff +#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_GET(x) (((x) & WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB) +#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_SET(x) (((x) << WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB) & WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK) + +#define WLAN_GPIO_PIN0_ADDRESS 0x00000028 +#define WLAN_GPIO_PIN0_OFFSET 0x00000028 +#define WLAN_GPIO_PIN0_CONFIG_MSB 13 +#define WLAN_GPIO_PIN0_CONFIG_LSB 11 +#define WLAN_GPIO_PIN0_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN0_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN0_CONFIG_MASK) >> WLAN_GPIO_PIN0_CONFIG_LSB) +#define WLAN_GPIO_PIN0_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN0_CONFIG_LSB) & WLAN_GPIO_PIN0_CONFIG_MASK) +#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN0_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN0_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN0_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN0_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN0_INT_TYPE_MASK) >> WLAN_GPIO_PIN0_INT_TYPE_LSB) +#define WLAN_GPIO_PIN0_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN0_INT_TYPE_LSB) & WLAN_GPIO_PIN0_INT_TYPE_MASK) +#define WLAN_GPIO_PIN0_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN0_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN0_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN0_PAD_PULL_MASK) >> WLAN_GPIO_PIN0_PAD_PULL_LSB) +#define WLAN_GPIO_PIN0_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN0_PAD_PULL_LSB) & WLAN_GPIO_PIN0_PAD_PULL_MASK) +#define WLAN_GPIO_PIN0_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN0_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN0_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN0_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN0_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN0_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN0_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN0_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN0_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN0_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN0_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN0_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN0_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN0_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN0_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN0_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN0_PAD_DRIVER_LSB) & WLAN_GPIO_PIN0_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN0_SOURCE_MSB 0 +#define WLAN_GPIO_PIN0_SOURCE_LSB 0 +#define WLAN_GPIO_PIN0_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN0_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN0_SOURCE_MASK) >> WLAN_GPIO_PIN0_SOURCE_LSB) +#define WLAN_GPIO_PIN0_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN0_SOURCE_LSB) & WLAN_GPIO_PIN0_SOURCE_MASK) + +#define WLAN_GPIO_PIN1_ADDRESS 0x0000002c +#define WLAN_GPIO_PIN1_OFFSET 0x0000002c +#define WLAN_GPIO_PIN1_CONFIG_MSB 13 +#define WLAN_GPIO_PIN1_CONFIG_LSB 11 +#define WLAN_GPIO_PIN1_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN1_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN1_CONFIG_MASK) >> WLAN_GPIO_PIN1_CONFIG_LSB) +#define WLAN_GPIO_PIN1_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN1_CONFIG_LSB) & WLAN_GPIO_PIN1_CONFIG_MASK) +#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN1_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN1_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN1_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN1_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN1_INT_TYPE_MASK) >> WLAN_GPIO_PIN1_INT_TYPE_LSB) +#define WLAN_GPIO_PIN1_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN1_INT_TYPE_LSB) & WLAN_GPIO_PIN1_INT_TYPE_MASK) +#define WLAN_GPIO_PIN1_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN1_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN1_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN1_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN1_PAD_PULL_MASK) >> WLAN_GPIO_PIN1_PAD_PULL_LSB) +#define WLAN_GPIO_PIN1_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN1_PAD_PULL_LSB) & WLAN_GPIO_PIN1_PAD_PULL_MASK) +#define WLAN_GPIO_PIN1_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN1_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN1_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN1_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN1_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN1_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN1_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN1_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN1_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN1_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN1_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN1_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN1_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN1_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN1_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN1_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN1_PAD_DRIVER_LSB) & WLAN_GPIO_PIN1_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN1_SOURCE_MSB 0 +#define WLAN_GPIO_PIN1_SOURCE_LSB 0 +#define WLAN_GPIO_PIN1_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN1_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN1_SOURCE_MASK) >> WLAN_GPIO_PIN1_SOURCE_LSB) +#define WLAN_GPIO_PIN1_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN1_SOURCE_LSB) & WLAN_GPIO_PIN1_SOURCE_MASK) + +#define WLAN_GPIO_PIN2_ADDRESS 0x00000030 +#define WLAN_GPIO_PIN2_OFFSET 0x00000030 +#define WLAN_GPIO_PIN2_CONFIG_MSB 13 +#define WLAN_GPIO_PIN2_CONFIG_LSB 11 +#define WLAN_GPIO_PIN2_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN2_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN2_CONFIG_MASK) >> WLAN_GPIO_PIN2_CONFIG_LSB) +#define WLAN_GPIO_PIN2_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN2_CONFIG_LSB) & WLAN_GPIO_PIN2_CONFIG_MASK) +#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN2_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN2_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN2_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN2_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN2_INT_TYPE_MASK) >> WLAN_GPIO_PIN2_INT_TYPE_LSB) +#define WLAN_GPIO_PIN2_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN2_INT_TYPE_LSB) & WLAN_GPIO_PIN2_INT_TYPE_MASK) +#define WLAN_GPIO_PIN2_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN2_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN2_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN2_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN2_PAD_PULL_MASK) >> WLAN_GPIO_PIN2_PAD_PULL_LSB) +#define WLAN_GPIO_PIN2_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN2_PAD_PULL_LSB) & WLAN_GPIO_PIN2_PAD_PULL_MASK) +#define WLAN_GPIO_PIN2_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN2_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN2_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN2_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN2_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN2_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN2_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN2_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN2_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN2_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN2_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN2_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN2_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN2_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN2_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN2_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN2_PAD_DRIVER_LSB) & WLAN_GPIO_PIN2_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN2_SOURCE_MSB 0 +#define WLAN_GPIO_PIN2_SOURCE_LSB 0 +#define WLAN_GPIO_PIN2_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN2_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN2_SOURCE_MASK) >> WLAN_GPIO_PIN2_SOURCE_LSB) +#define WLAN_GPIO_PIN2_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN2_SOURCE_LSB) & WLAN_GPIO_PIN2_SOURCE_MASK) + +#define WLAN_GPIO_PIN3_ADDRESS 0x00000034 +#define WLAN_GPIO_PIN3_OFFSET 0x00000034 +#define WLAN_GPIO_PIN3_CONFIG_MSB 13 +#define WLAN_GPIO_PIN3_CONFIG_LSB 11 +#define WLAN_GPIO_PIN3_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN3_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN3_CONFIG_MASK) >> WLAN_GPIO_PIN3_CONFIG_LSB) +#define WLAN_GPIO_PIN3_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN3_CONFIG_LSB) & WLAN_GPIO_PIN3_CONFIG_MASK) +#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN3_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN3_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN3_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN3_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN3_INT_TYPE_MASK) >> WLAN_GPIO_PIN3_INT_TYPE_LSB) +#define WLAN_GPIO_PIN3_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN3_INT_TYPE_LSB) & WLAN_GPIO_PIN3_INT_TYPE_MASK) +#define WLAN_GPIO_PIN3_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN3_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN3_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN3_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN3_PAD_PULL_MASK) >> WLAN_GPIO_PIN3_PAD_PULL_LSB) +#define WLAN_GPIO_PIN3_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN3_PAD_PULL_LSB) & WLAN_GPIO_PIN3_PAD_PULL_MASK) +#define WLAN_GPIO_PIN3_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN3_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN3_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN3_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN3_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN3_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN3_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN3_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN3_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN3_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN3_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN3_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN3_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN3_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN3_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN3_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN3_PAD_DRIVER_LSB) & WLAN_GPIO_PIN3_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN3_SOURCE_MSB 0 +#define WLAN_GPIO_PIN3_SOURCE_LSB 0 +#define WLAN_GPIO_PIN3_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN3_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN3_SOURCE_MASK) >> WLAN_GPIO_PIN3_SOURCE_LSB) +#define WLAN_GPIO_PIN3_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN3_SOURCE_LSB) & WLAN_GPIO_PIN3_SOURCE_MASK) + +#define WLAN_GPIO_PIN4_ADDRESS 0x00000038 +#define WLAN_GPIO_PIN4_OFFSET 0x00000038 +#define WLAN_GPIO_PIN4_CONFIG_MSB 13 +#define WLAN_GPIO_PIN4_CONFIG_LSB 11 +#define WLAN_GPIO_PIN4_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN4_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN4_CONFIG_MASK) >> WLAN_GPIO_PIN4_CONFIG_LSB) +#define WLAN_GPIO_PIN4_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN4_CONFIG_LSB) & WLAN_GPIO_PIN4_CONFIG_MASK) +#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN4_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN4_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN4_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN4_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN4_INT_TYPE_MASK) >> WLAN_GPIO_PIN4_INT_TYPE_LSB) +#define WLAN_GPIO_PIN4_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN4_INT_TYPE_LSB) & WLAN_GPIO_PIN4_INT_TYPE_MASK) +#define WLAN_GPIO_PIN4_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN4_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN4_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN4_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN4_PAD_PULL_MASK) >> WLAN_GPIO_PIN4_PAD_PULL_LSB) +#define WLAN_GPIO_PIN4_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN4_PAD_PULL_LSB) & WLAN_GPIO_PIN4_PAD_PULL_MASK) +#define WLAN_GPIO_PIN4_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN4_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN4_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN4_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN4_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN4_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN4_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN4_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN4_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN4_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN4_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN4_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN4_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN4_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN4_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN4_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN4_PAD_DRIVER_LSB) & WLAN_GPIO_PIN4_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN4_SOURCE_MSB 0 +#define WLAN_GPIO_PIN4_SOURCE_LSB 0 +#define WLAN_GPIO_PIN4_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN4_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN4_SOURCE_MASK) >> WLAN_GPIO_PIN4_SOURCE_LSB) +#define WLAN_GPIO_PIN4_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN4_SOURCE_LSB) & WLAN_GPIO_PIN4_SOURCE_MASK) + +#define WLAN_GPIO_PIN5_ADDRESS 0x0000003c +#define WLAN_GPIO_PIN5_OFFSET 0x0000003c +#define WLAN_GPIO_PIN5_CONFIG_MSB 13 +#define WLAN_GPIO_PIN5_CONFIG_LSB 11 +#define WLAN_GPIO_PIN5_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN5_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN5_CONFIG_MASK) >> WLAN_GPIO_PIN5_CONFIG_LSB) +#define WLAN_GPIO_PIN5_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN5_CONFIG_LSB) & WLAN_GPIO_PIN5_CONFIG_MASK) +#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN5_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN5_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN5_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN5_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN5_INT_TYPE_MASK) >> WLAN_GPIO_PIN5_INT_TYPE_LSB) +#define WLAN_GPIO_PIN5_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN5_INT_TYPE_LSB) & WLAN_GPIO_PIN5_INT_TYPE_MASK) +#define WLAN_GPIO_PIN5_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN5_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN5_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN5_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN5_PAD_PULL_MASK) >> WLAN_GPIO_PIN5_PAD_PULL_LSB) +#define WLAN_GPIO_PIN5_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN5_PAD_PULL_LSB) & WLAN_GPIO_PIN5_PAD_PULL_MASK) +#define WLAN_GPIO_PIN5_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN5_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN5_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN5_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN5_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN5_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN5_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN5_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN5_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN5_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN5_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN5_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN5_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN5_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN5_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN5_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN5_PAD_DRIVER_LSB) & WLAN_GPIO_PIN5_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN5_SOURCE_MSB 0 +#define WLAN_GPIO_PIN5_SOURCE_LSB 0 +#define WLAN_GPIO_PIN5_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN5_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN5_SOURCE_MASK) >> WLAN_GPIO_PIN5_SOURCE_LSB) +#define WLAN_GPIO_PIN5_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN5_SOURCE_LSB) & WLAN_GPIO_PIN5_SOURCE_MASK) + +#define WLAN_GPIO_PIN6_ADDRESS 0x00000040 +#define WLAN_GPIO_PIN6_OFFSET 0x00000040 +#define WLAN_GPIO_PIN6_CONFIG_MSB 13 +#define WLAN_GPIO_PIN6_CONFIG_LSB 11 +#define WLAN_GPIO_PIN6_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN6_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN6_CONFIG_MASK) >> WLAN_GPIO_PIN6_CONFIG_LSB) +#define WLAN_GPIO_PIN6_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN6_CONFIG_LSB) & WLAN_GPIO_PIN6_CONFIG_MASK) +#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN6_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN6_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN6_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN6_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN6_INT_TYPE_MASK) >> WLAN_GPIO_PIN6_INT_TYPE_LSB) +#define WLAN_GPIO_PIN6_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN6_INT_TYPE_LSB) & WLAN_GPIO_PIN6_INT_TYPE_MASK) +#define WLAN_GPIO_PIN6_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN6_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN6_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN6_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN6_PAD_PULL_MASK) >> WLAN_GPIO_PIN6_PAD_PULL_LSB) +#define WLAN_GPIO_PIN6_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN6_PAD_PULL_LSB) & WLAN_GPIO_PIN6_PAD_PULL_MASK) +#define WLAN_GPIO_PIN6_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN6_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN6_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN6_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN6_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN6_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN6_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN6_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN6_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN6_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN6_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN6_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN6_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN6_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN6_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN6_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN6_PAD_DRIVER_LSB) & WLAN_GPIO_PIN6_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN6_SOURCE_MSB 0 +#define WLAN_GPIO_PIN6_SOURCE_LSB 0 +#define WLAN_GPIO_PIN6_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN6_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN6_SOURCE_MASK) >> WLAN_GPIO_PIN6_SOURCE_LSB) +#define WLAN_GPIO_PIN6_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN6_SOURCE_LSB) & WLAN_GPIO_PIN6_SOURCE_MASK) + +#define WLAN_GPIO_PIN7_ADDRESS 0x00000044 +#define WLAN_GPIO_PIN7_OFFSET 0x00000044 +#define WLAN_GPIO_PIN7_CONFIG_MSB 13 +#define WLAN_GPIO_PIN7_CONFIG_LSB 11 +#define WLAN_GPIO_PIN7_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN7_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN7_CONFIG_MASK) >> WLAN_GPIO_PIN7_CONFIG_LSB) +#define WLAN_GPIO_PIN7_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN7_CONFIG_LSB) & WLAN_GPIO_PIN7_CONFIG_MASK) +#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN7_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN7_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN7_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN7_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN7_INT_TYPE_MASK) >> WLAN_GPIO_PIN7_INT_TYPE_LSB) +#define WLAN_GPIO_PIN7_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN7_INT_TYPE_LSB) & WLAN_GPIO_PIN7_INT_TYPE_MASK) +#define WLAN_GPIO_PIN7_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN7_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN7_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN7_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN7_PAD_PULL_MASK) >> WLAN_GPIO_PIN7_PAD_PULL_LSB) +#define WLAN_GPIO_PIN7_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN7_PAD_PULL_LSB) & WLAN_GPIO_PIN7_PAD_PULL_MASK) +#define WLAN_GPIO_PIN7_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN7_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN7_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN7_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN7_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN7_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN7_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN7_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN7_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN7_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN7_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN7_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN7_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN7_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN7_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN7_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN7_PAD_DRIVER_LSB) & WLAN_GPIO_PIN7_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN7_SOURCE_MSB 0 +#define WLAN_GPIO_PIN7_SOURCE_LSB 0 +#define WLAN_GPIO_PIN7_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN7_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN7_SOURCE_MASK) >> WLAN_GPIO_PIN7_SOURCE_LSB) +#define WLAN_GPIO_PIN7_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN7_SOURCE_LSB) & WLAN_GPIO_PIN7_SOURCE_MASK) + +#define WLAN_GPIO_PIN8_ADDRESS 0x00000048 +#define WLAN_GPIO_PIN8_OFFSET 0x00000048 +#define WLAN_GPIO_PIN8_CONFIG_MSB 13 +#define WLAN_GPIO_PIN8_CONFIG_LSB 11 +#define WLAN_GPIO_PIN8_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN8_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN8_CONFIG_MASK) >> WLAN_GPIO_PIN8_CONFIG_LSB) +#define WLAN_GPIO_PIN8_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN8_CONFIG_LSB) & WLAN_GPIO_PIN8_CONFIG_MASK) +#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN8_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN8_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN8_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN8_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN8_INT_TYPE_MASK) >> WLAN_GPIO_PIN8_INT_TYPE_LSB) +#define WLAN_GPIO_PIN8_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN8_INT_TYPE_LSB) & WLAN_GPIO_PIN8_INT_TYPE_MASK) +#define WLAN_GPIO_PIN8_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN8_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN8_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN8_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN8_PAD_PULL_MASK) >> WLAN_GPIO_PIN8_PAD_PULL_LSB) +#define WLAN_GPIO_PIN8_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN8_PAD_PULL_LSB) & WLAN_GPIO_PIN8_PAD_PULL_MASK) +#define WLAN_GPIO_PIN8_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN8_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN8_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN8_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN8_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN8_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN8_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN8_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN8_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN8_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN8_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN8_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN8_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN8_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN8_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN8_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN8_PAD_DRIVER_LSB) & WLAN_GPIO_PIN8_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN8_SOURCE_MSB 0 +#define WLAN_GPIO_PIN8_SOURCE_LSB 0 +#define WLAN_GPIO_PIN8_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN8_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN8_SOURCE_MASK) >> WLAN_GPIO_PIN8_SOURCE_LSB) +#define WLAN_GPIO_PIN8_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN8_SOURCE_LSB) & WLAN_GPIO_PIN8_SOURCE_MASK) + +#define WLAN_GPIO_PIN9_ADDRESS 0x0000004c +#define WLAN_GPIO_PIN9_OFFSET 0x0000004c +#define WLAN_GPIO_PIN9_CONFIG_MSB 13 +#define WLAN_GPIO_PIN9_CONFIG_LSB 11 +#define WLAN_GPIO_PIN9_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN9_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN9_CONFIG_MASK) >> WLAN_GPIO_PIN9_CONFIG_LSB) +#define WLAN_GPIO_PIN9_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN9_CONFIG_LSB) & WLAN_GPIO_PIN9_CONFIG_MASK) +#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN9_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN9_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN9_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN9_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN9_INT_TYPE_MASK) >> WLAN_GPIO_PIN9_INT_TYPE_LSB) +#define WLAN_GPIO_PIN9_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN9_INT_TYPE_LSB) & WLAN_GPIO_PIN9_INT_TYPE_MASK) +#define WLAN_GPIO_PIN9_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN9_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN9_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN9_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN9_PAD_PULL_MASK) >> WLAN_GPIO_PIN9_PAD_PULL_LSB) +#define WLAN_GPIO_PIN9_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN9_PAD_PULL_LSB) & WLAN_GPIO_PIN9_PAD_PULL_MASK) +#define WLAN_GPIO_PIN9_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN9_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN9_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN9_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN9_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN9_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN9_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN9_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN9_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN9_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN9_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN9_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN9_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN9_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN9_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN9_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN9_PAD_DRIVER_LSB) & WLAN_GPIO_PIN9_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN9_SOURCE_MSB 0 +#define WLAN_GPIO_PIN9_SOURCE_LSB 0 +#define WLAN_GPIO_PIN9_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN9_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN9_SOURCE_MASK) >> WLAN_GPIO_PIN9_SOURCE_LSB) +#define WLAN_GPIO_PIN9_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN9_SOURCE_LSB) & WLAN_GPIO_PIN9_SOURCE_MASK) + +#define WLAN_GPIO_PIN10_ADDRESS 0x00000050 +#define WLAN_GPIO_PIN10_OFFSET 0x00000050 +#define WLAN_GPIO_PIN10_CONFIG_MSB 13 +#define WLAN_GPIO_PIN10_CONFIG_LSB 11 +#define WLAN_GPIO_PIN10_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN10_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN10_CONFIG_MASK) >> WLAN_GPIO_PIN10_CONFIG_LSB) +#define WLAN_GPIO_PIN10_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN10_CONFIG_LSB) & WLAN_GPIO_PIN10_CONFIG_MASK) +#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN10_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN10_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN10_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN10_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN10_INT_TYPE_MASK) >> WLAN_GPIO_PIN10_INT_TYPE_LSB) +#define WLAN_GPIO_PIN10_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN10_INT_TYPE_LSB) & WLAN_GPIO_PIN10_INT_TYPE_MASK) +#define WLAN_GPIO_PIN10_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN10_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN10_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN10_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN10_PAD_PULL_MASK) >> WLAN_GPIO_PIN10_PAD_PULL_LSB) +#define WLAN_GPIO_PIN10_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN10_PAD_PULL_LSB) & WLAN_GPIO_PIN10_PAD_PULL_MASK) +#define WLAN_GPIO_PIN10_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN10_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN10_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN10_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN10_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN10_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN10_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN10_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN10_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN10_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN10_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN10_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN10_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN10_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN10_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN10_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN10_PAD_DRIVER_LSB) & WLAN_GPIO_PIN10_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN10_SOURCE_MSB 0 +#define WLAN_GPIO_PIN10_SOURCE_LSB 0 +#define WLAN_GPIO_PIN10_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN10_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN10_SOURCE_MASK) >> WLAN_GPIO_PIN10_SOURCE_LSB) +#define WLAN_GPIO_PIN10_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN10_SOURCE_LSB) & WLAN_GPIO_PIN10_SOURCE_MASK) + +#define WLAN_GPIO_PIN11_ADDRESS 0x00000054 +#define WLAN_GPIO_PIN11_OFFSET 0x00000054 +#define WLAN_GPIO_PIN11_CONFIG_MSB 13 +#define WLAN_GPIO_PIN11_CONFIG_LSB 11 +#define WLAN_GPIO_PIN11_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN11_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN11_CONFIG_MASK) >> WLAN_GPIO_PIN11_CONFIG_LSB) +#define WLAN_GPIO_PIN11_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN11_CONFIG_LSB) & WLAN_GPIO_PIN11_CONFIG_MASK) +#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN11_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN11_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN11_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN11_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN11_INT_TYPE_MASK) >> WLAN_GPIO_PIN11_INT_TYPE_LSB) +#define WLAN_GPIO_PIN11_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN11_INT_TYPE_LSB) & WLAN_GPIO_PIN11_INT_TYPE_MASK) +#define WLAN_GPIO_PIN11_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN11_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN11_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN11_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN11_PAD_PULL_MASK) >> WLAN_GPIO_PIN11_PAD_PULL_LSB) +#define WLAN_GPIO_PIN11_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN11_PAD_PULL_LSB) & WLAN_GPIO_PIN11_PAD_PULL_MASK) +#define WLAN_GPIO_PIN11_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN11_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN11_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN11_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN11_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN11_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN11_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN11_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN11_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN11_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN11_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN11_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN11_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN11_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN11_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN11_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN11_PAD_DRIVER_LSB) & WLAN_GPIO_PIN11_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN11_SOURCE_MSB 0 +#define WLAN_GPIO_PIN11_SOURCE_LSB 0 +#define WLAN_GPIO_PIN11_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN11_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN11_SOURCE_MASK) >> WLAN_GPIO_PIN11_SOURCE_LSB) +#define WLAN_GPIO_PIN11_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN11_SOURCE_LSB) & WLAN_GPIO_PIN11_SOURCE_MASK) + +#define WLAN_GPIO_PIN12_ADDRESS 0x00000058 +#define WLAN_GPIO_PIN12_OFFSET 0x00000058 +#define WLAN_GPIO_PIN12_CONFIG_MSB 13 +#define WLAN_GPIO_PIN12_CONFIG_LSB 11 +#define WLAN_GPIO_PIN12_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN12_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN12_CONFIG_MASK) >> WLAN_GPIO_PIN12_CONFIG_LSB) +#define WLAN_GPIO_PIN12_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN12_CONFIG_LSB) & WLAN_GPIO_PIN12_CONFIG_MASK) +#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN12_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN12_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN12_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN12_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN12_INT_TYPE_MASK) >> WLAN_GPIO_PIN12_INT_TYPE_LSB) +#define WLAN_GPIO_PIN12_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN12_INT_TYPE_LSB) & WLAN_GPIO_PIN12_INT_TYPE_MASK) +#define WLAN_GPIO_PIN12_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN12_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN12_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN12_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN12_PAD_PULL_MASK) >> WLAN_GPIO_PIN12_PAD_PULL_LSB) +#define WLAN_GPIO_PIN12_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN12_PAD_PULL_LSB) & WLAN_GPIO_PIN12_PAD_PULL_MASK) +#define WLAN_GPIO_PIN12_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN12_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN12_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN12_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN12_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN12_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN12_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN12_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN12_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN12_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN12_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN12_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN12_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN12_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN12_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN12_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN12_PAD_DRIVER_LSB) & WLAN_GPIO_PIN12_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN12_SOURCE_MSB 0 +#define WLAN_GPIO_PIN12_SOURCE_LSB 0 +#define WLAN_GPIO_PIN12_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN12_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN12_SOURCE_MASK) >> WLAN_GPIO_PIN12_SOURCE_LSB) +#define WLAN_GPIO_PIN12_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN12_SOURCE_LSB) & WLAN_GPIO_PIN12_SOURCE_MASK) + +#define WLAN_GPIO_PIN13_ADDRESS 0x0000005c +#define WLAN_GPIO_PIN13_OFFSET 0x0000005c +#define WLAN_GPIO_PIN13_CONFIG_MSB 13 +#define WLAN_GPIO_PIN13_CONFIG_LSB 11 +#define WLAN_GPIO_PIN13_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN13_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN13_CONFIG_MASK) >> WLAN_GPIO_PIN13_CONFIG_LSB) +#define WLAN_GPIO_PIN13_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN13_CONFIG_LSB) & WLAN_GPIO_PIN13_CONFIG_MASK) +#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN13_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN13_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN13_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN13_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN13_INT_TYPE_MASK) >> WLAN_GPIO_PIN13_INT_TYPE_LSB) +#define WLAN_GPIO_PIN13_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN13_INT_TYPE_LSB) & WLAN_GPIO_PIN13_INT_TYPE_MASK) +#define WLAN_GPIO_PIN13_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN13_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN13_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN13_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN13_PAD_PULL_MASK) >> WLAN_GPIO_PIN13_PAD_PULL_LSB) +#define WLAN_GPIO_PIN13_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN13_PAD_PULL_LSB) & WLAN_GPIO_PIN13_PAD_PULL_MASK) +#define WLAN_GPIO_PIN13_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN13_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN13_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN13_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN13_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN13_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN13_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN13_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN13_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN13_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN13_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN13_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN13_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN13_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN13_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN13_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN13_PAD_DRIVER_LSB) & WLAN_GPIO_PIN13_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN13_SOURCE_MSB 0 +#define WLAN_GPIO_PIN13_SOURCE_LSB 0 +#define WLAN_GPIO_PIN13_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN13_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN13_SOURCE_MASK) >> WLAN_GPIO_PIN13_SOURCE_LSB) +#define WLAN_GPIO_PIN13_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN13_SOURCE_LSB) & WLAN_GPIO_PIN13_SOURCE_MASK) + +#define WLAN_GPIO_PIN14_ADDRESS 0x00000060 +#define WLAN_GPIO_PIN14_OFFSET 0x00000060 +#define WLAN_GPIO_PIN14_CONFIG_MSB 13 +#define WLAN_GPIO_PIN14_CONFIG_LSB 11 +#define WLAN_GPIO_PIN14_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN14_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN14_CONFIG_MASK) >> WLAN_GPIO_PIN14_CONFIG_LSB) +#define WLAN_GPIO_PIN14_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN14_CONFIG_LSB) & WLAN_GPIO_PIN14_CONFIG_MASK) +#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN14_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN14_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN14_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN14_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN14_INT_TYPE_MASK) >> WLAN_GPIO_PIN14_INT_TYPE_LSB) +#define WLAN_GPIO_PIN14_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN14_INT_TYPE_LSB) & WLAN_GPIO_PIN14_INT_TYPE_MASK) +#define WLAN_GPIO_PIN14_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN14_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN14_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN14_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN14_PAD_PULL_MASK) >> WLAN_GPIO_PIN14_PAD_PULL_LSB) +#define WLAN_GPIO_PIN14_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN14_PAD_PULL_LSB) & WLAN_GPIO_PIN14_PAD_PULL_MASK) +#define WLAN_GPIO_PIN14_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN14_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN14_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN14_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN14_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN14_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN14_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN14_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN14_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN14_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN14_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN14_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN14_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN14_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN14_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN14_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN14_PAD_DRIVER_LSB) & WLAN_GPIO_PIN14_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN14_SOURCE_MSB 0 +#define WLAN_GPIO_PIN14_SOURCE_LSB 0 +#define WLAN_GPIO_PIN14_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN14_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN14_SOURCE_MASK) >> WLAN_GPIO_PIN14_SOURCE_LSB) +#define WLAN_GPIO_PIN14_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN14_SOURCE_LSB) & WLAN_GPIO_PIN14_SOURCE_MASK) + +#define WLAN_GPIO_PIN15_ADDRESS 0x00000064 +#define WLAN_GPIO_PIN15_OFFSET 0x00000064 +#define WLAN_GPIO_PIN15_CONFIG_MSB 13 +#define WLAN_GPIO_PIN15_CONFIG_LSB 11 +#define WLAN_GPIO_PIN15_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN15_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN15_CONFIG_MASK) >> WLAN_GPIO_PIN15_CONFIG_LSB) +#define WLAN_GPIO_PIN15_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN15_CONFIG_LSB) & WLAN_GPIO_PIN15_CONFIG_MASK) +#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN15_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN15_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN15_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN15_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN15_INT_TYPE_MASK) >> WLAN_GPIO_PIN15_INT_TYPE_LSB) +#define WLAN_GPIO_PIN15_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN15_INT_TYPE_LSB) & WLAN_GPIO_PIN15_INT_TYPE_MASK) +#define WLAN_GPIO_PIN15_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN15_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN15_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN15_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN15_PAD_PULL_MASK) >> WLAN_GPIO_PIN15_PAD_PULL_LSB) +#define WLAN_GPIO_PIN15_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN15_PAD_PULL_LSB) & WLAN_GPIO_PIN15_PAD_PULL_MASK) +#define WLAN_GPIO_PIN15_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN15_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN15_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN15_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN15_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN15_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN15_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN15_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN15_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN15_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN15_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN15_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN15_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN15_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN15_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN15_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN15_PAD_DRIVER_LSB) & WLAN_GPIO_PIN15_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN15_SOURCE_MSB 0 +#define WLAN_GPIO_PIN15_SOURCE_LSB 0 +#define WLAN_GPIO_PIN15_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN15_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN15_SOURCE_MASK) >> WLAN_GPIO_PIN15_SOURCE_LSB) +#define WLAN_GPIO_PIN15_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN15_SOURCE_LSB) & WLAN_GPIO_PIN15_SOURCE_MASK) + +#define WLAN_GPIO_PIN16_ADDRESS 0x00000068 +#define WLAN_GPIO_PIN16_OFFSET 0x00000068 +#define WLAN_GPIO_PIN16_CONFIG_MSB 13 +#define WLAN_GPIO_PIN16_CONFIG_LSB 11 +#define WLAN_GPIO_PIN16_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN16_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN16_CONFIG_MASK) >> WLAN_GPIO_PIN16_CONFIG_LSB) +#define WLAN_GPIO_PIN16_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN16_CONFIG_LSB) & WLAN_GPIO_PIN16_CONFIG_MASK) +#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN16_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN16_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN16_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN16_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN16_INT_TYPE_MASK) >> WLAN_GPIO_PIN16_INT_TYPE_LSB) +#define WLAN_GPIO_PIN16_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN16_INT_TYPE_LSB) & WLAN_GPIO_PIN16_INT_TYPE_MASK) +#define WLAN_GPIO_PIN16_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN16_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN16_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN16_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN16_PAD_PULL_MASK) >> WLAN_GPIO_PIN16_PAD_PULL_LSB) +#define WLAN_GPIO_PIN16_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN16_PAD_PULL_LSB) & WLAN_GPIO_PIN16_PAD_PULL_MASK) +#define WLAN_GPIO_PIN16_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN16_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN16_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN16_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN16_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN16_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN16_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN16_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN16_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN16_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN16_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN16_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN16_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN16_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN16_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN16_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN16_PAD_DRIVER_LSB) & WLAN_GPIO_PIN16_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN16_SOURCE_MSB 0 +#define WLAN_GPIO_PIN16_SOURCE_LSB 0 +#define WLAN_GPIO_PIN16_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN16_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN16_SOURCE_MASK) >> WLAN_GPIO_PIN16_SOURCE_LSB) +#define WLAN_GPIO_PIN16_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN16_SOURCE_LSB) & WLAN_GPIO_PIN16_SOURCE_MASK) + +#define WLAN_GPIO_PIN17_ADDRESS 0x0000006c +#define WLAN_GPIO_PIN17_OFFSET 0x0000006c +#define WLAN_GPIO_PIN17_CONFIG_MSB 13 +#define WLAN_GPIO_PIN17_CONFIG_LSB 11 +#define WLAN_GPIO_PIN17_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN17_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN17_CONFIG_MASK) >> WLAN_GPIO_PIN17_CONFIG_LSB) +#define WLAN_GPIO_PIN17_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN17_CONFIG_LSB) & WLAN_GPIO_PIN17_CONFIG_MASK) +#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN17_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN17_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN17_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN17_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN17_INT_TYPE_MASK) >> WLAN_GPIO_PIN17_INT_TYPE_LSB) +#define WLAN_GPIO_PIN17_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN17_INT_TYPE_LSB) & WLAN_GPIO_PIN17_INT_TYPE_MASK) +#define WLAN_GPIO_PIN17_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN17_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN17_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN17_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN17_PAD_PULL_MASK) >> WLAN_GPIO_PIN17_PAD_PULL_LSB) +#define WLAN_GPIO_PIN17_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN17_PAD_PULL_LSB) & WLAN_GPIO_PIN17_PAD_PULL_MASK) +#define WLAN_GPIO_PIN17_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN17_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN17_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN17_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN17_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN17_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN17_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN17_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN17_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN17_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN17_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN17_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN17_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN17_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN17_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN17_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN17_PAD_DRIVER_LSB) & WLAN_GPIO_PIN17_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN17_SOURCE_MSB 0 +#define WLAN_GPIO_PIN17_SOURCE_LSB 0 +#define WLAN_GPIO_PIN17_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN17_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN17_SOURCE_MASK) >> WLAN_GPIO_PIN17_SOURCE_LSB) +#define WLAN_GPIO_PIN17_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN17_SOURCE_LSB) & WLAN_GPIO_PIN17_SOURCE_MASK) + +#define WLAN_GPIO_PIN18_ADDRESS 0x00000070 +#define WLAN_GPIO_PIN18_OFFSET 0x00000070 +#define WLAN_GPIO_PIN18_CONFIG_MSB 13 +#define WLAN_GPIO_PIN18_CONFIG_LSB 11 +#define WLAN_GPIO_PIN18_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN18_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN18_CONFIG_MASK) >> WLAN_GPIO_PIN18_CONFIG_LSB) +#define WLAN_GPIO_PIN18_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN18_CONFIG_LSB) & WLAN_GPIO_PIN18_CONFIG_MASK) +#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN18_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN18_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN18_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN18_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN18_INT_TYPE_MASK) >> WLAN_GPIO_PIN18_INT_TYPE_LSB) +#define WLAN_GPIO_PIN18_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN18_INT_TYPE_LSB) & WLAN_GPIO_PIN18_INT_TYPE_MASK) +#define WLAN_GPIO_PIN18_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN18_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN18_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN18_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN18_PAD_PULL_MASK) >> WLAN_GPIO_PIN18_PAD_PULL_LSB) +#define WLAN_GPIO_PIN18_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN18_PAD_PULL_LSB) & WLAN_GPIO_PIN18_PAD_PULL_MASK) +#define WLAN_GPIO_PIN18_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN18_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN18_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN18_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN18_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN18_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN18_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN18_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN18_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN18_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN18_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN18_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN18_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN18_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN18_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN18_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN18_PAD_DRIVER_LSB) & WLAN_GPIO_PIN18_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN18_SOURCE_MSB 0 +#define WLAN_GPIO_PIN18_SOURCE_LSB 0 +#define WLAN_GPIO_PIN18_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN18_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN18_SOURCE_MASK) >> WLAN_GPIO_PIN18_SOURCE_LSB) +#define WLAN_GPIO_PIN18_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN18_SOURCE_LSB) & WLAN_GPIO_PIN18_SOURCE_MASK) + +#define WLAN_GPIO_PIN19_ADDRESS 0x00000074 +#define WLAN_GPIO_PIN19_OFFSET 0x00000074 +#define WLAN_GPIO_PIN19_CONFIG_MSB 13 +#define WLAN_GPIO_PIN19_CONFIG_LSB 11 +#define WLAN_GPIO_PIN19_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN19_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN19_CONFIG_MASK) >> WLAN_GPIO_PIN19_CONFIG_LSB) +#define WLAN_GPIO_PIN19_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN19_CONFIG_LSB) & WLAN_GPIO_PIN19_CONFIG_MASK) +#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN19_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN19_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN19_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN19_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN19_INT_TYPE_MASK) >> WLAN_GPIO_PIN19_INT_TYPE_LSB) +#define WLAN_GPIO_PIN19_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN19_INT_TYPE_LSB) & WLAN_GPIO_PIN19_INT_TYPE_MASK) +#define WLAN_GPIO_PIN19_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN19_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN19_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN19_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN19_PAD_PULL_MASK) >> WLAN_GPIO_PIN19_PAD_PULL_LSB) +#define WLAN_GPIO_PIN19_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN19_PAD_PULL_LSB) & WLAN_GPIO_PIN19_PAD_PULL_MASK) +#define WLAN_GPIO_PIN19_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN19_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN19_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN19_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN19_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN19_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN19_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN19_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN19_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN19_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN19_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN19_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN19_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN19_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN19_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN19_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN19_PAD_DRIVER_LSB) & WLAN_GPIO_PIN19_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN19_SOURCE_MSB 0 +#define WLAN_GPIO_PIN19_SOURCE_LSB 0 +#define WLAN_GPIO_PIN19_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN19_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN19_SOURCE_MASK) >> WLAN_GPIO_PIN19_SOURCE_LSB) +#define WLAN_GPIO_PIN19_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN19_SOURCE_LSB) & WLAN_GPIO_PIN19_SOURCE_MASK) + +#define WLAN_GPIO_PIN20_ADDRESS 0x00000078 +#define WLAN_GPIO_PIN20_OFFSET 0x00000078 +#define WLAN_GPIO_PIN20_CONFIG_MSB 13 +#define WLAN_GPIO_PIN20_CONFIG_LSB 11 +#define WLAN_GPIO_PIN20_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN20_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN20_CONFIG_MASK) >> WLAN_GPIO_PIN20_CONFIG_LSB) +#define WLAN_GPIO_PIN20_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN20_CONFIG_LSB) & WLAN_GPIO_PIN20_CONFIG_MASK) +#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN20_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN20_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN20_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN20_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN20_INT_TYPE_MASK) >> WLAN_GPIO_PIN20_INT_TYPE_LSB) +#define WLAN_GPIO_PIN20_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN20_INT_TYPE_LSB) & WLAN_GPIO_PIN20_INT_TYPE_MASK) +#define WLAN_GPIO_PIN20_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN20_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN20_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN20_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN20_PAD_PULL_MASK) >> WLAN_GPIO_PIN20_PAD_PULL_LSB) +#define WLAN_GPIO_PIN20_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN20_PAD_PULL_LSB) & WLAN_GPIO_PIN20_PAD_PULL_MASK) +#define WLAN_GPIO_PIN20_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN20_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN20_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN20_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN20_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN20_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN20_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN20_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN20_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN20_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN20_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN20_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN20_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN20_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN20_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN20_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN20_PAD_DRIVER_LSB) & WLAN_GPIO_PIN20_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN20_SOURCE_MSB 0 +#define WLAN_GPIO_PIN20_SOURCE_LSB 0 +#define WLAN_GPIO_PIN20_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN20_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN20_SOURCE_MASK) >> WLAN_GPIO_PIN20_SOURCE_LSB) +#define WLAN_GPIO_PIN20_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN20_SOURCE_LSB) & WLAN_GPIO_PIN20_SOURCE_MASK) + +#define WLAN_GPIO_PIN21_ADDRESS 0x0000007c +#define WLAN_GPIO_PIN21_OFFSET 0x0000007c +#define WLAN_GPIO_PIN21_CONFIG_MSB 13 +#define WLAN_GPIO_PIN21_CONFIG_LSB 11 +#define WLAN_GPIO_PIN21_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN21_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN21_CONFIG_MASK) >> WLAN_GPIO_PIN21_CONFIG_LSB) +#define WLAN_GPIO_PIN21_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN21_CONFIG_LSB) & WLAN_GPIO_PIN21_CONFIG_MASK) +#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN21_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN21_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN21_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN21_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN21_INT_TYPE_MASK) >> WLAN_GPIO_PIN21_INT_TYPE_LSB) +#define WLAN_GPIO_PIN21_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN21_INT_TYPE_LSB) & WLAN_GPIO_PIN21_INT_TYPE_MASK) +#define WLAN_GPIO_PIN21_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN21_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN21_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN21_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN21_PAD_PULL_MASK) >> WLAN_GPIO_PIN21_PAD_PULL_LSB) +#define WLAN_GPIO_PIN21_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN21_PAD_PULL_LSB) & WLAN_GPIO_PIN21_PAD_PULL_MASK) +#define WLAN_GPIO_PIN21_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN21_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN21_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN21_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN21_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN21_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN21_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN21_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN21_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN21_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN21_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN21_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN21_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN21_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN21_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN21_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN21_PAD_DRIVER_LSB) & WLAN_GPIO_PIN21_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN21_SOURCE_MSB 0 +#define WLAN_GPIO_PIN21_SOURCE_LSB 0 +#define WLAN_GPIO_PIN21_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN21_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN21_SOURCE_MASK) >> WLAN_GPIO_PIN21_SOURCE_LSB) +#define WLAN_GPIO_PIN21_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN21_SOURCE_LSB) & WLAN_GPIO_PIN21_SOURCE_MASK) + +#define WLAN_GPIO_PIN22_ADDRESS 0x00000080 +#define WLAN_GPIO_PIN22_OFFSET 0x00000080 +#define WLAN_GPIO_PIN22_CONFIG_MSB 13 +#define WLAN_GPIO_PIN22_CONFIG_LSB 11 +#define WLAN_GPIO_PIN22_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN22_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN22_CONFIG_MASK) >> WLAN_GPIO_PIN22_CONFIG_LSB) +#define WLAN_GPIO_PIN22_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN22_CONFIG_LSB) & WLAN_GPIO_PIN22_CONFIG_MASK) +#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN22_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN22_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN22_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN22_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN22_INT_TYPE_MASK) >> WLAN_GPIO_PIN22_INT_TYPE_LSB) +#define WLAN_GPIO_PIN22_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN22_INT_TYPE_LSB) & WLAN_GPIO_PIN22_INT_TYPE_MASK) +#define WLAN_GPIO_PIN22_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN22_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN22_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN22_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN22_PAD_PULL_MASK) >> WLAN_GPIO_PIN22_PAD_PULL_LSB) +#define WLAN_GPIO_PIN22_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN22_PAD_PULL_LSB) & WLAN_GPIO_PIN22_PAD_PULL_MASK) +#define WLAN_GPIO_PIN22_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN22_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN22_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN22_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN22_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN22_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN22_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN22_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN22_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN22_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN22_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN22_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN22_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN22_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN22_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN22_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN22_PAD_DRIVER_LSB) & WLAN_GPIO_PIN22_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN22_SOURCE_MSB 0 +#define WLAN_GPIO_PIN22_SOURCE_LSB 0 +#define WLAN_GPIO_PIN22_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN22_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN22_SOURCE_MASK) >> WLAN_GPIO_PIN22_SOURCE_LSB) +#define WLAN_GPIO_PIN22_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN22_SOURCE_LSB) & WLAN_GPIO_PIN22_SOURCE_MASK) + +#define WLAN_GPIO_PIN23_ADDRESS 0x00000084 +#define WLAN_GPIO_PIN23_OFFSET 0x00000084 +#define WLAN_GPIO_PIN23_CONFIG_MSB 13 +#define WLAN_GPIO_PIN23_CONFIG_LSB 11 +#define WLAN_GPIO_PIN23_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN23_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN23_CONFIG_MASK) >> WLAN_GPIO_PIN23_CONFIG_LSB) +#define WLAN_GPIO_PIN23_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN23_CONFIG_LSB) & WLAN_GPIO_PIN23_CONFIG_MASK) +#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN23_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN23_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN23_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN23_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN23_INT_TYPE_MASK) >> WLAN_GPIO_PIN23_INT_TYPE_LSB) +#define WLAN_GPIO_PIN23_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN23_INT_TYPE_LSB) & WLAN_GPIO_PIN23_INT_TYPE_MASK) +#define WLAN_GPIO_PIN23_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN23_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN23_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN23_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN23_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN23_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN23_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN23_PAD_DRIVER_LSB) & WLAN_GPIO_PIN23_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN23_SOURCE_MSB 0 +#define WLAN_GPIO_PIN23_SOURCE_LSB 0 +#define WLAN_GPIO_PIN23_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN23_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN23_SOURCE_MASK) >> WLAN_GPIO_PIN23_SOURCE_LSB) +#define WLAN_GPIO_PIN23_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN23_SOURCE_LSB) & WLAN_GPIO_PIN23_SOURCE_MASK) + +#define WLAN_GPIO_PIN24_ADDRESS 0x00000088 +#define WLAN_GPIO_PIN24_OFFSET 0x00000088 +#define WLAN_GPIO_PIN24_CONFIG_MSB 13 +#define WLAN_GPIO_PIN24_CONFIG_LSB 11 +#define WLAN_GPIO_PIN24_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN24_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN24_CONFIG_MASK) >> WLAN_GPIO_PIN24_CONFIG_LSB) +#define WLAN_GPIO_PIN24_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN24_CONFIG_LSB) & WLAN_GPIO_PIN24_CONFIG_MASK) +#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN24_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN24_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN24_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN24_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN24_INT_TYPE_MASK) >> WLAN_GPIO_PIN24_INT_TYPE_LSB) +#define WLAN_GPIO_PIN24_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN24_INT_TYPE_LSB) & WLAN_GPIO_PIN24_INT_TYPE_MASK) +#define WLAN_GPIO_PIN24_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN24_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN24_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN24_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN24_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN24_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN24_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN24_PAD_DRIVER_LSB) & WLAN_GPIO_PIN24_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN24_SOURCE_MSB 0 +#define WLAN_GPIO_PIN24_SOURCE_LSB 0 +#define WLAN_GPIO_PIN24_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN24_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN24_SOURCE_MASK) >> WLAN_GPIO_PIN24_SOURCE_LSB) +#define WLAN_GPIO_PIN24_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN24_SOURCE_LSB) & WLAN_GPIO_PIN24_SOURCE_MASK) + +#define WLAN_GPIO_PIN25_ADDRESS 0x0000008c +#define WLAN_GPIO_PIN25_OFFSET 0x0000008c +#define WLAN_GPIO_PIN25_CONFIG_MSB 13 +#define WLAN_GPIO_PIN25_CONFIG_LSB 11 +#define WLAN_GPIO_PIN25_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN25_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN25_CONFIG_MASK) >> WLAN_GPIO_PIN25_CONFIG_LSB) +#define WLAN_GPIO_PIN25_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN25_CONFIG_LSB) & WLAN_GPIO_PIN25_CONFIG_MASK) +#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN25_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN25_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN25_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN25_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN25_INT_TYPE_MASK) >> WLAN_GPIO_PIN25_INT_TYPE_LSB) +#define WLAN_GPIO_PIN25_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN25_INT_TYPE_LSB) & WLAN_GPIO_PIN25_INT_TYPE_MASK) +#define WLAN_GPIO_PIN25_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN25_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN25_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN25_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN25_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN25_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN25_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN25_PAD_DRIVER_LSB) & WLAN_GPIO_PIN25_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN25_SOURCE_MSB 0 +#define WLAN_GPIO_PIN25_SOURCE_LSB 0 +#define WLAN_GPIO_PIN25_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN25_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN25_SOURCE_MASK) >> WLAN_GPIO_PIN25_SOURCE_LSB) +#define WLAN_GPIO_PIN25_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN25_SOURCE_LSB) & WLAN_GPIO_PIN25_SOURCE_MASK) + +#define SDIO_ADDRESS 0x00000090 +#define SDIO_OFFSET 0x00000090 +#define SDIO_PINS_EN_MSB 0 +#define SDIO_PINS_EN_LSB 0 +#define SDIO_PINS_EN_MASK 0x00000001 +#define SDIO_PINS_EN_GET(x) (((x) & SDIO_PINS_EN_MASK) >> SDIO_PINS_EN_LSB) +#define SDIO_PINS_EN_SET(x) (((x) << SDIO_PINS_EN_LSB) & SDIO_PINS_EN_MASK) + +#define FUNC_BUS_ADDRESS 0x00000094 +#define FUNC_BUS_OFFSET 0x00000094 +#define FUNC_BUS_GPIO_MODE_MSB 22 +#define FUNC_BUS_GPIO_MODE_LSB 22 +#define FUNC_BUS_GPIO_MODE_MASK 0x00400000 +#define FUNC_BUS_GPIO_MODE_GET(x) (((x) & FUNC_BUS_GPIO_MODE_MASK) >> FUNC_BUS_GPIO_MODE_LSB) +#define FUNC_BUS_GPIO_MODE_SET(x) (((x) << FUNC_BUS_GPIO_MODE_LSB) & FUNC_BUS_GPIO_MODE_MASK) +#define FUNC_BUS_OE_L_MSB 21 +#define FUNC_BUS_OE_L_LSB 0 +#define FUNC_BUS_OE_L_MASK 0x003fffff +#define FUNC_BUS_OE_L_GET(x) (((x) & FUNC_BUS_OE_L_MASK) >> FUNC_BUS_OE_L_LSB) +#define FUNC_BUS_OE_L_SET(x) (((x) << FUNC_BUS_OE_L_LSB) & FUNC_BUS_OE_L_MASK) + +#define WL_SOC_APB_ADDRESS 0x00000098 +#define WL_SOC_APB_OFFSET 0x00000098 +#define WL_SOC_APB_TOGGLE_MSB 0 +#define WL_SOC_APB_TOGGLE_LSB 0 +#define WL_SOC_APB_TOGGLE_MASK 0x00000001 +#define WL_SOC_APB_TOGGLE_GET(x) (((x) & WL_SOC_APB_TOGGLE_MASK) >> WL_SOC_APB_TOGGLE_LSB) +#define WL_SOC_APB_TOGGLE_SET(x) (((x) << WL_SOC_APB_TOGGLE_LSB) & WL_SOC_APB_TOGGLE_MASK) + +#define WLAN_SIGMA_DELTA_ADDRESS 0x0000009c +#define WLAN_SIGMA_DELTA_OFFSET 0x0000009c +#define WLAN_SIGMA_DELTA_ENABLE_MSB 16 +#define WLAN_SIGMA_DELTA_ENABLE_LSB 16 +#define WLAN_SIGMA_DELTA_ENABLE_MASK 0x00010000 +#define WLAN_SIGMA_DELTA_ENABLE_GET(x) (((x) & WLAN_SIGMA_DELTA_ENABLE_MASK) >> WLAN_SIGMA_DELTA_ENABLE_LSB) +#define WLAN_SIGMA_DELTA_ENABLE_SET(x) (((x) << WLAN_SIGMA_DELTA_ENABLE_LSB) & WLAN_SIGMA_DELTA_ENABLE_MASK) +#define WLAN_SIGMA_DELTA_PRESCALAR_MSB 15 +#define WLAN_SIGMA_DELTA_PRESCALAR_LSB 8 +#define WLAN_SIGMA_DELTA_PRESCALAR_MASK 0x0000ff00 +#define WLAN_SIGMA_DELTA_PRESCALAR_GET(x) (((x) & WLAN_SIGMA_DELTA_PRESCALAR_MASK) >> WLAN_SIGMA_DELTA_PRESCALAR_LSB) +#define WLAN_SIGMA_DELTA_PRESCALAR_SET(x) (((x) << WLAN_SIGMA_DELTA_PRESCALAR_LSB) & WLAN_SIGMA_DELTA_PRESCALAR_MASK) +#define WLAN_SIGMA_DELTA_TARGET_MSB 7 +#define WLAN_SIGMA_DELTA_TARGET_LSB 0 +#define WLAN_SIGMA_DELTA_TARGET_MASK 0x000000ff +#define WLAN_SIGMA_DELTA_TARGET_GET(x) (((x) & WLAN_SIGMA_DELTA_TARGET_MASK) >> WLAN_SIGMA_DELTA_TARGET_LSB) +#define WLAN_SIGMA_DELTA_TARGET_SET(x) (((x) << WLAN_SIGMA_DELTA_TARGET_LSB) & WLAN_SIGMA_DELTA_TARGET_MASK) + +#define WL_BOOTSTRAP_ADDRESS 0x000000a0 +#define WL_BOOTSTRAP_OFFSET 0x000000a0 +#define WL_BOOTSTRAP_STATUS_MSB 22 +#define WL_BOOTSTRAP_STATUS_LSB 0 +#define WL_BOOTSTRAP_STATUS_MASK 0x007fffff +#define WL_BOOTSTRAP_STATUS_GET(x) (((x) & WL_BOOTSTRAP_STATUS_MASK) >> WL_BOOTSTRAP_STATUS_LSB) +#define WL_BOOTSTRAP_STATUS_SET(x) (((x) << WL_BOOTSTRAP_STATUS_LSB) & WL_BOOTSTRAP_STATUS_MASK) + +#define CLOCK_GPIO_ADDRESS 0x000000a4 +#define CLOCK_GPIO_OFFSET 0x000000a4 +#define CLOCK_GPIO_CLK_REQ_OUT_EN_MSB 2 +#define CLOCK_GPIO_CLK_REQ_OUT_EN_LSB 2 +#define CLOCK_GPIO_CLK_REQ_OUT_EN_MASK 0x00000004 +#define CLOCK_GPIO_CLK_REQ_OUT_EN_GET(x) (((x) & CLOCK_GPIO_CLK_REQ_OUT_EN_MASK) >> CLOCK_GPIO_CLK_REQ_OUT_EN_LSB) +#define CLOCK_GPIO_CLK_REQ_OUT_EN_SET(x) (((x) << CLOCK_GPIO_CLK_REQ_OUT_EN_LSB) & CLOCK_GPIO_CLK_REQ_OUT_EN_MASK) +#define CLOCK_GPIO_BT_CLK_REQ_EN_MSB 1 +#define CLOCK_GPIO_BT_CLK_REQ_EN_LSB 1 +#define CLOCK_GPIO_BT_CLK_REQ_EN_MASK 0x00000002 +#define CLOCK_GPIO_BT_CLK_REQ_EN_GET(x) (((x) & CLOCK_GPIO_BT_CLK_REQ_EN_MASK) >> CLOCK_GPIO_BT_CLK_REQ_EN_LSB) +#define CLOCK_GPIO_BT_CLK_REQ_EN_SET(x) (((x) << CLOCK_GPIO_BT_CLK_REQ_EN_LSB) & CLOCK_GPIO_BT_CLK_REQ_EN_MASK) +#define CLOCK_GPIO_BT_CLK_OUT_EN_MSB 0 +#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 +#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0x00000001 +#define CLOCK_GPIO_BT_CLK_OUT_EN_GET(x) (((x) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK) >> CLOCK_GPIO_BT_CLK_OUT_EN_LSB) +#define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) (((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK) + +#define WLAN_DEBUG_CONTROL_ADDRESS 0x000000a8 +#define WLAN_DEBUG_CONTROL_OFFSET 0x000000a8 +#define WLAN_DEBUG_CONTROL_ENABLE_MSB 0 +#define WLAN_DEBUG_CONTROL_ENABLE_LSB 0 +#define WLAN_DEBUG_CONTROL_ENABLE_MASK 0x00000001 +#define WLAN_DEBUG_CONTROL_ENABLE_GET(x) (((x) & WLAN_DEBUG_CONTROL_ENABLE_MASK) >> WLAN_DEBUG_CONTROL_ENABLE_LSB) +#define WLAN_DEBUG_CONTROL_ENABLE_SET(x) (((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & WLAN_DEBUG_CONTROL_ENABLE_MASK) + +#define WLAN_DEBUG_INPUT_SEL_ADDRESS 0x000000ac +#define WLAN_DEBUG_INPUT_SEL_OFFSET 0x000000ac +#define WLAN_DEBUG_INPUT_SEL_SHIFT_MSB 5 +#define WLAN_DEBUG_INPUT_SEL_SHIFT_LSB 4 +#define WLAN_DEBUG_INPUT_SEL_SHIFT_MASK 0x00000030 +#define WLAN_DEBUG_INPUT_SEL_SHIFT_GET(x) (((x) & WLAN_DEBUG_INPUT_SEL_SHIFT_MASK) >> WLAN_DEBUG_INPUT_SEL_SHIFT_LSB) +#define WLAN_DEBUG_INPUT_SEL_SHIFT_SET(x) (((x) << WLAN_DEBUG_INPUT_SEL_SHIFT_LSB) & WLAN_DEBUG_INPUT_SEL_SHIFT_MASK) +#define WLAN_DEBUG_INPUT_SEL_SRC_MSB 3 +#define WLAN_DEBUG_INPUT_SEL_SRC_LSB 0 +#define WLAN_DEBUG_INPUT_SEL_SRC_MASK 0x0000000f +#define WLAN_DEBUG_INPUT_SEL_SRC_GET(x) (((x) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> WLAN_DEBUG_INPUT_SEL_SRC_LSB) +#define WLAN_DEBUG_INPUT_SEL_SRC_SET(x) (((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) + +#define WLAN_DEBUG_OUT_ADDRESS 0x000000b0 +#define WLAN_DEBUG_OUT_OFFSET 0x000000b0 +#define WLAN_DEBUG_OUT_DATA_MSB 17 +#define WLAN_DEBUG_OUT_DATA_LSB 0 +#define WLAN_DEBUG_OUT_DATA_MASK 0x0003ffff +#define WLAN_DEBUG_OUT_DATA_GET(x) (((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB) +#define WLAN_DEBUG_OUT_DATA_SET(x) (((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK) + +#define WLAN_RESET_TUPLE_STATUS_ADDRESS 0x000000b4 +#define WLAN_RESET_TUPLE_STATUS_OFFSET 0x000000b4 +#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11 +#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8 +#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00 +#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) +#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) +#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7 +#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0 +#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff +#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) +#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) + +#define ANTENNA_SLEEP_CONTROL_ADDRESS 0x000000b8 +#define ANTENNA_SLEEP_CONTROL_OFFSET 0x000000b8 +#define ANTENNA_SLEEP_CONTROL_OVERRIDE_MSB 14 +#define ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB 10 +#define ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK 0x00007c00 +#define ANTENNA_SLEEP_CONTROL_OVERRIDE_GET(x) (((x) & ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK) >> ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB) +#define ANTENNA_SLEEP_CONTROL_OVERRIDE_SET(x) (((x) << ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB) & ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK) +#define ANTENNA_SLEEP_CONTROL_VALUE_MSB 9 +#define ANTENNA_SLEEP_CONTROL_VALUE_LSB 5 +#define ANTENNA_SLEEP_CONTROL_VALUE_MASK 0x000003e0 +#define ANTENNA_SLEEP_CONTROL_VALUE_GET(x) (((x) & ANTENNA_SLEEP_CONTROL_VALUE_MASK) >> ANTENNA_SLEEP_CONTROL_VALUE_LSB) +#define ANTENNA_SLEEP_CONTROL_VALUE_SET(x) (((x) << ANTENNA_SLEEP_CONTROL_VALUE_LSB) & ANTENNA_SLEEP_CONTROL_VALUE_MASK) +#define ANTENNA_SLEEP_CONTROL_ENABLE_MSB 4 +#define ANTENNA_SLEEP_CONTROL_ENABLE_LSB 0 +#define ANTENNA_SLEEP_CONTROL_ENABLE_MASK 0x0000001f +#define ANTENNA_SLEEP_CONTROL_ENABLE_GET(x) (((x) & ANTENNA_SLEEP_CONTROL_ENABLE_MASK) >> ANTENNA_SLEEP_CONTROL_ENABLE_LSB) +#define ANTENNA_SLEEP_CONTROL_ENABLE_SET(x) (((x) << ANTENNA_SLEEP_CONTROL_ENABLE_LSB) & ANTENNA_SLEEP_CONTROL_ENABLE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct gpio_athr_wlan_reg_reg_s { + volatile unsigned int wlan_gpio_out; + volatile unsigned int wlan_gpio_out_w1ts; + volatile unsigned int wlan_gpio_out_w1tc; + volatile unsigned int wlan_gpio_enable; + volatile unsigned int wlan_gpio_enable_w1ts; + volatile unsigned int wlan_gpio_enable_w1tc; + volatile unsigned int wlan_gpio_in; + volatile unsigned int wlan_gpio_status; + volatile unsigned int wlan_gpio_status_w1ts; + volatile unsigned int wlan_gpio_status_w1tc; + volatile unsigned int wlan_gpio_pin0; + volatile unsigned int wlan_gpio_pin1; + volatile unsigned int wlan_gpio_pin2; + volatile unsigned int wlan_gpio_pin3; + volatile unsigned int wlan_gpio_pin4; + volatile unsigned int wlan_gpio_pin5; + volatile unsigned int wlan_gpio_pin6; + volatile unsigned int wlan_gpio_pin7; + volatile unsigned int wlan_gpio_pin8; + volatile unsigned int wlan_gpio_pin9; + volatile unsigned int wlan_gpio_pin10; + volatile unsigned int wlan_gpio_pin11; + volatile unsigned int wlan_gpio_pin12; + volatile unsigned int wlan_gpio_pin13; + volatile unsigned int wlan_gpio_pin14; + volatile unsigned int wlan_gpio_pin15; + volatile unsigned int wlan_gpio_pin16; + volatile unsigned int wlan_gpio_pin17; + volatile unsigned int wlan_gpio_pin18; + volatile unsigned int wlan_gpio_pin19; + volatile unsigned int wlan_gpio_pin20; + volatile unsigned int wlan_gpio_pin21; + volatile unsigned int wlan_gpio_pin22; + volatile unsigned int wlan_gpio_pin23; + volatile unsigned int wlan_gpio_pin24; + volatile unsigned int wlan_gpio_pin25; + volatile unsigned int sdio; + volatile unsigned int func_bus; + volatile unsigned int wl_soc_apb; + volatile unsigned int wlan_sigma_delta; + volatile unsigned int wl_bootstrap; + volatile unsigned int clock_gpio; + volatile unsigned int wlan_debug_control; + volatile unsigned int wlan_debug_input_sel; + volatile unsigned int wlan_debug_out; + volatile unsigned int wlan_reset_tuple_status; + volatile unsigned int antenna_sleep_control; +} gpio_athr_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _GPIO_ATHR_WLAN_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_reg.h new file mode 100644 index 000000000000..b3e7126e26a2 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_reg.h @@ -0,0 +1,1094 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "gpio_athr_wlan_reg.h" + + +#ifndef BT_HEADERS + +#define GPIO_OUT_ADDRESS WLAN_GPIO_OUT_ADDRESS +#define GPIO_OUT_OFFSET WLAN_GPIO_OUT_OFFSET +#define GPIO_OUT_DATA_MSB WLAN_GPIO_OUT_DATA_MSB +#define GPIO_OUT_DATA_LSB WLAN_GPIO_OUT_DATA_LSB +#define GPIO_OUT_DATA_MASK WLAN_GPIO_OUT_DATA_MASK +#define GPIO_OUT_DATA_GET(x) WLAN_GPIO_OUT_DATA_GET(x) +#define GPIO_OUT_DATA_SET(x) WLAN_GPIO_OUT_DATA_SET(x) +#define GPIO_OUT_W1TS_ADDRESS WLAN_GPIO_OUT_W1TS_ADDRESS +#define GPIO_OUT_W1TS_OFFSET WLAN_GPIO_OUT_W1TS_OFFSET +#define GPIO_OUT_W1TS_DATA_MSB WLAN_GPIO_OUT_W1TS_DATA_MSB +#define GPIO_OUT_W1TS_DATA_LSB WLAN_GPIO_OUT_W1TS_DATA_LSB +#define GPIO_OUT_W1TS_DATA_MASK WLAN_GPIO_OUT_W1TS_DATA_MASK +#define GPIO_OUT_W1TS_DATA_GET(x) WLAN_GPIO_OUT_W1TS_DATA_GET(x) +#define GPIO_OUT_W1TS_DATA_SET(x) WLAN_GPIO_OUT_W1TS_DATA_SET(x) +#define GPIO_OUT_W1TC_ADDRESS WLAN_GPIO_OUT_W1TC_ADDRESS +#define GPIO_OUT_W1TC_OFFSET WLAN_GPIO_OUT_W1TC_OFFSET +#define GPIO_OUT_W1TC_DATA_MSB WLAN_GPIO_OUT_W1TC_DATA_MSB +#define GPIO_OUT_W1TC_DATA_LSB WLAN_GPIO_OUT_W1TC_DATA_LSB +#define GPIO_OUT_W1TC_DATA_MASK WLAN_GPIO_OUT_W1TC_DATA_MASK +#define GPIO_OUT_W1TC_DATA_GET(x) WLAN_GPIO_OUT_W1TC_DATA_GET(x) +#define GPIO_OUT_W1TC_DATA_SET(x) WLAN_GPIO_OUT_W1TC_DATA_SET(x) +#define GPIO_ENABLE_ADDRESS WLAN_GPIO_ENABLE_ADDRESS +#define GPIO_ENABLE_OFFSET WLAN_GPIO_ENABLE_OFFSET +#define GPIO_ENABLE_DATA_MSB WLAN_GPIO_ENABLE_DATA_MSB +#define GPIO_ENABLE_DATA_LSB WLAN_GPIO_ENABLE_DATA_LSB +#define GPIO_ENABLE_DATA_MASK WLAN_GPIO_ENABLE_DATA_MASK +#define GPIO_ENABLE_DATA_GET(x) WLAN_GPIO_ENABLE_DATA_GET(x) +#define GPIO_ENABLE_DATA_SET(x) WLAN_GPIO_ENABLE_DATA_SET(x) +#define GPIO_ENABLE_W1TS_ADDRESS WLAN_GPIO_ENABLE_W1TS_ADDRESS +#define GPIO_ENABLE_W1TS_OFFSET WLAN_GPIO_ENABLE_W1TS_OFFSET +#define GPIO_ENABLE_W1TS_DATA_MSB WLAN_GPIO_ENABLE_W1TS_DATA_MSB +#define GPIO_ENABLE_W1TS_DATA_LSB WLAN_GPIO_ENABLE_W1TS_DATA_LSB +#define GPIO_ENABLE_W1TS_DATA_MASK WLAN_GPIO_ENABLE_W1TS_DATA_MASK +#define GPIO_ENABLE_W1TS_DATA_GET(x) WLAN_GPIO_ENABLE_W1TS_DATA_GET(x) +#define GPIO_ENABLE_W1TS_DATA_SET(x) WLAN_GPIO_ENABLE_W1TS_DATA_SET(x) +#define GPIO_ENABLE_W1TC_ADDRESS WLAN_GPIO_ENABLE_W1TC_ADDRESS +#define GPIO_ENABLE_W1TC_OFFSET WLAN_GPIO_ENABLE_W1TC_OFFSET +#define GPIO_ENABLE_W1TC_DATA_MSB WLAN_GPIO_ENABLE_W1TC_DATA_MSB +#define GPIO_ENABLE_W1TC_DATA_LSB WLAN_GPIO_ENABLE_W1TC_DATA_LSB +#define GPIO_ENABLE_W1TC_DATA_MASK WLAN_GPIO_ENABLE_W1TC_DATA_MASK +#define GPIO_ENABLE_W1TC_DATA_GET(x) WLAN_GPIO_ENABLE_W1TC_DATA_GET(x) +#define GPIO_ENABLE_W1TC_DATA_SET(x) WLAN_GPIO_ENABLE_W1TC_DATA_SET(x) +#define GPIO_IN_ADDRESS WLAN_GPIO_IN_ADDRESS +#define GPIO_IN_OFFSET WLAN_GPIO_IN_OFFSET +#define GPIO_IN_DATA_MSB WLAN_GPIO_IN_DATA_MSB +#define GPIO_IN_DATA_LSB WLAN_GPIO_IN_DATA_LSB +#define GPIO_IN_DATA_MASK WLAN_GPIO_IN_DATA_MASK +#define GPIO_IN_DATA_GET(x) WLAN_GPIO_IN_DATA_GET(x) +#define GPIO_IN_DATA_SET(x) WLAN_GPIO_IN_DATA_SET(x) +#define GPIO_STATUS_ADDRESS WLAN_GPIO_STATUS_ADDRESS +#define GPIO_STATUS_OFFSET WLAN_GPIO_STATUS_OFFSET +#define GPIO_STATUS_INTERRUPT_MSB WLAN_GPIO_STATUS_INTERRUPT_MSB +#define GPIO_STATUS_INTERRUPT_LSB WLAN_GPIO_STATUS_INTERRUPT_LSB +#define GPIO_STATUS_INTERRUPT_MASK WLAN_GPIO_STATUS_INTERRUPT_MASK +#define GPIO_STATUS_INTERRUPT_GET(x) WLAN_GPIO_STATUS_INTERRUPT_GET(x) +#define GPIO_STATUS_INTERRUPT_SET(x) WLAN_GPIO_STATUS_INTERRUPT_SET(x) +#define GPIO_STATUS_W1TS_ADDRESS WLAN_GPIO_STATUS_W1TS_ADDRESS +#define GPIO_STATUS_W1TS_OFFSET WLAN_GPIO_STATUS_W1TS_OFFSET +#define GPIO_STATUS_W1TS_INTERRUPT_MSB WLAN_GPIO_STATUS_W1TS_INTERRUPT_MSB +#define GPIO_STATUS_W1TS_INTERRUPT_LSB WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB +#define GPIO_STATUS_W1TS_INTERRUPT_MASK WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK +#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) WLAN_GPIO_STATUS_W1TS_INTERRUPT_GET(x) +#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) WLAN_GPIO_STATUS_W1TS_INTERRUPT_SET(x) +#define GPIO_STATUS_W1TC_ADDRESS WLAN_GPIO_STATUS_W1TC_ADDRESS +#define GPIO_STATUS_W1TC_OFFSET WLAN_GPIO_STATUS_W1TC_OFFSET +#define GPIO_STATUS_W1TC_INTERRUPT_MSB WLAN_GPIO_STATUS_W1TC_INTERRUPT_MSB +#define GPIO_STATUS_W1TC_INTERRUPT_LSB WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB +#define GPIO_STATUS_W1TC_INTERRUPT_MASK WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK +#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) WLAN_GPIO_STATUS_W1TC_INTERRUPT_GET(x) +#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) WLAN_GPIO_STATUS_W1TC_INTERRUPT_SET(x) +#define GPIO_PIN0_ADDRESS WLAN_GPIO_PIN0_ADDRESS +#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_OFFSET +#define GPIO_PIN0_CONFIG_MSB WLAN_GPIO_PIN0_CONFIG_MSB +#define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB +#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK +#define GPIO_PIN0_CONFIG_GET(x) WLAN_GPIO_PIN0_CONFIG_GET(x) +#define GPIO_PIN0_CONFIG_SET(x) WLAN_GPIO_PIN0_CONFIG_SET(x) +#define GPIO_PIN0_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN0_WAKEUP_ENABLE_MSB +#define GPIO_PIN0_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB +#define GPIO_PIN0_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK +#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN0_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN0_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN0_INT_TYPE_MSB WLAN_GPIO_PIN0_INT_TYPE_MSB +#define GPIO_PIN0_INT_TYPE_LSB WLAN_GPIO_PIN0_INT_TYPE_LSB +#define GPIO_PIN0_INT_TYPE_MASK WLAN_GPIO_PIN0_INT_TYPE_MASK +#define GPIO_PIN0_INT_TYPE_GET(x) WLAN_GPIO_PIN0_INT_TYPE_GET(x) +#define GPIO_PIN0_INT_TYPE_SET(x) WLAN_GPIO_PIN0_INT_TYPE_SET(x) +#define GPIO_PIN0_PAD_PULL_MSB WLAN_GPIO_PIN0_PAD_PULL_MSB +#define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB +#define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK +#define GPIO_PIN0_PAD_PULL_GET(x) WLAN_GPIO_PIN0_PAD_PULL_GET(x) +#define GPIO_PIN0_PAD_PULL_SET(x) WLAN_GPIO_PIN0_PAD_PULL_SET(x) +#define GPIO_PIN0_PAD_STRENGTH_MSB WLAN_GPIO_PIN0_PAD_STRENGTH_MSB +#define GPIO_PIN0_PAD_STRENGTH_LSB WLAN_GPIO_PIN0_PAD_STRENGTH_LSB +#define GPIO_PIN0_PAD_STRENGTH_MASK WLAN_GPIO_PIN0_PAD_STRENGTH_MASK +#define GPIO_PIN0_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN0_PAD_STRENGTH_GET(x) +#define GPIO_PIN0_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN0_PAD_STRENGTH_SET(x) +#define GPIO_PIN0_PAD_DRIVER_MSB WLAN_GPIO_PIN0_PAD_DRIVER_MSB +#define GPIO_PIN0_PAD_DRIVER_LSB WLAN_GPIO_PIN0_PAD_DRIVER_LSB +#define GPIO_PIN0_PAD_DRIVER_MASK WLAN_GPIO_PIN0_PAD_DRIVER_MASK +#define GPIO_PIN0_PAD_DRIVER_GET(x) WLAN_GPIO_PIN0_PAD_DRIVER_GET(x) +#define GPIO_PIN0_PAD_DRIVER_SET(x) WLAN_GPIO_PIN0_PAD_DRIVER_SET(x) +#define GPIO_PIN0_SOURCE_MSB WLAN_GPIO_PIN0_SOURCE_MSB +#define GPIO_PIN0_SOURCE_LSB WLAN_GPIO_PIN0_SOURCE_LSB +#define GPIO_PIN0_SOURCE_MASK WLAN_GPIO_PIN0_SOURCE_MASK +#define GPIO_PIN0_SOURCE_GET(x) WLAN_GPIO_PIN0_SOURCE_GET(x) +#define GPIO_PIN0_SOURCE_SET(x) WLAN_GPIO_PIN0_SOURCE_SET(x) +#define GPIO_PIN1_ADDRESS WLAN_GPIO_PIN1_ADDRESS +#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_OFFSET +#define GPIO_PIN1_CONFIG_MSB WLAN_GPIO_PIN1_CONFIG_MSB +#define GPIO_PIN1_CONFIG_LSB WLAN_GPIO_PIN1_CONFIG_LSB +#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK +#define GPIO_PIN1_CONFIG_GET(x) WLAN_GPIO_PIN1_CONFIG_GET(x) +#define GPIO_PIN1_CONFIG_SET(x) WLAN_GPIO_PIN1_CONFIG_SET(x) +#define GPIO_PIN1_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN1_WAKEUP_ENABLE_MSB +#define GPIO_PIN1_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB +#define GPIO_PIN1_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK +#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN1_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN1_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN1_INT_TYPE_MSB WLAN_GPIO_PIN1_INT_TYPE_MSB +#define GPIO_PIN1_INT_TYPE_LSB WLAN_GPIO_PIN1_INT_TYPE_LSB +#define GPIO_PIN1_INT_TYPE_MASK WLAN_GPIO_PIN1_INT_TYPE_MASK +#define GPIO_PIN1_INT_TYPE_GET(x) WLAN_GPIO_PIN1_INT_TYPE_GET(x) +#define GPIO_PIN1_INT_TYPE_SET(x) WLAN_GPIO_PIN1_INT_TYPE_SET(x) +#define GPIO_PIN1_PAD_PULL_MSB WLAN_GPIO_PIN1_PAD_PULL_MSB +#define GPIO_PIN1_PAD_PULL_LSB WLAN_GPIO_PIN1_PAD_PULL_LSB +#define GPIO_PIN1_PAD_PULL_MASK WLAN_GPIO_PIN1_PAD_PULL_MASK +#define GPIO_PIN1_PAD_PULL_GET(x) WLAN_GPIO_PIN1_PAD_PULL_GET(x) +#define GPIO_PIN1_PAD_PULL_SET(x) WLAN_GPIO_PIN1_PAD_PULL_SET(x) +#define GPIO_PIN1_PAD_STRENGTH_MSB WLAN_GPIO_PIN1_PAD_STRENGTH_MSB +#define GPIO_PIN1_PAD_STRENGTH_LSB WLAN_GPIO_PIN1_PAD_STRENGTH_LSB +#define GPIO_PIN1_PAD_STRENGTH_MASK WLAN_GPIO_PIN1_PAD_STRENGTH_MASK +#define GPIO_PIN1_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN1_PAD_STRENGTH_GET(x) +#define GPIO_PIN1_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN1_PAD_STRENGTH_SET(x) +#define GPIO_PIN1_PAD_DRIVER_MSB WLAN_GPIO_PIN1_PAD_DRIVER_MSB +#define GPIO_PIN1_PAD_DRIVER_LSB WLAN_GPIO_PIN1_PAD_DRIVER_LSB +#define GPIO_PIN1_PAD_DRIVER_MASK WLAN_GPIO_PIN1_PAD_DRIVER_MASK +#define GPIO_PIN1_PAD_DRIVER_GET(x) WLAN_GPIO_PIN1_PAD_DRIVER_GET(x) +#define GPIO_PIN1_PAD_DRIVER_SET(x) WLAN_GPIO_PIN1_PAD_DRIVER_SET(x) +#define GPIO_PIN1_SOURCE_MSB WLAN_GPIO_PIN1_SOURCE_MSB +#define GPIO_PIN1_SOURCE_LSB WLAN_GPIO_PIN1_SOURCE_LSB +#define GPIO_PIN1_SOURCE_MASK WLAN_GPIO_PIN1_SOURCE_MASK +#define GPIO_PIN1_SOURCE_GET(x) WLAN_GPIO_PIN1_SOURCE_GET(x) +#define GPIO_PIN1_SOURCE_SET(x) WLAN_GPIO_PIN1_SOURCE_SET(x) +#define GPIO_PIN2_ADDRESS WLAN_GPIO_PIN2_ADDRESS +#define GPIO_PIN2_OFFSET WLAN_GPIO_PIN2_OFFSET +#define GPIO_PIN2_CONFIG_MSB WLAN_GPIO_PIN2_CONFIG_MSB +#define GPIO_PIN2_CONFIG_LSB WLAN_GPIO_PIN2_CONFIG_LSB +#define GPIO_PIN2_CONFIG_MASK WLAN_GPIO_PIN2_CONFIG_MASK +#define GPIO_PIN2_CONFIG_GET(x) WLAN_GPIO_PIN2_CONFIG_GET(x) +#define GPIO_PIN2_CONFIG_SET(x) WLAN_GPIO_PIN2_CONFIG_SET(x) +#define GPIO_PIN2_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN2_WAKEUP_ENABLE_MSB +#define GPIO_PIN2_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB +#define GPIO_PIN2_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK +#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN2_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN2_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN2_INT_TYPE_MSB WLAN_GPIO_PIN2_INT_TYPE_MSB +#define GPIO_PIN2_INT_TYPE_LSB WLAN_GPIO_PIN2_INT_TYPE_LSB +#define GPIO_PIN2_INT_TYPE_MASK WLAN_GPIO_PIN2_INT_TYPE_MASK +#define GPIO_PIN2_INT_TYPE_GET(x) WLAN_GPIO_PIN2_INT_TYPE_GET(x) +#define GPIO_PIN2_INT_TYPE_SET(x) WLAN_GPIO_PIN2_INT_TYPE_SET(x) +#define GPIO_PIN2_PAD_PULL_MSB WLAN_GPIO_PIN2_PAD_PULL_MSB +#define GPIO_PIN2_PAD_PULL_LSB WLAN_GPIO_PIN2_PAD_PULL_LSB +#define GPIO_PIN2_PAD_PULL_MASK WLAN_GPIO_PIN2_PAD_PULL_MASK +#define GPIO_PIN2_PAD_PULL_GET(x) WLAN_GPIO_PIN2_PAD_PULL_GET(x) +#define GPIO_PIN2_PAD_PULL_SET(x) WLAN_GPIO_PIN2_PAD_PULL_SET(x) +#define GPIO_PIN2_PAD_STRENGTH_MSB WLAN_GPIO_PIN2_PAD_STRENGTH_MSB +#define GPIO_PIN2_PAD_STRENGTH_LSB WLAN_GPIO_PIN2_PAD_STRENGTH_LSB +#define GPIO_PIN2_PAD_STRENGTH_MASK WLAN_GPIO_PIN2_PAD_STRENGTH_MASK +#define GPIO_PIN2_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN2_PAD_STRENGTH_GET(x) +#define GPIO_PIN2_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN2_PAD_STRENGTH_SET(x) +#define GPIO_PIN2_PAD_DRIVER_MSB WLAN_GPIO_PIN2_PAD_DRIVER_MSB +#define GPIO_PIN2_PAD_DRIVER_LSB WLAN_GPIO_PIN2_PAD_DRIVER_LSB +#define GPIO_PIN2_PAD_DRIVER_MASK WLAN_GPIO_PIN2_PAD_DRIVER_MASK +#define GPIO_PIN2_PAD_DRIVER_GET(x) WLAN_GPIO_PIN2_PAD_DRIVER_GET(x) +#define GPIO_PIN2_PAD_DRIVER_SET(x) WLAN_GPIO_PIN2_PAD_DRIVER_SET(x) +#define GPIO_PIN2_SOURCE_MSB WLAN_GPIO_PIN2_SOURCE_MSB +#define GPIO_PIN2_SOURCE_LSB WLAN_GPIO_PIN2_SOURCE_LSB +#define GPIO_PIN2_SOURCE_MASK WLAN_GPIO_PIN2_SOURCE_MASK +#define GPIO_PIN2_SOURCE_GET(x) WLAN_GPIO_PIN2_SOURCE_GET(x) +#define GPIO_PIN2_SOURCE_SET(x) WLAN_GPIO_PIN2_SOURCE_SET(x) +#define GPIO_PIN3_ADDRESS WLAN_GPIO_PIN3_ADDRESS +#define GPIO_PIN3_OFFSET WLAN_GPIO_PIN3_OFFSET +#define GPIO_PIN3_CONFIG_MSB WLAN_GPIO_PIN3_CONFIG_MSB +#define GPIO_PIN3_CONFIG_LSB WLAN_GPIO_PIN3_CONFIG_LSB +#define GPIO_PIN3_CONFIG_MASK WLAN_GPIO_PIN3_CONFIG_MASK +#define GPIO_PIN3_CONFIG_GET(x) WLAN_GPIO_PIN3_CONFIG_GET(x) +#define GPIO_PIN3_CONFIG_SET(x) WLAN_GPIO_PIN3_CONFIG_SET(x) +#define GPIO_PIN3_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN3_WAKEUP_ENABLE_MSB +#define GPIO_PIN3_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB +#define GPIO_PIN3_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK +#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN3_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN3_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN3_INT_TYPE_MSB WLAN_GPIO_PIN3_INT_TYPE_MSB +#define GPIO_PIN3_INT_TYPE_LSB WLAN_GPIO_PIN3_INT_TYPE_LSB +#define GPIO_PIN3_INT_TYPE_MASK WLAN_GPIO_PIN3_INT_TYPE_MASK +#define GPIO_PIN3_INT_TYPE_GET(x) WLAN_GPIO_PIN3_INT_TYPE_GET(x) +#define GPIO_PIN3_INT_TYPE_SET(x) WLAN_GPIO_PIN3_INT_TYPE_SET(x) +#define GPIO_PIN3_PAD_PULL_MSB WLAN_GPIO_PIN3_PAD_PULL_MSB +#define GPIO_PIN3_PAD_PULL_LSB WLAN_GPIO_PIN3_PAD_PULL_LSB +#define GPIO_PIN3_PAD_PULL_MASK WLAN_GPIO_PIN3_PAD_PULL_MASK +#define GPIO_PIN3_PAD_PULL_GET(x) WLAN_GPIO_PIN3_PAD_PULL_GET(x) +#define GPIO_PIN3_PAD_PULL_SET(x) WLAN_GPIO_PIN3_PAD_PULL_SET(x) +#define GPIO_PIN3_PAD_STRENGTH_MSB WLAN_GPIO_PIN3_PAD_STRENGTH_MSB +#define GPIO_PIN3_PAD_STRENGTH_LSB WLAN_GPIO_PIN3_PAD_STRENGTH_LSB +#define GPIO_PIN3_PAD_STRENGTH_MASK WLAN_GPIO_PIN3_PAD_STRENGTH_MASK +#define GPIO_PIN3_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN3_PAD_STRENGTH_GET(x) +#define GPIO_PIN3_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN3_PAD_STRENGTH_SET(x) +#define GPIO_PIN3_PAD_DRIVER_MSB WLAN_GPIO_PIN3_PAD_DRIVER_MSB +#define GPIO_PIN3_PAD_DRIVER_LSB WLAN_GPIO_PIN3_PAD_DRIVER_LSB +#define GPIO_PIN3_PAD_DRIVER_MASK WLAN_GPIO_PIN3_PAD_DRIVER_MASK +#define GPIO_PIN3_PAD_DRIVER_GET(x) WLAN_GPIO_PIN3_PAD_DRIVER_GET(x) +#define GPIO_PIN3_PAD_DRIVER_SET(x) WLAN_GPIO_PIN3_PAD_DRIVER_SET(x) +#define GPIO_PIN3_SOURCE_MSB WLAN_GPIO_PIN3_SOURCE_MSB +#define GPIO_PIN3_SOURCE_LSB WLAN_GPIO_PIN3_SOURCE_LSB +#define GPIO_PIN3_SOURCE_MASK WLAN_GPIO_PIN3_SOURCE_MASK +#define GPIO_PIN3_SOURCE_GET(x) WLAN_GPIO_PIN3_SOURCE_GET(x) +#define GPIO_PIN3_SOURCE_SET(x) WLAN_GPIO_PIN3_SOURCE_SET(x) +#define GPIO_PIN4_ADDRESS WLAN_GPIO_PIN4_ADDRESS +#define GPIO_PIN4_OFFSET WLAN_GPIO_PIN4_OFFSET +#define GPIO_PIN4_CONFIG_MSB WLAN_GPIO_PIN4_CONFIG_MSB +#define GPIO_PIN4_CONFIG_LSB WLAN_GPIO_PIN4_CONFIG_LSB +#define GPIO_PIN4_CONFIG_MASK WLAN_GPIO_PIN4_CONFIG_MASK +#define GPIO_PIN4_CONFIG_GET(x) WLAN_GPIO_PIN4_CONFIG_GET(x) +#define GPIO_PIN4_CONFIG_SET(x) WLAN_GPIO_PIN4_CONFIG_SET(x) +#define GPIO_PIN4_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN4_WAKEUP_ENABLE_MSB +#define GPIO_PIN4_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB +#define GPIO_PIN4_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK +#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN4_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN4_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN4_INT_TYPE_MSB WLAN_GPIO_PIN4_INT_TYPE_MSB +#define GPIO_PIN4_INT_TYPE_LSB WLAN_GPIO_PIN4_INT_TYPE_LSB +#define GPIO_PIN4_INT_TYPE_MASK WLAN_GPIO_PIN4_INT_TYPE_MASK +#define GPIO_PIN4_INT_TYPE_GET(x) WLAN_GPIO_PIN4_INT_TYPE_GET(x) +#define GPIO_PIN4_INT_TYPE_SET(x) WLAN_GPIO_PIN4_INT_TYPE_SET(x) +#define GPIO_PIN4_PAD_PULL_MSB WLAN_GPIO_PIN4_PAD_PULL_MSB +#define GPIO_PIN4_PAD_PULL_LSB WLAN_GPIO_PIN4_PAD_PULL_LSB +#define GPIO_PIN4_PAD_PULL_MASK WLAN_GPIO_PIN4_PAD_PULL_MASK +#define GPIO_PIN4_PAD_PULL_GET(x) WLAN_GPIO_PIN4_PAD_PULL_GET(x) +#define GPIO_PIN4_PAD_PULL_SET(x) WLAN_GPIO_PIN4_PAD_PULL_SET(x) +#define GPIO_PIN4_PAD_STRENGTH_MSB WLAN_GPIO_PIN4_PAD_STRENGTH_MSB +#define GPIO_PIN4_PAD_STRENGTH_LSB WLAN_GPIO_PIN4_PAD_STRENGTH_LSB +#define GPIO_PIN4_PAD_STRENGTH_MASK WLAN_GPIO_PIN4_PAD_STRENGTH_MASK +#define GPIO_PIN4_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN4_PAD_STRENGTH_GET(x) +#define GPIO_PIN4_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN4_PAD_STRENGTH_SET(x) +#define GPIO_PIN4_PAD_DRIVER_MSB WLAN_GPIO_PIN4_PAD_DRIVER_MSB +#define GPIO_PIN4_PAD_DRIVER_LSB WLAN_GPIO_PIN4_PAD_DRIVER_LSB +#define GPIO_PIN4_PAD_DRIVER_MASK WLAN_GPIO_PIN4_PAD_DRIVER_MASK +#define GPIO_PIN4_PAD_DRIVER_GET(x) WLAN_GPIO_PIN4_PAD_DRIVER_GET(x) +#define GPIO_PIN4_PAD_DRIVER_SET(x) WLAN_GPIO_PIN4_PAD_DRIVER_SET(x) +#define GPIO_PIN4_SOURCE_MSB WLAN_GPIO_PIN4_SOURCE_MSB +#define GPIO_PIN4_SOURCE_LSB WLAN_GPIO_PIN4_SOURCE_LSB +#define GPIO_PIN4_SOURCE_MASK WLAN_GPIO_PIN4_SOURCE_MASK +#define GPIO_PIN4_SOURCE_GET(x) WLAN_GPIO_PIN4_SOURCE_GET(x) +#define GPIO_PIN4_SOURCE_SET(x) WLAN_GPIO_PIN4_SOURCE_SET(x) +#define GPIO_PIN5_ADDRESS WLAN_GPIO_PIN5_ADDRESS +#define GPIO_PIN5_OFFSET WLAN_GPIO_PIN5_OFFSET +#define GPIO_PIN5_CONFIG_MSB WLAN_GPIO_PIN5_CONFIG_MSB +#define GPIO_PIN5_CONFIG_LSB WLAN_GPIO_PIN5_CONFIG_LSB +#define GPIO_PIN5_CONFIG_MASK WLAN_GPIO_PIN5_CONFIG_MASK +#define GPIO_PIN5_CONFIG_GET(x) WLAN_GPIO_PIN5_CONFIG_GET(x) +#define GPIO_PIN5_CONFIG_SET(x) WLAN_GPIO_PIN5_CONFIG_SET(x) +#define GPIO_PIN5_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN5_WAKEUP_ENABLE_MSB +#define GPIO_PIN5_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB +#define GPIO_PIN5_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK +#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN5_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN5_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN5_INT_TYPE_MSB WLAN_GPIO_PIN5_INT_TYPE_MSB +#define GPIO_PIN5_INT_TYPE_LSB WLAN_GPIO_PIN5_INT_TYPE_LSB +#define GPIO_PIN5_INT_TYPE_MASK WLAN_GPIO_PIN5_INT_TYPE_MASK +#define GPIO_PIN5_INT_TYPE_GET(x) WLAN_GPIO_PIN5_INT_TYPE_GET(x) +#define GPIO_PIN5_INT_TYPE_SET(x) WLAN_GPIO_PIN5_INT_TYPE_SET(x) +#define GPIO_PIN5_PAD_PULL_MSB WLAN_GPIO_PIN5_PAD_PULL_MSB +#define GPIO_PIN5_PAD_PULL_LSB WLAN_GPIO_PIN5_PAD_PULL_LSB +#define GPIO_PIN5_PAD_PULL_MASK WLAN_GPIO_PIN5_PAD_PULL_MASK +#define GPIO_PIN5_PAD_PULL_GET(x) WLAN_GPIO_PIN5_PAD_PULL_GET(x) +#define GPIO_PIN5_PAD_PULL_SET(x) WLAN_GPIO_PIN5_PAD_PULL_SET(x) +#define GPIO_PIN5_PAD_STRENGTH_MSB WLAN_GPIO_PIN5_PAD_STRENGTH_MSB +#define GPIO_PIN5_PAD_STRENGTH_LSB WLAN_GPIO_PIN5_PAD_STRENGTH_LSB +#define GPIO_PIN5_PAD_STRENGTH_MASK WLAN_GPIO_PIN5_PAD_STRENGTH_MASK +#define GPIO_PIN5_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN5_PAD_STRENGTH_GET(x) +#define GPIO_PIN5_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN5_PAD_STRENGTH_SET(x) +#define GPIO_PIN5_PAD_DRIVER_MSB WLAN_GPIO_PIN5_PAD_DRIVER_MSB +#define GPIO_PIN5_PAD_DRIVER_LSB WLAN_GPIO_PIN5_PAD_DRIVER_LSB +#define GPIO_PIN5_PAD_DRIVER_MASK WLAN_GPIO_PIN5_PAD_DRIVER_MASK +#define GPIO_PIN5_PAD_DRIVER_GET(x) WLAN_GPIO_PIN5_PAD_DRIVER_GET(x) +#define GPIO_PIN5_PAD_DRIVER_SET(x) WLAN_GPIO_PIN5_PAD_DRIVER_SET(x) +#define GPIO_PIN5_SOURCE_MSB WLAN_GPIO_PIN5_SOURCE_MSB +#define GPIO_PIN5_SOURCE_LSB WLAN_GPIO_PIN5_SOURCE_LSB +#define GPIO_PIN5_SOURCE_MASK WLAN_GPIO_PIN5_SOURCE_MASK +#define GPIO_PIN5_SOURCE_GET(x) WLAN_GPIO_PIN5_SOURCE_GET(x) +#define GPIO_PIN5_SOURCE_SET(x) WLAN_GPIO_PIN5_SOURCE_SET(x) +#define GPIO_PIN6_ADDRESS WLAN_GPIO_PIN6_ADDRESS +#define GPIO_PIN6_OFFSET WLAN_GPIO_PIN6_OFFSET +#define GPIO_PIN6_CONFIG_MSB WLAN_GPIO_PIN6_CONFIG_MSB +#define GPIO_PIN6_CONFIG_LSB WLAN_GPIO_PIN6_CONFIG_LSB +#define GPIO_PIN6_CONFIG_MASK WLAN_GPIO_PIN6_CONFIG_MASK +#define GPIO_PIN6_CONFIG_GET(x) WLAN_GPIO_PIN6_CONFIG_GET(x) +#define GPIO_PIN6_CONFIG_SET(x) WLAN_GPIO_PIN6_CONFIG_SET(x) +#define GPIO_PIN6_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN6_WAKEUP_ENABLE_MSB +#define GPIO_PIN6_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB +#define GPIO_PIN6_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK +#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN6_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN6_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN6_INT_TYPE_MSB WLAN_GPIO_PIN6_INT_TYPE_MSB +#define GPIO_PIN6_INT_TYPE_LSB WLAN_GPIO_PIN6_INT_TYPE_LSB +#define GPIO_PIN6_INT_TYPE_MASK WLAN_GPIO_PIN6_INT_TYPE_MASK +#define GPIO_PIN6_INT_TYPE_GET(x) WLAN_GPIO_PIN6_INT_TYPE_GET(x) +#define GPIO_PIN6_INT_TYPE_SET(x) WLAN_GPIO_PIN6_INT_TYPE_SET(x) +#define GPIO_PIN6_PAD_PULL_MSB WLAN_GPIO_PIN6_PAD_PULL_MSB +#define GPIO_PIN6_PAD_PULL_LSB WLAN_GPIO_PIN6_PAD_PULL_LSB +#define GPIO_PIN6_PAD_PULL_MASK WLAN_GPIO_PIN6_PAD_PULL_MASK +#define GPIO_PIN6_PAD_PULL_GET(x) WLAN_GPIO_PIN6_PAD_PULL_GET(x) +#define GPIO_PIN6_PAD_PULL_SET(x) WLAN_GPIO_PIN6_PAD_PULL_SET(x) +#define GPIO_PIN6_PAD_STRENGTH_MSB WLAN_GPIO_PIN6_PAD_STRENGTH_MSB +#define GPIO_PIN6_PAD_STRENGTH_LSB WLAN_GPIO_PIN6_PAD_STRENGTH_LSB +#define GPIO_PIN6_PAD_STRENGTH_MASK WLAN_GPIO_PIN6_PAD_STRENGTH_MASK +#define GPIO_PIN6_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN6_PAD_STRENGTH_GET(x) +#define GPIO_PIN6_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN6_PAD_STRENGTH_SET(x) +#define GPIO_PIN6_PAD_DRIVER_MSB WLAN_GPIO_PIN6_PAD_DRIVER_MSB +#define GPIO_PIN6_PAD_DRIVER_LSB WLAN_GPIO_PIN6_PAD_DRIVER_LSB +#define GPIO_PIN6_PAD_DRIVER_MASK WLAN_GPIO_PIN6_PAD_DRIVER_MASK +#define GPIO_PIN6_PAD_DRIVER_GET(x) WLAN_GPIO_PIN6_PAD_DRIVER_GET(x) +#define GPIO_PIN6_PAD_DRIVER_SET(x) WLAN_GPIO_PIN6_PAD_DRIVER_SET(x) +#define GPIO_PIN6_SOURCE_MSB WLAN_GPIO_PIN6_SOURCE_MSB +#define GPIO_PIN6_SOURCE_LSB WLAN_GPIO_PIN6_SOURCE_LSB +#define GPIO_PIN6_SOURCE_MASK WLAN_GPIO_PIN6_SOURCE_MASK +#define GPIO_PIN6_SOURCE_GET(x) WLAN_GPIO_PIN6_SOURCE_GET(x) +#define GPIO_PIN6_SOURCE_SET(x) WLAN_GPIO_PIN6_SOURCE_SET(x) +#define GPIO_PIN7_ADDRESS WLAN_GPIO_PIN7_ADDRESS +#define GPIO_PIN7_OFFSET WLAN_GPIO_PIN7_OFFSET +#define GPIO_PIN7_CONFIG_MSB WLAN_GPIO_PIN7_CONFIG_MSB +#define GPIO_PIN7_CONFIG_LSB WLAN_GPIO_PIN7_CONFIG_LSB +#define GPIO_PIN7_CONFIG_MASK WLAN_GPIO_PIN7_CONFIG_MASK +#define GPIO_PIN7_CONFIG_GET(x) WLAN_GPIO_PIN7_CONFIG_GET(x) +#define GPIO_PIN7_CONFIG_SET(x) WLAN_GPIO_PIN7_CONFIG_SET(x) +#define GPIO_PIN7_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN7_WAKEUP_ENABLE_MSB +#define GPIO_PIN7_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB +#define GPIO_PIN7_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK +#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN7_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN7_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN7_INT_TYPE_MSB WLAN_GPIO_PIN7_INT_TYPE_MSB +#define GPIO_PIN7_INT_TYPE_LSB WLAN_GPIO_PIN7_INT_TYPE_LSB +#define GPIO_PIN7_INT_TYPE_MASK WLAN_GPIO_PIN7_INT_TYPE_MASK +#define GPIO_PIN7_INT_TYPE_GET(x) WLAN_GPIO_PIN7_INT_TYPE_GET(x) +#define GPIO_PIN7_INT_TYPE_SET(x) WLAN_GPIO_PIN7_INT_TYPE_SET(x) +#define GPIO_PIN7_PAD_PULL_MSB WLAN_GPIO_PIN7_PAD_PULL_MSB +#define GPIO_PIN7_PAD_PULL_LSB WLAN_GPIO_PIN7_PAD_PULL_LSB +#define GPIO_PIN7_PAD_PULL_MASK WLAN_GPIO_PIN7_PAD_PULL_MASK +#define GPIO_PIN7_PAD_PULL_GET(x) WLAN_GPIO_PIN7_PAD_PULL_GET(x) +#define GPIO_PIN7_PAD_PULL_SET(x) WLAN_GPIO_PIN7_PAD_PULL_SET(x) +#define GPIO_PIN7_PAD_STRENGTH_MSB WLAN_GPIO_PIN7_PAD_STRENGTH_MSB +#define GPIO_PIN7_PAD_STRENGTH_LSB WLAN_GPIO_PIN7_PAD_STRENGTH_LSB +#define GPIO_PIN7_PAD_STRENGTH_MASK WLAN_GPIO_PIN7_PAD_STRENGTH_MASK +#define GPIO_PIN7_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN7_PAD_STRENGTH_GET(x) +#define GPIO_PIN7_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN7_PAD_STRENGTH_SET(x) +#define GPIO_PIN7_PAD_DRIVER_MSB WLAN_GPIO_PIN7_PAD_DRIVER_MSB +#define GPIO_PIN7_PAD_DRIVER_LSB WLAN_GPIO_PIN7_PAD_DRIVER_LSB +#define GPIO_PIN7_PAD_DRIVER_MASK WLAN_GPIO_PIN7_PAD_DRIVER_MASK +#define GPIO_PIN7_PAD_DRIVER_GET(x) WLAN_GPIO_PIN7_PAD_DRIVER_GET(x) +#define GPIO_PIN7_PAD_DRIVER_SET(x) WLAN_GPIO_PIN7_PAD_DRIVER_SET(x) +#define GPIO_PIN7_SOURCE_MSB WLAN_GPIO_PIN7_SOURCE_MSB +#define GPIO_PIN7_SOURCE_LSB WLAN_GPIO_PIN7_SOURCE_LSB +#define GPIO_PIN7_SOURCE_MASK WLAN_GPIO_PIN7_SOURCE_MASK +#define GPIO_PIN7_SOURCE_GET(x) WLAN_GPIO_PIN7_SOURCE_GET(x) +#define GPIO_PIN7_SOURCE_SET(x) WLAN_GPIO_PIN7_SOURCE_SET(x) +#define GPIO_PIN8_ADDRESS WLAN_GPIO_PIN8_ADDRESS +#define GPIO_PIN8_OFFSET WLAN_GPIO_PIN8_OFFSET +#define GPIO_PIN8_CONFIG_MSB WLAN_GPIO_PIN8_CONFIG_MSB +#define GPIO_PIN8_CONFIG_LSB WLAN_GPIO_PIN8_CONFIG_LSB +#define GPIO_PIN8_CONFIG_MASK WLAN_GPIO_PIN8_CONFIG_MASK +#define GPIO_PIN8_CONFIG_GET(x) WLAN_GPIO_PIN8_CONFIG_GET(x) +#define GPIO_PIN8_CONFIG_SET(x) WLAN_GPIO_PIN8_CONFIG_SET(x) +#define GPIO_PIN8_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN8_WAKEUP_ENABLE_MSB +#define GPIO_PIN8_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB +#define GPIO_PIN8_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK +#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN8_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN8_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN8_INT_TYPE_MSB WLAN_GPIO_PIN8_INT_TYPE_MSB +#define GPIO_PIN8_INT_TYPE_LSB WLAN_GPIO_PIN8_INT_TYPE_LSB +#define GPIO_PIN8_INT_TYPE_MASK WLAN_GPIO_PIN8_INT_TYPE_MASK +#define GPIO_PIN8_INT_TYPE_GET(x) WLAN_GPIO_PIN8_INT_TYPE_GET(x) +#define GPIO_PIN8_INT_TYPE_SET(x) WLAN_GPIO_PIN8_INT_TYPE_SET(x) +#define GPIO_PIN8_PAD_PULL_MSB WLAN_GPIO_PIN8_PAD_PULL_MSB +#define GPIO_PIN8_PAD_PULL_LSB WLAN_GPIO_PIN8_PAD_PULL_LSB +#define GPIO_PIN8_PAD_PULL_MASK WLAN_GPIO_PIN8_PAD_PULL_MASK +#define GPIO_PIN8_PAD_PULL_GET(x) WLAN_GPIO_PIN8_PAD_PULL_GET(x) +#define GPIO_PIN8_PAD_PULL_SET(x) WLAN_GPIO_PIN8_PAD_PULL_SET(x) +#define GPIO_PIN8_PAD_STRENGTH_MSB WLAN_GPIO_PIN8_PAD_STRENGTH_MSB +#define GPIO_PIN8_PAD_STRENGTH_LSB WLAN_GPIO_PIN8_PAD_STRENGTH_LSB +#define GPIO_PIN8_PAD_STRENGTH_MASK WLAN_GPIO_PIN8_PAD_STRENGTH_MASK +#define GPIO_PIN8_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN8_PAD_STRENGTH_GET(x) +#define GPIO_PIN8_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN8_PAD_STRENGTH_SET(x) +#define GPIO_PIN8_PAD_DRIVER_MSB WLAN_GPIO_PIN8_PAD_DRIVER_MSB +#define GPIO_PIN8_PAD_DRIVER_LSB WLAN_GPIO_PIN8_PAD_DRIVER_LSB +#define GPIO_PIN8_PAD_DRIVER_MASK WLAN_GPIO_PIN8_PAD_DRIVER_MASK +#define GPIO_PIN8_PAD_DRIVER_GET(x) WLAN_GPIO_PIN8_PAD_DRIVER_GET(x) +#define GPIO_PIN8_PAD_DRIVER_SET(x) WLAN_GPIO_PIN8_PAD_DRIVER_SET(x) +#define GPIO_PIN8_SOURCE_MSB WLAN_GPIO_PIN8_SOURCE_MSB +#define GPIO_PIN8_SOURCE_LSB WLAN_GPIO_PIN8_SOURCE_LSB +#define GPIO_PIN8_SOURCE_MASK WLAN_GPIO_PIN8_SOURCE_MASK +#define GPIO_PIN8_SOURCE_GET(x) WLAN_GPIO_PIN8_SOURCE_GET(x) +#define GPIO_PIN8_SOURCE_SET(x) WLAN_GPIO_PIN8_SOURCE_SET(x) +#define GPIO_PIN9_ADDRESS WLAN_GPIO_PIN9_ADDRESS +#define GPIO_PIN9_OFFSET WLAN_GPIO_PIN9_OFFSET +#define GPIO_PIN9_CONFIG_MSB WLAN_GPIO_PIN9_CONFIG_MSB +#define GPIO_PIN9_CONFIG_LSB WLAN_GPIO_PIN9_CONFIG_LSB +#define GPIO_PIN9_CONFIG_MASK WLAN_GPIO_PIN9_CONFIG_MASK +#define GPIO_PIN9_CONFIG_GET(x) WLAN_GPIO_PIN9_CONFIG_GET(x) +#define GPIO_PIN9_CONFIG_SET(x) WLAN_GPIO_PIN9_CONFIG_SET(x) +#define GPIO_PIN9_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN9_WAKEUP_ENABLE_MSB +#define GPIO_PIN9_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB +#define GPIO_PIN9_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK +#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN9_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN9_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN9_INT_TYPE_MSB WLAN_GPIO_PIN9_INT_TYPE_MSB +#define GPIO_PIN9_INT_TYPE_LSB WLAN_GPIO_PIN9_INT_TYPE_LSB +#define GPIO_PIN9_INT_TYPE_MASK WLAN_GPIO_PIN9_INT_TYPE_MASK +#define GPIO_PIN9_INT_TYPE_GET(x) WLAN_GPIO_PIN9_INT_TYPE_GET(x) +#define GPIO_PIN9_INT_TYPE_SET(x) WLAN_GPIO_PIN9_INT_TYPE_SET(x) +#define GPIO_PIN9_PAD_PULL_MSB WLAN_GPIO_PIN9_PAD_PULL_MSB +#define GPIO_PIN9_PAD_PULL_LSB WLAN_GPIO_PIN9_PAD_PULL_LSB +#define GPIO_PIN9_PAD_PULL_MASK WLAN_GPIO_PIN9_PAD_PULL_MASK +#define GPIO_PIN9_PAD_PULL_GET(x) WLAN_GPIO_PIN9_PAD_PULL_GET(x) +#define GPIO_PIN9_PAD_PULL_SET(x) WLAN_GPIO_PIN9_PAD_PULL_SET(x) +#define GPIO_PIN9_PAD_STRENGTH_MSB WLAN_GPIO_PIN9_PAD_STRENGTH_MSB +#define GPIO_PIN9_PAD_STRENGTH_LSB WLAN_GPIO_PIN9_PAD_STRENGTH_LSB +#define GPIO_PIN9_PAD_STRENGTH_MASK WLAN_GPIO_PIN9_PAD_STRENGTH_MASK +#define GPIO_PIN9_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN9_PAD_STRENGTH_GET(x) +#define GPIO_PIN9_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN9_PAD_STRENGTH_SET(x) +#define GPIO_PIN9_PAD_DRIVER_MSB WLAN_GPIO_PIN9_PAD_DRIVER_MSB +#define GPIO_PIN9_PAD_DRIVER_LSB WLAN_GPIO_PIN9_PAD_DRIVER_LSB +#define GPIO_PIN9_PAD_DRIVER_MASK WLAN_GPIO_PIN9_PAD_DRIVER_MASK +#define GPIO_PIN9_PAD_DRIVER_GET(x) WLAN_GPIO_PIN9_PAD_DRIVER_GET(x) +#define GPIO_PIN9_PAD_DRIVER_SET(x) WLAN_GPIO_PIN9_PAD_DRIVER_SET(x) +#define GPIO_PIN9_SOURCE_MSB WLAN_GPIO_PIN9_SOURCE_MSB +#define GPIO_PIN9_SOURCE_LSB WLAN_GPIO_PIN9_SOURCE_LSB +#define GPIO_PIN9_SOURCE_MASK WLAN_GPIO_PIN9_SOURCE_MASK +#define GPIO_PIN9_SOURCE_GET(x) WLAN_GPIO_PIN9_SOURCE_GET(x) +#define GPIO_PIN9_SOURCE_SET(x) WLAN_GPIO_PIN9_SOURCE_SET(x) +#define GPIO_PIN10_ADDRESS WLAN_GPIO_PIN10_ADDRESS +#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_OFFSET +#define GPIO_PIN10_CONFIG_MSB WLAN_GPIO_PIN10_CONFIG_MSB +#define GPIO_PIN10_CONFIG_LSB WLAN_GPIO_PIN10_CONFIG_LSB +#define GPIO_PIN10_CONFIG_MASK WLAN_GPIO_PIN10_CONFIG_MASK +#define GPIO_PIN10_CONFIG_GET(x) WLAN_GPIO_PIN10_CONFIG_GET(x) +#define GPIO_PIN10_CONFIG_SET(x) WLAN_GPIO_PIN10_CONFIG_SET(x) +#define GPIO_PIN10_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN10_WAKEUP_ENABLE_MSB +#define GPIO_PIN10_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB +#define GPIO_PIN10_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK +#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN10_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN10_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN10_INT_TYPE_MSB WLAN_GPIO_PIN10_INT_TYPE_MSB +#define GPIO_PIN10_INT_TYPE_LSB WLAN_GPIO_PIN10_INT_TYPE_LSB +#define GPIO_PIN10_INT_TYPE_MASK WLAN_GPIO_PIN10_INT_TYPE_MASK +#define GPIO_PIN10_INT_TYPE_GET(x) WLAN_GPIO_PIN10_INT_TYPE_GET(x) +#define GPIO_PIN10_INT_TYPE_SET(x) WLAN_GPIO_PIN10_INT_TYPE_SET(x) +#define GPIO_PIN10_PAD_PULL_MSB WLAN_GPIO_PIN10_PAD_PULL_MSB +#define GPIO_PIN10_PAD_PULL_LSB WLAN_GPIO_PIN10_PAD_PULL_LSB +#define GPIO_PIN10_PAD_PULL_MASK WLAN_GPIO_PIN10_PAD_PULL_MASK +#define GPIO_PIN10_PAD_PULL_GET(x) WLAN_GPIO_PIN10_PAD_PULL_GET(x) +#define GPIO_PIN10_PAD_PULL_SET(x) WLAN_GPIO_PIN10_PAD_PULL_SET(x) +#define GPIO_PIN10_PAD_STRENGTH_MSB WLAN_GPIO_PIN10_PAD_STRENGTH_MSB +#define GPIO_PIN10_PAD_STRENGTH_LSB WLAN_GPIO_PIN10_PAD_STRENGTH_LSB +#define GPIO_PIN10_PAD_STRENGTH_MASK WLAN_GPIO_PIN10_PAD_STRENGTH_MASK +#define GPIO_PIN10_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN10_PAD_STRENGTH_GET(x) +#define GPIO_PIN10_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN10_PAD_STRENGTH_SET(x) +#define GPIO_PIN10_PAD_DRIVER_MSB WLAN_GPIO_PIN10_PAD_DRIVER_MSB +#define GPIO_PIN10_PAD_DRIVER_LSB WLAN_GPIO_PIN10_PAD_DRIVER_LSB +#define GPIO_PIN10_PAD_DRIVER_MASK WLAN_GPIO_PIN10_PAD_DRIVER_MASK +#define GPIO_PIN10_PAD_DRIVER_GET(x) WLAN_GPIO_PIN10_PAD_DRIVER_GET(x) +#define GPIO_PIN10_PAD_DRIVER_SET(x) WLAN_GPIO_PIN10_PAD_DRIVER_SET(x) +#define GPIO_PIN10_SOURCE_MSB WLAN_GPIO_PIN10_SOURCE_MSB +#define GPIO_PIN10_SOURCE_LSB WLAN_GPIO_PIN10_SOURCE_LSB +#define GPIO_PIN10_SOURCE_MASK WLAN_GPIO_PIN10_SOURCE_MASK +#define GPIO_PIN10_SOURCE_GET(x) WLAN_GPIO_PIN10_SOURCE_GET(x) +#define GPIO_PIN10_SOURCE_SET(x) WLAN_GPIO_PIN10_SOURCE_SET(x) +#define GPIO_PIN11_ADDRESS WLAN_GPIO_PIN11_ADDRESS +#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_OFFSET +#define GPIO_PIN11_CONFIG_MSB WLAN_GPIO_PIN11_CONFIG_MSB +#define GPIO_PIN11_CONFIG_LSB WLAN_GPIO_PIN11_CONFIG_LSB +#define GPIO_PIN11_CONFIG_MASK WLAN_GPIO_PIN11_CONFIG_MASK +#define GPIO_PIN11_CONFIG_GET(x) WLAN_GPIO_PIN11_CONFIG_GET(x) +#define GPIO_PIN11_CONFIG_SET(x) WLAN_GPIO_PIN11_CONFIG_SET(x) +#define GPIO_PIN11_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN11_WAKEUP_ENABLE_MSB +#define GPIO_PIN11_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB +#define GPIO_PIN11_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK +#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN11_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN11_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN11_INT_TYPE_MSB WLAN_GPIO_PIN11_INT_TYPE_MSB +#define GPIO_PIN11_INT_TYPE_LSB WLAN_GPIO_PIN11_INT_TYPE_LSB +#define GPIO_PIN11_INT_TYPE_MASK WLAN_GPIO_PIN11_INT_TYPE_MASK +#define GPIO_PIN11_INT_TYPE_GET(x) WLAN_GPIO_PIN11_INT_TYPE_GET(x) +#define GPIO_PIN11_INT_TYPE_SET(x) WLAN_GPIO_PIN11_INT_TYPE_SET(x) +#define GPIO_PIN11_PAD_PULL_MSB WLAN_GPIO_PIN11_PAD_PULL_MSB +#define GPIO_PIN11_PAD_PULL_LSB WLAN_GPIO_PIN11_PAD_PULL_LSB +#define GPIO_PIN11_PAD_PULL_MASK WLAN_GPIO_PIN11_PAD_PULL_MASK +#define GPIO_PIN11_PAD_PULL_GET(x) WLAN_GPIO_PIN11_PAD_PULL_GET(x) +#define GPIO_PIN11_PAD_PULL_SET(x) WLAN_GPIO_PIN11_PAD_PULL_SET(x) +#define GPIO_PIN11_PAD_STRENGTH_MSB WLAN_GPIO_PIN11_PAD_STRENGTH_MSB +#define GPIO_PIN11_PAD_STRENGTH_LSB WLAN_GPIO_PIN11_PAD_STRENGTH_LSB +#define GPIO_PIN11_PAD_STRENGTH_MASK WLAN_GPIO_PIN11_PAD_STRENGTH_MASK +#define GPIO_PIN11_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN11_PAD_STRENGTH_GET(x) +#define GPIO_PIN11_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN11_PAD_STRENGTH_SET(x) +#define GPIO_PIN11_PAD_DRIVER_MSB WLAN_GPIO_PIN11_PAD_DRIVER_MSB +#define GPIO_PIN11_PAD_DRIVER_LSB WLAN_GPIO_PIN11_PAD_DRIVER_LSB +#define GPIO_PIN11_PAD_DRIVER_MASK WLAN_GPIO_PIN11_PAD_DRIVER_MASK +#define GPIO_PIN11_PAD_DRIVER_GET(x) WLAN_GPIO_PIN11_PAD_DRIVER_GET(x) +#define GPIO_PIN11_PAD_DRIVER_SET(x) WLAN_GPIO_PIN11_PAD_DRIVER_SET(x) +#define GPIO_PIN11_SOURCE_MSB WLAN_GPIO_PIN11_SOURCE_MSB +#define GPIO_PIN11_SOURCE_LSB WLAN_GPIO_PIN11_SOURCE_LSB +#define GPIO_PIN11_SOURCE_MASK WLAN_GPIO_PIN11_SOURCE_MASK +#define GPIO_PIN11_SOURCE_GET(x) WLAN_GPIO_PIN11_SOURCE_GET(x) +#define GPIO_PIN11_SOURCE_SET(x) WLAN_GPIO_PIN11_SOURCE_SET(x) +#define GPIO_PIN12_ADDRESS WLAN_GPIO_PIN12_ADDRESS +#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_OFFSET +#define GPIO_PIN12_CONFIG_MSB WLAN_GPIO_PIN12_CONFIG_MSB +#define GPIO_PIN12_CONFIG_LSB WLAN_GPIO_PIN12_CONFIG_LSB +#define GPIO_PIN12_CONFIG_MASK WLAN_GPIO_PIN12_CONFIG_MASK +#define GPIO_PIN12_CONFIG_GET(x) WLAN_GPIO_PIN12_CONFIG_GET(x) +#define GPIO_PIN12_CONFIG_SET(x) WLAN_GPIO_PIN12_CONFIG_SET(x) +#define GPIO_PIN12_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN12_WAKEUP_ENABLE_MSB +#define GPIO_PIN12_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB +#define GPIO_PIN12_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK +#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN12_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN12_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN12_INT_TYPE_MSB WLAN_GPIO_PIN12_INT_TYPE_MSB +#define GPIO_PIN12_INT_TYPE_LSB WLAN_GPIO_PIN12_INT_TYPE_LSB +#define GPIO_PIN12_INT_TYPE_MASK WLAN_GPIO_PIN12_INT_TYPE_MASK +#define GPIO_PIN12_INT_TYPE_GET(x) WLAN_GPIO_PIN12_INT_TYPE_GET(x) +#define GPIO_PIN12_INT_TYPE_SET(x) WLAN_GPIO_PIN12_INT_TYPE_SET(x) +#define GPIO_PIN12_PAD_PULL_MSB WLAN_GPIO_PIN12_PAD_PULL_MSB +#define GPIO_PIN12_PAD_PULL_LSB WLAN_GPIO_PIN12_PAD_PULL_LSB +#define GPIO_PIN12_PAD_PULL_MASK WLAN_GPIO_PIN12_PAD_PULL_MASK +#define GPIO_PIN12_PAD_PULL_GET(x) WLAN_GPIO_PIN12_PAD_PULL_GET(x) +#define GPIO_PIN12_PAD_PULL_SET(x) WLAN_GPIO_PIN12_PAD_PULL_SET(x) +#define GPIO_PIN12_PAD_STRENGTH_MSB WLAN_GPIO_PIN12_PAD_STRENGTH_MSB +#define GPIO_PIN12_PAD_STRENGTH_LSB WLAN_GPIO_PIN12_PAD_STRENGTH_LSB +#define GPIO_PIN12_PAD_STRENGTH_MASK WLAN_GPIO_PIN12_PAD_STRENGTH_MASK +#define GPIO_PIN12_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN12_PAD_STRENGTH_GET(x) +#define GPIO_PIN12_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN12_PAD_STRENGTH_SET(x) +#define GPIO_PIN12_PAD_DRIVER_MSB WLAN_GPIO_PIN12_PAD_DRIVER_MSB +#define GPIO_PIN12_PAD_DRIVER_LSB WLAN_GPIO_PIN12_PAD_DRIVER_LSB +#define GPIO_PIN12_PAD_DRIVER_MASK WLAN_GPIO_PIN12_PAD_DRIVER_MASK +#define GPIO_PIN12_PAD_DRIVER_GET(x) WLAN_GPIO_PIN12_PAD_DRIVER_GET(x) +#define GPIO_PIN12_PAD_DRIVER_SET(x) WLAN_GPIO_PIN12_PAD_DRIVER_SET(x) +#define GPIO_PIN12_SOURCE_MSB WLAN_GPIO_PIN12_SOURCE_MSB +#define GPIO_PIN12_SOURCE_LSB WLAN_GPIO_PIN12_SOURCE_LSB +#define GPIO_PIN12_SOURCE_MASK WLAN_GPIO_PIN12_SOURCE_MASK +#define GPIO_PIN12_SOURCE_GET(x) WLAN_GPIO_PIN12_SOURCE_GET(x) +#define GPIO_PIN12_SOURCE_SET(x) WLAN_GPIO_PIN12_SOURCE_SET(x) +#define GPIO_PIN13_ADDRESS WLAN_GPIO_PIN13_ADDRESS +#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_OFFSET +#define GPIO_PIN13_CONFIG_MSB WLAN_GPIO_PIN13_CONFIG_MSB +#define GPIO_PIN13_CONFIG_LSB WLAN_GPIO_PIN13_CONFIG_LSB +#define GPIO_PIN13_CONFIG_MASK WLAN_GPIO_PIN13_CONFIG_MASK +#define GPIO_PIN13_CONFIG_GET(x) WLAN_GPIO_PIN13_CONFIG_GET(x) +#define GPIO_PIN13_CONFIG_SET(x) WLAN_GPIO_PIN13_CONFIG_SET(x) +#define GPIO_PIN13_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN13_WAKEUP_ENABLE_MSB +#define GPIO_PIN13_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB +#define GPIO_PIN13_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK +#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN13_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN13_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN13_INT_TYPE_MSB WLAN_GPIO_PIN13_INT_TYPE_MSB +#define GPIO_PIN13_INT_TYPE_LSB WLAN_GPIO_PIN13_INT_TYPE_LSB +#define GPIO_PIN13_INT_TYPE_MASK WLAN_GPIO_PIN13_INT_TYPE_MASK +#define GPIO_PIN13_INT_TYPE_GET(x) WLAN_GPIO_PIN13_INT_TYPE_GET(x) +#define GPIO_PIN13_INT_TYPE_SET(x) WLAN_GPIO_PIN13_INT_TYPE_SET(x) +#define GPIO_PIN13_PAD_PULL_MSB WLAN_GPIO_PIN13_PAD_PULL_MSB +#define GPIO_PIN13_PAD_PULL_LSB WLAN_GPIO_PIN13_PAD_PULL_LSB +#define GPIO_PIN13_PAD_PULL_MASK WLAN_GPIO_PIN13_PAD_PULL_MASK +#define GPIO_PIN13_PAD_PULL_GET(x) WLAN_GPIO_PIN13_PAD_PULL_GET(x) +#define GPIO_PIN13_PAD_PULL_SET(x) WLAN_GPIO_PIN13_PAD_PULL_SET(x) +#define GPIO_PIN13_PAD_STRENGTH_MSB WLAN_GPIO_PIN13_PAD_STRENGTH_MSB +#define GPIO_PIN13_PAD_STRENGTH_LSB WLAN_GPIO_PIN13_PAD_STRENGTH_LSB +#define GPIO_PIN13_PAD_STRENGTH_MASK WLAN_GPIO_PIN13_PAD_STRENGTH_MASK +#define GPIO_PIN13_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN13_PAD_STRENGTH_GET(x) +#define GPIO_PIN13_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN13_PAD_STRENGTH_SET(x) +#define GPIO_PIN13_PAD_DRIVER_MSB WLAN_GPIO_PIN13_PAD_DRIVER_MSB +#define GPIO_PIN13_PAD_DRIVER_LSB WLAN_GPIO_PIN13_PAD_DRIVER_LSB +#define GPIO_PIN13_PAD_DRIVER_MASK WLAN_GPIO_PIN13_PAD_DRIVER_MASK +#define GPIO_PIN13_PAD_DRIVER_GET(x) WLAN_GPIO_PIN13_PAD_DRIVER_GET(x) +#define GPIO_PIN13_PAD_DRIVER_SET(x) WLAN_GPIO_PIN13_PAD_DRIVER_SET(x) +#define GPIO_PIN13_SOURCE_MSB WLAN_GPIO_PIN13_SOURCE_MSB +#define GPIO_PIN13_SOURCE_LSB WLAN_GPIO_PIN13_SOURCE_LSB +#define GPIO_PIN13_SOURCE_MASK WLAN_GPIO_PIN13_SOURCE_MASK +#define GPIO_PIN13_SOURCE_GET(x) WLAN_GPIO_PIN13_SOURCE_GET(x) +#define GPIO_PIN13_SOURCE_SET(x) WLAN_GPIO_PIN13_SOURCE_SET(x) +#define GPIO_PIN14_ADDRESS WLAN_GPIO_PIN14_ADDRESS +#define GPIO_PIN14_OFFSET WLAN_GPIO_PIN14_OFFSET +#define GPIO_PIN14_CONFIG_MSB WLAN_GPIO_PIN14_CONFIG_MSB +#define GPIO_PIN14_CONFIG_LSB WLAN_GPIO_PIN14_CONFIG_LSB +#define GPIO_PIN14_CONFIG_MASK WLAN_GPIO_PIN14_CONFIG_MASK +#define GPIO_PIN14_CONFIG_GET(x) WLAN_GPIO_PIN14_CONFIG_GET(x) +#define GPIO_PIN14_CONFIG_SET(x) WLAN_GPIO_PIN14_CONFIG_SET(x) +#define GPIO_PIN14_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN14_WAKEUP_ENABLE_MSB +#define GPIO_PIN14_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB +#define GPIO_PIN14_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK +#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN14_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN14_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN14_INT_TYPE_MSB WLAN_GPIO_PIN14_INT_TYPE_MSB +#define GPIO_PIN14_INT_TYPE_LSB WLAN_GPIO_PIN14_INT_TYPE_LSB +#define GPIO_PIN14_INT_TYPE_MASK WLAN_GPIO_PIN14_INT_TYPE_MASK +#define GPIO_PIN14_INT_TYPE_GET(x) WLAN_GPIO_PIN14_INT_TYPE_GET(x) +#define GPIO_PIN14_INT_TYPE_SET(x) WLAN_GPIO_PIN14_INT_TYPE_SET(x) +#define GPIO_PIN14_PAD_PULL_MSB WLAN_GPIO_PIN14_PAD_PULL_MSB +#define GPIO_PIN14_PAD_PULL_LSB WLAN_GPIO_PIN14_PAD_PULL_LSB +#define GPIO_PIN14_PAD_PULL_MASK WLAN_GPIO_PIN14_PAD_PULL_MASK +#define GPIO_PIN14_PAD_PULL_GET(x) WLAN_GPIO_PIN14_PAD_PULL_GET(x) +#define GPIO_PIN14_PAD_PULL_SET(x) WLAN_GPIO_PIN14_PAD_PULL_SET(x) +#define GPIO_PIN14_PAD_STRENGTH_MSB WLAN_GPIO_PIN14_PAD_STRENGTH_MSB +#define GPIO_PIN14_PAD_STRENGTH_LSB WLAN_GPIO_PIN14_PAD_STRENGTH_LSB +#define GPIO_PIN14_PAD_STRENGTH_MASK WLAN_GPIO_PIN14_PAD_STRENGTH_MASK +#define GPIO_PIN14_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN14_PAD_STRENGTH_GET(x) +#define GPIO_PIN14_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN14_PAD_STRENGTH_SET(x) +#define GPIO_PIN14_PAD_DRIVER_MSB WLAN_GPIO_PIN14_PAD_DRIVER_MSB +#define GPIO_PIN14_PAD_DRIVER_LSB WLAN_GPIO_PIN14_PAD_DRIVER_LSB +#define GPIO_PIN14_PAD_DRIVER_MASK WLAN_GPIO_PIN14_PAD_DRIVER_MASK +#define GPIO_PIN14_PAD_DRIVER_GET(x) WLAN_GPIO_PIN14_PAD_DRIVER_GET(x) +#define GPIO_PIN14_PAD_DRIVER_SET(x) WLAN_GPIO_PIN14_PAD_DRIVER_SET(x) +#define GPIO_PIN14_SOURCE_MSB WLAN_GPIO_PIN14_SOURCE_MSB +#define GPIO_PIN14_SOURCE_LSB WLAN_GPIO_PIN14_SOURCE_LSB +#define GPIO_PIN14_SOURCE_MASK WLAN_GPIO_PIN14_SOURCE_MASK +#define GPIO_PIN14_SOURCE_GET(x) WLAN_GPIO_PIN14_SOURCE_GET(x) +#define GPIO_PIN14_SOURCE_SET(x) WLAN_GPIO_PIN14_SOURCE_SET(x) +#define GPIO_PIN15_ADDRESS WLAN_GPIO_PIN15_ADDRESS +#define GPIO_PIN15_OFFSET WLAN_GPIO_PIN15_OFFSET +#define GPIO_PIN15_CONFIG_MSB WLAN_GPIO_PIN15_CONFIG_MSB +#define GPIO_PIN15_CONFIG_LSB WLAN_GPIO_PIN15_CONFIG_LSB +#define GPIO_PIN15_CONFIG_MASK WLAN_GPIO_PIN15_CONFIG_MASK +#define GPIO_PIN15_CONFIG_GET(x) WLAN_GPIO_PIN15_CONFIG_GET(x) +#define GPIO_PIN15_CONFIG_SET(x) WLAN_GPIO_PIN15_CONFIG_SET(x) +#define GPIO_PIN15_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN15_WAKEUP_ENABLE_MSB +#define GPIO_PIN15_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB +#define GPIO_PIN15_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK +#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN15_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN15_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN15_INT_TYPE_MSB WLAN_GPIO_PIN15_INT_TYPE_MSB +#define GPIO_PIN15_INT_TYPE_LSB WLAN_GPIO_PIN15_INT_TYPE_LSB +#define GPIO_PIN15_INT_TYPE_MASK WLAN_GPIO_PIN15_INT_TYPE_MASK +#define GPIO_PIN15_INT_TYPE_GET(x) WLAN_GPIO_PIN15_INT_TYPE_GET(x) +#define GPIO_PIN15_INT_TYPE_SET(x) WLAN_GPIO_PIN15_INT_TYPE_SET(x) +#define GPIO_PIN15_PAD_PULL_MSB WLAN_GPIO_PIN15_PAD_PULL_MSB +#define GPIO_PIN15_PAD_PULL_LSB WLAN_GPIO_PIN15_PAD_PULL_LSB +#define GPIO_PIN15_PAD_PULL_MASK WLAN_GPIO_PIN15_PAD_PULL_MASK +#define GPIO_PIN15_PAD_PULL_GET(x) WLAN_GPIO_PIN15_PAD_PULL_GET(x) +#define GPIO_PIN15_PAD_PULL_SET(x) WLAN_GPIO_PIN15_PAD_PULL_SET(x) +#define GPIO_PIN15_PAD_STRENGTH_MSB WLAN_GPIO_PIN15_PAD_STRENGTH_MSB +#define GPIO_PIN15_PAD_STRENGTH_LSB WLAN_GPIO_PIN15_PAD_STRENGTH_LSB +#define GPIO_PIN15_PAD_STRENGTH_MASK WLAN_GPIO_PIN15_PAD_STRENGTH_MASK +#define GPIO_PIN15_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN15_PAD_STRENGTH_GET(x) +#define GPIO_PIN15_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN15_PAD_STRENGTH_SET(x) +#define GPIO_PIN15_PAD_DRIVER_MSB WLAN_GPIO_PIN15_PAD_DRIVER_MSB +#define GPIO_PIN15_PAD_DRIVER_LSB WLAN_GPIO_PIN15_PAD_DRIVER_LSB +#define GPIO_PIN15_PAD_DRIVER_MASK WLAN_GPIO_PIN15_PAD_DRIVER_MASK +#define GPIO_PIN15_PAD_DRIVER_GET(x) WLAN_GPIO_PIN15_PAD_DRIVER_GET(x) +#define GPIO_PIN15_PAD_DRIVER_SET(x) WLAN_GPIO_PIN15_PAD_DRIVER_SET(x) +#define GPIO_PIN15_SOURCE_MSB WLAN_GPIO_PIN15_SOURCE_MSB +#define GPIO_PIN15_SOURCE_LSB WLAN_GPIO_PIN15_SOURCE_LSB +#define GPIO_PIN15_SOURCE_MASK WLAN_GPIO_PIN15_SOURCE_MASK +#define GPIO_PIN15_SOURCE_GET(x) WLAN_GPIO_PIN15_SOURCE_GET(x) +#define GPIO_PIN15_SOURCE_SET(x) WLAN_GPIO_PIN15_SOURCE_SET(x) +#define GPIO_PIN16_ADDRESS WLAN_GPIO_PIN16_ADDRESS +#define GPIO_PIN16_OFFSET WLAN_GPIO_PIN16_OFFSET +#define GPIO_PIN16_CONFIG_MSB WLAN_GPIO_PIN16_CONFIG_MSB +#define GPIO_PIN16_CONFIG_LSB WLAN_GPIO_PIN16_CONFIG_LSB +#define GPIO_PIN16_CONFIG_MASK WLAN_GPIO_PIN16_CONFIG_MASK +#define GPIO_PIN16_CONFIG_GET(x) WLAN_GPIO_PIN16_CONFIG_GET(x) +#define GPIO_PIN16_CONFIG_SET(x) WLAN_GPIO_PIN16_CONFIG_SET(x) +#define GPIO_PIN16_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN16_WAKEUP_ENABLE_MSB +#define GPIO_PIN16_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB +#define GPIO_PIN16_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK +#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN16_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN16_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN16_INT_TYPE_MSB WLAN_GPIO_PIN16_INT_TYPE_MSB +#define GPIO_PIN16_INT_TYPE_LSB WLAN_GPIO_PIN16_INT_TYPE_LSB +#define GPIO_PIN16_INT_TYPE_MASK WLAN_GPIO_PIN16_INT_TYPE_MASK +#define GPIO_PIN16_INT_TYPE_GET(x) WLAN_GPIO_PIN16_INT_TYPE_GET(x) +#define GPIO_PIN16_INT_TYPE_SET(x) WLAN_GPIO_PIN16_INT_TYPE_SET(x) +#define GPIO_PIN16_PAD_PULL_MSB WLAN_GPIO_PIN16_PAD_PULL_MSB +#define GPIO_PIN16_PAD_PULL_LSB WLAN_GPIO_PIN16_PAD_PULL_LSB +#define GPIO_PIN16_PAD_PULL_MASK WLAN_GPIO_PIN16_PAD_PULL_MASK +#define GPIO_PIN16_PAD_PULL_GET(x) WLAN_GPIO_PIN16_PAD_PULL_GET(x) +#define GPIO_PIN16_PAD_PULL_SET(x) WLAN_GPIO_PIN16_PAD_PULL_SET(x) +#define GPIO_PIN16_PAD_STRENGTH_MSB WLAN_GPIO_PIN16_PAD_STRENGTH_MSB +#define GPIO_PIN16_PAD_STRENGTH_LSB WLAN_GPIO_PIN16_PAD_STRENGTH_LSB +#define GPIO_PIN16_PAD_STRENGTH_MASK WLAN_GPIO_PIN16_PAD_STRENGTH_MASK +#define GPIO_PIN16_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN16_PAD_STRENGTH_GET(x) +#define GPIO_PIN16_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN16_PAD_STRENGTH_SET(x) +#define GPIO_PIN16_PAD_DRIVER_MSB WLAN_GPIO_PIN16_PAD_DRIVER_MSB +#define GPIO_PIN16_PAD_DRIVER_LSB WLAN_GPIO_PIN16_PAD_DRIVER_LSB +#define GPIO_PIN16_PAD_DRIVER_MASK WLAN_GPIO_PIN16_PAD_DRIVER_MASK +#define GPIO_PIN16_PAD_DRIVER_GET(x) WLAN_GPIO_PIN16_PAD_DRIVER_GET(x) +#define GPIO_PIN16_PAD_DRIVER_SET(x) WLAN_GPIO_PIN16_PAD_DRIVER_SET(x) +#define GPIO_PIN16_SOURCE_MSB WLAN_GPIO_PIN16_SOURCE_MSB +#define GPIO_PIN16_SOURCE_LSB WLAN_GPIO_PIN16_SOURCE_LSB +#define GPIO_PIN16_SOURCE_MASK WLAN_GPIO_PIN16_SOURCE_MASK +#define GPIO_PIN16_SOURCE_GET(x) WLAN_GPIO_PIN16_SOURCE_GET(x) +#define GPIO_PIN16_SOURCE_SET(x) WLAN_GPIO_PIN16_SOURCE_SET(x) +#define GPIO_PIN17_ADDRESS WLAN_GPIO_PIN17_ADDRESS +#define GPIO_PIN17_OFFSET WLAN_GPIO_PIN17_OFFSET +#define GPIO_PIN17_CONFIG_MSB WLAN_GPIO_PIN17_CONFIG_MSB +#define GPIO_PIN17_CONFIG_LSB WLAN_GPIO_PIN17_CONFIG_LSB +#define GPIO_PIN17_CONFIG_MASK WLAN_GPIO_PIN17_CONFIG_MASK +#define GPIO_PIN17_CONFIG_GET(x) WLAN_GPIO_PIN17_CONFIG_GET(x) +#define GPIO_PIN17_CONFIG_SET(x) WLAN_GPIO_PIN17_CONFIG_SET(x) +#define GPIO_PIN17_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN17_WAKEUP_ENABLE_MSB +#define GPIO_PIN17_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB +#define GPIO_PIN17_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK +#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN17_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN17_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN17_INT_TYPE_MSB WLAN_GPIO_PIN17_INT_TYPE_MSB +#define GPIO_PIN17_INT_TYPE_LSB WLAN_GPIO_PIN17_INT_TYPE_LSB +#define GPIO_PIN17_INT_TYPE_MASK WLAN_GPIO_PIN17_INT_TYPE_MASK +#define GPIO_PIN17_INT_TYPE_GET(x) WLAN_GPIO_PIN17_INT_TYPE_GET(x) +#define GPIO_PIN17_INT_TYPE_SET(x) WLAN_GPIO_PIN17_INT_TYPE_SET(x) +#define GPIO_PIN17_PAD_PULL_MSB WLAN_GPIO_PIN17_PAD_PULL_MSB +#define GPIO_PIN17_PAD_PULL_LSB WLAN_GPIO_PIN17_PAD_PULL_LSB +#define GPIO_PIN17_PAD_PULL_MASK WLAN_GPIO_PIN17_PAD_PULL_MASK +#define GPIO_PIN17_PAD_PULL_GET(x) WLAN_GPIO_PIN17_PAD_PULL_GET(x) +#define GPIO_PIN17_PAD_PULL_SET(x) WLAN_GPIO_PIN17_PAD_PULL_SET(x) +#define GPIO_PIN17_PAD_STRENGTH_MSB WLAN_GPIO_PIN17_PAD_STRENGTH_MSB +#define GPIO_PIN17_PAD_STRENGTH_LSB WLAN_GPIO_PIN17_PAD_STRENGTH_LSB +#define GPIO_PIN17_PAD_STRENGTH_MASK WLAN_GPIO_PIN17_PAD_STRENGTH_MASK +#define GPIO_PIN17_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN17_PAD_STRENGTH_GET(x) +#define GPIO_PIN17_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN17_PAD_STRENGTH_SET(x) +#define GPIO_PIN17_PAD_DRIVER_MSB WLAN_GPIO_PIN17_PAD_DRIVER_MSB +#define GPIO_PIN17_PAD_DRIVER_LSB WLAN_GPIO_PIN17_PAD_DRIVER_LSB +#define GPIO_PIN17_PAD_DRIVER_MASK WLAN_GPIO_PIN17_PAD_DRIVER_MASK +#define GPIO_PIN17_PAD_DRIVER_GET(x) WLAN_GPIO_PIN17_PAD_DRIVER_GET(x) +#define GPIO_PIN17_PAD_DRIVER_SET(x) WLAN_GPIO_PIN17_PAD_DRIVER_SET(x) +#define GPIO_PIN17_SOURCE_MSB WLAN_GPIO_PIN17_SOURCE_MSB +#define GPIO_PIN17_SOURCE_LSB WLAN_GPIO_PIN17_SOURCE_LSB +#define GPIO_PIN17_SOURCE_MASK WLAN_GPIO_PIN17_SOURCE_MASK +#define GPIO_PIN17_SOURCE_GET(x) WLAN_GPIO_PIN17_SOURCE_GET(x) +#define GPIO_PIN17_SOURCE_SET(x) WLAN_GPIO_PIN17_SOURCE_SET(x) +#define GPIO_PIN18_ADDRESS WLAN_GPIO_PIN18_ADDRESS +#define GPIO_PIN18_OFFSET WLAN_GPIO_PIN18_OFFSET +#define GPIO_PIN18_CONFIG_MSB WLAN_GPIO_PIN18_CONFIG_MSB +#define GPIO_PIN18_CONFIG_LSB WLAN_GPIO_PIN18_CONFIG_LSB +#define GPIO_PIN18_CONFIG_MASK WLAN_GPIO_PIN18_CONFIG_MASK +#define GPIO_PIN18_CONFIG_GET(x) WLAN_GPIO_PIN18_CONFIG_GET(x) +#define GPIO_PIN18_CONFIG_SET(x) WLAN_GPIO_PIN18_CONFIG_SET(x) +#define GPIO_PIN18_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN18_WAKEUP_ENABLE_MSB +#define GPIO_PIN18_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB +#define GPIO_PIN18_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK +#define GPIO_PIN18_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN18_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN18_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN18_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN18_INT_TYPE_MSB WLAN_GPIO_PIN18_INT_TYPE_MSB +#define GPIO_PIN18_INT_TYPE_LSB WLAN_GPIO_PIN18_INT_TYPE_LSB +#define GPIO_PIN18_INT_TYPE_MASK WLAN_GPIO_PIN18_INT_TYPE_MASK +#define GPIO_PIN18_INT_TYPE_GET(x) WLAN_GPIO_PIN18_INT_TYPE_GET(x) +#define GPIO_PIN18_INT_TYPE_SET(x) WLAN_GPIO_PIN18_INT_TYPE_SET(x) +#define GPIO_PIN18_PAD_PULL_MSB WLAN_GPIO_PIN18_PAD_PULL_MSB +#define GPIO_PIN18_PAD_PULL_LSB WLAN_GPIO_PIN18_PAD_PULL_LSB +#define GPIO_PIN18_PAD_PULL_MASK WLAN_GPIO_PIN18_PAD_PULL_MASK +#define GPIO_PIN18_PAD_PULL_GET(x) WLAN_GPIO_PIN18_PAD_PULL_GET(x) +#define GPIO_PIN18_PAD_PULL_SET(x) WLAN_GPIO_PIN18_PAD_PULL_SET(x) +#define GPIO_PIN18_PAD_STRENGTH_MSB WLAN_GPIO_PIN18_PAD_STRENGTH_MSB +#define GPIO_PIN18_PAD_STRENGTH_LSB WLAN_GPIO_PIN18_PAD_STRENGTH_LSB +#define GPIO_PIN18_PAD_STRENGTH_MASK WLAN_GPIO_PIN18_PAD_STRENGTH_MASK +#define GPIO_PIN18_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN18_PAD_STRENGTH_GET(x) +#define GPIO_PIN18_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN18_PAD_STRENGTH_SET(x) +#define GPIO_PIN18_PAD_DRIVER_MSB WLAN_GPIO_PIN18_PAD_DRIVER_MSB +#define GPIO_PIN18_PAD_DRIVER_LSB WLAN_GPIO_PIN18_PAD_DRIVER_LSB +#define GPIO_PIN18_PAD_DRIVER_MASK WLAN_GPIO_PIN18_PAD_DRIVER_MASK +#define GPIO_PIN18_PAD_DRIVER_GET(x) WLAN_GPIO_PIN18_PAD_DRIVER_GET(x) +#define GPIO_PIN18_PAD_DRIVER_SET(x) WLAN_GPIO_PIN18_PAD_DRIVER_SET(x) +#define GPIO_PIN18_SOURCE_MSB WLAN_GPIO_PIN18_SOURCE_MSB +#define GPIO_PIN18_SOURCE_LSB WLAN_GPIO_PIN18_SOURCE_LSB +#define GPIO_PIN18_SOURCE_MASK WLAN_GPIO_PIN18_SOURCE_MASK +#define GPIO_PIN18_SOURCE_GET(x) WLAN_GPIO_PIN18_SOURCE_GET(x) +#define GPIO_PIN18_SOURCE_SET(x) WLAN_GPIO_PIN18_SOURCE_SET(x) +#define GPIO_PIN19_ADDRESS WLAN_GPIO_PIN19_ADDRESS +#define GPIO_PIN19_OFFSET WLAN_GPIO_PIN19_OFFSET +#define GPIO_PIN19_CONFIG_MSB WLAN_GPIO_PIN19_CONFIG_MSB +#define GPIO_PIN19_CONFIG_LSB WLAN_GPIO_PIN19_CONFIG_LSB +#define GPIO_PIN19_CONFIG_MASK WLAN_GPIO_PIN19_CONFIG_MASK +#define GPIO_PIN19_CONFIG_GET(x) WLAN_GPIO_PIN19_CONFIG_GET(x) +#define GPIO_PIN19_CONFIG_SET(x) WLAN_GPIO_PIN19_CONFIG_SET(x) +#define GPIO_PIN19_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN19_WAKEUP_ENABLE_MSB +#define GPIO_PIN19_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB +#define GPIO_PIN19_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK +#define GPIO_PIN19_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN19_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN19_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN19_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN19_INT_TYPE_MSB WLAN_GPIO_PIN19_INT_TYPE_MSB +#define GPIO_PIN19_INT_TYPE_LSB WLAN_GPIO_PIN19_INT_TYPE_LSB +#define GPIO_PIN19_INT_TYPE_MASK WLAN_GPIO_PIN19_INT_TYPE_MASK +#define GPIO_PIN19_INT_TYPE_GET(x) WLAN_GPIO_PIN19_INT_TYPE_GET(x) +#define GPIO_PIN19_INT_TYPE_SET(x) WLAN_GPIO_PIN19_INT_TYPE_SET(x) +#define GPIO_PIN19_PAD_PULL_MSB WLAN_GPIO_PIN19_PAD_PULL_MSB +#define GPIO_PIN19_PAD_PULL_LSB WLAN_GPIO_PIN19_PAD_PULL_LSB +#define GPIO_PIN19_PAD_PULL_MASK WLAN_GPIO_PIN19_PAD_PULL_MASK +#define GPIO_PIN19_PAD_PULL_GET(x) WLAN_GPIO_PIN19_PAD_PULL_GET(x) +#define GPIO_PIN19_PAD_PULL_SET(x) WLAN_GPIO_PIN19_PAD_PULL_SET(x) +#define GPIO_PIN19_PAD_STRENGTH_MSB WLAN_GPIO_PIN19_PAD_STRENGTH_MSB +#define GPIO_PIN19_PAD_STRENGTH_LSB WLAN_GPIO_PIN19_PAD_STRENGTH_LSB +#define GPIO_PIN19_PAD_STRENGTH_MASK WLAN_GPIO_PIN19_PAD_STRENGTH_MASK +#define GPIO_PIN19_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN19_PAD_STRENGTH_GET(x) +#define GPIO_PIN19_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN19_PAD_STRENGTH_SET(x) +#define GPIO_PIN19_PAD_DRIVER_MSB WLAN_GPIO_PIN19_PAD_DRIVER_MSB +#define GPIO_PIN19_PAD_DRIVER_LSB WLAN_GPIO_PIN19_PAD_DRIVER_LSB +#define GPIO_PIN19_PAD_DRIVER_MASK WLAN_GPIO_PIN19_PAD_DRIVER_MASK +#define GPIO_PIN19_PAD_DRIVER_GET(x) WLAN_GPIO_PIN19_PAD_DRIVER_GET(x) +#define GPIO_PIN19_PAD_DRIVER_SET(x) WLAN_GPIO_PIN19_PAD_DRIVER_SET(x) +#define GPIO_PIN19_SOURCE_MSB WLAN_GPIO_PIN19_SOURCE_MSB +#define GPIO_PIN19_SOURCE_LSB WLAN_GPIO_PIN19_SOURCE_LSB +#define GPIO_PIN19_SOURCE_MASK WLAN_GPIO_PIN19_SOURCE_MASK +#define GPIO_PIN19_SOURCE_GET(x) WLAN_GPIO_PIN19_SOURCE_GET(x) +#define GPIO_PIN19_SOURCE_SET(x) WLAN_GPIO_PIN19_SOURCE_SET(x) +#define GPIO_PIN20_ADDRESS WLAN_GPIO_PIN20_ADDRESS +#define GPIO_PIN20_OFFSET WLAN_GPIO_PIN20_OFFSET +#define GPIO_PIN20_CONFIG_MSB WLAN_GPIO_PIN20_CONFIG_MSB +#define GPIO_PIN20_CONFIG_LSB WLAN_GPIO_PIN20_CONFIG_LSB +#define GPIO_PIN20_CONFIG_MASK WLAN_GPIO_PIN20_CONFIG_MASK +#define GPIO_PIN20_CONFIG_GET(x) WLAN_GPIO_PIN20_CONFIG_GET(x) +#define GPIO_PIN20_CONFIG_SET(x) WLAN_GPIO_PIN20_CONFIG_SET(x) +#define GPIO_PIN20_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN20_WAKEUP_ENABLE_MSB +#define GPIO_PIN20_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB +#define GPIO_PIN20_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK +#define GPIO_PIN20_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN20_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN20_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN20_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN20_INT_TYPE_MSB WLAN_GPIO_PIN20_INT_TYPE_MSB +#define GPIO_PIN20_INT_TYPE_LSB WLAN_GPIO_PIN20_INT_TYPE_LSB +#define GPIO_PIN20_INT_TYPE_MASK WLAN_GPIO_PIN20_INT_TYPE_MASK +#define GPIO_PIN20_INT_TYPE_GET(x) WLAN_GPIO_PIN20_INT_TYPE_GET(x) +#define GPIO_PIN20_INT_TYPE_SET(x) WLAN_GPIO_PIN20_INT_TYPE_SET(x) +#define GPIO_PIN20_PAD_PULL_MSB WLAN_GPIO_PIN20_PAD_PULL_MSB +#define GPIO_PIN20_PAD_PULL_LSB WLAN_GPIO_PIN20_PAD_PULL_LSB +#define GPIO_PIN20_PAD_PULL_MASK WLAN_GPIO_PIN20_PAD_PULL_MASK +#define GPIO_PIN20_PAD_PULL_GET(x) WLAN_GPIO_PIN20_PAD_PULL_GET(x) +#define GPIO_PIN20_PAD_PULL_SET(x) WLAN_GPIO_PIN20_PAD_PULL_SET(x) +#define GPIO_PIN20_PAD_STRENGTH_MSB WLAN_GPIO_PIN20_PAD_STRENGTH_MSB +#define GPIO_PIN20_PAD_STRENGTH_LSB WLAN_GPIO_PIN20_PAD_STRENGTH_LSB +#define GPIO_PIN20_PAD_STRENGTH_MASK WLAN_GPIO_PIN20_PAD_STRENGTH_MASK +#define GPIO_PIN20_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN20_PAD_STRENGTH_GET(x) +#define GPIO_PIN20_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN20_PAD_STRENGTH_SET(x) +#define GPIO_PIN20_PAD_DRIVER_MSB WLAN_GPIO_PIN20_PAD_DRIVER_MSB +#define GPIO_PIN20_PAD_DRIVER_LSB WLAN_GPIO_PIN20_PAD_DRIVER_LSB +#define GPIO_PIN20_PAD_DRIVER_MASK WLAN_GPIO_PIN20_PAD_DRIVER_MASK +#define GPIO_PIN20_PAD_DRIVER_GET(x) WLAN_GPIO_PIN20_PAD_DRIVER_GET(x) +#define GPIO_PIN20_PAD_DRIVER_SET(x) WLAN_GPIO_PIN20_PAD_DRIVER_SET(x) +#define GPIO_PIN20_SOURCE_MSB WLAN_GPIO_PIN20_SOURCE_MSB +#define GPIO_PIN20_SOURCE_LSB WLAN_GPIO_PIN20_SOURCE_LSB +#define GPIO_PIN20_SOURCE_MASK WLAN_GPIO_PIN20_SOURCE_MASK +#define GPIO_PIN20_SOURCE_GET(x) WLAN_GPIO_PIN20_SOURCE_GET(x) +#define GPIO_PIN20_SOURCE_SET(x) WLAN_GPIO_PIN20_SOURCE_SET(x) +#define GPIO_PIN21_ADDRESS WLAN_GPIO_PIN21_ADDRESS +#define GPIO_PIN21_OFFSET WLAN_GPIO_PIN21_OFFSET +#define GPIO_PIN21_CONFIG_MSB WLAN_GPIO_PIN21_CONFIG_MSB +#define GPIO_PIN21_CONFIG_LSB WLAN_GPIO_PIN21_CONFIG_LSB +#define GPIO_PIN21_CONFIG_MASK WLAN_GPIO_PIN21_CONFIG_MASK +#define GPIO_PIN21_CONFIG_GET(x) WLAN_GPIO_PIN21_CONFIG_GET(x) +#define GPIO_PIN21_CONFIG_SET(x) WLAN_GPIO_PIN21_CONFIG_SET(x) +#define GPIO_PIN21_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN21_WAKEUP_ENABLE_MSB +#define GPIO_PIN21_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB +#define GPIO_PIN21_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK +#define GPIO_PIN21_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN21_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN21_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN21_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN21_INT_TYPE_MSB WLAN_GPIO_PIN21_INT_TYPE_MSB +#define GPIO_PIN21_INT_TYPE_LSB WLAN_GPIO_PIN21_INT_TYPE_LSB +#define GPIO_PIN21_INT_TYPE_MASK WLAN_GPIO_PIN21_INT_TYPE_MASK +#define GPIO_PIN21_INT_TYPE_GET(x) WLAN_GPIO_PIN21_INT_TYPE_GET(x) +#define GPIO_PIN21_INT_TYPE_SET(x) WLAN_GPIO_PIN21_INT_TYPE_SET(x) +#define GPIO_PIN21_PAD_PULL_MSB WLAN_GPIO_PIN21_PAD_PULL_MSB +#define GPIO_PIN21_PAD_PULL_LSB WLAN_GPIO_PIN21_PAD_PULL_LSB +#define GPIO_PIN21_PAD_PULL_MASK WLAN_GPIO_PIN21_PAD_PULL_MASK +#define GPIO_PIN21_PAD_PULL_GET(x) WLAN_GPIO_PIN21_PAD_PULL_GET(x) +#define GPIO_PIN21_PAD_PULL_SET(x) WLAN_GPIO_PIN21_PAD_PULL_SET(x) +#define GPIO_PIN21_PAD_STRENGTH_MSB WLAN_GPIO_PIN21_PAD_STRENGTH_MSB +#define GPIO_PIN21_PAD_STRENGTH_LSB WLAN_GPIO_PIN21_PAD_STRENGTH_LSB +#define GPIO_PIN21_PAD_STRENGTH_MASK WLAN_GPIO_PIN21_PAD_STRENGTH_MASK +#define GPIO_PIN21_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN21_PAD_STRENGTH_GET(x) +#define GPIO_PIN21_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN21_PAD_STRENGTH_SET(x) +#define GPIO_PIN21_PAD_DRIVER_MSB WLAN_GPIO_PIN21_PAD_DRIVER_MSB +#define GPIO_PIN21_PAD_DRIVER_LSB WLAN_GPIO_PIN21_PAD_DRIVER_LSB +#define GPIO_PIN21_PAD_DRIVER_MASK WLAN_GPIO_PIN21_PAD_DRIVER_MASK +#define GPIO_PIN21_PAD_DRIVER_GET(x) WLAN_GPIO_PIN21_PAD_DRIVER_GET(x) +#define GPIO_PIN21_PAD_DRIVER_SET(x) WLAN_GPIO_PIN21_PAD_DRIVER_SET(x) +#define GPIO_PIN21_SOURCE_MSB WLAN_GPIO_PIN21_SOURCE_MSB +#define GPIO_PIN21_SOURCE_LSB WLAN_GPIO_PIN21_SOURCE_LSB +#define GPIO_PIN21_SOURCE_MASK WLAN_GPIO_PIN21_SOURCE_MASK +#define GPIO_PIN21_SOURCE_GET(x) WLAN_GPIO_PIN21_SOURCE_GET(x) +#define GPIO_PIN21_SOURCE_SET(x) WLAN_GPIO_PIN21_SOURCE_SET(x) +#define GPIO_PIN22_ADDRESS WLAN_GPIO_PIN22_ADDRESS +#define GPIO_PIN22_OFFSET WLAN_GPIO_PIN22_OFFSET +#define GPIO_PIN22_CONFIG_MSB WLAN_GPIO_PIN22_CONFIG_MSB +#define GPIO_PIN22_CONFIG_LSB WLAN_GPIO_PIN22_CONFIG_LSB +#define GPIO_PIN22_CONFIG_MASK WLAN_GPIO_PIN22_CONFIG_MASK +#define GPIO_PIN22_CONFIG_GET(x) WLAN_GPIO_PIN22_CONFIG_GET(x) +#define GPIO_PIN22_CONFIG_SET(x) WLAN_GPIO_PIN22_CONFIG_SET(x) +#define GPIO_PIN22_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN22_WAKEUP_ENABLE_MSB +#define GPIO_PIN22_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB +#define GPIO_PIN22_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK +#define GPIO_PIN22_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN22_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN22_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN22_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN22_INT_TYPE_MSB WLAN_GPIO_PIN22_INT_TYPE_MSB +#define GPIO_PIN22_INT_TYPE_LSB WLAN_GPIO_PIN22_INT_TYPE_LSB +#define GPIO_PIN22_INT_TYPE_MASK WLAN_GPIO_PIN22_INT_TYPE_MASK +#define GPIO_PIN22_INT_TYPE_GET(x) WLAN_GPIO_PIN22_INT_TYPE_GET(x) +#define GPIO_PIN22_INT_TYPE_SET(x) WLAN_GPIO_PIN22_INT_TYPE_SET(x) +#define GPIO_PIN22_PAD_PULL_MSB WLAN_GPIO_PIN22_PAD_PULL_MSB +#define GPIO_PIN22_PAD_PULL_LSB WLAN_GPIO_PIN22_PAD_PULL_LSB +#define GPIO_PIN22_PAD_PULL_MASK WLAN_GPIO_PIN22_PAD_PULL_MASK +#define GPIO_PIN22_PAD_PULL_GET(x) WLAN_GPIO_PIN22_PAD_PULL_GET(x) +#define GPIO_PIN22_PAD_PULL_SET(x) WLAN_GPIO_PIN22_PAD_PULL_SET(x) +#define GPIO_PIN22_PAD_STRENGTH_MSB WLAN_GPIO_PIN22_PAD_STRENGTH_MSB +#define GPIO_PIN22_PAD_STRENGTH_LSB WLAN_GPIO_PIN22_PAD_STRENGTH_LSB +#define GPIO_PIN22_PAD_STRENGTH_MASK WLAN_GPIO_PIN22_PAD_STRENGTH_MASK +#define GPIO_PIN22_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN22_PAD_STRENGTH_GET(x) +#define GPIO_PIN22_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN22_PAD_STRENGTH_SET(x) +#define GPIO_PIN22_PAD_DRIVER_MSB WLAN_GPIO_PIN22_PAD_DRIVER_MSB +#define GPIO_PIN22_PAD_DRIVER_LSB WLAN_GPIO_PIN22_PAD_DRIVER_LSB +#define GPIO_PIN22_PAD_DRIVER_MASK WLAN_GPIO_PIN22_PAD_DRIVER_MASK +#define GPIO_PIN22_PAD_DRIVER_GET(x) WLAN_GPIO_PIN22_PAD_DRIVER_GET(x) +#define GPIO_PIN22_PAD_DRIVER_SET(x) WLAN_GPIO_PIN22_PAD_DRIVER_SET(x) +#define GPIO_PIN22_SOURCE_MSB WLAN_GPIO_PIN22_SOURCE_MSB +#define GPIO_PIN22_SOURCE_LSB WLAN_GPIO_PIN22_SOURCE_LSB +#define GPIO_PIN22_SOURCE_MASK WLAN_GPIO_PIN22_SOURCE_MASK +#define GPIO_PIN22_SOURCE_GET(x) WLAN_GPIO_PIN22_SOURCE_GET(x) +#define GPIO_PIN22_SOURCE_SET(x) WLAN_GPIO_PIN22_SOURCE_SET(x) +#define GPIO_PIN23_ADDRESS WLAN_GPIO_PIN23_ADDRESS +#define GPIO_PIN23_OFFSET WLAN_GPIO_PIN23_OFFSET +#define GPIO_PIN23_CONFIG_MSB WLAN_GPIO_PIN23_CONFIG_MSB +#define GPIO_PIN23_CONFIG_LSB WLAN_GPIO_PIN23_CONFIG_LSB +#define GPIO_PIN23_CONFIG_MASK WLAN_GPIO_PIN23_CONFIG_MASK +#define GPIO_PIN23_CONFIG_GET(x) WLAN_GPIO_PIN23_CONFIG_GET(x) +#define GPIO_PIN23_CONFIG_SET(x) WLAN_GPIO_PIN23_CONFIG_SET(x) +#define GPIO_PIN23_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN23_WAKEUP_ENABLE_MSB +#define GPIO_PIN23_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB +#define GPIO_PIN23_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK +#define GPIO_PIN23_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN23_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN23_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN23_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN23_INT_TYPE_MSB WLAN_GPIO_PIN23_INT_TYPE_MSB +#define GPIO_PIN23_INT_TYPE_LSB WLAN_GPIO_PIN23_INT_TYPE_LSB +#define GPIO_PIN23_INT_TYPE_MASK WLAN_GPIO_PIN23_INT_TYPE_MASK +#define GPIO_PIN23_INT_TYPE_GET(x) WLAN_GPIO_PIN23_INT_TYPE_GET(x) +#define GPIO_PIN23_INT_TYPE_SET(x) WLAN_GPIO_PIN23_INT_TYPE_SET(x) +#define GPIO_PIN23_PAD_DRIVER_MSB WLAN_GPIO_PIN23_PAD_DRIVER_MSB +#define GPIO_PIN23_PAD_DRIVER_LSB WLAN_GPIO_PIN23_PAD_DRIVER_LSB +#define GPIO_PIN23_PAD_DRIVER_MASK WLAN_GPIO_PIN23_PAD_DRIVER_MASK +#define GPIO_PIN23_PAD_DRIVER_GET(x) WLAN_GPIO_PIN23_PAD_DRIVER_GET(x) +#define GPIO_PIN23_PAD_DRIVER_SET(x) WLAN_GPIO_PIN23_PAD_DRIVER_SET(x) +#define GPIO_PIN23_SOURCE_MSB WLAN_GPIO_PIN23_SOURCE_MSB +#define GPIO_PIN23_SOURCE_LSB WLAN_GPIO_PIN23_SOURCE_LSB +#define GPIO_PIN23_SOURCE_MASK WLAN_GPIO_PIN23_SOURCE_MASK +#define GPIO_PIN23_SOURCE_GET(x) WLAN_GPIO_PIN23_SOURCE_GET(x) +#define GPIO_PIN23_SOURCE_SET(x) WLAN_GPIO_PIN23_SOURCE_SET(x) +#define GPIO_PIN24_ADDRESS WLAN_GPIO_PIN24_ADDRESS +#define GPIO_PIN24_OFFSET WLAN_GPIO_PIN24_OFFSET +#define GPIO_PIN24_CONFIG_MSB WLAN_GPIO_PIN24_CONFIG_MSB +#define GPIO_PIN24_CONFIG_LSB WLAN_GPIO_PIN24_CONFIG_LSB +#define GPIO_PIN24_CONFIG_MASK WLAN_GPIO_PIN24_CONFIG_MASK +#define GPIO_PIN24_CONFIG_GET(x) WLAN_GPIO_PIN24_CONFIG_GET(x) +#define GPIO_PIN24_CONFIG_SET(x) WLAN_GPIO_PIN24_CONFIG_SET(x) +#define GPIO_PIN24_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN24_WAKEUP_ENABLE_MSB +#define GPIO_PIN24_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB +#define GPIO_PIN24_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK +#define GPIO_PIN24_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN24_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN24_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN24_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN24_INT_TYPE_MSB WLAN_GPIO_PIN24_INT_TYPE_MSB +#define GPIO_PIN24_INT_TYPE_LSB WLAN_GPIO_PIN24_INT_TYPE_LSB +#define GPIO_PIN24_INT_TYPE_MASK WLAN_GPIO_PIN24_INT_TYPE_MASK +#define GPIO_PIN24_INT_TYPE_GET(x) WLAN_GPIO_PIN24_INT_TYPE_GET(x) +#define GPIO_PIN24_INT_TYPE_SET(x) WLAN_GPIO_PIN24_INT_TYPE_SET(x) +#define GPIO_PIN24_PAD_DRIVER_MSB WLAN_GPIO_PIN24_PAD_DRIVER_MSB +#define GPIO_PIN24_PAD_DRIVER_LSB WLAN_GPIO_PIN24_PAD_DRIVER_LSB +#define GPIO_PIN24_PAD_DRIVER_MASK WLAN_GPIO_PIN24_PAD_DRIVER_MASK +#define GPIO_PIN24_PAD_DRIVER_GET(x) WLAN_GPIO_PIN24_PAD_DRIVER_GET(x) +#define GPIO_PIN24_PAD_DRIVER_SET(x) WLAN_GPIO_PIN24_PAD_DRIVER_SET(x) +#define GPIO_PIN24_SOURCE_MSB WLAN_GPIO_PIN24_SOURCE_MSB +#define GPIO_PIN24_SOURCE_LSB WLAN_GPIO_PIN24_SOURCE_LSB +#define GPIO_PIN24_SOURCE_MASK WLAN_GPIO_PIN24_SOURCE_MASK +#define GPIO_PIN24_SOURCE_GET(x) WLAN_GPIO_PIN24_SOURCE_GET(x) +#define GPIO_PIN24_SOURCE_SET(x) WLAN_GPIO_PIN24_SOURCE_SET(x) +#define GPIO_PIN25_ADDRESS WLAN_GPIO_PIN25_ADDRESS +#define GPIO_PIN25_OFFSET WLAN_GPIO_PIN25_OFFSET +#define GPIO_PIN25_CONFIG_MSB WLAN_GPIO_PIN25_CONFIG_MSB +#define GPIO_PIN25_CONFIG_LSB WLAN_GPIO_PIN25_CONFIG_LSB +#define GPIO_PIN25_CONFIG_MASK WLAN_GPIO_PIN25_CONFIG_MASK +#define GPIO_PIN25_CONFIG_GET(x) WLAN_GPIO_PIN25_CONFIG_GET(x) +#define GPIO_PIN25_CONFIG_SET(x) WLAN_GPIO_PIN25_CONFIG_SET(x) +#define GPIO_PIN25_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN25_WAKEUP_ENABLE_MSB +#define GPIO_PIN25_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB +#define GPIO_PIN25_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK +#define GPIO_PIN25_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN25_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN25_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN25_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN25_INT_TYPE_MSB WLAN_GPIO_PIN25_INT_TYPE_MSB +#define GPIO_PIN25_INT_TYPE_LSB WLAN_GPIO_PIN25_INT_TYPE_LSB +#define GPIO_PIN25_INT_TYPE_MASK WLAN_GPIO_PIN25_INT_TYPE_MASK +#define GPIO_PIN25_INT_TYPE_GET(x) WLAN_GPIO_PIN25_INT_TYPE_GET(x) +#define GPIO_PIN25_INT_TYPE_SET(x) WLAN_GPIO_PIN25_INT_TYPE_SET(x) +#define GPIO_PIN25_PAD_DRIVER_MSB WLAN_GPIO_PIN25_PAD_DRIVER_MSB +#define GPIO_PIN25_PAD_DRIVER_LSB WLAN_GPIO_PIN25_PAD_DRIVER_LSB +#define GPIO_PIN25_PAD_DRIVER_MASK WLAN_GPIO_PIN25_PAD_DRIVER_MASK +#define GPIO_PIN25_PAD_DRIVER_GET(x) WLAN_GPIO_PIN25_PAD_DRIVER_GET(x) +#define GPIO_PIN25_PAD_DRIVER_SET(x) WLAN_GPIO_PIN25_PAD_DRIVER_SET(x) +#define GPIO_PIN25_SOURCE_MSB WLAN_GPIO_PIN25_SOURCE_MSB +#define GPIO_PIN25_SOURCE_LSB WLAN_GPIO_PIN25_SOURCE_LSB +#define GPIO_PIN25_SOURCE_MASK WLAN_GPIO_PIN25_SOURCE_MASK +#define GPIO_PIN25_SOURCE_GET(x) WLAN_GPIO_PIN25_SOURCE_GET(x) +#define GPIO_PIN25_SOURCE_SET(x) WLAN_GPIO_PIN25_SOURCE_SET(x) +#define SIGMA_DELTA_ADDRESS WLAN_SIGMA_DELTA_ADDRESS +#define SIGMA_DELTA_OFFSET WLAN_SIGMA_DELTA_OFFSET +#define SIGMA_DELTA_ENABLE_MSB WLAN_SIGMA_DELTA_ENABLE_MSB +#define SIGMA_DELTA_ENABLE_LSB WLAN_SIGMA_DELTA_ENABLE_LSB +#define SIGMA_DELTA_ENABLE_MASK WLAN_SIGMA_DELTA_ENABLE_MASK +#define SIGMA_DELTA_ENABLE_GET(x) WLAN_SIGMA_DELTA_ENABLE_GET(x) +#define SIGMA_DELTA_ENABLE_SET(x) WLAN_SIGMA_DELTA_ENABLE_SET(x) +#define SIGMA_DELTA_PRESCALAR_MSB WLAN_SIGMA_DELTA_PRESCALAR_MSB +#define SIGMA_DELTA_PRESCALAR_LSB WLAN_SIGMA_DELTA_PRESCALAR_LSB +#define SIGMA_DELTA_PRESCALAR_MASK WLAN_SIGMA_DELTA_PRESCALAR_MASK +#define SIGMA_DELTA_PRESCALAR_GET(x) WLAN_SIGMA_DELTA_PRESCALAR_GET(x) +#define SIGMA_DELTA_PRESCALAR_SET(x) WLAN_SIGMA_DELTA_PRESCALAR_SET(x) +#define SIGMA_DELTA_TARGET_MSB WLAN_SIGMA_DELTA_TARGET_MSB +#define SIGMA_DELTA_TARGET_LSB WLAN_SIGMA_DELTA_TARGET_LSB +#define SIGMA_DELTA_TARGET_MASK WLAN_SIGMA_DELTA_TARGET_MASK +#define SIGMA_DELTA_TARGET_GET(x) WLAN_SIGMA_DELTA_TARGET_GET(x) +#define SIGMA_DELTA_TARGET_SET(x) WLAN_SIGMA_DELTA_TARGET_SET(x) +#define DEBUG_CONTROL_ADDRESS WLAN_DEBUG_CONTROL_ADDRESS +#define DEBUG_CONTROL_OFFSET WLAN_DEBUG_CONTROL_OFFSET +#define DEBUG_CONTROL_ENABLE_MSB WLAN_DEBUG_CONTROL_ENABLE_MSB +#define DEBUG_CONTROL_ENABLE_LSB WLAN_DEBUG_CONTROL_ENABLE_LSB +#define DEBUG_CONTROL_ENABLE_MASK WLAN_DEBUG_CONTROL_ENABLE_MASK +#define DEBUG_CONTROL_ENABLE_GET(x) WLAN_DEBUG_CONTROL_ENABLE_GET(x) +#define DEBUG_CONTROL_ENABLE_SET(x) WLAN_DEBUG_CONTROL_ENABLE_SET(x) +#define DEBUG_INPUT_SEL_ADDRESS WLAN_DEBUG_INPUT_SEL_ADDRESS +#define DEBUG_INPUT_SEL_OFFSET WLAN_DEBUG_INPUT_SEL_OFFSET +#define DEBUG_INPUT_SEL_SHIFT_MSB WLAN_DEBUG_INPUT_SEL_SHIFT_MSB +#define DEBUG_INPUT_SEL_SHIFT_LSB WLAN_DEBUG_INPUT_SEL_SHIFT_LSB +#define DEBUG_INPUT_SEL_SHIFT_MASK WLAN_DEBUG_INPUT_SEL_SHIFT_MASK +#define DEBUG_INPUT_SEL_SHIFT_GET(x) WLAN_DEBUG_INPUT_SEL_SHIFT_GET(x) +#define DEBUG_INPUT_SEL_SHIFT_SET(x) WLAN_DEBUG_INPUT_SEL_SHIFT_SET(x) +#define DEBUG_INPUT_SEL_SRC_MSB WLAN_DEBUG_INPUT_SEL_SRC_MSB +#define DEBUG_INPUT_SEL_SRC_LSB WLAN_DEBUG_INPUT_SEL_SRC_LSB +#define DEBUG_INPUT_SEL_SRC_MASK WLAN_DEBUG_INPUT_SEL_SRC_MASK +#define DEBUG_INPUT_SEL_SRC_GET(x) WLAN_DEBUG_INPUT_SEL_SRC_GET(x) +#define DEBUG_INPUT_SEL_SRC_SET(x) WLAN_DEBUG_INPUT_SEL_SRC_SET(x) +#define DEBUG_OUT_ADDRESS WLAN_DEBUG_OUT_ADDRESS +#define DEBUG_OUT_OFFSET WLAN_DEBUG_OUT_OFFSET +#define DEBUG_OUT_DATA_MSB WLAN_DEBUG_OUT_DATA_MSB +#define DEBUG_OUT_DATA_LSB WLAN_DEBUG_OUT_DATA_LSB +#define DEBUG_OUT_DATA_MASK WLAN_DEBUG_OUT_DATA_MASK +#define DEBUG_OUT_DATA_GET(x) WLAN_DEBUG_OUT_DATA_GET(x) +#define DEBUG_OUT_DATA_SET(x) WLAN_DEBUG_OUT_DATA_SET(x) +#define RESET_TUPLE_STATUS_ADDRESS WLAN_RESET_TUPLE_STATUS_ADDRESS +#define RESET_TUPLE_STATUS_OFFSET WLAN_RESET_TUPLE_STATUS_OFFSET +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) + + +#endif +#endif + + + diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_dma_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_dma_reg.h new file mode 100644 index 000000000000..f82f809171a0 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_dma_reg.h @@ -0,0 +1,605 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2002-2010 Atheros Communications Inc. +// All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +/*****************************************************************************/ +/* AR6003 WLAN MAC DMA register definitions */ +/*****************************************************************************/ + +#ifndef _AR6000_DMAREG_H_ +#define _AR6000_DMAREG_H_ + +/* + * Definitions for the Atheros AR6003 chipset. + */ + +/* DMA Control and Interrupt Registers */ +#define MAC_DMA_CR_ADDRESS 0x00000008 /* MAC control register */ +#define MAC_DMA_CR_RXE_MASK 0x00000004 /* Receive enable */ +#define MAC_DMA_CR_RXD_MASK 0x00000020 /* Receive disable */ +#define MAC_DMA_CR_SWI_MASK 0x00000040 /* One-shot software interrupt */ + +#define MAC_DMA_RXDP_ADDRESS 0x0000000C /* MAC receive queue descriptor pointer */ + +#define MAC_DMA_CFG_ADDRESS 0x00000014 /* MAC configuration and status register */ +#define MAC_DMA_CFG_SWTD_MASK 0x00000001 /* byteswap tx descriptor words */ +#define MAC_DMA_CFG_SWTB_MASK 0x00000002 /* byteswap tx data buffer words */ +#define MAC_DMA_CFG_SWRD_MASK 0x00000004 /* byteswap rx descriptor words */ +#define MAC_DMA_CFG_SWRB_MASK 0x00000008 /* byteswap rx data buffer words */ +#define MAC_DMA_CFG_SWRG_MASK 0x00000010 /* byteswap register access data words */ +#define MAC_DMA_CFG_AP_ADHOC_INDICATION_MASK 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */ +#define MAC_DMA_CFG_PHOK_MASK 0x00000100 /* PHY OK status */ +#define MAC_DMA_CFG_CLK_GATE_DIS_MASK 0x00000400 /* Clock gating disable */ + +#define MAC_DMA_MIRT_ADDRESS 0x00000020 /* Maximum rate threshold register */ +#define MAC_DMA_MIRT_THRESH_MASK 0x0000FFFF + +#define MAC_DMA_IER_ADDRESS 0x00000024 /* MAC Interrupt enable register */ +#define MAC_DMA_IER_ENABLE_MASK 0x00000001 /* Global interrupt enable */ +#define MAC_DMA_IER_DISABLE_MASK 0x00000000 /* Global interrupt disable */ + +#define MAC_DMA_TIMT_ADDRESS 0x00000028 /* Transmit Interrupt Mitigation Threshold */ +#define MAC_DMA_TIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet threshold mask */ +#define MAC_DMA_TIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet threshold mask */ + +#define MAC_DMA_RIMT_ADDRESS 0x0000002C /* Receive Interrupt Mitigation Threshold */ +#define MAC_DMA_RIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet threshold mask */ +#define MAC_DMA_RIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet threshold mask */ + +#define MAC_DMA_TXCFG_ADDRESS 0x00000030 /* MAC tx DMA size config register */ +#define MAC_DMA_FTRIG_MASK 0x000003F0 /* Mask for Frame trigger level */ +#define MAC_DMA_FTRIG_LSB 4 /* Shift for Frame trigger level */ +#define MAC_DMA_FTRIG_IMMED 0x00000000 /* bytes in PCU TX FIFO before air */ +#define MAC_DMA_FTRIG_64B 0x00000010 /* default */ +#define MAC_DMA_FTRIG_128B 0x00000020 +#define MAC_DMA_FTRIG_192B 0x00000030 +#define MAC_DMA_FTRIG_256B 0x00000040 /* 5 bits total */ +#define MAC_DMA_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY_MASK 0x00000800 + +#define MAC_DMA_RXCFG_ADDRESS 0x00000034 /* MAC rx DMA size config register */ +#define MAC_DMA_RXCFG_ZLFDMA_MASK 0x00000010 /* Enable DMA of zero-length frame */ +#define MAC_DMA_RXCFG_DMASIZE_4B 0x00000000 /* DMA size 4 bytes (TXCFG + RXCFG) */ +#define MAC_DMA_RXCFG_DMASIZE_8B 0x00000001 /* DMA size 8 bytes */ +#define MAC_DMA_RXCFG_DMASIZE_16B 0x00000002 /* DMA size 16 bytes */ +#define MAC_DMA_RXCFG_DMASIZE_32B 0x00000003 /* DMA size 32 bytes */ +#define MAC_DMA_RXCFG_DMASIZE_64B 0x00000004 /* DMA size 64 bytes */ +#define MAC_DMA_RXCFG_DMASIZE_128B 0x00000005 /* DMA size 128 bytes */ +#define MAC_DMA_RXCFG_DMASIZE_256B 0x00000006 /* DMA size 256 bytes */ +#define MAC_DMA_RXCFG_DMASIZE_512B 0x00000007 /* DMA size 512 bytes */ + +#define MAC_DMA_MIBC_ADDRESS 0x00000040 /* MAC MIB control register */ +#define MAC_DMA_MIBC_COW_MASK 0x00000001 /* counter overflow warning */ +#define MAC_DMA_MIBC_FMC_MASK 0x00000002 /* freeze MIB counters */ +#define MAC_DMA_MIBC_CMC_MASK 0x00000004 /* clear MIB counters */ +#define MAC_DMA_MIBC_MCS_MASK 0x00000008 /* MIB counter strobe, increment all */ + +#define MAC_DMA_TOPS_ADDRESS 0x00000044 /* MAC timeout prescale count */ +#define MAC_DMA_TOPS_MASK 0x0000FFFF /* Mask for timeout prescale */ + +#define MAC_DMA_RXNPTO_ADDRESS 0x00000048 /* MAC no frame received timeout */ +#define MAC_DMA_RXNPTO_MASK 0x000003FF /* Mask for no frame received timeout */ + +#define MAC_DMA_TXNPTO_ADDRESS 0x0000004C /* MAC no frame trasmitted timeout */ +#define MAC_DMA_TXNPTO_MASK 0x000003FF /* Mask for no frame transmitted timeout */ +#define MAC_DMA_TXNPTO_QCU_MASK 0x000FFC00 /* Mask indicating the set of QCUs */ + /* for which frame completions will cause */ + /* a reset of the no frame xmit'd timeout */ + +#define MAC_DMA_RPGTO_ADDRESS 0x00000050 /* MAC receive frame gap timeout */ +#define MAC_DMA_RPGTO_MASK 0x000003FF /* Mask for receive frame gap timeout */ + +#define MAC_DMA_RPCNT_ADDRESS 0x00000054 /* MAC receive frame count limit */ +#define MAC_DMA_RPCNT_MASK 0x0000001F /* Mask for receive frame count limit */ + +#define MAC_DMA_MACMISC_ADDRESS 0x00000058 /* MAC miscellaneous control/status register */ +#define MAC_DMA_MACMISC_DMA_OBS_MASK 0x000001E0 /* Mask for DMA observation bus mux select */ +#define MAC_DMA_MACMISC_DMA_OBS_LSB 5 /* Shift for DMA observation bus mux select */ +#define MAC_DMA_MACMISC_MISC_OBS 0x00000E00 /* Mask for MISC observation bus mux select */ +#define MAC_DMA_MACMISC_MISC_OBS_LSB 9 /* Shift for MISC observation bus mux select */ +#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB 0x00007000 /* Mask for MAC observation bus mux select (lsb) */ +#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB_LSB 12 /* Shift for MAC observation bus mux select (lsb) */ +#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB 0x00038000 /* Mask for MAC observation bus mux select (msb) */ +#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB_LSB 15 /* Shift for MAC observation bus mux select (msb) */ + + +#define MAC_DMA_ISR_ADDRESS 0x00000080 /* MAC Primary interrupt status register */ +/* + * Interrupt Status Registers + * + * Only the bits in the ISR_P register and the IMR_P registers + * control whether the MAC's INTA# output is asserted. The bits in + * the secondary interrupt status/mask registers control what bits + * are set in the primary interrupt status register; however the + * IMR_S* registers DO NOT determine whether INTA# is asserted. + * That is INTA# is asserted only when the logical AND of ISR_P + * and IMR_P is non-zero. The secondary interrupt mask/status + * registers affect what bits are set in ISR_P but they do not + * directly affect whether INTA# is asserted. + */ +#define MAC_DMA_ISR_RXOK_MASK 0x00000001 /* At least one frame received sans errors */ +#define MAC_DMA_ISR_RXDESC_MASK 0x00000002 /* Receive interrupt request */ +#define MAC_DMA_ISR_RXERR_MASK 0x00000004 /* Receive error interrupt */ +#define MAC_DMA_ISR_RXNOPKT_MASK 0x00000008 /* No frame received within timeout clock */ +#define MAC_DMA_ISR_RXEOL_MASK 0x00000010 /* Received descriptor empty interrupt */ +#define MAC_DMA_ISR_RXORN_MASK 0x00000020 /* Receive FIFO overrun interrupt */ +#define MAC_DMA_ISR_TXOK_MASK 0x00000040 /* Transmit okay interrupt */ +#define MAC_DMA_ISR_TXDESC_MASK 0x00000080 /* Transmit interrupt request */ +#define MAC_DMA_ISR_TXERR_MASK 0x00000100 /* Transmit error interrupt */ +#define MAC_DMA_ISR_TXNOPKT_MASK 0x00000200 /* No frame transmitted interrupt */ +#define MAC_DMA_ISR_TXEOL_MASK 0x00000400 /* Transmit descriptor empty interrupt */ +#define MAC_DMA_ISR_TXURN_MASK 0x00000800 /* Transmit FIFO underrun interrupt */ +#define MAC_DMA_ISR_MIB_MASK 0x00001000 /* MIB interrupt - see MIBC */ +#define MAC_DMA_ISR_SWI_MASK 0x00002000 /* Software interrupt */ +#define MAC_DMA_ISR_RXPHY_MASK 0x00004000 /* PHY receive error interrupt */ +#define MAC_DMA_ISR_RXKCM_MASK 0x00008000 /* Key-cache miss interrupt */ +#define MAC_DMA_ISR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi high threshold interrupt */ +#define MAC_DMA_ISR_BRSSI_LO_MASK 0x00020000 /* Beacon threshold interrupt */ +#define MAC_DMA_ISR_BMISS_MASK 0x00040000 /* Beacon missed interrupt */ +#define MAC_DMA_ISR_TXMINTR_MASK 0x00080000 /* Maximum transmit interrupt rate */ +#define MAC_DMA_ISR_BNR_MASK 0x00100000 /* Beacon not ready interrupt */ +#define MAC_DMA_ISR_HIUERR_MASK 0x00200000 /* An unexpected bus error has occurred */ +#define MAC_DMA_ISR_BCNMISC_MASK 0x00800000 /* 'or' of TIM, CABEND, DTIMSYNC, BCNTO */ +#define MAC_DMA_ISR_RXMINTR_MASK 0x01000000 /* Maximum receive interrupt rate */ +#define MAC_DMA_ISR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow interrupt */ +#define MAC_DMA_ISR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun interrupt */ +#define MAC_DMA_ISR_QTRIG_MASK 0x08000000 /* QCU scheduling trigger interrupt */ +#define MAC_DMA_ISR_TIMER_MASK 0x10000000 /* GENTMR interrupt */ +#define MAC_DMA_ISR_HCFTO_MASK 0x20000000 /* HCFTO interrupt */ +#define MAC_DMA_ISR_TXINTM_MASK 0x40000000 /* Transmit completion mitigation interrupt */ +#define MAC_DMA_ISR_RXINTM_MASK 0x80000000 /* Receive completion mitigation interrupt */ + +#define MAC_DMA_ISR_S0_ADDRESS 0x00000084 /* MAC Secondary interrupt status register 0 */ +#define MAC_DMA_ISR_S0_QCU_TXOK_MASK 0x000003FF /* Mask for TXOK (QCU 0-9) */ +#define MAC_DMA_ISR_S0_QCU_TXOK_LSB 0 +#define MAC_DMA_ISR_S0_QCU_TXDESC_MASK 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */ +#define MAC_DMA_ISR_S0_QCU_TXDESC_LSB 16 + +#define MAC_DMA_ISR_S1_ADDRESS 0x00000088 /* MAC Secondary interrupt status register 1 */ +#define MAC_DMA_ISR_S1_QCU_TXERR_MASK 0x000003FF /* Mask for TXERR (QCU 0-9) */ +#define MAC_DMA_ISR_S1_QCU_TXERR_LSB 0 +#define MAC_DMA_ISR_S1_QCU_TXEOL_MASK 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */ +#define MAC_DMA_ISR_S1_QCU_TXEOL_LSB 16 + +#define MAC_DMA_ISR_S2_ADDRESS 0x0000008c /* MAC Secondary interrupt status register 2 */ +#define MAC_DMA_ISR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN (QCU 0-9) */ +#define MAC_DMA_ISR_S2_QCU_TXURN_LSB 0 /* Shift for TXURN (QCU 0-9) */ +#define MAC_DMA_ISR_S2_RX_INT_MASK 0x00000800 +#define MAC_DMA_ISR_S2_WL_STOMPED_MASK 0x00001000 +#define MAC_DMA_ISR_S2_RX_PTR_BAD_MASK 0x00002000 +#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000 +#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000 +#define MAC_DMA_ISR_S2_BB_PANIC_IRQ_MASK 0x00010000 +#define MAC_DMA_ISR_S2_BT_STOMPED_MASK 0x00020000 +#define MAC_DMA_ISR_S2_BT_ACTIVE_RISING_MASK 0x00040000 +#define MAC_DMA_ISR_S2_BT_ACTIVE_FALLING_MASK 0x00080000 +#define MAC_DMA_ISR_S2_BT_PRIORITY_RISING_MASK 0x00100000 +#define MAC_DMA_ISR_S2_BT_PRIORITY_FALLING_MASK 0x00200000 +#define MAC_DMA_ISR_S2_CST_MASK 0x00400000 +#define MAC_DMA_ISR_S2_GTT_MASK 0x00800000 +#define MAC_DMA_ISR_S2_TIM_MASK 0x01000000 /* TIM */ +#define MAC_DMA_ISR_S2_CABEND_MASK 0x02000000 /* CABEND */ +#define MAC_DMA_ISR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */ +#define MAC_DMA_ISR_S2_BCNTO_MASK 0x08000000 /* BCNTO */ +#define MAC_DMA_ISR_S2_CABTO_MASK 0x10000000 /* CABTO */ +#define MAC_DMA_ISR_S2_DTIM_MASK 0x20000000 /* DTIM */ +#define MAC_DMA_ISR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */ + +#define MAC_DMA_ISR_S3_ADDRESS 0x00000090 /* MAC Secondary interrupt status register 3 */ +#define MAC_DMA_ISR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF (QCU 0-9) */ +#define MAC_DMA_ISR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */ + +#define MAC_DMA_ISR_S4_ADDRESS 0x00000094 /* MAC Secondary interrupt status register 4 */ +#define MAC_DMA_ISR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (QCU 0-9) */ + +#define MAC_DMA_ISR_S5_ADDRESS 0x00000098 /* MAC Secondary interrupt status register 5 */ +#define MAC_DMA_ISR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001 +#define MAC_DMA_ISR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002 +#define MAC_DMA_ISR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004 +#define MAC_DMA_ISR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008 +#define MAC_DMA_ISR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010 +#define MAC_DMA_ISR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020 +#define MAC_DMA_ISR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040 +#define MAC_DMA_ISR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080 +#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00 +#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_LSB 8 +#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x00000100 << (_i)) +#define MAC_DMA_ISR_S5_TIMER_OVERFLOW_MASK 0x00010000 +#define MAC_DMA_ISR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000 +#define MAC_DMA_ISR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000 +#define MAC_DMA_ISR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000 +#define MAC_DMA_ISR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000 +#define MAC_DMA_ISR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000 +#define MAC_DMA_ISR_S5_QUIET_TIMER_THRESHOLD_MASK 0x00400000 +#define MAC_DMA_ISR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i)) + +#define MAC_DMA_IMR_ADDRESS 0x000000A0 /* MAC Primary interrupt mask register */ +/* + * Interrupt Mask Registers + * + * Only the bits in the IMR control whether the MAC's INTA# + * output will be asserted. The bits in the secondary interrupt + * mask registers control what bits get set in the primary + * interrupt status register; however the IMR_S* registers + * DO NOT determine whether INTA# is asserted. + */ +#define MAC_DMA_IMR_RXOK_MASK 0x00000001 /* At least one frame received sans errors */ +#define MAC_DMA_IMR_RXDESC_MASK 0x00000002 /* Receive interrupt request */ +#define MAC_DMA_IMR_RXERR_MASK 0x00000004 /* Receive error interrupt */ +#define MAC_DMA_IMR_RXNOPKT_MASK 0x00000008 /* No frame received within timeout clock */ +#define MAC_DMA_IMR_RXEOL_MASK 0x00000010 /* Received descriptor empty interrupt */ +#define MAC_DMA_IMR_RXORN_MASK 0x00000020 /* Receive FIFO overrun interrupt */ +#define MAC_DMA_IMR_TXOK_MASK 0x00000040 /* Transmit okay interrupt */ +#define MAC_DMA_IMR_TXDESC_MASK 0x00000080 /* Transmit interrupt request */ +#define MAC_DMA_IMR_TXERR_MASK 0x00000100 /* Transmit error interrupt */ +#define MAC_DMA_IMR_TXNOPKT_MASK 0x00000200 /* No frame transmitted interrupt */ +#define MAC_DMA_IMR_TXEOL_MASK 0x00000400 /* Transmit descriptor empty interrupt */ +#define MAC_DMA_IMR_TXURN_MASK 0x00000800 /* Transmit FIFO underrun interrupt */ +#define MAC_DMA_IMR_MIB_MASK 0x00001000 /* MIB interrupt - see MIBC */ +#define MAC_DMA_IMR_SWI_MASK 0x00002000 /* Software interrupt */ +#define MAC_DMA_IMR_RXPHY_MASK 0x00004000 /* PHY receive error interrupt */ +#define MAC_DMA_IMR_RXKCM_MASK 0x00008000 /* Key-cache miss interrupt */ +#define MAC_DMA_IMR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi hi threshold interrupt */ +#define MAC_DMA_IMR_BRSSI_LO_MASK 0x00020000 /* Beacon rssi lo threshold interrupt */ +#define MAC_DMA_IMR_BMISS_MASK 0x00040000 /* Beacon missed interrupt */ +#define MAC_DMA_IMR_TXMINTR_MASK 0x00080000 /* Maximum transmit interrupt rate */ +#define MAC_DMA_IMR_BNR_MASK 0x00100000 /* BNR interrupt */ +#define MAC_DMA_IMR_HIUERR_MASK 0x00200000 /* An unexpected bus error has occurred */ +#define MAC_DMA_IMR_BCNMISC_MASK 0x00800000 /* Beacon Misc */ +#define MAC_DMA_IMR_RXMINTR_MASK 0x01000000 /* Maximum receive interrupt rate */ +#define MAC_DMA_IMR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow interrupt */ +#define MAC_DMA_IMR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun interrupt */ +#define MAC_DMA_IMR_QTRIG_MASK 0x08000000 /* QCU scheduling trigger interrupt */ +#define MAC_DMA_IMR_TIMER_MASK 0x10000000 /* GENTMR interrupt */ +#define MAC_DMA_IMR_HCFTO_MASK 0x20000000 /* HCFTO interrupt*/ +#define MAC_DMA_IMR_TXINTM_MASK 0x40000000 /* Transmit completion mitigation interrupt */ +#define MAC_DMA_IMR_RXINTM_MASK 0x80000000 /* Receive completion mitigation interrupt */ + +#define MAC_DMA_IMR_S0_ADDRESS 0x000000A4 /* MAC Secondary interrupt mask register 0 */ +#define MAC_DMA_IMR_S0_QCU_TXOK_MASK 0x000003FF /* TXOK (QCU 0-9) */ +#define MAC_DMA_IMR_S0_QCU_TXOK_LSB 0 +#define MAC_DMA_IMR_S0_QCU_TXDESC_MASK 0x03FF0000 /* TXDESC (QCU 0-9) */ +#define MAC_DMA_IMR_S0_QCU_TXDESC_LSB 16 + +#define MAC_DMA_IMR_S1_ADDRESS 0x000000A8 /* MAC Secondary interrupt mask register 1 */ +#define MAC_DMA_IMR_S1_QCU_TXERR_MASK 0x000003FF /* TXERR (QCU 0-9) */ +#define MAC_DMA_IMR_S1_QCU_TXERR_LSB 0 +#define MAC_DMA_IMR_S1_QCU_TXEOL_MASK 0x03FF0000 /* TXEOL (QCU 0-9) */ +#define MAC_DMA_IMR_S1_QCU_TXEOL_LSB 16 + +#define MAC_DMA_IMR_S2_ADDRESS 0x000000AC /* MAC Secondary interrupt mask register 2 */ +#define MAC_DMA_IMR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN (QCU 0-9) */ +#define MAC_DMA_IMR_S2_QCU_TXURN_LSB 0 +#define MAC_DMA_IMR_S2_RX_INT_MASK 0x00000800 +#define MAC_DMA_IMR_S2_WL_STOMPED_MASK 0x00001000 +#define MAC_DMA_IMR_S2_RX_PTR_BAD_MASK 0x00002000 +#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000 +#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000 +#define MAC_DMA_IMR_S2_BB_PANIC_IRQ_MASK 0x00010000 +#define MAC_DMA_IMR_S2_BT_STOMPED_MASK 0x00020000 +#define MAC_DMA_IMR_S2_BT_ACTIVE_RISING_MASK 0x00040000 +#define MAC_DMA_IMR_S2_BT_ACTIVE_FALLING_MASK 0x00080000 +#define MAC_DMA_IMR_S2_BT_PRIORITY_RISING_MASK 0x00100000 +#define MAC_DMA_IMR_S2_BT_PRIORITY_FALLING_MASK 0x00200000 +#define MAC_DMA_IMR_S2_CST_MASK 0x00400000 +#define MAC_DMA_IMR_S2_GTT_MASK 0x00800000 +#define MAC_DMA_IMR_S2_TIM_MASK 0x01000000 /* TIM */ +#define MAC_DMA_IMR_S2_CABEND_MASK 0x02000000 /* CABEND */ +#define MAC_DMA_IMR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */ +#define MAC_DMA_IMR_S2_BCNTO_MASK 0x08000000 /* BCNTO */ +#define MAC_DMA_IMR_S2_CABTO_MASK 0x10000000 /* CABTO */ +#define MAC_DMA_IMR_S2_DTIM_MASK 0x20000000 /* DTIM */ +#define MAC_DMA_IMR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */ + +#define MAC_DMA_IMR_S3_ADDRESS 0x000000B0 /* MAC Secondary interrupt mask register 3 */ +#define MAC_DMA_IMR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF (QCU 0-9) */ +#define MAC_DMA_IMR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */ +#define MAC_DMA_IMR_S3_QCU_QCBRURN_LSB 16 + +#define MAC_DMA_IMR_S4_ADDRESS 0x000000B4 /* MAC Secondary interrupt mask register 4 */ +#define MAC_DMA_IMR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (QCU 0-9) */ + +#define MAC_DMA_IMR_S5_ADDRESS 0x000000B8 /* MAC Secondary interrupt mask register 5 */ +#define MAC_DMA_IMR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001 +#define MAC_DMA_IMR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002 +#define MAC_DMA_IMR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004 +#define MAC_DMA_IMR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008 +#define MAC_DMA_IMR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010 +#define MAC_DMA_IMR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020 +#define MAC_DMA_IMR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040 +#define MAC_DMA_IMR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_LSB 8 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x100 << (_i)) +#define MAC_DMA_IMR_S5_TIMER_OVERFLOW_MASK 0x00010000 +#define MAC_DMA_IMR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000 +#define MAC_DMA_IMR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000 +#define MAC_DMA_IMR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000 +#define MAC_DMA_IMR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000 +#define MAC_DMA_IMR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000 +#define MAC_DMA_IMR_S5_QUIET_TIMER_THRESHOLD_MASK 0000400000 +#define MAC_DMA_IMR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i)) + +#define MAC_DMA_ISR_RAC_ADDRESS 0x000000C0 /* ISR read-and-clear access */ + +/* Shadow copies with read-and-clear access */ +#define MAC_DMA_ISR_S0_S_ADDRESS 0x000000C4 /* ISR_S0 shadow copy */ +#define MAC_DMA_ISR_S1_S_ADDRESS 0x000000C8 /* ISR_S1 shadow copy */ +#define MAC_DMA_ISR_S2_S_ADDRESS 0x000000Cc /* ISR_S2 shadow copy */ +#define MAC_DMA_ISR_S3_S_ADDRESS 0x000000D0 /* ISR_S3 shadow copy */ +#define MAC_DMA_ISR_S4_S_ADDRESS 0x000000D4 /* ISR_S4 shadow copy */ +#define MAC_DMA_ISR_S5_S_ADDRESS 0x000000D8 /* ISR_S5 shadow copy */ + +#define MAC_DMA_Q0_TXDP_ADDRESS 0x00000800 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q1_TXDP_ADDRESS 0x00000804 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q2_TXDP_ADDRESS 0x00000808 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q3_TXDP_ADDRESS 0x0000080C /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q4_TXDP_ADDRESS 0x00000810 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q5_TXDP_ADDRESS 0x00000814 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q6_TXDP_ADDRESS 0x00000818 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q7_TXDP_ADDRESS 0x0000081C /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q8_TXDP_ADDRESS 0x00000820 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q9_TXDP_ADDRESS 0x00000824 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_QTXDP_ADDRESS(_i) (MAC_DMA_Q0_TXDP_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_Q_TXE_ADDRESS 0x00000840 /* MAC Transmit Queue enable */ +#define MAC_DMA_Q_TXD_ADDRESS 0x00000880 /* MAC Transmit Queue disable */ +/* QCU registers */ + +#define MAC_DMA_Q0_CBRCFG_ADDRESS 0x000008C0 /* MAC CBR configuration */ +#define MAC_DMA_Q1_CBRCFG_ADDRESS 0x000008C4 /* MAC CBR configuration */ +#define MAC_DMA_Q2_CBRCFG_ADDRESS 0x000008C8 /* MAC CBR configuration */ +#define MAC_DMA_Q3_CBRCFG_ADDRESS 0x000008CC /* MAC CBR configuration */ +#define MAC_DMA_Q4_CBRCFG_ADDRESS 0x000008D0 /* MAC CBR configuration */ +#define MAC_DMA_Q5_CBRCFG_ADDRESS 0x000008D4 /* MAC CBR configuration */ +#define MAC_DMA_Q6_CBRCFG_ADDRESS 0x000008D8 /* MAC CBR configuration */ +#define MAC_DMA_Q7_CBRCFG_ADDRESS 0x000008DC /* MAC CBR configuration */ +#define MAC_DMA_Q8_CBRCFG_ADDRESS 0x000008E0 /* MAC CBR configuration */ +#define MAC_DMA_Q9_CBRCFG_ADDRESS 0x000008E4 /* MAC CBR configuration */ +#define MAC_DMA_QCBRCFG_ADDRESS(_i) (MAC_DMA_Q0_CBRCFG_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_MASK 0x00FFFFFF /* Mask for CBR interval (us) */ +#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_LSB 0 /* Shift for CBR interval */ +#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_MASK 0xFF000000 /* Mask for CBR overflow threshold */ +#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_LSB 24 /* Shift for CBR overflow thresh */ + + +#define MAC_DMA_Q0_RDYTIMECFG_ADDRESS 0x00000900 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q1_RDYTIMECFG_ADDRESS 0x00000904 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q2_RDYTIMECFG_ADDRESS 0x00000908 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q3_RDYTIMECFG_ADDRESS 0x0000090C /* MAC ReadyTime configuration */ +#define MAC_DMA_Q4_RDYTIMECFG_ADDRESS 0x00000910 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q5_RDYTIMECFG_ADDRESS 0x00000914 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q6_RDYTIMECFG_ADDRESS 0x00000918 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q7_RDYTIMECFG_ADDRESS 0x0000091C /* MAC ReadyTime configuration */ +#define MAC_DMA_Q8_RDYTIMECFG_ADDRESS 0x00000920 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q9_RDYTIMECFG_ADDRESS 0x00000924 /* MAC ReadyTime configuration */ +#define MAC_DMA_QRDYTIMECFG_ADDRESS(_i) (MAC_DMA_Q0_RDYTIMECFG_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_Q_RDYTIMECFG_INT_MASK 0x00FFFFFF /* CBR interval (us) */ +#define MAC_DMA_Q_RDYTIMECFG_INT_LSB 0 /* Shift for ReadyTime Interval (us) */ +#define MAC_DMA_Q_RDYTIMECFG_ENA_MASK 0x01000000 /* CBR enable */ + +#define MAC_DMA_Q_ONESHOTMAC_DMAM_SC_ADDRESS 0x00000940 /* MAC OneShotArm set control */ +#define MAC_DMA_Q_ONESHOTMAC_DMAM_CC_ADDRESS 0x00000980 /* MAC OneShotArm clear control */ + +#define MAC_DMA_Q0_MISC_ADDRESS 0x000009C0 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q1_MISC_ADDRESS 0x000009C4 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q2_MISC_ADDRESS 0x000009C8 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q3_MISC_ADDRESS 0x000009CC /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q4_MISC_ADDRESS 0x000009D0 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q5_MISC_ADDRESS 0x000009D4 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q6_MISC_ADDRESS 0x000009D8 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q7_MISC_ADDRESS 0x000009DC /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q8_MISC_ADDRESS 0x000009E0 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q9_MISC_ADDRESS 0x000009E4 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_QMISC_ADDRESS(_i) (MAC_DMA_Q0_MISC_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_Q_MISC_FSP_MASK 0x0000000F /* Frame Scheduling Policy mask */ +#define MAC_DMA_Q_MISC_FSP_ASAP 0 /* ASAP */ +#define MAC_DMA_Q_MISC_FSP_CBR 1 /* CBR */ +#define MAC_DMA_Q_MISC_FSP_DBA_GATED 2 /* DMA Beacon Alert gated */ +#define MAC_DMA_Q_MISC_FSP_TIM_GATED 3 /* TIM gated */ +#define MAC_DMA_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */ +#define MAC_DMA_Q_MISC_ONE_SHOT_EN_MASK 0x00000010 /* OneShot enable */ +#define MAC_DMA_Q_MISC_CBR_INCR_DIS1_MASK 0x00000020 /* Disable CBR expired counter incr + (empty q) */ +#define MAC_DMA_Q_MISC_CBR_INCR_DIS0_MASK 0x00000040 /* Disable CBR expired counter incr + (empty beacon q) */ +#define MAC_DMA_Q_MISC_BEACON_USE_MASK 0x00000080 /* Beacon use indication */ +#define MAC_DMA_Q_MISC_CBR_EXP_CNTR_LIMIT_MASK 0x00000100 /* CBR expired counter limit enable */ +#define MAC_DMA_Q_MISC_RDYTIME_EXP_POLICY_MASK 0x00000200 /* Enable TXE cleared on ReadyTime expired or VEOL */ +#define MAC_DMA_Q_MISC_RESET_CBR_EXP_CTR_MASK 0x00000400 /* Reset CBR expired counter */ +#define MAC_DMA_Q_MISC_DCU_EARLY_TERM_REQ_MASK 0x00000800 /* DCU frame early termination request control */ + +#define MAC_DMA_Q0_STS_ADDRESS 0x00000A00 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q1_STS_ADDRESS 0x00000A04 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q2_STS_ADDRESS 0x00000A08 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q3_STS_ADDRESS 0x00000A0C /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q4_STS_ADDRESS 0x00000A10 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q5_STS_ADDRESS 0x00000A14 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q6_STS_ADDRESS 0x00000A18 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q7_STS_ADDRESS 0x00000A1C /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q8_STS_ADDRESS 0x00000A20 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q9_STS_ADDRESS 0x00000A24 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_QSTS_ADDRESS(_i) (MAC_DMA_Q0_STS_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_Q_STS_PEND_FR_CNT_MASK 0x00000003 /* Mask for Pending Frame Count */ +#define MAC_DMA_Q_STS_CBR_EXP_CNT_MASK 0x0000FF00 /* Mask for CBR expired counter */ + +#define MAC_DMA_Q_RDYTIMESHDN_ADDRESS 0x00000A40 /* MAC ReadyTimeShutdown status */ + +/* DCU registers */ + +#define MAC_DMA_D0_QCUMASK_ADDRESS 0x00001000 /* MAC QCU Mask */ +#define MAC_DMA_D1_QCUMASK_ADDRESS 0x00001004 /* MAC QCU Mask */ +#define MAC_DMA_D2_QCUMASK_ADDRESS 0x00001008 /* MAC QCU Mask */ +#define MAC_DMA_D3_QCUMASK_ADDRESS 0x0000100C /* MAC QCU Mask */ +#define MAC_DMA_D4_QCUMASK_ADDRESS 0x00001010 /* MAC QCU Mask */ +#define MAC_DMA_D5_QCUMASK_ADDRESS 0x00001014 /* MAC QCU Mask */ +#define MAC_DMA_D6_QCUMASK_ADDRESS 0x00001018 /* MAC QCU Mask */ +#define MAC_DMA_D7_QCUMASK_ADDRESS 0x0000101C /* MAC QCU Mask */ +#define MAC_DMA_D8_QCUMASK_ADDRESS 0x00001020 /* MAC QCU Mask */ +#define MAC_DMA_D9_QCUMASK_ADDRESS 0x00001024 /* MAC QCU Mask */ +#define MAC_DMA_DQCUMASK_ADDRESS(_i) (MAC_DMA_D0_QCUMASK_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_D_QCUMASK_MASK 0x000003FF /* Mask for QCU Mask (QCU 0-9) */ + +#define MAC_DMA_D_GBL_IFS_SIFS_ADDRESS 0x00001030 /* DCU global SIFS settings */ + + +#define MAC_DMA_D0_LCL_IFS_ADDRESS 0x00001040 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D1_LCL_IFS_ADDRESS 0x00001044 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D2_LCL_IFS_ADDRESS 0x00001048 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D3_LCL_IFS_ADDRESS 0x0000104C /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D4_LCL_IFS_ADDRESS 0x00001050 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D5_LCL_IFS_ADDRESS 0x00001054 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D6_LCL_IFS_ADDRESS 0x00001058 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D7_LCL_IFS_ADDRESS 0x0000105C /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D8_LCL_IFS_ADDRESS 0x00001060 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D9_LCL_IFS_ADDRESS 0x00001064 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_DLCL_IFS_ADDRESS(_i) (MAC_DMA_D0_LCL_IFS_ADDRESS + ((_i)<<2)) +#define MAC_DMA_D_LCL_IFS_CWMIN_MASK 0x000003FF /* Mask for CW_MIN */ +#define MAC_DMA_D_LCL_IFS_CWMIN_LSB 0 +#define MAC_DMA_D_LCL_IFS_CWMAX_MASK 0x000FFC00 /* Mask for CW_MAX */ +#define MAC_DMA_D_LCL_IFS_CWMAX_LSB 10 +#define MAC_DMA_D_LCL_IFS_AIFS_MASK 0x0FF00000 /* Mask for AIFS */ +#define MAC_DMA_D_LCL_IFS_AIFS_LSB 20 +/* + * Note: even though this field is 8 bits wide the + * maximum supported AIFS value is 0xFc. Setting the AIFS value + * to 0xFd 0xFe, or 0xFf will not work correctly and will cause + * the DCU to hang. + */ +#define MAC_DMA_D_GBL_IFS_SLOT_ADDRESS 0x00001070 /* DC global slot interval */ + +#define MAC_DMA_D0_RETRY_LIMIT_ADDRESS 0x00001080 /* MAC Retry limits */ +#define MAC_DMA_D1_RETRY_LIMIT_ADDRESS 0x00001084 /* MAC Retry limits */ +#define MAC_DMA_D2_RETRY_LIMIT_ADDRESS 0x00001088 /* MAC Retry limits */ +#define MAC_DMA_D3_RETRY_LIMIT_ADDRESS 0x0000108C /* MAC Retry limits */ +#define MAC_DMA_D4_RETRY_LIMIT_ADDRESS 0x00001090 /* MAC Retry limits */ +#define MAC_DMA_D5_RETRY_LIMIT_ADDRESS 0x00001094 /* MAC Retry limits */ +#define MAC_DMA_D6_RETRY_LIMIT_ADDRESS 0x00001098 /* MAC Retry limits */ +#define MAC_DMA_D7_RETRY_LIMIT_ADDRESS 0x0000109C /* MAC Retry limits */ +#define MAC_DMA_D8_RETRY_LIMIT_ADDRESS 0x000010A0 /* MAC Retry limits */ +#define MAC_DMA_D9_RETRY_LIMIT_ADDRESS 0x000010A4 /* MAC Retry limits */ +#define MAC_DMA_DRETRY_LIMIT_ADDRESS(_i) (MAC_DMA_D0_RETRY_LIMIT_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_MASK 0x0000000F /* frame RTS failure limit */ +#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_LSB 0 +#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_MASK 0x00003F00 /* station RTS failure limit */ +#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_LSB 8 +#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_MASK 0x000FC000 /* station short retry limit */ +#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_LSB 14 + +#define MAC_DMA_D_GBL_IFS_EIFS_ADDRESS 0x000010B0 /* DCU global EIFS setting */ + +#define MAC_DMA_D0_CHNTIME_ADDRESS 0x000010C0 /* MAC ChannelTime settings */ +#define MAC_DMA_D1_CHNTIME_ADDRESS 0x000010C4 /* MAC ChannelTime settings */ +#define MAC_DMA_D2_CHNTIME_ADDRESS 0x000010C8 /* MAC ChannelTime settings */ +#define MAC_DMA_D3_CHNTIME_ADDRESS 0x000010CC /* MAC ChannelTime settings */ +#define MAC_DMA_D4_CHNTIME_ADDRESS 0x000010D0 /* MAC ChannelTime settings */ +#define MAC_DMA_D5_CHNTIME_ADDRESS 0x000010D4 /* MAC ChannelTime settings */ +#define MAC_DMA_D6_CHNTIME_ADDRESS 0x000010D8 /* MAC ChannelTime settings */ +#define MAC_DMA_D7_CHNTIME_ADDRESS 0x000010DC /* MAC ChannelTime settings */ +#define MAC_DMA_D8_CHNTIME_ADDRESS 0x000010E0 /* MAC ChannelTime settings */ +#define MAC_DMA_D9_CHNTIME_ADDRESS 0x000010E4 /* MAC ChannelTime settings */ +#define MAC_DMA_DCHNTIME_ADDRESS(_i) (MAC_DMA_D0_CHNTIME_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_D_CHNTIME_DUR_MASK 0x000FFFFF /* ChannelTime duration (us) */ +#define MAC_DMA_D_CHNTIME_DUR_LSB 0 /* Shift for ChannelTime duration */ +#define MAC_DMA_D_CHNTIME_EN_MASK 0x00100000 /* ChannelTime enable */ + +#define MAC_DMA_D_GBL_IFS_MISC_ADDRESS 0x000010f0 /* DCU global misc. IFS settings */ +#define MAC_DMA_D_GBL_IFS_MISC_LFSR_SLICE_SEL_MASK 0x00000007 /* LFSR slice select */ +#define MAC_DMA_D_GBL_IFS_MISC_TURBO_MODE_MASK 0x00000008 /* Turbo mode indication */ +#define MAC_DMA_D_GBL_IFS_MISC_DCU_ARBITER_DLY_MASK 0x00300000 /* DCU arbiter delay */ +#define MAC_DMA_D_GBL_IFS_IGNORE_BACKOFF_MASK 0x10000000 + +#define MAC_DMA_D0_MISC_ADDRESS 0x00001100 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D1_MISC_ADDRESS 0x00001104 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D2_MISC_ADDRESS 0x00001108 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D3_MISC_ADDRESS 0x0000110C /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D4_MISC_ADDRESS 0x00001110 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D5_MISC_ADDRESS 0x00001114 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D6_MISC_ADDRESS 0x00001118 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D7_MISC_ADDRESS 0x0000111C /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D8_MISC_ADDRESS 0x00001120 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D9_MISC_ADDRESS 0x00001124 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_DMISC_ADDRESS(_i) (MAC_DMA_D0_MISC_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_D0_EOL_ADDRESS 0x00001180 +#define MAC_DMA_D1_EOL_ADDRESS 0x00001184 +#define MAC_DMA_D2_EOL_ADDRESS 0x00001188 +#define MAC_DMA_D3_EOL_ADDRESS 0x0000118C +#define MAC_DMA_D4_EOL_ADDRESS 0x00001190 +#define MAC_DMA_D5_EOL_ADDRESS 0x00001194 +#define MAC_DMA_D6_EOL_ADDRESS 0x00001198 +#define MAC_DMA_D7_EOL_ADDRESS 0x0000119C +#define MAC_DMA_D8_EOL_ADDRESS 0x00001200 +#define MAC_DMA_D9_EOL_ADDRESS 0x00001204 +#define MAC_DMA_DEOL_ADDRESS(_i) (MAC_DMA_D0_EOL_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_D_MISC_BKOFF_THRESH_MASK 0x0000003F /* Backoff threshold */ +#define MAC_DMA_D_MISC_BACK_OFF_THRESH_LSB 0 +#define MAC_DMA_D_MISC_ETS_RTS_MASK 0x00000040 /* End of transmission series + station RTS/data failure + count reset policy */ +#define MAC_DMA_D_MISC_ETS_CW_MASK 0x00000080 /* End of transmission series + CW reset policy */ +#define MAC_DMA_D_MISC_FRAG_WAIT_EN_MASK 0x00000100 /* Fragment Starvation Policy */ + +#define MAC_DMA_D_MISC_FRAG_BKOFF_EN_MASK 0x00000200 /* Backoff during a frag burst */ +#define MAC_DMA_D_MISC_HCF_POLL_EN_MASK 0x00000800 /* HFC poll enable */ +#define MAC_DMA_D_MISC_BKOFF_PERSISTENCE_MASK 0x00001000 /* Backoff persistence factor + setting */ +#define MAC_DMA_D_MISC_VIR_COL_HANDLING_MASK 0x0000C000 /* Mask for Virtual collision + handling policy */ +#define MAC_DMA_D_MISC_VIR_COL_HANDLING_LSB 14 +#define MAC_DMA_D_MISC_VIR_COL_HANDLING_DEFAULT 0 /* Normal */ +#define MAC_DMA_D_MISC_VIR_COL_HANDLING_IGNORE 1 /* Ignore */ +#define MAC_DMA_D_MISC_BEACON_USE_MASK 0x00010000 /* Beacon use indication */ +#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_MASK 0x00060000 /* Mask for DCU arbiter lockout control */ +#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_LSB 17 +#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 /* No lockout*/ +#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame*/ +#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 /* Global */ +#define MAC_DMA_D_MISC_ARB_LOCKOUT_IGNORE_MASK 0x00080000 /* DCU arbiter lockout ignore control */ +#define MAC_DMA_D_MISC_SEQ_NUM_INCR_DIS_MASK 0x00100000 /* Sequence number increment disable */ +#define MAC_DMA_D_MISC_POST_FR_BKOFF_DIS_MASK 0x00200000 /* Post-frame backoff disable */ +#define MAC_DMA_D_MISC_VIRT_COLL_POLICY_MASK 0x00400000 /* Virtual coll. handling policy */ +#define MAC_DMA_D_MISC_BLOWN_IFS_POLICY_MASK 0x00800000 /* Blown IFS handling policy */ + +#define MAC_DMA_D_SEQNUM_ADDRESS 0x00001140 /* MAC Frame sequence number */ + + + +#define MAC_DMA_D_FPCTL_ADDRESS 0x00001230 /* DCU frame prefetch settings */ +#define MAC_DMA_D_TXPSE_ADDRESS 0x00001270 /* DCU transmit pause control/status */ + +#endif /* _AR6000_DMMAEG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_pcu_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_pcu_reg.h new file mode 100644 index 000000000000..6ccb08c5dab2 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_pcu_reg.h @@ -0,0 +1,3065 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MAC_PCU_REG_H_ +#define _MAC_PCU_REG_H_ + +#define MAC_PCU_STA_ADDR_L32_ADDRESS 0x00008000 +#define MAC_PCU_STA_ADDR_L32_OFFSET 0x00000000 +#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_MSB 31 +#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB 0 +#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK 0xffffffff +#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_GET(x) (((x) & MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK) >> MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB) +#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_SET(x) (((x) << MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB) & MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK) + +#define MAC_PCU_STA_ADDR_U16_ADDRESS 0x00008004 +#define MAC_PCU_STA_ADDR_U16_OFFSET 0x00000004 +#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MSB 31 +#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB 31 +#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK 0x80000000 +#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK) >> MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB) +#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB) & MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK) +#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MSB 30 +#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB 30 +#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK 0x40000000 +#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK) >> MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB) +#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB) & MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK) +#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MSB 29 +#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB 29 +#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK 0x20000000 +#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK) >> MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB) +#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB) & MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK) +#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MSB 28 +#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB 28 +#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK 0x10000000 +#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK) >> MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB) +#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB) & MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK) +#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MSB 27 +#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB 27 +#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK 0x08000000 +#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK) >> MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB) +#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB) & MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK) +#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MSB 26 +#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB 26 +#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK 0x04000000 +#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK) >> MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB) +#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB) & MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK) +#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MSB 25 +#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB 25 +#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK 0x02000000 +#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK) >> MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB) +#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB) & MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK) +#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MSB 24 +#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB 24 +#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK 0x01000000 +#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK) >> MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB) +#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB) & MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK) +#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MSB 23 +#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB 23 +#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK 0x00800000 +#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK) >> MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB) +#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB) & MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK) +#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MSB 22 +#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB 22 +#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK 0x00400000 +#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK) >> MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB) +#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB) & MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK) +#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_MSB 21 +#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB 21 +#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK 0x00200000 +#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK) >> MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB) +#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB) & MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK) +#define MAC_PCU_STA_ADDR_U16_PCF_MSB 20 +#define MAC_PCU_STA_ADDR_U16_PCF_LSB 20 +#define MAC_PCU_STA_ADDR_U16_PCF_MASK 0x00100000 +#define MAC_PCU_STA_ADDR_U16_PCF_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PCF_MASK) >> MAC_PCU_STA_ADDR_U16_PCF_LSB) +#define MAC_PCU_STA_ADDR_U16_PCF_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PCF_LSB) & MAC_PCU_STA_ADDR_U16_PCF_MASK) +#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MSB 19 +#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB 19 +#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK 0x00080000 +#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK) >> MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB) +#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB) & MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK) +#define MAC_PCU_STA_ADDR_U16_PW_SAVE_MSB 18 +#define MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB 18 +#define MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK 0x00040000 +#define MAC_PCU_STA_ADDR_U16_PW_SAVE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK) >> MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB) +#define MAC_PCU_STA_ADDR_U16_PW_SAVE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB) & MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK) +#define MAC_PCU_STA_ADDR_U16_ADHOC_MSB 17 +#define MAC_PCU_STA_ADDR_U16_ADHOC_LSB 17 +#define MAC_PCU_STA_ADDR_U16_ADHOC_MASK 0x00020000 +#define MAC_PCU_STA_ADDR_U16_ADHOC_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADHOC_MASK) >> MAC_PCU_STA_ADDR_U16_ADHOC_LSB) +#define MAC_PCU_STA_ADDR_U16_ADHOC_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADHOC_LSB) & MAC_PCU_STA_ADDR_U16_ADHOC_MASK) +#define MAC_PCU_STA_ADDR_U16_STA_AP_MSB 16 +#define MAC_PCU_STA_ADDR_U16_STA_AP_LSB 16 +#define MAC_PCU_STA_ADDR_U16_STA_AP_MASK 0x00010000 +#define MAC_PCU_STA_ADDR_U16_STA_AP_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_STA_AP_MASK) >> MAC_PCU_STA_ADDR_U16_STA_AP_LSB) +#define MAC_PCU_STA_ADDR_U16_STA_AP_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_STA_AP_LSB) & MAC_PCU_STA_ADDR_U16_STA_AP_MASK) +#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_MSB 15 +#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB 0 +#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK 0x0000ffff +#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK) >> MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB) +#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB) & MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK) + +#define MAC_PCU_BSSID_L32_ADDRESS 0x00008008 +#define MAC_PCU_BSSID_L32_OFFSET 0x00000008 +#define MAC_PCU_BSSID_L32_ADDR_MSB 31 +#define MAC_PCU_BSSID_L32_ADDR_LSB 0 +#define MAC_PCU_BSSID_L32_ADDR_MASK 0xffffffff +#define MAC_PCU_BSSID_L32_ADDR_GET(x) (((x) & MAC_PCU_BSSID_L32_ADDR_MASK) >> MAC_PCU_BSSID_L32_ADDR_LSB) +#define MAC_PCU_BSSID_L32_ADDR_SET(x) (((x) << MAC_PCU_BSSID_L32_ADDR_LSB) & MAC_PCU_BSSID_L32_ADDR_MASK) + +#define MAC_PCU_BSSID_U16_ADDRESS 0x0000800c +#define MAC_PCU_BSSID_U16_OFFSET 0x0000000c +#define MAC_PCU_BSSID_U16_AID_MSB 26 +#define MAC_PCU_BSSID_U16_AID_LSB 16 +#define MAC_PCU_BSSID_U16_AID_MASK 0x07ff0000 +#define MAC_PCU_BSSID_U16_AID_GET(x) (((x) & MAC_PCU_BSSID_U16_AID_MASK) >> MAC_PCU_BSSID_U16_AID_LSB) +#define MAC_PCU_BSSID_U16_AID_SET(x) (((x) << MAC_PCU_BSSID_U16_AID_LSB) & MAC_PCU_BSSID_U16_AID_MASK) +#define MAC_PCU_BSSID_U16_ADDR_MSB 15 +#define MAC_PCU_BSSID_U16_ADDR_LSB 0 +#define MAC_PCU_BSSID_U16_ADDR_MASK 0x0000ffff +#define MAC_PCU_BSSID_U16_ADDR_GET(x) (((x) & MAC_PCU_BSSID_U16_ADDR_MASK) >> MAC_PCU_BSSID_U16_ADDR_LSB) +#define MAC_PCU_BSSID_U16_ADDR_SET(x) (((x) << MAC_PCU_BSSID_U16_ADDR_LSB) & MAC_PCU_BSSID_U16_ADDR_MASK) + +#define MAC_PCU_BCN_RSSI_AVE_ADDRESS 0x00008010 +#define MAC_PCU_BCN_RSSI_AVE_OFFSET 0x00000010 +#define MAC_PCU_BCN_RSSI_AVE_VALUE_MSB 11 +#define MAC_PCU_BCN_RSSI_AVE_VALUE_LSB 0 +#define MAC_PCU_BCN_RSSI_AVE_VALUE_MASK 0x00000fff +#define MAC_PCU_BCN_RSSI_AVE_VALUE_GET(x) (((x) & MAC_PCU_BCN_RSSI_AVE_VALUE_MASK) >> MAC_PCU_BCN_RSSI_AVE_VALUE_LSB) +#define MAC_PCU_BCN_RSSI_AVE_VALUE_SET(x) (((x) << MAC_PCU_BCN_RSSI_AVE_VALUE_LSB) & MAC_PCU_BCN_RSSI_AVE_VALUE_MASK) + +#define MAC_PCU_ACK_CTS_TIMEOUT_ADDRESS 0x00008014 +#define MAC_PCU_ACK_CTS_TIMEOUT_OFFSET 0x00000014 +#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MSB 29 +#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB 16 +#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK 0x3fff0000 +#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_GET(x) (((x) & MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK) >> MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB) +#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_SET(x) (((x) << MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB) & MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK) +#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MSB 13 +#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB 0 +#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK 0x00003fff +#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_GET(x) (((x) & MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK) >> MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB) +#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_SET(x) (((x) << MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB) & MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK) + +#define MAC_PCU_BCN_RSSI_CTL_ADDRESS 0x00008018 +#define MAC_PCU_BCN_RSSI_CTL_OFFSET 0x00000018 +#define MAC_PCU_BCN_RSSI_CTL_RESET_MSB 29 +#define MAC_PCU_BCN_RSSI_CTL_RESET_LSB 29 +#define MAC_PCU_BCN_RSSI_CTL_RESET_MASK 0x20000000 +#define MAC_PCU_BCN_RSSI_CTL_RESET_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RESET_MASK) >> MAC_PCU_BCN_RSSI_CTL_RESET_LSB) +#define MAC_PCU_BCN_RSSI_CTL_RESET_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RESET_LSB) & MAC_PCU_BCN_RSSI_CTL_RESET_MASK) +#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_MSB 28 +#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB 24 +#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK 0x1f000000 +#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK) >> MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB) +#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB) & MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK) +#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MSB 23 +#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB 16 +#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK 0x00ff0000 +#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB) +#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK) +#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MSB 15 +#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB 8 +#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK 0x0000ff00 +#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB) +#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK) +#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MSB 7 +#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB 0 +#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK 0x000000ff +#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB) +#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK) + +#define MAC_PCU_USEC_LATENCY_ADDRESS 0x0000801c +#define MAC_PCU_USEC_LATENCY_OFFSET 0x0000001c +#define MAC_PCU_USEC_LATENCY_RX_LATENCY_MSB 28 +#define MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB 23 +#define MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK 0x1f800000 +#define MAC_PCU_USEC_LATENCY_RX_LATENCY_GET(x) (((x) & MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK) >> MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB) +#define MAC_PCU_USEC_LATENCY_RX_LATENCY_SET(x) (((x) << MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB) & MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK) +#define MAC_PCU_USEC_LATENCY_TX_LATENCY_MSB 22 +#define MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB 14 +#define MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK 0x007fc000 +#define MAC_PCU_USEC_LATENCY_TX_LATENCY_GET(x) (((x) & MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK) >> MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB) +#define MAC_PCU_USEC_LATENCY_TX_LATENCY_SET(x) (((x) << MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB) & MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK) +#define MAC_PCU_USEC_LATENCY_USEC_MSB 7 +#define MAC_PCU_USEC_LATENCY_USEC_LSB 0 +#define MAC_PCU_USEC_LATENCY_USEC_MASK 0x000000ff +#define MAC_PCU_USEC_LATENCY_USEC_GET(x) (((x) & MAC_PCU_USEC_LATENCY_USEC_MASK) >> MAC_PCU_USEC_LATENCY_USEC_LSB) +#define MAC_PCU_USEC_LATENCY_USEC_SET(x) (((x) << MAC_PCU_USEC_LATENCY_USEC_LSB) & MAC_PCU_USEC_LATENCY_USEC_MASK) + +#define PCU_MAX_CFP_DUR_ADDRESS 0x00008020 +#define PCU_MAX_CFP_DUR_OFFSET 0x00000020 +#define PCU_MAX_CFP_DUR_VALUE_MSB 15 +#define PCU_MAX_CFP_DUR_VALUE_LSB 0 +#define PCU_MAX_CFP_DUR_VALUE_MASK 0x0000ffff +#define PCU_MAX_CFP_DUR_VALUE_GET(x) (((x) & PCU_MAX_CFP_DUR_VALUE_MASK) >> PCU_MAX_CFP_DUR_VALUE_LSB) +#define PCU_MAX_CFP_DUR_VALUE_SET(x) (((x) << PCU_MAX_CFP_DUR_VALUE_LSB) & PCU_MAX_CFP_DUR_VALUE_MASK) + +#define MAC_PCU_RX_FILTER_ADDRESS 0x00008024 +#define MAC_PCU_RX_FILTER_OFFSET 0x00000024 +#define MAC_PCU_RX_FILTER_GENERIC_FILTER_MSB 25 +#define MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB 24 +#define MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK 0x03000000 +#define MAC_PCU_RX_FILTER_GENERIC_FILTER_GET(x) (((x) & MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK) >> MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB) +#define MAC_PCU_RX_FILTER_GENERIC_FILTER_SET(x) (((x) << MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB) & MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK) +#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_MSB 23 +#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB 18 +#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK 0x00fc0000 +#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_GET(x) (((x) & MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK) >> MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB) +#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_SET(x) (((x) << MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB) & MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK) +#define MAC_PCU_RX_FILTER_FROM_TO_DS_MSB 17 +#define MAC_PCU_RX_FILTER_FROM_TO_DS_LSB 17 +#define MAC_PCU_RX_FILTER_FROM_TO_DS_MASK 0x00020000 +#define MAC_PCU_RX_FILTER_FROM_TO_DS_GET(x) (((x) & MAC_PCU_RX_FILTER_FROM_TO_DS_MASK) >> MAC_PCU_RX_FILTER_FROM_TO_DS_LSB) +#define MAC_PCU_RX_FILTER_FROM_TO_DS_SET(x) (((x) << MAC_PCU_RX_FILTER_FROM_TO_DS_LSB) & MAC_PCU_RX_FILTER_FROM_TO_DS_MASK) +#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MSB 16 +#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB 16 +#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK 0x00010000 +#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_GET(x) (((x) & MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK) >> MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB) +#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_SET(x) (((x) << MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB) & MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK) +#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MSB 15 +#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB 15 +#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK 0x00008000 +#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_GET(x) (((x) & MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK) >> MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB) +#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_SET(x) (((x) << MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB) & MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK) +#define MAC_PCU_RX_FILTER_PS_POLL_MSB 14 +#define MAC_PCU_RX_FILTER_PS_POLL_LSB 14 +#define MAC_PCU_RX_FILTER_PS_POLL_MASK 0x00004000 +#define MAC_PCU_RX_FILTER_PS_POLL_GET(x) (((x) & MAC_PCU_RX_FILTER_PS_POLL_MASK) >> MAC_PCU_RX_FILTER_PS_POLL_LSB) +#define MAC_PCU_RX_FILTER_PS_POLL_SET(x) (((x) << MAC_PCU_RX_FILTER_PS_POLL_LSB) & MAC_PCU_RX_FILTER_PS_POLL_MASK) +#define MAC_PCU_RX_FILTER_ASSUME_RADAR_MSB 13 +#define MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB 13 +#define MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK 0x00002000 +#define MAC_PCU_RX_FILTER_ASSUME_RADAR_GET(x) (((x) & MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK) >> MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB) +#define MAC_PCU_RX_FILTER_ASSUME_RADAR_SET(x) (((x) << MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB) & MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK) +#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MSB 12 +#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB 12 +#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK 0x00001000 +#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_GET(x) (((x) & MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK) >> MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB) +#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_SET(x) (((x) << MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB) & MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK) +#define MAC_PCU_RX_FILTER_COMPRESSED_BA_MSB 11 +#define MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB 11 +#define MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK 0x00000800 +#define MAC_PCU_RX_FILTER_COMPRESSED_BA_GET(x) (((x) & MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK) >> MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB) +#define MAC_PCU_RX_FILTER_COMPRESSED_BA_SET(x) (((x) << MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB) & MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK) +#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_MSB 10 +#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB 10 +#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK 0x00000400 +#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_GET(x) (((x) & MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK) >> MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB) +#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_SET(x) (((x) << MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB) & MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK) +#define MAC_PCU_RX_FILTER_MY_BEACON_MSB 9 +#define MAC_PCU_RX_FILTER_MY_BEACON_LSB 9 +#define MAC_PCU_RX_FILTER_MY_BEACON_MASK 0x00000200 +#define MAC_PCU_RX_FILTER_MY_BEACON_GET(x) (((x) & MAC_PCU_RX_FILTER_MY_BEACON_MASK) >> MAC_PCU_RX_FILTER_MY_BEACON_LSB) +#define MAC_PCU_RX_FILTER_MY_BEACON_SET(x) (((x) << MAC_PCU_RX_FILTER_MY_BEACON_LSB) & MAC_PCU_RX_FILTER_MY_BEACON_MASK) +#define MAC_PCU_RX_FILTER_SYNC_FRAME_MSB 8 +#define MAC_PCU_RX_FILTER_SYNC_FRAME_LSB 8 +#define MAC_PCU_RX_FILTER_SYNC_FRAME_MASK 0x00000100 +#define MAC_PCU_RX_FILTER_SYNC_FRAME_GET(x) (((x) & MAC_PCU_RX_FILTER_SYNC_FRAME_MASK) >> MAC_PCU_RX_FILTER_SYNC_FRAME_LSB) +#define MAC_PCU_RX_FILTER_SYNC_FRAME_SET(x) (((x) << MAC_PCU_RX_FILTER_SYNC_FRAME_LSB) & MAC_PCU_RX_FILTER_SYNC_FRAME_MASK) +#define MAC_PCU_RX_FILTER_PROBE_REQ_MSB 7 +#define MAC_PCU_RX_FILTER_PROBE_REQ_LSB 7 +#define MAC_PCU_RX_FILTER_PROBE_REQ_MASK 0x00000080 +#define MAC_PCU_RX_FILTER_PROBE_REQ_GET(x) (((x) & MAC_PCU_RX_FILTER_PROBE_REQ_MASK) >> MAC_PCU_RX_FILTER_PROBE_REQ_LSB) +#define MAC_PCU_RX_FILTER_PROBE_REQ_SET(x) (((x) << MAC_PCU_RX_FILTER_PROBE_REQ_LSB) & MAC_PCU_RX_FILTER_PROBE_REQ_MASK) +#define MAC_PCU_RX_FILTER_XR_POLL_MSB 6 +#define MAC_PCU_RX_FILTER_XR_POLL_LSB 6 +#define MAC_PCU_RX_FILTER_XR_POLL_MASK 0x00000040 +#define MAC_PCU_RX_FILTER_XR_POLL_GET(x) (((x) & MAC_PCU_RX_FILTER_XR_POLL_MASK) >> MAC_PCU_RX_FILTER_XR_POLL_LSB) +#define MAC_PCU_RX_FILTER_XR_POLL_SET(x) (((x) << MAC_PCU_RX_FILTER_XR_POLL_LSB) & MAC_PCU_RX_FILTER_XR_POLL_MASK) +#define MAC_PCU_RX_FILTER_PROMISCUOUS_MSB 5 +#define MAC_PCU_RX_FILTER_PROMISCUOUS_LSB 5 +#define MAC_PCU_RX_FILTER_PROMISCUOUS_MASK 0x00000020 +#define MAC_PCU_RX_FILTER_PROMISCUOUS_GET(x) (((x) & MAC_PCU_RX_FILTER_PROMISCUOUS_MASK) >> MAC_PCU_RX_FILTER_PROMISCUOUS_LSB) +#define MAC_PCU_RX_FILTER_PROMISCUOUS_SET(x) (((x) << MAC_PCU_RX_FILTER_PROMISCUOUS_LSB) & MAC_PCU_RX_FILTER_PROMISCUOUS_MASK) +#define MAC_PCU_RX_FILTER_BEACON_MSB 4 +#define MAC_PCU_RX_FILTER_BEACON_LSB 4 +#define MAC_PCU_RX_FILTER_BEACON_MASK 0x00000010 +#define MAC_PCU_RX_FILTER_BEACON_GET(x) (((x) & MAC_PCU_RX_FILTER_BEACON_MASK) >> MAC_PCU_RX_FILTER_BEACON_LSB) +#define MAC_PCU_RX_FILTER_BEACON_SET(x) (((x) << MAC_PCU_RX_FILTER_BEACON_LSB) & MAC_PCU_RX_FILTER_BEACON_MASK) +#define MAC_PCU_RX_FILTER_CONTROL_MSB 3 +#define MAC_PCU_RX_FILTER_CONTROL_LSB 3 +#define MAC_PCU_RX_FILTER_CONTROL_MASK 0x00000008 +#define MAC_PCU_RX_FILTER_CONTROL_GET(x) (((x) & MAC_PCU_RX_FILTER_CONTROL_MASK) >> MAC_PCU_RX_FILTER_CONTROL_LSB) +#define MAC_PCU_RX_FILTER_CONTROL_SET(x) (((x) << MAC_PCU_RX_FILTER_CONTROL_LSB) & MAC_PCU_RX_FILTER_CONTROL_MASK) +#define MAC_PCU_RX_FILTER_BROADCAST_MSB 2 +#define MAC_PCU_RX_FILTER_BROADCAST_LSB 2 +#define MAC_PCU_RX_FILTER_BROADCAST_MASK 0x00000004 +#define MAC_PCU_RX_FILTER_BROADCAST_GET(x) (((x) & MAC_PCU_RX_FILTER_BROADCAST_MASK) >> MAC_PCU_RX_FILTER_BROADCAST_LSB) +#define MAC_PCU_RX_FILTER_BROADCAST_SET(x) (((x) << MAC_PCU_RX_FILTER_BROADCAST_LSB) & MAC_PCU_RX_FILTER_BROADCAST_MASK) +#define MAC_PCU_RX_FILTER_MULTICAST_MSB 1 +#define MAC_PCU_RX_FILTER_MULTICAST_LSB 1 +#define MAC_PCU_RX_FILTER_MULTICAST_MASK 0x00000002 +#define MAC_PCU_RX_FILTER_MULTICAST_GET(x) (((x) & MAC_PCU_RX_FILTER_MULTICAST_MASK) >> MAC_PCU_RX_FILTER_MULTICAST_LSB) +#define MAC_PCU_RX_FILTER_MULTICAST_SET(x) (((x) << MAC_PCU_RX_FILTER_MULTICAST_LSB) & MAC_PCU_RX_FILTER_MULTICAST_MASK) +#define MAC_PCU_RX_FILTER_UNICAST_MSB 0 +#define MAC_PCU_RX_FILTER_UNICAST_LSB 0 +#define MAC_PCU_RX_FILTER_UNICAST_MASK 0x00000001 +#define MAC_PCU_RX_FILTER_UNICAST_GET(x) (((x) & MAC_PCU_RX_FILTER_UNICAST_MASK) >> MAC_PCU_RX_FILTER_UNICAST_LSB) +#define MAC_PCU_RX_FILTER_UNICAST_SET(x) (((x) << MAC_PCU_RX_FILTER_UNICAST_LSB) & MAC_PCU_RX_FILTER_UNICAST_MASK) + +#define MAC_PCU_MCAST_FILTER_L32_ADDRESS 0x00008028 +#define MAC_PCU_MCAST_FILTER_L32_OFFSET 0x00000028 +#define MAC_PCU_MCAST_FILTER_L32_VALUE_MSB 31 +#define MAC_PCU_MCAST_FILTER_L32_VALUE_LSB 0 +#define MAC_PCU_MCAST_FILTER_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_MCAST_FILTER_L32_VALUE_GET(x) (((x) & MAC_PCU_MCAST_FILTER_L32_VALUE_MASK) >> MAC_PCU_MCAST_FILTER_L32_VALUE_LSB) +#define MAC_PCU_MCAST_FILTER_L32_VALUE_SET(x) (((x) << MAC_PCU_MCAST_FILTER_L32_VALUE_LSB) & MAC_PCU_MCAST_FILTER_L32_VALUE_MASK) + +#define MAC_PCU_MCAST_FILTER_U32_ADDRESS 0x0000802c +#define MAC_PCU_MCAST_FILTER_U32_OFFSET 0x0000002c +#define MAC_PCU_MCAST_FILTER_U32_VALUE_MSB 31 +#define MAC_PCU_MCAST_FILTER_U32_VALUE_LSB 0 +#define MAC_PCU_MCAST_FILTER_U32_VALUE_MASK 0xffffffff +#define MAC_PCU_MCAST_FILTER_U32_VALUE_GET(x) (((x) & MAC_PCU_MCAST_FILTER_U32_VALUE_MASK) >> MAC_PCU_MCAST_FILTER_U32_VALUE_LSB) +#define MAC_PCU_MCAST_FILTER_U32_VALUE_SET(x) (((x) << MAC_PCU_MCAST_FILTER_U32_VALUE_LSB) & MAC_PCU_MCAST_FILTER_U32_VALUE_MASK) + +#define MAC_PCU_DIAG_SW_ADDRESS 0x00008030 +#define MAC_PCU_DIAG_SW_OFFSET 0x00000030 +#define MAC_PCU_DIAG_SW_DEBUG_MODE_MSB 31 +#define MAC_PCU_DIAG_SW_DEBUG_MODE_LSB 30 +#define MAC_PCU_DIAG_SW_DEBUG_MODE_MASK 0xc0000000 +#define MAC_PCU_DIAG_SW_DEBUG_MODE_GET(x) (((x) & MAC_PCU_DIAG_SW_DEBUG_MODE_MASK) >> MAC_PCU_DIAG_SW_DEBUG_MODE_LSB) +#define MAC_PCU_DIAG_SW_DEBUG_MODE_SET(x) (((x) << MAC_PCU_DIAG_SW_DEBUG_MODE_LSB) & MAC_PCU_DIAG_SW_DEBUG_MODE_MASK) +#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MSB 29 +#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB 29 +#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK 0x20000000 +#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB) +#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK) +#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MSB 28 +#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB 28 +#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK 0x10000000 +#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB) +#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK) +#define MAC_PCU_DIAG_SW_OBS_SEL_2_MSB 27 +#define MAC_PCU_DIAG_SW_OBS_SEL_2_LSB 27 +#define MAC_PCU_DIAG_SW_OBS_SEL_2_MASK 0x08000000 +#define MAC_PCU_DIAG_SW_OBS_SEL_2_GET(x) (((x) & MAC_PCU_DIAG_SW_OBS_SEL_2_MASK) >> MAC_PCU_DIAG_SW_OBS_SEL_2_LSB) +#define MAC_PCU_DIAG_SW_OBS_SEL_2_SET(x) (((x) << MAC_PCU_DIAG_SW_OBS_SEL_2_LSB) & MAC_PCU_DIAG_SW_OBS_SEL_2_MASK) +#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MSB 26 +#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB 26 +#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK 0x04000000 +#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_GET(x) (((x) & MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK) >> MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB) +#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_SET(x) (((x) << MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB) & MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK) +#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MSB 25 +#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB 25 +#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK 0x02000000 +#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_GET(x) (((x) & MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK) >> MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB) +#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_SET(x) (((x) << MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB) & MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK) +#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MSB 24 +#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB 24 +#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK 0x01000000 +#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_GET(x) (((x) & MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK) >> MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB) +#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_SET(x) (((x) << MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB) & MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK) +#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MSB 23 +#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB 23 +#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK 0x00800000 +#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_GET(x) (((x) & MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK) >> MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB) +#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_SET(x) (((x) << MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB) & MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK) +#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MSB 22 +#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB 22 +#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK 0x00400000 +#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_GET(x) (((x) & MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK) >> MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB) +#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_SET(x) (((x) << MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB) & MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK) +#define MAC_PCU_DIAG_SW_IGNORE_NAV_MSB 21 +#define MAC_PCU_DIAG_SW_IGNORE_NAV_LSB 21 +#define MAC_PCU_DIAG_SW_IGNORE_NAV_MASK 0x00200000 +#define MAC_PCU_DIAG_SW_IGNORE_NAV_GET(x) (((x) & MAC_PCU_DIAG_SW_IGNORE_NAV_MASK) >> MAC_PCU_DIAG_SW_IGNORE_NAV_LSB) +#define MAC_PCU_DIAG_SW_IGNORE_NAV_SET(x) (((x) << MAC_PCU_DIAG_SW_IGNORE_NAV_LSB) & MAC_PCU_DIAG_SW_IGNORE_NAV_MASK) +#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MSB 20 +#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB 20 +#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK 0x00100000 +#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB) +#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK) +#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_MSB 19 +#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB 18 +#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK 0x000c0000 +#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_GET(x) (((x) & MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK) >> MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB) +#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_SET(x) (((x) << MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB) & MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK) +#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MSB 17 +#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB 17 +#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK 0x00020000 +#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_GET(x) (((x) & MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK) >> MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB) +#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_SET(x) (((x) << MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB) & MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK) +#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MSB 8 +#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB 8 +#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK 0x00000100 +#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_GET(x) (((x) & MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK) >> MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB) +#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_SET(x) (((x) << MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB) & MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK) +#define MAC_PCU_DIAG_SW_CORRUPT_FCS_MSB 7 +#define MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB 7 +#define MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK 0x00000080 +#define MAC_PCU_DIAG_SW_CORRUPT_FCS_GET(x) (((x) & MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK) >> MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB) +#define MAC_PCU_DIAG_SW_CORRUPT_FCS_SET(x) (((x) << MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB) & MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK) +#define MAC_PCU_DIAG_SW_LOOP_BACK_MSB 6 +#define MAC_PCU_DIAG_SW_LOOP_BACK_LSB 6 +#define MAC_PCU_DIAG_SW_LOOP_BACK_MASK 0x00000040 +#define MAC_PCU_DIAG_SW_LOOP_BACK_GET(x) (((x) & MAC_PCU_DIAG_SW_LOOP_BACK_MASK) >> MAC_PCU_DIAG_SW_LOOP_BACK_LSB) +#define MAC_PCU_DIAG_SW_LOOP_BACK_SET(x) (((x) << MAC_PCU_DIAG_SW_LOOP_BACK_LSB) & MAC_PCU_DIAG_SW_LOOP_BACK_MASK) +#define MAC_PCU_DIAG_SW_HALT_RX_MSB 5 +#define MAC_PCU_DIAG_SW_HALT_RX_LSB 5 +#define MAC_PCU_DIAG_SW_HALT_RX_MASK 0x00000020 +#define MAC_PCU_DIAG_SW_HALT_RX_GET(x) (((x) & MAC_PCU_DIAG_SW_HALT_RX_MASK) >> MAC_PCU_DIAG_SW_HALT_RX_LSB) +#define MAC_PCU_DIAG_SW_HALT_RX_SET(x) (((x) << MAC_PCU_DIAG_SW_HALT_RX_LSB) & MAC_PCU_DIAG_SW_HALT_RX_MASK) +#define MAC_PCU_DIAG_SW_NO_DECRYPT_MSB 4 +#define MAC_PCU_DIAG_SW_NO_DECRYPT_LSB 4 +#define MAC_PCU_DIAG_SW_NO_DECRYPT_MASK 0x00000010 +#define MAC_PCU_DIAG_SW_NO_DECRYPT_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_DECRYPT_MASK) >> MAC_PCU_DIAG_SW_NO_DECRYPT_LSB) +#define MAC_PCU_DIAG_SW_NO_DECRYPT_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_DECRYPT_LSB) & MAC_PCU_DIAG_SW_NO_DECRYPT_MASK) +#define MAC_PCU_DIAG_SW_NO_ENCRYPT_MSB 3 +#define MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB 3 +#define MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK 0x00000008 +#define MAC_PCU_DIAG_SW_NO_ENCRYPT_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK) >> MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB) +#define MAC_PCU_DIAG_SW_NO_ENCRYPT_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB) & MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK) +#define MAC_PCU_DIAG_SW_NO_CTS_MSB 2 +#define MAC_PCU_DIAG_SW_NO_CTS_LSB 2 +#define MAC_PCU_DIAG_SW_NO_CTS_MASK 0x00000004 +#define MAC_PCU_DIAG_SW_NO_CTS_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_CTS_MASK) >> MAC_PCU_DIAG_SW_NO_CTS_LSB) +#define MAC_PCU_DIAG_SW_NO_CTS_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_CTS_LSB) & MAC_PCU_DIAG_SW_NO_CTS_MASK) +#define MAC_PCU_DIAG_SW_NO_ACK_MSB 1 +#define MAC_PCU_DIAG_SW_NO_ACK_LSB 1 +#define MAC_PCU_DIAG_SW_NO_ACK_MASK 0x00000002 +#define MAC_PCU_DIAG_SW_NO_ACK_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_ACK_MASK) >> MAC_PCU_DIAG_SW_NO_ACK_LSB) +#define MAC_PCU_DIAG_SW_NO_ACK_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_ACK_LSB) & MAC_PCU_DIAG_SW_NO_ACK_MASK) +#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MSB 0 +#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB 0 +#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK 0x00000001 +#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_GET(x) (((x) & MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK) >> MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB) +#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_SET(x) (((x) << MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB) & MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK) + +#define MAC_PCU_TST_ADDAC_ADDRESS 0x00008034 +#define MAC_PCU_TST_ADDAC_OFFSET 0x00000034 +#define MAC_PCU_TST_ADDAC_TEST_ARM_MSB 20 +#define MAC_PCU_TST_ADDAC_TEST_ARM_LSB 20 +#define MAC_PCU_TST_ADDAC_TEST_ARM_MASK 0x00100000 +#define MAC_PCU_TST_ADDAC_TEST_ARM_GET(x) (((x) & MAC_PCU_TST_ADDAC_TEST_ARM_MASK) >> MAC_PCU_TST_ADDAC_TEST_ARM_LSB) +#define MAC_PCU_TST_ADDAC_TEST_ARM_SET(x) (((x) << MAC_PCU_TST_ADDAC_TEST_ARM_LSB) & MAC_PCU_TST_ADDAC_TEST_ARM_MASK) +#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_MSB 19 +#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB 19 +#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK 0x00080000 +#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_GET(x) (((x) & MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK) >> MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB) +#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_SET(x) (((x) << MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB) & MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK) +#define MAC_PCU_TST_ADDAC_CONT_TEST_MSB 18 +#define MAC_PCU_TST_ADDAC_CONT_TEST_LSB 18 +#define MAC_PCU_TST_ADDAC_CONT_TEST_MASK 0x00040000 +#define MAC_PCU_TST_ADDAC_CONT_TEST_GET(x) (((x) & MAC_PCU_TST_ADDAC_CONT_TEST_MASK) >> MAC_PCU_TST_ADDAC_CONT_TEST_LSB) +#define MAC_PCU_TST_ADDAC_CONT_TEST_SET(x) (((x) << MAC_PCU_TST_ADDAC_CONT_TEST_LSB) & MAC_PCU_TST_ADDAC_CONT_TEST_MASK) +#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_MSB 17 +#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB 17 +#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK 0x00020000 +#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_GET(x) (((x) & MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK) >> MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB) +#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_SET(x) (((x) << MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB) & MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK) +#define MAC_PCU_TST_ADDAC_TRIG_SEL_MSB 16 +#define MAC_PCU_TST_ADDAC_TRIG_SEL_LSB 16 +#define MAC_PCU_TST_ADDAC_TRIG_SEL_MASK 0x00010000 +#define MAC_PCU_TST_ADDAC_TRIG_SEL_GET(x) (((x) & MAC_PCU_TST_ADDAC_TRIG_SEL_MASK) >> MAC_PCU_TST_ADDAC_TRIG_SEL_LSB) +#define MAC_PCU_TST_ADDAC_TRIG_SEL_SET(x) (((x) << MAC_PCU_TST_ADDAC_TRIG_SEL_LSB) & MAC_PCU_TST_ADDAC_TRIG_SEL_MASK) +#define MAC_PCU_TST_ADDAC_UPPER_8B_MSB 14 +#define MAC_PCU_TST_ADDAC_UPPER_8B_LSB 14 +#define MAC_PCU_TST_ADDAC_UPPER_8B_MASK 0x00004000 +#define MAC_PCU_TST_ADDAC_UPPER_8B_GET(x) (((x) & MAC_PCU_TST_ADDAC_UPPER_8B_MASK) >> MAC_PCU_TST_ADDAC_UPPER_8B_LSB) +#define MAC_PCU_TST_ADDAC_UPPER_8B_SET(x) (((x) << MAC_PCU_TST_ADDAC_UPPER_8B_LSB) & MAC_PCU_TST_ADDAC_UPPER_8B_MASK) +#define MAC_PCU_TST_ADDAC_LOOP_LEN_MSB 13 +#define MAC_PCU_TST_ADDAC_LOOP_LEN_LSB 3 +#define MAC_PCU_TST_ADDAC_LOOP_LEN_MASK 0x00003ff8 +#define MAC_PCU_TST_ADDAC_LOOP_LEN_GET(x) (((x) & MAC_PCU_TST_ADDAC_LOOP_LEN_MASK) >> MAC_PCU_TST_ADDAC_LOOP_LEN_LSB) +#define MAC_PCU_TST_ADDAC_LOOP_LEN_SET(x) (((x) << MAC_PCU_TST_ADDAC_LOOP_LEN_LSB) & MAC_PCU_TST_ADDAC_LOOP_LEN_MASK) +#define MAC_PCU_TST_ADDAC_LOOP_MSB 2 +#define MAC_PCU_TST_ADDAC_LOOP_LSB 2 +#define MAC_PCU_TST_ADDAC_LOOP_MASK 0x00000004 +#define MAC_PCU_TST_ADDAC_LOOP_GET(x) (((x) & MAC_PCU_TST_ADDAC_LOOP_MASK) >> MAC_PCU_TST_ADDAC_LOOP_LSB) +#define MAC_PCU_TST_ADDAC_LOOP_SET(x) (((x) << MAC_PCU_TST_ADDAC_LOOP_LSB) & MAC_PCU_TST_ADDAC_LOOP_MASK) +#define MAC_PCU_TST_ADDAC_TESTMODE_MSB 1 +#define MAC_PCU_TST_ADDAC_TESTMODE_LSB 1 +#define MAC_PCU_TST_ADDAC_TESTMODE_MASK 0x00000002 +#define MAC_PCU_TST_ADDAC_TESTMODE_GET(x) (((x) & MAC_PCU_TST_ADDAC_TESTMODE_MASK) >> MAC_PCU_TST_ADDAC_TESTMODE_LSB) +#define MAC_PCU_TST_ADDAC_TESTMODE_SET(x) (((x) << MAC_PCU_TST_ADDAC_TESTMODE_LSB) & MAC_PCU_TST_ADDAC_TESTMODE_MASK) +#define MAC_PCU_TST_ADDAC_CONT_TX_MSB 0 +#define MAC_PCU_TST_ADDAC_CONT_TX_LSB 0 +#define MAC_PCU_TST_ADDAC_CONT_TX_MASK 0x00000001 +#define MAC_PCU_TST_ADDAC_CONT_TX_GET(x) (((x) & MAC_PCU_TST_ADDAC_CONT_TX_MASK) >> MAC_PCU_TST_ADDAC_CONT_TX_LSB) +#define MAC_PCU_TST_ADDAC_CONT_TX_SET(x) (((x) << MAC_PCU_TST_ADDAC_CONT_TX_LSB) & MAC_PCU_TST_ADDAC_CONT_TX_MASK) + +#define MAC_PCU_DEF_ANTENNA_ADDRESS 0x00008038 +#define MAC_PCU_DEF_ANTENNA_OFFSET 0x00000038 +#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MSB 28 +#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB 28 +#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK 0x10000000 +#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK) >> MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB) +#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB) & MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK) +#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MSB 24 +#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB 24 +#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK 0x01000000 +#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK) >> MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB) +#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB) & MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK) +#define MAC_PCU_DEF_ANTENNA_VALUE_MSB 23 +#define MAC_PCU_DEF_ANTENNA_VALUE_LSB 0 +#define MAC_PCU_DEF_ANTENNA_VALUE_MASK 0x00ffffff +#define MAC_PCU_DEF_ANTENNA_VALUE_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_VALUE_MASK) >> MAC_PCU_DEF_ANTENNA_VALUE_LSB) +#define MAC_PCU_DEF_ANTENNA_VALUE_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_VALUE_LSB) & MAC_PCU_DEF_ANTENNA_VALUE_MASK) + +#define MAC_PCU_AES_MUTE_MASK_0_ADDRESS 0x0000803c +#define MAC_PCU_AES_MUTE_MASK_0_OFFSET 0x0000003c +#define MAC_PCU_AES_MUTE_MASK_0_QOS_MSB 31 +#define MAC_PCU_AES_MUTE_MASK_0_QOS_LSB 16 +#define MAC_PCU_AES_MUTE_MASK_0_QOS_MASK 0xffff0000 +#define MAC_PCU_AES_MUTE_MASK_0_QOS_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_0_QOS_MASK) >> MAC_PCU_AES_MUTE_MASK_0_QOS_LSB) +#define MAC_PCU_AES_MUTE_MASK_0_QOS_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_0_QOS_LSB) & MAC_PCU_AES_MUTE_MASK_0_QOS_MASK) +#define MAC_PCU_AES_MUTE_MASK_0_FC_MSB 15 +#define MAC_PCU_AES_MUTE_MASK_0_FC_LSB 0 +#define MAC_PCU_AES_MUTE_MASK_0_FC_MASK 0x0000ffff +#define MAC_PCU_AES_MUTE_MASK_0_FC_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_0_FC_MASK) >> MAC_PCU_AES_MUTE_MASK_0_FC_LSB) +#define MAC_PCU_AES_MUTE_MASK_0_FC_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_0_FC_LSB) & MAC_PCU_AES_MUTE_MASK_0_FC_MASK) + +#define MAC_PCU_AES_MUTE_MASK_1_ADDRESS 0x00008040 +#define MAC_PCU_AES_MUTE_MASK_1_OFFSET 0x00000040 +#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MSB 31 +#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB 16 +#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK 0xffff0000 +#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK) >> MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB) +#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB) & MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK) +#define MAC_PCU_AES_MUTE_MASK_1_SEQ_MSB 15 +#define MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB 0 +#define MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK 0x0000ffff +#define MAC_PCU_AES_MUTE_MASK_1_SEQ_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK) >> MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB) +#define MAC_PCU_AES_MUTE_MASK_1_SEQ_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB) & MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK) + +#define MAC_PCU_GATED_CLKS_ADDRESS 0x00008044 +#define MAC_PCU_GATED_CLKS_OFFSET 0x00000044 +#define MAC_PCU_GATED_CLKS_GATED_REG_MSB 3 +#define MAC_PCU_GATED_CLKS_GATED_REG_LSB 3 +#define MAC_PCU_GATED_CLKS_GATED_REG_MASK 0x00000008 +#define MAC_PCU_GATED_CLKS_GATED_REG_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATED_REG_MASK) >> MAC_PCU_GATED_CLKS_GATED_REG_LSB) +#define MAC_PCU_GATED_CLKS_GATED_REG_SET(x) (((x) << MAC_PCU_GATED_CLKS_GATED_REG_LSB) & MAC_PCU_GATED_CLKS_GATED_REG_MASK) +#define MAC_PCU_GATED_CLKS_GATED_RX_MSB 2 +#define MAC_PCU_GATED_CLKS_GATED_RX_LSB 2 +#define MAC_PCU_GATED_CLKS_GATED_RX_MASK 0x00000004 +#define MAC_PCU_GATED_CLKS_GATED_RX_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATED_RX_MASK) >> MAC_PCU_GATED_CLKS_GATED_RX_LSB) +#define MAC_PCU_GATED_CLKS_GATED_RX_SET(x) (((x) << MAC_PCU_GATED_CLKS_GATED_RX_LSB) & MAC_PCU_GATED_CLKS_GATED_RX_MASK) +#define MAC_PCU_GATED_CLKS_GATED_TX_MSB 1 +#define MAC_PCU_GATED_CLKS_GATED_TX_LSB 1 +#define MAC_PCU_GATED_CLKS_GATED_TX_MASK 0x00000002 +#define MAC_PCU_GATED_CLKS_GATED_TX_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATED_TX_MASK) >> MAC_PCU_GATED_CLKS_GATED_TX_LSB) +#define MAC_PCU_GATED_CLKS_GATED_TX_SET(x) (((x) << MAC_PCU_GATED_CLKS_GATED_TX_LSB) & MAC_PCU_GATED_CLKS_GATED_TX_MASK) + +#define MAC_PCU_OBS_BUS_2_ADDRESS 0x00008048 +#define MAC_PCU_OBS_BUS_2_OFFSET 0x00000048 +#define MAC_PCU_OBS_BUS_2_VALUE_MSB 17 +#define MAC_PCU_OBS_BUS_2_VALUE_LSB 0 +#define MAC_PCU_OBS_BUS_2_VALUE_MASK 0x0003ffff +#define MAC_PCU_OBS_BUS_2_VALUE_GET(x) (((x) & MAC_PCU_OBS_BUS_2_VALUE_MASK) >> MAC_PCU_OBS_BUS_2_VALUE_LSB) +#define MAC_PCU_OBS_BUS_2_VALUE_SET(x) (((x) << MAC_PCU_OBS_BUS_2_VALUE_LSB) & MAC_PCU_OBS_BUS_2_VALUE_MASK) + +#define MAC_PCU_OBS_BUS_1_ADDRESS 0x0000804c +#define MAC_PCU_OBS_BUS_1_OFFSET 0x0000004c +#define MAC_PCU_OBS_BUS_1_TX_STATE_MSB 30 +#define MAC_PCU_OBS_BUS_1_TX_STATE_LSB 25 +#define MAC_PCU_OBS_BUS_1_TX_STATE_MASK 0x7e000000 +#define MAC_PCU_OBS_BUS_1_TX_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_STATE_MASK) >> MAC_PCU_OBS_BUS_1_TX_STATE_LSB) +#define MAC_PCU_OBS_BUS_1_TX_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_STATE_LSB) & MAC_PCU_OBS_BUS_1_TX_STATE_MASK) +#define MAC_PCU_OBS_BUS_1_RX_STATE_MSB 24 +#define MAC_PCU_OBS_BUS_1_RX_STATE_LSB 20 +#define MAC_PCU_OBS_BUS_1_RX_STATE_MASK 0x01f00000 +#define MAC_PCU_OBS_BUS_1_RX_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_STATE_MASK) >> MAC_PCU_OBS_BUS_1_RX_STATE_LSB) +#define MAC_PCU_OBS_BUS_1_RX_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_STATE_LSB) & MAC_PCU_OBS_BUS_1_RX_STATE_MASK) +#define MAC_PCU_OBS_BUS_1_WEP_STATE_MSB 17 +#define MAC_PCU_OBS_BUS_1_WEP_STATE_LSB 12 +#define MAC_PCU_OBS_BUS_1_WEP_STATE_MASK 0x0003f000 +#define MAC_PCU_OBS_BUS_1_WEP_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_WEP_STATE_MASK) >> MAC_PCU_OBS_BUS_1_WEP_STATE_LSB) +#define MAC_PCU_OBS_BUS_1_WEP_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_WEP_STATE_LSB) & MAC_PCU_OBS_BUS_1_WEP_STATE_MASK) +#define MAC_PCU_OBS_BUS_1_RX_CLEAR_MSB 11 +#define MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB 11 +#define MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK 0x00000800 +#define MAC_PCU_OBS_BUS_1_RX_CLEAR_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK) >> MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB) +#define MAC_PCU_OBS_BUS_1_RX_CLEAR_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB) & MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK) +#define MAC_PCU_OBS_BUS_1_RX_FRAME_MSB 10 +#define MAC_PCU_OBS_BUS_1_RX_FRAME_LSB 10 +#define MAC_PCU_OBS_BUS_1_RX_FRAME_MASK 0x00000400 +#define MAC_PCU_OBS_BUS_1_RX_FRAME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_FRAME_MASK) >> MAC_PCU_OBS_BUS_1_RX_FRAME_LSB) +#define MAC_PCU_OBS_BUS_1_RX_FRAME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_FRAME_LSB) & MAC_PCU_OBS_BUS_1_RX_FRAME_MASK) +#define MAC_PCU_OBS_BUS_1_TX_FRAME_MSB 9 +#define MAC_PCU_OBS_BUS_1_TX_FRAME_LSB 9 +#define MAC_PCU_OBS_BUS_1_TX_FRAME_MASK 0x00000200 +#define MAC_PCU_OBS_BUS_1_TX_FRAME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_FRAME_MASK) >> MAC_PCU_OBS_BUS_1_TX_FRAME_LSB) +#define MAC_PCU_OBS_BUS_1_TX_FRAME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_FRAME_LSB) & MAC_PCU_OBS_BUS_1_TX_FRAME_MASK) +#define MAC_PCU_OBS_BUS_1_TX_HOLD_MSB 8 +#define MAC_PCU_OBS_BUS_1_TX_HOLD_LSB 8 +#define MAC_PCU_OBS_BUS_1_TX_HOLD_MASK 0x00000100 +#define MAC_PCU_OBS_BUS_1_TX_HOLD_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_HOLD_MASK) >> MAC_PCU_OBS_BUS_1_TX_HOLD_LSB) +#define MAC_PCU_OBS_BUS_1_TX_HOLD_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_HOLD_LSB) & MAC_PCU_OBS_BUS_1_TX_HOLD_MASK) +#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MSB 7 +#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB 7 +#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK 0x00000080 +#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK) >> MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB) +#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB) & MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK) +#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MSB 6 +#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB 6 +#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK 0x00000040 +#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK) >> MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB) +#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB) & MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK) +#define MAC_PCU_OBS_BUS_1_TX_HCF_MSB 5 +#define MAC_PCU_OBS_BUS_1_TX_HCF_LSB 5 +#define MAC_PCU_OBS_BUS_1_TX_HCF_MASK 0x00000020 +#define MAC_PCU_OBS_BUS_1_TX_HCF_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_HCF_MASK) >> MAC_PCU_OBS_BUS_1_TX_HCF_LSB) +#define MAC_PCU_OBS_BUS_1_TX_HCF_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_HCF_LSB) & MAC_PCU_OBS_BUS_1_TX_HCF_MASK) +#define MAC_PCU_OBS_BUS_1_FILTER_PASS_MSB 4 +#define MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB 4 +#define MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK 0x00000010 +#define MAC_PCU_OBS_BUS_1_FILTER_PASS_GET(x) (((x) & MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK) >> MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB) +#define MAC_PCU_OBS_BUS_1_FILTER_PASS_SET(x) (((x) << MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB) & MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK) +#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MSB 3 +#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB 3 +#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK 0x00000008 +#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK) >> MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB) +#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB) & MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK) +#define MAC_PCU_OBS_BUS_1_RX_WEP_MSB 2 +#define MAC_PCU_OBS_BUS_1_RX_WEP_LSB 2 +#define MAC_PCU_OBS_BUS_1_RX_WEP_MASK 0x00000004 +#define MAC_PCU_OBS_BUS_1_RX_WEP_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_WEP_MASK) >> MAC_PCU_OBS_BUS_1_RX_WEP_LSB) +#define MAC_PCU_OBS_BUS_1_RX_WEP_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_WEP_LSB) & MAC_PCU_OBS_BUS_1_RX_WEP_MASK) +#define MAC_PCU_OBS_BUS_1_PCU_RX_END_MSB 1 +#define MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB 1 +#define MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK 0x00000002 +#define MAC_PCU_OBS_BUS_1_PCU_RX_END_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK) >> MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB) +#define MAC_PCU_OBS_BUS_1_PCU_RX_END_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB) & MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK) +#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MSB 0 +#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB 0 +#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK 0x00000001 +#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK) >> MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB) +#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB) & MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK) + +#define MAC_PCU_DYM_MIMO_PWR_SAVE_ADDRESS 0x00008050 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_OFFSET 0x00000050 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MSB 10 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB 8 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK 0x00000700 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MSB 6 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB 4 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK 0x00000070 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MSB 2 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB 2 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK 0x00000004 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MSB 1 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB 1 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK 0x00000002 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MSB 0 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB 0 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK 0x00000001 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK) + +#define MAC_PCU_LAST_BEACON_TSF_ADDRESS 0x00008054 +#define MAC_PCU_LAST_BEACON_TSF_OFFSET 0x00000054 +#define MAC_PCU_LAST_BEACON_TSF_VALUE_MSB 31 +#define MAC_PCU_LAST_BEACON_TSF_VALUE_LSB 0 +#define MAC_PCU_LAST_BEACON_TSF_VALUE_MASK 0xffffffff +#define MAC_PCU_LAST_BEACON_TSF_VALUE_GET(x) (((x) & MAC_PCU_LAST_BEACON_TSF_VALUE_MASK) >> MAC_PCU_LAST_BEACON_TSF_VALUE_LSB) +#define MAC_PCU_LAST_BEACON_TSF_VALUE_SET(x) (((x) << MAC_PCU_LAST_BEACON_TSF_VALUE_LSB) & MAC_PCU_LAST_BEACON_TSF_VALUE_MASK) + +#define MAC_PCU_NAV_ADDRESS 0x00008058 +#define MAC_PCU_NAV_OFFSET 0x00000058 +#define MAC_PCU_NAV_VALUE_MSB 25 +#define MAC_PCU_NAV_VALUE_LSB 0 +#define MAC_PCU_NAV_VALUE_MASK 0x03ffffff +#define MAC_PCU_NAV_VALUE_GET(x) (((x) & MAC_PCU_NAV_VALUE_MASK) >> MAC_PCU_NAV_VALUE_LSB) +#define MAC_PCU_NAV_VALUE_SET(x) (((x) << MAC_PCU_NAV_VALUE_LSB) & MAC_PCU_NAV_VALUE_MASK) + +#define MAC_PCU_RTS_SUCCESS_CNT_ADDRESS 0x0000805c +#define MAC_PCU_RTS_SUCCESS_CNT_OFFSET 0x0000005c +#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_MSB 15 +#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB 0 +#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK 0x0000ffff +#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_GET(x) (((x) & MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK) >> MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB) +#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_SET(x) (((x) << MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB) & MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK) + +#define MAC_PCU_RTS_FAIL_CNT_ADDRESS 0x00008060 +#define MAC_PCU_RTS_FAIL_CNT_OFFSET 0x00000060 +#define MAC_PCU_RTS_FAIL_CNT_VALUE_MSB 15 +#define MAC_PCU_RTS_FAIL_CNT_VALUE_LSB 0 +#define MAC_PCU_RTS_FAIL_CNT_VALUE_MASK 0x0000ffff +#define MAC_PCU_RTS_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_RTS_FAIL_CNT_VALUE_MASK) >> MAC_PCU_RTS_FAIL_CNT_VALUE_LSB) +#define MAC_PCU_RTS_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_RTS_FAIL_CNT_VALUE_LSB) & MAC_PCU_RTS_FAIL_CNT_VALUE_MASK) + +#define MAC_PCU_ACK_FAIL_CNT_ADDRESS 0x00008064 +#define MAC_PCU_ACK_FAIL_CNT_OFFSET 0x00000064 +#define MAC_PCU_ACK_FAIL_CNT_VALUE_MSB 15 +#define MAC_PCU_ACK_FAIL_CNT_VALUE_LSB 0 +#define MAC_PCU_ACK_FAIL_CNT_VALUE_MASK 0x0000ffff +#define MAC_PCU_ACK_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_ACK_FAIL_CNT_VALUE_MASK) >> MAC_PCU_ACK_FAIL_CNT_VALUE_LSB) +#define MAC_PCU_ACK_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_ACK_FAIL_CNT_VALUE_LSB) & MAC_PCU_ACK_FAIL_CNT_VALUE_MASK) + +#define MAC_PCU_FCS_FAIL_CNT_ADDRESS 0x00008068 +#define MAC_PCU_FCS_FAIL_CNT_OFFSET 0x00000068 +#define MAC_PCU_FCS_FAIL_CNT_VALUE_MSB 15 +#define MAC_PCU_FCS_FAIL_CNT_VALUE_LSB 0 +#define MAC_PCU_FCS_FAIL_CNT_VALUE_MASK 0x0000ffff +#define MAC_PCU_FCS_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_FCS_FAIL_CNT_VALUE_MASK) >> MAC_PCU_FCS_FAIL_CNT_VALUE_LSB) +#define MAC_PCU_FCS_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_FCS_FAIL_CNT_VALUE_LSB) & MAC_PCU_FCS_FAIL_CNT_VALUE_MASK) + +#define MAC_PCU_BEACON_CNT_ADDRESS 0x0000806c +#define MAC_PCU_BEACON_CNT_OFFSET 0x0000006c +#define MAC_PCU_BEACON_CNT_VALUE_MSB 15 +#define MAC_PCU_BEACON_CNT_VALUE_LSB 0 +#define MAC_PCU_BEACON_CNT_VALUE_MASK 0x0000ffff +#define MAC_PCU_BEACON_CNT_VALUE_GET(x) (((x) & MAC_PCU_BEACON_CNT_VALUE_MASK) >> MAC_PCU_BEACON_CNT_VALUE_LSB) +#define MAC_PCU_BEACON_CNT_VALUE_SET(x) (((x) << MAC_PCU_BEACON_CNT_VALUE_LSB) & MAC_PCU_BEACON_CNT_VALUE_MASK) + +#define MAC_PCU_XRMODE_ADDRESS 0x00008070 +#define MAC_PCU_XRMODE_OFFSET 0x00000070 +#define MAC_PCU_XRMODE_FRAME_HOLD_MSB 31 +#define MAC_PCU_XRMODE_FRAME_HOLD_LSB 20 +#define MAC_PCU_XRMODE_FRAME_HOLD_MASK 0xfff00000 +#define MAC_PCU_XRMODE_FRAME_HOLD_GET(x) (((x) & MAC_PCU_XRMODE_FRAME_HOLD_MASK) >> MAC_PCU_XRMODE_FRAME_HOLD_LSB) +#define MAC_PCU_XRMODE_FRAME_HOLD_SET(x) (((x) << MAC_PCU_XRMODE_FRAME_HOLD_LSB) & MAC_PCU_XRMODE_FRAME_HOLD_MASK) +#define MAC_PCU_XRMODE_WAIT_FOR_POLL_MSB 7 +#define MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB 7 +#define MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK 0x00000080 +#define MAC_PCU_XRMODE_WAIT_FOR_POLL_GET(x) (((x) & MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK) >> MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB) +#define MAC_PCU_XRMODE_WAIT_FOR_POLL_SET(x) (((x) << MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB) & MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK) +#define MAC_PCU_XRMODE_POLL_TYPE_MSB 5 +#define MAC_PCU_XRMODE_POLL_TYPE_LSB 0 +#define MAC_PCU_XRMODE_POLL_TYPE_MASK 0x0000003f +#define MAC_PCU_XRMODE_POLL_TYPE_GET(x) (((x) & MAC_PCU_XRMODE_POLL_TYPE_MASK) >> MAC_PCU_XRMODE_POLL_TYPE_LSB) +#define MAC_PCU_XRMODE_POLL_TYPE_SET(x) (((x) << MAC_PCU_XRMODE_POLL_TYPE_LSB) & MAC_PCU_XRMODE_POLL_TYPE_MASK) + +#define MAC_PCU_XRDEL_ADDRESS 0x00008074 +#define MAC_PCU_XRDEL_OFFSET 0x00000074 +#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MSB 31 +#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB 16 +#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK 0xffff0000 +#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_GET(x) (((x) & MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK) >> MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB) +#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_SET(x) (((x) << MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB) & MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK) +#define MAC_PCU_XRDEL_SLOT_DELAY_MSB 15 +#define MAC_PCU_XRDEL_SLOT_DELAY_LSB 0 +#define MAC_PCU_XRDEL_SLOT_DELAY_MASK 0x0000ffff +#define MAC_PCU_XRDEL_SLOT_DELAY_GET(x) (((x) & MAC_PCU_XRDEL_SLOT_DELAY_MASK) >> MAC_PCU_XRDEL_SLOT_DELAY_LSB) +#define MAC_PCU_XRDEL_SLOT_DELAY_SET(x) (((x) << MAC_PCU_XRDEL_SLOT_DELAY_LSB) & MAC_PCU_XRDEL_SLOT_DELAY_MASK) + +#define MAC_PCU_XRTO_ADDRESS 0x00008078 +#define MAC_PCU_XRTO_OFFSET 0x00000078 +#define MAC_PCU_XRTO_POLL_TIMEOUT_MSB 31 +#define MAC_PCU_XRTO_POLL_TIMEOUT_LSB 16 +#define MAC_PCU_XRTO_POLL_TIMEOUT_MASK 0xffff0000 +#define MAC_PCU_XRTO_POLL_TIMEOUT_GET(x) (((x) & MAC_PCU_XRTO_POLL_TIMEOUT_MASK) >> MAC_PCU_XRTO_POLL_TIMEOUT_LSB) +#define MAC_PCU_XRTO_POLL_TIMEOUT_SET(x) (((x) << MAC_PCU_XRTO_POLL_TIMEOUT_LSB) & MAC_PCU_XRTO_POLL_TIMEOUT_MASK) +#define MAC_PCU_XRTO_CHIRP_TIMEOUT_MSB 15 +#define MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB 0 +#define MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK 0x0000ffff +#define MAC_PCU_XRTO_CHIRP_TIMEOUT_GET(x) (((x) & MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK) >> MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB) +#define MAC_PCU_XRTO_CHIRP_TIMEOUT_SET(x) (((x) << MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB) & MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK) + +#define MAC_PCU_XRCRP_ADDRESS 0x0000807c +#define MAC_PCU_XRCRP_OFFSET 0x0000007c +#define MAC_PCU_XRCRP_CHIRP_GAP_MSB 31 +#define MAC_PCU_XRCRP_CHIRP_GAP_LSB 16 +#define MAC_PCU_XRCRP_CHIRP_GAP_MASK 0xffff0000 +#define MAC_PCU_XRCRP_CHIRP_GAP_GET(x) (((x) & MAC_PCU_XRCRP_CHIRP_GAP_MASK) >> MAC_PCU_XRCRP_CHIRP_GAP_LSB) +#define MAC_PCU_XRCRP_CHIRP_GAP_SET(x) (((x) << MAC_PCU_XRCRP_CHIRP_GAP_LSB) & MAC_PCU_XRCRP_CHIRP_GAP_MASK) +#define MAC_PCU_XRCRP_SEND_CHIRP_MSB 0 +#define MAC_PCU_XRCRP_SEND_CHIRP_LSB 0 +#define MAC_PCU_XRCRP_SEND_CHIRP_MASK 0x00000001 +#define MAC_PCU_XRCRP_SEND_CHIRP_GET(x) (((x) & MAC_PCU_XRCRP_SEND_CHIRP_MASK) >> MAC_PCU_XRCRP_SEND_CHIRP_LSB) +#define MAC_PCU_XRCRP_SEND_CHIRP_SET(x) (((x) << MAC_PCU_XRCRP_SEND_CHIRP_LSB) & MAC_PCU_XRCRP_SEND_CHIRP_MASK) + +#define MAC_PCU_XRSTMP_ADDRESS 0x00008080 +#define MAC_PCU_XRSTMP_OFFSET 0x00000080 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MSB 23 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB 16 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK 0x00ff0000 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB) +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK) +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MSB 15 +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB 8 +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK 0x0000ff00 +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB) +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK) +#define MAC_PCU_XRSTMP_RX_ABORT_DATA_MSB 5 +#define MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB 5 +#define MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK 0x00000020 +#define MAC_PCU_XRSTMP_RX_ABORT_DATA_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB) +#define MAC_PCU_XRSTMP_RX_ABORT_DATA_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB) & MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK) +#define MAC_PCU_XRSTMP_TX_STOMP_DATA_MSB 4 +#define MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB 4 +#define MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK 0x00000010 +#define MAC_PCU_XRSTMP_TX_STOMP_DATA_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB) +#define MAC_PCU_XRSTMP_TX_STOMP_DATA_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB) & MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK) +#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_MSB 3 +#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB 3 +#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK 0x00000008 +#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB) +#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB) & MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK) +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_MSB 2 +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB 2 +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK 0x00000004 +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB) +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK) +#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_MSB 1 +#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB 1 +#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK 0x00000002 +#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB) +#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB) & MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK) +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_MSB 0 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB 0 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK 0x00000001 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB) +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK) + +#define MAC_PCU_ADDR1_MASK_L32_ADDRESS 0x00008084 +#define MAC_PCU_ADDR1_MASK_L32_OFFSET 0x00000084 +#define MAC_PCU_ADDR1_MASK_L32_VALUE_MSB 31 +#define MAC_PCU_ADDR1_MASK_L32_VALUE_LSB 0 +#define MAC_PCU_ADDR1_MASK_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_ADDR1_MASK_L32_VALUE_GET(x) (((x) & MAC_PCU_ADDR1_MASK_L32_VALUE_MASK) >> MAC_PCU_ADDR1_MASK_L32_VALUE_LSB) +#define MAC_PCU_ADDR1_MASK_L32_VALUE_SET(x) (((x) << MAC_PCU_ADDR1_MASK_L32_VALUE_LSB) & MAC_PCU_ADDR1_MASK_L32_VALUE_MASK) + +#define MAC_PCU_ADDR1_MASK_U16_ADDRESS 0x00008088 +#define MAC_PCU_ADDR1_MASK_U16_OFFSET 0x00000088 +#define MAC_PCU_ADDR1_MASK_U16_VALUE_MSB 15 +#define MAC_PCU_ADDR1_MASK_U16_VALUE_LSB 0 +#define MAC_PCU_ADDR1_MASK_U16_VALUE_MASK 0x0000ffff +#define MAC_PCU_ADDR1_MASK_U16_VALUE_GET(x) (((x) & MAC_PCU_ADDR1_MASK_U16_VALUE_MASK) >> MAC_PCU_ADDR1_MASK_U16_VALUE_LSB) +#define MAC_PCU_ADDR1_MASK_U16_VALUE_SET(x) (((x) << MAC_PCU_ADDR1_MASK_U16_VALUE_LSB) & MAC_PCU_ADDR1_MASK_U16_VALUE_MASK) + +#define MAC_PCU_TPC_ADDRESS 0x0000808c +#define MAC_PCU_TPC_OFFSET 0x0000008c +#define MAC_PCU_TPC_CHIRP_PWR_MSB 21 +#define MAC_PCU_TPC_CHIRP_PWR_LSB 16 +#define MAC_PCU_TPC_CHIRP_PWR_MASK 0x003f0000 +#define MAC_PCU_TPC_CHIRP_PWR_GET(x) (((x) & MAC_PCU_TPC_CHIRP_PWR_MASK) >> MAC_PCU_TPC_CHIRP_PWR_LSB) +#define MAC_PCU_TPC_CHIRP_PWR_SET(x) (((x) << MAC_PCU_TPC_CHIRP_PWR_LSB) & MAC_PCU_TPC_CHIRP_PWR_MASK) +#define MAC_PCU_TPC_CTS_PWR_MSB 13 +#define MAC_PCU_TPC_CTS_PWR_LSB 8 +#define MAC_PCU_TPC_CTS_PWR_MASK 0x00003f00 +#define MAC_PCU_TPC_CTS_PWR_GET(x) (((x) & MAC_PCU_TPC_CTS_PWR_MASK) >> MAC_PCU_TPC_CTS_PWR_LSB) +#define MAC_PCU_TPC_CTS_PWR_SET(x) (((x) << MAC_PCU_TPC_CTS_PWR_LSB) & MAC_PCU_TPC_CTS_PWR_MASK) +#define MAC_PCU_TPC_ACK_PWR_MSB 5 +#define MAC_PCU_TPC_ACK_PWR_LSB 0 +#define MAC_PCU_TPC_ACK_PWR_MASK 0x0000003f +#define MAC_PCU_TPC_ACK_PWR_GET(x) (((x) & MAC_PCU_TPC_ACK_PWR_MASK) >> MAC_PCU_TPC_ACK_PWR_LSB) +#define MAC_PCU_TPC_ACK_PWR_SET(x) (((x) << MAC_PCU_TPC_ACK_PWR_LSB) & MAC_PCU_TPC_ACK_PWR_MASK) + +#define MAC_PCU_TX_FRAME_CNT_ADDRESS 0x00008090 +#define MAC_PCU_TX_FRAME_CNT_OFFSET 0x00000090 +#define MAC_PCU_TX_FRAME_CNT_VALUE_MSB 31 +#define MAC_PCU_TX_FRAME_CNT_VALUE_LSB 0 +#define MAC_PCU_TX_FRAME_CNT_VALUE_MASK 0xffffffff +#define MAC_PCU_TX_FRAME_CNT_VALUE_GET(x) (((x) & MAC_PCU_TX_FRAME_CNT_VALUE_MASK) >> MAC_PCU_TX_FRAME_CNT_VALUE_LSB) +#define MAC_PCU_TX_FRAME_CNT_VALUE_SET(x) (((x) << MAC_PCU_TX_FRAME_CNT_VALUE_LSB) & MAC_PCU_TX_FRAME_CNT_VALUE_MASK) + +#define MAC_PCU_RX_FRAME_CNT_ADDRESS 0x00008094 +#define MAC_PCU_RX_FRAME_CNT_OFFSET 0x00000094 +#define MAC_PCU_RX_FRAME_CNT_VALUE_MSB 31 +#define MAC_PCU_RX_FRAME_CNT_VALUE_LSB 0 +#define MAC_PCU_RX_FRAME_CNT_VALUE_MASK 0xffffffff +#define MAC_PCU_RX_FRAME_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_FRAME_CNT_VALUE_MASK) >> MAC_PCU_RX_FRAME_CNT_VALUE_LSB) +#define MAC_PCU_RX_FRAME_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_FRAME_CNT_VALUE_LSB) & MAC_PCU_RX_FRAME_CNT_VALUE_MASK) + +#define MAC_PCU_RX_CLEAR_CNT_ADDRESS 0x00008098 +#define MAC_PCU_RX_CLEAR_CNT_OFFSET 0x00000098 +#define MAC_PCU_RX_CLEAR_CNT_VALUE_MSB 31 +#define MAC_PCU_RX_CLEAR_CNT_VALUE_LSB 0 +#define MAC_PCU_RX_CLEAR_CNT_VALUE_MASK 0xffffffff +#define MAC_PCU_RX_CLEAR_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_CLEAR_CNT_VALUE_MASK) >> MAC_PCU_RX_CLEAR_CNT_VALUE_LSB) +#define MAC_PCU_RX_CLEAR_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_CLEAR_CNT_VALUE_LSB) & MAC_PCU_RX_CLEAR_CNT_VALUE_MASK) + +#define MAC_PCU_CYCLE_CNT_ADDRESS 0x0000809c +#define MAC_PCU_CYCLE_CNT_OFFSET 0x0000009c +#define MAC_PCU_CYCLE_CNT_VALUE_MSB 31 +#define MAC_PCU_CYCLE_CNT_VALUE_LSB 0 +#define MAC_PCU_CYCLE_CNT_VALUE_MASK 0xffffffff +#define MAC_PCU_CYCLE_CNT_VALUE_GET(x) (((x) & MAC_PCU_CYCLE_CNT_VALUE_MASK) >> MAC_PCU_CYCLE_CNT_VALUE_LSB) +#define MAC_PCU_CYCLE_CNT_VALUE_SET(x) (((x) << MAC_PCU_CYCLE_CNT_VALUE_LSB) & MAC_PCU_CYCLE_CNT_VALUE_MASK) + +#define MAC_PCU_QUIET_TIME_1_ADDRESS 0x000080a0 +#define MAC_PCU_QUIET_TIME_1_OFFSET 0x000000a0 +#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MSB 17 +#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB 17 +#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK 0x00020000 +#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_GET(x) (((x) & MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK) >> MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB) +#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_SET(x) (((x) << MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB) & MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK) + +#define MAC_PCU_QUIET_TIME_2_ADDRESS 0x000080a4 +#define MAC_PCU_QUIET_TIME_2_OFFSET 0x000000a4 +#define MAC_PCU_QUIET_TIME_2_DURATION_MSB 31 +#define MAC_PCU_QUIET_TIME_2_DURATION_LSB 16 +#define MAC_PCU_QUIET_TIME_2_DURATION_MASK 0xffff0000 +#define MAC_PCU_QUIET_TIME_2_DURATION_GET(x) (((x) & MAC_PCU_QUIET_TIME_2_DURATION_MASK) >> MAC_PCU_QUIET_TIME_2_DURATION_LSB) +#define MAC_PCU_QUIET_TIME_2_DURATION_SET(x) (((x) << MAC_PCU_QUIET_TIME_2_DURATION_LSB) & MAC_PCU_QUIET_TIME_2_DURATION_MASK) + +#define MAC_PCU_QOS_NO_ACK_ADDRESS 0x000080a8 +#define MAC_PCU_QOS_NO_ACK_OFFSET 0x000000a8 +#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MSB 8 +#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB 7 +#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK 0x00000180 +#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK) >> MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB) +#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB) & MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK) +#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MSB 6 +#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB 4 +#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK 0x00000070 +#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK) >> MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB) +#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB) & MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK) +#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MSB 3 +#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB 0 +#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK 0x0000000f +#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK) >> MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB) +#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB) & MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK) + +#define MAC_PCU_PHY_ERROR_MASK_ADDRESS 0x000080ac +#define MAC_PCU_PHY_ERROR_MASK_OFFSET 0x000000ac +#define MAC_PCU_PHY_ERROR_MASK_VALUE_MSB 31 +#define MAC_PCU_PHY_ERROR_MASK_VALUE_LSB 0 +#define MAC_PCU_PHY_ERROR_MASK_VALUE_MASK 0xffffffff +#define MAC_PCU_PHY_ERROR_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_VALUE_LSB) +#define MAC_PCU_PHY_ERROR_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_VALUE_MASK) + +#define MAC_PCU_XRLAT_ADDRESS 0x000080b0 +#define MAC_PCU_XRLAT_OFFSET 0x000000b0 +#define MAC_PCU_XRLAT_VALUE_MSB 11 +#define MAC_PCU_XRLAT_VALUE_LSB 0 +#define MAC_PCU_XRLAT_VALUE_MASK 0x00000fff +#define MAC_PCU_XRLAT_VALUE_GET(x) (((x) & MAC_PCU_XRLAT_VALUE_MASK) >> MAC_PCU_XRLAT_VALUE_LSB) +#define MAC_PCU_XRLAT_VALUE_SET(x) (((x) << MAC_PCU_XRLAT_VALUE_LSB) & MAC_PCU_XRLAT_VALUE_MASK) + +#define MAC_PCU_RXBUF_ADDRESS 0x000080b4 +#define MAC_PCU_RXBUF_OFFSET 0x000000b4 +#define MAC_PCU_RXBUF_REG_RD_ENABLE_MSB 11 +#define MAC_PCU_RXBUF_REG_RD_ENABLE_LSB 11 +#define MAC_PCU_RXBUF_REG_RD_ENABLE_MASK 0x00000800 +#define MAC_PCU_RXBUF_REG_RD_ENABLE_GET(x) (((x) & MAC_PCU_RXBUF_REG_RD_ENABLE_MASK) >> MAC_PCU_RXBUF_REG_RD_ENABLE_LSB) +#define MAC_PCU_RXBUF_REG_RD_ENABLE_SET(x) (((x) << MAC_PCU_RXBUF_REG_RD_ENABLE_LSB) & MAC_PCU_RXBUF_REG_RD_ENABLE_MASK) +#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MSB 10 +#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB 0 +#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK 0x000007ff +#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_GET(x) (((x) & MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK) >> MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB) +#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_SET(x) (((x) << MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB) & MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK) + +#define MAC_PCU_MIC_QOS_CONTROL_ADDRESS 0x000080b8 +#define MAC_PCU_MIC_QOS_CONTROL_OFFSET 0x000000b8 +#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_MSB 16 +#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB 16 +#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK 0x00010000 +#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK) >> MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB) & MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MSB 15 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB 14 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK 0x0000c000 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MSB 13 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB 12 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK 0x00003000 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MSB 11 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB 10 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK 0x00000c00 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MSB 9 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB 8 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK 0x00000300 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MSB 7 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB 6 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK 0x000000c0 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MSB 5 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB 4 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK 0x00000030 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MSB 3 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB 2 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK 0x0000000c +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MSB 1 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB 0 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK 0x00000003 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK) + +#define MAC_PCU_MIC_QOS_SELECT_ADDRESS 0x000080bc +#define MAC_PCU_MIC_QOS_SELECT_OFFSET 0x000000bc +#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_MSB 31 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB 28 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK 0xf0000000 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_MSB 27 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB 24 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK 0x0f000000 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_MSB 23 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB 20 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK 0x00f00000 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_MSB 19 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB 16 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK 0x000f0000 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_MSB 15 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB 12 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK 0x0000f000 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_MSB 11 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB 8 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK 0x00000f00 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_MSB 7 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB 4 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK 0x000000f0 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_MSB 3 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB 0 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK 0x0000000f +#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK) + +#define MAC_PCU_MISC_MODE_ADDRESS 0x000080c0 +#define MAC_PCU_MISC_MODE_OFFSET 0x000000c0 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_MSB 31 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_LSB 30 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_MASK 0xc0000000 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_LSB) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_MASK) +#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MSB 29 +#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB 29 +#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK 0x20000000 +#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_GET(x) (((x) & MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK) >> MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB) +#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_SET(x) (((x) << MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB) & MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK) +#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MSB 28 +#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB 28 +#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK 0x10000000 +#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_GET(x) (((x) & MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK) >> MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB) +#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_SET(x) (((x) << MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB) & MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK) +#define MAC_PCU_MISC_MODE_SEL_EVM_MSB 27 +#define MAC_PCU_MISC_MODE_SEL_EVM_LSB 27 +#define MAC_PCU_MISC_MODE_SEL_EVM_MASK 0x08000000 +#define MAC_PCU_MISC_MODE_SEL_EVM_GET(x) (((x) & MAC_PCU_MISC_MODE_SEL_EVM_MASK) >> MAC_PCU_MISC_MODE_SEL_EVM_LSB) +#define MAC_PCU_MISC_MODE_SEL_EVM_SET(x) (((x) << MAC_PCU_MISC_MODE_SEL_EVM_LSB) & MAC_PCU_MISC_MODE_SEL_EVM_MASK) +#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MSB 26 +#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB 26 +#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK 0x04000000 +#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK) >> MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB) +#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB) & MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK) +#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MSB 25 +#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB 25 +#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK 0x02000000 +#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK) >> MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB) +#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB) & MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK) +#define MAC_PCU_MISC_MODE_CLEAR_VMF_MSB 24 +#define MAC_PCU_MISC_MODE_CLEAR_VMF_LSB 24 +#define MAC_PCU_MISC_MODE_CLEAR_VMF_MASK 0x01000000 +#define MAC_PCU_MISC_MODE_CLEAR_VMF_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_VMF_MASK) >> MAC_PCU_MISC_MODE_CLEAR_VMF_LSB) +#define MAC_PCU_MISC_MODE_CLEAR_VMF_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_VMF_LSB) & MAC_PCU_MISC_MODE_CLEAR_VMF_MASK) +#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MSB 23 +#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB 23 +#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK 0x00800000 +#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK) >> MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB) +#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB) & MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK) +#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MSB 22 +#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB 22 +#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK 0x00400000 +#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_GET(x) (((x) & MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK) >> MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB) +#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_SET(x) (((x) << MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB) & MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK) +#define MAC_PCU_MISC_MODE_TBTT_PROTECT_MSB 21 +#define MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB 21 +#define MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK 0x00200000 +#define MAC_PCU_MISC_MODE_TBTT_PROTECT_GET(x) (((x) & MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK) >> MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB) +#define MAC_PCU_MISC_MODE_TBTT_PROTECT_SET(x) (((x) << MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB) & MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK) +#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MSB 20 +#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB 20 +#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK 0x00100000 +#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_GET(x) (((x) & MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK) >> MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB) +#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_SET(x) (((x) << MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB) & MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK) +#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MSB 18 +#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB 18 +#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK 0x00040000 +#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_GET(x) (((x) & MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK) >> MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB) +#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_SET(x) (((x) << MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB) & MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK) +#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MSB 14 +#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB 14 +#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK 0x00004000 +#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_GET(x) (((x) & MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK) >> MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB) +#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_SET(x) (((x) << MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB) & MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK) +#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MSB 12 +#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB 12 +#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK 0x00001000 +#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK) >> MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB) +#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB) & MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK) +#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MSB 11 +#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB 11 +#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK 0x00000800 +#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_GET(x) (((x) & MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK) >> MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB) +#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_SET(x) (((x) << MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB) & MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MSB 10 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB 10 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK 0x00000400 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MSB 9 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB 9 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK 0x00000200 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK) +#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MSB 4 +#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB 4 +#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK 0x00000010 +#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK) >> MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB) +#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB) & MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK) +#define MAC_PCU_MISC_MODE_TX_ADD_TSF_MSB 3 +#define MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB 3 +#define MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK 0x00000008 +#define MAC_PCU_MISC_MODE_TX_ADD_TSF_GET(x) (((x) & MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK) >> MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB) +#define MAC_PCU_MISC_MODE_TX_ADD_TSF_SET(x) (((x) << MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB) & MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK) +#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MSB 2 +#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB 2 +#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK 0x00000004 +#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK) >> MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB) +#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB) & MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MSB 1 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB 1 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK 0x00000002 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK) +#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MSB 0 +#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB 0 +#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK 0x00000001 +#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_GET(x) (((x) & MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK) >> MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB) +#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_SET(x) (((x) << MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB) & MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK) + +#define MAC_PCU_FILTER_OFDM_CNT_ADDRESS 0x000080c4 +#define MAC_PCU_FILTER_OFDM_CNT_OFFSET 0x000000c4 +#define MAC_PCU_FILTER_OFDM_CNT_VALUE_MSB 23 +#define MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB 0 +#define MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK 0x00ffffff +#define MAC_PCU_FILTER_OFDM_CNT_VALUE_GET(x) (((x) & MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK) >> MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB) +#define MAC_PCU_FILTER_OFDM_CNT_VALUE_SET(x) (((x) << MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB) & MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK) + +#define MAC_PCU_FILTER_CCK_CNT_ADDRESS 0x000080c8 +#define MAC_PCU_FILTER_CCK_CNT_OFFSET 0x000000c8 +#define MAC_PCU_FILTER_CCK_CNT_VALUE_MSB 23 +#define MAC_PCU_FILTER_CCK_CNT_VALUE_LSB 0 +#define MAC_PCU_FILTER_CCK_CNT_VALUE_MASK 0x00ffffff +#define MAC_PCU_FILTER_CCK_CNT_VALUE_GET(x) (((x) & MAC_PCU_FILTER_CCK_CNT_VALUE_MASK) >> MAC_PCU_FILTER_CCK_CNT_VALUE_LSB) +#define MAC_PCU_FILTER_CCK_CNT_VALUE_SET(x) (((x) << MAC_PCU_FILTER_CCK_CNT_VALUE_LSB) & MAC_PCU_FILTER_CCK_CNT_VALUE_MASK) + +#define MAC_PCU_PHY_ERR_CNT_1_ADDRESS 0x000080cc +#define MAC_PCU_PHY_ERR_CNT_1_OFFSET 0x000000cc +#define MAC_PCU_PHY_ERR_CNT_1_VALUE_MSB 23 +#define MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK 0x00ffffff +#define MAC_PCU_PHY_ERR_CNT_1_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB) +#define MAC_PCU_PHY_ERR_CNT_1_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK) + +#define MAC_PCU_PHY_ERR_CNT_1_MASK_ADDRESS 0x000080d0 +#define MAC_PCU_PHY_ERR_CNT_1_MASK_OFFSET 0x000000d0 +#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MSB 31 +#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK 0xffffffff +#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB) +#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK) + +#define MAC_PCU_PHY_ERR_CNT_2_ADDRESS 0x000080d4 +#define MAC_PCU_PHY_ERR_CNT_2_OFFSET 0x000000d4 +#define MAC_PCU_PHY_ERR_CNT_2_VALUE_MSB 23 +#define MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK 0x00ffffff +#define MAC_PCU_PHY_ERR_CNT_2_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB) +#define MAC_PCU_PHY_ERR_CNT_2_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK) + +#define MAC_PCU_PHY_ERR_CNT_2_MASK_ADDRESS 0x000080d8 +#define MAC_PCU_PHY_ERR_CNT_2_MASK_OFFSET 0x000000d8 +#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MSB 31 +#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK 0xffffffff +#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB) +#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK) + +#define MAC_PCU_TSF_THRESHOLD_ADDRESS 0x000080dc +#define MAC_PCU_TSF_THRESHOLD_OFFSET 0x000000dc +#define MAC_PCU_TSF_THRESHOLD_VALUE_MSB 15 +#define MAC_PCU_TSF_THRESHOLD_VALUE_LSB 0 +#define MAC_PCU_TSF_THRESHOLD_VALUE_MASK 0x0000ffff +#define MAC_PCU_TSF_THRESHOLD_VALUE_GET(x) (((x) & MAC_PCU_TSF_THRESHOLD_VALUE_MASK) >> MAC_PCU_TSF_THRESHOLD_VALUE_LSB) +#define MAC_PCU_TSF_THRESHOLD_VALUE_SET(x) (((x) << MAC_PCU_TSF_THRESHOLD_VALUE_LSB) & MAC_PCU_TSF_THRESHOLD_VALUE_MASK) + +#define MAC_PCU_PHY_ERROR_EIFS_MASK_ADDRESS 0x000080e0 +#define MAC_PCU_PHY_ERROR_EIFS_MASK_OFFSET 0x000000e0 +#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MSB 31 +#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB 0 +#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK 0xffffffff +#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB) +#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK) + +#define MAC_PCU_PHY_ERR_CNT_3_ADDRESS 0x000080e4 +#define MAC_PCU_PHY_ERR_CNT_3_OFFSET 0x000000e4 +#define MAC_PCU_PHY_ERR_CNT_3_VALUE_MSB 23 +#define MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK 0x00ffffff +#define MAC_PCU_PHY_ERR_CNT_3_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB) +#define MAC_PCU_PHY_ERR_CNT_3_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK) + +#define MAC_PCU_PHY_ERR_CNT_3_MASK_ADDRESS 0x000080e8 +#define MAC_PCU_PHY_ERR_CNT_3_MASK_OFFSET 0x000000e8 +#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MSB 31 +#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK 0xffffffff +#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB) +#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK) + +#define MAC_PCU_BLUETOOTH_MODE_ADDRESS 0x000080ec +#define MAC_PCU_BLUETOOTH_MODE_OFFSET 0x000000ec +#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MSB 31 +#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB 24 +#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK 0xff000000 +#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB) +#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK) +#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MSB 23 +#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB 18 +#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK 0x00fc0000 +#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB) +#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK) +#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MSB 17 +#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB 17 +#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK 0x00020000 +#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK) >> MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB) +#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB) & MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK) +#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MSB 16 +#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB 13 +#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK 0x0001e000 +#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK) >> MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB) +#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB) & MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK) +#define MAC_PCU_BLUETOOTH_MODE_QUIET_MSB 12 +#define MAC_PCU_BLUETOOTH_MODE_QUIET_LSB 12 +#define MAC_PCU_BLUETOOTH_MODE_QUIET_MASK 0x00001000 +#define MAC_PCU_BLUETOOTH_MODE_QUIET_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_QUIET_MASK) >> MAC_PCU_BLUETOOTH_MODE_QUIET_LSB) +#define MAC_PCU_BLUETOOTH_MODE_QUIET_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_QUIET_LSB) & MAC_PCU_BLUETOOTH_MODE_QUIET_MASK) +#define MAC_PCU_BLUETOOTH_MODE_MODE_MSB 11 +#define MAC_PCU_BLUETOOTH_MODE_MODE_LSB 10 +#define MAC_PCU_BLUETOOTH_MODE_MODE_MASK 0x00000c00 +#define MAC_PCU_BLUETOOTH_MODE_MODE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_MODE_MASK) >> MAC_PCU_BLUETOOTH_MODE_MODE_LSB) +#define MAC_PCU_BLUETOOTH_MODE_MODE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_MODE_LSB) & MAC_PCU_BLUETOOTH_MODE_MODE_MASK) +#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MSB 9 +#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB 9 +#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK 0x00000200 +#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB) +#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK) +#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MSB 8 +#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB 8 +#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK 0x00000100 +#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB) +#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK) +#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MSB 7 +#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB 0 +#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK 0x000000ff +#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB) +#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK) + +#define MAC_PCU_BLUETOOTH_WEIGHTS_ADDRESS 0x000080f0 +#define MAC_PCU_BLUETOOTH_WEIGHTS_OFFSET 0x000000f0 +#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MSB 31 +#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB 16 +#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK 0xffff0000 +#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB) +#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK) +#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MSB 15 +#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB 0 +#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK 0x0000ffff +#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB) +#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK) + +#define MAC_PCU_BLUETOOTH_MODE2_ADDRESS 0x000080f4 +#define MAC_PCU_BLUETOOTH_MODE2_OFFSET 0x000000f4 +#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MSB 31 +#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB 31 +#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK 0x80000000 +#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB) & MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MSB 30 +#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB 30 +#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK 0x40000000 +#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB) & MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MSB 29 +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB 28 +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK 0x30000000 +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK) >> MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MSB 27 +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB 26 +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK 0x0c000000 +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK) >> MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MSB 25 +#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB 25 +#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK 0x02000000 +#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MSB 24 +#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB 24 +#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK 0x01000000 +#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB) & MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MSB 23 +#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB 22 +#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK 0x00c00000 +#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB) & MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MSB 21 +#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB 21 +#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK 0x00200000 +#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB) & MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MSB 20 +#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB 20 +#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK 0x00100000 +#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK) >> MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB) & MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MSB 19 +#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB 19 +#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK 0x00080000 +#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK) >> MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB) & MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MSB 17 +#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB 17 +#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK 0x00020000 +#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK) >> MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB) & MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MSB 16 +#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB 16 +#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK 0x00010000 +#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK) >> MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB) & MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MSB 15 +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB 8 +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK 0x0000ff00 +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK) >> MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MSB 7 +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB 0 +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK 0x000000ff +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK) >> MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK) + +#define MAC_PCU_TXSIFS_ADDRESS 0x000080f8 +#define MAC_PCU_TXSIFS_OFFSET 0x000000f8 +#define MAC_PCU_TXSIFS_ACK_SHIFT_MSB 14 +#define MAC_PCU_TXSIFS_ACK_SHIFT_LSB 12 +#define MAC_PCU_TXSIFS_ACK_SHIFT_MASK 0x00007000 +#define MAC_PCU_TXSIFS_ACK_SHIFT_GET(x) (((x) & MAC_PCU_TXSIFS_ACK_SHIFT_MASK) >> MAC_PCU_TXSIFS_ACK_SHIFT_LSB) +#define MAC_PCU_TXSIFS_ACK_SHIFT_SET(x) (((x) << MAC_PCU_TXSIFS_ACK_SHIFT_LSB) & MAC_PCU_TXSIFS_ACK_SHIFT_MASK) +#define MAC_PCU_TXSIFS_TX_LATENCY_MSB 11 +#define MAC_PCU_TXSIFS_TX_LATENCY_LSB 8 +#define MAC_PCU_TXSIFS_TX_LATENCY_MASK 0x00000f00 +#define MAC_PCU_TXSIFS_TX_LATENCY_GET(x) (((x) & MAC_PCU_TXSIFS_TX_LATENCY_MASK) >> MAC_PCU_TXSIFS_TX_LATENCY_LSB) +#define MAC_PCU_TXSIFS_TX_LATENCY_SET(x) (((x) << MAC_PCU_TXSIFS_TX_LATENCY_LSB) & MAC_PCU_TXSIFS_TX_LATENCY_MASK) +#define MAC_PCU_TXSIFS_SIFS_TIME_MSB 7 +#define MAC_PCU_TXSIFS_SIFS_TIME_LSB 0 +#define MAC_PCU_TXSIFS_SIFS_TIME_MASK 0x000000ff +#define MAC_PCU_TXSIFS_SIFS_TIME_GET(x) (((x) & MAC_PCU_TXSIFS_SIFS_TIME_MASK) >> MAC_PCU_TXSIFS_SIFS_TIME_LSB) +#define MAC_PCU_TXSIFS_SIFS_TIME_SET(x) (((x) << MAC_PCU_TXSIFS_SIFS_TIME_LSB) & MAC_PCU_TXSIFS_SIFS_TIME_MASK) + +#define MAC_PCU_TXOP_X_ADDRESS 0x000080fc +#define MAC_PCU_TXOP_X_OFFSET 0x000000fc +#define MAC_PCU_TXOP_X_VALUE_MSB 7 +#define MAC_PCU_TXOP_X_VALUE_LSB 0 +#define MAC_PCU_TXOP_X_VALUE_MASK 0x000000ff +#define MAC_PCU_TXOP_X_VALUE_GET(x) (((x) & MAC_PCU_TXOP_X_VALUE_MASK) >> MAC_PCU_TXOP_X_VALUE_LSB) +#define MAC_PCU_TXOP_X_VALUE_SET(x) (((x) << MAC_PCU_TXOP_X_VALUE_LSB) & MAC_PCU_TXOP_X_VALUE_MASK) + +#define MAC_PCU_TXOP_0_3_ADDRESS 0x00008100 +#define MAC_PCU_TXOP_0_3_OFFSET 0x00000100 +#define MAC_PCU_TXOP_0_3_VALUE_3_MSB 31 +#define MAC_PCU_TXOP_0_3_VALUE_3_LSB 24 +#define MAC_PCU_TXOP_0_3_VALUE_3_MASK 0xff000000 +#define MAC_PCU_TXOP_0_3_VALUE_3_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_3_MASK) >> MAC_PCU_TXOP_0_3_VALUE_3_LSB) +#define MAC_PCU_TXOP_0_3_VALUE_3_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_3_LSB) & MAC_PCU_TXOP_0_3_VALUE_3_MASK) +#define MAC_PCU_TXOP_0_3_VALUE_2_MSB 23 +#define MAC_PCU_TXOP_0_3_VALUE_2_LSB 16 +#define MAC_PCU_TXOP_0_3_VALUE_2_MASK 0x00ff0000 +#define MAC_PCU_TXOP_0_3_VALUE_2_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_2_MASK) >> MAC_PCU_TXOP_0_3_VALUE_2_LSB) +#define MAC_PCU_TXOP_0_3_VALUE_2_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_2_LSB) & MAC_PCU_TXOP_0_3_VALUE_2_MASK) +#define MAC_PCU_TXOP_0_3_VALUE_1_MSB 15 +#define MAC_PCU_TXOP_0_3_VALUE_1_LSB 8 +#define MAC_PCU_TXOP_0_3_VALUE_1_MASK 0x0000ff00 +#define MAC_PCU_TXOP_0_3_VALUE_1_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_1_MASK) >> MAC_PCU_TXOP_0_3_VALUE_1_LSB) +#define MAC_PCU_TXOP_0_3_VALUE_1_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_1_LSB) & MAC_PCU_TXOP_0_3_VALUE_1_MASK) +#define MAC_PCU_TXOP_0_3_VALUE_0_MSB 7 +#define MAC_PCU_TXOP_0_3_VALUE_0_LSB 0 +#define MAC_PCU_TXOP_0_3_VALUE_0_MASK 0x000000ff +#define MAC_PCU_TXOP_0_3_VALUE_0_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_0_MASK) >> MAC_PCU_TXOP_0_3_VALUE_0_LSB) +#define MAC_PCU_TXOP_0_3_VALUE_0_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_0_LSB) & MAC_PCU_TXOP_0_3_VALUE_0_MASK) + +#define MAC_PCU_TXOP_4_7_ADDRESS 0x00008104 +#define MAC_PCU_TXOP_4_7_OFFSET 0x00000104 +#define MAC_PCU_TXOP_4_7_VALUE_7_MSB 31 +#define MAC_PCU_TXOP_4_7_VALUE_7_LSB 24 +#define MAC_PCU_TXOP_4_7_VALUE_7_MASK 0xff000000 +#define MAC_PCU_TXOP_4_7_VALUE_7_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_7_MASK) >> MAC_PCU_TXOP_4_7_VALUE_7_LSB) +#define MAC_PCU_TXOP_4_7_VALUE_7_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_7_LSB) & MAC_PCU_TXOP_4_7_VALUE_7_MASK) +#define MAC_PCU_TXOP_4_7_VALUE_6_MSB 23 +#define MAC_PCU_TXOP_4_7_VALUE_6_LSB 16 +#define MAC_PCU_TXOP_4_7_VALUE_6_MASK 0x00ff0000 +#define MAC_PCU_TXOP_4_7_VALUE_6_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_6_MASK) >> MAC_PCU_TXOP_4_7_VALUE_6_LSB) +#define MAC_PCU_TXOP_4_7_VALUE_6_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_6_LSB) & MAC_PCU_TXOP_4_7_VALUE_6_MASK) +#define MAC_PCU_TXOP_4_7_VALUE_5_MSB 15 +#define MAC_PCU_TXOP_4_7_VALUE_5_LSB 8 +#define MAC_PCU_TXOP_4_7_VALUE_5_MASK 0x0000ff00 +#define MAC_PCU_TXOP_4_7_VALUE_5_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_5_MASK) >> MAC_PCU_TXOP_4_7_VALUE_5_LSB) +#define MAC_PCU_TXOP_4_7_VALUE_5_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_5_LSB) & MAC_PCU_TXOP_4_7_VALUE_5_MASK) +#define MAC_PCU_TXOP_4_7_VALUE_4_MSB 7 +#define MAC_PCU_TXOP_4_7_VALUE_4_LSB 0 +#define MAC_PCU_TXOP_4_7_VALUE_4_MASK 0x000000ff +#define MAC_PCU_TXOP_4_7_VALUE_4_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_4_MASK) >> MAC_PCU_TXOP_4_7_VALUE_4_LSB) +#define MAC_PCU_TXOP_4_7_VALUE_4_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_4_LSB) & MAC_PCU_TXOP_4_7_VALUE_4_MASK) + +#define MAC_PCU_TXOP_8_11_ADDRESS 0x00008108 +#define MAC_PCU_TXOP_8_11_OFFSET 0x00000108 +#define MAC_PCU_TXOP_8_11_VALUE_11_MSB 31 +#define MAC_PCU_TXOP_8_11_VALUE_11_LSB 24 +#define MAC_PCU_TXOP_8_11_VALUE_11_MASK 0xff000000 +#define MAC_PCU_TXOP_8_11_VALUE_11_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_11_MASK) >> MAC_PCU_TXOP_8_11_VALUE_11_LSB) +#define MAC_PCU_TXOP_8_11_VALUE_11_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_11_LSB) & MAC_PCU_TXOP_8_11_VALUE_11_MASK) +#define MAC_PCU_TXOP_8_11_VALUE_10_MSB 23 +#define MAC_PCU_TXOP_8_11_VALUE_10_LSB 16 +#define MAC_PCU_TXOP_8_11_VALUE_10_MASK 0x00ff0000 +#define MAC_PCU_TXOP_8_11_VALUE_10_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_10_MASK) >> MAC_PCU_TXOP_8_11_VALUE_10_LSB) +#define MAC_PCU_TXOP_8_11_VALUE_10_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_10_LSB) & MAC_PCU_TXOP_8_11_VALUE_10_MASK) +#define MAC_PCU_TXOP_8_11_VALUE_9_MSB 15 +#define MAC_PCU_TXOP_8_11_VALUE_9_LSB 8 +#define MAC_PCU_TXOP_8_11_VALUE_9_MASK 0x0000ff00 +#define MAC_PCU_TXOP_8_11_VALUE_9_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_9_MASK) >> MAC_PCU_TXOP_8_11_VALUE_9_LSB) +#define MAC_PCU_TXOP_8_11_VALUE_9_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_9_LSB) & MAC_PCU_TXOP_8_11_VALUE_9_MASK) +#define MAC_PCU_TXOP_8_11_VALUE_8_MSB 7 +#define MAC_PCU_TXOP_8_11_VALUE_8_LSB 0 +#define MAC_PCU_TXOP_8_11_VALUE_8_MASK 0x000000ff +#define MAC_PCU_TXOP_8_11_VALUE_8_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_8_MASK) >> MAC_PCU_TXOP_8_11_VALUE_8_LSB) +#define MAC_PCU_TXOP_8_11_VALUE_8_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_8_LSB) & MAC_PCU_TXOP_8_11_VALUE_8_MASK) + +#define MAC_PCU_TXOP_12_15_ADDRESS 0x0000810c +#define MAC_PCU_TXOP_12_15_OFFSET 0x0000010c +#define MAC_PCU_TXOP_12_15_VALUE_15_MSB 31 +#define MAC_PCU_TXOP_12_15_VALUE_15_LSB 24 +#define MAC_PCU_TXOP_12_15_VALUE_15_MASK 0xff000000 +#define MAC_PCU_TXOP_12_15_VALUE_15_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_15_MASK) >> MAC_PCU_TXOP_12_15_VALUE_15_LSB) +#define MAC_PCU_TXOP_12_15_VALUE_15_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_15_LSB) & MAC_PCU_TXOP_12_15_VALUE_15_MASK) +#define MAC_PCU_TXOP_12_15_VALUE_14_MSB 23 +#define MAC_PCU_TXOP_12_15_VALUE_14_LSB 16 +#define MAC_PCU_TXOP_12_15_VALUE_14_MASK 0x00ff0000 +#define MAC_PCU_TXOP_12_15_VALUE_14_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_14_MASK) >> MAC_PCU_TXOP_12_15_VALUE_14_LSB) +#define MAC_PCU_TXOP_12_15_VALUE_14_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_14_LSB) & MAC_PCU_TXOP_12_15_VALUE_14_MASK) +#define MAC_PCU_TXOP_12_15_VALUE_13_MSB 15 +#define MAC_PCU_TXOP_12_15_VALUE_13_LSB 8 +#define MAC_PCU_TXOP_12_15_VALUE_13_MASK 0x0000ff00 +#define MAC_PCU_TXOP_12_15_VALUE_13_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_13_MASK) >> MAC_PCU_TXOP_12_15_VALUE_13_LSB) +#define MAC_PCU_TXOP_12_15_VALUE_13_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_13_LSB) & MAC_PCU_TXOP_12_15_VALUE_13_MASK) +#define MAC_PCU_TXOP_12_15_VALUE_12_MSB 7 +#define MAC_PCU_TXOP_12_15_VALUE_12_LSB 0 +#define MAC_PCU_TXOP_12_15_VALUE_12_MASK 0x000000ff +#define MAC_PCU_TXOP_12_15_VALUE_12_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_12_MASK) >> MAC_PCU_TXOP_12_15_VALUE_12_LSB) +#define MAC_PCU_TXOP_12_15_VALUE_12_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_12_LSB) & MAC_PCU_TXOP_12_15_VALUE_12_MASK) + +#define MAC_PCU_LOGIC_ANALYZER_ADDRESS 0x00008110 +#define MAC_PCU_LOGIC_ANALYZER_OFFSET 0x00000110 +#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MSB 31 +#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB 18 +#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK 0xfffc0000 +#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK) >> MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB) +#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB) & MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK) +#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MSB 17 +#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB 8 +#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK 0x0003ff00 +#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK) >> MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB) +#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB) & MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK) +#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MSB 7 +#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB 4 +#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK 0x000000f0 +#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK) >> MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB) +#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB) & MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK) +#define MAC_PCU_LOGIC_ANALYZER_ENABLE_MSB 3 +#define MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB 3 +#define MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK 0x00000008 +#define MAC_PCU_LOGIC_ANALYZER_ENABLE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK) >> MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB) +#define MAC_PCU_LOGIC_ANALYZER_ENABLE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB) & MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK) +#define MAC_PCU_LOGIC_ANALYZER_STATE_MSB 2 +#define MAC_PCU_LOGIC_ANALYZER_STATE_LSB 2 +#define MAC_PCU_LOGIC_ANALYZER_STATE_MASK 0x00000004 +#define MAC_PCU_LOGIC_ANALYZER_STATE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_STATE_MASK) >> MAC_PCU_LOGIC_ANALYZER_STATE_LSB) +#define MAC_PCU_LOGIC_ANALYZER_STATE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_STATE_LSB) & MAC_PCU_LOGIC_ANALYZER_STATE_MASK) +#define MAC_PCU_LOGIC_ANALYZER_CLEAR_MSB 1 +#define MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB 1 +#define MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK 0x00000002 +#define MAC_PCU_LOGIC_ANALYZER_CLEAR_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK) >> MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB) +#define MAC_PCU_LOGIC_ANALYZER_CLEAR_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB) & MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK) +#define MAC_PCU_LOGIC_ANALYZER_HOLD_MSB 0 +#define MAC_PCU_LOGIC_ANALYZER_HOLD_LSB 0 +#define MAC_PCU_LOGIC_ANALYZER_HOLD_MASK 0x00000001 +#define MAC_PCU_LOGIC_ANALYZER_HOLD_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_HOLD_MASK) >> MAC_PCU_LOGIC_ANALYZER_HOLD_LSB) +#define MAC_PCU_LOGIC_ANALYZER_HOLD_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_HOLD_LSB) & MAC_PCU_LOGIC_ANALYZER_HOLD_MASK) + +#define MAC_PCU_LOGIC_ANALYZER_32L_ADDRESS 0x00008114 +#define MAC_PCU_LOGIC_ANALYZER_32L_OFFSET 0x00000114 +#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_MSB 31 +#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB 0 +#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK 0xffffffff +#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK) >> MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB) +#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB) & MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK) + +#define MAC_PCU_LOGIC_ANALYZER_16U_ADDRESS 0x00008118 +#define MAC_PCU_LOGIC_ANALYZER_16U_OFFSET 0x00000118 +#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_MSB 15 +#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB 0 +#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK 0x0000ffff +#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK) >> MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB) +#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB) & MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK) + +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_ADDRESS 0x0000811c +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_OFFSET 0x0000011c +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MSB 23 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB 16 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK 0x00ff0000 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MSB 15 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB 8 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK 0x0000ff00 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MSB 7 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK 0x000000ff +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK) + +#define MAC_PCU_AZIMUTH_MODE_ADDRESS 0x00008120 +#define MAC_PCU_AZIMUTH_MODE_OFFSET 0x00000120 +#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MSB 7 +#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB 7 +#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK 0x00000080 +#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK) >> MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB) +#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB) & MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK) +#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MSB 6 +#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB 6 +#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK 0x00000040 +#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK) >> MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB) +#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB) & MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK) +#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MSB 5 +#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB 5 +#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK 0x00000020 +#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK) >> MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB) +#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB) & MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK) +#define MAC_PCU_AZIMUTH_MODE_CLK_EN_MSB 4 +#define MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB 4 +#define MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK 0x00000010 +#define MAC_PCU_AZIMUTH_MODE_CLK_EN_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK) >> MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB) +#define MAC_PCU_AZIMUTH_MODE_CLK_EN_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB) & MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK) +#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MSB 3 +#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB 3 +#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK 0x00000008 +#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK) >> MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB) +#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB) & MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK) +#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MSB 2 +#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB 2 +#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK 0x00000004 +#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK) >> MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB) +#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB) & MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK) +#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MSB 1 +#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB 1 +#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK 0x00000002 +#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK) >> MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB) +#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB) & MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK) +#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MSB 0 +#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB 0 +#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK 0x00000001 +#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK) >> MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB) +#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB) & MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK) + +#define MAC_PCU_20_40_MODE_ADDRESS 0x00008124 +#define MAC_PCU_20_40_MODE_OFFSET 0x00000124 +#define MAC_PCU_20_40_MODE_PIFS_CYCLES_MSB 15 +#define MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB 4 +#define MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK 0x0000fff0 +#define MAC_PCU_20_40_MODE_PIFS_CYCLES_GET(x) (((x) & MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK) >> MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB) +#define MAC_PCU_20_40_MODE_PIFS_CYCLES_SET(x) (((x) << MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB) & MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK) +#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MSB 3 +#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB 3 +#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK 0x00000008 +#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_GET(x) (((x) & MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK) >> MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB) +#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_SET(x) (((x) << MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB) & MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK) +#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MSB 2 +#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB 2 +#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK 0x00000004 +#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_GET(x) (((x) & MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK) >> MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB) +#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_SET(x) (((x) << MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB) & MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK) +#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MSB 1 +#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB 1 +#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK 0x00000002 +#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_GET(x) (((x) & MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK) >> MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB) +#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_SET(x) (((x) << MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB) & MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK) +#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MSB 0 +#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB 0 +#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK 0x00000001 +#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_GET(x) (((x) & MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK) >> MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB) +#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_SET(x) (((x) << MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB) & MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK) + +#define MAC_PCU_RX_CLEAR_DIFF_CNT_ADDRESS 0x00008128 +#define MAC_PCU_RX_CLEAR_DIFF_CNT_OFFSET 0x00000128 +#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MSB 31 +#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB 0 +#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK 0xffffffff +#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK) >> MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB) +#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB) & MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK) + +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_ADDRESS 0x0000812c +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_OFFSET 0x0000012c +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MSB 2 +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB 0 +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK 0x00000007 +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_GET(x) (((x) & MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK) >> MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_SET(x) (((x) << MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB) & MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK) + +#define MAC_PCU_BA_BAR_CONTROL_ADDRESS 0x00008130 +#define MAC_PCU_BA_BAR_CONTROL_OFFSET 0x00000130 +#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MSB 12 +#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB 12 +#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK 0x00001000 +#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK) >> MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB) +#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB) & MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK) +#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MSB 11 +#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB 11 +#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK 0x00000800 +#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK) >> MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB) +#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB) & MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK) +#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MSB 10 +#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB 10 +#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK 0x00000400 +#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK) >> MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB) +#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB) & MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK) +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MSB 9 +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB 9 +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK 0x00000200 +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK) >> MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB) +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK) +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MSB 8 +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB 8 +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK 0x00000100 +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK) >> MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB) +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK) +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MSB 7 +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB 4 +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK 0x000000f0 +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK) >> MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB) +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK) +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MSB 3 +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB 0 +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK 0x0000000f +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK) >> MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB) +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK) + +#define MAC_PCU_LEGACY_PLCP_SPOOF_ADDRESS 0x00008134 +#define MAC_PCU_LEGACY_PLCP_SPOOF_OFFSET 0x00000134 +#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MSB 12 +#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB 8 +#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK 0x00001f00 +#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_GET(x) (((x) & MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK) >> MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB) +#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_SET(x) (((x) << MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB) & MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK) +#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MSB 7 +#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB 0 +#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK 0x000000ff +#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_GET(x) (((x) & MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK) >> MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB) +#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_SET(x) (((x) << MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB) & MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK) + +#define MAC_PCU_PHY_ERROR_MASK_CONT_ADDRESS 0x00008138 +#define MAC_PCU_PHY_ERROR_MASK_CONT_OFFSET 0x00000138 +#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MSB 23 +#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB 16 +#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK 0x00ff0000 +#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB) +#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK) +#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MSB 7 +#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB 0 +#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK 0x000000ff +#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB) +#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK) + +#define MAC_PCU_TX_TIMER_ADDRESS 0x0000813c +#define MAC_PCU_TX_TIMER_OFFSET 0x0000013c +#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MSB 25 +#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB 25 +#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK 0x02000000 +#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_GET(x) (((x) & MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK) >> MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB) +#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_SET(x) (((x) << MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB) & MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK) +#define MAC_PCU_TX_TIMER_QUIET_TIMER_MSB 24 +#define MAC_PCU_TX_TIMER_QUIET_TIMER_LSB 20 +#define MAC_PCU_TX_TIMER_QUIET_TIMER_MASK 0x01f00000 +#define MAC_PCU_TX_TIMER_QUIET_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_QUIET_TIMER_MASK) >> MAC_PCU_TX_TIMER_QUIET_TIMER_LSB) +#define MAC_PCU_TX_TIMER_QUIET_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_QUIET_TIMER_LSB) & MAC_PCU_TX_TIMER_QUIET_TIMER_MASK) +#define MAC_PCU_TX_TIMER_RIFS_TIMER_MSB 19 +#define MAC_PCU_TX_TIMER_RIFS_TIMER_LSB 16 +#define MAC_PCU_TX_TIMER_RIFS_TIMER_MASK 0x000f0000 +#define MAC_PCU_TX_TIMER_RIFS_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_RIFS_TIMER_MASK) >> MAC_PCU_TX_TIMER_RIFS_TIMER_LSB) +#define MAC_PCU_TX_TIMER_RIFS_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_RIFS_TIMER_LSB) & MAC_PCU_TX_TIMER_RIFS_TIMER_MASK) +#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MSB 15 +#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB 15 +#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK 0x00008000 +#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_GET(x) (((x) & MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK) >> MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB) +#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_SET(x) (((x) << MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB) & MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK) +#define MAC_PCU_TX_TIMER_TX_TIMER_MSB 14 +#define MAC_PCU_TX_TIMER_TX_TIMER_LSB 0 +#define MAC_PCU_TX_TIMER_TX_TIMER_MASK 0x00007fff +#define MAC_PCU_TX_TIMER_TX_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_TX_TIMER_MASK) >> MAC_PCU_TX_TIMER_TX_TIMER_LSB) +#define MAC_PCU_TX_TIMER_TX_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_TX_TIMER_LSB) & MAC_PCU_TX_TIMER_TX_TIMER_MASK) + +#define MAC_PCU_TXBUF_CTRL_ADDRESS 0x00008140 +#define MAC_PCU_TXBUF_CTRL_OFFSET 0x00000140 +#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MSB 16 +#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB 16 +#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK 0x00010000 +#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_GET(x) (((x) & MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK) >> MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB) +#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_SET(x) (((x) << MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB) & MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK) +#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MSB 11 +#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB 0 +#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK 0x00000fff +#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_GET(x) (((x) & MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK) >> MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB) +#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_SET(x) (((x) << MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB) & MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK) + +#define MAC_PCU_MISC_MODE2_ADDRESS 0x00008144 +#define MAC_PCU_MISC_MODE2_OFFSET 0x00000144 +#define MAC_PCU_MISC_MODE2_RESERVED_1_MSB 31 +#define MAC_PCU_MISC_MODE2_RESERVED_1_LSB 28 +#define MAC_PCU_MISC_MODE2_RESERVED_1_MASK 0xf0000000 +#define MAC_PCU_MISC_MODE2_RESERVED_1_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESERVED_1_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_1_LSB) +#define MAC_PCU_MISC_MODE2_RESERVED_1_SET(x) (((x) << MAC_PCU_MISC_MODE2_RESERVED_1_LSB) & MAC_PCU_MISC_MODE2_RESERVED_1_MASK) +#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MSB 27 +#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB 27 +#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK 0x08000000 +#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_GET(x) (((x) & MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK) >> MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB) +#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_SET(x) (((x) << MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB) & MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK) +#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MSB 26 +#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB 26 +#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK 0x04000000 +#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_GET(x) (((x) & MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK) >> MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB) +#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_SET(x) (((x) << MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB) & MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK) +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MSB 25 +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB 25 +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK 0x02000000 +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_GET(x) (((x) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK) >> MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB) +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_SET(x) (((x) << MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK) +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MSB 24 +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB 24 +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK 0x01000000 +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_GET(x) (((x) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK) >> MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB) +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_SET(x) (((x) << MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK) +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MSB 23 +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB 23 +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK 0x00800000 +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_GET(x) (((x) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK) >> MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB) +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_SET(x) (((x) << MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK) +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MSB 22 +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB 22 +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK 0x00400000 +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_GET(x) (((x) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK) >> MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB) +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_SET(x) (((x) << MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK) +#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MSB 21 +#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB 21 +#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK 0x00200000 +#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_GET(x) (((x) & MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK) >> MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB) +#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_SET(x) (((x) << MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB) & MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK) +#define MAC_PCU_MISC_MODE2_BUG_28676_MSB 20 +#define MAC_PCU_MISC_MODE2_BUG_28676_LSB 20 +#define MAC_PCU_MISC_MODE2_BUG_28676_MASK 0x00100000 +#define MAC_PCU_MISC_MODE2_BUG_28676_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_28676_MASK) >> MAC_PCU_MISC_MODE2_BUG_28676_LSB) +#define MAC_PCU_MISC_MODE2_BUG_28676_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_28676_LSB) & MAC_PCU_MISC_MODE2_BUG_28676_MASK) +#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MSB 19 +#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB 19 +#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK 0x00080000 +#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_GET(x) (((x) & MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK) >> MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB) +#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_SET(x) (((x) << MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB) & MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK) +#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MSB 18 +#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB 18 +#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK 0x00040000 +#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK) >> MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB) +#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB) & MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK) +#define MAC_PCU_MISC_MODE2_AGG_WEP_MSB 17 +#define MAC_PCU_MISC_MODE2_AGG_WEP_LSB 17 +#define MAC_PCU_MISC_MODE2_AGG_WEP_MASK 0x00020000 +#define MAC_PCU_MISC_MODE2_AGG_WEP_GET(x) (((x) & MAC_PCU_MISC_MODE2_AGG_WEP_MASK) >> MAC_PCU_MISC_MODE2_AGG_WEP_LSB) +#define MAC_PCU_MISC_MODE2_AGG_WEP_SET(x) (((x) << MAC_PCU_MISC_MODE2_AGG_WEP_LSB) & MAC_PCU_MISC_MODE2_AGG_WEP_MASK) +#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MSB 16 +#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB 16 +#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK 0x00010000 +#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_GET(x) (((x) & MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK) >> MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB) +#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_SET(x) (((x) << MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB) & MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK) +#define MAC_PCU_MISC_MODE2_MGMT_QOS_MSB 15 +#define MAC_PCU_MISC_MODE2_MGMT_QOS_LSB 8 +#define MAC_PCU_MISC_MODE2_MGMT_QOS_MASK 0x0000ff00 +#define MAC_PCU_MISC_MODE2_MGMT_QOS_GET(x) (((x) & MAC_PCU_MISC_MODE2_MGMT_QOS_MASK) >> MAC_PCU_MISC_MODE2_MGMT_QOS_LSB) +#define MAC_PCU_MISC_MODE2_MGMT_QOS_SET(x) (((x) << MAC_PCU_MISC_MODE2_MGMT_QOS_LSB) & MAC_PCU_MISC_MODE2_MGMT_QOS_MASK) +#define MAC_PCU_MISC_MODE2_CFP_IGNORE_MSB 7 +#define MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB 7 +#define MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK 0x00000080 +#define MAC_PCU_MISC_MODE2_CFP_IGNORE_GET(x) (((x) & MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK) >> MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB) +#define MAC_PCU_MISC_MODE2_CFP_IGNORE_SET(x) (((x) << MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB) & MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK) +#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MSB 6 +#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB 6 +#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK 0x00000040 +#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB) +#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB) & MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK) +#define MAC_PCU_MISC_MODE2_RESERVED_2_MSB 5 +#define MAC_PCU_MISC_MODE2_RESERVED_2_LSB 5 +#define MAC_PCU_MISC_MODE2_RESERVED_2_MASK 0x00000020 +#define MAC_PCU_MISC_MODE2_RESERVED_2_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESERVED_2_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_2_LSB) +#define MAC_PCU_MISC_MODE2_RESERVED_2_SET(x) (((x) << MAC_PCU_MISC_MODE2_RESERVED_2_LSB) & MAC_PCU_MISC_MODE2_RESERVED_2_MASK) +#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MSB 4 +#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB 4 +#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK 0x00000010 +#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB) +#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB) & MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK) +#define MAC_PCU_MISC_MODE2_RESERVED_0_MSB 3 +#define MAC_PCU_MISC_MODE2_RESERVED_0_LSB 3 +#define MAC_PCU_MISC_MODE2_RESERVED_0_MASK 0x00000008 +#define MAC_PCU_MISC_MODE2_RESERVED_0_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESERVED_0_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_0_LSB) +#define MAC_PCU_MISC_MODE2_RESERVED_0_SET(x) (((x) << MAC_PCU_MISC_MODE2_RESERVED_0_LSB) & MAC_PCU_MISC_MODE2_RESERVED_0_MASK) +#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MSB 2 +#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB 2 +#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK 0x00000004 +#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_GET(x) (((x) & MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK) >> MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB) +#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_SET(x) (((x) << MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB) & MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK) +#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MSB 1 +#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB 1 +#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK 0x00000002 +#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB) +#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB) & MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK) +#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MSB 0 +#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB 0 +#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK 0x00000001 +#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB) +#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB) & MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK) + +#define MAC_PCU_ALT_AES_MUTE_MASK_ADDRESS 0x00008148 +#define MAC_PCU_ALT_AES_MUTE_MASK_OFFSET 0x00000148 +#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_MSB 31 +#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB 16 +#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK 0xffff0000 +#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_GET(x) (((x) & MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK) >> MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB) +#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_SET(x) (((x) << MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB) & MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK) + +#define MAC_PCU_AZIMUTH_TIME_STAMP_ADDRESS 0x0000814c +#define MAC_PCU_AZIMUTH_TIME_STAMP_OFFSET 0x0000014c +#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MSB 31 +#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB 0 +#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK 0xffffffff +#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_GET(x) (((x) & MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK) >> MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB) +#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_SET(x) (((x) << MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB) & MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK) + +#define MAC_PCU_MAX_CFP_DUR_ADDRESS 0x00008150 +#define MAC_PCU_MAX_CFP_DUR_OFFSET 0x00000150 +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MSB 7 +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB 4 +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK 0x000000f0 +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_GET(x) (((x) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK) >> MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB) +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_SET(x) (((x) << MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK) +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MSB 3 +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB 0 +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK 0x0000000f +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_GET(x) (((x) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK) >> MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB) +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_SET(x) (((x) << MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK) + +#define MAC_PCU_HCF_TIMEOUT_ADDRESS 0x00008154 +#define MAC_PCU_HCF_TIMEOUT_OFFSET 0x00000154 +#define MAC_PCU_HCF_TIMEOUT_VALUE_MSB 15 +#define MAC_PCU_HCF_TIMEOUT_VALUE_LSB 0 +#define MAC_PCU_HCF_TIMEOUT_VALUE_MASK 0x0000ffff +#define MAC_PCU_HCF_TIMEOUT_VALUE_GET(x) (((x) & MAC_PCU_HCF_TIMEOUT_VALUE_MASK) >> MAC_PCU_HCF_TIMEOUT_VALUE_LSB) +#define MAC_PCU_HCF_TIMEOUT_VALUE_SET(x) (((x) << MAC_PCU_HCF_TIMEOUT_VALUE_LSB) & MAC_PCU_HCF_TIMEOUT_VALUE_MASK) + +#define MAC_PCU_BLUETOOTH_WEIGHTS2_ADDRESS 0x00008158 +#define MAC_PCU_BLUETOOTH_WEIGHTS2_OFFSET 0x00000158 +#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MSB 31 +#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB 16 +#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK 0xffff0000 +#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB) +#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK) + +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_ADDRESS 0x0000815c +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_OFFSET 0x0000015c +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MSB 31 +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB 0 +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK 0xffffffff +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_GET(x) (((x) & MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK) >> MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB) +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_SET(x) (((x) << MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB) & MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK) + +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_ADDRESS 0x00008160 +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_OFFSET 0x00000160 +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MSB 31 +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB 0 +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK 0xffffffff +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_GET(x) (((x) & MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK) >> MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB) +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_SET(x) (((x) << MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB) & MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK) + +#define MAC_PCU_BLUETOOTH_MODE3_ADDRESS 0x00008164 +#define MAC_PCU_BLUETOOTH_MODE3_OFFSET 0x00000164 +#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MSB 31 +#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB 28 +#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK 0xf0000000 +#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK) >> MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB) & MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MSB 27 +#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB 27 +#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK 0x08000000 +#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MSB 26 +#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB 25 +#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK 0x06000000 +#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK) >> MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB) & MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MSB 24 +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB 24 +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK 0x01000000 +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MSB 23 +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB 23 +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK 0x00800000 +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MSB 22 +#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB 22 +#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK 0x00400000 +#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK) >> MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB) & MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MSB 21 +#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB 21 +#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK 0x00200000 +#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MSB 20 +#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB 20 +#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK 0x00100000 +#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK) >> MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB) & MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MSB 19 +#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB 16 +#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK 0x000f0000 +#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK) >> MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB) & MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MSB 15 +#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB 8 +#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK 0x0000ff00 +#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MSB 7 +#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB 0 +#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK 0x000000ff +#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK) + +#define MAC_PCU_BLUETOOTH_MODE4_ADDRESS 0x00008168 +#define MAC_PCU_BLUETOOTH_MODE4_OFFSET 0x00000168 +#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MSB 31 +#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB 16 +#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK 0xffff0000 +#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB) +#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK) +#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MSB 15 +#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB 0 +#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK 0x0000ffff +#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB) +#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK) + +#define MAC_PCU_BT_BT_ADDRESS 0x00008200 +#define MAC_PCU_BT_BT_OFFSET 0x00000200 +#define MAC_PCU_BT_BT_WEIGHT_MSB 31 +#define MAC_PCU_BT_BT_WEIGHT_LSB 0 +#define MAC_PCU_BT_BT_WEIGHT_MASK 0xffffffff +#define MAC_PCU_BT_BT_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_WEIGHT_MASK) >> MAC_PCU_BT_BT_WEIGHT_LSB) +#define MAC_PCU_BT_BT_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_WEIGHT_LSB) & MAC_PCU_BT_BT_WEIGHT_MASK) + +#define MAC_PCU_BT_BT_ASYNC_ADDRESS 0x00008300 +#define MAC_PCU_BT_BT_ASYNC_OFFSET 0x00000300 +#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MSB 15 +#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB 12 +#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK 0x0000f000 +#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB) +#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK) +#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MSB 11 +#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB 8 +#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK 0x00000f00 +#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB) +#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK) +#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MSB 7 +#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB 4 +#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK 0x000000f0 +#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB) +#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK) +#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MSB 3 +#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB 0 +#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK 0x0000000f +#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB) +#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK) + +#define MAC_PCU_BT_WL_1_ADDRESS 0x00008304 +#define MAC_PCU_BT_WL_1_OFFSET 0x00000304 +#define MAC_PCU_BT_WL_1_WEIGHT_MSB 31 +#define MAC_PCU_BT_WL_1_WEIGHT_LSB 0 +#define MAC_PCU_BT_WL_1_WEIGHT_MASK 0xffffffff +#define MAC_PCU_BT_WL_1_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_1_WEIGHT_MASK) >> MAC_PCU_BT_WL_1_WEIGHT_LSB) +#define MAC_PCU_BT_WL_1_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_1_WEIGHT_LSB) & MAC_PCU_BT_WL_1_WEIGHT_MASK) + +#define MAC_PCU_BT_WL_2_ADDRESS 0x00008308 +#define MAC_PCU_BT_WL_2_OFFSET 0x00000308 +#define MAC_PCU_BT_WL_2_WEIGHT_MSB 31 +#define MAC_PCU_BT_WL_2_WEIGHT_LSB 0 +#define MAC_PCU_BT_WL_2_WEIGHT_MASK 0xffffffff +#define MAC_PCU_BT_WL_2_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_2_WEIGHT_MASK) >> MAC_PCU_BT_WL_2_WEIGHT_LSB) +#define MAC_PCU_BT_WL_2_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_2_WEIGHT_LSB) & MAC_PCU_BT_WL_2_WEIGHT_MASK) + +#define MAC_PCU_BT_WL_3_ADDRESS 0x0000830c +#define MAC_PCU_BT_WL_3_OFFSET 0x0000030c +#define MAC_PCU_BT_WL_3_WEIGHT_MSB 31 +#define MAC_PCU_BT_WL_3_WEIGHT_LSB 0 +#define MAC_PCU_BT_WL_3_WEIGHT_MASK 0xffffffff +#define MAC_PCU_BT_WL_3_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_3_WEIGHT_MASK) >> MAC_PCU_BT_WL_3_WEIGHT_LSB) +#define MAC_PCU_BT_WL_3_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_3_WEIGHT_LSB) & MAC_PCU_BT_WL_3_WEIGHT_MASK) + +#define MAC_PCU_BT_WL_4_ADDRESS 0x00008310 +#define MAC_PCU_BT_WL_4_OFFSET 0x00000310 +#define MAC_PCU_BT_WL_4_WEIGHT_MSB 31 +#define MAC_PCU_BT_WL_4_WEIGHT_LSB 0 +#define MAC_PCU_BT_WL_4_WEIGHT_MASK 0xffffffff +#define MAC_PCU_BT_WL_4_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_4_WEIGHT_MASK) >> MAC_PCU_BT_WL_4_WEIGHT_LSB) +#define MAC_PCU_BT_WL_4_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_4_WEIGHT_LSB) & MAC_PCU_BT_WL_4_WEIGHT_MASK) + +#define MAC_PCU_COEX_EPTA_ADDRESS 0x00008314 +#define MAC_PCU_COEX_EPTA_OFFSET 0x00000314 +#define MAC_PCU_COEX_EPTA_WT_IDX_MSB 12 +#define MAC_PCU_COEX_EPTA_WT_IDX_LSB 6 +#define MAC_PCU_COEX_EPTA_WT_IDX_MASK 0x00001fc0 +#define MAC_PCU_COEX_EPTA_WT_IDX_GET(x) (((x) & MAC_PCU_COEX_EPTA_WT_IDX_MASK) >> MAC_PCU_COEX_EPTA_WT_IDX_LSB) +#define MAC_PCU_COEX_EPTA_WT_IDX_SET(x) (((x) << MAC_PCU_COEX_EPTA_WT_IDX_LSB) & MAC_PCU_COEX_EPTA_WT_IDX_MASK) +#define MAC_PCU_COEX_EPTA_LINKID_MSB 5 +#define MAC_PCU_COEX_EPTA_LINKID_LSB 0 +#define MAC_PCU_COEX_EPTA_LINKID_MASK 0x0000003f +#define MAC_PCU_COEX_EPTA_LINKID_GET(x) (((x) & MAC_PCU_COEX_EPTA_LINKID_MASK) >> MAC_PCU_COEX_EPTA_LINKID_LSB) +#define MAC_PCU_COEX_EPTA_LINKID_SET(x) (((x) << MAC_PCU_COEX_EPTA_LINKID_LSB) & MAC_PCU_COEX_EPTA_LINKID_MASK) + +#define MAC_PCU_COEX_LNAMAXGAIN1_ADDRESS 0x00008318 +#define MAC_PCU_COEX_LNAMAXGAIN1_OFFSET 0x00000318 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MSB 31 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB 24 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK 0xff000000 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MSB 23 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB 16 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK 0x00ff0000 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MSB 15 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB 8 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK 0x0000ff00 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MSB 7 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB 0 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK 0x000000ff +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK) + +#define MAC_PCU_COEX_LNAMAXGAIN2_ADDRESS 0x0000831c +#define MAC_PCU_COEX_LNAMAXGAIN2_OFFSET 0x0000031c +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MSB 31 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB 24 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK 0xff000000 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MSB 23 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB 16 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK 0x00ff0000 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MSB 15 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB 8 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK 0x0000ff00 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MSB 7 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB 0 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK 0x000000ff +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK) + +#define MAC_PCU_COEX_LNAMAXGAIN3_ADDRESS 0x00008320 +#define MAC_PCU_COEX_LNAMAXGAIN3_OFFSET 0x00000320 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MSB 31 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB 24 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK 0xff000000 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MSB 23 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB 16 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK 0x00ff0000 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MSB 15 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB 8 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK 0x0000ff00 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MSB 7 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB 0 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK 0x000000ff +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK) + +#define MAC_PCU_COEX_LNAMAXGAIN4_ADDRESS 0x00008324 +#define MAC_PCU_COEX_LNAMAXGAIN4_OFFSET 0x00000324 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MSB 31 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB 24 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK 0xff000000 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MSB 23 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB 16 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK 0x00ff0000 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MSB 15 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB 8 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK 0x0000ff00 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MSB 7 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB 0 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK 0x000000ff +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK) + +#define MAC_PCU_BASIC_RATE_SET0_ADDRESS 0x00008328 +#define MAC_PCU_BASIC_RATE_SET0_OFFSET 0x00000328 +#define MAC_PCU_BASIC_RATE_SET0_VALUE_MSB 29 +#define MAC_PCU_BASIC_RATE_SET0_VALUE_LSB 0 +#define MAC_PCU_BASIC_RATE_SET0_VALUE_MASK 0x3fffffff +#define MAC_PCU_BASIC_RATE_SET0_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET0_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET0_VALUE_LSB) +#define MAC_PCU_BASIC_RATE_SET0_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET0_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET0_VALUE_MASK) + +#define MAC_PCU_BASIC_RATE_SET1_ADDRESS 0x0000832c +#define MAC_PCU_BASIC_RATE_SET1_OFFSET 0x0000032c +#define MAC_PCU_BASIC_RATE_SET1_VALUE_MSB 29 +#define MAC_PCU_BASIC_RATE_SET1_VALUE_LSB 0 +#define MAC_PCU_BASIC_RATE_SET1_VALUE_MASK 0x3fffffff +#define MAC_PCU_BASIC_RATE_SET1_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET1_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET1_VALUE_LSB) +#define MAC_PCU_BASIC_RATE_SET1_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET1_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET1_VALUE_MASK) + +#define MAC_PCU_BASIC_RATE_SET2_ADDRESS 0x00008330 +#define MAC_PCU_BASIC_RATE_SET2_OFFSET 0x00000330 +#define MAC_PCU_BASIC_RATE_SET2_VALUE_MSB 29 +#define MAC_PCU_BASIC_RATE_SET2_VALUE_LSB 0 +#define MAC_PCU_BASIC_RATE_SET2_VALUE_MASK 0x3fffffff +#define MAC_PCU_BASIC_RATE_SET2_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET2_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET2_VALUE_LSB) +#define MAC_PCU_BASIC_RATE_SET2_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET2_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET2_VALUE_MASK) + +#define MAC_PCU_BASIC_RATE_SET3_ADDRESS 0x00008334 +#define MAC_PCU_BASIC_RATE_SET3_OFFSET 0x00000334 +#define MAC_PCU_BASIC_RATE_SET3_VALUE_MSB 24 +#define MAC_PCU_BASIC_RATE_SET3_VALUE_LSB 0 +#define MAC_PCU_BASIC_RATE_SET3_VALUE_MASK 0x01ffffff +#define MAC_PCU_BASIC_RATE_SET3_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET3_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET3_VALUE_LSB) +#define MAC_PCU_BASIC_RATE_SET3_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET3_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET3_VALUE_MASK) + +#define MAC_PCU_RX_INT_STATUS0_ADDRESS 0x00008338 +#define MAC_PCU_RX_INT_STATUS0_OFFSET 0x00000338 +#define MAC_PCU_RX_INT_STATUS0_DURATION_H_MSB 31 +#define MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB 24 +#define MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK 0xff000000 +#define MAC_PCU_RX_INT_STATUS0_DURATION_H_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK) >> MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB) +#define MAC_PCU_RX_INT_STATUS0_DURATION_H_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB) & MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK) +#define MAC_PCU_RX_INT_STATUS0_DURATION_L_MSB 23 +#define MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB 16 +#define MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK 0x00ff0000 +#define MAC_PCU_RX_INT_STATUS0_DURATION_L_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK) >> MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB) +#define MAC_PCU_RX_INT_STATUS0_DURATION_L_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB) & MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK) +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MSB 15 +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB 8 +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK 0x0000ff00 +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK) >> MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB) +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK) +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MSB 7 +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB 0 +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK 0x000000ff +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK) >> MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB) +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK) + +#define MAC_PCU_RX_INT_STATUS1_ADDRESS 0x0000833c +#define MAC_PCU_RX_INT_STATUS1_OFFSET 0x0000033c +#define MAC_PCU_RX_INT_STATUS1_VALUE_MSB 17 +#define MAC_PCU_RX_INT_STATUS1_VALUE_LSB 0 +#define MAC_PCU_RX_INT_STATUS1_VALUE_MASK 0x0003ffff +#define MAC_PCU_RX_INT_STATUS1_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS1_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS1_VALUE_LSB) +#define MAC_PCU_RX_INT_STATUS1_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS1_VALUE_LSB) & MAC_PCU_RX_INT_STATUS1_VALUE_MASK) + +#define MAC_PCU_RX_INT_STATUS2_ADDRESS 0x00008340 +#define MAC_PCU_RX_INT_STATUS2_OFFSET 0x00000340 +#define MAC_PCU_RX_INT_STATUS2_VALUE_MSB 26 +#define MAC_PCU_RX_INT_STATUS2_VALUE_LSB 0 +#define MAC_PCU_RX_INT_STATUS2_VALUE_MASK 0x07ffffff +#define MAC_PCU_RX_INT_STATUS2_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS2_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS2_VALUE_LSB) +#define MAC_PCU_RX_INT_STATUS2_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS2_VALUE_LSB) & MAC_PCU_RX_INT_STATUS2_VALUE_MASK) + +#define MAC_PCU_RX_INT_STATUS3_ADDRESS 0x00008344 +#define MAC_PCU_RX_INT_STATUS3_OFFSET 0x00000344 +#define MAC_PCU_RX_INT_STATUS3_VALUE_MSB 23 +#define MAC_PCU_RX_INT_STATUS3_VALUE_LSB 0 +#define MAC_PCU_RX_INT_STATUS3_VALUE_MASK 0x00ffffff +#define MAC_PCU_RX_INT_STATUS3_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS3_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS3_VALUE_LSB) +#define MAC_PCU_RX_INT_STATUS3_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS3_VALUE_LSB) & MAC_PCU_RX_INT_STATUS3_VALUE_MASK) + +#define HT_HALF_GI_RATE1_ADDRESS 0x00008348 +#define HT_HALF_GI_RATE1_OFFSET 0x00000348 +#define HT_HALF_GI_RATE1_MCS3_MSB 31 +#define HT_HALF_GI_RATE1_MCS3_LSB 24 +#define HT_HALF_GI_RATE1_MCS3_MASK 0xff000000 +#define HT_HALF_GI_RATE1_MCS3_GET(x) (((x) & HT_HALF_GI_RATE1_MCS3_MASK) >> HT_HALF_GI_RATE1_MCS3_LSB) +#define HT_HALF_GI_RATE1_MCS3_SET(x) (((x) << HT_HALF_GI_RATE1_MCS3_LSB) & HT_HALF_GI_RATE1_MCS3_MASK) +#define HT_HALF_GI_RATE1_MCS2_MSB 23 +#define HT_HALF_GI_RATE1_MCS2_LSB 16 +#define HT_HALF_GI_RATE1_MCS2_MASK 0x00ff0000 +#define HT_HALF_GI_RATE1_MCS2_GET(x) (((x) & HT_HALF_GI_RATE1_MCS2_MASK) >> HT_HALF_GI_RATE1_MCS2_LSB) +#define HT_HALF_GI_RATE1_MCS2_SET(x) (((x) << HT_HALF_GI_RATE1_MCS2_LSB) & HT_HALF_GI_RATE1_MCS2_MASK) +#define HT_HALF_GI_RATE1_MCS1_MSB 15 +#define HT_HALF_GI_RATE1_MCS1_LSB 8 +#define HT_HALF_GI_RATE1_MCS1_MASK 0x0000ff00 +#define HT_HALF_GI_RATE1_MCS1_GET(x) (((x) & HT_HALF_GI_RATE1_MCS1_MASK) >> HT_HALF_GI_RATE1_MCS1_LSB) +#define HT_HALF_GI_RATE1_MCS1_SET(x) (((x) << HT_HALF_GI_RATE1_MCS1_LSB) & HT_HALF_GI_RATE1_MCS1_MASK) +#define HT_HALF_GI_RATE1_MCS0_MSB 7 +#define HT_HALF_GI_RATE1_MCS0_LSB 0 +#define HT_HALF_GI_RATE1_MCS0_MASK 0x000000ff +#define HT_HALF_GI_RATE1_MCS0_GET(x) (((x) & HT_HALF_GI_RATE1_MCS0_MASK) >> HT_HALF_GI_RATE1_MCS0_LSB) +#define HT_HALF_GI_RATE1_MCS0_SET(x) (((x) << HT_HALF_GI_RATE1_MCS0_LSB) & HT_HALF_GI_RATE1_MCS0_MASK) + +#define HT_HALF_GI_RATE2_ADDRESS 0x0000834c +#define HT_HALF_GI_RATE2_OFFSET 0x0000034c +#define HT_HALF_GI_RATE2_MCS7_MSB 31 +#define HT_HALF_GI_RATE2_MCS7_LSB 24 +#define HT_HALF_GI_RATE2_MCS7_MASK 0xff000000 +#define HT_HALF_GI_RATE2_MCS7_GET(x) (((x) & HT_HALF_GI_RATE2_MCS7_MASK) >> HT_HALF_GI_RATE2_MCS7_LSB) +#define HT_HALF_GI_RATE2_MCS7_SET(x) (((x) << HT_HALF_GI_RATE2_MCS7_LSB) & HT_HALF_GI_RATE2_MCS7_MASK) +#define HT_HALF_GI_RATE2_MCS6_MSB 23 +#define HT_HALF_GI_RATE2_MCS6_LSB 16 +#define HT_HALF_GI_RATE2_MCS6_MASK 0x00ff0000 +#define HT_HALF_GI_RATE2_MCS6_GET(x) (((x) & HT_HALF_GI_RATE2_MCS6_MASK) >> HT_HALF_GI_RATE2_MCS6_LSB) +#define HT_HALF_GI_RATE2_MCS6_SET(x) (((x) << HT_HALF_GI_RATE2_MCS6_LSB) & HT_HALF_GI_RATE2_MCS6_MASK) +#define HT_HALF_GI_RATE2_MCS5_MSB 15 +#define HT_HALF_GI_RATE2_MCS5_LSB 8 +#define HT_HALF_GI_RATE2_MCS5_MASK 0x0000ff00 +#define HT_HALF_GI_RATE2_MCS5_GET(x) (((x) & HT_HALF_GI_RATE2_MCS5_MASK) >> HT_HALF_GI_RATE2_MCS5_LSB) +#define HT_HALF_GI_RATE2_MCS5_SET(x) (((x) << HT_HALF_GI_RATE2_MCS5_LSB) & HT_HALF_GI_RATE2_MCS5_MASK) +#define HT_HALF_GI_RATE2_MCS4_MSB 7 +#define HT_HALF_GI_RATE2_MCS4_LSB 0 +#define HT_HALF_GI_RATE2_MCS4_MASK 0x000000ff +#define HT_HALF_GI_RATE2_MCS4_GET(x) (((x) & HT_HALF_GI_RATE2_MCS4_MASK) >> HT_HALF_GI_RATE2_MCS4_LSB) +#define HT_HALF_GI_RATE2_MCS4_SET(x) (((x) << HT_HALF_GI_RATE2_MCS4_LSB) & HT_HALF_GI_RATE2_MCS4_MASK) + +#define HT_FULL_GI_RATE1_ADDRESS 0x00008350 +#define HT_FULL_GI_RATE1_OFFSET 0x00000350 +#define HT_FULL_GI_RATE1_MCS3_MSB 31 +#define HT_FULL_GI_RATE1_MCS3_LSB 24 +#define HT_FULL_GI_RATE1_MCS3_MASK 0xff000000 +#define HT_FULL_GI_RATE1_MCS3_GET(x) (((x) & HT_FULL_GI_RATE1_MCS3_MASK) >> HT_FULL_GI_RATE1_MCS3_LSB) +#define HT_FULL_GI_RATE1_MCS3_SET(x) (((x) << HT_FULL_GI_RATE1_MCS3_LSB) & HT_FULL_GI_RATE1_MCS3_MASK) +#define HT_FULL_GI_RATE1_MCS2_MSB 23 +#define HT_FULL_GI_RATE1_MCS2_LSB 16 +#define HT_FULL_GI_RATE1_MCS2_MASK 0x00ff0000 +#define HT_FULL_GI_RATE1_MCS2_GET(x) (((x) & HT_FULL_GI_RATE1_MCS2_MASK) >> HT_FULL_GI_RATE1_MCS2_LSB) +#define HT_FULL_GI_RATE1_MCS2_SET(x) (((x) << HT_FULL_GI_RATE1_MCS2_LSB) & HT_FULL_GI_RATE1_MCS2_MASK) +#define HT_FULL_GI_RATE1_MCS1_MSB 15 +#define HT_FULL_GI_RATE1_MCS1_LSB 8 +#define HT_FULL_GI_RATE1_MCS1_MASK 0x0000ff00 +#define HT_FULL_GI_RATE1_MCS1_GET(x) (((x) & HT_FULL_GI_RATE1_MCS1_MASK) >> HT_FULL_GI_RATE1_MCS1_LSB) +#define HT_FULL_GI_RATE1_MCS1_SET(x) (((x) << HT_FULL_GI_RATE1_MCS1_LSB) & HT_FULL_GI_RATE1_MCS1_MASK) +#define HT_FULL_GI_RATE1_MCS0_MSB 7 +#define HT_FULL_GI_RATE1_MCS0_LSB 0 +#define HT_FULL_GI_RATE1_MCS0_MASK 0x000000ff +#define HT_FULL_GI_RATE1_MCS0_GET(x) (((x) & HT_FULL_GI_RATE1_MCS0_MASK) >> HT_FULL_GI_RATE1_MCS0_LSB) +#define HT_FULL_GI_RATE1_MCS0_SET(x) (((x) << HT_FULL_GI_RATE1_MCS0_LSB) & HT_FULL_GI_RATE1_MCS0_MASK) + +#define HT_FULL_GI_RATE2_ADDRESS 0x00008354 +#define HT_FULL_GI_RATE2_OFFSET 0x00000354 +#define HT_FULL_GI_RATE2_MCS7_MSB 31 +#define HT_FULL_GI_RATE2_MCS7_LSB 24 +#define HT_FULL_GI_RATE2_MCS7_MASK 0xff000000 +#define HT_FULL_GI_RATE2_MCS7_GET(x) (((x) & HT_FULL_GI_RATE2_MCS7_MASK) >> HT_FULL_GI_RATE2_MCS7_LSB) +#define HT_FULL_GI_RATE2_MCS7_SET(x) (((x) << HT_FULL_GI_RATE2_MCS7_LSB) & HT_FULL_GI_RATE2_MCS7_MASK) +#define HT_FULL_GI_RATE2_MCS6_MSB 23 +#define HT_FULL_GI_RATE2_MCS6_LSB 16 +#define HT_FULL_GI_RATE2_MCS6_MASK 0x00ff0000 +#define HT_FULL_GI_RATE2_MCS6_GET(x) (((x) & HT_FULL_GI_RATE2_MCS6_MASK) >> HT_FULL_GI_RATE2_MCS6_LSB) +#define HT_FULL_GI_RATE2_MCS6_SET(x) (((x) << HT_FULL_GI_RATE2_MCS6_LSB) & HT_FULL_GI_RATE2_MCS6_MASK) +#define HT_FULL_GI_RATE2_MCS5_MSB 15 +#define HT_FULL_GI_RATE2_MCS5_LSB 8 +#define HT_FULL_GI_RATE2_MCS5_MASK 0x0000ff00 +#define HT_FULL_GI_RATE2_MCS5_GET(x) (((x) & HT_FULL_GI_RATE2_MCS5_MASK) >> HT_FULL_GI_RATE2_MCS5_LSB) +#define HT_FULL_GI_RATE2_MCS5_SET(x) (((x) << HT_FULL_GI_RATE2_MCS5_LSB) & HT_FULL_GI_RATE2_MCS5_MASK) +#define HT_FULL_GI_RATE2_MCS4_MSB 7 +#define HT_FULL_GI_RATE2_MCS4_LSB 0 +#define HT_FULL_GI_RATE2_MCS4_MASK 0x000000ff +#define HT_FULL_GI_RATE2_MCS4_GET(x) (((x) & HT_FULL_GI_RATE2_MCS4_MASK) >> HT_FULL_GI_RATE2_MCS4_LSB) +#define HT_FULL_GI_RATE2_MCS4_SET(x) (((x) << HT_FULL_GI_RATE2_MCS4_LSB) & HT_FULL_GI_RATE2_MCS4_MASK) + +#define LEGACY_RATE1_ADDRESS 0x00008358 +#define LEGACY_RATE1_OFFSET 0x00000358 +#define LEGACY_RATE1_RATE12_MSB 29 +#define LEGACY_RATE1_RATE12_LSB 24 +#define LEGACY_RATE1_RATE12_MASK 0x3f000000 +#define LEGACY_RATE1_RATE12_GET(x) (((x) & LEGACY_RATE1_RATE12_MASK) >> LEGACY_RATE1_RATE12_LSB) +#define LEGACY_RATE1_RATE12_SET(x) (((x) << LEGACY_RATE1_RATE12_LSB) & LEGACY_RATE1_RATE12_MASK) +#define LEGACY_RATE1_RATE11_MSB 23 +#define LEGACY_RATE1_RATE11_LSB 18 +#define LEGACY_RATE1_RATE11_MASK 0x00fc0000 +#define LEGACY_RATE1_RATE11_GET(x) (((x) & LEGACY_RATE1_RATE11_MASK) >> LEGACY_RATE1_RATE11_LSB) +#define LEGACY_RATE1_RATE11_SET(x) (((x) << LEGACY_RATE1_RATE11_LSB) & LEGACY_RATE1_RATE11_MASK) +#define LEGACY_RATE1_RATE10_MSB 17 +#define LEGACY_RATE1_RATE10_LSB 12 +#define LEGACY_RATE1_RATE10_MASK 0x0003f000 +#define LEGACY_RATE1_RATE10_GET(x) (((x) & LEGACY_RATE1_RATE10_MASK) >> LEGACY_RATE1_RATE10_LSB) +#define LEGACY_RATE1_RATE10_SET(x) (((x) << LEGACY_RATE1_RATE10_LSB) & LEGACY_RATE1_RATE10_MASK) +#define LEGACY_RATE1_RATE9_MSB 11 +#define LEGACY_RATE1_RATE9_LSB 6 +#define LEGACY_RATE1_RATE9_MASK 0x00000fc0 +#define LEGACY_RATE1_RATE9_GET(x) (((x) & LEGACY_RATE1_RATE9_MASK) >> LEGACY_RATE1_RATE9_LSB) +#define LEGACY_RATE1_RATE9_SET(x) (((x) << LEGACY_RATE1_RATE9_LSB) & LEGACY_RATE1_RATE9_MASK) +#define LEGACY_RATE1_RATE8_MSB 5 +#define LEGACY_RATE1_RATE8_LSB 0 +#define LEGACY_RATE1_RATE8_MASK 0x0000003f +#define LEGACY_RATE1_RATE8_GET(x) (((x) & LEGACY_RATE1_RATE8_MASK) >> LEGACY_RATE1_RATE8_LSB) +#define LEGACY_RATE1_RATE8_SET(x) (((x) << LEGACY_RATE1_RATE8_LSB) & LEGACY_RATE1_RATE8_MASK) + +#define LEGACY_RATE2_ADDRESS 0x0000835c +#define LEGACY_RATE2_OFFSET 0x0000035c +#define LEGACY_RATE2_RATE25_MSB 29 +#define LEGACY_RATE2_RATE25_LSB 24 +#define LEGACY_RATE2_RATE25_MASK 0x3f000000 +#define LEGACY_RATE2_RATE25_GET(x) (((x) & LEGACY_RATE2_RATE25_MASK) >> LEGACY_RATE2_RATE25_LSB) +#define LEGACY_RATE2_RATE25_SET(x) (((x) << LEGACY_RATE2_RATE25_LSB) & LEGACY_RATE2_RATE25_MASK) +#define LEGACY_RATE2_RATE24_MSB 23 +#define LEGACY_RATE2_RATE24_LSB 18 +#define LEGACY_RATE2_RATE24_MASK 0x00fc0000 +#define LEGACY_RATE2_RATE24_GET(x) (((x) & LEGACY_RATE2_RATE24_MASK) >> LEGACY_RATE2_RATE24_LSB) +#define LEGACY_RATE2_RATE24_SET(x) (((x) << LEGACY_RATE2_RATE24_LSB) & LEGACY_RATE2_RATE24_MASK) +#define LEGACY_RATE2_RATE15_MSB 17 +#define LEGACY_RATE2_RATE15_LSB 12 +#define LEGACY_RATE2_RATE15_MASK 0x0003f000 +#define LEGACY_RATE2_RATE15_GET(x) (((x) & LEGACY_RATE2_RATE15_MASK) >> LEGACY_RATE2_RATE15_LSB) +#define LEGACY_RATE2_RATE15_SET(x) (((x) << LEGACY_RATE2_RATE15_LSB) & LEGACY_RATE2_RATE15_MASK) +#define LEGACY_RATE2_RATE14_MSB 11 +#define LEGACY_RATE2_RATE14_LSB 6 +#define LEGACY_RATE2_RATE14_MASK 0x00000fc0 +#define LEGACY_RATE2_RATE14_GET(x) (((x) & LEGACY_RATE2_RATE14_MASK) >> LEGACY_RATE2_RATE14_LSB) +#define LEGACY_RATE2_RATE14_SET(x) (((x) << LEGACY_RATE2_RATE14_LSB) & LEGACY_RATE2_RATE14_MASK) +#define LEGACY_RATE2_RATE13_MSB 5 +#define LEGACY_RATE2_RATE13_LSB 0 +#define LEGACY_RATE2_RATE13_MASK 0x0000003f +#define LEGACY_RATE2_RATE13_GET(x) (((x) & LEGACY_RATE2_RATE13_MASK) >> LEGACY_RATE2_RATE13_LSB) +#define LEGACY_RATE2_RATE13_SET(x) (((x) << LEGACY_RATE2_RATE13_LSB) & LEGACY_RATE2_RATE13_MASK) + +#define LEGACY_RATE3_ADDRESS 0x00008360 +#define LEGACY_RATE3_OFFSET 0x00000360 +#define LEGACY_RATE3_RATE30_MSB 29 +#define LEGACY_RATE3_RATE30_LSB 24 +#define LEGACY_RATE3_RATE30_MASK 0x3f000000 +#define LEGACY_RATE3_RATE30_GET(x) (((x) & LEGACY_RATE3_RATE30_MASK) >> LEGACY_RATE3_RATE30_LSB) +#define LEGACY_RATE3_RATE30_SET(x) (((x) << LEGACY_RATE3_RATE30_LSB) & LEGACY_RATE3_RATE30_MASK) +#define LEGACY_RATE3_RATE29_MSB 23 +#define LEGACY_RATE3_RATE29_LSB 18 +#define LEGACY_RATE3_RATE29_MASK 0x00fc0000 +#define LEGACY_RATE3_RATE29_GET(x) (((x) & LEGACY_RATE3_RATE29_MASK) >> LEGACY_RATE3_RATE29_LSB) +#define LEGACY_RATE3_RATE29_SET(x) (((x) << LEGACY_RATE3_RATE29_LSB) & LEGACY_RATE3_RATE29_MASK) +#define LEGACY_RATE3_RATE28_MSB 17 +#define LEGACY_RATE3_RATE28_LSB 12 +#define LEGACY_RATE3_RATE28_MASK 0x0003f000 +#define LEGACY_RATE3_RATE28_GET(x) (((x) & LEGACY_RATE3_RATE28_MASK) >> LEGACY_RATE3_RATE28_LSB) +#define LEGACY_RATE3_RATE28_SET(x) (((x) << LEGACY_RATE3_RATE28_LSB) & LEGACY_RATE3_RATE28_MASK) +#define LEGACY_RATE3_RATE27_MSB 11 +#define LEGACY_RATE3_RATE27_LSB 6 +#define LEGACY_RATE3_RATE27_MASK 0x00000fc0 +#define LEGACY_RATE3_RATE27_GET(x) (((x) & LEGACY_RATE3_RATE27_MASK) >> LEGACY_RATE3_RATE27_LSB) +#define LEGACY_RATE3_RATE27_SET(x) (((x) << LEGACY_RATE3_RATE27_LSB) & LEGACY_RATE3_RATE27_MASK) +#define LEGACY_RATE3_RATE26_MSB 5 +#define LEGACY_RATE3_RATE26_LSB 0 +#define LEGACY_RATE3_RATE26_MASK 0x0000003f +#define LEGACY_RATE3_RATE26_GET(x) (((x) & LEGACY_RATE3_RATE26_MASK) >> LEGACY_RATE3_RATE26_LSB) +#define LEGACY_RATE3_RATE26_SET(x) (((x) << LEGACY_RATE3_RATE26_LSB) & LEGACY_RATE3_RATE26_MASK) + +#define RX_INT_FILTER_ADDRESS 0x00008364 +#define RX_INT_FILTER_OFFSET 0x00000364 +#define RX_INT_FILTER_BEACON_MSB 17 +#define RX_INT_FILTER_BEACON_LSB 17 +#define RX_INT_FILTER_BEACON_MASK 0x00020000 +#define RX_INT_FILTER_BEACON_GET(x) (((x) & RX_INT_FILTER_BEACON_MASK) >> RX_INT_FILTER_BEACON_LSB) +#define RX_INT_FILTER_BEACON_SET(x) (((x) << RX_INT_FILTER_BEACON_LSB) & RX_INT_FILTER_BEACON_MASK) +#define RX_INT_FILTER_AMPDU_MSB 16 +#define RX_INT_FILTER_AMPDU_LSB 16 +#define RX_INT_FILTER_AMPDU_MASK 0x00010000 +#define RX_INT_FILTER_AMPDU_GET(x) (((x) & RX_INT_FILTER_AMPDU_MASK) >> RX_INT_FILTER_AMPDU_LSB) +#define RX_INT_FILTER_AMPDU_SET(x) (((x) << RX_INT_FILTER_AMPDU_LSB) & RX_INT_FILTER_AMPDU_MASK) +#define RX_INT_FILTER_EOSP_MSB 15 +#define RX_INT_FILTER_EOSP_LSB 15 +#define RX_INT_FILTER_EOSP_MASK 0x00008000 +#define RX_INT_FILTER_EOSP_GET(x) (((x) & RX_INT_FILTER_EOSP_MASK) >> RX_INT_FILTER_EOSP_LSB) +#define RX_INT_FILTER_EOSP_SET(x) (((x) << RX_INT_FILTER_EOSP_LSB) & RX_INT_FILTER_EOSP_MASK) +#define RX_INT_FILTER_LENGTH_LOW_MSB 14 +#define RX_INT_FILTER_LENGTH_LOW_LSB 14 +#define RX_INT_FILTER_LENGTH_LOW_MASK 0x00004000 +#define RX_INT_FILTER_LENGTH_LOW_GET(x) (((x) & RX_INT_FILTER_LENGTH_LOW_MASK) >> RX_INT_FILTER_LENGTH_LOW_LSB) +#define RX_INT_FILTER_LENGTH_LOW_SET(x) (((x) << RX_INT_FILTER_LENGTH_LOW_LSB) & RX_INT_FILTER_LENGTH_LOW_MASK) +#define RX_INT_FILTER_LENGTH_HIGH_MSB 13 +#define RX_INT_FILTER_LENGTH_HIGH_LSB 13 +#define RX_INT_FILTER_LENGTH_HIGH_MASK 0x00002000 +#define RX_INT_FILTER_LENGTH_HIGH_GET(x) (((x) & RX_INT_FILTER_LENGTH_HIGH_MASK) >> RX_INT_FILTER_LENGTH_HIGH_LSB) +#define RX_INT_FILTER_LENGTH_HIGH_SET(x) (((x) << RX_INT_FILTER_LENGTH_HIGH_LSB) & RX_INT_FILTER_LENGTH_HIGH_MASK) +#define RX_INT_FILTER_RSSI_MSB 12 +#define RX_INT_FILTER_RSSI_LSB 12 +#define RX_INT_FILTER_RSSI_MASK 0x00001000 +#define RX_INT_FILTER_RSSI_GET(x) (((x) & RX_INT_FILTER_RSSI_MASK) >> RX_INT_FILTER_RSSI_LSB) +#define RX_INT_FILTER_RSSI_SET(x) (((x) << RX_INT_FILTER_RSSI_LSB) & RX_INT_FILTER_RSSI_MASK) +#define RX_INT_FILTER_RATE_LOW_MSB 11 +#define RX_INT_FILTER_RATE_LOW_LSB 11 +#define RX_INT_FILTER_RATE_LOW_MASK 0x00000800 +#define RX_INT_FILTER_RATE_LOW_GET(x) (((x) & RX_INT_FILTER_RATE_LOW_MASK) >> RX_INT_FILTER_RATE_LOW_LSB) +#define RX_INT_FILTER_RATE_LOW_SET(x) (((x) << RX_INT_FILTER_RATE_LOW_LSB) & RX_INT_FILTER_RATE_LOW_MASK) +#define RX_INT_FILTER_RATE_HIGH_MSB 10 +#define RX_INT_FILTER_RATE_HIGH_LSB 10 +#define RX_INT_FILTER_RATE_HIGH_MASK 0x00000400 +#define RX_INT_FILTER_RATE_HIGH_GET(x) (((x) & RX_INT_FILTER_RATE_HIGH_MASK) >> RX_INT_FILTER_RATE_HIGH_LSB) +#define RX_INT_FILTER_RATE_HIGH_SET(x) (((x) << RX_INT_FILTER_RATE_HIGH_LSB) & RX_INT_FILTER_RATE_HIGH_MASK) +#define RX_INT_FILTER_MORE_FRAG_MSB 9 +#define RX_INT_FILTER_MORE_FRAG_LSB 9 +#define RX_INT_FILTER_MORE_FRAG_MASK 0x00000200 +#define RX_INT_FILTER_MORE_FRAG_GET(x) (((x) & RX_INT_FILTER_MORE_FRAG_MASK) >> RX_INT_FILTER_MORE_FRAG_LSB) +#define RX_INT_FILTER_MORE_FRAG_SET(x) (((x) << RX_INT_FILTER_MORE_FRAG_LSB) & RX_INT_FILTER_MORE_FRAG_MASK) +#define RX_INT_FILTER_MORE_DATA_MSB 8 +#define RX_INT_FILTER_MORE_DATA_LSB 8 +#define RX_INT_FILTER_MORE_DATA_MASK 0x00000100 +#define RX_INT_FILTER_MORE_DATA_GET(x) (((x) & RX_INT_FILTER_MORE_DATA_MASK) >> RX_INT_FILTER_MORE_DATA_LSB) +#define RX_INT_FILTER_MORE_DATA_SET(x) (((x) << RX_INT_FILTER_MORE_DATA_LSB) & RX_INT_FILTER_MORE_DATA_MASK) +#define RX_INT_FILTER_RETRY_MSB 7 +#define RX_INT_FILTER_RETRY_LSB 7 +#define RX_INT_FILTER_RETRY_MASK 0x00000080 +#define RX_INT_FILTER_RETRY_GET(x) (((x) & RX_INT_FILTER_RETRY_MASK) >> RX_INT_FILTER_RETRY_LSB) +#define RX_INT_FILTER_RETRY_SET(x) (((x) << RX_INT_FILTER_RETRY_LSB) & RX_INT_FILTER_RETRY_MASK) +#define RX_INT_FILTER_CTS_MSB 6 +#define RX_INT_FILTER_CTS_LSB 6 +#define RX_INT_FILTER_CTS_MASK 0x00000040 +#define RX_INT_FILTER_CTS_GET(x) (((x) & RX_INT_FILTER_CTS_MASK) >> RX_INT_FILTER_CTS_LSB) +#define RX_INT_FILTER_CTS_SET(x) (((x) << RX_INT_FILTER_CTS_LSB) & RX_INT_FILTER_CTS_MASK) +#define RX_INT_FILTER_ACK_MSB 5 +#define RX_INT_FILTER_ACK_LSB 5 +#define RX_INT_FILTER_ACK_MASK 0x00000020 +#define RX_INT_FILTER_ACK_GET(x) (((x) & RX_INT_FILTER_ACK_MASK) >> RX_INT_FILTER_ACK_LSB) +#define RX_INT_FILTER_ACK_SET(x) (((x) << RX_INT_FILTER_ACK_LSB) & RX_INT_FILTER_ACK_MASK) +#define RX_INT_FILTER_RTS_MSB 4 +#define RX_INT_FILTER_RTS_LSB 4 +#define RX_INT_FILTER_RTS_MASK 0x00000010 +#define RX_INT_FILTER_RTS_GET(x) (((x) & RX_INT_FILTER_RTS_MASK) >> RX_INT_FILTER_RTS_LSB) +#define RX_INT_FILTER_RTS_SET(x) (((x) << RX_INT_FILTER_RTS_LSB) & RX_INT_FILTER_RTS_MASK) +#define RX_INT_FILTER_MCAST_MSB 3 +#define RX_INT_FILTER_MCAST_LSB 3 +#define RX_INT_FILTER_MCAST_MASK 0x00000008 +#define RX_INT_FILTER_MCAST_GET(x) (((x) & RX_INT_FILTER_MCAST_MASK) >> RX_INT_FILTER_MCAST_LSB) +#define RX_INT_FILTER_MCAST_SET(x) (((x) << RX_INT_FILTER_MCAST_LSB) & RX_INT_FILTER_MCAST_MASK) +#define RX_INT_FILTER_BCAST_MSB 2 +#define RX_INT_FILTER_BCAST_LSB 2 +#define RX_INT_FILTER_BCAST_MASK 0x00000004 +#define RX_INT_FILTER_BCAST_GET(x) (((x) & RX_INT_FILTER_BCAST_MASK) >> RX_INT_FILTER_BCAST_LSB) +#define RX_INT_FILTER_BCAST_SET(x) (((x) << RX_INT_FILTER_BCAST_LSB) & RX_INT_FILTER_BCAST_MASK) +#define RX_INT_FILTER_DIRECTED_MSB 1 +#define RX_INT_FILTER_DIRECTED_LSB 1 +#define RX_INT_FILTER_DIRECTED_MASK 0x00000002 +#define RX_INT_FILTER_DIRECTED_GET(x) (((x) & RX_INT_FILTER_DIRECTED_MASK) >> RX_INT_FILTER_DIRECTED_LSB) +#define RX_INT_FILTER_DIRECTED_SET(x) (((x) << RX_INT_FILTER_DIRECTED_LSB) & RX_INT_FILTER_DIRECTED_MASK) +#define RX_INT_FILTER_ENABLE_MSB 0 +#define RX_INT_FILTER_ENABLE_LSB 0 +#define RX_INT_FILTER_ENABLE_MASK 0x00000001 +#define RX_INT_FILTER_ENABLE_GET(x) (((x) & RX_INT_FILTER_ENABLE_MASK) >> RX_INT_FILTER_ENABLE_LSB) +#define RX_INT_FILTER_ENABLE_SET(x) (((x) << RX_INT_FILTER_ENABLE_LSB) & RX_INT_FILTER_ENABLE_MASK) + +#define RX_INT_OVERFLOW_ADDRESS 0x00008368 +#define RX_INT_OVERFLOW_OFFSET 0x00000368 +#define RX_INT_OVERFLOW_STATUS_MSB 0 +#define RX_INT_OVERFLOW_STATUS_LSB 0 +#define RX_INT_OVERFLOW_STATUS_MASK 0x00000001 +#define RX_INT_OVERFLOW_STATUS_GET(x) (((x) & RX_INT_OVERFLOW_STATUS_MASK) >> RX_INT_OVERFLOW_STATUS_LSB) +#define RX_INT_OVERFLOW_STATUS_SET(x) (((x) << RX_INT_OVERFLOW_STATUS_LSB) & RX_INT_OVERFLOW_STATUS_MASK) + +#define RX_FILTER_THRESH_ADDRESS 0x0000836c +#define RX_FILTER_THRESH_OFFSET 0x0000036c +#define RX_FILTER_THRESH_RSSI_LOW_MSB 23 +#define RX_FILTER_THRESH_RSSI_LOW_LSB 16 +#define RX_FILTER_THRESH_RSSI_LOW_MASK 0x00ff0000 +#define RX_FILTER_THRESH_RSSI_LOW_GET(x) (((x) & RX_FILTER_THRESH_RSSI_LOW_MASK) >> RX_FILTER_THRESH_RSSI_LOW_LSB) +#define RX_FILTER_THRESH_RSSI_LOW_SET(x) (((x) << RX_FILTER_THRESH_RSSI_LOW_LSB) & RX_FILTER_THRESH_RSSI_LOW_MASK) +#define RX_FILTER_THRESH_RATE_LOW_MSB 15 +#define RX_FILTER_THRESH_RATE_LOW_LSB 8 +#define RX_FILTER_THRESH_RATE_LOW_MASK 0x0000ff00 +#define RX_FILTER_THRESH_RATE_LOW_GET(x) (((x) & RX_FILTER_THRESH_RATE_LOW_MASK) >> RX_FILTER_THRESH_RATE_LOW_LSB) +#define RX_FILTER_THRESH_RATE_LOW_SET(x) (((x) << RX_FILTER_THRESH_RATE_LOW_LSB) & RX_FILTER_THRESH_RATE_LOW_MASK) +#define RX_FILTER_THRESH_RATE_HIGH_MSB 7 +#define RX_FILTER_THRESH_RATE_HIGH_LSB 0 +#define RX_FILTER_THRESH_RATE_HIGH_MASK 0x000000ff +#define RX_FILTER_THRESH_RATE_HIGH_GET(x) (((x) & RX_FILTER_THRESH_RATE_HIGH_MASK) >> RX_FILTER_THRESH_RATE_HIGH_LSB) +#define RX_FILTER_THRESH_RATE_HIGH_SET(x) (((x) << RX_FILTER_THRESH_RATE_HIGH_LSB) & RX_FILTER_THRESH_RATE_HIGH_MASK) + +#define RX_FILTER_THRESH1_ADDRESS 0x00008370 +#define RX_FILTER_THRESH1_OFFSET 0x00000370 +#define RX_FILTER_THRESH1_LENGTH_LOW_MSB 23 +#define RX_FILTER_THRESH1_LENGTH_LOW_LSB 12 +#define RX_FILTER_THRESH1_LENGTH_LOW_MASK 0x00fff000 +#define RX_FILTER_THRESH1_LENGTH_LOW_GET(x) (((x) & RX_FILTER_THRESH1_LENGTH_LOW_MASK) >> RX_FILTER_THRESH1_LENGTH_LOW_LSB) +#define RX_FILTER_THRESH1_LENGTH_LOW_SET(x) (((x) << RX_FILTER_THRESH1_LENGTH_LOW_LSB) & RX_FILTER_THRESH1_LENGTH_LOW_MASK) +#define RX_FILTER_THRESH1_LENGTH_HIGH_MSB 11 +#define RX_FILTER_THRESH1_LENGTH_HIGH_LSB 0 +#define RX_FILTER_THRESH1_LENGTH_HIGH_MASK 0x00000fff +#define RX_FILTER_THRESH1_LENGTH_HIGH_GET(x) (((x) & RX_FILTER_THRESH1_LENGTH_HIGH_MASK) >> RX_FILTER_THRESH1_LENGTH_HIGH_LSB) +#define RX_FILTER_THRESH1_LENGTH_HIGH_SET(x) (((x) << RX_FILTER_THRESH1_LENGTH_HIGH_LSB) & RX_FILTER_THRESH1_LENGTH_HIGH_MASK) + +#define RX_PRIORITY_THRESH0_ADDRESS 0x00008374 +#define RX_PRIORITY_THRESH0_OFFSET 0x00000374 +#define RX_PRIORITY_THRESH0_RSSI_LOW_MSB 31 +#define RX_PRIORITY_THRESH0_RSSI_LOW_LSB 24 +#define RX_PRIORITY_THRESH0_RSSI_LOW_MASK 0xff000000 +#define RX_PRIORITY_THRESH0_RSSI_LOW_GET(x) (((x) & RX_PRIORITY_THRESH0_RSSI_LOW_MASK) >> RX_PRIORITY_THRESH0_RSSI_LOW_LSB) +#define RX_PRIORITY_THRESH0_RSSI_LOW_SET(x) (((x) << RX_PRIORITY_THRESH0_RSSI_LOW_LSB) & RX_PRIORITY_THRESH0_RSSI_LOW_MASK) +#define RX_PRIORITY_THRESH0_RSSI_HIGH_MSB 23 +#define RX_PRIORITY_THRESH0_RSSI_HIGH_LSB 16 +#define RX_PRIORITY_THRESH0_RSSI_HIGH_MASK 0x00ff0000 +#define RX_PRIORITY_THRESH0_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH0_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH0_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH0_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH0_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH0_RSSI_HIGH_MASK) +#define RX_PRIORITY_THRESH0_RATE_LOW_MSB 15 +#define RX_PRIORITY_THRESH0_RATE_LOW_LSB 8 +#define RX_PRIORITY_THRESH0_RATE_LOW_MASK 0x0000ff00 +#define RX_PRIORITY_THRESH0_RATE_LOW_GET(x) (((x) & RX_PRIORITY_THRESH0_RATE_LOW_MASK) >> RX_PRIORITY_THRESH0_RATE_LOW_LSB) +#define RX_PRIORITY_THRESH0_RATE_LOW_SET(x) (((x) << RX_PRIORITY_THRESH0_RATE_LOW_LSB) & RX_PRIORITY_THRESH0_RATE_LOW_MASK) +#define RX_PRIORITY_THRESH0_RATE_HIGH_MSB 7 +#define RX_PRIORITY_THRESH0_RATE_HIGH_LSB 0 +#define RX_PRIORITY_THRESH0_RATE_HIGH_MASK 0x000000ff +#define RX_PRIORITY_THRESH0_RATE_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH0_RATE_HIGH_MASK) >> RX_PRIORITY_THRESH0_RATE_HIGH_LSB) +#define RX_PRIORITY_THRESH0_RATE_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH0_RATE_HIGH_LSB) & RX_PRIORITY_THRESH0_RATE_HIGH_MASK) + +#define RX_PRIORITY_THRESH1_ADDRESS 0x00008378 +#define RX_PRIORITY_THRESH1_OFFSET 0x00000378 +#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MSB 31 +#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB 24 +#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK 0xff000000 +#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK) +#define RX_PRIORITY_THRESH1_LENGTH_LOW_MSB 23 +#define RX_PRIORITY_THRESH1_LENGTH_LOW_LSB 12 +#define RX_PRIORITY_THRESH1_LENGTH_LOW_MASK 0x00fff000 +#define RX_PRIORITY_THRESH1_LENGTH_LOW_GET(x) (((x) & RX_PRIORITY_THRESH1_LENGTH_LOW_MASK) >> RX_PRIORITY_THRESH1_LENGTH_LOW_LSB) +#define RX_PRIORITY_THRESH1_LENGTH_LOW_SET(x) (((x) << RX_PRIORITY_THRESH1_LENGTH_LOW_LSB) & RX_PRIORITY_THRESH1_LENGTH_LOW_MASK) +#define RX_PRIORITY_THRESH1_LENGTH_HIGH_MSB 11 +#define RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB 0 +#define RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK 0x00000fff +#define RX_PRIORITY_THRESH1_LENGTH_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK) >> RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB) +#define RX_PRIORITY_THRESH1_LENGTH_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB) & RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK) + +#define RX_PRIORITY_THRESH2_ADDRESS 0x0000837c +#define RX_PRIORITY_THRESH2_OFFSET 0x0000037c +#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MSB 31 +#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB 24 +#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK 0xff000000 +#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK) +#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MSB 23 +#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB 16 +#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK 0x00ff0000 +#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK) +#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MSB 15 +#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB 8 +#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK 0x0000ff00 +#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK) +#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MSB 7 +#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB 0 +#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK 0x000000ff +#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK) + +#define RX_PRIORITY_THRESH3_ADDRESS 0x00008380 +#define RX_PRIORITY_THRESH3_OFFSET 0x00000380 +#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MSB 15 +#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB 8 +#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK 0x0000ff00 +#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK) +#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MSB 7 +#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB 0 +#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK 0x000000ff +#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK) + +#define RX_PRIORITY_OFFSET0_ADDRESS 0x00008384 +#define RX_PRIORITY_OFFSET0_OFFSET 0x00000384 +#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MSB 29 +#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB 24 +#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK 0x3f000000 +#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET0_RSSI_LOW_MSB 23 +#define RX_PRIORITY_OFFSET0_RSSI_LOW_LSB 18 +#define RX_PRIORITY_OFFSET0_RSSI_LOW_MASK 0x00fc0000 +#define RX_PRIORITY_OFFSET0_RSSI_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET0_RSSI_LOW_MASK) >> RX_PRIORITY_OFFSET0_RSSI_LOW_LSB) +#define RX_PRIORITY_OFFSET0_RSSI_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET0_RSSI_LOW_LSB) & RX_PRIORITY_OFFSET0_RSSI_LOW_MASK) +#define RX_PRIORITY_OFFSET0_RSSI_HIGH_MSB 17 +#define RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB 12 +#define RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK 0x0003f000 +#define RX_PRIORITY_OFFSET0_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET0_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MSB 11 +#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB 6 +#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK 0x00000fc0 +#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK) >> RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB) +#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB) & RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK) +#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MSB 5 +#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB 0 +#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK 0x0000003f +#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK) >> RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB) +#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB) & RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK) + +#define RX_PRIORITY_OFFSET1_ADDRESS 0x00008388 +#define RX_PRIORITY_OFFSET1_OFFSET 0x00000388 +#define RX_PRIORITY_OFFSET1_RTS_MSB 29 +#define RX_PRIORITY_OFFSET1_RTS_LSB 24 +#define RX_PRIORITY_OFFSET1_RTS_MASK 0x3f000000 +#define RX_PRIORITY_OFFSET1_RTS_GET(x) (((x) & RX_PRIORITY_OFFSET1_RTS_MASK) >> RX_PRIORITY_OFFSET1_RTS_LSB) +#define RX_PRIORITY_OFFSET1_RTS_SET(x) (((x) << RX_PRIORITY_OFFSET1_RTS_LSB) & RX_PRIORITY_OFFSET1_RTS_MASK) +#define RX_PRIORITY_OFFSET1_RETX_MSB 23 +#define RX_PRIORITY_OFFSET1_RETX_LSB 18 +#define RX_PRIORITY_OFFSET1_RETX_MASK 0x00fc0000 +#define RX_PRIORITY_OFFSET1_RETX_GET(x) (((x) & RX_PRIORITY_OFFSET1_RETX_MASK) >> RX_PRIORITY_OFFSET1_RETX_LSB) +#define RX_PRIORITY_OFFSET1_RETX_SET(x) (((x) << RX_PRIORITY_OFFSET1_RETX_LSB) & RX_PRIORITY_OFFSET1_RETX_MASK) +#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MSB 17 +#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB 12 +#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK 0x0003f000 +#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET1_LENGTH_LOW_MSB 11 +#define RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB 6 +#define RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK 0x00000fc0 +#define RX_PRIORITY_OFFSET1_LENGTH_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK) >> RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB) +#define RX_PRIORITY_OFFSET1_LENGTH_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB) & RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK) +#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_MSB 5 +#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB 0 +#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK 0x0000003f +#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK) >> RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB) +#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB) & RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK) + +#define RX_PRIORITY_OFFSET2_ADDRESS 0x0000838c +#define RX_PRIORITY_OFFSET2_OFFSET 0x0000038c +#define RX_PRIORITY_OFFSET2_BEACON_MSB 29 +#define RX_PRIORITY_OFFSET2_BEACON_LSB 24 +#define RX_PRIORITY_OFFSET2_BEACON_MASK 0x3f000000 +#define RX_PRIORITY_OFFSET2_BEACON_GET(x) (((x) & RX_PRIORITY_OFFSET2_BEACON_MASK) >> RX_PRIORITY_OFFSET2_BEACON_LSB) +#define RX_PRIORITY_OFFSET2_BEACON_SET(x) (((x) << RX_PRIORITY_OFFSET2_BEACON_LSB) & RX_PRIORITY_OFFSET2_BEACON_MASK) +#define RX_PRIORITY_OFFSET2_MGMT_MSB 23 +#define RX_PRIORITY_OFFSET2_MGMT_LSB 18 +#define RX_PRIORITY_OFFSET2_MGMT_MASK 0x00fc0000 +#define RX_PRIORITY_OFFSET2_MGMT_GET(x) (((x) & RX_PRIORITY_OFFSET2_MGMT_MASK) >> RX_PRIORITY_OFFSET2_MGMT_LSB) +#define RX_PRIORITY_OFFSET2_MGMT_SET(x) (((x) << RX_PRIORITY_OFFSET2_MGMT_LSB) & RX_PRIORITY_OFFSET2_MGMT_MASK) +#define RX_PRIORITY_OFFSET2_ATIM_MSB 17 +#define RX_PRIORITY_OFFSET2_ATIM_LSB 12 +#define RX_PRIORITY_OFFSET2_ATIM_MASK 0x0003f000 +#define RX_PRIORITY_OFFSET2_ATIM_GET(x) (((x) & RX_PRIORITY_OFFSET2_ATIM_MASK) >> RX_PRIORITY_OFFSET2_ATIM_LSB) +#define RX_PRIORITY_OFFSET2_ATIM_SET(x) (((x) << RX_PRIORITY_OFFSET2_ATIM_LSB) & RX_PRIORITY_OFFSET2_ATIM_MASK) +#define RX_PRIORITY_OFFSET2_PRESP_MSB 11 +#define RX_PRIORITY_OFFSET2_PRESP_LSB 6 +#define RX_PRIORITY_OFFSET2_PRESP_MASK 0x00000fc0 +#define RX_PRIORITY_OFFSET2_PRESP_GET(x) (((x) & RX_PRIORITY_OFFSET2_PRESP_MASK) >> RX_PRIORITY_OFFSET2_PRESP_LSB) +#define RX_PRIORITY_OFFSET2_PRESP_SET(x) (((x) << RX_PRIORITY_OFFSET2_PRESP_LSB) & RX_PRIORITY_OFFSET2_PRESP_MASK) +#define RX_PRIORITY_OFFSET2_XCAST_MSB 5 +#define RX_PRIORITY_OFFSET2_XCAST_LSB 0 +#define RX_PRIORITY_OFFSET2_XCAST_MASK 0x0000003f +#define RX_PRIORITY_OFFSET2_XCAST_GET(x) (((x) & RX_PRIORITY_OFFSET2_XCAST_MASK) >> RX_PRIORITY_OFFSET2_XCAST_LSB) +#define RX_PRIORITY_OFFSET2_XCAST_SET(x) (((x) << RX_PRIORITY_OFFSET2_XCAST_LSB) & RX_PRIORITY_OFFSET2_XCAST_MASK) + +#define RX_PRIORITY_OFFSET3_ADDRESS 0x00008390 +#define RX_PRIORITY_OFFSET3_OFFSET 0x00000390 +#define RX_PRIORITY_OFFSET3_PS_POLL_MSB 29 +#define RX_PRIORITY_OFFSET3_PS_POLL_LSB 24 +#define RX_PRIORITY_OFFSET3_PS_POLL_MASK 0x3f000000 +#define RX_PRIORITY_OFFSET3_PS_POLL_GET(x) (((x) & RX_PRIORITY_OFFSET3_PS_POLL_MASK) >> RX_PRIORITY_OFFSET3_PS_POLL_LSB) +#define RX_PRIORITY_OFFSET3_PS_POLL_SET(x) (((x) << RX_PRIORITY_OFFSET3_PS_POLL_LSB) & RX_PRIORITY_OFFSET3_PS_POLL_MASK) +#define RX_PRIORITY_OFFSET3_AMSDU_MSB 23 +#define RX_PRIORITY_OFFSET3_AMSDU_LSB 18 +#define RX_PRIORITY_OFFSET3_AMSDU_MASK 0x00fc0000 +#define RX_PRIORITY_OFFSET3_AMSDU_GET(x) (((x) & RX_PRIORITY_OFFSET3_AMSDU_MASK) >> RX_PRIORITY_OFFSET3_AMSDU_LSB) +#define RX_PRIORITY_OFFSET3_AMSDU_SET(x) (((x) << RX_PRIORITY_OFFSET3_AMSDU_LSB) & RX_PRIORITY_OFFSET3_AMSDU_MASK) +#define RX_PRIORITY_OFFSET3_AMPDU_MSB 17 +#define RX_PRIORITY_OFFSET3_AMPDU_LSB 12 +#define RX_PRIORITY_OFFSET3_AMPDU_MASK 0x0003f000 +#define RX_PRIORITY_OFFSET3_AMPDU_GET(x) (((x) & RX_PRIORITY_OFFSET3_AMPDU_MASK) >> RX_PRIORITY_OFFSET3_AMPDU_LSB) +#define RX_PRIORITY_OFFSET3_AMPDU_SET(x) (((x) << RX_PRIORITY_OFFSET3_AMPDU_LSB) & RX_PRIORITY_OFFSET3_AMPDU_MASK) +#define RX_PRIORITY_OFFSET3_EOSP_MSB 11 +#define RX_PRIORITY_OFFSET3_EOSP_LSB 6 +#define RX_PRIORITY_OFFSET3_EOSP_MASK 0x00000fc0 +#define RX_PRIORITY_OFFSET3_EOSP_GET(x) (((x) & RX_PRIORITY_OFFSET3_EOSP_MASK) >> RX_PRIORITY_OFFSET3_EOSP_LSB) +#define RX_PRIORITY_OFFSET3_EOSP_SET(x) (((x) << RX_PRIORITY_OFFSET3_EOSP_LSB) & RX_PRIORITY_OFFSET3_EOSP_MASK) +#define RX_PRIORITY_OFFSET3_MORE_MSB 5 +#define RX_PRIORITY_OFFSET3_MORE_LSB 0 +#define RX_PRIORITY_OFFSET3_MORE_MASK 0x0000003f +#define RX_PRIORITY_OFFSET3_MORE_GET(x) (((x) & RX_PRIORITY_OFFSET3_MORE_MASK) >> RX_PRIORITY_OFFSET3_MORE_LSB) +#define RX_PRIORITY_OFFSET3_MORE_SET(x) (((x) << RX_PRIORITY_OFFSET3_MORE_LSB) & RX_PRIORITY_OFFSET3_MORE_MASK) + +#define RX_PRIORITY_OFFSET4_ADDRESS 0x00008394 +#define RX_PRIORITY_OFFSET4_OFFSET 0x00000394 +#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MSB 29 +#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB 24 +#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK 0x3f000000 +#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MSB 23 +#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB 18 +#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK 0x00fc0000 +#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET4_BEACON_SSID_MSB 17 +#define RX_PRIORITY_OFFSET4_BEACON_SSID_LSB 12 +#define RX_PRIORITY_OFFSET4_BEACON_SSID_MASK 0x0003f000 +#define RX_PRIORITY_OFFSET4_BEACON_SSID_GET(x) (((x) & RX_PRIORITY_OFFSET4_BEACON_SSID_MASK) >> RX_PRIORITY_OFFSET4_BEACON_SSID_LSB) +#define RX_PRIORITY_OFFSET4_BEACON_SSID_SET(x) (((x) << RX_PRIORITY_OFFSET4_BEACON_SSID_LSB) & RX_PRIORITY_OFFSET4_BEACON_SSID_MASK) +#define RX_PRIORITY_OFFSET4_NULL_MSB 11 +#define RX_PRIORITY_OFFSET4_NULL_LSB 6 +#define RX_PRIORITY_OFFSET4_NULL_MASK 0x00000fc0 +#define RX_PRIORITY_OFFSET4_NULL_GET(x) (((x) & RX_PRIORITY_OFFSET4_NULL_MASK) >> RX_PRIORITY_OFFSET4_NULL_LSB) +#define RX_PRIORITY_OFFSET4_NULL_SET(x) (((x) << RX_PRIORITY_OFFSET4_NULL_LSB) & RX_PRIORITY_OFFSET4_NULL_MASK) +#define RX_PRIORITY_OFFSET4_PREQ_MSB 5 +#define RX_PRIORITY_OFFSET4_PREQ_LSB 0 +#define RX_PRIORITY_OFFSET4_PREQ_MASK 0x0000003f +#define RX_PRIORITY_OFFSET4_PREQ_GET(x) (((x) & RX_PRIORITY_OFFSET4_PREQ_MASK) >> RX_PRIORITY_OFFSET4_PREQ_LSB) +#define RX_PRIORITY_OFFSET4_PREQ_SET(x) (((x) << RX_PRIORITY_OFFSET4_PREQ_LSB) & RX_PRIORITY_OFFSET4_PREQ_MASK) + +#define RX_PRIORITY_OFFSET5_ADDRESS 0x00008398 +#define RX_PRIORITY_OFFSET5_OFFSET 0x00000398 +#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MSB 17 +#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB 12 +#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK 0x0003f000 +#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MSB 11 +#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB 6 +#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK 0x00000fc0 +#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MSB 5 +#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB 0 +#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK 0x0000003f +#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK) + +#define MAC_PCU_BSSID2_L32_ADDRESS 0x0000839c +#define MAC_PCU_BSSID2_L32_OFFSET 0x0000039c +#define MAC_PCU_BSSID2_L32_ADDR_MSB 31 +#define MAC_PCU_BSSID2_L32_ADDR_LSB 0 +#define MAC_PCU_BSSID2_L32_ADDR_MASK 0xffffffff +#define MAC_PCU_BSSID2_L32_ADDR_GET(x) (((x) & MAC_PCU_BSSID2_L32_ADDR_MASK) >> MAC_PCU_BSSID2_L32_ADDR_LSB) +#define MAC_PCU_BSSID2_L32_ADDR_SET(x) (((x) << MAC_PCU_BSSID2_L32_ADDR_LSB) & MAC_PCU_BSSID2_L32_ADDR_MASK) + +#define MAC_PCU_BSSID2_U16_ADDRESS 0x000083a0 +#define MAC_PCU_BSSID2_U16_OFFSET 0x000003a0 +#define MAC_PCU_BSSID2_U16_ENABLE_MSB 16 +#define MAC_PCU_BSSID2_U16_ENABLE_LSB 16 +#define MAC_PCU_BSSID2_U16_ENABLE_MASK 0x00010000 +#define MAC_PCU_BSSID2_U16_ENABLE_GET(x) (((x) & MAC_PCU_BSSID2_U16_ENABLE_MASK) >> MAC_PCU_BSSID2_U16_ENABLE_LSB) +#define MAC_PCU_BSSID2_U16_ENABLE_SET(x) (((x) << MAC_PCU_BSSID2_U16_ENABLE_LSB) & MAC_PCU_BSSID2_U16_ENABLE_MASK) +#define MAC_PCU_BSSID2_U16_ADDR_MSB 15 +#define MAC_PCU_BSSID2_U16_ADDR_LSB 0 +#define MAC_PCU_BSSID2_U16_ADDR_MASK 0x0000ffff +#define MAC_PCU_BSSID2_U16_ADDR_GET(x) (((x) & MAC_PCU_BSSID2_U16_ADDR_MASK) >> MAC_PCU_BSSID2_U16_ADDR_LSB) +#define MAC_PCU_BSSID2_U16_ADDR_SET(x) (((x) << MAC_PCU_BSSID2_U16_ADDR_LSB) & MAC_PCU_BSSID2_U16_ADDR_MASK) + +#define MAC_PCU_TSF1_STATUS_L32_ADDRESS 0x000083a4 +#define MAC_PCU_TSF1_STATUS_L32_OFFSET 0x000003a4 +#define MAC_PCU_TSF1_STATUS_L32_VALUE_MSB 31 +#define MAC_PCU_TSF1_STATUS_L32_VALUE_LSB 0 +#define MAC_PCU_TSF1_STATUS_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF1_STATUS_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF1_STATUS_L32_VALUE_MASK) >> MAC_PCU_TSF1_STATUS_L32_VALUE_LSB) +#define MAC_PCU_TSF1_STATUS_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF1_STATUS_L32_VALUE_LSB) & MAC_PCU_TSF1_STATUS_L32_VALUE_MASK) + +#define MAC_PCU_TSF1_STATUS_U32_ADDRESS 0x000083a8 +#define MAC_PCU_TSF1_STATUS_U32_OFFSET 0x000003a8 +#define MAC_PCU_TSF1_STATUS_U32_VALUE_MSB 31 +#define MAC_PCU_TSF1_STATUS_U32_VALUE_LSB 0 +#define MAC_PCU_TSF1_STATUS_U32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF1_STATUS_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF1_STATUS_U32_VALUE_MASK) >> MAC_PCU_TSF1_STATUS_U32_VALUE_LSB) +#define MAC_PCU_TSF1_STATUS_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF1_STATUS_U32_VALUE_LSB) & MAC_PCU_TSF1_STATUS_U32_VALUE_MASK) + +#define MAC_PCU_TSF2_STATUS_L32_ADDRESS 0x000083ac +#define MAC_PCU_TSF2_STATUS_L32_OFFSET 0x000003ac +#define MAC_PCU_TSF2_STATUS_L32_VALUE_MSB 31 +#define MAC_PCU_TSF2_STATUS_L32_VALUE_LSB 0 +#define MAC_PCU_TSF2_STATUS_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF2_STATUS_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_STATUS_L32_VALUE_MASK) >> MAC_PCU_TSF2_STATUS_L32_VALUE_LSB) +#define MAC_PCU_TSF2_STATUS_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_STATUS_L32_VALUE_LSB) & MAC_PCU_TSF2_STATUS_L32_VALUE_MASK) + +#define MAC_PCU_TSF2_STATUS_U32_ADDRESS 0x000083b0 +#define MAC_PCU_TSF2_STATUS_U32_OFFSET 0x000003b0 +#define MAC_PCU_TSF2_STATUS_U32_VALUE_MSB 31 +#define MAC_PCU_TSF2_STATUS_U32_VALUE_LSB 0 +#define MAC_PCU_TSF2_STATUS_U32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF2_STATUS_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_STATUS_U32_VALUE_MASK) >> MAC_PCU_TSF2_STATUS_U32_VALUE_LSB) +#define MAC_PCU_TSF2_STATUS_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_STATUS_U32_VALUE_LSB) & MAC_PCU_TSF2_STATUS_U32_VALUE_MASK) + +#define MAC_PCU_TXBUF_BA_ADDRESS 0x00008400 +#define MAC_PCU_TXBUF_BA_OFFSET 0x00000400 +#define MAC_PCU_TXBUF_BA_DATA_MSB 31 +#define MAC_PCU_TXBUF_BA_DATA_LSB 0 +#define MAC_PCU_TXBUF_BA_DATA_MASK 0xffffffff +#define MAC_PCU_TXBUF_BA_DATA_GET(x) (((x) & MAC_PCU_TXBUF_BA_DATA_MASK) >> MAC_PCU_TXBUF_BA_DATA_LSB) +#define MAC_PCU_TXBUF_BA_DATA_SET(x) (((x) << MAC_PCU_TXBUF_BA_DATA_LSB) & MAC_PCU_TXBUF_BA_DATA_MASK) + +#define MAC_PCU_KEY_CACHE_1_ADDRESS 0x00008800 +#define MAC_PCU_KEY_CACHE_1_OFFSET 0x00000800 +#define MAC_PCU_KEY_CACHE_1_DATA_MSB 31 +#define MAC_PCU_KEY_CACHE_1_DATA_LSB 0 +#define MAC_PCU_KEY_CACHE_1_DATA_MASK 0xffffffff +#define MAC_PCU_KEY_CACHE_1_DATA_GET(x) (((x) & MAC_PCU_KEY_CACHE_1_DATA_MASK) >> MAC_PCU_KEY_CACHE_1_DATA_LSB) +#define MAC_PCU_KEY_CACHE_1_DATA_SET(x) (((x) << MAC_PCU_KEY_CACHE_1_DATA_LSB) & MAC_PCU_KEY_CACHE_1_DATA_MASK) + +#define MAC_PCU_BASEBAND_0_ADDRESS 0x00009800 +#define MAC_PCU_BASEBAND_0_OFFSET 0x00001800 +#define MAC_PCU_BASEBAND_0_DATA_MSB 31 +#define MAC_PCU_BASEBAND_0_DATA_LSB 0 +#define MAC_PCU_BASEBAND_0_DATA_MASK 0xffffffff +#define MAC_PCU_BASEBAND_0_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_0_DATA_MASK) >> MAC_PCU_BASEBAND_0_DATA_LSB) +#define MAC_PCU_BASEBAND_0_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_0_DATA_LSB) & MAC_PCU_BASEBAND_0_DATA_MASK) + +#define MAC_PCU_BASEBAND_1_ADDRESS 0x0000a000 +#define MAC_PCU_BASEBAND_1_OFFSET 0x00002000 +#define MAC_PCU_BASEBAND_1_DATA_MSB 31 +#define MAC_PCU_BASEBAND_1_DATA_LSB 0 +#define MAC_PCU_BASEBAND_1_DATA_MASK 0xffffffff +#define MAC_PCU_BASEBAND_1_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_1_DATA_MASK) >> MAC_PCU_BASEBAND_1_DATA_LSB) +#define MAC_PCU_BASEBAND_1_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_1_DATA_LSB) & MAC_PCU_BASEBAND_1_DATA_MASK) + +#define MAC_PCU_BASEBAND_2_ADDRESS 0x0000c000 +#define MAC_PCU_BASEBAND_2_OFFSET 0x00004000 +#define MAC_PCU_BASEBAND_2_DATA_MSB 31 +#define MAC_PCU_BASEBAND_2_DATA_LSB 0 +#define MAC_PCU_BASEBAND_2_DATA_MASK 0xffffffff +#define MAC_PCU_BASEBAND_2_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_2_DATA_MASK) >> MAC_PCU_BASEBAND_2_DATA_LSB) +#define MAC_PCU_BASEBAND_2_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_2_DATA_LSB) & MAC_PCU_BASEBAND_2_DATA_MASK) + +#define MAC_PCU_BASEBAND_3_ADDRESS 0x0000d000 +#define MAC_PCU_BASEBAND_3_OFFSET 0x00005000 +#define MAC_PCU_BASEBAND_3_DATA_MSB 31 +#define MAC_PCU_BASEBAND_3_DATA_LSB 0 +#define MAC_PCU_BASEBAND_3_DATA_MASK 0xffffffff +#define MAC_PCU_BASEBAND_3_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_3_DATA_MASK) >> MAC_PCU_BASEBAND_3_DATA_LSB) +#define MAC_PCU_BASEBAND_3_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_3_DATA_LSB) & MAC_PCU_BASEBAND_3_DATA_MASK) + +#define MAC_PCU_BUF_ADDRESS 0x0000e000 +#define MAC_PCU_BUF_OFFSET 0x00006000 +#define MAC_PCU_BUF_DATA_MSB 31 +#define MAC_PCU_BUF_DATA_LSB 0 +#define MAC_PCU_BUF_DATA_MASK 0xffffffff +#define MAC_PCU_BUF_DATA_GET(x) (((x) & MAC_PCU_BUF_DATA_MASK) >> MAC_PCU_BUF_DATA_LSB) +#define MAC_PCU_BUF_DATA_SET(x) (((x) << MAC_PCU_BUF_DATA_LSB) & MAC_PCU_BUF_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mac_pcu_reg_s { + volatile unsigned int mac_pcu_sta_addr_l32; + volatile unsigned int mac_pcu_sta_addr_u16; + volatile unsigned int mac_pcu_bssid_l32; + volatile unsigned int mac_pcu_bssid_u16; + volatile unsigned int mac_pcu_bcn_rssi_ave; + volatile unsigned int mac_pcu_ack_cts_timeout; + volatile unsigned int mac_pcu_bcn_rssi_ctl; + volatile unsigned int mac_pcu_usec_latency; + volatile unsigned int pcu_max_cfp_dur; + volatile unsigned int mac_pcu_rx_filter; + volatile unsigned int mac_pcu_mcast_filter_l32; + volatile unsigned int mac_pcu_mcast_filter_u32; + volatile unsigned int mac_pcu_diag_sw; + volatile unsigned int mac_pcu_tst_addac; + volatile unsigned int mac_pcu_def_antenna; + volatile unsigned int mac_pcu_aes_mute_mask_0; + volatile unsigned int mac_pcu_aes_mute_mask_1; + volatile unsigned int mac_pcu_gated_clks; + volatile unsigned int mac_pcu_obs_bus_2; + volatile unsigned int mac_pcu_obs_bus_1; + volatile unsigned int mac_pcu_dym_mimo_pwr_save; + volatile unsigned int mac_pcu_last_beacon_tsf; + volatile unsigned int mac_pcu_nav; + volatile unsigned int mac_pcu_rts_success_cnt; + volatile unsigned int mac_pcu_rts_fail_cnt; + volatile unsigned int mac_pcu_ack_fail_cnt; + volatile unsigned int mac_pcu_fcs_fail_cnt; + volatile unsigned int mac_pcu_beacon_cnt; + volatile unsigned int mac_pcu_xrmode; + volatile unsigned int mac_pcu_xrdel; + volatile unsigned int mac_pcu_xrto; + volatile unsigned int mac_pcu_xrcrp; + volatile unsigned int mac_pcu_xrstmp; + volatile unsigned int mac_pcu_addr1_mask_l32; + volatile unsigned int mac_pcu_addr1_mask_u16; + volatile unsigned int mac_pcu_tpc; + volatile unsigned int mac_pcu_tx_frame_cnt; + volatile unsigned int mac_pcu_rx_frame_cnt; + volatile unsigned int mac_pcu_rx_clear_cnt; + volatile unsigned int mac_pcu_cycle_cnt; + volatile unsigned int mac_pcu_quiet_time_1; + volatile unsigned int mac_pcu_quiet_time_2; + volatile unsigned int mac_pcu_qos_no_ack; + volatile unsigned int mac_pcu_phy_error_mask; + volatile unsigned int mac_pcu_xrlat; + volatile unsigned int mac_pcu_rxbuf; + volatile unsigned int mac_pcu_mic_qos_control; + volatile unsigned int mac_pcu_mic_qos_select; + volatile unsigned int mac_pcu_misc_mode; + volatile unsigned int mac_pcu_filter_ofdm_cnt; + volatile unsigned int mac_pcu_filter_cck_cnt; + volatile unsigned int mac_pcu_phy_err_cnt_1; + volatile unsigned int mac_pcu_phy_err_cnt_1_mask; + volatile unsigned int mac_pcu_phy_err_cnt_2; + volatile unsigned int mac_pcu_phy_err_cnt_2_mask; + volatile unsigned int mac_pcu_tsf_threshold; + volatile unsigned int mac_pcu_phy_error_eifs_mask; + volatile unsigned int mac_pcu_phy_err_cnt_3; + volatile unsigned int mac_pcu_phy_err_cnt_3_mask; + volatile unsigned int mac_pcu_bluetooth_mode; + volatile unsigned int mac_pcu_bluetooth_weights; + volatile unsigned int mac_pcu_bluetooth_mode2; + volatile unsigned int mac_pcu_txsifs; + volatile unsigned int mac_pcu_txop_x; + volatile unsigned int mac_pcu_txop_0_3; + volatile unsigned int mac_pcu_txop_4_7; + volatile unsigned int mac_pcu_txop_8_11; + volatile unsigned int mac_pcu_txop_12_15; + volatile unsigned int mac_pcu_logic_analyzer; + volatile unsigned int mac_pcu_logic_analyzer_32l; + volatile unsigned int mac_pcu_logic_analyzer_16u; + volatile unsigned int mac_pcu_phy_err_cnt_mask_cont; + volatile unsigned int mac_pcu_azimuth_mode; + volatile unsigned int mac_pcu_20_40_mode; + volatile unsigned int mac_pcu_rx_clear_diff_cnt; + volatile unsigned int mac_pcu_self_gen_antenna_mask; + volatile unsigned int mac_pcu_ba_bar_control; + volatile unsigned int mac_pcu_legacy_plcp_spoof; + volatile unsigned int mac_pcu_phy_error_mask_cont; + volatile unsigned int mac_pcu_tx_timer; + volatile unsigned int mac_pcu_txbuf_ctrl; + volatile unsigned int mac_pcu_misc_mode2; + volatile unsigned int mac_pcu_alt_aes_mute_mask; + volatile unsigned int mac_pcu_azimuth_time_stamp; + volatile unsigned int mac_pcu_max_cfp_dur; + volatile unsigned int mac_pcu_hcf_timeout; + volatile unsigned int mac_pcu_bluetooth_weights2; + volatile unsigned int mac_pcu_bluetooth_tsf_bt_active; + volatile unsigned int mac_pcu_bluetooth_tsf_bt_priority; + volatile unsigned int mac_pcu_bluetooth_mode3; + volatile unsigned int mac_pcu_bluetooth_mode4; + unsigned char pad0[148]; /* pad to 0x200 */ + volatile unsigned int mac_pcu_bt_bt[64]; + volatile unsigned int mac_pcu_bt_bt_async; + volatile unsigned int mac_pcu_bt_wl_1; + volatile unsigned int mac_pcu_bt_wl_2; + volatile unsigned int mac_pcu_bt_wl_3; + volatile unsigned int mac_pcu_bt_wl_4; + volatile unsigned int mac_pcu_coex_epta; + volatile unsigned int mac_pcu_coex_lnamaxgain1; + volatile unsigned int mac_pcu_coex_lnamaxgain2; + volatile unsigned int mac_pcu_coex_lnamaxgain3; + volatile unsigned int mac_pcu_coex_lnamaxgain4; + volatile unsigned int mac_pcu_basic_rate_set0; + volatile unsigned int mac_pcu_basic_rate_set1; + volatile unsigned int mac_pcu_basic_rate_set2; + volatile unsigned int mac_pcu_basic_rate_set3; + volatile unsigned int mac_pcu_rx_int_status0; + volatile unsigned int mac_pcu_rx_int_status1; + volatile unsigned int mac_pcu_rx_int_status2; + volatile unsigned int mac_pcu_rx_int_status3; + volatile unsigned int ht_half_gi_rate1; + volatile unsigned int ht_half_gi_rate2; + volatile unsigned int ht_full_gi_rate1; + volatile unsigned int ht_full_gi_rate2; + volatile unsigned int legacy_rate1; + volatile unsigned int legacy_rate2; + volatile unsigned int legacy_rate3; + volatile unsigned int rx_int_filter; + volatile unsigned int rx_int_overflow; + volatile unsigned int rx_filter_thresh; + volatile unsigned int rx_filter_thresh1; + volatile unsigned int rx_priority_thresh0; + volatile unsigned int rx_priority_thresh1; + volatile unsigned int rx_priority_thresh2; + volatile unsigned int rx_priority_thresh3; + volatile unsigned int rx_priority_offset0; + volatile unsigned int rx_priority_offset1; + volatile unsigned int rx_priority_offset2; + volatile unsigned int rx_priority_offset3; + volatile unsigned int rx_priority_offset4; + volatile unsigned int rx_priority_offset5; + volatile unsigned int mac_pcu_bssid2_l32; + volatile unsigned int mac_pcu_bssid2_u16; + volatile unsigned int mac_pcu_tsf1_status_l32; + volatile unsigned int mac_pcu_tsf1_status_u32; + volatile unsigned int mac_pcu_tsf2_status_l32; + volatile unsigned int mac_pcu_tsf2_status_u32; + unsigned char pad1[76]; /* pad to 0x400 */ + volatile unsigned int mac_pcu_txbuf_ba[64]; + unsigned char pad2[768]; /* pad to 0x800 */ + volatile unsigned int mac_pcu_key_cache_1[256]; + unsigned char pad3[3072]; /* pad to 0x1800 */ + volatile unsigned int mac_pcu_baseband_0[512]; + volatile unsigned int mac_pcu_baseband_1[2048]; + volatile unsigned int mac_pcu_baseband_2[1024]; + volatile unsigned int mac_pcu_baseband_3[1024]; + volatile unsigned int mac_pcu_buf[512]; +} mac_pcu_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MAC_PCU_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_host_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_host_reg.h new file mode 100644 index 000000000000..3af562156f6e --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_host_reg.h @@ -0,0 +1,37 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "mbox_wlan_host_reg.h" + + +#ifndef BT_HEADERS + + + +#endif +#endif + + + diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_reg.h new file mode 100644 index 000000000000..cc67585e2e8b --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_reg.h @@ -0,0 +1,560 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "mbox_wlan_reg.h" + + +#ifndef BT_HEADERS + +#define MBOX_FIFO_ADDRESS WLAN_MBOX_FIFO_ADDRESS +#define MBOX_FIFO_OFFSET WLAN_MBOX_FIFO_OFFSET +#define MBOX_FIFO_DATA_MSB WLAN_MBOX_FIFO_DATA_MSB +#define MBOX_FIFO_DATA_LSB WLAN_MBOX_FIFO_DATA_LSB +#define MBOX_FIFO_DATA_MASK WLAN_MBOX_FIFO_DATA_MASK +#define MBOX_FIFO_DATA_GET(x) WLAN_MBOX_FIFO_DATA_GET(x) +#define MBOX_FIFO_DATA_SET(x) WLAN_MBOX_FIFO_DATA_SET(x) +#define MBOX_FIFO_STATUS_ADDRESS WLAN_MBOX_FIFO_STATUS_ADDRESS +#define MBOX_FIFO_STATUS_OFFSET WLAN_MBOX_FIFO_STATUS_OFFSET +#define MBOX_FIFO_STATUS_EMPTY_MSB WLAN_MBOX_FIFO_STATUS_EMPTY_MSB +#define MBOX_FIFO_STATUS_EMPTY_LSB WLAN_MBOX_FIFO_STATUS_EMPTY_LSB +#define MBOX_FIFO_STATUS_EMPTY_MASK WLAN_MBOX_FIFO_STATUS_EMPTY_MASK +#define MBOX_FIFO_STATUS_EMPTY_GET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x) +#define MBOX_FIFO_STATUS_EMPTY_SET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x) +#define MBOX_FIFO_STATUS_FULL_MSB WLAN_MBOX_FIFO_STATUS_FULL_MSB +#define MBOX_FIFO_STATUS_FULL_LSB WLAN_MBOX_FIFO_STATUS_FULL_LSB +#define MBOX_FIFO_STATUS_FULL_MASK WLAN_MBOX_FIFO_STATUS_FULL_MASK +#define MBOX_FIFO_STATUS_FULL_GET(x) WLAN_MBOX_FIFO_STATUS_FULL_GET(x) +#define MBOX_FIFO_STATUS_FULL_SET(x) WLAN_MBOX_FIFO_STATUS_FULL_SET(x) +#define MBOX_DMA_POLICY_ADDRESS WLAN_MBOX_DMA_POLICY_ADDRESS +#define MBOX_DMA_POLICY_OFFSET WLAN_MBOX_DMA_POLICY_OFFSET +#define MBOX_DMA_POLICY_TX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB +#define MBOX_DMA_POLICY_TX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB +#define MBOX_DMA_POLICY_TX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK +#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x) +#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x) +#define MBOX_DMA_POLICY_TX_ORDER_MSB WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB +#define MBOX_DMA_POLICY_TX_ORDER_LSB WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB +#define MBOX_DMA_POLICY_TX_ORDER_MASK WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK +#define MBOX_DMA_POLICY_TX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x) +#define MBOX_DMA_POLICY_TX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x) +#define MBOX_DMA_POLICY_RX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB +#define MBOX_DMA_POLICY_RX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB +#define MBOX_DMA_POLICY_RX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK +#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x) +#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x) +#define MBOX_DMA_POLICY_RX_ORDER_MSB WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB +#define MBOX_DMA_POLICY_RX_ORDER_LSB WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB +#define MBOX_DMA_POLICY_RX_ORDER_MASK WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK +#define MBOX_DMA_POLICY_RX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x) +#define MBOX_DMA_POLICY_RX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x) +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX0_DMA_RX_CONTROL_ADDRESS WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS +#define MBOX0_DMA_RX_CONTROL_OFFSET WLAN_MBOX0_DMA_RX_CONTROL_OFFSET +#define MBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB +#define MBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB +#define MBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK +#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x) +#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x) +#define MBOX0_DMA_RX_CONTROL_START_MSB WLAN_MBOX0_DMA_RX_CONTROL_START_MSB +#define MBOX0_DMA_RX_CONTROL_START_LSB WLAN_MBOX0_DMA_RX_CONTROL_START_LSB +#define MBOX0_DMA_RX_CONTROL_START_MASK WLAN_MBOX0_DMA_RX_CONTROL_START_MASK +#define MBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x) +#define MBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x) +#define MBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB +#define MBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB +#define MBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK +#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x) +#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x) +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX0_DMA_TX_CONTROL_ADDRESS WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS +#define MBOX0_DMA_TX_CONTROL_OFFSET WLAN_MBOX0_DMA_TX_CONTROL_OFFSET +#define MBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB +#define MBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB +#define MBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK +#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x) +#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x) +#define MBOX0_DMA_TX_CONTROL_START_MSB WLAN_MBOX0_DMA_TX_CONTROL_START_MSB +#define MBOX0_DMA_TX_CONTROL_START_LSB WLAN_MBOX0_DMA_TX_CONTROL_START_LSB +#define MBOX0_DMA_TX_CONTROL_START_MASK WLAN_MBOX0_DMA_TX_CONTROL_START_MASK +#define MBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x) +#define MBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x) +#define MBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB +#define MBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB +#define MBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK +#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x) +#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x) +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX1_DMA_RX_CONTROL_ADDRESS WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS +#define MBOX1_DMA_RX_CONTROL_OFFSET WLAN_MBOX1_DMA_RX_CONTROL_OFFSET +#define MBOX1_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB +#define MBOX1_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB +#define MBOX1_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK +#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x) +#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x) +#define MBOX1_DMA_RX_CONTROL_START_MSB WLAN_MBOX1_DMA_RX_CONTROL_START_MSB +#define MBOX1_DMA_RX_CONTROL_START_LSB WLAN_MBOX1_DMA_RX_CONTROL_START_LSB +#define MBOX1_DMA_RX_CONTROL_START_MASK WLAN_MBOX1_DMA_RX_CONTROL_START_MASK +#define MBOX1_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x) +#define MBOX1_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x) +#define MBOX1_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB +#define MBOX1_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB +#define MBOX1_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK +#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x) +#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x) +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX1_DMA_TX_CONTROL_ADDRESS WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS +#define MBOX1_DMA_TX_CONTROL_OFFSET WLAN_MBOX1_DMA_TX_CONTROL_OFFSET +#define MBOX1_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB +#define MBOX1_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB +#define MBOX1_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK +#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x) +#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x) +#define MBOX1_DMA_TX_CONTROL_START_MSB WLAN_MBOX1_DMA_TX_CONTROL_START_MSB +#define MBOX1_DMA_TX_CONTROL_START_LSB WLAN_MBOX1_DMA_TX_CONTROL_START_LSB +#define MBOX1_DMA_TX_CONTROL_START_MASK WLAN_MBOX1_DMA_TX_CONTROL_START_MASK +#define MBOX1_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x) +#define MBOX1_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x) +#define MBOX1_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB +#define MBOX1_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB +#define MBOX1_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK +#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x) +#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x) +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX2_DMA_RX_CONTROL_ADDRESS WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS +#define MBOX2_DMA_RX_CONTROL_OFFSET WLAN_MBOX2_DMA_RX_CONTROL_OFFSET +#define MBOX2_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB +#define MBOX2_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB +#define MBOX2_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK +#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x) +#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x) +#define MBOX2_DMA_RX_CONTROL_START_MSB WLAN_MBOX2_DMA_RX_CONTROL_START_MSB +#define MBOX2_DMA_RX_CONTROL_START_LSB WLAN_MBOX2_DMA_RX_CONTROL_START_LSB +#define MBOX2_DMA_RX_CONTROL_START_MASK WLAN_MBOX2_DMA_RX_CONTROL_START_MASK +#define MBOX2_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x) +#define MBOX2_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x) +#define MBOX2_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB +#define MBOX2_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB +#define MBOX2_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK +#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x) +#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x) +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX2_DMA_TX_CONTROL_ADDRESS WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS +#define MBOX2_DMA_TX_CONTROL_OFFSET WLAN_MBOX2_DMA_TX_CONTROL_OFFSET +#define MBOX2_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB +#define MBOX2_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB +#define MBOX2_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK +#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x) +#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x) +#define MBOX2_DMA_TX_CONTROL_START_MSB WLAN_MBOX2_DMA_TX_CONTROL_START_MSB +#define MBOX2_DMA_TX_CONTROL_START_LSB WLAN_MBOX2_DMA_TX_CONTROL_START_LSB +#define MBOX2_DMA_TX_CONTROL_START_MASK WLAN_MBOX2_DMA_TX_CONTROL_START_MASK +#define MBOX2_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x) +#define MBOX2_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x) +#define MBOX2_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB +#define MBOX2_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB +#define MBOX2_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK +#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x) +#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x) +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX3_DMA_RX_CONTROL_ADDRESS WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS +#define MBOX3_DMA_RX_CONTROL_OFFSET WLAN_MBOX3_DMA_RX_CONTROL_OFFSET +#define MBOX3_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB +#define MBOX3_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB +#define MBOX3_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK +#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x) +#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x) +#define MBOX3_DMA_RX_CONTROL_START_MSB WLAN_MBOX3_DMA_RX_CONTROL_START_MSB +#define MBOX3_DMA_RX_CONTROL_START_LSB WLAN_MBOX3_DMA_RX_CONTROL_START_LSB +#define MBOX3_DMA_RX_CONTROL_START_MASK WLAN_MBOX3_DMA_RX_CONTROL_START_MASK +#define MBOX3_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x) +#define MBOX3_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x) +#define MBOX3_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB +#define MBOX3_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB +#define MBOX3_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK +#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x) +#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x) +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX3_DMA_TX_CONTROL_ADDRESS WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS +#define MBOX3_DMA_TX_CONTROL_OFFSET WLAN_MBOX3_DMA_TX_CONTROL_OFFSET +#define MBOX3_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB +#define MBOX3_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB +#define MBOX3_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK +#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x) +#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x) +#define MBOX3_DMA_TX_CONTROL_START_MSB WLAN_MBOX3_DMA_TX_CONTROL_START_MSB +#define MBOX3_DMA_TX_CONTROL_START_LSB WLAN_MBOX3_DMA_TX_CONTROL_START_LSB +#define MBOX3_DMA_TX_CONTROL_START_MASK WLAN_MBOX3_DMA_TX_CONTROL_START_MASK +#define MBOX3_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x) +#define MBOX3_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x) +#define MBOX3_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB +#define MBOX3_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB +#define MBOX3_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK +#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x) +#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x) +#define MBOX_INT_STATUS_ADDRESS WLAN_MBOX_INT_STATUS_ADDRESS +#define MBOX_INT_STATUS_OFFSET WLAN_MBOX_INT_STATUS_OFFSET +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) +#define MBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB +#define MBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB +#define MBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK +#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x) +#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x) +#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB +#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB +#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK +#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) +#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB +#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK +#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) +#define MBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB +#define MBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB +#define MBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK +#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x) +#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x) +#define MBOX_INT_STATUS_HOST_MSB WLAN_MBOX_INT_STATUS_HOST_MSB +#define MBOX_INT_STATUS_HOST_LSB WLAN_MBOX_INT_STATUS_HOST_LSB +#define MBOX_INT_STATUS_HOST_MASK WLAN_MBOX_INT_STATUS_HOST_MASK +#define MBOX_INT_STATUS_HOST_GET(x) WLAN_MBOX_INT_STATUS_HOST_GET(x) +#define MBOX_INT_STATUS_HOST_SET(x) WLAN_MBOX_INT_STATUS_HOST_SET(x) +#define MBOX_INT_ENABLE_ADDRESS WLAN_MBOX_INT_ENABLE_ADDRESS +#define MBOX_INT_ENABLE_OFFSET WLAN_MBOX_INT_ENABLE_OFFSET +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) +#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB +#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB +#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK +#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) +#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB +#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK +#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) +#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB +#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB +#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK +#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) +#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) +#define MBOX_INT_ENABLE_HOST_MSB WLAN_MBOX_INT_ENABLE_HOST_MSB +#define MBOX_INT_ENABLE_HOST_LSB WLAN_MBOX_INT_ENABLE_HOST_LSB +#define MBOX_INT_ENABLE_HOST_MASK WLAN_MBOX_INT_ENABLE_HOST_MASK +#define MBOX_INT_ENABLE_HOST_GET(x) WLAN_MBOX_INT_ENABLE_HOST_GET(x) +#define MBOX_INT_ENABLE_HOST_SET(x) WLAN_MBOX_INT_ENABLE_HOST_SET(x) +#define INT_HOST_ADDRESS WLAN_INT_HOST_ADDRESS +#define INT_HOST_OFFSET WLAN_INT_HOST_OFFSET +#define INT_HOST_VECTOR_MSB WLAN_INT_HOST_VECTOR_MSB +#define INT_HOST_VECTOR_LSB WLAN_INT_HOST_VECTOR_LSB +#define INT_HOST_VECTOR_MASK WLAN_INT_HOST_VECTOR_MASK +#define INT_HOST_VECTOR_GET(x) WLAN_INT_HOST_VECTOR_GET(x) +#define INT_HOST_VECTOR_SET(x) WLAN_INT_HOST_VECTOR_SET(x) +#define LOCAL_COUNT_ADDRESS WLAN_LOCAL_COUNT_ADDRESS +#define LOCAL_COUNT_OFFSET WLAN_LOCAL_COUNT_OFFSET +#define LOCAL_COUNT_VALUE_MSB WLAN_LOCAL_COUNT_VALUE_MSB +#define LOCAL_COUNT_VALUE_LSB WLAN_LOCAL_COUNT_VALUE_LSB +#define LOCAL_COUNT_VALUE_MASK WLAN_LOCAL_COUNT_VALUE_MASK +#define LOCAL_COUNT_VALUE_GET(x) WLAN_LOCAL_COUNT_VALUE_GET(x) +#define LOCAL_COUNT_VALUE_SET(x) WLAN_LOCAL_COUNT_VALUE_SET(x) +#define COUNT_INC_ADDRESS WLAN_COUNT_INC_ADDRESS +#define COUNT_INC_OFFSET WLAN_COUNT_INC_OFFSET +#define COUNT_INC_VALUE_MSB WLAN_COUNT_INC_VALUE_MSB +#define COUNT_INC_VALUE_LSB WLAN_COUNT_INC_VALUE_LSB +#define COUNT_INC_VALUE_MASK WLAN_COUNT_INC_VALUE_MASK +#define COUNT_INC_VALUE_GET(x) WLAN_COUNT_INC_VALUE_GET(x) +#define COUNT_INC_VALUE_SET(x) WLAN_COUNT_INC_VALUE_SET(x) +#define LOCAL_SCRATCH_ADDRESS WLAN_LOCAL_SCRATCH_ADDRESS +#define LOCAL_SCRATCH_OFFSET WLAN_LOCAL_SCRATCH_OFFSET +#define LOCAL_SCRATCH_VALUE_MSB WLAN_LOCAL_SCRATCH_VALUE_MSB +#define LOCAL_SCRATCH_VALUE_LSB WLAN_LOCAL_SCRATCH_VALUE_LSB +#define LOCAL_SCRATCH_VALUE_MASK WLAN_LOCAL_SCRATCH_VALUE_MASK +#define LOCAL_SCRATCH_VALUE_GET(x) WLAN_LOCAL_SCRATCH_VALUE_GET(x) +#define LOCAL_SCRATCH_VALUE_SET(x) WLAN_LOCAL_SCRATCH_VALUE_SET(x) +#define USE_LOCAL_BUS_ADDRESS WLAN_USE_LOCAL_BUS_ADDRESS +#define USE_LOCAL_BUS_OFFSET WLAN_USE_LOCAL_BUS_OFFSET +#define USE_LOCAL_BUS_PIN_INIT_MSB WLAN_USE_LOCAL_BUS_PIN_INIT_MSB +#define USE_LOCAL_BUS_PIN_INIT_LSB WLAN_USE_LOCAL_BUS_PIN_INIT_LSB +#define USE_LOCAL_BUS_PIN_INIT_MASK WLAN_USE_LOCAL_BUS_PIN_INIT_MASK +#define USE_LOCAL_BUS_PIN_INIT_GET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x) +#define USE_LOCAL_BUS_PIN_INIT_SET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x) +#define SDIO_CONFIG_ADDRESS WLAN_SDIO_CONFIG_ADDRESS +#define SDIO_CONFIG_OFFSET WLAN_SDIO_CONFIG_OFFSET +#define SDIO_CONFIG_CCCR_IOR1_MSB WLAN_SDIO_CONFIG_CCCR_IOR1_MSB +#define SDIO_CONFIG_CCCR_IOR1_LSB WLAN_SDIO_CONFIG_CCCR_IOR1_LSB +#define SDIO_CONFIG_CCCR_IOR1_MASK WLAN_SDIO_CONFIG_CCCR_IOR1_MASK +#define SDIO_CONFIG_CCCR_IOR1_GET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x) +#define SDIO_CONFIG_CCCR_IOR1_SET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x) +#define MBOX_DEBUG_ADDRESS WLAN_MBOX_DEBUG_ADDRESS +#define MBOX_DEBUG_OFFSET WLAN_MBOX_DEBUG_OFFSET +#define MBOX_DEBUG_SEL_MSB WLAN_MBOX_DEBUG_SEL_MSB +#define MBOX_DEBUG_SEL_LSB WLAN_MBOX_DEBUG_SEL_LSB +#define MBOX_DEBUG_SEL_MASK WLAN_MBOX_DEBUG_SEL_MASK +#define MBOX_DEBUG_SEL_GET(x) WLAN_MBOX_DEBUG_SEL_GET(x) +#define MBOX_DEBUG_SEL_SET(x) WLAN_MBOX_DEBUG_SEL_SET(x) +#define MBOX_FIFO_RESET_ADDRESS WLAN_MBOX_FIFO_RESET_ADDRESS +#define MBOX_FIFO_RESET_OFFSET WLAN_MBOX_FIFO_RESET_OFFSET +#define MBOX_FIFO_RESET_INIT_MSB WLAN_MBOX_FIFO_RESET_INIT_MSB +#define MBOX_FIFO_RESET_INIT_LSB WLAN_MBOX_FIFO_RESET_INIT_LSB +#define MBOX_FIFO_RESET_INIT_MASK WLAN_MBOX_FIFO_RESET_INIT_MASK +#define MBOX_FIFO_RESET_INIT_GET(x) WLAN_MBOX_FIFO_RESET_INIT_GET(x) +#define MBOX_FIFO_RESET_INIT_SET(x) WLAN_MBOX_FIFO_RESET_INIT_SET(x) +#define MBOX_TXFIFO_POP_ADDRESS WLAN_MBOX_TXFIFO_POP_ADDRESS +#define MBOX_TXFIFO_POP_OFFSET WLAN_MBOX_TXFIFO_POP_OFFSET +#define MBOX_TXFIFO_POP_DATA_MSB WLAN_MBOX_TXFIFO_POP_DATA_MSB +#define MBOX_TXFIFO_POP_DATA_LSB WLAN_MBOX_TXFIFO_POP_DATA_LSB +#define MBOX_TXFIFO_POP_DATA_MASK WLAN_MBOX_TXFIFO_POP_DATA_MASK +#define MBOX_TXFIFO_POP_DATA_GET(x) WLAN_MBOX_TXFIFO_POP_DATA_GET(x) +#define MBOX_TXFIFO_POP_DATA_SET(x) WLAN_MBOX_TXFIFO_POP_DATA_SET(x) +#define MBOX_RXFIFO_POP_ADDRESS WLAN_MBOX_RXFIFO_POP_ADDRESS +#define MBOX_RXFIFO_POP_OFFSET WLAN_MBOX_RXFIFO_POP_OFFSET +#define MBOX_RXFIFO_POP_DATA_MSB WLAN_MBOX_RXFIFO_POP_DATA_MSB +#define MBOX_RXFIFO_POP_DATA_LSB WLAN_MBOX_RXFIFO_POP_DATA_LSB +#define MBOX_RXFIFO_POP_DATA_MASK WLAN_MBOX_RXFIFO_POP_DATA_MASK +#define MBOX_RXFIFO_POP_DATA_GET(x) WLAN_MBOX_RXFIFO_POP_DATA_GET(x) +#define MBOX_RXFIFO_POP_DATA_SET(x) WLAN_MBOX_RXFIFO_POP_DATA_SET(x) +#define SDIO_DEBUG_ADDRESS WLAN_SDIO_DEBUG_ADDRESS +#define SDIO_DEBUG_OFFSET WLAN_SDIO_DEBUG_OFFSET +#define SDIO_DEBUG_SEL_MSB WLAN_SDIO_DEBUG_SEL_MSB +#define SDIO_DEBUG_SEL_LSB WLAN_SDIO_DEBUG_SEL_LSB +#define SDIO_DEBUG_SEL_MASK WLAN_SDIO_DEBUG_SEL_MASK +#define SDIO_DEBUG_SEL_GET(x) WLAN_SDIO_DEBUG_SEL_GET(x) +#define SDIO_DEBUG_SEL_SET(x) WLAN_SDIO_DEBUG_SEL_SET(x) +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define GMBOX0_DMA_RX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS +#define GMBOX0_DMA_RX_CONTROL_OFFSET WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET +#define GMBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB +#define GMBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB +#define GMBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK +#define GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) +#define GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) +#define GMBOX0_DMA_RX_CONTROL_START_MSB WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB +#define GMBOX0_DMA_RX_CONTROL_START_LSB WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB +#define GMBOX0_DMA_RX_CONTROL_START_MASK WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK +#define GMBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x) +#define GMBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x) +#define GMBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB +#define GMBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB +#define GMBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK +#define GMBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x) +#define GMBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x) +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define GMBOX0_DMA_TX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS +#define GMBOX0_DMA_TX_CONTROL_OFFSET WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET +#define GMBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB +#define GMBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB +#define GMBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK +#define GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) +#define GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) +#define GMBOX0_DMA_TX_CONTROL_START_MSB WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB +#define GMBOX0_DMA_TX_CONTROL_START_LSB WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB +#define GMBOX0_DMA_TX_CONTROL_START_MASK WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK +#define GMBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x) +#define GMBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x) +#define GMBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB +#define GMBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB +#define GMBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK +#define GMBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x) +#define GMBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x) +#define GMBOX_INT_STATUS_ADDRESS WLAN_GMBOX_INT_STATUS_ADDRESS +#define GMBOX_INT_STATUS_OFFSET WLAN_GMBOX_INT_STATUS_OFFSET +#define GMBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB +#define GMBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB +#define GMBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK +#define GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) +#define GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) +#define GMBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB +#define GMBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB +#define GMBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK +#define GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) +#define GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) +#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB +#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB +#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK +#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) +#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) +#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB +#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB +#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK +#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) +#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) +#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB +#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB +#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK +#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) +#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) +#define GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB +#define GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB +#define GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK +#define GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) +#define GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) +#define GMBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB +#define GMBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB +#define GMBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK +#define GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) +#define GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) +#define GMBOX_INT_ENABLE_ADDRESS WLAN_GMBOX_INT_ENABLE_ADDRESS +#define GMBOX_INT_ENABLE_OFFSET WLAN_GMBOX_INT_ENABLE_OFFSET +#define GMBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB +#define GMBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB +#define GMBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK +#define GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) +#define GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) +#define GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB +#define GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB +#define GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK +#define GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) +#define GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) +#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB +#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB +#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK +#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) +#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) +#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB +#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB +#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK +#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) +#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) +#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB +#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB +#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK +#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) +#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) +#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB +#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB +#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK +#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) +#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) +#define GMBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB +#define GMBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB +#define GMBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK +#define GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) +#define GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) +#define HOST_IF_WINDOW_ADDRESS WLAN_HOST_IF_WINDOW_ADDRESS +#define HOST_IF_WINDOW_OFFSET WLAN_HOST_IF_WINDOW_OFFSET +#define HOST_IF_WINDOW_DATA_MSB WLAN_HOST_IF_WINDOW_DATA_MSB +#define HOST_IF_WINDOW_DATA_LSB WLAN_HOST_IF_WINDOW_DATA_LSB +#define HOST_IF_WINDOW_DATA_MASK WLAN_HOST_IF_WINDOW_DATA_MASK +#define HOST_IF_WINDOW_DATA_GET(x) WLAN_HOST_IF_WINDOW_DATA_GET(x) +#define HOST_IF_WINDOW_DATA_SET(x) WLAN_HOST_IF_WINDOW_DATA_SET(x) + + +#endif +#endif + + + diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h new file mode 100644 index 000000000000..60855021c2b0 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h @@ -0,0 +1,522 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MBOX_WLAN_HOST_REG_REG_H_ +#define _MBOX_WLAN_HOST_REG_REG_H_ + +#define HOST_INT_STATUS_ADDRESS 0x00000400 +#define HOST_INT_STATUS_OFFSET 0x00000400 +#define HOST_INT_STATUS_ERROR_MSB 7 +#define HOST_INT_STATUS_ERROR_LSB 7 +#define HOST_INT_STATUS_ERROR_MASK 0x00000080 +#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) +#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK) +#define HOST_INT_STATUS_CPU_MSB 6 +#define HOST_INT_STATUS_CPU_LSB 6 +#define HOST_INT_STATUS_CPU_MASK 0x00000040 +#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) +#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK) +#define HOST_INT_STATUS_INT_MSB 5 +#define HOST_INT_STATUS_INT_LSB 5 +#define HOST_INT_STATUS_INT_MASK 0x00000020 +#define HOST_INT_STATUS_INT_GET(x) (((x) & HOST_INT_STATUS_INT_MASK) >> HOST_INT_STATUS_INT_LSB) +#define HOST_INT_STATUS_INT_SET(x) (((x) << HOST_INT_STATUS_INT_LSB) & HOST_INT_STATUS_INT_MASK) +#define HOST_INT_STATUS_COUNTER_MSB 4 +#define HOST_INT_STATUS_COUNTER_LSB 4 +#define HOST_INT_STATUS_COUNTER_MASK 0x00000010 +#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) +#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK) +#define HOST_INT_STATUS_MBOX_DATA_MSB 3 +#define HOST_INT_STATUS_MBOX_DATA_LSB 0 +#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f +#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB) +#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ADDRESS 0x00000401 +#define CPU_INT_STATUS_OFFSET 0x00000401 +#define CPU_INT_STATUS_BIT_MSB 7 +#define CPU_INT_STATUS_BIT_LSB 0 +#define CPU_INT_STATUS_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB) +#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK) + +#define ERROR_INT_STATUS_ADDRESS 0x00000402 +#define ERROR_INT_STATUS_OFFSET 0x00000402 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MSB 6 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB 6 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB) +#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK) +#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MSB 5 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB 5 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB) +#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK) +#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MSB 4 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB 4 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB) +#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK) +#define ERROR_INT_STATUS_SPI_MSB 3 +#define ERROR_INT_STATUS_SPI_LSB 3 +#define ERROR_INT_STATUS_SPI_MASK 0x00000008 +#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB) +#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK) +#define ERROR_INT_STATUS_WAKEUP_MSB 2 +#define ERROR_INT_STATUS_WAKEUP_LSB 2 +#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 +#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB) +#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK) +#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB) +#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) +#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB) +#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ADDRESS 0x00000403 +#define COUNTER_INT_STATUS_OFFSET 0x00000403 +#define COUNTER_INT_STATUS_COUNTER_MSB 7 +#define COUNTER_INT_STATUS_COUNTER_LSB 0 +#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff +#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB) +#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK) + +#define MBOX_FRAME_ADDRESS 0x00000404 +#define MBOX_FRAME_OFFSET 0x00000404 +#define MBOX_FRAME_RX_EOM_MSB 7 +#define MBOX_FRAME_RX_EOM_LSB 4 +#define MBOX_FRAME_RX_EOM_MASK 0x000000f0 +#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB) +#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK) +#define MBOX_FRAME_RX_SOM_MSB 3 +#define MBOX_FRAME_RX_SOM_LSB 0 +#define MBOX_FRAME_RX_SOM_MASK 0x0000000f +#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB) +#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK) + +#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 +#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405 +#define RX_LOOKAHEAD_VALID_MBOX_MSB 3 +#define RX_LOOKAHEAD_VALID_MBOX_LSB 0 +#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f +#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB) +#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK) + +#define HOST_INT_STATUS2_ADDRESS 0x00000406 +#define HOST_INT_STATUS2_OFFSET 0x00000406 +#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MSB 2 +#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB 2 +#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK 0x00000004 +#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB) +#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK) +#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MSB 1 +#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB 1 +#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK 0x00000002 +#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB) +#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK) +#define HOST_INT_STATUS2_GMBOX_DATA_MSB 0 +#define HOST_INT_STATUS2_GMBOX_DATA_LSB 0 +#define HOST_INT_STATUS2_GMBOX_DATA_MASK 0x00000001 +#define HOST_INT_STATUS2_GMBOX_DATA_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_DATA_MASK) >> HOST_INT_STATUS2_GMBOX_DATA_LSB) +#define HOST_INT_STATUS2_GMBOX_DATA_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_DATA_LSB) & HOST_INT_STATUS2_GMBOX_DATA_MASK) + +#define GMBOX_RX_AVAIL_ADDRESS 0x00000407 +#define GMBOX_RX_AVAIL_OFFSET 0x00000407 +#define GMBOX_RX_AVAIL_BYTE_MSB 6 +#define GMBOX_RX_AVAIL_BYTE_LSB 0 +#define GMBOX_RX_AVAIL_BYTE_MASK 0x0000007f +#define GMBOX_RX_AVAIL_BYTE_GET(x) (((x) & GMBOX_RX_AVAIL_BYTE_MASK) >> GMBOX_RX_AVAIL_BYTE_LSB) +#define GMBOX_RX_AVAIL_BYTE_SET(x) (((x) << GMBOX_RX_AVAIL_BYTE_LSB) & GMBOX_RX_AVAIL_BYTE_MASK) + +#define RX_LOOKAHEAD0_ADDRESS 0x00000408 +#define RX_LOOKAHEAD0_OFFSET 0x00000408 +#define RX_LOOKAHEAD0_DATA_MSB 7 +#define RX_LOOKAHEAD0_DATA_LSB 0 +#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB) +#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK) + +#define RX_LOOKAHEAD1_ADDRESS 0x0000040c +#define RX_LOOKAHEAD1_OFFSET 0x0000040c +#define RX_LOOKAHEAD1_DATA_MSB 7 +#define RX_LOOKAHEAD1_DATA_LSB 0 +#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB) +#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK) + +#define RX_LOOKAHEAD2_ADDRESS 0x00000410 +#define RX_LOOKAHEAD2_OFFSET 0x00000410 +#define RX_LOOKAHEAD2_DATA_MSB 7 +#define RX_LOOKAHEAD2_DATA_LSB 0 +#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB) +#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK) + +#define RX_LOOKAHEAD3_ADDRESS 0x00000414 +#define RX_LOOKAHEAD3_OFFSET 0x00000414 +#define RX_LOOKAHEAD3_DATA_MSB 7 +#define RX_LOOKAHEAD3_DATA_LSB 0 +#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB) +#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK) + +#define INT_STATUS_ENABLE_ADDRESS 0x00000418 +#define INT_STATUS_ENABLE_OFFSET 0x00000418 +#define INT_STATUS_ENABLE_ERROR_MSB 7 +#define INT_STATUS_ENABLE_ERROR_LSB 7 +#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080 +#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB) +#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) +#define INT_STATUS_ENABLE_CPU_MSB 6 +#define INT_STATUS_ENABLE_CPU_LSB 6 +#define INT_STATUS_ENABLE_CPU_MASK 0x00000040 +#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB) +#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) +#define INT_STATUS_ENABLE_INT_MSB 5 +#define INT_STATUS_ENABLE_INT_LSB 5 +#define INT_STATUS_ENABLE_INT_MASK 0x00000020 +#define INT_STATUS_ENABLE_INT_GET(x) (((x) & INT_STATUS_ENABLE_INT_MASK) >> INT_STATUS_ENABLE_INT_LSB) +#define INT_STATUS_ENABLE_INT_SET(x) (((x) << INT_STATUS_ENABLE_INT_LSB) & INT_STATUS_ENABLE_INT_MASK) +#define INT_STATUS_ENABLE_COUNTER_MSB 4 +#define INT_STATUS_ENABLE_COUNTER_LSB 4 +#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 +#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB) +#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK) +#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3 +#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0 +#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f +#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB) +#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 +#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419 +#define CPU_INT_STATUS_ENABLE_BIT_MSB 7 +#define CPU_INT_STATUS_ENABLE_BIT_LSB 0 +#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB) +#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK) + +#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a +#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MSB 6 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB 6 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB) +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK) +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MSB 5 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB 5 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB) +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK) +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MSB 4 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB 4 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB) +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK) +#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004 +#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB) +#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7 +#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 +#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB) +#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) + +#define COUNT_ADDRESS 0x00000420 +#define COUNT_OFFSET 0x00000420 +#define COUNT_VALUE_MSB 7 +#define COUNT_VALUE_LSB 0 +#define COUNT_VALUE_MASK 0x000000ff +#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB) +#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK) + +#define COUNT_DEC_ADDRESS 0x00000440 +#define COUNT_DEC_OFFSET 0x00000440 +#define COUNT_DEC_VALUE_MSB 7 +#define COUNT_DEC_VALUE_LSB 0 +#define COUNT_DEC_VALUE_MASK 0x000000ff +#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB) +#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK) + +#define SCRATCH_ADDRESS 0x00000460 +#define SCRATCH_OFFSET 0x00000460 +#define SCRATCH_VALUE_MSB 7 +#define SCRATCH_VALUE_LSB 0 +#define SCRATCH_VALUE_MASK 0x000000ff +#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB) +#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK) + +#define FIFO_TIMEOUT_ADDRESS 0x00000468 +#define FIFO_TIMEOUT_OFFSET 0x00000468 +#define FIFO_TIMEOUT_VALUE_MSB 7 +#define FIFO_TIMEOUT_VALUE_LSB 0 +#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff +#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB) +#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK) + +#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469 +#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469 +#define FIFO_TIMEOUT_ENABLE_SET_MSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_LSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001 +#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB) +#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK) + +#define DISABLE_SLEEP_ADDRESS 0x0000046a +#define DISABLE_SLEEP_OFFSET 0x0000046a +#define DISABLE_SLEEP_FOR_INT_MSB 1 +#define DISABLE_SLEEP_FOR_INT_LSB 1 +#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002 +#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB) +#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK) +#define DISABLE_SLEEP_ON_MSB 0 +#define DISABLE_SLEEP_ON_LSB 0 +#define DISABLE_SLEEP_ON_MASK 0x00000001 +#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB) +#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK) + +#define LOCAL_BUS_ADDRESS 0x00000470 +#define LOCAL_BUS_OFFSET 0x00000470 +#define LOCAL_BUS_STATE_MSB 1 +#define LOCAL_BUS_STATE_LSB 0 +#define LOCAL_BUS_STATE_MASK 0x00000003 +#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB) +#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK) + +#define INT_WLAN_ADDRESS 0x00000472 +#define INT_WLAN_OFFSET 0x00000472 +#define INT_WLAN_VECTOR_MSB 7 +#define INT_WLAN_VECTOR_LSB 0 +#define INT_WLAN_VECTOR_MASK 0x000000ff +#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB) +#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK) + +#define WINDOW_DATA_ADDRESS 0x00000474 +#define WINDOW_DATA_OFFSET 0x00000474 +#define WINDOW_DATA_DATA_MSB 7 +#define WINDOW_DATA_DATA_LSB 0 +#define WINDOW_DATA_DATA_MASK 0x000000ff +#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB) +#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK) + +#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 +#define WINDOW_WRITE_ADDR_OFFSET 0x00000478 +#define WINDOW_WRITE_ADDR_ADDR_MSB 7 +#define WINDOW_WRITE_ADDR_ADDR_LSB 0 +#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB) +#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK) + +#define WINDOW_READ_ADDR_ADDRESS 0x0000047c +#define WINDOW_READ_ADDR_OFFSET 0x0000047c +#define WINDOW_READ_ADDR_ADDR_MSB 7 +#define WINDOW_READ_ADDR_ADDR_LSB 0 +#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB) +#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK) + +#define HOST_CTRL_SPI_CONFIG_ADDRESS 0x00000480 +#define HOST_CTRL_SPI_CONFIG_OFFSET 0x00000480 +#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MSB 4 +#define HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB 4 +#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK 0x00000010 +#define HOST_CTRL_SPI_CONFIG_SPI_RESET_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK) >> HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB) +#define HOST_CTRL_SPI_CONFIG_SPI_RESET_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK) +#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MSB 3 +#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB 3 +#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008 +#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB) +#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK) +#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MSB 2 +#define HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB 2 +#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK 0x00000004 +#define HOST_CTRL_SPI_CONFIG_TEST_MODE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK) >> HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB) +#define HOST_CTRL_SPI_CONFIG_TEST_MODE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK) +#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MSB 1 +#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB 0 +#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK 0x00000003 +#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK) >> HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB) +#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK) + +#define HOST_CTRL_SPI_STATUS_ADDRESS 0x00000481 +#define HOST_CTRL_SPI_STATUS_OFFSET 0x00000481 +#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MSB 3 +#define HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB 3 +#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK 0x00000008 +#define HOST_CTRL_SPI_STATUS_ADDR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB) +#define HOST_CTRL_SPI_STATUS_ADDR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK) +#define HOST_CTRL_SPI_STATUS_RD_ERR_MSB 2 +#define HOST_CTRL_SPI_STATUS_RD_ERR_LSB 2 +#define HOST_CTRL_SPI_STATUS_RD_ERR_MASK 0x00000004 +#define HOST_CTRL_SPI_STATUS_RD_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK) >> HOST_CTRL_SPI_STATUS_RD_ERR_LSB) +#define HOST_CTRL_SPI_STATUS_RD_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_RD_ERR_LSB) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK) +#define HOST_CTRL_SPI_STATUS_WR_ERR_MSB 1 +#define HOST_CTRL_SPI_STATUS_WR_ERR_LSB 1 +#define HOST_CTRL_SPI_STATUS_WR_ERR_MASK 0x00000002 +#define HOST_CTRL_SPI_STATUS_WR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_WR_ERR_LSB) +#define HOST_CTRL_SPI_STATUS_WR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_WR_ERR_LSB) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK) +#define HOST_CTRL_SPI_STATUS_READY_MSB 0 +#define HOST_CTRL_SPI_STATUS_READY_LSB 0 +#define HOST_CTRL_SPI_STATUS_READY_MASK 0x00000001 +#define HOST_CTRL_SPI_STATUS_READY_GET(x) (((x) & HOST_CTRL_SPI_STATUS_READY_MASK) >> HOST_CTRL_SPI_STATUS_READY_LSB) +#define HOST_CTRL_SPI_STATUS_READY_SET(x) (((x) << HOST_CTRL_SPI_STATUS_READY_LSB) & HOST_CTRL_SPI_STATUS_READY_MASK) + +#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482 +#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482 +#define NON_ASSOC_SLEEP_EN_BIT_MSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_LSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001 +#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB) +#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK) + +#define CPU_DBG_SEL_ADDRESS 0x00000483 +#define CPU_DBG_SEL_OFFSET 0x00000483 +#define CPU_DBG_SEL_BIT_MSB 5 +#define CPU_DBG_SEL_BIT_LSB 0 +#define CPU_DBG_SEL_BIT_MASK 0x0000003f +#define CPU_DBG_SEL_BIT_GET(x) (((x) & CPU_DBG_SEL_BIT_MASK) >> CPU_DBG_SEL_BIT_LSB) +#define CPU_DBG_SEL_BIT_SET(x) (((x) << CPU_DBG_SEL_BIT_LSB) & CPU_DBG_SEL_BIT_MASK) + +#define CPU_DBG_ADDRESS 0x00000484 +#define CPU_DBG_OFFSET 0x00000484 +#define CPU_DBG_DATA_MSB 7 +#define CPU_DBG_DATA_LSB 0 +#define CPU_DBG_DATA_MASK 0x000000ff +#define CPU_DBG_DATA_GET(x) (((x) & CPU_DBG_DATA_MASK) >> CPU_DBG_DATA_LSB) +#define CPU_DBG_DATA_SET(x) (((x) << CPU_DBG_DATA_LSB) & CPU_DBG_DATA_MASK) + +#define INT_STATUS2_ENABLE_ADDRESS 0x00000488 +#define INT_STATUS2_ENABLE_OFFSET 0x00000488 +#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MSB 2 +#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB 2 +#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK 0x00000004 +#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB) +#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK) +#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MSB 1 +#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB 1 +#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK 0x00000002 +#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB) +#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK) +#define INT_STATUS2_ENABLE_GMBOX_DATA_MSB 0 +#define INT_STATUS2_ENABLE_GMBOX_DATA_LSB 0 +#define INT_STATUS2_ENABLE_GMBOX_DATA_MASK 0x00000001 +#define INT_STATUS2_ENABLE_GMBOX_DATA_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK) >> INT_STATUS2_ENABLE_GMBOX_DATA_LSB) +#define INT_STATUS2_ENABLE_GMBOX_DATA_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_DATA_LSB) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK) + +#define GMBOX_RX_LOOKAHEAD_ADDRESS 0x00000490 +#define GMBOX_RX_LOOKAHEAD_OFFSET 0x00000490 +#define GMBOX_RX_LOOKAHEAD_DATA_MSB 7 +#define GMBOX_RX_LOOKAHEAD_DATA_LSB 0 +#define GMBOX_RX_LOOKAHEAD_DATA_MASK 0x000000ff +#define GMBOX_RX_LOOKAHEAD_DATA_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_DATA_MASK) >> GMBOX_RX_LOOKAHEAD_DATA_LSB) +#define GMBOX_RX_LOOKAHEAD_DATA_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_DATA_LSB) & GMBOX_RX_LOOKAHEAD_DATA_MASK) + +#define GMBOX_RX_LOOKAHEAD_MUX_ADDRESS 0x00000498 +#define GMBOX_RX_LOOKAHEAD_MUX_OFFSET 0x00000498 +#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MSB 0 +#define GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB 0 +#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK 0x00000001 +#define GMBOX_RX_LOOKAHEAD_MUX_SEL_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK) >> GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB) +#define GMBOX_RX_LOOKAHEAD_MUX_SEL_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK) + +#define CIS_WINDOW_ADDRESS 0x00000600 +#define CIS_WINDOW_OFFSET 0x00000600 +#define CIS_WINDOW_DATA_MSB 7 +#define CIS_WINDOW_DATA_LSB 0 +#define CIS_WINDOW_DATA_MASK 0x000000ff +#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB) +#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_wlan_host_reg_reg_s { + unsigned char pad0[1024]; /* pad to 0x400 */ + volatile unsigned char host_int_status; + volatile unsigned char cpu_int_status; + volatile unsigned char error_int_status; + volatile unsigned char counter_int_status; + volatile unsigned char mbox_frame; + volatile unsigned char rx_lookahead_valid; + volatile unsigned char host_int_status2; + volatile unsigned char gmbox_rx_avail; + volatile unsigned char rx_lookahead0[4]; + volatile unsigned char rx_lookahead1[4]; + volatile unsigned char rx_lookahead2[4]; + volatile unsigned char rx_lookahead3[4]; + volatile unsigned char int_status_enable; + volatile unsigned char cpu_int_status_enable; + volatile unsigned char error_status_enable; + volatile unsigned char counter_int_status_enable; + unsigned char pad1[4]; /* pad to 0x420 */ + volatile unsigned char count[8]; + unsigned char pad2[24]; /* pad to 0x440 */ + volatile unsigned char count_dec[32]; + volatile unsigned char scratch[8]; + volatile unsigned char fifo_timeout; + volatile unsigned char fifo_timeout_enable; + volatile unsigned char disable_sleep; + unsigned char pad3[5]; /* pad to 0x470 */ + volatile unsigned char local_bus; + unsigned char pad4[1]; /* pad to 0x472 */ + volatile unsigned char int_wlan; + unsigned char pad5[1]; /* pad to 0x474 */ + volatile unsigned char window_data[4]; + volatile unsigned char window_write_addr[4]; + volatile unsigned char window_read_addr[4]; + volatile unsigned char host_ctrl_spi_config; + volatile unsigned char host_ctrl_spi_status; + volatile unsigned char non_assoc_sleep_en; + volatile unsigned char cpu_dbg_sel; + volatile unsigned char cpu_dbg[4]; + volatile unsigned char int_status2_enable; + unsigned char pad6[7]; /* pad to 0x490 */ + volatile unsigned char gmbox_rx_lookahead[8]; + volatile unsigned char gmbox_rx_lookahead_mux; + unsigned char pad7[359]; /* pad to 0x600 */ + volatile unsigned char cis_window[512]; +} mbox_wlan_host_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_WLAN_HOST_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_reg.h new file mode 100644 index 000000000000..e00270fc1450 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_reg.h @@ -0,0 +1,638 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MBOX_WLAN_REG_REG_H_ +#define _MBOX_WLAN_REG_REG_H_ + +#define WLAN_MBOX_FIFO_ADDRESS 0x00000000 +#define WLAN_MBOX_FIFO_OFFSET 0x00000000 +#define WLAN_MBOX_FIFO_DATA_MSB 19 +#define WLAN_MBOX_FIFO_DATA_LSB 0 +#define WLAN_MBOX_FIFO_DATA_MASK 0x000fffff +#define WLAN_MBOX_FIFO_DATA_GET(x) (((x) & WLAN_MBOX_FIFO_DATA_MASK) >> WLAN_MBOX_FIFO_DATA_LSB) +#define WLAN_MBOX_FIFO_DATA_SET(x) (((x) << WLAN_MBOX_FIFO_DATA_LSB) & WLAN_MBOX_FIFO_DATA_MASK) + +#define WLAN_MBOX_FIFO_STATUS_ADDRESS 0x00000010 +#define WLAN_MBOX_FIFO_STATUS_OFFSET 0x00000010 +#define WLAN_MBOX_FIFO_STATUS_EMPTY_MSB 19 +#define WLAN_MBOX_FIFO_STATUS_EMPTY_LSB 16 +#define WLAN_MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000 +#define WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK) >> WLAN_MBOX_FIFO_STATUS_EMPTY_LSB) +#define WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << WLAN_MBOX_FIFO_STATUS_EMPTY_LSB) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK) +#define WLAN_MBOX_FIFO_STATUS_FULL_MSB 15 +#define WLAN_MBOX_FIFO_STATUS_FULL_LSB 12 +#define WLAN_MBOX_FIFO_STATUS_FULL_MASK 0x0000f000 +#define WLAN_MBOX_FIFO_STATUS_FULL_GET(x) (((x) & WLAN_MBOX_FIFO_STATUS_FULL_MASK) >> WLAN_MBOX_FIFO_STATUS_FULL_LSB) +#define WLAN_MBOX_FIFO_STATUS_FULL_SET(x) (((x) << WLAN_MBOX_FIFO_STATUS_FULL_LSB) & WLAN_MBOX_FIFO_STATUS_FULL_MASK) + +#define WLAN_MBOX_DMA_POLICY_ADDRESS 0x00000014 +#define WLAN_MBOX_DMA_POLICY_OFFSET 0x00000014 +#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB 3 +#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB 3 +#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008 +#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB) +#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK) +#define WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB 2 +#define WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB 2 +#define WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004 +#define WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB) +#define WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK) +#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB 1 +#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB 1 +#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002 +#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB) +#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK) +#define WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB 0 +#define WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB 0 +#define WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001 +#define WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB) +#define WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK) + +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018 +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018 +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c +#define WLAN_MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c +#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB) +#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK) +#define WLAN_MBOX0_DMA_RX_CONTROL_START_MSB 1 +#define WLAN_MBOX0_DMA_RX_CONTROL_START_LSB 1 +#define WLAN_MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_START_LSB) +#define WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK) +#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB) +#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK) + +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020 +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020 +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024 +#define WLAN_MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024 +#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB) +#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK) +#define WLAN_MBOX0_DMA_TX_CONTROL_START_MSB 1 +#define WLAN_MBOX0_DMA_TX_CONTROL_START_LSB 1 +#define WLAN_MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_START_LSB) +#define WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK) +#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB) +#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK) + +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028 +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028 +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c +#define WLAN_MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c +#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB) +#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK) +#define WLAN_MBOX1_DMA_RX_CONTROL_START_MSB 1 +#define WLAN_MBOX1_DMA_RX_CONTROL_START_LSB 1 +#define WLAN_MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_START_LSB) +#define WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK) +#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB) +#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK) + +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030 +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030 +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034 +#define WLAN_MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034 +#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB) +#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK) +#define WLAN_MBOX1_DMA_TX_CONTROL_START_MSB 1 +#define WLAN_MBOX1_DMA_TX_CONTROL_START_LSB 1 +#define WLAN_MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_START_LSB) +#define WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK) +#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB) +#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK) + +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038 +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038 +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c +#define WLAN_MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c +#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB) +#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK) +#define WLAN_MBOX2_DMA_RX_CONTROL_START_MSB 1 +#define WLAN_MBOX2_DMA_RX_CONTROL_START_LSB 1 +#define WLAN_MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_START_LSB) +#define WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK) +#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB) +#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK) + +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040 +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040 +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044 +#define WLAN_MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044 +#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB) +#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK) +#define WLAN_MBOX2_DMA_TX_CONTROL_START_MSB 1 +#define WLAN_MBOX2_DMA_TX_CONTROL_START_LSB 1 +#define WLAN_MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_START_LSB) +#define WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK) +#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB) +#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK) + +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048 +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048 +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c +#define WLAN_MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c +#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB) +#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK) +#define WLAN_MBOX3_DMA_RX_CONTROL_START_MSB 1 +#define WLAN_MBOX3_DMA_RX_CONTROL_START_LSB 1 +#define WLAN_MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_START_LSB) +#define WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK) +#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB) +#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK) + +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050 +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050 +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054 +#define WLAN_MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054 +#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB) +#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK) +#define WLAN_MBOX3_DMA_TX_CONTROL_START_MSB 1 +#define WLAN_MBOX3_DMA_TX_CONTROL_START_LSB 1 +#define WLAN_MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_START_LSB) +#define WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK) +#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB) +#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK) + +#define WLAN_MBOX_INT_STATUS_ADDRESS 0x00000058 +#define WLAN_MBOX_INT_STATUS_OFFSET 0x00000058 +#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31 +#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28 +#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000 +#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) +#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) +#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27 +#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24 +#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) +#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) +#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23 +#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20 +#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000 +#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) +#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) +#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB 17 +#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB 17 +#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000 +#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB) +#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK) +#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16 +#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16 +#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000 +#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB) +#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK) +#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15 +#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12 +#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000 +#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) +#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) +#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB 11 +#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB 8 +#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00 +#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB) +#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK) +#define WLAN_MBOX_INT_STATUS_HOST_MSB 7 +#define WLAN_MBOX_INT_STATUS_HOST_LSB 0 +#define WLAN_MBOX_INT_STATUS_HOST_MASK 0x000000ff +#define WLAN_MBOX_INT_STATUS_HOST_GET(x) (((x) & WLAN_MBOX_INT_STATUS_HOST_MASK) >> WLAN_MBOX_INT_STATUS_HOST_LSB) +#define WLAN_MBOX_INT_STATUS_HOST_SET(x) (((x) << WLAN_MBOX_INT_STATUS_HOST_LSB) & WLAN_MBOX_INT_STATUS_HOST_MASK) + +#define WLAN_MBOX_INT_ENABLE_ADDRESS 0x0000005c +#define WLAN_MBOX_INT_ENABLE_OFFSET 0x0000005c +#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31 +#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28 +#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000 +#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) +#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) +#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27 +#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24 +#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) +#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) +#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23 +#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20 +#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000 +#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) +#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) +#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17 +#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17 +#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000 +#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB) +#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK) +#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16 +#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16 +#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000 +#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) +#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) +#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15 +#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12 +#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000 +#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) +#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) +#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11 +#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8 +#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00 +#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB) +#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK) +#define WLAN_MBOX_INT_ENABLE_HOST_MSB 7 +#define WLAN_MBOX_INT_ENABLE_HOST_LSB 0 +#define WLAN_MBOX_INT_ENABLE_HOST_MASK 0x000000ff +#define WLAN_MBOX_INT_ENABLE_HOST_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_HOST_MASK) >> WLAN_MBOX_INT_ENABLE_HOST_LSB) +#define WLAN_MBOX_INT_ENABLE_HOST_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_HOST_LSB) & WLAN_MBOX_INT_ENABLE_HOST_MASK) + +#define WLAN_INT_HOST_ADDRESS 0x00000060 +#define WLAN_INT_HOST_OFFSET 0x00000060 +#define WLAN_INT_HOST_VECTOR_MSB 7 +#define WLAN_INT_HOST_VECTOR_LSB 0 +#define WLAN_INT_HOST_VECTOR_MASK 0x000000ff +#define WLAN_INT_HOST_VECTOR_GET(x) (((x) & WLAN_INT_HOST_VECTOR_MASK) >> WLAN_INT_HOST_VECTOR_LSB) +#define WLAN_INT_HOST_VECTOR_SET(x) (((x) << WLAN_INT_HOST_VECTOR_LSB) & WLAN_INT_HOST_VECTOR_MASK) + +#define WLAN_LOCAL_COUNT_ADDRESS 0x00000080 +#define WLAN_LOCAL_COUNT_OFFSET 0x00000080 +#define WLAN_LOCAL_COUNT_VALUE_MSB 7 +#define WLAN_LOCAL_COUNT_VALUE_LSB 0 +#define WLAN_LOCAL_COUNT_VALUE_MASK 0x000000ff +#define WLAN_LOCAL_COUNT_VALUE_GET(x) (((x) & WLAN_LOCAL_COUNT_VALUE_MASK) >> WLAN_LOCAL_COUNT_VALUE_LSB) +#define WLAN_LOCAL_COUNT_VALUE_SET(x) (((x) << WLAN_LOCAL_COUNT_VALUE_LSB) & WLAN_LOCAL_COUNT_VALUE_MASK) + +#define WLAN_COUNT_INC_ADDRESS 0x000000a0 +#define WLAN_COUNT_INC_OFFSET 0x000000a0 +#define WLAN_COUNT_INC_VALUE_MSB 7 +#define WLAN_COUNT_INC_VALUE_LSB 0 +#define WLAN_COUNT_INC_VALUE_MASK 0x000000ff +#define WLAN_COUNT_INC_VALUE_GET(x) (((x) & WLAN_COUNT_INC_VALUE_MASK) >> WLAN_COUNT_INC_VALUE_LSB) +#define WLAN_COUNT_INC_VALUE_SET(x) (((x) << WLAN_COUNT_INC_VALUE_LSB) & WLAN_COUNT_INC_VALUE_MASK) + +#define WLAN_LOCAL_SCRATCH_ADDRESS 0x000000c0 +#define WLAN_LOCAL_SCRATCH_OFFSET 0x000000c0 +#define WLAN_LOCAL_SCRATCH_VALUE_MSB 7 +#define WLAN_LOCAL_SCRATCH_VALUE_LSB 0 +#define WLAN_LOCAL_SCRATCH_VALUE_MASK 0x000000ff +#define WLAN_LOCAL_SCRATCH_VALUE_GET(x) (((x) & WLAN_LOCAL_SCRATCH_VALUE_MASK) >> WLAN_LOCAL_SCRATCH_VALUE_LSB) +#define WLAN_LOCAL_SCRATCH_VALUE_SET(x) (((x) << WLAN_LOCAL_SCRATCH_VALUE_LSB) & WLAN_LOCAL_SCRATCH_VALUE_MASK) + +#define WLAN_USE_LOCAL_BUS_ADDRESS 0x000000e0 +#define WLAN_USE_LOCAL_BUS_OFFSET 0x000000e0 +#define WLAN_USE_LOCAL_BUS_PIN_INIT_MSB 0 +#define WLAN_USE_LOCAL_BUS_PIN_INIT_LSB 0 +#define WLAN_USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001 +#define WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK) >> WLAN_USE_LOCAL_BUS_PIN_INIT_LSB) +#define WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << WLAN_USE_LOCAL_BUS_PIN_INIT_LSB) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK) + +#define WLAN_SDIO_CONFIG_ADDRESS 0x000000e4 +#define WLAN_SDIO_CONFIG_OFFSET 0x000000e4 +#define WLAN_SDIO_CONFIG_CCCR_IOR1_MSB 0 +#define WLAN_SDIO_CONFIG_CCCR_IOR1_LSB 0 +#define WLAN_SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001 +#define WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK) >> WLAN_SDIO_CONFIG_CCCR_IOR1_LSB) +#define WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << WLAN_SDIO_CONFIG_CCCR_IOR1_LSB) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK) + +#define WLAN_MBOX_DEBUG_ADDRESS 0x000000e8 +#define WLAN_MBOX_DEBUG_OFFSET 0x000000e8 +#define WLAN_MBOX_DEBUG_SEL_MSB 2 +#define WLAN_MBOX_DEBUG_SEL_LSB 0 +#define WLAN_MBOX_DEBUG_SEL_MASK 0x00000007 +#define WLAN_MBOX_DEBUG_SEL_GET(x) (((x) & WLAN_MBOX_DEBUG_SEL_MASK) >> WLAN_MBOX_DEBUG_SEL_LSB) +#define WLAN_MBOX_DEBUG_SEL_SET(x) (((x) << WLAN_MBOX_DEBUG_SEL_LSB) & WLAN_MBOX_DEBUG_SEL_MASK) + +#define WLAN_MBOX_FIFO_RESET_ADDRESS 0x000000ec +#define WLAN_MBOX_FIFO_RESET_OFFSET 0x000000ec +#define WLAN_MBOX_FIFO_RESET_INIT_MSB 0 +#define WLAN_MBOX_FIFO_RESET_INIT_LSB 0 +#define WLAN_MBOX_FIFO_RESET_INIT_MASK 0x00000001 +#define WLAN_MBOX_FIFO_RESET_INIT_GET(x) (((x) & WLAN_MBOX_FIFO_RESET_INIT_MASK) >> WLAN_MBOX_FIFO_RESET_INIT_LSB) +#define WLAN_MBOX_FIFO_RESET_INIT_SET(x) (((x) << WLAN_MBOX_FIFO_RESET_INIT_LSB) & WLAN_MBOX_FIFO_RESET_INIT_MASK) + +#define WLAN_MBOX_TXFIFO_POP_ADDRESS 0x000000f0 +#define WLAN_MBOX_TXFIFO_POP_OFFSET 0x000000f0 +#define WLAN_MBOX_TXFIFO_POP_DATA_MSB 0 +#define WLAN_MBOX_TXFIFO_POP_DATA_LSB 0 +#define WLAN_MBOX_TXFIFO_POP_DATA_MASK 0x00000001 +#define WLAN_MBOX_TXFIFO_POP_DATA_GET(x) (((x) & WLAN_MBOX_TXFIFO_POP_DATA_MASK) >> WLAN_MBOX_TXFIFO_POP_DATA_LSB) +#define WLAN_MBOX_TXFIFO_POP_DATA_SET(x) (((x) << WLAN_MBOX_TXFIFO_POP_DATA_LSB) & WLAN_MBOX_TXFIFO_POP_DATA_MASK) + +#define WLAN_MBOX_RXFIFO_POP_ADDRESS 0x00000100 +#define WLAN_MBOX_RXFIFO_POP_OFFSET 0x00000100 +#define WLAN_MBOX_RXFIFO_POP_DATA_MSB 0 +#define WLAN_MBOX_RXFIFO_POP_DATA_LSB 0 +#define WLAN_MBOX_RXFIFO_POP_DATA_MASK 0x00000001 +#define WLAN_MBOX_RXFIFO_POP_DATA_GET(x) (((x) & WLAN_MBOX_RXFIFO_POP_DATA_MASK) >> WLAN_MBOX_RXFIFO_POP_DATA_LSB) +#define WLAN_MBOX_RXFIFO_POP_DATA_SET(x) (((x) << WLAN_MBOX_RXFIFO_POP_DATA_LSB) & WLAN_MBOX_RXFIFO_POP_DATA_MASK) + +#define WLAN_SDIO_DEBUG_ADDRESS 0x00000110 +#define WLAN_SDIO_DEBUG_OFFSET 0x00000110 +#define WLAN_SDIO_DEBUG_SEL_MSB 3 +#define WLAN_SDIO_DEBUG_SEL_LSB 0 +#define WLAN_SDIO_DEBUG_SEL_MASK 0x0000000f +#define WLAN_SDIO_DEBUG_SEL_GET(x) (((x) & WLAN_SDIO_DEBUG_SEL_MASK) >> WLAN_SDIO_DEBUG_SEL_LSB) +#define WLAN_SDIO_DEBUG_SEL_SET(x) (((x) << WLAN_SDIO_DEBUG_SEL_LSB) & WLAN_SDIO_DEBUG_SEL_MASK) + +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000114 +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000114 +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS 0x00000118 +#define WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET 0x00000118 +#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB 2 +#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB 2 +#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB) +#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK) +#define WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB 1 +#define WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB 1 +#define WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 +#define WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB) +#define WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK) +#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB 0 +#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB 0 +#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB) +#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK) + +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x0000011c +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x0000011c +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS 0x00000120 +#define WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET 0x00000120 +#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB 2 +#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB 2 +#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB) +#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK) +#define WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB 1 +#define WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB 1 +#define WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 +#define WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB) +#define WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK) +#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB 0 +#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB 0 +#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB) +#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK) + +#define WLAN_GMBOX_INT_STATUS_ADDRESS 0x00000124 +#define WLAN_GMBOX_INT_STATUS_OFFSET 0x00000124 +#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB 6 +#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB 6 +#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00000040 +#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB) +#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK) +#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB 5 +#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB 5 +#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00000020 +#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB) +#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK) +#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 4 +#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 4 +#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000010 +#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) +#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) +#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 3 +#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 3 +#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000008 +#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) +#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) +#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 2 +#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 2 +#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000004 +#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) +#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) +#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB 1 +#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB 1 +#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x00000002 +#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) +#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) +#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB 0 +#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB 0 +#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000001 +#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB) +#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK) + +#define WLAN_GMBOX_INT_ENABLE_ADDRESS 0x00000128 +#define WLAN_GMBOX_INT_ENABLE_OFFSET 0x00000128 +#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB 6 +#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB 6 +#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00000040 +#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB) +#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK) +#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB 5 +#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB 5 +#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00000020 +#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) +#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) +#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 4 +#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 4 +#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000010 +#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) +#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 3 +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 3 +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000008 +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 2 +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 2 +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000004 +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) +#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 1 +#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 1 +#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x00000002 +#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) +#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) +#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB 0 +#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB 0 +#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000001 +#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB) +#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK) + +#define WLAN_HOST_IF_WINDOW_ADDRESS 0x00002000 +#define WLAN_HOST_IF_WINDOW_OFFSET 0x00002000 +#define WLAN_HOST_IF_WINDOW_DATA_MSB 7 +#define WLAN_HOST_IF_WINDOW_DATA_LSB 0 +#define WLAN_HOST_IF_WINDOW_DATA_MASK 0x000000ff +#define WLAN_HOST_IF_WINDOW_DATA_GET(x) (((x) & WLAN_HOST_IF_WINDOW_DATA_MASK) >> WLAN_HOST_IF_WINDOW_DATA_LSB) +#define WLAN_HOST_IF_WINDOW_DATA_SET(x) (((x) << WLAN_HOST_IF_WINDOW_DATA_LSB) & WLAN_HOST_IF_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_wlan_reg_reg_s { + volatile unsigned int wlan_mbox_fifo[4]; + volatile unsigned int wlan_mbox_fifo_status; + volatile unsigned int wlan_mbox_dma_policy; + volatile unsigned int wlan_mbox0_dma_rx_descriptor_base; + volatile unsigned int wlan_mbox0_dma_rx_control; + volatile unsigned int wlan_mbox0_dma_tx_descriptor_base; + volatile unsigned int wlan_mbox0_dma_tx_control; + volatile unsigned int wlan_mbox1_dma_rx_descriptor_base; + volatile unsigned int wlan_mbox1_dma_rx_control; + volatile unsigned int wlan_mbox1_dma_tx_descriptor_base; + volatile unsigned int wlan_mbox1_dma_tx_control; + volatile unsigned int wlan_mbox2_dma_rx_descriptor_base; + volatile unsigned int wlan_mbox2_dma_rx_control; + volatile unsigned int wlan_mbox2_dma_tx_descriptor_base; + volatile unsigned int wlan_mbox2_dma_tx_control; + volatile unsigned int wlan_mbox3_dma_rx_descriptor_base; + volatile unsigned int wlan_mbox3_dma_rx_control; + volatile unsigned int wlan_mbox3_dma_tx_descriptor_base; + volatile unsigned int wlan_mbox3_dma_tx_control; + volatile unsigned int wlan_mbox_int_status; + volatile unsigned int wlan_mbox_int_enable; + volatile unsigned int wlan_int_host; + unsigned char pad0[28]; /* pad to 0x80 */ + volatile unsigned int wlan_local_count[8]; + volatile unsigned int wlan_count_inc[8]; + volatile unsigned int wlan_local_scratch[8]; + volatile unsigned int wlan_use_local_bus; + volatile unsigned int wlan_sdio_config; + volatile unsigned int wlan_mbox_debug; + volatile unsigned int wlan_mbox_fifo_reset; + volatile unsigned int wlan_mbox_txfifo_pop[4]; + volatile unsigned int wlan_mbox_rxfifo_pop[4]; + volatile unsigned int wlan_sdio_debug; + volatile unsigned int wlan_gmbox0_dma_rx_descriptor_base; + volatile unsigned int wlan_gmbox0_dma_rx_control; + volatile unsigned int wlan_gmbox0_dma_tx_descriptor_base; + volatile unsigned int wlan_gmbox0_dma_tx_control; + volatile unsigned int wlan_gmbox_int_status; + volatile unsigned int wlan_gmbox_int_enable; + unsigned char pad1[7892]; /* pad to 0x2000 */ + volatile unsigned int wlan_host_if_window[2048]; +} mbox_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_WLAN_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rdma_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rdma_reg.h new file mode 100644 index 000000000000..56ffda5b1a30 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rdma_reg.h @@ -0,0 +1,564 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _RDMA_REG_REG_H_ +#define _RDMA_REG_REG_H_ + +#define DMA_CONFIG_ADDRESS 0x00000000 +#define DMA_CONFIG_OFFSET 0x00000000 +#define DMA_CONFIG_WLBB_PWD_EN_MSB 4 +#define DMA_CONFIG_WLBB_PWD_EN_LSB 4 +#define DMA_CONFIG_WLBB_PWD_EN_MASK 0x00000010 +#define DMA_CONFIG_WLBB_PWD_EN_GET(x) (((x) & DMA_CONFIG_WLBB_PWD_EN_MASK) >> DMA_CONFIG_WLBB_PWD_EN_LSB) +#define DMA_CONFIG_WLBB_PWD_EN_SET(x) (((x) << DMA_CONFIG_WLBB_PWD_EN_LSB) & DMA_CONFIG_WLBB_PWD_EN_MASK) +#define DMA_CONFIG_WLMAC_PWD_EN_MSB 3 +#define DMA_CONFIG_WLMAC_PWD_EN_LSB 3 +#define DMA_CONFIG_WLMAC_PWD_EN_MASK 0x00000008 +#define DMA_CONFIG_WLMAC_PWD_EN_GET(x) (((x) & DMA_CONFIG_WLMAC_PWD_EN_MASK) >> DMA_CONFIG_WLMAC_PWD_EN_LSB) +#define DMA_CONFIG_WLMAC_PWD_EN_SET(x) (((x) << DMA_CONFIG_WLMAC_PWD_EN_LSB) & DMA_CONFIG_WLMAC_PWD_EN_MASK) +#define DMA_CONFIG_ENABLE_RETENTION_MSB 2 +#define DMA_CONFIG_ENABLE_RETENTION_LSB 2 +#define DMA_CONFIG_ENABLE_RETENTION_MASK 0x00000004 +#define DMA_CONFIG_ENABLE_RETENTION_GET(x) (((x) & DMA_CONFIG_ENABLE_RETENTION_MASK) >> DMA_CONFIG_ENABLE_RETENTION_LSB) +#define DMA_CONFIG_ENABLE_RETENTION_SET(x) (((x) << DMA_CONFIG_ENABLE_RETENTION_LSB) & DMA_CONFIG_ENABLE_RETENTION_MASK) +#define DMA_CONFIG_RTC_PRIORITY_MSB 1 +#define DMA_CONFIG_RTC_PRIORITY_LSB 1 +#define DMA_CONFIG_RTC_PRIORITY_MASK 0x00000002 +#define DMA_CONFIG_RTC_PRIORITY_GET(x) (((x) & DMA_CONFIG_RTC_PRIORITY_MASK) >> DMA_CONFIG_RTC_PRIORITY_LSB) +#define DMA_CONFIG_RTC_PRIORITY_SET(x) (((x) << DMA_CONFIG_RTC_PRIORITY_LSB) & DMA_CONFIG_RTC_PRIORITY_MASK) +#define DMA_CONFIG_DMA_TYPE_MSB 0 +#define DMA_CONFIG_DMA_TYPE_LSB 0 +#define DMA_CONFIG_DMA_TYPE_MASK 0x00000001 +#define DMA_CONFIG_DMA_TYPE_GET(x) (((x) & DMA_CONFIG_DMA_TYPE_MASK) >> DMA_CONFIG_DMA_TYPE_LSB) +#define DMA_CONFIG_DMA_TYPE_SET(x) (((x) << DMA_CONFIG_DMA_TYPE_LSB) & DMA_CONFIG_DMA_TYPE_MASK) + +#define DMA_CONTROL_ADDRESS 0x00000004 +#define DMA_CONTROL_OFFSET 0x00000004 +#define DMA_CONTROL_START_MSB 1 +#define DMA_CONTROL_START_LSB 1 +#define DMA_CONTROL_START_MASK 0x00000002 +#define DMA_CONTROL_START_GET(x) (((x) & DMA_CONTROL_START_MASK) >> DMA_CONTROL_START_LSB) +#define DMA_CONTROL_START_SET(x) (((x) << DMA_CONTROL_START_LSB) & DMA_CONTROL_START_MASK) +#define DMA_CONTROL_STOP_MSB 0 +#define DMA_CONTROL_STOP_LSB 0 +#define DMA_CONTROL_STOP_MASK 0x00000001 +#define DMA_CONTROL_STOP_GET(x) (((x) & DMA_CONTROL_STOP_MASK) >> DMA_CONTROL_STOP_LSB) +#define DMA_CONTROL_STOP_SET(x) (((x) << DMA_CONTROL_STOP_LSB) & DMA_CONTROL_STOP_MASK) + +#define DMA_SRC_ADDRESS 0x00000008 +#define DMA_SRC_OFFSET 0x00000008 +#define DMA_SRC_ADDR_MSB 31 +#define DMA_SRC_ADDR_LSB 2 +#define DMA_SRC_ADDR_MASK 0xfffffffc +#define DMA_SRC_ADDR_GET(x) (((x) & DMA_SRC_ADDR_MASK) >> DMA_SRC_ADDR_LSB) +#define DMA_SRC_ADDR_SET(x) (((x) << DMA_SRC_ADDR_LSB) & DMA_SRC_ADDR_MASK) + +#define DMA_DEST_ADDRESS 0x0000000c +#define DMA_DEST_OFFSET 0x0000000c +#define DMA_DEST_ADDR_MSB 31 +#define DMA_DEST_ADDR_LSB 2 +#define DMA_DEST_ADDR_MASK 0xfffffffc +#define DMA_DEST_ADDR_GET(x) (((x) & DMA_DEST_ADDR_MASK) >> DMA_DEST_ADDR_LSB) +#define DMA_DEST_ADDR_SET(x) (((x) << DMA_DEST_ADDR_LSB) & DMA_DEST_ADDR_MASK) + +#define DMA_LENGTH_ADDRESS 0x00000010 +#define DMA_LENGTH_OFFSET 0x00000010 +#define DMA_LENGTH_WORDS_MSB 11 +#define DMA_LENGTH_WORDS_LSB 0 +#define DMA_LENGTH_WORDS_MASK 0x00000fff +#define DMA_LENGTH_WORDS_GET(x) (((x) & DMA_LENGTH_WORDS_MASK) >> DMA_LENGTH_WORDS_LSB) +#define DMA_LENGTH_WORDS_SET(x) (((x) << DMA_LENGTH_WORDS_LSB) & DMA_LENGTH_WORDS_MASK) + +#define VMC_BASE_ADDRESS 0x00000014 +#define VMC_BASE_OFFSET 0x00000014 +#define VMC_BASE_ADDR_MSB 31 +#define VMC_BASE_ADDR_LSB 2 +#define VMC_BASE_ADDR_MASK 0xfffffffc +#define VMC_BASE_ADDR_GET(x) (((x) & VMC_BASE_ADDR_MASK) >> VMC_BASE_ADDR_LSB) +#define VMC_BASE_ADDR_SET(x) (((x) << VMC_BASE_ADDR_LSB) & VMC_BASE_ADDR_MASK) + +#define INDIRECT_REG_ADDRESS 0x00000018 +#define INDIRECT_REG_OFFSET 0x00000018 +#define INDIRECT_REG_ID_MSB 31 +#define INDIRECT_REG_ID_LSB 2 +#define INDIRECT_REG_ID_MASK 0xfffffffc +#define INDIRECT_REG_ID_GET(x) (((x) & INDIRECT_REG_ID_MASK) >> INDIRECT_REG_ID_LSB) +#define INDIRECT_REG_ID_SET(x) (((x) << INDIRECT_REG_ID_LSB) & INDIRECT_REG_ID_MASK) + +#define INDIRECT_RETURN_ADDRESS 0x0000001c +#define INDIRECT_RETURN_OFFSET 0x0000001c +#define INDIRECT_RETURN_ADDR_MSB 31 +#define INDIRECT_RETURN_ADDR_LSB 2 +#define INDIRECT_RETURN_ADDR_MASK 0xfffffffc +#define INDIRECT_RETURN_ADDR_GET(x) (((x) & INDIRECT_RETURN_ADDR_MASK) >> INDIRECT_RETURN_ADDR_LSB) +#define INDIRECT_RETURN_ADDR_SET(x) (((x) << INDIRECT_RETURN_ADDR_LSB) & INDIRECT_RETURN_ADDR_MASK) + +#define RDMA_REGION_0__ADDRESS 0x00000020 +#define RDMA_REGION_0__OFFSET 0x00000020 +#define RDMA_REGION_0__ADDR_MSB 31 +#define RDMA_REGION_0__ADDR_LSB 13 +#define RDMA_REGION_0__ADDR_MASK 0xffffe000 +#define RDMA_REGION_0__ADDR_GET(x) (((x) & RDMA_REGION_0__ADDR_MASK) >> RDMA_REGION_0__ADDR_LSB) +#define RDMA_REGION_0__ADDR_SET(x) (((x) << RDMA_REGION_0__ADDR_LSB) & RDMA_REGION_0__ADDR_MASK) +#define RDMA_REGION_0__LENGTH_MSB 12 +#define RDMA_REGION_0__LENGTH_LSB 2 +#define RDMA_REGION_0__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_0__LENGTH_GET(x) (((x) & RDMA_REGION_0__LENGTH_MASK) >> RDMA_REGION_0__LENGTH_LSB) +#define RDMA_REGION_0__LENGTH_SET(x) (((x) << RDMA_REGION_0__LENGTH_LSB) & RDMA_REGION_0__LENGTH_MASK) +#define RDMA_REGION_0__INDI_MSB 1 +#define RDMA_REGION_0__INDI_LSB 1 +#define RDMA_REGION_0__INDI_MASK 0x00000002 +#define RDMA_REGION_0__INDI_GET(x) (((x) & RDMA_REGION_0__INDI_MASK) >> RDMA_REGION_0__INDI_LSB) +#define RDMA_REGION_0__INDI_SET(x) (((x) << RDMA_REGION_0__INDI_LSB) & RDMA_REGION_0__INDI_MASK) +#define RDMA_REGION_0__NEXT_MSB 0 +#define RDMA_REGION_0__NEXT_LSB 0 +#define RDMA_REGION_0__NEXT_MASK 0x00000001 +#define RDMA_REGION_0__NEXT_GET(x) (((x) & RDMA_REGION_0__NEXT_MASK) >> RDMA_REGION_0__NEXT_LSB) +#define RDMA_REGION_0__NEXT_SET(x) (((x) << RDMA_REGION_0__NEXT_LSB) & RDMA_REGION_0__NEXT_MASK) + +#define RDMA_REGION_1__ADDRESS 0x00000024 +#define RDMA_REGION_1__OFFSET 0x00000024 +#define RDMA_REGION_1__ADDR_MSB 31 +#define RDMA_REGION_1__ADDR_LSB 13 +#define RDMA_REGION_1__ADDR_MASK 0xffffe000 +#define RDMA_REGION_1__ADDR_GET(x) (((x) & RDMA_REGION_1__ADDR_MASK) >> RDMA_REGION_1__ADDR_LSB) +#define RDMA_REGION_1__ADDR_SET(x) (((x) << RDMA_REGION_1__ADDR_LSB) & RDMA_REGION_1__ADDR_MASK) +#define RDMA_REGION_1__LENGTH_MSB 12 +#define RDMA_REGION_1__LENGTH_LSB 2 +#define RDMA_REGION_1__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_1__LENGTH_GET(x) (((x) & RDMA_REGION_1__LENGTH_MASK) >> RDMA_REGION_1__LENGTH_LSB) +#define RDMA_REGION_1__LENGTH_SET(x) (((x) << RDMA_REGION_1__LENGTH_LSB) & RDMA_REGION_1__LENGTH_MASK) +#define RDMA_REGION_1__INDI_MSB 1 +#define RDMA_REGION_1__INDI_LSB 1 +#define RDMA_REGION_1__INDI_MASK 0x00000002 +#define RDMA_REGION_1__INDI_GET(x) (((x) & RDMA_REGION_1__INDI_MASK) >> RDMA_REGION_1__INDI_LSB) +#define RDMA_REGION_1__INDI_SET(x) (((x) << RDMA_REGION_1__INDI_LSB) & RDMA_REGION_1__INDI_MASK) +#define RDMA_REGION_1__NEXT_MSB 0 +#define RDMA_REGION_1__NEXT_LSB 0 +#define RDMA_REGION_1__NEXT_MASK 0x00000001 +#define RDMA_REGION_1__NEXT_GET(x) (((x) & RDMA_REGION_1__NEXT_MASK) >> RDMA_REGION_1__NEXT_LSB) +#define RDMA_REGION_1__NEXT_SET(x) (((x) << RDMA_REGION_1__NEXT_LSB) & RDMA_REGION_1__NEXT_MASK) + +#define RDMA_REGION_2__ADDRESS 0x00000028 +#define RDMA_REGION_2__OFFSET 0x00000028 +#define RDMA_REGION_2__ADDR_MSB 31 +#define RDMA_REGION_2__ADDR_LSB 13 +#define RDMA_REGION_2__ADDR_MASK 0xffffe000 +#define RDMA_REGION_2__ADDR_GET(x) (((x) & RDMA_REGION_2__ADDR_MASK) >> RDMA_REGION_2__ADDR_LSB) +#define RDMA_REGION_2__ADDR_SET(x) (((x) << RDMA_REGION_2__ADDR_LSB) & RDMA_REGION_2__ADDR_MASK) +#define RDMA_REGION_2__LENGTH_MSB 12 +#define RDMA_REGION_2__LENGTH_LSB 2 +#define RDMA_REGION_2__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_2__LENGTH_GET(x) (((x) & RDMA_REGION_2__LENGTH_MASK) >> RDMA_REGION_2__LENGTH_LSB) +#define RDMA_REGION_2__LENGTH_SET(x) (((x) << RDMA_REGION_2__LENGTH_LSB) & RDMA_REGION_2__LENGTH_MASK) +#define RDMA_REGION_2__INDI_MSB 1 +#define RDMA_REGION_2__INDI_LSB 1 +#define RDMA_REGION_2__INDI_MASK 0x00000002 +#define RDMA_REGION_2__INDI_GET(x) (((x) & RDMA_REGION_2__INDI_MASK) >> RDMA_REGION_2__INDI_LSB) +#define RDMA_REGION_2__INDI_SET(x) (((x) << RDMA_REGION_2__INDI_LSB) & RDMA_REGION_2__INDI_MASK) +#define RDMA_REGION_2__NEXT_MSB 0 +#define RDMA_REGION_2__NEXT_LSB 0 +#define RDMA_REGION_2__NEXT_MASK 0x00000001 +#define RDMA_REGION_2__NEXT_GET(x) (((x) & RDMA_REGION_2__NEXT_MASK) >> RDMA_REGION_2__NEXT_LSB) +#define RDMA_REGION_2__NEXT_SET(x) (((x) << RDMA_REGION_2__NEXT_LSB) & RDMA_REGION_2__NEXT_MASK) + +#define RDMA_REGION_3__ADDRESS 0x0000002c +#define RDMA_REGION_3__OFFSET 0x0000002c +#define RDMA_REGION_3__ADDR_MSB 31 +#define RDMA_REGION_3__ADDR_LSB 13 +#define RDMA_REGION_3__ADDR_MASK 0xffffe000 +#define RDMA_REGION_3__ADDR_GET(x) (((x) & RDMA_REGION_3__ADDR_MASK) >> RDMA_REGION_3__ADDR_LSB) +#define RDMA_REGION_3__ADDR_SET(x) (((x) << RDMA_REGION_3__ADDR_LSB) & RDMA_REGION_3__ADDR_MASK) +#define RDMA_REGION_3__LENGTH_MSB 12 +#define RDMA_REGION_3__LENGTH_LSB 2 +#define RDMA_REGION_3__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_3__LENGTH_GET(x) (((x) & RDMA_REGION_3__LENGTH_MASK) >> RDMA_REGION_3__LENGTH_LSB) +#define RDMA_REGION_3__LENGTH_SET(x) (((x) << RDMA_REGION_3__LENGTH_LSB) & RDMA_REGION_3__LENGTH_MASK) +#define RDMA_REGION_3__INDI_MSB 1 +#define RDMA_REGION_3__INDI_LSB 1 +#define RDMA_REGION_3__INDI_MASK 0x00000002 +#define RDMA_REGION_3__INDI_GET(x) (((x) & RDMA_REGION_3__INDI_MASK) >> RDMA_REGION_3__INDI_LSB) +#define RDMA_REGION_3__INDI_SET(x) (((x) << RDMA_REGION_3__INDI_LSB) & RDMA_REGION_3__INDI_MASK) +#define RDMA_REGION_3__NEXT_MSB 0 +#define RDMA_REGION_3__NEXT_LSB 0 +#define RDMA_REGION_3__NEXT_MASK 0x00000001 +#define RDMA_REGION_3__NEXT_GET(x) (((x) & RDMA_REGION_3__NEXT_MASK) >> RDMA_REGION_3__NEXT_LSB) +#define RDMA_REGION_3__NEXT_SET(x) (((x) << RDMA_REGION_3__NEXT_LSB) & RDMA_REGION_3__NEXT_MASK) + +#define RDMA_REGION_4__ADDRESS 0x00000030 +#define RDMA_REGION_4__OFFSET 0x00000030 +#define RDMA_REGION_4__ADDR_MSB 31 +#define RDMA_REGION_4__ADDR_LSB 13 +#define RDMA_REGION_4__ADDR_MASK 0xffffe000 +#define RDMA_REGION_4__ADDR_GET(x) (((x) & RDMA_REGION_4__ADDR_MASK) >> RDMA_REGION_4__ADDR_LSB) +#define RDMA_REGION_4__ADDR_SET(x) (((x) << RDMA_REGION_4__ADDR_LSB) & RDMA_REGION_4__ADDR_MASK) +#define RDMA_REGION_4__LENGTH_MSB 12 +#define RDMA_REGION_4__LENGTH_LSB 2 +#define RDMA_REGION_4__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_4__LENGTH_GET(x) (((x) & RDMA_REGION_4__LENGTH_MASK) >> RDMA_REGION_4__LENGTH_LSB) +#define RDMA_REGION_4__LENGTH_SET(x) (((x) << RDMA_REGION_4__LENGTH_LSB) & RDMA_REGION_4__LENGTH_MASK) +#define RDMA_REGION_4__INDI_MSB 1 +#define RDMA_REGION_4__INDI_LSB 1 +#define RDMA_REGION_4__INDI_MASK 0x00000002 +#define RDMA_REGION_4__INDI_GET(x) (((x) & RDMA_REGION_4__INDI_MASK) >> RDMA_REGION_4__INDI_LSB) +#define RDMA_REGION_4__INDI_SET(x) (((x) << RDMA_REGION_4__INDI_LSB) & RDMA_REGION_4__INDI_MASK) +#define RDMA_REGION_4__NEXT_MSB 0 +#define RDMA_REGION_4__NEXT_LSB 0 +#define RDMA_REGION_4__NEXT_MASK 0x00000001 +#define RDMA_REGION_4__NEXT_GET(x) (((x) & RDMA_REGION_4__NEXT_MASK) >> RDMA_REGION_4__NEXT_LSB) +#define RDMA_REGION_4__NEXT_SET(x) (((x) << RDMA_REGION_4__NEXT_LSB) & RDMA_REGION_4__NEXT_MASK) + +#define RDMA_REGION_5__ADDRESS 0x00000034 +#define RDMA_REGION_5__OFFSET 0x00000034 +#define RDMA_REGION_5__ADDR_MSB 31 +#define RDMA_REGION_5__ADDR_LSB 13 +#define RDMA_REGION_5__ADDR_MASK 0xffffe000 +#define RDMA_REGION_5__ADDR_GET(x) (((x) & RDMA_REGION_5__ADDR_MASK) >> RDMA_REGION_5__ADDR_LSB) +#define RDMA_REGION_5__ADDR_SET(x) (((x) << RDMA_REGION_5__ADDR_LSB) & RDMA_REGION_5__ADDR_MASK) +#define RDMA_REGION_5__LENGTH_MSB 12 +#define RDMA_REGION_5__LENGTH_LSB 2 +#define RDMA_REGION_5__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_5__LENGTH_GET(x) (((x) & RDMA_REGION_5__LENGTH_MASK) >> RDMA_REGION_5__LENGTH_LSB) +#define RDMA_REGION_5__LENGTH_SET(x) (((x) << RDMA_REGION_5__LENGTH_LSB) & RDMA_REGION_5__LENGTH_MASK) +#define RDMA_REGION_5__INDI_MSB 1 +#define RDMA_REGION_5__INDI_LSB 1 +#define RDMA_REGION_5__INDI_MASK 0x00000002 +#define RDMA_REGION_5__INDI_GET(x) (((x) & RDMA_REGION_5__INDI_MASK) >> RDMA_REGION_5__INDI_LSB) +#define RDMA_REGION_5__INDI_SET(x) (((x) << RDMA_REGION_5__INDI_LSB) & RDMA_REGION_5__INDI_MASK) +#define RDMA_REGION_5__NEXT_MSB 0 +#define RDMA_REGION_5__NEXT_LSB 0 +#define RDMA_REGION_5__NEXT_MASK 0x00000001 +#define RDMA_REGION_5__NEXT_GET(x) (((x) & RDMA_REGION_5__NEXT_MASK) >> RDMA_REGION_5__NEXT_LSB) +#define RDMA_REGION_5__NEXT_SET(x) (((x) << RDMA_REGION_5__NEXT_LSB) & RDMA_REGION_5__NEXT_MASK) + +#define RDMA_REGION_6__ADDRESS 0x00000038 +#define RDMA_REGION_6__OFFSET 0x00000038 +#define RDMA_REGION_6__ADDR_MSB 31 +#define RDMA_REGION_6__ADDR_LSB 13 +#define RDMA_REGION_6__ADDR_MASK 0xffffe000 +#define RDMA_REGION_6__ADDR_GET(x) (((x) & RDMA_REGION_6__ADDR_MASK) >> RDMA_REGION_6__ADDR_LSB) +#define RDMA_REGION_6__ADDR_SET(x) (((x) << RDMA_REGION_6__ADDR_LSB) & RDMA_REGION_6__ADDR_MASK) +#define RDMA_REGION_6__LENGTH_MSB 12 +#define RDMA_REGION_6__LENGTH_LSB 2 +#define RDMA_REGION_6__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_6__LENGTH_GET(x) (((x) & RDMA_REGION_6__LENGTH_MASK) >> RDMA_REGION_6__LENGTH_LSB) +#define RDMA_REGION_6__LENGTH_SET(x) (((x) << RDMA_REGION_6__LENGTH_LSB) & RDMA_REGION_6__LENGTH_MASK) +#define RDMA_REGION_6__INDI_MSB 1 +#define RDMA_REGION_6__INDI_LSB 1 +#define RDMA_REGION_6__INDI_MASK 0x00000002 +#define RDMA_REGION_6__INDI_GET(x) (((x) & RDMA_REGION_6__INDI_MASK) >> RDMA_REGION_6__INDI_LSB) +#define RDMA_REGION_6__INDI_SET(x) (((x) << RDMA_REGION_6__INDI_LSB) & RDMA_REGION_6__INDI_MASK) +#define RDMA_REGION_6__NEXT_MSB 0 +#define RDMA_REGION_6__NEXT_LSB 0 +#define RDMA_REGION_6__NEXT_MASK 0x00000001 +#define RDMA_REGION_6__NEXT_GET(x) (((x) & RDMA_REGION_6__NEXT_MASK) >> RDMA_REGION_6__NEXT_LSB) +#define RDMA_REGION_6__NEXT_SET(x) (((x) << RDMA_REGION_6__NEXT_LSB) & RDMA_REGION_6__NEXT_MASK) + +#define RDMA_REGION_7__ADDRESS 0x0000003c +#define RDMA_REGION_7__OFFSET 0x0000003c +#define RDMA_REGION_7__ADDR_MSB 31 +#define RDMA_REGION_7__ADDR_LSB 13 +#define RDMA_REGION_7__ADDR_MASK 0xffffe000 +#define RDMA_REGION_7__ADDR_GET(x) (((x) & RDMA_REGION_7__ADDR_MASK) >> RDMA_REGION_7__ADDR_LSB) +#define RDMA_REGION_7__ADDR_SET(x) (((x) << RDMA_REGION_7__ADDR_LSB) & RDMA_REGION_7__ADDR_MASK) +#define RDMA_REGION_7__LENGTH_MSB 12 +#define RDMA_REGION_7__LENGTH_LSB 2 +#define RDMA_REGION_7__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_7__LENGTH_GET(x) (((x) & RDMA_REGION_7__LENGTH_MASK) >> RDMA_REGION_7__LENGTH_LSB) +#define RDMA_REGION_7__LENGTH_SET(x) (((x) << RDMA_REGION_7__LENGTH_LSB) & RDMA_REGION_7__LENGTH_MASK) +#define RDMA_REGION_7__INDI_MSB 1 +#define RDMA_REGION_7__INDI_LSB 1 +#define RDMA_REGION_7__INDI_MASK 0x00000002 +#define RDMA_REGION_7__INDI_GET(x) (((x) & RDMA_REGION_7__INDI_MASK) >> RDMA_REGION_7__INDI_LSB) +#define RDMA_REGION_7__INDI_SET(x) (((x) << RDMA_REGION_7__INDI_LSB) & RDMA_REGION_7__INDI_MASK) +#define RDMA_REGION_7__NEXT_MSB 0 +#define RDMA_REGION_7__NEXT_LSB 0 +#define RDMA_REGION_7__NEXT_MASK 0x00000001 +#define RDMA_REGION_7__NEXT_GET(x) (((x) & RDMA_REGION_7__NEXT_MASK) >> RDMA_REGION_7__NEXT_LSB) +#define RDMA_REGION_7__NEXT_SET(x) (((x) << RDMA_REGION_7__NEXT_LSB) & RDMA_REGION_7__NEXT_MASK) + +#define RDMA_REGION_8__ADDRESS 0x00000040 +#define RDMA_REGION_8__OFFSET 0x00000040 +#define RDMA_REGION_8__ADDR_MSB 31 +#define RDMA_REGION_8__ADDR_LSB 13 +#define RDMA_REGION_8__ADDR_MASK 0xffffe000 +#define RDMA_REGION_8__ADDR_GET(x) (((x) & RDMA_REGION_8__ADDR_MASK) >> RDMA_REGION_8__ADDR_LSB) +#define RDMA_REGION_8__ADDR_SET(x) (((x) << RDMA_REGION_8__ADDR_LSB) & RDMA_REGION_8__ADDR_MASK) +#define RDMA_REGION_8__LENGTH_MSB 12 +#define RDMA_REGION_8__LENGTH_LSB 2 +#define RDMA_REGION_8__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_8__LENGTH_GET(x) (((x) & RDMA_REGION_8__LENGTH_MASK) >> RDMA_REGION_8__LENGTH_LSB) +#define RDMA_REGION_8__LENGTH_SET(x) (((x) << RDMA_REGION_8__LENGTH_LSB) & RDMA_REGION_8__LENGTH_MASK) +#define RDMA_REGION_8__INDI_MSB 1 +#define RDMA_REGION_8__INDI_LSB 1 +#define RDMA_REGION_8__INDI_MASK 0x00000002 +#define RDMA_REGION_8__INDI_GET(x) (((x) & RDMA_REGION_8__INDI_MASK) >> RDMA_REGION_8__INDI_LSB) +#define RDMA_REGION_8__INDI_SET(x) (((x) << RDMA_REGION_8__INDI_LSB) & RDMA_REGION_8__INDI_MASK) +#define RDMA_REGION_8__NEXT_MSB 0 +#define RDMA_REGION_8__NEXT_LSB 0 +#define RDMA_REGION_8__NEXT_MASK 0x00000001 +#define RDMA_REGION_8__NEXT_GET(x) (((x) & RDMA_REGION_8__NEXT_MASK) >> RDMA_REGION_8__NEXT_LSB) +#define RDMA_REGION_8__NEXT_SET(x) (((x) << RDMA_REGION_8__NEXT_LSB) & RDMA_REGION_8__NEXT_MASK) + +#define RDMA_REGION_9__ADDRESS 0x00000044 +#define RDMA_REGION_9__OFFSET 0x00000044 +#define RDMA_REGION_9__ADDR_MSB 31 +#define RDMA_REGION_9__ADDR_LSB 13 +#define RDMA_REGION_9__ADDR_MASK 0xffffe000 +#define RDMA_REGION_9__ADDR_GET(x) (((x) & RDMA_REGION_9__ADDR_MASK) >> RDMA_REGION_9__ADDR_LSB) +#define RDMA_REGION_9__ADDR_SET(x) (((x) << RDMA_REGION_9__ADDR_LSB) & RDMA_REGION_9__ADDR_MASK) +#define RDMA_REGION_9__LENGTH_MSB 12 +#define RDMA_REGION_9__LENGTH_LSB 2 +#define RDMA_REGION_9__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_9__LENGTH_GET(x) (((x) & RDMA_REGION_9__LENGTH_MASK) >> RDMA_REGION_9__LENGTH_LSB) +#define RDMA_REGION_9__LENGTH_SET(x) (((x) << RDMA_REGION_9__LENGTH_LSB) & RDMA_REGION_9__LENGTH_MASK) +#define RDMA_REGION_9__INDI_MSB 1 +#define RDMA_REGION_9__INDI_LSB 1 +#define RDMA_REGION_9__INDI_MASK 0x00000002 +#define RDMA_REGION_9__INDI_GET(x) (((x) & RDMA_REGION_9__INDI_MASK) >> RDMA_REGION_9__INDI_LSB) +#define RDMA_REGION_9__INDI_SET(x) (((x) << RDMA_REGION_9__INDI_LSB) & RDMA_REGION_9__INDI_MASK) +#define RDMA_REGION_9__NEXT_MSB 0 +#define RDMA_REGION_9__NEXT_LSB 0 +#define RDMA_REGION_9__NEXT_MASK 0x00000001 +#define RDMA_REGION_9__NEXT_GET(x) (((x) & RDMA_REGION_9__NEXT_MASK) >> RDMA_REGION_9__NEXT_LSB) +#define RDMA_REGION_9__NEXT_SET(x) (((x) << RDMA_REGION_9__NEXT_LSB) & RDMA_REGION_9__NEXT_MASK) + +#define RDMA_REGION_10__ADDRESS 0x00000048 +#define RDMA_REGION_10__OFFSET 0x00000048 +#define RDMA_REGION_10__ADDR_MSB 31 +#define RDMA_REGION_10__ADDR_LSB 13 +#define RDMA_REGION_10__ADDR_MASK 0xffffe000 +#define RDMA_REGION_10__ADDR_GET(x) (((x) & RDMA_REGION_10__ADDR_MASK) >> RDMA_REGION_10__ADDR_LSB) +#define RDMA_REGION_10__ADDR_SET(x) (((x) << RDMA_REGION_10__ADDR_LSB) & RDMA_REGION_10__ADDR_MASK) +#define RDMA_REGION_10__LENGTH_MSB 12 +#define RDMA_REGION_10__LENGTH_LSB 2 +#define RDMA_REGION_10__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_10__LENGTH_GET(x) (((x) & RDMA_REGION_10__LENGTH_MASK) >> RDMA_REGION_10__LENGTH_LSB) +#define RDMA_REGION_10__LENGTH_SET(x) (((x) << RDMA_REGION_10__LENGTH_LSB) & RDMA_REGION_10__LENGTH_MASK) +#define RDMA_REGION_10__INDI_MSB 1 +#define RDMA_REGION_10__INDI_LSB 1 +#define RDMA_REGION_10__INDI_MASK 0x00000002 +#define RDMA_REGION_10__INDI_GET(x) (((x) & RDMA_REGION_10__INDI_MASK) >> RDMA_REGION_10__INDI_LSB) +#define RDMA_REGION_10__INDI_SET(x) (((x) << RDMA_REGION_10__INDI_LSB) & RDMA_REGION_10__INDI_MASK) +#define RDMA_REGION_10__NEXT_MSB 0 +#define RDMA_REGION_10__NEXT_LSB 0 +#define RDMA_REGION_10__NEXT_MASK 0x00000001 +#define RDMA_REGION_10__NEXT_GET(x) (((x) & RDMA_REGION_10__NEXT_MASK) >> RDMA_REGION_10__NEXT_LSB) +#define RDMA_REGION_10__NEXT_SET(x) (((x) << RDMA_REGION_10__NEXT_LSB) & RDMA_REGION_10__NEXT_MASK) + +#define RDMA_REGION_11__ADDRESS 0x0000004c +#define RDMA_REGION_11__OFFSET 0x0000004c +#define RDMA_REGION_11__ADDR_MSB 31 +#define RDMA_REGION_11__ADDR_LSB 13 +#define RDMA_REGION_11__ADDR_MASK 0xffffe000 +#define RDMA_REGION_11__ADDR_GET(x) (((x) & RDMA_REGION_11__ADDR_MASK) >> RDMA_REGION_11__ADDR_LSB) +#define RDMA_REGION_11__ADDR_SET(x) (((x) << RDMA_REGION_11__ADDR_LSB) & RDMA_REGION_11__ADDR_MASK) +#define RDMA_REGION_11__LENGTH_MSB 12 +#define RDMA_REGION_11__LENGTH_LSB 2 +#define RDMA_REGION_11__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_11__LENGTH_GET(x) (((x) & RDMA_REGION_11__LENGTH_MASK) >> RDMA_REGION_11__LENGTH_LSB) +#define RDMA_REGION_11__LENGTH_SET(x) (((x) << RDMA_REGION_11__LENGTH_LSB) & RDMA_REGION_11__LENGTH_MASK) +#define RDMA_REGION_11__INDI_MSB 1 +#define RDMA_REGION_11__INDI_LSB 1 +#define RDMA_REGION_11__INDI_MASK 0x00000002 +#define RDMA_REGION_11__INDI_GET(x) (((x) & RDMA_REGION_11__INDI_MASK) >> RDMA_REGION_11__INDI_LSB) +#define RDMA_REGION_11__INDI_SET(x) (((x) << RDMA_REGION_11__INDI_LSB) & RDMA_REGION_11__INDI_MASK) +#define RDMA_REGION_11__NEXT_MSB 0 +#define RDMA_REGION_11__NEXT_LSB 0 +#define RDMA_REGION_11__NEXT_MASK 0x00000001 +#define RDMA_REGION_11__NEXT_GET(x) (((x) & RDMA_REGION_11__NEXT_MASK) >> RDMA_REGION_11__NEXT_LSB) +#define RDMA_REGION_11__NEXT_SET(x) (((x) << RDMA_REGION_11__NEXT_LSB) & RDMA_REGION_11__NEXT_MASK) + +#define RDMA_REGION_12__ADDRESS 0x00000050 +#define RDMA_REGION_12__OFFSET 0x00000050 +#define RDMA_REGION_12__ADDR_MSB 31 +#define RDMA_REGION_12__ADDR_LSB 13 +#define RDMA_REGION_12__ADDR_MASK 0xffffe000 +#define RDMA_REGION_12__ADDR_GET(x) (((x) & RDMA_REGION_12__ADDR_MASK) >> RDMA_REGION_12__ADDR_LSB) +#define RDMA_REGION_12__ADDR_SET(x) (((x) << RDMA_REGION_12__ADDR_LSB) & RDMA_REGION_12__ADDR_MASK) +#define RDMA_REGION_12__LENGTH_MSB 12 +#define RDMA_REGION_12__LENGTH_LSB 2 +#define RDMA_REGION_12__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_12__LENGTH_GET(x) (((x) & RDMA_REGION_12__LENGTH_MASK) >> RDMA_REGION_12__LENGTH_LSB) +#define RDMA_REGION_12__LENGTH_SET(x) (((x) << RDMA_REGION_12__LENGTH_LSB) & RDMA_REGION_12__LENGTH_MASK) +#define RDMA_REGION_12__INDI_MSB 1 +#define RDMA_REGION_12__INDI_LSB 1 +#define RDMA_REGION_12__INDI_MASK 0x00000002 +#define RDMA_REGION_12__INDI_GET(x) (((x) & RDMA_REGION_12__INDI_MASK) >> RDMA_REGION_12__INDI_LSB) +#define RDMA_REGION_12__INDI_SET(x) (((x) << RDMA_REGION_12__INDI_LSB) & RDMA_REGION_12__INDI_MASK) +#define RDMA_REGION_12__NEXT_MSB 0 +#define RDMA_REGION_12__NEXT_LSB 0 +#define RDMA_REGION_12__NEXT_MASK 0x00000001 +#define RDMA_REGION_12__NEXT_GET(x) (((x) & RDMA_REGION_12__NEXT_MASK) >> RDMA_REGION_12__NEXT_LSB) +#define RDMA_REGION_12__NEXT_SET(x) (((x) << RDMA_REGION_12__NEXT_LSB) & RDMA_REGION_12__NEXT_MASK) + +#define RDMA_REGION_13__ADDRESS 0x00000054 +#define RDMA_REGION_13__OFFSET 0x00000054 +#define RDMA_REGION_13__ADDR_MSB 31 +#define RDMA_REGION_13__ADDR_LSB 13 +#define RDMA_REGION_13__ADDR_MASK 0xffffe000 +#define RDMA_REGION_13__ADDR_GET(x) (((x) & RDMA_REGION_13__ADDR_MASK) >> RDMA_REGION_13__ADDR_LSB) +#define RDMA_REGION_13__ADDR_SET(x) (((x) << RDMA_REGION_13__ADDR_LSB) & RDMA_REGION_13__ADDR_MASK) +#define RDMA_REGION_13__LENGTH_MSB 12 +#define RDMA_REGION_13__LENGTH_LSB 2 +#define RDMA_REGION_13__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_13__LENGTH_GET(x) (((x) & RDMA_REGION_13__LENGTH_MASK) >> RDMA_REGION_13__LENGTH_LSB) +#define RDMA_REGION_13__LENGTH_SET(x) (((x) << RDMA_REGION_13__LENGTH_LSB) & RDMA_REGION_13__LENGTH_MASK) +#define RDMA_REGION_13__INDI_MSB 1 +#define RDMA_REGION_13__INDI_LSB 1 +#define RDMA_REGION_13__INDI_MASK 0x00000002 +#define RDMA_REGION_13__INDI_GET(x) (((x) & RDMA_REGION_13__INDI_MASK) >> RDMA_REGION_13__INDI_LSB) +#define RDMA_REGION_13__INDI_SET(x) (((x) << RDMA_REGION_13__INDI_LSB) & RDMA_REGION_13__INDI_MASK) +#define RDMA_REGION_13__NEXT_MSB 0 +#define RDMA_REGION_13__NEXT_LSB 0 +#define RDMA_REGION_13__NEXT_MASK 0x00000001 +#define RDMA_REGION_13__NEXT_GET(x) (((x) & RDMA_REGION_13__NEXT_MASK) >> RDMA_REGION_13__NEXT_LSB) +#define RDMA_REGION_13__NEXT_SET(x) (((x) << RDMA_REGION_13__NEXT_LSB) & RDMA_REGION_13__NEXT_MASK) + +#define RDMA_REGION_14__ADDRESS 0x00000058 +#define RDMA_REGION_14__OFFSET 0x00000058 +#define RDMA_REGION_14__ADDR_MSB 31 +#define RDMA_REGION_14__ADDR_LSB 13 +#define RDMA_REGION_14__ADDR_MASK 0xffffe000 +#define RDMA_REGION_14__ADDR_GET(x) (((x) & RDMA_REGION_14__ADDR_MASK) >> RDMA_REGION_14__ADDR_LSB) +#define RDMA_REGION_14__ADDR_SET(x) (((x) << RDMA_REGION_14__ADDR_LSB) & RDMA_REGION_14__ADDR_MASK) +#define RDMA_REGION_14__LENGTH_MSB 12 +#define RDMA_REGION_14__LENGTH_LSB 2 +#define RDMA_REGION_14__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_14__LENGTH_GET(x) (((x) & RDMA_REGION_14__LENGTH_MASK) >> RDMA_REGION_14__LENGTH_LSB) +#define RDMA_REGION_14__LENGTH_SET(x) (((x) << RDMA_REGION_14__LENGTH_LSB) & RDMA_REGION_14__LENGTH_MASK) +#define RDMA_REGION_14__INDI_MSB 1 +#define RDMA_REGION_14__INDI_LSB 1 +#define RDMA_REGION_14__INDI_MASK 0x00000002 +#define RDMA_REGION_14__INDI_GET(x) (((x) & RDMA_REGION_14__INDI_MASK) >> RDMA_REGION_14__INDI_LSB) +#define RDMA_REGION_14__INDI_SET(x) (((x) << RDMA_REGION_14__INDI_LSB) & RDMA_REGION_14__INDI_MASK) +#define RDMA_REGION_14__NEXT_MSB 0 +#define RDMA_REGION_14__NEXT_LSB 0 +#define RDMA_REGION_14__NEXT_MASK 0x00000001 +#define RDMA_REGION_14__NEXT_GET(x) (((x) & RDMA_REGION_14__NEXT_MASK) >> RDMA_REGION_14__NEXT_LSB) +#define RDMA_REGION_14__NEXT_SET(x) (((x) << RDMA_REGION_14__NEXT_LSB) & RDMA_REGION_14__NEXT_MASK) + +#define RDMA_REGION_15__ADDRESS 0x0000005c +#define RDMA_REGION_15__OFFSET 0x0000005c +#define RDMA_REGION_15__ADDR_MSB 31 +#define RDMA_REGION_15__ADDR_LSB 13 +#define RDMA_REGION_15__ADDR_MASK 0xffffe000 +#define RDMA_REGION_15__ADDR_GET(x) (((x) & RDMA_REGION_15__ADDR_MASK) >> RDMA_REGION_15__ADDR_LSB) +#define RDMA_REGION_15__ADDR_SET(x) (((x) << RDMA_REGION_15__ADDR_LSB) & RDMA_REGION_15__ADDR_MASK) +#define RDMA_REGION_15__LENGTH_MSB 12 +#define RDMA_REGION_15__LENGTH_LSB 2 +#define RDMA_REGION_15__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_15__LENGTH_GET(x) (((x) & RDMA_REGION_15__LENGTH_MASK) >> RDMA_REGION_15__LENGTH_LSB) +#define RDMA_REGION_15__LENGTH_SET(x) (((x) << RDMA_REGION_15__LENGTH_LSB) & RDMA_REGION_15__LENGTH_MASK) +#define RDMA_REGION_15__INDI_MSB 1 +#define RDMA_REGION_15__INDI_LSB 1 +#define RDMA_REGION_15__INDI_MASK 0x00000002 +#define RDMA_REGION_15__INDI_GET(x) (((x) & RDMA_REGION_15__INDI_MASK) >> RDMA_REGION_15__INDI_LSB) +#define RDMA_REGION_15__INDI_SET(x) (((x) << RDMA_REGION_15__INDI_LSB) & RDMA_REGION_15__INDI_MASK) +#define RDMA_REGION_15__NEXT_MSB 0 +#define RDMA_REGION_15__NEXT_LSB 0 +#define RDMA_REGION_15__NEXT_MASK 0x00000001 +#define RDMA_REGION_15__NEXT_GET(x) (((x) & RDMA_REGION_15__NEXT_MASK) >> RDMA_REGION_15__NEXT_LSB) +#define RDMA_REGION_15__NEXT_SET(x) (((x) << RDMA_REGION_15__NEXT_LSB) & RDMA_REGION_15__NEXT_MASK) + +#define DMA_STATUS_ADDRESS 0x00000060 +#define DMA_STATUS_OFFSET 0x00000060 +#define DMA_STATUS_ERROR_CODE_MSB 14 +#define DMA_STATUS_ERROR_CODE_LSB 4 +#define DMA_STATUS_ERROR_CODE_MASK 0x00007ff0 +#define DMA_STATUS_ERROR_CODE_GET(x) (((x) & DMA_STATUS_ERROR_CODE_MASK) >> DMA_STATUS_ERROR_CODE_LSB) +#define DMA_STATUS_ERROR_CODE_SET(x) (((x) << DMA_STATUS_ERROR_CODE_LSB) & DMA_STATUS_ERROR_CODE_MASK) +#define DMA_STATUS_ERROR_MSB 3 +#define DMA_STATUS_ERROR_LSB 3 +#define DMA_STATUS_ERROR_MASK 0x00000008 +#define DMA_STATUS_ERROR_GET(x) (((x) & DMA_STATUS_ERROR_MASK) >> DMA_STATUS_ERROR_LSB) +#define DMA_STATUS_ERROR_SET(x) (((x) << DMA_STATUS_ERROR_LSB) & DMA_STATUS_ERROR_MASK) +#define DMA_STATUS_DONE_MSB 2 +#define DMA_STATUS_DONE_LSB 2 +#define DMA_STATUS_DONE_MASK 0x00000004 +#define DMA_STATUS_DONE_GET(x) (((x) & DMA_STATUS_DONE_MASK) >> DMA_STATUS_DONE_LSB) +#define DMA_STATUS_DONE_SET(x) (((x) << DMA_STATUS_DONE_LSB) & DMA_STATUS_DONE_MASK) +#define DMA_STATUS_STOPPED_MSB 1 +#define DMA_STATUS_STOPPED_LSB 1 +#define DMA_STATUS_STOPPED_MASK 0x00000002 +#define DMA_STATUS_STOPPED_GET(x) (((x) & DMA_STATUS_STOPPED_MASK) >> DMA_STATUS_STOPPED_LSB) +#define DMA_STATUS_STOPPED_SET(x) (((x) << DMA_STATUS_STOPPED_LSB) & DMA_STATUS_STOPPED_MASK) +#define DMA_STATUS_RUNNING_MSB 0 +#define DMA_STATUS_RUNNING_LSB 0 +#define DMA_STATUS_RUNNING_MASK 0x00000001 +#define DMA_STATUS_RUNNING_GET(x) (((x) & DMA_STATUS_RUNNING_MASK) >> DMA_STATUS_RUNNING_LSB) +#define DMA_STATUS_RUNNING_SET(x) (((x) << DMA_STATUS_RUNNING_LSB) & DMA_STATUS_RUNNING_MASK) + +#define DMA_INT_EN_ADDRESS 0x00000064 +#define DMA_INT_EN_OFFSET 0x00000064 +#define DMA_INT_EN_ERROR_ENA_MSB 3 +#define DMA_INT_EN_ERROR_ENA_LSB 3 +#define DMA_INT_EN_ERROR_ENA_MASK 0x00000008 +#define DMA_INT_EN_ERROR_ENA_GET(x) (((x) & DMA_INT_EN_ERROR_ENA_MASK) >> DMA_INT_EN_ERROR_ENA_LSB) +#define DMA_INT_EN_ERROR_ENA_SET(x) (((x) << DMA_INT_EN_ERROR_ENA_LSB) & DMA_INT_EN_ERROR_ENA_MASK) +#define DMA_INT_EN_DONE_ENA_MSB 2 +#define DMA_INT_EN_DONE_ENA_LSB 2 +#define DMA_INT_EN_DONE_ENA_MASK 0x00000004 +#define DMA_INT_EN_DONE_ENA_GET(x) (((x) & DMA_INT_EN_DONE_ENA_MASK) >> DMA_INT_EN_DONE_ENA_LSB) +#define DMA_INT_EN_DONE_ENA_SET(x) (((x) << DMA_INT_EN_DONE_ENA_LSB) & DMA_INT_EN_DONE_ENA_MASK) +#define DMA_INT_EN_STOPPED_ENA_MSB 1 +#define DMA_INT_EN_STOPPED_ENA_LSB 1 +#define DMA_INT_EN_STOPPED_ENA_MASK 0x00000002 +#define DMA_INT_EN_STOPPED_ENA_GET(x) (((x) & DMA_INT_EN_STOPPED_ENA_MASK) >> DMA_INT_EN_STOPPED_ENA_LSB) +#define DMA_INT_EN_STOPPED_ENA_SET(x) (((x) << DMA_INT_EN_STOPPED_ENA_LSB) & DMA_INT_EN_STOPPED_ENA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct rdma_reg_reg_s { + volatile unsigned int dma_config; + volatile unsigned int dma_control; + volatile unsigned int dma_src; + volatile unsigned int dma_dest; + volatile unsigned int dma_length; + volatile unsigned int vmc_base; + volatile unsigned int indirect_reg; + volatile unsigned int indirect_return; + volatile unsigned int rdma_region_0_; + volatile unsigned int rdma_region_1_; + volatile unsigned int rdma_region_2_; + volatile unsigned int rdma_region_3_; + volatile unsigned int rdma_region_4_; + volatile unsigned int rdma_region_5_; + volatile unsigned int rdma_region_6_; + volatile unsigned int rdma_region_7_; + volatile unsigned int rdma_region_8_; + volatile unsigned int rdma_region_9_; + volatile unsigned int rdma_region_10_; + volatile unsigned int rdma_region_11_; + volatile unsigned int rdma_region_12_; + volatile unsigned int rdma_region_13_; + volatile unsigned int rdma_region_14_; + volatile unsigned int rdma_region_15_; + volatile unsigned int dma_status; + volatile unsigned int dma_int_en; +} rdma_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _RDMA_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_reg.h new file mode 100644 index 000000000000..0855de5f1400 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_reg.h @@ -0,0 +1,975 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "rtc_wlan_reg.h" + + +#ifndef BT_HEADERS + +#define RESET_CONTROL_ADDRESS WLAN_RESET_CONTROL_ADDRESS +#define RESET_CONTROL_OFFSET WLAN_RESET_CONTROL_OFFSET +#define RESET_CONTROL_DEBUG_UART_RST_MSB WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB +#define RESET_CONTROL_DEBUG_UART_RST_LSB WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB +#define RESET_CONTROL_DEBUG_UART_RST_MASK WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK +#define RESET_CONTROL_DEBUG_UART_RST_GET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x) +#define RESET_CONTROL_DEBUG_UART_RST_SET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x) +#define RESET_CONTROL_BB_COLD_RST_MSB WLAN_RESET_CONTROL_BB_COLD_RST_MSB +#define RESET_CONTROL_BB_COLD_RST_LSB WLAN_RESET_CONTROL_BB_COLD_RST_LSB +#define RESET_CONTROL_BB_COLD_RST_MASK WLAN_RESET_CONTROL_BB_COLD_RST_MASK +#define RESET_CONTROL_BB_COLD_RST_GET(x) WLAN_RESET_CONTROL_BB_COLD_RST_GET(x) +#define RESET_CONTROL_BB_COLD_RST_SET(x) WLAN_RESET_CONTROL_BB_COLD_RST_SET(x) +#define RESET_CONTROL_BB_WARM_RST_MSB WLAN_RESET_CONTROL_BB_WARM_RST_MSB +#define RESET_CONTROL_BB_WARM_RST_LSB WLAN_RESET_CONTROL_BB_WARM_RST_LSB +#define RESET_CONTROL_BB_WARM_RST_MASK WLAN_RESET_CONTROL_BB_WARM_RST_MASK +#define RESET_CONTROL_BB_WARM_RST_GET(x) WLAN_RESET_CONTROL_BB_WARM_RST_GET(x) +#define RESET_CONTROL_BB_WARM_RST_SET(x) WLAN_RESET_CONTROL_BB_WARM_RST_SET(x) +#define RESET_CONTROL_CPU_INIT_RESET_MSB WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB +#define RESET_CONTROL_CPU_INIT_RESET_LSB WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB +#define RESET_CONTROL_CPU_INIT_RESET_MASK WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK +#define RESET_CONTROL_CPU_INIT_RESET_GET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x) +#define RESET_CONTROL_CPU_INIT_RESET_SET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x) +#define RESET_CONTROL_VMC_REMAP_RESET_MSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB +#define RESET_CONTROL_VMC_REMAP_RESET_LSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB +#define RESET_CONTROL_VMC_REMAP_RESET_MASK WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK +#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x) +#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x) +#define RESET_CONTROL_RST_OUT_MSB WLAN_RESET_CONTROL_RST_OUT_MSB +#define RESET_CONTROL_RST_OUT_LSB WLAN_RESET_CONTROL_RST_OUT_LSB +#define RESET_CONTROL_RST_OUT_MASK WLAN_RESET_CONTROL_RST_OUT_MASK +#define RESET_CONTROL_RST_OUT_GET(x) WLAN_RESET_CONTROL_RST_OUT_GET(x) +#define RESET_CONTROL_RST_OUT_SET(x) WLAN_RESET_CONTROL_RST_OUT_SET(x) +#define RESET_CONTROL_COLD_RST_MSB WLAN_RESET_CONTROL_COLD_RST_MSB +#define RESET_CONTROL_COLD_RST_LSB WLAN_RESET_CONTROL_COLD_RST_LSB +#define RESET_CONTROL_COLD_RST_MASK WLAN_RESET_CONTROL_COLD_RST_MASK +#define RESET_CONTROL_COLD_RST_GET(x) WLAN_RESET_CONTROL_COLD_RST_GET(x) +#define RESET_CONTROL_COLD_RST_SET(x) WLAN_RESET_CONTROL_COLD_RST_SET(x) +#define RESET_CONTROL_WARM_RST_MSB WLAN_RESET_CONTROL_WARM_RST_MSB +#define RESET_CONTROL_WARM_RST_LSB WLAN_RESET_CONTROL_WARM_RST_LSB +#define RESET_CONTROL_WARM_RST_MASK WLAN_RESET_CONTROL_WARM_RST_MASK +#define RESET_CONTROL_WARM_RST_GET(x) WLAN_RESET_CONTROL_WARM_RST_GET(x) +#define RESET_CONTROL_WARM_RST_SET(x) WLAN_RESET_CONTROL_WARM_RST_SET(x) +#define RESET_CONTROL_CPU_WARM_RST_MSB WLAN_RESET_CONTROL_CPU_WARM_RST_MSB +#define RESET_CONTROL_CPU_WARM_RST_LSB WLAN_RESET_CONTROL_CPU_WARM_RST_LSB +#define RESET_CONTROL_CPU_WARM_RST_MASK WLAN_RESET_CONTROL_CPU_WARM_RST_MASK +#define RESET_CONTROL_CPU_WARM_RST_GET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x) +#define RESET_CONTROL_CPU_WARM_RST_SET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x) +#define RESET_CONTROL_MAC_COLD_RST_MSB WLAN_RESET_CONTROL_MAC_COLD_RST_MSB +#define RESET_CONTROL_MAC_COLD_RST_LSB WLAN_RESET_CONTROL_MAC_COLD_RST_LSB +#define RESET_CONTROL_MAC_COLD_RST_MASK WLAN_RESET_CONTROL_MAC_COLD_RST_MASK +#define RESET_CONTROL_MAC_COLD_RST_GET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x) +#define RESET_CONTROL_MAC_COLD_RST_SET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x) +#define RESET_CONTROL_MAC_WARM_RST_MSB WLAN_RESET_CONTROL_MAC_WARM_RST_MSB +#define RESET_CONTROL_MAC_WARM_RST_LSB WLAN_RESET_CONTROL_MAC_WARM_RST_LSB +#define RESET_CONTROL_MAC_WARM_RST_MASK WLAN_RESET_CONTROL_MAC_WARM_RST_MASK +#define RESET_CONTROL_MAC_WARM_RST_GET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x) +#define RESET_CONTROL_MAC_WARM_RST_SET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x) +#define RESET_CONTROL_MBOX_RST_MSB WLAN_RESET_CONTROL_MBOX_RST_MSB +#define RESET_CONTROL_MBOX_RST_LSB WLAN_RESET_CONTROL_MBOX_RST_LSB +#define RESET_CONTROL_MBOX_RST_MASK WLAN_RESET_CONTROL_MBOX_RST_MASK +#define RESET_CONTROL_MBOX_RST_GET(x) WLAN_RESET_CONTROL_MBOX_RST_GET(x) +#define RESET_CONTROL_MBOX_RST_SET(x) WLAN_RESET_CONTROL_MBOX_RST_SET(x) +#define RESET_CONTROL_UART_RST_MSB WLAN_RESET_CONTROL_UART_RST_MSB +#define RESET_CONTROL_UART_RST_LSB WLAN_RESET_CONTROL_UART_RST_LSB +#define RESET_CONTROL_UART_RST_MASK WLAN_RESET_CONTROL_UART_RST_MASK +#define RESET_CONTROL_UART_RST_GET(x) WLAN_RESET_CONTROL_UART_RST_GET(x) +#define RESET_CONTROL_UART_RST_SET(x) WLAN_RESET_CONTROL_UART_RST_SET(x) +#define RESET_CONTROL_SI0_RST_MSB WLAN_RESET_CONTROL_SI0_RST_MSB +#define RESET_CONTROL_SI0_RST_LSB WLAN_RESET_CONTROL_SI0_RST_LSB +#define RESET_CONTROL_SI0_RST_MASK WLAN_RESET_CONTROL_SI0_RST_MASK +#define RESET_CONTROL_SI0_RST_GET(x) WLAN_RESET_CONTROL_SI0_RST_GET(x) +#define RESET_CONTROL_SI0_RST_SET(x) WLAN_RESET_CONTROL_SI0_RST_SET(x) +#define XTAL_CONTROL_ADDRESS WLAN_XTAL_CONTROL_ADDRESS +#define XTAL_CONTROL_OFFSET WLAN_XTAL_CONTROL_OFFSET +#define XTAL_CONTROL_TCXO_MSB WLAN_XTAL_CONTROL_TCXO_MSB +#define XTAL_CONTROL_TCXO_LSB WLAN_XTAL_CONTROL_TCXO_LSB +#define XTAL_CONTROL_TCXO_MASK WLAN_XTAL_CONTROL_TCXO_MASK +#define XTAL_CONTROL_TCXO_GET(x) WLAN_XTAL_CONTROL_TCXO_GET(x) +#define XTAL_CONTROL_TCXO_SET(x) WLAN_XTAL_CONTROL_TCXO_SET(x) +#define TCXO_DETECT_ADDRESS WLAN_TCXO_DETECT_ADDRESS +#define TCXO_DETECT_OFFSET WLAN_TCXO_DETECT_OFFSET +#define TCXO_DETECT_PRESENT_MSB WLAN_TCXO_DETECT_PRESENT_MSB +#define TCXO_DETECT_PRESENT_LSB WLAN_TCXO_DETECT_PRESENT_LSB +#define TCXO_DETECT_PRESENT_MASK WLAN_TCXO_DETECT_PRESENT_MASK +#define TCXO_DETECT_PRESENT_GET(x) WLAN_TCXO_DETECT_PRESENT_GET(x) +#define TCXO_DETECT_PRESENT_SET(x) WLAN_TCXO_DETECT_PRESENT_SET(x) +#define XTAL_TEST_ADDRESS WLAN_XTAL_TEST_ADDRESS +#define XTAL_TEST_OFFSET WLAN_XTAL_TEST_OFFSET +#define XTAL_TEST_NOTCXODET_MSB WLAN_XTAL_TEST_NOTCXODET_MSB +#define XTAL_TEST_NOTCXODET_LSB WLAN_XTAL_TEST_NOTCXODET_LSB +#define XTAL_TEST_NOTCXODET_MASK WLAN_XTAL_TEST_NOTCXODET_MASK +#define XTAL_TEST_NOTCXODET_GET(x) WLAN_XTAL_TEST_NOTCXODET_GET(x) +#define XTAL_TEST_NOTCXODET_SET(x) WLAN_XTAL_TEST_NOTCXODET_SET(x) +#define QUADRATURE_ADDRESS WLAN_QUADRATURE_ADDRESS +#define QUADRATURE_OFFSET WLAN_QUADRATURE_OFFSET +#define QUADRATURE_ADC_MSB WLAN_QUADRATURE_ADC_MSB +#define QUADRATURE_ADC_LSB WLAN_QUADRATURE_ADC_LSB +#define QUADRATURE_ADC_MASK WLAN_QUADRATURE_ADC_MASK +#define QUADRATURE_ADC_GET(x) WLAN_QUADRATURE_ADC_GET(x) +#define QUADRATURE_ADC_SET(x) WLAN_QUADRATURE_ADC_SET(x) +#define QUADRATURE_SEL_MSB WLAN_QUADRATURE_SEL_MSB +#define QUADRATURE_SEL_LSB WLAN_QUADRATURE_SEL_LSB +#define QUADRATURE_SEL_MASK WLAN_QUADRATURE_SEL_MASK +#define QUADRATURE_SEL_GET(x) WLAN_QUADRATURE_SEL_GET(x) +#define QUADRATURE_SEL_SET(x) WLAN_QUADRATURE_SEL_SET(x) +#define QUADRATURE_DAC_MSB WLAN_QUADRATURE_DAC_MSB +#define QUADRATURE_DAC_LSB WLAN_QUADRATURE_DAC_LSB +#define QUADRATURE_DAC_MASK WLAN_QUADRATURE_DAC_MASK +#define QUADRATURE_DAC_GET(x) WLAN_QUADRATURE_DAC_GET(x) +#define QUADRATURE_DAC_SET(x) WLAN_QUADRATURE_DAC_SET(x) +#define PLL_CONTROL_ADDRESS WLAN_PLL_CONTROL_ADDRESS +#define PLL_CONTROL_OFFSET WLAN_PLL_CONTROL_OFFSET +#define PLL_CONTROL_DIG_TEST_CLK_MSB WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB +#define PLL_CONTROL_DIG_TEST_CLK_LSB WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB +#define PLL_CONTROL_DIG_TEST_CLK_MASK WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK +#define PLL_CONTROL_DIG_TEST_CLK_GET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x) +#define PLL_CONTROL_DIG_TEST_CLK_SET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x) +#define PLL_CONTROL_MAC_OVERRIDE_MSB WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB +#define PLL_CONTROL_MAC_OVERRIDE_LSB WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB +#define PLL_CONTROL_MAC_OVERRIDE_MASK WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK +#define PLL_CONTROL_MAC_OVERRIDE_GET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x) +#define PLL_CONTROL_MAC_OVERRIDE_SET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x) +#define PLL_CONTROL_NOPWD_MSB WLAN_PLL_CONTROL_NOPWD_MSB +#define PLL_CONTROL_NOPWD_LSB WLAN_PLL_CONTROL_NOPWD_LSB +#define PLL_CONTROL_NOPWD_MASK WLAN_PLL_CONTROL_NOPWD_MASK +#define PLL_CONTROL_NOPWD_GET(x) WLAN_PLL_CONTROL_NOPWD_GET(x) +#define PLL_CONTROL_NOPWD_SET(x) WLAN_PLL_CONTROL_NOPWD_SET(x) +#define PLL_CONTROL_UPDATING_MSB WLAN_PLL_CONTROL_UPDATING_MSB +#define PLL_CONTROL_UPDATING_LSB WLAN_PLL_CONTROL_UPDATING_LSB +#define PLL_CONTROL_UPDATING_MASK WLAN_PLL_CONTROL_UPDATING_MASK +#define PLL_CONTROL_UPDATING_GET(x) WLAN_PLL_CONTROL_UPDATING_GET(x) +#define PLL_CONTROL_UPDATING_SET(x) WLAN_PLL_CONTROL_UPDATING_SET(x) +#define PLL_CONTROL_BYPASS_MSB WLAN_PLL_CONTROL_BYPASS_MSB +#define PLL_CONTROL_BYPASS_LSB WLAN_PLL_CONTROL_BYPASS_LSB +#define PLL_CONTROL_BYPASS_MASK WLAN_PLL_CONTROL_BYPASS_MASK +#define PLL_CONTROL_BYPASS_GET(x) WLAN_PLL_CONTROL_BYPASS_GET(x) +#define PLL_CONTROL_BYPASS_SET(x) WLAN_PLL_CONTROL_BYPASS_SET(x) +#define PLL_CONTROL_REFDIV_MSB WLAN_PLL_CONTROL_REFDIV_MSB +#define PLL_CONTROL_REFDIV_LSB WLAN_PLL_CONTROL_REFDIV_LSB +#define PLL_CONTROL_REFDIV_MASK WLAN_PLL_CONTROL_REFDIV_MASK +#define PLL_CONTROL_REFDIV_GET(x) WLAN_PLL_CONTROL_REFDIV_GET(x) +#define PLL_CONTROL_REFDIV_SET(x) WLAN_PLL_CONTROL_REFDIV_SET(x) +#define PLL_CONTROL_DIV_MSB WLAN_PLL_CONTROL_DIV_MSB +#define PLL_CONTROL_DIV_LSB WLAN_PLL_CONTROL_DIV_LSB +#define PLL_CONTROL_DIV_MASK WLAN_PLL_CONTROL_DIV_MASK +#define PLL_CONTROL_DIV_GET(x) WLAN_PLL_CONTROL_DIV_GET(x) +#define PLL_CONTROL_DIV_SET(x) WLAN_PLL_CONTROL_DIV_SET(x) +#define PLL_SETTLE_ADDRESS WLAN_PLL_SETTLE_ADDRESS +#define PLL_SETTLE_OFFSET WLAN_PLL_SETTLE_OFFSET +#define PLL_SETTLE_TIME_MSB WLAN_PLL_SETTLE_TIME_MSB +#define PLL_SETTLE_TIME_LSB WLAN_PLL_SETTLE_TIME_LSB +#define PLL_SETTLE_TIME_MASK WLAN_PLL_SETTLE_TIME_MASK +#define PLL_SETTLE_TIME_GET(x) WLAN_PLL_SETTLE_TIME_GET(x) +#define PLL_SETTLE_TIME_SET(x) WLAN_PLL_SETTLE_TIME_SET(x) +#define XTAL_SETTLE_ADDRESS WLAN_XTAL_SETTLE_ADDRESS +#define XTAL_SETTLE_OFFSET WLAN_XTAL_SETTLE_OFFSET +#define XTAL_SETTLE_TIME_MSB WLAN_XTAL_SETTLE_TIME_MSB +#define XTAL_SETTLE_TIME_LSB WLAN_XTAL_SETTLE_TIME_LSB +#define XTAL_SETTLE_TIME_MASK WLAN_XTAL_SETTLE_TIME_MASK +#define XTAL_SETTLE_TIME_GET(x) WLAN_XTAL_SETTLE_TIME_GET(x) +#define XTAL_SETTLE_TIME_SET(x) WLAN_XTAL_SETTLE_TIME_SET(x) +#define CPU_CLOCK_ADDRESS WLAN_CPU_CLOCK_ADDRESS +#define CPU_CLOCK_OFFSET WLAN_CPU_CLOCK_OFFSET +#define CPU_CLOCK_STANDARD_MSB WLAN_CPU_CLOCK_STANDARD_MSB +#define CPU_CLOCK_STANDARD_LSB WLAN_CPU_CLOCK_STANDARD_LSB +#define CPU_CLOCK_STANDARD_MASK WLAN_CPU_CLOCK_STANDARD_MASK +#define CPU_CLOCK_STANDARD_GET(x) WLAN_CPU_CLOCK_STANDARD_GET(x) +#define CPU_CLOCK_STANDARD_SET(x) WLAN_CPU_CLOCK_STANDARD_SET(x) +#define CLOCK_OUT_ADDRESS WLAN_CLOCK_OUT_ADDRESS +#define CLOCK_OUT_OFFSET WLAN_CLOCK_OUT_OFFSET +#define CLOCK_OUT_SELECT_MSB WLAN_CLOCK_OUT_SELECT_MSB +#define CLOCK_OUT_SELECT_LSB WLAN_CLOCK_OUT_SELECT_LSB +#define CLOCK_OUT_SELECT_MASK WLAN_CLOCK_OUT_SELECT_MASK +#define CLOCK_OUT_SELECT_GET(x) WLAN_CLOCK_OUT_SELECT_GET(x) +#define CLOCK_OUT_SELECT_SET(x) WLAN_CLOCK_OUT_SELECT_SET(x) +#define CLOCK_CONTROL_ADDRESS WLAN_CLOCK_CONTROL_ADDRESS +#define CLOCK_CONTROL_OFFSET WLAN_CLOCK_CONTROL_OFFSET +#define CLOCK_CONTROL_LF_CLK32_MSB WLAN_CLOCK_CONTROL_LF_CLK32_MSB +#define CLOCK_CONTROL_LF_CLK32_LSB WLAN_CLOCK_CONTROL_LF_CLK32_LSB +#define CLOCK_CONTROL_LF_CLK32_MASK WLAN_CLOCK_CONTROL_LF_CLK32_MASK +#define CLOCK_CONTROL_LF_CLK32_GET(x) WLAN_CLOCK_CONTROL_LF_CLK32_GET(x) +#define CLOCK_CONTROL_LF_CLK32_SET(x) WLAN_CLOCK_CONTROL_LF_CLK32_SET(x) +#define CLOCK_CONTROL_SI0_CLK_MSB WLAN_CLOCK_CONTROL_SI0_CLK_MSB +#define CLOCK_CONTROL_SI0_CLK_LSB WLAN_CLOCK_CONTROL_SI0_CLK_LSB +#define CLOCK_CONTROL_SI0_CLK_MASK WLAN_CLOCK_CONTROL_SI0_CLK_MASK +#define CLOCK_CONTROL_SI0_CLK_GET(x) WLAN_CLOCK_CONTROL_SI0_CLK_GET(x) +#define CLOCK_CONTROL_SI0_CLK_SET(x) WLAN_CLOCK_CONTROL_SI0_CLK_SET(x) +#define BIAS_OVERRIDE_ADDRESS WLAN_BIAS_OVERRIDE_ADDRESS +#define BIAS_OVERRIDE_OFFSET WLAN_BIAS_OVERRIDE_OFFSET +#define BIAS_OVERRIDE_ON_MSB WLAN_BIAS_OVERRIDE_ON_MSB +#define BIAS_OVERRIDE_ON_LSB WLAN_BIAS_OVERRIDE_ON_LSB +#define BIAS_OVERRIDE_ON_MASK WLAN_BIAS_OVERRIDE_ON_MASK +#define BIAS_OVERRIDE_ON_GET(x) WLAN_BIAS_OVERRIDE_ON_GET(x) +#define BIAS_OVERRIDE_ON_SET(x) WLAN_BIAS_OVERRIDE_ON_SET(x) +#define WDT_CONTROL_ADDRESS WLAN_WDT_CONTROL_ADDRESS +#define WDT_CONTROL_OFFSET WLAN_WDT_CONTROL_OFFSET +#define WDT_CONTROL_ACTION_MSB WLAN_WDT_CONTROL_ACTION_MSB +#define WDT_CONTROL_ACTION_LSB WLAN_WDT_CONTROL_ACTION_LSB +#define WDT_CONTROL_ACTION_MASK WLAN_WDT_CONTROL_ACTION_MASK +#define WDT_CONTROL_ACTION_GET(x) WLAN_WDT_CONTROL_ACTION_GET(x) +#define WDT_CONTROL_ACTION_SET(x) WLAN_WDT_CONTROL_ACTION_SET(x) +#define WDT_STATUS_ADDRESS WLAN_WDT_STATUS_ADDRESS +#define WDT_STATUS_OFFSET WLAN_WDT_STATUS_OFFSET +#define WDT_STATUS_INTERRUPT_MSB WLAN_WDT_STATUS_INTERRUPT_MSB +#define WDT_STATUS_INTERRUPT_LSB WLAN_WDT_STATUS_INTERRUPT_LSB +#define WDT_STATUS_INTERRUPT_MASK WLAN_WDT_STATUS_INTERRUPT_MASK +#define WDT_STATUS_INTERRUPT_GET(x) WLAN_WDT_STATUS_INTERRUPT_GET(x) +#define WDT_STATUS_INTERRUPT_SET(x) WLAN_WDT_STATUS_INTERRUPT_SET(x) +#define WDT_ADDRESS WLAN_WDT_ADDRESS +#define WDT_OFFSET WLAN_WDT_OFFSET +#define WDT_TARGET_MSB WLAN_WDT_TARGET_MSB +#define WDT_TARGET_LSB WLAN_WDT_TARGET_LSB +#define WDT_TARGET_MASK WLAN_WDT_TARGET_MASK +#define WDT_TARGET_GET(x) WLAN_WDT_TARGET_GET(x) +#define WDT_TARGET_SET(x) WLAN_WDT_TARGET_SET(x) +#define WDT_COUNT_ADDRESS WLAN_WDT_COUNT_ADDRESS +#define WDT_COUNT_OFFSET WLAN_WDT_COUNT_OFFSET +#define WDT_COUNT_VALUE_MSB WLAN_WDT_COUNT_VALUE_MSB +#define WDT_COUNT_VALUE_LSB WLAN_WDT_COUNT_VALUE_LSB +#define WDT_COUNT_VALUE_MASK WLAN_WDT_COUNT_VALUE_MASK +#define WDT_COUNT_VALUE_GET(x) WLAN_WDT_COUNT_VALUE_GET(x) +#define WDT_COUNT_VALUE_SET(x) WLAN_WDT_COUNT_VALUE_SET(x) +#define WDT_RESET_ADDRESS WLAN_WDT_RESET_ADDRESS +#define WDT_RESET_OFFSET WLAN_WDT_RESET_OFFSET +#define WDT_RESET_VALUE_MSB WLAN_WDT_RESET_VALUE_MSB +#define WDT_RESET_VALUE_LSB WLAN_WDT_RESET_VALUE_LSB +#define WDT_RESET_VALUE_MASK WLAN_WDT_RESET_VALUE_MASK +#define WDT_RESET_VALUE_GET(x) WLAN_WDT_RESET_VALUE_GET(x) +#define WDT_RESET_VALUE_SET(x) WLAN_WDT_RESET_VALUE_SET(x) +#define INT_STATUS_ADDRESS WLAN_INT_STATUS_ADDRESS +#define INT_STATUS_OFFSET WLAN_INT_STATUS_OFFSET +#define INT_STATUS_HCI_UART_MSB WLAN_INT_STATUS_HCI_UART_MSB +#define INT_STATUS_HCI_UART_LSB WLAN_INT_STATUS_HCI_UART_LSB +#define INT_STATUS_HCI_UART_MASK WLAN_INT_STATUS_HCI_UART_MASK +#define INT_STATUS_HCI_UART_GET(x) WLAN_INT_STATUS_HCI_UART_GET(x) +#define INT_STATUS_HCI_UART_SET(x) WLAN_INT_STATUS_HCI_UART_SET(x) +#define INT_STATUS_THERM_MSB WLAN_INT_STATUS_THERM_MSB +#define INT_STATUS_THERM_LSB WLAN_INT_STATUS_THERM_LSB +#define INT_STATUS_THERM_MASK WLAN_INT_STATUS_THERM_MASK +#define INT_STATUS_THERM_GET(x) WLAN_INT_STATUS_THERM_GET(x) +#define INT_STATUS_THERM_SET(x) WLAN_INT_STATUS_THERM_SET(x) +#define INT_STATUS_EFUSE_OVERWRITE_MSB WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB +#define INT_STATUS_EFUSE_OVERWRITE_LSB WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB +#define INT_STATUS_EFUSE_OVERWRITE_MASK WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK +#define INT_STATUS_EFUSE_OVERWRITE_GET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x) +#define INT_STATUS_EFUSE_OVERWRITE_SET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x) +#define INT_STATUS_UART_MBOX_MSB WLAN_INT_STATUS_UART_MBOX_MSB +#define INT_STATUS_UART_MBOX_LSB WLAN_INT_STATUS_UART_MBOX_LSB +#define INT_STATUS_UART_MBOX_MASK WLAN_INT_STATUS_UART_MBOX_MASK +#define INT_STATUS_UART_MBOX_GET(x) WLAN_INT_STATUS_UART_MBOX_GET(x) +#define INT_STATUS_UART_MBOX_SET(x) WLAN_INT_STATUS_UART_MBOX_SET(x) +#define INT_STATUS_GENERIC_MBOX_MSB WLAN_INT_STATUS_GENERIC_MBOX_MSB +#define INT_STATUS_GENERIC_MBOX_LSB WLAN_INT_STATUS_GENERIC_MBOX_LSB +#define INT_STATUS_GENERIC_MBOX_MASK WLAN_INT_STATUS_GENERIC_MBOX_MASK +#define INT_STATUS_GENERIC_MBOX_GET(x) WLAN_INT_STATUS_GENERIC_MBOX_GET(x) +#define INT_STATUS_GENERIC_MBOX_SET(x) WLAN_INT_STATUS_GENERIC_MBOX_SET(x) +#define INT_STATUS_RDMA_MSB WLAN_INT_STATUS_RDMA_MSB +#define INT_STATUS_RDMA_LSB WLAN_INT_STATUS_RDMA_LSB +#define INT_STATUS_RDMA_MASK WLAN_INT_STATUS_RDMA_MASK +#define INT_STATUS_RDMA_GET(x) WLAN_INT_STATUS_RDMA_GET(x) +#define INT_STATUS_RDMA_SET(x) WLAN_INT_STATUS_RDMA_SET(x) +#define INT_STATUS_BTCOEX_MSB WLAN_INT_STATUS_BTCOEX_MSB +#define INT_STATUS_BTCOEX_LSB WLAN_INT_STATUS_BTCOEX_LSB +#define INT_STATUS_BTCOEX_MASK WLAN_INT_STATUS_BTCOEX_MASK +#define INT_STATUS_BTCOEX_GET(x) WLAN_INT_STATUS_BTCOEX_GET(x) +#define INT_STATUS_BTCOEX_SET(x) WLAN_INT_STATUS_BTCOEX_SET(x) +#define INT_STATUS_RTC_POWER_MSB WLAN_INT_STATUS_RTC_POWER_MSB +#define INT_STATUS_RTC_POWER_LSB WLAN_INT_STATUS_RTC_POWER_LSB +#define INT_STATUS_RTC_POWER_MASK WLAN_INT_STATUS_RTC_POWER_MASK +#define INT_STATUS_RTC_POWER_GET(x) WLAN_INT_STATUS_RTC_POWER_GET(x) +#define INT_STATUS_RTC_POWER_SET(x) WLAN_INT_STATUS_RTC_POWER_SET(x) +#define INT_STATUS_MAC_MSB WLAN_INT_STATUS_MAC_MSB +#define INT_STATUS_MAC_LSB WLAN_INT_STATUS_MAC_LSB +#define INT_STATUS_MAC_MASK WLAN_INT_STATUS_MAC_MASK +#define INT_STATUS_MAC_GET(x) WLAN_INT_STATUS_MAC_GET(x) +#define INT_STATUS_MAC_SET(x) WLAN_INT_STATUS_MAC_SET(x) +#define INT_STATUS_MAILBOX_MSB WLAN_INT_STATUS_MAILBOX_MSB +#define INT_STATUS_MAILBOX_LSB WLAN_INT_STATUS_MAILBOX_LSB +#define INT_STATUS_MAILBOX_MASK WLAN_INT_STATUS_MAILBOX_MASK +#define INT_STATUS_MAILBOX_GET(x) WLAN_INT_STATUS_MAILBOX_GET(x) +#define INT_STATUS_MAILBOX_SET(x) WLAN_INT_STATUS_MAILBOX_SET(x) +#define INT_STATUS_RTC_ALARM_MSB WLAN_INT_STATUS_RTC_ALARM_MSB +#define INT_STATUS_RTC_ALARM_LSB WLAN_INT_STATUS_RTC_ALARM_LSB +#define INT_STATUS_RTC_ALARM_MASK WLAN_INT_STATUS_RTC_ALARM_MASK +#define INT_STATUS_RTC_ALARM_GET(x) WLAN_INT_STATUS_RTC_ALARM_GET(x) +#define INT_STATUS_RTC_ALARM_SET(x) WLAN_INT_STATUS_RTC_ALARM_SET(x) +#define INT_STATUS_HF_TIMER_MSB WLAN_INT_STATUS_HF_TIMER_MSB +#define INT_STATUS_HF_TIMER_LSB WLAN_INT_STATUS_HF_TIMER_LSB +#define INT_STATUS_HF_TIMER_MASK WLAN_INT_STATUS_HF_TIMER_MASK +#define INT_STATUS_HF_TIMER_GET(x) WLAN_INT_STATUS_HF_TIMER_GET(x) +#define INT_STATUS_HF_TIMER_SET(x) WLAN_INT_STATUS_HF_TIMER_SET(x) +#define INT_STATUS_LF_TIMER3_MSB WLAN_INT_STATUS_LF_TIMER3_MSB +#define INT_STATUS_LF_TIMER3_LSB WLAN_INT_STATUS_LF_TIMER3_LSB +#define INT_STATUS_LF_TIMER3_MASK WLAN_INT_STATUS_LF_TIMER3_MASK +#define INT_STATUS_LF_TIMER3_GET(x) WLAN_INT_STATUS_LF_TIMER3_GET(x) +#define INT_STATUS_LF_TIMER3_SET(x) WLAN_INT_STATUS_LF_TIMER3_SET(x) +#define INT_STATUS_LF_TIMER2_MSB WLAN_INT_STATUS_LF_TIMER2_MSB +#define INT_STATUS_LF_TIMER2_LSB WLAN_INT_STATUS_LF_TIMER2_LSB +#define INT_STATUS_LF_TIMER2_MASK WLAN_INT_STATUS_LF_TIMER2_MASK +#define INT_STATUS_LF_TIMER2_GET(x) WLAN_INT_STATUS_LF_TIMER2_GET(x) +#define INT_STATUS_LF_TIMER2_SET(x) WLAN_INT_STATUS_LF_TIMER2_SET(x) +#define INT_STATUS_LF_TIMER1_MSB WLAN_INT_STATUS_LF_TIMER1_MSB +#define INT_STATUS_LF_TIMER1_LSB WLAN_INT_STATUS_LF_TIMER1_LSB +#define INT_STATUS_LF_TIMER1_MASK WLAN_INT_STATUS_LF_TIMER1_MASK +#define INT_STATUS_LF_TIMER1_GET(x) WLAN_INT_STATUS_LF_TIMER1_GET(x) +#define INT_STATUS_LF_TIMER1_SET(x) WLAN_INT_STATUS_LF_TIMER1_SET(x) +#define INT_STATUS_LF_TIMER0_MSB WLAN_INT_STATUS_LF_TIMER0_MSB +#define INT_STATUS_LF_TIMER0_LSB WLAN_INT_STATUS_LF_TIMER0_LSB +#define INT_STATUS_LF_TIMER0_MASK WLAN_INT_STATUS_LF_TIMER0_MASK +#define INT_STATUS_LF_TIMER0_GET(x) WLAN_INT_STATUS_LF_TIMER0_GET(x) +#define INT_STATUS_LF_TIMER0_SET(x) WLAN_INT_STATUS_LF_TIMER0_SET(x) +#define INT_STATUS_KEYPAD_MSB WLAN_INT_STATUS_KEYPAD_MSB +#define INT_STATUS_KEYPAD_LSB WLAN_INT_STATUS_KEYPAD_LSB +#define INT_STATUS_KEYPAD_MASK WLAN_INT_STATUS_KEYPAD_MASK +#define INT_STATUS_KEYPAD_GET(x) WLAN_INT_STATUS_KEYPAD_GET(x) +#define INT_STATUS_KEYPAD_SET(x) WLAN_INT_STATUS_KEYPAD_SET(x) +#define INT_STATUS_SI_MSB WLAN_INT_STATUS_SI_MSB +#define INT_STATUS_SI_LSB WLAN_INT_STATUS_SI_LSB +#define INT_STATUS_SI_MASK WLAN_INT_STATUS_SI_MASK +#define INT_STATUS_SI_GET(x) WLAN_INT_STATUS_SI_GET(x) +#define INT_STATUS_SI_SET(x) WLAN_INT_STATUS_SI_SET(x) +#define INT_STATUS_GPIO_MSB WLAN_INT_STATUS_GPIO_MSB +#define INT_STATUS_GPIO_LSB WLAN_INT_STATUS_GPIO_LSB +#define INT_STATUS_GPIO_MASK WLAN_INT_STATUS_GPIO_MASK +#define INT_STATUS_GPIO_GET(x) WLAN_INT_STATUS_GPIO_GET(x) +#define INT_STATUS_GPIO_SET(x) WLAN_INT_STATUS_GPIO_SET(x) +#define INT_STATUS_UART_MSB WLAN_INT_STATUS_UART_MSB +#define INT_STATUS_UART_LSB WLAN_INT_STATUS_UART_LSB +#define INT_STATUS_UART_MASK WLAN_INT_STATUS_UART_MASK +#define INT_STATUS_UART_GET(x) WLAN_INT_STATUS_UART_GET(x) +#define INT_STATUS_UART_SET(x) WLAN_INT_STATUS_UART_SET(x) +#define INT_STATUS_ERROR_MSB WLAN_INT_STATUS_ERROR_MSB +#define INT_STATUS_ERROR_LSB WLAN_INT_STATUS_ERROR_LSB +#define INT_STATUS_ERROR_MASK WLAN_INT_STATUS_ERROR_MASK +#define INT_STATUS_ERROR_GET(x) WLAN_INT_STATUS_ERROR_GET(x) +#define INT_STATUS_ERROR_SET(x) WLAN_INT_STATUS_ERROR_SET(x) +#define INT_STATUS_WDT_INT_MSB WLAN_INT_STATUS_WDT_INT_MSB +#define INT_STATUS_WDT_INT_LSB WLAN_INT_STATUS_WDT_INT_LSB +#define INT_STATUS_WDT_INT_MASK WLAN_INT_STATUS_WDT_INT_MASK +#define INT_STATUS_WDT_INT_GET(x) WLAN_INT_STATUS_WDT_INT_GET(x) +#define INT_STATUS_WDT_INT_SET(x) WLAN_INT_STATUS_WDT_INT_SET(x) +#define LF_TIMER0_ADDRESS WLAN_LF_TIMER0_ADDRESS +#define LF_TIMER0_OFFSET WLAN_LF_TIMER0_OFFSET +#define LF_TIMER0_TARGET_MSB WLAN_LF_TIMER0_TARGET_MSB +#define LF_TIMER0_TARGET_LSB WLAN_LF_TIMER0_TARGET_LSB +#define LF_TIMER0_TARGET_MASK WLAN_LF_TIMER0_TARGET_MASK +#define LF_TIMER0_TARGET_GET(x) WLAN_LF_TIMER0_TARGET_GET(x) +#define LF_TIMER0_TARGET_SET(x) WLAN_LF_TIMER0_TARGET_SET(x) +#define LF_TIMER_COUNT0_ADDRESS WLAN_LF_TIMER_COUNT0_ADDRESS +#define LF_TIMER_COUNT0_OFFSET WLAN_LF_TIMER_COUNT0_OFFSET +#define LF_TIMER_COUNT0_VALUE_MSB WLAN_LF_TIMER_COUNT0_VALUE_MSB +#define LF_TIMER_COUNT0_VALUE_LSB WLAN_LF_TIMER_COUNT0_VALUE_LSB +#define LF_TIMER_COUNT0_VALUE_MASK WLAN_LF_TIMER_COUNT0_VALUE_MASK +#define LF_TIMER_COUNT0_VALUE_GET(x) WLAN_LF_TIMER_COUNT0_VALUE_GET(x) +#define LF_TIMER_COUNT0_VALUE_SET(x) WLAN_LF_TIMER_COUNT0_VALUE_SET(x) +#define LF_TIMER_CONTROL0_ADDRESS WLAN_LF_TIMER_CONTROL0_ADDRESS +#define LF_TIMER_CONTROL0_OFFSET WLAN_LF_TIMER_CONTROL0_OFFSET +#define LF_TIMER_CONTROL0_ENABLE_MSB WLAN_LF_TIMER_CONTROL0_ENABLE_MSB +#define LF_TIMER_CONTROL0_ENABLE_LSB WLAN_LF_TIMER_CONTROL0_ENABLE_LSB +#define LF_TIMER_CONTROL0_ENABLE_MASK WLAN_LF_TIMER_CONTROL0_ENABLE_MASK +#define LF_TIMER_CONTROL0_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x) +#define LF_TIMER_CONTROL0_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x) +#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB +#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB +#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK +#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) +#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) +#define LF_TIMER_CONTROL0_RESET_MSB WLAN_LF_TIMER_CONTROL0_RESET_MSB +#define LF_TIMER_CONTROL0_RESET_LSB WLAN_LF_TIMER_CONTROL0_RESET_LSB +#define LF_TIMER_CONTROL0_RESET_MASK WLAN_LF_TIMER_CONTROL0_RESET_MASK +#define LF_TIMER_CONTROL0_RESET_GET(x) WLAN_LF_TIMER_CONTROL0_RESET_GET(x) +#define LF_TIMER_CONTROL0_RESET_SET(x) WLAN_LF_TIMER_CONTROL0_RESET_SET(x) +#define LF_TIMER_STATUS0_ADDRESS WLAN_LF_TIMER_STATUS0_ADDRESS +#define LF_TIMER_STATUS0_OFFSET WLAN_LF_TIMER_STATUS0_OFFSET +#define LF_TIMER_STATUS0_INTERRUPT_MSB WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB +#define LF_TIMER_STATUS0_INTERRUPT_LSB WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB +#define LF_TIMER_STATUS0_INTERRUPT_MASK WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK +#define LF_TIMER_STATUS0_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x) +#define LF_TIMER_STATUS0_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x) +#define LF_TIMER1_ADDRESS WLAN_LF_TIMER1_ADDRESS +#define LF_TIMER1_OFFSET WLAN_LF_TIMER1_OFFSET +#define LF_TIMER1_TARGET_MSB WLAN_LF_TIMER1_TARGET_MSB +#define LF_TIMER1_TARGET_LSB WLAN_LF_TIMER1_TARGET_LSB +#define LF_TIMER1_TARGET_MASK WLAN_LF_TIMER1_TARGET_MASK +#define LF_TIMER1_TARGET_GET(x) WLAN_LF_TIMER1_TARGET_GET(x) +#define LF_TIMER1_TARGET_SET(x) WLAN_LF_TIMER1_TARGET_SET(x) +#define LF_TIMER_COUNT1_ADDRESS WLAN_LF_TIMER_COUNT1_ADDRESS +#define LF_TIMER_COUNT1_OFFSET WLAN_LF_TIMER_COUNT1_OFFSET +#define LF_TIMER_COUNT1_VALUE_MSB WLAN_LF_TIMER_COUNT1_VALUE_MSB +#define LF_TIMER_COUNT1_VALUE_LSB WLAN_LF_TIMER_COUNT1_VALUE_LSB +#define LF_TIMER_COUNT1_VALUE_MASK WLAN_LF_TIMER_COUNT1_VALUE_MASK +#define LF_TIMER_COUNT1_VALUE_GET(x) WLAN_LF_TIMER_COUNT1_VALUE_GET(x) +#define LF_TIMER_COUNT1_VALUE_SET(x) WLAN_LF_TIMER_COUNT1_VALUE_SET(x) +#define LF_TIMER_CONTROL1_ADDRESS WLAN_LF_TIMER_CONTROL1_ADDRESS +#define LF_TIMER_CONTROL1_OFFSET WLAN_LF_TIMER_CONTROL1_OFFSET +#define LF_TIMER_CONTROL1_ENABLE_MSB WLAN_LF_TIMER_CONTROL1_ENABLE_MSB +#define LF_TIMER_CONTROL1_ENABLE_LSB WLAN_LF_TIMER_CONTROL1_ENABLE_LSB +#define LF_TIMER_CONTROL1_ENABLE_MASK WLAN_LF_TIMER_CONTROL1_ENABLE_MASK +#define LF_TIMER_CONTROL1_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x) +#define LF_TIMER_CONTROL1_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x) +#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB +#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB +#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK +#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) +#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) +#define LF_TIMER_CONTROL1_RESET_MSB WLAN_LF_TIMER_CONTROL1_RESET_MSB +#define LF_TIMER_CONTROL1_RESET_LSB WLAN_LF_TIMER_CONTROL1_RESET_LSB +#define LF_TIMER_CONTROL1_RESET_MASK WLAN_LF_TIMER_CONTROL1_RESET_MASK +#define LF_TIMER_CONTROL1_RESET_GET(x) WLAN_LF_TIMER_CONTROL1_RESET_GET(x) +#define LF_TIMER_CONTROL1_RESET_SET(x) WLAN_LF_TIMER_CONTROL1_RESET_SET(x) +#define LF_TIMER_STATUS1_ADDRESS WLAN_LF_TIMER_STATUS1_ADDRESS +#define LF_TIMER_STATUS1_OFFSET WLAN_LF_TIMER_STATUS1_OFFSET +#define LF_TIMER_STATUS1_INTERRUPT_MSB WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB +#define LF_TIMER_STATUS1_INTERRUPT_LSB WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB +#define LF_TIMER_STATUS1_INTERRUPT_MASK WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK +#define LF_TIMER_STATUS1_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x) +#define LF_TIMER_STATUS1_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x) +#define LF_TIMER2_ADDRESS WLAN_LF_TIMER2_ADDRESS +#define LF_TIMER2_OFFSET WLAN_LF_TIMER2_OFFSET +#define LF_TIMER2_TARGET_MSB WLAN_LF_TIMER2_TARGET_MSB +#define LF_TIMER2_TARGET_LSB WLAN_LF_TIMER2_TARGET_LSB +#define LF_TIMER2_TARGET_MASK WLAN_LF_TIMER2_TARGET_MASK +#define LF_TIMER2_TARGET_GET(x) WLAN_LF_TIMER2_TARGET_GET(x) +#define LF_TIMER2_TARGET_SET(x) WLAN_LF_TIMER2_TARGET_SET(x) +#define LF_TIMER_COUNT2_ADDRESS WLAN_LF_TIMER_COUNT2_ADDRESS +#define LF_TIMER_COUNT2_OFFSET WLAN_LF_TIMER_COUNT2_OFFSET +#define LF_TIMER_COUNT2_VALUE_MSB WLAN_LF_TIMER_COUNT2_VALUE_MSB +#define LF_TIMER_COUNT2_VALUE_LSB WLAN_LF_TIMER_COUNT2_VALUE_LSB +#define LF_TIMER_COUNT2_VALUE_MASK WLAN_LF_TIMER_COUNT2_VALUE_MASK +#define LF_TIMER_COUNT2_VALUE_GET(x) WLAN_LF_TIMER_COUNT2_VALUE_GET(x) +#define LF_TIMER_COUNT2_VALUE_SET(x) WLAN_LF_TIMER_COUNT2_VALUE_SET(x) +#define LF_TIMER_CONTROL2_ADDRESS WLAN_LF_TIMER_CONTROL2_ADDRESS +#define LF_TIMER_CONTROL2_OFFSET WLAN_LF_TIMER_CONTROL2_OFFSET +#define LF_TIMER_CONTROL2_ENABLE_MSB WLAN_LF_TIMER_CONTROL2_ENABLE_MSB +#define LF_TIMER_CONTROL2_ENABLE_LSB WLAN_LF_TIMER_CONTROL2_ENABLE_LSB +#define LF_TIMER_CONTROL2_ENABLE_MASK WLAN_LF_TIMER_CONTROL2_ENABLE_MASK +#define LF_TIMER_CONTROL2_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x) +#define LF_TIMER_CONTROL2_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x) +#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB +#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB +#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK +#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) +#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) +#define LF_TIMER_CONTROL2_RESET_MSB WLAN_LF_TIMER_CONTROL2_RESET_MSB +#define LF_TIMER_CONTROL2_RESET_LSB WLAN_LF_TIMER_CONTROL2_RESET_LSB +#define LF_TIMER_CONTROL2_RESET_MASK WLAN_LF_TIMER_CONTROL2_RESET_MASK +#define LF_TIMER_CONTROL2_RESET_GET(x) WLAN_LF_TIMER_CONTROL2_RESET_GET(x) +#define LF_TIMER_CONTROL2_RESET_SET(x) WLAN_LF_TIMER_CONTROL2_RESET_SET(x) +#define LF_TIMER_STATUS2_ADDRESS WLAN_LF_TIMER_STATUS2_ADDRESS +#define LF_TIMER_STATUS2_OFFSET WLAN_LF_TIMER_STATUS2_OFFSET +#define LF_TIMER_STATUS2_INTERRUPT_MSB WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB +#define LF_TIMER_STATUS2_INTERRUPT_LSB WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB +#define LF_TIMER_STATUS2_INTERRUPT_MASK WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK +#define LF_TIMER_STATUS2_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x) +#define LF_TIMER_STATUS2_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x) +#define LF_TIMER3_ADDRESS WLAN_LF_TIMER3_ADDRESS +#define LF_TIMER3_OFFSET WLAN_LF_TIMER3_OFFSET +#define LF_TIMER3_TARGET_MSB WLAN_LF_TIMER3_TARGET_MSB +#define LF_TIMER3_TARGET_LSB WLAN_LF_TIMER3_TARGET_LSB +#define LF_TIMER3_TARGET_MASK WLAN_LF_TIMER3_TARGET_MASK +#define LF_TIMER3_TARGET_GET(x) WLAN_LF_TIMER3_TARGET_GET(x) +#define LF_TIMER3_TARGET_SET(x) WLAN_LF_TIMER3_TARGET_SET(x) +#define LF_TIMER_COUNT3_ADDRESS WLAN_LF_TIMER_COUNT3_ADDRESS +#define LF_TIMER_COUNT3_OFFSET WLAN_LF_TIMER_COUNT3_OFFSET +#define LF_TIMER_COUNT3_VALUE_MSB WLAN_LF_TIMER_COUNT3_VALUE_MSB +#define LF_TIMER_COUNT3_VALUE_LSB WLAN_LF_TIMER_COUNT3_VALUE_LSB +#define LF_TIMER_COUNT3_VALUE_MASK WLAN_LF_TIMER_COUNT3_VALUE_MASK +#define LF_TIMER_COUNT3_VALUE_GET(x) WLAN_LF_TIMER_COUNT3_VALUE_GET(x) +#define LF_TIMER_COUNT3_VALUE_SET(x) WLAN_LF_TIMER_COUNT3_VALUE_SET(x) +#define LF_TIMER_CONTROL3_ADDRESS WLAN_LF_TIMER_CONTROL3_ADDRESS +#define LF_TIMER_CONTROL3_OFFSET WLAN_LF_TIMER_CONTROL3_OFFSET +#define LF_TIMER_CONTROL3_ENABLE_MSB WLAN_LF_TIMER_CONTROL3_ENABLE_MSB +#define LF_TIMER_CONTROL3_ENABLE_LSB WLAN_LF_TIMER_CONTROL3_ENABLE_LSB +#define LF_TIMER_CONTROL3_ENABLE_MASK WLAN_LF_TIMER_CONTROL3_ENABLE_MASK +#define LF_TIMER_CONTROL3_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x) +#define LF_TIMER_CONTROL3_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x) +#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB +#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB +#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK +#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) +#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) +#define LF_TIMER_CONTROL3_RESET_MSB WLAN_LF_TIMER_CONTROL3_RESET_MSB +#define LF_TIMER_CONTROL3_RESET_LSB WLAN_LF_TIMER_CONTROL3_RESET_LSB +#define LF_TIMER_CONTROL3_RESET_MASK WLAN_LF_TIMER_CONTROL3_RESET_MASK +#define LF_TIMER_CONTROL3_RESET_GET(x) WLAN_LF_TIMER_CONTROL3_RESET_GET(x) +#define LF_TIMER_CONTROL3_RESET_SET(x) WLAN_LF_TIMER_CONTROL3_RESET_SET(x) +#define LF_TIMER_STATUS3_ADDRESS WLAN_LF_TIMER_STATUS3_ADDRESS +#define LF_TIMER_STATUS3_OFFSET WLAN_LF_TIMER_STATUS3_OFFSET +#define LF_TIMER_STATUS3_INTERRUPT_MSB WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB +#define LF_TIMER_STATUS3_INTERRUPT_LSB WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB +#define LF_TIMER_STATUS3_INTERRUPT_MASK WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK +#define LF_TIMER_STATUS3_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x) +#define LF_TIMER_STATUS3_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x) +#define HF_TIMER_ADDRESS WLAN_HF_TIMER_ADDRESS +#define HF_TIMER_OFFSET WLAN_HF_TIMER_OFFSET +#define HF_TIMER_TARGET_MSB WLAN_HF_TIMER_TARGET_MSB +#define HF_TIMER_TARGET_LSB WLAN_HF_TIMER_TARGET_LSB +#define HF_TIMER_TARGET_MASK WLAN_HF_TIMER_TARGET_MASK +#define HF_TIMER_TARGET_GET(x) WLAN_HF_TIMER_TARGET_GET(x) +#define HF_TIMER_TARGET_SET(x) WLAN_HF_TIMER_TARGET_SET(x) +#define HF_TIMER_COUNT_ADDRESS WLAN_HF_TIMER_COUNT_ADDRESS +#define HF_TIMER_COUNT_OFFSET WLAN_HF_TIMER_COUNT_OFFSET +#define HF_TIMER_COUNT_VALUE_MSB WLAN_HF_TIMER_COUNT_VALUE_MSB +#define HF_TIMER_COUNT_VALUE_LSB WLAN_HF_TIMER_COUNT_VALUE_LSB +#define HF_TIMER_COUNT_VALUE_MASK WLAN_HF_TIMER_COUNT_VALUE_MASK +#define HF_TIMER_COUNT_VALUE_GET(x) WLAN_HF_TIMER_COUNT_VALUE_GET(x) +#define HF_TIMER_COUNT_VALUE_SET(x) WLAN_HF_TIMER_COUNT_VALUE_SET(x) +#define HF_LF_COUNT_ADDRESS WLAN_HF_LF_COUNT_ADDRESS +#define HF_LF_COUNT_OFFSET WLAN_HF_LF_COUNT_OFFSET +#define HF_LF_COUNT_VALUE_MSB WLAN_HF_LF_COUNT_VALUE_MSB +#define HF_LF_COUNT_VALUE_LSB WLAN_HF_LF_COUNT_VALUE_LSB +#define HF_LF_COUNT_VALUE_MASK WLAN_HF_LF_COUNT_VALUE_MASK +#define HF_LF_COUNT_VALUE_GET(x) WLAN_HF_LF_COUNT_VALUE_GET(x) +#define HF_LF_COUNT_VALUE_SET(x) WLAN_HF_LF_COUNT_VALUE_SET(x) +#define HF_TIMER_CONTROL_ADDRESS WLAN_HF_TIMER_CONTROL_ADDRESS +#define HF_TIMER_CONTROL_OFFSET WLAN_HF_TIMER_CONTROL_OFFSET +#define HF_TIMER_CONTROL_ENABLE_MSB WLAN_HF_TIMER_CONTROL_ENABLE_MSB +#define HF_TIMER_CONTROL_ENABLE_LSB WLAN_HF_TIMER_CONTROL_ENABLE_LSB +#define HF_TIMER_CONTROL_ENABLE_MASK WLAN_HF_TIMER_CONTROL_ENABLE_MASK +#define HF_TIMER_CONTROL_ENABLE_GET(x) WLAN_HF_TIMER_CONTROL_ENABLE_GET(x) +#define HF_TIMER_CONTROL_ENABLE_SET(x) WLAN_HF_TIMER_CONTROL_ENABLE_SET(x) +#define HF_TIMER_CONTROL_ON_MSB WLAN_HF_TIMER_CONTROL_ON_MSB +#define HF_TIMER_CONTROL_ON_LSB WLAN_HF_TIMER_CONTROL_ON_LSB +#define HF_TIMER_CONTROL_ON_MASK WLAN_HF_TIMER_CONTROL_ON_MASK +#define HF_TIMER_CONTROL_ON_GET(x) WLAN_HF_TIMER_CONTROL_ON_GET(x) +#define HF_TIMER_CONTROL_ON_SET(x) WLAN_HF_TIMER_CONTROL_ON_SET(x) +#define HF_TIMER_CONTROL_AUTO_RESTART_MSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB +#define HF_TIMER_CONTROL_AUTO_RESTART_LSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB +#define HF_TIMER_CONTROL_AUTO_RESTART_MASK WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK +#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x) +#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x) +#define HF_TIMER_CONTROL_RESET_MSB WLAN_HF_TIMER_CONTROL_RESET_MSB +#define HF_TIMER_CONTROL_RESET_LSB WLAN_HF_TIMER_CONTROL_RESET_LSB +#define HF_TIMER_CONTROL_RESET_MASK WLAN_HF_TIMER_CONTROL_RESET_MASK +#define HF_TIMER_CONTROL_RESET_GET(x) WLAN_HF_TIMER_CONTROL_RESET_GET(x) +#define HF_TIMER_CONTROL_RESET_SET(x) WLAN_HF_TIMER_CONTROL_RESET_SET(x) +#define HF_TIMER_STATUS_ADDRESS WLAN_HF_TIMER_STATUS_ADDRESS +#define HF_TIMER_STATUS_OFFSET WLAN_HF_TIMER_STATUS_OFFSET +#define HF_TIMER_STATUS_INTERRUPT_MSB WLAN_HF_TIMER_STATUS_INTERRUPT_MSB +#define HF_TIMER_STATUS_INTERRUPT_LSB WLAN_HF_TIMER_STATUS_INTERRUPT_LSB +#define HF_TIMER_STATUS_INTERRUPT_MASK WLAN_HF_TIMER_STATUS_INTERRUPT_MASK +#define HF_TIMER_STATUS_INTERRUPT_GET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x) +#define HF_TIMER_STATUS_INTERRUPT_SET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x) +#define RTC_CONTROL_ADDRESS WLAN_RTC_CONTROL_ADDRESS +#define RTC_CONTROL_OFFSET WLAN_RTC_CONTROL_OFFSET +#define RTC_CONTROL_ENABLE_MSB WLAN_RTC_CONTROL_ENABLE_MSB +#define RTC_CONTROL_ENABLE_LSB WLAN_RTC_CONTROL_ENABLE_LSB +#define RTC_CONTROL_ENABLE_MASK WLAN_RTC_CONTROL_ENABLE_MASK +#define RTC_CONTROL_ENABLE_GET(x) WLAN_RTC_CONTROL_ENABLE_GET(x) +#define RTC_CONTROL_ENABLE_SET(x) WLAN_RTC_CONTROL_ENABLE_SET(x) +#define RTC_CONTROL_LOAD_RTC_MSB WLAN_RTC_CONTROL_LOAD_RTC_MSB +#define RTC_CONTROL_LOAD_RTC_LSB WLAN_RTC_CONTROL_LOAD_RTC_LSB +#define RTC_CONTROL_LOAD_RTC_MASK WLAN_RTC_CONTROL_LOAD_RTC_MASK +#define RTC_CONTROL_LOAD_RTC_GET(x) WLAN_RTC_CONTROL_LOAD_RTC_GET(x) +#define RTC_CONTROL_LOAD_RTC_SET(x) WLAN_RTC_CONTROL_LOAD_RTC_SET(x) +#define RTC_CONTROL_LOAD_ALARM_MSB WLAN_RTC_CONTROL_LOAD_ALARM_MSB +#define RTC_CONTROL_LOAD_ALARM_LSB WLAN_RTC_CONTROL_LOAD_ALARM_LSB +#define RTC_CONTROL_LOAD_ALARM_MASK WLAN_RTC_CONTROL_LOAD_ALARM_MASK +#define RTC_CONTROL_LOAD_ALARM_GET(x) WLAN_RTC_CONTROL_LOAD_ALARM_GET(x) +#define RTC_CONTROL_LOAD_ALARM_SET(x) WLAN_RTC_CONTROL_LOAD_ALARM_SET(x) +#define RTC_TIME_ADDRESS WLAN_RTC_TIME_ADDRESS +#define RTC_TIME_OFFSET WLAN_RTC_TIME_OFFSET +#define RTC_TIME_WEEK_DAY_MSB WLAN_RTC_TIME_WEEK_DAY_MSB +#define RTC_TIME_WEEK_DAY_LSB WLAN_RTC_TIME_WEEK_DAY_LSB +#define RTC_TIME_WEEK_DAY_MASK WLAN_RTC_TIME_WEEK_DAY_MASK +#define RTC_TIME_WEEK_DAY_GET(x) WLAN_RTC_TIME_WEEK_DAY_GET(x) +#define RTC_TIME_WEEK_DAY_SET(x) WLAN_RTC_TIME_WEEK_DAY_SET(x) +#define RTC_TIME_HOUR_MSB WLAN_RTC_TIME_HOUR_MSB +#define RTC_TIME_HOUR_LSB WLAN_RTC_TIME_HOUR_LSB +#define RTC_TIME_HOUR_MASK WLAN_RTC_TIME_HOUR_MASK +#define RTC_TIME_HOUR_GET(x) WLAN_RTC_TIME_HOUR_GET(x) +#define RTC_TIME_HOUR_SET(x) WLAN_RTC_TIME_HOUR_SET(x) +#define RTC_TIME_MINUTE_MSB WLAN_RTC_TIME_MINUTE_MSB +#define RTC_TIME_MINUTE_LSB WLAN_RTC_TIME_MINUTE_LSB +#define RTC_TIME_MINUTE_MASK WLAN_RTC_TIME_MINUTE_MASK +#define RTC_TIME_MINUTE_GET(x) WLAN_RTC_TIME_MINUTE_GET(x) +#define RTC_TIME_MINUTE_SET(x) WLAN_RTC_TIME_MINUTE_SET(x) +#define RTC_TIME_SECOND_MSB WLAN_RTC_TIME_SECOND_MSB +#define RTC_TIME_SECOND_LSB WLAN_RTC_TIME_SECOND_LSB +#define RTC_TIME_SECOND_MASK WLAN_RTC_TIME_SECOND_MASK +#define RTC_TIME_SECOND_GET(x) WLAN_RTC_TIME_SECOND_GET(x) +#define RTC_TIME_SECOND_SET(x) WLAN_RTC_TIME_SECOND_SET(x) +#define RTC_DATE_ADDRESS WLAN_RTC_DATE_ADDRESS +#define RTC_DATE_OFFSET WLAN_RTC_DATE_OFFSET +#define RTC_DATE_YEAR_MSB WLAN_RTC_DATE_YEAR_MSB +#define RTC_DATE_YEAR_LSB WLAN_RTC_DATE_YEAR_LSB +#define RTC_DATE_YEAR_MASK WLAN_RTC_DATE_YEAR_MASK +#define RTC_DATE_YEAR_GET(x) WLAN_RTC_DATE_YEAR_GET(x) +#define RTC_DATE_YEAR_SET(x) WLAN_RTC_DATE_YEAR_SET(x) +#define RTC_DATE_MONTH_MSB WLAN_RTC_DATE_MONTH_MSB +#define RTC_DATE_MONTH_LSB WLAN_RTC_DATE_MONTH_LSB +#define RTC_DATE_MONTH_MASK WLAN_RTC_DATE_MONTH_MASK +#define RTC_DATE_MONTH_GET(x) WLAN_RTC_DATE_MONTH_GET(x) +#define RTC_DATE_MONTH_SET(x) WLAN_RTC_DATE_MONTH_SET(x) +#define RTC_DATE_MONTH_DAY_MSB WLAN_RTC_DATE_MONTH_DAY_MSB +#define RTC_DATE_MONTH_DAY_LSB WLAN_RTC_DATE_MONTH_DAY_LSB +#define RTC_DATE_MONTH_DAY_MASK WLAN_RTC_DATE_MONTH_DAY_MASK +#define RTC_DATE_MONTH_DAY_GET(x) WLAN_RTC_DATE_MONTH_DAY_GET(x) +#define RTC_DATE_MONTH_DAY_SET(x) WLAN_RTC_DATE_MONTH_DAY_SET(x) +#define RTC_SET_TIME_ADDRESS WLAN_RTC_SET_TIME_ADDRESS +#define RTC_SET_TIME_OFFSET WLAN_RTC_SET_TIME_OFFSET +#define RTC_SET_TIME_WEEK_DAY_MSB WLAN_RTC_SET_TIME_WEEK_DAY_MSB +#define RTC_SET_TIME_WEEK_DAY_LSB WLAN_RTC_SET_TIME_WEEK_DAY_LSB +#define RTC_SET_TIME_WEEK_DAY_MASK WLAN_RTC_SET_TIME_WEEK_DAY_MASK +#define RTC_SET_TIME_WEEK_DAY_GET(x) WLAN_RTC_SET_TIME_WEEK_DAY_GET(x) +#define RTC_SET_TIME_WEEK_DAY_SET(x) WLAN_RTC_SET_TIME_WEEK_DAY_SET(x) +#define RTC_SET_TIME_HOUR_MSB WLAN_RTC_SET_TIME_HOUR_MSB +#define RTC_SET_TIME_HOUR_LSB WLAN_RTC_SET_TIME_HOUR_LSB +#define RTC_SET_TIME_HOUR_MASK WLAN_RTC_SET_TIME_HOUR_MASK +#define RTC_SET_TIME_HOUR_GET(x) WLAN_RTC_SET_TIME_HOUR_GET(x) +#define RTC_SET_TIME_HOUR_SET(x) WLAN_RTC_SET_TIME_HOUR_SET(x) +#define RTC_SET_TIME_MINUTE_MSB WLAN_RTC_SET_TIME_MINUTE_MSB +#define RTC_SET_TIME_MINUTE_LSB WLAN_RTC_SET_TIME_MINUTE_LSB +#define RTC_SET_TIME_MINUTE_MASK WLAN_RTC_SET_TIME_MINUTE_MASK +#define RTC_SET_TIME_MINUTE_GET(x) WLAN_RTC_SET_TIME_MINUTE_GET(x) +#define RTC_SET_TIME_MINUTE_SET(x) WLAN_RTC_SET_TIME_MINUTE_SET(x) +#define RTC_SET_TIME_SECOND_MSB WLAN_RTC_SET_TIME_SECOND_MSB +#define RTC_SET_TIME_SECOND_LSB WLAN_RTC_SET_TIME_SECOND_LSB +#define RTC_SET_TIME_SECOND_MASK WLAN_RTC_SET_TIME_SECOND_MASK +#define RTC_SET_TIME_SECOND_GET(x) WLAN_RTC_SET_TIME_SECOND_GET(x) +#define RTC_SET_TIME_SECOND_SET(x) WLAN_RTC_SET_TIME_SECOND_SET(x) +#define RTC_SET_DATE_ADDRESS WLAN_RTC_SET_DATE_ADDRESS +#define RTC_SET_DATE_OFFSET WLAN_RTC_SET_DATE_OFFSET +#define RTC_SET_DATE_YEAR_MSB WLAN_RTC_SET_DATE_YEAR_MSB +#define RTC_SET_DATE_YEAR_LSB WLAN_RTC_SET_DATE_YEAR_LSB +#define RTC_SET_DATE_YEAR_MASK WLAN_RTC_SET_DATE_YEAR_MASK +#define RTC_SET_DATE_YEAR_GET(x) WLAN_RTC_SET_DATE_YEAR_GET(x) +#define RTC_SET_DATE_YEAR_SET(x) WLAN_RTC_SET_DATE_YEAR_SET(x) +#define RTC_SET_DATE_MONTH_MSB WLAN_RTC_SET_DATE_MONTH_MSB +#define RTC_SET_DATE_MONTH_LSB WLAN_RTC_SET_DATE_MONTH_LSB +#define RTC_SET_DATE_MONTH_MASK WLAN_RTC_SET_DATE_MONTH_MASK +#define RTC_SET_DATE_MONTH_GET(x) WLAN_RTC_SET_DATE_MONTH_GET(x) +#define RTC_SET_DATE_MONTH_SET(x) WLAN_RTC_SET_DATE_MONTH_SET(x) +#define RTC_SET_DATE_MONTH_DAY_MSB WLAN_RTC_SET_DATE_MONTH_DAY_MSB +#define RTC_SET_DATE_MONTH_DAY_LSB WLAN_RTC_SET_DATE_MONTH_DAY_LSB +#define RTC_SET_DATE_MONTH_DAY_MASK WLAN_RTC_SET_DATE_MONTH_DAY_MASK +#define RTC_SET_DATE_MONTH_DAY_GET(x) WLAN_RTC_SET_DATE_MONTH_DAY_GET(x) +#define RTC_SET_DATE_MONTH_DAY_SET(x) WLAN_RTC_SET_DATE_MONTH_DAY_SET(x) +#define RTC_SET_ALARM_ADDRESS WLAN_RTC_SET_ALARM_ADDRESS +#define RTC_SET_ALARM_OFFSET WLAN_RTC_SET_ALARM_OFFSET +#define RTC_SET_ALARM_HOUR_MSB WLAN_RTC_SET_ALARM_HOUR_MSB +#define RTC_SET_ALARM_HOUR_LSB WLAN_RTC_SET_ALARM_HOUR_LSB +#define RTC_SET_ALARM_HOUR_MASK WLAN_RTC_SET_ALARM_HOUR_MASK +#define RTC_SET_ALARM_HOUR_GET(x) WLAN_RTC_SET_ALARM_HOUR_GET(x) +#define RTC_SET_ALARM_HOUR_SET(x) WLAN_RTC_SET_ALARM_HOUR_SET(x) +#define RTC_SET_ALARM_MINUTE_MSB WLAN_RTC_SET_ALARM_MINUTE_MSB +#define RTC_SET_ALARM_MINUTE_LSB WLAN_RTC_SET_ALARM_MINUTE_LSB +#define RTC_SET_ALARM_MINUTE_MASK WLAN_RTC_SET_ALARM_MINUTE_MASK +#define RTC_SET_ALARM_MINUTE_GET(x) WLAN_RTC_SET_ALARM_MINUTE_GET(x) +#define RTC_SET_ALARM_MINUTE_SET(x) WLAN_RTC_SET_ALARM_MINUTE_SET(x) +#define RTC_SET_ALARM_SECOND_MSB WLAN_RTC_SET_ALARM_SECOND_MSB +#define RTC_SET_ALARM_SECOND_LSB WLAN_RTC_SET_ALARM_SECOND_LSB +#define RTC_SET_ALARM_SECOND_MASK WLAN_RTC_SET_ALARM_SECOND_MASK +#define RTC_SET_ALARM_SECOND_GET(x) WLAN_RTC_SET_ALARM_SECOND_GET(x) +#define RTC_SET_ALARM_SECOND_SET(x) WLAN_RTC_SET_ALARM_SECOND_SET(x) +#define RTC_CONFIG_ADDRESS WLAN_RTC_CONFIG_ADDRESS +#define RTC_CONFIG_OFFSET WLAN_RTC_CONFIG_OFFSET +#define RTC_CONFIG_BCD_MSB WLAN_RTC_CONFIG_BCD_MSB +#define RTC_CONFIG_BCD_LSB WLAN_RTC_CONFIG_BCD_LSB +#define RTC_CONFIG_BCD_MASK WLAN_RTC_CONFIG_BCD_MASK +#define RTC_CONFIG_BCD_GET(x) WLAN_RTC_CONFIG_BCD_GET(x) +#define RTC_CONFIG_BCD_SET(x) WLAN_RTC_CONFIG_BCD_SET(x) +#define RTC_CONFIG_TWELVE_HOUR_MSB WLAN_RTC_CONFIG_TWELVE_HOUR_MSB +#define RTC_CONFIG_TWELVE_HOUR_LSB WLAN_RTC_CONFIG_TWELVE_HOUR_LSB +#define RTC_CONFIG_TWELVE_HOUR_MASK WLAN_RTC_CONFIG_TWELVE_HOUR_MASK +#define RTC_CONFIG_TWELVE_HOUR_GET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x) +#define RTC_CONFIG_TWELVE_HOUR_SET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x) +#define RTC_CONFIG_DSE_MSB WLAN_RTC_CONFIG_DSE_MSB +#define RTC_CONFIG_DSE_LSB WLAN_RTC_CONFIG_DSE_LSB +#define RTC_CONFIG_DSE_MASK WLAN_RTC_CONFIG_DSE_MASK +#define RTC_CONFIG_DSE_GET(x) WLAN_RTC_CONFIG_DSE_GET(x) +#define RTC_CONFIG_DSE_SET(x) WLAN_RTC_CONFIG_DSE_SET(x) +#define RTC_ALARM_STATUS_ADDRESS WLAN_RTC_ALARM_STATUS_ADDRESS +#define RTC_ALARM_STATUS_OFFSET WLAN_RTC_ALARM_STATUS_OFFSET +#define RTC_ALARM_STATUS_ENABLE_MSB WLAN_RTC_ALARM_STATUS_ENABLE_MSB +#define RTC_ALARM_STATUS_ENABLE_LSB WLAN_RTC_ALARM_STATUS_ENABLE_LSB +#define RTC_ALARM_STATUS_ENABLE_MASK WLAN_RTC_ALARM_STATUS_ENABLE_MASK +#define RTC_ALARM_STATUS_ENABLE_GET(x) WLAN_RTC_ALARM_STATUS_ENABLE_GET(x) +#define RTC_ALARM_STATUS_ENABLE_SET(x) WLAN_RTC_ALARM_STATUS_ENABLE_SET(x) +#define RTC_ALARM_STATUS_INTERRUPT_MSB WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB +#define RTC_ALARM_STATUS_INTERRUPT_LSB WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB +#define RTC_ALARM_STATUS_INTERRUPT_MASK WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK +#define RTC_ALARM_STATUS_INTERRUPT_GET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x) +#define RTC_ALARM_STATUS_INTERRUPT_SET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x) +#define UART_WAKEUP_ADDRESS WLAN_UART_WAKEUP_ADDRESS +#define UART_WAKEUP_OFFSET WLAN_UART_WAKEUP_OFFSET +#define UART_WAKEUP_ENABLE_MSB WLAN_UART_WAKEUP_ENABLE_MSB +#define UART_WAKEUP_ENABLE_LSB WLAN_UART_WAKEUP_ENABLE_LSB +#define UART_WAKEUP_ENABLE_MASK WLAN_UART_WAKEUP_ENABLE_MASK +#define UART_WAKEUP_ENABLE_GET(x) WLAN_UART_WAKEUP_ENABLE_GET(x) +#define UART_WAKEUP_ENABLE_SET(x) WLAN_UART_WAKEUP_ENABLE_SET(x) +#define RESET_CAUSE_ADDRESS WLAN_RESET_CAUSE_ADDRESS +#define RESET_CAUSE_OFFSET WLAN_RESET_CAUSE_OFFSET +#define RESET_CAUSE_LAST_MSB WLAN_RESET_CAUSE_LAST_MSB +#define RESET_CAUSE_LAST_LSB WLAN_RESET_CAUSE_LAST_LSB +#define RESET_CAUSE_LAST_MASK WLAN_RESET_CAUSE_LAST_MASK +#define RESET_CAUSE_LAST_GET(x) WLAN_RESET_CAUSE_LAST_GET(x) +#define RESET_CAUSE_LAST_SET(x) WLAN_RESET_CAUSE_LAST_SET(x) +#define SYSTEM_SLEEP_ADDRESS WLAN_SYSTEM_SLEEP_ADDRESS +#define SYSTEM_SLEEP_OFFSET WLAN_SYSTEM_SLEEP_OFFSET +#define SYSTEM_SLEEP_HOST_IF_MSB WLAN_SYSTEM_SLEEP_HOST_IF_MSB +#define SYSTEM_SLEEP_HOST_IF_LSB WLAN_SYSTEM_SLEEP_HOST_IF_LSB +#define SYSTEM_SLEEP_HOST_IF_MASK WLAN_SYSTEM_SLEEP_HOST_IF_MASK +#define SYSTEM_SLEEP_HOST_IF_GET(x) WLAN_SYSTEM_SLEEP_HOST_IF_GET(x) +#define SYSTEM_SLEEP_HOST_IF_SET(x) WLAN_SYSTEM_SLEEP_HOST_IF_SET(x) +#define SYSTEM_SLEEP_MBOX_MSB WLAN_SYSTEM_SLEEP_MBOX_MSB +#define SYSTEM_SLEEP_MBOX_LSB WLAN_SYSTEM_SLEEP_MBOX_LSB +#define SYSTEM_SLEEP_MBOX_MASK WLAN_SYSTEM_SLEEP_MBOX_MASK +#define SYSTEM_SLEEP_MBOX_GET(x) WLAN_SYSTEM_SLEEP_MBOX_GET(x) +#define SYSTEM_SLEEP_MBOX_SET(x) WLAN_SYSTEM_SLEEP_MBOX_SET(x) +#define SYSTEM_SLEEP_MAC_IF_MSB WLAN_SYSTEM_SLEEP_MAC_IF_MSB +#define SYSTEM_SLEEP_MAC_IF_LSB WLAN_SYSTEM_SLEEP_MAC_IF_LSB +#define SYSTEM_SLEEP_MAC_IF_MASK WLAN_SYSTEM_SLEEP_MAC_IF_MASK +#define SYSTEM_SLEEP_MAC_IF_GET(x) WLAN_SYSTEM_SLEEP_MAC_IF_GET(x) +#define SYSTEM_SLEEP_MAC_IF_SET(x) WLAN_SYSTEM_SLEEP_MAC_IF_SET(x) +#define SYSTEM_SLEEP_LIGHT_MSB WLAN_SYSTEM_SLEEP_LIGHT_MSB +#define SYSTEM_SLEEP_LIGHT_LSB WLAN_SYSTEM_SLEEP_LIGHT_LSB +#define SYSTEM_SLEEP_LIGHT_MASK WLAN_SYSTEM_SLEEP_LIGHT_MASK +#define SYSTEM_SLEEP_LIGHT_GET(x) WLAN_SYSTEM_SLEEP_LIGHT_GET(x) +#define SYSTEM_SLEEP_LIGHT_SET(x) WLAN_SYSTEM_SLEEP_LIGHT_SET(x) +#define SYSTEM_SLEEP_DISABLE_MSB WLAN_SYSTEM_SLEEP_DISABLE_MSB +#define SYSTEM_SLEEP_DISABLE_LSB WLAN_SYSTEM_SLEEP_DISABLE_LSB +#define SYSTEM_SLEEP_DISABLE_MASK WLAN_SYSTEM_SLEEP_DISABLE_MASK +#define SYSTEM_SLEEP_DISABLE_GET(x) WLAN_SYSTEM_SLEEP_DISABLE_GET(x) +#define SYSTEM_SLEEP_DISABLE_SET(x) WLAN_SYSTEM_SLEEP_DISABLE_SET(x) +#define SDIO_WRAPPER_ADDRESS WLAN_SDIO_WRAPPER_ADDRESS +#define SDIO_WRAPPER_OFFSET WLAN_SDIO_WRAPPER_OFFSET +#define SDIO_WRAPPER_SLEEP_MSB WLAN_SDIO_WRAPPER_SLEEP_MSB +#define SDIO_WRAPPER_SLEEP_LSB WLAN_SDIO_WRAPPER_SLEEP_LSB +#define SDIO_WRAPPER_SLEEP_MASK WLAN_SDIO_WRAPPER_SLEEP_MASK +#define SDIO_WRAPPER_SLEEP_GET(x) WLAN_SDIO_WRAPPER_SLEEP_GET(x) +#define SDIO_WRAPPER_SLEEP_SET(x) WLAN_SDIO_WRAPPER_SLEEP_SET(x) +#define SDIO_WRAPPER_WAKEUP_MSB WLAN_SDIO_WRAPPER_WAKEUP_MSB +#define SDIO_WRAPPER_WAKEUP_LSB WLAN_SDIO_WRAPPER_WAKEUP_LSB +#define SDIO_WRAPPER_WAKEUP_MASK WLAN_SDIO_WRAPPER_WAKEUP_MASK +#define SDIO_WRAPPER_WAKEUP_GET(x) WLAN_SDIO_WRAPPER_WAKEUP_GET(x) +#define SDIO_WRAPPER_WAKEUP_SET(x) WLAN_SDIO_WRAPPER_WAKEUP_SET(x) +#define SDIO_WRAPPER_SOC_ON_MSB WLAN_SDIO_WRAPPER_SOC_ON_MSB +#define SDIO_WRAPPER_SOC_ON_LSB WLAN_SDIO_WRAPPER_SOC_ON_LSB +#define SDIO_WRAPPER_SOC_ON_MASK WLAN_SDIO_WRAPPER_SOC_ON_MASK +#define SDIO_WRAPPER_SOC_ON_GET(x) WLAN_SDIO_WRAPPER_SOC_ON_GET(x) +#define SDIO_WRAPPER_SOC_ON_SET(x) WLAN_SDIO_WRAPPER_SOC_ON_SET(x) +#define SDIO_WRAPPER_ON_MSB WLAN_SDIO_WRAPPER_ON_MSB +#define SDIO_WRAPPER_ON_LSB WLAN_SDIO_WRAPPER_ON_LSB +#define SDIO_WRAPPER_ON_MASK WLAN_SDIO_WRAPPER_ON_MASK +#define SDIO_WRAPPER_ON_GET(x) WLAN_SDIO_WRAPPER_ON_GET(x) +#define SDIO_WRAPPER_ON_SET(x) WLAN_SDIO_WRAPPER_ON_SET(x) +#define MAC_SLEEP_CONTROL_ADDRESS WLAN_MAC_SLEEP_CONTROL_ADDRESS +#define MAC_SLEEP_CONTROL_OFFSET WLAN_MAC_SLEEP_CONTROL_OFFSET +#define MAC_SLEEP_CONTROL_ENABLE_MSB WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB +#define MAC_SLEEP_CONTROL_ENABLE_LSB WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB +#define MAC_SLEEP_CONTROL_ENABLE_MASK WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK +#define MAC_SLEEP_CONTROL_ENABLE_GET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x) +#define MAC_SLEEP_CONTROL_ENABLE_SET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x) +#define KEEP_AWAKE_ADDRESS WLAN_KEEP_AWAKE_ADDRESS +#define KEEP_AWAKE_OFFSET WLAN_KEEP_AWAKE_OFFSET +#define KEEP_AWAKE_COUNT_MSB WLAN_KEEP_AWAKE_COUNT_MSB +#define KEEP_AWAKE_COUNT_LSB WLAN_KEEP_AWAKE_COUNT_LSB +#define KEEP_AWAKE_COUNT_MASK WLAN_KEEP_AWAKE_COUNT_MASK +#define KEEP_AWAKE_COUNT_GET(x) WLAN_KEEP_AWAKE_COUNT_GET(x) +#define KEEP_AWAKE_COUNT_SET(x) WLAN_KEEP_AWAKE_COUNT_SET(x) +#define LPO_CAL_TIME_ADDRESS WLAN_LPO_CAL_TIME_ADDRESS +#define LPO_CAL_TIME_OFFSET WLAN_LPO_CAL_TIME_OFFSET +#define LPO_CAL_TIME_LENGTH_MSB WLAN_LPO_CAL_TIME_LENGTH_MSB +#define LPO_CAL_TIME_LENGTH_LSB WLAN_LPO_CAL_TIME_LENGTH_LSB +#define LPO_CAL_TIME_LENGTH_MASK WLAN_LPO_CAL_TIME_LENGTH_MASK +#define LPO_CAL_TIME_LENGTH_GET(x) WLAN_LPO_CAL_TIME_LENGTH_GET(x) +#define LPO_CAL_TIME_LENGTH_SET(x) WLAN_LPO_CAL_TIME_LENGTH_SET(x) +#define LPO_INIT_DIVIDEND_INT_ADDRESS WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS +#define LPO_INIT_DIVIDEND_INT_OFFSET WLAN_LPO_INIT_DIVIDEND_INT_OFFSET +#define LPO_INIT_DIVIDEND_INT_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB +#define LPO_INIT_DIVIDEND_INT_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB +#define LPO_INIT_DIVIDEND_INT_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK +#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x) +#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x) +#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS +#define LPO_INIT_DIVIDEND_FRACTION_OFFSET WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) +#define LPO_CAL_ADDRESS WLAN_LPO_CAL_ADDRESS +#define LPO_CAL_OFFSET WLAN_LPO_CAL_OFFSET +#define LPO_CAL_ENABLE_MSB WLAN_LPO_CAL_ENABLE_MSB +#define LPO_CAL_ENABLE_LSB WLAN_LPO_CAL_ENABLE_LSB +#define LPO_CAL_ENABLE_MASK WLAN_LPO_CAL_ENABLE_MASK +#define LPO_CAL_ENABLE_GET(x) WLAN_LPO_CAL_ENABLE_GET(x) +#define LPO_CAL_ENABLE_SET(x) WLAN_LPO_CAL_ENABLE_SET(x) +#define LPO_CAL_COUNT_MSB WLAN_LPO_CAL_COUNT_MSB +#define LPO_CAL_COUNT_LSB WLAN_LPO_CAL_COUNT_LSB +#define LPO_CAL_COUNT_MASK WLAN_LPO_CAL_COUNT_MASK +#define LPO_CAL_COUNT_GET(x) WLAN_LPO_CAL_COUNT_GET(x) +#define LPO_CAL_COUNT_SET(x) WLAN_LPO_CAL_COUNT_SET(x) +#define LPO_CAL_TEST_CONTROL_ADDRESS WLAN_LPO_CAL_TEST_CONTROL_ADDRESS +#define LPO_CAL_TEST_CONTROL_OFFSET WLAN_LPO_CAL_TEST_CONTROL_OFFSET +#define LPO_CAL_TEST_CONTROL_ENABLE_MSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB +#define LPO_CAL_TEST_CONTROL_ENABLE_LSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB +#define LPO_CAL_TEST_CONTROL_ENABLE_MASK WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK +#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x) +#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) +#define LPO_CAL_TEST_STATUS_ADDRESS WLAN_LPO_CAL_TEST_STATUS_ADDRESS +#define LPO_CAL_TEST_STATUS_OFFSET WLAN_LPO_CAL_TEST_STATUS_OFFSET +#define LPO_CAL_TEST_STATUS_READY_MSB WLAN_LPO_CAL_TEST_STATUS_READY_MSB +#define LPO_CAL_TEST_STATUS_READY_LSB WLAN_LPO_CAL_TEST_STATUS_READY_LSB +#define LPO_CAL_TEST_STATUS_READY_MASK WLAN_LPO_CAL_TEST_STATUS_READY_MASK +#define LPO_CAL_TEST_STATUS_READY_GET(x) WLAN_LPO_CAL_TEST_STATUS_READY_GET(x) +#define LPO_CAL_TEST_STATUS_READY_SET(x) WLAN_LPO_CAL_TEST_STATUS_READY_SET(x) +#define LPO_CAL_TEST_STATUS_COUNT_MSB WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB +#define LPO_CAL_TEST_STATUS_COUNT_LSB WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB +#define LPO_CAL_TEST_STATUS_COUNT_MASK WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK +#define LPO_CAL_TEST_STATUS_COUNT_GET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x) +#define LPO_CAL_TEST_STATUS_COUNT_SET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x) +#define CHIP_ID_ADDRESS WLAN_CHIP_ID_ADDRESS +#define CHIP_ID_OFFSET WLAN_CHIP_ID_OFFSET +#define CHIP_ID_DEVICE_ID_MSB WLAN_CHIP_ID_DEVICE_ID_MSB +#define CHIP_ID_DEVICE_ID_LSB WLAN_CHIP_ID_DEVICE_ID_LSB +#define CHIP_ID_DEVICE_ID_MASK WLAN_CHIP_ID_DEVICE_ID_MASK +#define CHIP_ID_DEVICE_ID_GET(x) WLAN_CHIP_ID_DEVICE_ID_GET(x) +#define CHIP_ID_DEVICE_ID_SET(x) WLAN_CHIP_ID_DEVICE_ID_SET(x) +#define CHIP_ID_CONFIG_ID_MSB WLAN_CHIP_ID_CONFIG_ID_MSB +#define CHIP_ID_CONFIG_ID_LSB WLAN_CHIP_ID_CONFIG_ID_LSB +#define CHIP_ID_CONFIG_ID_MASK WLAN_CHIP_ID_CONFIG_ID_MASK +#define CHIP_ID_CONFIG_ID_GET(x) WLAN_CHIP_ID_CONFIG_ID_GET(x) +#define CHIP_ID_CONFIG_ID_SET(x) WLAN_CHIP_ID_CONFIG_ID_SET(x) +#define CHIP_ID_VERSION_ID_MSB WLAN_CHIP_ID_VERSION_ID_MSB +#define CHIP_ID_VERSION_ID_LSB WLAN_CHIP_ID_VERSION_ID_LSB +#define CHIP_ID_VERSION_ID_MASK WLAN_CHIP_ID_VERSION_ID_MASK +#define CHIP_ID_VERSION_ID_GET(x) WLAN_CHIP_ID_VERSION_ID_GET(x) +#define CHIP_ID_VERSION_ID_SET(x) WLAN_CHIP_ID_VERSION_ID_SET(x) +#define DERIVED_RTC_CLK_ADDRESS WLAN_DERIVED_RTC_CLK_ADDRESS +#define DERIVED_RTC_CLK_OFFSET WLAN_DERIVED_RTC_CLK_OFFSET +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) +#define DERIVED_RTC_CLK_FORCE_MSB WLAN_DERIVED_RTC_CLK_FORCE_MSB +#define DERIVED_RTC_CLK_FORCE_LSB WLAN_DERIVED_RTC_CLK_FORCE_LSB +#define DERIVED_RTC_CLK_FORCE_MASK WLAN_DERIVED_RTC_CLK_FORCE_MASK +#define DERIVED_RTC_CLK_FORCE_GET(x) WLAN_DERIVED_RTC_CLK_FORCE_GET(x) +#define DERIVED_RTC_CLK_FORCE_SET(x) WLAN_DERIVED_RTC_CLK_FORCE_SET(x) +#define DERIVED_RTC_CLK_PERIOD_MSB WLAN_DERIVED_RTC_CLK_PERIOD_MSB +#define DERIVED_RTC_CLK_PERIOD_LSB WLAN_DERIVED_RTC_CLK_PERIOD_LSB +#define DERIVED_RTC_CLK_PERIOD_MASK WLAN_DERIVED_RTC_CLK_PERIOD_MASK +#define DERIVED_RTC_CLK_PERIOD_GET(x) WLAN_DERIVED_RTC_CLK_PERIOD_GET(x) +#define DERIVED_RTC_CLK_PERIOD_SET(x) WLAN_DERIVED_RTC_CLK_PERIOD_SET(x) +#define POWER_REG_ADDRESS WLAN_POWER_REG_ADDRESS +#define POWER_REG_OFFSET WLAN_POWER_REG_OFFSET +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) +#define POWER_REG_DEBUG_EN_MSB WLAN_POWER_REG_DEBUG_EN_MSB +#define POWER_REG_DEBUG_EN_LSB WLAN_POWER_REG_DEBUG_EN_LSB +#define POWER_REG_DEBUG_EN_MASK WLAN_POWER_REG_DEBUG_EN_MASK +#define POWER_REG_DEBUG_EN_GET(x) WLAN_POWER_REG_DEBUG_EN_GET(x) +#define POWER_REG_DEBUG_EN_SET(x) WLAN_POWER_REG_DEBUG_EN_SET(x) +#define POWER_REG_WLAN_BB_PWD_EN_MSB WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB +#define POWER_REG_WLAN_BB_PWD_EN_LSB WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB +#define POWER_REG_WLAN_BB_PWD_EN_MASK WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK +#define POWER_REG_WLAN_BB_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x) +#define POWER_REG_WLAN_BB_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x) +#define POWER_REG_WLAN_MAC_PWD_EN_MSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB +#define POWER_REG_WLAN_MAC_PWD_EN_LSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB +#define POWER_REG_WLAN_MAC_PWD_EN_MASK WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK +#define POWER_REG_WLAN_MAC_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x) +#define POWER_REG_WLAN_MAC_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x) +#define POWER_REG_VLVL_MSB WLAN_POWER_REG_VLVL_MSB +#define POWER_REG_VLVL_LSB WLAN_POWER_REG_VLVL_LSB +#define POWER_REG_VLVL_MASK WLAN_POWER_REG_VLVL_MASK +#define POWER_REG_VLVL_GET(x) WLAN_POWER_REG_VLVL_GET(x) +#define POWER_REG_VLVL_SET(x) WLAN_POWER_REG_VLVL_SET(x) +#define POWER_REG_CPU_INT_ENABLE_MSB WLAN_POWER_REG_CPU_INT_ENABLE_MSB +#define POWER_REG_CPU_INT_ENABLE_LSB WLAN_POWER_REG_CPU_INT_ENABLE_LSB +#define POWER_REG_CPU_INT_ENABLE_MASK WLAN_POWER_REG_CPU_INT_ENABLE_MASK +#define POWER_REG_CPU_INT_ENABLE_GET(x) WLAN_POWER_REG_CPU_INT_ENABLE_GET(x) +#define POWER_REG_CPU_INT_ENABLE_SET(x) WLAN_POWER_REG_CPU_INT_ENABLE_SET(x) +#define POWER_REG_WLAN_ISO_DIS_MSB WLAN_POWER_REG_WLAN_ISO_DIS_MSB +#define POWER_REG_WLAN_ISO_DIS_LSB WLAN_POWER_REG_WLAN_ISO_DIS_LSB +#define POWER_REG_WLAN_ISO_DIS_MASK WLAN_POWER_REG_WLAN_ISO_DIS_MASK +#define POWER_REG_WLAN_ISO_DIS_GET(x) WLAN_POWER_REG_WLAN_ISO_DIS_GET(x) +#define POWER_REG_WLAN_ISO_DIS_SET(x) WLAN_POWER_REG_WLAN_ISO_DIS_SET(x) +#define POWER_REG_WLAN_ISO_CNTL_MSB WLAN_POWER_REG_WLAN_ISO_CNTL_MSB +#define POWER_REG_WLAN_ISO_CNTL_LSB WLAN_POWER_REG_WLAN_ISO_CNTL_LSB +#define POWER_REG_WLAN_ISO_CNTL_MASK WLAN_POWER_REG_WLAN_ISO_CNTL_MASK +#define POWER_REG_WLAN_ISO_CNTL_GET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x) +#define POWER_REG_WLAN_ISO_CNTL_SET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x) +#define POWER_REG_RADIO_PWD_EN_MSB WLAN_POWER_REG_RADIO_PWD_EN_MSB +#define POWER_REG_RADIO_PWD_EN_LSB WLAN_POWER_REG_RADIO_PWD_EN_LSB +#define POWER_REG_RADIO_PWD_EN_MASK WLAN_POWER_REG_RADIO_PWD_EN_MASK +#define POWER_REG_RADIO_PWD_EN_GET(x) WLAN_POWER_REG_RADIO_PWD_EN_GET(x) +#define POWER_REG_RADIO_PWD_EN_SET(x) WLAN_POWER_REG_RADIO_PWD_EN_SET(x) +#define POWER_REG_SOC_ISO_EN_MSB WLAN_POWER_REG_SOC_ISO_EN_MSB +#define POWER_REG_SOC_ISO_EN_LSB WLAN_POWER_REG_SOC_ISO_EN_LSB +#define POWER_REG_SOC_ISO_EN_MASK WLAN_POWER_REG_SOC_ISO_EN_MASK +#define POWER_REG_SOC_ISO_EN_GET(x) WLAN_POWER_REG_SOC_ISO_EN_GET(x) +#define POWER_REG_SOC_ISO_EN_SET(x) WLAN_POWER_REG_SOC_ISO_EN_SET(x) +#define POWER_REG_WLAN_ISO_EN_MSB WLAN_POWER_REG_WLAN_ISO_EN_MSB +#define POWER_REG_WLAN_ISO_EN_LSB WLAN_POWER_REG_WLAN_ISO_EN_LSB +#define POWER_REG_WLAN_ISO_EN_MASK WLAN_POWER_REG_WLAN_ISO_EN_MASK +#define POWER_REG_WLAN_ISO_EN_GET(x) WLAN_POWER_REG_WLAN_ISO_EN_GET(x) +#define POWER_REG_WLAN_ISO_EN_SET(x) WLAN_POWER_REG_WLAN_ISO_EN_SET(x) +#define POWER_REG_WLAN_PWD_EN_MSB WLAN_POWER_REG_WLAN_PWD_EN_MSB +#define POWER_REG_WLAN_PWD_EN_LSB WLAN_POWER_REG_WLAN_PWD_EN_LSB +#define POWER_REG_WLAN_PWD_EN_MASK WLAN_POWER_REG_WLAN_PWD_EN_MASK +#define POWER_REG_WLAN_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_PWD_EN_GET(x) +#define POWER_REG_WLAN_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_PWD_EN_SET(x) +#define POWER_REG_POWER_EN_MSB WLAN_POWER_REG_POWER_EN_MSB +#define POWER_REG_POWER_EN_LSB WLAN_POWER_REG_POWER_EN_LSB +#define POWER_REG_POWER_EN_MASK WLAN_POWER_REG_POWER_EN_MASK +#define POWER_REG_POWER_EN_GET(x) WLAN_POWER_REG_POWER_EN_GET(x) +#define POWER_REG_POWER_EN_SET(x) WLAN_POWER_REG_POWER_EN_SET(x) +#define CORE_CLK_CTRL_ADDRESS WLAN_CORE_CLK_CTRL_ADDRESS +#define CORE_CLK_CTRL_OFFSET WLAN_CORE_CLK_CTRL_OFFSET +#define CORE_CLK_CTRL_DIV_MSB WLAN_CORE_CLK_CTRL_DIV_MSB +#define CORE_CLK_CTRL_DIV_LSB WLAN_CORE_CLK_CTRL_DIV_LSB +#define CORE_CLK_CTRL_DIV_MASK WLAN_CORE_CLK_CTRL_DIV_MASK +#define CORE_CLK_CTRL_DIV_GET(x) WLAN_CORE_CLK_CTRL_DIV_GET(x) +#define CORE_CLK_CTRL_DIV_SET(x) WLAN_CORE_CLK_CTRL_DIV_SET(x) +#define GPIO_WAKEUP_CONTROL_ADDRESS WLAN_GPIO_WAKEUP_CONTROL_ADDRESS +#define GPIO_WAKEUP_CONTROL_OFFSET WLAN_GPIO_WAKEUP_CONTROL_OFFSET +#define GPIO_WAKEUP_CONTROL_ENABLE_MSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB +#define GPIO_WAKEUP_CONTROL_ENABLE_LSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB +#define GPIO_WAKEUP_CONTROL_ENABLE_MASK WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK +#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x) +#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x) + + +#endif +#endif + + + diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_wlan_reg.h new file mode 100644 index 000000000000..abf872650054 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_wlan_reg.h @@ -0,0 +1,2065 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _RTC_WLAN_REG_REG_H_ +#define _RTC_WLAN_REG_REG_H_ + +#define WLAN_RESET_CONTROL_ADDRESS 0x00000000 +#define WLAN_RESET_CONTROL_OFFSET 0x00000000 +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB 14 +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB 14 +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK 0x00004000 +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x) (((x) & WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK) >> WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB) +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x) (((x) << WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB) & WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK) +#define WLAN_RESET_CONTROL_BB_COLD_RST_MSB 13 +#define WLAN_RESET_CONTROL_BB_COLD_RST_LSB 13 +#define WLAN_RESET_CONTROL_BB_COLD_RST_MASK 0x00002000 +#define WLAN_RESET_CONTROL_BB_COLD_RST_GET(x) (((x) & WLAN_RESET_CONTROL_BB_COLD_RST_MASK) >> WLAN_RESET_CONTROL_BB_COLD_RST_LSB) +#define WLAN_RESET_CONTROL_BB_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_BB_COLD_RST_LSB) & WLAN_RESET_CONTROL_BB_COLD_RST_MASK) +#define WLAN_RESET_CONTROL_BB_WARM_RST_MSB 12 +#define WLAN_RESET_CONTROL_BB_WARM_RST_LSB 12 +#define WLAN_RESET_CONTROL_BB_WARM_RST_MASK 0x00001000 +#define WLAN_RESET_CONTROL_BB_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_BB_WARM_RST_MASK) >> WLAN_RESET_CONTROL_BB_WARM_RST_LSB) +#define WLAN_RESET_CONTROL_BB_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_BB_WARM_RST_LSB) & WLAN_RESET_CONTROL_BB_WARM_RST_MASK) +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB 11 +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB 11 +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800 +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK) >> WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB) +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB) & WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK) +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB 10 +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB 10 +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400 +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK) >> WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB) +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB) & WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK) +#define WLAN_RESET_CONTROL_RST_OUT_MSB 9 +#define WLAN_RESET_CONTROL_RST_OUT_LSB 9 +#define WLAN_RESET_CONTROL_RST_OUT_MASK 0x00000200 +#define WLAN_RESET_CONTROL_RST_OUT_GET(x) (((x) & WLAN_RESET_CONTROL_RST_OUT_MASK) >> WLAN_RESET_CONTROL_RST_OUT_LSB) +#define WLAN_RESET_CONTROL_RST_OUT_SET(x) (((x) << WLAN_RESET_CONTROL_RST_OUT_LSB) & WLAN_RESET_CONTROL_RST_OUT_MASK) +#define WLAN_RESET_CONTROL_COLD_RST_MSB 8 +#define WLAN_RESET_CONTROL_COLD_RST_LSB 8 +#define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000100 +#define WLAN_RESET_CONTROL_COLD_RST_GET(x) (((x) & WLAN_RESET_CONTROL_COLD_RST_MASK) >> WLAN_RESET_CONTROL_COLD_RST_LSB) +#define WLAN_RESET_CONTROL_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_COLD_RST_LSB) & WLAN_RESET_CONTROL_COLD_RST_MASK) +#define WLAN_RESET_CONTROL_WARM_RST_MSB 7 +#define WLAN_RESET_CONTROL_WARM_RST_LSB 7 +#define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000080 +#define WLAN_RESET_CONTROL_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_WARM_RST_MASK) >> WLAN_RESET_CONTROL_WARM_RST_LSB) +#define WLAN_RESET_CONTROL_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_WARM_RST_LSB) & WLAN_RESET_CONTROL_WARM_RST_MASK) +#define WLAN_RESET_CONTROL_CPU_WARM_RST_MSB 6 +#define WLAN_RESET_CONTROL_CPU_WARM_RST_LSB 6 +#define WLAN_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 +#define WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_CPU_WARM_RST_MASK) >> WLAN_RESET_CONTROL_CPU_WARM_RST_LSB) +#define WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_CPU_WARM_RST_LSB) & WLAN_RESET_CONTROL_CPU_WARM_RST_MASK) +#define WLAN_RESET_CONTROL_MAC_COLD_RST_MSB 5 +#define WLAN_RESET_CONTROL_MAC_COLD_RST_LSB 5 +#define WLAN_RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020 +#define WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x) (((x) & WLAN_RESET_CONTROL_MAC_COLD_RST_MASK) >> WLAN_RESET_CONTROL_MAC_COLD_RST_LSB) +#define WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MAC_COLD_RST_LSB) & WLAN_RESET_CONTROL_MAC_COLD_RST_MASK) +#define WLAN_RESET_CONTROL_MAC_WARM_RST_MSB 4 +#define WLAN_RESET_CONTROL_MAC_WARM_RST_LSB 4 +#define WLAN_RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010 +#define WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_MAC_WARM_RST_MASK) >> WLAN_RESET_CONTROL_MAC_WARM_RST_LSB) +#define WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MAC_WARM_RST_LSB) & WLAN_RESET_CONTROL_MAC_WARM_RST_MASK) +#define WLAN_RESET_CONTROL_MBOX_RST_MSB 2 +#define WLAN_RESET_CONTROL_MBOX_RST_LSB 2 +#define WLAN_RESET_CONTROL_MBOX_RST_MASK 0x00000004 +#define WLAN_RESET_CONTROL_MBOX_RST_GET(x) (((x) & WLAN_RESET_CONTROL_MBOX_RST_MASK) >> WLAN_RESET_CONTROL_MBOX_RST_LSB) +#define WLAN_RESET_CONTROL_MBOX_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MBOX_RST_LSB) & WLAN_RESET_CONTROL_MBOX_RST_MASK) +#define WLAN_RESET_CONTROL_UART_RST_MSB 1 +#define WLAN_RESET_CONTROL_UART_RST_LSB 1 +#define WLAN_RESET_CONTROL_UART_RST_MASK 0x00000002 +#define WLAN_RESET_CONTROL_UART_RST_GET(x) (((x) & WLAN_RESET_CONTROL_UART_RST_MASK) >> WLAN_RESET_CONTROL_UART_RST_LSB) +#define WLAN_RESET_CONTROL_UART_RST_SET(x) (((x) << WLAN_RESET_CONTROL_UART_RST_LSB) & WLAN_RESET_CONTROL_UART_RST_MASK) +#define WLAN_RESET_CONTROL_SI0_RST_MSB 0 +#define WLAN_RESET_CONTROL_SI0_RST_LSB 0 +#define WLAN_RESET_CONTROL_SI0_RST_MASK 0x00000001 +#define WLAN_RESET_CONTROL_SI0_RST_GET(x) (((x) & WLAN_RESET_CONTROL_SI0_RST_MASK) >> WLAN_RESET_CONTROL_SI0_RST_LSB) +#define WLAN_RESET_CONTROL_SI0_RST_SET(x) (((x) << WLAN_RESET_CONTROL_SI0_RST_LSB) & WLAN_RESET_CONTROL_SI0_RST_MASK) + +#define WLAN_XTAL_CONTROL_ADDRESS 0x00000004 +#define WLAN_XTAL_CONTROL_OFFSET 0x00000004 +#define WLAN_XTAL_CONTROL_TCXO_MSB 0 +#define WLAN_XTAL_CONTROL_TCXO_LSB 0 +#define WLAN_XTAL_CONTROL_TCXO_MASK 0x00000001 +#define WLAN_XTAL_CONTROL_TCXO_GET(x) (((x) & WLAN_XTAL_CONTROL_TCXO_MASK) >> WLAN_XTAL_CONTROL_TCXO_LSB) +#define WLAN_XTAL_CONTROL_TCXO_SET(x) (((x) << WLAN_XTAL_CONTROL_TCXO_LSB) & WLAN_XTAL_CONTROL_TCXO_MASK) + +#define WLAN_TCXO_DETECT_ADDRESS 0x00000008 +#define WLAN_TCXO_DETECT_OFFSET 0x00000008 +#define WLAN_TCXO_DETECT_PRESENT_MSB 0 +#define WLAN_TCXO_DETECT_PRESENT_LSB 0 +#define WLAN_TCXO_DETECT_PRESENT_MASK 0x00000001 +#define WLAN_TCXO_DETECT_PRESENT_GET(x) (((x) & WLAN_TCXO_DETECT_PRESENT_MASK) >> WLAN_TCXO_DETECT_PRESENT_LSB) +#define WLAN_TCXO_DETECT_PRESENT_SET(x) (((x) << WLAN_TCXO_DETECT_PRESENT_LSB) & WLAN_TCXO_DETECT_PRESENT_MASK) + +#define WLAN_XTAL_TEST_ADDRESS 0x0000000c +#define WLAN_XTAL_TEST_OFFSET 0x0000000c +#define WLAN_XTAL_TEST_NOTCXODET_MSB 0 +#define WLAN_XTAL_TEST_NOTCXODET_LSB 0 +#define WLAN_XTAL_TEST_NOTCXODET_MASK 0x00000001 +#define WLAN_XTAL_TEST_NOTCXODET_GET(x) (((x) & WLAN_XTAL_TEST_NOTCXODET_MASK) >> WLAN_XTAL_TEST_NOTCXODET_LSB) +#define WLAN_XTAL_TEST_NOTCXODET_SET(x) (((x) << WLAN_XTAL_TEST_NOTCXODET_LSB) & WLAN_XTAL_TEST_NOTCXODET_MASK) + +#define WLAN_QUADRATURE_ADDRESS 0x00000010 +#define WLAN_QUADRATURE_OFFSET 0x00000010 +#define WLAN_QUADRATURE_ADC_MSB 7 +#define WLAN_QUADRATURE_ADC_LSB 4 +#define WLAN_QUADRATURE_ADC_MASK 0x000000f0 +#define WLAN_QUADRATURE_ADC_GET(x) (((x) & WLAN_QUADRATURE_ADC_MASK) >> WLAN_QUADRATURE_ADC_LSB) +#define WLAN_QUADRATURE_ADC_SET(x) (((x) << WLAN_QUADRATURE_ADC_LSB) & WLAN_QUADRATURE_ADC_MASK) +#define WLAN_QUADRATURE_SEL_MSB 2 +#define WLAN_QUADRATURE_SEL_LSB 2 +#define WLAN_QUADRATURE_SEL_MASK 0x00000004 +#define WLAN_QUADRATURE_SEL_GET(x) (((x) & WLAN_QUADRATURE_SEL_MASK) >> WLAN_QUADRATURE_SEL_LSB) +#define WLAN_QUADRATURE_SEL_SET(x) (((x) << WLAN_QUADRATURE_SEL_LSB) & WLAN_QUADRATURE_SEL_MASK) +#define WLAN_QUADRATURE_DAC_MSB 1 +#define WLAN_QUADRATURE_DAC_LSB 0 +#define WLAN_QUADRATURE_DAC_MASK 0x00000003 +#define WLAN_QUADRATURE_DAC_GET(x) (((x) & WLAN_QUADRATURE_DAC_MASK) >> WLAN_QUADRATURE_DAC_LSB) +#define WLAN_QUADRATURE_DAC_SET(x) (((x) << WLAN_QUADRATURE_DAC_LSB) & WLAN_QUADRATURE_DAC_MASK) + +#define WLAN_PLL_CONTROL_ADDRESS 0x00000014 +#define WLAN_PLL_CONTROL_OFFSET 0x00000014 +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB 20 +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB 20 +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000 +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x) (((x) & WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK) >> WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB) +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x) (((x) << WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB) & WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK) +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB 19 +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB 19 +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000 +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x) (((x) & WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK) >> WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB) +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x) (((x) << WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB) & WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK) +#define WLAN_PLL_CONTROL_NOPWD_MSB 18 +#define WLAN_PLL_CONTROL_NOPWD_LSB 18 +#define WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000 +#define WLAN_PLL_CONTROL_NOPWD_GET(x) (((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB) +#define WLAN_PLL_CONTROL_NOPWD_SET(x) (((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK) +#define WLAN_PLL_CONTROL_UPDATING_MSB 17 +#define WLAN_PLL_CONTROL_UPDATING_LSB 17 +#define WLAN_PLL_CONTROL_UPDATING_MASK 0x00020000 +#define WLAN_PLL_CONTROL_UPDATING_GET(x) (((x) & WLAN_PLL_CONTROL_UPDATING_MASK) >> WLAN_PLL_CONTROL_UPDATING_LSB) +#define WLAN_PLL_CONTROL_UPDATING_SET(x) (((x) << WLAN_PLL_CONTROL_UPDATING_LSB) & WLAN_PLL_CONTROL_UPDATING_MASK) +#define WLAN_PLL_CONTROL_BYPASS_MSB 16 +#define WLAN_PLL_CONTROL_BYPASS_LSB 16 +#define WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000 +#define WLAN_PLL_CONTROL_BYPASS_GET(x) (((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB) +#define WLAN_PLL_CONTROL_BYPASS_SET(x) (((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK) +#define WLAN_PLL_CONTROL_REFDIV_MSB 15 +#define WLAN_PLL_CONTROL_REFDIV_LSB 12 +#define WLAN_PLL_CONTROL_REFDIV_MASK 0x0000f000 +#define WLAN_PLL_CONTROL_REFDIV_GET(x) (((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB) +#define WLAN_PLL_CONTROL_REFDIV_SET(x) (((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK) +#define WLAN_PLL_CONTROL_DIV_MSB 9 +#define WLAN_PLL_CONTROL_DIV_LSB 0 +#define WLAN_PLL_CONTROL_DIV_MASK 0x000003ff +#define WLAN_PLL_CONTROL_DIV_GET(x) (((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB) +#define WLAN_PLL_CONTROL_DIV_SET(x) (((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK) + +#define WLAN_PLL_SETTLE_ADDRESS 0x00000018 +#define WLAN_PLL_SETTLE_OFFSET 0x00000018 +#define WLAN_PLL_SETTLE_TIME_MSB 11 +#define WLAN_PLL_SETTLE_TIME_LSB 0 +#define WLAN_PLL_SETTLE_TIME_MASK 0x00000fff +#define WLAN_PLL_SETTLE_TIME_GET(x) (((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB) +#define WLAN_PLL_SETTLE_TIME_SET(x) (((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK) + +#define WLAN_XTAL_SETTLE_ADDRESS 0x0000001c +#define WLAN_XTAL_SETTLE_OFFSET 0x0000001c +#define WLAN_XTAL_SETTLE_TIME_MSB 7 +#define WLAN_XTAL_SETTLE_TIME_LSB 0 +#define WLAN_XTAL_SETTLE_TIME_MASK 0x000000ff +#define WLAN_XTAL_SETTLE_TIME_GET(x) (((x) & WLAN_XTAL_SETTLE_TIME_MASK) >> WLAN_XTAL_SETTLE_TIME_LSB) +#define WLAN_XTAL_SETTLE_TIME_SET(x) (((x) << WLAN_XTAL_SETTLE_TIME_LSB) & WLAN_XTAL_SETTLE_TIME_MASK) + +#define WLAN_CPU_CLOCK_ADDRESS 0x00000020 +#define WLAN_CPU_CLOCK_OFFSET 0x00000020 +#define WLAN_CPU_CLOCK_STANDARD_MSB 1 +#define WLAN_CPU_CLOCK_STANDARD_LSB 0 +#define WLAN_CPU_CLOCK_STANDARD_MASK 0x00000003 +#define WLAN_CPU_CLOCK_STANDARD_GET(x) (((x) & WLAN_CPU_CLOCK_STANDARD_MASK) >> WLAN_CPU_CLOCK_STANDARD_LSB) +#define WLAN_CPU_CLOCK_STANDARD_SET(x) (((x) << WLAN_CPU_CLOCK_STANDARD_LSB) & WLAN_CPU_CLOCK_STANDARD_MASK) + +#define WLAN_CLOCK_OUT_ADDRESS 0x00000024 +#define WLAN_CLOCK_OUT_OFFSET 0x00000024 +#define WLAN_CLOCK_OUT_SELECT_MSB 3 +#define WLAN_CLOCK_OUT_SELECT_LSB 0 +#define WLAN_CLOCK_OUT_SELECT_MASK 0x0000000f +#define WLAN_CLOCK_OUT_SELECT_GET(x) (((x) & WLAN_CLOCK_OUT_SELECT_MASK) >> WLAN_CLOCK_OUT_SELECT_LSB) +#define WLAN_CLOCK_OUT_SELECT_SET(x) (((x) << WLAN_CLOCK_OUT_SELECT_LSB) & WLAN_CLOCK_OUT_SELECT_MASK) + +#define WLAN_CLOCK_CONTROL_ADDRESS 0x00000028 +#define WLAN_CLOCK_CONTROL_OFFSET 0x00000028 +#define WLAN_CLOCK_CONTROL_LF_CLK32_MSB 2 +#define WLAN_CLOCK_CONTROL_LF_CLK32_LSB 2 +#define WLAN_CLOCK_CONTROL_LF_CLK32_MASK 0x00000004 +#define WLAN_CLOCK_CONTROL_LF_CLK32_GET(x) (((x) & WLAN_CLOCK_CONTROL_LF_CLK32_MASK) >> WLAN_CLOCK_CONTROL_LF_CLK32_LSB) +#define WLAN_CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << WLAN_CLOCK_CONTROL_LF_CLK32_LSB) & WLAN_CLOCK_CONTROL_LF_CLK32_MASK) +#define WLAN_CLOCK_CONTROL_SI0_CLK_MSB 0 +#define WLAN_CLOCK_CONTROL_SI0_CLK_LSB 0 +#define WLAN_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 +#define WLAN_CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK) >> WLAN_CLOCK_CONTROL_SI0_CLK_LSB) +#define WLAN_CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << WLAN_CLOCK_CONTROL_SI0_CLK_LSB) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK) + +#define WLAN_BIAS_OVERRIDE_ADDRESS 0x0000002c +#define WLAN_BIAS_OVERRIDE_OFFSET 0x0000002c +#define WLAN_BIAS_OVERRIDE_ON_MSB 0 +#define WLAN_BIAS_OVERRIDE_ON_LSB 0 +#define WLAN_BIAS_OVERRIDE_ON_MASK 0x00000001 +#define WLAN_BIAS_OVERRIDE_ON_GET(x) (((x) & WLAN_BIAS_OVERRIDE_ON_MASK) >> WLAN_BIAS_OVERRIDE_ON_LSB) +#define WLAN_BIAS_OVERRIDE_ON_SET(x) (((x) << WLAN_BIAS_OVERRIDE_ON_LSB) & WLAN_BIAS_OVERRIDE_ON_MASK) + +#define WLAN_WDT_CONTROL_ADDRESS 0x00000030 +#define WLAN_WDT_CONTROL_OFFSET 0x00000030 +#define WLAN_WDT_CONTROL_ACTION_MSB 2 +#define WLAN_WDT_CONTROL_ACTION_LSB 0 +#define WLAN_WDT_CONTROL_ACTION_MASK 0x00000007 +#define WLAN_WDT_CONTROL_ACTION_GET(x) (((x) & WLAN_WDT_CONTROL_ACTION_MASK) >> WLAN_WDT_CONTROL_ACTION_LSB) +#define WLAN_WDT_CONTROL_ACTION_SET(x) (((x) << WLAN_WDT_CONTROL_ACTION_LSB) & WLAN_WDT_CONTROL_ACTION_MASK) + +#define WLAN_WDT_STATUS_ADDRESS 0x00000034 +#define WLAN_WDT_STATUS_OFFSET 0x00000034 +#define WLAN_WDT_STATUS_INTERRUPT_MSB 0 +#define WLAN_WDT_STATUS_INTERRUPT_LSB 0 +#define WLAN_WDT_STATUS_INTERRUPT_MASK 0x00000001 +#define WLAN_WDT_STATUS_INTERRUPT_GET(x) (((x) & WLAN_WDT_STATUS_INTERRUPT_MASK) >> WLAN_WDT_STATUS_INTERRUPT_LSB) +#define WLAN_WDT_STATUS_INTERRUPT_SET(x) (((x) << WLAN_WDT_STATUS_INTERRUPT_LSB) & WLAN_WDT_STATUS_INTERRUPT_MASK) + +#define WLAN_WDT_ADDRESS 0x00000038 +#define WLAN_WDT_OFFSET 0x00000038 +#define WLAN_WDT_TARGET_MSB 21 +#define WLAN_WDT_TARGET_LSB 0 +#define WLAN_WDT_TARGET_MASK 0x003fffff +#define WLAN_WDT_TARGET_GET(x) (((x) & WLAN_WDT_TARGET_MASK) >> WLAN_WDT_TARGET_LSB) +#define WLAN_WDT_TARGET_SET(x) (((x) << WLAN_WDT_TARGET_LSB) & WLAN_WDT_TARGET_MASK) + +#define WLAN_WDT_COUNT_ADDRESS 0x0000003c +#define WLAN_WDT_COUNT_OFFSET 0x0000003c +#define WLAN_WDT_COUNT_VALUE_MSB 21 +#define WLAN_WDT_COUNT_VALUE_LSB 0 +#define WLAN_WDT_COUNT_VALUE_MASK 0x003fffff +#define WLAN_WDT_COUNT_VALUE_GET(x) (((x) & WLAN_WDT_COUNT_VALUE_MASK) >> WLAN_WDT_COUNT_VALUE_LSB) +#define WLAN_WDT_COUNT_VALUE_SET(x) (((x) << WLAN_WDT_COUNT_VALUE_LSB) & WLAN_WDT_COUNT_VALUE_MASK) + +#define WLAN_WDT_RESET_ADDRESS 0x00000040 +#define WLAN_WDT_RESET_OFFSET 0x00000040 +#define WLAN_WDT_RESET_VALUE_MSB 0 +#define WLAN_WDT_RESET_VALUE_LSB 0 +#define WLAN_WDT_RESET_VALUE_MASK 0x00000001 +#define WLAN_WDT_RESET_VALUE_GET(x) (((x) & WLAN_WDT_RESET_VALUE_MASK) >> WLAN_WDT_RESET_VALUE_LSB) +#define WLAN_WDT_RESET_VALUE_SET(x) (((x) << WLAN_WDT_RESET_VALUE_LSB) & WLAN_WDT_RESET_VALUE_MASK) + +#define WLAN_INT_STATUS_ADDRESS 0x00000044 +#define WLAN_INT_STATUS_OFFSET 0x00000044 +#define WLAN_INT_STATUS_HCI_UART_MSB 21 +#define WLAN_INT_STATUS_HCI_UART_LSB 21 +#define WLAN_INT_STATUS_HCI_UART_MASK 0x00200000 +#define WLAN_INT_STATUS_HCI_UART_GET(x) (((x) & WLAN_INT_STATUS_HCI_UART_MASK) >> WLAN_INT_STATUS_HCI_UART_LSB) +#define WLAN_INT_STATUS_HCI_UART_SET(x) (((x) << WLAN_INT_STATUS_HCI_UART_LSB) & WLAN_INT_STATUS_HCI_UART_MASK) +#define WLAN_INT_STATUS_THERM_MSB 20 +#define WLAN_INT_STATUS_THERM_LSB 20 +#define WLAN_INT_STATUS_THERM_MASK 0x00100000 +#define WLAN_INT_STATUS_THERM_GET(x) (((x) & WLAN_INT_STATUS_THERM_MASK) >> WLAN_INT_STATUS_THERM_LSB) +#define WLAN_INT_STATUS_THERM_SET(x) (((x) << WLAN_INT_STATUS_THERM_LSB) & WLAN_INT_STATUS_THERM_MASK) +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB 19 +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB 19 +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK 0x00080000 +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x) (((x) & WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK) >> WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB) +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x) (((x) << WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB) & WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK) +#define WLAN_INT_STATUS_UART_MBOX_MSB 18 +#define WLAN_INT_STATUS_UART_MBOX_LSB 18 +#define WLAN_INT_STATUS_UART_MBOX_MASK 0x00040000 +#define WLAN_INT_STATUS_UART_MBOX_GET(x) (((x) & WLAN_INT_STATUS_UART_MBOX_MASK) >> WLAN_INT_STATUS_UART_MBOX_LSB) +#define WLAN_INT_STATUS_UART_MBOX_SET(x) (((x) << WLAN_INT_STATUS_UART_MBOX_LSB) & WLAN_INT_STATUS_UART_MBOX_MASK) +#define WLAN_INT_STATUS_GENERIC_MBOX_MSB 17 +#define WLAN_INT_STATUS_GENERIC_MBOX_LSB 17 +#define WLAN_INT_STATUS_GENERIC_MBOX_MASK 0x00020000 +#define WLAN_INT_STATUS_GENERIC_MBOX_GET(x) (((x) & WLAN_INT_STATUS_GENERIC_MBOX_MASK) >> WLAN_INT_STATUS_GENERIC_MBOX_LSB) +#define WLAN_INT_STATUS_GENERIC_MBOX_SET(x) (((x) << WLAN_INT_STATUS_GENERIC_MBOX_LSB) & WLAN_INT_STATUS_GENERIC_MBOX_MASK) +#define WLAN_INT_STATUS_RDMA_MSB 16 +#define WLAN_INT_STATUS_RDMA_LSB 16 +#define WLAN_INT_STATUS_RDMA_MASK 0x00010000 +#define WLAN_INT_STATUS_RDMA_GET(x) (((x) & WLAN_INT_STATUS_RDMA_MASK) >> WLAN_INT_STATUS_RDMA_LSB) +#define WLAN_INT_STATUS_RDMA_SET(x) (((x) << WLAN_INT_STATUS_RDMA_LSB) & WLAN_INT_STATUS_RDMA_MASK) +#define WLAN_INT_STATUS_BTCOEX_MSB 15 +#define WLAN_INT_STATUS_BTCOEX_LSB 15 +#define WLAN_INT_STATUS_BTCOEX_MASK 0x00008000 +#define WLAN_INT_STATUS_BTCOEX_GET(x) (((x) & WLAN_INT_STATUS_BTCOEX_MASK) >> WLAN_INT_STATUS_BTCOEX_LSB) +#define WLAN_INT_STATUS_BTCOEX_SET(x) (((x) << WLAN_INT_STATUS_BTCOEX_LSB) & WLAN_INT_STATUS_BTCOEX_MASK) +#define WLAN_INT_STATUS_RTC_POWER_MSB 14 +#define WLAN_INT_STATUS_RTC_POWER_LSB 14 +#define WLAN_INT_STATUS_RTC_POWER_MASK 0x00004000 +#define WLAN_INT_STATUS_RTC_POWER_GET(x) (((x) & WLAN_INT_STATUS_RTC_POWER_MASK) >> WLAN_INT_STATUS_RTC_POWER_LSB) +#define WLAN_INT_STATUS_RTC_POWER_SET(x) (((x) << WLAN_INT_STATUS_RTC_POWER_LSB) & WLAN_INT_STATUS_RTC_POWER_MASK) +#define WLAN_INT_STATUS_MAC_MSB 13 +#define WLAN_INT_STATUS_MAC_LSB 13 +#define WLAN_INT_STATUS_MAC_MASK 0x00002000 +#define WLAN_INT_STATUS_MAC_GET(x) (((x) & WLAN_INT_STATUS_MAC_MASK) >> WLAN_INT_STATUS_MAC_LSB) +#define WLAN_INT_STATUS_MAC_SET(x) (((x) << WLAN_INT_STATUS_MAC_LSB) & WLAN_INT_STATUS_MAC_MASK) +#define WLAN_INT_STATUS_MAILBOX_MSB 12 +#define WLAN_INT_STATUS_MAILBOX_LSB 12 +#define WLAN_INT_STATUS_MAILBOX_MASK 0x00001000 +#define WLAN_INT_STATUS_MAILBOX_GET(x) (((x) & WLAN_INT_STATUS_MAILBOX_MASK) >> WLAN_INT_STATUS_MAILBOX_LSB) +#define WLAN_INT_STATUS_MAILBOX_SET(x) (((x) << WLAN_INT_STATUS_MAILBOX_LSB) & WLAN_INT_STATUS_MAILBOX_MASK) +#define WLAN_INT_STATUS_RTC_ALARM_MSB 11 +#define WLAN_INT_STATUS_RTC_ALARM_LSB 11 +#define WLAN_INT_STATUS_RTC_ALARM_MASK 0x00000800 +#define WLAN_INT_STATUS_RTC_ALARM_GET(x) (((x) & WLAN_INT_STATUS_RTC_ALARM_MASK) >> WLAN_INT_STATUS_RTC_ALARM_LSB) +#define WLAN_INT_STATUS_RTC_ALARM_SET(x) (((x) << WLAN_INT_STATUS_RTC_ALARM_LSB) & WLAN_INT_STATUS_RTC_ALARM_MASK) +#define WLAN_INT_STATUS_HF_TIMER_MSB 10 +#define WLAN_INT_STATUS_HF_TIMER_LSB 10 +#define WLAN_INT_STATUS_HF_TIMER_MASK 0x00000400 +#define WLAN_INT_STATUS_HF_TIMER_GET(x) (((x) & WLAN_INT_STATUS_HF_TIMER_MASK) >> WLAN_INT_STATUS_HF_TIMER_LSB) +#define WLAN_INT_STATUS_HF_TIMER_SET(x) (((x) << WLAN_INT_STATUS_HF_TIMER_LSB) & WLAN_INT_STATUS_HF_TIMER_MASK) +#define WLAN_INT_STATUS_LF_TIMER3_MSB 9 +#define WLAN_INT_STATUS_LF_TIMER3_LSB 9 +#define WLAN_INT_STATUS_LF_TIMER3_MASK 0x00000200 +#define WLAN_INT_STATUS_LF_TIMER3_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER3_MASK) >> WLAN_INT_STATUS_LF_TIMER3_LSB) +#define WLAN_INT_STATUS_LF_TIMER3_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER3_LSB) & WLAN_INT_STATUS_LF_TIMER3_MASK) +#define WLAN_INT_STATUS_LF_TIMER2_MSB 8 +#define WLAN_INT_STATUS_LF_TIMER2_LSB 8 +#define WLAN_INT_STATUS_LF_TIMER2_MASK 0x00000100 +#define WLAN_INT_STATUS_LF_TIMER2_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER2_MASK) >> WLAN_INT_STATUS_LF_TIMER2_LSB) +#define WLAN_INT_STATUS_LF_TIMER2_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER2_LSB) & WLAN_INT_STATUS_LF_TIMER2_MASK) +#define WLAN_INT_STATUS_LF_TIMER1_MSB 7 +#define WLAN_INT_STATUS_LF_TIMER1_LSB 7 +#define WLAN_INT_STATUS_LF_TIMER1_MASK 0x00000080 +#define WLAN_INT_STATUS_LF_TIMER1_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER1_MASK) >> WLAN_INT_STATUS_LF_TIMER1_LSB) +#define WLAN_INT_STATUS_LF_TIMER1_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER1_LSB) & WLAN_INT_STATUS_LF_TIMER1_MASK) +#define WLAN_INT_STATUS_LF_TIMER0_MSB 6 +#define WLAN_INT_STATUS_LF_TIMER0_LSB 6 +#define WLAN_INT_STATUS_LF_TIMER0_MASK 0x00000040 +#define WLAN_INT_STATUS_LF_TIMER0_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER0_MASK) >> WLAN_INT_STATUS_LF_TIMER0_LSB) +#define WLAN_INT_STATUS_LF_TIMER0_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER0_LSB) & WLAN_INT_STATUS_LF_TIMER0_MASK) +#define WLAN_INT_STATUS_KEYPAD_MSB 5 +#define WLAN_INT_STATUS_KEYPAD_LSB 5 +#define WLAN_INT_STATUS_KEYPAD_MASK 0x00000020 +#define WLAN_INT_STATUS_KEYPAD_GET(x) (((x) & WLAN_INT_STATUS_KEYPAD_MASK) >> WLAN_INT_STATUS_KEYPAD_LSB) +#define WLAN_INT_STATUS_KEYPAD_SET(x) (((x) << WLAN_INT_STATUS_KEYPAD_LSB) & WLAN_INT_STATUS_KEYPAD_MASK) +#define WLAN_INT_STATUS_SI_MSB 4 +#define WLAN_INT_STATUS_SI_LSB 4 +#define WLAN_INT_STATUS_SI_MASK 0x00000010 +#define WLAN_INT_STATUS_SI_GET(x) (((x) & WLAN_INT_STATUS_SI_MASK) >> WLAN_INT_STATUS_SI_LSB) +#define WLAN_INT_STATUS_SI_SET(x) (((x) << WLAN_INT_STATUS_SI_LSB) & WLAN_INT_STATUS_SI_MASK) +#define WLAN_INT_STATUS_GPIO_MSB 3 +#define WLAN_INT_STATUS_GPIO_LSB 3 +#define WLAN_INT_STATUS_GPIO_MASK 0x00000008 +#define WLAN_INT_STATUS_GPIO_GET(x) (((x) & WLAN_INT_STATUS_GPIO_MASK) >> WLAN_INT_STATUS_GPIO_LSB) +#define WLAN_INT_STATUS_GPIO_SET(x) (((x) << WLAN_INT_STATUS_GPIO_LSB) & WLAN_INT_STATUS_GPIO_MASK) +#define WLAN_INT_STATUS_UART_MSB 2 +#define WLAN_INT_STATUS_UART_LSB 2 +#define WLAN_INT_STATUS_UART_MASK 0x00000004 +#define WLAN_INT_STATUS_UART_GET(x) (((x) & WLAN_INT_STATUS_UART_MASK) >> WLAN_INT_STATUS_UART_LSB) +#define WLAN_INT_STATUS_UART_SET(x) (((x) << WLAN_INT_STATUS_UART_LSB) & WLAN_INT_STATUS_UART_MASK) +#define WLAN_INT_STATUS_ERROR_MSB 1 +#define WLAN_INT_STATUS_ERROR_LSB 1 +#define WLAN_INT_STATUS_ERROR_MASK 0x00000002 +#define WLAN_INT_STATUS_ERROR_GET(x) (((x) & WLAN_INT_STATUS_ERROR_MASK) >> WLAN_INT_STATUS_ERROR_LSB) +#define WLAN_INT_STATUS_ERROR_SET(x) (((x) << WLAN_INT_STATUS_ERROR_LSB) & WLAN_INT_STATUS_ERROR_MASK) +#define WLAN_INT_STATUS_WDT_INT_MSB 0 +#define WLAN_INT_STATUS_WDT_INT_LSB 0 +#define WLAN_INT_STATUS_WDT_INT_MASK 0x00000001 +#define WLAN_INT_STATUS_WDT_INT_GET(x) (((x) & WLAN_INT_STATUS_WDT_INT_MASK) >> WLAN_INT_STATUS_WDT_INT_LSB) +#define WLAN_INT_STATUS_WDT_INT_SET(x) (((x) << WLAN_INT_STATUS_WDT_INT_LSB) & WLAN_INT_STATUS_WDT_INT_MASK) + +#define WLAN_LF_TIMER0_ADDRESS 0x00000048 +#define WLAN_LF_TIMER0_OFFSET 0x00000048 +#define WLAN_LF_TIMER0_TARGET_MSB 31 +#define WLAN_LF_TIMER0_TARGET_LSB 0 +#define WLAN_LF_TIMER0_TARGET_MASK 0xffffffff +#define WLAN_LF_TIMER0_TARGET_GET(x) (((x) & WLAN_LF_TIMER0_TARGET_MASK) >> WLAN_LF_TIMER0_TARGET_LSB) +#define WLAN_LF_TIMER0_TARGET_SET(x) (((x) << WLAN_LF_TIMER0_TARGET_LSB) & WLAN_LF_TIMER0_TARGET_MASK) + +#define WLAN_LF_TIMER_COUNT0_ADDRESS 0x0000004c +#define WLAN_LF_TIMER_COUNT0_OFFSET 0x0000004c +#define WLAN_LF_TIMER_COUNT0_VALUE_MSB 31 +#define WLAN_LF_TIMER_COUNT0_VALUE_LSB 0 +#define WLAN_LF_TIMER_COUNT0_VALUE_MASK 0xffffffff +#define WLAN_LF_TIMER_COUNT0_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT0_VALUE_MASK) >> WLAN_LF_TIMER_COUNT0_VALUE_LSB) +#define WLAN_LF_TIMER_COUNT0_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT0_VALUE_LSB) & WLAN_LF_TIMER_COUNT0_VALUE_MASK) + +#define WLAN_LF_TIMER_CONTROL0_ADDRESS 0x00000050 +#define WLAN_LF_TIMER_CONTROL0_OFFSET 0x00000050 +#define WLAN_LF_TIMER_CONTROL0_ENABLE_MSB 2 +#define WLAN_LF_TIMER_CONTROL0_ENABLE_LSB 2 +#define WLAN_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 +#define WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL0_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL0_ENABLE_LSB) +#define WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL0_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL0_ENABLE_MASK) +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1 +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1 +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002 +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB) +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK) +#define WLAN_LF_TIMER_CONTROL0_RESET_MSB 0 +#define WLAN_LF_TIMER_CONTROL0_RESET_LSB 0 +#define WLAN_LF_TIMER_CONTROL0_RESET_MASK 0x00000001 +#define WLAN_LF_TIMER_CONTROL0_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL0_RESET_MASK) >> WLAN_LF_TIMER_CONTROL0_RESET_LSB) +#define WLAN_LF_TIMER_CONTROL0_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL0_RESET_LSB) & WLAN_LF_TIMER_CONTROL0_RESET_MASK) + +#define WLAN_LF_TIMER_STATUS0_ADDRESS 0x00000054 +#define WLAN_LF_TIMER_STATUS0_OFFSET 0x00000054 +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB 0 +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB 0 +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001 +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB) +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK) + +#define WLAN_LF_TIMER1_ADDRESS 0x00000058 +#define WLAN_LF_TIMER1_OFFSET 0x00000058 +#define WLAN_LF_TIMER1_TARGET_MSB 31 +#define WLAN_LF_TIMER1_TARGET_LSB 0 +#define WLAN_LF_TIMER1_TARGET_MASK 0xffffffff +#define WLAN_LF_TIMER1_TARGET_GET(x) (((x) & WLAN_LF_TIMER1_TARGET_MASK) >> WLAN_LF_TIMER1_TARGET_LSB) +#define WLAN_LF_TIMER1_TARGET_SET(x) (((x) << WLAN_LF_TIMER1_TARGET_LSB) & WLAN_LF_TIMER1_TARGET_MASK) + +#define WLAN_LF_TIMER_COUNT1_ADDRESS 0x0000005c +#define WLAN_LF_TIMER_COUNT1_OFFSET 0x0000005c +#define WLAN_LF_TIMER_COUNT1_VALUE_MSB 31 +#define WLAN_LF_TIMER_COUNT1_VALUE_LSB 0 +#define WLAN_LF_TIMER_COUNT1_VALUE_MASK 0xffffffff +#define WLAN_LF_TIMER_COUNT1_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT1_VALUE_MASK) >> WLAN_LF_TIMER_COUNT1_VALUE_LSB) +#define WLAN_LF_TIMER_COUNT1_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT1_VALUE_LSB) & WLAN_LF_TIMER_COUNT1_VALUE_MASK) + +#define WLAN_LF_TIMER_CONTROL1_ADDRESS 0x00000060 +#define WLAN_LF_TIMER_CONTROL1_OFFSET 0x00000060 +#define WLAN_LF_TIMER_CONTROL1_ENABLE_MSB 2 +#define WLAN_LF_TIMER_CONTROL1_ENABLE_LSB 2 +#define WLAN_LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004 +#define WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL1_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL1_ENABLE_LSB) +#define WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL1_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL1_ENABLE_MASK) +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1 +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1 +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002 +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB) +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK) +#define WLAN_LF_TIMER_CONTROL1_RESET_MSB 0 +#define WLAN_LF_TIMER_CONTROL1_RESET_LSB 0 +#define WLAN_LF_TIMER_CONTROL1_RESET_MASK 0x00000001 +#define WLAN_LF_TIMER_CONTROL1_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL1_RESET_MASK) >> WLAN_LF_TIMER_CONTROL1_RESET_LSB) +#define WLAN_LF_TIMER_CONTROL1_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL1_RESET_LSB) & WLAN_LF_TIMER_CONTROL1_RESET_MASK) + +#define WLAN_LF_TIMER_STATUS1_ADDRESS 0x00000064 +#define WLAN_LF_TIMER_STATUS1_OFFSET 0x00000064 +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB 0 +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB 0 +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001 +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB) +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK) + +#define WLAN_LF_TIMER2_ADDRESS 0x00000068 +#define WLAN_LF_TIMER2_OFFSET 0x00000068 +#define WLAN_LF_TIMER2_TARGET_MSB 31 +#define WLAN_LF_TIMER2_TARGET_LSB 0 +#define WLAN_LF_TIMER2_TARGET_MASK 0xffffffff +#define WLAN_LF_TIMER2_TARGET_GET(x) (((x) & WLAN_LF_TIMER2_TARGET_MASK) >> WLAN_LF_TIMER2_TARGET_LSB) +#define WLAN_LF_TIMER2_TARGET_SET(x) (((x) << WLAN_LF_TIMER2_TARGET_LSB) & WLAN_LF_TIMER2_TARGET_MASK) + +#define WLAN_LF_TIMER_COUNT2_ADDRESS 0x0000006c +#define WLAN_LF_TIMER_COUNT2_OFFSET 0x0000006c +#define WLAN_LF_TIMER_COUNT2_VALUE_MSB 31 +#define WLAN_LF_TIMER_COUNT2_VALUE_LSB 0 +#define WLAN_LF_TIMER_COUNT2_VALUE_MASK 0xffffffff +#define WLAN_LF_TIMER_COUNT2_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT2_VALUE_MASK) >> WLAN_LF_TIMER_COUNT2_VALUE_LSB) +#define WLAN_LF_TIMER_COUNT2_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT2_VALUE_LSB) & WLAN_LF_TIMER_COUNT2_VALUE_MASK) + +#define WLAN_LF_TIMER_CONTROL2_ADDRESS 0x00000070 +#define WLAN_LF_TIMER_CONTROL2_OFFSET 0x00000070 +#define WLAN_LF_TIMER_CONTROL2_ENABLE_MSB 2 +#define WLAN_LF_TIMER_CONTROL2_ENABLE_LSB 2 +#define WLAN_LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004 +#define WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL2_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL2_ENABLE_LSB) +#define WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL2_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL2_ENABLE_MASK) +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1 +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1 +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002 +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB) +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK) +#define WLAN_LF_TIMER_CONTROL2_RESET_MSB 0 +#define WLAN_LF_TIMER_CONTROL2_RESET_LSB 0 +#define WLAN_LF_TIMER_CONTROL2_RESET_MASK 0x00000001 +#define WLAN_LF_TIMER_CONTROL2_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL2_RESET_MASK) >> WLAN_LF_TIMER_CONTROL2_RESET_LSB) +#define WLAN_LF_TIMER_CONTROL2_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL2_RESET_LSB) & WLAN_LF_TIMER_CONTROL2_RESET_MASK) + +#define WLAN_LF_TIMER_STATUS2_ADDRESS 0x00000074 +#define WLAN_LF_TIMER_STATUS2_OFFSET 0x00000074 +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB 0 +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB 0 +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001 +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB) +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK) + +#define WLAN_LF_TIMER3_ADDRESS 0x00000078 +#define WLAN_LF_TIMER3_OFFSET 0x00000078 +#define WLAN_LF_TIMER3_TARGET_MSB 31 +#define WLAN_LF_TIMER3_TARGET_LSB 0 +#define WLAN_LF_TIMER3_TARGET_MASK 0xffffffff +#define WLAN_LF_TIMER3_TARGET_GET(x) (((x) & WLAN_LF_TIMER3_TARGET_MASK) >> WLAN_LF_TIMER3_TARGET_LSB) +#define WLAN_LF_TIMER3_TARGET_SET(x) (((x) << WLAN_LF_TIMER3_TARGET_LSB) & WLAN_LF_TIMER3_TARGET_MASK) + +#define WLAN_LF_TIMER_COUNT3_ADDRESS 0x0000007c +#define WLAN_LF_TIMER_COUNT3_OFFSET 0x0000007c +#define WLAN_LF_TIMER_COUNT3_VALUE_MSB 31 +#define WLAN_LF_TIMER_COUNT3_VALUE_LSB 0 +#define WLAN_LF_TIMER_COUNT3_VALUE_MASK 0xffffffff +#define WLAN_LF_TIMER_COUNT3_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT3_VALUE_MASK) >> WLAN_LF_TIMER_COUNT3_VALUE_LSB) +#define WLAN_LF_TIMER_COUNT3_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT3_VALUE_LSB) & WLAN_LF_TIMER_COUNT3_VALUE_MASK) + +#define WLAN_LF_TIMER_CONTROL3_ADDRESS 0x00000080 +#define WLAN_LF_TIMER_CONTROL3_OFFSET 0x00000080 +#define WLAN_LF_TIMER_CONTROL3_ENABLE_MSB 2 +#define WLAN_LF_TIMER_CONTROL3_ENABLE_LSB 2 +#define WLAN_LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004 +#define WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL3_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL3_ENABLE_LSB) +#define WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL3_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL3_ENABLE_MASK) +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1 +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1 +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002 +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB) +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK) +#define WLAN_LF_TIMER_CONTROL3_RESET_MSB 0 +#define WLAN_LF_TIMER_CONTROL3_RESET_LSB 0 +#define WLAN_LF_TIMER_CONTROL3_RESET_MASK 0x00000001 +#define WLAN_LF_TIMER_CONTROL3_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL3_RESET_MASK) >> WLAN_LF_TIMER_CONTROL3_RESET_LSB) +#define WLAN_LF_TIMER_CONTROL3_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL3_RESET_LSB) & WLAN_LF_TIMER_CONTROL3_RESET_MASK) + +#define WLAN_LF_TIMER_STATUS3_ADDRESS 0x00000084 +#define WLAN_LF_TIMER_STATUS3_OFFSET 0x00000084 +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB 0 +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB 0 +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001 +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB) +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK) + +#define WLAN_HF_TIMER_ADDRESS 0x00000088 +#define WLAN_HF_TIMER_OFFSET 0x00000088 +#define WLAN_HF_TIMER_TARGET_MSB 31 +#define WLAN_HF_TIMER_TARGET_LSB 12 +#define WLAN_HF_TIMER_TARGET_MASK 0xfffff000 +#define WLAN_HF_TIMER_TARGET_GET(x) (((x) & WLAN_HF_TIMER_TARGET_MASK) >> WLAN_HF_TIMER_TARGET_LSB) +#define WLAN_HF_TIMER_TARGET_SET(x) (((x) << WLAN_HF_TIMER_TARGET_LSB) & WLAN_HF_TIMER_TARGET_MASK) + +#define WLAN_HF_TIMER_COUNT_ADDRESS 0x0000008c +#define WLAN_HF_TIMER_COUNT_OFFSET 0x0000008c +#define WLAN_HF_TIMER_COUNT_VALUE_MSB 31 +#define WLAN_HF_TIMER_COUNT_VALUE_LSB 12 +#define WLAN_HF_TIMER_COUNT_VALUE_MASK 0xfffff000 +#define WLAN_HF_TIMER_COUNT_VALUE_GET(x) (((x) & WLAN_HF_TIMER_COUNT_VALUE_MASK) >> WLAN_HF_TIMER_COUNT_VALUE_LSB) +#define WLAN_HF_TIMER_COUNT_VALUE_SET(x) (((x) << WLAN_HF_TIMER_COUNT_VALUE_LSB) & WLAN_HF_TIMER_COUNT_VALUE_MASK) + +#define WLAN_HF_LF_COUNT_ADDRESS 0x00000090 +#define WLAN_HF_LF_COUNT_OFFSET 0x00000090 +#define WLAN_HF_LF_COUNT_VALUE_MSB 31 +#define WLAN_HF_LF_COUNT_VALUE_LSB 0 +#define WLAN_HF_LF_COUNT_VALUE_MASK 0xffffffff +#define WLAN_HF_LF_COUNT_VALUE_GET(x) (((x) & WLAN_HF_LF_COUNT_VALUE_MASK) >> WLAN_HF_LF_COUNT_VALUE_LSB) +#define WLAN_HF_LF_COUNT_VALUE_SET(x) (((x) << WLAN_HF_LF_COUNT_VALUE_LSB) & WLAN_HF_LF_COUNT_VALUE_MASK) + +#define WLAN_HF_TIMER_CONTROL_ADDRESS 0x00000094 +#define WLAN_HF_TIMER_CONTROL_OFFSET 0x00000094 +#define WLAN_HF_TIMER_CONTROL_ENABLE_MSB 3 +#define WLAN_HF_TIMER_CONTROL_ENABLE_LSB 3 +#define WLAN_HF_TIMER_CONTROL_ENABLE_MASK 0x00000008 +#define WLAN_HF_TIMER_CONTROL_ENABLE_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_ENABLE_MASK) >> WLAN_HF_TIMER_CONTROL_ENABLE_LSB) +#define WLAN_HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_ENABLE_LSB) & WLAN_HF_TIMER_CONTROL_ENABLE_MASK) +#define WLAN_HF_TIMER_CONTROL_ON_MSB 2 +#define WLAN_HF_TIMER_CONTROL_ON_LSB 2 +#define WLAN_HF_TIMER_CONTROL_ON_MASK 0x00000004 +#define WLAN_HF_TIMER_CONTROL_ON_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_ON_MASK) >> WLAN_HF_TIMER_CONTROL_ON_LSB) +#define WLAN_HF_TIMER_CONTROL_ON_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_ON_LSB) & WLAN_HF_TIMER_CONTROL_ON_MASK) +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB 1 +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB 1 +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002 +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB) +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB) & WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK) +#define WLAN_HF_TIMER_CONTROL_RESET_MSB 0 +#define WLAN_HF_TIMER_CONTROL_RESET_LSB 0 +#define WLAN_HF_TIMER_CONTROL_RESET_MASK 0x00000001 +#define WLAN_HF_TIMER_CONTROL_RESET_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_RESET_MASK) >> WLAN_HF_TIMER_CONTROL_RESET_LSB) +#define WLAN_HF_TIMER_CONTROL_RESET_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_RESET_LSB) & WLAN_HF_TIMER_CONTROL_RESET_MASK) + +#define WLAN_HF_TIMER_STATUS_ADDRESS 0x00000098 +#define WLAN_HF_TIMER_STATUS_OFFSET 0x00000098 +#define WLAN_HF_TIMER_STATUS_INTERRUPT_MSB 0 +#define WLAN_HF_TIMER_STATUS_INTERRUPT_LSB 0 +#define WLAN_HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001 +#define WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x) (((x) & WLAN_HF_TIMER_STATUS_INTERRUPT_MASK) >> WLAN_HF_TIMER_STATUS_INTERRUPT_LSB) +#define WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << WLAN_HF_TIMER_STATUS_INTERRUPT_LSB) & WLAN_HF_TIMER_STATUS_INTERRUPT_MASK) + +#define WLAN_RTC_CONTROL_ADDRESS 0x0000009c +#define WLAN_RTC_CONTROL_OFFSET 0x0000009c +#define WLAN_RTC_CONTROL_ENABLE_MSB 2 +#define WLAN_RTC_CONTROL_ENABLE_LSB 2 +#define WLAN_RTC_CONTROL_ENABLE_MASK 0x00000004 +#define WLAN_RTC_CONTROL_ENABLE_GET(x) (((x) & WLAN_RTC_CONTROL_ENABLE_MASK) >> WLAN_RTC_CONTROL_ENABLE_LSB) +#define WLAN_RTC_CONTROL_ENABLE_SET(x) (((x) << WLAN_RTC_CONTROL_ENABLE_LSB) & WLAN_RTC_CONTROL_ENABLE_MASK) +#define WLAN_RTC_CONTROL_LOAD_RTC_MSB 1 +#define WLAN_RTC_CONTROL_LOAD_RTC_LSB 1 +#define WLAN_RTC_CONTROL_LOAD_RTC_MASK 0x00000002 +#define WLAN_RTC_CONTROL_LOAD_RTC_GET(x) (((x) & WLAN_RTC_CONTROL_LOAD_RTC_MASK) >> WLAN_RTC_CONTROL_LOAD_RTC_LSB) +#define WLAN_RTC_CONTROL_LOAD_RTC_SET(x) (((x) << WLAN_RTC_CONTROL_LOAD_RTC_LSB) & WLAN_RTC_CONTROL_LOAD_RTC_MASK) +#define WLAN_RTC_CONTROL_LOAD_ALARM_MSB 0 +#define WLAN_RTC_CONTROL_LOAD_ALARM_LSB 0 +#define WLAN_RTC_CONTROL_LOAD_ALARM_MASK 0x00000001 +#define WLAN_RTC_CONTROL_LOAD_ALARM_GET(x) (((x) & WLAN_RTC_CONTROL_LOAD_ALARM_MASK) >> WLAN_RTC_CONTROL_LOAD_ALARM_LSB) +#define WLAN_RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << WLAN_RTC_CONTROL_LOAD_ALARM_LSB) & WLAN_RTC_CONTROL_LOAD_ALARM_MASK) + +#define WLAN_RTC_TIME_ADDRESS 0x000000a0 +#define WLAN_RTC_TIME_OFFSET 0x000000a0 +#define WLAN_RTC_TIME_WEEK_DAY_MSB 26 +#define WLAN_RTC_TIME_WEEK_DAY_LSB 24 +#define WLAN_RTC_TIME_WEEK_DAY_MASK 0x07000000 +#define WLAN_RTC_TIME_WEEK_DAY_GET(x) (((x) & WLAN_RTC_TIME_WEEK_DAY_MASK) >> WLAN_RTC_TIME_WEEK_DAY_LSB) +#define WLAN_RTC_TIME_WEEK_DAY_SET(x) (((x) << WLAN_RTC_TIME_WEEK_DAY_LSB) & WLAN_RTC_TIME_WEEK_DAY_MASK) +#define WLAN_RTC_TIME_HOUR_MSB 21 +#define WLAN_RTC_TIME_HOUR_LSB 16 +#define WLAN_RTC_TIME_HOUR_MASK 0x003f0000 +#define WLAN_RTC_TIME_HOUR_GET(x) (((x) & WLAN_RTC_TIME_HOUR_MASK) >> WLAN_RTC_TIME_HOUR_LSB) +#define WLAN_RTC_TIME_HOUR_SET(x) (((x) << WLAN_RTC_TIME_HOUR_LSB) & WLAN_RTC_TIME_HOUR_MASK) +#define WLAN_RTC_TIME_MINUTE_MSB 14 +#define WLAN_RTC_TIME_MINUTE_LSB 8 +#define WLAN_RTC_TIME_MINUTE_MASK 0x00007f00 +#define WLAN_RTC_TIME_MINUTE_GET(x) (((x) & WLAN_RTC_TIME_MINUTE_MASK) >> WLAN_RTC_TIME_MINUTE_LSB) +#define WLAN_RTC_TIME_MINUTE_SET(x) (((x) << WLAN_RTC_TIME_MINUTE_LSB) & WLAN_RTC_TIME_MINUTE_MASK) +#define WLAN_RTC_TIME_SECOND_MSB 6 +#define WLAN_RTC_TIME_SECOND_LSB 0 +#define WLAN_RTC_TIME_SECOND_MASK 0x0000007f +#define WLAN_RTC_TIME_SECOND_GET(x) (((x) & WLAN_RTC_TIME_SECOND_MASK) >> WLAN_RTC_TIME_SECOND_LSB) +#define WLAN_RTC_TIME_SECOND_SET(x) (((x) << WLAN_RTC_TIME_SECOND_LSB) & WLAN_RTC_TIME_SECOND_MASK) + +#define WLAN_RTC_DATE_ADDRESS 0x000000a4 +#define WLAN_RTC_DATE_OFFSET 0x000000a4 +#define WLAN_RTC_DATE_YEAR_MSB 23 +#define WLAN_RTC_DATE_YEAR_LSB 16 +#define WLAN_RTC_DATE_YEAR_MASK 0x00ff0000 +#define WLAN_RTC_DATE_YEAR_GET(x) (((x) & WLAN_RTC_DATE_YEAR_MASK) >> WLAN_RTC_DATE_YEAR_LSB) +#define WLAN_RTC_DATE_YEAR_SET(x) (((x) << WLAN_RTC_DATE_YEAR_LSB) & WLAN_RTC_DATE_YEAR_MASK) +#define WLAN_RTC_DATE_MONTH_MSB 12 +#define WLAN_RTC_DATE_MONTH_LSB 8 +#define WLAN_RTC_DATE_MONTH_MASK 0x00001f00 +#define WLAN_RTC_DATE_MONTH_GET(x) (((x) & WLAN_RTC_DATE_MONTH_MASK) >> WLAN_RTC_DATE_MONTH_LSB) +#define WLAN_RTC_DATE_MONTH_SET(x) (((x) << WLAN_RTC_DATE_MONTH_LSB) & WLAN_RTC_DATE_MONTH_MASK) +#define WLAN_RTC_DATE_MONTH_DAY_MSB 5 +#define WLAN_RTC_DATE_MONTH_DAY_LSB 0 +#define WLAN_RTC_DATE_MONTH_DAY_MASK 0x0000003f +#define WLAN_RTC_DATE_MONTH_DAY_GET(x) (((x) & WLAN_RTC_DATE_MONTH_DAY_MASK) >> WLAN_RTC_DATE_MONTH_DAY_LSB) +#define WLAN_RTC_DATE_MONTH_DAY_SET(x) (((x) << WLAN_RTC_DATE_MONTH_DAY_LSB) & WLAN_RTC_DATE_MONTH_DAY_MASK) + +#define WLAN_RTC_SET_TIME_ADDRESS 0x000000a8 +#define WLAN_RTC_SET_TIME_OFFSET 0x000000a8 +#define WLAN_RTC_SET_TIME_WEEK_DAY_MSB 26 +#define WLAN_RTC_SET_TIME_WEEK_DAY_LSB 24 +#define WLAN_RTC_SET_TIME_WEEK_DAY_MASK 0x07000000 +#define WLAN_RTC_SET_TIME_WEEK_DAY_GET(x) (((x) & WLAN_RTC_SET_TIME_WEEK_DAY_MASK) >> WLAN_RTC_SET_TIME_WEEK_DAY_LSB) +#define WLAN_RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << WLAN_RTC_SET_TIME_WEEK_DAY_LSB) & WLAN_RTC_SET_TIME_WEEK_DAY_MASK) +#define WLAN_RTC_SET_TIME_HOUR_MSB 21 +#define WLAN_RTC_SET_TIME_HOUR_LSB 16 +#define WLAN_RTC_SET_TIME_HOUR_MASK 0x003f0000 +#define WLAN_RTC_SET_TIME_HOUR_GET(x) (((x) & WLAN_RTC_SET_TIME_HOUR_MASK) >> WLAN_RTC_SET_TIME_HOUR_LSB) +#define WLAN_RTC_SET_TIME_HOUR_SET(x) (((x) << WLAN_RTC_SET_TIME_HOUR_LSB) & WLAN_RTC_SET_TIME_HOUR_MASK) +#define WLAN_RTC_SET_TIME_MINUTE_MSB 14 +#define WLAN_RTC_SET_TIME_MINUTE_LSB 8 +#define WLAN_RTC_SET_TIME_MINUTE_MASK 0x00007f00 +#define WLAN_RTC_SET_TIME_MINUTE_GET(x) (((x) & WLAN_RTC_SET_TIME_MINUTE_MASK) >> WLAN_RTC_SET_TIME_MINUTE_LSB) +#define WLAN_RTC_SET_TIME_MINUTE_SET(x) (((x) << WLAN_RTC_SET_TIME_MINUTE_LSB) & WLAN_RTC_SET_TIME_MINUTE_MASK) +#define WLAN_RTC_SET_TIME_SECOND_MSB 6 +#define WLAN_RTC_SET_TIME_SECOND_LSB 0 +#define WLAN_RTC_SET_TIME_SECOND_MASK 0x0000007f +#define WLAN_RTC_SET_TIME_SECOND_GET(x) (((x) & WLAN_RTC_SET_TIME_SECOND_MASK) >> WLAN_RTC_SET_TIME_SECOND_LSB) +#define WLAN_RTC_SET_TIME_SECOND_SET(x) (((x) << WLAN_RTC_SET_TIME_SECOND_LSB) & WLAN_RTC_SET_TIME_SECOND_MASK) + +#define WLAN_RTC_SET_DATE_ADDRESS 0x000000ac +#define WLAN_RTC_SET_DATE_OFFSET 0x000000ac +#define WLAN_RTC_SET_DATE_YEAR_MSB 23 +#define WLAN_RTC_SET_DATE_YEAR_LSB 16 +#define WLAN_RTC_SET_DATE_YEAR_MASK 0x00ff0000 +#define WLAN_RTC_SET_DATE_YEAR_GET(x) (((x) & WLAN_RTC_SET_DATE_YEAR_MASK) >> WLAN_RTC_SET_DATE_YEAR_LSB) +#define WLAN_RTC_SET_DATE_YEAR_SET(x) (((x) << WLAN_RTC_SET_DATE_YEAR_LSB) & WLAN_RTC_SET_DATE_YEAR_MASK) +#define WLAN_RTC_SET_DATE_MONTH_MSB 12 +#define WLAN_RTC_SET_DATE_MONTH_LSB 8 +#define WLAN_RTC_SET_DATE_MONTH_MASK 0x00001f00 +#define WLAN_RTC_SET_DATE_MONTH_GET(x) (((x) & WLAN_RTC_SET_DATE_MONTH_MASK) >> WLAN_RTC_SET_DATE_MONTH_LSB) +#define WLAN_RTC_SET_DATE_MONTH_SET(x) (((x) << WLAN_RTC_SET_DATE_MONTH_LSB) & WLAN_RTC_SET_DATE_MONTH_MASK) +#define WLAN_RTC_SET_DATE_MONTH_DAY_MSB 5 +#define WLAN_RTC_SET_DATE_MONTH_DAY_LSB 0 +#define WLAN_RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f +#define WLAN_RTC_SET_DATE_MONTH_DAY_GET(x) (((x) & WLAN_RTC_SET_DATE_MONTH_DAY_MASK) >> WLAN_RTC_SET_DATE_MONTH_DAY_LSB) +#define WLAN_RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << WLAN_RTC_SET_DATE_MONTH_DAY_LSB) & WLAN_RTC_SET_DATE_MONTH_DAY_MASK) + +#define WLAN_RTC_SET_ALARM_ADDRESS 0x000000b0 +#define WLAN_RTC_SET_ALARM_OFFSET 0x000000b0 +#define WLAN_RTC_SET_ALARM_HOUR_MSB 21 +#define WLAN_RTC_SET_ALARM_HOUR_LSB 16 +#define WLAN_RTC_SET_ALARM_HOUR_MASK 0x003f0000 +#define WLAN_RTC_SET_ALARM_HOUR_GET(x) (((x) & WLAN_RTC_SET_ALARM_HOUR_MASK) >> WLAN_RTC_SET_ALARM_HOUR_LSB) +#define WLAN_RTC_SET_ALARM_HOUR_SET(x) (((x) << WLAN_RTC_SET_ALARM_HOUR_LSB) & WLAN_RTC_SET_ALARM_HOUR_MASK) +#define WLAN_RTC_SET_ALARM_MINUTE_MSB 14 +#define WLAN_RTC_SET_ALARM_MINUTE_LSB 8 +#define WLAN_RTC_SET_ALARM_MINUTE_MASK 0x00007f00 +#define WLAN_RTC_SET_ALARM_MINUTE_GET(x) (((x) & WLAN_RTC_SET_ALARM_MINUTE_MASK) >> WLAN_RTC_SET_ALARM_MINUTE_LSB) +#define WLAN_RTC_SET_ALARM_MINUTE_SET(x) (((x) << WLAN_RTC_SET_ALARM_MINUTE_LSB) & WLAN_RTC_SET_ALARM_MINUTE_MASK) +#define WLAN_RTC_SET_ALARM_SECOND_MSB 6 +#define WLAN_RTC_SET_ALARM_SECOND_LSB 0 +#define WLAN_RTC_SET_ALARM_SECOND_MASK 0x0000007f +#define WLAN_RTC_SET_ALARM_SECOND_GET(x) (((x) & WLAN_RTC_SET_ALARM_SECOND_MASK) >> WLAN_RTC_SET_ALARM_SECOND_LSB) +#define WLAN_RTC_SET_ALARM_SECOND_SET(x) (((x) << WLAN_RTC_SET_ALARM_SECOND_LSB) & WLAN_RTC_SET_ALARM_SECOND_MASK) + +#define WLAN_RTC_CONFIG_ADDRESS 0x000000b4 +#define WLAN_RTC_CONFIG_OFFSET 0x000000b4 +#define WLAN_RTC_CONFIG_BCD_MSB 2 +#define WLAN_RTC_CONFIG_BCD_LSB 2 +#define WLAN_RTC_CONFIG_BCD_MASK 0x00000004 +#define WLAN_RTC_CONFIG_BCD_GET(x) (((x) & WLAN_RTC_CONFIG_BCD_MASK) >> WLAN_RTC_CONFIG_BCD_LSB) +#define WLAN_RTC_CONFIG_BCD_SET(x) (((x) << WLAN_RTC_CONFIG_BCD_LSB) & WLAN_RTC_CONFIG_BCD_MASK) +#define WLAN_RTC_CONFIG_TWELVE_HOUR_MSB 1 +#define WLAN_RTC_CONFIG_TWELVE_HOUR_LSB 1 +#define WLAN_RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002 +#define WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x) (((x) & WLAN_RTC_CONFIG_TWELVE_HOUR_MASK) >> WLAN_RTC_CONFIG_TWELVE_HOUR_LSB) +#define WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << WLAN_RTC_CONFIG_TWELVE_HOUR_LSB) & WLAN_RTC_CONFIG_TWELVE_HOUR_MASK) +#define WLAN_RTC_CONFIG_DSE_MSB 0 +#define WLAN_RTC_CONFIG_DSE_LSB 0 +#define WLAN_RTC_CONFIG_DSE_MASK 0x00000001 +#define WLAN_RTC_CONFIG_DSE_GET(x) (((x) & WLAN_RTC_CONFIG_DSE_MASK) >> WLAN_RTC_CONFIG_DSE_LSB) +#define WLAN_RTC_CONFIG_DSE_SET(x) (((x) << WLAN_RTC_CONFIG_DSE_LSB) & WLAN_RTC_CONFIG_DSE_MASK) + +#define WLAN_RTC_ALARM_STATUS_ADDRESS 0x000000b8 +#define WLAN_RTC_ALARM_STATUS_OFFSET 0x000000b8 +#define WLAN_RTC_ALARM_STATUS_ENABLE_MSB 1 +#define WLAN_RTC_ALARM_STATUS_ENABLE_LSB 1 +#define WLAN_RTC_ALARM_STATUS_ENABLE_MASK 0x00000002 +#define WLAN_RTC_ALARM_STATUS_ENABLE_GET(x) (((x) & WLAN_RTC_ALARM_STATUS_ENABLE_MASK) >> WLAN_RTC_ALARM_STATUS_ENABLE_LSB) +#define WLAN_RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << WLAN_RTC_ALARM_STATUS_ENABLE_LSB) & WLAN_RTC_ALARM_STATUS_ENABLE_MASK) +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB 0 +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB 0 +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001 +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x) & WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK) >> WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB) +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB) & WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK) + +#define WLAN_UART_WAKEUP_ADDRESS 0x000000bc +#define WLAN_UART_WAKEUP_OFFSET 0x000000bc +#define WLAN_UART_WAKEUP_ENABLE_MSB 0 +#define WLAN_UART_WAKEUP_ENABLE_LSB 0 +#define WLAN_UART_WAKEUP_ENABLE_MASK 0x00000001 +#define WLAN_UART_WAKEUP_ENABLE_GET(x) (((x) & WLAN_UART_WAKEUP_ENABLE_MASK) >> WLAN_UART_WAKEUP_ENABLE_LSB) +#define WLAN_UART_WAKEUP_ENABLE_SET(x) (((x) << WLAN_UART_WAKEUP_ENABLE_LSB) & WLAN_UART_WAKEUP_ENABLE_MASK) + +#define WLAN_RESET_CAUSE_ADDRESS 0x000000c0 +#define WLAN_RESET_CAUSE_OFFSET 0x000000c0 +#define WLAN_RESET_CAUSE_LAST_MSB 2 +#define WLAN_RESET_CAUSE_LAST_LSB 0 +#define WLAN_RESET_CAUSE_LAST_MASK 0x00000007 +#define WLAN_RESET_CAUSE_LAST_GET(x) (((x) & WLAN_RESET_CAUSE_LAST_MASK) >> WLAN_RESET_CAUSE_LAST_LSB) +#define WLAN_RESET_CAUSE_LAST_SET(x) (((x) << WLAN_RESET_CAUSE_LAST_LSB) & WLAN_RESET_CAUSE_LAST_MASK) + +#define WLAN_SYSTEM_SLEEP_ADDRESS 0x000000c4 +#define WLAN_SYSTEM_SLEEP_OFFSET 0x000000c4 +#define WLAN_SYSTEM_SLEEP_HOST_IF_MSB 4 +#define WLAN_SYSTEM_SLEEP_HOST_IF_LSB 4 +#define WLAN_SYSTEM_SLEEP_HOST_IF_MASK 0x00000010 +#define WLAN_SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & WLAN_SYSTEM_SLEEP_HOST_IF_MASK) >> WLAN_SYSTEM_SLEEP_HOST_IF_LSB) +#define WLAN_SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << WLAN_SYSTEM_SLEEP_HOST_IF_LSB) & WLAN_SYSTEM_SLEEP_HOST_IF_MASK) +#define WLAN_SYSTEM_SLEEP_MBOX_MSB 3 +#define WLAN_SYSTEM_SLEEP_MBOX_LSB 3 +#define WLAN_SYSTEM_SLEEP_MBOX_MASK 0x00000008 +#define WLAN_SYSTEM_SLEEP_MBOX_GET(x) (((x) & WLAN_SYSTEM_SLEEP_MBOX_MASK) >> WLAN_SYSTEM_SLEEP_MBOX_LSB) +#define WLAN_SYSTEM_SLEEP_MBOX_SET(x) (((x) << WLAN_SYSTEM_SLEEP_MBOX_LSB) & WLAN_SYSTEM_SLEEP_MBOX_MASK) +#define WLAN_SYSTEM_SLEEP_MAC_IF_MSB 2 +#define WLAN_SYSTEM_SLEEP_MAC_IF_LSB 2 +#define WLAN_SYSTEM_SLEEP_MAC_IF_MASK 0x00000004 +#define WLAN_SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & WLAN_SYSTEM_SLEEP_MAC_IF_MASK) >> WLAN_SYSTEM_SLEEP_MAC_IF_LSB) +#define WLAN_SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << WLAN_SYSTEM_SLEEP_MAC_IF_LSB) & WLAN_SYSTEM_SLEEP_MAC_IF_MASK) +#define WLAN_SYSTEM_SLEEP_LIGHT_MSB 1 +#define WLAN_SYSTEM_SLEEP_LIGHT_LSB 1 +#define WLAN_SYSTEM_SLEEP_LIGHT_MASK 0x00000002 +#define WLAN_SYSTEM_SLEEP_LIGHT_GET(x) (((x) & WLAN_SYSTEM_SLEEP_LIGHT_MASK) >> WLAN_SYSTEM_SLEEP_LIGHT_LSB) +#define WLAN_SYSTEM_SLEEP_LIGHT_SET(x) (((x) << WLAN_SYSTEM_SLEEP_LIGHT_LSB) & WLAN_SYSTEM_SLEEP_LIGHT_MASK) +#define WLAN_SYSTEM_SLEEP_DISABLE_MSB 0 +#define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 +#define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 +#define WLAN_SYSTEM_SLEEP_DISABLE_GET(x) (((x) & WLAN_SYSTEM_SLEEP_DISABLE_MASK) >> WLAN_SYSTEM_SLEEP_DISABLE_LSB) +#define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & WLAN_SYSTEM_SLEEP_DISABLE_MASK) + +#define WLAN_SDIO_WRAPPER_ADDRESS 0x000000c8 +#define WLAN_SDIO_WRAPPER_OFFSET 0x000000c8 +#define WLAN_SDIO_WRAPPER_SLEEP_MSB 3 +#define WLAN_SDIO_WRAPPER_SLEEP_LSB 3 +#define WLAN_SDIO_WRAPPER_SLEEP_MASK 0x00000008 +#define WLAN_SDIO_WRAPPER_SLEEP_GET(x) (((x) & WLAN_SDIO_WRAPPER_SLEEP_MASK) >> WLAN_SDIO_WRAPPER_SLEEP_LSB) +#define WLAN_SDIO_WRAPPER_SLEEP_SET(x) (((x) << WLAN_SDIO_WRAPPER_SLEEP_LSB) & WLAN_SDIO_WRAPPER_SLEEP_MASK) +#define WLAN_SDIO_WRAPPER_WAKEUP_MSB 2 +#define WLAN_SDIO_WRAPPER_WAKEUP_LSB 2 +#define WLAN_SDIO_WRAPPER_WAKEUP_MASK 0x00000004 +#define WLAN_SDIO_WRAPPER_WAKEUP_GET(x) (((x) & WLAN_SDIO_WRAPPER_WAKEUP_MASK) >> WLAN_SDIO_WRAPPER_WAKEUP_LSB) +#define WLAN_SDIO_WRAPPER_WAKEUP_SET(x) (((x) << WLAN_SDIO_WRAPPER_WAKEUP_LSB) & WLAN_SDIO_WRAPPER_WAKEUP_MASK) +#define WLAN_SDIO_WRAPPER_SOC_ON_MSB 1 +#define WLAN_SDIO_WRAPPER_SOC_ON_LSB 1 +#define WLAN_SDIO_WRAPPER_SOC_ON_MASK 0x00000002 +#define WLAN_SDIO_WRAPPER_SOC_ON_GET(x) (((x) & WLAN_SDIO_WRAPPER_SOC_ON_MASK) >> WLAN_SDIO_WRAPPER_SOC_ON_LSB) +#define WLAN_SDIO_WRAPPER_SOC_ON_SET(x) (((x) << WLAN_SDIO_WRAPPER_SOC_ON_LSB) & WLAN_SDIO_WRAPPER_SOC_ON_MASK) +#define WLAN_SDIO_WRAPPER_ON_MSB 0 +#define WLAN_SDIO_WRAPPER_ON_LSB 0 +#define WLAN_SDIO_WRAPPER_ON_MASK 0x00000001 +#define WLAN_SDIO_WRAPPER_ON_GET(x) (((x) & WLAN_SDIO_WRAPPER_ON_MASK) >> WLAN_SDIO_WRAPPER_ON_LSB) +#define WLAN_SDIO_WRAPPER_ON_SET(x) (((x) << WLAN_SDIO_WRAPPER_ON_LSB) & WLAN_SDIO_WRAPPER_ON_MASK) + +#define WLAN_MAC_SLEEP_CONTROL_ADDRESS 0x000000cc +#define WLAN_MAC_SLEEP_CONTROL_OFFSET 0x000000cc +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB 1 +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB 0 +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003 +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x) (((x) & WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK) >> WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB) +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x) (((x) << WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB) & WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK) + +#define WLAN_KEEP_AWAKE_ADDRESS 0x000000d0 +#define WLAN_KEEP_AWAKE_OFFSET 0x000000d0 +#define WLAN_KEEP_AWAKE_COUNT_MSB 7 +#define WLAN_KEEP_AWAKE_COUNT_LSB 0 +#define WLAN_KEEP_AWAKE_COUNT_MASK 0x000000ff +#define WLAN_KEEP_AWAKE_COUNT_GET(x) (((x) & WLAN_KEEP_AWAKE_COUNT_MASK) >> WLAN_KEEP_AWAKE_COUNT_LSB) +#define WLAN_KEEP_AWAKE_COUNT_SET(x) (((x) << WLAN_KEEP_AWAKE_COUNT_LSB) & WLAN_KEEP_AWAKE_COUNT_MASK) + +#define WLAN_LPO_CAL_TIME_ADDRESS 0x000000d4 +#define WLAN_LPO_CAL_TIME_OFFSET 0x000000d4 +#define WLAN_LPO_CAL_TIME_LENGTH_MSB 13 +#define WLAN_LPO_CAL_TIME_LENGTH_LSB 0 +#define WLAN_LPO_CAL_TIME_LENGTH_MASK 0x00003fff +#define WLAN_LPO_CAL_TIME_LENGTH_GET(x) (((x) & WLAN_LPO_CAL_TIME_LENGTH_MASK) >> WLAN_LPO_CAL_TIME_LENGTH_LSB) +#define WLAN_LPO_CAL_TIME_LENGTH_SET(x) (((x) << WLAN_LPO_CAL_TIME_LENGTH_LSB) & WLAN_LPO_CAL_TIME_LENGTH_MASK) + +#define WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8 +#define WLAN_LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8 +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB 23 +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB 0 +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x) (((x) & WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB) +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x) (((x) << WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB) & WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK) + +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10 +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0 +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) + +#define WLAN_LPO_CAL_ADDRESS 0x000000e0 +#define WLAN_LPO_CAL_OFFSET 0x000000e0 +#define WLAN_LPO_CAL_ENABLE_MSB 20 +#define WLAN_LPO_CAL_ENABLE_LSB 20 +#define WLAN_LPO_CAL_ENABLE_MASK 0x00100000 +#define WLAN_LPO_CAL_ENABLE_GET(x) (((x) & WLAN_LPO_CAL_ENABLE_MASK) >> WLAN_LPO_CAL_ENABLE_LSB) +#define WLAN_LPO_CAL_ENABLE_SET(x) (((x) << WLAN_LPO_CAL_ENABLE_LSB) & WLAN_LPO_CAL_ENABLE_MASK) +#define WLAN_LPO_CAL_COUNT_MSB 19 +#define WLAN_LPO_CAL_COUNT_LSB 0 +#define WLAN_LPO_CAL_COUNT_MASK 0x000fffff +#define WLAN_LPO_CAL_COUNT_GET(x) (((x) & WLAN_LPO_CAL_COUNT_MASK) >> WLAN_LPO_CAL_COUNT_LSB) +#define WLAN_LPO_CAL_COUNT_SET(x) (((x) << WLAN_LPO_CAL_COUNT_LSB) & WLAN_LPO_CAL_COUNT_MASK) + +#define WLAN_LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4 +#define WLAN_LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4 +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB 5 +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB 5 +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00000020 +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x) (((x) & WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB) +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x) (((x) << WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB) & WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK) +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4 +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0 +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) + +#define WLAN_LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8 +#define WLAN_LPO_CAL_TEST_STATUS_OFFSET 0x000000e8 +#define WLAN_LPO_CAL_TEST_STATUS_READY_MSB 16 +#define WLAN_LPO_CAL_TEST_STATUS_READY_LSB 16 +#define WLAN_LPO_CAL_TEST_STATUS_READY_MASK 0x00010000 +#define WLAN_LPO_CAL_TEST_STATUS_READY_GET(x) (((x) & WLAN_LPO_CAL_TEST_STATUS_READY_MASK) >> WLAN_LPO_CAL_TEST_STATUS_READY_LSB) +#define WLAN_LPO_CAL_TEST_STATUS_READY_SET(x) (((x) << WLAN_LPO_CAL_TEST_STATUS_READY_LSB) & WLAN_LPO_CAL_TEST_STATUS_READY_MASK) +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB 15 +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB 0 +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x) (((x) & WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK) >> WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB) +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x) (((x) << WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB) & WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK) + +#define WLAN_CHIP_ID_ADDRESS 0x000000ec +#define WLAN_CHIP_ID_OFFSET 0x000000ec +#define WLAN_CHIP_ID_DEVICE_ID_MSB 31 +#define WLAN_CHIP_ID_DEVICE_ID_LSB 16 +#define WLAN_CHIP_ID_DEVICE_ID_MASK 0xffff0000 +#define WLAN_CHIP_ID_DEVICE_ID_GET(x) (((x) & WLAN_CHIP_ID_DEVICE_ID_MASK) >> WLAN_CHIP_ID_DEVICE_ID_LSB) +#define WLAN_CHIP_ID_DEVICE_ID_SET(x) (((x) << WLAN_CHIP_ID_DEVICE_ID_LSB) & WLAN_CHIP_ID_DEVICE_ID_MASK) +#define WLAN_CHIP_ID_CONFIG_ID_MSB 15 +#define WLAN_CHIP_ID_CONFIG_ID_LSB 4 +#define WLAN_CHIP_ID_CONFIG_ID_MASK 0x0000fff0 +#define WLAN_CHIP_ID_CONFIG_ID_GET(x) (((x) & WLAN_CHIP_ID_CONFIG_ID_MASK) >> WLAN_CHIP_ID_CONFIG_ID_LSB) +#define WLAN_CHIP_ID_CONFIG_ID_SET(x) (((x) << WLAN_CHIP_ID_CONFIG_ID_LSB) & WLAN_CHIP_ID_CONFIG_ID_MASK) +#define WLAN_CHIP_ID_VERSION_ID_MSB 3 +#define WLAN_CHIP_ID_VERSION_ID_LSB 0 +#define WLAN_CHIP_ID_VERSION_ID_MASK 0x0000000f +#define WLAN_CHIP_ID_VERSION_ID_GET(x) (((x) & WLAN_CHIP_ID_VERSION_ID_MASK) >> WLAN_CHIP_ID_VERSION_ID_LSB) +#define WLAN_CHIP_ID_VERSION_ID_SET(x) (((x) << WLAN_CHIP_ID_VERSION_ID_LSB) & WLAN_CHIP_ID_VERSION_ID_MASK) + +#define WLAN_DERIVED_RTC_CLK_ADDRESS 0x000000f0 +#define WLAN_DERIVED_RTC_CLK_OFFSET 0x000000f0 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) +#define WLAN_DERIVED_RTC_CLK_FORCE_MSB 17 +#define WLAN_DERIVED_RTC_CLK_FORCE_LSB 16 +#define WLAN_DERIVED_RTC_CLK_FORCE_MASK 0x00030000 +#define WLAN_DERIVED_RTC_CLK_FORCE_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_FORCE_MASK) >> WLAN_DERIVED_RTC_CLK_FORCE_LSB) +#define WLAN_DERIVED_RTC_CLK_FORCE_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_FORCE_LSB) & WLAN_DERIVED_RTC_CLK_FORCE_MASK) +#define WLAN_DERIVED_RTC_CLK_PERIOD_MSB 15 +#define WLAN_DERIVED_RTC_CLK_PERIOD_LSB 1 +#define WLAN_DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe +#define WLAN_DERIVED_RTC_CLK_PERIOD_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_PERIOD_MASK) >> WLAN_DERIVED_RTC_CLK_PERIOD_LSB) +#define WLAN_DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_PERIOD_LSB) & WLAN_DERIVED_RTC_CLK_PERIOD_MASK) + +#define MAC_PCU_SLP32_MODE_ADDRESS 0x000000f4 +#define MAC_PCU_SLP32_MODE_OFFSET 0x000000f4 +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MSB 24 +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB 24 +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK 0x01000000 +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK) >> MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB) +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB) & MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK) +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MSB 23 +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB 23 +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK 0x00800000 +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_GET(x) (((x) & MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK) >> MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB) +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_SET(x) (((x) << MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB) & MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK) +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MSB 22 +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB 22 +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK 0x00400000 +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_GET(x) (((x) & MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK) >> MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB) +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_SET(x) (((x) << MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB) & MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK) +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK 0x00200000 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB) +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK) +#define MAC_PCU_SLP32_MODE_ENABLE_MSB 20 +#define MAC_PCU_SLP32_MODE_ENABLE_LSB 20 +#define MAC_PCU_SLP32_MODE_ENABLE_MASK 0x00100000 +#define MAC_PCU_SLP32_MODE_ENABLE_GET(x) (((x) & MAC_PCU_SLP32_MODE_ENABLE_MASK) >> MAC_PCU_SLP32_MODE_ENABLE_LSB) +#define MAC_PCU_SLP32_MODE_ENABLE_SET(x) (((x) << MAC_PCU_SLP32_MODE_ENABLE_LSB) & MAC_PCU_SLP32_MODE_ENABLE_MASK) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB 19 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB 0 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) + +#define MAC_PCU_SLP32_WAKE_ADDRESS 0x000000f8 +#define MAC_PCU_SLP32_WAKE_OFFSET 0x000000f8 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB 15 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB 0 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK 0x0000ffff +#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x) (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) +#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x) (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) + +#define MAC_PCU_SLP32_INC_ADDRESS 0x000000fc +#define MAC_PCU_SLP32_INC_OFFSET 0x000000fc +#define MAC_PCU_SLP32_INC_TSF_INC_MSB 19 +#define MAC_PCU_SLP32_INC_TSF_INC_LSB 0 +#define MAC_PCU_SLP32_INC_TSF_INC_MASK 0x000fffff +#define MAC_PCU_SLP32_INC_TSF_INC_GET(x) (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB) +#define MAC_PCU_SLP32_INC_TSF_INC_SET(x) (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK) + +#define MAC_PCU_SLP_MIB1_ADDRESS 0x00000100 +#define MAC_PCU_SLP_MIB1_OFFSET 0x00000100 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB 31 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB 0 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) + +#define MAC_PCU_SLP_MIB2_ADDRESS 0x00000104 +#define MAC_PCU_SLP_MIB2_OFFSET 0x00000104 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB 31 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB 0 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) + +#define MAC_PCU_SLP_MIB3_ADDRESS 0x00000108 +#define MAC_PCU_SLP_MIB3_OFFSET 0x00000108 +#define MAC_PCU_SLP_MIB3_PENDING_MSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_LSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_MASK 0x00000002 +#define MAC_PCU_SLP_MIB3_PENDING_GET(x) (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB) +#define MAC_PCU_SLP_MIB3_PENDING_SET(x) (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK) +#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK 0x00000001 +#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB) +#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) + +#define WLAN_POWER_REG_ADDRESS 0x0000010c +#define WLAN_POWER_REG_OFFSET 0x0000010c +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB 15 +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB 15 +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK 0x00008000 +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) (((x) & WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK) >> WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB) +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) (((x) << WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB) & WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK) +#define WLAN_POWER_REG_DEBUG_EN_MSB 14 +#define WLAN_POWER_REG_DEBUG_EN_LSB 14 +#define WLAN_POWER_REG_DEBUG_EN_MASK 0x00004000 +#define WLAN_POWER_REG_DEBUG_EN_GET(x) (((x) & WLAN_POWER_REG_DEBUG_EN_MASK) >> WLAN_POWER_REG_DEBUG_EN_LSB) +#define WLAN_POWER_REG_DEBUG_EN_SET(x) (((x) << WLAN_POWER_REG_DEBUG_EN_LSB) & WLAN_POWER_REG_DEBUG_EN_MASK) +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB 13 +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB 13 +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK 0x00002000 +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB) +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK) +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB 12 +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB 12 +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK 0x00001000 +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB) +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK) +#define WLAN_POWER_REG_VLVL_MSB 11 +#define WLAN_POWER_REG_VLVL_LSB 8 +#define WLAN_POWER_REG_VLVL_MASK 0x00000f00 +#define WLAN_POWER_REG_VLVL_GET(x) (((x) & WLAN_POWER_REG_VLVL_MASK) >> WLAN_POWER_REG_VLVL_LSB) +#define WLAN_POWER_REG_VLVL_SET(x) (((x) << WLAN_POWER_REG_VLVL_LSB) & WLAN_POWER_REG_VLVL_MASK) +#define WLAN_POWER_REG_CPU_INT_ENABLE_MSB 7 +#define WLAN_POWER_REG_CPU_INT_ENABLE_LSB 7 +#define WLAN_POWER_REG_CPU_INT_ENABLE_MASK 0x00000080 +#define WLAN_POWER_REG_CPU_INT_ENABLE_GET(x) (((x) & WLAN_POWER_REG_CPU_INT_ENABLE_MASK) >> WLAN_POWER_REG_CPU_INT_ENABLE_LSB) +#define WLAN_POWER_REG_CPU_INT_ENABLE_SET(x) (((x) << WLAN_POWER_REG_CPU_INT_ENABLE_LSB) & WLAN_POWER_REG_CPU_INT_ENABLE_MASK) +#define WLAN_POWER_REG_WLAN_ISO_DIS_MSB 6 +#define WLAN_POWER_REG_WLAN_ISO_DIS_LSB 6 +#define WLAN_POWER_REG_WLAN_ISO_DIS_MASK 0x00000040 +#define WLAN_POWER_REG_WLAN_ISO_DIS_GET(x) (((x) & WLAN_POWER_REG_WLAN_ISO_DIS_MASK) >> WLAN_POWER_REG_WLAN_ISO_DIS_LSB) +#define WLAN_POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << WLAN_POWER_REG_WLAN_ISO_DIS_LSB) & WLAN_POWER_REG_WLAN_ISO_DIS_MASK) +#define WLAN_POWER_REG_WLAN_ISO_CNTL_MSB 5 +#define WLAN_POWER_REG_WLAN_ISO_CNTL_LSB 5 +#define WLAN_POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020 +#define WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x) (((x) & WLAN_POWER_REG_WLAN_ISO_CNTL_MASK) >> WLAN_POWER_REG_WLAN_ISO_CNTL_LSB) +#define WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x) (((x) << WLAN_POWER_REG_WLAN_ISO_CNTL_LSB) & WLAN_POWER_REG_WLAN_ISO_CNTL_MASK) +#define WLAN_POWER_REG_RADIO_PWD_EN_MSB 4 +#define WLAN_POWER_REG_RADIO_PWD_EN_LSB 4 +#define WLAN_POWER_REG_RADIO_PWD_EN_MASK 0x00000010 +#define WLAN_POWER_REG_RADIO_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_RADIO_PWD_EN_MASK) >> WLAN_POWER_REG_RADIO_PWD_EN_LSB) +#define WLAN_POWER_REG_RADIO_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_RADIO_PWD_EN_LSB) & WLAN_POWER_REG_RADIO_PWD_EN_MASK) +#define WLAN_POWER_REG_SOC_ISO_EN_MSB 3 +#define WLAN_POWER_REG_SOC_ISO_EN_LSB 3 +#define WLAN_POWER_REG_SOC_ISO_EN_MASK 0x00000008 +#define WLAN_POWER_REG_SOC_ISO_EN_GET(x) (((x) & WLAN_POWER_REG_SOC_ISO_EN_MASK) >> WLAN_POWER_REG_SOC_ISO_EN_LSB) +#define WLAN_POWER_REG_SOC_ISO_EN_SET(x) (((x) << WLAN_POWER_REG_SOC_ISO_EN_LSB) & WLAN_POWER_REG_SOC_ISO_EN_MASK) +#define WLAN_POWER_REG_WLAN_ISO_EN_MSB 2 +#define WLAN_POWER_REG_WLAN_ISO_EN_LSB 2 +#define WLAN_POWER_REG_WLAN_ISO_EN_MASK 0x00000004 +#define WLAN_POWER_REG_WLAN_ISO_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_ISO_EN_MASK) >> WLAN_POWER_REG_WLAN_ISO_EN_LSB) +#define WLAN_POWER_REG_WLAN_ISO_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_ISO_EN_LSB) & WLAN_POWER_REG_WLAN_ISO_EN_MASK) +#define WLAN_POWER_REG_WLAN_PWD_EN_MSB 1 +#define WLAN_POWER_REG_WLAN_PWD_EN_LSB 1 +#define WLAN_POWER_REG_WLAN_PWD_EN_MASK 0x00000002 +#define WLAN_POWER_REG_WLAN_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_PWD_EN_LSB) +#define WLAN_POWER_REG_WLAN_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_PWD_EN_MASK) +#define WLAN_POWER_REG_POWER_EN_MSB 0 +#define WLAN_POWER_REG_POWER_EN_LSB 0 +#define WLAN_POWER_REG_POWER_EN_MASK 0x00000001 +#define WLAN_POWER_REG_POWER_EN_GET(x) (((x) & WLAN_POWER_REG_POWER_EN_MASK) >> WLAN_POWER_REG_POWER_EN_LSB) +#define WLAN_POWER_REG_POWER_EN_SET(x) (((x) << WLAN_POWER_REG_POWER_EN_LSB) & WLAN_POWER_REG_POWER_EN_MASK) + +#define WLAN_CORE_CLK_CTRL_ADDRESS 0x00000110 +#define WLAN_CORE_CLK_CTRL_OFFSET 0x00000110 +#define WLAN_CORE_CLK_CTRL_DIV_MSB 2 +#define WLAN_CORE_CLK_CTRL_DIV_LSB 0 +#define WLAN_CORE_CLK_CTRL_DIV_MASK 0x00000007 +#define WLAN_CORE_CLK_CTRL_DIV_GET(x) (((x) & WLAN_CORE_CLK_CTRL_DIV_MASK) >> WLAN_CORE_CLK_CTRL_DIV_LSB) +#define WLAN_CORE_CLK_CTRL_DIV_SET(x) (((x) << WLAN_CORE_CLK_CTRL_DIV_LSB) & WLAN_CORE_CLK_CTRL_DIV_MASK) + +#define WLAN_GPIO_WAKEUP_CONTROL_ADDRESS 0x00000114 +#define WLAN_GPIO_WAKEUP_CONTROL_OFFSET 0x00000114 +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB 0 +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB 0 +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001 +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x) (((x) & WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB) +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x) (((x) << WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB) & WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK) + +#define HT_ADDRESS 0x00000118 +#define HT_OFFSET 0x00000118 +#define HT_MODE_MSB 0 +#define HT_MODE_LSB 0 +#define HT_MODE_MASK 0x00000001 +#define HT_MODE_GET(x) (((x) & HT_MODE_MASK) >> HT_MODE_LSB) +#define HT_MODE_SET(x) (((x) << HT_MODE_LSB) & HT_MODE_MASK) + +#define MAC_PCU_TSF_L32_ADDRESS 0x0000011c +#define MAC_PCU_TSF_L32_OFFSET 0x0000011c +#define MAC_PCU_TSF_L32_VALUE_MSB 31 +#define MAC_PCU_TSF_L32_VALUE_LSB 0 +#define MAC_PCU_TSF_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF_L32_VALUE_MASK) >> MAC_PCU_TSF_L32_VALUE_LSB) +#define MAC_PCU_TSF_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF_L32_VALUE_LSB) & MAC_PCU_TSF_L32_VALUE_MASK) + +#define MAC_PCU_TSF_U32_ADDRESS 0x00000120 +#define MAC_PCU_TSF_U32_OFFSET 0x00000120 +#define MAC_PCU_TSF_U32_VALUE_MSB 31 +#define MAC_PCU_TSF_U32_VALUE_LSB 0 +#define MAC_PCU_TSF_U32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF_U32_VALUE_MASK) >> MAC_PCU_TSF_U32_VALUE_LSB) +#define MAC_PCU_TSF_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF_U32_VALUE_LSB) & MAC_PCU_TSF_U32_VALUE_MASK) + +#define MAC_PCU_WBTIMER_ADDRESS 0x00000124 +#define MAC_PCU_WBTIMER_OFFSET 0x00000124 +#define MAC_PCU_WBTIMER_VALUE_MSB 31 +#define MAC_PCU_WBTIMER_VALUE_LSB 0 +#define MAC_PCU_WBTIMER_VALUE_MASK 0xffffffff +#define MAC_PCU_WBTIMER_VALUE_GET(x) (((x) & MAC_PCU_WBTIMER_VALUE_MASK) >> MAC_PCU_WBTIMER_VALUE_LSB) +#define MAC_PCU_WBTIMER_VALUE_SET(x) (((x) << MAC_PCU_WBTIMER_VALUE_LSB) & MAC_PCU_WBTIMER_VALUE_MASK) + +#define MAC_PCU_GENERIC_TIMERS_ADDRESS 0x00000140 +#define MAC_PCU_GENERIC_TIMERS_OFFSET 0x00000140 +#define MAC_PCU_GENERIC_TIMERS_DATA_MSB 31 +#define MAC_PCU_GENERIC_TIMERS_DATA_LSB 0 +#define MAC_PCU_GENERIC_TIMERS_DATA_MASK 0xffffffff +#define MAC_PCU_GENERIC_TIMERS_DATA_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_DATA_MASK) >> MAC_PCU_GENERIC_TIMERS_DATA_LSB) +#define MAC_PCU_GENERIC_TIMERS_DATA_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_DATA_LSB) & MAC_PCU_GENERIC_TIMERS_DATA_MASK) + +#define MAC_PCU_GENERIC_TIMERS_MODE_ADDRESS 0x00000180 +#define MAC_PCU_GENERIC_TIMERS_MODE_OFFSET 0x00000180 +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MSB 15 +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB 0 +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK 0x0000ffff +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB) +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB) & MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK) + +#define MAC_PCU_GENERIC_TIMERS2_ADDRESS 0x000001c0 +#define MAC_PCU_GENERIC_TIMERS2_OFFSET 0x000001c0 +#define MAC_PCU_GENERIC_TIMERS2_DATA_MSB 31 +#define MAC_PCU_GENERIC_TIMERS2_DATA_LSB 0 +#define MAC_PCU_GENERIC_TIMERS2_DATA_MASK 0xffffffff +#define MAC_PCU_GENERIC_TIMERS2_DATA_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS2_DATA_MASK) >> MAC_PCU_GENERIC_TIMERS2_DATA_LSB) +#define MAC_PCU_GENERIC_TIMERS2_DATA_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS2_DATA_LSB) & MAC_PCU_GENERIC_TIMERS2_DATA_MASK) + +#define MAC_PCU_GENERIC_TIMERS_MODE2_ADDRESS 0x00000200 +#define MAC_PCU_GENERIC_TIMERS_MODE2_OFFSET 0x00000200 +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MSB 15 +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB 0 +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK 0x0000ffff +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB) +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB) & MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK) + +#define MAC_PCU_SLP1_ADDRESS 0x00000204 +#define MAC_PCU_SLP1_OFFSET 0x00000204 +#define MAC_PCU_SLP1_ASSUME_DTIM_MSB 19 +#define MAC_PCU_SLP1_ASSUME_DTIM_LSB 19 +#define MAC_PCU_SLP1_ASSUME_DTIM_MASK 0x00080000 +#define MAC_PCU_SLP1_ASSUME_DTIM_GET(x) (((x) & MAC_PCU_SLP1_ASSUME_DTIM_MASK) >> MAC_PCU_SLP1_ASSUME_DTIM_LSB) +#define MAC_PCU_SLP1_ASSUME_DTIM_SET(x) (((x) << MAC_PCU_SLP1_ASSUME_DTIM_LSB) & MAC_PCU_SLP1_ASSUME_DTIM_MASK) +#define MAC_PCU_SLP1_CAB_TIMEOUT_MSB 15 +#define MAC_PCU_SLP1_CAB_TIMEOUT_LSB 0 +#define MAC_PCU_SLP1_CAB_TIMEOUT_MASK 0x0000ffff +#define MAC_PCU_SLP1_CAB_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP1_CAB_TIMEOUT_MASK) >> MAC_PCU_SLP1_CAB_TIMEOUT_LSB) +#define MAC_PCU_SLP1_CAB_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP1_CAB_TIMEOUT_LSB) & MAC_PCU_SLP1_CAB_TIMEOUT_MASK) + +#define MAC_PCU_SLP2_ADDRESS 0x00000208 +#define MAC_PCU_SLP2_OFFSET 0x00000208 +#define MAC_PCU_SLP2_BEACON_TIMEOUT_MSB 15 +#define MAC_PCU_SLP2_BEACON_TIMEOUT_LSB 0 +#define MAC_PCU_SLP2_BEACON_TIMEOUT_MASK 0x0000ffff +#define MAC_PCU_SLP2_BEACON_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP2_BEACON_TIMEOUT_MASK) >> MAC_PCU_SLP2_BEACON_TIMEOUT_LSB) +#define MAC_PCU_SLP2_BEACON_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP2_BEACON_TIMEOUT_LSB) & MAC_PCU_SLP2_BEACON_TIMEOUT_MASK) + +#define MAC_PCU_RESET_TSF_ADDRESS 0x0000020c +#define MAC_PCU_RESET_TSF_OFFSET 0x0000020c +#define MAC_PCU_RESET_TSF_ONE_SHOT2_MSB 25 +#define MAC_PCU_RESET_TSF_ONE_SHOT2_LSB 25 +#define MAC_PCU_RESET_TSF_ONE_SHOT2_MASK 0x02000000 +#define MAC_PCU_RESET_TSF_ONE_SHOT2_GET(x) (((x) & MAC_PCU_RESET_TSF_ONE_SHOT2_MASK) >> MAC_PCU_RESET_TSF_ONE_SHOT2_LSB) +#define MAC_PCU_RESET_TSF_ONE_SHOT2_SET(x) (((x) << MAC_PCU_RESET_TSF_ONE_SHOT2_LSB) & MAC_PCU_RESET_TSF_ONE_SHOT2_MASK) +#define MAC_PCU_RESET_TSF_ONE_SHOT_MSB 24 +#define MAC_PCU_RESET_TSF_ONE_SHOT_LSB 24 +#define MAC_PCU_RESET_TSF_ONE_SHOT_MASK 0x01000000 +#define MAC_PCU_RESET_TSF_ONE_SHOT_GET(x) (((x) & MAC_PCU_RESET_TSF_ONE_SHOT_MASK) >> MAC_PCU_RESET_TSF_ONE_SHOT_LSB) +#define MAC_PCU_RESET_TSF_ONE_SHOT_SET(x) (((x) << MAC_PCU_RESET_TSF_ONE_SHOT_LSB) & MAC_PCU_RESET_TSF_ONE_SHOT_MASK) + +#define MAC_PCU_TSF_ADD_PLL_ADDRESS 0x00000210 +#define MAC_PCU_TSF_ADD_PLL_OFFSET 0x00000210 +#define MAC_PCU_TSF_ADD_PLL_VALUE_MSB 7 +#define MAC_PCU_TSF_ADD_PLL_VALUE_LSB 0 +#define MAC_PCU_TSF_ADD_PLL_VALUE_MASK 0x000000ff +#define MAC_PCU_TSF_ADD_PLL_VALUE_GET(x) (((x) & MAC_PCU_TSF_ADD_PLL_VALUE_MASK) >> MAC_PCU_TSF_ADD_PLL_VALUE_LSB) +#define MAC_PCU_TSF_ADD_PLL_VALUE_SET(x) (((x) << MAC_PCU_TSF_ADD_PLL_VALUE_LSB) & MAC_PCU_TSF_ADD_PLL_VALUE_MASK) + +#define SLEEP_RETENTION_ADDRESS 0x00000214 +#define SLEEP_RETENTION_OFFSET 0x00000214 +#define SLEEP_RETENTION_TIME_MSB 9 +#define SLEEP_RETENTION_TIME_LSB 2 +#define SLEEP_RETENTION_TIME_MASK 0x000003fc +#define SLEEP_RETENTION_TIME_GET(x) (((x) & SLEEP_RETENTION_TIME_MASK) >> SLEEP_RETENTION_TIME_LSB) +#define SLEEP_RETENTION_TIME_SET(x) (((x) << SLEEP_RETENTION_TIME_LSB) & SLEEP_RETENTION_TIME_MASK) +#define SLEEP_RETENTION_MODE_MSB 1 +#define SLEEP_RETENTION_MODE_LSB 1 +#define SLEEP_RETENTION_MODE_MASK 0x00000002 +#define SLEEP_RETENTION_MODE_GET(x) (((x) & SLEEP_RETENTION_MODE_MASK) >> SLEEP_RETENTION_MODE_LSB) +#define SLEEP_RETENTION_MODE_SET(x) (((x) << SLEEP_RETENTION_MODE_LSB) & SLEEP_RETENTION_MODE_MASK) +#define SLEEP_RETENTION_ENABLE_MSB 0 +#define SLEEP_RETENTION_ENABLE_LSB 0 +#define SLEEP_RETENTION_ENABLE_MASK 0x00000001 +#define SLEEP_RETENTION_ENABLE_GET(x) (((x) & SLEEP_RETENTION_ENABLE_MASK) >> SLEEP_RETENTION_ENABLE_LSB) +#define SLEEP_RETENTION_ENABLE_SET(x) (((x) << SLEEP_RETENTION_ENABLE_LSB) & SLEEP_RETENTION_ENABLE_MASK) + +#define BTCOEXCTRL_ADDRESS 0x00000218 +#define BTCOEXCTRL_OFFSET 0x00000218 +#define BTCOEXCTRL_WBTIMER_ENABLE_MSB 26 +#define BTCOEXCTRL_WBTIMER_ENABLE_LSB 26 +#define BTCOEXCTRL_WBTIMER_ENABLE_MASK 0x04000000 +#define BTCOEXCTRL_WBTIMER_ENABLE_GET(x) (((x) & BTCOEXCTRL_WBTIMER_ENABLE_MASK) >> BTCOEXCTRL_WBTIMER_ENABLE_LSB) +#define BTCOEXCTRL_WBTIMER_ENABLE_SET(x) (((x) << BTCOEXCTRL_WBTIMER_ENABLE_LSB) & BTCOEXCTRL_WBTIMER_ENABLE_MASK) +#define BTCOEXCTRL_WBSYNC_ON_BEACON_MSB 25 +#define BTCOEXCTRL_WBSYNC_ON_BEACON_LSB 25 +#define BTCOEXCTRL_WBSYNC_ON_BEACON_MASK 0x02000000 +#define BTCOEXCTRL_WBSYNC_ON_BEACON_GET(x) (((x) & BTCOEXCTRL_WBSYNC_ON_BEACON_MASK) >> BTCOEXCTRL_WBSYNC_ON_BEACON_LSB) +#define BTCOEXCTRL_WBSYNC_ON_BEACON_SET(x) (((x) << BTCOEXCTRL_WBSYNC_ON_BEACON_LSB) & BTCOEXCTRL_WBSYNC_ON_BEACON_MASK) +#define BTCOEXCTRL_PTA_MODE_MSB 24 +#define BTCOEXCTRL_PTA_MODE_LSB 23 +#define BTCOEXCTRL_PTA_MODE_MASK 0x01800000 +#define BTCOEXCTRL_PTA_MODE_GET(x) (((x) & BTCOEXCTRL_PTA_MODE_MASK) >> BTCOEXCTRL_PTA_MODE_LSB) +#define BTCOEXCTRL_PTA_MODE_SET(x) (((x) << BTCOEXCTRL_PTA_MODE_LSB) & BTCOEXCTRL_PTA_MODE_MASK) +#define BTCOEXCTRL_FREQ_TIME_MSB 22 +#define BTCOEXCTRL_FREQ_TIME_LSB 18 +#define BTCOEXCTRL_FREQ_TIME_MASK 0x007c0000 +#define BTCOEXCTRL_FREQ_TIME_GET(x) (((x) & BTCOEXCTRL_FREQ_TIME_MASK) >> BTCOEXCTRL_FREQ_TIME_LSB) +#define BTCOEXCTRL_FREQ_TIME_SET(x) (((x) << BTCOEXCTRL_FREQ_TIME_LSB) & BTCOEXCTRL_FREQ_TIME_MASK) +#define BTCOEXCTRL_PRIORITY_TIME_MSB 17 +#define BTCOEXCTRL_PRIORITY_TIME_LSB 12 +#define BTCOEXCTRL_PRIORITY_TIME_MASK 0x0003f000 +#define BTCOEXCTRL_PRIORITY_TIME_GET(x) (((x) & BTCOEXCTRL_PRIORITY_TIME_MASK) >> BTCOEXCTRL_PRIORITY_TIME_LSB) +#define BTCOEXCTRL_PRIORITY_TIME_SET(x) (((x) << BTCOEXCTRL_PRIORITY_TIME_LSB) & BTCOEXCTRL_PRIORITY_TIME_MASK) +#define BTCOEXCTRL_SYNC_DET_EN_MSB 11 +#define BTCOEXCTRL_SYNC_DET_EN_LSB 11 +#define BTCOEXCTRL_SYNC_DET_EN_MASK 0x00000800 +#define BTCOEXCTRL_SYNC_DET_EN_GET(x) (((x) & BTCOEXCTRL_SYNC_DET_EN_MASK) >> BTCOEXCTRL_SYNC_DET_EN_LSB) +#define BTCOEXCTRL_SYNC_DET_EN_SET(x) (((x) << BTCOEXCTRL_SYNC_DET_EN_LSB) & BTCOEXCTRL_SYNC_DET_EN_MASK) +#define BTCOEXCTRL_IDLE_CNT_EN_MSB 10 +#define BTCOEXCTRL_IDLE_CNT_EN_LSB 10 +#define BTCOEXCTRL_IDLE_CNT_EN_MASK 0x00000400 +#define BTCOEXCTRL_IDLE_CNT_EN_GET(x) (((x) & BTCOEXCTRL_IDLE_CNT_EN_MASK) >> BTCOEXCTRL_IDLE_CNT_EN_LSB) +#define BTCOEXCTRL_IDLE_CNT_EN_SET(x) (((x) << BTCOEXCTRL_IDLE_CNT_EN_LSB) & BTCOEXCTRL_IDLE_CNT_EN_MASK) +#define BTCOEXCTRL_FRAME_CNT_EN_MSB 9 +#define BTCOEXCTRL_FRAME_CNT_EN_LSB 9 +#define BTCOEXCTRL_FRAME_CNT_EN_MASK 0x00000200 +#define BTCOEXCTRL_FRAME_CNT_EN_GET(x) (((x) & BTCOEXCTRL_FRAME_CNT_EN_MASK) >> BTCOEXCTRL_FRAME_CNT_EN_LSB) +#define BTCOEXCTRL_FRAME_CNT_EN_SET(x) (((x) << BTCOEXCTRL_FRAME_CNT_EN_LSB) & BTCOEXCTRL_FRAME_CNT_EN_MASK) +#define BTCOEXCTRL_CLK_CNT_EN_MSB 8 +#define BTCOEXCTRL_CLK_CNT_EN_LSB 8 +#define BTCOEXCTRL_CLK_CNT_EN_MASK 0x00000100 +#define BTCOEXCTRL_CLK_CNT_EN_GET(x) (((x) & BTCOEXCTRL_CLK_CNT_EN_MASK) >> BTCOEXCTRL_CLK_CNT_EN_LSB) +#define BTCOEXCTRL_CLK_CNT_EN_SET(x) (((x) << BTCOEXCTRL_CLK_CNT_EN_LSB) & BTCOEXCTRL_CLK_CNT_EN_MASK) +#define BTCOEXCTRL_GAP_MSB 7 +#define BTCOEXCTRL_GAP_LSB 0 +#define BTCOEXCTRL_GAP_MASK 0x000000ff +#define BTCOEXCTRL_GAP_GET(x) (((x) & BTCOEXCTRL_GAP_MASK) >> BTCOEXCTRL_GAP_LSB) +#define BTCOEXCTRL_GAP_SET(x) (((x) << BTCOEXCTRL_GAP_LSB) & BTCOEXCTRL_GAP_MASK) + +#define WBSYNC_PRIORITY1_ADDRESS 0x0000021c +#define WBSYNC_PRIORITY1_OFFSET 0x0000021c +#define WBSYNC_PRIORITY1_BITMAP_MSB 31 +#define WBSYNC_PRIORITY1_BITMAP_LSB 0 +#define WBSYNC_PRIORITY1_BITMAP_MASK 0xffffffff +#define WBSYNC_PRIORITY1_BITMAP_GET(x) (((x) & WBSYNC_PRIORITY1_BITMAP_MASK) >> WBSYNC_PRIORITY1_BITMAP_LSB) +#define WBSYNC_PRIORITY1_BITMAP_SET(x) (((x) << WBSYNC_PRIORITY1_BITMAP_LSB) & WBSYNC_PRIORITY1_BITMAP_MASK) + +#define WBSYNC_PRIORITY2_ADDRESS 0x00000220 +#define WBSYNC_PRIORITY2_OFFSET 0x00000220 +#define WBSYNC_PRIORITY2_BITMAP_MSB 31 +#define WBSYNC_PRIORITY2_BITMAP_LSB 0 +#define WBSYNC_PRIORITY2_BITMAP_MASK 0xffffffff +#define WBSYNC_PRIORITY2_BITMAP_GET(x) (((x) & WBSYNC_PRIORITY2_BITMAP_MASK) >> WBSYNC_PRIORITY2_BITMAP_LSB) +#define WBSYNC_PRIORITY2_BITMAP_SET(x) (((x) << WBSYNC_PRIORITY2_BITMAP_LSB) & WBSYNC_PRIORITY2_BITMAP_MASK) + +#define WBSYNC_PRIORITY3_ADDRESS 0x00000224 +#define WBSYNC_PRIORITY3_OFFSET 0x00000224 +#define WBSYNC_PRIORITY3_BITMAP_MSB 31 +#define WBSYNC_PRIORITY3_BITMAP_LSB 0 +#define WBSYNC_PRIORITY3_BITMAP_MASK 0xffffffff +#define WBSYNC_PRIORITY3_BITMAP_GET(x) (((x) & WBSYNC_PRIORITY3_BITMAP_MASK) >> WBSYNC_PRIORITY3_BITMAP_LSB) +#define WBSYNC_PRIORITY3_BITMAP_SET(x) (((x) << WBSYNC_PRIORITY3_BITMAP_LSB) & WBSYNC_PRIORITY3_BITMAP_MASK) + +#define BTCOEX0_ADDRESS 0x00000228 +#define BTCOEX0_OFFSET 0x00000228 +#define BTCOEX0_SYNC_DUR_MSB 7 +#define BTCOEX0_SYNC_DUR_LSB 0 +#define BTCOEX0_SYNC_DUR_MASK 0x000000ff +#define BTCOEX0_SYNC_DUR_GET(x) (((x) & BTCOEX0_SYNC_DUR_MASK) >> BTCOEX0_SYNC_DUR_LSB) +#define BTCOEX0_SYNC_DUR_SET(x) (((x) << BTCOEX0_SYNC_DUR_LSB) & BTCOEX0_SYNC_DUR_MASK) + +#define BTCOEX1_ADDRESS 0x0000022c +#define BTCOEX1_OFFSET 0x0000022c +#define BTCOEX1_CLK_THRES_MSB 20 +#define BTCOEX1_CLK_THRES_LSB 0 +#define BTCOEX1_CLK_THRES_MASK 0x001fffff +#define BTCOEX1_CLK_THRES_GET(x) (((x) & BTCOEX1_CLK_THRES_MASK) >> BTCOEX1_CLK_THRES_LSB) +#define BTCOEX1_CLK_THRES_SET(x) (((x) << BTCOEX1_CLK_THRES_LSB) & BTCOEX1_CLK_THRES_MASK) + +#define BTCOEX2_ADDRESS 0x00000230 +#define BTCOEX2_OFFSET 0x00000230 +#define BTCOEX2_FRAME_THRES_MSB 7 +#define BTCOEX2_FRAME_THRES_LSB 0 +#define BTCOEX2_FRAME_THRES_MASK 0x000000ff +#define BTCOEX2_FRAME_THRES_GET(x) (((x) & BTCOEX2_FRAME_THRES_MASK) >> BTCOEX2_FRAME_THRES_LSB) +#define BTCOEX2_FRAME_THRES_SET(x) (((x) << BTCOEX2_FRAME_THRES_LSB) & BTCOEX2_FRAME_THRES_MASK) + +#define BTCOEX3_ADDRESS 0x00000234 +#define BTCOEX3_OFFSET 0x00000234 +#define BTCOEX3_CLK_CNT_MSB 20 +#define BTCOEX3_CLK_CNT_LSB 0 +#define BTCOEX3_CLK_CNT_MASK 0x001fffff +#define BTCOEX3_CLK_CNT_GET(x) (((x) & BTCOEX3_CLK_CNT_MASK) >> BTCOEX3_CLK_CNT_LSB) +#define BTCOEX3_CLK_CNT_SET(x) (((x) << BTCOEX3_CLK_CNT_LSB) & BTCOEX3_CLK_CNT_MASK) + +#define BTCOEX4_ADDRESS 0x00000238 +#define BTCOEX4_OFFSET 0x00000238 +#define BTCOEX4_FRAME_CNT_MSB 7 +#define BTCOEX4_FRAME_CNT_LSB 0 +#define BTCOEX4_FRAME_CNT_MASK 0x000000ff +#define BTCOEX4_FRAME_CNT_GET(x) (((x) & BTCOEX4_FRAME_CNT_MASK) >> BTCOEX4_FRAME_CNT_LSB) +#define BTCOEX4_FRAME_CNT_SET(x) (((x) << BTCOEX4_FRAME_CNT_LSB) & BTCOEX4_FRAME_CNT_MASK) + +#define BTCOEX5_ADDRESS 0x0000023c +#define BTCOEX5_OFFSET 0x0000023c +#define BTCOEX5_IDLE_CNT_MSB 15 +#define BTCOEX5_IDLE_CNT_LSB 0 +#define BTCOEX5_IDLE_CNT_MASK 0x0000ffff +#define BTCOEX5_IDLE_CNT_GET(x) (((x) & BTCOEX5_IDLE_CNT_MASK) >> BTCOEX5_IDLE_CNT_LSB) +#define BTCOEX5_IDLE_CNT_SET(x) (((x) << BTCOEX5_IDLE_CNT_LSB) & BTCOEX5_IDLE_CNT_MASK) + +#define BTCOEX6_ADDRESS 0x00000240 +#define BTCOEX6_OFFSET 0x00000240 +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_MSB 31 +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB 0 +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK 0xffffffff +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_GET(x) (((x) & BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK) >> BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB) +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_SET(x) (((x) << BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB) & BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK) + +#define LOCK_ADDRESS 0x00000244 +#define LOCK_OFFSET 0x00000244 +#define LOCK_TLOCK_SLAVE_MSB 31 +#define LOCK_TLOCK_SLAVE_LSB 24 +#define LOCK_TLOCK_SLAVE_MASK 0xff000000 +#define LOCK_TLOCK_SLAVE_GET(x) (((x) & LOCK_TLOCK_SLAVE_MASK) >> LOCK_TLOCK_SLAVE_LSB) +#define LOCK_TLOCK_SLAVE_SET(x) (((x) << LOCK_TLOCK_SLAVE_LSB) & LOCK_TLOCK_SLAVE_MASK) +#define LOCK_TUNLOCK_SLAVE_MSB 23 +#define LOCK_TUNLOCK_SLAVE_LSB 16 +#define LOCK_TUNLOCK_SLAVE_MASK 0x00ff0000 +#define LOCK_TUNLOCK_SLAVE_GET(x) (((x) & LOCK_TUNLOCK_SLAVE_MASK) >> LOCK_TUNLOCK_SLAVE_LSB) +#define LOCK_TUNLOCK_SLAVE_SET(x) (((x) << LOCK_TUNLOCK_SLAVE_LSB) & LOCK_TUNLOCK_SLAVE_MASK) +#define LOCK_TLOCK_MASTER_MSB 15 +#define LOCK_TLOCK_MASTER_LSB 8 +#define LOCK_TLOCK_MASTER_MASK 0x0000ff00 +#define LOCK_TLOCK_MASTER_GET(x) (((x) & LOCK_TLOCK_MASTER_MASK) >> LOCK_TLOCK_MASTER_LSB) +#define LOCK_TLOCK_MASTER_SET(x) (((x) << LOCK_TLOCK_MASTER_LSB) & LOCK_TLOCK_MASTER_MASK) +#define LOCK_TUNLOCK_MASTER_MSB 7 +#define LOCK_TUNLOCK_MASTER_LSB 0 +#define LOCK_TUNLOCK_MASTER_MASK 0x000000ff +#define LOCK_TUNLOCK_MASTER_GET(x) (((x) & LOCK_TUNLOCK_MASTER_MASK) >> LOCK_TUNLOCK_MASTER_LSB) +#define LOCK_TUNLOCK_MASTER_SET(x) (((x) << LOCK_TUNLOCK_MASTER_LSB) & LOCK_TUNLOCK_MASTER_MASK) + +#define NOLOCK_PRIORITY_ADDRESS 0x00000248 +#define NOLOCK_PRIORITY_OFFSET 0x00000248 +#define NOLOCK_PRIORITY_BITMAP_MSB 31 +#define NOLOCK_PRIORITY_BITMAP_LSB 0 +#define NOLOCK_PRIORITY_BITMAP_MASK 0xffffffff +#define NOLOCK_PRIORITY_BITMAP_GET(x) (((x) & NOLOCK_PRIORITY_BITMAP_MASK) >> NOLOCK_PRIORITY_BITMAP_LSB) +#define NOLOCK_PRIORITY_BITMAP_SET(x) (((x) << NOLOCK_PRIORITY_BITMAP_LSB) & NOLOCK_PRIORITY_BITMAP_MASK) + +#define WBSYNC_ADDRESS 0x0000024c +#define WBSYNC_OFFSET 0x0000024c +#define WBSYNC_BTCLOCK_MSB 31 +#define WBSYNC_BTCLOCK_LSB 0 +#define WBSYNC_BTCLOCK_MASK 0xffffffff +#define WBSYNC_BTCLOCK_GET(x) (((x) & WBSYNC_BTCLOCK_MASK) >> WBSYNC_BTCLOCK_LSB) +#define WBSYNC_BTCLOCK_SET(x) (((x) << WBSYNC_BTCLOCK_LSB) & WBSYNC_BTCLOCK_MASK) + +#define WBSYNC1_ADDRESS 0x00000250 +#define WBSYNC1_OFFSET 0x00000250 +#define WBSYNC1_BTCLOCK_MSB 31 +#define WBSYNC1_BTCLOCK_LSB 0 +#define WBSYNC1_BTCLOCK_MASK 0xffffffff +#define WBSYNC1_BTCLOCK_GET(x) (((x) & WBSYNC1_BTCLOCK_MASK) >> WBSYNC1_BTCLOCK_LSB) +#define WBSYNC1_BTCLOCK_SET(x) (((x) << WBSYNC1_BTCLOCK_LSB) & WBSYNC1_BTCLOCK_MASK) + +#define WBSYNC2_ADDRESS 0x00000254 +#define WBSYNC2_OFFSET 0x00000254 +#define WBSYNC2_BTCLOCK_MSB 31 +#define WBSYNC2_BTCLOCK_LSB 0 +#define WBSYNC2_BTCLOCK_MASK 0xffffffff +#define WBSYNC2_BTCLOCK_GET(x) (((x) & WBSYNC2_BTCLOCK_MASK) >> WBSYNC2_BTCLOCK_LSB) +#define WBSYNC2_BTCLOCK_SET(x) (((x) << WBSYNC2_BTCLOCK_LSB) & WBSYNC2_BTCLOCK_MASK) + +#define WBSYNC3_ADDRESS 0x00000258 +#define WBSYNC3_OFFSET 0x00000258 +#define WBSYNC3_BTCLOCK_MSB 31 +#define WBSYNC3_BTCLOCK_LSB 0 +#define WBSYNC3_BTCLOCK_MASK 0xffffffff +#define WBSYNC3_BTCLOCK_GET(x) (((x) & WBSYNC3_BTCLOCK_MASK) >> WBSYNC3_BTCLOCK_LSB) +#define WBSYNC3_BTCLOCK_SET(x) (((x) << WBSYNC3_BTCLOCK_LSB) & WBSYNC3_BTCLOCK_MASK) + +#define WB_TIMER_TARGET_ADDRESS 0x0000025c +#define WB_TIMER_TARGET_OFFSET 0x0000025c +#define WB_TIMER_TARGET_VALUE_MSB 31 +#define WB_TIMER_TARGET_VALUE_LSB 0 +#define WB_TIMER_TARGET_VALUE_MASK 0xffffffff +#define WB_TIMER_TARGET_VALUE_GET(x) (((x) & WB_TIMER_TARGET_VALUE_MASK) >> WB_TIMER_TARGET_VALUE_LSB) +#define WB_TIMER_TARGET_VALUE_SET(x) (((x) << WB_TIMER_TARGET_VALUE_LSB) & WB_TIMER_TARGET_VALUE_MASK) + +#define WB_TIMER_SLOP_ADDRESS 0x00000260 +#define WB_TIMER_SLOP_OFFSET 0x00000260 +#define WB_TIMER_SLOP_VALUE_MSB 9 +#define WB_TIMER_SLOP_VALUE_LSB 0 +#define WB_TIMER_SLOP_VALUE_MASK 0x000003ff +#define WB_TIMER_SLOP_VALUE_GET(x) (((x) & WB_TIMER_SLOP_VALUE_MASK) >> WB_TIMER_SLOP_VALUE_LSB) +#define WB_TIMER_SLOP_VALUE_SET(x) (((x) << WB_TIMER_SLOP_VALUE_LSB) & WB_TIMER_SLOP_VALUE_MASK) + +#define BTCOEX_INT_EN_ADDRESS 0x00000264 +#define BTCOEX_INT_EN_OFFSET 0x00000264 +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MSB 11 +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB 11 +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK 0x00000800 +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_GET(x) (((x) & BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK) >> BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB) +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_SET(x) (((x) << BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB) & BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK) +#define BTCOEX_INT_EN_I2C_TX_FAILED_MSB 10 +#define BTCOEX_INT_EN_I2C_TX_FAILED_LSB 10 +#define BTCOEX_INT_EN_I2C_TX_FAILED_MASK 0x00000400 +#define BTCOEX_INT_EN_I2C_TX_FAILED_GET(x) (((x) & BTCOEX_INT_EN_I2C_TX_FAILED_MASK) >> BTCOEX_INT_EN_I2C_TX_FAILED_LSB) +#define BTCOEX_INT_EN_I2C_TX_FAILED_SET(x) (((x) << BTCOEX_INT_EN_I2C_TX_FAILED_LSB) & BTCOEX_INT_EN_I2C_TX_FAILED_MASK) +#define BTCOEX_INT_EN_I2C_MESG_SENT_MSB 9 +#define BTCOEX_INT_EN_I2C_MESG_SENT_LSB 9 +#define BTCOEX_INT_EN_I2C_MESG_SENT_MASK 0x00000200 +#define BTCOEX_INT_EN_I2C_MESG_SENT_GET(x) (((x) & BTCOEX_INT_EN_I2C_MESG_SENT_MASK) >> BTCOEX_INT_EN_I2C_MESG_SENT_LSB) +#define BTCOEX_INT_EN_I2C_MESG_SENT_SET(x) (((x) << BTCOEX_INT_EN_I2C_MESG_SENT_LSB) & BTCOEX_INT_EN_I2C_MESG_SENT_MASK) +#define BTCOEX_INT_EN_ST_MESG_RECV_MSB 8 +#define BTCOEX_INT_EN_ST_MESG_RECV_LSB 8 +#define BTCOEX_INT_EN_ST_MESG_RECV_MASK 0x00000100 +#define BTCOEX_INT_EN_ST_MESG_RECV_GET(x) (((x) & BTCOEX_INT_EN_ST_MESG_RECV_MASK) >> BTCOEX_INT_EN_ST_MESG_RECV_LSB) +#define BTCOEX_INT_EN_ST_MESG_RECV_SET(x) (((x) << BTCOEX_INT_EN_ST_MESG_RECV_LSB) & BTCOEX_INT_EN_ST_MESG_RECV_MASK) +#define BTCOEX_INT_EN_WB_TIMER_MSB 7 +#define BTCOEX_INT_EN_WB_TIMER_LSB 7 +#define BTCOEX_INT_EN_WB_TIMER_MASK 0x00000080 +#define BTCOEX_INT_EN_WB_TIMER_GET(x) (((x) & BTCOEX_INT_EN_WB_TIMER_MASK) >> BTCOEX_INT_EN_WB_TIMER_LSB) +#define BTCOEX_INT_EN_WB_TIMER_SET(x) (((x) << BTCOEX_INT_EN_WB_TIMER_LSB) & BTCOEX_INT_EN_WB_TIMER_MASK) +#define BTCOEX_INT_EN_NOSYNC_MSB 4 +#define BTCOEX_INT_EN_NOSYNC_LSB 4 +#define BTCOEX_INT_EN_NOSYNC_MASK 0x00000010 +#define BTCOEX_INT_EN_NOSYNC_GET(x) (((x) & BTCOEX_INT_EN_NOSYNC_MASK) >> BTCOEX_INT_EN_NOSYNC_LSB) +#define BTCOEX_INT_EN_NOSYNC_SET(x) (((x) << BTCOEX_INT_EN_NOSYNC_LSB) & BTCOEX_INT_EN_NOSYNC_MASK) +#define BTCOEX_INT_EN_SYNC_MSB 3 +#define BTCOEX_INT_EN_SYNC_LSB 3 +#define BTCOEX_INT_EN_SYNC_MASK 0x00000008 +#define BTCOEX_INT_EN_SYNC_GET(x) (((x) & BTCOEX_INT_EN_SYNC_MASK) >> BTCOEX_INT_EN_SYNC_LSB) +#define BTCOEX_INT_EN_SYNC_SET(x) (((x) << BTCOEX_INT_EN_SYNC_LSB) & BTCOEX_INT_EN_SYNC_MASK) +#define BTCOEX_INT_EN_END_MSB 2 +#define BTCOEX_INT_EN_END_LSB 2 +#define BTCOEX_INT_EN_END_MASK 0x00000004 +#define BTCOEX_INT_EN_END_GET(x) (((x) & BTCOEX_INT_EN_END_MASK) >> BTCOEX_INT_EN_END_LSB) +#define BTCOEX_INT_EN_END_SET(x) (((x) << BTCOEX_INT_EN_END_LSB) & BTCOEX_INT_EN_END_MASK) +#define BTCOEX_INT_EN_FRAME_CNT_MSB 1 +#define BTCOEX_INT_EN_FRAME_CNT_LSB 1 +#define BTCOEX_INT_EN_FRAME_CNT_MASK 0x00000002 +#define BTCOEX_INT_EN_FRAME_CNT_GET(x) (((x) & BTCOEX_INT_EN_FRAME_CNT_MASK) >> BTCOEX_INT_EN_FRAME_CNT_LSB) +#define BTCOEX_INT_EN_FRAME_CNT_SET(x) (((x) << BTCOEX_INT_EN_FRAME_CNT_LSB) & BTCOEX_INT_EN_FRAME_CNT_MASK) +#define BTCOEX_INT_EN_CLK_CNT_MSB 0 +#define BTCOEX_INT_EN_CLK_CNT_LSB 0 +#define BTCOEX_INT_EN_CLK_CNT_MASK 0x00000001 +#define BTCOEX_INT_EN_CLK_CNT_GET(x) (((x) & BTCOEX_INT_EN_CLK_CNT_MASK) >> BTCOEX_INT_EN_CLK_CNT_LSB) +#define BTCOEX_INT_EN_CLK_CNT_SET(x) (((x) << BTCOEX_INT_EN_CLK_CNT_LSB) & BTCOEX_INT_EN_CLK_CNT_MASK) + +#define BTCOEX_INT_STAT_ADDRESS 0x00000268 +#define BTCOEX_INT_STAT_OFFSET 0x00000268 +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MSB 11 +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB 11 +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK 0x00000800 +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_GET(x) (((x) & BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK) >> BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB) +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_SET(x) (((x) << BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB) & BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK) +#define BTCOEX_INT_STAT_I2C_TX_FAILED_MSB 10 +#define BTCOEX_INT_STAT_I2C_TX_FAILED_LSB 10 +#define BTCOEX_INT_STAT_I2C_TX_FAILED_MASK 0x00000400 +#define BTCOEX_INT_STAT_I2C_TX_FAILED_GET(x) (((x) & BTCOEX_INT_STAT_I2C_TX_FAILED_MASK) >> BTCOEX_INT_STAT_I2C_TX_FAILED_LSB) +#define BTCOEX_INT_STAT_I2C_TX_FAILED_SET(x) (((x) << BTCOEX_INT_STAT_I2C_TX_FAILED_LSB) & BTCOEX_INT_STAT_I2C_TX_FAILED_MASK) +#define BTCOEX_INT_STAT_I2C_MESG_SENT_MSB 9 +#define BTCOEX_INT_STAT_I2C_MESG_SENT_LSB 9 +#define BTCOEX_INT_STAT_I2C_MESG_SENT_MASK 0x00000200 +#define BTCOEX_INT_STAT_I2C_MESG_SENT_GET(x) (((x) & BTCOEX_INT_STAT_I2C_MESG_SENT_MASK) >> BTCOEX_INT_STAT_I2C_MESG_SENT_LSB) +#define BTCOEX_INT_STAT_I2C_MESG_SENT_SET(x) (((x) << BTCOEX_INT_STAT_I2C_MESG_SENT_LSB) & BTCOEX_INT_STAT_I2C_MESG_SENT_MASK) +#define BTCOEX_INT_STAT_I2C_MESG_RECV_MSB 8 +#define BTCOEX_INT_STAT_I2C_MESG_RECV_LSB 8 +#define BTCOEX_INT_STAT_I2C_MESG_RECV_MASK 0x00000100 +#define BTCOEX_INT_STAT_I2C_MESG_RECV_GET(x) (((x) & BTCOEX_INT_STAT_I2C_MESG_RECV_MASK) >> BTCOEX_INT_STAT_I2C_MESG_RECV_LSB) +#define BTCOEX_INT_STAT_I2C_MESG_RECV_SET(x) (((x) << BTCOEX_INT_STAT_I2C_MESG_RECV_LSB) & BTCOEX_INT_STAT_I2C_MESG_RECV_MASK) +#define BTCOEX_INT_STAT_WB_TIMER_MSB 7 +#define BTCOEX_INT_STAT_WB_TIMER_LSB 7 +#define BTCOEX_INT_STAT_WB_TIMER_MASK 0x00000080 +#define BTCOEX_INT_STAT_WB_TIMER_GET(x) (((x) & BTCOEX_INT_STAT_WB_TIMER_MASK) >> BTCOEX_INT_STAT_WB_TIMER_LSB) +#define BTCOEX_INT_STAT_WB_TIMER_SET(x) (((x) << BTCOEX_INT_STAT_WB_TIMER_LSB) & BTCOEX_INT_STAT_WB_TIMER_MASK) +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_MSB 6 +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB 6 +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK 0x00000040 +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_GET(x) (((x) & BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK) >> BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB) +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_SET(x) (((x) << BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB) & BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK) +#define BTCOEX_INT_STAT_BTPRIORITY_MSB 5 +#define BTCOEX_INT_STAT_BTPRIORITY_LSB 5 +#define BTCOEX_INT_STAT_BTPRIORITY_MASK 0x00000020 +#define BTCOEX_INT_STAT_BTPRIORITY_GET(x) (((x) & BTCOEX_INT_STAT_BTPRIORITY_MASK) >> BTCOEX_INT_STAT_BTPRIORITY_LSB) +#define BTCOEX_INT_STAT_BTPRIORITY_SET(x) (((x) << BTCOEX_INT_STAT_BTPRIORITY_LSB) & BTCOEX_INT_STAT_BTPRIORITY_MASK) +#define BTCOEX_INT_STAT_NOSYNC_MSB 4 +#define BTCOEX_INT_STAT_NOSYNC_LSB 4 +#define BTCOEX_INT_STAT_NOSYNC_MASK 0x00000010 +#define BTCOEX_INT_STAT_NOSYNC_GET(x) (((x) & BTCOEX_INT_STAT_NOSYNC_MASK) >> BTCOEX_INT_STAT_NOSYNC_LSB) +#define BTCOEX_INT_STAT_NOSYNC_SET(x) (((x) << BTCOEX_INT_STAT_NOSYNC_LSB) & BTCOEX_INT_STAT_NOSYNC_MASK) +#define BTCOEX_INT_STAT_SYNC_MSB 3 +#define BTCOEX_INT_STAT_SYNC_LSB 3 +#define BTCOEX_INT_STAT_SYNC_MASK 0x00000008 +#define BTCOEX_INT_STAT_SYNC_GET(x) (((x) & BTCOEX_INT_STAT_SYNC_MASK) >> BTCOEX_INT_STAT_SYNC_LSB) +#define BTCOEX_INT_STAT_SYNC_SET(x) (((x) << BTCOEX_INT_STAT_SYNC_LSB) & BTCOEX_INT_STAT_SYNC_MASK) +#define BTCOEX_INT_STAT_END_MSB 2 +#define BTCOEX_INT_STAT_END_LSB 2 +#define BTCOEX_INT_STAT_END_MASK 0x00000004 +#define BTCOEX_INT_STAT_END_GET(x) (((x) & BTCOEX_INT_STAT_END_MASK) >> BTCOEX_INT_STAT_END_LSB) +#define BTCOEX_INT_STAT_END_SET(x) (((x) << BTCOEX_INT_STAT_END_LSB) & BTCOEX_INT_STAT_END_MASK) +#define BTCOEX_INT_STAT_FRAME_CNT_MSB 1 +#define BTCOEX_INT_STAT_FRAME_CNT_LSB 1 +#define BTCOEX_INT_STAT_FRAME_CNT_MASK 0x00000002 +#define BTCOEX_INT_STAT_FRAME_CNT_GET(x) (((x) & BTCOEX_INT_STAT_FRAME_CNT_MASK) >> BTCOEX_INT_STAT_FRAME_CNT_LSB) +#define BTCOEX_INT_STAT_FRAME_CNT_SET(x) (((x) << BTCOEX_INT_STAT_FRAME_CNT_LSB) & BTCOEX_INT_STAT_FRAME_CNT_MASK) +#define BTCOEX_INT_STAT_CLK_CNT_MSB 0 +#define BTCOEX_INT_STAT_CLK_CNT_LSB 0 +#define BTCOEX_INT_STAT_CLK_CNT_MASK 0x00000001 +#define BTCOEX_INT_STAT_CLK_CNT_GET(x) (((x) & BTCOEX_INT_STAT_CLK_CNT_MASK) >> BTCOEX_INT_STAT_CLK_CNT_LSB) +#define BTCOEX_INT_STAT_CLK_CNT_SET(x) (((x) << BTCOEX_INT_STAT_CLK_CNT_LSB) & BTCOEX_INT_STAT_CLK_CNT_MASK) + +#define BTPRIORITY_INT_EN_ADDRESS 0x0000026c +#define BTPRIORITY_INT_EN_OFFSET 0x0000026c +#define BTPRIORITY_INT_EN_BITMAP_MSB 31 +#define BTPRIORITY_INT_EN_BITMAP_LSB 0 +#define BTPRIORITY_INT_EN_BITMAP_MASK 0xffffffff +#define BTPRIORITY_INT_EN_BITMAP_GET(x) (((x) & BTPRIORITY_INT_EN_BITMAP_MASK) >> BTPRIORITY_INT_EN_BITMAP_LSB) +#define BTPRIORITY_INT_EN_BITMAP_SET(x) (((x) << BTPRIORITY_INT_EN_BITMAP_LSB) & BTPRIORITY_INT_EN_BITMAP_MASK) + +#define BTPRIORITY_INT_STAT_ADDRESS 0x00000270 +#define BTPRIORITY_INT_STAT_OFFSET 0x00000270 +#define BTPRIORITY_INT_STAT_BITMAP_MSB 31 +#define BTPRIORITY_INT_STAT_BITMAP_LSB 0 +#define BTPRIORITY_INT_STAT_BITMAP_MASK 0xffffffff +#define BTPRIORITY_INT_STAT_BITMAP_GET(x) (((x) & BTPRIORITY_INT_STAT_BITMAP_MASK) >> BTPRIORITY_INT_STAT_BITMAP_LSB) +#define BTPRIORITY_INT_STAT_BITMAP_SET(x) (((x) << BTPRIORITY_INT_STAT_BITMAP_LSB) & BTPRIORITY_INT_STAT_BITMAP_MASK) + +#define BTPRIORITY_STOMP_INT_EN_ADDRESS 0x00000274 +#define BTPRIORITY_STOMP_INT_EN_OFFSET 0x00000274 +#define BTPRIORITY_STOMP_INT_EN_BITMAP_MSB 31 +#define BTPRIORITY_STOMP_INT_EN_BITMAP_LSB 0 +#define BTPRIORITY_STOMP_INT_EN_BITMAP_MASK 0xffffffff +#define BTPRIORITY_STOMP_INT_EN_BITMAP_GET(x) (((x) & BTPRIORITY_STOMP_INT_EN_BITMAP_MASK) >> BTPRIORITY_STOMP_INT_EN_BITMAP_LSB) +#define BTPRIORITY_STOMP_INT_EN_BITMAP_SET(x) (((x) << BTPRIORITY_STOMP_INT_EN_BITMAP_LSB) & BTPRIORITY_STOMP_INT_EN_BITMAP_MASK) + +#define BTPRIORITY_STOMP_INT_STAT_ADDRESS 0x00000278 +#define BTPRIORITY_STOMP_INT_STAT_OFFSET 0x00000278 +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_MSB 31 +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB 0 +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK 0xffffffff +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_GET(x) (((x) & BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK) >> BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB) +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_SET(x) (((x) << BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB) & BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK) + +#define MAC_PCU_BMISS_TIMEOUT_ADDRESS 0x0000027c +#define MAC_PCU_BMISS_TIMEOUT_OFFSET 0x0000027c +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_MSB 24 +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB 24 +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK 0x01000000 +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB) +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK) +#define MAC_PCU_BMISS_TIMEOUT_VALUE_MSB 23 +#define MAC_PCU_BMISS_TIMEOUT_VALUE_LSB 0 +#define MAC_PCU_BMISS_TIMEOUT_VALUE_MASK 0x00ffffff +#define MAC_PCU_BMISS_TIMEOUT_VALUE_GET(x) (((x) & MAC_PCU_BMISS_TIMEOUT_VALUE_MASK) >> MAC_PCU_BMISS_TIMEOUT_VALUE_LSB) +#define MAC_PCU_BMISS_TIMEOUT_VALUE_SET(x) (((x) << MAC_PCU_BMISS_TIMEOUT_VALUE_LSB) & MAC_PCU_BMISS_TIMEOUT_VALUE_MASK) + +#define MAC_PCU_CAB_AWAKE_ADDRESS 0x00000280 +#define MAC_PCU_CAB_AWAKE_OFFSET 0x00000280 +#define MAC_PCU_CAB_AWAKE_ENABLE_MSB 16 +#define MAC_PCU_CAB_AWAKE_ENABLE_LSB 16 +#define MAC_PCU_CAB_AWAKE_ENABLE_MASK 0x00010000 +#define MAC_PCU_CAB_AWAKE_ENABLE_GET(x) (((x) & MAC_PCU_CAB_AWAKE_ENABLE_MASK) >> MAC_PCU_CAB_AWAKE_ENABLE_LSB) +#define MAC_PCU_CAB_AWAKE_ENABLE_SET(x) (((x) << MAC_PCU_CAB_AWAKE_ENABLE_LSB) & MAC_PCU_CAB_AWAKE_ENABLE_MASK) +#define MAC_PCU_CAB_AWAKE_DURATION_MSB 15 +#define MAC_PCU_CAB_AWAKE_DURATION_LSB 0 +#define MAC_PCU_CAB_AWAKE_DURATION_MASK 0x0000ffff +#define MAC_PCU_CAB_AWAKE_DURATION_GET(x) (((x) & MAC_PCU_CAB_AWAKE_DURATION_MASK) >> MAC_PCU_CAB_AWAKE_DURATION_LSB) +#define MAC_PCU_CAB_AWAKE_DURATION_SET(x) (((x) << MAC_PCU_CAB_AWAKE_DURATION_LSB) & MAC_PCU_CAB_AWAKE_DURATION_MASK) + +#define LP_PERF_COUNTER_ADDRESS 0x00000284 +#define LP_PERF_COUNTER_OFFSET 0x00000284 +#define LP_PERF_COUNTER_EN_MSB 0 +#define LP_PERF_COUNTER_EN_LSB 0 +#define LP_PERF_COUNTER_EN_MASK 0x00000001 +#define LP_PERF_COUNTER_EN_GET(x) (((x) & LP_PERF_COUNTER_EN_MASK) >> LP_PERF_COUNTER_EN_LSB) +#define LP_PERF_COUNTER_EN_SET(x) (((x) << LP_PERF_COUNTER_EN_LSB) & LP_PERF_COUNTER_EN_MASK) + +#define LP_PERF_LIGHT_SLEEP_ADDRESS 0x00000288 +#define LP_PERF_LIGHT_SLEEP_OFFSET 0x00000288 +#define LP_PERF_LIGHT_SLEEP_CNT_MSB 31 +#define LP_PERF_LIGHT_SLEEP_CNT_LSB 0 +#define LP_PERF_LIGHT_SLEEP_CNT_MASK 0xffffffff +#define LP_PERF_LIGHT_SLEEP_CNT_GET(x) (((x) & LP_PERF_LIGHT_SLEEP_CNT_MASK) >> LP_PERF_LIGHT_SLEEP_CNT_LSB) +#define LP_PERF_LIGHT_SLEEP_CNT_SET(x) (((x) << LP_PERF_LIGHT_SLEEP_CNT_LSB) & LP_PERF_LIGHT_SLEEP_CNT_MASK) + +#define LP_PERF_DEEP_SLEEP_ADDRESS 0x0000028c +#define LP_PERF_DEEP_SLEEP_OFFSET 0x0000028c +#define LP_PERF_DEEP_SLEEP_CNT_MSB 31 +#define LP_PERF_DEEP_SLEEP_CNT_LSB 0 +#define LP_PERF_DEEP_SLEEP_CNT_MASK 0xffffffff +#define LP_PERF_DEEP_SLEEP_CNT_GET(x) (((x) & LP_PERF_DEEP_SLEEP_CNT_MASK) >> LP_PERF_DEEP_SLEEP_CNT_LSB) +#define LP_PERF_DEEP_SLEEP_CNT_SET(x) (((x) << LP_PERF_DEEP_SLEEP_CNT_LSB) & LP_PERF_DEEP_SLEEP_CNT_MASK) + +#define LP_PERF_ON_ADDRESS 0x00000290 +#define LP_PERF_ON_OFFSET 0x00000290 +#define LP_PERF_ON_CNT_MSB 31 +#define LP_PERF_ON_CNT_LSB 0 +#define LP_PERF_ON_CNT_MASK 0xffffffff +#define LP_PERF_ON_CNT_GET(x) (((x) & LP_PERF_ON_CNT_MASK) >> LP_PERF_ON_CNT_LSB) +#define LP_PERF_ON_CNT_SET(x) (((x) << LP_PERF_ON_CNT_LSB) & LP_PERF_ON_CNT_MASK) + +#define ST_64_BIT_ADDRESS 0x00000294 +#define ST_64_BIT_OFFSET 0x00000294 +#define ST_64_BIT_TIMEOUT_MSB 26 +#define ST_64_BIT_TIMEOUT_LSB 9 +#define ST_64_BIT_TIMEOUT_MASK 0x07fffe00 +#define ST_64_BIT_TIMEOUT_GET(x) (((x) & ST_64_BIT_TIMEOUT_MASK) >> ST_64_BIT_TIMEOUT_LSB) +#define ST_64_BIT_TIMEOUT_SET(x) (((x) << ST_64_BIT_TIMEOUT_LSB) & ST_64_BIT_TIMEOUT_MASK) +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MSB 8 +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB 8 +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK 0x00000100 +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_GET(x) (((x) & ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK) >> ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB) +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_SET(x) (((x) << ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB) & ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK) +#define ST_64_BIT_DRIVE_MODE_MSB 7 +#define ST_64_BIT_DRIVE_MODE_LSB 7 +#define ST_64_BIT_DRIVE_MODE_MASK 0x00000080 +#define ST_64_BIT_DRIVE_MODE_GET(x) (((x) & ST_64_BIT_DRIVE_MODE_MASK) >> ST_64_BIT_DRIVE_MODE_LSB) +#define ST_64_BIT_DRIVE_MODE_SET(x) (((x) << ST_64_BIT_DRIVE_MODE_LSB) & ST_64_BIT_DRIVE_MODE_MASK) +#define ST_64_BIT_CLOCK_GATE_MSB 6 +#define ST_64_BIT_CLOCK_GATE_LSB 6 +#define ST_64_BIT_CLOCK_GATE_MASK 0x00000040 +#define ST_64_BIT_CLOCK_GATE_GET(x) (((x) & ST_64_BIT_CLOCK_GATE_MASK) >> ST_64_BIT_CLOCK_GATE_LSB) +#define ST_64_BIT_CLOCK_GATE_SET(x) (((x) << ST_64_BIT_CLOCK_GATE_LSB) & ST_64_BIT_CLOCK_GATE_MASK) +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MSB 5 +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB 1 +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK 0x0000003e +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_GET(x) (((x) & ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK) >> ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB) +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_SET(x) (((x) << ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB) & ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK) +#define ST_64_BIT_MODE_MSB 0 +#define ST_64_BIT_MODE_LSB 0 +#define ST_64_BIT_MODE_MASK 0x00000001 +#define ST_64_BIT_MODE_GET(x) (((x) & ST_64_BIT_MODE_MASK) >> ST_64_BIT_MODE_LSB) +#define ST_64_BIT_MODE_SET(x) (((x) << ST_64_BIT_MODE_LSB) & ST_64_BIT_MODE_MASK) + +#define MESSAGE_WR_ADDRESS 0x00000298 +#define MESSAGE_WR_OFFSET 0x00000298 +#define MESSAGE_WR_TYPE_MSB 31 +#define MESSAGE_WR_TYPE_LSB 0 +#define MESSAGE_WR_TYPE_MASK 0xffffffff +#define MESSAGE_WR_TYPE_GET(x) (((x) & MESSAGE_WR_TYPE_MASK) >> MESSAGE_WR_TYPE_LSB) +#define MESSAGE_WR_TYPE_SET(x) (((x) << MESSAGE_WR_TYPE_LSB) & MESSAGE_WR_TYPE_MASK) + +#define MESSAGE_WR_P_ADDRESS 0x0000029c +#define MESSAGE_WR_P_OFFSET 0x0000029c +#define MESSAGE_WR_P_PARAMETER_MSB 31 +#define MESSAGE_WR_P_PARAMETER_LSB 0 +#define MESSAGE_WR_P_PARAMETER_MASK 0xffffffff +#define MESSAGE_WR_P_PARAMETER_GET(x) (((x) & MESSAGE_WR_P_PARAMETER_MASK) >> MESSAGE_WR_P_PARAMETER_LSB) +#define MESSAGE_WR_P_PARAMETER_SET(x) (((x) << MESSAGE_WR_P_PARAMETER_LSB) & MESSAGE_WR_P_PARAMETER_MASK) + +#define MESSAGE_RD_ADDRESS 0x000002a0 +#define MESSAGE_RD_OFFSET 0x000002a0 +#define MESSAGE_RD_TYPE_MSB 31 +#define MESSAGE_RD_TYPE_LSB 0 +#define MESSAGE_RD_TYPE_MASK 0xffffffff +#define MESSAGE_RD_TYPE_GET(x) (((x) & MESSAGE_RD_TYPE_MASK) >> MESSAGE_RD_TYPE_LSB) +#define MESSAGE_RD_TYPE_SET(x) (((x) << MESSAGE_RD_TYPE_LSB) & MESSAGE_RD_TYPE_MASK) + +#define MESSAGE_RD_P_ADDRESS 0x000002a4 +#define MESSAGE_RD_P_OFFSET 0x000002a4 +#define MESSAGE_RD_P_PARAMETER_MSB 31 +#define MESSAGE_RD_P_PARAMETER_LSB 0 +#define MESSAGE_RD_P_PARAMETER_MASK 0xffffffff +#define MESSAGE_RD_P_PARAMETER_GET(x) (((x) & MESSAGE_RD_P_PARAMETER_MASK) >> MESSAGE_RD_P_PARAMETER_LSB) +#define MESSAGE_RD_P_PARAMETER_SET(x) (((x) << MESSAGE_RD_P_PARAMETER_LSB) & MESSAGE_RD_P_PARAMETER_MASK) + +#define CHIP_MODE_ADDRESS 0x000002a8 +#define CHIP_MODE_OFFSET 0x000002a8 +#define CHIP_MODE_BIT_MSB 1 +#define CHIP_MODE_BIT_LSB 0 +#define CHIP_MODE_BIT_MASK 0x00000003 +#define CHIP_MODE_BIT_GET(x) (((x) & CHIP_MODE_BIT_MASK) >> CHIP_MODE_BIT_LSB) +#define CHIP_MODE_BIT_SET(x) (((x) << CHIP_MODE_BIT_LSB) & CHIP_MODE_BIT_MASK) + +#define CLK_REQ_FALL_EDGE_ADDRESS 0x000002ac +#define CLK_REQ_FALL_EDGE_OFFSET 0x000002ac +#define CLK_REQ_FALL_EDGE_EN_MSB 31 +#define CLK_REQ_FALL_EDGE_EN_LSB 31 +#define CLK_REQ_FALL_EDGE_EN_MASK 0x80000000 +#define CLK_REQ_FALL_EDGE_EN_GET(x) (((x) & CLK_REQ_FALL_EDGE_EN_MASK) >> CLK_REQ_FALL_EDGE_EN_LSB) +#define CLK_REQ_FALL_EDGE_EN_SET(x) (((x) << CLK_REQ_FALL_EDGE_EN_LSB) & CLK_REQ_FALL_EDGE_EN_MASK) +#define CLK_REQ_FALL_EDGE_DELAY_MSB 7 +#define CLK_REQ_FALL_EDGE_DELAY_LSB 0 +#define CLK_REQ_FALL_EDGE_DELAY_MASK 0x000000ff +#define CLK_REQ_FALL_EDGE_DELAY_GET(x) (((x) & CLK_REQ_FALL_EDGE_DELAY_MASK) >> CLK_REQ_FALL_EDGE_DELAY_LSB) +#define CLK_REQ_FALL_EDGE_DELAY_SET(x) (((x) << CLK_REQ_FALL_EDGE_DELAY_LSB) & CLK_REQ_FALL_EDGE_DELAY_MASK) + +#define OTP_ADDRESS 0x000002b0 +#define OTP_OFFSET 0x000002b0 +#define OTP_LDO25_EN_MSB 1 +#define OTP_LDO25_EN_LSB 1 +#define OTP_LDO25_EN_MASK 0x00000002 +#define OTP_LDO25_EN_GET(x) (((x) & OTP_LDO25_EN_MASK) >> OTP_LDO25_EN_LSB) +#define OTP_LDO25_EN_SET(x) (((x) << OTP_LDO25_EN_LSB) & OTP_LDO25_EN_MASK) +#define OTP_VDD12_EN_MSB 0 +#define OTP_VDD12_EN_LSB 0 +#define OTP_VDD12_EN_MASK 0x00000001 +#define OTP_VDD12_EN_GET(x) (((x) & OTP_VDD12_EN_MASK) >> OTP_VDD12_EN_LSB) +#define OTP_VDD12_EN_SET(x) (((x) << OTP_VDD12_EN_LSB) & OTP_VDD12_EN_MASK) + +#define OTP_STATUS_ADDRESS 0x000002b4 +#define OTP_STATUS_OFFSET 0x000002b4 +#define OTP_STATUS_LDO25_EN_READY_MSB 1 +#define OTP_STATUS_LDO25_EN_READY_LSB 1 +#define OTP_STATUS_LDO25_EN_READY_MASK 0x00000002 +#define OTP_STATUS_LDO25_EN_READY_GET(x) (((x) & OTP_STATUS_LDO25_EN_READY_MASK) >> OTP_STATUS_LDO25_EN_READY_LSB) +#define OTP_STATUS_LDO25_EN_READY_SET(x) (((x) << OTP_STATUS_LDO25_EN_READY_LSB) & OTP_STATUS_LDO25_EN_READY_MASK) +#define OTP_STATUS_VDD12_EN_READY_MSB 0 +#define OTP_STATUS_VDD12_EN_READY_LSB 0 +#define OTP_STATUS_VDD12_EN_READY_MASK 0x00000001 +#define OTP_STATUS_VDD12_EN_READY_GET(x) (((x) & OTP_STATUS_VDD12_EN_READY_MASK) >> OTP_STATUS_VDD12_EN_READY_LSB) +#define OTP_STATUS_VDD12_EN_READY_SET(x) (((x) << OTP_STATUS_VDD12_EN_READY_LSB) & OTP_STATUS_VDD12_EN_READY_MASK) + +#define PMU_ADDRESS 0x000002b8 +#define PMU_OFFSET 0x000002b8 +#define PMU_REG_WAKEUP_TIME_SEL_MSB 1 +#define PMU_REG_WAKEUP_TIME_SEL_LSB 0 +#define PMU_REG_WAKEUP_TIME_SEL_MASK 0x00000003 +#define PMU_REG_WAKEUP_TIME_SEL_GET(x) (((x) & PMU_REG_WAKEUP_TIME_SEL_MASK) >> PMU_REG_WAKEUP_TIME_SEL_LSB) +#define PMU_REG_WAKEUP_TIME_SEL_SET(x) (((x) << PMU_REG_WAKEUP_TIME_SEL_LSB) & PMU_REG_WAKEUP_TIME_SEL_MASK) + +#define PMU_CONFIG_ADDRESS 0x000002c0 +#define PMU_CONFIG_OFFSET 0x000002c0 +#define PMU_CONFIG_VALUE_MSB 15 +#define PMU_CONFIG_VALUE_LSB 0 +#define PMU_CONFIG_VALUE_MASK 0x0000ffff +#define PMU_CONFIG_VALUE_GET(x) (((x) & PMU_CONFIG_VALUE_MASK) >> PMU_CONFIG_VALUE_LSB) +#define PMU_CONFIG_VALUE_SET(x) (((x) << PMU_CONFIG_VALUE_LSB) & PMU_CONFIG_VALUE_MASK) + +#define PMU_BYPASS_ADDRESS 0x000002c8 +#define PMU_BYPASS_OFFSET 0x000002c8 +#define PMU_BYPASS_SWREG_MSB 2 +#define PMU_BYPASS_SWREG_LSB 2 +#define PMU_BYPASS_SWREG_MASK 0x00000004 +#define PMU_BYPASS_SWREG_GET(x) (((x) & PMU_BYPASS_SWREG_MASK) >> PMU_BYPASS_SWREG_LSB) +#define PMU_BYPASS_SWREG_SET(x) (((x) << PMU_BYPASS_SWREG_LSB) & PMU_BYPASS_SWREG_MASK) +#define PMU_BYPASS_DREG_MSB 1 +#define PMU_BYPASS_DREG_LSB 1 +#define PMU_BYPASS_DREG_MASK 0x00000002 +#define PMU_BYPASS_DREG_GET(x) (((x) & PMU_BYPASS_DREG_MASK) >> PMU_BYPASS_DREG_LSB) +#define PMU_BYPASS_DREG_SET(x) (((x) << PMU_BYPASS_DREG_LSB) & PMU_BYPASS_DREG_MASK) +#define PMU_BYPASS_PAREG_MSB 0 +#define PMU_BYPASS_PAREG_LSB 0 +#define PMU_BYPASS_PAREG_MASK 0x00000001 +#define PMU_BYPASS_PAREG_GET(x) (((x) & PMU_BYPASS_PAREG_MASK) >> PMU_BYPASS_PAREG_LSB) +#define PMU_BYPASS_PAREG_SET(x) (((x) << PMU_BYPASS_PAREG_LSB) & PMU_BYPASS_PAREG_MASK) + +#define MAC_PCU_TSF2_L32_ADDRESS 0x000002cc +#define MAC_PCU_TSF2_L32_OFFSET 0x000002cc +#define MAC_PCU_TSF2_L32_VALUE_MSB 31 +#define MAC_PCU_TSF2_L32_VALUE_LSB 0 +#define MAC_PCU_TSF2_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF2_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_L32_VALUE_MASK) >> MAC_PCU_TSF2_L32_VALUE_LSB) +#define MAC_PCU_TSF2_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_L32_VALUE_LSB) & MAC_PCU_TSF2_L32_VALUE_MASK) + +#define MAC_PCU_TSF2_U32_ADDRESS 0x000002d0 +#define MAC_PCU_TSF2_U32_OFFSET 0x000002d0 +#define MAC_PCU_TSF2_U32_VALUE_MSB 31 +#define MAC_PCU_TSF2_U32_VALUE_LSB 0 +#define MAC_PCU_TSF2_U32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF2_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_U32_VALUE_MASK) >> MAC_PCU_TSF2_U32_VALUE_LSB) +#define MAC_PCU_TSF2_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_U32_VALUE_LSB) & MAC_PCU_TSF2_U32_VALUE_MASK) + +#define MAC_PCU_GENERIC_TIMERS_MODE3_ADDRESS 0x000002d4 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OFFSET 0x000002d4 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MSB 27 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB 24 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK 0x0f000000 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB) +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB) & MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK) +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MSB 19 +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB 0 +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK 0x000fffff +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB) +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB) & MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK) + +#define MAC_PCU_DIRECT_CONNECT_ADDRESS 0x000002d8 +#define MAC_PCU_DIRECT_CONNECT_OFFSET 0x000002d8 +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MSB 2 +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB 2 +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK 0x00000004 +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK) >> MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB) +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB) & MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK) +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MSB 1 +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB 1 +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK 0x00000002 +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK) >> MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB) +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB) & MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK) +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MSB 0 +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB 0 +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK 0x00000001 +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK) >> MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB) +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB) & MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK) + +#define THERM_CTRL1_ADDRESS 0x000002dc +#define THERM_CTRL1_OFFSET 0x000002dc +#define THERM_CTRL1_BYPASS_MSB 16 +#define THERM_CTRL1_BYPASS_LSB 16 +#define THERM_CTRL1_BYPASS_MASK 0x00010000 +#define THERM_CTRL1_BYPASS_GET(x) (((x) & THERM_CTRL1_BYPASS_MASK) >> THERM_CTRL1_BYPASS_LSB) +#define THERM_CTRL1_BYPASS_SET(x) (((x) << THERM_CTRL1_BYPASS_LSB) & THERM_CTRL1_BYPASS_MASK) +#define THERM_CTRL1_WIDTH_ARBITOR_MSB 15 +#define THERM_CTRL1_WIDTH_ARBITOR_LSB 12 +#define THERM_CTRL1_WIDTH_ARBITOR_MASK 0x0000f000 +#define THERM_CTRL1_WIDTH_ARBITOR_GET(x) (((x) & THERM_CTRL1_WIDTH_ARBITOR_MASK) >> THERM_CTRL1_WIDTH_ARBITOR_LSB) +#define THERM_CTRL1_WIDTH_ARBITOR_SET(x) (((x) << THERM_CTRL1_WIDTH_ARBITOR_LSB) & THERM_CTRL1_WIDTH_ARBITOR_MASK) +#define THERM_CTRL1_WIDTH_MSB 11 +#define THERM_CTRL1_WIDTH_LSB 5 +#define THERM_CTRL1_WIDTH_MASK 0x00000fe0 +#define THERM_CTRL1_WIDTH_GET(x) (((x) & THERM_CTRL1_WIDTH_MASK) >> THERM_CTRL1_WIDTH_LSB) +#define THERM_CTRL1_WIDTH_SET(x) (((x) << THERM_CTRL1_WIDTH_LSB) & THERM_CTRL1_WIDTH_MASK) +#define THERM_CTRL1_TYPE_MSB 4 +#define THERM_CTRL1_TYPE_LSB 3 +#define THERM_CTRL1_TYPE_MASK 0x00000018 +#define THERM_CTRL1_TYPE_GET(x) (((x) & THERM_CTRL1_TYPE_MASK) >> THERM_CTRL1_TYPE_LSB) +#define THERM_CTRL1_TYPE_SET(x) (((x) << THERM_CTRL1_TYPE_LSB) & THERM_CTRL1_TYPE_MASK) +#define THERM_CTRL1_MEASURE_MSB 2 +#define THERM_CTRL1_MEASURE_LSB 2 +#define THERM_CTRL1_MEASURE_MASK 0x00000004 +#define THERM_CTRL1_MEASURE_GET(x) (((x) & THERM_CTRL1_MEASURE_MASK) >> THERM_CTRL1_MEASURE_LSB) +#define THERM_CTRL1_MEASURE_SET(x) (((x) << THERM_CTRL1_MEASURE_LSB) & THERM_CTRL1_MEASURE_MASK) +#define THERM_CTRL1_INT_EN_MSB 1 +#define THERM_CTRL1_INT_EN_LSB 1 +#define THERM_CTRL1_INT_EN_MASK 0x00000002 +#define THERM_CTRL1_INT_EN_GET(x) (((x) & THERM_CTRL1_INT_EN_MASK) >> THERM_CTRL1_INT_EN_LSB) +#define THERM_CTRL1_INT_EN_SET(x) (((x) << THERM_CTRL1_INT_EN_LSB) & THERM_CTRL1_INT_EN_MASK) +#define THERM_CTRL1_INT_STATUS_MSB 0 +#define THERM_CTRL1_INT_STATUS_LSB 0 +#define THERM_CTRL1_INT_STATUS_MASK 0x00000001 +#define THERM_CTRL1_INT_STATUS_GET(x) (((x) & THERM_CTRL1_INT_STATUS_MASK) >> THERM_CTRL1_INT_STATUS_LSB) +#define THERM_CTRL1_INT_STATUS_SET(x) (((x) << THERM_CTRL1_INT_STATUS_LSB) & THERM_CTRL1_INT_STATUS_MASK) + +#define THERM_CTRL2_ADDRESS 0x000002e0 +#define THERM_CTRL2_OFFSET 0x000002e0 +#define THERM_CTRL2_ADC_OFF_MSB 25 +#define THERM_CTRL2_ADC_OFF_LSB 25 +#define THERM_CTRL2_ADC_OFF_MASK 0x02000000 +#define THERM_CTRL2_ADC_OFF_GET(x) (((x) & THERM_CTRL2_ADC_OFF_MASK) >> THERM_CTRL2_ADC_OFF_LSB) +#define THERM_CTRL2_ADC_OFF_SET(x) (((x) << THERM_CTRL2_ADC_OFF_LSB) & THERM_CTRL2_ADC_OFF_MASK) +#define THERM_CTRL2_ADC_ON_MSB 24 +#define THERM_CTRL2_ADC_ON_LSB 24 +#define THERM_CTRL2_ADC_ON_MASK 0x01000000 +#define THERM_CTRL2_ADC_ON_GET(x) (((x) & THERM_CTRL2_ADC_ON_MASK) >> THERM_CTRL2_ADC_ON_LSB) +#define THERM_CTRL2_ADC_ON_SET(x) (((x) << THERM_CTRL2_ADC_ON_LSB) & THERM_CTRL2_ADC_ON_MASK) +#define THERM_CTRL2_SAMPLE_MSB 23 +#define THERM_CTRL2_SAMPLE_LSB 16 +#define THERM_CTRL2_SAMPLE_MASK 0x00ff0000 +#define THERM_CTRL2_SAMPLE_GET(x) (((x) & THERM_CTRL2_SAMPLE_MASK) >> THERM_CTRL2_SAMPLE_LSB) +#define THERM_CTRL2_SAMPLE_SET(x) (((x) << THERM_CTRL2_SAMPLE_LSB) & THERM_CTRL2_SAMPLE_MASK) +#define THERM_CTRL2_HIGH_MSB 15 +#define THERM_CTRL2_HIGH_LSB 8 +#define THERM_CTRL2_HIGH_MASK 0x0000ff00 +#define THERM_CTRL2_HIGH_GET(x) (((x) & THERM_CTRL2_HIGH_MASK) >> THERM_CTRL2_HIGH_LSB) +#define THERM_CTRL2_HIGH_SET(x) (((x) << THERM_CTRL2_HIGH_LSB) & THERM_CTRL2_HIGH_MASK) +#define THERM_CTRL2_LOW_MSB 7 +#define THERM_CTRL2_LOW_LSB 0 +#define THERM_CTRL2_LOW_MASK 0x000000ff +#define THERM_CTRL2_LOW_GET(x) (((x) & THERM_CTRL2_LOW_MASK) >> THERM_CTRL2_LOW_LSB) +#define THERM_CTRL2_LOW_SET(x) (((x) << THERM_CTRL2_LOW_LSB) & THERM_CTRL2_LOW_MASK) + +#define THERM_CTRL3_ADDRESS 0x000002e4 +#define THERM_CTRL3_OFFSET 0x000002e4 +#define THERM_CTRL3_ADC_GAIN_MSB 16 +#define THERM_CTRL3_ADC_GAIN_LSB 8 +#define THERM_CTRL3_ADC_GAIN_MASK 0x0001ff00 +#define THERM_CTRL3_ADC_GAIN_GET(x) (((x) & THERM_CTRL3_ADC_GAIN_MASK) >> THERM_CTRL3_ADC_GAIN_LSB) +#define THERM_CTRL3_ADC_GAIN_SET(x) (((x) << THERM_CTRL3_ADC_GAIN_LSB) & THERM_CTRL3_ADC_GAIN_MASK) +#define THERM_CTRL3_ADC_OFFSET_MSB 7 +#define THERM_CTRL3_ADC_OFFSET_LSB 0 +#define THERM_CTRL3_ADC_OFFSET_MASK 0x000000ff +#define THERM_CTRL3_ADC_OFFSET_GET(x) (((x) & THERM_CTRL3_ADC_OFFSET_MASK) >> THERM_CTRL3_ADC_OFFSET_LSB) +#define THERM_CTRL3_ADC_OFFSET_SET(x) (((x) << THERM_CTRL3_ADC_OFFSET_LSB) & THERM_CTRL3_ADC_OFFSET_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct rtc_wlan_reg_reg_s { + volatile unsigned int wlan_reset_control; + volatile unsigned int wlan_xtal_control; + volatile unsigned int wlan_tcxo_detect; + volatile unsigned int wlan_xtal_test; + volatile unsigned int wlan_quadrature; + volatile unsigned int wlan_pll_control; + volatile unsigned int wlan_pll_settle; + volatile unsigned int wlan_xtal_settle; + volatile unsigned int wlan_cpu_clock; + volatile unsigned int wlan_clock_out; + volatile unsigned int wlan_clock_control; + volatile unsigned int wlan_bias_override; + volatile unsigned int wlan_wdt_control; + volatile unsigned int wlan_wdt_status; + volatile unsigned int wlan_wdt; + volatile unsigned int wlan_wdt_count; + volatile unsigned int wlan_wdt_reset; + volatile unsigned int wlan_int_status; + volatile unsigned int wlan_lf_timer0; + volatile unsigned int wlan_lf_timer_count0; + volatile unsigned int wlan_lf_timer_control0; + volatile unsigned int wlan_lf_timer_status0; + volatile unsigned int wlan_lf_timer1; + volatile unsigned int wlan_lf_timer_count1; + volatile unsigned int wlan_lf_timer_control1; + volatile unsigned int wlan_lf_timer_status1; + volatile unsigned int wlan_lf_timer2; + volatile unsigned int wlan_lf_timer_count2; + volatile unsigned int wlan_lf_timer_control2; + volatile unsigned int wlan_lf_timer_status2; + volatile unsigned int wlan_lf_timer3; + volatile unsigned int wlan_lf_timer_count3; + volatile unsigned int wlan_lf_timer_control3; + volatile unsigned int wlan_lf_timer_status3; + volatile unsigned int wlan_hf_timer; + volatile unsigned int wlan_hf_timer_count; + volatile unsigned int wlan_hf_lf_count; + volatile unsigned int wlan_hf_timer_control; + volatile unsigned int wlan_hf_timer_status; + volatile unsigned int wlan_rtc_control; + volatile unsigned int wlan_rtc_time; + volatile unsigned int wlan_rtc_date; + volatile unsigned int wlan_rtc_set_time; + volatile unsigned int wlan_rtc_set_date; + volatile unsigned int wlan_rtc_set_alarm; + volatile unsigned int wlan_rtc_config; + volatile unsigned int wlan_rtc_alarm_status; + volatile unsigned int wlan_uart_wakeup; + volatile unsigned int wlan_reset_cause; + volatile unsigned int wlan_system_sleep; + volatile unsigned int wlan_sdio_wrapper; + volatile unsigned int wlan_mac_sleep_control; + volatile unsigned int wlan_keep_awake; + volatile unsigned int wlan_lpo_cal_time; + volatile unsigned int wlan_lpo_init_dividend_int; + volatile unsigned int wlan_lpo_init_dividend_fraction; + volatile unsigned int wlan_lpo_cal; + volatile unsigned int wlan_lpo_cal_test_control; + volatile unsigned int wlan_lpo_cal_test_status; + volatile unsigned int wlan_chip_id; + volatile unsigned int wlan_derived_rtc_clk; + volatile unsigned int mac_pcu_slp32_mode; + volatile unsigned int mac_pcu_slp32_wake; + volatile unsigned int mac_pcu_slp32_inc; + volatile unsigned int mac_pcu_slp_mib1; + volatile unsigned int mac_pcu_slp_mib2; + volatile unsigned int mac_pcu_slp_mib3; + volatile unsigned int wlan_power_reg; + volatile unsigned int wlan_core_clk_ctrl; + volatile unsigned int wlan_gpio_wakeup_control; + volatile unsigned int ht; + volatile unsigned int mac_pcu_tsf_l32; + volatile unsigned int mac_pcu_tsf_u32; + volatile unsigned int mac_pcu_wbtimer; + unsigned char pad0[24]; /* pad to 0x140 */ + volatile unsigned int mac_pcu_generic_timers[16]; + volatile unsigned int mac_pcu_generic_timers_mode; + unsigned char pad1[60]; /* pad to 0x1c0 */ + volatile unsigned int mac_pcu_generic_timers2[16]; + volatile unsigned int mac_pcu_generic_timers_mode2; + volatile unsigned int mac_pcu_slp1; + volatile unsigned int mac_pcu_slp2; + volatile unsigned int mac_pcu_reset_tsf; + volatile unsigned int mac_pcu_tsf_add_pll; + volatile unsigned int sleep_retention; + volatile unsigned int btcoexctrl; + volatile unsigned int wbsync_priority1; + volatile unsigned int wbsync_priority2; + volatile unsigned int wbsync_priority3; + volatile unsigned int btcoex0; + volatile unsigned int btcoex1; + volatile unsigned int btcoex2; + volatile unsigned int btcoex3; + volatile unsigned int btcoex4; + volatile unsigned int btcoex5; + volatile unsigned int btcoex6; + volatile unsigned int lock; + volatile unsigned int nolock_priority; + volatile unsigned int wbsync; + volatile unsigned int wbsync1; + volatile unsigned int wbsync2; + volatile unsigned int wbsync3; + volatile unsigned int wb_timer_target; + volatile unsigned int wb_timer_slop; + volatile unsigned int btcoex_int_en; + volatile unsigned int btcoex_int_stat; + volatile unsigned int btpriority_int_en; + volatile unsigned int btpriority_int_stat; + volatile unsigned int btpriority_stomp_int_en; + volatile unsigned int btpriority_stomp_int_stat; + volatile unsigned int mac_pcu_bmiss_timeout; + volatile unsigned int mac_pcu_cab_awake; + volatile unsigned int lp_perf_counter; + volatile unsigned int lp_perf_light_sleep; + volatile unsigned int lp_perf_deep_sleep; + volatile unsigned int lp_perf_on; + volatile unsigned int st_64_bit; + volatile unsigned int message_wr; + volatile unsigned int message_wr_p; + volatile unsigned int message_rd; + volatile unsigned int message_rd_p; + volatile unsigned int chip_mode; + volatile unsigned int clk_req_fall_edge; + volatile unsigned int otp; + volatile unsigned int otp_status; + volatile unsigned int pmu; + unsigned char pad2[4]; /* pad to 0x2c0 */ + volatile unsigned int pmu_config[2]; + volatile unsigned int pmu_bypass; + volatile unsigned int mac_pcu_tsf2_l32; + volatile unsigned int mac_pcu_tsf2_u32; + volatile unsigned int mac_pcu_generic_timers_mode3; + volatile unsigned int mac_pcu_direct_connect; + volatile unsigned int therm_ctrl1; + volatile unsigned int therm_ctrl2; + volatile unsigned int therm_ctrl3; +} rtc_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _RTC_WLAN_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/si_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/si_reg.h new file mode 100644 index 000000000000..2cd2e3cadbbc --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/si_reg.h @@ -0,0 +1,209 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _SI_REG_REG_H_ +#define _SI_REG_REG_H_ + +#define SI_CONFIG_ADDRESS 0x00000000 +#define SI_CONFIG_OFFSET 0x00000000 +#define SI_CONFIG_ERR_INT_MSB 19 +#define SI_CONFIG_ERR_INT_LSB 19 +#define SI_CONFIG_ERR_INT_MASK 0x00080000 +#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB) +#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK) +#define SI_CONFIG_BIDIR_OD_DATA_MSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_LSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 +#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB) +#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK) +#define SI_CONFIG_I2C_MSB 16 +#define SI_CONFIG_I2C_LSB 16 +#define SI_CONFIG_I2C_MASK 0x00010000 +#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB) +#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) +#define SI_CONFIG_POS_SAMPLE_MSB 7 +#define SI_CONFIG_POS_SAMPLE_LSB 7 +#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 +#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB) +#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK) +#define SI_CONFIG_POS_DRIVE_MSB 6 +#define SI_CONFIG_POS_DRIVE_LSB 6 +#define SI_CONFIG_POS_DRIVE_MASK 0x00000040 +#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB) +#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK) +#define SI_CONFIG_INACTIVE_DATA_MSB 5 +#define SI_CONFIG_INACTIVE_DATA_LSB 5 +#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 +#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB) +#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK) +#define SI_CONFIG_INACTIVE_CLK_MSB 4 +#define SI_CONFIG_INACTIVE_CLK_LSB 4 +#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 +#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB) +#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK) +#define SI_CONFIG_DIVIDER_MSB 3 +#define SI_CONFIG_DIVIDER_LSB 0 +#define SI_CONFIG_DIVIDER_MASK 0x0000000f +#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB) +#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) + +#define SI_CS_ADDRESS 0x00000004 +#define SI_CS_OFFSET 0x00000004 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) +#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) +#define SI_CS_DONE_ERR_MSB 10 +#define SI_CS_DONE_ERR_LSB 10 +#define SI_CS_DONE_ERR_MASK 0x00000400 +#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB) +#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK) +#define SI_CS_DONE_INT_MSB 9 +#define SI_CS_DONE_INT_LSB 9 +#define SI_CS_DONE_INT_MASK 0x00000200 +#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB) +#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK) +#define SI_CS_START_MSB 8 +#define SI_CS_START_LSB 8 +#define SI_CS_START_MASK 0x00000100 +#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB) +#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) +#define SI_CS_RX_CNT_MSB 7 +#define SI_CS_RX_CNT_LSB 4 +#define SI_CS_RX_CNT_MASK 0x000000f0 +#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB) +#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) +#define SI_CS_TX_CNT_MSB 3 +#define SI_CS_TX_CNT_LSB 0 +#define SI_CS_TX_CNT_MASK 0x0000000f +#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB) +#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) + +#define SI_TX_DATA0_ADDRESS 0x00000008 +#define SI_TX_DATA0_OFFSET 0x00000008 +#define SI_TX_DATA0_DATA3_MSB 31 +#define SI_TX_DATA0_DATA3_LSB 24 +#define SI_TX_DATA0_DATA3_MASK 0xff000000 +#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB) +#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK) +#define SI_TX_DATA0_DATA2_MSB 23 +#define SI_TX_DATA0_DATA2_LSB 16 +#define SI_TX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB) +#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK) +#define SI_TX_DATA0_DATA1_MSB 15 +#define SI_TX_DATA0_DATA1_LSB 8 +#define SI_TX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB) +#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK) +#define SI_TX_DATA0_DATA0_MSB 7 +#define SI_TX_DATA0_DATA0_LSB 0 +#define SI_TX_DATA0_DATA0_MASK 0x000000ff +#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB) +#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK) + +#define SI_TX_DATA1_ADDRESS 0x0000000c +#define SI_TX_DATA1_OFFSET 0x0000000c +#define SI_TX_DATA1_DATA7_MSB 31 +#define SI_TX_DATA1_DATA7_LSB 24 +#define SI_TX_DATA1_DATA7_MASK 0xff000000 +#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB) +#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK) +#define SI_TX_DATA1_DATA6_MSB 23 +#define SI_TX_DATA1_DATA6_LSB 16 +#define SI_TX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB) +#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK) +#define SI_TX_DATA1_DATA5_MSB 15 +#define SI_TX_DATA1_DATA5_LSB 8 +#define SI_TX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB) +#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK) +#define SI_TX_DATA1_DATA4_MSB 7 +#define SI_TX_DATA1_DATA4_LSB 0 +#define SI_TX_DATA1_DATA4_MASK 0x000000ff +#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB) +#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK) + +#define SI_RX_DATA0_ADDRESS 0x00000010 +#define SI_RX_DATA0_OFFSET 0x00000010 +#define SI_RX_DATA0_DATA3_MSB 31 +#define SI_RX_DATA0_DATA3_LSB 24 +#define SI_RX_DATA0_DATA3_MASK 0xff000000 +#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB) +#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK) +#define SI_RX_DATA0_DATA2_MSB 23 +#define SI_RX_DATA0_DATA2_LSB 16 +#define SI_RX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB) +#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK) +#define SI_RX_DATA0_DATA1_MSB 15 +#define SI_RX_DATA0_DATA1_LSB 8 +#define SI_RX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB) +#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK) +#define SI_RX_DATA0_DATA0_MSB 7 +#define SI_RX_DATA0_DATA0_LSB 0 +#define SI_RX_DATA0_DATA0_MASK 0x000000ff +#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB) +#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK) + +#define SI_RX_DATA1_ADDRESS 0x00000014 +#define SI_RX_DATA1_OFFSET 0x00000014 +#define SI_RX_DATA1_DATA7_MSB 31 +#define SI_RX_DATA1_DATA7_LSB 24 +#define SI_RX_DATA1_DATA7_MASK 0xff000000 +#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB) +#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK) +#define SI_RX_DATA1_DATA6_MSB 23 +#define SI_RX_DATA1_DATA6_LSB 16 +#define SI_RX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB) +#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK) +#define SI_RX_DATA1_DATA5_MSB 15 +#define SI_RX_DATA1_DATA5_LSB 8 +#define SI_RX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB) +#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK) +#define SI_RX_DATA1_DATA4_MSB 7 +#define SI_RX_DATA1_DATA4_LSB 0 +#define SI_RX_DATA1_DATA4_MASK 0x000000ff +#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB) +#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct si_reg_reg_s { + volatile unsigned int si_config; + volatile unsigned int si_cs; + volatile unsigned int si_tx_data0; + volatile unsigned int si_tx_data1; + volatile unsigned int si_rx_data0; + volatile unsigned int si_rx_data1; +} si_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _SI_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/uart_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/uart_reg.h new file mode 100644 index 000000000000..a8eccaf6d745 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/uart_reg.h @@ -0,0 +1,260 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _UART_REG_REG_H_ +#define _UART_REG_REG_H_ + +#define UART_DATA_ADDRESS 0x00000000 +#define UART_DATA_OFFSET 0x00000000 +#define UART_DATA_TX_CSR_MSB 9 +#define UART_DATA_TX_CSR_LSB 9 +#define UART_DATA_TX_CSR_MASK 0x00000200 +#define UART_DATA_TX_CSR_GET(x) (((x) & UART_DATA_TX_CSR_MASK) >> UART_DATA_TX_CSR_LSB) +#define UART_DATA_TX_CSR_SET(x) (((x) << UART_DATA_TX_CSR_LSB) & UART_DATA_TX_CSR_MASK) +#define UART_DATA_RX_CSR_MSB 8 +#define UART_DATA_RX_CSR_LSB 8 +#define UART_DATA_RX_CSR_MASK 0x00000100 +#define UART_DATA_RX_CSR_GET(x) (((x) & UART_DATA_RX_CSR_MASK) >> UART_DATA_RX_CSR_LSB) +#define UART_DATA_RX_CSR_SET(x) (((x) << UART_DATA_RX_CSR_LSB) & UART_DATA_RX_CSR_MASK) +#define UART_DATA_TXRX_DATA_MSB 7 +#define UART_DATA_TXRX_DATA_LSB 0 +#define UART_DATA_TXRX_DATA_MASK 0x000000ff +#define UART_DATA_TXRX_DATA_GET(x) (((x) & UART_DATA_TXRX_DATA_MASK) >> UART_DATA_TXRX_DATA_LSB) +#define UART_DATA_TXRX_DATA_SET(x) (((x) << UART_DATA_TXRX_DATA_LSB) & UART_DATA_TXRX_DATA_MASK) + +#define UART_CONTROL_ADDRESS 0x00000004 +#define UART_CONTROL_OFFSET 0x00000004 +#define UART_CONTROL_RX_BUSY_MSB 15 +#define UART_CONTROL_RX_BUSY_LSB 15 +#define UART_CONTROL_RX_BUSY_MASK 0x00008000 +#define UART_CONTROL_RX_BUSY_GET(x) (((x) & UART_CONTROL_RX_BUSY_MASK) >> UART_CONTROL_RX_BUSY_LSB) +#define UART_CONTROL_RX_BUSY_SET(x) (((x) << UART_CONTROL_RX_BUSY_LSB) & UART_CONTROL_RX_BUSY_MASK) +#define UART_CONTROL_TX_BUSY_MSB 14 +#define UART_CONTROL_TX_BUSY_LSB 14 +#define UART_CONTROL_TX_BUSY_MASK 0x00004000 +#define UART_CONTROL_TX_BUSY_GET(x) (((x) & UART_CONTROL_TX_BUSY_MASK) >> UART_CONTROL_TX_BUSY_LSB) +#define UART_CONTROL_TX_BUSY_SET(x) (((x) << UART_CONTROL_TX_BUSY_LSB) & UART_CONTROL_TX_BUSY_MASK) +#define UART_CONTROL_HOST_INT_ENABLE_MSB 13 +#define UART_CONTROL_HOST_INT_ENABLE_LSB 13 +#define UART_CONTROL_HOST_INT_ENABLE_MASK 0x00002000 +#define UART_CONTROL_HOST_INT_ENABLE_GET(x) (((x) & UART_CONTROL_HOST_INT_ENABLE_MASK) >> UART_CONTROL_HOST_INT_ENABLE_LSB) +#define UART_CONTROL_HOST_INT_ENABLE_SET(x) (((x) << UART_CONTROL_HOST_INT_ENABLE_LSB) & UART_CONTROL_HOST_INT_ENABLE_MASK) +#define UART_CONTROL_HOST_INT_MSB 12 +#define UART_CONTROL_HOST_INT_LSB 12 +#define UART_CONTROL_HOST_INT_MASK 0x00001000 +#define UART_CONTROL_HOST_INT_GET(x) (((x) & UART_CONTROL_HOST_INT_MASK) >> UART_CONTROL_HOST_INT_LSB) +#define UART_CONTROL_HOST_INT_SET(x) (((x) << UART_CONTROL_HOST_INT_LSB) & UART_CONTROL_HOST_INT_MASK) +#define UART_CONTROL_TX_BREAK_MSB 11 +#define UART_CONTROL_TX_BREAK_LSB 11 +#define UART_CONTROL_TX_BREAK_MASK 0x00000800 +#define UART_CONTROL_TX_BREAK_GET(x) (((x) & UART_CONTROL_TX_BREAK_MASK) >> UART_CONTROL_TX_BREAK_LSB) +#define UART_CONTROL_TX_BREAK_SET(x) (((x) << UART_CONTROL_TX_BREAK_LSB) & UART_CONTROL_TX_BREAK_MASK) +#define UART_CONTROL_RX_BREAK_MSB 10 +#define UART_CONTROL_RX_BREAK_LSB 10 +#define UART_CONTROL_RX_BREAK_MASK 0x00000400 +#define UART_CONTROL_RX_BREAK_GET(x) (((x) & UART_CONTROL_RX_BREAK_MASK) >> UART_CONTROL_RX_BREAK_LSB) +#define UART_CONTROL_RX_BREAK_SET(x) (((x) << UART_CONTROL_RX_BREAK_LSB) & UART_CONTROL_RX_BREAK_MASK) +#define UART_CONTROL_SERIAL_TX_READY_MSB 9 +#define UART_CONTROL_SERIAL_TX_READY_LSB 9 +#define UART_CONTROL_SERIAL_TX_READY_MASK 0x00000200 +#define UART_CONTROL_SERIAL_TX_READY_GET(x) (((x) & UART_CONTROL_SERIAL_TX_READY_MASK) >> UART_CONTROL_SERIAL_TX_READY_LSB) +#define UART_CONTROL_SERIAL_TX_READY_SET(x) (((x) << UART_CONTROL_SERIAL_TX_READY_LSB) & UART_CONTROL_SERIAL_TX_READY_MASK) +#define UART_CONTROL_TX_READY_ORIDE_MSB 8 +#define UART_CONTROL_TX_READY_ORIDE_LSB 8 +#define UART_CONTROL_TX_READY_ORIDE_MASK 0x00000100 +#define UART_CONTROL_TX_READY_ORIDE_GET(x) (((x) & UART_CONTROL_TX_READY_ORIDE_MASK) >> UART_CONTROL_TX_READY_ORIDE_LSB) +#define UART_CONTROL_TX_READY_ORIDE_SET(x) (((x) << UART_CONTROL_TX_READY_ORIDE_LSB) & UART_CONTROL_TX_READY_ORIDE_MASK) +#define UART_CONTROL_RX_READY_ORIDE_MSB 7 +#define UART_CONTROL_RX_READY_ORIDE_LSB 7 +#define UART_CONTROL_RX_READY_ORIDE_MASK 0x00000080 +#define UART_CONTROL_RX_READY_ORIDE_GET(x) (((x) & UART_CONTROL_RX_READY_ORIDE_MASK) >> UART_CONTROL_RX_READY_ORIDE_LSB) +#define UART_CONTROL_RX_READY_ORIDE_SET(x) (((x) << UART_CONTROL_RX_READY_ORIDE_LSB) & UART_CONTROL_RX_READY_ORIDE_MASK) +#define UART_CONTROL_DMA_ENABLE_MSB 6 +#define UART_CONTROL_DMA_ENABLE_LSB 6 +#define UART_CONTROL_DMA_ENABLE_MASK 0x00000040 +#define UART_CONTROL_DMA_ENABLE_GET(x) (((x) & UART_CONTROL_DMA_ENABLE_MASK) >> UART_CONTROL_DMA_ENABLE_LSB) +#define UART_CONTROL_DMA_ENABLE_SET(x) (((x) << UART_CONTROL_DMA_ENABLE_LSB) & UART_CONTROL_DMA_ENABLE_MASK) +#define UART_CONTROL_FLOW_ENABLE_MSB 5 +#define UART_CONTROL_FLOW_ENABLE_LSB 5 +#define UART_CONTROL_FLOW_ENABLE_MASK 0x00000020 +#define UART_CONTROL_FLOW_ENABLE_GET(x) (((x) & UART_CONTROL_FLOW_ENABLE_MASK) >> UART_CONTROL_FLOW_ENABLE_LSB) +#define UART_CONTROL_FLOW_ENABLE_SET(x) (((x) << UART_CONTROL_FLOW_ENABLE_LSB) & UART_CONTROL_FLOW_ENABLE_MASK) +#define UART_CONTROL_FLOW_INVERT_MSB 4 +#define UART_CONTROL_FLOW_INVERT_LSB 4 +#define UART_CONTROL_FLOW_INVERT_MASK 0x00000010 +#define UART_CONTROL_FLOW_INVERT_GET(x) (((x) & UART_CONTROL_FLOW_INVERT_MASK) >> UART_CONTROL_FLOW_INVERT_LSB) +#define UART_CONTROL_FLOW_INVERT_SET(x) (((x) << UART_CONTROL_FLOW_INVERT_LSB) & UART_CONTROL_FLOW_INVERT_MASK) +#define UART_CONTROL_IFC_ENABLE_MSB 3 +#define UART_CONTROL_IFC_ENABLE_LSB 3 +#define UART_CONTROL_IFC_ENABLE_MASK 0x00000008 +#define UART_CONTROL_IFC_ENABLE_GET(x) (((x) & UART_CONTROL_IFC_ENABLE_MASK) >> UART_CONTROL_IFC_ENABLE_LSB) +#define UART_CONTROL_IFC_ENABLE_SET(x) (((x) << UART_CONTROL_IFC_ENABLE_LSB) & UART_CONTROL_IFC_ENABLE_MASK) +#define UART_CONTROL_IFC_DCE_MSB 2 +#define UART_CONTROL_IFC_DCE_LSB 2 +#define UART_CONTROL_IFC_DCE_MASK 0x00000004 +#define UART_CONTROL_IFC_DCE_GET(x) (((x) & UART_CONTROL_IFC_DCE_MASK) >> UART_CONTROL_IFC_DCE_LSB) +#define UART_CONTROL_IFC_DCE_SET(x) (((x) << UART_CONTROL_IFC_DCE_LSB) & UART_CONTROL_IFC_DCE_MASK) +#define UART_CONTROL_PARITY_ENABLE_MSB 1 +#define UART_CONTROL_PARITY_ENABLE_LSB 1 +#define UART_CONTROL_PARITY_ENABLE_MASK 0x00000002 +#define UART_CONTROL_PARITY_ENABLE_GET(x) (((x) & UART_CONTROL_PARITY_ENABLE_MASK) >> UART_CONTROL_PARITY_ENABLE_LSB) +#define UART_CONTROL_PARITY_ENABLE_SET(x) (((x) << UART_CONTROL_PARITY_ENABLE_LSB) & UART_CONTROL_PARITY_ENABLE_MASK) +#define UART_CONTROL_PARITY_EVEN_MSB 0 +#define UART_CONTROL_PARITY_EVEN_LSB 0 +#define UART_CONTROL_PARITY_EVEN_MASK 0x00000001 +#define UART_CONTROL_PARITY_EVEN_GET(x) (((x) & UART_CONTROL_PARITY_EVEN_MASK) >> UART_CONTROL_PARITY_EVEN_LSB) +#define UART_CONTROL_PARITY_EVEN_SET(x) (((x) << UART_CONTROL_PARITY_EVEN_LSB) & UART_CONTROL_PARITY_EVEN_MASK) + +#define UART_CLKDIV_ADDRESS 0x00000008 +#define UART_CLKDIV_OFFSET 0x00000008 +#define UART_CLKDIV_CLK_SCALE_MSB 23 +#define UART_CLKDIV_CLK_SCALE_LSB 16 +#define UART_CLKDIV_CLK_SCALE_MASK 0x00ff0000 +#define UART_CLKDIV_CLK_SCALE_GET(x) (((x) & UART_CLKDIV_CLK_SCALE_MASK) >> UART_CLKDIV_CLK_SCALE_LSB) +#define UART_CLKDIV_CLK_SCALE_SET(x) (((x) << UART_CLKDIV_CLK_SCALE_LSB) & UART_CLKDIV_CLK_SCALE_MASK) +#define UART_CLKDIV_CLK_STEP_MSB 15 +#define UART_CLKDIV_CLK_STEP_LSB 0 +#define UART_CLKDIV_CLK_STEP_MASK 0x0000ffff +#define UART_CLKDIV_CLK_STEP_GET(x) (((x) & UART_CLKDIV_CLK_STEP_MASK) >> UART_CLKDIV_CLK_STEP_LSB) +#define UART_CLKDIV_CLK_STEP_SET(x) (((x) << UART_CLKDIV_CLK_STEP_LSB) & UART_CLKDIV_CLK_STEP_MASK) + +#define UART_INT_ADDRESS 0x0000000c +#define UART_INT_OFFSET 0x0000000c +#define UART_INT_TX_EMPTY_INT_MSB 9 +#define UART_INT_TX_EMPTY_INT_LSB 9 +#define UART_INT_TX_EMPTY_INT_MASK 0x00000200 +#define UART_INT_TX_EMPTY_INT_GET(x) (((x) & UART_INT_TX_EMPTY_INT_MASK) >> UART_INT_TX_EMPTY_INT_LSB) +#define UART_INT_TX_EMPTY_INT_SET(x) (((x) << UART_INT_TX_EMPTY_INT_LSB) & UART_INT_TX_EMPTY_INT_MASK) +#define UART_INT_RX_FULL_INT_MSB 8 +#define UART_INT_RX_FULL_INT_LSB 8 +#define UART_INT_RX_FULL_INT_MASK 0x00000100 +#define UART_INT_RX_FULL_INT_GET(x) (((x) & UART_INT_RX_FULL_INT_MASK) >> UART_INT_RX_FULL_INT_LSB) +#define UART_INT_RX_FULL_INT_SET(x) (((x) << UART_INT_RX_FULL_INT_LSB) & UART_INT_RX_FULL_INT_MASK) +#define UART_INT_RX_BREAK_OFF_INT_MSB 7 +#define UART_INT_RX_BREAK_OFF_INT_LSB 7 +#define UART_INT_RX_BREAK_OFF_INT_MASK 0x00000080 +#define UART_INT_RX_BREAK_OFF_INT_GET(x) (((x) & UART_INT_RX_BREAK_OFF_INT_MASK) >> UART_INT_RX_BREAK_OFF_INT_LSB) +#define UART_INT_RX_BREAK_OFF_INT_SET(x) (((x) << UART_INT_RX_BREAK_OFF_INT_LSB) & UART_INT_RX_BREAK_OFF_INT_MASK) +#define UART_INT_RX_BREAK_ON_INT_MSB 6 +#define UART_INT_RX_BREAK_ON_INT_LSB 6 +#define UART_INT_RX_BREAK_ON_INT_MASK 0x00000040 +#define UART_INT_RX_BREAK_ON_INT_GET(x) (((x) & UART_INT_RX_BREAK_ON_INT_MASK) >> UART_INT_RX_BREAK_ON_INT_LSB) +#define UART_INT_RX_BREAK_ON_INT_SET(x) (((x) << UART_INT_RX_BREAK_ON_INT_LSB) & UART_INT_RX_BREAK_ON_INT_MASK) +#define UART_INT_RX_PARITY_ERR_INT_MSB 5 +#define UART_INT_RX_PARITY_ERR_INT_LSB 5 +#define UART_INT_RX_PARITY_ERR_INT_MASK 0x00000020 +#define UART_INT_RX_PARITY_ERR_INT_GET(x) (((x) & UART_INT_RX_PARITY_ERR_INT_MASK) >> UART_INT_RX_PARITY_ERR_INT_LSB) +#define UART_INT_RX_PARITY_ERR_INT_SET(x) (((x) << UART_INT_RX_PARITY_ERR_INT_LSB) & UART_INT_RX_PARITY_ERR_INT_MASK) +#define UART_INT_TX_OFLOW_ERR_INT_MSB 4 +#define UART_INT_TX_OFLOW_ERR_INT_LSB 4 +#define UART_INT_TX_OFLOW_ERR_INT_MASK 0x00000010 +#define UART_INT_TX_OFLOW_ERR_INT_GET(x) (((x) & UART_INT_TX_OFLOW_ERR_INT_MASK) >> UART_INT_TX_OFLOW_ERR_INT_LSB) +#define UART_INT_TX_OFLOW_ERR_INT_SET(x) (((x) << UART_INT_TX_OFLOW_ERR_INT_LSB) & UART_INT_TX_OFLOW_ERR_INT_MASK) +#define UART_INT_RX_OFLOW_ERR_INT_MSB 3 +#define UART_INT_RX_OFLOW_ERR_INT_LSB 3 +#define UART_INT_RX_OFLOW_ERR_INT_MASK 0x00000008 +#define UART_INT_RX_OFLOW_ERR_INT_GET(x) (((x) & UART_INT_RX_OFLOW_ERR_INT_MASK) >> UART_INT_RX_OFLOW_ERR_INT_LSB) +#define UART_INT_RX_OFLOW_ERR_INT_SET(x) (((x) << UART_INT_RX_OFLOW_ERR_INT_LSB) & UART_INT_RX_OFLOW_ERR_INT_MASK) +#define UART_INT_RX_FRAMING_ERR_INT_MSB 2 +#define UART_INT_RX_FRAMING_ERR_INT_LSB 2 +#define UART_INT_RX_FRAMING_ERR_INT_MASK 0x00000004 +#define UART_INT_RX_FRAMING_ERR_INT_GET(x) (((x) & UART_INT_RX_FRAMING_ERR_INT_MASK) >> UART_INT_RX_FRAMING_ERR_INT_LSB) +#define UART_INT_RX_FRAMING_ERR_INT_SET(x) (((x) << UART_INT_RX_FRAMING_ERR_INT_LSB) & UART_INT_RX_FRAMING_ERR_INT_MASK) +#define UART_INT_TX_READY_INT_MSB 1 +#define UART_INT_TX_READY_INT_LSB 1 +#define UART_INT_TX_READY_INT_MASK 0x00000002 +#define UART_INT_TX_READY_INT_GET(x) (((x) & UART_INT_TX_READY_INT_MASK) >> UART_INT_TX_READY_INT_LSB) +#define UART_INT_TX_READY_INT_SET(x) (((x) << UART_INT_TX_READY_INT_LSB) & UART_INT_TX_READY_INT_MASK) +#define UART_INT_RX_VALID_INT_MSB 0 +#define UART_INT_RX_VALID_INT_LSB 0 +#define UART_INT_RX_VALID_INT_MASK 0x00000001 +#define UART_INT_RX_VALID_INT_GET(x) (((x) & UART_INT_RX_VALID_INT_MASK) >> UART_INT_RX_VALID_INT_LSB) +#define UART_INT_RX_VALID_INT_SET(x) (((x) << UART_INT_RX_VALID_INT_LSB) & UART_INT_RX_VALID_INT_MASK) + +#define UART_INT_EN_ADDRESS 0x00000010 +#define UART_INT_EN_OFFSET 0x00000010 +#define UART_INT_EN_TX_EMPTY_INT_EN_MSB 9 +#define UART_INT_EN_TX_EMPTY_INT_EN_LSB 9 +#define UART_INT_EN_TX_EMPTY_INT_EN_MASK 0x00000200 +#define UART_INT_EN_TX_EMPTY_INT_EN_GET(x) (((x) & UART_INT_EN_TX_EMPTY_INT_EN_MASK) >> UART_INT_EN_TX_EMPTY_INT_EN_LSB) +#define UART_INT_EN_TX_EMPTY_INT_EN_SET(x) (((x) << UART_INT_EN_TX_EMPTY_INT_EN_LSB) & UART_INT_EN_TX_EMPTY_INT_EN_MASK) +#define UART_INT_EN_RX_FULL_INT_EN_MSB 8 +#define UART_INT_EN_RX_FULL_INT_EN_LSB 8 +#define UART_INT_EN_RX_FULL_INT_EN_MASK 0x00000100 +#define UART_INT_EN_RX_FULL_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FULL_INT_EN_MASK) >> UART_INT_EN_RX_FULL_INT_EN_LSB) +#define UART_INT_EN_RX_FULL_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FULL_INT_EN_LSB) & UART_INT_EN_RX_FULL_INT_EN_MASK) +#define UART_INT_EN_RX_BREAK_OFF_INT_EN_MSB 7 +#define UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB 7 +#define UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK 0x00000080 +#define UART_INT_EN_RX_BREAK_OFF_INT_EN_GET(x) (((x) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB) +#define UART_INT_EN_RX_BREAK_OFF_INT_EN_SET(x) (((x) << UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK) +#define UART_INT_EN_RX_BREAK_ON_INT_EN_MSB 6 +#define UART_INT_EN_RX_BREAK_ON_INT_EN_LSB 6 +#define UART_INT_EN_RX_BREAK_ON_INT_EN_MASK 0x00000040 +#define UART_INT_EN_RX_BREAK_ON_INT_EN_GET(x) (((x) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_ON_INT_EN_LSB) +#define UART_INT_EN_RX_BREAK_ON_INT_EN_SET(x) (((x) << UART_INT_EN_RX_BREAK_ON_INT_EN_LSB) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK) +#define UART_INT_EN_RX_PARITY_ERR_INT_EN_MSB 5 +#define UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB 5 +#define UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK 0x00000020 +#define UART_INT_EN_RX_PARITY_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK) >> UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB) +#define UART_INT_EN_RX_PARITY_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK) +#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MSB 4 +#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB 4 +#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK 0x00000010 +#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB) +#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK) +#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MSB 3 +#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB 3 +#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK 0x00000008 +#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB) +#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK) +#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MSB 2 +#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB 2 +#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK 0x00000004 +#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK) >> UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB) +#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK) +#define UART_INT_EN_TX_READY_INT_EN_MSB 1 +#define UART_INT_EN_TX_READY_INT_EN_LSB 1 +#define UART_INT_EN_TX_READY_INT_EN_MASK 0x00000002 +#define UART_INT_EN_TX_READY_INT_EN_GET(x) (((x) & UART_INT_EN_TX_READY_INT_EN_MASK) >> UART_INT_EN_TX_READY_INT_EN_LSB) +#define UART_INT_EN_TX_READY_INT_EN_SET(x) (((x) << UART_INT_EN_TX_READY_INT_EN_LSB) & UART_INT_EN_TX_READY_INT_EN_MASK) +#define UART_INT_EN_RX_VALID_INT_EN_MSB 0 +#define UART_INT_EN_RX_VALID_INT_EN_LSB 0 +#define UART_INT_EN_RX_VALID_INT_EN_MASK 0x00000001 +#define UART_INT_EN_RX_VALID_INT_EN_GET(x) (((x) & UART_INT_EN_RX_VALID_INT_EN_MASK) >> UART_INT_EN_RX_VALID_INT_EN_LSB) +#define UART_INT_EN_RX_VALID_INT_EN_SET(x) (((x) << UART_INT_EN_RX_VALID_INT_EN_LSB) & UART_INT_EN_RX_VALID_INT_EN_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct uart_reg_reg_s { + volatile unsigned int uart_data; + volatile unsigned int uart_control; + volatile unsigned int uart_clkdiv; + volatile unsigned int uart_int; + volatile unsigned int uart_int_en; +} uart_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _UART_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_reg.h new file mode 100644 index 000000000000..b233cbc513bc --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_reg.h @@ -0,0 +1,37 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "umbox_wlan_reg.h" + + +#ifndef BT_HEADERS + + + +#endif +#endif + + + diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_wlan_reg.h new file mode 100644 index 000000000000..4737a2805b2f --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_wlan_reg.h @@ -0,0 +1,322 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _UMBOX_WLAN_REG_REG_H_ +#define _UMBOX_WLAN_REG_REG_H_ + +#define UMBOX_FIFO_ADDRESS 0x00000000 +#define UMBOX_FIFO_OFFSET 0x00000000 +#define UMBOX_FIFO_DATA_MSB 8 +#define UMBOX_FIFO_DATA_LSB 0 +#define UMBOX_FIFO_DATA_MASK 0x000001ff +#define UMBOX_FIFO_DATA_GET(x) (((x) & UMBOX_FIFO_DATA_MASK) >> UMBOX_FIFO_DATA_LSB) +#define UMBOX_FIFO_DATA_SET(x) (((x) << UMBOX_FIFO_DATA_LSB) & UMBOX_FIFO_DATA_MASK) + +#define UMBOX_FIFO_STATUS_ADDRESS 0x00000008 +#define UMBOX_FIFO_STATUS_OFFSET 0x00000008 +#define UMBOX_FIFO_STATUS_TX_EMPTY_MSB 3 +#define UMBOX_FIFO_STATUS_TX_EMPTY_LSB 3 +#define UMBOX_FIFO_STATUS_TX_EMPTY_MASK 0x00000008 +#define UMBOX_FIFO_STATUS_TX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_TX_EMPTY_LSB) +#define UMBOX_FIFO_STATUS_TX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_EMPTY_LSB) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK) +#define UMBOX_FIFO_STATUS_TX_FULL_MSB 2 +#define UMBOX_FIFO_STATUS_TX_FULL_LSB 2 +#define UMBOX_FIFO_STATUS_TX_FULL_MASK 0x00000004 +#define UMBOX_FIFO_STATUS_TX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_FULL_MASK) >> UMBOX_FIFO_STATUS_TX_FULL_LSB) +#define UMBOX_FIFO_STATUS_TX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_FULL_LSB) & UMBOX_FIFO_STATUS_TX_FULL_MASK) +#define UMBOX_FIFO_STATUS_RX_EMPTY_MSB 1 +#define UMBOX_FIFO_STATUS_RX_EMPTY_LSB 1 +#define UMBOX_FIFO_STATUS_RX_EMPTY_MASK 0x00000002 +#define UMBOX_FIFO_STATUS_RX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_RX_EMPTY_LSB) +#define UMBOX_FIFO_STATUS_RX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_EMPTY_LSB) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK) +#define UMBOX_FIFO_STATUS_RX_FULL_MSB 0 +#define UMBOX_FIFO_STATUS_RX_FULL_LSB 0 +#define UMBOX_FIFO_STATUS_RX_FULL_MASK 0x00000001 +#define UMBOX_FIFO_STATUS_RX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_FULL_MASK) >> UMBOX_FIFO_STATUS_RX_FULL_LSB) +#define UMBOX_FIFO_STATUS_RX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_FULL_LSB) & UMBOX_FIFO_STATUS_RX_FULL_MASK) + +#define UMBOX_DMA_POLICY_ADDRESS 0x0000000c +#define UMBOX_DMA_POLICY_OFFSET 0x0000000c +#define UMBOX_DMA_POLICY_TX_QUANTUM_MSB 3 +#define UMBOX_DMA_POLICY_TX_QUANTUM_LSB 3 +#define UMBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008 +#define UMBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_TX_QUANTUM_LSB) +#define UMBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_TX_QUANTUM_LSB) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK) +#define UMBOX_DMA_POLICY_TX_ORDER_MSB 2 +#define UMBOX_DMA_POLICY_TX_ORDER_LSB 2 +#define UMBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004 +#define UMBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_TX_ORDER_MASK) >> UMBOX_DMA_POLICY_TX_ORDER_LSB) +#define UMBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_TX_ORDER_LSB) & UMBOX_DMA_POLICY_TX_ORDER_MASK) +#define UMBOX_DMA_POLICY_RX_QUANTUM_MSB 1 +#define UMBOX_DMA_POLICY_RX_QUANTUM_LSB 1 +#define UMBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002 +#define UMBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_RX_QUANTUM_LSB) +#define UMBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_RX_QUANTUM_LSB) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK) +#define UMBOX_DMA_POLICY_RX_ORDER_MSB 0 +#define UMBOX_DMA_POLICY_RX_ORDER_LSB 0 +#define UMBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001 +#define UMBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_RX_ORDER_MASK) >> UMBOX_DMA_POLICY_RX_ORDER_LSB) +#define UMBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_RX_ORDER_LSB) & UMBOX_DMA_POLICY_RX_ORDER_MASK) + +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000010 +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000010 +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define UMBOX0_DMA_RX_CONTROL_ADDRESS 0x00000014 +#define UMBOX0_DMA_RX_CONTROL_OFFSET 0x00000014 +#define UMBOX0_DMA_RX_CONTROL_RESUME_MSB 2 +#define UMBOX0_DMA_RX_CONTROL_RESUME_LSB 2 +#define UMBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define UMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_RX_CONTROL_RESUME_LSB) +#define UMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_RESUME_LSB) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK) +#define UMBOX0_DMA_RX_CONTROL_START_MSB 1 +#define UMBOX0_DMA_RX_CONTROL_START_LSB 1 +#define UMBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 +#define UMBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_START_MASK) >> UMBOX0_DMA_RX_CONTROL_START_LSB) +#define UMBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_START_LSB) & UMBOX0_DMA_RX_CONTROL_START_MASK) +#define UMBOX0_DMA_RX_CONTROL_STOP_MSB 0 +#define UMBOX0_DMA_RX_CONTROL_STOP_LSB 0 +#define UMBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define UMBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_STOP_MASK) >> UMBOX0_DMA_RX_CONTROL_STOP_LSB) +#define UMBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_STOP_LSB) & UMBOX0_DMA_RX_CONTROL_STOP_MASK) + +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000018 +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000018 +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define UMBOX0_DMA_TX_CONTROL_ADDRESS 0x0000001c +#define UMBOX0_DMA_TX_CONTROL_OFFSET 0x0000001c +#define UMBOX0_DMA_TX_CONTROL_RESUME_MSB 2 +#define UMBOX0_DMA_TX_CONTROL_RESUME_LSB 2 +#define UMBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define UMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_TX_CONTROL_RESUME_LSB) +#define UMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_RESUME_LSB) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK) +#define UMBOX0_DMA_TX_CONTROL_START_MSB 1 +#define UMBOX0_DMA_TX_CONTROL_START_LSB 1 +#define UMBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 +#define UMBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_START_MASK) >> UMBOX0_DMA_TX_CONTROL_START_LSB) +#define UMBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_START_LSB) & UMBOX0_DMA_TX_CONTROL_START_MASK) +#define UMBOX0_DMA_TX_CONTROL_STOP_MSB 0 +#define UMBOX0_DMA_TX_CONTROL_STOP_LSB 0 +#define UMBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define UMBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_STOP_MASK) >> UMBOX0_DMA_TX_CONTROL_STOP_LSB) +#define UMBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_STOP_LSB) & UMBOX0_DMA_TX_CONTROL_STOP_MASK) + +#define UMBOX_FIFO_TIMEOUT_ADDRESS 0x00000020 +#define UMBOX_FIFO_TIMEOUT_OFFSET 0x00000020 +#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MSB 8 +#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB 8 +#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000100 +#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK) >> UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB) +#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK) +#define UMBOX_FIFO_TIMEOUT_VALUE_MSB 7 +#define UMBOX_FIFO_TIMEOUT_VALUE_LSB 0 +#define UMBOX_FIFO_TIMEOUT_VALUE_MASK 0x000000ff +#define UMBOX_FIFO_TIMEOUT_VALUE_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_VALUE_MASK) >> UMBOX_FIFO_TIMEOUT_VALUE_LSB) +#define UMBOX_FIFO_TIMEOUT_VALUE_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_VALUE_LSB) & UMBOX_FIFO_TIMEOUT_VALUE_MASK) + +#define UMBOX_INT_STATUS_ADDRESS 0x00000024 +#define UMBOX_INT_STATUS_OFFSET 0x00000024 +#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MSB 9 +#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB 9 +#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK 0x00000200 +#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB) +#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK) +#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MSB 8 +#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB 8 +#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK 0x00000100 +#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB) +#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK) +#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 7 +#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 7 +#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000080 +#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) +#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) +#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 6 +#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 6 +#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000040 +#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) +#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) +#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 5 +#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 5 +#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000020 +#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) +#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) +#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MSB 4 +#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB 4 +#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK 0x00000010 +#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB) +#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK) +#define UMBOX_INT_STATUS_TX_OVERFLOW_MSB 3 +#define UMBOX_INT_STATUS_TX_OVERFLOW_LSB 3 +#define UMBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00000008 +#define UMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> UMBOX_INT_STATUS_TX_OVERFLOW_LSB) +#define UMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_TX_OVERFLOW_LSB) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK) +#define UMBOX_INT_STATUS_RX_UNDERFLOW_MSB 2 +#define UMBOX_INT_STATUS_RX_UNDERFLOW_LSB 2 +#define UMBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00000004 +#define UMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_RX_UNDERFLOW_LSB) +#define UMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK) +#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MSB 1 +#define UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB 1 +#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x00000002 +#define UMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) +#define UMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) +#define UMBOX_INT_STATUS_RX_NOT_FULL_MSB 0 +#define UMBOX_INT_STATUS_RX_NOT_FULL_LSB 0 +#define UMBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000001 +#define UMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> UMBOX_INT_STATUS_RX_NOT_FULL_LSB) +#define UMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_STATUS_RX_NOT_FULL_LSB) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK) + +#define UMBOX_INT_ENABLE_ADDRESS 0x00000028 +#define UMBOX_INT_ENABLE_OFFSET 0x00000028 +#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MSB 9 +#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB 9 +#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK 0x00000200 +#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB) +#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK) +#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MSB 8 +#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB 8 +#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK 0x00000100 +#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB) +#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK) +#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 7 +#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 7 +#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000080 +#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) +#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) +#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 6 +#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 6 +#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000040 +#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) +#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) +#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 5 +#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 5 +#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000020 +#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) +#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) +#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MSB 4 +#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB 4 +#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK 0x00000010 +#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB) +#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK) +#define UMBOX_INT_ENABLE_TX_OVERFLOW_MSB 3 +#define UMBOX_INT_ENABLE_TX_OVERFLOW_LSB 3 +#define UMBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00000008 +#define UMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_TX_OVERFLOW_LSB) +#define UMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK) +#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MSB 2 +#define UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB 2 +#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00000004 +#define UMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) +#define UMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) +#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 1 +#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 1 +#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x00000002 +#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) +#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) +#define UMBOX_INT_ENABLE_RX_NOT_FULL_MSB 0 +#define UMBOX_INT_ENABLE_RX_NOT_FULL_LSB 0 +#define UMBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000001 +#define UMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> UMBOX_INT_ENABLE_RX_NOT_FULL_LSB) +#define UMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK) + +#define UMBOX_DEBUG_ADDRESS 0x0000002c +#define UMBOX_DEBUG_OFFSET 0x0000002c +#define UMBOX_DEBUG_SEL_MSB 2 +#define UMBOX_DEBUG_SEL_LSB 0 +#define UMBOX_DEBUG_SEL_MASK 0x00000007 +#define UMBOX_DEBUG_SEL_GET(x) (((x) & UMBOX_DEBUG_SEL_MASK) >> UMBOX_DEBUG_SEL_LSB) +#define UMBOX_DEBUG_SEL_SET(x) (((x) << UMBOX_DEBUG_SEL_LSB) & UMBOX_DEBUG_SEL_MASK) + +#define UMBOX_FIFO_RESET_ADDRESS 0x00000030 +#define UMBOX_FIFO_RESET_OFFSET 0x00000030 +#define UMBOX_FIFO_RESET_INIT_MSB 0 +#define UMBOX_FIFO_RESET_INIT_LSB 0 +#define UMBOX_FIFO_RESET_INIT_MASK 0x00000001 +#define UMBOX_FIFO_RESET_INIT_GET(x) (((x) & UMBOX_FIFO_RESET_INIT_MASK) >> UMBOX_FIFO_RESET_INIT_LSB) +#define UMBOX_FIFO_RESET_INIT_SET(x) (((x) << UMBOX_FIFO_RESET_INIT_LSB) & UMBOX_FIFO_RESET_INIT_MASK) + +#define UMBOX_HCI_FRAMER_ADDRESS 0x00000034 +#define UMBOX_HCI_FRAMER_OFFSET 0x00000034 +#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MSB 6 +#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB 6 +#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK 0x00000040 +#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_GET(x) (((x) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK) >> UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB) +#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_SET(x) (((x) << UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK) +#define UMBOX_HCI_FRAMER_ENABLE_MSB 5 +#define UMBOX_HCI_FRAMER_ENABLE_LSB 5 +#define UMBOX_HCI_FRAMER_ENABLE_MASK 0x00000020 +#define UMBOX_HCI_FRAMER_ENABLE_GET(x) (((x) & UMBOX_HCI_FRAMER_ENABLE_MASK) >> UMBOX_HCI_FRAMER_ENABLE_LSB) +#define UMBOX_HCI_FRAMER_ENABLE_SET(x) (((x) << UMBOX_HCI_FRAMER_ENABLE_LSB) & UMBOX_HCI_FRAMER_ENABLE_MASK) +#define UMBOX_HCI_FRAMER_SYNC_ERROR_MSB 4 +#define UMBOX_HCI_FRAMER_SYNC_ERROR_LSB 4 +#define UMBOX_HCI_FRAMER_SYNC_ERROR_MASK 0x00000010 +#define UMBOX_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK) >> UMBOX_HCI_FRAMER_SYNC_ERROR_LSB) +#define UMBOX_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << UMBOX_HCI_FRAMER_SYNC_ERROR_LSB) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK) +#define UMBOX_HCI_FRAMER_UNDERFLOW_MSB 3 +#define UMBOX_HCI_FRAMER_UNDERFLOW_LSB 3 +#define UMBOX_HCI_FRAMER_UNDERFLOW_MASK 0x00000008 +#define UMBOX_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_HCI_FRAMER_UNDERFLOW_LSB) +#define UMBOX_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK) +#define UMBOX_HCI_FRAMER_OVERFLOW_MSB 2 +#define UMBOX_HCI_FRAMER_OVERFLOW_LSB 2 +#define UMBOX_HCI_FRAMER_OVERFLOW_MASK 0x00000004 +#define UMBOX_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_HCI_FRAMER_OVERFLOW_LSB) +#define UMBOX_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_HCI_FRAMER_OVERFLOW_MASK) +#define UMBOX_HCI_FRAMER_CONFIG_MODE_MSB 1 +#define UMBOX_HCI_FRAMER_CONFIG_MODE_LSB 0 +#define UMBOX_HCI_FRAMER_CONFIG_MODE_MASK 0x00000003 +#define UMBOX_HCI_FRAMER_CONFIG_MODE_GET(x) (((x) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK) >> UMBOX_HCI_FRAMER_CONFIG_MODE_LSB) +#define UMBOX_HCI_FRAMER_CONFIG_MODE_SET(x) (((x) << UMBOX_HCI_FRAMER_CONFIG_MODE_LSB) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct umbox_wlan_reg_reg_s { + volatile unsigned int umbox_fifo[2]; + volatile unsigned int umbox_fifo_status; + volatile unsigned int umbox_dma_policy; + volatile unsigned int umbox0_dma_rx_descriptor_base; + volatile unsigned int umbox0_dma_rx_control; + volatile unsigned int umbox0_dma_tx_descriptor_base; + volatile unsigned int umbox0_dma_tx_control; + volatile unsigned int umbox_fifo_timeout; + volatile unsigned int umbox_int_status; + volatile unsigned int umbox_int_enable; + volatile unsigned int umbox_debug; + volatile unsigned int umbox_fifo_reset; + volatile unsigned int umbox_hci_framer; +} umbox_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _UMBOX_WLAN_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_reg.h new file mode 100644 index 000000000000..c3d8088a5554 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_reg.h @@ -0,0 +1,167 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "vmc_wlan_reg.h" + + +#ifndef BT_HEADERS + +#define MC_BCAM_VALID_ADDRESS WLAN_MC_BCAM_VALID_ADDRESS +#define MC_BCAM_VALID_OFFSET WLAN_MC_BCAM_VALID_OFFSET +#define MC_BCAM_VALID_BIT_MSB WLAN_MC_BCAM_VALID_BIT_MSB +#define MC_BCAM_VALID_BIT_LSB WLAN_MC_BCAM_VALID_BIT_LSB +#define MC_BCAM_VALID_BIT_MASK WLAN_MC_BCAM_VALID_BIT_MASK +#define MC_BCAM_VALID_BIT_GET(x) WLAN_MC_BCAM_VALID_BIT_GET(x) +#define MC_BCAM_VALID_BIT_SET(x) WLAN_MC_BCAM_VALID_BIT_SET(x) +#define MC_BCAM_COMPARE_ADDRESS WLAN_MC_BCAM_COMPARE_ADDRESS +#define MC_BCAM_COMPARE_OFFSET WLAN_MC_BCAM_COMPARE_OFFSET +#define MC_BCAM_COMPARE_KEY_MSB WLAN_MC_BCAM_COMPARE_KEY_MSB +#define MC_BCAM_COMPARE_KEY_LSB WLAN_MC_BCAM_COMPARE_KEY_LSB +#define MC_BCAM_COMPARE_KEY_MASK WLAN_MC_BCAM_COMPARE_KEY_MASK +#define MC_BCAM_COMPARE_KEY_GET(x) WLAN_MC_BCAM_COMPARE_KEY_GET(x) +#define MC_BCAM_COMPARE_KEY_SET(x) WLAN_MC_BCAM_COMPARE_KEY_SET(x) +#define MC_BCAM_TARGET_ADDRESS WLAN_MC_BCAM_TARGET_ADDRESS +#define MC_BCAM_TARGET_OFFSET WLAN_MC_BCAM_TARGET_OFFSET +#define MC_BCAM_TARGET_INST_MSB WLAN_MC_BCAM_TARGET_INST_MSB +#define MC_BCAM_TARGET_INST_LSB WLAN_MC_BCAM_TARGET_INST_LSB +#define MC_BCAM_TARGET_INST_MASK WLAN_MC_BCAM_TARGET_INST_MASK +#define MC_BCAM_TARGET_INST_GET(x) WLAN_MC_BCAM_TARGET_INST_GET(x) +#define MC_BCAM_TARGET_INST_SET(x) WLAN_MC_BCAM_TARGET_INST_SET(x) +#define APB_ADDR_ERROR_CONTROL_ADDRESS WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS +#define APB_ADDR_ERROR_CONTROL_OFFSET WLAN_APB_ADDR_ERROR_CONTROL_OFFSET +#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB +#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB +#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK +#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) +#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) +#define APB_ADDR_ERROR_CONTROL_ENABLE_MSB WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB +#define APB_ADDR_ERROR_CONTROL_ENABLE_LSB WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB +#define APB_ADDR_ERROR_CONTROL_ENABLE_MASK WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK +#define APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) +#define APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) +#define APB_ADDR_ERROR_STATUS_ADDRESS WLAN_APB_ADDR_ERROR_STATUS_ADDRESS +#define APB_ADDR_ERROR_STATUS_OFFSET WLAN_APB_ADDR_ERROR_STATUS_OFFSET +#define APB_ADDR_ERROR_STATUS_WRITE_MSB WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB +#define APB_ADDR_ERROR_STATUS_WRITE_LSB WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB +#define APB_ADDR_ERROR_STATUS_WRITE_MASK WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK +#define APB_ADDR_ERROR_STATUS_WRITE_GET(x) WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x) +#define APB_ADDR_ERROR_STATUS_WRITE_SET(x) WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x) +#define APB_ADDR_ERROR_STATUS_ADDRESS_MSB WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB +#define APB_ADDR_ERROR_STATUS_ADDRESS_LSB WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB +#define APB_ADDR_ERROR_STATUS_ADDRESS_MASK WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK +#define APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) +#define APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) +#define AHB_ADDR_ERROR_CONTROL_ADDRESS WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS +#define AHB_ADDR_ERROR_CONTROL_OFFSET WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET +#define AHB_ADDR_ERROR_CONTROL_ENABLE_MSB WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB +#define AHB_ADDR_ERROR_CONTROL_ENABLE_LSB WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB +#define AHB_ADDR_ERROR_CONTROL_ENABLE_MASK WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK +#define AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) +#define AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) +#define AHB_ADDR_ERROR_STATUS_ADDRESS WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS +#define AHB_ADDR_ERROR_STATUS_OFFSET WLAN_AHB_ADDR_ERROR_STATUS_OFFSET +#define AHB_ADDR_ERROR_STATUS_MAC_MSB WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB +#define AHB_ADDR_ERROR_STATUS_MAC_LSB WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB +#define AHB_ADDR_ERROR_STATUS_MAC_MASK WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK +#define AHB_ADDR_ERROR_STATUS_MAC_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x) +#define AHB_ADDR_ERROR_STATUS_MAC_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x) +#define AHB_ADDR_ERROR_STATUS_MBOX_MSB WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB +#define AHB_ADDR_ERROR_STATUS_MBOX_LSB WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB +#define AHB_ADDR_ERROR_STATUS_MBOX_MASK WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK +#define AHB_ADDR_ERROR_STATUS_MBOX_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x) +#define AHB_ADDR_ERROR_STATUS_MBOX_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x) +#define AHB_ADDR_ERROR_STATUS_ADDRESS_MSB WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB +#define AHB_ADDR_ERROR_STATUS_ADDRESS_LSB WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB +#define AHB_ADDR_ERROR_STATUS_ADDRESS_MASK WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK +#define AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) +#define AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) +#define BCAM_CONFLICT_ERROR_ADDRESS WLAN_BCAM_CONFLICT_ERROR_ADDRESS +#define BCAM_CONFLICT_ERROR_OFFSET WLAN_BCAM_CONFLICT_ERROR_OFFSET +#define BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB +#define BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB +#define BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK +#define BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) +#define BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) +#define BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB +#define BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB +#define BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK +#define BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) +#define BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) +#define CPU_PERF_CNT_ADDRESS WLAN_CPU_PERF_CNT_ADDRESS +#define CPU_PERF_CNT_OFFSET WLAN_CPU_PERF_CNT_OFFSET +#define CPU_PERF_CNT_EN_MSB WLAN_CPU_PERF_CNT_EN_MSB +#define CPU_PERF_CNT_EN_LSB WLAN_CPU_PERF_CNT_EN_LSB +#define CPU_PERF_CNT_EN_MASK WLAN_CPU_PERF_CNT_EN_MASK +#define CPU_PERF_CNT_EN_GET(x) WLAN_CPU_PERF_CNT_EN_GET(x) +#define CPU_PERF_CNT_EN_SET(x) WLAN_CPU_PERF_CNT_EN_SET(x) +#define CPU_INST_FETCH_ADDRESS WLAN_CPU_INST_FETCH_ADDRESS +#define CPU_INST_FETCH_OFFSET WLAN_CPU_INST_FETCH_OFFSET +#define CPU_INST_FETCH_CNT_MSB WLAN_CPU_INST_FETCH_CNT_MSB +#define CPU_INST_FETCH_CNT_LSB WLAN_CPU_INST_FETCH_CNT_LSB +#define CPU_INST_FETCH_CNT_MASK WLAN_CPU_INST_FETCH_CNT_MASK +#define CPU_INST_FETCH_CNT_GET(x) WLAN_CPU_INST_FETCH_CNT_GET(x) +#define CPU_INST_FETCH_CNT_SET(x) WLAN_CPU_INST_FETCH_CNT_SET(x) +#define CPU_DATA_FETCH_ADDRESS WLAN_CPU_DATA_FETCH_ADDRESS +#define CPU_DATA_FETCH_OFFSET WLAN_CPU_DATA_FETCH_OFFSET +#define CPU_DATA_FETCH_CNT_MSB WLAN_CPU_DATA_FETCH_CNT_MSB +#define CPU_DATA_FETCH_CNT_LSB WLAN_CPU_DATA_FETCH_CNT_LSB +#define CPU_DATA_FETCH_CNT_MASK WLAN_CPU_DATA_FETCH_CNT_MASK +#define CPU_DATA_FETCH_CNT_GET(x) WLAN_CPU_DATA_FETCH_CNT_GET(x) +#define CPU_DATA_FETCH_CNT_SET(x) WLAN_CPU_DATA_FETCH_CNT_SET(x) +#define CPU_RAM1_CONFLICT_ADDRESS WLAN_CPU_RAM1_CONFLICT_ADDRESS +#define CPU_RAM1_CONFLICT_OFFSET WLAN_CPU_RAM1_CONFLICT_OFFSET +#define CPU_RAM1_CONFLICT_CNT_MSB WLAN_CPU_RAM1_CONFLICT_CNT_MSB +#define CPU_RAM1_CONFLICT_CNT_LSB WLAN_CPU_RAM1_CONFLICT_CNT_LSB +#define CPU_RAM1_CONFLICT_CNT_MASK WLAN_CPU_RAM1_CONFLICT_CNT_MASK +#define CPU_RAM1_CONFLICT_CNT_GET(x) WLAN_CPU_RAM1_CONFLICT_CNT_GET(x) +#define CPU_RAM1_CONFLICT_CNT_SET(x) WLAN_CPU_RAM1_CONFLICT_CNT_SET(x) +#define CPU_RAM2_CONFLICT_ADDRESS WLAN_CPU_RAM2_CONFLICT_ADDRESS +#define CPU_RAM2_CONFLICT_OFFSET WLAN_CPU_RAM2_CONFLICT_OFFSET +#define CPU_RAM2_CONFLICT_CNT_MSB WLAN_CPU_RAM2_CONFLICT_CNT_MSB +#define CPU_RAM2_CONFLICT_CNT_LSB WLAN_CPU_RAM2_CONFLICT_CNT_LSB +#define CPU_RAM2_CONFLICT_CNT_MASK WLAN_CPU_RAM2_CONFLICT_CNT_MASK +#define CPU_RAM2_CONFLICT_CNT_GET(x) WLAN_CPU_RAM2_CONFLICT_CNT_GET(x) +#define CPU_RAM2_CONFLICT_CNT_SET(x) WLAN_CPU_RAM2_CONFLICT_CNT_SET(x) +#define CPU_RAM3_CONFLICT_ADDRESS WLAN_CPU_RAM3_CONFLICT_ADDRESS +#define CPU_RAM3_CONFLICT_OFFSET WLAN_CPU_RAM3_CONFLICT_OFFSET +#define CPU_RAM3_CONFLICT_CNT_MSB WLAN_CPU_RAM3_CONFLICT_CNT_MSB +#define CPU_RAM3_CONFLICT_CNT_LSB WLAN_CPU_RAM3_CONFLICT_CNT_LSB +#define CPU_RAM3_CONFLICT_CNT_MASK WLAN_CPU_RAM3_CONFLICT_CNT_MASK +#define CPU_RAM3_CONFLICT_CNT_GET(x) WLAN_CPU_RAM3_CONFLICT_CNT_GET(x) +#define CPU_RAM3_CONFLICT_CNT_SET(x) WLAN_CPU_RAM3_CONFLICT_CNT_SET(x) +#define CPU_RAM4_CONFLICT_ADDRESS WLAN_CPU_RAM4_CONFLICT_ADDRESS +#define CPU_RAM4_CONFLICT_OFFSET WLAN_CPU_RAM4_CONFLICT_OFFSET +#define CPU_RAM4_CONFLICT_CNT_MSB WLAN_CPU_RAM4_CONFLICT_CNT_MSB +#define CPU_RAM4_CONFLICT_CNT_LSB WLAN_CPU_RAM4_CONFLICT_CNT_LSB +#define CPU_RAM4_CONFLICT_CNT_MASK WLAN_CPU_RAM4_CONFLICT_CNT_MASK +#define CPU_RAM4_CONFLICT_CNT_GET(x) WLAN_CPU_RAM4_CONFLICT_CNT_GET(x) +#define CPU_RAM4_CONFLICT_CNT_SET(x) WLAN_CPU_RAM4_CONFLICT_CNT_SET(x) + + +#endif +#endif + + + diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h new file mode 100644 index 000000000000..d28de3938b2e --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h @@ -0,0 +1,195 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _VMC_WLAN_REG_REG_H_ +#define _VMC_WLAN_REG_REG_H_ + +#define WLAN_MC_BCAM_VALID_ADDRESS 0x00000000 +#define WLAN_MC_BCAM_VALID_OFFSET 0x00000000 +#define WLAN_MC_BCAM_VALID_BIT_MSB 0 +#define WLAN_MC_BCAM_VALID_BIT_LSB 0 +#define WLAN_MC_BCAM_VALID_BIT_MASK 0x00000001 +#define WLAN_MC_BCAM_VALID_BIT_GET(x) (((x) & WLAN_MC_BCAM_VALID_BIT_MASK) >> WLAN_MC_BCAM_VALID_BIT_LSB) +#define WLAN_MC_BCAM_VALID_BIT_SET(x) (((x) << WLAN_MC_BCAM_VALID_BIT_LSB) & WLAN_MC_BCAM_VALID_BIT_MASK) + +#define WLAN_MC_BCAM_COMPARE_ADDRESS 0x00000200 +#define WLAN_MC_BCAM_COMPARE_OFFSET 0x00000200 +#define WLAN_MC_BCAM_COMPARE_KEY_MSB 19 +#define WLAN_MC_BCAM_COMPARE_KEY_LSB 2 +#define WLAN_MC_BCAM_COMPARE_KEY_MASK 0x000ffffc +#define WLAN_MC_BCAM_COMPARE_KEY_GET(x) (((x) & WLAN_MC_BCAM_COMPARE_KEY_MASK) >> WLAN_MC_BCAM_COMPARE_KEY_LSB) +#define WLAN_MC_BCAM_COMPARE_KEY_SET(x) (((x) << WLAN_MC_BCAM_COMPARE_KEY_LSB) & WLAN_MC_BCAM_COMPARE_KEY_MASK) + +#define WLAN_MC_BCAM_TARGET_ADDRESS 0x00000400 +#define WLAN_MC_BCAM_TARGET_OFFSET 0x00000400 +#define WLAN_MC_BCAM_TARGET_INST_MSB 31 +#define WLAN_MC_BCAM_TARGET_INST_LSB 0 +#define WLAN_MC_BCAM_TARGET_INST_MASK 0xffffffff +#define WLAN_MC_BCAM_TARGET_INST_GET(x) (((x) & WLAN_MC_BCAM_TARGET_INST_MASK) >> WLAN_MC_BCAM_TARGET_INST_LSB) +#define WLAN_MC_BCAM_TARGET_INST_SET(x) (((x) << WLAN_MC_BCAM_TARGET_INST_LSB) & WLAN_MC_BCAM_TARGET_INST_MASK) + +#define WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS 0x00000600 +#define WLAN_APB_ADDR_ERROR_CONTROL_OFFSET 0x00000600 +#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1 +#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1 +#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002 +#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) +#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) +#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB 0 +#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB 0 +#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001 +#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB) +#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK) + +#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS 0x00000604 +#define WLAN_APB_ADDR_ERROR_STATUS_OFFSET 0x00000604 +#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB 25 +#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB 25 +#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK 0x02000000 +#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB) +#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK) +#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB 24 +#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB 0 +#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff +#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB) +#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK) + +#define WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS 0x00000608 +#define WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET 0x00000608 +#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB 0 +#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB 0 +#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001 +#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB) +#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK) + +#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS 0x0000060c +#define WLAN_AHB_ADDR_ERROR_STATUS_OFFSET 0x0000060c +#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB 31 +#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB 31 +#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK 0x80000000 +#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB) +#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK) +#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB 30 +#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB 30 +#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK 0x40000000 +#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB) +#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK) +#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB 23 +#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB 0 +#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK 0x00ffffff +#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB) +#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK) + +#define WLAN_BCAM_CONFLICT_ERROR_ADDRESS 0x00000610 +#define WLAN_BCAM_CONFLICT_ERROR_OFFSET 0x00000610 +#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB 1 +#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB 1 +#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK 0x00000002 +#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB) +#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK) +#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB 0 +#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB 0 +#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK 0x00000001 +#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB) +#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK) + +#define WLAN_CPU_PERF_CNT_ADDRESS 0x00000614 +#define WLAN_CPU_PERF_CNT_OFFSET 0x00000614 +#define WLAN_CPU_PERF_CNT_EN_MSB 0 +#define WLAN_CPU_PERF_CNT_EN_LSB 0 +#define WLAN_CPU_PERF_CNT_EN_MASK 0x00000001 +#define WLAN_CPU_PERF_CNT_EN_GET(x) (((x) & WLAN_CPU_PERF_CNT_EN_MASK) >> WLAN_CPU_PERF_CNT_EN_LSB) +#define WLAN_CPU_PERF_CNT_EN_SET(x) (((x) << WLAN_CPU_PERF_CNT_EN_LSB) & WLAN_CPU_PERF_CNT_EN_MASK) + +#define WLAN_CPU_INST_FETCH_ADDRESS 0x00000618 +#define WLAN_CPU_INST_FETCH_OFFSET 0x00000618 +#define WLAN_CPU_INST_FETCH_CNT_MSB 31 +#define WLAN_CPU_INST_FETCH_CNT_LSB 0 +#define WLAN_CPU_INST_FETCH_CNT_MASK 0xffffffff +#define WLAN_CPU_INST_FETCH_CNT_GET(x) (((x) & WLAN_CPU_INST_FETCH_CNT_MASK) >> WLAN_CPU_INST_FETCH_CNT_LSB) +#define WLAN_CPU_INST_FETCH_CNT_SET(x) (((x) << WLAN_CPU_INST_FETCH_CNT_LSB) & WLAN_CPU_INST_FETCH_CNT_MASK) + +#define WLAN_CPU_DATA_FETCH_ADDRESS 0x0000061c +#define WLAN_CPU_DATA_FETCH_OFFSET 0x0000061c +#define WLAN_CPU_DATA_FETCH_CNT_MSB 31 +#define WLAN_CPU_DATA_FETCH_CNT_LSB 0 +#define WLAN_CPU_DATA_FETCH_CNT_MASK 0xffffffff +#define WLAN_CPU_DATA_FETCH_CNT_GET(x) (((x) & WLAN_CPU_DATA_FETCH_CNT_MASK) >> WLAN_CPU_DATA_FETCH_CNT_LSB) +#define WLAN_CPU_DATA_FETCH_CNT_SET(x) (((x) << WLAN_CPU_DATA_FETCH_CNT_LSB) & WLAN_CPU_DATA_FETCH_CNT_MASK) + +#define WLAN_CPU_RAM1_CONFLICT_ADDRESS 0x00000620 +#define WLAN_CPU_RAM1_CONFLICT_OFFSET 0x00000620 +#define WLAN_CPU_RAM1_CONFLICT_CNT_MSB 11 +#define WLAN_CPU_RAM1_CONFLICT_CNT_LSB 0 +#define WLAN_CPU_RAM1_CONFLICT_CNT_MASK 0x00000fff +#define WLAN_CPU_RAM1_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM1_CONFLICT_CNT_LSB) +#define WLAN_CPU_RAM1_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM1_CONFLICT_CNT_LSB) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK) + +#define WLAN_CPU_RAM2_CONFLICT_ADDRESS 0x00000624 +#define WLAN_CPU_RAM2_CONFLICT_OFFSET 0x00000624 +#define WLAN_CPU_RAM2_CONFLICT_CNT_MSB 11 +#define WLAN_CPU_RAM2_CONFLICT_CNT_LSB 0 +#define WLAN_CPU_RAM2_CONFLICT_CNT_MASK 0x00000fff +#define WLAN_CPU_RAM2_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM2_CONFLICT_CNT_LSB) +#define WLAN_CPU_RAM2_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM2_CONFLICT_CNT_LSB) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK) + +#define WLAN_CPU_RAM3_CONFLICT_ADDRESS 0x00000628 +#define WLAN_CPU_RAM3_CONFLICT_OFFSET 0x00000628 +#define WLAN_CPU_RAM3_CONFLICT_CNT_MSB 11 +#define WLAN_CPU_RAM3_CONFLICT_CNT_LSB 0 +#define WLAN_CPU_RAM3_CONFLICT_CNT_MASK 0x00000fff +#define WLAN_CPU_RAM3_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM3_CONFLICT_CNT_LSB) +#define WLAN_CPU_RAM3_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM3_CONFLICT_CNT_LSB) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK) + +#define WLAN_CPU_RAM4_CONFLICT_ADDRESS 0x0000062c +#define WLAN_CPU_RAM4_CONFLICT_OFFSET 0x0000062c +#define WLAN_CPU_RAM4_CONFLICT_CNT_MSB 11 +#define WLAN_CPU_RAM4_CONFLICT_CNT_LSB 0 +#define WLAN_CPU_RAM4_CONFLICT_CNT_MASK 0x00000fff +#define WLAN_CPU_RAM4_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM4_CONFLICT_CNT_LSB) +#define WLAN_CPU_RAM4_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM4_CONFLICT_CNT_LSB) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct vmc_wlan_reg_reg_s { + volatile unsigned int wlan_mc_bcam_valid[128]; + volatile unsigned int wlan_mc_bcam_compare[128]; + volatile unsigned int wlan_mc_bcam_target[128]; + volatile unsigned int wlan_apb_addr_error_control; + volatile unsigned int wlan_apb_addr_error_status; + volatile unsigned int wlan_ahb_addr_error_control; + volatile unsigned int wlan_ahb_addr_error_status; + volatile unsigned int wlan_bcam_conflict_error; + volatile unsigned int wlan_cpu_perf_cnt; + volatile unsigned int wlan_cpu_inst_fetch; + volatile unsigned int wlan_cpu_data_fetch; + volatile unsigned int wlan_cpu_ram1_conflict; + volatile unsigned int wlan_cpu_ram2_conflict; + volatile unsigned int wlan_cpu_ram3_conflict; + volatile unsigned int wlan_cpu_ram4_conflict; +} vmc_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _VMC_WLAN_REG_H_ */ |