diff options
Diffstat (limited to 'drivers/staging/comedi/drivers/amplc_dio200.c')
| -rw-r--r-- | drivers/staging/comedi/drivers/amplc_dio200.c | 1468 |
1 files changed, 1034 insertions, 434 deletions
diff --git a/drivers/staging/comedi/drivers/amplc_dio200.c b/drivers/staging/comedi/drivers/amplc_dio200.c index 29eb52d11d2f..5f309ba88a1a 100644 --- a/drivers/staging/comedi/drivers/amplc_dio200.c +++ b/drivers/staging/comedi/drivers/amplc_dio200.c @@ -25,185 +25,238 @@ */ /* -Driver: amplc_dio200 -Description: Amplicon 200 Series Digital I/O -Author: Ian Abbott <abbotti@mev.co.uk> -Devices: [Amplicon] PC212E (pc212e), PC214E (pc214e), PC215E (pc215e), - PCI215 (pci215 or amplc_dio200), PC218E (pc218e), PC272E (pc272e), - PCI272 (pci272 or amplc_dio200) -Updated: Wed, 22 Oct 2008 13:36:02 +0100 -Status: works - -Configuration options - PC212E, PC214E, PC215E, PC218E, PC272E: - [0] - I/O port base address - [1] - IRQ (optional, but commands won't work without it) - -Configuration options - PCI215, PCI272: - [0] - PCI bus of device (optional) - [1] - PCI slot of device (optional) - If bus/slot is not specified, the first available PCI device will - be used. - -Passing a zero for an option is the same as leaving it unspecified. - -SUBDEVICES - - PC218E PC212E PC215E/PCI215 - ------------- ------------- ------------- - Subdevices 7 6 5 - 0 CTR-X1 PPI-X PPI-X - 1 CTR-X2 CTR-Y1 PPI-Y - 2 CTR-Y1 CTR-Y2 CTR-Z1 - 3 CTR-Y2 CTR-Z1 CTR-Z2 - 4 CTR-Z1 CTR-Z2 INTERRUPT - 5 CTR-Z2 INTERRUPT - 6 INTERRUPT - - PC214E PC272E/PCI272 - ------------- ------------- - Subdevices 4 4 - 0 PPI-X PPI-X - 1 PPI-Y PPI-Y - 2 CTR-Z1* PPI-Z - 3 INTERRUPT* INTERRUPT - -Each PPI is a 8255 chip providing 24 DIO channels. The DIO channels -are configurable as inputs or outputs in four groups: - - Port A - channels 0 to 7 - Port B - channels 8 to 15 - Port CL - channels 16 to 19 - Port CH - channels 20 to 23 - -Only mode 0 of the 8255 chips is supported. - -Each CTR is a 8254 chip providing 3 16-bit counter channels. Each -channel is configured individually with INSN_CONFIG instructions. The -specific type of configuration instruction is specified in data[0]. -Some configuration instructions expect an additional parameter in -data[1]; others return a value in data[1]. The following configuration -instructions are supported: - - INSN_CONFIG_SET_COUNTER_MODE. Sets the counter channel's mode and - BCD/binary setting specified in data[1]. - - INSN_CONFIG_8254_READ_STATUS. Reads the status register value for the - counter channel into data[1]. - - INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel's clock source as - specified in data[1] (this is a hardware-specific value). Not - supported on PC214E. For the other boards, valid clock sources are - 0 to 7 as follows: - - 0. CLK n, the counter channel's dedicated CLK input from the SK1 - connector. (N.B. for other values, the counter channel's CLKn - pin on the SK1 connector is an output!) - 1. Internal 10 MHz clock. - 2. Internal 1 MHz clock. - 3. Internal 100 kHz clock. - 4. Internal 10 kHz clock. - 5. Internal 1 kHz clock. - 6. OUT n-1, the output of counter channel n-1 (see note 1 below). - 7. Ext Clock, the counter chip's dedicated Ext Clock input from - the SK1 connector. This pin is shared by all three counter - channels on the chip. - - INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current - clock source in data[1]. For internal clock sources, data[2] is set - to the period in ns. - - INSN_CONFIG_SET_GATE_SRC. Sets the counter channel's gate source as - specified in data[2] (this is a hardware-specific value). Not - supported on PC214E. For the other boards, valid gate sources are 0 - to 7 as follows: - - 0. VCC (internal +5V d.c.), i.e. gate permanently enabled. - 1. GND (internal 0V d.c.), i.e. gate permanently disabled. - 2. GAT n, the counter channel's dedicated GAT input from the SK1 - connector. (N.B. for other values, the counter channel's GATn - pin on the SK1 connector is an output!) - 3. /OUT n-2, the inverted output of counter channel n-2 (see note - 2 below). - 4. Reserved. - 5. Reserved. - 6. Reserved. - 7. Reserved. - - INSN_CONFIG_GET_GATE_SRC. Returns the counter channel's current gate - source in data[2]. - -Clock and gate interconnection notes: - - 1. Clock source OUT n-1 is the output of the preceding channel on the - same counter subdevice if n > 0, or the output of channel 2 on the - preceding counter subdevice (see note 3) if n = 0. - - 2. Gate source /OUT n-2 is the inverted output of channel 0 on the - same counter subdevice if n = 2, or the inverted output of channel n+1 - on the preceding counter subdevice (see note 3) if n < 2. - - 3. The counter subdevices are connected in a ring, so the highest - counter subdevice precedes the lowest. - -The 'INTERRUPT' subdevice pretends to be a digital input subdevice. The -digital inputs come from the interrupt status register. The number of -channels matches the number of interrupt sources. The PC214E does not -have an interrupt status register; see notes on 'INTERRUPT SOURCES' -below. - -INTERRUPT SOURCES - - PC218E PC212E PC215E/PCI215 - ------------- ------------- ------------- - Sources 6 6 6 - 0 CTR-X1-OUT PPI-X-C0 PPI-X-C0 - 1 CTR-X2-OUT PPI-X-C3 PPI-X-C3 - 2 CTR-Y1-OUT CTR-Y1-OUT PPI-Y-C0 - 3 CTR-Y2-OUT CTR-Y2-OUT PPI-Y-C3 - 4 CTR-Z1-OUT CTR-Z1-OUT CTR-Z1-OUT - 5 CTR-Z2-OUT CTR-Z2-OUT CTR-Z2-OUT - - PC214E PC272E/PCI272 - ------------- ------------- - Sources 1 6 - 0 JUMPER-J5 PPI-X-C0 - 1 PPI-X-C3 - 2 PPI-Y-C0 - 3 PPI-Y-C3 - 4 PPI-Z-C0 - 5 PPI-Z-C3 - -When an interrupt source is enabled in the interrupt source enable -register, a rising edge on the source signal latches the corresponding -bit to 1 in the interrupt status register. - -When the interrupt status register value as a whole (actually, just the -6 least significant bits) goes from zero to non-zero, the board will -generate an interrupt. For level-triggered hardware interrupts (PCI -card), the interrupt will remain asserted until the interrupt status -register is cleared to zero. For edge-triggered hardware interrupts -(ISA card), no further interrupts will occur until the interrupt status -register is cleared to zero. To clear a bit to zero in the interrupt -status register, the corresponding interrupt source must be disabled -in the interrupt source enable register (there is no separate interrupt -clear register). - -The PC214E does not have an interrupt source enable register or an -interrupt status register; its 'INTERRUPT' subdevice has a single -channel and its interrupt source is selected by the position of jumper -J5. - -COMMANDS - -The driver supports a read streaming acquisition command on the -'INTERRUPT' subdevice. The channel list selects the interrupt sources -to be enabled. All channels will be sampled together (convert_src == -TRIG_NOW). The scan begins a short time after the hardware interrupt -occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT, -scan_begin_arg == 0). The value read from the interrupt status register -is packed into a short value, one bit per requested channel, in the -order they appear in the channel list. -*/ + * Driver: amplc_dio200 + * Description: Amplicon 200 Series Digital I/O + * Author: Ian Abbott <abbotti@mev.co.uk> + * Devices: [Amplicon] PC212E (pc212e), PC214E (pc214e), PC215E (pc215e), + * PCI215 (pci215), PCIe215 (pcie215), PC218E (pc218e), PCIe236 (pcie236), + * PC272E (pc272e), PCI272 (pci272), PCIe296 (pcie296) + * Updated: Wed, 24 Oct 2012 16:22:34 +0100 + * Status: works + * + * Configuration options - PC212E, PC214E, PC215E, PC218E, PC272E: + * [0] - I/O port base address + * [1] - IRQ (optional, but commands won't work without it) + * + * Manual configuration of PCI(e) cards is not supported; they are configured + * automatically. + * + * Passing a zero for an option is the same as leaving it unspecified. + * + * SUBDEVICES + * + * PC212E PC214E PC215E/PCI215 + * ------------- ------------- ------------- + * Subdevices 6 4 5 + * 0 PPI-X PPI-X PPI-X + * 1 CTR-Y1 PPI-Y PPI-Y + * 2 CTR-Y2 CTR-Z1* CTR-Z1 + * 3 CTR-Z1 INTERRUPT* CTR-Z2 + * 4 CTR-Z2 INTERRUPT + * 5 INTERRUPT + * + * PCIe215 PC218E PCIe236 + * ------------- ------------- ------------- + * Subdevices 8 7 8 + * 0 PPI-X CTR-X1 PPI-X + * 1 UNUSED CTR-X2 UNUSED + * 2 PPI-Y CTR-Y1 UNUSED + * 3 UNUSED CTR-Y2 UNUSED + * 4 CTR-Z1 CTR-Z1 CTR-Z1 + * 5 CTR-Z2 CTR-Z2 CTR-Z2 + * 6 TIMER INTERRUPT TIMER + * 7 INTERRUPT INTERRUPT + * + * PC272E/PCI272 PCIe296 + * ------------- ------------- + * Subdevices 4 8 + * 0 PPI-X PPI-X1 + * 1 PPI-Y PPI-X2 + * 2 PPI-Z PPI-Y1 + * 3 INTERRUPT PPI-Y2 + * 4 CTR-Z1 + * 5 CTR-Z2 + * 6 TIMER + * 7 INTERRUPT + * + * Each PPI is a 8255 chip providing 24 DIO channels. The DIO channels + * are configurable as inputs or outputs in four groups: + * + * Port A - channels 0 to 7 + * Port B - channels 8 to 15 + * Port CL - channels 16 to 19 + * Port CH - channels 20 to 23 + * + * Only mode 0 of the 8255 chips is supported. + * + * Each CTR is a 8254 chip providing 3 16-bit counter channels. Each + * channel is configured individually with INSN_CONFIG instructions. The + * specific type of configuration instruction is specified in data[0]. + * Some configuration instructions expect an additional parameter in + * data[1]; others return a value in data[1]. The following configuration + * instructions are supported: + * + * INSN_CONFIG_SET_COUNTER_MODE. Sets the counter channel's mode and + * BCD/binary setting specified in data[1]. + * + * INSN_CONFIG_8254_READ_STATUS. Reads the status register value for the + * counter channel into data[1]. + * + * INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel's clock source as + * specified in data[1] (this is a hardware-specific value). Not + * supported on PC214E. For the other boards, valid clock sources are + * 0 to 7 as follows: + * + * 0. CLK n, the counter channel's dedicated CLK input from the SK1 + * connector. (N.B. for other values, the counter channel's CLKn + * pin on the SK1 connector is an output!) + * 1. Internal 10 MHz clock. + * 2. Internal 1 MHz clock. + * 3. Internal 100 kHz clock. + * 4. Internal 10 kHz clock. + * 5. Internal 1 kHz clock. + * 6. OUT n-1, the output of counter channel n-1 (see note 1 below). + * 7. Ext Clock, the counter chip's dedicated Ext Clock input from + * the SK1 connector. This pin is shared by all three counter + * channels on the chip. + * + * For the PCIe boards, clock sources in the range 0 to 31 are allowed + * and the following additional clock sources are defined: + * + * 8. HIGH logic level. + * 9. LOW logic level. + * 10. "Pattern present" signal. + * 11. Internal 20 MHz clock. + * + * INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current + * clock source in data[1]. For internal clock sources, data[2] is set + * to the period in ns. + * + * INSN_CONFIG_SET_GATE_SRC. Sets the counter channel's gate source as + * specified in data[2] (this is a hardware-specific value). Not + * supported on PC214E. For the other boards, valid gate sources are 0 + * to 7 as follows: + * + * 0. VCC (internal +5V d.c.), i.e. gate permanently enabled. + * 1. GND (internal 0V d.c.), i.e. gate permanently disabled. + * 2. GAT n, the counter channel's dedicated GAT input from the SK1 + * connector. (N.B. for other values, the counter channel's GATn + * pin on the SK1 connector is an output!) + * 3. /OUT n-2, the inverted output of counter channel n-2 (see note + * 2 below). + * 4. Reserved. + * 5. Reserved. + * 6. Reserved. + * 7. Reserved. + * + * For the PCIe boards, gate sources in the range 0 to 31 are allowed; + * the following additional clock sources and clock sources 6 and 7 are + * (re)defined: + * + * 6. /GAT n, negated version of the counter channel's dedicated + * GAT input (negated version of gate source 2). + * 7. OUT n-2, the non-inverted output of counter channel n-2 + * (negated version of gate source 3). + * 8. "Pattern present" signal, HIGH while pattern present. + * 9. "Pattern occurred" latched signal, latches HIGH when pattern + * occurs. + * 10. "Pattern gone away" latched signal, latches LOW when pattern + * goes away after it occurred. + * 11. Negated "pattern present" signal, LOW while pattern present + * (negated version of gate source 8). + * 12. Negated "pattern occurred" latched signal, latches LOW when + * pattern occurs (negated version of gate source 9). + * 13. Negated "pattern gone away" latched signal, latches LOW when + * pattern goes away after it occurred (negated version of gate + * source 10). + * + * INSN_CONFIG_GET_GATE_SRC. Returns the counter channel's current gate + * source in data[2]. + * + * Clock and gate interconnection notes: + * + * 1. Clock source OUT n-1 is the output of the preceding channel on the + * same counter subdevice if n > 0, or the output of channel 2 on the + * preceding counter subdevice (see note 3) if n = 0. + * + * 2. Gate source /OUT n-2 is the inverted output of channel 0 on the + * same counter subdevice if n = 2, or the inverted output of channel n+1 + * on the preceding counter subdevice (see note 3) if n < 2. + * + * 3. The counter subdevices are connected in a ring, so the highest + * counter subdevice precedes the lowest. + * + * The 'TIMER' subdevice is a free-running 32-bit timer subdevice. + * + * The 'INTERRUPT' subdevice pretends to be a digital input subdevice. The + * digital inputs come from the interrupt status register. The number of + * channels matches the number of interrupt sources. The PC214E does not + * have an interrupt status register; see notes on 'INTERRUPT SOURCES' + * below. + * + * INTERRUPT SOURCES + * + * PC212E PC214E PC215E/PCI215 + * ------------- ------------- ------------- + * Sources 6 1 6 + * 0 PPI-X-C0 JUMPER-J5 PPI-X-C0 + * 1 PPI-X-C3 PPI-X-C3 + * 2 CTR-Y1-OUT1 PPI-Y-C0 + * 3 CTR-Y2-OUT1 PPI-Y-C3 + * 4 CTR-Z1-OUT1 CTR-Z1-OUT1 + * 5 CTR-Z2-OUT1 CTR-Z2-OUT1 + * + * PCIe215 PC218E PCIe236 + * ------------- ------------- ------------- + * Sources 6 6 6 + * 0 PPI-X-C0 CTR-X1-OUT1 PPI-X-C0 + * 1 PPI-X-C3 CTR-X2-OUT1 PPI-X-C3 + * 2 PPI-Y-C0 CTR-Y1-OUT1 unused + * 3 PPI-Y-C3 CTR-Y2-OUT1 unused + * 4 CTR-Z1-OUT1 CTR-Z1-OUT1 CTR-Z1-OUT1 + * 5 CTR-Z2-OUT1 CTR-Z2-OUT1 CTR-Z2-OUT1 + * + * PC272E/PCI272 PCIe296 + * ------------- ------------- + * Sources 6 6 + * 0 PPI-X-C0 PPI-X1-C0 + * 1 PPI-X-C3 PPI-X1-C3 + * 2 PPI-Y-C0 PPI-Y1-C0 + * 3 PPI-Y-C3 PPI-Y1-C3 + * 4 PPI-Z-C0 CTR-Z1-OUT1 + * 5 PPI-Z-C3 CTR-Z2-OUT1 + * + * When an interrupt source is enabled in the interrupt source enable + * register, a rising edge on the source signal latches the corresponding + * bit to 1 in the interrupt status register. + * + * When the interrupt status register value as a whole (actually, just the + * 6 least significant bits) goes from zero to non-zero, the board will + * generate an interrupt. For level-triggered hardware interrupts (PCI + * card), the interrupt will remain asserted until the interrupt status + * register is cleared to zero. For edge-triggered hardware interrupts + * (ISA card), no further interrupts will occur until the interrupt status + * register is cleared to zero. To clear a bit to zero in the interrupt + * status register, the corresponding interrupt source must be disabled + * in the interrupt source enable register (there is no separate interrupt + * clear register). + * + * The PC214E does not have an interrupt source enable register or an + * interrupt status register; its 'INTERRUPT' subdevice has a single + * channel and its interrupt source is selected by the position of jumper + * J5. + * + * COMMANDS + * + * The driver supports a read streaming acquisition command on the + * 'INTERRUPT' subdevice. The channel list selects the interrupt sources + * to be enabled. All channels will be sampled together (convert_src == + * TRIG_NOW). The scan begins a short time after the hardware interrupt + * occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT, + * scan_begin_arg == 0). The value read from the interrupt status register + * is packed into a short value, one bit per requested channel, in the + * order they appear in the channel list. + */ #include <linux/interrupt.h> #include <linux/slab.h> @@ -211,7 +264,6 @@ order they appear in the channel list. #include "../comedidev.h" #include "comedi_fc.h" -#include "8255.h" #include "8253.h" #define DIO200_DRIVER_NAME "amplc_dio200" @@ -220,13 +272,24 @@ order they appear in the channel list. #define DO_PCI IS_ENABLED(CONFIG_COMEDI_AMPLC_DIO200_PCI) /* PCI IDs */ -#define PCI_VENDOR_ID_AMPLICON 0x14dc #define PCI_DEVICE_ID_AMPLICON_PCI272 0x000a #define PCI_DEVICE_ID_AMPLICON_PCI215 0x000b -#define PCI_DEVICE_ID_INVALID 0xffff +#define PCI_DEVICE_ID_AMPLICON_PCIE236 0x0011 +#define PCI_DEVICE_ID_AMPLICON_PCIE215 0x0012 +#define PCI_DEVICE_ID_AMPLICON_PCIE296 0x0014 + +/* 8255 control register bits */ +#define CR_C_LO_IO 0x01 +#define CR_B_IO 0x02 +#define CR_B_MODE 0x04 +#define CR_C_HI_IO 0x08 +#define CR_A_IO 0x10 +#define CR_A_MODE(a) ((a)<<5) +#define CR_CW 0x80 /* 200 series registers */ #define DIO200_IO_SIZE 0x20 +#define DIO200_PCIE_IO_SIZE 0x4000 #define DIO200_XCLK_SCE 0x18 /* Group X clock selection register */ #define DIO200_YCLK_SCE 0x19 /* Group Y clock selection register */ #define DIO200_ZCLK_SCE 0x1a /* Group Z clock selection register */ @@ -234,30 +297,78 @@ order they appear in the channel list. #define DIO200_YGAT_SCE 0x1c /* Group Y gate selection register */ #define DIO200_ZGAT_SCE 0x1d /* Group Z gate selection register */ #define DIO200_INT_SCE 0x1e /* Interrupt enable/status register */ +/* Extra registers for new PCIe boards */ +#define DIO200_ENHANCE 0x20 /* 1 to enable enhanced features */ +#define DIO200_VERSION 0x24 /* Hardware version register */ +#define DIO200_TS_CONFIG 0x600 /* Timestamp timer config register */ +#define DIO200_TS_COUNT 0x602 /* Timestamp timer count register */ /* - * Macros for constructing value for DIO_200_?CLK_SCE and + * Functions for constructing value for DIO_200_?CLK_SCE and * DIO_200_?GAT_SCE registers: * * 'which' is: 0 for CTR-X1, CTR-Y1, CTR-Z1; 1 for CTR-X2, CTR-Y2 or CTR-Z2. * 'chan' is the channel: 0, 1 or 2. - * 'source' is the signal source: 0 to 7. + * 'source' is the signal source: 0 to 7, or 0 to 31 for "enhanced" boards. */ -#define CLK_SCE(which, chan, source) (((which) << 5) | ((chan) << 3) | (source)) -#define GAT_SCE(which, chan, source) (((which) << 5) | ((chan) << 3) | (source)) +static unsigned char clk_gat_sce(unsigned int which, unsigned int chan, + unsigned int source) +{ + return (which << 5) | (chan << 3) | + ((source & 030) << 3) | (source & 007); +} + +static unsigned char clk_sce(unsigned int which, unsigned int chan, + unsigned int source) +{ + return clk_gat_sce(which, chan, source); +} + +static unsigned char gat_sce(unsigned int which, unsigned int chan, + unsigned int source) +{ + return clk_gat_sce(which, chan, source); +} /* * Periods of the internal clock sources in nanoseconds. */ -static const unsigned clock_period[8] = { - 0, /* dedicated clock input/output pin */ - 100, /* 10 MHz */ - 1000, /* 1 MHz */ - 10000, /* 100 kHz */ - 100000, /* 10 kHz */ - 1000000, /* 1 kHz */ - 0, /* OUT N-1 */ - 0 /* group clock input pin */ +static const unsigned int clock_period[32] = { + [1] = 100, /* 10 MHz */ + [2] = 1000, /* 1 MHz */ + [3] = 10000, /* 100 kHz */ + [4] = 100000, /* 10 kHz */ + [5] = 1000000, /* 1 kHz */ + [11] = 50, /* 20 MHz (enhanced boards) */ + /* clock sources 12 and later reserved for enhanced boards */ +}; + +/* + * Timestamp timer configuration register (for new PCIe boards). + */ +#define TS_CONFIG_RESET 0x100 /* Reset counter to zero. */ +#define TS_CONFIG_CLK_SRC_MASK 0x0FF /* Clock source. */ +#define TS_CONFIG_MAX_CLK_SRC 2 /* Maximum clock source value. */ + +/* + * Periods of the timestamp timer clock sources in nanoseconds. + */ +static const unsigned int ts_clock_period[TS_CONFIG_MAX_CLK_SRC + 1] = { + 1, /* 1 nanosecond (but with 20 ns granularity). */ + 1000, /* 1 microsecond. */ + 1000000, /* 1 millisecond. */ +}; + +/* + * Register region. + */ +enum dio200_regtype { no_regtype = 0, io_regtype, mmio_regtype }; +struct dio200_region { + union { + unsigned long iobase; /* I/O base address */ + unsigned char __iomem *membase; /* mapped MMIO base address */ + } u; + enum dio200_regtype regtype; }; /* @@ -269,13 +380,14 @@ enum dio200_bustype { isa_bustype, pci_bustype }; enum dio200_model { pc212e_model, pc214e_model, - pc215e_model, pci215_model, + pc215e_model, pci215_model, pcie215_model, pc218e_model, + pcie236_model, pc272e_model, pci272_model, - anypci_model + pcie296_model, }; -enum dio200_layout { +enum dio200_layout_idx { #if DO_ISA pc212_layout, pc214_layout, @@ -284,7 +396,12 @@ enum dio200_layout { #if DO_ISA pc218_layout, #endif - pc272_layout + pc272_layout, +#if DO_PCI + pcie215_layout, + pcie236_layout, + pcie296_layout, +#endif }; struct dio200_board { @@ -292,7 +409,10 @@ struct dio200_board { unsigned short devid; enum dio200_bustype bustype; enum dio200_model model; - enum dio200_layout layout; + enum dio200_layout_idx layout; + unsigned char mainbar; + unsigned char mainshift; + unsigned int mainsize; }; static const struct dio200_board dio200_boards[] = { @@ -302,30 +422,35 @@ static const struct dio200_board dio200_boards[] = { .bustype = isa_bustype, .model = pc212e_model, .layout = pc212_layout, + .mainsize = DIO200_IO_SIZE, }, { .name = "pc214e", .bustype = isa_bustype, .model = pc214e_model, .layout = pc214_layout, + .mainsize = DIO200_IO_SIZE, }, { .name = "pc215e", .bustype = isa_bustype, .model = pc215e_model, .layout = pc215_layout, + .mainsize = DIO200_IO_SIZE, }, { .name = "pc218e", .bustype = isa_bustype, .model = pc218e_model, .layout = pc218_layout, + .mainsize = DIO200_IO_SIZE, }, { .name = "pc272e", .bustype = isa_bustype, .model = pc272e_model, .layout = pc272_layout, + .mainsize = DIO200_IO_SIZE, }, #endif #if DO_PCI @@ -335,6 +460,8 @@ static const struct dio200_board dio200_boards[] = { .bustype = pci_bustype, .model = pci215_model, .layout = pc215_layout, + .mainbar = 2, + .mainsize = DIO200_IO_SIZE, }, { .name = "pci272", @@ -342,12 +469,38 @@ static const struct dio200_board dio200_boards[] = { .bustype = pci_bustype, .model = pci272_model, .layout = pc272_layout, + .mainbar = 2, + .mainsize = DIO200_IO_SIZE, + }, + { + .name = "pcie215", + .devid = PCI_DEVICE_ID_AMPLICON_PCIE215, + .bustype = pci_bustype, + .model = pcie215_model, + .layout = pcie215_layout, + .mainbar = 1, + .mainshift = 3, + .mainsize = DIO200_PCIE_IO_SIZE, }, { - .name = DIO200_DRIVER_NAME, - .devid = PCI_DEVICE_ID_INVALID, + .name = "pcie236", + .devid = PCI_DEVICE_ID_AMPLICON_PCIE236, .bustype = pci_bustype, - .model = anypci_model, /* wildcard */ + .model = pcie236_model, + .layout = pcie236_layout, + .mainbar = 1, + .mainshift = 3, + .mainsize = DIO200_PCIE_IO_SIZE, + }, + { + .name = "pcie296", + .devid = PCI_DEVICE_ID_AMPLICON_PCIE296, + .bustype = pci_bustype, + .model = pcie296_model, + .layout = pcie296_layout, + .mainbar = 1, + .mainshift = 3, + .mainsize = DIO200_PCIE_IO_SIZE, }, #endif }; @@ -357,20 +510,21 @@ static const struct dio200_board dio200_boards[] = { * layout. */ -enum dio200_sdtype { sd_none, sd_intr, sd_8255, sd_8254 }; +enum dio200_sdtype { sd_none, sd_intr, sd_8255, sd_8254, sd_timer }; -#define DIO200_MAX_SUBDEVS 7 +#define DIO200_MAX_SUBDEVS 8 #define DIO200_MAX_ISNS 6 -struct dio200_layout_struct { +struct dio200_layout { unsigned short n_subdevs; /* number of subdevices */ unsigned char sdtype[DIO200_MAX_SUBDEVS]; /* enum dio200_sdtype */ unsigned char sdinfo[DIO200_MAX_SUBDEVS]; /* depends on sdtype */ char has_int_sce; /* has interrupt enable/status register */ char has_clk_gat_sce; /* has clock/gate selection registers */ + char has_enhancements; /* has enhanced features */ }; -static const struct dio200_layout_struct dio200_layouts[] = { +static const struct dio200_layout dio200_layouts[] = { #if DO_ISA [pc212_layout] = { .n_subdevs = 6, @@ -421,6 +575,38 @@ static const struct dio200_layout_struct dio200_layouts[] = { .has_int_sce = 1, .has_clk_gat_sce = 0, }, +#if DO_PCI + [pcie215_layout] = { + .n_subdevs = 8, + .sdtype = {sd_8255, sd_none, sd_8255, sd_none, + sd_8254, sd_8254, sd_timer, sd_intr}, + .sdinfo = {0x00, 0x00, 0x08, 0x00, + 0x10, 0x14, 0x00, 0x3F}, + .has_int_sce = 1, + .has_clk_gat_sce = 1, + .has_enhancements = 1, + }, + [pcie236_layout] = { + .n_subdevs = 8, + .sdtype = {sd_8255, sd_none, sd_none, sd_none, + sd_8254, sd_8254, sd_timer, sd_intr}, + .sdinfo = {0x00, 0x00, 0x00, 0x00, + 0x10, 0x14, 0x00, 0x3F}, + .has_int_sce = 1, + .has_clk_gat_sce = 1, + .has_enhancements = 1, + }, + [pcie296_layout] = { + .n_subdevs = 8, + .sdtype = {sd_8255, sd_8255, sd_8255, sd_8255, + sd_8254, sd_8254, sd_timer, sd_intr}, + .sdinfo = {0x00, 0x04, 0x08, 0x0C, + 0x10, 0x14, 0x00, 0x3F}, + .has_int_sce = 1, + .has_clk_gat_sce = 1, + .has_enhancements = 1, + }, +#endif }; /* this structure is for data unique to this hardware driver. If @@ -428,31 +614,46 @@ static const struct dio200_layout_struct dio200_layouts[] = { feel free to suggest moving the variable to the struct comedi_device struct. */ struct dio200_private { + struct dio200_region io; /* Register region */ int intr_sd; }; struct dio200_subdev_8254 { - unsigned long iobase; /* Counter base address */ - unsigned long clk_sce_iobase; /* CLK_SCE base address */ - unsigned long gat_sce_iobase; /* GAT_SCE base address */ - int which; /* Bit 5 of CLK_SCE or GAT_SCE */ - int has_clk_gat_sce; - unsigned clock_src[3]; /* Current clock sources */ - unsigned gate_src[3]; /* Current gate sources */ + unsigned int ofs; /* Counter base offset */ + unsigned int clk_sce_ofs; /* CLK_SCE base address */ + unsigned int gat_sce_ofs; /* GAT_SCE base address */ + int which; /* Bit 5 of CLK_SCE or GAT_SCE */ + unsigned int clock_src[3]; /* Current clock sources */ + unsigned int gate_src[3]; /* Current gate sources */ spinlock_t spinlock; }; +struct dio200_subdev_8255 { + unsigned int ofs; /* DIO base offset */ +}; + struct dio200_subdev_intr { - unsigned long iobase; + unsigned int ofs; spinlock_t spinlock; int active; - int has_int_sce; unsigned int valid_isns; unsigned int enabled_isns; unsigned int stopcount; int continuous; }; +static inline const struct dio200_layout * +dio200_board_layout(const struct dio200_board *board) +{ + return &dio200_layouts[board->layout]; +} + +static inline const struct dio200_layout * +dio200_dev_layout(struct comedi_device *dev) +{ + return dio200_board_layout(comedi_board(dev)); +} + static inline bool is_pci_board(const struct dio200_board *board) { return DO_PCI && board->bustype == pci_bustype; @@ -464,6 +665,70 @@ static inline bool is_isa_board(const struct dio200_board *board) } /* + * Read 8-bit register. + */ +static unsigned char dio200_read8(struct comedi_device *dev, + unsigned int offset) +{ + const struct dio200_board *thisboard = comedi_board(dev); + struct dio200_private *devpriv = dev->private; + + offset <<= thisboard->mainshift; + if (devpriv->io.regtype == io_regtype) + return inb(devpriv->io.u.iobase + offset); + else + return readb(devpriv->io.u.membase + offset); +} + +/* + * Write 8-bit register. + */ +static void dio200_write8(struct comedi_device *dev, unsigned int offset, + unsigned char val) +{ + const struct dio200_board *thisboard = comedi_board(dev); + struct dio200_private *devpriv = dev->private; + + offset <<= thisboard->mainshift; + if (devpriv->io.regtype == io_regtype) + outb(val, devpriv->io.u.iobase + offset); + else + writeb(val, devpriv->io.u.membase + offset); +} + +/* + * Read 32-bit register. + */ +static unsigned int dio200_read32(struct comedi_device *dev, + unsigned int offset) +{ + const struct dio200_board *thisboard = comedi_board(dev); + struct dio200_private *devpriv = dev->private; + + offset <<= thisboard->mainshift; + if (devpriv->io.regtype == io_regtype) + return inl(devpriv->io.u.iobase + offset); + else + return readl(devpriv->io.u.membase + offset); +} + +/* + * Write 32-bit register. + */ +static void dio200_write32(struct comedi_device *dev, unsigned int offset, + unsigned int val) +{ + const struct dio200_board *thisboard = comedi_board(dev); + struct dio200_private *devpriv = dev->private; + + offset <<= thisboard->mainshift; + if (devpriv->io.regtype == io_regtype) + outl(val, devpriv->io.u.iobase + offset); + else + writel(val, devpriv->io.u.membase + offset); +} + +/* * This function looks for a board matching the supplied PCI device. */ static const struct dio200_board * @@ -479,49 +744,6 @@ dio200_find_pci_board(struct pci_dev *pci_dev) } /* - * This function looks for a PCI device matching the requested board name, - * bus and slot. - */ -static struct pci_dev *dio200_find_pci_dev(struct comedi_device *dev, - struct comedi_devconfig *it) -{ - const struct dio200_board *thisboard = comedi_board(dev); - struct pci_dev *pci_dev = NULL; - int bus = it->options[0]; - int slot = it->options[1]; - - for_each_pci_dev(pci_dev) { - if (bus || slot) { - if (bus != pci_dev->bus->number || - slot != PCI_SLOT(pci_dev->devfn)) - continue; - } - if (pci_dev->vendor != PCI_VENDOR_ID_AMPLICON) - continue; - - if (thisboard->model == anypci_model) { - /* Wildcard board matches any supported PCI board. */ - const struct dio200_board *foundboard; - - foundboard = dio200_find_pci_board(pci_dev); - if (foundboard == NULL) - continue; - /* Replace wildcard board_ptr. */ - dev->board_ptr = foundboard; - } else { - /* Match specific model name. */ - if (pci_dev->device != thisboard->devid) - continue; - } - return pci_dev; - } - dev_err(dev->class_dev, - "No supported board found! (req. bus %d, slot %d)\n", - bus, slot); - return NULL; -} - -/* * This function checks and requests an I/O region, reporting an error * if there is a conflict. */ @@ -545,11 +767,12 @@ dio200_subdev_intr_insn_bits(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data) { + const struct dio200_layout *layout = dio200_dev_layout(dev); struct dio200_subdev_intr *subpriv = s->private; - if (subpriv->has_int_sce) { + if (layout->has_int_sce) { /* Just read the interrupt status register. */ - data[1] = inb(subpriv->iobase) & subpriv->valid_isns; + data[1] = dio200_read8(dev, subpriv->ofs) & subpriv->valid_isns; } else { /* No interrupt status register. */ data[0] = 0; @@ -564,12 +787,13 @@ dio200_subdev_intr_insn_bits(struct comedi_device *dev, static void dio200_stop_intr(struct comedi_device *dev, struct comedi_subdevice *s) { + const struct dio200_layout *layout = dio200_dev_layout(dev); struct dio200_subdev_intr *subpriv = s->private; subpriv->active = 0; subpriv->enabled_isns = 0; - if (subpriv->has_int_sce) - outb(0, subpriv->iobase); + if (layout->has_int_sce) + dio200_write8(dev, subpriv->ofs, 0); } /* @@ -580,6 +804,7 @@ static int dio200_start_intr(struct comedi_device *dev, { unsigned int n; unsigned isn_bits; + const struct dio200_layout *layout = dio200_dev_layout(dev); struct dio200_subdev_intr *subpriv = s->private; struct comedi_cmd *cmd = &s->async->cmd; int retval = 0; @@ -599,8 +824,8 @@ static int dio200_start_intr(struct comedi_device *dev, isn_bits &= subpriv->valid_isns; /* Enable interrupt sources. */ subpriv->enabled_isns = isn_bits; - if (subpriv->has_int_sce) - outb(isn_bits, subpriv->iobase); + if (layout->has_int_sce) + dio200_write8(dev, subpriv->ofs, isn_bits); } return retval; @@ -642,6 +867,7 @@ dio200_inttrig_start_intr(struct comedi_device *dev, struct comedi_subdevice *s, static int dio200_handle_read_intr(struct comedi_device *dev, struct comedi_subdevice *s) { + const struct dio200_layout *layout = dio200_dev_layout(dev); struct dio200_subdev_intr *subpriv = s->private; unsigned triggered; unsigned intstat; @@ -653,7 +879,7 @@ static int dio200_handle_read_intr(struct comedi_device *dev, spin_lock_irqsave(&subpriv->spinlock, flags); oldevents = s->async->events; - if (subpriv->has_int_sce) { + if (layout->has_int_sce) { /* * Collect interrupt sources that have triggered and disable * them temporarily. Loop around until no extra interrupt @@ -665,11 +891,11 @@ static int dio200_handle_read_intr(struct comedi_device *dev, * loop in case of misconfiguration. */ cur_enabled = subpriv->enabled_isns; - while ((intstat = (inb(subpriv->iobase) & subpriv->valid_isns - & ~triggered)) != 0) { + while ((intstat = (dio200_read8(dev, subpriv->ofs) & + subpriv->valid_isns & ~triggered)) != 0) { triggered |= intstat; cur_enabled &= ~triggered; - outb(cur_enabled, subpriv->iobase); + dio200_write8(dev, subpriv->ofs, cur_enabled); } } else { /* @@ -687,8 +913,8 @@ static int dio200_handle_read_intr(struct comedi_device *dev, * Reenable them NOW to minimize the time they are disabled. */ cur_enabled = subpriv->enabled_isns; - if (subpriv->has_int_sce) - outb(cur_enabled, subpriv->iobase); + if (layout->has_int_sce) + dio200_write8(dev, subpriv->ofs, cur_enabled); if (subpriv->active) { /* @@ -794,41 +1020,19 @@ dio200_subdev_intr_cmdtest(struct comedi_device *dev, if (err) return 2; - /* step 3: make sure arguments are trivially compatible */ + /* Step 3: check if arguments are trivially valid */ - /* cmd->start_src == TRIG_NOW || cmd->start_src == TRIG_INT */ - if (cmd->start_arg != 0) { - cmd->start_arg = 0; - err++; - } - - /* cmd->scan_begin_src == TRIG_EXT */ - if (cmd->scan_begin_arg != 0) { - cmd->scan_begin_arg = 0; - err++; - } - - /* cmd->convert_src == TRIG_NOW */ - if (cmd->convert_arg != 0) { - cmd->convert_arg = 0; - err++; - } - - /* cmd->scan_end_src == TRIG_COUNT */ - if (cmd->scan_end_arg != cmd->chanlist_len) { - cmd->scan_end_arg = cmd->chanlist_len; - err++; - } + err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0); + err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0); + err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0); + err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len); switch (cmd->stop_src) { case TRIG_COUNT: /* any count allowed */ break; case TRIG_NONE: - if (cmd->stop_arg != 0) { - cmd->stop_arg = 0; - err++; - } + err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0); break; default: break; @@ -894,9 +1098,9 @@ static int dio200_subdev_intr_cmd(struct comedi_device *dev, */ static int dio200_subdev_intr_init(struct comedi_device *dev, struct comedi_subdevice *s, - unsigned long iobase, unsigned valid_isns, - int has_int_sce) + unsigned int offset, unsigned valid_isns) { + const struct dio200_layout *layout = dio200_dev_layout(dev); struct dio200_subdev_intr *subpriv; subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL); @@ -904,18 +1108,18 @@ dio200_subdev_intr_init(struct comedi_device *dev, struct comedi_subdevice *s, dev_err(dev->class_dev, "error! out of memory!\n"); return -ENOMEM; } - subpriv->iobase = iobase; - subpriv->has_int_sce = has_int_sce; + subpriv->ofs = offset; subpriv->valid_isns = valid_isns; spin_lock_init(&subpriv->spinlock); - if (has_int_sce) - outb(0, subpriv->iobase); /* Disable interrupt sources. */ + if (layout->has_int_sce) + /* Disable interrupt sources. */ + dio200_write8(dev, subpriv->ofs, 0); s->private = subpriv; s->type = COMEDI_SUBD_DI; s->subdev_flags = SDF_READABLE | SDF_CMD_READ; - if (has_int_sce) { + if (layout->has_int_sce) { s->n_chan = DIO200_MAX_ISNS; s->len_chanlist = DIO200_MAX_ISNS; } else { @@ -968,6 +1172,73 @@ static irqreturn_t dio200_interrupt(int irq, void *d) } /* + * Read an '8254' counter subdevice channel. + */ +static unsigned int +dio200_subdev_8254_read_chan(struct comedi_device *dev, + struct comedi_subdevice *s, unsigned int chan) +{ + struct dio200_subdev_8254 *subpriv = s->private; + unsigned int val; + + /* latch counter */ + val = chan << 6; + dio200_write8(dev, subpriv->ofs + i8254_control_reg, val); + /* read lsb, msb */ + val = dio200_read8(dev, subpriv->ofs + chan); + val += dio200_read8(dev, subpriv->ofs + chan) << 8; + return val; +} + +/* + * Write an '8254' subdevice channel. + */ +static void +dio200_subdev_8254_write_chan(struct comedi_device *dev, + struct comedi_subdevice *s, unsigned int chan, + unsigned int count) +{ + struct dio200_subdev_8254 *subpriv = s->private; + + /* write lsb, msb */ + dio200_write8(dev, subpriv->ofs + chan, count & 0xff); + dio200_write8(dev, subpriv->ofs + chan, (count >> 8) & 0xff); +} + +/* + * Set mode of an '8254' subdevice channel. + */ +static void +dio200_subdev_8254_set_mode(struct comedi_device *dev, + struct comedi_subdevice *s, unsigned int chan, + unsigned int mode) +{ + struct dio200_subdev_8254 *subpriv = s->private; + unsigned int byte; + + byte = chan << 6; + byte |= 0x30; /* access order: lsb, msb */ + byte |= (mode & 0xf); /* counter mode and BCD|binary */ + dio200_write8(dev, subpriv->ofs + i8254_control_reg, byte); +} + +/* + * Read status byte of an '8254' counter subdevice channel. + */ +static unsigned int +dio200_subdev_8254_status(struct comedi_device *dev, + struct comedi_subdevice *s, unsigned int chan) +{ + struct dio200_subdev_8254 *subpriv = s->private; + + /* latch status */ + dio200_write8(dev, subpriv->ofs + i8254_control_reg, + 0xe0 | (2 << chan)); + /* read status */ + return dio200_read8(dev, subpriv->ofs + chan); +} + +/* * Handle 'insn_read' for an '8254' counter subdevice. */ static int @@ -976,13 +1247,15 @@ dio200_subdev_8254_read(struct comedi_device *dev, struct comedi_subdevice *s, { struct dio200_subdev_8254 *subpriv = s->private; int chan = CR_CHAN(insn->chanspec); + unsigned int n; unsigned long flags; - spin_lock_irqsave(&subpriv->spinlock, flags); - data[0] = i8254_read(subpriv->iobase, 0, chan); - spin_unlock_irqrestore(&subpriv->spinlock, flags); - - return 1; + for (n = 0; n < insn->n; n++) { + spin_lock_irqsave(&subpriv->spinlock, flags); + data[n] = dio200_subdev_8254_read_chan(dev, s, chan); + spin_unlock_irqrestore(&subpriv->spinlock, flags); + } + return insn->n; } /* @@ -994,34 +1267,40 @@ dio200_subdev_8254_write(struct comedi_device *dev, struct comedi_subdevice *s, { struct dio200_subdev_8254 *subpriv = s->private; int chan = CR_CHAN(insn->chanspec); + unsigned int n; unsigned long flags; - spin_lock_irqsave(&subpriv->spinlock, flags); - i8254_write(subpriv->iobase, 0, chan, data[0]); - spin_unlock_irqrestore(&subpriv->spinlock, flags); - - return 1; + for (n = 0; n < insn->n; n++) { + spin_lock_irqsave(&subpriv->spinlock, flags); + dio200_subdev_8254_write_chan(dev, s, chan, data[n]); + spin_unlock_irqrestore(&subpriv->spinlock, flags); + } + return insn->n; } /* * Set gate source for an '8254' counter subdevice channel. */ static int -dio200_set_gate_src(struct dio200_subdev_8254 *subpriv, - unsigned int counter_number, unsigned int gate_src) +dio200_subdev_8254_set_gate_src(struct comedi_device *dev, + struct comedi_subdevice *s, + unsigned int counter_number, + unsigned int gate_src) { + const struct dio200_layout *layout = dio200_dev_layout(dev); + struct dio200_subdev_8254 *subpriv = s->private; unsigned char byte; - if (!subpriv->has_clk_gat_sce) + if (!layout->has_clk_gat_sce) return -1; if (counter_number > 2) return -1; - if (gate_src > 7) + if (gate_src > (layout->has_enhancements ? 31 : 7)) return -1; subpriv->gate_src[counter_number] = gate_src; - byte = GAT_SCE(subpriv->which, counter_number, gate_src); - outb(byte, subpriv->gat_sce_iobase); + byte = gat_sce(subpriv->which, counter_number, gate_src); + dio200_write8(dev, subpriv->gat_sce_ofs, byte); return 0; } @@ -1030,10 +1309,14 @@ dio200_set_gate_src(struct dio200_subdev_8254 *subpriv, * Get gate source for an '8254' counter subdevice channel. */ static int -dio200_get_gate_src(struct dio200_subdev_8254 *subpriv, - unsigned int counter_number) +dio200_subdev_8254_get_gate_src(struct comedi_device *dev, + struct comedi_subdevice *s, + unsigned int counter_number) { - if (!subpriv->has_clk_gat_sce) + const struct dio200_layout *layout = dio200_dev_layout(dev); + struct dio200_subdev_8254 *subpriv = s->private; + + if (!layout->has_clk_gat_sce) return -1; if (counter_number > 2) return -1; @@ -1045,21 +1328,25 @@ dio200_get_gate_src(struct dio200_subdev_8254 *subpriv, * Set clock source for an '8254' counter subdevice channel. */ static int -dio200_set_clock_src(struct dio200_subdev_8254 *subpriv, - unsigned int counter_number, unsigned int clock_src) +dio200_subdev_8254_set_clock_src(struct comedi_device *dev, + struct comedi_subdevice *s, + unsigned int counter_number, + unsigned int clock_src) { + const struct dio200_layout *layout = dio200_dev_layout(dev); + struct dio200_subdev_8254 *subpriv = s->private; unsigned char byte; - if (!subpriv->has_clk_gat_sce) + if (!layout->has_clk_gat_sce) return -1; if (counter_number > 2) return -1; - if (clock_src > 7) + if (clock_src > (layout->has_enhancements ? 31 : 7)) return -1; subpriv->clock_src[counter_number] = clock_src; - byte = CLK_SCE(subpriv->which, counter_number, clock_src); - outb(byte, subpriv->clk_sce_iobase); + byte = clk_sce(subpriv->which, counter_number, clock_src); + dio200_write8(dev, subpriv->clk_sce_ofs, byte); return 0; } @@ -1068,12 +1355,16 @@ dio200_set_clock_src(struct dio200_subdev_8254 *subpriv, * Get clock source for an '8254' counter subdevice channel. */ static int -dio200_get_clock_src(struct dio200_subdev_8254 *subpriv, - unsigned int counter_number, unsigned int *period_ns) +dio200_subdev_8254_get_clock_src(struct comedi_device *dev, + struct comedi_subdevice *s, + unsigned int counter_number, + unsigned int *period_ns) { + const struct dio200_layout *layout = dio200_dev_layout(dev); + struct dio200_subdev_8254 *subpriv = s->private; unsigned clock_src; - if (!subpriv->has_clk_gat_sce) + if (!layout->has_clk_gat_sce) return -1; if (counter_number > 2) return -1; @@ -1098,20 +1389,21 @@ dio200_subdev_8254_config(struct comedi_device *dev, struct comedi_subdevice *s, spin_lock_irqsave(&subpriv->spinlock, flags); switch (data[0]) { case INSN_CONFIG_SET_COUNTER_MODE: - ret = i8254_set_mode(subpriv->iobase, 0, chan, data[1]); - if (ret < 0) + if (data[1] > (I8254_MODE5 | I8254_BINARY)) ret = -EINVAL; + else + dio200_subdev_8254_set_mode(dev, s, chan, data[1]); break; case INSN_CONFIG_8254_READ_STATUS: - data[1] = i8254_status(subpriv->iobase, 0, chan); + data[1] = dio200_subdev_8254_status(dev, s, chan); break; case INSN_CONFIG_SET_GATE_SRC: - ret = dio200_set_gate_src(subpriv, chan, data[2]); + ret = dio200_subdev_8254_set_gate_src(dev, s, chan, data[2]); if (ret < 0) ret = -EINVAL; break; case INSN_CONFIG_GET_GATE_SRC: - ret = dio200_get_gate_src(subpriv, chan); + ret = dio200_subdev_8254_get_gate_src(dev, s, chan); if (ret < 0) { ret = -EINVAL; break; @@ -1119,12 +1411,12 @@ dio200_subdev_8254_config(struct comedi_device *dev, struct comedi_subdevice *s, data[2] = ret; break; case INSN_CONFIG_SET_CLOCK_SRC: - ret = dio200_set_clock_src(subpriv, chan, data[1]); + ret = dio200_subdev_8254_set_clock_src(dev, s, chan, data[1]); if (ret < 0) ret = -EINVAL; break; case INSN_CONFIG_GET_CLOCK_SRC: - ret = dio200_get_clock_src(subpriv, chan, &data[2]); + ret = dio200_subdev_8254_get_clock_src(dev, s, chan, &data[2]); if (ret < 0) { ret = -EINVAL; break; @@ -1141,15 +1433,12 @@ dio200_subdev_8254_config(struct comedi_device *dev, struct comedi_subdevice *s, /* * This function initializes an '8254' counter subdevice. - * - * Note: iobase is the base address of the board, not the subdevice; - * offset is the offset to the 8254 chip. */ static int dio200_subdev_8254_init(struct comedi_device *dev, struct comedi_subdevice *s, - unsigned long iobase, unsigned offset, - int has_clk_gat_sce) + unsigned int offset) { + const struct dio200_layout *layout = dio200_dev_layout(dev); struct dio200_subdev_8254 *subpriv; unsigned int chan; @@ -1169,27 +1458,24 @@ dio200_subdev_8254_init(struct comedi_device *dev, struct comedi_subdevice *s, s->insn_config = dio200_subdev_8254_config; spin_lock_init(&subpriv->spinlock); - subpriv->iobase = offset + iobase; - subpriv->has_clk_gat_sce = has_clk_gat_sce; - if (has_clk_gat_sce) { + subpriv->ofs = offset; + if (layout->has_clk_gat_sce) { /* Derive CLK_SCE and GAT_SCE register offsets from * 8254 offset. */ - subpriv->clk_sce_iobase = - DIO200_XCLK_SCE + (offset >> 3) + iobase; - subpriv->gat_sce_iobase = - DIO200_XGAT_SCE + (offset >> 3) + iobase; + subpriv->clk_sce_ofs = DIO200_XCLK_SCE + (offset >> 3); + subpriv->gat_sce_ofs = DIO200_XGAT_SCE + (offset >> 3); subpriv->which = (offset >> 2) & 1; } /* Initialize channels. */ for (chan = 0; chan < 3; chan++) { - i8254_set_mode(subpriv->iobase, 0, chan, - I8254_MODE0 | I8254_BINARY); - if (subpriv->has_clk_gat_sce) { + dio200_subdev_8254_set_mode(dev, s, chan, + I8254_MODE0 | I8254_BINARY); + if (layout->has_clk_gat_sce) { /* Gate source 0 is VCC (logic 1). */ - dio200_set_gate_src(subpriv, chan, 0); + dio200_subdev_8254_set_gate_src(dev, s, chan, 0); /* Clock source 0 is the dedicated clock input. */ - dio200_set_clock_src(subpriv, chan, 0); + dio200_subdev_8254_set_clock_src(dev, s, chan, 0); } } @@ -1207,16 +1493,294 @@ dio200_subdev_8254_cleanup(struct comedi_device *dev, kfree(subpriv); } +/* + * This function sets I/O directions for an '8255' DIO subdevice. + */ +static void dio200_subdev_8255_set_dir(struct comedi_device *dev, + struct comedi_subdevice *s) +{ + struct dio200_subdev_8255 *subpriv = s->private; + int config; + + config = CR_CW; + /* 1 in io_bits indicates output, 1 in config indicates input */ + if (!(s->io_bits & 0x0000ff)) + config |= CR_A_IO; + if (!(s->io_bits & 0x00ff00)) + config |= CR_B_IO; + if (!(s->io_bits & 0x0f0000)) + config |= CR_C_LO_IO; + if (!(s->io_bits & 0xf00000)) + config |= CR_C_HI_IO; + dio200_write8(dev, subpriv->ofs + 3, config); +} + +/* + * Handle 'insn_bits' for an '8255' DIO subdevice. + */ +static int dio200_subdev_8255_bits(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, unsigned int *data) +{ + struct dio200_subdev_8255 *subpriv = s->private; + + if (data[0]) { + s->state &= ~data[0]; + s->state |= (data[0] & data[1]); + if (data[0] & 0xff) + dio200_write8(dev, subpriv->ofs, s->state & 0xff); + if (data[0] & 0xff00) + dio200_write8(dev, subpriv->ofs + 1, + (s->state >> 8) & 0xff); + if (data[0] & 0xff0000) + dio200_write8(dev, subpriv->ofs + 2, + (s->state >> 16) & 0xff); + } + data[1] = dio200_read8(dev, subpriv->ofs); + data[1] |= dio200_read8(dev, subpriv->ofs + 1) << 8; + data[1] |= dio200_read8(dev, subpriv->ofs + 2) << 16; + return 2; +} + +/* + * Handle 'insn_config' for an '8255' DIO subdevice. + */ +static int dio200_subdev_8255_config(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + unsigned int mask; + unsigned int bits; + + mask = 1 << CR_CHAN(insn->chanspec); + if (mask & 0x0000ff) + bits = 0x0000ff; + else if (mask & 0x00ff00) + bits = 0x00ff00; + else if (mask & 0x0f0000) + bits = 0x0f0000; + else + bits = 0xf00000; + switch (data[0]) { + case INSN_CONFIG_DIO_INPUT: + s->io_bits &= ~bits; + break; + case INSN_CONFIG_DIO_OUTPUT: + s->io_bits |= bits; + break; + case INSN_CONFIG_DIO_QUERY: + data[1] = (s->io_bits & bits) ? COMEDI_OUTPUT : COMEDI_INPUT; + return insn->n; + break; + default: + return -EINVAL; + } + dio200_subdev_8255_set_dir(dev, s); + return 1; +} + +/* + * This function initializes an '8255' DIO subdevice. + * + * offset is the offset to the 8255 chip. + */ +static int dio200_subdev_8255_init(struct comedi_device *dev, + struct comedi_subdevice *s, + unsigned int offset) +{ + struct dio200_subdev_8255 *subpriv; + + subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL); + if (!subpriv) + return -ENOMEM; + subpriv->ofs = offset; + s->private = subpriv; + s->type = COMEDI_SUBD_DIO; + s->subdev_flags = SDF_READABLE | SDF_WRITABLE; + s->n_chan = 24; + s->range_table = &range_digital; + s->maxdata = 1; + s->insn_bits = dio200_subdev_8255_bits; + s->insn_config = dio200_subdev_8255_config; + s->state = 0; + s->io_bits = 0; + dio200_subdev_8255_set_dir(dev, s); + return 0; +} + +/* + * This function cleans up an '8255' DIO subdevice. + */ +static void dio200_subdev_8255_cleanup(struct comedi_device *dev, + struct comedi_subdevice *s) +{ + struct dio200_subdev_8255 *subpriv = s->private; + + kfree(subpriv); +} + +/* + * Handle 'insn_read' for a timer subdevice. + */ +static int dio200_subdev_timer_read(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + unsigned int n; + + for (n = 0; n < insn->n; n++) + data[n] = dio200_read32(dev, DIO200_TS_COUNT); + return n; +} + +/* + * Reset timer subdevice. + */ +static void dio200_subdev_timer_reset(struct comedi_device *dev, + struct comedi_subdevice *s) +{ + unsigned int clock; + + clock = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK; + dio200_write32(dev, DIO200_TS_CONFIG, clock | TS_CONFIG_RESET); + dio200_write32(dev, DIO200_TS_CONFIG, clock); +} + +/* + * Get timer subdevice clock source and period. + */ +static void dio200_subdev_timer_get_clock_src(struct comedi_device *dev, + struct comedi_subdevice *s, + unsigned int *src, + unsigned int *period) +{ + unsigned int clk; + + clk = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK; + *src = clk; + *period = (clk < ARRAY_SIZE(ts_clock_period)) ? + ts_clock_period[clk] : 0; +} + +/* + * Set timer subdevice clock source. + */ +static int dio200_subdev_timer_set_clock_src(struct comedi_device *dev, + struct comedi_subdevice *s, + unsigned int src) +{ + if (src > TS_CONFIG_MAX_CLK_SRC) + return -EINVAL; + dio200_write32(dev, DIO200_TS_CONFIG, src); + return 0; +} + +/* + * Handle 'insn_config' for a timer subdevice. + */ +static int dio200_subdev_timer_config(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + int ret = 0; + + switch (data[0]) { + case INSN_CONFIG_RESET: + dio200_subdev_timer_reset(dev, s); + break; + case INSN_CONFIG_SET_CLOCK_SRC: + ret = dio200_subdev_timer_set_clock_src(dev, s, data[1]); + if (ret < 0) + ret = -EINVAL; + break; + case INSN_CONFIG_GET_CLOCK_SRC: + dio200_subdev_timer_get_clock_src(dev, s, &data[1], &data[2]); + break; + default: + ret = -EINVAL; + break; + } + return ret < 0 ? ret : insn->n; +} + +/* + * This function initializes a timer subdevice. + * + * Uses the timestamp timer registers. There is only one timestamp timer. + */ +static int dio200_subdev_timer_init(struct comedi_device *dev, + struct comedi_subdevice *s) +{ + s->type = COMEDI_SUBD_TIMER; + s->subdev_flags = SDF_READABLE | SDF_LSAMPL; + s->n_chan = 1; + s->maxdata = 0xFFFFFFFF; + s->insn_read = dio200_subdev_timer_read; + s->insn_config = dio200_subdev_timer_config; + return 0; +} + +/* + * This function cleans up a timer subdevice. + */ +static void dio200_subdev_timer_cleanup(struct comedi_device *dev, + struct comedi_subdevice *s) +{ + /* Nothing to do. */ +} + +/* + * This function does some special set-up for the PCIe boards + * PCIe215, PCIe236, PCIe296. + */ +static int dio200_pcie_board_setup(struct comedi_device *dev) +{ + struct pci_dev *pcidev = comedi_to_pci_dev(dev); + void __iomem *brbase; + resource_size_t brlen; + + /* + * The board uses Altera Cyclone IV with PCI-Express hard IP. + * The FPGA configuration has the PCI-Express Avalon-MM Bridge + * Control registers in PCI BAR 0, offset 0, and the length of + * these registers is 0x4000. + * + * We need to write 0x80 to the "Avalon-MM to PCI-Express Interrupt + * Enable" register at offset 0x50 to allow generation of PCIe + * interrupts when RXmlrq_i is asserted in the SOPC Builder system. + */ + brlen = pci_resource_len(pcidev, 0); + if (brlen < 0x4000 || + !(pci_resource_flags(pcidev, 0) & IORESOURCE_MEM)) { + dev_err(dev->class_dev, "error! bad PCI region!\n"); + return -EINVAL; + } + brbase = ioremap_nocache(pci_resource_start(pcidev, 0), brlen); + if (!brbase) { + dev_err(dev->class_dev, "error! failed to map registers!\n"); + return -ENOMEM; + } + writel(0x80, brbase + 0x50); + iounmap(brbase); + /* Enable "enhanced" features of board. */ + dio200_write8(dev, DIO200_ENHANCE, 1); + return 0; +} + static void dio200_report_attach(struct comedi_device *dev, unsigned int irq) { const struct dio200_board *thisboard = comedi_board(dev); + struct dio200_private *devpriv = dev->private; struct pci_dev *pcidev = comedi_to_pci_dev(dev); char tmpbuf[60]; int tmplen; if (is_isa_board(thisboard)) tmplen = scnprintf(tmpbuf, sizeof(tmpbuf), - "(base %#lx) ", dev->iobase); + "(base %#lx) ", devpriv->io.u.iobase); else if (is_pci_board(thisboard)) tmplen = scnprintf(tmpbuf, sizeof(tmpbuf), "(pci %s) ", pci_name(pcidev)); @@ -1232,20 +1796,18 @@ static void dio200_report_attach(struct comedi_device *dev, unsigned int irq) dev_info(dev->class_dev, "%s %sattached\n", dev->board_name, tmpbuf); } -static int dio200_common_attach(struct comedi_device *dev, unsigned long iobase, - unsigned int irq, unsigned long req_irq_flags) +static int dio200_common_attach(struct comedi_device *dev, unsigned int irq, + unsigned long req_irq_flags) { const struct dio200_board *thisboard = comedi_board(dev); struct dio200_private *devpriv = dev->private; - const struct dio200_layout_struct *layout = - &dio200_layouts[thisboard->layout]; + const struct dio200_layout *layout = dio200_board_layout(thisboard); struct comedi_subdevice *s; int sdx; unsigned int n; int ret; devpriv->intr_sd = -1; - dev->iobase = iobase; dev->board_name = thisboard->name; ret = comedi_alloc_subdevices(dev, layout->n_subdevs); @@ -1257,16 +1819,15 @@ static int dio200_common_attach(struct comedi_device *dev, unsigned long iobase, switch (layout->sdtype[n]) { case sd_8254: /* counter subdevice (8254) */ - ret = dio200_subdev_8254_init(dev, s, iobase, - layout->sdinfo[n], - layout->has_clk_gat_sce); + ret = dio200_subdev_8254_init(dev, s, + layout->sdinfo[n]); if (ret < 0) return ret; break; case sd_8255: /* digital i/o subdevice (8255) */ - ret = subdev_8255_init(dev, s, NULL, - iobase + layout->sdinfo[n]); + ret = dio200_subdev_8255_init(dev, s, + layout->sdinfo[n]); if (ret < 0) return ret; break; @@ -1274,11 +1835,9 @@ static int dio200_common_attach(struct comedi_device *dev, unsigned long iobase, /* 'INTERRUPT' subdevice */ if (irq) { ret = dio200_subdev_intr_init(dev, s, - iobase + DIO200_INT_SCE, - layout->sdinfo[n], - layout-> - has_int_sce); + layout->sdinfo[n] + ); if (ret < 0) return ret; devpriv->intr_sd = n; @@ -1286,6 +1845,16 @@ static int dio200_common_attach(struct comedi_device *dev, unsigned long iobase, s->type = COMEDI_SUBD_UNUSED; } break; + case sd_timer: + /* Only on PCIe boards. */ + if (DO_PCI) { + ret = dio200_subdev_timer_init(dev, s); + if (ret < 0) + return ret; + } else { + s->type = COMEDI_SUBD_UNUSED; + } + break; default: s->type = COMEDI_SUBD_UNUSED; break; @@ -1307,24 +1876,6 @@ static int dio200_common_attach(struct comedi_device *dev, unsigned long iobase, return 1; } -static int dio200_pci_common_attach(struct comedi_device *dev, - struct pci_dev *pci_dev) -{ - unsigned long iobase; - int ret; - - comedi_set_hw_dev(dev, &pci_dev->dev); - - ret = comedi_pci_enable(pci_dev, DIO200_DRIVER_NAME); - if (ret < 0) { - dev_err(dev->class_dev, - "error! cannot enable PCI device and request regions!\n"); - return ret; - } - iobase = pci_resource_start(pci_dev, 2); - return dio200_common_attach(dev, iobase, pci_dev->irq, IRQF_SHARED); -} - /* * Attach is called by the Comedi core to configure the driver * for a particular board. If you specified a board_name array @@ -1334,15 +1885,15 @@ static int dio200_pci_common_attach(struct comedi_device *dev, static int dio200_attach(struct comedi_device *dev, struct comedi_devconfig *it) { const struct dio200_board *thisboard = comedi_board(dev); + struct dio200_private *devpriv; int ret; dev_info(dev->class_dev, DIO200_DRIVER_NAME ": attach\n"); - ret = alloc_private(dev, sizeof(struct dio200_private)); - if (ret < 0) { - dev_err(dev->class_dev, "error! out of memory!\n"); - return ret; - } + devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL); + if (!devpriv) + return -ENOMEM; + dev->private = devpriv; /* Process options and reserve resources according to bus type. */ if (is_isa_board(thisboard)) { @@ -1351,17 +1902,17 @@ static int dio200_attach(struct comedi_device *dev, struct comedi_devconfig *it) iobase = it->options[0]; irq = it->options[1]; - ret = dio200_request_region(dev, iobase, DIO200_IO_SIZE); + ret = dio200_request_region(dev, iobase, thisboard->mainsize); if (ret < 0) return ret; - return dio200_common_attach(dev, iobase, irq, 0); + devpriv->io.u.iobase = iobase; + devpriv->io.regtype = io_regtype; + return dio200_common_attach(dev, irq, 0); } else if (is_pci_board(thisboard)) { - struct pci_dev *pci_dev; - - pci_dev = dio200_find_pci_dev(dev, it); - if (!pci_dev) - return -EIO; - return dio200_pci_common_attach(dev, pci_dev); + dev_err(dev->class_dev, + "Manual configuration of PCI board '%s' is not supported\n", + thisboard->name); + return -EIO; } else { dev_err(dev->class_dev, DIO200_DRIVER_NAME ": BUG! cannot determine board type!\n"); @@ -1370,13 +1921,18 @@ static int dio200_attach(struct comedi_device *dev, struct comedi_devconfig *it) } /* - * The attach_pci hook (if non-NULL) is called at PCI probe time in preference - * to the "manual" attach hook. dev->board_ptr is NULL on entry. There should - * be a board entry matching the supplied PCI device. + * The auto_attach hook is called at PCI probe time via + * comedi_pci_auto_config(). dev->board_ptr is NULL on entry. + * There should be a board entry matching the supplied PCI device. */ -static int __devinit dio200_attach_pci(struct comedi_device *dev, - struct pci_dev *pci_dev) +static int dio200_auto_attach(struct comedi_device *dev, + unsigned long context_unused) { + struct pci_dev *pci_dev = comedi_to_pci_dev(dev); + const struct dio200_board *thisboard; + struct dio200_private *devpriv; + resource_size_t base, len; + unsigned int bar; int ret; if (!DO_PCI) @@ -1384,38 +1940,71 @@ static int __devinit dio200_attach_pci(struct comedi_device *dev, dev_info(dev->class_dev, DIO200_DRIVER_NAME ": attach pci %s\n", pci_name(pci_dev)); - ret = alloc_private(dev, sizeof(struct dio200_private)); - if (ret < 0) { - dev_err(dev->class_dev, "error! out of memory!\n"); - return ret; - } + + devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL); + if (!devpriv) + return -ENOMEM; + dev->private = devpriv; + dev->board_ptr = dio200_find_pci_board(pci_dev); if (dev->board_ptr == NULL) { dev_err(dev->class_dev, "BUG! cannot determine board type!\n"); return -EINVAL; } - /* - * Need to 'get' the PCI device to match the 'put' in dio200_detach(). - * TODO: Remove the pci_dev_get() and matching pci_dev_put() once - * support for manual attachment of PCI devices via dio200_attach() - * has been removed. - */ - pci_dev_get(pci_dev); - return dio200_pci_common_attach(dev, pci_dev); + thisboard = comedi_board(dev); + ret = comedi_pci_enable(pci_dev, DIO200_DRIVER_NAME); + if (ret < 0) { + dev_err(dev->class_dev, + "error! cannot enable PCI device and request regions!\n"); + return ret; + } + bar = thisboard->mainbar; + base = pci_resource_start(pci_dev, bar); + len = pci_resource_len(pci_dev, bar); + if (len < thisboard->mainsize) { + dev_err(dev->class_dev, "error! PCI region size too small!\n"); + return -EINVAL; + } + if ((pci_resource_flags(pci_dev, bar) & IORESOURCE_MEM) != 0) { + devpriv->io.u.membase = ioremap_nocache(base, len); + if (!devpriv->io.u.membase) { + dev_err(dev->class_dev, + "error! cannot remap registers\n"); + return -ENOMEM; + } + devpriv->io.regtype = mmio_regtype; + } else { + devpriv->io.u.iobase = (unsigned long)base; + devpriv->io.regtype = io_regtype; + } + switch (thisboard->model) + { + case pcie215_model: + case pcie236_model: + case pcie296_model: + ret = dio200_pcie_board_setup(dev); + if (ret < 0) + return ret; + break; + default: + break; + } + return dio200_common_attach(dev, pci_dev->irq, IRQF_SHARED); } static void dio200_detach(struct comedi_device *dev) { const struct dio200_board *thisboard = comedi_board(dev); - const struct dio200_layout_struct *layout; + struct dio200_private *devpriv = dev->private; + const struct dio200_layout *layout; unsigned n; - if (!thisboard) + if (!thisboard || !devpriv) return; if (dev->irq) free_irq(dev->irq, dev); if (dev->subdevices) { - layout = &dio200_layouts[thisboard->layout]; + layout = dio200_board_layout(thisboard); for (n = 0; n < dev->n_subdevices; n++) { struct comedi_subdevice *s = &dev->subdevices[n]; switch (layout->sdtype[n]) { @@ -1423,25 +2012,33 @@ static void dio200_detach(struct comedi_device *dev) dio200_subdev_8254_cleanup(dev, s); break; case sd_8255: - subdev_8255_cleanup(dev, s); + dio200_subdev_8255_cleanup(dev, s); break; case sd_intr: dio200_subdev_intr_cleanup(dev, s); break; + case sd_timer: + /* Only on PCIe boards. */ + if (DO_PCI) + dio200_subdev_timer_cleanup(dev, s); + break; default: break; } } } if (is_isa_board(thisboard)) { - if (dev->iobase) - release_region(dev->iobase, DIO200_IO_SIZE); + if (devpriv->io.regtype == io_regtype) + release_region(devpriv->io.u.iobase, + thisboard->mainsize); } else if (is_pci_board(thisboard)) { struct pci_dev *pcidev = comedi_to_pci_dev(dev); if (pcidev) { - if (dev->iobase) + if (devpriv->io.regtype != no_regtype) { + if (devpriv->io.regtype == mmio_regtype) + iounmap(devpriv->io.u.membase); comedi_pci_disable(pcidev); - pci_dev_put(pcidev); + } } } } @@ -1456,7 +2053,7 @@ static struct comedi_driver amplc_dio200_driver = { .driver_name = DIO200_DRIVER_NAME, .module = THIS_MODULE, .attach = dio200_attach, - .attach_pci = dio200_attach_pci, + .auto_attach = dio200_auto_attach, .detach = dio200_detach, .board_name = &dio200_boards[0].name, .offset = sizeof(struct dio200_board), @@ -1467,19 +2064,22 @@ static struct comedi_driver amplc_dio200_driver = { static DEFINE_PCI_DEVICE_TABLE(dio200_pci_table) = { { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI215) }, { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI272) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE236) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE215) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE296) }, {0} }; MODULE_DEVICE_TABLE(pci, dio200_pci_table); -static int __devinit amplc_dio200_pci_probe(struct pci_dev *dev, +static int amplc_dio200_pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) { return comedi_pci_auto_config(dev, &lc_dio200_driver); } -static void __devexit amplc_dio200_pci_remove(struct pci_dev *dev) +static void amplc_dio200_pci_remove(struct pci_dev *dev) { comedi_pci_auto_unconfig(dev); } @@ -1488,7 +2088,7 @@ static struct pci_driver amplc_dio200_pci_driver = { .name = DIO200_DRIVER_NAME, .id_table = dio200_pci_table, .probe = &lc_dio200_pci_probe, - .remove = __devexit_p(&lc_dio200_pci_remove) + .remove = &lc_dio200_pci_remove }; module_comedi_pci_driver(amplc_dio200_driver, amplc_dio200_pci_driver); #else |