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path: root/drivers/staging/comedi/drivers/mite.c
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Diffstat (limited to 'drivers/staging/comedi/drivers/mite.c')
-rw-r--r--drivers/staging/comedi/drivers/mite.c285
1 files changed, 135 insertions, 150 deletions
diff --git a/drivers/staging/comedi/drivers/mite.c b/drivers/staging/comedi/drivers/mite.c
index a93166d6a8f8..e27850f628ce 100644
--- a/drivers/staging/comedi/drivers/mite.c
+++ b/drivers/staging/comedi/drivers/mite.c
@@ -49,6 +49,8 @@
/* #define USE_KMALLOC */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
#include "mite.h"
#include "comedi_fc.h"
@@ -59,52 +61,38 @@
#define PCI_DAQ_SIZE 4096
#define PCI_DAQ_SIZE_660X 8192
-struct mite_struct *mite_devices;
-EXPORT_SYMBOL(mite_devices);
-
#define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
-void mite_init(void)
+struct mite_struct *mite_alloc(struct pci_dev *pcidev)
{
- struct pci_dev *pcidev = NULL;
struct mite_struct *mite;
-
- for_each_pci_dev(pcidev) {
- if (pcidev->vendor == PCI_VENDOR_ID_NI) {
- unsigned i;
-
- mite = kzalloc(sizeof(*mite), GFP_KERNEL);
- if (!mite) {
- printk(KERN_ERR "mite: allocation failed\n");
- pci_dev_put(pcidev);
- return;
- }
- spin_lock_init(&mite->lock);
- mite->pcidev = pci_dev_get(pcidev);
- for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
- mite->channels[i].mite = mite;
- mite->channels[i].channel = i;
- mite->channels[i].done = 1;
- }
- mite->next = mite_devices;
- mite_devices = mite;
+ unsigned int i;
+
+ mite = kzalloc(sizeof(*mite), GFP_KERNEL);
+ if (mite) {
+ spin_lock_init(&mite->lock);
+ mite->pcidev = pcidev;
+ for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
+ mite->channels[i].mite = mite;
+ mite->channels[i].channel = i;
+ mite->channels[i].done = 1;
}
}
+ return mite;
}
+EXPORT_SYMBOL(mite_alloc);
static void dump_chip_signature(u32 csigr_bits)
{
- printk(KERN_INFO "mite: version = %i, type = %i, mite mode = %i,"
- "interface mode = %i\n",
- mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
- mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
- printk(KERN_INFO "mite: num channels = %i, write post fifo depth = %i,"
- "wins = %i, iowins = %i\n",
- mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
- mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
+ pr_info("version = %i, type = %i, mite mode = %i, interface mode = %i\n",
+ mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
+ mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
+ pr_info("num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n",
+ mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
+ mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
}
-unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
+static unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
{
unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel));
unsigned empty_count = (fcr_bits >> 16) & 0xff;
@@ -121,7 +109,8 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
unsigned unknown_dma_burst_bits;
if (comedi_pci_enable(mite->pcidev, "mite")) {
- printk(KERN_ERR "error enabling mite and requesting io regions\n");
+ dev_err(&mite->pcidev->dev,
+ "error enabling mite and requesting io regions\n");
return -EIO;
}
pci_set_master(mite->pcidev);
@@ -130,11 +119,10 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
mite->mite_phys_addr = addr;
mite->mite_io_addr = ioremap(addr, PCI_MITE_SIZE);
if (!mite->mite_io_addr) {
- printk(KERN_ERR "Failed to remap mite io memory address\n");
+ dev_err(&mite->pcidev->dev,
+ "Failed to remap mite io memory address\n");
return -ENOMEM;
}
- printk(KERN_INFO "MITE:0x%08llx mapped to %p ",
- (unsigned long long)mite->mite_phys_addr, mite->mite_io_addr);
addr = pci_resource_start(mite->pcidev, 1);
mite->daq_phys_addr = addr;
@@ -145,15 +133,15 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
*/
mite->daq_io_addr = ioremap(mite->daq_phys_addr, length);
if (!mite->daq_io_addr) {
- printk(KERN_ERR "Failed to remap daq io memory address\n");
+ dev_err(&mite->pcidev->dev,
+ "Failed to remap daq io memory address\n");
return -ENOMEM;
}
- printk(KERN_INFO "DAQ:0x%08llx mapped to %p\n",
- (unsigned long long)mite->daq_phys_addr, mite->daq_io_addr);
if (use_iodwbsr_1) {
writel(0, mite->mite_io_addr + MITE_IODWBSR);
- printk(KERN_INFO "mite: using I/O Window Base Size register 1\n");
+ dev_info(&mite->pcidev->dev,
+ "using I/O Window Base Size register 1\n");
writel(mite->daq_phys_addr | WENAB |
MITE_IODWBSR_1_WSIZE_bits(length),
mite->mite_io_addr + MITE_IODWBSR_1);
@@ -178,9 +166,9 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
mite->num_channels = mite_csigr_dmac(csigr_bits);
if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
- printk(KERN_WARNING "mite: bug? chip claims to have %i dma "
- "channels. Setting to %i.\n",
- mite->num_channels, MAX_MITE_DMA_CHANNELS);
+ dev_warn(&mite->pcidev->dev,
+ "mite: bug? chip claims to have %i dma channels. Setting to %i.\n",
+ mite->num_channels, MAX_MITE_DMA_CHANNELS);
mite->num_channels = MAX_MITE_DMA_CHANNELS;
}
dump_chip_signature(csigr_bits);
@@ -193,9 +181,7 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
mite->mite_io_addr + MITE_CHCR(i));
}
mite->fifo_size = mite_fifo_size(mite, 0);
- printk(KERN_INFO "mite: fifo size is %i.\n", mite->fifo_size);
- mite->used = 1;
-
+ dev_info(&mite->pcidev->dev, "fifo size is %i.\n", mite->fifo_size);
return 0;
}
EXPORT_SYMBOL(mite_setup2);
@@ -206,17 +192,6 @@ int mite_setup(struct mite_struct *mite)
}
EXPORT_SYMBOL(mite_setup);
-void mite_cleanup(void)
-{
- struct mite_struct *mite, *next;
-
- for (mite = mite_devices; mite; mite = next) {
- pci_dev_put(mite->pcidev);
- next = mite->next;
- kfree(mite);
- }
-}
-
void mite_unsetup(struct mite_struct *mite)
{
/* unsigned long offset, start, length; */
@@ -236,26 +211,43 @@ void mite_unsetup(struct mite_struct *mite)
comedi_pci_disable(mite->pcidev);
mite->mite_phys_addr = 0;
}
-
- mite->used = 0;
}
EXPORT_SYMBOL(mite_unsetup);
-void mite_list_devices(void)
+struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite)
+{
+ struct mite_dma_descriptor_ring *ring =
+ kmalloc(sizeof(struct mite_dma_descriptor_ring), GFP_KERNEL);
+
+ if (ring == NULL)
+ return ring;
+ ring->hw_dev = get_device(&mite->pcidev->dev);
+ if (ring->hw_dev == NULL) {
+ kfree(ring);
+ return NULL;
+ }
+ ring->n_links = 0;
+ ring->descriptors = NULL;
+ ring->descriptors_dma_addr = 0;
+ return ring;
+};
+EXPORT_SYMBOL(mite_alloc_ring);
+
+void mite_free_ring(struct mite_dma_descriptor_ring *ring)
{
- struct mite_struct *mite, *next;
-
- printk(KERN_INFO "Available NI device IDs:");
- if (mite_devices)
- for (mite = mite_devices; mite; mite = next) {
- next = mite->next;
- printk(KERN_INFO " 0x%04x", mite_device_id(mite));
- if (mite->used)
- printk(KERN_INFO "(used)");
+ if (ring) {
+ if (ring->descriptors) {
+ dma_free_coherent(ring->hw_dev,
+ ring->n_links *
+ sizeof(struct mite_dma_descriptor),
+ ring->descriptors,
+ ring->descriptors_dma_addr);
}
- printk(KERN_INFO "\n");
-}
-EXPORT_SYMBOL(mite_list_devices);
+ put_device(ring->hw_dev);
+ kfree(ring);
+ }
+};
+EXPORT_SYMBOL(mite_free_ring);
struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
struct
@@ -317,7 +309,7 @@ void mite_dma_arm(struct mite_channel *mite_chan)
int chor;
unsigned long flags;
- MDPRINTK("mite_dma_arm ch%i\n", channel);
+ MDPRINTK("mite_dma_arm ch%i\n", mite_chan->channel);
/*
* memory barrier is intended to insure any twiddling with the buffer
* is done before writing to the mite to arm dma transfer
@@ -365,7 +357,8 @@ int mite_buf_change(struct mite_dma_descriptor_ring *ring,
n_links * sizeof(struct mite_dma_descriptor),
&ring->descriptors_dma_addr, GFP_KERNEL);
if (!ring->descriptors) {
- printk(KERN_ERR "mite: ring buffer allocation failed\n");
+ dev_err(async->subdevice->device->class_dev,
+ "mite: ring buffer allocation failed\n");
return -ENOMEM;
}
ring->n_links = n_links;
@@ -442,8 +435,7 @@ void mite_prep_dma(struct mite_channel *mite_chan,
mcr |= CR_PSIZE32;
break;
default:
- printk(KERN_WARNING "mite: bug! invalid mem bit width for dma "
- "transfer\n");
+ pr_warn("bug! invalid mem bit width for dma transfer\n");
break;
}
writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
@@ -462,8 +454,7 @@ void mite_prep_dma(struct mite_channel *mite_chan,
dcr |= CR_PSIZE32;
break;
default:
- printk(KERN_WARNING "mite: bug! invalid dev bit width for dma "
- "transfer\n");
+ pr_warn("bug! invalid dev bit width for dma transfer\n");
break;
}
writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
@@ -483,7 +474,7 @@ void mite_prep_dma(struct mite_channel *mite_chan,
}
EXPORT_SYMBOL(mite_prep_dma);
-u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
+static u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
{
struct mite_struct *mite = mite_chan->mite;
return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel));
@@ -577,7 +568,8 @@ int mite_sync_input_dma(struct mite_channel *mite_chan,
nbytes = mite_bytes_written_to_memory_lb(mite_chan);
if ((int)(mite_bytes_written_to_memory_ub(mite_chan) -
old_alloc_count) > 0) {
- printk("mite: DMA overwrite of free area\n");
+ dev_warn(async->subdevice->device->class_dev,
+ "mite: DMA overwrite of free area\n");
async->events |= COMEDI_CB_OVERFLOW;
return -1;
}
@@ -621,7 +613,8 @@ int mite_sync_output_dma(struct mite_channel *mite_chan,
(int)(nbytes_ub - stop_count) > 0)
nbytes_ub = stop_count;
if ((int)(nbytes_ub - old_alloc_count) > 0) {
- printk(KERN_ERR "mite: DMA underrun\n");
+ dev_warn(async->subdevice->device->class_dev,
+ "mite: DMA underrun\n");
async->events |= COMEDI_CB_OVERFLOW;
return -1;
}
@@ -672,8 +665,6 @@ EXPORT_SYMBOL(mite_done);
#ifdef DEBUG_MITE
-static void mite_decode(char **bit_str, unsigned int bits);
-
/* names of bits in mite registers */
static const char *const mite_CHOR_strings[] = {
@@ -743,86 +734,80 @@ static const char *const mite_CHSR_strings[] = {
"28", "lpauses", "30", "int",
};
-void mite_dump_regs(struct mite_channel *mite_chan)
-{
- unsigned long mite_io_addr =
- (unsigned long)mite_chan->mite->mite_io_addr;
- unsigned long addr = 0;
- unsigned long temp = 0;
-
- printk(KERN_DEBUG "mite_dump_regs ch%i\n", mite_chan->channel);
- printk(KERN_DEBUG "mite address is =0x%08lx\n", mite_io_addr);
-
- addr = mite_io_addr + MITE_CHOR(channel);
- printk(KERN_DEBUG "mite status[CHOR]at 0x%08lx =0x%08lx\n", addr,
- temp = readl(addr));
- mite_decode(mite_CHOR_strings, temp);
- addr = mite_io_addr + MITE_CHCR(channel);
- printk(KERN_DEBUG "mite status[CHCR]at 0x%08lx =0x%08lx\n", addr,
- temp = readl(addr));
- mite_decode(mite_CHCR_strings, temp);
- addr = mite_io_addr + MITE_TCR(channel);
- printk(KERN_DEBUG "mite status[TCR] at 0x%08lx =0x%08x\n", addr,
- readl(addr));
- addr = mite_io_addr + MITE_MCR(channel);
- printk(KERN_DEBUG "mite status[MCR] at 0x%08lx =0x%08lx\n", addr,
- temp = readl(addr));
- mite_decode(mite_MCR_strings, temp);
-
- addr = mite_io_addr + MITE_MAR(channel);
- printk(KERN_DEBUG "mite status[MAR] at 0x%08lx =0x%08x\n", addr,
- readl(addr));
- addr = mite_io_addr + MITE_DCR(channel);
- printk(KERN_DEBUG "mite status[DCR] at 0x%08lx =0x%08lx\n", addr,
- temp = readl(addr));
- mite_decode(mite_DCR_strings, temp);
- addr = mite_io_addr + MITE_DAR(channel);
- printk(KERN_DEBUG "mite status[DAR] at 0x%08lx =0x%08x\n", addr,
- readl(addr));
- addr = mite_io_addr + MITE_LKCR(channel);
- printk(KERN_DEBUG "mite status[LKCR]at 0x%08lx =0x%08lx\n", addr,
- temp = readl(addr));
- mite_decode(mite_LKCR_strings, temp);
- addr = mite_io_addr + MITE_LKAR(channel);
- printk(KERN_DEBUG "mite status[LKAR]at 0x%08lx =0x%08x\n", addr,
- readl(addr));
- addr = mite_io_addr + MITE_CHSR(channel);
- printk(KERN_DEBUG "mite status[CHSR]at 0x%08lx =0x%08lx\n", addr,
- temp = readl(addr));
- mite_decode(mite_CHSR_strings, temp);
- addr = mite_io_addr + MITE_FCR(channel);
- printk(KERN_DEBUG "mite status[FCR] at 0x%08lx =0x%08x\n\n", addr,
- readl(addr));
-}
-EXPORT_SYMBOL(mite_dump_regs);
-
-static void mite_decode(char **bit_str, unsigned int bits)
+static void mite_decode(const char *const *bit_str, unsigned int bits)
{
int i;
for (i = 31; i >= 0; i--) {
if (bits & (1 << i))
- printk(KERN_DEBUG " %s", bit_str[i]);
+ pr_debug(" %s\n", bit_str[i]);
}
- printk(KERN_DEBUG "\n");
}
-EXPORT_SYMBOL(mite_decode);
-#endif
-#ifdef MODULE
-int __init init_module(void)
+void mite_dump_regs(struct mite_channel *mite_chan)
{
- mite_init();
- mite_list_devices();
+ void __iomem *mite_io_addr = mite_chan->mite->mite_io_addr;
+ unsigned int offset;
+ unsigned int value;
+ int channel = mite_chan->channel;
+
+ pr_debug("mite_dump_regs ch%i\n", channel);
+ pr_debug("mite address is =%p\n", mite_io_addr);
+
+ offset = MITE_CHOR(channel);
+ value = readl(mite_io_addr + offset);
+ pr_debug("mite status[CHOR] at 0x%08x =0x%08x\n", offset, value);
+ mite_decode(mite_CHOR_strings, value);
+ offset = MITE_CHCR(channel);
+ value = readl(mite_io_addr + offset);
+ pr_debug("mite status[CHCR] at 0x%08x =0x%08x\n", offset, value);
+ mite_decode(mite_CHCR_strings, value);
+ offset = MITE_TCR(channel);
+ value = readl(mite_io_addr + offset);
+ pr_debug("mite status[TCR] at 0x%08x =0x%08x\n", offset, value);
+ offset = MITE_MCR(channel);
+ value = readl(mite_io_addr + offset);
+ pr_debug("mite status[MCR] at 0x%08x =0x%08x\n", offset, value);
+ mite_decode(mite_MCR_strings, value);
+ offset = MITE_MAR(channel);
+ value = readl(mite_io_addr + offset);
+ pr_debug("mite status[MAR] at 0x%08x =0x%08x\n", offset, value);
+ offset = MITE_DCR(channel);
+ value = readl(mite_io_addr + offset);
+ pr_debug("mite status[DCR] at 0x%08x =0x%08x\n", offset, value);
+ mite_decode(mite_DCR_strings, value);
+ offset = MITE_DAR(channel);
+ value = readl(mite_io_addr + offset);
+ pr_debug("mite status[DAR] at 0x%08x =0x%08x\n", offset, value);
+ offset = MITE_LKCR(channel);
+ value = readl(mite_io_addr + offset);
+ pr_debug("mite status[LKCR] at 0x%08x =0x%08x\n", offset, value);
+ mite_decode(mite_LKCR_strings, value);
+ offset = MITE_LKAR(channel);
+ value = readl(mite_io_addr + offset);
+ pr_debug("mite status[LKAR] at 0x%08x =0x%08x\n", offset, value);
+ offset = MITE_CHSR(channel);
+ value = readl(mite_io_addr + offset);
+ pr_debug("mite status[CHSR] at 0x%08x =0x%08x\n", offset, value);
+ mite_decode(mite_CHSR_strings, value);
+ offset = MITE_FCR(channel);
+ value = readl(mite_io_addr + offset);
+ pr_debug("mite status[FCR] at 0x%08x =0x%08x\n", offset, value);
+}
+EXPORT_SYMBOL(mite_dump_regs);
+#endif
+static int __init mite_module_init(void)
+{
return 0;
}
-void __exit cleanup_module(void)
+static void __exit mite_module_exit(void)
{
- mite_cleanup();
}
-#endif
+
+module_init(mite_module_init);
+module_exit(mite_module_exit);
MODULE_AUTHOR("Comedi http://www.comedi.org");
MODULE_DESCRIPTION("Comedi low-level driver");
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.