diff options
Diffstat (limited to 'drivers/staging/comedi/drivers/ni_mio_common.c')
| -rw-r--r-- | drivers/staging/comedi/drivers/ni_mio_common.c | 981 |
1 files changed, 423 insertions, 558 deletions
diff --git a/drivers/staging/comedi/drivers/ni_mio_common.c b/drivers/staging/comedi/drivers/ni_mio_common.c index dcaf7e89f299..8dabb19519a5 100644 --- a/drivers/staging/comedi/drivers/ni_mio_common.c +++ b/drivers/staging/comedi/drivers/ni_mio_common.c @@ -1,56 +1,53 @@ /* - comedi/drivers/ni_mio_common.c - Hardware driver for DAQ-STC based boards - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org> - Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * Hardware driver for DAQ-STC based boards + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org> + * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ /* - This file is meant to be included by another file, e.g., - ni_atmio.c or ni_pcimio.c. - - Interrupt support originally added by Truxton Fulton - <trux@truxton.com> - - References (from ftp://ftp.natinst.com/support/manuals): - - 340747b.pdf AT-MIO E series Register Level Programmer Manual - 341079b.pdf PCI E Series RLPM - 340934b.pdf DAQ-STC reference manual - 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/) - release_ni611x.pdf - release_ni67xx.pdf - Other possibly relevant info: - - 320517c.pdf User manual (obsolete) - 320517f.pdf User manual (new) - 320889a.pdf delete - 320906c.pdf maximum signal ratings - 321066a.pdf about 16x - 321791a.pdf discontinuation of at-mio-16e-10 rev. c - 321808a.pdf about at-mio-16e-10 rev P - 321837a.pdf discontinuation of at-mio-16de-10 rev d - 321838a.pdf about at-mio-16de-10 rev N - - ISSUES: - - - the interrupt routine needs to be cleaned up - - 2006-02-07: S-Series PCI-6143: Support has been added but is not - fully tested as yet. Terry Barnaby, BEAM Ltd. -*/ + * This file is meant to be included by another file, e.g., + * ni_atmio.c or ni_pcimio.c. + * + * Interrupt support originally added by Truxton Fulton <trux@truxton.com> + * + * References (ftp://ftp.natinst.com/support/manuals): + * 340747b.pdf AT-MIO E series Register Level Programmer Manual + * 341079b.pdf PCI E Series RLPM + * 340934b.pdf DAQ-STC reference manual + * + * 67xx and 611x registers (ftp://ftp.ni.com/support/daq/mhddk/documentation/) + * release_ni611x.pdf + * release_ni67xx.pdf + * + * Other possibly relevant info: + * 320517c.pdf User manual (obsolete) + * 320517f.pdf User manual (new) + * 320889a.pdf delete + * 320906c.pdf maximum signal ratings + * 321066a.pdf about 16x + * 321791a.pdf discontinuation of at-mio-16e-10 rev. c + * 321808a.pdf about at-mio-16e-10 rev P + * 321837a.pdf discontinuation of at-mio-16de-10 rev d + * 321838a.pdf about at-mio-16de-10 rev N + * + * ISSUES: + * - the interrupt routine needs to be cleaned up + * + * 2006-02-07: S-Series PCI-6143: Support has been added but is not + * fully tested as yet. Terry Barnaby, BEAM Ltd. + */ #include <linux/interrupt.h> #include <linux/sched.h> @@ -216,19 +213,8 @@ enum ni_common_subdevices { NI_FREQ_OUT_SUBDEV, NI_NUM_SUBDEVICES }; -static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index) -{ - switch (counter_index) { - case 0: - return NI_GPCT0_SUBDEV; - case 1: - return NI_GPCT1_SUBDEV; - default: - break; - } - BUG(); - return NI_GPCT0_SUBDEV; -} + +#define NI_GPCT_SUBDEV(x) (NI_GPCT0_SUBDEV + (x)) enum timebase_nanoseconds { TIMEBASE_1_NS = 50, @@ -242,7 +228,7 @@ enum timebase_nanoseconds { static const int num_adc_stages_611x = 3; -static void ni_writel(struct comedi_device *dev, uint32_t data, int reg) +static void ni_writel(struct comedi_device *dev, unsigned int data, int reg) { if (dev->mmio) writel(data, dev->mmio + reg); @@ -250,7 +236,7 @@ static void ni_writel(struct comedi_device *dev, uint32_t data, int reg) outl(data, dev->iobase + reg); } -static void ni_writew(struct comedi_device *dev, uint16_t data, int reg) +static void ni_writew(struct comedi_device *dev, unsigned int data, int reg) { if (dev->mmio) writew(data, dev->mmio + reg); @@ -258,7 +244,7 @@ static void ni_writew(struct comedi_device *dev, uint16_t data, int reg) outw(data, dev->iobase + reg); } -static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg) +static void ni_writeb(struct comedi_device *dev, unsigned int data, int reg) { if (dev->mmio) writeb(data, dev->mmio + reg); @@ -266,7 +252,7 @@ static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg) outb(data, dev->iobase + reg); } -static uint32_t ni_readl(struct comedi_device *dev, int reg) +static unsigned int ni_readl(struct comedi_device *dev, int reg) { if (dev->mmio) return readl(dev->mmio + reg); @@ -274,7 +260,7 @@ static uint32_t ni_readl(struct comedi_device *dev, int reg) return inl(dev->iobase + reg); } -static uint16_t ni_readw(struct comedi_device *dev, int reg) +static unsigned int ni_readw(struct comedi_device *dev, int reg) { if (dev->mmio) return readw(dev->mmio + reg); @@ -282,7 +268,7 @@ static uint16_t ni_readw(struct comedi_device *dev, int reg) return inw(dev->iobase + reg); } -static uint8_t ni_readb(struct comedi_device *dev, int reg) +static unsigned int ni_readb(struct comedi_device *dev, int reg) { if (dev->mmio) return readb(dev->mmio + reg); @@ -457,7 +443,8 @@ static unsigned int m_series_stc_read(struct comedi_device *dev, } } -static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg) +static void ni_stc_writew(struct comedi_device *dev, + unsigned int data, int reg) { struct ni_private *devpriv = dev->private; unsigned long flags; @@ -476,7 +463,8 @@ static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg) } } -static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg) +static void ni_stc_writel(struct comedi_device *dev, + unsigned int data, int reg) { struct ni_private *devpriv = dev->private; @@ -488,11 +476,11 @@ static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg) } } -static uint16_t ni_stc_readw(struct comedi_device *dev, int reg) +static unsigned int ni_stc_readw(struct comedi_device *dev, int reg) { struct ni_private *devpriv = dev->private; unsigned long flags; - uint16_t val; + unsigned int val; if (devpriv->is_m_series) { val = m_series_stc_read(dev, reg); @@ -509,10 +497,10 @@ static uint16_t ni_stc_readw(struct comedi_device *dev, int reg) return val; } -static uint32_t ni_stc_readl(struct comedi_device *dev, int reg) +static unsigned int ni_stc_readl(struct comedi_device *dev, int reg) { struct ni_private *devpriv = dev->private; - uint32_t val; + unsigned int val; if (devpriv->is_m_series) { val = m_series_stc_read(dev, reg); @@ -524,7 +512,8 @@ static uint32_t ni_stc_readl(struct comedi_device *dev, int reg) } static inline void ni_set_bitfield(struct comedi_device *dev, int reg, - unsigned bit_mask, unsigned bit_values) + unsigned int bit_mask, + unsigned int bit_values) { struct ni_private *devpriv = dev->private; unsigned long flags; @@ -556,6 +545,11 @@ static inline void ni_set_bitfield(struct comedi_device *dev, int reg, devpriv->g0_g1_select_reg |= bit_values & bit_mask; ni_writeb(dev, devpriv->g0_g1_select_reg, reg); break; + case NI_M_CDIO_DMA_SEL_REG: + devpriv->cdio_dma_select_reg &= ~bit_mask; + devpriv->cdio_dma_select_reg |= bit_values & bit_mask; + ni_writeb(dev, devpriv->cdio_dma_select_reg, reg); + break; default: dev_err(dev->class_dev, "called with invalid register %d\n", reg); @@ -566,116 +560,35 @@ static inline void ni_set_bitfield(struct comedi_device *dev, int reg, } #ifdef PCIDMA -/* DMA channel setup */ -static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel) -{ - if (channel < 4) - return 1 << channel; - if (channel == 4) - return 0x3; - if (channel == 5) - return 0x5; - BUG(); - return 0; -} - -static inline void ni_set_ai_dma_channel(struct comedi_device *dev, - unsigned channel) -{ - unsigned bits = ni_stc_dma_channel_select_bitfield(channel); - - ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, - NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits)); -} - -static inline void ni_set_ai_dma_no_channel(struct comedi_device *dev) -{ - ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, NI_E_DMA_AI_SEL_MASK, 0); -} - -static inline void ni_set_ao_dma_channel(struct comedi_device *dev, - unsigned channel) -{ - unsigned bits = ni_stc_dma_channel_select_bitfield(channel); - - ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, - NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits)); -} - -static inline void ni_set_ao_dma_no_channel(struct comedi_device *dev) -{ - ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, NI_E_DMA_AO_SEL_MASK, 0); -} - -static inline void ni_set_gpct_dma_channel(struct comedi_device *dev, - unsigned gpct_index, - unsigned channel) -{ - unsigned bits = ni_stc_dma_channel_select_bitfield(channel); - - ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG, - NI_E_DMA_G0_G1_SEL_MASK(gpct_index), - NI_E_DMA_G0_G1_SEL(gpct_index, bits)); -} - -static inline void ni_set_gpct_dma_no_channel(struct comedi_device *dev, - unsigned gpct_index) -{ - ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG, - NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0); -} - -static inline void ni_set_cdo_dma_channel(struct comedi_device *dev, - unsigned mite_channel) -{ - struct ni_private *devpriv = dev->private; - unsigned long flags; - unsigned bits; - - spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); - devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK; - /* - * XXX just guessing ni_stc_dma_channel_select_bitfield() - * returns the right bits, under the assumption the cdio dma - * selection works just like ai/ao/gpct. - * Definitely works for dma channels 0 and 1. - */ - bits = ni_stc_dma_channel_select_bitfield(mite_channel); - devpriv->cdio_dma_select_reg |= NI_M_CDIO_DMA_SEL_CDO(bits); - ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG); - mmiowb(); - spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); -} - -static inline void ni_set_cdo_dma_no_channel(struct comedi_device *dev) -{ - struct ni_private *devpriv = dev->private; - unsigned long flags; - spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); - devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK; - ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG); - mmiowb(); - spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); -} +/* selects the MITE channel to use for DMA */ +#define NI_STC_DMA_CHAN_SEL(x) (((x) < 4) ? BIT(x) : \ + ((x) == 4) ? 0x3 : \ + ((x) == 5) ? 0x5 : 0x0) +/* DMA channel setup */ static int ni_request_ai_mite_channel(struct comedi_device *dev) { struct ni_private *devpriv = dev->private; + struct mite_channel *mite_chan; unsigned long flags; + unsigned int bits; spin_lock_irqsave(&devpriv->mite_channel_lock, flags); - BUG_ON(devpriv->ai_mite_chan); - devpriv->ai_mite_chan = - mite_request_channel(devpriv->mite, devpriv->ai_mite_ring); - if (!devpriv->ai_mite_chan) { + mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring); + if (!mite_chan) { spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); dev_err(dev->class_dev, "failed to reserve mite dma channel for analog input\n"); return -EBUSY; } - devpriv->ai_mite_chan->dir = COMEDI_INPUT; - ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel); + mite_chan->dir = COMEDI_INPUT; + devpriv->ai_mite_chan = mite_chan; + + bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); + ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, + NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits)); + spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); return 0; } @@ -683,37 +596,42 @@ static int ni_request_ai_mite_channel(struct comedi_device *dev) static int ni_request_ao_mite_channel(struct comedi_device *dev) { struct ni_private *devpriv = dev->private; + struct mite_channel *mite_chan; unsigned long flags; + unsigned int bits; spin_lock_irqsave(&devpriv->mite_channel_lock, flags); - BUG_ON(devpriv->ao_mite_chan); - devpriv->ao_mite_chan = - mite_request_channel(devpriv->mite, devpriv->ao_mite_ring); - if (!devpriv->ao_mite_chan) { + mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring); + if (!mite_chan) { spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); dev_err(dev->class_dev, "failed to reserve mite dma channel for analog outut\n"); return -EBUSY; } - devpriv->ao_mite_chan->dir = COMEDI_OUTPUT; - ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel); + mite_chan->dir = COMEDI_OUTPUT; + devpriv->ao_mite_chan = mite_chan; + + bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); + ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, + NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits)); + spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); return 0; } static int ni_request_gpct_mite_channel(struct comedi_device *dev, - unsigned gpct_index, + unsigned int gpct_index, enum comedi_io_direction direction) { struct ni_private *devpriv = dev->private; - unsigned long flags; + struct ni_gpct *counter = &devpriv->counter_dev->counters[gpct_index]; struct mite_channel *mite_chan; + unsigned long flags; + unsigned int bits; spin_lock_irqsave(&devpriv->mite_channel_lock, flags); - BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan); - mite_chan = - mite_request_channel(devpriv->mite, - devpriv->gpct_mite_ring[gpct_index]); + mite_chan = mite_request_channel(devpriv->mite, + devpriv->gpct_mite_ring[gpct_index]); if (!mite_chan) { spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); dev_err(dev->class_dev, @@ -721,37 +639,50 @@ static int ni_request_gpct_mite_channel(struct comedi_device *dev, return -EBUSY; } mite_chan->dir = direction; - ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index], - mite_chan); - ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel); + ni_tio_set_mite_channel(counter, mite_chan); + + bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); + ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG, + NI_E_DMA_G0_G1_SEL_MASK(gpct_index), + NI_E_DMA_G0_G1_SEL(gpct_index, bits)); + spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); return 0; } -#endif /* PCIDMA */ - static int ni_request_cdo_mite_channel(struct comedi_device *dev) { -#ifdef PCIDMA struct ni_private *devpriv = dev->private; + struct mite_channel *mite_chan; unsigned long flags; + unsigned int bits; spin_lock_irqsave(&devpriv->mite_channel_lock, flags); - BUG_ON(devpriv->cdo_mite_chan); - devpriv->cdo_mite_chan = - mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring); - if (!devpriv->cdo_mite_chan) { + mite_chan = mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring); + if (!mite_chan) { spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); dev_err(dev->class_dev, "failed to reserve mite dma channel for correlated digital output\n"); return -EBUSY; } - devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT; - ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel); + mite_chan->dir = COMEDI_OUTPUT; + devpriv->cdo_mite_chan = mite_chan; + + /* + * XXX just guessing NI_STC_DMA_CHAN_SEL() + * returns the right bits, under the assumption the cdio dma + * selection works just like ai/ao/gpct. + * Definitely works for dma channels 0 and 1. + */ + bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); + ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG, + NI_M_CDIO_DMA_SEL_CDO_MASK, + NI_M_CDIO_DMA_SEL_CDO(bits)); + spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); -#endif /* PCIDMA */ return 0; } +#endif /* PCIDMA */ static void ni_release_ai_mite_channel(struct comedi_device *dev) { @@ -761,7 +692,8 @@ static void ni_release_ai_mite_channel(struct comedi_device *dev) spin_lock_irqsave(&devpriv->mite_channel_lock, flags); if (devpriv->ai_mite_chan) { - ni_set_ai_dma_no_channel(dev); + ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, + NI_E_DMA_AI_SEL_MASK, 0); mite_release_channel(devpriv->ai_mite_chan); devpriv->ai_mite_chan = NULL; } @@ -777,7 +709,8 @@ static void ni_release_ao_mite_channel(struct comedi_device *dev) spin_lock_irqsave(&devpriv->mite_channel_lock, flags); if (devpriv->ao_mite_chan) { - ni_set_ao_dma_no_channel(dev); + ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, + NI_E_DMA_AO_SEL_MASK, 0); mite_release_channel(devpriv->ao_mite_chan); devpriv->ao_mite_chan = NULL; } @@ -787,7 +720,7 @@ static void ni_release_ao_mite_channel(struct comedi_device *dev) #ifdef PCIDMA static void ni_release_gpct_mite_channel(struct comedi_device *dev, - unsigned gpct_index) + unsigned int gpct_index) { struct ni_private *devpriv = dev->private; unsigned long flags; @@ -797,7 +730,8 @@ static void ni_release_gpct_mite_channel(struct comedi_device *dev, struct mite_channel *mite_chan = devpriv->counter_dev->counters[gpct_index].mite_chan; - ni_set_gpct_dma_no_channel(dev, gpct_index); + ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG, + NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0); ni_tio_set_mite_channel(&devpriv-> counter_dev->counters[gpct_index], NULL); @@ -805,30 +739,27 @@ static void ni_release_gpct_mite_channel(struct comedi_device *dev, } spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); } -#endif /* PCIDMA */ static void ni_release_cdo_mite_channel(struct comedi_device *dev) { -#ifdef PCIDMA struct ni_private *devpriv = dev->private; unsigned long flags; spin_lock_irqsave(&devpriv->mite_channel_lock, flags); if (devpriv->cdo_mite_chan) { - ni_set_cdo_dma_no_channel(dev); + ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG, + NI_M_CDIO_DMA_SEL_CDO_MASK, 0); mite_release_channel(devpriv->cdo_mite_chan); devpriv->cdo_mite_chan = NULL; } spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); -#endif /* PCIDMA */ } -#ifdef PCIDMA static void ni_e_series_enable_second_irq(struct comedi_device *dev, - unsigned gpct_index, short enable) + unsigned int gpct_index, short enable) { struct ni_private *devpriv = dev->private; - uint16_t val = 0; + unsigned int val = 0; int reg; if (devpriv->is_m_series || gpct_index > 1) @@ -875,8 +806,10 @@ static void ni_clear_ai_fifo(struct comedi_device *dev) ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0)); ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0)); #if 0 - /* the NI example code does 3 convert pulses for 625x boards, - but that appears to be wrong in practice. */ + /* + * The NI example code does 3 convert pulses for 625x + * boards, But that appears to be wrong in practice. + */ ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG); ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, @@ -888,8 +821,8 @@ static void ni_clear_ai_fifo(struct comedi_device *dev) } } -static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data, - int addr) +static inline void ni_ao_win_outw(struct comedi_device *dev, + unsigned int data, int addr) { struct ni_private *devpriv = dev->private; unsigned long flags; @@ -900,8 +833,8 @@ static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data, spin_unlock_irqrestore(&devpriv->window_lock, flags); } -static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data, - int addr) +static inline void ni_ao_win_outl(struct comedi_device *dev, + unsigned int data, int addr) { struct ni_private *devpriv = dev->private; unsigned long flags; @@ -925,20 +858,21 @@ static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr) return data; } -/* ni_set_bits( ) allows different parts of the ni_mio_common driver to -* share registers (such as Interrupt_A_Register) without interfering with -* each other. -* -* NOTE: the switch/case statements are optimized out for a constant argument -* so this is actually quite fast--- If you must wrap another function around this -* make it inline to avoid a large speed penalty. -* -* value should only be 1 or 0. -*/ +/* + * ni_set_bits( ) allows different parts of the ni_mio_common driver to + * share registers (such as Interrupt_A_Register) without interfering with + * each other. + * + * NOTE: the switch/case statements are optimized out for a constant argument + * so this is actually quite fast--- If you must wrap another function around + * this make it inline to avoid a large speed penalty. + * + * value should only be 1 or 0. + */ static inline void ni_set_bits(struct comedi_device *dev, int reg, - unsigned bits, unsigned value) + unsigned int bits, unsigned int value) { - unsigned bit_values; + unsigned int bit_values; if (value) bit_values = bits; @@ -956,7 +890,7 @@ static void ni_sync_ai_dma(struct comedi_device *dev) spin_lock_irqsave(&devpriv->mite_channel_lock, flags); if (devpriv->ai_mite_chan) - mite_sync_input_dma(devpriv->ai_mite_chan, s); + mite_sync_dma(devpriv->ai_mite_chan, s); spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); } @@ -972,9 +906,8 @@ static int ni_ai_drain_dma(struct comedi_device *dev) if (devpriv->ai_mite_chan) { for (i = 0; i < timeout; i++) { if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & - NISTC_AI_STATUS1_FIFO_E) - && mite_bytes_in_transit(devpriv->ai_mite_chan) == - 0) + NISTC_AI_STATUS1_FIFO_E) && + mite_bytes_in_transit(devpriv->ai_mite_chan) == 0) break; udelay(5); } @@ -994,19 +927,6 @@ static int ni_ai_drain_dma(struct comedi_device *dev) return retval; } -static void mite_handle_b_linkc(struct mite_struct *mite, - struct comedi_device *dev) -{ - struct ni_private *devpriv = dev->private; - struct comedi_subdevice *s = dev->write_subdev; - unsigned long flags; - - spin_lock_irqsave(&devpriv->mite_channel_lock, flags); - if (devpriv->ao_mite_chan) - mite_sync_output_dma(devpriv->ao_mite_chan, s); - spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); -} - static int ni_ao_wait_for_dma_load(struct comedi_device *dev) { static const int timeout = 10000; @@ -1018,9 +938,11 @@ static int ni_ao_wait_for_dma_load(struct comedi_device *dev) b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG); if (b_status & NISTC_AO_STATUS1_FIFO_HF) break; - /* if we poll too often, the pci bus activity seems - to slow the dma transfer down */ - udelay(10); + /* + * If we poll too often, the pci bus activity seems + * to slow the dma transfer down. + */ + usleep_range(10, 100); } if (i == timeout) { dev_err(dev->class_dev, "timed out waiting for dma load\n"); @@ -1038,7 +960,7 @@ static void ni_ao_fifo_load(struct comedi_device *dev, struct ni_private *devpriv = dev->private; int i; unsigned short d; - u32 packed_data; + unsigned int packed_data; for (i = 0; i < n; i++) { comedi_buf_read_samples(s, &d, 1); @@ -1128,7 +1050,7 @@ static void ni_ai_fifo_read(struct comedi_device *dev, { struct ni_private *devpriv = dev->private; struct comedi_async *async = s->async; - u32 dl; + unsigned int dl; unsigned short data; int i; @@ -1148,7 +1070,10 @@ static void ni_ai_fifo_read(struct comedi_device *dev, comedi_buf_write_samples(s, &data, 1); } } else if (devpriv->is_6143) { - /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */ + /* + * This just reads the FIFO assuming the data is present, + * no checks on the FIFO status are performed. + */ for (i = 0; i < n / 2; i++) { dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG); @@ -1192,16 +1117,13 @@ static void ni_handle_fifo_half_full(struct comedi_device *dev) } #endif -/* - Empties the AI fifo -*/ +/* Empties the AI fifo */ static void ni_handle_fifo_dregs(struct comedi_device *dev) { struct ni_private *devpriv = dev->private; struct comedi_subdevice *s = dev->read_subdev; - u32 dl; + unsigned int dl; unsigned short data; - unsigned short fifo_empty; int i; if (devpriv->is_611x) { @@ -1237,15 +1159,16 @@ static void ni_handle_fifo_dregs(struct comedi_device *dev) } } else { - fifo_empty = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & - NISTC_AI_STATUS1_FIFO_E; - while (fifo_empty == 0) { + unsigned short fe; /* fifo empty */ + + fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & + NISTC_AI_STATUS1_FIFO_E; + while (fe == 0) { for (i = 0; i < ARRAY_SIZE(devpriv->ai_fifo_buffer); i++) { - fifo_empty = ni_stc_readw(dev, - NISTC_AI_STATUS1_REG) & - NISTC_AI_STATUS1_FIFO_E; - if (fifo_empty) + fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & + NISTC_AI_STATUS1_FIFO_E; + if (fe) break; devpriv->ai_fifo_buffer[i] = ni_readw(dev, NI_E_AI_FIFO_DATA_REG); @@ -1260,7 +1183,7 @@ static void get_last_sample_611x(struct comedi_device *dev) struct ni_private *devpriv = dev->private; struct comedi_subdevice *s = dev->read_subdev; unsigned short data; - u32 dl; + unsigned int dl; if (!devpriv->is_611x) return; @@ -1278,7 +1201,7 @@ static void get_last_sample_6143(struct comedi_device *dev) struct ni_private *devpriv = dev->private; struct comedi_subdevice *s = dev->read_subdev; unsigned short data; - u32 dl; + unsigned int dl; if (!devpriv->is_6143) return; @@ -1365,42 +1288,23 @@ static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status) ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG); } -static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, - unsigned ai_mite_status) +static void handle_a_interrupt(struct comedi_device *dev, + struct comedi_subdevice *s, + unsigned short status) { - struct comedi_subdevice *s = dev->read_subdev; struct comedi_cmd *cmd = &s->async->cmd; - /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */ - if (s->type == COMEDI_SUBD_UNUSED) - return; - -#ifdef PCIDMA - if (ai_mite_status & CHSR_LINKC) - ni_sync_ai_dma(dev); - - if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | - CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | - CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) { - dev_err(dev->class_dev, - "unknown mite interrupt (ai_mite_status=%08x)\n", - ai_mite_status); - s->async->events |= COMEDI_CB_ERROR; - /* disable_irq(dev->irq); */ - } -#endif - /* test for all uncommon interrupt events at the same time */ if (status & (NISTC_AI_STATUS1_ERR | NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) { if (status == 0xffff) { dev_err(dev->class_dev, "Card removed?\n"); - /* we probably aren't even running a command now, - * so it's a good idea to be careful. */ - if (comedi_is_subdevice_running(s)) { + /* + * We probably aren't even running a command now, + * so it's a good idea to be careful. + */ + if (comedi_is_subdevice_running(s)) s->async->events |= COMEDI_CB_ERROR; - comedi_handle_events(dev, s); - } return; } if (status & NISTC_AI_STATUS1_ERR) { @@ -1412,8 +1316,6 @@ static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, s->async->events |= COMEDI_CB_ERROR; if (status & NISTC_AI_STATUS1_OVER) s->async->events |= COMEDI_CB_OVERFLOW; - - comedi_handle_events(dev, s); return; } if (status & NISTC_AI_STATUS1_SC_TC) { @@ -1425,8 +1327,11 @@ static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, if (status & NISTC_AI_STATUS1_FIFO_HF) { int i; static const int timeout = 10; - /* pcmcia cards (at least 6036) seem to stop producing interrupts if we - *fail to get the fifo less than half full, so loop to be sure.*/ + /* + * PCMCIA cards (at least 6036) seem to stop producing + * interrupts if we fail to get the fifo less than half + * full, so loop to be sure. + */ for (i = 0; i < timeout; ++i) { ni_handle_fifo_half_full(dev); if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) & @@ -1438,8 +1343,6 @@ static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, if (status & NISTC_AI_STATUS1_STOP) ni_handle_eos(dev, s); - - comedi_handle_events(dev, s); } static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status) @@ -1465,29 +1368,9 @@ static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status) } static void handle_b_interrupt(struct comedi_device *dev, - unsigned short b_status, unsigned ao_mite_status) + struct comedi_subdevice *s, + unsigned short b_status) { - struct comedi_subdevice *s = dev->write_subdev; - /* unsigned short ack=0; */ - -#ifdef PCIDMA - /* Currently, mite.c requires us to handle LINKC */ - if (ao_mite_status & CHSR_LINKC) { - struct ni_private *devpriv = dev->private; - - mite_handle_b_linkc(devpriv->mite, dev); - } - - if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | - CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | - CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) { - dev_err(dev->class_dev, - "unknown mite interrupt (ao_mite_status=%08x)\n", - ao_mite_status); - s->async->events |= COMEDI_CB_ERROR; - } -#endif - if (b_status == 0xffff) return; if (b_status & NISTC_AO_STATUS1_OVERRUN) { @@ -1515,8 +1398,6 @@ static void handle_b_interrupt(struct comedi_device *dev, } } #endif - - comedi_handle_events(dev, s); } static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s, @@ -1606,8 +1487,11 @@ static int ni_ao_setup_MITE_dma(struct comedi_device *dev) if (devpriv->is_611x || devpriv->is_6713) { mite_prep_dma(devpriv->ao_mite_chan, 32, 32); } else { - /* doing 32 instead of 16 bit wide transfers from memory - makes the mite do 32 bit pci transfers, doubling pci bandwidth. */ + /* + * Doing 32 instead of 16 bit wide transfers from + * memory makes the mite do 32 bit pci transfers, + * doubling pci bandwidth. + */ mite_prep_dma(devpriv->ao_mite_chan, 16, 32); } mite_dma_arm(devpriv->ao_mite_chan); @@ -1622,16 +1506,15 @@ static int ni_ao_setup_MITE_dma(struct comedi_device *dev) #endif /* PCIDMA */ /* - used for both cancel ioctl and board initialization - - this is pretty harsh for a cancel, but it works... + * used for both cancel ioctl and board initialization + * + * this is pretty harsh for a cancel, but it works... */ - static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s) { struct ni_private *devpriv = dev->private; - unsigned ai_personal; - unsigned ai_out_ctrl; + unsigned int ai_personal; + unsigned int ai_out_ctrl; ni_release_ai_mite_channel(dev); /* ai configuration */ @@ -1736,12 +1619,12 @@ static void ni_m_series_load_channelgain_list(struct comedi_device *dev, unsigned int chan, range, aref; unsigned int i; unsigned int dither; - unsigned range_code; + unsigned int range_code; ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG); if ((list[0] & CR_ALT_SOURCE)) { - unsigned bypass_bits; + unsigned int bypass_bits; chan = CR_CHAN(list[0]); range = CR_RANGE(list[0]); @@ -1760,7 +1643,7 @@ static void ni_m_series_load_channelgain_list(struct comedi_device *dev, ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG); } for (i = 0; i < n_chan; i++) { - unsigned config_bits = 0; + unsigned int config_bits = 0; chan = CR_CHAN(list[i]); aref = CR_AREF(list[i]); @@ -1842,8 +1725,8 @@ static void ni_load_channelgain_list(struct comedi_device *dev, return; } if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) { - if (devpriv->changain_state - && devpriv->changain_spec == list[0]) { + if (devpriv->changain_state && + devpriv->changain_spec == list[0]) { /* ready to go. */ return; } @@ -1857,8 +1740,8 @@ static void ni_load_channelgain_list(struct comedi_device *dev, /* Set up Calibration mode if required */ if (devpriv->is_6143) { - if ((list[0] & CR_ALT_SOURCE) - && !devpriv->ai_calib_source_enabled) { + if ((list[0] & CR_ALT_SOURCE) && + !devpriv->ai_calib_source_enabled) { /* Strobe Relay enable bit */ ni_writew(dev, devpriv->ai_calib_source | NI6143_CALIB_CHAN_RELAY_ON, @@ -1866,9 +1749,10 @@ static void ni_load_channelgain_list(struct comedi_device *dev, ni_writew(dev, devpriv->ai_calib_source, NI6143_CALIB_CHAN_REG); devpriv->ai_calib_source_enabled = 1; - msleep_interruptible(100); /* Allow relays to change */ - } else if (!(list[0] & CR_ALT_SOURCE) - && devpriv->ai_calib_source_enabled) { + /* Allow relays to change */ + msleep_interruptible(100); + } else if (!(list[0] & CR_ALT_SOURCE) && + devpriv->ai_calib_source_enabled) { /* Strobe Relay disable bit */ ni_writew(dev, devpriv->ai_calib_source | NI6143_CALIB_CHAN_RELAY_OFF, @@ -1876,7 +1760,8 @@ static void ni_load_channelgain_list(struct comedi_device *dev, ni_writew(dev, devpriv->ai_calib_source, NI6143_CALIB_CHAN_REG); devpriv->ai_calib_source_enabled = 0; - msleep_interruptible(100); /* Allow relays to change */ + /* Allow relays to change */ + msleep_interruptible(100); } } @@ -1949,7 +1834,7 @@ static int ni_ai_insn_read(struct comedi_device *dev, struct ni_private *devpriv = dev->private; unsigned int mask = (s->maxdata + 1) >> 1; int i, n; - unsigned signbits; + unsigned int signbits; unsigned int d; unsigned long dl; @@ -1997,7 +1882,11 @@ static int ni_ai_insn_read(struct comedi_device *dev, ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG); - /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */ + /* + * The 6143 has 32-bit FIFOs. You need to strobe a + * bit to move a single 16bit stranded sample into + * the FIFO. + */ dl = 0; for (i = 0; i < NI_TIMEOUT; i++) { if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & @@ -2035,7 +1924,8 @@ static int ni_ai_insn_read(struct comedi_device *dev, data[n] = dl; } else { d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG); - d += signbits; /* subtle: needs to be short addition */ + /* subtle: needs to be short addition */ + d += signbits; data[n] = d; } } @@ -2043,8 +1933,8 @@ static int ni_ai_insn_read(struct comedi_device *dev, return insn->n; } -static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec, - unsigned int flags) +static int ni_ns_to_timer(const struct comedi_device *dev, + unsigned int nanosec, unsigned int flags) { struct ni_private *devpriv = dev->private; int divider; @@ -2064,14 +1954,14 @@ static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec, return divider - 1; } -static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer) +static unsigned int ni_timer_to_ns(const struct comedi_device *dev, int timer) { struct ni_private *devpriv = dev->private; return devpriv->clock_ns * (timer + 1); } -static void ni_cmd_set_mite_transfer(struct mite_dma_descriptor_ring *ring, +static void ni_cmd_set_mite_transfer(struct mite_ring *ring, struct comedi_subdevice *sdev, const struct comedi_cmd *cmd, unsigned int max_count) { @@ -2102,8 +1992,8 @@ static void ni_cmd_set_mite_transfer(struct mite_dma_descriptor_ring *ring, #endif } -static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev, - unsigned num_channels) +static unsigned int ni_min_ai_scan_period_ns(struct comedi_device *dev, + unsigned int num_channels) { const struct ni_board_struct *board = dev->board_ptr; struct ni_private *devpriv = dev->private; @@ -2294,7 +2184,7 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) int start_stop_select = 0; unsigned int stop_count; int interrupt_a_enable = 0; - unsigned ai_trig; + unsigned int ai_trig; if (dev->irq == 0) { dev_err(dev->class_dev, "cannot run command without an irq\n"); @@ -2307,8 +2197,10 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) /* start configuration */ ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG); - /* disable analog triggering for now, since it - * interferes with the use of pfi0 */ + /* + * Disable analog triggering for now, since it interferes + * with the use of pfi0. + */ devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA; ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG); @@ -2369,7 +2261,10 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) if (stop_count == 0) { devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS; interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP; - /* this is required to get the last sample for chanlist_len > 1, not sure why */ + /* + * This is required to get the last sample for + * chanlist_len > 1, not sure why. + */ if (cmd->chanlist_len > 1) start_stop_select |= NISTC_AI_STOP_POLARITY | NISTC_AI_STOP_EDGE; @@ -2489,7 +2384,7 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) switch (devpriv->aimode) { case AIMODE_HALF_FULL: - /*generate FIFO interrupts and DMA requests on half-full */ + /* FIFO interrupts and DMA requests on half-full */ #ifdef PCIDMA ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E, NISTC_AI_MODE3_REG); @@ -2880,9 +2775,11 @@ static int ni_ao_inttrig(struct comedi_device *dev, if (trig_num != cmd->start_arg) return -EINVAL; - /* Null trig at beginning prevent ao start trigger from executing more than - once per command (and doing things like trying to allocate the ao dma channel - multiple times) */ + /* + * Null trig at beginning prevent ao start trigger from executing more + * than once per command (and doing things like trying to allocate the + * ao dma channel multiple times). + */ s->async->inttrig = NULL; ni_set_bits(dev, NISTC_INTB_ENA_REG, @@ -2951,7 +2848,7 @@ static void ni_ao_cmd_personalize(struct comedi_device *dev, const struct comedi_cmd *cmd) { const struct ni_board_struct *board = dev->board_ptr; - unsigned bits; + unsigned int bits; ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG); @@ -2999,6 +2896,7 @@ static void ni_ao_cmd_set_trigger(struct comedi_device *dev, const struct comedi_cmd *cmd) { struct ni_private *devpriv = dev->private; + unsigned int trigsel; ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG); @@ -3012,39 +2910,20 @@ static void ni_ao_cmd_set_trigger(struct comedi_device *dev, } ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); - { - unsigned int trigsel = devpriv->ao_trigger_select; - - switch (cmd->start_src) { - case TRIG_INT: - case TRIG_NOW: - trigsel &= ~(NISTC_AO_TRIG_START1_POLARITY | - NISTC_AO_TRIG_START1_SEL_MASK); - trigsel |= NISTC_AO_TRIG_START1_EDGE | - NISTC_AO_TRIG_START1_SYNC; - break; - case TRIG_EXT: - trigsel = NISTC_AO_TRIG_START1_SEL( - CR_CHAN(cmd->start_arg) + 1); - if (cmd->start_arg & CR_INVERT) - /* - * 0=active high, 1=active low. - * see daq-stc 3-24 (p186) - */ - trigsel |= NISTC_AO_TRIG_START1_POLARITY; - if (cmd->start_arg & CR_EDGE) - /* 0=edge detection disabled, 1=enabled */ - trigsel |= NISTC_AO_TRIG_START1_EDGE; - break; - default: - BUG(); - break; - } - - devpriv->ao_trigger_select = trigsel; - ni_stc_writew(dev, devpriv->ao_trigger_select, - NISTC_AO_TRIG_SEL_REG); + if (cmd->start_src == TRIG_INT) { + trigsel = NISTC_AO_TRIG_START1_EDGE | + NISTC_AO_TRIG_START1_SYNC; + } else { /* TRIG_EXT */ + trigsel = NISTC_AO_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + 1); + /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */ + if (cmd->start_arg & CR_INVERT) + trigsel |= NISTC_AO_TRIG_START1_POLARITY; + /* 0=edge detection disabled, 1=enabled */ + if (cmd->start_arg & CR_EDGE) + trigsel |= NISTC_AO_TRIG_START1_EDGE; } + ni_stc_writew(dev, trigsel, NISTC_AO_TRIG_SEL_REG); + /* AO_Delayed_START1 = 0, we do not support delayed start...yet */ /* sync */ @@ -3149,8 +3028,9 @@ static void ni_ao_cmd_set_update(struct comedi_device *dev, NISTC_AO_MODE1_UPDATE_SRC_POLARITY ); - switch (cmd->scan_begin_src) { - case TRIG_TIMER: + if (cmd->scan_begin_src == TRIG_TIMER) { + unsigned int trigvar; + devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA; /* @@ -3181,34 +3061,25 @@ static void ni_ao_cmd_set_update(struct comedi_device *dev, * eseries/ni67xx and tMSeries.h for mseries. */ - { - unsigned trigvar = ni_ns_to_timer(dev, - cmd->scan_begin_arg, - CMDF_ROUND_NEAREST); + trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg, + CMDF_ROUND_NEAREST); - /* - * Wait N TB3 ticks after the start trigger before - * clocking(N must be >=2). - */ - /* following line: 2-1 per STC */ - ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG); - ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, - NISTC_AO_CMD1_REG); - /* following line: N-1 per STC */ - ni_stc_writel(dev, trigvar - 1, NISTC_AO_UI_LOADA_REG); - } - break; - case TRIG_EXT: + /* + * Wait N TB3 ticks after the start trigger before + * clocking (N must be >=2). + */ + /* following line: 2-1 per STC */ + ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG); + ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG); + /* following line: N-1 per STC */ + ni_stc_writel(dev, trigvar - 1, NISTC_AO_UI_LOADA_REG); + } else { /* TRIG_EXT */ /* FIXME: assert scan_begin_arg != 0, ret failure otherwise */ devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA; devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC( CR_CHAN(cmd->scan_begin_arg)); if (cmd->scan_begin_arg & CR_INVERT) devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY; - break; - default: - BUG(); - break; } ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG); @@ -3231,7 +3102,7 @@ static void ni_ao_cmd_set_channels(struct comedi_device *dev, { struct ni_private *devpriv = dev->private; const struct comedi_cmd *cmd = &s->async->cmd; - unsigned bits = 0; + unsigned int bits = 0; ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG); @@ -3474,7 +3345,6 @@ static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s) devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE; else devpriv->ao_mode3 = 0; - devpriv->ao_trigger_select = 0; ni_stc_writew(dev, 0, NISTC_AO_PERSONAL_REG); ni_stc_writew(dev, 0, NISTC_AO_CMD1_REG); @@ -3550,6 +3420,7 @@ static int ni_dio_insn_bits(struct comedi_device *dev, return insn->n; } +#ifdef PCIDMA static int ni_m_series_dio_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_insn *insn, @@ -3652,13 +3523,11 @@ static int ni_cdo_inttrig(struct comedi_device *dev, unsigned int trig_num) { struct comedi_cmd *cmd = &s->async->cmd; - const unsigned timeout = 1000; + const unsigned int timeout = 1000; int retval = 0; - unsigned i; -#ifdef PCIDMA + unsigned int i; struct ni_private *devpriv = dev->private; unsigned long flags; -#endif if (trig_num != cmd->start_arg) return -EINVAL; @@ -3668,7 +3537,6 @@ static int ni_cdo_inttrig(struct comedi_device *dev, /* read alloc the entire buffer */ comedi_buf_read_alloc(s, s->async->prealloc_bufsz); -#ifdef PCIDMA spin_lock_irqsave(&devpriv->mite_channel_lock, flags); if (devpriv->cdo_mite_chan) { mite_prep_dma(devpriv->cdo_mite_chan, 32, 32); @@ -3680,7 +3548,7 @@ static int ni_cdo_inttrig(struct comedi_device *dev, spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); if (retval < 0) return retval; -#endif + /* * XXX not sure what interrupt C group does * wait for dma to fill output fifo @@ -3690,7 +3558,7 @@ static int ni_cdo_inttrig(struct comedi_device *dev, if (ni_readl(dev, NI_M_CDIO_STATUS_REG) & NI_M_CDIO_STATUS_CDO_FIFO_FULL) break; - udelay(10); + usleep_range(10, 100); } if (i == timeout) { dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n"); @@ -3708,7 +3576,7 @@ static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s) { struct ni_private *devpriv = dev->private; const struct comedi_cmd *cmd = &s->async->cmd; - unsigned cdo_mode_bits; + unsigned int cdo_mode_bits; int retval; ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG); @@ -3759,28 +3627,14 @@ static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s) static void handle_cdio_interrupt(struct comedi_device *dev) { struct ni_private *devpriv = dev->private; - unsigned cdio_status; + unsigned int cdio_status; struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV]; -#ifdef PCIDMA unsigned long flags; -#endif - if (!devpriv->is_m_series) - return; -#ifdef PCIDMA spin_lock_irqsave(&devpriv->mite_channel_lock, flags); - if (devpriv->cdo_mite_chan) { - unsigned cdo_mite_status = - mite_get_status(devpriv->cdo_mite_chan); - if (cdo_mite_status & CHSR_LINKC) { - writel(CHOR_CLRLC, - devpriv->mite->mite_io_addr + - MITE_CHOR(devpriv->cdo_mite_chan->channel)); - } - mite_sync_output_dma(devpriv->cdo_mite_chan, s); - } + if (devpriv->cdo_mite_chan) + mite_ack_linkc(devpriv->cdo_mite_chan, s, true); spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); -#endif cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG); if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) { @@ -3796,6 +3650,7 @@ static void handle_cdio_interrupt(struct comedi_device *dev) } comedi_handle_events(dev, s); } +#endif /* PCIDMA */ static int ni_serial_hw_readwrite8(struct comedi_device *dev, struct comedi_subdevice *s, @@ -3813,7 +3668,7 @@ static int ni_serial_hw_readwrite8(struct comedi_device *dev, status1 = ni_stc_readw(dev, NISTC_STATUS1_REG); if (status1 & NISTC_STATUS1_SERIO_IN_PROG) { err = -EBUSY; - goto Error; + goto error; } devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START; @@ -3829,7 +3684,7 @@ static int ni_serial_hw_readwrite8(struct comedi_device *dev, dev_err(dev->class_dev, "SPI serial I/O didn't finish in time!\n"); err = -ETIME; - goto Error; + goto error; } } @@ -3842,7 +3697,7 @@ static int ni_serial_hw_readwrite8(struct comedi_device *dev, if (data_in) *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG); -Error: +error: ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); return err; @@ -3860,16 +3715,20 @@ static int ni_serial_sw_readwrite8(struct comedi_device *dev, udelay((devpriv->serial_interval_ns + 999) / 1000); for (mask = 0x80; mask; mask >>= 1) { - /* Output current bit; note that we cannot touch s->state - because it is a per-subdevice field, and serial is - a separate subdevice from DIO. */ + /* + * Output current bit; note that we cannot touch s->state + * because it is a per-subdevice field, and serial is + * a separate subdevice from DIO. + */ devpriv->dio_output &= ~NISTC_DIO_SDOUT; if (data_out & mask) devpriv->dio_output |= NISTC_DIO_SDOUT; ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG); - /* Assert SDCLK (active low, inverted), wait for half of - the delay, deassert SDCLK, and wait for the other half. */ + /* + * Assert SDCLK (active low, inverted), wait for half of + * the delay, deassert SDCLK, and wait for the other half. + */ devpriv->dio_control |= NISTC_DIO_SDCLK; ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); @@ -3897,7 +3756,7 @@ static int ni_serial_insn_config(struct comedi_device *dev, unsigned int *data) { struct ni_private *devpriv = dev->private; - unsigned clk_fout = devpriv->clock_and_fout; + unsigned int clk_fout = devpriv->clock_and_fout; int err = insn->n; unsigned char byte_out, byte_in = 0; @@ -3916,8 +3775,10 @@ static int ni_serial_insn_config(struct comedi_device *dev, data[1] = SERIAL_DISABLED; devpriv->serial_interval_ns = data[1]; } else if (data[1] <= SERIAL_600NS) { - /* Warning: this clock speed is too fast to reliably - control SCXI. */ + /* + * Warning: this clock speed is too fast to reliably + * control SCXI. + */ devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE; clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE; clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2; @@ -3933,10 +3794,12 @@ static int ni_serial_insn_config(struct comedi_device *dev, devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE; clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE | NISTC_CLK_FOUT_DIO_SER_OUT_DIV2; - /* Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects - 600ns/1.2us. If you turn divide_by_2 off with the - slow clock, you will still get 10us, except then - all your delays are wrong. */ + /* + * Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects + * 600ns/1.2us. If you turn divide_by_2 off with the + * slow clock, you will still get 10us, except then + * all your delays are wrong. + */ data[1] = SERIAL_10US; devpriv->serial_interval_ns = data[1]; } else { @@ -4046,15 +3909,11 @@ static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev, return regmap->mio_reg; } -static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, +static void ni_gpct_write_register(struct ni_gpct *counter, unsigned int bits, enum ni_gpct_register reg) { struct comedi_device *dev = counter->counter_dev->dev; unsigned int stc_register = ni_gpct_to_stc_register(dev, reg); - static const unsigned gpct_interrupt_a_enable_mask = - NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC; - static const unsigned gpct_interrupt_b_enable_mask = - NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC; if (stc_register == 0) return; @@ -4082,25 +3941,22 @@ static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, /* 16 bit registers */ case NITIO_G0_INT_ENA: - BUG_ON(bits & ~gpct_interrupt_a_enable_mask); ni_set_bitfield(dev, stc_register, - gpct_interrupt_a_enable_mask, bits); + NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC, + bits); break; case NITIO_G1_INT_ENA: - BUG_ON(bits & ~gpct_interrupt_b_enable_mask); ni_set_bitfield(dev, stc_register, - gpct_interrupt_b_enable_mask, bits); + NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC, + bits); break; - case NITIO_G01_RESET: - BUG_ON(bits & ~(NISTC_RESET_G0 | NISTC_RESET_G1)); - /* fall-through */ default: ni_stc_writew(dev, bits, stc_register); } } -static unsigned ni_gpct_read_register(struct ni_gpct *counter, - enum ni_gpct_register reg) +static unsigned int ni_gpct_read_register(struct ni_gpct *counter, + enum ni_gpct_register reg) { struct comedi_device *dev = counter->counter_dev->dev; unsigned int stc_register = ni_gpct_to_stc_register(dev, reg); @@ -4227,7 +4083,7 @@ static int ni_m_series_pwm_config(struct comedi_device *dev, unsigned int *data) { struct ni_private *devpriv = dev->private; - unsigned up_count, down_count; + unsigned int up_count, down_count; switch (data[0]) { case INSN_CONFIG_PWM_OUTPUT: @@ -4287,7 +4143,7 @@ static int ni_6143_pwm_config(struct comedi_device *dev, unsigned int *data) { struct ni_private *devpriv = dev->private; - unsigned up_count, down_count; + unsigned int up_count, down_count; switch (data[0]) { case INSN_CONFIG_PWM_OUTPUT: @@ -4343,13 +4199,13 @@ static int ni_6143_pwm_config(struct comedi_device *dev, static int pack_mb88341(int addr, int val, int *bitstring) { /* - Fujitsu MB 88341 - Note that address bits are reversed. Thanks to - Ingo Keen for noticing this. - - Note also that the 88341 expects address values from - 1-12, whereas we use channel numbers 0-11. The NI - docs use 1-12, also, so be careful here. + * Fujitsu MB 88341 + * Note that address bits are reversed. Thanks to + * Ingo Keen for noticing this. + * + * Note also that the 88341 expects address values from + * 1-12, whereas we use channel numbers 0-11. The NI + * docs use 1-12, also, so be careful here. */ addr++; *bitstring = ((addr & 0x1) << 11) | @@ -4495,12 +4351,12 @@ static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s) s->n_chan = n_chans; if (diffbits) { - unsigned int *maxdata_list; + unsigned int *maxdata_list = devpriv->caldac_maxdata_list; if (n_chans > MAX_N_CALDACS) dev_err(dev->class_dev, "BUG! MAX_N_CALDACS too small\n"); - s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list; + s->maxdata_list = maxdata_list; chan = 0; for (i = 0; i < n_dacs; i++) { type = board->caldac[i]; @@ -4574,8 +4430,8 @@ static int ni_m_series_eeprom_insn_read(struct comedi_device *dev, return 1; } -static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, - unsigned chan) +static unsigned int ni_old_get_pfi_routing(struct comedi_device *dev, + unsigned int chan) { /* pre-m-series boards have fixed signals on pfi pins */ switch (chan) { @@ -4607,7 +4463,7 @@ static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, } static int ni_old_set_pfi_routing(struct comedi_device *dev, - unsigned chan, unsigned source) + unsigned int chan, unsigned int source) { /* pre-m-series boards have fixed signals on pfi pins */ if (source != ni_old_get_pfi_routing(dev, chan)) @@ -4615,21 +4471,21 @@ static int ni_old_set_pfi_routing(struct comedi_device *dev, return 2; } -static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev, - unsigned chan) +static unsigned int ni_m_series_get_pfi_routing(struct comedi_device *dev, + unsigned int chan) { struct ni_private *devpriv = dev->private; - const unsigned array_offset = chan / 3; + const unsigned int array_offset = chan / 3; return NI_M_PFI_OUT_SEL_TO_SRC(chan, devpriv->pfi_output_select_reg[array_offset]); } static int ni_m_series_set_pfi_routing(struct comedi_device *dev, - unsigned chan, unsigned source) + unsigned int chan, unsigned int source) { struct ni_private *devpriv = dev->private; - unsigned index = chan / 3; + unsigned int index = chan / 3; unsigned short val = devpriv->pfi_output_select_reg[index]; if ((source & 0x1f) != source) @@ -4643,7 +4499,8 @@ static int ni_m_series_set_pfi_routing(struct comedi_device *dev, return 2; } -static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan) +static unsigned int ni_get_pfi_routing(struct comedi_device *dev, + unsigned int chan) { struct ni_private *devpriv = dev->private; @@ -4652,8 +4509,8 @@ static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan) : ni_old_get_pfi_routing(dev, chan); } -static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan, - unsigned source) +static int ni_set_pfi_routing(struct comedi_device *dev, + unsigned int chan, unsigned int source) { struct ni_private *devpriv = dev->private; @@ -4663,11 +4520,11 @@ static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan, } static int ni_config_filter(struct comedi_device *dev, - unsigned pfi_channel, + unsigned int pfi_channel, enum ni_pfi_filter_select filter) { struct ni_private *devpriv = dev->private; - unsigned bits; + unsigned int bits; if (!devpriv->is_m_series) return -ENOTSUPP; @@ -4818,9 +4675,12 @@ static int cs5529_ai_insn_read(struct comedi_device *dev, unsigned int channel_select; const unsigned int INTERNAL_REF = 0x1000; - /* Set calibration adc source. Docs lie, reference select bits 8 to 11 + /* + * Set calibration adc source. Docs lie, reference select bits 8 to 11 * do nothing. bit 12 seems to chooses internal reference voltage, bit - * 13 causes the adc input to go overrange (maybe reads external reference?) */ + * 13 causes the adc input to go overrange (maybe reads external + * reference?) + */ if (insn->chanspec & CR_ALT_SOURCE) channel_select = INTERNAL_REF; else @@ -4875,27 +4735,28 @@ static int init_cs5529(struct comedi_device *dev) * Find best multiplier/divider to try and get the PLL running at 80 MHz * given an arbitrary frequency input clock. */ -static int ni_mseries_get_pll_parameters(unsigned reference_period_ns, - unsigned *freq_divider, - unsigned *freq_multiplier, - unsigned *actual_period_ns) -{ - unsigned div; - unsigned best_div = 1; - unsigned mult; - unsigned best_mult = 1; - static const unsigned pico_per_nano = 1000; - - const unsigned reference_picosec = reference_period_ns * pico_per_nano; - /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to - * 20 MHz for most timing clocks */ - static const unsigned target_picosec = 12500; - static const unsigned fudge_factor_80_to_20Mhz = 4; +static int ni_mseries_get_pll_parameters(unsigned int reference_period_ns, + unsigned int *freq_divider, + unsigned int *freq_multiplier, + unsigned int *actual_period_ns) +{ + unsigned int div; + unsigned int best_div = 1; + unsigned int mult; + unsigned int best_mult = 1; + static const unsigned int pico_per_nano = 1000; + const unsigned int reference_picosec = reference_period_ns * + pico_per_nano; + /* + * m-series wants the phased-locked loop to output 80MHz, which is + * divided by 4 to 20 MHz for most timing clocks + */ + static const unsigned int target_picosec = 12500; int best_period_picosec = 0; for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) { for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) { - unsigned new_period_ps = + unsigned int new_period_ps = (reference_picosec * div) / mult; if (abs(new_period_ps - target_picosec) < abs(best_period_picosec - target_picosec)) { @@ -4910,29 +4771,33 @@ static int ni_mseries_get_pll_parameters(unsigned reference_period_ns, *freq_divider = best_div; *freq_multiplier = best_mult; - *actual_period_ns = DIV_ROUND_CLOSEST(best_period_picosec * - fudge_factor_80_to_20Mhz, + /* return the actual period (* fudge factor for 80 to 20 MHz) */ + *actual_period_ns = DIV_ROUND_CLOSEST(best_period_picosec * 4, pico_per_nano); return 0; } static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, - unsigned source, unsigned period_ns) + unsigned int source, + unsigned int period_ns) { struct ni_private *devpriv = dev->private; - static const unsigned min_period_ns = 50; - static const unsigned max_period_ns = 1000; - static const unsigned timeout = 1000; - unsigned pll_control_bits; - unsigned freq_divider; - unsigned freq_multiplier; - unsigned rtsi; - unsigned i; + static const unsigned int min_period_ns = 50; + static const unsigned int max_period_ns = 1000; + static const unsigned int timeout = 1000; + unsigned int pll_control_bits; + unsigned int freq_divider; + unsigned int freq_multiplier; + unsigned int rtsi; + unsigned int i; int retval; if (source == NI_MIO_PLL_PXI10_CLOCK) period_ns = 100; - /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */ + /* + * These limits are somewhat arbitrary, but NI advertises 1 to 20MHz + * range so we'll use that. + */ if (period_ns < min_period_ns || period_ns > max_period_ns) { dev_err(dev->class_dev, "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n", @@ -4982,7 +4847,7 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG); devpriv->clock_source = source; - /* it seems to typically take a few hundred microseconds for PLL to lock */ + /* it takes a few hundred microseconds for PLL to lock */ for (i = 0; i < timeout; ++i) { if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED) break; @@ -4998,7 +4863,7 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, } static int ni_set_master_clock(struct comedi_device *dev, - unsigned source, unsigned period_ns) + unsigned int source, unsigned int period_ns) { struct ni_private *devpriv = dev->private; @@ -5043,7 +4908,7 @@ static int ni_set_master_clock(struct comedi_device *dev, } static int ni_valid_rtsi_output_source(struct comedi_device *dev, - unsigned chan, unsigned source) + unsigned int chan, unsigned int source) { struct ni_private *devpriv = dev->private; @@ -5078,7 +4943,7 @@ static int ni_valid_rtsi_output_source(struct comedi_device *dev, } static int ni_set_rtsi_routing(struct comedi_device *dev, - unsigned chan, unsigned src) + unsigned int chan, unsigned int src) { struct ni_private *devpriv = dev->private; @@ -5098,7 +4963,8 @@ static int ni_set_rtsi_routing(struct comedi_device *dev, return 2; } -static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan) +static unsigned int ni_get_rtsi_routing(struct comedi_device *dev, + unsigned int chan) { struct ni_private *devpriv = dev->private; @@ -5262,10 +5128,10 @@ static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s) static irqreturn_t ni_E_interrupt(int irq, void *d) { struct comedi_device *dev = d; + struct comedi_subdevice *s_ai = dev->read_subdev; + struct comedi_subdevice *s_ao = dev->write_subdev; unsigned short a_status; unsigned short b_status; - unsigned int ai_mite_status = 0; - unsigned int ao_mite_status = 0; unsigned long flags; #ifdef PCIDMA struct ni_private *devpriv = dev->private; @@ -5273,7 +5139,7 @@ static irqreturn_t ni_E_interrupt(int irq, void *d) if (!dev->attached) return IRQ_NONE; - smp_mb(); /* make sure dev->attached is checked before handler does anything else. */ + smp_mb(); /* make sure dev->attached is checked */ /* lock to avoid race with comedi_poll */ spin_lock_irqsave(&dev->spinlock, flags); @@ -5284,34 +5150,33 @@ static irqreturn_t ni_E_interrupt(int irq, void *d) unsigned long flags_too; spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too); - if (devpriv->ai_mite_chan) { - ai_mite_status = mite_get_status(devpriv->ai_mite_chan); - if (ai_mite_status & CHSR_LINKC) - writel(CHOR_CLRLC, - devpriv->mite->mite_io_addr + - MITE_CHOR(devpriv-> - ai_mite_chan->channel)); - } - if (devpriv->ao_mite_chan) { - ao_mite_status = mite_get_status(devpriv->ao_mite_chan); - if (ao_mite_status & CHSR_LINKC) - writel(CHOR_CLRLC, - devpriv->mite->mite_io_addr + - MITE_CHOR(devpriv-> - ao_mite_chan->channel)); - } + if (s_ai && devpriv->ai_mite_chan) + mite_ack_linkc(devpriv->ai_mite_chan, s_ai, false); + if (s_ao && devpriv->ao_mite_chan) + mite_ack_linkc(devpriv->ao_mite_chan, s_ao, false); spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too); } #endif ack_a_interrupt(dev, a_status); ack_b_interrupt(dev, b_status); - if ((a_status & NISTC_AI_STATUS1_INTA) || (ai_mite_status & CHSR_INT)) - handle_a_interrupt(dev, a_status, ai_mite_status); - if ((b_status & NISTC_AO_STATUS1_INTB) || (ao_mite_status & CHSR_INT)) - handle_b_interrupt(dev, b_status, ao_mite_status); + if (s_ai) { + if (a_status & NISTC_AI_STATUS1_INTA) + handle_a_interrupt(dev, s_ai, a_status); + /* handle any interrupt or dma events */ + comedi_handle_events(dev, s_ai); + } + if (s_ao) { + if (b_status & NISTC_AO_STATUS1_INTB) + handle_b_interrupt(dev, s_ao, b_status); + /* handle any interrupt or dma events */ + comedi_handle_events(dev, s_ao); + } handle_gpct_interrupt(dev, 0); handle_gpct_interrupt(dev, 1); - handle_cdio_interrupt(dev); +#ifdef PCIDMA + if (devpriv->is_m_series) + handle_cdio_interrupt(dev); +#endif spin_unlock_irqrestore(&dev->spinlock, flags); return IRQ_HANDLED; @@ -5333,7 +5198,7 @@ static int ni_alloc_private(struct comedi_device *dev) } static int ni_E_init(struct comedi_device *dev, - unsigned interrupt_pin, unsigned irq_polarity) + unsigned int interrupt_pin, unsigned int irq_polarity) { const struct ni_board_struct *board = dev->board_ptr; struct ni_private *devpriv = dev->private; @@ -5450,6 +5315,7 @@ static int ni_E_init(struct comedi_device *dev, s->maxdata = 1; s->range_table = &range_digital; if (devpriv->is_m_series) { +#ifdef PCIDMA s->subdev_flags |= SDF_LSAMPL; s->insn_bits = ni_m_series_dio_insn_bits; s->insn_config = ni_m_series_dio_insn_config; @@ -5469,6 +5335,7 @@ static int ni_E_init(struct comedi_device *dev, NI_M_CDI_CMD_RESET, NI_M_CDIO_CMD_REG); ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG); +#endif /* PCIDMA */ } else { s->insn_bits = ni_dio_insn_bits; s->insn_config = ni_dio_insn_config; @@ -5675,8 +5542,6 @@ static void mio_common_detach(struct comedi_device *dev) { struct ni_private *devpriv = dev->private; - if (devpriv) { - if (devpriv->counter_dev) - ni_gpct_device_destroy(devpriv->counter_dev); - } + if (devpriv) + ni_gpct_device_destroy(devpriv->counter_dev); } |