diff options
Diffstat (limited to 'drivers/staging/comedi/drivers/ni_pcimio.c')
| -rw-r--r-- | drivers/staging/comedi/drivers/ni_pcimio.c | 775 |
1 files changed, 189 insertions, 586 deletions
diff --git a/drivers/staging/comedi/drivers/ni_pcimio.c b/drivers/staging/comedi/drivers/ni_pcimio.c index 89300dc78e35..da61fa70decf 100644 --- a/drivers/staging/comedi/drivers/ni_pcimio.c +++ b/drivers/staging/comedi/drivers/ni_pcimio.c @@ -118,13 +118,6 @@ Bugs: #define PCIDMA -#define PCIMIO 1 -#undef ATMIO - -#define MAX_N_CALDACS (16+16+2) - -#define DRV_NAME "ni_pcimio" - /* These are not all the possible ao ranges for 628x boards. They can do OFFSET +- REFERENCE where OFFSET can be 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can @@ -218,87 +211,79 @@ static const struct ni_board_struct ni_boards[] = { [BOARD_PCIMIO_16XE_50] = { .name = "pci-mio-16xe-50", .n_adchan = 16, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 2048, .alwaysdither = 1, .gainlkup = ai_gain_8, .ai_speed = 50000, .n_aochan = 2, - .aobits = 12, + .ao_maxdata = 0x0fff, .ao_range_table = &range_bipolar10, .ao_speed = 50000, - .num_p0_dio_channels = 8, .caldac = { dac8800, dac8043 }, }, [BOARD_PCIMIO_16XE_10] = { .name = "pci-mio-16xe-10", /* aka pci-6030E */ .n_adchan = 16, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 512, .alwaysdither = 1, .gainlkup = ai_gain_14, .ai_speed = 10000, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 2048, .ao_range_table = &range_ni_E_ao_ext, - .ao_unipolar = 1, .ao_speed = 10000, - .num_p0_dio_channels = 8, .caldac = { dac8800, dac8043, ad8522 }, }, [BOARD_PCI6014] = { .name = "pci-6014", .n_adchan = 16, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 512, .alwaysdither = 1, .gainlkup = ai_gain_4, .ai_speed = 5000, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_range_table = &range_bipolar10, .ao_speed = 100000, - .num_p0_dio_channels = 8, .caldac = { ad8804_debug }, }, [BOARD_PXI6030E] = { .name = "pxi-6030e", .n_adchan = 16, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 512, .alwaysdither = 1, .gainlkup = ai_gain_14, .ai_speed = 10000, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 2048, .ao_range_table = &range_ni_E_ao_ext, - .ao_unipolar = 1, .ao_speed = 10000, - .num_p0_dio_channels = 8, .caldac = { dac8800, dac8043, ad8522 }, }, [BOARD_PCIMIO_16E_1] = { .name = "pci-mio-16e-1", /* aka pci-6070e */ .n_adchan = 16, - .adbits = 12, + .ai_maxdata = 0x0fff, .ai_fifo_depth = 512, .gainlkup = ai_gain_16, .ai_speed = 800, .n_aochan = 2, - .aobits = 12, + .ao_maxdata = 0x0fff, .ao_fifo_depth = 2048, .ao_range_table = &range_ni_E_ao_ext, - .ao_unipolar = 1, .ao_speed = 1000, - .num_p0_dio_channels = 8, .caldac = { mb88341 }, }, [BOARD_PCIMIO_16E_4] = { .name = "pci-mio-16e-4", /* aka pci-6040e */ .n_adchan = 16, - .adbits = 12, + .ai_maxdata = 0x0fff, .ai_fifo_depth = 512, .gainlkup = ai_gain_16, /* @@ -307,216 +292,195 @@ static const struct ni_board_struct ni_boards[] = { */ .ai_speed = 2000, .n_aochan = 2, - .aobits = 12, + .ao_maxdata = 0x0fff, .ao_fifo_depth = 512, .ao_range_table = &range_ni_E_ao_ext, - .ao_unipolar = 1, .ao_speed = 1000, - .num_p0_dio_channels = 8, .caldac = { ad8804_debug }, /* doc says mb88341 */ }, [BOARD_PXI6040E] = { .name = "pxi-6040e", .n_adchan = 16, - .adbits = 12, + .ai_maxdata = 0x0fff, .ai_fifo_depth = 512, .gainlkup = ai_gain_16, .ai_speed = 2000, .n_aochan = 2, - .aobits = 12, + .ao_maxdata = 0x0fff, .ao_fifo_depth = 512, .ao_range_table = &range_ni_E_ao_ext, - .ao_unipolar = 1, .ao_speed = 1000, - .num_p0_dio_channels = 8, .caldac = { mb88341 }, }, [BOARD_PCI6031E] = { .name = "pci-6031e", .n_adchan = 64, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 512, .alwaysdither = 1, .gainlkup = ai_gain_14, .ai_speed = 10000, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 2048, .ao_range_table = &range_ni_E_ao_ext, - .ao_unipolar = 1, .ao_speed = 10000, - .num_p0_dio_channels = 8, .caldac = { dac8800, dac8043, ad8522 }, }, [BOARD_PCI6032E] = { .name = "pci-6032e", .n_adchan = 16, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 512, .alwaysdither = 1, .gainlkup = ai_gain_14, .ai_speed = 10000, - .num_p0_dio_channels = 8, .caldac = { dac8800, dac8043, ad8522 }, }, [BOARD_PCI6033E] = { .name = "pci-6033e", .n_adchan = 64, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 512, .alwaysdither = 1, .gainlkup = ai_gain_14, .ai_speed = 10000, - .num_p0_dio_channels = 8, .caldac = { dac8800, dac8043, ad8522 }, }, [BOARD_PCI6071E] = { .name = "pci-6071e", .n_adchan = 64, - .adbits = 12, + .ai_maxdata = 0x0fff, .ai_fifo_depth = 512, .alwaysdither = 1, .gainlkup = ai_gain_16, .ai_speed = 800, .n_aochan = 2, - .aobits = 12, + .ao_maxdata = 0x0fff, .ao_fifo_depth = 2048, .ao_range_table = &range_ni_E_ao_ext, - .ao_unipolar = 1, .ao_speed = 1000, - .num_p0_dio_channels = 8, .caldac = { ad8804_debug }, }, [BOARD_PCI6023E] = { .name = "pci-6023e", .n_adchan = 16, - .adbits = 12, + .ai_maxdata = 0x0fff, .ai_fifo_depth = 512, .gainlkup = ai_gain_4, .ai_speed = 5000, - .num_p0_dio_channels = 8, .caldac = { ad8804_debug }, /* manual is wrong */ }, [BOARD_PCI6024E] = { .name = "pci-6024e", .n_adchan = 16, - .adbits = 12, + .ai_maxdata = 0x0fff, .ai_fifo_depth = 512, .gainlkup = ai_gain_4, .ai_speed = 5000, .n_aochan = 2, - .aobits = 12, + .ao_maxdata = 0x0fff, .ao_range_table = &range_bipolar10, .ao_speed = 100000, - .num_p0_dio_channels = 8, .caldac = { ad8804_debug }, /* manual is wrong */ }, [BOARD_PCI6025E] = { .name = "pci-6025e", .n_adchan = 16, - .adbits = 12, + .ai_maxdata = 0x0fff, .ai_fifo_depth = 512, .gainlkup = ai_gain_4, .ai_speed = 5000, .n_aochan = 2, - .aobits = 12, + .ao_maxdata = 0x0fff, .ao_range_table = &range_bipolar10, .ao_speed = 100000, - .num_p0_dio_channels = 8, .caldac = { ad8804_debug }, /* manual is wrong */ .has_8255 = 1, }, [BOARD_PXI6025E] = { .name = "pxi-6025e", .n_adchan = 16, - .adbits = 12, + .ai_maxdata = 0x0fff, .ai_fifo_depth = 512, .gainlkup = ai_gain_4, .ai_speed = 5000, .n_aochan = 2, - .aobits = 12, + .ao_maxdata = 0x0fff, .ao_range_table = &range_ni_E_ao_ext, - .ao_unipolar = 1, .ao_speed = 100000, - .num_p0_dio_channels = 8, .caldac = { ad8804_debug }, /* manual is wrong */ .has_8255 = 1, }, [BOARD_PCI6034E] = { .name = "pci-6034e", .n_adchan = 16, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 512, .alwaysdither = 1, .gainlkup = ai_gain_4, .ai_speed = 5000, - .num_p0_dio_channels = 8, .caldac = { ad8804_debug }, }, [BOARD_PCI6035E] = { .name = "pci-6035e", .n_adchan = 16, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 512, .alwaysdither = 1, .gainlkup = ai_gain_4, .ai_speed = 5000, .n_aochan = 2, - .aobits = 12, + .ao_maxdata = 0x0fff, .ao_range_table = &range_bipolar10, .ao_speed = 100000, - .num_p0_dio_channels = 8, .caldac = { ad8804_debug }, }, [BOARD_PCI6052E] = { .name = "pci-6052e", .n_adchan = 16, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 512, .alwaysdither = 1, .gainlkup = ai_gain_16, .ai_speed = 3000, .n_aochan = 2, - .aobits = 16, - .ao_unipolar = 1, + .ao_maxdata = 0xffff, .ao_fifo_depth = 2048, .ao_range_table = &range_ni_E_ao_ext, .ao_speed = 3000, - .num_p0_dio_channels = 8, /* manual is wrong */ .caldac = { ad8804_debug, ad8804_debug, ad8522 }, }, [BOARD_PCI6110] = { .name = "pci-6110", .n_adchan = 4, - .adbits = 12, + .ai_maxdata = 0x0fff, .ai_fifo_depth = 8192, .alwaysdither = 0, .gainlkup = ai_gain_611x, .ai_speed = 200, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .reg_type = ni_reg_611x, .ao_range_table = &range_bipolar10, .ao_fifo_depth = 2048, .ao_speed = 250, - .num_p0_dio_channels = 8, .caldac = { ad8804, ad8804 }, }, [BOARD_PCI6111] = { .name = "pci-6111", .n_adchan = 2, - .adbits = 12, + .ai_maxdata = 0x0fff, .ai_fifo_depth = 8192, .gainlkup = ai_gain_611x, .ai_speed = 200, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .reg_type = ni_reg_611x, .ao_range_table = &range_bipolar10, .ao_fifo_depth = 2048, .ao_speed = 250, - .num_p0_dio_channels = 8, .caldac = { ad8804, ad8804 }, }, #if 0 @@ -524,16 +488,15 @@ static const struct ni_board_struct ni_boards[] = { [BOARD_PCI6115] = { /* .device_id = 0x2ed0, */ .name = "pci-6115", .n_adchan = 4, - .adbits = 12, + .ai_maxdata = 0x0fff, .ai_fifo_depth = 8192, .gainlkup = ai_gain_611x, .ai_speed = 100, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_671x = 1, .ao_fifo_depth = 2048, .ao_speed = 250, - .num_p0_dio_channels = 8, .reg_611x = 1, /* XXX */ .caldac = { ad8804_debug, ad8804_debug, ad8804_debug }, @@ -543,17 +506,16 @@ static const struct ni_board_struct ni_boards[] = { [BOARD_PXI6115] = { /* .device_id = ????, */ .name = "pxi-6115", .n_adchan = 4, - .adbits = 12, + .ai_maxdata = 0x0fff, .ai_fifo_depth = 8192, .gainlkup = ai_gain_611x, .ai_speed = 100, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_671x = 1, .ao_fifo_depth = 2048, .ao_speed = 250, .reg_611x = 1, - .num_p0_dio_channels = 8, /* XXX */ .caldac = { ad8804_debug, ad8804_debug, ad8804_debug }, }, @@ -561,56 +523,51 @@ static const struct ni_board_struct ni_boards[] = { [BOARD_PCI6711] = { .name = "pci-6711", .n_aochan = 4, - .aobits = 12, + .ao_maxdata = 0x0fff, /* data sheet says 8192, but fifo really holds 16384 samples */ .ao_fifo_depth = 16384, .ao_range_table = &range_bipolar10, .ao_speed = 1000, - .num_p0_dio_channels = 8, .reg_type = ni_reg_6711, .caldac = { ad8804_debug }, }, [BOARD_PXI6711] = { .name = "pxi-6711", .n_aochan = 4, - .aobits = 12, + .ao_maxdata = 0x0fff, .ao_fifo_depth = 16384, .ao_range_table = &range_bipolar10, .ao_speed = 1000, - .num_p0_dio_channels = 8, .reg_type = ni_reg_6711, .caldac = { ad8804_debug }, }, [BOARD_PCI6713] = { .name = "pci-6713", .n_aochan = 8, - .aobits = 12, + .ao_maxdata = 0x0fff, .ao_fifo_depth = 16384, .ao_range_table = &range_bipolar10, .ao_speed = 1000, - .num_p0_dio_channels = 8, .reg_type = ni_reg_6713, .caldac = { ad8804_debug, ad8804_debug }, }, [BOARD_PXI6713] = { .name = "pxi-6713", .n_aochan = 8, - .aobits = 12, + .ao_maxdata = 0x0fff, .ao_fifo_depth = 16384, .ao_range_table = &range_bipolar10, .ao_speed = 1000, - .num_p0_dio_channels = 8, .reg_type = ni_reg_6713, .caldac = { ad8804_debug, ad8804_debug }, }, [BOARD_PCI6731] = { .name = "pci-6731", .n_aochan = 4, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 8192, .ao_range_table = &range_bipolar10, .ao_speed = 1000, - .num_p0_dio_channels = 8, .reg_type = ni_reg_6711, .caldac = { ad8804_debug }, }, @@ -618,10 +575,9 @@ static const struct ni_board_struct ni_boards[] = { [BOARD_PXI6731] = { /* .device_id = ????, */ .name = "pxi-6731", .n_aochan = 4, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 8192, .ao_range_table = &range_bipolar10, - .num_p0_dio_channels = 8, .reg_type = ni_reg_6711, .caldac = { ad8804_debug }, }, @@ -629,759 +585,462 @@ static const struct ni_board_struct ni_boards[] = { [BOARD_PCI6733] = { .name = "pci-6733", .n_aochan = 8, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 16384, .ao_range_table = &range_bipolar10, .ao_speed = 1000, - .num_p0_dio_channels = 8, .reg_type = ni_reg_6713, .caldac = { ad8804_debug, ad8804_debug }, }, [BOARD_PXI6733] = { .name = "pxi-6733", .n_aochan = 8, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 16384, .ao_range_table = &range_bipolar10, .ao_speed = 1000, - .num_p0_dio_channels = 8, .reg_type = ni_reg_6713, .caldac = { ad8804_debug, ad8804_debug }, }, [BOARD_PXI6071E] = { .name = "pxi-6071e", .n_adchan = 64, - .adbits = 12, + .ai_maxdata = 0x0fff, .ai_fifo_depth = 512, .alwaysdither = 1, .gainlkup = ai_gain_16, .ai_speed = 800, .n_aochan = 2, - .aobits = 12, + .ao_maxdata = 0x0fff, .ao_fifo_depth = 2048, .ao_range_table = &range_ni_E_ao_ext, - .ao_unipolar = 1, .ao_speed = 1000, - .num_p0_dio_channels = 8, .caldac = { ad8804_debug }, }, [BOARD_PXI6070E] = { .name = "pxi-6070e", .n_adchan = 16, - .adbits = 12, + .ai_maxdata = 0x0fff, .ai_fifo_depth = 512, .alwaysdither = 1, .gainlkup = ai_gain_16, .ai_speed = 800, .n_aochan = 2, - .aobits = 12, + .ao_maxdata = 0x0fff, .ao_fifo_depth = 2048, .ao_range_table = &range_ni_E_ao_ext, - .ao_unipolar = 1, .ao_speed = 1000, - .num_p0_dio_channels = 8, .caldac = { ad8804_debug }, }, [BOARD_PXI6052E] = { .name = "pxi-6052e", .n_adchan = 16, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 512, .alwaysdither = 1, .gainlkup = ai_gain_16, .ai_speed = 3000, .n_aochan = 2, - .aobits = 16, - .ao_unipolar = 1, + .ao_maxdata = 0xffff, .ao_fifo_depth = 2048, .ao_range_table = &range_ni_E_ao_ext, .ao_speed = 3000, - .num_p0_dio_channels = 8, .caldac = { mb88341, mb88341, ad8522 }, }, [BOARD_PXI6031E] = { .name = "pxi-6031e", .n_adchan = 64, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 512, .alwaysdither = 1, .gainlkup = ai_gain_14, .ai_speed = 10000, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 2048, .ao_range_table = &range_ni_E_ao_ext, - .ao_unipolar = 1, .ao_speed = 10000, - .num_p0_dio_channels = 8, .caldac = { dac8800, dac8043, ad8522 }, }, [BOARD_PCI6036E] = { .name = "pci-6036e", .n_adchan = 16, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 512, .alwaysdither = 1, .gainlkup = ai_gain_4, .ai_speed = 5000, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_range_table = &range_bipolar10, .ao_speed = 100000, - .num_p0_dio_channels = 8, .caldac = { ad8804_debug }, }, [BOARD_PCI6220] = { .name = "pci-6220", .n_adchan = 16, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 512, /* FIXME: guess */ .gainlkup = ai_gain_622x, .ai_speed = 4000, - .num_p0_dio_channels = 8, .reg_type = ni_reg_622x, .caldac = { caldac_none }, }, [BOARD_PCI6221] = { .name = "pci-6221", .n_adchan = 16, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 4095, .gainlkup = ai_gain_622x, .ai_speed = 4000, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 8191, .ao_range_table = &range_bipolar10, .reg_type = ni_reg_622x, .ao_speed = 1200, - .num_p0_dio_channels = 8, .caldac = { caldac_none }, }, [BOARD_PCI6221_37PIN] = { .name = "pci-6221_37pin", .n_adchan = 16, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 4095, .gainlkup = ai_gain_622x, .ai_speed = 4000, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 8191, .ao_range_table = &range_bipolar10, .reg_type = ni_reg_622x, .ao_speed = 1200, - .num_p0_dio_channels = 8, .caldac = { caldac_none }, }, [BOARD_PCI6224] = { .name = "pci-6224", .n_adchan = 32, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 4095, .gainlkup = ai_gain_622x, .ai_speed = 4000, .reg_type = ni_reg_622x, - .num_p0_dio_channels = 32, + .has_32dio_chan = 1, .caldac = { caldac_none }, }, [BOARD_PXI6224] = { .name = "pxi-6224", .n_adchan = 32, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 4095, .gainlkup = ai_gain_622x, .ai_speed = 4000, .reg_type = ni_reg_622x, - .num_p0_dio_channels = 32, + .has_32dio_chan = 1, .caldac = { caldac_none }, }, [BOARD_PCI6225] = { .name = "pci-6225", .n_adchan = 80, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 4095, .gainlkup = ai_gain_622x, .ai_speed = 4000, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 8191, .ao_range_table = &range_bipolar10, .reg_type = ni_reg_622x, .ao_speed = 1200, - .num_p0_dio_channels = 32, + .has_32dio_chan = 1, .caldac = { caldac_none }, }, [BOARD_PXI6225] = { .name = "pxi-6225", .n_adchan = 80, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 4095, .gainlkup = ai_gain_622x, .ai_speed = 4000, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 8191, .ao_range_table = &range_bipolar10, .reg_type = ni_reg_622x, .ao_speed = 1200, - .num_p0_dio_channels = 32, + .has_32dio_chan = 1, .caldac = { caldac_none }, }, [BOARD_PCI6229] = { .name = "pci-6229", .n_adchan = 32, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 4095, .gainlkup = ai_gain_622x, .ai_speed = 4000, .n_aochan = 4, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 8191, .ao_range_table = &range_bipolar10, .reg_type = ni_reg_622x, .ao_speed = 1200, - .num_p0_dio_channels = 32, + .has_32dio_chan = 1, .caldac = { caldac_none }, }, [BOARD_PCI6250] = { .name = "pci-6250", .n_adchan = 16, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 4095, .gainlkup = ai_gain_628x, .ai_speed = 800, .reg_type = ni_reg_625x, - .num_p0_dio_channels = 8, .caldac = { caldac_none }, }, [BOARD_PCI6251] = { .name = "pci-6251", .n_adchan = 16, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 4095, .gainlkup = ai_gain_628x, .ai_speed = 800, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 8191, .ao_range_table = &range_ni_M_625x_ao, .reg_type = ni_reg_625x, .ao_speed = 350, - .num_p0_dio_channels = 8, .caldac = { caldac_none }, }, [BOARD_PCIE6251] = { .name = "pcie-6251", .n_adchan = 16, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 4095, .gainlkup = ai_gain_628x, .ai_speed = 800, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 8191, .ao_range_table = &range_ni_M_625x_ao, .reg_type = ni_reg_625x, .ao_speed = 350, - .num_p0_dio_channels = 8, .caldac = { caldac_none }, }, [BOARD_PXIE6251] = { .name = "pxie-6251", .n_adchan = 16, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 4095, .gainlkup = ai_gain_628x, .ai_speed = 800, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 8191, .ao_range_table = &range_ni_M_625x_ao, .reg_type = ni_reg_625x, .ao_speed = 350, - .num_p0_dio_channels = 8, .caldac = { caldac_none }, }, [BOARD_PCI6254] = { .name = "pci-6254", .n_adchan = 32, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 4095, .gainlkup = ai_gain_628x, .ai_speed = 800, .reg_type = ni_reg_625x, - .num_p0_dio_channels = 32, + .has_32dio_chan = 1, .caldac = { caldac_none }, }, [BOARD_PCI6259] = { .name = "pci-6259", .n_adchan = 32, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 4095, .gainlkup = ai_gain_628x, .ai_speed = 800, .n_aochan = 4, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 8191, .ao_range_table = &range_ni_M_625x_ao, .reg_type = ni_reg_625x, .ao_speed = 350, - .num_p0_dio_channels = 32, + .has_32dio_chan = 1, .caldac = { caldac_none }, }, [BOARD_PCIE6259] = { .name = "pcie-6259", .n_adchan = 32, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 4095, .gainlkup = ai_gain_628x, .ai_speed = 800, .n_aochan = 4, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 8191, .ao_range_table = &range_ni_M_625x_ao, .reg_type = ni_reg_625x, .ao_speed = 350, - .num_p0_dio_channels = 32, + .has_32dio_chan = 1, .caldac = { caldac_none }, }, [BOARD_PCI6280] = { .name = "pci-6280", .n_adchan = 16, - .adbits = 18, + .ai_maxdata = 0x3ffff, .ai_fifo_depth = 2047, .gainlkup = ai_gain_628x, .ai_speed = 1600, .ao_fifo_depth = 8191, .reg_type = ni_reg_628x, - .num_p0_dio_channels = 8, .caldac = { caldac_none }, }, [BOARD_PCI6281] = { .name = "pci-6281", .n_adchan = 16, - .adbits = 18, + .ai_maxdata = 0x3ffff, .ai_fifo_depth = 2047, .gainlkup = ai_gain_628x, .ai_speed = 1600, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 8191, .ao_range_table = &range_ni_M_628x_ao, .reg_type = ni_reg_628x, - .ao_unipolar = 1, .ao_speed = 350, - .num_p0_dio_channels = 8, .caldac = { caldac_none }, }, [BOARD_PXI6281] = { .name = "pxi-6281", .n_adchan = 16, - .adbits = 18, + .ai_maxdata = 0x3ffff, .ai_fifo_depth = 2047, .gainlkup = ai_gain_628x, .ai_speed = 1600, .n_aochan = 2, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 8191, .ao_range_table = &range_ni_M_628x_ao, .reg_type = ni_reg_628x, - .ao_unipolar = 1, .ao_speed = 350, - .num_p0_dio_channels = 8, .caldac = { caldac_none }, }, [BOARD_PCI6284] = { .name = "pci-6284", .n_adchan = 32, - .adbits = 18, + .ai_maxdata = 0x3ffff, .ai_fifo_depth = 2047, .gainlkup = ai_gain_628x, .ai_speed = 1600, .reg_type = ni_reg_628x, - .num_p0_dio_channels = 32, + .has_32dio_chan = 1, .caldac = { caldac_none }, }, [BOARD_PCI6289] = { .name = "pci-6289", .n_adchan = 32, - .adbits = 18, + .ai_maxdata = 0x3ffff, .ai_fifo_depth = 2047, .gainlkup = ai_gain_628x, .ai_speed = 1600, .n_aochan = 4, - .aobits = 16, + .ao_maxdata = 0xffff, .ao_fifo_depth = 8191, .ao_range_table = &range_ni_M_628x_ao, .reg_type = ni_reg_628x, - .ao_unipolar = 1, .ao_speed = 350, - .num_p0_dio_channels = 32, + .has_32dio_chan = 1, .caldac = { caldac_none }, }, [BOARD_PCI6143] = { .name = "pci-6143", .n_adchan = 8, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 1024, .gainlkup = ai_gain_6143, .ai_speed = 4000, .reg_type = ni_reg_6143, - .num_p0_dio_channels = 8, .caldac = { ad8804_debug, ad8804_debug }, }, [BOARD_PXI6143] = { .name = "pxi-6143", .n_adchan = 8, - .adbits = 16, + .ai_maxdata = 0xffff, .ai_fifo_depth = 1024, .gainlkup = ai_gain_6143, .ai_speed = 4000, .reg_type = ni_reg_6143, - .num_p0_dio_channels = 8, .caldac = { ad8804_debug, ad8804_debug }, }, }; -struct ni_private { -NI_PRIVATE_COMMON}; - -/* How we access registers */ - -#define ni_writel(a, b) (writel((a), devpriv->mite->daq_io_addr + (b))) -#define ni_readl(a) (readl(devpriv->mite->daq_io_addr + (a))) -#define ni_writew(a, b) (writew((a), devpriv->mite->daq_io_addr + (b))) -#define ni_readw(a) (readw(devpriv->mite->daq_io_addr + (a))) -#define ni_writeb(a, b) (writeb((a), devpriv->mite->daq_io_addr + (b))) -#define ni_readb(a) (readb(devpriv->mite->daq_io_addr + (a))) - -/* How we access STC registers */ - -/* We automatically take advantage of STC registers that can be - * read/written directly in the I/O space of the board. Most - * PCIMIO devices map the low 8 STC registers to iobase+addr*2. - * The 611x devices map the write registers to iobase+addr*2, and - * the read registers to iobase+(addr-1)*2. */ -/* However, the 611x boards still aren't working, so I'm disabling - * non-windowed STC access temporarily */ +#include "ni_mio_common.c" -static void e_series_win_out(struct comedi_device *dev, uint16_t data, int reg) +static int pcimio_ai_change(struct comedi_device *dev, + struct comedi_subdevice *s) { struct ni_private *devpriv = dev->private; - unsigned long flags; + int ret; + + ret = mite_buf_change(devpriv->ai_mite_ring, s); + if (ret < 0) + return ret; - spin_lock_irqsave(&devpriv->window_lock, flags); - ni_writew(reg, Window_Address); - ni_writew(data, Window_Data); - spin_unlock_irqrestore(&devpriv->window_lock, flags); + return 0; } -static uint16_t e_series_win_in(struct comedi_device *dev, int reg) +static int pcimio_ao_change(struct comedi_device *dev, + struct comedi_subdevice *s) { struct ni_private *devpriv = dev->private; - unsigned long flags; - uint16_t ret; + int ret; - spin_lock_irqsave(&devpriv->window_lock, flags); - ni_writew(reg, Window_Address); - ret = ni_readw(Window_Data); - spin_unlock_irqrestore(&devpriv->window_lock, flags); + ret = mite_buf_change(devpriv->ao_mite_ring, s); + if (ret < 0) + return ret; - return ret; + return 0; } -static void m_series_stc_writew(struct comedi_device *dev, uint16_t data, - int reg) +static int pcimio_gpct0_change(struct comedi_device *dev, + struct comedi_subdevice *s) { struct ni_private *devpriv = dev->private; - unsigned offset; - - switch (reg) { - case ADC_FIFO_Clear: - offset = M_Offset_AI_FIFO_Clear; - break; - case AI_Command_1_Register: - offset = M_Offset_AI_Command_1; - break; - case AI_Command_2_Register: - offset = M_Offset_AI_Command_2; - break; - case AI_Mode_1_Register: - offset = M_Offset_AI_Mode_1; - break; - case AI_Mode_2_Register: - offset = M_Offset_AI_Mode_2; - break; - case AI_Mode_3_Register: - offset = M_Offset_AI_Mode_3; - break; - case AI_Output_Control_Register: - offset = M_Offset_AI_Output_Control; - break; - case AI_Personal_Register: - offset = M_Offset_AI_Personal; - break; - case AI_SI2_Load_A_Register: - /* this is actually a 32 bit register on m series boards */ - ni_writel(data, M_Offset_AI_SI2_Load_A); - return; - break; - case AI_SI2_Load_B_Register: - /* this is actually a 32 bit register on m series boards */ - ni_writel(data, M_Offset_AI_SI2_Load_B); - return; - break; - case AI_START_STOP_Select_Register: - offset = M_Offset_AI_START_STOP_Select; - break; - case AI_Trigger_Select_Register: - offset = M_Offset_AI_Trigger_Select; - break; - case Analog_Trigger_Etc_Register: - offset = M_Offset_Analog_Trigger_Etc; - break; - case AO_Command_1_Register: - offset = M_Offset_AO_Command_1; - break; - case AO_Command_2_Register: - offset = M_Offset_AO_Command_2; - break; - case AO_Mode_1_Register: - offset = M_Offset_AO_Mode_1; - break; - case AO_Mode_2_Register: - offset = M_Offset_AO_Mode_2; - break; - case AO_Mode_3_Register: - offset = M_Offset_AO_Mode_3; - break; - case AO_Output_Control_Register: - offset = M_Offset_AO_Output_Control; - break; - case AO_Personal_Register: - offset = M_Offset_AO_Personal; - break; - case AO_Start_Select_Register: - offset = M_Offset_AO_Start_Select; - break; - case AO_Trigger_Select_Register: - offset = M_Offset_AO_Trigger_Select; - break; - case Clock_and_FOUT_Register: - offset = M_Offset_Clock_and_FOUT; - break; - case Configuration_Memory_Clear: - offset = M_Offset_Configuration_Memory_Clear; - break; - case DAC_FIFO_Clear: - offset = M_Offset_AO_FIFO_Clear; - break; - case DIO_Control_Register: - dev_dbg(dev->class_dev, - "%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n", - __func__, reg); - return; - break; - case G_Autoincrement_Register(0): - offset = M_Offset_G0_Autoincrement; - break; - case G_Autoincrement_Register(1): - offset = M_Offset_G1_Autoincrement; - break; - case G_Command_Register(0): - offset = M_Offset_G0_Command; - break; - case G_Command_Register(1): - offset = M_Offset_G1_Command; - break; - case G_Input_Select_Register(0): - offset = M_Offset_G0_Input_Select; - break; - case G_Input_Select_Register(1): - offset = M_Offset_G1_Input_Select; - break; - case G_Mode_Register(0): - offset = M_Offset_G0_Mode; - break; - case G_Mode_Register(1): - offset = M_Offset_G1_Mode; - break; - case Interrupt_A_Ack_Register: - offset = M_Offset_Interrupt_A_Ack; - break; - case Interrupt_A_Enable_Register: - offset = M_Offset_Interrupt_A_Enable; - break; - case Interrupt_B_Ack_Register: - offset = M_Offset_Interrupt_B_Ack; - break; - case Interrupt_B_Enable_Register: - offset = M_Offset_Interrupt_B_Enable; - break; - case Interrupt_Control_Register: - offset = M_Offset_Interrupt_Control; - break; - case IO_Bidirection_Pin_Register: - offset = M_Offset_IO_Bidirection_Pin; - break; - case Joint_Reset_Register: - offset = M_Offset_Joint_Reset; - break; - case RTSI_Trig_A_Output_Register: - offset = M_Offset_RTSI_Trig_A_Output; - break; - case RTSI_Trig_B_Output_Register: - offset = M_Offset_RTSI_Trig_B_Output; - break; - case RTSI_Trig_Direction_Register: - offset = M_Offset_RTSI_Trig_Direction; - break; - /* FIXME: DIO_Output_Register (16 bit reg) is replaced by M_Offset_Static_Digital_Output (32 bit) - and M_Offset_SCXI_Serial_Data_Out (8 bit) */ - default: - dev_warn(dev->class_dev, - "%s: bug! unhandled register=0x%x in switch.\n", - __func__, reg); - BUG(); - return; - break; - } - ni_writew(data, offset); -} + int ret; -static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg) -{ - struct ni_private *devpriv = dev->private; - unsigned offset; - - switch (reg) { - case AI_Status_1_Register: - offset = M_Offset_AI_Status_1; - break; - case AO_Status_1_Register: - offset = M_Offset_AO_Status_1; - break; - case AO_Status_2_Register: - offset = M_Offset_AO_Status_2; - break; - case DIO_Serial_Input_Register: - return ni_readb(M_Offset_SCXI_Serial_Data_In); - break; - case Joint_Status_1_Register: - offset = M_Offset_Joint_Status_1; - break; - case Joint_Status_2_Register: - offset = M_Offset_Joint_Status_2; - break; - case G_Status_Register: - offset = M_Offset_G01_Status; - break; - default: - dev_warn(dev->class_dev, - "%s: bug! unhandled register=0x%x in switch.\n", - __func__, reg); - BUG(); - return 0; - break; - } - return ni_readw(offset); + ret = mite_buf_change(devpriv->gpct_mite_ring[0], s); + if (ret < 0) + return ret; + + return 0; } -static void m_series_stc_writel(struct comedi_device *dev, uint32_t data, - int reg) +static int pcimio_gpct1_change(struct comedi_device *dev, + struct comedi_subdevice *s) { struct ni_private *devpriv = dev->private; - unsigned offset; - - switch (reg) { - case AI_SC_Load_A_Registers: - offset = M_Offset_AI_SC_Load_A; - break; - case AI_SI_Load_A_Registers: - offset = M_Offset_AI_SI_Load_A; - break; - case AO_BC_Load_A_Register: - offset = M_Offset_AO_BC_Load_A; - break; - case AO_UC_Load_A_Register: - offset = M_Offset_AO_UC_Load_A; - break; - case AO_UI_Load_A_Register: - offset = M_Offset_AO_UI_Load_A; - break; - case G_Load_A_Register(0): - offset = M_Offset_G0_Load_A; - break; - case G_Load_A_Register(1): - offset = M_Offset_G1_Load_A; - break; - case G_Load_B_Register(0): - offset = M_Offset_G0_Load_B; - break; - case G_Load_B_Register(1): - offset = M_Offset_G1_Load_B; - break; - default: - dev_warn(dev->class_dev, - "%s: bug! unhandled register=0x%x in switch.\n", - __func__, reg); - BUG(); - return; - break; - } - ni_writel(data, offset); + int ret; + + ret = mite_buf_change(devpriv->gpct_mite_ring[1], s); + if (ret < 0) + return ret; + + return 0; } -static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg) +static int pcimio_dio_change(struct comedi_device *dev, + struct comedi_subdevice *s) { struct ni_private *devpriv = dev->private; - unsigned offset; - - switch (reg) { - case G_HW_Save_Register(0): - offset = M_Offset_G0_HW_Save; - break; - case G_HW_Save_Register(1): - offset = M_Offset_G1_HW_Save; - break; - case G_Save_Register(0): - offset = M_Offset_G0_Save; - break; - case G_Save_Register(1): - offset = M_Offset_G1_Save; - break; - default: - dev_warn(dev->class_dev, - "%s: bug! unhandled register=0x%x in switch.\n", - __func__, reg); - BUG(); - return 0; - break; - } - return ni_readl(offset); -} - -#define interrupt_pin(a) 0 -#define IRQ_POLARITY 1 + int ret; -#define NI_E_IRQ_FLAGS IRQF_SHARED + ret = mite_buf_change(devpriv->cdo_mite_ring, s); + if (ret < 0) + return ret; -#include "ni_mio_common.c" + return 0; +} -static int pcimio_ai_change(struct comedi_device *dev, - struct comedi_subdevice *s, unsigned long new_size); -static int pcimio_ao_change(struct comedi_device *dev, - struct comedi_subdevice *s, unsigned long new_size); -static int pcimio_gpct0_change(struct comedi_device *dev, - struct comedi_subdevice *s, - unsigned long new_size); -static int pcimio_gpct1_change(struct comedi_device *dev, - struct comedi_subdevice *s, - unsigned long new_size); -static int pcimio_dio_change(struct comedi_device *dev, - struct comedi_subdevice *s, - unsigned long new_size); static void m_series_init_eeprom_buffer(struct comedi_device *dev) { @@ -1408,12 +1067,12 @@ static void m_series_init_eeprom_buffer(struct comedi_device *dev) BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number)); for (i = 0; i < serial_number_eeprom_length; ++i) { char *byte_ptr = (char *)&devpriv->serial_number + i; - *byte_ptr = ni_readb(serial_number_eeprom_offset + i); + *byte_ptr = ni_readb(dev, serial_number_eeprom_offset + i); } devpriv->serial_number = be32_to_cpu(devpriv->serial_number); for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i) - devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i); + devpriv->eeprom_buffer[i] = ni_readb(dev, Start_Cal_EEPROM + i); writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1); writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR); @@ -1427,21 +1086,26 @@ static void init_6143(struct comedi_device *dev) struct ni_private *devpriv = dev->private; /* Disable interrupts */ - devpriv->stc_writew(dev, 0, Interrupt_Control_Register); + ni_stc_writew(dev, 0, Interrupt_Control_Register); /* Initialise 6143 AI specific bits */ - ni_writeb(0x00, Magic_6143); /* Set G0,G1 DMA mode to E series version */ - ni_writeb(0x80, PipelineDelay_6143); /* Set EOCMode, ADCMode and pipelinedelay */ - ni_writeb(0x00, EOC_Set_6143); /* Set EOC Delay */ + + /* Set G0,G1 DMA mode to E series version */ + ni_writeb(dev, 0x00, Magic_6143); + /* Set EOCMode, ADCMode and pipelinedelay */ + ni_writeb(dev, 0x80, PipelineDelay_6143); + /* Set EOC Delay */ + ni_writeb(dev, 0x00, EOC_Set_6143); /* Set the FIFO half full level */ - ni_writel(board->ai_fifo_depth / 2, AIFIFO_Flag_6143); + ni_writel(dev, board->ai_fifo_depth / 2, AIFIFO_Flag_6143); /* Strobe Relay disable bit */ devpriv->ai_calib_source_enabled = 0; - ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff, + ni_writew(dev, devpriv->ai_calib_source | + Calibration_Channel_6143_RelayOff, Calibration_Channel_6143); - ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143); + ni_writew(dev, devpriv->ai_calib_source, Calibration_Channel_6143); } static void pcimio_detach(struct comedi_device *dev) @@ -1457,11 +1121,10 @@ static void pcimio_detach(struct comedi_device *dev) mite_free_ring(devpriv->cdo_mite_ring); mite_free_ring(devpriv->gpct_mite_ring[0]); mite_free_ring(devpriv->gpct_mite_ring[1]); - if (devpriv->mite) { - mite_unsetup(devpriv->mite); - mite_free(devpriv->mite); - } + mite_detach(devpriv->mite); } + if (dev->mmio) + iounmap(dev->mmio); comedi_pci_disable(dev); } @@ -1494,23 +1157,30 @@ static int pcimio_auto_attach(struct comedi_device *dev, if (!devpriv->mite) return -ENOMEM; - if (board->reg_type & ni_reg_m_series_mask) { - devpriv->stc_writew = &m_series_stc_writew; - devpriv->stc_readw = &m_series_stc_readw; - devpriv->stc_writel = &m_series_stc_writel; - devpriv->stc_readl = &m_series_stc_readl; - } else { - devpriv->stc_writew = &e_series_win_out; - devpriv->stc_readw = &e_series_win_in; - devpriv->stc_writel = &win_out2; - devpriv->stc_readl = &win_in2; - } - - ret = mite_setup(devpriv->mite); - if (ret < 0) { - pr_warn("error setting up mite\n"); + if (board->reg_type & ni_reg_m_series_mask) + devpriv->is_m_series = 1; + if (board->reg_type & ni_reg_6xxx_mask) + devpriv->is_6xxx = 1; + if (board->reg_type == ni_reg_611x) + devpriv->is_611x = 1; + if (board->reg_type == ni_reg_6143) + devpriv->is_6143 = 1; + if (board->reg_type == ni_reg_622x) + devpriv->is_622x = 1; + if (board->reg_type == ni_reg_625x) + devpriv->is_625x = 1; + if (board->reg_type == ni_reg_628x) + devpriv->is_628x = 1; + if (board->reg_type & ni_reg_67xx_mask) + devpriv->is_67xx = 1; + if (board->reg_type == ni_reg_6711) + devpriv->is_6711 = 1; + if (board->reg_type == ni_reg_6713) + devpriv->is_6713 = 1; + + ret = mite_setup(dev, devpriv->mite); + if (ret < 0) return ret; - } devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite); if (devpriv->ai_mite_ring == NULL) @@ -1528,20 +1198,20 @@ static int pcimio_auto_attach(struct comedi_device *dev, if (devpriv->gpct_mite_ring[1] == NULL) return -ENOMEM; - if (board->reg_type & ni_reg_m_series_mask) + if (devpriv->is_m_series) m_series_init_eeprom_buffer(dev); - if (board->reg_type == ni_reg_6143) + if (devpriv->is_6143) init_6143(dev); - irq = mite_irq(devpriv->mite); + irq = pcidev->irq; if (irq) { - ret = request_irq(irq, ni_E_interrupt, NI_E_IRQ_FLAGS, + ret = request_irq(irq, ni_E_interrupt, IRQF_SHARED, dev->board_name, dev); if (ret == 0) dev->irq = irq; } - ret = ni_E_init(dev); + ret = ni_E_init(dev, 0, 1); if (ret < 0) return ret; @@ -1554,73 +1224,6 @@ static int pcimio_auto_attach(struct comedi_device *dev, return 0; } -static int pcimio_ai_change(struct comedi_device *dev, - struct comedi_subdevice *s, unsigned long new_size) -{ - struct ni_private *devpriv = dev->private; - int ret; - - ret = mite_buf_change(devpriv->ai_mite_ring, s); - if (ret < 0) - return ret; - - return 0; -} - -static int pcimio_ao_change(struct comedi_device *dev, - struct comedi_subdevice *s, unsigned long new_size) -{ - struct ni_private *devpriv = dev->private; - int ret; - - ret = mite_buf_change(devpriv->ao_mite_ring, s); - if (ret < 0) - return ret; - - return 0; -} - -static int pcimio_gpct0_change(struct comedi_device *dev, - struct comedi_subdevice *s, - unsigned long new_size) -{ - struct ni_private *devpriv = dev->private; - int ret; - - ret = mite_buf_change(devpriv->gpct_mite_ring[0], s); - if (ret < 0) - return ret; - - return 0; -} - -static int pcimio_gpct1_change(struct comedi_device *dev, - struct comedi_subdevice *s, - unsigned long new_size) -{ - struct ni_private *devpriv = dev->private; - int ret; - - ret = mite_buf_change(devpriv->gpct_mite_ring[1], s); - if (ret < 0) - return ret; - - return 0; -} - -static int pcimio_dio_change(struct comedi_device *dev, - struct comedi_subdevice *s, unsigned long new_size) -{ - struct ni_private *devpriv = dev->private; - int ret; - - ret = mite_buf_change(devpriv->cdo_mite_ring, s); - if (ret < 0) - return ret; - - return 0; -} - static struct comedi_driver ni_pcimio_driver = { .driver_name = "ni_pcimio", .module = THIS_MODULE, |