diff options
Diffstat (limited to '')
| -rw-r--r-- | drivers/staging/comedi/drivers/ni_tio_internal.h | 387 |
1 files changed, 114 insertions, 273 deletions
diff --git a/drivers/staging/comedi/drivers/ni_tio_internal.h b/drivers/staging/comedi/drivers/ni_tio_internal.h index 15b81b8fc5c4..2bceae493e23 100644 --- a/drivers/staging/comedi/drivers/ni_tio_internal.h +++ b/drivers/staging/comedi/drivers/ni_tio_internal.h @@ -22,296 +22,139 @@ #include "ni_tio.h" #define NITIO_AUTO_INC_REG(x) (NITIO_G0_AUTO_INC + (x)) +#define GI_AUTO_INC_MASK 0xff #define NITIO_CMD_REG(x) (NITIO_G0_CMD + (x)) +#define GI_ARM (1 << 0) +#define GI_SAVE_TRACE (1 << 1) +#define GI_LOAD (1 << 2) +#define GI_DISARM (1 << 4) +#define GI_CNT_DIR(x) (((x) & 0x3) << 5) +#define GI_CNT_DIR_MASK (3 << 5) +#define GI_WRITE_SWITCH (1 << 7) +#define GI_SYNC_GATE (1 << 8) +#define GI_LITTLE_BIG_ENDIAN (1 << 9) +#define GI_BANK_SWITCH_START (1 << 10) +#define GI_BANK_SWITCH_MODE (1 << 11) +#define GI_BANK_SWITCH_ENABLE (1 << 12) +#define GI_ARM_COPY (1 << 13) +#define GI_SAVE_TRACE_COPY (1 << 14) +#define GI_DISARM_COPY (1 << 15) #define NITIO_HW_SAVE_REG(x) (NITIO_G0_HW_SAVE + (x)) #define NITIO_SW_SAVE_REG(x) (NITIO_G0_SW_SAVE + (x)) #define NITIO_MODE_REG(x) (NITIO_G0_MODE + (x)) +#define GI_GATING_DISABLED (0 << 0) +#define GI_LEVEL_GATING (1 << 0) +#define GI_RISING_EDGE_GATING (2 << 0) +#define GI_FALLING_EDGE_GATING (3 << 0) +#define GI_GATING_MODE_MASK (3 << 0) +#define GI_GATE_ON_BOTH_EDGES (1 << 2) +#define GI_EDGE_GATE_STARTS_STOPS (0 << 3) +#define GI_EDGE_GATE_STOPS_STARTS (1 << 3) +#define GI_EDGE_GATE_STARTS (2 << 3) +#define GI_EDGE_GATE_NO_STARTS_OR_STOPS (3 << 3) +#define GI_EDGE_GATE_MODE_MASK (3 << 3) +#define GI_STOP_ON_GATE (0 << 5) +#define GI_STOP_ON_GATE_OR_TC (1 << 5) +#define GI_STOP_ON_GATE_OR_SECOND_TC (2 << 5) +#define GI_STOP_MODE_MASK (3 << 5) +#define GI_LOAD_SRC_SEL (1 << 7) +#define GI_OUTPUT_TC_PULSE (1 << 8) +#define GI_OUTPUT_TC_TOGGLE (2 << 8) +#define GI_OUTPUT_TC_OR_GATE_TOGGLE (3 << 8) +#define GI_OUTPUT_MODE_MASK (3 << 8) +#define GI_NO_HARDWARE_DISARM (0 << 10) +#define GI_DISARM_AT_TC (1 << 10) +#define GI_DISARM_AT_GATE (2 << 10) +#define GI_DISARM_AT_TC_OR_GATE (3 << 10) +#define GI_COUNTING_ONCE_MASK (3 << 10) +#define GI_LOADING_ON_TC (1 << 12) +#define GI_GATE_POL_INVERT (1 << 13) +#define GI_LOADING_ON_GATE (1 << 14) +#define GI_RELOAD_SRC_SWITCHING (1 << 15) #define NITIO_LOADA_REG(x) (NITIO_G0_LOADA + (x)) #define NITIO_LOADB_REG(x) (NITIO_G0_LOADB + (x)) #define NITIO_INPUT_SEL_REG(x) (NITIO_G0_INPUT_SEL + (x)) +#define GI_READ_ACKS_IRQ (1 << 0) +#define GI_WRITE_ACKS_IRQ (1 << 1) +#define GI_BITS_TO_SRC(x) (((x) >> 2) & 0x1f) +#define GI_SRC_SEL(x) (((x) & 0x1f) << 2) +#define GI_SRC_SEL_MASK (0x1f << 2) +#define GI_BITS_TO_GATE(x) (((x) >> 7) & 0x1f) +#define GI_GATE_SEL(x) (((x) & 0x1f) << 7) +#define GI_GATE_SEL_MASK (0x1f << 7) +#define GI_GATE_SEL_LOAD_SRC (1 << 12) +#define GI_OR_GATE (1 << 13) +#define GI_OUTPUT_POL_INVERT (1 << 14) +#define GI_SRC_POL_INVERT (1 << 15) #define NITIO_CNT_MODE_REG(x) (NITIO_G0_CNT_MODE + (x)) +#define GI_CNT_MODE(x) (((x) & 0x7) << 0) +#define GI_CNT_MODE_NORMAL GI_CNT_MODE(0) +#define GI_CNT_MODE_QUADX1 GI_CNT_MODE(1) +#define GI_CNT_MODE_QUADX2 GI_CNT_MODE(2) +#define GI_CNT_MODE_QUADX4 GI_CNT_MODE(3) +#define GI_CNT_MODE_TWO_PULSE GI_CNT_MODE(4) +#define GI_CNT_MODE_SYNC_SRC GI_CNT_MODE(6) +#define GI_CNT_MODE_MASK (7 << 0) +#define GI_INDEX_MODE (1 << 4) +#define GI_INDEX_PHASE(x) (((x) & 0x3) << 5) +#define GI_INDEX_PHASE_MASK (3 << 5) +#define GI_HW_ARM_ENA (1 << 7) +#define GI_HW_ARM_SEL(x) ((x) << 8) +#define GI_660X_HW_ARM_SEL_MASK (0x7 << 8) +#define GI_M_HW_ARM_SEL_MASK (0x1f << 8) +#define GI_660X_PRESCALE_X8 (1 << 12) +#define GI_M_PRESCALE_X8 (1 << 13) +#define GI_660X_ALT_SYNC (1 << 13) +#define GI_M_ALT_SYNC (1 << 14) +#define GI_660X_PRESCALE_X2 (1 << 14) +#define GI_M_PRESCALE_X2 (1 << 15) #define NITIO_GATE2_REG(x) (NITIO_G0_GATE2 + (x)) +#define GI_GATE2_MODE (1 << 0) +#define GI_BITS_TO_GATE2(x) (((x) >> 7) & 0x1f) +#define GI_GATE2_SEL(x) (((x) & 0x1f) << 7) +#define GI_GATE2_SEL_MASK (0x1f << 7) +#define GI_GATE2_POL_INVERT (1 << 13) +#define GI_GATE2_SUBSEL (1 << 14) +#define GI_SRC_SUBSEL (1 << 15) #define NITIO_SHARED_STATUS_REG(x) (NITIO_G01_STATUS + ((x) / 2)) +#define GI_SAVE(x) (((x) % 2) ? (1 << 1) : (1 << 0)) +#define GI_COUNTING(x) (((x) % 2) ? (1 << 3) : (1 << 2)) +#define GI_NEXT_LOAD_SRC(x) (((x) % 2) ? (1 << 5) : (1 << 4)) +#define GI_STALE_DATA(x) (((x) % 2) ? (1 << 7) : (1 << 6)) +#define GI_ARMED(x) (((x) % 2) ? (1 << 9) : (1 << 8)) +#define GI_NO_LOAD_BETWEEN_GATES(x) (((x) % 2) ? (1 << 11) : (1 << 10)) +#define GI_TC_ERROR(x) (((x) % 2) ? (1 << 13) : (1 << 12)) +#define GI_GATE_ERROR(x) (((x) % 2) ? (1 << 15) : (1 << 14)) #define NITIO_RESET_REG(x) (NITIO_G01_RESET + ((x) / 2)) +#define GI_RESET(x) (1 << (2 + ((x) % 2))) #define NITIO_STATUS1_REG(x) (NITIO_G01_STATUS1 + ((x) / 2)) #define NITIO_STATUS2_REG(x) (NITIO_G01_STATUS2 + ((x) / 2)) +#define GI_OUTPUT(x) (((x) % 2) ? (1 << 1) : (1 << 0)) +#define GI_HW_SAVE(x) (((x) % 2) ? (1 << 13) : (1 << 12)) +#define GI_PERMANENT_STALE(x) (((x) % 2) ? (1 << 15) : (1 << 14)) #define NITIO_DMA_CFG_REG(x) (NITIO_G0_DMA_CFG + (x)) +#define GI_DMA_ENABLE (1 << 0) +#define GI_DMA_WRITE (1 << 1) +#define GI_DMA_INT_ENA (1 << 2) +#define GI_DMA_RESET (1 << 3) +#define GI_DMA_BANKSW_ERROR (1 << 4) #define NITIO_DMA_STATUS_REG(x) (NITIO_G0_DMA_STATUS + (x)) +#define GI_DMA_READBANK (1 << 13) +#define GI_DRQ_ERROR (1 << 14) +#define GI_DRQ_STATUS (1 << 15) #define NITIO_ABZ_REG(x) (NITIO_G0_ABZ + (x)) #define NITIO_INT_ACK_REG(x) (NITIO_G0_INT_ACK + (x)) +#define GI_GATE_ERROR_CONFIRM(x) (((x) % 2) ? (1 << 1) : (1 << 5)) +#define GI_TC_ERROR_CONFIRM(x) (((x) % 2) ? (1 << 2) : (1 << 6)) +#define GI_TC_INTERRUPT_ACK (1 << 14) +#define GI_GATE_INTERRUPT_ACK (1 << 15) #define NITIO_STATUS_REG(x) (NITIO_G0_STATUS + (x)) +#define GI_GATE_INTERRUPT (1 << 2) +#define GI_TC (1 << 3) +#define GI_INTERRUPT (1 << 15) #define NITIO_INT_ENA_REG(x) (NITIO_G0_INT_ENA + (x)) - -enum Gi_Auto_Increment_Reg_Bits { - Gi_Auto_Increment_Mask = 0xff -}; - -#define Gi_Up_Down_Shift 5 -enum Gi_Command_Reg_Bits { - Gi_Arm_Bit = 0x1, - Gi_Save_Trace_Bit = 0x2, - Gi_Load_Bit = 0x4, - Gi_Disarm_Bit = 0x10, - Gi_Up_Down_Mask = 0x3 << Gi_Up_Down_Shift, - Gi_Always_Down_Bits = 0x0 << Gi_Up_Down_Shift, - Gi_Always_Up_Bits = 0x1 << Gi_Up_Down_Shift, - Gi_Up_Down_Hardware_IO_Bits = 0x2 << Gi_Up_Down_Shift, - Gi_Up_Down_Hardware_Gate_Bits = 0x3 << Gi_Up_Down_Shift, - Gi_Write_Switch_Bit = 0x80, - Gi_Synchronize_Gate_Bit = 0x100, - Gi_Little_Big_Endian_Bit = 0x200, - Gi_Bank_Switch_Start_Bit = 0x400, - Gi_Bank_Switch_Mode_Bit = 0x800, - Gi_Bank_Switch_Enable_Bit = 0x1000, - Gi_Arm_Copy_Bit = 0x2000, - Gi_Save_Trace_Copy_Bit = 0x4000, - Gi_Disarm_Copy_Bit = 0x8000 -}; - -#define Gi_Index_Phase_Bitshift 5 -#define Gi_HW_Arm_Select_Shift 8 -enum Gi_Counting_Mode_Reg_Bits { - Gi_Counting_Mode_Mask = 0x7, - Gi_Counting_Mode_Normal_Bits = 0x0, - Gi_Counting_Mode_QuadratureX1_Bits = 0x1, - Gi_Counting_Mode_QuadratureX2_Bits = 0x2, - Gi_Counting_Mode_QuadratureX4_Bits = 0x3, - Gi_Counting_Mode_Two_Pulse_Bits = 0x4, - Gi_Counting_Mode_Sync_Source_Bits = 0x6, - Gi_Index_Mode_Bit = 0x10, - Gi_Index_Phase_Mask = 0x3 << Gi_Index_Phase_Bitshift, - Gi_Index_Phase_LowA_LowB = 0x0 << Gi_Index_Phase_Bitshift, - Gi_Index_Phase_LowA_HighB = 0x1 << Gi_Index_Phase_Bitshift, - Gi_Index_Phase_HighA_LowB = 0x2 << Gi_Index_Phase_Bitshift, - Gi_Index_Phase_HighA_HighB = 0x3 << Gi_Index_Phase_Bitshift, - /* from m-series example code, not documented in 660x register level - * manual */ - Gi_HW_Arm_Enable_Bit = 0x80, - /* from m-series example code, not documented in 660x register level - * manual */ - Gi_660x_HW_Arm_Select_Mask = 0x7 << Gi_HW_Arm_Select_Shift, - Gi_660x_Prescale_X8_Bit = 0x1000, - Gi_M_Series_Prescale_X8_Bit = 0x2000, - Gi_M_Series_HW_Arm_Select_Mask = 0x1f << Gi_HW_Arm_Select_Shift, - /* must be set for clocks over 40MHz, which includes synchronous - * counting and quadrature modes */ - Gi_660x_Alternate_Sync_Bit = 0x2000, - Gi_M_Series_Alternate_Sync_Bit = 0x4000, - /* from m-series example code, not documented in 660x register level - * manual */ - Gi_660x_Prescale_X2_Bit = 0x4000, - Gi_M_Series_Prescale_X2_Bit = 0x8000, -}; - -#define Gi_Source_Select_Shift 2 -#define Gi_Gate_Select_Shift 7 -enum Gi_Input_Select_Bits { - Gi_Read_Acknowledges_Irq = 0x1, /* not present on 660x */ - Gi_Write_Acknowledges_Irq = 0x2, /* not present on 660x */ - Gi_Source_Select_Mask = 0x7c, - Gi_Gate_Select_Mask = 0x1f << Gi_Gate_Select_Shift, - Gi_Gate_Select_Load_Source_Bit = 0x1000, - Gi_Or_Gate_Bit = 0x2000, - Gi_Output_Polarity_Bit = 0x4000, /* set to invert */ - Gi_Source_Polarity_Bit = 0x8000 /* set to invert */ -}; - -enum Gi_Mode_Bits { - Gi_Gating_Mode_Mask = 0x3, - Gi_Gating_Disabled_Bits = 0x0, - Gi_Level_Gating_Bits = 0x1, - Gi_Rising_Edge_Gating_Bits = 0x2, - Gi_Falling_Edge_Gating_Bits = 0x3, - Gi_Gate_On_Both_Edges_Bit = 0x4, /* used in conjunction with - * rising edge gating mode */ - Gi_Trigger_Mode_for_Edge_Gate_Mask = 0x18, - Gi_Edge_Gate_Starts_Stops_Bits = 0x0, - Gi_Edge_Gate_Stops_Starts_Bits = 0x8, - Gi_Edge_Gate_Starts_Bits = 0x10, - Gi_Edge_Gate_No_Starts_or_Stops_Bits = 0x18, - Gi_Stop_Mode_Mask = 0x60, - Gi_Stop_on_Gate_Bits = 0x00, - Gi_Stop_on_Gate_or_TC_Bits = 0x20, - Gi_Stop_on_Gate_or_Second_TC_Bits = 0x40, - Gi_Load_Source_Select_Bit = 0x80, - Gi_Output_Mode_Mask = 0x300, - Gi_Output_TC_Pulse_Bits = 0x100, - Gi_Output_TC_Toggle_Bits = 0x200, - Gi_Output_TC_or_Gate_Toggle_Bits = 0x300, - Gi_Counting_Once_Mask = 0xc00, - Gi_No_Hardware_Disarm_Bits = 0x000, - Gi_Disarm_at_TC_Bits = 0x400, - Gi_Disarm_at_Gate_Bits = 0x800, - Gi_Disarm_at_TC_or_Gate_Bits = 0xc00, - Gi_Loading_On_TC_Bit = 0x1000, - Gi_Gate_Polarity_Bit = 0x2000, - Gi_Loading_On_Gate_Bit = 0x4000, - Gi_Reload_Source_Switching_Bit = 0x8000 -}; - -#define Gi_Second_Gate_Select_Shift 7 -/*FIXME: m-series has a second gate subselect bit */ -/*FIXME: m-series second gate sources are undocumented (by NI)*/ -enum Gi_Second_Gate_Bits { - Gi_Second_Gate_Mode_Bit = 0x1, - Gi_Second_Gate_Select_Mask = 0x1f << Gi_Second_Gate_Select_Shift, - Gi_Second_Gate_Polarity_Bit = 0x2000, - Gi_Second_Gate_Subselect_Bit = 0x4000, /* m-series only */ - Gi_Source_Subselect_Bit = 0x8000 /* m-series only */ -}; -static inline unsigned Gi_Second_Gate_Select_Bits(unsigned second_gate_select) -{ - return (second_gate_select << Gi_Second_Gate_Select_Shift) & - Gi_Second_Gate_Select_Mask; -} - -enum Gxx_Status_Bits { - G0_Save_Bit = 0x1, - G1_Save_Bit = 0x2, - G0_Counting_Bit = 0x4, - G1_Counting_Bit = 0x8, - G0_Next_Load_Source_Bit = 0x10, - G1_Next_Load_Source_Bit = 0x20, - G0_Stale_Data_Bit = 0x40, - G1_Stale_Data_Bit = 0x80, - G0_Armed_Bit = 0x100, - G1_Armed_Bit = 0x200, - G0_No_Load_Between_Gates_Bit = 0x400, - G1_No_Load_Between_Gates_Bit = 0x800, - G0_TC_Error_Bit = 0x1000, - G1_TC_Error_Bit = 0x2000, - G0_Gate_Error_Bit = 0x4000, - G1_Gate_Error_Bit = 0x8000 -}; -static inline enum Gxx_Status_Bits Gi_Counting_Bit(unsigned counter_index) -{ - if (counter_index % 2) - return G1_Counting_Bit; - return G0_Counting_Bit; -} - -static inline enum Gxx_Status_Bits Gi_Armed_Bit(unsigned counter_index) -{ - if (counter_index % 2) - return G1_Armed_Bit; - return G0_Armed_Bit; -} - -static inline enum Gxx_Status_Bits Gi_Next_Load_Source_Bit(unsigned - counter_index) -{ - if (counter_index % 2) - return G1_Next_Load_Source_Bit; - return G0_Next_Load_Source_Bit; -} - -static inline enum Gxx_Status_Bits Gi_Stale_Data_Bit(unsigned counter_index) -{ - if (counter_index % 2) - return G1_Stale_Data_Bit; - return G0_Stale_Data_Bit; -} - -static inline enum Gxx_Status_Bits Gi_TC_Error_Bit(unsigned counter_index) -{ - if (counter_index % 2) - return G1_TC_Error_Bit; - return G0_TC_Error_Bit; -} - -static inline enum Gxx_Status_Bits Gi_Gate_Error_Bit(unsigned counter_index) -{ - if (counter_index % 2) - return G1_Gate_Error_Bit; - return G0_Gate_Error_Bit; -} - -/* joint reset register bits */ -static inline unsigned Gi_Reset_Bit(unsigned counter_index) -{ - return 0x1 << (2 + (counter_index % 2)); -} - -enum Gxx_Joint_Status2_Bits { - G0_Output_Bit = 0x1, - G1_Output_Bit = 0x2, - G0_HW_Save_Bit = 0x1000, - G1_HW_Save_Bit = 0x2000, - G0_Permanent_Stale_Bit = 0x4000, - G1_Permanent_Stale_Bit = 0x8000 -}; -static inline enum Gxx_Joint_Status2_Bits Gi_Permanent_Stale_Bit(unsigned - counter_index) -{ - if (counter_index % 2) - return G1_Permanent_Stale_Bit; - return G0_Permanent_Stale_Bit; -} - -enum Gi_DMA_Config_Reg_Bits { - Gi_DMA_Enable_Bit = 0x1, - Gi_DMA_Write_Bit = 0x2, - Gi_DMA_Int_Bit = 0x4 -}; - -enum Gi_DMA_Status_Reg_Bits { - Gi_DMA_Readbank_Bit = 0x2000, - Gi_DRQ_Error_Bit = 0x4000, - Gi_DRQ_Status_Bit = 0x8000 -}; - -enum G02_Interrupt_Acknowledge_Bits { - G0_Gate_Error_Confirm_Bit = 0x20, - G0_TC_Error_Confirm_Bit = 0x40 -}; -enum G13_Interrupt_Acknowledge_Bits { - G1_Gate_Error_Confirm_Bit = 0x2, - G1_TC_Error_Confirm_Bit = 0x4 -}; -static inline unsigned Gi_Gate_Error_Confirm_Bit(unsigned counter_index) -{ - if (counter_index % 2) - return G1_Gate_Error_Confirm_Bit; - return G0_Gate_Error_Confirm_Bit; -} - -static inline unsigned Gi_TC_Error_Confirm_Bit(unsigned counter_index) -{ - if (counter_index % 2) - return G1_TC_Error_Confirm_Bit; - return G0_TC_Error_Confirm_Bit; -} - -/* bits that are the same in G0/G2 and G1/G3 interrupt acknowledge registers */ -enum Gxx_Interrupt_Acknowledge_Bits { - Gi_TC_Interrupt_Ack_Bit = 0x4000, - Gi_Gate_Interrupt_Ack_Bit = 0x8000 -}; - -enum Gi_Status_Bits { - Gi_Gate_Interrupt_Bit = 0x4, - Gi_TC_Bit = 0x8, - Gi_Interrupt_Bit = 0x8000 -}; - -enum G02_Interrupt_Enable_Bits { - G0_TC_Interrupt_Enable_Bit = 0x40, - G0_Gate_Interrupt_Enable_Bit = 0x100 -}; -enum G13_Interrupt_Enable_Bits { - G1_TC_Interrupt_Enable_Bit = 0x200, - G1_Gate_Interrupt_Enable_Bit = 0x400 -}; -static inline unsigned Gi_Gate_Interrupt_Enable_Bit(unsigned counter_index) -{ - unsigned bit; - - if (counter_index % 2) - bit = G1_Gate_Interrupt_Enable_Bit; - else - bit = G0_Gate_Interrupt_Enable_Bit; - return bit; -} +#define GI_TC_INTERRUPT_ENABLE(x) (((x) % 2) ? (1 << 9) : (1 << 6)) +#define GI_GATE_INTERRUPT_ENABLE(x) (((x) % 2) ? (1 << 10) : (1 << 8)) static inline void write_register(struct ni_gpct *counter, unsigned bits, enum ni_gpct_register reg) @@ -334,11 +177,9 @@ static inline int ni_tio_counting_mode_registers_present(const struct switch (counter_dev->variant) { case ni_gpct_variant_e_series: return 0; - break; case ni_gpct_variant_m_series: case ni_gpct_variant_660x: return 1; - break; default: BUG(); break; |