diff options
Diffstat (limited to 'drivers/staging/crystalhd')
| -rw-r--r-- | drivers/staging/crystalhd/bc_dts_glob_lnx.h | 19 | ||||
| -rw-r--r-- | drivers/staging/crystalhd/crystalhd_cmds.c | 28 | ||||
| -rw-r--r-- | drivers/staging/crystalhd/crystalhd_cmds.h | 19 | ||||
| -rw-r--r-- | drivers/staging/crystalhd/crystalhd_fw_if.h | 81 | ||||
| -rw-r--r-- | drivers/staging/crystalhd/crystalhd_hw.c | 231 | ||||
| -rw-r--r-- | drivers/staging/crystalhd/crystalhd_hw.h | 121 | ||||
| -rw-r--r-- | drivers/staging/crystalhd/crystalhd_lnx.c | 33 | ||||
| -rw-r--r-- | drivers/staging/crystalhd/crystalhd_lnx.h | 4 | ||||
| -rw-r--r-- | drivers/staging/crystalhd/crystalhd_misc.c | 39 | ||||
| -rw-r--r-- | drivers/staging/crystalhd/crystalhd_misc.h | 37 |
10 files changed, 371 insertions, 241 deletions
diff --git a/drivers/staging/crystalhd/bc_dts_glob_lnx.h b/drivers/staging/crystalhd/bc_dts_glob_lnx.h index fd1a6e680c8a..981708f3ee39 100644 --- a/drivers/staging/crystalhd/bc_dts_glob_lnx.h +++ b/drivers/staging/crystalhd/bc_dts_glob_lnx.h @@ -58,11 +58,11 @@ * between the driver and the application. */ enum BC_DTS_GLOBALS { - BC_MAX_FW_CMD_BUFF_SZ = 0x40, /* FW passthrough cmd/rsp buffer size */ + BC_MAX_FW_CMD_BUFF_SZ = 0x40, /* FW passthrough cmd/rsp buffer size */ PCI_CFG_SIZE = 256, /* PCI config size buffer */ BC_IOCTL_DATA_POOL_SIZE = 8, /* BC_IOCTL_DATA Pool size */ - BC_LINK_MAX_OPENS = 3, /* Maximum simultaneous opens*/ - BC_LINK_MAX_SGLS = 1024, /* Maximum SG elements 4M/4K */ + BC_LINK_MAX_OPENS = 3, /* Maximum simultaneous opens*/ + BC_LINK_MAX_SGLS = 1024, /* Maximum SG elements 4M/4K */ BC_TX_LIST_CNT = 2, /* Max Tx DMA Rings */ BC_RX_LIST_CNT = 8, /* Max Rx DMA Rings*/ BC_PROC_OUTPUT_TIMEOUT = 3000, /* Milliseconds */ @@ -240,11 +240,14 @@ enum BC_DRV_CMD { DRV_CMD_ADD_RXBUFFS, /* Add Rx side buffers to driver pool */ DRV_CMD_FETCH_RXBUFF, /* Get Rx DMAed buffer */ DRV_CMD_START_RX_CAP, /* Start Rx Buffer Capture */ - DRV_CMD_FLUSH_RX_CAP, /* Stop the capture for now...we will enhance this later*/ + DRV_CMD_FLUSH_RX_CAP, /* Stop the capture for now... + we will enhance this later*/ DRV_CMD_GET_DRV_STAT, /* Get Driver Internal Statistics */ DRV_CMD_RST_DRV_STAT, /* Reset Driver Internal Statistics */ - DRV_CMD_NOTIFY_MODE, /* Notify the Mode to driver in which the application is Operating*/ - DRV_CMD_CHANGE_CLOCK, /* Change the core clock to either save power or improve performance */ + DRV_CMD_NOTIFY_MODE, /* Notify the Mode to driver + in which the application is Operating*/ + DRV_CMD_CHANGE_CLOCK, /* Change the core clock to either save power + or improve performance */ /* MUST be the last one.. */ DRV_CMD_END, /* End of the List.. */ @@ -283,8 +286,8 @@ struct crystalhd_ioctl_data { struct BC_IOCTL_DATA udata; /* IOCTL from App..*/ uint32_t u_id; /* Driver specific user ID */ uint32_t cmd; /* Cmd ID for driver's use. */ - void *add_cdata; /* Additional command specific data..*/ - uint32_t add_cdata_sz; /* Additional command specific data size */ + void *add_cdata; /* Additional command specific data..*/ + uint32_t add_cdata_sz; /* Additional command specific data size */ struct crystalhd_ioctl_data *next; /* List/Fifo management */ }; diff --git a/drivers/staging/crystalhd/crystalhd_cmds.c b/drivers/staging/crystalhd/crystalhd_cmds.c index ed99daa6ef46..3ab502b8c3be 100644 --- a/drivers/staging/crystalhd/crystalhd_cmds.c +++ b/drivers/staging/crystalhd/crystalhd_cmds.c @@ -472,8 +472,8 @@ static enum BC_STATUS bc_cproc_hw_txdma(struct crystalhd_cmd *ctx, } /* Helper function to check on user buffers */ -static enum BC_STATUS bc_cproc_check_inbuffs(bool pin, void *ubuff, uint32_t ub_sz, - uint32_t uv_off, bool en_422) +static enum BC_STATUS bc_cproc_check_inbuffs(bool pin, void *ubuff, + uint32_t ub_sz, uint32_t uv_off, bool en_422) { if (!ubuff || !ub_sz) { BCMLOG_ERR("%s->Invalid Arg %p %x\n", @@ -483,8 +483,9 @@ static enum BC_STATUS bc_cproc_check_inbuffs(bool pin, void *ubuff, uint32_t ub_ /* Check for alignment */ if (((uintptr_t)ubuff) & 0x03) { - BCMLOG_ERR("%s-->Un-aligned address not implemented yet.. %p\n", - ((pin) ? "TX" : "RX"), ubuff); + BCMLOG_ERR( + "%s-->Un-aligned address not implemented yet.. %p\n", + ((pin) ? "TX" : "RX"), ubuff); return BC_STS_NOT_IMPL; } if (pin) @@ -572,7 +573,8 @@ static enum BC_STATUS bc_cproc_add_cap_buff(struct crystalhd_cmd *ctx, if (!dio_hnd) return BC_STS_ERROR; - sts = crystalhd_hw_add_cap_buffer(&ctx->hw_ctx, dio_hnd, (ctx->state == BC_LINK_READY)); + sts = crystalhd_hw_add_cap_buffer(&ctx->hw_ctx, dio_hnd, + (ctx->state == BC_LINK_READY)); if ((sts != BC_STS_SUCCESS) && (sts != BC_STS_BUSY)) { crystalhd_unmap_dio(ctx->adp, dio_hnd); return sts; @@ -618,7 +620,8 @@ static enum BC_STATUS bc_cproc_fetch_frame(struct crystalhd_cmd *ctx, sts = crystalhd_hw_get_cap_buffer(&ctx->hw_ctx, &frame->PibInfo, &dio); if (sts != BC_STS_SUCCESS) - return (ctx->state & BC_LINK_SUSPEND) ? BC_STS_IO_USER_ABORT : sts; + return (ctx->state & BC_LINK_SUSPEND) ? + BC_STS_IO_USER_ABORT : sts; frame->Flags = dio->uinfo.comp_flags; @@ -673,7 +676,8 @@ static enum BC_STATUS bc_cproc_flush_cap_buffs(struct crystalhd_cmd *ctx, frame = &idata->udata.u.DecOutData; for (count = 0; count < BC_RX_LIST_CNT; count++) { - sts = crystalhd_hw_get_cap_buffer(&ctx->hw_ctx, &frame->PibInfo, &dio); + sts = crystalhd_hw_get_cap_buffer(&ctx->hw_ctx, + &frame->PibInfo, &dio); if (sts != BC_STS_SUCCESS) break; @@ -916,7 +920,8 @@ enum BC_STATUS crystalhd_user_open(struct crystalhd_cmd *ctx, * Closer application handle and release app specific * resources. */ -enum BC_STATUS crystalhd_user_close(struct crystalhd_cmd *ctx, struct crystalhd_user *uc) +enum BC_STATUS crystalhd_user_close(struct crystalhd_cmd *ctx, + struct crystalhd_user *uc) { uint32_t mode = uc->mode; @@ -1008,8 +1013,8 @@ enum BC_STATUS crystalhd_delete_cmd_context(struct crystalhd_cmd *ctx) * mode of operation and returns the function pointer * from the cproc table. */ -crystalhd_cmd_proc crystalhd_get_cmd_proc(struct crystalhd_cmd *ctx, uint32_t cmd, - struct crystalhd_user *uc) +crystalhd_cmd_proc crystalhd_get_cmd_proc(struct crystalhd_cmd *ctx, + uint32_t cmd, struct crystalhd_user *uc) { crystalhd_cmd_proc cproc = NULL; unsigned int i, tbl_sz; @@ -1024,7 +1029,8 @@ crystalhd_cmd_proc crystalhd_get_cmd_proc(struct crystalhd_cmd *ctx, uint32_t cm return NULL; } - tbl_sz = sizeof(g_crystalhd_cproc_tbl) / sizeof(struct crystalhd_cmd_tbl); + tbl_sz = sizeof(g_crystalhd_cproc_tbl) / + sizeof(struct crystalhd_cmd_tbl); for (i = 0; i < tbl_sz; i++) { if (g_crystalhd_cproc_tbl[i].cmd_id == cmd) { if ((uc->mode == DTS_MONITOR_MODE) && diff --git a/drivers/staging/crystalhd/crystalhd_cmds.h b/drivers/staging/crystalhd/crystalhd_cmds.h index 4066ba393a17..377cd9d68b08 100644 --- a/drivers/staging/crystalhd/crystalhd_cmds.h +++ b/drivers/staging/crystalhd/crystalhd_cmds.h @@ -66,7 +66,8 @@ struct crystalhd_cmd { struct crystalhd_hw hw_ctx; }; -typedef enum BC_STATUS(*crystalhd_cmd_proc)(struct crystalhd_cmd *, struct crystalhd_ioctl_data *); +typedef enum BC_STATUS(*crystalhd_cmd_proc)(struct crystalhd_cmd *, + struct crystalhd_ioctl_data *); struct crystalhd_cmd_tbl { uint32_t cmd_id; @@ -74,13 +75,17 @@ struct crystalhd_cmd_tbl { uint32_t block_mon; }; -enum BC_STATUS crystalhd_suspend(struct crystalhd_cmd *ctx, struct crystalhd_ioctl_data *idata); +enum BC_STATUS crystalhd_suspend(struct crystalhd_cmd *ctx, + struct crystalhd_ioctl_data *idata); enum BC_STATUS crystalhd_resume(struct crystalhd_cmd *ctx); -crystalhd_cmd_proc crystalhd_get_cmd_proc(struct crystalhd_cmd *ctx, uint32_t cmd, - struct crystalhd_user *uc); -enum BC_STATUS crystalhd_user_open(struct crystalhd_cmd *ctx, struct crystalhd_user **user_ctx); -enum BC_STATUS crystalhd_user_close(struct crystalhd_cmd *ctx, struct crystalhd_user *uc); -enum BC_STATUS crystalhd_setup_cmd_context(struct crystalhd_cmd *ctx, struct crystalhd_adp *adp); +crystalhd_cmd_proc crystalhd_get_cmd_proc(struct crystalhd_cmd *ctx, + uint32_t cmd, struct crystalhd_user *uc); +enum BC_STATUS crystalhd_user_open(struct crystalhd_cmd *ctx, + struct crystalhd_user **user_ctx); +enum BC_STATUS crystalhd_user_close(struct crystalhd_cmd *ctx, + struct crystalhd_user *uc); +enum BC_STATUS crystalhd_setup_cmd_context(struct crystalhd_cmd *ctx, + struct crystalhd_adp *adp); enum BC_STATUS crystalhd_delete_cmd_context(struct crystalhd_cmd *ctx); bool crystalhd_cmd_interrupt(struct crystalhd_cmd *ctx); diff --git a/drivers/staging/crystalhd/crystalhd_fw_if.h b/drivers/staging/crystalhd/crystalhd_fw_if.h index 9e2831e68bba..4b363a5069d7 100644 --- a/drivers/staging/crystalhd/crystalhd_fw_if.h +++ b/drivers/staging/crystalhd/crystalhd_fw_if.h @@ -106,7 +106,8 @@ struct ppb_vc1 { struct fgt_sei { struct fgt_sei *next; - unsigned char model_values[3][MAX_FGT_VALUE_INTERVAL][MAX_FGT_MODEL_VALUE]; + unsigned char + model_values[3][MAX_FGT_VALUE_INTERVAL][MAX_FGT_MODEL_VALUE]; unsigned char upper_bound[3][MAX_FGT_VALUE_INTERVAL]; unsigned char lower_bound[3][MAX_FGT_VALUE_INTERVAL]; @@ -125,10 +126,12 @@ struct fgt_sei { unsigned char blending_mode_id; /* Blending mode. */ unsigned char log2_scale_factor; /* Log2 scale factor (2-7). */ - unsigned char comp_flag[3]; /* Components [0,2] parameters present flag. */ - unsigned char num_intervals_minus1[3]; /* Number of intensity level intervals. */ + unsigned char comp_flag[3]; /* Components [0,2] + parameters present flag. */ + unsigned char num_intervals_minus1[3]; /* Number of + intensity level intervals. */ unsigned char num_model_values[3]; /* Number of model values. */ - uint16_t repetition_period; /* Repetition period (0-16384) */ + uint16_t repetition_period; /* Repetition period (0-16384) */ }; @@ -266,40 +269,40 @@ enum c011_ts_cmd { /* Decoding commands */ eCMD_C011_DEC_CHAN_OPEN = eCMD_C011_CMD_BASE + 0x100, - eCMD_C011_DEC_CHAN_CLOSE = eCMD_C011_CMD_BASE + 0x101, - eCMD_C011_DEC_CHAN_ACTIVATE = eCMD_C011_CMD_BASE + 0x102, - eCMD_C011_DEC_CHAN_STATUS = eCMD_C011_CMD_BASE + 0x103, - eCMD_C011_DEC_CHAN_FLUSH = eCMD_C011_CMD_BASE + 0x104, + eCMD_C011_DEC_CHAN_CLOSE = eCMD_C011_CMD_BASE + 0x101, + eCMD_C011_DEC_CHAN_ACTIVATE = eCMD_C011_CMD_BASE + 0x102, + eCMD_C011_DEC_CHAN_STATUS = eCMD_C011_CMD_BASE + 0x103, + eCMD_C011_DEC_CHAN_FLUSH = eCMD_C011_CMD_BASE + 0x104, eCMD_C011_DEC_CHAN_TRICK_PLAY = eCMD_C011_CMD_BASE + 0x105, - eCMD_C011_DEC_CHAN_TS_PIDS = eCMD_C011_CMD_BASE + 0x106, + eCMD_C011_DEC_CHAN_TS_PIDS = eCMD_C011_CMD_BASE + 0x106, eCMD_C011_DEC_CHAN_PS_STREAM_ID = eCMD_C011_CMD_BASE + 0x107, eCMD_C011_DEC_CHAN_INPUT_PARAMS = eCMD_C011_CMD_BASE + 0x108, eCMD_C011_DEC_CHAN_VIDEO_OUTPUT = eCMD_C011_CMD_BASE + 0x109, - eCMD_C011_DEC_CHAN_OUTPUT_FORMAT = eCMD_C011_CMD_BASE + 0x10A, - eCMD_C011_DEC_CHAN_SCALING_FILTERS = eCMD_C011_CMD_BASE + 0x10B, - eCMD_C011_DEC_CHAN_OSD_MODE = eCMD_C011_CMD_BASE + 0x10D, + eCMD_C011_DEC_CHAN_OUTPUT_FORMAT = eCMD_C011_CMD_BASE + 0x10A, + eCMD_C011_DEC_CHAN_SCALING_FILTERS = eCMD_C011_CMD_BASE + 0x10B, + eCMD_C011_DEC_CHAN_OSD_MODE = eCMD_C011_CMD_BASE + 0x10D, eCMD_C011_DEC_CHAN_DROP = eCMD_C011_CMD_BASE + 0x10E, - eCMD_C011_DEC_CHAN_RELEASE = eCMD_C011_CMD_BASE + 0x10F, - eCMD_C011_DEC_CHAN_STREAM_SETTINGS = eCMD_C011_CMD_BASE + 0x110, + eCMD_C011_DEC_CHAN_RELEASE = eCMD_C011_CMD_BASE + 0x10F, + eCMD_C011_DEC_CHAN_STREAM_SETTINGS = eCMD_C011_CMD_BASE + 0x110, eCMD_C011_DEC_CHAN_PAUSE_OUTPUT = eCMD_C011_CMD_BASE + 0x111, - eCMD_C011_DEC_CHAN_CHANGE = eCMD_C011_CMD_BASE + 0x112, - eCMD_C011_DEC_CHAN_SET_STC = eCMD_C011_CMD_BASE + 0x113, - eCMD_C011_DEC_CHAN_SET_PTS = eCMD_C011_CMD_BASE + 0x114, - eCMD_C011_DEC_CHAN_CC_MODE = eCMD_C011_CMD_BASE + 0x115, - eCMD_C011_DEC_CREATE_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x116, - eCMD_C011_DEC_COPY_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x117, - eCMD_C011_DEC_DELETE_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x118, - eCMD_C011_DEC_CHAN_SET_DECYPTION = eCMD_C011_CMD_BASE + 0x119, + eCMD_C011_DEC_CHAN_CHANGE = eCMD_C011_CMD_BASE + 0x112, + eCMD_C011_DEC_CHAN_SET_STC = eCMD_C011_CMD_BASE + 0x113, + eCMD_C011_DEC_CHAN_SET_PTS = eCMD_C011_CMD_BASE + 0x114, + eCMD_C011_DEC_CHAN_CC_MODE = eCMD_C011_CMD_BASE + 0x115, + eCMD_C011_DEC_CREATE_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x116, + eCMD_C011_DEC_COPY_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x117, + eCMD_C011_DEC_DELETE_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x118, + eCMD_C011_DEC_CHAN_SET_DECYPTION = eCMD_C011_CMD_BASE + 0x119, eCMD_C011_DEC_CHAN_START_VIDEO = eCMD_C011_CMD_BASE + 0x11A, eCMD_C011_DEC_CHAN_STOP_VIDEO = eCMD_C011_CMD_BASE + 0x11B, eCMD_C011_DEC_CHAN_PIC_CAPTURE = eCMD_C011_CMD_BASE + 0x11C, - eCMD_C011_DEC_CHAN_PAUSE = eCMD_C011_CMD_BASE + 0x11D, + eCMD_C011_DEC_CHAN_PAUSE = eCMD_C011_CMD_BASE + 0x11D, eCMD_C011_DEC_CHAN_PAUSE_STATE = eCMD_C011_CMD_BASE + 0x11E, - eCMD_C011_DEC_CHAN_SET_SLOWM_RATE = eCMD_C011_CMD_BASE + 0x11F, - eCMD_C011_DEC_CHAN_GET_SLOWM_RATE = eCMD_C011_CMD_BASE + 0x120, + eCMD_C011_DEC_CHAN_SET_SLOWM_RATE = eCMD_C011_CMD_BASE + 0x11F, + eCMD_C011_DEC_CHAN_GET_SLOWM_RATE = eCMD_C011_CMD_BASE + 0x120, eCMD_C011_DEC_CHAN_SET_FF_RATE = eCMD_C011_CMD_BASE + 0x121, eCMD_C011_DEC_CHAN_GET_FF_RATE = eCMD_C011_CMD_BASE + 0x122, - eCMD_C011_DEC_CHAN_FRAME_ADVANCE = eCMD_C011_CMD_BASE + 0x123, + eCMD_C011_DEC_CHAN_FRAME_ADVANCE = eCMD_C011_CMD_BASE + 0x123, eCMD_C011_DEC_CHAN_SET_SKIP_PIC_MODE = eCMD_C011_CMD_BASE + 0x124, eCMD_C011_DEC_CHAN_GET_SKIP_PIC_MODE = eCMD_C011_CMD_BASE + 0x125, eCMD_C011_DEC_CHAN_FILL_PIC_BUF = eCMD_C011_CMD_BASE + 0x126, @@ -308,15 +311,16 @@ enum c011_ts_cmd { eCMD_C011_DEC_CHAN_SET_BRCM_TRICK_MODE = eCMD_C011_CMD_BASE + 0x129, eCMD_C011_DEC_CHAN_GET_BRCM_TRICK_MODE = eCMD_C011_CMD_BASE + 0x12A, eCMD_C011_DEC_CHAN_REVERSE_FIELD_STATUS = eCMD_C011_CMD_BASE + 0x12B, - eCMD_C011_DEC_CHAN_I_PICTURE_FOUND = eCMD_C011_CMD_BASE + 0x12C, - eCMD_C011_DEC_CHAN_SET_PARAMETER = eCMD_C011_CMD_BASE + 0x12D, + eCMD_C011_DEC_CHAN_I_PICTURE_FOUND = eCMD_C011_CMD_BASE + 0x12C, + eCMD_C011_DEC_CHAN_SET_PARAMETER = eCMD_C011_CMD_BASE + 0x12D, eCMD_C011_DEC_CHAN_SET_USER_DATA_MODE = eCMD_C011_CMD_BASE + 0x12E, - eCMD_C011_DEC_CHAN_SET_PAUSE_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x12F, - eCMD_C011_DEC_CHAN_SET_SLOW_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x130, + eCMD_C011_DEC_CHAN_SET_PAUSE_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x12F, + eCMD_C011_DEC_CHAN_SET_SLOW_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x130, eCMD_C011_DEC_CHAN_SET_FF_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x131, - eCMD_C011_DEC_CHAN_SET_DISPLAY_TIMING_MODE = eCMD_C011_CMD_BASE + 0x132, - eCMD_C011_DEC_CHAN_SET_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x133, - eCMD_C011_DEC_CHAN_GET_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x134, + eCMD_C011_DEC_CHAN_SET_DISPLAY_TIMING_MODE = eCMD_C011_CMD_BASE + + 0x132, + eCMD_C011_DEC_CHAN_SET_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x133, + eCMD_C011_DEC_CHAN_GET_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x134, eCMD_C011_DEC_CHAN_SET_REVERSE_FIELD = eCMD_C011_CMD_BASE + 0x135, eCMD_C011_DEC_CHAN_STREAM_OPEN = eCMD_C011_CMD_BASE + 0x136, eCMD_C011_DEC_CHAN_SET_PCR_PID = eCMD_C011_CMD_BASE + 0x137, @@ -328,19 +332,22 @@ enum c011_ts_cmd { eCMD_C011_DEC_CHAN_GET_DISPLAY_ORDER = eCMD_C011_CMD_BASE + 0x143, eCMD_C011_DEC_CHAN_SET_HOST_TRICK_MODE = eCMD_C011_CMD_BASE + 0x144, eCMD_C011_DEC_CHAN_SET_OPERATION_MODE = eCMD_C011_CMD_BASE + 0x145, - eCMD_C011_DEC_CHAN_DISPLAY_PAUSE_UNTO_PTS = eCMD_C011_CMD_BASE + 0x146, - eCMD_C011_DEC_CHAN_SET_PTS_STC_DIFF_THRESHOLD = eCMD_C011_CMD_BASE + 0x147, + eCMD_C011_DEC_CHAN_DISPLAY_PAUSE_UNTO_PTS = eCMD_C011_CMD_BASE + 0x146, + eCMD_C011_DEC_CHAN_SET_PTS_STC_DIFF_THRESHOLD = eCMD_C011_CMD_BASE + + 0x147, eCMD_C011_DEC_CHAN_SEND_COMPRESSED_BUF = eCMD_C011_CMD_BASE + 0x148, eCMD_C011_DEC_CHAN_SET_CLIPPING = eCMD_C011_CMD_BASE + 0x149, eCMD_C011_DEC_CHAN_SET_PARAMETERS_FOR_HARD_RESET_INTERRUPT_TO_HOST = eCMD_C011_CMD_BASE + 0x150, /* Decoder RevD commands */ - eCMD_C011_DEC_CHAN_SET_CSC = eCMD_C011_CMD_BASE + 0x180, /* color space conversion */ + eCMD_C011_DEC_CHAN_SET_CSC = eCMD_C011_CMD_BASE + 0x180, /* color + space conversion */ eCMD_C011_DEC_CHAN_SET_RANGE_REMAP = eCMD_C011_CMD_BASE + 0x181, eCMD_C011_DEC_CHAN_SET_FGT = eCMD_C011_CMD_BASE + 0x182, /* Note: 0x183 not implemented yet in Rev D main */ - eCMD_C011_DEC_CHAN_SET_LASTPICTURE_PADDING = eCMD_C011_CMD_BASE + 0x183, + eCMD_C011_DEC_CHAN_SET_LASTPICTURE_PADDING = eCMD_C011_CMD_BASE + + 0x183, /* Decoder 7412 commands (7412-only) */ eCMD_C011_DEC_CHAN_SET_CONTENT_KEY = eCMD_C011_CMD_BASE + 0x190, diff --git a/drivers/staging/crystalhd/crystalhd_hw.c b/drivers/staging/crystalhd/crystalhd_hw.c index e617d2fcbb1f..0c8cb329420f 100644 --- a/drivers/staging/crystalhd/crystalhd_hw.c +++ b/drivers/staging/crystalhd/crystalhd_hw.c @@ -94,15 +94,19 @@ static bool crystalhd_bring_out_of_rst(struct crystalhd_adp *adp) * Enable clocks while 7412 reset is asserted, delay * De-assert 7412 reset */ - rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_DECODER_CTRL); + rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, + MISC_PERST_DECODER_CTRL); rst_deco_cntrl.stop_bcm_7412_clk = 0; rst_deco_cntrl.bcm7412_rst = 1; - crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg); + crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, + rst_deco_cntrl.whole_reg); msleep_interruptible(10); - rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_DECODER_CTRL); + rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, + MISC_PERST_DECODER_CTRL); rst_deco_cntrl.bcm7412_rst = 0; - crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg); + crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, + rst_deco_cntrl.whole_reg); msleep_interruptible(50); /* Disable OTP_CONTENT_MISC to 0 to disable all secure modes */ @@ -132,9 +136,11 @@ static bool crystalhd_put_in_reset(struct crystalhd_adp *adp) * Assert 7412 reset, delay * Assert 7412 stop clock */ - rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_DECODER_CTRL); + rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, + MISC_PERST_DECODER_CTRL); rst_deco_cntrl.stop_bcm_7412_clk = 1; - crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg); + crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, + rst_deco_cntrl.whole_reg); msleep_interruptible(50); /* Bus Arbiter Timeout: GISB_ARBITER_TIMER @@ -213,7 +219,8 @@ static void crystalhd_clear_errors(struct crystalhd_adp *adp) { uint32_t reg; - /* FIXME: jarod: wouldn't we want to write a 0 to the reg? Or does the write clear the bits specified? */ + /* FIXME: jarod: wouldn't we want to write a 0 to the reg? + Or does the write clear the bits specified? */ reg = crystalhd_reg_rd(adp, MISC1_Y_RX_ERROR_STATUS); if (reg) crystalhd_reg_wr(adp, MISC1_Y_RX_ERROR_STATUS, reg); @@ -263,10 +270,12 @@ static bool crystalhd_load_firmware_config(struct crystalhd_adp *adp) crystalhd_reg_wr(adp, DCI_DRAM_BASE_ADDR, (BC_DRAM_FW_CFG_ADDR >> 19)); crystalhd_reg_wr(adp, AES_CMD, 0); - crystalhd_reg_wr(adp, AES_CONFIG_INFO, (BC_DRAM_FW_CFG_ADDR & 0x7FFFF)); + crystalhd_reg_wr(adp, AES_CONFIG_INFO, + (BC_DRAM_FW_CFG_ADDR & 0x7FFFF)); crystalhd_reg_wr(adp, AES_CMD, 0x1); - /* FIXME: jarod: I've seen this fail, and introducing extra delays helps... */ + /* FIXME: jarod: I've seen this fail, + and introducing extra delays helps... */ for (i = 0; i < 100; ++i) { reg = crystalhd_reg_rd(adp, AES_STATUS); if (reg & 0x1) @@ -349,7 +358,8 @@ static bool crystalhd_stop_device(struct crystalhd_adp *adp) return true; } -static struct crystalhd_rx_dma_pkt *crystalhd_hw_alloc_rx_pkt(struct crystalhd_hw *hw) +static struct crystalhd_rx_dma_pkt *crystalhd_hw_alloc_rx_pkt( + struct crystalhd_hw *hw) { unsigned long flags = 0; struct crystalhd_rx_dma_pkt *temp = NULL; @@ -484,8 +494,8 @@ hw_create_ioq_err: } -static bool crystalhd_code_in_full(struct crystalhd_adp *adp, uint32_t needed_sz, - bool b_188_byte_pkts, uint8_t flags) +static bool crystalhd_code_in_full(struct crystalhd_adp *adp, + uint32_t needed_sz, bool b_188_byte_pkts, uint8_t flags) { uint32_t base, end, writep, readp; uint32_t cpbSize, cpbFullness, fifoSize; @@ -525,7 +535,7 @@ static bool crystalhd_code_in_full(struct crystalhd_adp *adp, uint32_t needed_sz } static enum BC_STATUS crystalhd_hw_tx_req_complete(struct crystalhd_hw *hw, - uint32_t list_id, enum BC_STATUS cs) + uint32_t list_id, enum BC_STATUS cs) { struct tx_dma_pkt *tx_req; @@ -536,7 +546,8 @@ static enum BC_STATUS crystalhd_hw_tx_req_complete(struct crystalhd_hw *hw, hw->pwr_lock--; - tx_req = (struct tx_dma_pkt *)crystalhd_dioq_find_and_fetch(hw->tx_actq, list_id); + tx_req = (struct tx_dma_pkt *)crystalhd_dioq_find_and_fetch( + hw->tx_actq, list_id); if (!tx_req) { if (cs != BC_STS_IO_USER_ABORT) BCMLOG_ERR("Find and Fetch Did not find req\n"); @@ -559,7 +570,8 @@ static enum BC_STATUS crystalhd_hw_tx_req_complete(struct crystalhd_hw *hw, return crystalhd_dioq_add(hw->tx_freeq, tx_req, false, 0); } -static bool crystalhd_tx_list0_handler(struct crystalhd_hw *hw, uint32_t err_sts) +static bool crystalhd_tx_list0_handler(struct crystalhd_hw *hw, + uint32_t err_sts) { uint32_t err_mask, tmp; unsigned long flags = 0; @@ -591,7 +603,8 @@ static bool crystalhd_tx_list0_handler(struct crystalhd_hw *hw, uint32_t err_sts return true; } -static bool crystalhd_tx_list1_handler(struct crystalhd_hw *hw, uint32_t err_sts) +static bool crystalhd_tx_list1_handler(struct crystalhd_hw *hw, + uint32_t err_sts) { uint32_t err_mask, tmp; unsigned long flags = 0; @@ -663,14 +676,15 @@ static void crystalhd_hw_dump_desc(struct dma_descriptor *p_dma_desc, if (!p_dma_desc || !cnt) return; - /* FIXME: jarod: perhaps a modparam desc_debug to enable this, rather than - * setting ll (log level, I presume) to non-zero? */ + /* FIXME: jarod: perhaps a modparam desc_debug to enable this, + rather than setting ll (log level, I presume) to non-zero? */ if (!ll) return; for (ix = ul_desc_index; ix < (ul_desc_index + cnt); ix++) { - BCMLOG(ll, "%s[%d] Buff[%x:%x] Next:[%x:%x] XferSz:%x Intr:%x,Last:%x\n", - ((p_dma_desc[ul_desc_index].dma_dir) ? "TDesc" : "RDesc"), + BCMLOG(ll, + "%s[%d] Buff[%x:%x] Next:[%x:%x] XferSz:%x Intr:%x,Last:%x\n", + ((p_dma_desc[ul_desc_index].dma_dir) ? "TDesc" : "RDesc"), ul_desc_index, p_dma_desc[ul_desc_index].buff_addr_high, p_dma_desc[ul_desc_index].buff_addr_low, @@ -707,7 +721,8 @@ static enum BC_STATUS crystalhd_hw_fill_desc(struct crystalhd_dio_req *ioreq, /* Get SGLE length */ len = crystalhd_get_sgle_len(ioreq, sg_ix); if (len % 4) { - BCMLOG_ERR(" len in sg %d %d %d\n", len, sg_ix, sg_cnt); + BCMLOG_ERR(" len in sg %d %d %d\n", len, sg_ix, + sg_cnt); return BC_STS_NOT_IMPL; } /* Setup DMA desc with Phy addr & Length at current index. */ @@ -722,7 +737,8 @@ static enum BC_STATUS crystalhd_hw_fill_desc(struct crystalhd_dio_req *ioreq, desc[ix].dma_dir = ioreq->uinfo.dir_tx; /* Chain DMA descriptor. */ - addr_temp.full_addr = desc_phy_addr + sizeof(struct dma_descriptor); + addr_temp.full_addr = desc_phy_addr + + sizeof(struct dma_descriptor); desc[ix].next_desc_addr_low = addr_temp.low_part; desc[ix].next_desc_addr_high = addr_temp.high_part; @@ -731,8 +747,9 @@ static enum BC_STATUS crystalhd_hw_fill_desc(struct crystalhd_dio_req *ioreq, /* Debug.. */ if ((!len) || (len > crystalhd_get_sgle_len(ioreq, sg_ix))) { - BCMLOG_ERR("inv-len(%x) Ix(%d) count:%x xfr_sz:%x sg_cnt:%d\n", - len, ix, count, xfr_sz, sg_cnt); + BCMLOG_ERR( + "inv-len(%x) Ix(%d) count:%x xfr_sz:%x sg_cnt:%d\n", + len, ix, count, xfr_sz, sg_cnt); return BC_STS_ERROR; } /* Length expects Multiple of 4 */ @@ -774,7 +791,8 @@ static enum BC_STATUS crystalhd_hw_fill_desc(struct crystalhd_dio_req *ioreq, return BC_STS_SUCCESS; } -static enum BC_STATUS crystalhd_xlat_sgl_to_dma_desc(struct crystalhd_dio_req *ioreq, +static enum BC_STATUS crystalhd_xlat_sgl_to_dma_desc( + struct crystalhd_dio_req *ioreq, struct dma_desc_mem *pdesc_mem, uint32_t *uv_desc_index) { @@ -887,12 +905,14 @@ static enum BC_STATUS crystalhd_stop_tx_dma_engine(struct crystalhd_hw *hw) while ((l1 || l2) && cnt) { if (l1) { - l1 = crystalhd_reg_rd(hw->adp, MISC1_TX_FIRST_DESC_L_ADDR_LIST0); + l1 = crystalhd_reg_rd(hw->adp, + MISC1_TX_FIRST_DESC_L_ADDR_LIST0); l1 &= DMA_START_BIT; } if (l2) { - l2 = crystalhd_reg_rd(hw->adp, MISC1_TX_FIRST_DESC_L_ADDR_LIST1); + l2 = crystalhd_reg_rd(hw->adp, + MISC1_TX_FIRST_DESC_L_ADDR_LIST1); l2 &= DMA_START_BIT; } @@ -986,7 +1006,8 @@ static uint32_t crystalhd_get_addr_from_pib_Q(struct crystalhd_hw *hw) return addr_entry; } -static bool crystalhd_rel_addr_to_pib_Q(struct crystalhd_hw *hw, uint32_t addr_to_rel) +static bool crystalhd_rel_addr_to_pib_Q(struct crystalhd_hw *hw, + uint32_t addr_to_rel) { uint32_t Q_addr; uint32_t r_offset, w_offset, n_offset; @@ -1021,7 +1042,8 @@ static bool crystalhd_rel_addr_to_pib_Q(struct crystalhd_hw *hw, uint32_t addr_t return true; } -static void cpy_pib_to_app(struct c011_pib *src_pib, struct BC_PIC_INFO_BLOCK *dst_pib) +static void cpy_pib_to_app(struct c011_pib *src_pib, + struct BC_PIC_INFO_BLOCK *dst_pib) { if (!src_pib || !dst_pib) { BCMLOG_ERR("Invalid Arguments\n"); @@ -1063,11 +1085,13 @@ static void crystalhd_hw_proc_pib(struct crystalhd_hw *hw) (uint32_t *)&src_pib); if (src_pib.bFormatChange) { - rx_pkt = (struct crystalhd_rx_dma_pkt *)crystalhd_dioq_fetch(hw->rx_freeq); + rx_pkt = (struct crystalhd_rx_dma_pkt *) + crystalhd_dioq_fetch(hw->rx_freeq); if (!rx_pkt) return; rx_pkt->flags = 0; - rx_pkt->flags |= COMP_FLAG_PIB_VALID | COMP_FLAG_FMT_CHANGE; + rx_pkt->flags |= COMP_FLAG_PIB_VALID | + COMP_FLAG_FMT_CHANGE; AppPib = &rx_pkt->pib; cpy_pib_to_app(&src_pib, AppPib); @@ -1084,7 +1108,8 @@ static void crystalhd_hw_proc_pib(struct crystalhd_hw *hw) rx_pkt->pib.pulldown, rx_pkt->pib.ycom); - crystalhd_dioq_add(hw->rx_rdyq, (void *)rx_pkt, true, rx_pkt->pkt_tag); + crystalhd_dioq_add(hw->rx_rdyq, (void *)rx_pkt, true, + rx_pkt->pkt_tag); } @@ -1096,16 +1121,20 @@ static void crystalhd_start_rx_dma_engine(struct crystalhd_hw *hw) { uint32_t dma_cntrl; - dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); + dma_cntrl = crystalhd_reg_rd(hw->adp, + MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); if (!(dma_cntrl & DMA_START_BIT)) { dma_cntrl |= DMA_START_BIT; - crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); + crystalhd_reg_wr(hw->adp, + MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); } - dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); + dma_cntrl = crystalhd_reg_rd(hw->adp, + MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); if (!(dma_cntrl & DMA_START_BIT)) { dma_cntrl |= DMA_START_BIT; - crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); + crystalhd_reg_wr(hw->adp, + MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); } return; @@ -1116,44 +1145,52 @@ static void crystalhd_stop_rx_dma_engine(struct crystalhd_hw *hw) uint32_t dma_cntrl = 0, count = 30; uint32_t l0y = 1, l0uv = 1, l1y = 1, l1uv = 1; - dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); + dma_cntrl = crystalhd_reg_rd(hw->adp, + MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); if ((dma_cntrl & DMA_START_BIT)) { dma_cntrl &= ~DMA_START_BIT; - crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); + crystalhd_reg_wr(hw->adp, + MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); } - dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); + dma_cntrl = crystalhd_reg_rd(hw->adp, + MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); if ((dma_cntrl & DMA_START_BIT)) { dma_cntrl &= ~DMA_START_BIT; - crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); + crystalhd_reg_wr(hw->adp, + MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); } /* Poll for 3seconds (30 * 100ms) on both the lists..*/ while ((l0y || l0uv || l1y || l1uv) && count) { if (l0y) { - l0y = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0); + l0y = crystalhd_reg_rd(hw->adp, + MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0); l0y &= DMA_START_BIT; if (!l0y) hw->rx_list_sts[0] &= ~rx_waiting_y_intr; } if (l1y) { - l1y = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1); + l1y = crystalhd_reg_rd(hw->adp, + MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1); l1y &= DMA_START_BIT; if (!l1y) hw->rx_list_sts[1] &= ~rx_waiting_y_intr; } if (l0uv) { - l0uv = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0); + l0uv = crystalhd_reg_rd(hw->adp, + MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0); l0uv &= DMA_START_BIT; if (!l0uv) hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; } if (l1uv) { - l1uv = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1); + l1uv = crystalhd_reg_rd(hw->adp, + MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1); l1uv &= DMA_START_BIT; if (!l1uv) hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; @@ -1168,7 +1205,8 @@ static void crystalhd_stop_rx_dma_engine(struct crystalhd_hw *hw) count, hw->rx_list_sts[0], hw->rx_list_sts[1]); } -static enum BC_STATUS crystalhd_hw_prog_rxdma(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt *rx_pkt) +static enum BC_STATUS crystalhd_hw_prog_rxdma(struct crystalhd_hw *hw, + struct crystalhd_rx_dma_pkt *rx_pkt) { uint32_t y_low_addr_reg, y_high_addr_reg; uint32_t uv_low_addr_reg, uv_high_addr_reg; @@ -1186,7 +1224,8 @@ static enum BC_STATUS crystalhd_hw_prog_rxdma(struct crystalhd_hw *hw, struct cr } spin_lock_irqsave(&hw->rx_lock, flags); - /* FIXME: jarod: sts_free is an enum for 0, in crystalhd_hw.h... yuk... */ + /* FIXME: jarod: sts_free is an enum for 0, + in crystalhd_hw.h... yuk... */ if (sts_free != hw->rx_list_sts[hw->rx_list_post_index]) { spin_unlock_irqrestore(&hw->rx_lock, flags); return BC_STS_BUSY; @@ -1210,7 +1249,8 @@ static enum BC_STATUS crystalhd_hw_prog_rxdma(struct crystalhd_hw *hw, struct cr hw->rx_list_post_index = (hw->rx_list_post_index + 1) % DMA_ENGINE_CNT; spin_unlock_irqrestore(&hw->rx_lock, flags); - crystalhd_dioq_add(hw->rx_actq, (void *)rx_pkt, false, rx_pkt->pkt_tag); + crystalhd_dioq_add(hw->rx_actq, (void *)rx_pkt, false, + rx_pkt->pkt_tag); crystalhd_start_rx_dma_engine(hw); /* Program the Y descriptor */ @@ -1221,8 +1261,10 @@ static enum BC_STATUS crystalhd_hw_prog_rxdma(struct crystalhd_hw *hw, struct cr if (rx_pkt->uv_phy_addr) { /* Program the UV descriptor */ desc_addr.full_addr = rx_pkt->uv_phy_addr; - crystalhd_reg_wr(hw->adp, uv_high_addr_reg, desc_addr.high_part); - crystalhd_reg_wr(hw->adp, uv_low_addr_reg, desc_addr.low_part | 0x01); + crystalhd_reg_wr(hw->adp, uv_high_addr_reg, + desc_addr.high_part); + crystalhd_reg_wr(hw->adp, uv_low_addr_reg, + desc_addr.low_part | 0x01); } return BC_STS_SUCCESS; @@ -1268,16 +1310,20 @@ static void crystalhd_hw_finalize_pause(struct crystalhd_hw *hw) hw->stop_pending = 0; - dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); + dma_cntrl = crystalhd_reg_rd(hw->adp, + MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); if (dma_cntrl & DMA_START_BIT) { dma_cntrl &= ~DMA_START_BIT; - crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); + crystalhd_reg_wr(hw->adp, + MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); } - dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); + dma_cntrl = crystalhd_reg_rd(hw->adp, + MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); if (dma_cntrl & DMA_START_BIT) { dma_cntrl &= ~DMA_START_BIT; - crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); + crystalhd_reg_wr(hw->adp, + MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); } hw->rx_list_post_index = 0; @@ -1287,8 +1333,8 @@ static void crystalhd_hw_finalize_pause(struct crystalhd_hw *hw) crystalhd_reg_wr(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, aspm); } -static enum BC_STATUS crystalhd_rx_pkt_done(struct crystalhd_hw *hw, uint32_t list_index, - enum BC_STATUS comp_sts) +static enum BC_STATUS crystalhd_rx_pkt_done(struct crystalhd_hw *hw, + uint32_t list_index, enum BC_STATUS comp_sts) { struct crystalhd_rx_dma_pkt *rx_pkt = NULL; uint32_t y_dw_dnsz, uv_dw_dnsz; @@ -1302,7 +1348,8 @@ static enum BC_STATUS crystalhd_rx_pkt_done(struct crystalhd_hw *hw, uint32_t li rx_pkt = crystalhd_dioq_find_and_fetch(hw->rx_actq, hw->rx_pkt_tag_seed + list_index); if (!rx_pkt) { - BCMLOG_ERR("Act-Q:PostIx:%x L0Sts:%x L1Sts:%x current L:%x tag:%x comp:%x\n", + BCMLOG_ERR( + "Act-Q:PostIx:%x L0Sts:%x L1Sts:%x current L:%x tag:%x comp:%x\n", hw->rx_list_post_index, hw->rx_list_sts[0], hw->rx_list_sts[1], list_index, hw->rx_pkt_tag_seed + list_index, comp_sts); @@ -1324,8 +1371,8 @@ static enum BC_STATUS crystalhd_rx_pkt_done(struct crystalhd_hw *hw, uint32_t li return crystalhd_hw_post_cap_buff(hw, rx_pkt); } -static bool crystalhd_rx_list0_handler(struct crystalhd_hw *hw, uint32_t int_sts, - uint32_t y_err_sts, uint32_t uv_err_sts) +static bool crystalhd_rx_list0_handler(struct crystalhd_hw *hw, + uint32_t int_sts, uint32_t y_err_sts, uint32_t uv_err_sts) { uint32_t tmp; enum list_sts tmp_lsts; @@ -1367,7 +1414,8 @@ static bool crystalhd_rx_list0_handler(struct crystalhd_hw *hw, uint32_t int_sts tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK; } - if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) { + if (uv_err_sts & + MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) { hw->rx_list_sts[0] &= ~rx_uv_mask; hw->rx_list_sts[0] |= rx_uv_error; tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK; @@ -1392,8 +1440,8 @@ static bool crystalhd_rx_list0_handler(struct crystalhd_hw *hw, uint32_t int_sts return (tmp_lsts != hw->rx_list_sts[0]); } -static bool crystalhd_rx_list1_handler(struct crystalhd_hw *hw, uint32_t int_sts, - uint32_t y_err_sts, uint32_t uv_err_sts) +static bool crystalhd_rx_list1_handler(struct crystalhd_hw *hw, + uint32_t int_sts, uint32_t y_err_sts, uint32_t uv_err_sts) { uint32_t tmp; enum list_sts tmp_lsts; @@ -1486,9 +1534,11 @@ static void crystalhd_rx_isr(struct crystalhd_hw *hw, uint32_t intr_sts) /* Update States..*/ spin_lock_irqsave(&hw->rx_lock, flags); if (i == 0) - ret = crystalhd_rx_list0_handler(hw, intr_sts, y_err_sts, uv_err_sts); + ret = crystalhd_rx_list0_handler(hw, intr_sts, + y_err_sts, uv_err_sts); else - ret = crystalhd_rx_list1_handler(hw, intr_sts, y_err_sts, uv_err_sts); + ret = crystalhd_rx_list1_handler(hw, intr_sts, + y_err_sts, uv_err_sts); if (ret) { switch (hw->rx_list_sts[i]) { case sts_free: @@ -1501,11 +1551,13 @@ static void crystalhd_rx_isr(struct crystalhd_hw *hw, uint32_t intr_sts) /* We got error on both or Y or uv. */ hw->stats.rx_errors++; crystalhd_get_dnsz(hw, i, &y_dn_sz, &uv_dn_sz); - /* FIXME: jarod: this is where my mini pci-e card is tripping up */ + /* FIXME: jarod: this is where + my mini pci-e card is tripping up */ BCMLOG(BCMLOG_DBG, "list_index:%x rx[%d] Y:%x " "UV:%x Int:%x YDnSz:%x UVDnSz:%x\n", i, hw->stats.rx_errors, y_err_sts, - uv_err_sts, intr_sts, y_dn_sz, uv_dn_sz); + uv_err_sts, intr_sts, y_dn_sz, + uv_dn_sz); hw->rx_list_sts[i] = sts_free; comp_sts = BC_STS_ERROR; break; @@ -1567,14 +1619,17 @@ static enum BC_STATUS crystalhd_put_ddr2sleep(struct crystalhd_hw *hw) union link_misc_perst_decoder_ctrl rst_cntrl_reg; /* Pulse reset pin of 7412 (MISC_PERST_DECODER_CTRL) */ - rst_cntrl_reg.whole_reg = crystalhd_reg_rd(hw->adp, MISC_PERST_DECODER_CTRL); + rst_cntrl_reg.whole_reg = crystalhd_reg_rd(hw->adp, + MISC_PERST_DECODER_CTRL); rst_cntrl_reg.bcm_7412_rst = 1; - crystalhd_reg_wr(hw->adp, MISC_PERST_DECODER_CTRL, rst_cntrl_reg.whole_reg); + crystalhd_reg_wr(hw->adp, MISC_PERST_DECODER_CTRL, + rst_cntrl_reg.whole_reg); msleep_interruptible(50); rst_cntrl_reg.bcm_7412_rst = 0; - crystalhd_reg_wr(hw->adp, MISC_PERST_DECODER_CTRL, rst_cntrl_reg.whole_reg); + crystalhd_reg_wr(hw->adp, MISC_PERST_DECODER_CTRL, + rst_cntrl_reg.whole_reg); /* Close all banks, put DDR in idle */ bc_dec_reg_wr(hw->adp, SDRAM_PRECHARGE, 0); @@ -1622,7 +1677,8 @@ static enum BC_STATUS crystalhd_put_ddr2sleep(struct crystalhd_hw *hw) ** *************************************************/ -enum BC_STATUS crystalhd_download_fw(struct crystalhd_adp *adp, void *buffer, uint32_t sz) +enum BC_STATUS crystalhd_download_fw(struct crystalhd_adp *adp, void *buffer, + uint32_t sz) { uint32_t reg_data, cnt, *temp_buff; uint32_t fw_sig_len = 36; @@ -1828,7 +1884,8 @@ bool crystalhd_hw_interrupt(struct crystalhd_adp *adp, struct crystalhd_hw *hw) crystalhd_hw_proc_pib(hw); bc_dec_reg_wr(adp, Stream2Host_Intr_Sts, deco_intr); - /* FIXME: jarod: No udelay? might this be the real reason mini pci-e cards were stalling out? */ + /* FIXME: jarod: No udelay? might this be + the real reason mini pci-e cards were stalling out? */ bc_dec_reg_wr(adp, Stream2Host_Intr_Sts, 0); rc = 1; } @@ -1852,7 +1909,8 @@ bool crystalhd_hw_interrupt(struct crystalhd_adp *adp, struct crystalhd_hw *hw) return rc; } -enum BC_STATUS crystalhd_hw_open(struct crystalhd_hw *hw, struct crystalhd_adp *adp) +enum BC_STATUS crystalhd_hw_open(struct crystalhd_hw *hw, + struct crystalhd_adp *adp) { if (!hw || !adp) { BCMLOG_ERR("Invalid Arguments\n"); @@ -1967,7 +2025,8 @@ enum BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *hw) } rpkt->desc_mem.pdma_desc_start = mem; rpkt->desc_mem.phy_addr = phy_addr; - rpkt->desc_mem.sz = BC_LINK_MAX_SGLS * sizeof(struct dma_descriptor); + rpkt->desc_mem.sz = BC_LINK_MAX_SGLS * + sizeof(struct dma_descriptor); rpkt->pkt_tag = hw->rx_pkt_tag_seed + i; crystalhd_hw_free_rx_pkt(hw, rpkt); } @@ -2013,7 +2072,8 @@ enum BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *hw) return BC_STS_SUCCESS; } -enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, struct crystalhd_dio_req *ioreq, +enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, + struct crystalhd_dio_req *ioreq, hw_comp_callback call_back, wait_queue_head_t *cb_event, uint32_t *list_id, uint8_t data_flags) @@ -2047,7 +2107,8 @@ enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, struct crystalhd_di } /* Get a list from TxFreeQ */ - tx_dma_packet = (struct tx_dma_pkt *)crystalhd_dioq_fetch(hw->tx_freeq); + tx_dma_packet = (struct tx_dma_pkt *)crystalhd_dioq_fetch( + hw->tx_freeq); if (!tx_dma_packet) { BCMLOG_ERR("No empty elements..\n"); return BC_STS_ERR_USAGE; @@ -2105,7 +2166,8 @@ enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, struct crystalhd_di crystalhd_start_tx_dma_engine(hw); crystalhd_reg_wr(hw->adp, first_desc_u_addr, desc_addr.high_part); - crystalhd_reg_wr(hw->adp, first_desc_l_addr, desc_addr.low_part | 0x01); + crystalhd_reg_wr(hw->adp, first_desc_l_addr, desc_addr.low_part | + 0x01); /* Be sure we set the valid bit ^^^^ */ return BC_STS_SUCCESS; @@ -2120,7 +2182,8 @@ enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, struct crystalhd_di * * FIX_ME: Not Tested the actual condition.. */ -enum BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id) +enum BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, + uint32_t list_id) { if (!hw || !list_id) { BCMLOG_ERR("Invalid Arguments\n"); @@ -2134,7 +2197,7 @@ enum BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id) } enum BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw, - struct crystalhd_dio_req *ioreq, bool en_post) + struct crystalhd_dio_req *ioreq, bool en_post) { struct crystalhd_rx_dma_pkt *rpkt; uint32_t tag, uv_desc_ix = 0; @@ -2154,7 +2217,8 @@ enum BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw, rpkt->dio_req = ioreq; tag = rpkt->pkt_tag; - sts = crystalhd_xlat_sgl_to_dma_desc(ioreq, &rpkt->desc_mem, &uv_desc_ix); + sts = crystalhd_xlat_sgl_to_dma_desc(ioreq, &rpkt->desc_mem, + &uv_desc_ix); if (sts != BC_STS_SUCCESS) return sts; @@ -2163,7 +2227,7 @@ enum BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw, /* Store the address of UV in the rx packet for post*/ if (uv_desc_ix) rpkt->uv_phy_addr = rpkt->desc_mem.phy_addr + - (sizeof(struct dma_descriptor) * (uv_desc_ix + 1)); + (sizeof(struct dma_descriptor) * (uv_desc_ix + 1)); if (en_post) sts = crystalhd_hw_post_cap_buff(hw, rpkt); @@ -2190,7 +2254,8 @@ enum BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw, rpkt = crystalhd_dioq_fetch_wait(hw->rx_rdyq, timeout, &sig_pending); if (!rpkt) { if (sig_pending) { - BCMLOG(BCMLOG_INFO, "wait on frame time out %d\n", sig_pending); + BCMLOG(BCMLOG_INFO, "wait on frame time out %d\n", + sig_pending); return BC_STS_IO_USER_ABORT; } else { return BC_STS_TIMEOUT; @@ -2305,7 +2370,8 @@ enum BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw) return BC_STS_SUCCESS; } -void crystalhd_hw_stats(struct crystalhd_hw *hw, struct crystalhd_hw_stats *stats) +void crystalhd_hw_stats(struct crystalhd_hw *hw, + struct crystalhd_hw_stats *stats) { if (!hw) { BCMLOG_ERR("Invalid Arguments\n"); @@ -2378,7 +2444,8 @@ enum BC_STATUS crystalhd_hw_set_core_clock(struct crystalhd_hw *hw) if (reg & 0x00020000) { hw->prev_n = n; - /* FIXME: jarod: outputting a random "C" is... confusing... */ + /* FIXME: jarod: outputting + a random "C" is... confusing... */ BCMLOG(BCMLOG_INFO, "C"); return BC_STS_SUCCESS; } else { diff --git a/drivers/staging/crystalhd/crystalhd_hw.h b/drivers/staging/crystalhd/crystalhd_hw.h index 2d0e6c6005e5..37809442c553 100644 --- a/drivers/staging/crystalhd/crystalhd_hw.h +++ b/drivers/staging/crystalhd/crystalhd_hw.h @@ -46,7 +46,7 @@ #define Cpu2HstMbx1 0x00100F04 #define MbxStat1 0x00100F08 #define Stream2Host_Intr_Sts 0x00100F24 -#define C011_RET_SUCCESS 0x0 /* Reutrn status of firmware command. */ +#define C011_RET_SUCCESS 0x0 /* Reutrn status of firmware command. */ /* TS input status register */ #define TS_StreamAFIFOStatus 0x0010044C @@ -103,7 +103,7 @@ #define BC_FWIMG_ST_ADDR 0x00000000 /* FIXME: jarod: there's a kernel function that'll do this for us... */ #define rotr32_1(x, n) (((x) >> n) | ((x) << (32 - n))) -#define bswap_32_1(x) ((rotr32_1((x), 24) & 0x00ff00ff) | (rotr32_1((x), 8) & 0xff00ff00)) +#define bswap_32_1(x) ((rotr32_1((x), 24) & 0x00ff00ff) | (rotr32_1((x), 8) & 0xff00ff00)) #define DecHt_HostSwReset 0x340000 #define BC_DRAM_FW_CFG_ADDR 0x001c2000 @@ -136,9 +136,11 @@ union intr_mask_reg { union link_misc_perst_deco_ctrl { struct { - uint32_t bcm7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/ + uint32_t bcm7412_rst:1; /* 1 -> BCM7412 is held + in reset. Reset value 1.*/ uint32_t reserved0:3; /* Reserved.No Effect*/ - uint32_t stop_bcm_7412_clk:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/ + uint32_t stop_bcm_7412_clk:1; /* 1 ->Stops branch of + 27MHz clk used to clk BCM7412*/ uint32_t reserved1:27; /* Reseved. No Effect*/ }; @@ -148,13 +150,18 @@ union link_misc_perst_deco_ctrl { union link_misc_perst_clk_ctrl { struct { - uint32_t sel_alt_clk:1; /* When set, selects a 6.75MHz clock as the source of core_clk */ - uint32_t stop_core_clk:1; /* When set, stops the branch of core_clk that is not needed for low power operation */ - uint32_t pll_pwr_dn:1; /* When set, powers down the main PLL. The alternate clock bit should be set - to select an alternate clock before setting this bit.*/ + uint32_t sel_alt_clk:1; /* When set, selects a + 6.75MHz clock as the source of core_clk */ + uint32_t stop_core_clk:1; /* When set, stops the branch + of core_clk that is not needed for low power operation */ + uint32_t pll_pwr_dn:1; /* When set, powers down the + main PLL. The alternate clock bit should be set to + select an alternate clock before setting this bit.*/ uint32_t reserved0:5; /* Reserved */ - uint32_t pll_mult:8; /* This setting controls the multiplier for the PLL. */ - uint32_t pll_div:4; /* This setting controls the divider for the PLL. */ + uint32_t pll_mult:8; /* This setting controls + the multiplier for the PLL. */ + uint32_t pll_div:4; /* This setting controls + the divider for the PLL. */ uint32_t reserved1:12; /* Reserved */ }; @@ -164,9 +171,11 @@ union link_misc_perst_clk_ctrl { union link_misc_perst_decoder_ctrl { struct { - uint32_t bcm_7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/ + uint32_t bcm_7412_rst:1; /* 1 -> BCM7412 is held + in reset. Reset value 1.*/ uint32_t res0:3; /* Reserved.No Effect*/ - uint32_t stop_7412_clk:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/ + uint32_t stop_7412_clk:1; /* 1 ->Stops branch of 27MHz + clk used to clk BCM7412*/ uint32_t res1:27; /* Reseved. No Effect */ }; @@ -225,10 +234,12 @@ struct dma_descriptor { /* 8 32-bit values */ * The virtual address will determine what should be freed. */ struct dma_desc_mem { - struct dma_descriptor *pdma_desc_start; /* 32-bytes for dma descriptor. should be first element */ - dma_addr_t phy_addr; /* physical address of each DMA desc */ + struct dma_descriptor *pdma_desc_start; /* 32-bytes for dma + descriptor. should be first element */ + dma_addr_t phy_addr; /* physical address + of each DMA desc */ uint32_t sz; - struct _dma_desc_mem_ *Next; /* points to Next Descriptor in chain */ + struct _dma_desc_mem_ *Next; /* points to Next Descriptor in chain */ }; @@ -323,50 +334,54 @@ struct crystalhd_hw { #define CLOCK_PRESET 175 /* DMA engine register BIT mask wrappers.. */ -#define DMA_START_BIT MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK - -#define GET_RX_INTR_MASK (INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK | \ - INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK | \ - INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK | \ - INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK | \ - INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK | \ - INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK | \ - INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK | \ - INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK) - -#define GET_Y0_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \ - MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \ - MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \ - MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) - -#define GET_UV0_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \ - MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \ - MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \ - MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) - -#define GET_Y1_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \ - MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \ - MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \ - MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) - -#define GET_UV1_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \ - MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \ - MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \ - MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) +#define DMA_START_BIT MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK + +#define GET_RX_INTR_MASK (INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK | \ + INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK | \ + INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK | \ + INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK | \ + INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK | \ + INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK | \ + INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK | \ + INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK) + +#define GET_Y0_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \ + MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \ + MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \ + MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) + +#define GET_UV0_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \ + MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \ + MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \ + MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) + +#define GET_Y1_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \ + MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \ + MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \ + MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) + +#define GET_UV1_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \ + MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \ + MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \ + MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) /**** API Exposed to the other layers ****/ enum BC_STATUS crystalhd_download_fw(struct crystalhd_adp *adp, void *buffer, uint32_t sz); -enum BC_STATUS crystalhd_do_fw_cmd(struct crystalhd_hw *hw, struct BC_FW_CMD *fw_cmd); -bool crystalhd_hw_interrupt(struct crystalhd_adp *adp, struct crystalhd_hw *hw); -enum BC_STATUS crystalhd_hw_open(struct crystalhd_hw *, struct crystalhd_adp *); +enum BC_STATUS crystalhd_do_fw_cmd(struct crystalhd_hw *hw, + struct BC_FW_CMD *fw_cmd); +bool crystalhd_hw_interrupt(struct crystalhd_adp *adp, + struct crystalhd_hw *hw); +enum BC_STATUS crystalhd_hw_open(struct crystalhd_hw *, + struct crystalhd_adp *); enum BC_STATUS crystalhd_hw_close(struct crystalhd_hw *); enum BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *); enum BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *); -enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, struct crystalhd_dio_req *ioreq, +enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, + struct crystalhd_dio_req *ioreq, hw_comp_callback call_back, wait_queue_head_t *cb_event, uint32_t *list_id, uint8_t data_flags); @@ -374,15 +389,17 @@ enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, struct crystalhd_di enum BC_STATUS crystalhd_hw_pause(struct crystalhd_hw *hw); enum BC_STATUS crystalhd_hw_unpause(struct crystalhd_hw *hw); enum BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw); -enum BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id); +enum BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, + uint32_t list_id); enum BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw, - struct crystalhd_dio_req *ioreq, bool en_post); + struct crystalhd_dio_req *ioreq, bool en_post); enum BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw, struct BC_PIC_INFO_BLOCK *pib, struct crystalhd_dio_req **ioreq); enum BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw); enum BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw); -void crystalhd_hw_stats(struct crystalhd_hw *hw, struct crystalhd_hw_stats *stats); +void crystalhd_hw_stats(struct crystalhd_hw *hw, + struct crystalhd_hw_stats *stats); /* API to program the core clock on the decoder */ enum BC_STATUS crystalhd_hw_set_core_clock(struct crystalhd_hw *); diff --git a/drivers/staging/crystalhd/crystalhd_lnx.c b/drivers/staging/crystalhd/crystalhd_lnx.c index 85f51fb18425..c1f6163cdeb8 100644 --- a/drivers/staging/crystalhd/crystalhd_lnx.c +++ b/drivers/staging/crystalhd/crystalhd_lnx.c @@ -75,7 +75,8 @@ static int chd_dec_disable_int(struct crystalhd_adp *adp) return 0; } -struct crystalhd_ioctl_data *chd_dec_alloc_iodata(struct crystalhd_adp *adp, bool isr) +struct crystalhd_ioctl_data *chd_dec_alloc_iodata(struct crystalhd_adp *adp, + bool isr) { unsigned long flags = 0; struct crystalhd_ioctl_data *temp; @@ -95,8 +96,8 @@ struct crystalhd_ioctl_data *chd_dec_alloc_iodata(struct crystalhd_adp *adp, boo return temp; } -void chd_dec_free_iodata(struct crystalhd_adp *adp, struct crystalhd_ioctl_data *iodata, - bool isr) +void chd_dec_free_iodata(struct crystalhd_adp *adp, + struct crystalhd_ioctl_data *iodata, bool isr) { unsigned long flags = 0; @@ -109,7 +110,8 @@ void chd_dec_free_iodata(struct crystalhd_adp *adp, struct crystalhd_ioctl_data spin_unlock_irqrestore(&adp->lock, flags); } -static inline int crystalhd_user_data(unsigned long ud, void *dr, int size, int set) +static inline int crystalhd_user_data(unsigned long ud, void *dr, + int size, int set) { int rc; @@ -131,8 +133,8 @@ static inline int crystalhd_user_data(unsigned long ud, void *dr, int size, int return rc; } -static int chd_dec_fetch_cdata(struct crystalhd_adp *adp, struct crystalhd_ioctl_data *io, - uint32_t m_sz, unsigned long ua) +static int chd_dec_fetch_cdata(struct crystalhd_adp *adp, + struct crystalhd_ioctl_data *io, uint32_t m_sz, unsigned long ua) { unsigned long ua_off; int rc = 0; @@ -163,7 +165,7 @@ static int chd_dec_fetch_cdata(struct crystalhd_adp *adp, struct crystalhd_ioctl } static int chd_dec_release_cdata(struct crystalhd_adp *adp, - struct crystalhd_ioctl_data *io, unsigned long ua) + struct crystalhd_ioctl_data *io, unsigned long ua) { unsigned long ua_off; int rc; @@ -178,8 +180,9 @@ static int chd_dec_release_cdata(struct crystalhd_adp *adp, rc = crystalhd_user_data(ua_off, io->add_cdata, io->add_cdata_sz, 1); if (rc) { - BCMLOG_ERR("failed to push add_cdata sz:%x ua_off:%x\n", - io->add_cdata_sz, (unsigned int)ua_off); + BCMLOG_ERR( + "failed to push add_cdata sz:%x ua_off:%x\n", + io->add_cdata_sz, (unsigned int)ua_off); return -ENODATA; } } @@ -252,10 +255,7 @@ static int chd_dec_api_cmd(struct crystalhd_adp *adp, unsigned long ua, rc = chd_dec_proc_user_data(adp, temp, ua, 1); } - if (temp) { - chd_dec_free_iodata(adp, temp, 0); - temp = NULL; - } + chd_dec_free_iodata(adp, temp, 0); return rc; } @@ -378,8 +378,8 @@ static int chd_dec_init_chdev(struct crystalhd_adp *adp) goto class_create_fail; } - dev = device_create(crystalhd_class, NULL, MKDEV(adp->chd_dec_major, 0), - NULL, "crystalhd"); + dev = device_create(crystalhd_class, NULL, + MKDEV(adp->chd_dec_major, 0), NULL, "crystalhd"); if (IS_ERR(dev)) { rc = PTR_ERR(dev); BCMLOG_ERR("failed to create device\n"); @@ -394,7 +394,8 @@ static int chd_dec_init_chdev(struct crystalhd_adp *adp) /* Allocate general purpose ioctl pool. */ for (i = 0; i < CHD_IODATA_POOL_SZ; i++) { - temp = kzalloc(sizeof(struct crystalhd_ioctl_data), GFP_KERNEL); + temp = kzalloc(sizeof(struct crystalhd_ioctl_data), + GFP_KERNEL); if (!temp) { BCMLOG_ERR("ioctl data pool kzalloc failed\n"); rc = -ENOMEM; diff --git a/drivers/staging/crystalhd/crystalhd_lnx.h b/drivers/staging/crystalhd/crystalhd_lnx.h index a9e36336d097..bac572a8bc2e 100644 --- a/drivers/staging/crystalhd/crystalhd_lnx.h +++ b/drivers/staging/crystalhd/crystalhd_lnx.h @@ -77,8 +77,8 @@ struct crystalhd_adp { int chd_dec_major; unsigned int cfg_users; - struct crystalhd_ioctl_data *idata_free_head; /* ioctl data pool */ - struct crystalhd_elem *elem_pool_head; /* Queue element pool */ + struct crystalhd_ioctl_data *idata_free_head; /* ioctl data pool */ + struct crystalhd_elem *elem_pool_head; /* Queue element pool */ struct crystalhd_cmd cmds; diff --git a/drivers/staging/crystalhd/crystalhd_misc.c b/drivers/staging/crystalhd/crystalhd_misc.c index a5f109c632dc..51f698052aff 100644 --- a/drivers/staging/crystalhd/crystalhd_misc.c +++ b/drivers/staging/crystalhd/crystalhd_misc.c @@ -30,19 +30,22 @@ uint32_t g_linklog_level; -static inline uint32_t crystalhd_dram_rd(struct crystalhd_adp *adp, uint32_t mem_off) +static inline uint32_t crystalhd_dram_rd(struct crystalhd_adp *adp, + uint32_t mem_off) { crystalhd_reg_wr(adp, DCI_DRAM_BASE_ADDR, (mem_off >> 19)); return bc_dec_reg_rd(adp, (0x00380000 | (mem_off & 0x0007FFFF))); } -static inline void crystalhd_dram_wr(struct crystalhd_adp *adp, uint32_t mem_off, uint32_t val) +static inline void crystalhd_dram_wr(struct crystalhd_adp *adp, + uint32_t mem_off, uint32_t val) { crystalhd_reg_wr(adp, DCI_DRAM_BASE_ADDR, (mem_off >> 19)); bc_dec_reg_wr(adp, (0x00380000 | (mem_off & 0x0007FFFF)), val); } -static inline enum BC_STATUS bc_chk_dram_range(struct crystalhd_adp *adp, uint32_t start_off, uint32_t cnt) +static inline enum BC_STATUS bc_chk_dram_range(struct crystalhd_adp *adp, + uint32_t start_off, uint32_t cnt) { return BC_STS_SUCCESS; } @@ -66,7 +69,8 @@ static struct crystalhd_dio_req *crystalhd_alloc_dio(struct crystalhd_adp *adp) return temp; } -static void crystalhd_free_dio(struct crystalhd_adp *adp, struct crystalhd_dio_req *dio) +static void crystalhd_free_dio(struct crystalhd_adp *adp, + struct crystalhd_dio_req *dio) { unsigned long flags = 0; @@ -99,7 +103,8 @@ static struct crystalhd_elem *crystalhd_alloc_elem(struct crystalhd_adp *adp) return temp; } -static void crystalhd_free_elem(struct crystalhd_adp *adp, struct crystalhd_elem *elem) +static void crystalhd_free_elem(struct crystalhd_adp *adp, + struct crystalhd_elem *elem) { unsigned long flags = 0; @@ -120,7 +125,8 @@ static inline void crystalhd_set_sg(struct scatterlist *sg, struct page *page, #endif } -static inline void crystalhd_init_sg(struct scatterlist *sg, unsigned int entries) +static inline void crystalhd_init_sg(struct scatterlist *sg, + unsigned int entries) { /* http://lkml.org/lkml/2007/11/27/68 */ sg_init_table(sg, entries); @@ -208,7 +214,8 @@ uint32_t crystalhd_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off) * configuration space. * */ -void crystalhd_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val) +void crystalhd_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, + uint32_t val) { if (!adp || (reg_off > adp->pci_i2o_len)) { BCMLOG_ERR("link_wr_reg_off outof range: 0x%08x\n", reg_off); @@ -469,7 +476,8 @@ enum BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *adp, * by calling the call back provided during creation. * */ -void crystalhd_delete_dioq(struct crystalhd_adp *adp, struct crystalhd_dioq *dioq) +void crystalhd_delete_dioq(struct crystalhd_adp *adp, + struct crystalhd_dioq *dioq) { void *temp; @@ -639,7 +647,8 @@ void *crystalhd_dioq_fetch_wait(struct crystalhd_dioq *ioq, uint32_t to_secs, while ((ioq->count == 0) && count) { spin_unlock_irqrestore(&ioq->lock, flags); - crystalhd_wait_on_event(&ioq->event, (ioq->count > 0), 1000, rc, 0); + crystalhd_wait_on_event(&ioq->event, + (ioq->count > 0), 1000, rc, 0); if (rc == 0) { goto out; } else if (rc == -EINTR) { @@ -678,7 +687,8 @@ enum BC_STATUS crystalhd_map_dio(struct crystalhd_adp *adp, void *ubuff, struct crystalhd_dio_req **dio_hnd) { struct crystalhd_dio_req *dio; - /* FIXME: jarod: should some of these unsigned longs be uint32_t or uintptr_t? */ + /* FIXME: jarod: should some of these + unsigned longs be uint32_t or uintptr_t? */ unsigned long start = 0, end = 0, uaddr = 0, count = 0; unsigned long spsz = 0, uv_start = 0; int i = 0, rw = 0, res = 0, nr_pages = 0, skip_fb_sg = 0; @@ -723,7 +733,8 @@ enum BC_STATUS crystalhd_map_dio(struct crystalhd_adp *adp, void *ubuff, if (uv_offset) { uv_start = (uaddr + (unsigned long)uv_offset) >> PAGE_SHIFT; dio->uinfo.uv_sg_ix = uv_start - start; - dio->uinfo.uv_sg_off = ((uaddr + (unsigned long)uv_offset) & ~PAGE_MASK); + dio->uinfo.uv_sg_off = ((uaddr + (unsigned long)uv_offset) & + ~PAGE_MASK); } dio->fb_size = ubuff_sz & 0x03; @@ -819,7 +830,8 @@ enum BC_STATUS crystalhd_map_dio(struct crystalhd_adp *adp, void *ubuff, * * This routine is to unmap the user buffer pages. */ -enum BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *adp, struct crystalhd_dio_req *dio) +enum BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *adp, + struct crystalhd_dio_req *dio) { struct page *page = NULL; int j = 0; @@ -841,7 +853,8 @@ enum BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *adp, struct crystalhd_d } } if (dio->sig == crystalhd_dio_sg_mapped) - pci_unmap_sg(adp->pdev, dio->sg, dio->page_cnt, dio->direction); + pci_unmap_sg(adp->pdev, dio->sg, dio->page_cnt, + dio->direction); crystalhd_free_dio(adp, dio); diff --git a/drivers/staging/crystalhd/crystalhd_misc.h b/drivers/staging/crystalhd/crystalhd_misc.h index 8cdaa7a34814..4dae3a797e95 100644 --- a/drivers/staging/crystalhd/crystalhd_misc.h +++ b/drivers/staging/crystalhd/crystalhd_misc.h @@ -127,12 +127,16 @@ uint32_t crystalhd_reg_rd(struct crystalhd_adp *, uint32_t); void crystalhd_reg_wr(struct crystalhd_adp *, uint32_t, uint32_t); /*========= Decoder (7412) memory access routines..=================*/ -enum BC_STATUS crystalhd_mem_rd(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t *); -enum BC_STATUS crystalhd_mem_wr(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t *); +enum BC_STATUS crystalhd_mem_rd(struct crystalhd_adp *, + uint32_t, uint32_t, uint32_t *); +enum BC_STATUS crystalhd_mem_wr(struct crystalhd_adp *, + uint32_t, uint32_t, uint32_t *); /*==========Link (70012) PCIe Config access routines.================*/ -enum BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t *); -enum BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t); +enum BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *, + uint32_t, uint32_t, uint32_t *); +enum BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *, + uint32_t, uint32_t, uint32_t); /*========= Linux Kernel Interface routines. ======================= */ void *bc_kern_dma_alloc(struct crystalhd_adp *, uint32_t, dma_addr_t *); @@ -168,20 +172,26 @@ do { \ /*================ Direct IO mapping routines ==================*/ extern int crystalhd_create_dio_pool(struct crystalhd_adp *, uint32_t); extern void crystalhd_destroy_dio_pool(struct crystalhd_adp *); -extern enum BC_STATUS crystalhd_map_dio(struct crystalhd_adp *, void *, uint32_t, - uint32_t, bool, bool, struct crystalhd_dio_req**); +extern enum BC_STATUS crystalhd_map_dio(struct crystalhd_adp *, void *, + uint32_t, uint32_t, bool, bool, struct crystalhd_dio_req**); -extern enum BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *, struct crystalhd_dio_req*); +extern enum BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *, + struct crystalhd_dio_req*); #define crystalhd_get_sgle_paddr(_dio, _ix) (cpu_to_le64(sg_dma_address(&_dio->sg[_ix]))) #define crystalhd_get_sgle_len(_dio, _ix) (cpu_to_le32(sg_dma_len(&_dio->sg[_ix]))) /*================ General Purpose Queues ==================*/ -extern enum BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *, struct crystalhd_dioq **, crystalhd_data_free_cb , void *); -extern void crystalhd_delete_dioq(struct crystalhd_adp *, struct crystalhd_dioq *); -extern enum BC_STATUS crystalhd_dioq_add(struct crystalhd_dioq *ioq, void *data, bool wake, uint32_t tag); +extern enum BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *, + struct crystalhd_dioq **, crystalhd_data_free_cb , void *); +extern void crystalhd_delete_dioq(struct crystalhd_adp *, + struct crystalhd_dioq *); +extern enum BC_STATUS crystalhd_dioq_add(struct crystalhd_dioq *ioq, + void *data, bool wake, uint32_t tag); extern void *crystalhd_dioq_fetch(struct crystalhd_dioq *ioq); -extern void *crystalhd_dioq_find_and_fetch(struct crystalhd_dioq *ioq, uint32_t tag); -extern void *crystalhd_dioq_fetch_wait(struct crystalhd_dioq *ioq, uint32_t to_secs, uint32_t *sig_pend); +extern void *crystalhd_dioq_find_and_fetch(struct crystalhd_dioq *ioq, + uint32_t tag); +extern void *crystalhd_dioq_fetch_wait(struct crystalhd_dioq *ioq, + uint32_t to_secs, uint32_t *sig_pend); #define crystalhd_dioq_count(_ioq) ((_ioq) ? _ioq->count : 0) @@ -190,7 +200,8 @@ extern void crystalhd_delete_elem_pool(struct crystalhd_adp *); /*================ Debug routines/macros .. ================================*/ -extern void crystalhd_show_buffer(uint32_t off, uint8_t *buff, uint32_t dwcount); +extern void crystalhd_show_buffer(uint32_t off, uint8_t *buff, + uint32_t dwcount); enum _chd_log_levels { BCMLOG_ERROR = 0x80000000, /* Don't disable this option */ |