diff options
Diffstat (limited to 'drivers/staging/cx25821/cx25821-video-upstream-ch2.c')
-rw-r--r-- | drivers/staging/cx25821/cx25821-video-upstream-ch2.c | 91 |
1 files changed, 56 insertions, 35 deletions
diff --git a/drivers/staging/cx25821/cx25821-video-upstream-ch2.c b/drivers/staging/cx25821/cx25821-video-upstream-ch2.c index 343df6619fe8..d12dbb572e8b 100644 --- a/drivers/staging/cx25821/cx25821-video-upstream-ch2.c +++ b/drivers/staging/cx25821/cx25821-video-upstream-ch2.c @@ -84,7 +84,7 @@ static __le32 *cx25821_risc_field_upstream_ch2(struct cx25821_dev *dev, { unsigned int line, i; struct sram_channel *sram_ch = - &dev->sram_channels[dev->_channel2_upstream_select]; + dev->channels[dev->_channel2_upstream_select].sram_channels; int dist_betwn_starts = bpl * 2; /* sync instruction */ @@ -110,8 +110,11 @@ static __le32 *cx25821_risc_field_upstream_ch2(struct cx25821_dev *dev, offset += dist_betwn_starts; } - // check if we need to enable the FIFO after the first 4 lines - // For the upstream video channel, the risc engine will enable the FIFO. + /* + check if we need to enable the FIFO after the first 4 lines + For the upstream video channel, the risc engine will enable + the FIFO. + */ if (fifo_enable && line == 3) { *(rp++) = RISC_WRITECR; *(rp++) = sram_ch->dma_ctl; @@ -130,7 +133,7 @@ int cx25821_risc_buffer_upstream_ch2(struct cx25821_dev *dev, { __le32 *rp; int fifo_enable = 0; - int singlefield_lines = lines >> 1; //get line count for single field + int singlefield_lines = lines >> 1; /*get line count for single field */ int odd_num_lines = singlefield_lines; int frame = 0; int frame_size = 0; @@ -174,7 +177,7 @@ int cx25821_risc_buffer_upstream_ch2(struct cx25821_dev *dev, fifo_enable = FIFO_DISABLE; - //Even field + /* Even field */ rp = cx25821_risc_field_upstream_ch2(dev, rp, dev-> _data_buf_phys_addr_ch2 + @@ -192,7 +195,10 @@ int cx25821_risc_buffer_upstream_ch2(struct cx25821_dev *dev, risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2; } - // Loop to 2ndFrameRISC or to Start of Risc program & generate IRQ + /* + Loop to 2ndFrameRISC or to Start of + Risc program & generate IRQ + */ *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag); *(rp++) = cpu_to_le32(risc_phys_jump_addr); *(rp++) = cpu_to_le32(0); @@ -204,7 +210,7 @@ int cx25821_risc_buffer_upstream_ch2(struct cx25821_dev *dev, void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev) { struct sram_channel *sram_ch = - &dev->sram_channels[VID_UPSTREAM_SRAM_CHANNEL_J]; + dev->channels[VID_UPSTREAM_SRAM_CHANNEL_J].sram_channels; u32 tmp = 0; if (!dev->_is_running_ch2) { @@ -212,15 +218,15 @@ void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev) ("cx25821: No video file is currently running so return!\n"); return; } - //Disable RISC interrupts + /* Disable RISC interrupts */ tmp = cx_read(sram_ch->int_msk); cx_write(sram_ch->int_msk, tmp & ~_intr_msk); - //Turn OFF risc and fifo + /* Turn OFF risc and fifo */ tmp = cx_read(sram_ch->dma_ctl); cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN)); - //Clear data buffer memory + /* Clear data buffer memory */ if (dev->_data_buf_virt_addr_ch2) memset(dev->_data_buf_virt_addr_ch2, 0, dev->_data_buf_size_ch2); @@ -371,8 +377,8 @@ static void cx25821_vidups_handler_ch2(struct work_struct *work) } cx25821_get_frame_ch2(dev, - &dev->sram_channels[dev-> - _channel2_upstream_select]); + dev->channels[dev-> + _channel2_upstream_select].sram_channels); } int cx25821_openfile_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch) @@ -488,7 +494,7 @@ static int cx25821_upstream_buffer_prepare_ch2(struct cx25821_dev *dev, return -ENOMEM; } - //Iniitize at this address until n bytes to 0 + /* Iniitize at this address until n bytes to 0 */ memset(dev->_dma_virt_addr_ch2, 0, dev->_risc_size_ch2); if (dev->_data_buf_virt_addr_ch2 != NULL) { @@ -496,7 +502,7 @@ static int cx25821_upstream_buffer_prepare_ch2(struct cx25821_dev *dev, dev->_data_buf_virt_addr_ch2, dev->_data_buf_phys_addr_ch2); } - //For Video Data buffer allocation + /* For Video Data buffer allocation */ dev->_data_buf_virt_addr_ch2 = pci_alloc_consistent(dev->pci, dev->upstream_databuf_size_ch2, &data_dma_addr); @@ -509,14 +515,14 @@ static int cx25821_upstream_buffer_prepare_ch2(struct cx25821_dev *dev, return -ENOMEM; } - //Initialize at this address until n bytes to 0 + /* Initialize at this address until n bytes to 0 */ memset(dev->_data_buf_virt_addr_ch2, 0, dev->_data_buf_size_ch2); ret = cx25821_openfile_ch2(dev, sram_ch); if (ret < 0) return ret; - //Creating RISC programs + /* Creating RISC programs */ ret = cx25821_risc_buffer_upstream_ch2(dev, dev->pci, 0, bpl, dev->_lines_count_ch2); @@ -536,7 +542,7 @@ int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev, int chan_num, u32 status) { u32 int_msk_tmp; - struct sram_channel *channel = &dev->sram_channels[chan_num]; + struct sram_channel *channel = dev->channels[chan_num].sram_channels; int singlefield_lines = NTSC_FIELD_HEIGHT; int line_size_in_bytes = Y422_LINE_SZ; int odd_risc_prog_size = 0; @@ -544,10 +550,13 @@ int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev, int chan_num, __le32 *rp; if (status & FLD_VID_SRC_RISC1) { - // We should only process one program per call + /* We should only process one program per call */ u32 prog_cnt = cx_read(channel->gpcnt); - //Since we've identified our IRQ, clear our bits from the interrupt mask and interrupt status registers + /* + Since we've identified our IRQ, clear our bits from the + interrupt mask and interrupt status registers + */ int_msk_tmp = cx_read(channel->int_msk); cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk); cx_write(channel->int_stat, _intr_msk); @@ -588,7 +597,7 @@ int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev, int chan_num, FIFO_DISABLE, ODD_FIELD); - // Jump to Even Risc program of 1st Frame + /* Jump to Even Risc program of 1st Frame */ *(rp++) = cpu_to_le32(RISC_JUMP); *(rp++) = cpu_to_le32(risc_phys_jump_addr); *(rp++) = cpu_to_le32(0); @@ -603,7 +612,7 @@ int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev, int chan_num, dev->_frame_count_ch2); return -1; } - //ElSE, set the interrupt mask register, re-enable irq. + /* ElSE, set the interrupt mask register, re-enable irq. */ int_msk_tmp = cx_read(channel->int_msk); cx_write(channel->int_msk, int_msk_tmp |= _intr_msk); @@ -623,12 +632,12 @@ static irqreturn_t cx25821_upstream_irq_ch2(int irq, void *dev_id) channel_num = VID_UPSTREAM_SRAM_CHANNEL_J; - sram_ch = &dev->sram_channels[channel_num]; + sram_ch = dev->channels[channel_num].sram_channels; msk_stat = cx_read(sram_ch->int_mstat); vid_status = cx_read(sram_ch->int_stat); - // Only deal with our interrupt + /* Only deal with our interrupt */ if (vid_status) { handled = cx25821_video_upstream_irq_ch2(dev, channel_num, @@ -658,7 +667,10 @@ static void cx25821_set_pixelengine_ch2(struct cx25821_dev *dev, value |= dev->_isNTSC_ch2 ? 0 : 0x10; cx_write(ch->vid_fmt_ctl, value); - // set number of active pixels in each line. Default is 720 pixels in both NTSC and PAL format + /* + set number of active pixels in each line. Default is 720 + pixels in both NTSC and PAL format + */ cx_write(ch->vid_active_ctl1, width); num_lines = (height / 2) & 0x3FF; @@ -670,7 +682,7 @@ static void cx25821_set_pixelengine_ch2(struct cx25821_dev *dev, value = (num_lines << 16) | odd_num_lines; - // set number of active lines in field 0 (top) and field 1 (bottom) + /* set number of active lines in field 0 (top) and field 1 (bottom) */ cx_write(ch->vid_active_ctl2, value); cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3); @@ -682,21 +694,27 @@ int cx25821_start_video_dma_upstream_ch2(struct cx25821_dev *dev, u32 tmp = 0; int err = 0; - // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C + /* + 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface + for channel A-C + */ tmp = cx_read(VID_CH_MODE_SEL); cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF); - // Set the physical start address of the RISC program in the initial program counter(IPC) member of the cmds. + /* + Set the physical start address of the RISC program in the initial + program counter(IPC) member of the cmds. + */ cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr_ch2); - cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */ + cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */ /* reset counter */ cx_write(sram_ch->gpcnt_ctl, 3); - // Clear our bits from the interrupt status register. + /* Clear our bits from the interrupt status register. */ cx_write(sram_ch->int_stat, _intr_msk); - //Set the interrupt mask register, enable irq. + /* Set the interrupt mask register, enable irq. */ cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit)); tmp = cx_read(sram_ch->int_msk); cx_write(sram_ch->int_msk, tmp |= _intr_msk); @@ -709,7 +727,7 @@ int cx25821_start_video_dma_upstream_ch2(struct cx25821_dev *dev, dev->pci->irq); goto fail_irq; } - // Start the DMA engine + /* Start the DMA engine */ tmp = cx_read(sram_ch->dma_ctl); cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN); @@ -740,7 +758,7 @@ int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select, } dev->_channel2_upstream_select = channel_select; - sram_ch = &dev->sram_channels[channel_select]; + sram_ch = dev->channels[channel_select].sram_channels; INIT_WORK(&dev->_irq_work_entry_ch2, cx25821_vidups_handler_ch2); dev->_irq_queues_ch2 = @@ -751,7 +769,10 @@ int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select, ("cx25821: create_singlethread_workqueue() for Video FAILED!\n"); return -ENOMEM; } - // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C + /* + 656/VIP SRC Upstream Channel I & J and 7 - + Host Bus Interface for channel A-C + */ tmp = cx_read(VID_CH_MODE_SEL); cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF); @@ -787,7 +808,7 @@ int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select, str_length + 1); } - //Default if filename is empty string + /* Default if filename is empty string */ if (strcmp(dev->input_filename_ch2, "") == 0) { if (dev->_isNTSC_ch2) { dev->_filename_ch2 = @@ -812,7 +833,7 @@ int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select, dev->upstream_riscbuf_size_ch2 = risc_buffer_size * 2; dev->upstream_databuf_size_ch2 = data_frame_size * 2; - //Allocating buffers and prepare RISC program + /* Allocating buffers and prepare RISC program */ retval = cx25821_upstream_buffer_prepare_ch2(dev, sram_ch, dev->_line_size_ch2); |