diff options
Diffstat (limited to 'drivers/staging/dgnc/dgnc_cls.h')
| -rw-r--r-- | drivers/staging/dgnc/dgnc_cls.h | 53 |
1 files changed, 23 insertions, 30 deletions
diff --git a/drivers/staging/dgnc/dgnc_cls.h b/drivers/staging/dgnc/dgnc_cls.h index 465d79a6f75f..2597e36d38c4 100644 --- a/drivers/staging/dgnc/dgnc_cls.h +++ b/drivers/staging/dgnc/dgnc_cls.h @@ -11,21 +11,11 @@ * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR * PURPOSE. See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * NOTE: THIS IS A SHARED HEADER. DO NOT CHANGE CODING STYLE!!! - * */ #ifndef __DGNC_CLS_H #define __DGNC_CLS_H -#include "dgnc_types.h" - - /************************************************************************ * Per channel/port Classic UART structure * ************************************************************************ @@ -35,15 +25,25 @@ * U = Unused. * ************************************************************************/ +/* + * txrx : WR RHR/THR - Holding reg + * ier : WR IER - Interrupt Enable Reg + * isr_fcr : WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg + * lcr : WR LCR - Line Control Reg + * mcr : WR MCR - Modem Control Reg + * lsr : WR LSR - Line Status Reg + * msr : WR MSG - Modem Status Reg + * spr : WR SPR - Scratch pad Reg + */ struct cls_uart_struct { - u8 txrx; /* WR RHR/THR - Holding Reg */ - u8 ier; /* WR IER - Interrupt Enable Reg */ - u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */ - u8 lcr; /* WR LCR - Line Control Reg */ - u8 mcr; /* WR MCR - Modem Control Reg */ - u8 lsr; /* WR LSR - Line Status Reg */ - u8 msr; /* WR MSR - Modem Status Reg */ - u8 spr; /* WR SPR - Scratch Pad Reg */ + u8 txrx; + u8 ier; + u8 isr_fcr; + u8 lcr; + u8 mcr; + u8 lsr; + u8 msr; + u8 spr; }; /* Where to read the interrupt register (8bits) */ @@ -51,18 +51,15 @@ struct cls_uart_struct { #define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF -#define UART_16654_FCR_TXTRIGGER_8 0x0 #define UART_16654_FCR_TXTRIGGER_16 0x10 -#define UART_16654_FCR_TXTRIGGER_32 0x20 -#define UART_16654_FCR_TXTRIGGER_56 0x30 - -#define UART_16654_FCR_RXTRIGGER_8 0x0 #define UART_16654_FCR_RXTRIGGER_16 0x40 #define UART_16654_FCR_RXTRIGGER_56 0x80 -#define UART_16654_FCR_RXTRIGGER_60 0xC0 -#define UART_IIR_CTSRTS 0x20 /* Received CTS/RTS change of state */ -#define UART_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */ +/* Received CTS/RTS change of state */ +#define UART_IIR_CTSRTS 0x20 + +/* Receiver data TIMEOUT */ +#define UART_IIR_RDI_TIMEOUT 0x0C /* * These are the EXTENDED definitions for the Exar 654's Interrupt @@ -73,10 +70,6 @@ struct cls_uart_struct { #define UART_EXAR654_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */ #define UART_EXAR654_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */ #define UART_EXAR654_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */ - -#define UART_EXAR654_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */ -#define UART_EXAR654_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */ - #define UART_EXAR654_IER_XOFF 0x20 /* Xoff Interrupt Enable */ #define UART_EXAR654_IER_RTSDTR 0x40 /* Output Interrupt Enable */ #define UART_EXAR654_IER_CTSDSR 0x80 /* Input Interrupt Enable */ |