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-rw-r--r--drivers/staging/et131x/et1310_phy.h941
1 files changed, 458 insertions, 483 deletions
diff --git a/drivers/staging/et131x/et1310_phy.h b/drivers/staging/et131x/et1310_phy.h
index d624cbbadbd7..080656c6142c 100644
--- a/drivers/staging/et131x/et1310_phy.h
+++ b/drivers/staging/et131x/et1310_phy.h
@@ -2,7 +2,7 @@
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
- * Copyright © 2005 Agere Systems Inc.
+ * Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
@@ -20,7 +20,7 @@
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
- * Copyright © 2005 Agere Systems Inc.
+ * Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
@@ -41,7 +41,7 @@
*
* Disclaimer
*
- * THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
@@ -63,9 +63,6 @@
#define TRUEPHY_SUCCESS 0
#define TRUEPHY_FAILURE 1
-typedef void *TRUEPHY_HANDLE;
-typedef void *TRUEPHY_PLATFORM_HANDLE;
-typedef void *TRUEPHY_OSAL_HANDLE;
/* MI Register Addresses */
#define MI_CONTROL_REG 0
@@ -105,31 +102,31 @@ typedef void *TRUEPHY_OSAL_HANDLE;
/* PHY Register Mapping(MI) Management Interface Regs */
typedef struct _MI_REGS_t {
- u8 bmcr; // Basic mode control reg(Reg 0x00)
- u8 bmsr; // Basic mode status reg(Reg 0x01)
- u8 idr1; // Phy identifier reg 1(Reg 0x02)
- u8 idr2; // Phy identifier reg 2(Reg 0x03)
- u8 anar; // Auto-Negotiation advertisement(Reg 0x04)
- u8 anlpar; // Auto-Negotiation link Partner Ability(Reg 0x05)
- u8 aner; // Auto-Negotiation expansion reg(Reg 0x06)
- u8 annptr; // Auto-Negotiation next page transmit reg(Reg 0x07)
- u8 lpnpr; // link partner next page reg(Reg 0x08)
- u8 gcr; // Gigabit basic mode control reg(Reg 0x09)
- u8 gsr; // Gigabit basic mode status reg(Reg 0x0A)
- u8 mi_res1[4]; // Future use by MI working group(Reg 0x0B - 0x0E)
- u8 esr; // Extended status reg(Reg 0x0F)
- u8 mi_res2[3]; // Future use by MI working group(Reg 0x10 - 0x12)
- u8 loop_ctl; // Loopback Control Reg(Reg 0x13)
- u8 mi_res3; // Future use by MI working group(Reg 0x14)
- u8 mcr; // MI Control Reg(Reg 0x15)
- u8 pcr; // Configuration Reg(Reg 0x16)
- u8 phy_ctl; // PHY Control Reg(Reg 0x17)
- u8 imr; // Interrupt Mask Reg(Reg 0x18)
- u8 isr; // Interrupt Status Reg(Reg 0x19)
- u8 psr; // PHY Status Reg(Reg 0x1A)
- u8 lcr1; // LED Control 1 Reg(Reg 0x1B)
- u8 lcr2; // LED Control 2 Reg(Reg 0x1C)
- u8 mi_res4[3]; // Future use by MI working group(Reg 0x1D - 0x1F)
+ u8 bmcr; /* Basic mode control reg(Reg 0x00) */
+ u8 bmsr; /* Basic mode status reg(Reg 0x01) */
+ u8 idr1; /* Phy identifier reg 1(Reg 0x02) */
+ u8 idr2; /* Phy identifier reg 2(Reg 0x03) */
+ u8 anar; /* Auto-Negotiation advertisement(Reg 0x04) */
+ u8 anlpar; /* Auto-Negotiation link Partner Ability(Reg 0x05) */
+ u8 aner; /* Auto-Negotiation expansion reg(Reg 0x06) */
+ u8 annptr; /* Auto-Negotiation next page transmit reg(Reg 0x07) */
+ u8 lpnpr; /* link partner next page reg(Reg 0x08) */
+ u8 gcr; /* Gigabit basic mode control reg(Reg 0x09) */
+ u8 gsr; /* Gigabit basic mode status reg(Reg 0x0A) */
+ u8 mi_res1[4]; /* Future use by MI working group(Reg 0x0B - 0x0E) */
+ u8 esr; /* Extended status reg(Reg 0x0F) */
+ u8 mi_res2[3]; /* Future use by MI working group(Reg 0x10 - 0x12) */
+ u8 loop_ctl; /* Loopback Control Reg(Reg 0x13) */
+ u8 mi_res3; /* Future use by MI working group(Reg 0x14) */
+ u8 mcr; /* MI Control Reg(Reg 0x15) */
+ u8 pcr; /* Configuration Reg(Reg 0x16) */
+ u8 phy_ctl; /* PHY Control Reg(Reg 0x17) */
+ u8 imr; /* Interrupt Mask Reg(Reg 0x18) */
+ u8 isr; /* Interrupt Status Reg(Reg 0x19) */
+ u8 psr; /* PHY Status Reg(Reg 0x1A) */
+ u8 lcr1; /* LED Control 1 Reg(Reg 0x1B) */
+ u8 lcr2; /* LED Control 2 Reg(Reg 0x1C) */
+ u8 mi_res4[3]; /* Future use by MI working group(Reg 0x1D - 0x1F) */
} MI_REGS_t, *PMI_REGS_t;
/* MI Register 0: Basic mode control register */
@@ -137,29 +134,29 @@ typedef union _MI_BMCR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 reset:1; // bit 15
- u16 loopback:1; // bit 14
- u16 speed_sel:1; // bit 13
- u16 enable_autoneg:1; // bit 12
- u16 power_down:1; // bit 11
- u16 isolate:1; // bit 10
- u16 restart_autoneg:1; // bit 9
- u16 duplex_mode:1; // bit 8
- u16 col_test:1; // bit 7
- u16 speed_1000_sel:1; // bit 6
- u16 res1:6; // bits 0-5
+ u16 reset:1; /* bit 15 */
+ u16 loopback:1; /* bit 14 */
+ u16 speed_sel:1; /* bit 13 */
+ u16 enable_autoneg:1; /* bit 12 */
+ u16 power_down:1; /* bit 11 */
+ u16 isolate:1; /* bit 10 */
+ u16 restart_autoneg:1; /* bit 9 */
+ u16 duplex_mode:1; /* bit 8 */
+ u16 col_test:1; /* bit 7 */
+ u16 speed_1000_sel:1; /* bit 6 */
+ u16 res1:6; /* bits 0-5 */
#else
- u16 res1:6; // bits 0-5
- u16 speed_1000_sel:1; // bit 6
- u16 col_test:1; // bit 7
- u16 duplex_mode:1; // bit 8
- u16 restart_autoneg:1; // bit 9
- u16 isolate:1; // bit 10
- u16 power_down:1; // bit 11
- u16 enable_autoneg:1; // bit 12
- u16 speed_sel:1; // bit 13
- u16 loopback:1; // bit 14
- u16 reset:1; // bit 15
+ u16 res1:6; /* bits 0-5 */
+ u16 speed_1000_sel:1; /* bit 6 */
+ u16 col_test:1; /* bit 7 */
+ u16 duplex_mode:1; /* bit 8 */
+ u16 restart_autoneg:1; /* bit 9 */
+ u16 isolate:1; /* bit 10 */
+ u16 power_down:1; /* bit 11 */
+ u16 enable_autoneg:1; /* bit 12 */
+ u16 speed_sel:1; /* bit 13 */
+ u16 loopback:1; /* bit 14 */
+ u16 reset:1; /* bit 15 */
#endif
} bits;
} MI_BMCR_t, *PMI_BMCR_t;
@@ -169,39 +166,39 @@ typedef union _MI_BMSR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 link_100T4:1; // bit 15
- u16 link_100fdx:1; // bit 14
- u16 link_100hdx:1; // bit 13
- u16 link_10fdx:1; // bit 12
- u16 link_10hdx:1; // bit 11
- u16 link_100T2fdx:1; // bit 10
- u16 link_100T2hdx:1; // bit 9
- u16 extend_status:1; // bit 8
- u16 res1:1; // bit 7
- u16 preamble_supress:1; // bit 6
- u16 auto_neg_complete:1; // bit 5
- u16 remote_fault:1; // bit 4
- u16 auto_neg_able:1; // bit 3
- u16 link_status:1; // bit 2
- u16 jabber_detect:1; // bit 1
- u16 ext_cap:1; // bit 0
+ u16 link_100T4:1; /* bit 15 */
+ u16 link_100fdx:1; /* bit 14 */
+ u16 link_100hdx:1; /* bit 13 */
+ u16 link_10fdx:1; /* bit 12 */
+ u16 link_10hdx:1; /* bit 11 */
+ u16 link_100T2fdx:1; /* bit 10 */
+ u16 link_100T2hdx:1; /* bit 9 */
+ u16 extend_status:1; /* bit 8 */
+ u16 res1:1; /* bit 7 */
+ u16 preamble_supress:1; /* bit 6 */
+ u16 auto_neg_complete:1; /* bit 5 */
+ u16 remote_fault:1; /* bit 4 */
+ u16 auto_neg_able:1; /* bit 3 */
+ u16 link_status:1; /* bit 2 */
+ u16 jabber_detect:1; /* bit 1 */
+ u16 ext_cap:1; /* bit 0 */
#else
- u16 ext_cap:1; // bit 0
- u16 jabber_detect:1; // bit 1
- u16 link_status:1; // bit 2
- u16 auto_neg_able:1; // bit 3
- u16 remote_fault:1; // bit 4
- u16 auto_neg_complete:1; // bit 5
- u16 preamble_supress:1; // bit 6
- u16 res1:1; // bit 7
- u16 extend_status:1; // bit 8
- u16 link_100T2hdx:1; // bit 9
- u16 link_100T2fdx:1; // bit 10
- u16 link_10hdx:1; // bit 11
- u16 link_10fdx:1; // bit 12
- u16 link_100hdx:1; // bit 13
- u16 link_100fdx:1; // bit 14
- u16 link_100T4:1; // bit 15
+ u16 ext_cap:1; /* bit 0 */
+ u16 jabber_detect:1; /* bit 1 */
+ u16 link_status:1; /* bit 2 */
+ u16 auto_neg_able:1; /* bit 3 */
+ u16 remote_fault:1; /* bit 4 */
+ u16 auto_neg_complete:1; /* bit 5 */
+ u16 preamble_supress:1; /* bit 6 */
+ u16 res1:1; /* bit 7 */
+ u16 extend_status:1; /* bit 8 */
+ u16 link_100T2hdx:1; /* bit 9 */
+ u16 link_100T2fdx:1; /* bit 10 */
+ u16 link_10hdx:1; /* bit 11 */
+ u16 link_10fdx:1; /* bit 12 */
+ u16 link_100hdx:1; /* bit 13 */
+ u16 link_100fdx:1; /* bit 14 */
+ u16 link_100T4:1; /* bit 15 */
#endif
} bits;
} MI_BMSR_t, *PMI_BMSR_t;
@@ -210,7 +207,7 @@ typedef union _MI_BMSR_t {
typedef union _MI_IDR1_t {
u16 value;
struct {
- u16 ieee_address:16; // 0x0282 default(bits 0-15)
+ u16 ieee_address:16; /* 0x0282 default(bits 0-15) */
} bits;
} MI_IDR1_t, *PMI_IDR1_t;
@@ -219,13 +216,13 @@ typedef union _MI_IDR2_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 ieee_address:6; // 111100 default(bits 10-15)
- u16 model_no:6; // 000001 default(bits 4-9)
- u16 rev_no:4; // 0010 default(bits 0-3)
+ u16 ieee_address:6; /* 111100 default(bits 10-15) */
+ u16 model_no:6; /* 000001 default(bits 4-9) */
+ u16 rev_no:4; /* 0010 default(bits 0-3) */
#else
- u16 rev_no:4; // 0010 default(bits 0-3)
- u16 model_no:6; // 000001 default(bits 4-9)
- u16 ieee_address:6; // 111100 default(bits 10-15)
+ u16 rev_no:4; /* 0010 default(bits 0-3) */
+ u16 model_no:6; /* 000001 default(bits 4-9) */
+ u16 ieee_address:6; /* 111100 default(bits 10-15) */
#endif
} bits;
} MI_IDR2_t, *PMI_IDR2_t;
@@ -235,31 +232,31 @@ typedef union _MI_ANAR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 np_indication:1; // bit 15
- u16 res2:1; // bit 14
- u16 remote_fault:1; // bit 13
- u16 res1:1; // bit 12
- u16 cap_asmpause:1; // bit 11
- u16 cap_pause:1; // bit 10
- u16 cap_100T4:1; // bit 9
- u16 cap_100fdx:1; // bit 8
- u16 cap_100hdx:1; // bit 7
- u16 cap_10fdx:1; // bit 6
- u16 cap_10hdx:1; // bit 5
- u16 selector:5; // bits 0-4
+ u16 np_indication:1; /* bit 15 */
+ u16 res2:1; /* bit 14 */
+ u16 remote_fault:1; /* bit 13 */
+ u16 res1:1; /* bit 12 */
+ u16 cap_asmpause:1; /* bit 11 */
+ u16 cap_pause:1; /* bit 10 */
+ u16 cap_100T4:1; /* bit 9 */
+ u16 cap_100fdx:1; /* bit 8 */
+ u16 cap_100hdx:1; /* bit 7 */
+ u16 cap_10fdx:1; /* bit 6 */
+ u16 cap_10hdx:1; /* bit 5 */
+ u16 selector:5; /* bits 0-4 */
#else
- u16 selector:5; // bits 0-4
- u16 cap_10hdx:1; // bit 5
- u16 cap_10fdx:1; // bit 6
- u16 cap_100hdx:1; // bit 7
- u16 cap_100fdx:1; // bit 8
- u16 cap_100T4:1; // bit 9
- u16 cap_pause:1; // bit 10
- u16 cap_asmpause:1; // bit 11
- u16 res1:1; // bit 12
- u16 remote_fault:1; // bit 13
- u16 res2:1; // bit 14
- u16 np_indication:1; // bit 15
+ u16 selector:5; /* bits 0-4 */
+ u16 cap_10hdx:1; /* bit 5 */
+ u16 cap_10fdx:1; /* bit 6 */
+ u16 cap_100hdx:1; /* bit 7 */
+ u16 cap_100fdx:1; /* bit 8 */
+ u16 cap_100T4:1; /* bit 9 */
+ u16 cap_pause:1; /* bit 10 */
+ u16 cap_asmpause:1; /* bit 11 */
+ u16 res1:1; /* bit 12 */
+ u16 remote_fault:1; /* bit 13 */
+ u16 res2:1; /* bit 14 */
+ u16 np_indication:1; /* bit 15 */
#endif
} bits;
} MI_ANAR_t, *PMI_ANAR_t;
@@ -269,31 +266,31 @@ typedef struct _MI_ANLPAR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 np_indication:1; // bit 15
- u16 acknowledge:1; // bit 14
- u16 remote_fault:1; // bit 13
- u16 res1:1; // bit 12
- u16 cap_asmpause:1; // bit 11
- u16 cap_pause:1; // bit 10
- u16 cap_100T4:1; // bit 9
- u16 cap_100fdx:1; // bit 8
- u16 cap_100hdx:1; // bit 7
- u16 cap_10fdx:1; // bit 6
- u16 cap_10hdx:1; // bit 5
- u16 selector:5; // bits 0-4
+ u16 np_indication:1; /* bit 15 */
+ u16 acknowledge:1; /* bit 14 */
+ u16 remote_fault:1; /* bit 13 */
+ u16 res1:1; /* bit 12 */
+ u16 cap_asmpause:1; /* bit 11 */
+ u16 cap_pause:1; /* bit 10 */
+ u16 cap_100T4:1; /* bit 9 */
+ u16 cap_100fdx:1; /* bit 8 */
+ u16 cap_100hdx:1; /* bit 7 */
+ u16 cap_10fdx:1; /* bit 6 */
+ u16 cap_10hdx:1; /* bit 5 */
+ u16 selector:5; /* bits 0-4 */
#else
- u16 selector:5; // bits 0-4
- u16 cap_10hdx:1; // bit 5
- u16 cap_10fdx:1; // bit 6
- u16 cap_100hdx:1; // bit 7
- u16 cap_100fdx:1; // bit 8
- u16 cap_100T4:1; // bit 9
- u16 cap_pause:1; // bit 10
- u16 cap_asmpause:1; // bit 11
- u16 res1:1; // bit 12
- u16 remote_fault:1; // bit 13
- u16 acknowledge:1; // bit 14
- u16 np_indication:1; // bit 15
+ u16 selector:5; /* bits 0-4 */
+ u16 cap_10hdx:1; /* bit 5 */
+ u16 cap_10fdx:1; /* bit 6 */
+ u16 cap_100hdx:1; /* bit 7 */
+ u16 cap_100fdx:1; /* bit 8 */
+ u16 cap_100T4:1; /* bit 9 */
+ u16 cap_pause:1; /* bit 10 */
+ u16 cap_asmpause:1; /* bit 11 */
+ u16 res1:1; /* bit 12 */
+ u16 remote_fault:1; /* bit 13 */
+ u16 acknowledge:1; /* bit 14 */
+ u16 np_indication:1; /* bit 15 */
#endif
} bits;
} MI_ANLPAR_t, *PMI_ANLPAR_t;
@@ -303,19 +300,19 @@ typedef union _MI_ANER_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 res:11; // bits 5-15
- u16 pdf:1; // bit 4
- u16 lp_np_able:1; // bit 3
- u16 np_able:1; // bit 2
- u16 page_rx:1; // bit 1
- u16 lp_an_able:1; // bit 0
+ u16 res:11; /* bits 5-15 */
+ u16 pdf:1; /* bit 4 */
+ u16 lp_np_able:1; /* bit 3 */
+ u16 np_able:1; /* bit 2 */
+ u16 page_rx:1; /* bit 1 */
+ u16 lp_an_able:1; /* bit 0 */
#else
- u16 lp_an_able:1; // bit 0
- u16 page_rx:1; // bit 1
- u16 np_able:1; // bit 2
- u16 lp_np_able:1; // bit 3
- u16 pdf:1; // bit 4
- u16 res:11; // bits 5-15
+ u16 lp_an_able:1; /* bit 0 */
+ u16 page_rx:1; /* bit 1 */
+ u16 np_able:1; /* bit 2 */
+ u16 lp_np_able:1; /* bit 3 */
+ u16 pdf:1; /* bit 4 */
+ u16 res:11; /* bits 5-15 */
#endif
} bits;
} MI_ANER_t, *PMI_ANER_t;
@@ -325,19 +322,19 @@ typedef union _MI_ANNPTR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 np:1; // bit 15
- u16 res1:1; // bit 14
- u16 msg_page:1; // bit 13
- u16 ack2:1; // bit 12
- u16 toggle:1; // bit 11
- u16 msg:11; // bits 0-10
+ u16 np:1; /* bit 15 */
+ u16 res1:1; /* bit 14 */
+ u16 msg_page:1; /* bit 13 */
+ u16 ack2:1; /* bit 12 */
+ u16 toggle:1; /* bit 11 */
+ u16 msg:11; /* bits 0-10 */
#else
- u16 msg:11; // bits 0-10
- u16 toggle:1; // bit 11
- u16 ack2:1; // bit 12
- u16 msg_page:1; // bit 13
- u16 res1:1; // bit 14
- u16 np:1; // bit 15
+ u16 msg:11; /* bits 0-10 */
+ u16 toggle:1; /* bit 11 */
+ u16 ack2:1; /* bit 12 */
+ u16 msg_page:1; /* bit 13 */
+ u16 res1:1; /* bit 14 */
+ u16 np:1; /* bit 15 */
#endif
} bits;
} MI_ANNPTR_t, *PMI_ANNPTR_t;
@@ -347,19 +344,19 @@ typedef union _MI_LPNPR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 np:1; // bit 15
- u16 ack:1; // bit 14
- u16 msg_page:1; // bit 13
- u16 ack2:1; // bit 12
- u16 toggle:1; // bit 11
- u16 msg:11; // bits 0-10
+ u16 np:1; /* bit 15 */
+ u16 ack:1; /* bit 14 */
+ u16 msg_page:1; /* bit 13 */
+ u16 ack2:1; /* bit 12 */
+ u16 toggle:1; /* bit 11 */
+ u16 msg:11; /* bits 0-10 */
#else
- u16 msg:11; // bits 0-10
- u16 toggle:1; // bit 11
- u16 ack2:1; // bit 12
- u16 msg_page:1; // bit 13
- u16 ack:1; // bit 14
- u16 np:1; // bit 15
+ u16 msg:11; /* bits 0-10 */
+ u16 toggle:1; /* bit 11 */
+ u16 ack2:1; /* bit 12 */
+ u16 msg_page:1; /* bit 13 */
+ u16 ack:1; /* bit 14 */
+ u16 np:1; /* bit 15 */
#endif
} bits;
} MI_LPNPR_t, *PMI_LPNPR_t;
@@ -369,21 +366,21 @@ typedef union _MI_GCR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 test_mode:3; // bits 13-15
- u16 ms_config_en:1; // bit 12
- u16 ms_value:1; // bit 11
- u16 port_type:1; // bit 10
- u16 link_1000fdx:1; // bit 9
- u16 link_1000hdx:1; // bit 8
- u16 res:8; // bit 0-7
+ u16 test_mode:3; /* bits 13-15 */
+ u16 ms_config_en:1; /* bit 12 */
+ u16 ms_value:1; /* bit 11 */
+ u16 port_type:1; /* bit 10 */
+ u16 link_1000fdx:1; /* bit 9 */
+ u16 link_1000hdx:1; /* bit 8 */
+ u16 res:8; /* bit 0-7 */
#else
- u16 res:8; // bit 0-7
- u16 link_1000hdx:1; // bit 8
- u16 link_1000fdx:1; // bit 9
- u16 port_type:1; // bit 10
- u16 ms_value:1; // bit 11
- u16 ms_config_en:1; // bit 12
- u16 test_mode:3; // bits 13-15
+ u16 res:8; /* bit 0-7 */
+ u16 link_1000hdx:1; /* bit 8 */
+ u16 link_1000fdx:1; /* bit 9 */
+ u16 port_type:1; /* bit 10 */
+ u16 ms_value:1; /* bit 11 */
+ u16 ms_config_en:1; /* bit 12 */
+ u16 test_mode:3; /* bits 13-15 */
#endif
} bits;
} MI_GCR_t, *PMI_GCR_t;
@@ -393,23 +390,23 @@ typedef union _MI_GSR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 ms_config_fault:1; // bit 15
- u16 ms_resolve:1; // bit 14
- u16 local_rx_status:1; // bit 13
- u16 remote_rx_status:1; // bit 12
- u16 link_1000fdx:1; // bit 11
- u16 link_1000hdx:1; // bit 10
- u16 res:2; // bits 8-9
- u16 idle_err_cnt:8; // bits 0-7
+ u16 ms_config_fault:1; /* bit 15 */
+ u16 ms_resolve:1; /* bit 14 */
+ u16 local_rx_status:1; /* bit 13 */
+ u16 remote_rx_status:1; /* bit 12 */
+ u16 link_1000fdx:1; /* bit 11 */
+ u16 link_1000hdx:1; /* bit 10 */
+ u16 res:2; /* bits 8-9 */
+ u16 idle_err_cnt:8; /* bits 0-7 */
#else
- u16 idle_err_cnt:8; // bits 0-7
- u16 res:2; // bits 8-9
- u16 link_1000hdx:1; // bit 10
- u16 link_1000fdx:1; // bit 11
- u16 remote_rx_status:1; // bit 12
- u16 local_rx_status:1; // bit 13
- u16 ms_resolve:1; // bit 14
- u16 ms_config_fault:1; // bit 15
+ u16 idle_err_cnt:8; /* bits 0-7 */
+ u16 res:2; /* bits 8-9 */
+ u16 link_1000hdx:1; /* bit 10 */
+ u16 link_1000fdx:1; /* bit 11 */
+ u16 remote_rx_status:1; /* bit 12 */
+ u16 local_rx_status:1; /* bit 13 */
+ u16 ms_resolve:1; /* bit 14 */
+ u16 ms_config_fault:1; /* bit 15 */
#endif
} bits;
} MI_GSR_t, *PMI_GSR_t;
@@ -419,39 +416,39 @@ typedef union _MI_RES_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 res15:1; // bit 15
- u16 res14:1; // bit 14
- u16 res13:1; // bit 13
- u16 res12:1; // bit 12
- u16 res11:1; // bit 11
- u16 res10:1; // bit 10
- u16 res9:1; // bit 9
- u16 res8:1; // bit 8
- u16 res7:1; // bit 7
- u16 res6:1; // bit 6
- u16 res5:1; // bit 5
- u16 res4:1; // bit 4
- u16 res3:1; // bit 3
- u16 res2:1; // bit 2
- u16 res1:1; // bit 1
- u16 res0:1; // bit 0
+ u16 res15:1; /* bit 15 */
+ u16 res14:1; /* bit 14 */
+ u16 res13:1; /* bit 13 */
+ u16 res12:1; /* bit 12 */
+ u16 res11:1; /* bit 11 */
+ u16 res10:1; /* bit 10 */
+ u16 res9:1; /* bit 9 */
+ u16 res8:1; /* bit 8 */
+ u16 res7:1; /* bit 7 */
+ u16 res6:1; /* bit 6 */
+ u16 res5:1; /* bit 5 */
+ u16 res4:1; /* bit 4 */
+ u16 res3:1; /* bit 3 */
+ u16 res2:1; /* bit 2 */
+ u16 res1:1; /* bit 1 */
+ u16 res0:1; /* bit 0 */
#else
- u16 res0:1; // bit 0
- u16 res1:1; // bit 1
- u16 res2:1; // bit 2
- u16 res3:1; // bit 3
- u16 res4:1; // bit 4
- u16 res5:1; // bit 5
- u16 res6:1; // bit 6
- u16 res7:1; // bit 7
- u16 res8:1; // bit 8
- u16 res9:1; // bit 9
- u16 res10:1; // bit 10
- u16 res11:1; // bit 11
- u16 res12:1; // bit 12
- u16 res13:1; // bit 13
- u16 res14:1; // bit 14
- u16 res15:1; // bit 15
+ u16 res0:1; /* bit 0 */
+ u16 res1:1; /* bit 1 */
+ u16 res2:1; /* bit 2 */
+ u16 res3:1; /* bit 3 */
+ u16 res4:1; /* bit 4 */
+ u16 res5:1; /* bit 5 */
+ u16 res6:1; /* bit 6 */
+ u16 res7:1; /* bit 7 */
+ u16 res8:1; /* bit 8 */
+ u16 res9:1; /* bit 9 */
+ u16 res10:1; /* bit 10 */
+ u16 res11:1; /* bit 11 */
+ u16 res12:1; /* bit 12 */
+ u16 res13:1; /* bit 13 */
+ u16 res14:1; /* bit 14 */
+ u16 res15:1; /* bit 15 */
#endif
} bits;
} MI_RES_t, *PMI_RES_t;
@@ -461,17 +458,17 @@ typedef union _MI_ESR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 link_1000Xfdx:1; // bit 15
- u16 link_1000Xhdx:1; // bit 14
- u16 link_1000fdx:1; // bit 13
- u16 link_1000hdx:1; // bit 12
- u16 res:12; // bit 0-11
+ u16 link_1000Xfdx:1; /* bit 15 */
+ u16 link_1000Xhdx:1; /* bit 14 */
+ u16 link_1000fdx:1; /* bit 13 */
+ u16 link_1000hdx:1; /* bit 12 */
+ u16 res:12; /* bit 0-11 */
#else
- u16 res:12; // bit 0-11
- u16 link_1000hdx:1; // bit 12
- u16 link_1000fdx:1; // bit 13
- u16 link_1000Xhdx:1; // bit 14
- u16 link_1000Xfdx:1; // bit 15
+ u16 res:12; /* bit 0-11 */
+ u16 link_1000hdx:1; /* bit 12 */
+ u16 link_1000fdx:1; /* bit 13 */
+ u16 link_1000Xhdx:1; /* bit 14 */
+ u16 link_1000Xfdx:1; /* bit 15 */
#endif
} bits;
} MI_ESR_t, *PMI_ESR_t;
@@ -483,21 +480,21 @@ typedef union _MI_LCR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 mii_en:1; // bit 15
- u16 pcs_en:1; // bit 14
- u16 pmd_en:1; // bit 13
- u16 all_digital_en:1; // bit 12
- u16 replica_en:1; // bit 11
- u16 line_driver_en:1; // bit 10
- u16 res:10; // bit 0-9
+ u16 mii_en:1; /* bit 15 */
+ u16 pcs_en:1; /* bit 14 */
+ u16 pmd_en:1; /* bit 13 */
+ u16 all_digital_en:1; /* bit 12 */
+ u16 replica_en:1; /* bit 11 */
+ u16 line_driver_en:1; /* bit 10 */
+ u16 res:10; /* bit 0-9 */
#else
- u16 res:10; // bit 0-9
- u16 line_driver_en:1; // bit 10
- u16 replica_en:1; // bit 11
- u16 all_digital_en:1; // bit 12
- u16 pmd_en:1; // bit 13
- u16 pcs_en:1; // bit 14
- u16 mii_en:1; // bit 15
+ u16 res:10; /* bit 0-9 */
+ u16 line_driver_en:1; /* bit 10 */
+ u16 replica_en:1; /* bit 11 */
+ u16 all_digital_en:1; /* bit 12 */
+ u16 pmd_en:1; /* bit 13 */
+ u16 pcs_en:1; /* bit 14 */
+ u16 mii_en:1; /* bit 15 */
#endif
} bits;
} MI_LCR_t, *PMI_LCR_t;
@@ -509,19 +506,19 @@ typedef union _MI_MICR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 res1:5; // bits 11-15
- u16 mi_error_count:7; // bits 4-10
- u16 res2:1; // bit 3
- u16 ignore_10g_fr:1; // bit 2
- u16 res3:1; // bit 1
- u16 preamble_supress_en:1; // bit 0
+ u16 res1:5; /* bits 11-15 */
+ u16 mi_error_count:7; /* bits 4-10 */
+ u16 res2:1; /* bit 3 */
+ u16 ignore_10g_fr:1; /* bit 2 */
+ u16 res3:1; /* bit 1 */
+ u16 preamble_supress_en:1; /* bit 0 */
#else
- u16 preamble_supress_en:1; // bit 0
- u16 res3:1; // bit 1
- u16 ignore_10g_fr:1; // bit 2
- u16 res2:1; // bit 3
- u16 mi_error_count:7; // bits 4-10
- u16 res1:5; // bits 11-15
+ u16 preamble_supress_en:1; /* bit 0 */
+ u16 res3:1; /* bit 1 */
+ u16 ignore_10g_fr:1; /* bit 2 */
+ u16 res2:1; /* bit 3 */
+ u16 mi_error_count:7; /* bits 4-10 */
+ u16 res1:5; /* bits 11-15 */
#endif
} bits;
} MI_MICR_t, *PMI_MICR_t;
@@ -531,31 +528,31 @@ typedef union _MI_PHY_CONFIG_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 crs_tx_en:1; // bit 15
- u16 res1:1; // bit 14
- u16 tx_fifo_depth:2; // bits 12-13
- u16 speed_downshift:2; // bits 10-11
- u16 pbi_detect:1; // bit 9
- u16 tbi_rate:1; // bit 8
- u16 alternate_np:1; // bit 7
- u16 group_mdio_en:1; // bit 6
- u16 tx_clock_en:1; // bit 5
- u16 sys_clock_en:1; // bit 4
- u16 res2:1; // bit 3
- u16 mac_if_mode:3; // bits 0-2
+ u16 crs_tx_en:1; /* bit 15 */
+ u16 res1:1; /* bit 14 */
+ u16 tx_fifo_depth:2; /* bits 12-13 */
+ u16 speed_downshift:2; /* bits 10-11 */
+ u16 pbi_detect:1; /* bit 9 */
+ u16 tbi_rate:1; /* bit 8 */
+ u16 alternate_np:1; /* bit 7 */
+ u16 group_mdio_en:1; /* bit 6 */
+ u16 tx_clock_en:1; /* bit 5 */
+ u16 sys_clock_en:1; /* bit 4 */
+ u16 res2:1; /* bit 3 */
+ u16 mac_if_mode:3; /* bits 0-2 */
#else
- u16 mac_if_mode:3; // bits 0-2
- u16 res2:1; // bit 3
- u16 sys_clock_en:1; // bit 4
- u16 tx_clock_en:1; // bit 5
- u16 group_mdio_en:1; // bit 6
- u16 alternate_np:1; // bit 7
- u16 tbi_rate:1; // bit 8
- u16 pbi_detect:1; // bit 9
- u16 speed_downshift:2; // bits 10-11
- u16 tx_fifo_depth:2; // bits 12-13
- u16 res1:1; // bit 14
- u16 crs_tx_en:1; // bit 15
+ u16 mac_if_mode:3; /* bits 0-2 */
+ u16 res2:1; /* bit 3 */
+ u16 sys_clock_en:1; /* bit 4 */
+ u16 tx_clock_en:1; /* bit 5 */
+ u16 group_mdio_en:1; /* bit 6 */
+ u16 alternate_np:1; /* bit 7 */
+ u16 tbi_rate:1; /* bit 8 */
+ u16 pbi_detect:1; /* bit 9 */
+ u16 speed_downshift:2; /* bits 10-11 */
+ u16 tx_fifo_depth:2; /* bits 12-13 */
+ u16 res1:1; /* bit 14 */
+ u16 crs_tx_en:1; /* bit 15 */
#endif
} bits;
} MI_PHY_CONFIG_t, *PMI_PHY_CONFIG_t;
@@ -565,29 +562,29 @@ typedef union _MI_PHY_CONTROL_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 res1:1; // bit 15
- u16 tdr_en:1; // bit 14
- u16 res2:1; // bit 13
- u16 downshift_attempts:2; // bits 11-12
- u16 res3:5; // bit 6-10
- u16 jabber_10baseT:1; // bit 5
- u16 sqe_10baseT:1; // bit 4
- u16 tp_loopback_10baseT:1; // bit 3
- u16 preamble_gen_en:1; // bit 2
- u16 res4:1; // bit 1
- u16 force_int:1; // bit 0
+ u16 res1:1; /* bit 15 */
+ u16 tdr_en:1; /* bit 14 */
+ u16 res2:1; /* bit 13 */
+ u16 downshift_attempts:2; /* bits 11-12 */
+ u16 res3:5; /* bit 6-10 */
+ u16 jabber_10baseT:1; /* bit 5 */
+ u16 sqe_10baseT:1; /* bit 4 */
+ u16 tp_loopback_10baseT:1; /* bit 3 */
+ u16 preamble_gen_en:1; /* bit 2 */
+ u16 res4:1; /* bit 1 */
+ u16 force_int:1; /* bit 0 */
#else
- u16 force_int:1; // bit 0
- u16 res4:1; // bit 1
- u16 preamble_gen_en:1; // bit 2
- u16 tp_loopback_10baseT:1; // bit 3
- u16 sqe_10baseT:1; // bit 4
- u16 jabber_10baseT:1; // bit 5
- u16 res3:5; // bit 6-10
- u16 downshift_attempts:2; // bits 11-12
- u16 res2:1; // bit 13
- u16 tdr_en:1; // bit 14
- u16 res1:1; // bit 15
+ u16 force_int:1; /* bit 0 */
+ u16 res4:1; /* bit 1 */
+ u16 preamble_gen_en:1; /* bit 2 */
+ u16 tp_loopback_10baseT:1; /* bit 3 */
+ u16 sqe_10baseT:1; /* bit 4 */
+ u16 jabber_10baseT:1; /* bit 5 */
+ u16 res3:5; /* bit 6-10 */
+ u16 downshift_attempts:2; /* bits 11-12 */
+ u16 res2:1; /* bit 13 */
+ u16 tdr_en:1; /* bit 14 */
+ u16 res1:1; /* bit 15 */
#endif
} bits;
} MI_PHY_CONTROL_t, *PMI_PHY_CONTROL_t;
@@ -597,29 +594,29 @@ typedef union _MI_IMR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 res1:6; // bits 10-15
- u16 mdio_sync_lost:1; // bit 9
- u16 autoneg_status:1; // bit 8
- u16 hi_bit_err:1; // bit 7
- u16 np_rx:1; // bit 6
- u16 err_counter_full:1; // bit 5
- u16 fifo_over_underflow:1; // bit 4
- u16 rx_status:1; // bit 3
- u16 link_status:1; // bit 2
- u16 automatic_speed:1; // bit 1
- u16 int_en:1; // bit 0
+ u16 res1:6; /* bits 10-15 */
+ u16 mdio_sync_lost:1; /* bit 9 */
+ u16 autoneg_status:1; /* bit 8 */
+ u16 hi_bit_err:1; /* bit 7 */
+ u16 np_rx:1; /* bit 6 */
+ u16 err_counter_full:1; /* bit 5 */
+ u16 fifo_over_underflow:1; /* bit 4 */
+ u16 rx_status:1; /* bit 3 */
+ u16 link_status:1; /* bit 2 */
+ u16 automatic_speed:1; /* bit 1 */
+ u16 int_en:1; /* bit 0 */
#else
- u16 int_en:1; // bit 0
- u16 automatic_speed:1; // bit 1
- u16 link_status:1; // bit 2
- u16 rx_status:1; // bit 3
- u16 fifo_over_underflow:1; // bit 4
- u16 err_counter_full:1; // bit 5
- u16 np_rx:1; // bit 6
- u16 hi_bit_err:1; // bit 7
- u16 autoneg_status:1; // bit 8
- u16 mdio_sync_lost:1; // bit 9
- u16 res1:6; // bits 10-15
+ u16 int_en:1; /* bit 0 */
+ u16 automatic_speed:1; /* bit 1 */
+ u16 link_status:1; /* bit 2 */
+ u16 rx_status:1; /* bit 3 */
+ u16 fifo_over_underflow:1; /* bit 4 */
+ u16 err_counter_full:1; /* bit 5 */
+ u16 np_rx:1; /* bit 6 */
+ u16 hi_bit_err:1; /* bit 7 */
+ u16 autoneg_status:1; /* bit 8 */
+ u16 mdio_sync_lost:1; /* bit 9 */
+ u16 res1:6; /* bits 10-15 */
#endif
} bits;
} MI_IMR_t, *PMI_IMR_t;
@@ -629,29 +626,29 @@ typedef union _MI_ISR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 res1:6; // bits 10-15
- u16 mdio_sync_lost:1; // bit 9
- u16 autoneg_status:1; // bit 8
- u16 hi_bit_err:1; // bit 7
- u16 np_rx:1; // bit 6
- u16 err_counter_full:1; // bit 5
- u16 fifo_over_underflow:1; // bit 4
- u16 rx_status:1; // bit 3
- u16 link_status:1; // bit 2
- u16 automatic_speed:1; // bit 1
- u16 int_en:1; // bit 0
+ u16 res1:6; /* bits 10-15 */
+ u16 mdio_sync_lost:1; /* bit 9 */
+ u16 autoneg_status:1; /* bit 8 */
+ u16 hi_bit_err:1; /* bit 7 */
+ u16 np_rx:1; /* bit 6 */
+ u16 err_counter_full:1; /* bit 5 */
+ u16 fifo_over_underflow:1; /* bit 4 */
+ u16 rx_status:1; /* bit 3 */
+ u16 link_status:1; /* bit 2 */
+ u16 automatic_speed:1; /* bit 1 */
+ u16 int_en:1; /* bit 0 */
#else
- u16 int_en:1; // bit 0
- u16 automatic_speed:1; // bit 1
- u16 link_status:1; // bit 2
- u16 rx_status:1; // bit 3
- u16 fifo_over_underflow:1; // bit 4
- u16 err_counter_full:1; // bit 5
- u16 np_rx:1; // bit 6
- u16 hi_bit_err:1; // bit 7
- u16 autoneg_status:1; // bit 8
- u16 mdio_sync_lost:1; // bit 9
- u16 res1:6; // bits 10-15
+ u16 int_en:1; /* bit 0 */
+ u16 automatic_speed:1; /* bit 1 */
+ u16 link_status:1; /* bit 2 */
+ u16 rx_status:1; /* bit 3 */
+ u16 fifo_over_underflow:1; /* bit 4 */
+ u16 err_counter_full:1; /* bit 5 */
+ u16 np_rx:1; /* bit 6 */
+ u16 hi_bit_err:1; /* bit 7 */
+ u16 autoneg_status:1; /* bit 8 */
+ u16 mdio_sync_lost:1; /* bit 9 */
+ u16 res1:6; /* bits 10-15 */
#endif
} bits;
} MI_ISR_t, *PMI_ISR_t;
@@ -661,35 +658,35 @@ typedef union _MI_PSR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 res1:1; // bit 15
- u16 autoneg_fault:2; // bit 13-14
- u16 autoneg_status:1; // bit 12
- u16 mdi_x_status:1; // bit 11
- u16 polarity_status:1; // bit 10
- u16 speed_status:2; // bits 8-9
- u16 duplex_status:1; // bit 7
- u16 link_status:1; // bit 6
- u16 tx_status:1; // bit 5
- u16 rx_status:1; // bit 4
- u16 collision_status:1; // bit 3
- u16 autoneg_en:1; // bit 2
- u16 pause_en:1; // bit 1
- u16 asymmetric_dir:1; // bit 0
+ u16 res1:1; /* bit 15 */
+ u16 autoneg_fault:2; /* bit 13-14 */
+ u16 autoneg_status:1; /* bit 12 */
+ u16 mdi_x_status:1; /* bit 11 */
+ u16 polarity_status:1; /* bit 10 */
+ u16 speed_status:2; /* bits 8-9 */
+ u16 duplex_status:1; /* bit 7 */
+ u16 link_status:1; /* bit 6 */
+ u16 tx_status:1; /* bit 5 */
+ u16 rx_status:1; /* bit 4 */
+ u16 collision_status:1; /* bit 3 */
+ u16 autoneg_en:1; /* bit 2 */
+ u16 pause_en:1; /* bit 1 */
+ u16 asymmetric_dir:1; /* bit 0 */
#else
- u16 asymmetric_dir:1; // bit 0
- u16 pause_en:1; // bit 1
- u16 autoneg_en:1; // bit 2
- u16 collision_status:1; // bit 3
- u16 rx_status:1; // bit 4
- u16 tx_status:1; // bit 5
- u16 link_status:1; // bit 6
- u16 duplex_status:1; // bit 7
- u16 speed_status:2; // bits 8-9
- u16 polarity_status:1; // bit 10
- u16 mdi_x_status:1; // bit 11
- u16 autoneg_status:1; // bit 12
- u16 autoneg_fault:2; // bit 13-14
- u16 res1:1; // bit 15
+ u16 asymmetric_dir:1; /* bit 0 */
+ u16 pause_en:1; /* bit 1 */
+ u16 autoneg_en:1; /* bit 2 */
+ u16 collision_status:1; /* bit 3 */
+ u16 rx_status:1; /* bit 4 */
+ u16 tx_status:1; /* bit 5 */
+ u16 link_status:1; /* bit 6 */
+ u16 duplex_status:1; /* bit 7 */
+ u16 speed_status:2; /* bits 8-9 */
+ u16 polarity_status:1; /* bit 10 */
+ u16 mdi_x_status:1; /* bit 11 */
+ u16 autoneg_status:1; /* bit 12 */
+ u16 autoneg_fault:2; /* bit 13-14 */
+ u16 res1:1; /* bit 15 */
#endif
} bits;
} MI_PSR_t, *PMI_PSR_t;
@@ -699,25 +696,25 @@ typedef union _MI_LCR1_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 res1:2; // bits 14-15
- u16 led_dup_indicate:2; // bits 12-13
- u16 led_10baseT:2; // bits 10-11
- u16 led_collision:2; // bits 8-9
- u16 res2:2; // bits 6-7
- u16 res3:2; // bits 4-5
- u16 pulse_dur:2; // bits 2-3
- u16 pulse_stretch1:1; // bit 1
- u16 pulse_stretch0:1; // bit 0
+ u16 res1:2; /* bits 14-15 */
+ u16 led_dup_indicate:2; /* bits 12-13 */
+ u16 led_10baseT:2; /* bits 10-11 */
+ u16 led_collision:2; /* bits 8-9 */
+ u16 res2:2; /* bits 6-7 */
+ u16 res3:2; /* bits 4-5 */
+ u16 pulse_dur:2; /* bits 2-3 */
+ u16 pulse_stretch1:1; /* bit 1 */
+ u16 pulse_stretch0:1; /* bit 0 */
#else
- u16 pulse_stretch0:1; // bit 0
- u16 pulse_stretch1:1; // bit 1
- u16 pulse_dur:2; // bits 2-3
- u16 res3:2; // bits 4-5
- u16 res2:2; // bits 6-7
- u16 led_collision:2; // bits 8-9
- u16 led_10baseT:2; // bits 10-11
- u16 led_dup_indicate:2; // bits 12-13
- u16 res1:2; // bits 14-15
+ u16 pulse_stretch0:1; /* bit 0 */
+ u16 pulse_stretch1:1; /* bit 1 */
+ u16 pulse_dur:2; /* bits 2-3 */
+ u16 res3:2; /* bits 4-5 */
+ u16 res2:2; /* bits 6-7 */
+ u16 led_collision:2; /* bits 8-9 */
+ u16 led_10baseT:2; /* bits 10-11 */
+ u16 led_dup_indicate:2; /* bits 12-13 */
+ u16 res1:2; /* bits 14-15 */
#endif
} bits;
} MI_LCR1_t, *PMI_LCR1_t;
@@ -727,43 +724,21 @@ typedef union _MI_LCR2_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
- u16 led_link:4; // bits 12-15
- u16 led_tx_rx:4; // bits 8-11
- u16 led_100BaseTX:4; // bits 4-7
- u16 led_1000BaseT:4; // bits 0-3
+ u16 led_link:4; /* bits 12-15 */
+ u16 led_tx_rx:4; /* bits 8-11 */
+ u16 led_100BaseTX:4; /* bits 4-7 */
+ u16 led_1000BaseT:4; /* bits 0-3 */
#else
- u16 led_1000BaseT:4; // bits 0-3
- u16 led_100BaseTX:4; // bits 4-7
- u16 led_tx_rx:4; // bits 8-11
- u16 led_link:4; // bits 12-15
+ u16 led_1000BaseT:4; /* bits 0-3 */
+ u16 led_100BaseTX:4; /* bits 4-7 */
+ u16 led_tx_rx:4; /* bits 8-11 */
+ u16 led_link:4; /* bits 12-15 */
#endif
} bits;
} MI_LCR2_t, *PMI_LCR2_t;
/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
-/* TruePHY headers */
-typedef struct _TRUEPHY_ACCESS_MI_REGS_ {
- TRUEPHY_HANDLE hTruePhy;
- int32_t nPhyId;
- u8 bReadWrite;
- u8 *pbyRegs;
- u8 *pwData;
- int32_t nRegCount;
-} TRUEPHY_ACCESS_MI_REGS, *PTRUEPHY_ACCESS_MI_REGS;
-
-/* TruePHY headers */
-typedef struct _TAG_TPAL_ACCESS_MI_REGS_ {
- u32 nPhyId;
- u8 bReadWrite;
- u32 nRegCount;
- u16 Data[4096];
- u8 Regs[4096];
-} TPAL_ACCESS_MI_REGS, *PTPAL_ACCESS_MI_REGS;
-
-
-typedef TRUEPHY_HANDLE TPAL_HANDLE;
-
/* Forward declaration of the private adapter structure */
struct et131x_adapter;
@@ -802,41 +777,41 @@ void SetPhy_10BaseTHalfDuplex(struct et131x_adapter *adapter);
/* Defines for PHY access routines */
-// Define bit operation flags
+/* Define bit operation flags */
#define TRUEPHY_BIT_CLEAR 0
#define TRUEPHY_BIT_SET 1
#define TRUEPHY_BIT_READ 2
-// Define read/write operation flags
+/* Define read/write operation flags */
#ifndef TRUEPHY_READ
#define TRUEPHY_READ 0
#define TRUEPHY_WRITE 1
#define TRUEPHY_MASK 2
#endif
-// Define speeds
+/* Define speeds */
#define TRUEPHY_SPEED_10MBPS 0
#define TRUEPHY_SPEED_100MBPS 1
#define TRUEPHY_SPEED_1000MBPS 2
-// Define duplex modes
+/* Define duplex modes */
#define TRUEPHY_DUPLEX_HALF 0
#define TRUEPHY_DUPLEX_FULL 1
-// Define master/slave configuration values
+/* Define master/slave configuration values */
#define TRUEPHY_CFG_SLAVE 0
#define TRUEPHY_CFG_MASTER 1
-// Define MDI/MDI-X settings
+/* Define MDI/MDI-X settings */
#define TRUEPHY_MDI 0
#define TRUEPHY_MDIX 1
#define TRUEPHY_AUTO_MDI_MDIX 2
-// Define 10Base-T link polarities
+/* Define 10Base-T link polarities */
#define TRUEPHY_POLARITY_NORMAL 0
#define TRUEPHY_POLARITY_INVERTED 1
-// Define auto-negotiation results
+/* Define auto-negotiation results */
#define TRUEPHY_ANEG_NOT_COMPLETE 0
#define TRUEPHY_ANEG_COMPLETE 1
#define TRUEPHY_ANEG_DISABLED 2
@@ -848,38 +823,38 @@ void SetPhy_10BaseTHalfDuplex(struct et131x_adapter *adapter);
#define TRUEPHY_ADV_DUPLEX_BOTH \
(TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF)
-#define PHY_CONTROL 0x00 //#define TRU_MI_CONTROL_REGISTER 0
-#define PHY_STATUS 0x01 //#define TRU_MI_STATUS_REGISTER 1
-#define PHY_ID_1 0x02 //#define TRU_MI_PHY_IDENTIFIER_1_REGISTER 2
-#define PHY_ID_2 0x03 //#define TRU_MI_PHY_IDENTIFIER_2_REGISTER 3
-#define PHY_AUTO_ADVERTISEMENT 0x04 //#define TRU_MI_ADVERTISEMENT_REGISTER 4
-#define PHY_AUTO_LINK_PARTNER 0x05 //#define TRU_MI_LINK_PARTNER_ABILITY_REGISTER 5
-#define PHY_AUTO_EXPANSION 0x06 //#define TRU_MI_EXPANSION_REGISTER 6
-#define PHY_AUTO_NEXT_PAGE_TX 0x07 //#define TRU_MI_NEXT_PAGE_TRANSMIT_REGISTER 7
-#define PHY_LINK_PARTNER_NEXT_PAGE 0x08 //#define TRU_MI_LINK_PARTNER_NEXT_PAGE_REGISTER 8
-#define PHY_1000_CONTROL 0x09 //#define TRU_MI_1000BASET_CONTROL_REGISTER 9
-#define PHY_1000_STATUS 0x0A //#define TRU_MI_1000BASET_STATUS_REGISTER 10
-
-#define PHY_EXTENDED_STATUS 0x0F //#define TRU_MI_EXTENDED_STATUS_REGISTER 15
-
-// some defines for modem registers that seem to be 'reserved'
+#define PHY_CONTROL 0x00 /* #define TRU_MI_CONTROL_REGISTER 0 */
+#define PHY_STATUS 0x01 /* #define TRU_MI_STATUS_REGISTER 1 */
+#define PHY_ID_1 0x02 /* #define TRU_MI_PHY_IDENTIFIER_1_REGISTER 2 */
+#define PHY_ID_2 0x03 /* #define TRU_MI_PHY_IDENTIFIER_2_REGISTER 3 */
+#define PHY_AUTO_ADVERTISEMENT 0x04 /* #define TRU_MI_ADVERTISEMENT_REGISTER 4 */
+#define PHY_AUTO_LINK_PARTNER 0x05 /* #define TRU_MI_LINK_PARTNER_ABILITY_REGISTER 5 */
+#define PHY_AUTO_EXPANSION 0x06 /* #define TRU_MI_EXPANSION_REGISTER 6 */
+#define PHY_AUTO_NEXT_PAGE_TX 0x07 /* #define TRU_MI_NEXT_PAGE_TRANSMIT_REGISTER 7 */
+#define PHY_LINK_PARTNER_NEXT_PAGE 0x08 /* #define TRU_MI_LINK_PARTNER_NEXT_PAGE_REGISTER 8 */
+#define PHY_1000_CONTROL 0x09 /* #define TRU_MI_1000BASET_CONTROL_REGISTER 9 */
+#define PHY_1000_STATUS 0x0A /* #define TRU_MI_1000BASET_STATUS_REGISTER 10 */
+
+#define PHY_EXTENDED_STATUS 0x0F /* #define TRU_MI_EXTENDED_STATUS_REGISTER 15 */
+
+/* some defines for modem registers that seem to be 'reserved' */
#define PHY_INDEX_REG 0x10
#define PHY_DATA_REG 0x11
-#define PHY_MPHY_CONTROL_REG 0x12 //#define TRU_VMI_MPHY_CONTROL_REGISTER 18
-
-#define PHY_LOOPBACK_CONTROL 0x13 //#define TRU_VMI_LOOPBACK_CONTROL_1_REGISTER 19
- //#define TRU_VMI_LOOPBACK_CONTROL_2_REGISTER 20
-#define PHY_REGISTER_MGMT_CONTROL 0x15 //#define TRU_VMI_MI_SEQ_CONTROL_REGISTER 21
-#define PHY_CONFIG 0x16 //#define TRU_VMI_CONFIGURATION_REGISTER 22
-#define PHY_PHY_CONTROL 0x17 //#define TRU_VMI_PHY_CONTROL_REGISTER 23
-#define PHY_INTERRUPT_MASK 0x18 //#define TRU_VMI_INTERRUPT_MASK_REGISTER 24
-#define PHY_INTERRUPT_STATUS 0x19 //#define TRU_VMI_INTERRUPT_STATUS_REGISTER 25
-#define PHY_PHY_STATUS 0x1A //#define TRU_VMI_PHY_STATUS_REGISTER 26
-#define PHY_LED_1 0x1B //#define TRU_VMI_LED_CONTROL_1_REGISTER 27
-#define PHY_LED_2 0x1C //#define TRU_VMI_LED_CONTROL_2_REGISTER 28
- //#define TRU_VMI_LINK_CONTROL_REGISTER 29
- //#define TRU_VMI_TIMING_CONTROL_REGISTER
+#define PHY_MPHY_CONTROL_REG 0x12 /* #define TRU_VMI_MPHY_CONTROL_REGISTER 18 */
+
+#define PHY_LOOPBACK_CONTROL 0x13 /* #define TRU_VMI_LOOPBACK_CONTROL_1_REGISTER 19 */
+ /* #define TRU_VMI_LOOPBACK_CONTROL_2_REGISTER 20 */
+#define PHY_REGISTER_MGMT_CONTROL 0x15 /* #define TRU_VMI_MI_SEQ_CONTROL_REGISTER 21 */
+#define PHY_CONFIG 0x16 /* #define TRU_VMI_CONFIGURATION_REGISTER 22 */
+#define PHY_PHY_CONTROL 0x17 /* #define TRU_VMI_PHY_CONTROL_REGISTER 23 */
+#define PHY_INTERRUPT_MASK 0x18 /* #define TRU_VMI_INTERRUPT_MASK_REGISTER 24 */
+#define PHY_INTERRUPT_STATUS 0x19 /* #define TRU_VMI_INTERRUPT_STATUS_REGISTER 25 */
+#define PHY_PHY_STATUS 0x1A /* #define TRU_VMI_PHY_STATUS_REGISTER 26 */
+#define PHY_LED_1 0x1B /* #define TRU_VMI_LED_CONTROL_1_REGISTER 27 */
+#define PHY_LED_2 0x1C /* #define TRU_VMI_LED_CONTROL_2_REGISTER 28 */
+ /* #define TRU_VMI_LINK_CONTROL_REGISTER 29 */
+ /* #define TRU_VMI_TIMING_CONTROL_REGISTER */
/* Prototypes for PHY access routines */
void ET1310_PhyInit(struct et131x_adapter *adapter);
@@ -895,12 +870,12 @@ void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *adapter,
void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *adapter,
u16 duplex);
void ET1310_PhyLinkStatus(struct et131x_adapter *adapter,
- u8 *ucLinkStatus,
- u32 *uiAutoNeg,
- u32 *uiLinkSpeed,
- u32 *uiDuplexMode,
- u32 *uiMdiMdix,
- u32 *uiMasterSlave, u32 *uiPolarity);
+ u8 *Link_status,
+ u32 *autoneg,
+ u32 *linkspeed,
+ u32 *duplex_mode,
+ u32 *mdi_mdix,
+ u32 *masterslave, u32 *polarity);
void ET1310_PhyAndOrReg(struct et131x_adapter *adapter,
u16 regnum, u16 andMask, u16 orMask);
void ET1310_PhyAccessMiBit(struct et131x_adapter *adapter,
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.