diff options
Diffstat (limited to 'drivers/staging/gma500/psb_drv.h')
| -rw-r--r-- | drivers/staging/gma500/psb_drv.h | 494 |
1 files changed, 299 insertions, 195 deletions
diff --git a/drivers/staging/gma500/psb_drv.h b/drivers/staging/gma500/psb_drv.h index e19a45478757..72f487a2a1b7 100644 --- a/drivers/staging/gma500/psb_drv.h +++ b/drivers/staging/gma500/psb_drv.h @@ -1,5 +1,5 @@ /************************************************************************** - * Copyright (c) 2007-2008, Intel Corporation. + * Copyright (c) 2007-2011, Intel Corporation. * All Rights Reserved. * * This program is free software; you can redistribute it and/or modify it @@ -20,52 +20,48 @@ #ifndef _PSB_DRV_H_ #define _PSB_DRV_H_ -#include <linux/version.h> #include <linux/kref.h> #include <drm/drmP.h> #include "drm_global.h" +#include "gem_glue.h" #include "psb_drm.h" #include "psb_reg.h" #include "psb_intel_drv.h" -#include "psb_gtt.h" -#include "psb_powermgmt.h" +#include "gtt.h" +#include "power.h" #include "mrst.h" +#include "medfield.h" -/*Append new drm mode definition here, align with libdrm definition*/ -#define DRM_MODE_SCALE_NO_SCALE 2 +/* Append new drm mode definition here, align with libdrm definition */ +#define DRM_MODE_SCALE_NO_SCALE 2 +#define DRM_MODE_CONNECTOR_MIPI 15 enum { - CHIP_PSB_8108 = 0, - CHIP_PSB_8109 = 1, - CHIP_MRST_4100 = 2, + CHIP_PSB_8108 = 0, /* Poulsbo */ + CHIP_PSB_8109 = 1, /* Poulsbo */ + CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */ + CHIP_MFLD_0130 = 3, /* Medfield */ }; #define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100) +#define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130) /* - *Hardware bugfixes + * Driver definitions */ -#define DRIVER_NAME "pvrsrvkm" -#define DRIVER_DESC "drm driver for the Intel GMA500" -#define DRIVER_AUTHOR "Intel Corporation" +#define DRIVER_NAME "gma500" +#define DRIVER_DESC "DRM driver for the Intel GMA500" -#define PSB_DRM_DRIVER_DATE "2009-03-10" -#define PSB_DRM_DRIVER_MAJOR 8 -#define PSB_DRM_DRIVER_MINOR 1 +#define PSB_DRM_DRIVER_DATE "2011-06-06" +#define PSB_DRM_DRIVER_MAJOR 1 +#define PSB_DRM_DRIVER_MINOR 0 #define PSB_DRM_DRIVER_PATCHLEVEL 0 /* - *TTM driver private offsets. + * Hardware offsets */ - -#define DRM_PSB_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) - -#define PSB_OBJECT_HASH_ORDER 13 -#define PSB_FILE_OBJECT_HASH_ORDER 12 -#define PSB_BO_HASH_ORDER 12 - #define PSB_VDC_OFFSET 0x00000000 #define PSB_VDC_SIZE 0x000080000 #define MRST_MMIO_SIZE 0x0000C0000 @@ -73,42 +69,52 @@ enum { #define PSB_SGX_SIZE 0x8000 #define PSB_SGX_OFFSET 0x00040000 #define MRST_SGX_OFFSET 0x00080000 +/* + * PCI resource identifiers + */ #define PSB_MMIO_RESOURCE 0 #define PSB_GATT_RESOURCE 2 #define PSB_GTT_RESOURCE 3 +/* + * PCI configuration + */ #define PSB_GMCH_CTRL 0x52 #define PSB_BSM 0x5C #define _PSB_GMCH_ENABLED 0x4 #define PSB_PGETBL_CTL 0x2020 #define _PSB_PGETBL_ENABLED 0x00000001 #define PSB_SGX_2D_SLAVE_PORT 0x4000 + +/* To get rid of */ #define PSB_TT_PRIV0_LIMIT (256*1024*1024) #define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT) -#define PSB_NUM_VALIDATE_BUFFERS 2048 /* - *Flags for external memory type field. + * SGX side MMU definitions (these can probably go) */ +/* + * Flags for external memory type field. + */ #define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */ #define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */ #define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */ - /* - *PTE's and PDE's + * PTE's and PDE's */ - #define PSB_PDE_MASK 0x003FFFFF #define PSB_PDE_SHIFT 22 #define PSB_PTE_SHIFT 12 - +/* + * Cache control + */ #define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */ #define PSB_PTE_WO 0x0002 /* Write only */ #define PSB_PTE_RO 0x0004 /* Read only */ #define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */ /* - *VDC registers and bits + * VDC registers and bits */ #define PSB_MSVDX_CLOCKGATING 0x2064 #define PSB_TOPAZ_CLOCKGATING 0x2068 @@ -130,8 +136,12 @@ enum { #define _LNC_IRQ_TOPAZ_FLAG (1<<20) /* This flag includes all the display IRQ bits excepts the vblank irqs. */ -#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | _MDFLD_PIPEB_EVENT_FLAG | \ - _PSB_PIPEA_EVENT_FLAG | _PSB_VSYNC_PIPEA_FLAG | _MDFLD_MIPIA_FLAG | _MDFLD_MIPIC_FLAG) +#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \ + _MDFLD_PIPEB_EVENT_FLAG | \ + _PSB_PIPEA_EVENT_FLAG | \ + _PSB_VSYNC_PIPEA_FLAG | \ + _MDFLD_MIPIA_FLAG | \ + _MDFLD_MIPIC_FLAG) #define PSB_INT_IDENTITY_R 0x20A4 #define PSB_INT_MASK_R 0x20A8 #define PSB_INT_ENABLE_R 0x20A0 @@ -197,10 +207,25 @@ enum { #define PSB_WATCHDOG_DELAY (DRM_HZ * 2) #define PSB_LID_DELAY (DRM_HZ / 10) -#define MDFLD_PNW_A0 0x00 #define MDFLD_PNW_B0 0x04 #define MDFLD_PNW_C0 0x08 +#define MDFLD_DSR_2D_3D_0 (1 << 0) +#define MDFLD_DSR_2D_3D_2 (1 << 1) +#define MDFLD_DSR_CURSOR_0 (1 << 2) +#define MDFLD_DSR_CURSOR_2 (1 << 3) +#define MDFLD_DSR_OVERLAY_0 (1 << 4) +#define MDFLD_DSR_OVERLAY_2 (1 << 5) +#define MDFLD_DSR_MIPI_CONTROL (1 << 6) +#define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4)) +#define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5)) +#define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2) + +#define MDFLD_DSR_RR 45 +#define MDFLD_DPU_ENABLE (1 << 31) +#define MDFLD_DSR_FULLSCREEN (1 << 30) +#define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR) + #define PSB_PWR_STATE_ON 1 #define PSB_PWR_STATE_OFF 2 @@ -214,6 +239,12 @@ enum { #define PSB_PCIx_MSI_ADDR_LOC 0x94 #define PSB_PCIx_MSI_DATA_LOC 0x98 +/* Medfield crystal settings */ +#define KSEL_CRYSTAL_19 1 +#define KSEL_BYPASS_19 5 +#define KSEL_BYPASS_25 6 +#define KSEL_BYPASS_83_100 7 + struct opregion_header; struct opregion_acpi; struct opregion_swsci; @@ -227,13 +258,13 @@ struct psb_intel_opregion { int enabled; }; +struct psb_ops; struct drm_psb_private { struct drm_device *dev; + const struct psb_ops *ops; - unsigned long chipset; - - struct psb_gtt *pg; + struct psb_gtt gtt; /* GTT Memory manager */ struct psb_gtt_mm *gtt_mm; @@ -271,14 +302,14 @@ struct drm_psb_private { /* * Power - */ + */ bool suspended; bool display_power; int display_count; /* - *Modesetting + * Modesetting */ struct psb_intel_mode_device mode_dev; @@ -287,12 +318,8 @@ struct drm_psb_private { uint32_t num_pipe; /* - *Memory managers + * OSPM info (Power management base) (can go ?) */ - - /* - *OSPM info - */ uint32_t ospm_base; /* @@ -304,11 +331,11 @@ struct drm_psb_private { u32 fuse_reg_value; u32 video_device_fuse; - /* pci revision id for B0:D2:F0 */ + /* PCI revision ID for B0:D2:F0 */ uint8_t platform_rev_id; /* - *LVDS info + * LVDS info */ int backlight_duty_cycle; /* restore backlight to this value */ bool panel_wants_dither; @@ -316,10 +343,10 @@ struct drm_psb_private { struct drm_display_mode *lfp_lvds_vbt_mode; struct drm_display_mode *sdvo_lvds_vbt_mode; - struct bdb_lvds_backlight *lvds_bl; /*LVDS backlight info from VBT*/ + struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */ struct psb_intel_i2c_chan *lvds_i2c_bus; - /* Feature bits from the VBIOS*/ + /* Feature bits from the VBIOS */ unsigned int int_tv_support:1; unsigned int lvds_dither:1; unsigned int lvds_vbt:1; @@ -328,17 +355,30 @@ struct drm_psb_private { int lvds_ssc_freq; bool is_lvds_on; bool is_mipi_on; + u32 mipi_ctrl_display; unsigned int core_freq; uint32_t iLVDS_enable; - /*runtime PM state*/ + /* Runtime PM state */ int rpm_enabled; - /* Moorestown specific */ + /* MID specific */ struct mrst_vbt vbt_data; struct mrst_gct_data gct_data; + /* MIPI Panel type etc */ + int panel_id; + bool dual_mipi; /* dual display - DPI & DBI */ + bool dpi_panel_on; /* The DPI panel power is on */ + bool dpi_panel_on2; /* The DPI panel power is on */ + bool dbi_panel_on; /* The DBI panel power is on */ + bool dbi_panel_on2; /* The DBI panel power is on */ + u32 dsr_fb_update; /* DSR FB update counter */ + + /* Moorestown HDMI state */ + struct mrst_hdmi_dev *hdmi_priv; + /* Moorestown pipe config register value cache */ uint32_t pipeconf; uint32_t pipeconf1; @@ -349,8 +389,13 @@ struct drm_psb_private { uint32_t dspcntr1; uint32_t dspcntr2; + /* Moorestown MM backlight cache */ + uint8_t saveBKLTCNT; + uint8_t saveBKLTREQ; + uint8_t saveBKLTBRTL; + /* - *Register state + * Register state */ uint32_t saveDSPACNTR; uint32_t saveDSPBCNTR; @@ -373,6 +418,7 @@ struct drm_psb_private { uint32_t saveDSPAPOS; uint32_t saveDSPABASE; uint32_t saveDSPASURF; + uint32_t saveDSPASTATUS; uint32_t saveFPB0; uint32_t saveFPB1; uint32_t saveDPLL_B; @@ -388,6 +434,7 @@ struct drm_psb_private { uint32_t saveDSPBPOS; uint32_t saveDSPBBASE; uint32_t saveDSPBSURF; + uint32_t saveDSPBSTATUS; uint32_t saveVCLK_DIVISOR_VGA0; uint32_t saveVCLK_DIVISOR_VGA1; uint32_t saveVCLK_POST_DIV; @@ -458,6 +505,77 @@ struct drm_psb_private { uint32_t msi_addr; uint32_t msi_data; + /* Medfield specific register save state */ + uint32_t saveHDMIPHYMISCCTL; + uint32_t saveHDMIB_CONTROL; + uint32_t saveDSPCCNTR; + uint32_t savePIPECCONF; + uint32_t savePIPECSRC; + uint32_t saveHTOTAL_C; + uint32_t saveHBLANK_C; + uint32_t saveHSYNC_C; + uint32_t saveVTOTAL_C; + uint32_t saveVBLANK_C; + uint32_t saveVSYNC_C; + uint32_t saveDSPCSTRIDE; + uint32_t saveDSPCSIZE; + uint32_t saveDSPCPOS; + uint32_t saveDSPCSURF; + uint32_t saveDSPCSTATUS; + uint32_t saveDSPCLINOFF; + uint32_t saveDSPCTILEOFF; + uint32_t saveDSPCCURSOR_CTRL; + uint32_t saveDSPCCURSOR_BASE; + uint32_t saveDSPCCURSOR_POS; + uint32_t save_palette_c[256]; + uint32_t saveOV_OVADD_C; + uint32_t saveOV_OGAMC0_C; + uint32_t saveOV_OGAMC1_C; + uint32_t saveOV_OGAMC2_C; + uint32_t saveOV_OGAMC3_C; + uint32_t saveOV_OGAMC4_C; + uint32_t saveOV_OGAMC5_C; + + /* DSI register save */ + uint32_t saveDEVICE_READY_REG; + uint32_t saveINTR_EN_REG; + uint32_t saveDSI_FUNC_PRG_REG; + uint32_t saveHS_TX_TIMEOUT_REG; + uint32_t saveLP_RX_TIMEOUT_REG; + uint32_t saveTURN_AROUND_TIMEOUT_REG; + uint32_t saveDEVICE_RESET_REG; + uint32_t saveDPI_RESOLUTION_REG; + uint32_t saveHORIZ_SYNC_PAD_COUNT_REG; + uint32_t saveHORIZ_BACK_PORCH_COUNT_REG; + uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG; + uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG; + uint32_t saveVERT_SYNC_PAD_COUNT_REG; + uint32_t saveVERT_BACK_PORCH_COUNT_REG; + uint32_t saveVERT_FRONT_PORCH_COUNT_REG; + uint32_t saveHIGH_LOW_SWITCH_COUNT_REG; + uint32_t saveINIT_COUNT_REG; + uint32_t saveMAX_RET_PAK_REG; + uint32_t saveVIDEO_FMT_REG; + uint32_t saveEOT_DISABLE_REG; + uint32_t saveLP_BYTECLK_REG; + uint32_t saveHS_LS_DBI_ENABLE_REG; + uint32_t saveTXCLKESC_REG; + uint32_t saveDPHY_PARAM_REG; + uint32_t saveMIPI_CONTROL_REG; + uint32_t saveMIPI; + uint32_t saveMIPI_C; + + /* DPST register save */ + uint32_t saveHISTOGRAM_INT_CONTROL_REG; + uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG; + uint32_t savePWM_CONTROL_LOGIC; + + /* + * DSI info. + */ + void * dbi_dsr_info; + void * dbi_dpu_info; + void * dsi_configs[2]; /* * LID-Switch */ @@ -468,7 +586,7 @@ struct drm_psb_private { u32 lid_last_state; /* - *Watchdog + * Watchdog */ uint32_t apm_reg; @@ -478,14 +596,71 @@ struct drm_psb_private { * Used for modifying backlight from * xrandr -- consider removing and using HAL instead */ + struct backlight_device *backlight_device; struct drm_property *backlight_property; uint32_t blc_adj1; uint32_t blc_adj2; - void * fbdev; + void *fbdev; + /* DPST state */ + uint32_t dsr_idle_count; + bool is_in_idle; + bool dsr_enable; + void (*exit_idle)(struct drm_device *dev, u32 update_src); + + /* 2D acceleration */ + struct mutex mutex_2d; + + /* FIXME: Arrays anyone ? */ + struct mdfld_dsi_encoder *encoder0; + struct mdfld_dsi_encoder *encoder2; + struct mdfld_dsi_dbi_output * dbi_output; + struct mdfld_dsi_dbi_output * dbi_output2; + u32 bpp; + u32 bpp2; + + bool dispstatus; +}; + + +/* + * Operations for each board type + */ + +struct psb_ops { + const char *name; + unsigned int accel_2d:1; + int pipes; /* Number of output pipes */ + int crtcs; /* Number of CRTCs */ + int sgx_offset; /* Base offset of SGX device */ + + /* Sub functions */ + struct drm_crtc_helper_funcs const *crtc_helper; + struct drm_crtc_funcs const *crtc_funcs; + + /* Setup hooks */ + int (*chip_setup)(struct drm_device *dev); + void (*chip_teardown)(struct drm_device *dev); + + /* Display management hooks */ + int (*output_init)(struct drm_device *dev); + /* Power management hooks */ + void (*init_pm)(struct drm_device *dev); + int (*save_regs)(struct drm_device *dev); + int (*restore_regs)(struct drm_device *dev); + int (*power_up)(struct drm_device *dev); + int (*power_down)(struct drm_device *dev); + + void (*lvds_bl_power)(struct drm_device *dev, bool on); +#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE + /* Backlight */ + int (*backlight_init)(struct drm_device *dev); +#endif + int i2c_bus; /* I2C bus identifier for Moorestown */ }; + struct psb_mmu_driver; extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int); @@ -497,7 +672,7 @@ static inline struct drm_psb_private *psb_priv(struct drm_device *dev) } /* - *MMU stuff. + * MMU stuff. */ extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers, @@ -525,7 +700,7 @@ extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual, unsigned long *pfn); /* - *Enable / disable MMU for different requestors. + * Enable / disable MMU for different requestors. */ @@ -552,7 +727,7 @@ extern void psb_irq_turn_on_dpst(struct drm_device *dev); extern void psb_irq_turn_off_dpst(struct drm_device *dev); extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands); -extern int psb_vblank_wait2(struct drm_device *dev,unsigned int *sequence); +extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence); extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence); extern int psb_enable_vblank(struct drm_device *dev, int crtc); extern void psb_disable_vblank(struct drm_device *dev, int crtc); @@ -564,41 +739,33 @@ psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask); extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc); +extern int mdfld_enable_te(struct drm_device *dev, int pipe); +extern void mdfld_disable_te(struct drm_device *dev, int pipe); + /* - * psb_opregion.c + * intel_opregion.c */ -extern int psb_intel_opregion_init(struct drm_device *dev); +extern int gma_intel_opregion_init(struct drm_device *dev); +extern int gma_intel_opregion_exit(struct drm_device *dev); /* - *psb_fb.c + * framebuffer.c */ extern int psbfb_probed(struct drm_device *dev); extern int psbfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); -extern int psbfb_kms_off_ioctl(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int psbfb_kms_on_ioctl(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern void *psbfb_vdc_reg(struct drm_device* dev); - /* - * psb_2d.c + * accel_2d.c */ -extern void psbfb_fillrect(struct fb_info *info, - const struct fb_fillrect *rect); extern void psbfb_copyarea(struct fb_info *info, const struct fb_copyarea *region); -extern void psbfb_imageblit(struct fb_info *info, - const struct fb_image *image); extern int psbfb_sync(struct fb_info *info); - extern void psb_spank(struct drm_psb_private *dev_priv); - -extern int psbfb_2d_submit(struct drm_psb_private *dev_priv, uint32_t *cmdbuf, - unsigned size); +extern int psb_accel_ioctl(struct drm_device *dev, void *data, + struct drm_file *file); /* - *psb_reset.c + * psb_reset.c */ extern void psb_lid_timer_init(struct drm_psb_private *dev_priv); @@ -608,14 +775,11 @@ extern void psb_print_pagefault(struct drm_psb_private *dev_priv); /* modesetting */ extern void psb_modeset_init(struct drm_device *dev); extern void psb_modeset_cleanup(struct drm_device *dev); -extern int psb_fbdev_init(struct drm_device * dev); +extern int psb_fbdev_init(struct drm_device *dev); -/* psb_bl.c */ -int psb_backlight_init(struct drm_device *dev); -void psb_backlight_exit(void); -int psb_set_brightness(struct backlight_device *bd); -int psb_get_brightness(struct backlight_device *bd); -struct backlight_device * psb_get_backlight_device(void); +/* backlight.c */ +int gma_backlight_init(struct drm_device *dev); +void gma_backlight_exit(struct drm_device *dev); /* mrst_crtc.c */ extern const struct drm_crtc_helper_funcs mrst_helper_funcs; @@ -624,26 +788,43 @@ extern const struct drm_crtc_helper_funcs mrst_helper_funcs; extern void mrst_lvds_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev); +/* psb_intel_display.c */ +extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs; +extern const struct drm_crtc_funcs psb_intel_crtc_funcs; + /* psb_intel_lvds.c */ -extern void psb_intel_lvds_prepare(struct drm_encoder *encoder); -extern void psb_intel_lvds_commit(struct drm_encoder *encoder); extern const struct drm_connector_helper_funcs psb_intel_lvds_connector_helper_funcs; extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs; -/* psb_gem.c */ +/* gem.c */ extern int psb_gem_init_object(struct drm_gem_object *obj); extern void psb_gem_free_object(struct drm_gem_object *obj); extern int psb_gem_get_aperture(struct drm_device *dev, void *data, - struct drm_file *file); + struct drm_file *file); extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev, struct drm_mode_create_dumb *args); extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev, uint32_t handle); extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev, - uint32_t handle, uint64_t *offset); + uint32_t handle, uint64_t *offset); extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); +extern int psb_gem_create_ioctl(struct drm_device *dev, void *data, + struct drm_file *file); +extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data, + struct drm_file *file); + +/* psb_device.c */ +extern const struct psb_ops psb_chip_ops; + +/* mrst_device.c */ +extern const struct psb_ops mrst_chip_ops; + +/* mdfld_device.c */ +extern const struct psb_ops mdfld_chip_ops; +/* cdv_device.c */ +extern const struct psb_ops cdv_chip_ops; /* * Debug print bits setting @@ -661,110 +842,62 @@ extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); #define PSB_D_MSVDX (1 << 9) #define PSB_D_TOPAZ (1 << 10) -#ifndef DRM_DEBUG_CODE -/* To enable debug printout, set drm_psb_debug in psb_drv.c - * to any combination of above print flags. - */ -/* #define DRM_DEBUG_CODE 2 */ -#endif - -extern int drm_psb_debug; extern int drm_psb_no_fb; extern int drm_idle_check_interval; -#define PSB_DEBUG_GENERAL(_fmt, _arg...) \ - PSB_DEBUG(PSB_D_GENERAL, _fmt, ##_arg) -#define PSB_DEBUG_INIT(_fmt, _arg...) \ - PSB_DEBUG(PSB_D_INIT, _fmt, ##_arg) -#define PSB_DEBUG_IRQ(_fmt, _arg...) \ - PSB_DEBUG(PSB_D_IRQ, _fmt, ##_arg) -#define PSB_DEBUG_ENTRY(_fmt, _arg...) \ - PSB_DEBUG(PSB_D_ENTRY, _fmt, ##_arg) -#define PSB_DEBUG_HV(_fmt, _arg...) \ - PSB_DEBUG(PSB_D_HV, _fmt, ##_arg) -#define PSB_DEBUG_DBI_BF(_fmt, _arg...) \ - PSB_DEBUG(PSB_D_DBI_BF, _fmt, ##_arg) -#define PSB_DEBUG_PM(_fmt, _arg...) \ - PSB_DEBUG(PSB_D_PM, _fmt, ##_arg) -#define PSB_DEBUG_RENDER(_fmt, _arg...) \ - PSB_DEBUG(PSB_D_RENDER, _fmt, ##_arg) -#define PSB_DEBUG_REG(_fmt, _arg...) \ - PSB_DEBUG(PSB_D_REG, _fmt, ##_arg) -#define PSB_DEBUG_MSVDX(_fmt, _arg...) \ - PSB_DEBUG(PSB_D_MSVDX, _fmt, ##_arg) -#define PSB_DEBUG_TOPAZ(_fmt, _arg...) \ - PSB_DEBUG(PSB_D_TOPAZ, _fmt, ##_arg) - -#if DRM_DEBUG_CODE -#define PSB_DEBUG(_flag, _fmt, _arg...) \ - do { \ - if (unlikely((_flag) & drm_psb_debug)) \ - printk(KERN_DEBUG \ - "[psb:0x%02x:%s] " _fmt , _flag, \ - __func__ , ##_arg); \ - } while (0) -#else -#define PSB_DEBUG(_fmt, _arg...) do { } while (0) -#endif - /* - *Utilities + * Utilities */ -#define DRM_DRIVER_PRIVATE_T struct drm_psb_private static inline u32 MRST_MSG_READ32(uint port, uint offset) { int mcr = (0xD0<<24) | (port << 16) | (offset << 8); uint32_t ret_val = 0; - struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0); - pci_write_config_dword (pci_root, 0xD0, mcr); - pci_read_config_dword (pci_root, 0xD4, &ret_val); + struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); + pci_write_config_dword(pci_root, 0xD0, mcr); + pci_read_config_dword(pci_root, 0xD4, &ret_val); pci_dev_put(pci_root); return ret_val; } static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value) { int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0; - struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0); - pci_write_config_dword (pci_root, 0xD4, value); - pci_write_config_dword (pci_root, 0xD0, mcr); + struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); + pci_write_config_dword(pci_root, 0xD4, value); + pci_write_config_dword(pci_root, 0xD0, mcr); pci_dev_put(pci_root); } static inline u32 MDFLD_MSG_READ32(uint port, uint offset) { int mcr = (0x10<<24) | (port << 16) | (offset << 8); uint32_t ret_val = 0; - struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0); - pci_write_config_dword (pci_root, 0xD0, mcr); - pci_read_config_dword (pci_root, 0xD4, &ret_val); + struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); + pci_write_config_dword(pci_root, 0xD0, mcr); + pci_read_config_dword(pci_root, 0xD4, &ret_val); pci_dev_put(pci_root); return ret_val; } static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value) { int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0; - struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0); - pci_write_config_dword (pci_root, 0xD4, value); - pci_write_config_dword (pci_root, 0xD0, mcr); + struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); + pci_write_config_dword(pci_root, 0xD4, value); + pci_write_config_dword(pci_root, 0xD0, mcr); pci_dev_put(pci_root); } static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg) { struct drm_psb_private *dev_priv = dev->dev_private; - int reg_val = ioread32(dev_priv->vdc_reg + (reg)); - PSB_DEBUG_REG("reg = 0x%x. reg_val = 0x%x. \n", reg, reg_val); - return reg_val; + return ioread32(dev_priv->vdc_reg + reg); } #define REG_READ(reg) REGISTER_READ(dev, (reg)) + static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg, uint32_t val) { struct drm_psb_private *dev_priv = dev->dev_private; - if ((reg < 0x70084 || reg >0x70088) && (reg < 0xa000 || reg >0xa3ff)) - PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg, val); - iowrite32((val), dev_priv->vdc_reg + (reg)); } @@ -774,9 +907,6 @@ static inline void REGISTER_WRITE16(struct drm_device *dev, uint32_t reg, uint32_t val) { struct drm_psb_private *dev_priv = dev->dev_private; - - PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg, val); - iowrite16((val), dev_priv->vdc_reg + (reg)); } @@ -786,60 +916,34 @@ static inline void REGISTER_WRITE8(struct drm_device *dev, uint32_t reg, uint32_t val) { struct drm_psb_private *dev_priv = dev->dev_private; - - PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg, val); - iowrite8((val), dev_priv->vdc_reg + (reg)); } -#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val)) +#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val)) -#define PSB_ALIGN_TO(_val, _align) \ - (((_val) + ((_align) - 1)) & ~((_align) - 1)) -#define PSB_WVDC32(_val, _offs) \ - iowrite32(_val, dev_priv->vdc_reg + (_offs)) -#define PSB_RVDC32(_offs) \ - ioread32(dev_priv->vdc_reg + (_offs)) +#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs)) +#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs)) /* #define TRAP_SGX_PM_FAULT 1 */ #ifdef TRAP_SGX_PM_FAULT -#define PSB_RSGX32(_offs) \ -({ \ - if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \ - printk(KERN_ERR "access sgx when it's off!! (READ) %s, %d\n", \ - __FILE__, __LINE__); \ - mdelay(1000); \ - } \ - ioread32(dev_priv->sgx_reg + (_offs)); \ +#define PSB_RSGX32(_offs) \ +({ \ + if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \ + printk(KERN_ERR \ + "access sgx when it's off!! (READ) %s, %d\n", \ + __FILE__, __LINE__); \ + melay(1000); \ + } \ + ioread32(dev_priv->sgx_reg + (_offs)); \ }) #else -#define PSB_RSGX32(_offs) \ - ioread32(dev_priv->sgx_reg + (_offs)) +#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs)) #endif -#define PSB_WSGX32(_val, _offs) \ - iowrite32(_val, dev_priv->sgx_reg + (_offs)) +#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs)) #define MSVDX_REG_DUMP 0 -#if MSVDX_REG_DUMP - -#define PSB_WMSVDX32(_val, _offs) \ - printk("MSVDX: write %08x to reg 0x%08x\n", (unsigned int)(_val), (unsigned int)(_offs));\ - iowrite32(_val, dev_priv->msvdx_reg + (_offs)) -#define PSB_RMSVDX32(_offs) \ - ioread32(dev_priv->msvdx_reg + (_offs)) - -#else - -#define PSB_WMSVDX32(_val, _offs) \ - iowrite32(_val, dev_priv->msvdx_reg + (_offs)) -#define PSB_RMSVDX32(_offs) \ - ioread32(dev_priv->msvdx_reg + (_offs)) - -#endif -#define PSB_ALPL(_val, _base) \ - (((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) -#define PSB_ALPLM(_val, _base) \ - ((((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) & (_base ## _MASK)) +#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs)) +#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs)) #endif |