diff options
Diffstat (limited to 'drivers/staging/mt7621-mmc/mt6575_sd.h')
-rw-r--r-- | drivers/staging/mt7621-mmc/mt6575_sd.h | 588 |
1 files changed, 45 insertions, 543 deletions
diff --git a/drivers/staging/mt7621-mmc/mt6575_sd.h b/drivers/staging/mt7621-mmc/mt6575_sd.h index 33fa59a019ec..4e287c140acb 100644 --- a/drivers/staging/mt7621-mmc/mt6575_sd.h +++ b/drivers/staging/mt7621-mmc/mt6575_sd.h @@ -42,11 +42,6 @@ // #include <mach/mt6575_reg_base.h> /* --- by chhung */ /*--------------------------------------------------------------------------*/ -/* Common Macro */ -/*--------------------------------------------------------------------------*/ -#define REG_ADDR(x) (base + OFFSET_##x) - -/*--------------------------------------------------------------------------*/ /* Common Definition */ /*--------------------------------------------------------------------------*/ #define MSDC_FIFO_SZ (128) @@ -56,13 +51,6 @@ #define MSDC_MS (0) #define MSDC_SDMMC (1) -#define MSDC_MODE_UNKNOWN (0) -#define MSDC_MODE_PIO (1) -#define MSDC_MODE_DMA_BASIC (2) -#define MSDC_MODE_DMA_DESC (3) -#define MSDC_MODE_DMA_ENHANCED (4) -#define MSDC_MODE_MMC_STREAM (5) - #define MSDC_BUS_1BITS (0) #define MSDC_BUS_4BITS (1) #define MSDC_BUS_8BITS (2) @@ -102,117 +90,51 @@ enum { /*--------------------------------------------------------------------------*/ /* Register Offset */ /*--------------------------------------------------------------------------*/ -#define OFFSET_MSDC_CFG (0x0) -#define OFFSET_MSDC_IOCON (0x04) -#define OFFSET_MSDC_PS (0x08) -#define OFFSET_MSDC_INT (0x0c) -#define OFFSET_MSDC_INTEN (0x10) -#define OFFSET_MSDC_FIFOCS (0x14) -#define OFFSET_MSDC_TXDATA (0x18) -#define OFFSET_MSDC_RXDATA (0x1c) -#define OFFSET_SDC_CFG (0x30) -#define OFFSET_SDC_CMD (0x34) -#define OFFSET_SDC_ARG (0x38) -#define OFFSET_SDC_STS (0x3c) -#define OFFSET_SDC_RESP0 (0x40) -#define OFFSET_SDC_RESP1 (0x44) -#define OFFSET_SDC_RESP2 (0x48) -#define OFFSET_SDC_RESP3 (0x4c) -#define OFFSET_SDC_BLK_NUM (0x50) -#define OFFSET_SDC_CSTS (0x58) -#define OFFSET_SDC_CSTS_EN (0x5c) -#define OFFSET_SDC_DCRC_STS (0x60) -#define OFFSET_EMMC_CFG0 (0x70) -#define OFFSET_EMMC_CFG1 (0x74) -#define OFFSET_EMMC_STS (0x78) -#define OFFSET_EMMC_IOCON (0x7c) -#define OFFSET_SDC_ACMD_RESP (0x80) -#define OFFSET_SDC_ACMD19_TRG (0x84) -#define OFFSET_SDC_ACMD19_STS (0x88) -#define OFFSET_MSDC_DMA_SA (0x90) -#define OFFSET_MSDC_DMA_CA (0x94) -#define OFFSET_MSDC_DMA_CTRL (0x98) -#define OFFSET_MSDC_DMA_CFG (0x9c) -#define OFFSET_MSDC_DBG_SEL (0xa0) -#define OFFSET_MSDC_DBG_OUT (0xa4) -#define OFFSET_MSDC_PATCH_BIT (0xb0) -#define OFFSET_MSDC_PATCH_BIT1 (0xb4) -#define OFFSET_MSDC_PAD_CTL0 (0xe0) -#define OFFSET_MSDC_PAD_CTL1 (0xe4) -#define OFFSET_MSDC_PAD_CTL2 (0xe8) -#define OFFSET_MSDC_PAD_TUNE (0xec) -#define OFFSET_MSDC_DAT_RDDLY0 (0xf0) -#define OFFSET_MSDC_DAT_RDDLY1 (0xf4) -#define OFFSET_MSDC_HW_DBG (0xf8) -#define OFFSET_MSDC_VERSION (0x100) -#define OFFSET_MSDC_ECO_VER (0x104) - -/*--------------------------------------------------------------------------*/ -/* Register Address */ -/*--------------------------------------------------------------------------*/ - -/* common register */ -#define MSDC_CFG REG_ADDR(MSDC_CFG) -#define MSDC_IOCON REG_ADDR(MSDC_IOCON) -#define MSDC_PS REG_ADDR(MSDC_PS) -#define MSDC_INT REG_ADDR(MSDC_INT) -#define MSDC_INTEN REG_ADDR(MSDC_INTEN) -#define MSDC_FIFOCS REG_ADDR(MSDC_FIFOCS) -#define MSDC_TXDATA REG_ADDR(MSDC_TXDATA) -#define MSDC_RXDATA REG_ADDR(MSDC_RXDATA) -#define MSDC_PATCH_BIT0 REG_ADDR(MSDC_PATCH_BIT) - -/* sdmmc register */ -#define SDC_CFG REG_ADDR(SDC_CFG) -#define SDC_CMD REG_ADDR(SDC_CMD) -#define SDC_ARG REG_ADDR(SDC_ARG) -#define SDC_STS REG_ADDR(SDC_STS) -#define SDC_RESP0 REG_ADDR(SDC_RESP0) -#define SDC_RESP1 REG_ADDR(SDC_RESP1) -#define SDC_RESP2 REG_ADDR(SDC_RESP2) -#define SDC_RESP3 REG_ADDR(SDC_RESP3) -#define SDC_BLK_NUM REG_ADDR(SDC_BLK_NUM) -#define SDC_CSTS REG_ADDR(SDC_CSTS) -#define SDC_CSTS_EN REG_ADDR(SDC_CSTS_EN) -#define SDC_DCRC_STS REG_ADDR(SDC_DCRC_STS) - -/* emmc register*/ -#define EMMC_CFG0 REG_ADDR(EMMC_CFG0) -#define EMMC_CFG1 REG_ADDR(EMMC_CFG1) -#define EMMC_STS REG_ADDR(EMMC_STS) -#define EMMC_IOCON REG_ADDR(EMMC_IOCON) - -/* auto command register */ -#define SDC_ACMD_RESP REG_ADDR(SDC_ACMD_RESP) -#define SDC_ACMD19_TRG REG_ADDR(SDC_ACMD19_TRG) -#define SDC_ACMD19_STS REG_ADDR(SDC_ACMD19_STS) - -/* dma register */ -#define MSDC_DMA_SA REG_ADDR(MSDC_DMA_SA) -#define MSDC_DMA_CA REG_ADDR(MSDC_DMA_CA) -#define MSDC_DMA_CTRL REG_ADDR(MSDC_DMA_CTRL) -#define MSDC_DMA_CFG REG_ADDR(MSDC_DMA_CFG) - -/* pad ctrl register */ -#define MSDC_PAD_CTL0 REG_ADDR(MSDC_PAD_CTL0) -#define MSDC_PAD_CTL1 REG_ADDR(MSDC_PAD_CTL1) -#define MSDC_PAD_CTL2 REG_ADDR(MSDC_PAD_CTL2) - -/* data read delay */ -#define MSDC_DAT_RDDLY0 REG_ADDR(MSDC_DAT_RDDLY0) -#define MSDC_DAT_RDDLY1 REG_ADDR(MSDC_DAT_RDDLY1) - -/* debug register */ -#define MSDC_DBG_SEL REG_ADDR(MSDC_DBG_SEL) -#define MSDC_DBG_OUT REG_ADDR(MSDC_DBG_OUT) - -/* misc register */ -#define MSDC_PATCH_BIT REG_ADDR(MSDC_PATCH_BIT) -#define MSDC_PATCH_BIT1 REG_ADDR(MSDC_PATCH_BIT1) -#define MSDC_PAD_TUNE REG_ADDR(MSDC_PAD_TUNE) -#define MSDC_HW_DBG REG_ADDR(MSDC_HW_DBG) -#define MSDC_VERSION REG_ADDR(MSDC_VERSION) -#define MSDC_ECO_VER REG_ADDR(MSDC_ECO_VER) /* ECO Version */ +#define MSDC_CFG (0x0) +#define MSDC_IOCON (0x04) +#define MSDC_PS (0x08) +#define MSDC_INT (0x0c) +#define MSDC_INTEN (0x10) +#define MSDC_FIFOCS (0x14) +#define MSDC_TXDATA (0x18) +#define MSDC_RXDATA (0x1c) +#define SDC_CFG (0x30) +#define SDC_CMD (0x34) +#define SDC_ARG (0x38) +#define SDC_STS (0x3c) +#define SDC_RESP0 (0x40) +#define SDC_RESP1 (0x44) +#define SDC_RESP2 (0x48) +#define SDC_RESP3 (0x4c) +#define SDC_BLK_NUM (0x50) +#define SDC_CSTS (0x58) +#define SDC_CSTS_EN (0x5c) +#define SDC_DCRC_STS (0x60) +#define EMMC_CFG0 (0x70) +#define EMMC_CFG1 (0x74) +#define EMMC_STS (0x78) +#define EMMC_IOCON (0x7c) +#define SDC_ACMD_RESP (0x80) +#define SDC_ACMD19_TRG (0x84) +#define SDC_ACMD19_STS (0x88) +#define MSDC_DMA_SA (0x90) +#define MSDC_DMA_CA (0x94) +#define MSDC_DMA_CTRL (0x98) +#define MSDC_DMA_CFG (0x9c) +#define MSDC_DBG_SEL (0xa0) +#define MSDC_DBG_OUT (0xa4) +#define MSDC_PATCH_BIT (0xb0) +#define MSDC_PATCH_BIT0 MSDC_PATCH_BIT +#define MSDC_PATCH_BIT1 (0xb4) +#define MSDC_PAD_CTL0 (0xe0) +#define MSDC_PAD_CTL1 (0xe4) +#define MSDC_PAD_CTL2 (0xe8) +#define MSDC_PAD_TUNE (0xec) +#define MSDC_DAT_RDDLY0 (0xf0) +#define MSDC_DAT_RDDLY1 (0xf4) +#define MSDC_HW_DBG (0xf8) +#define MSDC_VERSION (0x100) +#define MSDC_ECO_VER (0x104) /*--------------------------------------------------------------------------*/ /* Register Mask */ @@ -478,422 +400,7 @@ struct bd { u32 rsv3:16; }; -/*--------------------------------------------------------------------------*/ -/* Register Debugging Structure */ -/*--------------------------------------------------------------------------*/ - -struct msdc_cfg_reg { - u32 msdc:1; - u32 ckpwn:1; - u32 rst:1; - u32 pio:1; - u32 ckdrven:1; - u32 start18v:1; - u32 pass18v:1; - u32 ckstb:1; - u32 ckdiv:8; - u32 ckmod:2; - u32 pad:14; -}; - -struct msdc_iocon_reg { - u32 sdr104cksel:1; - u32 rsmpl:1; - u32 dsmpl:1; - u32 ddlysel:1; - u32 ddr50ckd:1; - u32 dsplsel:1; - u32 pad1:10; - u32 d0spl:1; - u32 d1spl:1; - u32 d2spl:1; - u32 d3spl:1; - u32 d4spl:1; - u32 d5spl:1; - u32 d6spl:1; - u32 d7spl:1; - u32 riscsz:1; - u32 pad2:7; -}; - -struct msdc_ps_reg { - u32 cden:1; - u32 cdsts:1; - u32 pad1:10; - u32 cddebounce:4; - u32 dat:8; - u32 cmd:1; - u32 pad2:6; - u32 wp:1; -}; - -struct msdc_int_reg { - u32 mmcirq:1; - u32 cdsc:1; - u32 pad1:1; - u32 atocmdrdy:1; - u32 atocmdtmo:1; - u32 atocmdcrc:1; - u32 dmaqempty:1; - u32 sdioirq:1; - u32 cmdrdy:1; - u32 cmdtmo:1; - u32 rspcrc:1; - u32 csta:1; - u32 xfercomp:1; - u32 dxferdone:1; - u32 dattmo:1; - u32 datcrc:1; - u32 atocmd19done:1; - u32 pad2:15; -}; - -struct msdc_inten_reg { - u32 mmcirq:1; - u32 cdsc:1; - u32 pad1:1; - u32 atocmdrdy:1; - u32 atocmdtmo:1; - u32 atocmdcrc:1; - u32 dmaqempty:1; - u32 sdioirq:1; - u32 cmdrdy:1; - u32 cmdtmo:1; - u32 rspcrc:1; - u32 csta:1; - u32 xfercomp:1; - u32 dxferdone:1; - u32 dattmo:1; - u32 datcrc:1; - u32 atocmd19done:1; - u32 pad2:15; -}; - -struct msdc_fifocs_reg { - u32 rxcnt:8; - u32 pad1:8; - u32 txcnt:8; - u32 pad2:7; - u32 clr:1; -}; - -struct msdc_txdat_reg { - u32 val; -}; - -struct msdc_rxdat_reg { - u32 val; -}; - -struct sdc_cfg_reg { - u32 sdiowkup:1; - u32 inswkup:1; - u32 pad1:14; - u32 buswidth:2; - u32 pad2:1; - u32 sdio:1; - u32 sdioide:1; - u32 intblkgap:1; - u32 pad4:2; - u32 dtoc:8; -}; - -struct sdc_cmd_reg { - u32 cmd:6; - u32 brk:1; - u32 rsptyp:3; - u32 pad1:1; - u32 dtype:2; - u32 rw:1; - u32 stop:1; - u32 goirq:1; - u32 blklen:12; - u32 atocmd:2; - u32 volswth:1; - u32 pad2:1; -}; - -struct sdc_arg_reg { - u32 arg; -}; - -struct sdc_sts_reg { - u32 sdcbusy:1; - u32 cmdbusy:1; - u32 pad:29; - u32 swrcmpl:1; -}; - -struct sdc_resp0_reg { - u32 val; -}; - -struct sdc_resp1_reg { - u32 val; -}; - -struct sdc_resp2_reg { - u32 val; -}; - -struct sdc_resp3_reg { - u32 val; -}; - -struct sdc_blknum_reg { - u32 num; -}; - -struct sdc_csts_reg { - u32 sts; -}; - -struct sdc_cstsen_reg { - u32 sts; -}; - -struct sdc_datcrcsts_reg { - u32 datcrcsts:8; - u32 ddrcrcsts:4; - u32 pad:20; -}; - -struct emmc_cfg0_reg { - u32 bootstart:1; - u32 bootstop:1; - u32 bootmode:1; - u32 pad1:9; - u32 bootwaidly:3; - u32 bootsupp:1; - u32 pad2:16; -}; - -struct emmc_cfg1_reg { - u32 bootcrctmc:16; - u32 pad:4; - u32 bootacktmc:12; -}; - -struct emmc_sts_reg { - u32 bootcrcerr:1; - u32 bootackerr:1; - u32 bootdattmo:1; - u32 bootacktmo:1; - u32 bootupstate:1; - u32 bootackrcv:1; - u32 bootdatrcv:1; - u32 pad:25; -}; - -struct emmc_iocon_reg { - u32 bootrst:1; - u32 pad:31; -}; - -struct msdc_acmd_resp_reg { - u32 val; -}; - -struct msdc_acmd19_trg_reg { - u32 tunesel:4; - u32 pad:28; -}; - -struct msdc_acmd19_sts_reg { - u32 val; -}; - -struct msdc_dma_sa_reg { - u32 addr; -}; - -struct msdc_dma_ca_reg { - u32 addr; -}; - -struct msdc_dma_ctrl_reg { - u32 start:1; - u32 stop:1; - u32 resume:1; - u32 pad1:5; - u32 mode:1; - u32 pad2:1; - u32 lastbuf:1; - u32 pad3:1; - u32 brustsz:3; - u32 pad4:1; - u32 xfersz:16; -}; - -struct msdc_dma_cfg_reg { - u32 status:1; - u32 decsen:1; - u32 pad1:2; - u32 bdcsen:1; - u32 gpdcsen:1; - u32 pad2:26; -}; - -struct msdc_dbg_sel_reg { - u32 sel:16; - u32 pad2:16; -}; - -struct msdc_dbg_out_reg { - u32 val; -}; - -struct msdc_pad_ctl0_reg { - u32 clkdrvn:3; - u32 rsv0:1; - u32 clkdrvp:3; - u32 rsv1:1; - u32 clksr:1; - u32 rsv2:7; - u32 clkpd:1; - u32 clkpu:1; - u32 clksmt:1; - u32 clkies:1; - u32 clktdsel:4; - u32 clkrdsel:8; -}; - -struct msdc_pad_ctl1_reg { - u32 cmddrvn:3; - u32 rsv0:1; - u32 cmddrvp:3; - u32 rsv1:1; - u32 cmdsr:1; - u32 rsv2:7; - u32 cmdpd:1; - u32 cmdpu:1; - u32 cmdsmt:1; - u32 cmdies:1; - u32 cmdtdsel:4; - u32 cmdrdsel:8; -}; - -struct msdc_pad_ctl2_reg { - u32 datdrvn:3; - u32 rsv0:1; - u32 datdrvp:3; - u32 rsv1:1; - u32 datsr:1; - u32 rsv2:7; - u32 datpd:1; - u32 datpu:1; - u32 datsmt:1; - u32 daties:1; - u32 dattdsel:4; - u32 datrdsel:8; -}; - -struct msdc_pad_tune_reg { - u32 wrrxdly:3; - u32 pad1:5; - u32 rdrxdly:8; - u32 pad2:16; -}; - -struct msdc_dat_rddly0 { - u32 dat0:5; - u32 rsv0:3; - u32 dat1:5; - u32 rsv1:3; - u32 dat2:5; - u32 rsv2:3; - u32 dat3:5; - u32 rsv3:3; -}; - -struct msdc_dat_rddly1 { - u32 dat4:5; - u32 rsv4:3; - u32 dat5:5; - u32 rsv5:3; - u32 dat6:5; - u32 rsv6:3; - u32 dat7:5; - u32 rsv7:3; -}; - -struct msdc_hw_dbg_reg { - u32 dbg0sel:8; - u32 dbg1sel:6; - u32 pad1:2; - u32 dbg2sel:6; - u32 pad2:2; - u32 dbg3sel:6; - u32 pad3:2; -}; - -struct msdc_version_reg { - u32 val; -}; - -struct msdc_eco_ver_reg { - u32 val; -}; - -struct msdc_regs { - struct msdc_cfg_reg msdc_cfg; /* base+0x00h */ - struct msdc_iocon_reg msdc_iocon; /* base+0x04h */ - struct msdc_ps_reg msdc_ps; /* base+0x08h */ - struct msdc_int_reg msdc_int; /* base+0x0ch */ - struct msdc_inten_reg msdc_inten; /* base+0x10h */ - struct msdc_fifocs_reg msdc_fifocs; /* base+0x14h */ - struct msdc_txdat_reg msdc_txdat; /* base+0x18h */ - struct msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */ - u32 rsv1[4]; - struct sdc_cfg_reg sdc_cfg; /* base+0x30h */ - struct sdc_cmd_reg sdc_cmd; /* base+0x34h */ - struct sdc_arg_reg sdc_arg; /* base+0x38h */ - struct sdc_sts_reg sdc_sts; /* base+0x3ch */ - struct sdc_resp0_reg sdc_resp0; /* base+0x40h */ - struct sdc_resp1_reg sdc_resp1; /* base+0x44h */ - struct sdc_resp2_reg sdc_resp2; /* base+0x48h */ - struct sdc_resp3_reg sdc_resp3; /* base+0x4ch */ - struct sdc_blknum_reg sdc_blknum; /* base+0x50h */ - u32 rsv2[1]; - struct sdc_csts_reg sdc_csts; /* base+0x58h */ - struct sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */ - struct sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */ - u32 rsv3[3]; - struct emmc_cfg0_reg emmc_cfg0; /* base+0x70h */ - struct emmc_cfg1_reg emmc_cfg1; /* base+0x74h */ - struct emmc_sts_reg emmc_sts; /* base+0x78h */ - struct emmc_iocon_reg emmc_iocon; /* base+0x7ch */ - struct msdc_acmd_resp_reg acmd_resp; /* base+0x80h */ - struct msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */ - struct msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */ - u32 rsv4[1]; - struct msdc_dma_sa_reg dma_sa; /* base+0x90h */ - struct msdc_dma_ca_reg dma_ca; /* base+0x94h */ - struct msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */ - struct msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */ - struct msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */ - struct msdc_dbg_out_reg dbg_out; /* base+0xa4h */ - u32 rsv5[2]; - u32 patch0; /* base+0xb0h */ - u32 patch1; /* base+0xb4h */ - u32 rsv6[10]; - struct msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */ - struct msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */ - struct msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */ - struct msdc_pad_tune_reg pad_tune; /* base+0xech */ - struct msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */ - struct msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */ - struct msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */ - u32 rsv7[1]; - struct msdc_version_reg version; /* base+0x100h */ - struct msdc_eco_ver_reg eco_ver; /* base+0x104h */ -}; - struct msdc_dma { - u32 sglen; /* size of scatter list */ - struct scatterlist *sg; /* I/O scatter list */ - u8 mode; /* dma mode */ - struct gpd *gpd; /* pointer to gpd array */ struct bd *bd; /* pointer to bd array */ dma_addr_t gpd_addr; /* the physical address of gpd array */ @@ -947,11 +454,6 @@ struct msdc_host { u32 app_cmd_arg; }; -#define sdr_read8(reg) readb(reg) -#define sdr_read32(reg) readl(reg) -#define sdr_write8(reg, val) writeb(val, reg) -#define sdr_write32(reg, val) writel(val, reg) - static inline void sdr_set_bits(void __iomem *reg, u32 bs) { u32 val = readl(reg); |