diff options
Diffstat (limited to 'drivers/staging/mt7621-pci/pci-mt7621.c')
| -rw-r--r-- | drivers/staging/mt7621-pci/pci-mt7621.c | 930 |
1 files changed, 558 insertions, 372 deletions
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 8371a9cdb164..31310b6fb7db 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -1,33 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ -/************************************************************************** - * - * BRIEF MODULE DESCRIPTION +/* + * BRIEF MODULE DESCRIPTION * PCI init for Ralink RT2880 solution * - * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw) * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * - ************************************************************************** * May 2007 Bruce Chang * Initial Release * @@ -36,13 +13,11 @@ * * May 2011 Bruce Chang * support RT6855/MT7620 PCIe - * - ************************************************************************** */ #include <linux/bitops.h> -#include <linux/clk.h> #include <linux/delay.h> +#include <linux/iopoll.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_address.h> @@ -57,29 +32,44 @@ #include "../../pci/pci.h" -/* - * These functions and structures provide the BIOS scan and mapping of the PCI - * devices. - */ +/* sysctl */ +#define MT7621_CHIP_REV_ID 0x0c +#define RALINK_CLKCFG1 0x30 +#define RALINK_RSTCTRL 0x34 +#define CHIP_REV_MT7621_E2 0x0101 -#define RALINK_PCIE0_CLK_EN BIT(24) -#define RALINK_PCIE1_CLK_EN BIT(25) -#define RALINK_PCIE2_CLK_EN BIT(26) +/* RALINK_RSTCTRL bits */ +#define RALINK_PCIE_RST BIT(23) + +/* MediaTek specific configuration registers */ +#define PCIE_FTS_NUM 0x70c +#define PCIE_FTS_NUM_MASK GENMASK(15, 8) +#define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8) -#define RALINK_PCI_CONFIG_ADDR 0x20 -#define RALINK_PCI_CONFIG_DATA 0x24 -#define RALINK_PCI_MEMBASE 0x28 -#define RALINK_PCI_IOBASE 0x2C -#define RALINK_PCIE0_RST BIT(24) -#define RALINK_PCIE1_RST BIT(25) -#define RALINK_PCIE2_RST BIT(26) +/* rt_sysc_membase relative registers */ +#define RALINK_PCIE_CLK_GEN 0x7c +#define RALINK_PCIE_CLK_GEN1 0x80 +/* Host-PCI bridge registers */ #define RALINK_PCI_PCICFG_ADDR 0x0000 #define RALINK_PCI_PCIMSK_ADDR 0x000C - -#define RT6855_PCIE0_OFFSET 0x2000 -#define RT6855_PCIE1_OFFSET 0x3000 -#define RT6855_PCIE2_OFFSET 0x4000 +#define RALINK_PCI_CONFIG_ADDR 0x0020 +#define RALINK_PCI_CONFIG_DATA 0x0024 +#define RALINK_PCI_MEMBASE 0x0028 +#define RALINK_PCI_IOBASE 0x002C + +/* PCICFG virtual bridges */ +#define MT7621_BR0_MASK GENMASK(19, 16) +#define MT7621_BR1_MASK GENMASK(23, 20) +#define MT7621_BR2_MASK GENMASK(27, 24) +#define MT7621_BR_ALL_MASK GENMASK(27, 16) +#define MT7621_BR0_SHIFT 16 +#define MT7621_BR1_SHIFT 20 +#define MT7621_BR2_SHIFT 24 + +/* PCIe RC control registers */ +#define MT7621_PCIE_OFFSET 0x2000 +#define MT7621_NEXT_PORT 0x1000 #define RALINK_PCI_BAR0SETUP_ADDR 0x0010 #define RALINK_PCI_IMBASEBAR0_ADDR 0x0018 @@ -88,54 +78,105 @@ #define RALINK_PCI_SUBID 0x0038 #define RALINK_PCI_STATUS 0x0050 -#define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000 -#define RALINK_PCIEPHY_P2_CTL_OFFSET 0xA000 - -#define RALINK_PCI_MM_MAP_BASE 0x60000000 +/* Some definition values */ +#define PCIE_REVISION_ID BIT(0) +#define PCIE_CLASS_CODE (0x60400 << 8) +#define PCIE_BAR_MAP_MAX GENMASK(30, 16) +#define PCIE_BAR_ENABLE BIT(0) +#define PCIE_PORT_INT_EN(x) BIT(20 + (x)) +#define PCIE_PORT_CLK_EN(x) BIT(24 + (x)) +#define PCIE_PORT_PERST(x) BIT(1 + (x)) +#define PCIE_PORT_LINKUP BIT(0) + +#define PCIE_CLK_GEN_EN BIT(31) +#define PCIE_CLK_GEN_DIS 0 +#define PCIE_CLK_GEN1_DIS GENMASK(30,24) +#define PCIE_CLK_GEN1_EN (BIT(27) | BIT(25)) #define RALINK_PCI_IO_MAP_BASE 0x1e160000 +#define MEMORY_BASE 0x0 -#define ASSERT_SYSRST_PCIE(val) \ - do { \ - if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101) \ - rt_sysc_m32(0, val, RALINK_RSTCTRL); \ - else \ - rt_sysc_m32(val, 0, RALINK_RSTCTRL); \ - } while (0) -#define DEASSERT_SYSRST_PCIE(val) \ - do { \ - if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101) \ - rt_sysc_m32(val, 0, RALINK_RSTCTRL); \ - else \ - rt_sysc_m32(0, val, RALINK_RSTCTRL); \ - } while (0) - -#define RALINK_CLKCFG1 0x30 -#define RALINK_RSTCTRL 0x34 -#define RALINK_GPIOMODE 0x60 -#define RALINK_PCIE_CLK_GEN 0x7c -#define RALINK_PCIE_CLK_GEN1 0x80 -//RALINK_RSTCTRL bit -#define RALINK_PCIE_RST BIT(23) -#define RALINK_PCI_RST BIT(24) -//RALINK_CLKCFG1 bit -#define RALINK_PCI_CLK_EN BIT(19) -#define RALINK_PCIE_CLK_EN BIT(21) +/* pcie phy related macros */ +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000 +#define RALINK_PCIEPHY_P2_CTL_OFFSET 0xA000 -#define MEMORY_BASE 0x0 -static int pcie_link_status; +#define RG_P0_TO_P1_WIDTH 0x100 + +#define RG_PE1_PIPE_REG 0x02c +#define RG_PE1_PIPE_RST BIT(12) +#define RG_PE1_PIPE_CMD_FRC BIT(4) + +#define RG_PE1_H_LCDDS_REG 0x49c +#define RG_PE1_H_LCDDS_PCW GENMASK(30, 0) +#define RG_PE1_H_LCDDS_PCW_VAL(x) ((0x7fffffff & (x)) << 0) + +#define RG_PE1_FRC_H_XTAL_REG 0x400 +#define RG_PE1_FRC_H_XTAL_TYPE BIT(8) +#define RG_PE1_H_XTAL_TYPE GENMASK(10, 9) +#define RG_PE1_H_XTAL_TYPE_VAL(x) ((0x3 & (x)) << 9) + +#define RG_PE1_FRC_PHY_REG 0x000 +#define RG_PE1_FRC_PHY_EN BIT(4) +#define RG_PE1_PHY_EN BIT(5) + +#define RG_PE1_H_PLL_REG 0x490 +#define RG_PE1_H_PLL_BC GENMASK(23, 22) +#define RG_PE1_H_PLL_BC_VAL(x) ((0x3 & (x)) << 22) +#define RG_PE1_H_PLL_BP GENMASK(21, 18) +#define RG_PE1_H_PLL_BP_VAL(x) ((0xf & (x)) << 18) +#define RG_PE1_H_PLL_IR GENMASK(15, 12) +#define RG_PE1_H_PLL_IR_VAL(x) ((0xf & (x)) << 12) +#define RG_PE1_H_PLL_IC GENMASK(11, 8) +#define RG_PE1_H_PLL_IC_VAL(x) ((0xf & (x)) << 8) +#define RG_PE1_H_PLL_PREDIV GENMASK(7, 6) +#define RG_PE1_H_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6) +#define RG_PE1_PLL_DIVEN GENMASK(3, 1) +#define RG_PE1_PLL_DIVEN_VAL(x) ((0x7 & (x)) << 1) + +#define RG_PE1_H_PLL_FBKSEL_REG 0x4bc +#define RG_PE1_H_PLL_FBKSEL GENMASK(5, 4) +#define RG_PE1_H_PLL_FBKSEL_VAL(x) ((0x3 & (x)) << 4) + +#define RG_PE1_H_LCDDS_SSC_PRD_REG 0x4a4 +#define RG_PE1_H_LCDDS_SSC_PRD GENMASK(15, 0) +#define RG_PE1_H_LCDDS_SSC_PRD_VAL(x) ((0xffff & (x)) << 0) + +#define RG_PE1_H_LCDDS_SSC_DELTA_REG 0x4a8 +#define RG_PE1_H_LCDDS_SSC_DELTA GENMASK(11, 0) +#define RG_PE1_H_LCDDS_SSC_DELTA_VAL(x) ((0xfff & (x)) << 0) +#define RG_PE1_H_LCDDS_SSC_DELTA1 GENMASK(27, 16) +#define RG_PE1_H_LCDDS_SSC_DELTA1_VAL(x) ((0xff & (x)) << 16) + +#define RG_PE1_LCDDS_CLK_PH_INV_REG 0x4a0 +#define RG_PE1_LCDDS_CLK_PH_INV BIT(5) + +#define RG_PE1_H_PLL_BR_REG 0x4ac +#define RG_PE1_H_PLL_BR GENMASK(18, 16) +#define RG_PE1_H_PLL_BR_VAL(x) ((0x7 & (x)) << 16) + +#define RG_PE1_MSTCKDIV_REG 0x414 +#define RG_PE1_MSTCKDIV GENMASK(7, 6) +#define RG_PE1_MSTCKDIV_VAL(x) ((0x3 & (x)) << 6) + +#define RG_PE1_FRC_MSTCKDIV BIT(5) /** * struct mt7621_pcie_port - PCIe port information - * @base: IO mapped register base + * @base: I/O mapped register base * @list: port list * @pcie: pointer to PCIe host info - * @reset: pointer to port reset control + * @phy_reg_offset: offset to related phy registers + * @pcie_rst: pointer to port reset control + * @slot: port slot + * @enabled: indicates if port is enabled */ struct mt7621_pcie_port { void __iomem *base; struct list_head list; struct mt7621_pcie *pcie; - struct reset_control *reset; + u32 phy_reg_offset; + struct reset_control *pcie_rst; + u32 slot; + bool enabled; }; /** @@ -171,6 +212,17 @@ static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg) writel(val, pcie->base + reg); } +static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg) +{ + return readl(port->base + reg); +} + +static inline void pcie_port_write(struct mt7621_pcie_port *port, + u32 val, u32 reg) +{ + writel(val, port->base + reg); +} + static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot, unsigned int func, unsigned int where) { @@ -196,8 +248,7 @@ struct pci_ops mt7621_pci_ops = { .write = pci_generic_config_write, }; -static u32 -read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) +static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) { u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg); @@ -205,8 +256,8 @@ read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) return pcie_read(pcie, RALINK_PCI_CONFIG_DATA); } -static void -write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val) +static void write_config(struct mt7621_pcie *pcie, unsigned int dev, + u32 reg, u32 val) { u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg); @@ -214,125 +265,194 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val) pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA); } -static void -set_pcie_phy(struct mt7621_pcie *pcie, u32 offset, - int start_b, int bits, int val) +static void bypass_pipe_rst(struct mt7621_pcie_port *port) { + struct mt7621_pcie *pcie = port->pcie; + u32 phy_offset = port->phy_reg_offset; + u32 offset = (port->slot != 1) ? + phy_offset + RG_PE1_PIPE_REG : + phy_offset + RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH; u32 reg = pcie_read(pcie, offset); - reg &= ~(((1 << bits) - 1) << start_b); - reg |= val << start_b; + reg &= ~(RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC); + reg |= (RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC); pcie_write(pcie, reg, offset); } -static void -bypass_pipe_rst(struct mt7621_pcie *pcie) -{ - /* PCIe Port 0 */ - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4] - /* PCIe Port 1 */ - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01); // rg_pe1_pipe_rst_b - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4] - /* PCIe Port 2 */ - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4] -} - -static void -set_phy_for_ssc(struct mt7621_pcie *pcie) +static void set_phy_for_ssc(struct mt7621_pcie_port *port) { - unsigned long reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); + struct mt7621_pcie *pcie = port->pcie; + struct device *dev = pcie->dev; + u32 phy_offset = port->phy_reg_offset; + u32 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); + u32 offset; + u32 val; reg = (reg >> 6) & 0x7; - /* Set PCIe Port0 & Port1 PHY to disable SSC */ + /* Set PCIe Port PHY to disable SSC */ /* Debug Xtal Type */ - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable - if (reg <= 5 && reg >= 3) { // 40MHz Xtal - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) - printk("***** Xtal 40MHz *****\n"); - } else { // 25MHz | 20MHz Xtal - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) + offset = phy_offset + RG_PE1_FRC_H_XTAL_REG; + val = pcie_read(pcie, offset); + val &= ~(RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE); + val |= RG_PE1_FRC_H_XTAL_TYPE; + val |= RG_PE1_H_XTAL_TYPE_VAL(0x00); + pcie_write(pcie, val, offset); + + /* disable port */ + offset = (port->slot != 1) ? + phy_offset + RG_PE1_FRC_PHY_REG : + phy_offset + RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH; + val = pcie_read(pcie, offset); + val &= ~(RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN); + val |= RG_PE1_FRC_PHY_EN; + pcie_write(pcie, val, offset); + + /* Set Pre-divider ratio (for host mode) */ + offset = phy_offset + RG_PE1_H_PLL_REG; + val = pcie_read(pcie, offset); + val &= ~(RG_PE1_H_PLL_PREDIV); + + if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */ + val |= RG_PE1_H_PLL_PREDIV_VAL(0x01); + pcie_write(pcie, val, offset); + dev_info(dev, "Xtal is 40MHz\n"); + } else { /* 25MHz | 20MHz Xtal */ + val |= RG_PE1_H_PLL_PREDIV_VAL(0x00); + pcie_write(pcie, val, offset); if (reg >= 6) { - printk("***** Xtal 25MHz *****\n"); - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0, 31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode) - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial + dev_info(dev, "Xtal is 25MHz\n"); + + /* Select feedback clock */ + offset = phy_offset + RG_PE1_H_PLL_FBKSEL_REG; + val = pcie_read(pcie, offset); + val &= ~(RG_PE1_H_PLL_FBKSEL); + val |= RG_PE1_H_PLL_FBKSEL_VAL(0x01); + pcie_write(pcie, val, offset); + + /* DDS NCPO PCW (for host mode) */ + offset = phy_offset + RG_PE1_H_LCDDS_SSC_PRD_REG; + val = pcie_read(pcie, offset); + val &= ~(RG_PE1_H_LCDDS_SSC_PRD); + val |= RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18000000); + pcie_write(pcie, val, offset); + + /* DDS SSC dither period control */ + offset = phy_offset + RG_PE1_H_LCDDS_SSC_PRD_REG; + val = pcie_read(pcie, offset); + val &= ~(RG_PE1_H_LCDDS_SSC_PRD); + val |= RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18d); + pcie_write(pcie, val, offset); + + /* DDS SSC dither amplitude control */ + offset = phy_offset + RG_PE1_H_LCDDS_SSC_DELTA_REG; + val = pcie_read(pcie, offset); + val &= ~(RG_PE1_H_LCDDS_SSC_DELTA | + RG_PE1_H_LCDDS_SSC_DELTA1); + val |= RG_PE1_H_LCDDS_SSC_DELTA_VAL(0x4a); + val |= RG_PE1_H_LCDDS_SSC_DELTA1_VAL(0x4a); + pcie_write(pcie, val, offset); } else { - printk("***** Xtal 20MHz *****\n"); + dev_info(dev, "Xtal is 20MHz\n"); } } - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN - if (reg <= 5 && reg >= 3) { // 40MHz Xtal - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv - } - /* Enable PHY and disable force mode */ - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control - set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control - /* Set PCIe Port2 PHY to disable SSC */ - /* Debug Xtal Type */ - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable - if (reg <= 5 && reg >= 3) { // 40MHz Xtal - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) - } else { // 25MHz | 20MHz Xtal - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) - if (reg >= 6) { // 25MHz Xtal - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0, 31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode) - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial - } - } - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN - if (reg <= 5 && reg >= 3) { // 40MHz Xtal - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv + /* DDS clock inversion */ + offset = phy_offset + RG_PE1_LCDDS_CLK_PH_INV_REG; + val = pcie_read(pcie, offset); + val &= ~(RG_PE1_LCDDS_CLK_PH_INV); + val |= RG_PE1_LCDDS_CLK_PH_INV; + pcie_write(pcie, val, offset); + + /* Set PLL bits */ + offset = phy_offset + RG_PE1_H_PLL_REG; + val = pcie_read(pcie, offset); + val &= ~(RG_PE1_H_PLL_BC | RG_PE1_H_PLL_BP | RG_PE1_H_PLL_IR | + RG_PE1_H_PLL_IC | RG_PE1_PLL_DIVEN); + val |= RG_PE1_H_PLL_BC_VAL(0x02); + val |= RG_PE1_H_PLL_BP_VAL(0x06); + val |= RG_PE1_H_PLL_IR_VAL(0x02); + val |= RG_PE1_H_PLL_IC_VAL(0x01); + val |= RG_PE1_PLL_DIVEN_VAL(0x02); + pcie_write(pcie, val, offset); + + offset = phy_offset + RG_PE1_H_PLL_BR_REG; + val = pcie_read(pcie, offset); + val &= ~(RG_PE1_H_PLL_BR); + val |= RG_PE1_H_PLL_BR_VAL(0x00); + pcie_write(pcie, val, offset); + + if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */ + /* set force mode enable of da_pe1_mstckdiv */ + offset = phy_offset + RG_PE1_MSTCKDIV_REG; + val = pcie_read(pcie, offset); + val &= ~(RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV); + val |= (RG_PE1_MSTCKDIV_VAL(0x01) | RG_PE1_FRC_MSTCKDIV); + pcie_write(pcie, val, offset); } + /* Enable PHY and disable force mode */ - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable - set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control + offset = (port->slot != 1) ? + phy_offset + RG_PE1_FRC_PHY_REG : + phy_offset + RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH; + val = pcie_read(pcie, offset); + val &= ~(RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN); + val |= (RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN); + pcie_write(pcie, val, offset); +} + +static void mt7621_enable_phy(struct mt7621_pcie_port *port) +{ + u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID); + + if ((chip_rev_id & 0xFFFF) == CHIP_REV_MT7621_E2) + bypass_pipe_rst(port); + set_phy_for_ssc(port); +} + +static inline void mt7621_control_assert(struct mt7621_pcie_port *port) +{ + u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID); + + if ((chip_rev_id & 0xFFFF) == CHIP_REV_MT7621_E2) + reset_control_assert(port->pcie_rst); + else + reset_control_deassert(port->pcie_rst); +} + +static inline void mt7621_control_deassert(struct mt7621_pcie_port *port) +{ + u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID); + + if ((chip_rev_id & 0xFFFF) == CHIP_REV_MT7621_E2) + reset_control_deassert(port->pcie_rst); + else + reset_control_assert(port->pcie_rst); } -static void setup_cm_memory_region(struct resource *mem_resource) +static void mt7621_reset_port(struct mt7621_pcie_port *port) { + mt7621_control_assert(port); + msleep(100); + mt7621_control_deassert(port); +} + +static void setup_cm_memory_region(struct mt7621_pcie *pcie) +{ + struct resource *mem_resource = &pcie->mem; + struct device *dev = pcie->dev; resource_size_t mask; if (mips_cps_numiocu(0)) { - /* FIXME: hardware doesn't accept mask values with 1s after + /* + * FIXME: hardware doesn't accept mask values with 1s after * 0s (e.g. 0xffef), so it would be great to warn if that's - * about to happen */ + * about to happen + */ mask = ~(mem_resource->end - mem_resource->start); write_gcr_reg1_base(mem_resource->start); write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0); - printk("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n", + dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n", (unsigned long long)read_gcr_reg1_base(), (unsigned long long)read_gcr_reg1_mask()); } @@ -382,10 +502,54 @@ static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie) return 0; } +static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie, + struct device_node *node, + int slot) +{ + struct mt7621_pcie_port *port; + struct device *dev = pcie->dev; + struct device_node *pnode = dev->of_node; + struct resource regs; + char name[6]; + int err; + + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + err = of_address_to_resource(pnode, slot + 1, ®s); + if (err) { + dev_err(dev, "missing \"reg\" property\n"); + return err; + } + + port->base = devm_ioremap_resource(dev, ®s); + if (IS_ERR(port->base)) + return PTR_ERR(port->base); + + snprintf(name, sizeof(name), "pcie%d", slot); + port->pcie_rst = devm_reset_control_get_exclusive(dev, name); + if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) { + dev_err(dev, "failed to get pcie%d reset control\n", slot); + return PTR_ERR(port->pcie_rst); + } + + port->slot = slot; + port->pcie = pcie; + port->phy_reg_offset = (slot != 2) ? + RALINK_PCIEPHY_P0P1_CTL_OFFSET : + RALINK_PCIEPHY_P2_CTL_OFFSET; + + INIT_LIST_HEAD(&port->list); + list_add_tail(&port->list, &pcie->ports); + + return 0; +} + static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie) { struct device *dev = pcie->dev; - struct device_node *node = dev->of_node; + struct device_node *node = dev->of_node, *child; struct resource regs; int err; @@ -399,6 +563,215 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie) if (IS_ERR(pcie->base)) return PTR_ERR(pcie->base); + for_each_available_child_of_node(node, child) { + int slot; + + err = of_pci_get_devfn(child); + if (err < 0) { + dev_err(dev, "failed to parse devfn: %d\n", err); + return err; + } + + slot = PCI_SLOT(err); + + err = mt7621_pcie_parse_port(pcie, child, slot); + if (err) + return err; + } + + return 0; +} + +static int mt7621_pcie_init_port(struct mt7621_pcie_port *port) +{ + struct mt7621_pcie *pcie = port->pcie; + struct device *dev = pcie->dev; + u32 slot = port->slot; + u32 val = 0; + + /* + * Any MT7621 Ralink pcie controller that doesn't have 0x0101 at + * the end of the chip_id has inverted PCI resets. + */ + mt7621_reset_port(port); + + val = read_config(pcie, slot, PCIE_FTS_NUM); + dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot); + + if ((pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) == 0) { + dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", slot); + mt7621_control_assert(port); + rt_sysc_m32(PCIE_PORT_CLK_EN(slot), 0, RALINK_CLKCFG1); + port->enabled = false; + } else { + port->enabled = true; + } + + mt7621_enable_phy(port); + + return 0; +} + +static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie) +{ + struct device *dev = pcie->dev; + struct mt7621_pcie_port *port, *tmp; + int err; + + list_for_each_entry_safe(port, tmp, &pcie->ports, list) { + u32 slot = port->slot; + + err = mt7621_pcie_init_port(port); + if (err) { + dev_err(dev, "Initiating port %d failed\n", slot); + list_del(&port->list); + } + } + + rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL); + rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1); + rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN); + rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1); + rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN); + msleep(50); + rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL); +} + +static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port) +{ + struct mt7621_pcie *pcie = port->pcie; + u32 slot = port->slot; + u32 offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT); + u32 val; + int err; + + /* assert port PERST_N */ + val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); + val |= PCIE_PORT_PERST(slot); + pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); + + /* de-assert port PERST_N */ + val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); + val &= ~PCIE_PORT_PERST(slot); + pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); + + /* 100ms timeout value should be enough for Gen1 training */ + err = readl_poll_timeout(port->base + RALINK_PCI_STATUS, + val, !!(val & PCIE_PORT_LINKUP), + 20, 100 * USEC_PER_MSEC); + if (err) + return -ETIMEDOUT; + + /* enable pcie interrupt */ + val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR); + val |= PCIE_PORT_INT_EN(slot); + pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR); + + /* map 2G DDR region */ + pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, + offset + RALINK_PCI_BAR0SETUP_ADDR); + pcie_write(pcie, MEMORY_BASE, + offset + RALINK_PCI_IMBASEBAR0_ADDR); + + /* configure class code and revision ID */ + pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID, + offset + RALINK_PCI_CLASS); + + return 0; +} + +static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie) +{ + struct device *dev = pcie->dev; + struct mt7621_pcie_port *port; + u8 num_slots_enabled = 0; + u32 slot; + u32 val; + + list_for_each_entry(port, &pcie->ports, list) { + if (port->enabled) { + if (!mt7621_pcie_enable_port(port)) { + dev_err(dev, "de-assert port %d PERST_N\n", + port->slot); + continue; + } + dev_info(dev, "PCIE%d enabled\n", slot); + num_slots_enabled++; + } + } + + for (slot = 0; slot < num_slots_enabled; slot++) { + val = read_config(pcie, slot, 0x4); + write_config(pcie, slot, 0x4, val | 0x4); + /* configure RC FTS number to 250 when it leaves L0s */ + val = read_config(pcie, slot, PCIE_FTS_NUM); + val &= ~PCIE_FTS_NUM_MASK; + val |= PCIE_FTS_NUM_L0(0x50); + write_config(pcie, slot, PCIE_FTS_NUM, val); + } +} + +static int mt7621_pcie_init_virtual_bridges(struct mt7621_pcie *pcie) +{ + u32 pcie_link_status = 0; + u32 val= 0; + struct mt7621_pcie_port *port; + + list_for_each_entry(port, &pcie->ports, list) { + u32 slot = port->slot; + + if (port->enabled) + pcie_link_status |= BIT(slot); + } + + if (pcie_link_status == 0) + return -1; + + /* + * pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num + * 3'b000 x x x + * 3'b001 x x 0 + * 3'b010 x 0 x + * 3'b011 x 1 0 + * 3'b100 0 x x + * 3'b101 1 x 0 + * 3'b110 1 0 x + * 3'b111 2 1 0 + */ + switch (pcie_link_status) { + case 2: + val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); + val &= ~(MT7621_BR0_MASK | MT7621_BR1_MASK); + val |= 0x1 << MT7621_BR0_SHIFT; + val |= 0x0 << MT7621_BR1_SHIFT; + pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); + break; + case 4: + val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); + val &= ~MT7621_BR_ALL_MASK; + val |= 0x1 << MT7621_BR0_SHIFT; + val |= 0x2 << MT7621_BR1_SHIFT; + val |= 0x0 << MT7621_BR2_SHIFT; + pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); + break; + case 5: + val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); + val &= ~MT7621_BR_ALL_MASK; + val |= 0x0 << MT7621_BR0_SHIFT; + val |= 0x2 << MT7621_BR1_SHIFT; + val |= 0x1 << MT7621_BR2_SHIFT; + pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); + break; + case 6: + val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); + val &= ~MT7621_BR_ALL_MASK; + val |= 0x2 << MT7621_BR0_SHIFT; + val |= 0x0 << MT7621_BR1_SHIFT; + val |= 0x1 << MT7621_BR2_SHIFT; + pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); + break; + } + return 0; } @@ -441,7 +814,6 @@ static int mt7621_pci_probe(struct platform_device *pdev) struct mt7621_pcie *pcie; struct pci_host_bridge *bridge; int err; - u32 val = 0; LIST_HEAD(res); if (!dev->of_node) @@ -449,7 +821,7 @@ static int mt7621_pci_probe(struct platform_device *pdev) bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); if (!bridge) - return -ENODEV; + return -ENOMEM; pcie = pci_host_bridge_priv(bridge); pcie->dev = dev; @@ -468,204 +840,18 @@ static int mt7621_pci_probe(struct platform_device *pdev) ioport_resource.start = 0; ioport_resource.end = ~0UL; /* no limit */ - val = RALINK_PCIE0_RST; - val |= RALINK_PCIE1_RST; - val |= RALINK_PCIE2_RST; - - ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST); - - *(unsigned int *)(0xbe000060) &= ~(0x3 << 10 | 0x3 << 3); - *(unsigned int *)(0xbe000060) |= BIT(10) | BIT(3); - mdelay(100); - *(unsigned int *)(0xbe000600) |= BIT(19) | BIT(8) | BIT(7); // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3) - mdelay(100); - *(unsigned int *)(0xbe000620) &= ~(BIT(19) | BIT(8) | BIT(7)); // clear DATA - - mdelay(100); - - val = RALINK_PCIE0_RST; - val |= RALINK_PCIE1_RST; - val |= RALINK_PCIE2_RST; - - DEASSERT_SYSRST_PCIE(val); + mt7621_pcie_init_ports(pcie); - if ((*(unsigned int *)(0xbe00000c) & 0xFFFF) == 0x0101) // MT7621 E2 - bypass_pipe_rst(pcie); - set_phy_for_ssc(pcie); - - list_for_each_entry_safe(port, tmp, &pcie->ports, list) { - u32 slot = port->slot; - val = read_config(pcie, slot, 0x70c); - dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot); - } - - rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL); - rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1); - - rt_sysc_m32(0x80000000, 0, RALINK_PCIE_CLK_GEN); - rt_sysc_m32(0x7f000000, 0xa << 24, RALINK_PCIE_CLK_GEN1); - rt_sysc_m32(0, 0x80000000, RALINK_PCIE_CLK_GEN); - - mdelay(50); - rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL); - - /* Use GPIO control instead of PERST_N */ - *(unsigned int *)(0xbe000620) |= BIT(19) | BIT(8) | BIT(7); // set DATA - mdelay(1000); - - if ((pcie_read(pcie, RT6855_PCIE0_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) { - printk("PCIE0 no card, disable it(RST&CLK)\n"); - ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST); - rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1); - pcie_link_status &= ~(BIT(0)); - } else { - pcie_link_status |= BIT(0); - val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR); - val |= BIT(20); // enable pcie1 interrupt - pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR); - } - - if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) { - printk("PCIE1 no card, disable it(RST&CLK)\n"); - ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST); - rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1); - pcie_link_status &= ~(BIT(1)); - } else { - pcie_link_status |= BIT(1); - val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR); - val |= BIT(21); // enable pcie1 interrupt - pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR); - } - - if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) { - printk("PCIE2 no card, disable it(RST&CLK)\n"); - ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST); - rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RALINK_CLKCFG1); - pcie_link_status &= ~(BIT(2)); - } else { - pcie_link_status |= BIT(2); - val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR); - val |= BIT(22); // enable pcie2 interrupt - pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR); - } - - if (pcie_link_status == 0) + err = mt7621_pcie_init_virtual_bridges(pcie); + if (err) { + dev_err(dev, "Nothing is connected in virtual bridges. Exiting..."); return 0; - -/* -pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num -3'b000 x x x -3'b001 x x 0 -3'b010 x 0 x -3'b011 x 1 0 -3'b100 0 x x -3'b101 1 x 0 -3'b110 1 0 x -3'b111 2 1 0 -*/ - switch (pcie_link_status) { - case 2: - val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); - val &= ~0x00ff0000; - val |= 0x1 << 16; // port 0 - val |= 0x0 << 20; // port 1 - pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); - break; - case 4: - val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); - val &= ~0x0fff0000; - val |= 0x1 << 16; //port0 - val |= 0x2 << 20; //port1 - val |= 0x0 << 24; //port2 - pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); - break; - case 5: - val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); - val &= ~0x0fff0000; - val |= 0x0 << 16; //port0 - val |= 0x2 << 20; //port1 - val |= 0x1 << 24; //port2 - pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); - break; - case 6: - val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); - val &= ~0x0fff0000; - val |= 0x2 << 16; //port0 - val |= 0x0 << 20; //port1 - val |= 0x1 << 24; //port2 - pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); - break; } -/* - ioport_resource.start = mt7621_res_pci_io1.start; - ioport_resource.end = mt7621_res_pci_io1.end; -*/ - pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE); pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE); - //PCIe0 - if ((pcie_link_status & 0x1) != 0) { - /* open 7FFF:2G; ENABLE */ - pcie_write(pcie, 0x7FFF0001, - RT6855_PCIE0_OFFSET + RALINK_PCI_BAR0SETUP_ADDR); - pcie_write(pcie, MEMORY_BASE, - RT6855_PCIE0_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR); - pcie_write(pcie, 0x06040001, - RT6855_PCIE0_OFFSET + RALINK_PCI_CLASS); - printk("PCIE0 enabled\n"); - } - - //PCIe1 - if ((pcie_link_status & 0x2) != 0) { - /* open 7FFF:2G; ENABLE */ - pcie_write(pcie, 0x7FFF0001, - RT6855_PCIE1_OFFSET + RALINK_PCI_BAR0SETUP_ADDR); - pcie_write(pcie, MEMORY_BASE, - RT6855_PCIE1_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR); - pcie_write(pcie, 0x06040001, - RT6855_PCIE1_OFFSET + RALINK_PCI_CLASS); - printk("PCIE1 enabled\n"); - } - - //PCIe2 - if ((pcie_link_status & 0x4) != 0) { - /* open 7FFF:2G; ENABLE */ - pcie_write(pcie, 0x7FFF0001, - RT6855_PCIE2_OFFSET + RALINK_PCI_BAR0SETUP_ADDR); - pcie_write(pcie, MEMORY_BASE, - RT6855_PCIE2_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR); - pcie_write(pcie, 0x06040001, - RT6855_PCIE2_OFFSET + RALINK_PCI_CLASS); - printk("PCIE2 enabled\n"); - } - - switch (pcie_link_status) { - case 7: - val = read_config(pcie, 2, 0x4); - write_config(pcie, 2, 0x4, val | 0x4); - val = read_config(pcie, 2, 0x70c); - val &= ~(0xff) << 8; - val |= 0x50 << 8; - write_config(pcie, 2, 0x70c, val); - case 3: - case 5: - case 6: - val = read_config(pcie, 1, 0x4); - write_config(pcie, 1, 0x4, val | 0x4); - val = read_config(pcie, 1, 0x70c); - val &= ~(0xff) << 8; - val |= 0x50 << 8; - write_config(pcie, 1, 0x70c, val); - default: - val = read_config(pcie, 0, 0x4); - write_config(pcie, 0, 0x4, val | 0x4); //bus master enable - val = read_config(pcie, 0, 0x70c); - val &= ~(0xff) << 8; - val |= 0x50 << 8; - write_config(pcie, 0, 0x70c, val); - } + mt7621_pcie_enable_ports(pcie); err = mt7621_pci_parse_request_of_pci_ranges(pcie); if (err) { @@ -673,7 +859,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num return err; } - setup_cm_memory_region(&pcie->mem); + setup_cm_memory_region(pcie); err = mt7621_pcie_request_resources(pcie, &res); if (err) { |