diff options
Diffstat (limited to 'drivers/staging/r8188eu/hal/rtl8188e_phycfg.c')
-rw-r--r-- | drivers/staging/r8188eu/hal/rtl8188e_phycfg.c | 197 |
1 files changed, 44 insertions, 153 deletions
diff --git a/drivers/staging/r8188eu/hal/rtl8188e_phycfg.c b/drivers/staging/r8188eu/hal/rtl8188e_phycfg.c index bb0cda0c16a0..302b15b2874d 100644 --- a/drivers/staging/r8188eu/hal/rtl8188e_phycfg.c +++ b/drivers/staging/r8188eu/hal/rtl8188e_phycfg.c @@ -143,7 +143,7 @@ phy_RFSerialRead( ) { u32 retValue = 0; - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8188e *pHalData = &Adapter->haldata; struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef[eRFPath]; u32 NewOffset; u32 tmplong, tmplong2; @@ -161,31 +161,31 @@ phy_RFSerialRead( /* For 92S LSSI Read RFLSSIRead */ /* For RF A/B write 0x824/82c(does not work in the future) */ /* We must use 0x824 for RF A and B to execute read trigger */ - tmplong = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord); + tmplong = rtl8188e_PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord); if (eRFPath == RF_PATH_A) tmplong2 = tmplong; else - tmplong2 = PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord); + tmplong2 = rtl8188e_PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord); tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /* T65 RF */ - PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong & (~bLSSIReadEdge)); + rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong & (~bLSSIReadEdge)); udelay(10);/* PlatformStallExecution(10); */ - PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2); + rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2); udelay(100);/* PlatformStallExecution(100); */ udelay(10);/* PlatformStallExecution(10); */ if (eRFPath == RF_PATH_A) - RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT(8)); + RfPiEnable = (u8)rtl8188e_PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT(8)); else if (eRFPath == RF_PATH_B) - RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT(8)); + RfPiEnable = (u8)rtl8188e_PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT(8)); if (RfPiEnable) { /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */ - retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData); + retValue = rtl8188e_PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData); } else { /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */ - retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); + retValue = rtl8188e_PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); } return retValue; } @@ -242,7 +242,7 @@ phy_RFSerialWrite( ) { u32 DataAndAddr = 0; - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8188e *pHalData = &Adapter->haldata; struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef[eRFPath]; u32 NewOffset; @@ -263,7 +263,7 @@ phy_RFSerialWrite( /* */ /* Write Operation */ /* */ - PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); + rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); } /** @@ -355,7 +355,7 @@ rtl8188e_PHY_SetRFReg( *---------------------------------------------------------------------------*/ s32 PHY_MACConfig8188E(struct adapter *Adapter) { - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8188e *pHalData = &Adapter->haldata; int rtStatus = _SUCCESS; /* */ @@ -387,19 +387,15 @@ phy_InitBBRFRegisterDefinition( struct adapter *Adapter ) { - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8188e *pHalData = &Adapter->haldata; /* RF Interface Sowrtware Control */ pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */ pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ - pHalData->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;/* 16 LSBs if read 32-bit from 0x874 */ - pHalData->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;/* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ /* RF Interface Readback Value */ pHalData->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; /* 16 LSBs if read 32-bit from 0x8E0 */ pHalData->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;/* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ - pHalData->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;/* 16 LSBs if read 32-bit from 0x8E4 */ - pHalData->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;/* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ /* RF Interface Output (and Enable) */ pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */ @@ -416,14 +412,10 @@ phy_InitBBRFRegisterDefinition( /* RF parameter */ pHalData->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; /* BB Band Select */ pHalData->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; - pHalData->PHYRegDef[RF_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; - pHalData->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ pHalData->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */ pHalData->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */ - pHalData->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */ - pHalData->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */ /* Tranceiver A~D HSSI Parameter-1 */ pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; /* wire control parameter1 */ @@ -436,50 +428,34 @@ phy_InitBBRFRegisterDefinition( /* RF switch Control */ pHalData->PHYRegDef[RF_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; /* TR/Ant switch control */ pHalData->PHYRegDef[RF_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; - pHalData->PHYRegDef[RF_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; - pHalData->PHYRegDef[RF_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; /* AGC control 1 */ pHalData->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; pHalData->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; - pHalData->PHYRegDef[RF_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; - pHalData->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; /* AGC control 2 */ pHalData->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; pHalData->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; - pHalData->PHYRegDef[RF_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; - pHalData->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; /* RX AFE control 1 */ pHalData->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; pHalData->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; - pHalData->PHYRegDef[RF_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; - pHalData->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; /* RX AFE control 1 */ pHalData->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE; pHalData->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; - pHalData->PHYRegDef[RF_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; - pHalData->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; /* Tx AFE control 1 */ pHalData->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; pHalData->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; - pHalData->PHYRegDef[RF_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; - pHalData->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; /* Tx AFE control 2 */ pHalData->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE; pHalData->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; - pHalData->PHYRegDef[RF_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; - pHalData->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; /* Tranceiver LSSI Readback SI mode */ pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; - pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; - pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; /* Tranceiver LSSI Readback PI mode */ pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback; @@ -488,7 +464,7 @@ phy_InitBBRFRegisterDefinition( void storePwrIndexDiffRateOffset(struct adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data) { - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8188e *pHalData = &Adapter->haldata; if (RegAddr == rTxAGC_A_Rate18_06) pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data; @@ -506,8 +482,7 @@ void storePwrIndexDiffRateOffset(struct adapter *Adapter, u32 RegAddr, u32 BitMa pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data; if (RegAddr == rTxAGC_A_Mcs15_Mcs12) { pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data; - if (pHalData->rf_type == RF_1T1R) - pHalData->pwrGroupCnt++; + pHalData->pwrGroupCnt++; } if (RegAddr == rTxAGC_B_Rate18_06) pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data; @@ -523,17 +498,14 @@ void storePwrIndexDiffRateOffset(struct adapter *Adapter, u32 RegAddr, u32 BitMa pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data; if (RegAddr == rTxAGC_B_Mcs11_Mcs08) pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data; - if (RegAddr == rTxAGC_B_Mcs15_Mcs12) { + if (RegAddr == rTxAGC_B_Mcs15_Mcs12) pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data; - if (pHalData->rf_type != RF_1T1R) - pHalData->pwrGroupCnt++; - } } static int phy_BB8188E_Config_ParaFile(struct adapter *Adapter) { struct eeprom_priv *pEEPROM = &Adapter->eeprompriv; - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8188e *pHalData = &Adapter->haldata; int rtStatus = _SUCCESS; /* */ @@ -574,7 +546,7 @@ PHY_BBConfig8188E( ) { int rtStatus = _SUCCESS; - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8188e *pHalData = &Adapter->haldata; u32 RegVal; u8 CrystalCap; @@ -595,7 +567,7 @@ PHY_BBConfig8188E( /* write 0x24[16:11] = 0x24[22:17] = CrystalCap */ CrystalCap = pHalData->CrystalCap & 0x3F; - PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6))); + rtl8188e_PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6))); return rtStatus; } @@ -613,82 +585,25 @@ static void getTxPowerIndex88E(struct adapter *Adapter, u8 channel, u8 *cckPower u8 *ofdmPowerLevel, u8 *BW20PowerLevel, u8 *BW40PowerLevel) { - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8188e *pHalData = &Adapter->haldata; u8 index = (channel - 1); - u8 TxCount = 0, path_nums; - if ((RF_1T2R == pHalData->rf_type) || (RF_1T1R == pHalData->rf_type)) - path_nums = 1; - else - path_nums = 2; - - for (TxCount = 0; TxCount < path_nums; TxCount++) { - if (TxCount == RF_PATH_A) { - /* 1. CCK */ - cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index]; - /* 2. OFDM */ - ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index] + - pHalData->OFDM_24G_Diff[TxCount][RF_PATH_A]; - /* 1. BW20 */ - BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index] + - pHalData->BW20_24G_Diff[TxCount][RF_PATH_A]; - /* 2. BW40 */ - BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index]; - } else if (TxCount == RF_PATH_B) { - /* 1. CCK */ - cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index]; - /* 2. OFDM */ - ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index] + - pHalData->BW20_24G_Diff[RF_PATH_A][index] + - pHalData->BW20_24G_Diff[TxCount][index]; - /* 1. BW20 */ - BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index] + - pHalData->BW20_24G_Diff[TxCount][RF_PATH_A] + - pHalData->BW20_24G_Diff[TxCount][index]; - /* 2. BW40 */ - BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index]; - } else if (TxCount == RF_PATH_C) { - /* 1. CCK */ - cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index]; - /* 2. OFDM */ - ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index] + - pHalData->BW20_24G_Diff[RF_PATH_A][index] + - pHalData->BW20_24G_Diff[RF_PATH_B][index] + - pHalData->BW20_24G_Diff[TxCount][index]; - /* 1. BW20 */ - BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index] + - pHalData->BW20_24G_Diff[RF_PATH_A][index] + - pHalData->BW20_24G_Diff[RF_PATH_B][index] + - pHalData->BW20_24G_Diff[TxCount][index]; - /* 2. BW40 */ - BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index]; - } else if (TxCount == RF_PATH_D) { - /* 1. CCK */ - cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index]; - /* 2. OFDM */ - ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index] + - pHalData->BW20_24G_Diff[RF_PATH_A][index] + - pHalData->BW20_24G_Diff[RF_PATH_B][index] + - pHalData->BW20_24G_Diff[RF_PATH_C][index] + - pHalData->BW20_24G_Diff[TxCount][index]; - - /* 1. BW20 */ - BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index] + - pHalData->BW20_24G_Diff[RF_PATH_A][index] + - pHalData->BW20_24G_Diff[RF_PATH_B][index] + - pHalData->BW20_24G_Diff[RF_PATH_C][index] + - pHalData->BW20_24G_Diff[TxCount][index]; - - /* 2. BW40 */ - BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index]; - } - } + /* 1. CCK */ + cckPowerLevel[RF_PATH_A] = pHalData->Index24G_CCK_Base[index]; + /* 2. OFDM */ + ofdmPowerLevel[RF_PATH_A] = pHalData->Index24G_BW40_Base[index] + + pHalData->OFDM_24G_Diff[RF_PATH_A]; + /* 1. BW20 */ + BW20PowerLevel[RF_PATH_A] = pHalData->Index24G_BW40_Base[index] + + pHalData->BW20_24G_Diff[RF_PATH_A]; + /* 2. BW40 */ + BW40PowerLevel[RF_PATH_A] = pHalData->Index24G_BW40_Base[index]; } static void phy_PowerIndexCheck88E(struct adapter *Adapter, u8 channel, u8 *cckPowerLevel, u8 *ofdmPowerLevel, u8 *BW20PowerLevel, u8 *BW40PowerLevel) { - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8188e *pHalData = &Adapter->haldata; pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0]; pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0]; @@ -752,17 +667,10 @@ _PHY_SetBWMode92C( struct adapter *Adapter ) { - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8188e *pHalData = &Adapter->haldata; u8 regBwOpMode; u8 regRRSR_RSC; - if (pHalData->rf_chip == RF_PSEUDO_11N) - return; - - /* There is no 40MHz mode in RF_8225. */ - if (pHalData->rf_chip == RF_8225) - return; - if (Adapter->bDriverStopped) return; @@ -796,17 +704,17 @@ _PHY_SetBWMode92C( switch (pHalData->CurrentChannelBW) { /* 20 MHz channel*/ case HT_CHANNEL_WIDTH_20: - PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); - PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0); + rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); + rtl8188e_PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0); break; /* 40 MHz channel*/ case HT_CHANNEL_WIDTH_40: - PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); - PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1); + rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); + rtl8188e_PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1); /* Set Control channel to upper or lower. These settings are required only for 40MHz */ - PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1)); - PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC); - PHY_SetBBReg(Adapter, 0x818, (BIT(26) | BIT(27)), + rtl8188e_PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1)); + rtl8188e_PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC); + rtl8188e_PHY_SetBBReg(Adapter, 0x818, (BIT(26) | BIT(27)), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); break; default: @@ -814,21 +722,7 @@ _PHY_SetBWMode92C( } /* Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 */ - /* 3<3>Set RF related register */ - switch (pHalData->rf_chip) { - case RF_8225: - break; - case RF_8256: - /* Please implement this function in Hal8190PciPhy8256.c */ - break; - case RF_PSEUDO_11N: - break; - case RF_6052: - rtl8188e_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW); - break; - default: - break; - } + rtl8188e_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW); } /*----------------------------------------------------------------------------- @@ -848,7 +742,7 @@ _PHY_SetBWMode92C( void PHY_SetBWMode8188E(struct adapter *Adapter, enum ht_channel_width Bandwidth, /* 20M or 40M */ unsigned char Offset) /* Upper, Lower, or Don't care */ { - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8188e *pHalData = &Adapter->haldata; enum ht_channel_width tmpBW = pHalData->CurrentChannelBW; pHalData->CurrentChannelBW = Bandwidth; @@ -865,7 +759,7 @@ static void _PHY_SwChnl8192C(struct adapter *Adapter, u8 channel) { u8 eRFPath = 0; u32 param1, param2; - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8188e *pHalData = &Adapter->haldata; if (Adapter->bNotifyChannelChange) DBG_88E("[%s] ch = %d\n", __func__, channel); @@ -877,16 +771,13 @@ static void _PHY_SwChnl8192C(struct adapter *Adapter, u8 channel) param1 = RF_CHNLBW; param2 = channel; pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2); - PHY_SetRFReg(Adapter, (enum rf_radio_path)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]); + rtl8188e_PHY_SetRFReg(Adapter, (enum rf_radio_path)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]); } void PHY_SwChnl8188E(struct adapter *Adapter, u8 channel) { /* Call after initialization */ - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); - - if (pHalData->rf_chip == RF_PSEUDO_11N) - return; /* return immediately if it is peudo-phy */ + struct hal_data_8188e *pHalData = &Adapter->haldata; if (channel == 0) channel = 1; |