diff options
Diffstat (limited to 'drivers/staging/r8188eu/hal/rtl8188e_rf6052.c')
-rw-r--r-- | drivers/staging/r8188eu/hal/rtl8188e_rf6052.c | 65 |
1 files changed, 27 insertions, 38 deletions
diff --git a/drivers/staging/r8188eu/hal/rtl8188e_rf6052.c b/drivers/staging/r8188eu/hal/rtl8188e_rf6052.c index 946a1b97d96f..6e0231099986 100644 --- a/drivers/staging/r8188eu/hal/rtl8188e_rf6052.c +++ b/drivers/staging/r8188eu/hal/rtl8188e_rf6052.c @@ -46,16 +46,16 @@ void rtl8188e_PHY_RF6052SetBandwidth(struct adapter *Adapter, enum ht_channel_width Bandwidth) { - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8188e *pHalData = &Adapter->haldata; switch (Bandwidth) { case HT_CHANNEL_WIDTH_20: pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10) | BIT(11)); - PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); + rtl8188e_PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); break; case HT_CHANNEL_WIDTH_40: pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10)); - PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); + rtl8188e_PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); break; default: break; @@ -84,31 +84,24 @@ rtl8188e_PHY_RF6052SetCckTxPower( struct adapter *Adapter, u8 *pPowerlevel) { - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8188e *pHalData = &Adapter->haldata; struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; u32 TxAGC[2] = {0, 0}, tmpval = 0, pwrtrac_value; - bool TurboScanOff = false; u8 idx1, idx2; u8 *ptr; u8 direction; - /* FOR CE ,must disable turbo scan */ - TurboScanOff = true; if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) { TxAGC[RF_PATH_A] = 0x3f3f3f3f; TxAGC[RF_PATH_B] = 0x3f3f3f3f; - TurboScanOff = true;/* disable turbo scan */ - - if (TurboScanOff) { - for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { - TxAGC[idx1] = - pPowerlevel[idx1] | (pPowerlevel[idx1] << 8) | - (pPowerlevel[idx1] << 16) | (pPowerlevel[idx1] << 24); - /* 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. */ - if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA) - TxAGC[idx1] = 0x20; - } + for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { + TxAGC[idx1] = + pPowerlevel[idx1] | (pPowerlevel[idx1] << 8) | + (pPowerlevel[idx1] << 16) | (pPowerlevel[idx1] << 24); + /* 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. */ + if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA) + TxAGC[idx1] = 0x20; } } else { for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { @@ -148,15 +141,15 @@ rtl8188e_PHY_RF6052SetCckTxPower( /* rf-A cck tx power */ tmpval = TxAGC[RF_PATH_A] & 0xff; - PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); + rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); tmpval = TxAGC[RF_PATH_A] >> 8; - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); + rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); /* rf-B cck tx power */ tmpval = TxAGC[RF_PATH_B] >> 24; - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); + rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); tmpval = TxAGC[RF_PATH_B] & 0x00ffffff; - PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); + rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); } /* PHY_RF6052SetCckTxPower */ /* */ @@ -166,7 +159,7 @@ rtl8188e_PHY_RF6052SetCckTxPower( static void getpowerbase88e(struct adapter *Adapter, u8 *pPowerLevelOFDM, u8 *pPowerLevelBW20, u8 *pPowerLevelBW40, u8 Channel, u32 *OfdmBase, u32 *MCSBase) { - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8188e *pHalData = &Adapter->haldata; u32 powerBase0, powerBase1; u8 i; @@ -190,7 +183,7 @@ static void get_rx_power_val_by_reg(struct adapter *Adapter, u8 Channel, u8 index, u32 *powerBase0, u32 *powerBase1, u32 *pOutWriteVal) { - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8188e *pHalData = &Adapter->haldata; u8 i, chnlGroup = 0, pwr_diff_limit[4], customer_pwr_limit; s8 pwr_diff = 0; u32 writeVal, customer_limit, rf; @@ -272,7 +265,6 @@ static void get_rx_power_val_by_reg(struct adapter *Adapter, u8 Channel, } static void writeOFDMPowerReg88E(struct adapter *Adapter, u8 index, u32 *pValue) { - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); u16 regoffset_a[6] = { rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24, rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04, @@ -299,13 +291,10 @@ static void writeOFDMPowerReg88E(struct adapter *Adapter, u8 index, u32 *pValue) else regoffset = regoffset_b[index]; - PHY_SetBBReg(Adapter, regoffset, bMaskDWord, writeVal); + rtl8188e_PHY_SetBBReg(Adapter, regoffset, bMaskDWord, writeVal); /* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */ - if (((pHalData->rf_type == RF_2T2R) && - (regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs15_Mcs12)) || - ((pHalData->rf_type != RF_2T2R) && - (regoffset == rTxAGC_A_Mcs07_Mcs04 || regoffset == rTxAGC_B_Mcs07_Mcs04))) { + if (regoffset == rTxAGC_A_Mcs07_Mcs04 || regoffset == rTxAGC_B_Mcs07_Mcs04) { writeVal = pwr_val[3]; if (regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_A_Mcs07_Mcs04) regoffset = 0xc90; @@ -353,7 +342,7 @@ rtl8188e_PHY_RF6052SetOFDMTxPower( u8 *pPowerLevelBW40, u8 Channel) { - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8188e *pHalData = &Adapter->haldata; u32 writeVal[2], powerBase0[2], powerBase1[2], pwrtrac_value; u8 direction; u8 index = 0; @@ -383,7 +372,7 @@ rtl8188e_PHY_RF6052SetOFDMTxPower( static int phy_RF6052_Config_ParaFile(struct adapter *Adapter) { struct bb_reg_def *pPhyReg; - struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8188e *pHalData = &Adapter->haldata; u32 u4RegValue = 0; u8 eRFPath = 0; int rtStatus = _SUCCESS; @@ -393,21 +382,21 @@ static int phy_RF6052_Config_ParaFile(struct adapter *Adapter) pPhyReg = &pHalData->PHYRegDef[eRFPath]; /*----Store original RFENV control type----*/ - u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); + u4RegValue = rtl8188e_PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); /*----Set RF_ENV enable----*/ - PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1); + rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1); udelay(1);/* PlatformStallExecution(1); */ /*----Set RF_ENV output high----*/ - PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); + rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); udelay(1);/* PlatformStallExecution(1); */ /* Set bit number of Address and Data for RF register */ - PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */ + rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */ udelay(1);/* PlatformStallExecution(1); */ - PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */ + rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */ udelay(1);/* PlatformStallExecution(1); */ /*----Initialize RF fom connfiguration file----*/ @@ -415,7 +404,7 @@ static int phy_RF6052_Config_ParaFile(struct adapter *Adapter) rtStatus = _FAIL; /*----Restore RFENV control type----*/; - PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); + rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); if (rtStatus != _SUCCESS) goto phy_RF6052_Config_ParaFile_Fail; |