diff options
Diffstat (limited to 'drivers/staging/rtl8188eu/hal/phy.c')
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/phy.c | 49 |
1 files changed, 24 insertions, 25 deletions
diff --git a/drivers/staging/rtl8188eu/hal/phy.c b/drivers/staging/rtl8188eu/hal/phy.c index 920688fc9e9f..a970189ba8c6 100644 --- a/drivers/staging/rtl8188eu/hal/phy.c +++ b/drivers/staging/rtl8188eu/hal/phy.c @@ -51,8 +51,7 @@ void phy_set_bb_reg(struct adapter *adapt, u32 regaddr, u32 bitmask, u32 data) usb_write32(adapt, regaddr, data); } -static u32 rf_serial_read(struct adapter *adapt, - enum rf_radio_path rfpath, u32 offset) +static u32 rf_serial_read(struct adapter *adapt, enum rf_radio_path rfpath, u32 offset) { u32 ret = 0; struct bb_reg_def *phyreg = &adapt->HalData->PHYRegDef[rfpath]; @@ -107,7 +106,7 @@ static void rf_serial_write(struct adapter *adapt, } u32 rtw_hal_read_rfreg(struct adapter *adapt, enum rf_radio_path rf_path, - u32 reg_addr, u32 bit_mask) + u32 reg_addr, u32 bit_mask) { u32 original_value, bit_shift; @@ -117,7 +116,7 @@ u32 rtw_hal_read_rfreg(struct adapter *adapt, enum rf_radio_path rf_path, } void phy_set_rf_reg(struct adapter *adapt, enum rf_radio_path rf_path, - u32 reg_addr, u32 bit_mask, u32 data) + u32 reg_addr, u32 bit_mask, u32 data) { u32 original_value, bit_shift; @@ -190,7 +189,7 @@ void phy_set_tx_power_level(struct adapter *adapt, u8 channel) rtl88eu_phy_rf6052_set_cck_txpower(adapt, &cck_pwr[0]); rtl88eu_phy_rf6052_set_ofdm_txpower(adapt, &ofdm_pwr[0], &bw20_pwr[0], - &bw40_pwr[0], channel); + &bw40_pwr[0], channel); } static void phy_set_bw_mode_callback(struct adapter *adapt) @@ -236,11 +235,11 @@ static void phy_set_bw_mode_callback(struct adapter *adapt) * These settings are required only for 40MHz */ phy_set_bb_reg(adapt, rCCK0_System, bCCKSideBand, - (hal_data->nCur40MhzPrimeSC >> 1)); + (hal_data->nCur40MhzPrimeSC >> 1)); phy_set_bb_reg(adapt, rOFDM1_LSTF, 0xC00, hal_data->nCur40MhzPrimeSC); phy_set_bb_reg(adapt, 0x818, (BIT(26) | BIT(27)), - (hal_data->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); + (hal_data->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); break; default: break; @@ -251,7 +250,7 @@ static void phy_set_bw_mode_callback(struct adapter *adapt) } void rtw_hal_set_bwmode(struct adapter *adapt, enum ht_channel_width bandwidth, - unsigned char offset) + unsigned char offset) { struct hal_data_8188e *hal_data = adapt->HalData; enum ht_channel_width tmp_bw = hal_data->CurrentChannelBW; @@ -345,7 +344,7 @@ static void dm_txpwr_track_setpwr(struct odm_dm_struct *dm_odm) { if (dm_odm->BbSwingFlagOfdm || dm_odm->BbSwingFlagCck) { ODM_RT_TRACE(dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("dm_txpwr_track_setpwr CH=%d\n", *dm_odm->pChannel)); + ("%s CH=%d\n", __func__, *dm_odm->pChannel)); phy_set_tx_power_level(dm_odm->Adapter, *dm_odm->pChannel); dm_odm->BbSwingFlagOfdm = false; dm_odm->BbSwingFlagCck = false; @@ -403,11 +402,11 @@ void rtl88eu_dm_txpower_tracking_callback_thermalmeter(struct adapter *adapt) for (i = 0; i < CCK_TABLE_SIZE; i++) { if ((dm_odm->RFCalibrateInfo.bCCKinCH14 && - memcmp(&temp_cck, &CCKSwingTable_Ch14[i][2], 4)) || - memcmp(&temp_cck, &CCKSwingTable_Ch1_Ch13[i][2], 4)) { - cck_index_old = (u8)i; - dm_odm->BbSwingIdxCckBase = (u8)i; - break; + memcmp(&temp_cck, &CCKSwingTable_Ch14[i][2], 4)) || + memcmp(&temp_cck, &CCKSwingTable_Ch1_Ch13[i][2], 4)) { + cck_index_old = (u8)i; + dm_odm->BbSwingIdxCckBase = (u8)i; + break; } } @@ -437,7 +436,7 @@ void rtl88eu_dm_txpower_tracking_callback_thermalmeter(struct adapter *adapt) thermal_val = (u8)(thermal_avg / thermal_avg_count); if (dm_odm->RFCalibrateInfo.bDoneTxpower && - !dm_odm->RFCalibrateInfo.bReloadtxpowerindex) { + !dm_odm->RFCalibrateInfo.bReloadtxpowerindex) { delta = abs(thermal_val - dm_odm->RFCalibrateInfo.ThermalValue); } else { delta = abs(thermal_val - hal_data->EEPROMThermalMeter); @@ -1039,10 +1038,10 @@ static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8], for (i = 0; i < retry_count; i++) { path_a_ok = phy_path_a_iqk(adapt, is2t); if (path_a_ok == 0x01) { - result[t][0] = (phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, - bMaskDWord) & 0x3FF0000) >> 16; - result[t][1] = (phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, - bMaskDWord) & 0x3FF0000) >> 16; + result[t][0] = (phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, + bMaskDWord) & 0x3FF0000) >> 16; + result[t][1] = (phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, + bMaskDWord) & 0x3FF0000) >> 16; break; } } @@ -1050,10 +1049,10 @@ static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8], for (i = 0; i < retry_count; i++) { path_a_ok = phy_path_a_rx_iqk(adapt, is2t); if (path_a_ok == 0x03) { - result[t][2] = (phy_query_bb_reg(adapt, rRx_Power_Before_IQK_A_2, - bMaskDWord) & 0x3FF0000) >> 16; - result[t][3] = (phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, - bMaskDWord) & 0x3FF0000) >> 16; + result[t][2] = (phy_query_bb_reg(adapt, rRx_Power_Before_IQK_A_2, + bMaskDWord) & 0x3FF0000) >> 16; + result[t][3] = (phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, + bMaskDWord) & 0x3FF0000) >> 16; break; } ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, @@ -1149,12 +1148,12 @@ static void phy_lc_calibrate(struct adapter *adapt, bool is2t) /* 1. Read original RF mode */ /* Path-A */ rf_a_mode = rtw_hal_read_rfreg(adapt, RF_PATH_A, RF_AC, - bMask12Bits); + bMask12Bits); /* Path-B */ if (is2t) rf_b_mode = rtw_hal_read_rfreg(adapt, RF_PATH_B, RF_AC, - bMask12Bits); + bMask12Bits); /* 2. Set RF mode = standby mode */ /* Path-A */ |