diff options
Diffstat (limited to 'drivers/staging/rtl8188eu/hal')
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/Hal8188ERateAdaptive.c | 14 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/bb_cfg.c | 93 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/fw.c | 5 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/mac_cfg.c | 4 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/odm.c | 33 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/odm_HWConfig.c | 6 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/odm_RTL8188E.c | 122 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/phy.c | 32 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/rf_cfg.c | 6 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c | 26 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c | 27 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/rtl8188eu_led.c | 6 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/rtl8188eu_recv.c | 2 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/rtl8188eu_xmit.c | 6 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/usb_halinit.c | 56 |
15 files changed, 219 insertions, 219 deletions
diff --git a/drivers/staging/rtl8188eu/hal/Hal8188ERateAdaptive.c b/drivers/staging/rtl8188eu/hal/Hal8188ERateAdaptive.c index 2633a13b4e58..a108e8032327 100644 --- a/drivers/staging/rtl8188eu/hal/Hal8188ERateAdaptive.c +++ b/drivers/staging/rtl8188eu/hal/Hal8188ERateAdaptive.c @@ -127,7 +127,7 @@ static int odm_RateDown_8188E(struct odm_dm_struct *dm_odm, ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDown_8188E()\n")); - if (NULL == pRaInfo) { + if (!pRaInfo) { ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateDown_8188E(): pRaInfo is NULL\n")); return -1; @@ -193,7 +193,7 @@ static int odm_RateUp_8188E( ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateUp_8188E()\n")); - if (NULL == pRaInfo) { + if (!pRaInfo) { ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateUp_8188E(): pRaInfo is NULL\n")); return -1; @@ -624,7 +624,7 @@ int ODM_RAInfo_Init_all(struct odm_dm_struct *dm_odm) u8 ODM_RA_GetShortGI_8188E(struct odm_dm_struct *dm_odm, u8 macid) { - if ((NULL == dm_odm) || (macid >= ASSOCIATE_ENTRY_NUM)) + if ((!dm_odm) || (macid >= ASSOCIATE_ENTRY_NUM)) return 0; ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("macid =%d SGI =%d\n", macid, dm_odm->RAInfo[macid].RateSGI)); @@ -635,7 +635,7 @@ u8 ODM_RA_GetDecisionRate_8188E(struct odm_dm_struct *dm_odm, u8 macid) { u8 DecisionRate = 0; - if ((NULL == dm_odm) || (macid >= ASSOCIATE_ENTRY_NUM)) + if ((!dm_odm) || (macid >= ASSOCIATE_ENTRY_NUM)) return 0; DecisionRate = dm_odm->RAInfo[macid].DecisionRate; ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, @@ -647,7 +647,7 @@ u8 ODM_RA_GetHwPwrStatus_8188E(struct odm_dm_struct *dm_odm, u8 macid) { u8 PTStage = 5; - if ((NULL == dm_odm) || (macid >= ASSOCIATE_ENTRY_NUM)) + if ((!dm_odm) || (macid >= ASSOCIATE_ENTRY_NUM)) return 0; PTStage = dm_odm->RAInfo[macid].PTStage; ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, @@ -659,7 +659,7 @@ void ODM_RA_UpdateRateInfo_8188E(struct odm_dm_struct *dm_odm, u8 macid, u8 Rate { struct odm_ra_info *pRaInfo = NULL; - if ((NULL == dm_odm) || (macid >= ASSOCIATE_ENTRY_NUM)) + if ((!dm_odm) || (macid >= ASSOCIATE_ENTRY_NUM)) return; ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("macid =%d RateID = 0x%x RateMask = 0x%x SGIEnable =%d\n", @@ -676,7 +676,7 @@ void ODM_RA_SetRSSI_8188E(struct odm_dm_struct *dm_odm, u8 macid, u8 Rssi) { struct odm_ra_info *pRaInfo = NULL; - if ((NULL == dm_odm) || (macid >= ASSOCIATE_ENTRY_NUM)) + if ((!dm_odm) || (macid >= ASSOCIATE_ENTRY_NUM)) return; ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, (" macid =%d Rssi =%d\n", macid, Rssi)); diff --git a/drivers/staging/rtl8188eu/hal/bb_cfg.c b/drivers/staging/rtl8188eu/hal/bb_cfg.c index 9c7e626aa703..f58a8222c899 100644 --- a/drivers/staging/rtl8188eu/hal/bb_cfg.c +++ b/drivers/staging/rtl8188eu/hal/bb_cfg.c @@ -22,14 +22,6 @@ #include <phy.h> -#define read_next_pair(array, v1, v2, i) \ - do { \ - i += 2; \ - v1 = array[i]; \ - v2 = array[i+1]; \ - } while (0) - - /* AGC_TAB_1T.TXT */ static u32 array_agc_tab_1t_8188e[] = { @@ -166,12 +158,12 @@ static u32 array_agc_tab_1t_8188e[] = { static bool set_baseband_agc_config(struct adapter *adapt) { u32 i; - u32 arraylen = sizeof(array_agc_tab_1t_8188e)/sizeof(u32); + const u32 arraylen = ARRAY_SIZE(array_agc_tab_1t_8188e); u32 *array = array_agc_tab_1t_8188e; for (i = 0; i < arraylen; i += 2) { u32 v1 = array[i]; - u32 v2 = array[i+1]; + u32 v2 = array[i + 1]; if (v1 < 0xCDCDCDCD) { phy_set_bb_reg(adapt, v1, bMaskDWord, v2); @@ -401,12 +393,12 @@ static void rtl_bb_delay(struct adapter *adapt, u32 addr, u32 data) static bool set_baseband_phy_config(struct adapter *adapt) { u32 i; - u32 arraylen = sizeof(array_phy_reg_1t_8188e)/sizeof(u32); + const u32 arraylen = ARRAY_SIZE(array_phy_reg_1t_8188e); u32 *array = array_phy_reg_1t_8188e; for (i = 0; i < arraylen; i += 2) { u32 v1 = array[i]; - u32 v2 = array[i+1]; + u32 v2 = array[i + 1]; if (v1 < 0xCDCDCDCD) rtl_bb_delay(adapt, v1, v2); @@ -508,53 +500,55 @@ static u32 array_phy_reg_pg_8188e[] = { }; -static void store_pwrindex_offset(struct adapter *Adapter, u32 regaddr, u32 bitmask, u32 data) +static void store_pwrindex_offset(struct adapter *adapter, + u32 regaddr, u32 bitmask, u32 data) { - struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter); - u8 pwrGrpCnt = hal_data->pwrGroupCnt; + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapter); + u32 * const power_level_offset = + hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt]; if (regaddr == rTxAGC_A_Rate18_06) - hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][0] = data; + power_level_offset[0] = data; if (regaddr == rTxAGC_A_Rate54_24) - hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][1] = data; + power_level_offset[1] = data; if (regaddr == rTxAGC_A_CCK1_Mcs32) - hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][6] = data; + power_level_offset[6] = data; if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) - hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][7] = data; + power_level_offset[7] = data; if (regaddr == rTxAGC_A_Mcs03_Mcs00) - hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][2] = data; + power_level_offset[2] = data; if (regaddr == rTxAGC_A_Mcs07_Mcs04) - hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][3] = data; + power_level_offset[3] = data; if (regaddr == rTxAGC_A_Mcs11_Mcs08) - hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][4] = data; + power_level_offset[4] = data; if (regaddr == rTxAGC_A_Mcs15_Mcs12) { - hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][5] = data; + power_level_offset[5] = data; if (hal_data->rf_type == RF_1T1R) hal_data->pwrGroupCnt++; } if (regaddr == rTxAGC_B_Rate18_06) - hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][8] = data; + power_level_offset[8] = data; if (regaddr == rTxAGC_B_Rate54_24) - hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][9] = data; + power_level_offset[9] = data; if (regaddr == rTxAGC_B_CCK1_55_Mcs32) - hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][14] = data; + power_level_offset[14] = data; if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) - hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][15] = data; + power_level_offset[15] = data; if (regaddr == rTxAGC_B_Mcs03_Mcs00) - hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][10] = data; + power_level_offset[10] = data; if (regaddr == rTxAGC_B_Mcs07_Mcs04) - hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][11] = data; + power_level_offset[11] = data; if (regaddr == rTxAGC_B_Mcs11_Mcs08) - hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][12] = data; + power_level_offset[12] = data; if (regaddr == rTxAGC_B_Mcs15_Mcs12) { - hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][13] = data; + power_level_offset[13] = data; if (hal_data->rf_type != RF_1T1R) hal_data->pwrGroupCnt++; } } static void rtl_addr_delay(struct adapter *adapt, - u32 addr, u32 bit_mask, u32 data) + u32 addr, u32 bit_mask, u32 data) { switch (addr) { case 0xfe: @@ -582,14 +576,14 @@ static void rtl_addr_delay(struct adapter *adapt, static bool config_bb_with_pgheader(struct adapter *adapt) { - u32 i = 0; - u32 arraylen = sizeof(array_phy_reg_pg_8188e) / sizeof(u32); + u32 i; + const u32 arraylen = ARRAY_SIZE(array_phy_reg_pg_8188e); u32 *array = array_phy_reg_pg_8188e; for (i = 0; i < arraylen; i += 3) { u32 v1 = array[i]; - u32 v2 = array[i+1]; - u32 v3 = array[i+2]; + u32 v2 = array[i + 1]; + u32 v3 = array[i + 2]; if (v1 < 0xCDCDCDCD) rtl_addr_delay(adapt, v1, v2, v3); @@ -597,15 +591,15 @@ static bool config_bb_with_pgheader(struct adapter *adapt) return true; } -static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *Adapter) +static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *adapter) { - struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter); + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapter); struct bb_reg_def *reg[4]; - reg[RF_PATH_A] = &(hal_data->PHYRegDef[RF_PATH_A]); - reg[RF_PATH_B] = &(hal_data->PHYRegDef[RF_PATH_B]); - reg[RF_PATH_C] = &(hal_data->PHYRegDef[RF_PATH_C]); - reg[RF_PATH_D] = &(hal_data->PHYRegDef[RF_PATH_D]); + reg[RF_PATH_A] = &hal_data->PHYRegDef[RF_PATH_A]; + reg[RF_PATH_B] = &hal_data->PHYRegDef[RF_PATH_B]; + reg[RF_PATH_C] = &hal_data->PHYRegDef[RF_PATH_C]; + reg[RF_PATH_D] = &hal_data->PHYRegDef[RF_PATH_D]; reg[RF_PATH_A]->rfintfs = rFPGA0_XAB_RFInterfaceSW; reg[RF_PATH_B]->rfintfs = rFPGA0_XAB_RFInterfaceSW; @@ -688,13 +682,13 @@ static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *Adapter) static bool config_parafile(struct adapter *adapt) { - struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(adapt); + struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt); struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); set_baseband_phy_config(adapt); /* If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */ - if (!pEEPROM->bautoload_fail_flag) { + if (!eeprom->bautoload_fail_flag) { hal_data->pwrGroupCnt = 0; config_bb_with_pgheader(adapt); } @@ -713,18 +707,21 @@ bool rtl88eu_phy_bb_config(struct adapter *adapt) /* Enable BB and RF */ regval = usb_read16(adapt, REG_SYS_FUNC_EN); - usb_write16(adapt, REG_SYS_FUNC_EN, (u16)(regval|BIT13|BIT0|BIT1)); + usb_write16(adapt, REG_SYS_FUNC_EN, + (u16)(regval | BIT(13) | BIT(0) | BIT(1))); - usb_write8(adapt, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB); + usb_write8(adapt, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB); - usb_write8(adapt, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB); + usb_write8(adapt, REG_SYS_FUNC_EN, FEN_USBA | + FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB); /* Config BB and AGC */ rtstatus = config_parafile(adapt); /* write 0x24[16:11] = 0x24[22:17] = crystal_cap */ crystal_cap = hal_data->CrystalCap & 0x3F; - phy_set_bb_reg(adapt, REG_AFE_XTAL_CTRL, 0x7ff800, (crystal_cap | (crystal_cap << 6))); + phy_set_bb_reg(adapt, REG_AFE_XTAL_CTRL, 0x7ff800, + (crystal_cap | (crystal_cap << 6))); return rtstatus; } diff --git a/drivers/staging/rtl8188eu/hal/fw.c b/drivers/staging/rtl8188eu/hal/fw.c index a71c54295508..23aa6d37acac 100644 --- a/drivers/staging/rtl8188eu/hal/fw.c +++ b/drivers/staging/rtl8188eu/hal/fw.c @@ -190,7 +190,6 @@ int rtl88eu_download_fw(struct adapter *adapt) struct rtl92c_firmware_header *pfwheader = NULL; u8 *pfwdata; u32 fwsize; - int err; if (request_firmware(&fw, fw_name, device)) { dev_err(device, "Firmware %s not available\n", fw_name); @@ -229,7 +228,5 @@ int rtl88eu_download_fw(struct adapter *adapt) _rtl88e_write_fw(adapt, pfwdata, fwsize); _rtl88e_enable_fw_download(adapt, false); - err = _rtl88e_fw_free_to_go(adapt); - - return err; + return _rtl88e_fw_free_to_go(adapt); } diff --git a/drivers/staging/rtl8188eu/hal/mac_cfg.c b/drivers/staging/rtl8188eu/hal/mac_cfg.c index febc83a5adb8..0bc1b215219a 100644 --- a/drivers/staging/rtl8188eu/hal/mac_cfg.c +++ b/drivers/staging/rtl8188eu/hal/mac_cfg.c @@ -123,10 +123,10 @@ bool rtl88eu_phy_mac_config(struct adapter *adapt) u32 arraylength; u32 *ptrarray; - arraylength = sizeof(array_MAC_REG_8188E)/sizeof(u32); + arraylength = ARRAY_SIZE(array_MAC_REG_8188E); ptrarray = array_MAC_REG_8188E; - for (i = 0; i < arraylength; i = i + 2) + for (i = 0; i < arraylength; i += 2) usb_write8(adapt, ptrarray[i], (u8)ptrarray[i + 1]); usb_write8(adapt, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); diff --git a/drivers/staging/rtl8188eu/hal/odm.c b/drivers/staging/rtl8188eu/hal/odm.c index 710fdc3449f8..2c25d3b02036 100644 --- a/drivers/staging/rtl8188eu/hal/odm.c +++ b/drivers/staging/rtl8188eu/hal/odm.c @@ -437,7 +437,7 @@ void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm) { struct adapter *adapter = pDM_Odm->Adapter; - pDM_Odm->bCckHighPower = (bool)phy_query_bb_reg(adapter, 0x824, BIT9); + pDM_Odm->bCckHighPower = (bool)phy_query_bb_reg(adapter, 0x824, BIT(9)); pDM_Odm->RFPathRxEnable = (u8)phy_query_bb_reg(adapter, 0xc04, 0x0F); ODM_InitDebugSetting(pDM_Odm); @@ -736,8 +736,8 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) return; /* hold ofdm counter */ - phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */ - phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */ + phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */ + phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */ ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); @@ -760,8 +760,8 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) FalseAlmCnt->Cnt_BW_USC = (ret_value & 0xffff0000)>>16; /* hold cck counter */ - phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1); - phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT14, 1); + phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(12), 1); + phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(14), 1); ret_value = phy_query_bb_reg(adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); FalseAlmCnt->Cnt_Cck_fail = ret_value; @@ -853,7 +853,7 @@ void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) } if (pDM_PSTable->initialize == 0) { pDM_PSTable->Reg874 = (phy_query_bb_reg(adapter, 0x874, bMaskDWord)&0x1CC000)>>14; - pDM_PSTable->RegC70 = (phy_query_bb_reg(adapter, 0xc70, bMaskDWord)&BIT3)>>3; + pDM_PSTable->RegC70 = (phy_query_bb_reg(adapter, 0xc70, bMaskDWord) & BIT(3))>>3; pDM_PSTable->Reg85C = (phy_query_bb_reg(adapter, 0x85c, bMaskDWord)&0xFF000000)>>24; pDM_PSTable->RegA74 = (phy_query_bb_reg(adapter, 0xa74, bMaskDWord)&0xF000)>>12; pDM_PSTable->initialize = 1; @@ -881,19 +881,19 @@ void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) { if (pDM_PSTable->CurRFState == RF_Save) { - phy_set_bb_reg(adapter, 0x874 , 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ - phy_set_bb_reg(adapter, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */ + phy_set_bb_reg(adapter, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ + phy_set_bb_reg(adapter, 0xc70, BIT(3), 0); /* RegC70[3]=1'b0 */ phy_set_bb_reg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */ phy_set_bb_reg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */ phy_set_bb_reg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */ - phy_set_bb_reg(adapter, 0x818, BIT28, 0x0); /* Reg818[28]=1'b0 */ - phy_set_bb_reg(adapter, 0x818, BIT28, 0x1); /* Reg818[28]=1'b1 */ + phy_set_bb_reg(adapter, 0x818, BIT(28), 0x0); /* Reg818[28]=1'b0 */ + phy_set_bb_reg(adapter, 0x818, BIT(28), 0x1); /* Reg818[28]=1'b1 */ } else { - phy_set_bb_reg(adapter, 0x874 , 0x1CC000, pDM_PSTable->Reg874); - phy_set_bb_reg(adapter, 0xc70, BIT3, pDM_PSTable->RegC70); + phy_set_bb_reg(adapter, 0x874, 0x1CC000, pDM_PSTable->Reg874); + phy_set_bb_reg(adapter, 0xc70, BIT(3), pDM_PSTable->RegC70); phy_set_bb_reg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); phy_set_bb_reg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74); - phy_set_bb_reg(adapter, 0x818, BIT28, 0x0); + phy_set_bb_reg(adapter, 0x818, BIT(28), 0x0); } pDM_PSTable->PreRFState = pDM_PSTable->CurRFState; } @@ -1043,7 +1043,7 @@ void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm) for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i]; if (IS_STA_VALID(pstat)) { - if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false , &pstat->rssi_level)) { + if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level)) { ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level)); @@ -1188,7 +1188,8 @@ void odm_RSSIMonitorCheckCE(struct odm_dm_struct *pDM_Odm) pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0; FindMinimumRSSI(Adapter); - ODM_CmnInfoUpdate(&pHalData->odmpriv , ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM); + ODM_CmnInfoUpdate(&pHalData->odmpriv, ODM_CMNINFO_RSSI_MIN, + pdmpriv->MinUndecoratedPWDBForDM); } /* 3============================================================ */ @@ -1228,7 +1229,7 @@ void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm) return; if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */ - phy_set_rf_reg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); + phy_set_rf_reg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03); pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; return; diff --git a/drivers/staging/rtl8188eu/hal/odm_HWConfig.c b/drivers/staging/rtl8188eu/hal/odm_HWConfig.c index 36afe45d1c9a..28b9f7f591c0 100644 --- a/drivers/staging/rtl8188eu/hal/odm_HWConfig.c +++ b/drivers/staging/rtl8188eu/hal/odm_HWConfig.c @@ -362,7 +362,7 @@ static void odm_Process_RSSIForDM(struct odm_dm_struct *dm_odm, } } - pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT0; + pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT(0); } else { RSSI_Ave = pPhyInfo->RxPWDBAll; @@ -391,10 +391,10 @@ static void odm_Process_RSSIForDM(struct odm_dm_struct *dm_odm, pEntry->rssi_stat.ValidBit++; for (i = 0; i < pEntry->rssi_stat.ValidBit; i++) - OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i)&BIT0; + OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i) & BIT(0); if (pEntry->rssi_stat.ValidBit == 64) { - Weighting = ((OFDM_pkt<<4) > 64) ? 64 : (OFDM_pkt<<4); + Weighting = min_t(u32, OFDM_pkt << 4, 64); UndecoratedSmoothedPWDB = (Weighting*UndecoratedSmoothedOFDM+(64-Weighting)*UndecoratedSmoothedCCK)>>6; } else { if (pEntry->rssi_stat.ValidBit != 0) diff --git a/drivers/staging/rtl8188eu/hal/odm_RTL8188E.c b/drivers/staging/rtl8188eu/hal/odm_RTL8188E.c index d3c6873925ba..c0242a095c19 100644 --- a/drivers/staging/rtl8188eu/hal/odm_RTL8188E.c +++ b/drivers/staging/rtl8188eu/hal/odm_RTL8188E.c @@ -28,26 +28,26 @@ static void dm_rx_hw_antena_div_init(struct odm_dm_struct *dm_odm) if (*(dm_odm->mp_mode) == 1) { dm_odm->AntDivType = CGCS_RX_SW_ANTDIV; - phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); - phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); + phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0); + phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); return; } /* MAC Setting */ value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, - value32|(BIT23|BIT25)); + value32|(BIT(23) | BIT(25))); /* Pin Settings */ - phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0); - phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0); - phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 1); - phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); + phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); + phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); + phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); + phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* OFDM Settings */ phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0); /* CCK Settings */ - phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); - phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); + phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); + phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT); phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201); } @@ -59,37 +59,37 @@ static void dm_trx_hw_antenna_div_init(struct odm_dm_struct *dm_odm) if (*(dm_odm->mp_mode) == 1) { dm_odm->AntDivType = CGCS_RX_SW_ANTDIV; - phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); + phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0); phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, - BIT5|BIT4|BIT3, 0); + BIT(5) | BIT(4) | BIT(3), 0); return; } /* MAC Setting */ value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, - value32|(BIT23|BIT25)); + value32|(BIT(23) | BIT(25))); /* Pin Settings */ - phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0); - phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0); - phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 0); - phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); + phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); + phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); + phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); + phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* OFDM Settings */ phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0); /* CCK Settings */ - phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); - phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); + phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); + phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* Tx Settings */ - phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0); + phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0); rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT); /* antenna mapping table */ if (!dm_odm->bIsMPChip) { /* testchip */ phy_set_bb_reg(adapter, ODM_REG_RX_DEFUALT_A_11N, - BIT10|BIT9|BIT8, 1); + BIT(10) | BIT(9) | BIT(8), 1); phy_set_bb_reg(adapter, ODM_REG_RX_DEFUALT_A_11N, - BIT13|BIT12|BIT11, 2); + BIT(13) | BIT(12) | BIT(11), 2); } else { /* MPchip */ phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord, 0x0201); @@ -118,40 +118,40 @@ static void dm_fast_training_init(struct odm_dm_struct *dm_odm) /* MAC Setting */ value32 = phy_query_bb_reg(adapter, 0x4c, bMaskDWord); - phy_set_bb_reg(adapter, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); + phy_set_bb_reg(adapter, 0x4c, bMaskDWord, value32|(BIT(23) | BIT(25))); value32 = phy_query_bb_reg(adapter, 0x7B4, bMaskDWord); - phy_set_bb_reg(adapter, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); + phy_set_bb_reg(adapter, 0x7b4, bMaskDWord, value32|(BIT(16) | BIT(17))); /* Match MAC ADDR */ phy_set_bb_reg(adapter, 0x7b4, 0xFFFF, 0); phy_set_bb_reg(adapter, 0x7b0, bMaskDWord, 0); - phy_set_bb_reg(adapter, 0x870, BIT9|BIT8, 0); - phy_set_bb_reg(adapter, 0x864, BIT10, 0); - phy_set_bb_reg(adapter, 0xb2c, BIT22, 0); - phy_set_bb_reg(adapter, 0xb2c, BIT31, 1); + phy_set_bb_reg(adapter, 0x870, BIT(9) | BIT(8), 0); + phy_set_bb_reg(adapter, 0x864, BIT(10), 0); + phy_set_bb_reg(adapter, 0xb2c, BIT(22), 0); + phy_set_bb_reg(adapter, 0xb2c, BIT(31), 1); phy_set_bb_reg(adapter, 0xca4, bMaskDWord, 0x000000a0); /* antenna mapping table */ if (AntCombination == 2) { if (!dm_odm->bIsMPChip) { /* testchip */ - phy_set_bb_reg(adapter, 0x858, BIT10|BIT9|BIT8, 1); - phy_set_bb_reg(adapter, 0x858, BIT13|BIT12|BIT11, 2); + phy_set_bb_reg(adapter, 0x858, BIT(10) | BIT(9) | BIT(8), 1); + phy_set_bb_reg(adapter, 0x858, BIT(13) | BIT(12) | BIT(11), 2); } else { /* MPchip */ phy_set_bb_reg(adapter, 0x914, bMaskByte0, 1); phy_set_bb_reg(adapter, 0x914, bMaskByte1, 2); } } else if (AntCombination == 7) { if (!dm_odm->bIsMPChip) { /* testchip */ - phy_set_bb_reg(adapter, 0x858, BIT10|BIT9|BIT8, 0); - phy_set_bb_reg(adapter, 0x858, BIT13|BIT12|BIT11, 1); - phy_set_bb_reg(adapter, 0x878, BIT16, 0); - phy_set_bb_reg(adapter, 0x858, BIT15|BIT14, 2); - phy_set_bb_reg(adapter, 0x878, BIT19|BIT18|BIT17, 3); - phy_set_bb_reg(adapter, 0x878, BIT22|BIT21|BIT20, 4); - phy_set_bb_reg(adapter, 0x878, BIT25|BIT24|BIT23, 5); - phy_set_bb_reg(adapter, 0x878, BIT28|BIT27|BIT26, 6); - phy_set_bb_reg(adapter, 0x878, BIT31|BIT30|BIT29, 7); + phy_set_bb_reg(adapter, 0x858, BIT(10) | BIT(9) | BIT(8), 0); + phy_set_bb_reg(adapter, 0x858, BIT(13) | BIT(12) | BIT(11), 1); + phy_set_bb_reg(adapter, 0x878, BIT(16), 0); + phy_set_bb_reg(adapter, 0x858, BIT(15) | BIT(14), 2); + phy_set_bb_reg(adapter, 0x878, BIT(19) | BIT(18) | BIT(17), 3); + phy_set_bb_reg(adapter, 0x878, BIT(22) | BIT(21) | BIT(20), 4); + phy_set_bb_reg(adapter, 0x878, BIT(25) | BIT(24) | BIT(23), 5); + phy_set_bb_reg(adapter, 0x878, BIT(28) | BIT(27) | BIT(26), 6); + phy_set_bb_reg(adapter, 0x878, BIT(31) | BIT(30) | BIT(29), 7); } else { /* MPchip */ phy_set_bb_reg(adapter, 0x914, bMaskByte0, 0); phy_set_bb_reg(adapter, 0x914, bMaskByte1, 1); @@ -165,13 +165,13 @@ static void dm_fast_training_init(struct odm_dm_struct *dm_odm) } /* Default Ant Setting when no fast training */ - phy_set_bb_reg(adapter, 0x80c, BIT21, 1); - phy_set_bb_reg(adapter, 0x864, BIT5|BIT4|BIT3, 0); - phy_set_bb_reg(adapter, 0x864, BIT8|BIT7|BIT6, 1); + phy_set_bb_reg(adapter, 0x80c, BIT(21), 1); + phy_set_bb_reg(adapter, 0x864, BIT(5) | BIT(4) | BIT(3), 0); + phy_set_bb_reg(adapter, 0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Enter Traing state */ - phy_set_bb_reg(adapter, 0x864, BIT2|BIT1|BIT0, (AntCombination-1)); - phy_set_bb_reg(adapter, 0xc50, BIT7, 1); + phy_set_bb_reg(adapter, 0x864, BIT(2) | BIT(1) | BIT(0), (AntCombination-1)); + phy_set_bb_reg(adapter, 0xc50, BIT(7), 1); } void rtl88eu_dm_antenna_div_init(struct odm_dm_struct *dm_odm) @@ -205,18 +205,18 @@ void rtl88eu_dm_update_rx_idle_ant(struct odm_dm_struct *dm_odm, u8 ant) if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) { phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, - BIT5|BIT4|BIT3, default_ant); + BIT(5) | BIT(4) | BIT(3), default_ant); phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, - BIT8|BIT7|BIT6, optional_ant); + BIT(8) | BIT(7) | BIT(6), optional_ant); phy_set_bb_reg(adapter, ODM_REG_ANTSEL_CTRL_11N, - BIT14|BIT13|BIT12, default_ant); + BIT(14) | BIT(13) | BIT(12), default_ant); phy_set_bb_reg(adapter, ODM_REG_RESP_TX_11N, - BIT6|BIT7, default_ant); + BIT(6) | BIT(7), default_ant); } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) { phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, - BIT5|BIT4|BIT3, default_ant); + BIT(5) | BIT(4) | BIT(3), default_ant); phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, - BIT8|BIT7|BIT6, optional_ant); + BIT(8) | BIT(7) | BIT(6), optional_ant); } } dm_fat_tbl->RxIdleAnt = ant; @@ -231,9 +231,9 @@ static void update_tx_ant_88eu(struct odm_dm_struct *dm_odm, u8 ant, u32 mac_id) target_ant = MAIN_ANT_CG_TRX; else target_ant = AUX_ANT_CG_TRX; - dm_fat_tbl->antsel_a[mac_id] = target_ant&BIT0; - dm_fat_tbl->antsel_b[mac_id] = (target_ant&BIT1)>>1; - dm_fat_tbl->antsel_c[mac_id] = (target_ant&BIT2)>>2; + dm_fat_tbl->antsel_a[mac_id] = target_ant & BIT(0); + dm_fat_tbl->antsel_b[mac_id] = (target_ant & BIT(1))>>1; + dm_fat_tbl->antsel_c[mac_id] = (target_ant & BIT(2))>>2; } void rtl88eu_dm_set_tx_ant_by_tx_info(struct odm_dm_struct *dm_odm, @@ -292,8 +292,7 @@ static void rtl88eu_dm_hw_ant_div(struct odm_dm_struct *dm_odm) (dm_fat_tbl->AuxAnt_Sum[i]/dm_fat_tbl->AuxAnt_Cnt[i]) : 0; target_ant = (main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT; /* 2 Select max_rssi for DIG */ - local_max_rssi = (main_rssi > aux_rssi) ? - main_rssi : aux_rssi; + local_max_rssi = max(main_rssi, aux_rssi); if ((local_max_rssi > ant_div_max_rssi) && (local_max_rssi < 40)) ant_div_max_rssi = local_max_rssi; @@ -308,8 +307,7 @@ static void rtl88eu_dm_hw_ant_div(struct odm_dm_struct *dm_odm) (aux_rssi == 0)) aux_rssi = main_rssi; - local_min_rssi = (main_rssi > aux_rssi) ? - aux_rssi : main_rssi; + local_min_rssi = min(main_rssi, aux_rssi); if (local_min_rssi < min_rssi) { min_rssi = local_min_rssi; RxIdleAnt = target_ant; @@ -344,12 +342,12 @@ void rtl88eu_dm_antenna_diversity(struct odm_dm_struct *dm_odm) if (dm_fat_tbl->bBecomeLinked) { ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn off HW AntDiv\n")); - phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); + phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0); phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, - BIT15, 0); + BIT(15), 0); if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, - BIT21, 0); + BIT(21), 0); dm_fat_tbl->bBecomeLinked = dm_odm->bLinked; } return; @@ -357,12 +355,12 @@ void rtl88eu_dm_antenna_diversity(struct odm_dm_struct *dm_odm) if (!dm_fat_tbl->bBecomeLinked) { ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn on HW AntDiv\n")); - phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 1); + phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 1); phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, - BIT15, 1); + BIT(15), 1); if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, - BIT21, 1); + BIT(21), 1); dm_fat_tbl->bBecomeLinked = dm_odm->bLinked; } } diff --git a/drivers/staging/rtl8188eu/hal/phy.c b/drivers/staging/rtl8188eu/hal/phy.c index 2eafa503f343..d3e8a8ea1829 100644 --- a/drivers/staging/rtl8188eu/hal/phy.c +++ b/drivers/staging/rtl8188eu/hal/phy.c @@ -97,9 +97,9 @@ static u32 rf_serial_read(struct adapter *adapt, udelay(10); if (rfpath == RF_PATH_A) - rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, BIT8); + rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, BIT(8)); else if (rfpath == RF_PATH_B) - rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XB_HSSIParameter1, BIT8); + rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XB_HSSIParameter1, BIT(8)); if (rfpi_enable) ret = phy_query_bb_reg(adapt, phyreg->rfLSSIReadBackPi, @@ -293,7 +293,7 @@ static void phy_set_bw_mode_callback(struct adapter *adapt) (hal_data->nCur40MhzPrimeSC>>1)); phy_set_bb_reg(adapt, rOFDM1_LSTF, 0xC00, hal_data->nCur40MhzPrimeSC); - phy_set_bb_reg(adapt, 0x818, (BIT26 | BIT27), + phy_set_bb_reg(adapt, 0x818, (BIT(26) | BIT(27)), (hal_data->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); break; default: @@ -652,7 +652,7 @@ static u8 phy_path_a_iqk(struct adapter *adapt, bool config_pathb) reg_e94 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, bMaskDWord); reg_e9c = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord); - if (!(reg_eac & BIT28) && + if (!(reg_eac & BIT(28)) && (((reg_e94 & 0x03FF0000)>>16) != 0x142) && (((reg_e9c & 0x03FF0000)>>16) != 0x42)) result |= 0x01; @@ -705,7 +705,7 @@ static u8 phy_path_a_rx_iqk(struct adapter *adapt, bool configPathB) reg_e94 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, bMaskDWord); reg_e9c = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord); - if (!(reg_eac & BIT28) && + if (!(reg_eac & BIT(28)) && (((reg_e94 & 0x03FF0000)>>16) != 0x142) && (((reg_e9c & 0x03FF0000)>>16) != 0x42)) result |= 0x01; @@ -753,7 +753,7 @@ static u8 phy_path_a_rx_iqk(struct adapter *adapt, bool configPathB) phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000); phy_set_rf_reg(adapt, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); - if (!(reg_eac & BIT27) && /* if Tx is OK, check whether Rx is OK */ + if (!(reg_eac & BIT(27)) && /* if Tx is OK, check whether Rx is OK */ (((reg_ea4 & 0x03FF0000)>>16) != 0x132) && (((reg_eac & 0x03FF0000)>>16) != 0x36)) result |= 0x02; @@ -783,14 +783,14 @@ static u8 phy_path_b_iqk(struct adapter *adapt) regec4 = phy_query_bb_reg(adapt, rRx_Power_Before_IQK_B_2, bMaskDWord); regecc = phy_query_bb_reg(adapt, rRx_Power_After_IQK_B_2, bMaskDWord); - if (!(regeac & BIT31) && + if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000)>>16) != 0x142) && (((regebc & 0x03FF0000)>>16) != 0x42)) result |= 0x01; else return result; - if (!(regeac & BIT30) && + if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000)>>16) != 0x132) && (((regecc & 0x03FF0000)>>16) != 0x36)) result |= 0x02; @@ -959,9 +959,9 @@ static void mac_setting_calibration(struct adapter *adapt, u32 *mac_reg, u32 *ba usb_write8(adapt, mac_reg[i], 0x3F); for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) { - usb_write8(adapt, mac_reg[i], (u8)(backup[i]&(~BIT3))); + usb_write8(adapt, mac_reg[i], (u8)(backup[i]&(~BIT(3)))); } - usb_write8(adapt, mac_reg[i], (u8)(backup[i]&(~BIT5))); + usb_write8(adapt, mac_reg[i], (u8)(backup[i]&(~BIT(5)))); } static void path_a_standby(struct adapter *adapt) @@ -1013,7 +1013,7 @@ static bool simularity_compare(struct adapter *adapt, s32 resulta[][8], tmp2 = resulta[c2][i]; } - diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); + diff = abs(tmp1 - tmp2); if (diff > MAX_TOLERANCE) { if ((i == 2 || i == 6) && !sim_bitmap) { @@ -1117,15 +1117,15 @@ static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8], } /* BB setting */ - phy_set_bb_reg(adapt, rFPGA0_RFMOD, BIT24, 0x00); + phy_set_bb_reg(adapt, rFPGA0_RFMOD, BIT(24), 0x00); phy_set_bb_reg(adapt, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); phy_set_bb_reg(adapt, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); phy_set_bb_reg(adapt, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); - phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); - phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); - phy_set_bb_reg(adapt, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); - phy_set_bb_reg(adapt, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); + phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(10), 0x01); + phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(26), 0x01); + phy_set_bb_reg(adapt, rFPGA0_XA_RFInterfaceOE, BIT(10), 0x00); + phy_set_bb_reg(adapt, rFPGA0_XB_RFInterfaceOE, BIT(10), 0x00); if (is2t) { phy_set_bb_reg(adapt, rFPGA0_XA_LSSIParameter, bMaskDWord, diff --git a/drivers/staging/rtl8188eu/hal/rf_cfg.c b/drivers/staging/rtl8188eu/hal/rf_cfg.c index 954cade478db..44945427cc34 100644 --- a/drivers/staging/rtl8188eu/hal/rf_cfg.c +++ b/drivers/staging/rtl8188eu/hal/rf_cfg.c @@ -188,7 +188,7 @@ static void rtl8188e_config_rf_reg(struct adapter *adapt, u32 addr, u32 data) { u32 content = 0x1000; /*RF Content: radio_a_txt*/ - u32 maskforphyset = (u32)(content & 0xE000); + u32 maskforphyset = content & 0xE000; rtl_rfreg_delay(adapt, RF90_PATH_A, addr | maskforphyset, RFREG_OFFSET_MASK, @@ -198,7 +198,7 @@ static void rtl8188e_config_rf_reg(struct adapter *adapt, static bool rtl88e_phy_config_rf_with_headerfile(struct adapter *adapt) { u32 i; - u32 array_len = sizeof(Array_RadioA_1T_8188E)/sizeof(u32); + u32 array_len = ARRAY_SIZE(Array_RadioA_1T_8188E); u32 *array = Array_RadioA_1T_8188E; for (i = 0; i < array_len; i += 2) { @@ -214,7 +214,7 @@ static bool rtl88e_phy_config_rf_with_headerfile(struct adapter *adapt) while (v2 != 0xDEAD && v2 != 0xCDEF && v2 != 0xCDCD && i < array_len - 2) READ_NEXT_PAIR(v1, v2, i); - i -= 2; + i -= 2; } else { READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && v2 != 0xCDEF && diff --git a/drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c b/drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c index 0a62bfa210fe..580876313e98 100644 --- a/drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c +++ b/drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c @@ -149,7 +149,7 @@ void rtl8188e_Add_RateATid(struct adapter *pAdapter, u32 bitmap, u8 arg, u8 rssi init_rate = get_highest_rate_idx(bitmap&0x0fffffff)&0x3f; - shortGIrate = (arg&BIT(5)) ? true : false; + shortGIrate = (arg & BIT(5)) ? true : false; if (shortGIrate) init_rate |= BIT(6); @@ -277,7 +277,7 @@ static void ConstructBeacon(struct adapter *adapt, u8 *pframe, u32 *pLength) /* supported rates... */ rate_len = rtw_get_rateset_len(cur_network->SupportedRates); - pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen); + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, min_t(u32, rate_len, 8), cur_network->SupportedRates, &pktlen); /* DS parameter set */ pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen); @@ -467,7 +467,7 @@ static void SetFwRsvdPagePkt(struct adapter *adapt, bool bDLFinished) DBG_88E("%s\n", __func__); ReservedPagePacket = kzalloc(1000, GFP_KERNEL); - if (ReservedPagePacket == NULL) { + if (!ReservedPagePacket) { DBG_88E("%s: alloc ReservedPagePacket fail!\n", __func__); return; } @@ -537,7 +537,7 @@ static void SetFwRsvdPagePkt(struct adapter *adapt, bool bDLFinished) TotalPacketLen = BufIndex + QosNullLength; pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) + if (!pmgntframe) goto exit; /* update attribute */ @@ -577,23 +577,23 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *adapt, u8 mstatus) /* Do not set TSF again here or vWiFi beacon DMA INT will not work. */ /* Set REG_CR bit 8. DMA beacon by SW. */ - haldata->RegCR_1 |= BIT0; + haldata->RegCR_1 |= BIT(0); usb_write8(adapt, REG_CR+1, haldata->RegCR_1); /* Disable Hw protection for a time which revserd for Hw sending beacon. */ /* Fix download reserved page packet fail that access collision with the protection time. */ /* 2010.05.11. Added by tynli. */ usb_write8(adapt, REG_BCN_CTRL, usb_read8(adapt, REG_BCN_CTRL)&(~BIT(3))); - usb_write8(adapt, REG_BCN_CTRL, usb_read8(adapt, REG_BCN_CTRL)|BIT(4)); + usb_write8(adapt, REG_BCN_CTRL, usb_read8(adapt, REG_BCN_CTRL) | BIT(4)); - if (haldata->RegFwHwTxQCtrl&BIT6) { + if (haldata->RegFwHwTxQCtrl & BIT(6)) { DBG_88E("HalDownloadRSVDPage(): There is an Adapter is sending beacon.\n"); bSendBeacon = true; } /* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */ - usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl&(~BIT6))); - haldata->RegFwHwTxQCtrl &= (~BIT6); + usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl&(~BIT(6)))); + haldata->RegFwHwTxQCtrl &= (~BIT(6)); /* Clear beacon valid check bit. */ rtw_hal_set_hwreg(adapt, HW_VAR_BCN_VALID, NULL); @@ -626,7 +626,7 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *adapt, u8 mstatus) /* */ /* Enable Bcn */ - usb_write8(adapt, REG_BCN_CTRL, usb_read8(adapt, REG_BCN_CTRL)|BIT(3)); + usb_write8(adapt, REG_BCN_CTRL, usb_read8(adapt, REG_BCN_CTRL) | BIT(3)); usb_write8(adapt, REG_BCN_CTRL, usb_read8(adapt, REG_BCN_CTRL)&(~BIT(4))); /* To make sure that if there exists an adapter which would like to send beacon. */ @@ -635,8 +635,8 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *adapt, u8 mstatus) /* the beacon cannot be sent by HW. */ /* 2010.06.23. Added by tynli. */ if (bSendBeacon) { - usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl|BIT6)); - haldata->RegFwHwTxQCtrl |= BIT6; + usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl | BIT(6))); + haldata->RegFwHwTxQCtrl |= BIT(6); } /* Update RSVD page location H2C to Fw. */ @@ -647,7 +647,7 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *adapt, u8 mstatus) /* Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli. */ /* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */ - haldata->RegCR_1 &= (~BIT0); + haldata->RegCR_1 &= (~BIT(0)); usb_write8(adapt, REG_CR+1, haldata->RegCR_1); } } diff --git a/drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c b/drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c index a6295ca6a73e..e3e5d6f5d4f9 100644 --- a/drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c +++ b/drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c @@ -106,8 +106,8 @@ void _8051Reset88E(struct adapter *padapter) u8 u1bTmp; u1bTmp = usb_read8(padapter, REG_SYS_FUNC_EN+1); - usb_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT2)); - usb_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp|(BIT2)); + usb_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT(2))); + usb_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp|(BIT(2))); DBG_88E("=====> _8051Reset88E(): 8051 reset success .\n"); } @@ -184,10 +184,10 @@ static void hal_notch_filter_8188e(struct adapter *adapter, bool enable) { if (enable) { DBG_88E("Enable notch filter\n"); - usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) | BIT1); + usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) | BIT(1)); } else { DBG_88E("Disable notch filter\n"); - usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1); + usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) & ~BIT(1)); } } void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc) @@ -372,7 +372,7 @@ static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G, pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_HT20_DIFF; } else { pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4; - if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ + if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */ pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0; } @@ -380,7 +380,7 @@ static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G, pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_OFDM_DIFF; } else { pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f); - if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ + if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */ pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0; } pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0; @@ -390,7 +390,7 @@ static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G, pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; } else { pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4; - if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ + if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */ pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0; } @@ -398,7 +398,7 @@ static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G, pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; } else { pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f); - if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ + if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */ pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0; } eeAddr++; @@ -407,7 +407,7 @@ static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G, pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; } else { pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4; - if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ + if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */ pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0; } @@ -415,7 +415,7 @@ static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G, pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; } else { pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f); - if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ + if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */ pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0; } eeAddr++; @@ -444,6 +444,9 @@ static u8 Hal_GetChnlGroup88E(u8 chnl, u8 *pGroup) else if (chnl == 14) /* Channel 14 */ *pGroup = 5; } else { + + /* probably, this branch is suitable only for 5 GHz */ + bIn24G = false; if (chnl <= 40) @@ -485,13 +488,13 @@ void Hal_ReadPowerSavingMode88E(struct adapter *padapter, u8 *hwinfo, bool AutoL /* hw power down mode selection , 0:rf-off / 1:power down */ if (padapter->registrypriv.hwpdn_mode == 2) - padapter->pwrctrlpriv.bHWPowerdown = (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & BIT4); + padapter->pwrctrlpriv.bHWPowerdown = (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & BIT(4)); else padapter->pwrctrlpriv.bHWPowerdown = padapter->registrypriv.hwpdn_mode; /* decide hw if support remote wakeup function */ /* if hw supported, 8051 (SIE) will generate WeakUP signal(D+/D- toggle) when autoresume */ - padapter->pwrctrlpriv.bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT1) ? true : false; + padapter->pwrctrlpriv.bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT(1)) ? true : false; DBG_88E("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) , bSupportRemoteWakeup(%x)\n", __func__, padapter->pwrctrlpriv.bHWPwrPindetect, padapter->pwrctrlpriv.bHWPowerdown , padapter->pwrctrlpriv.bSupportRemoteWakeup); diff --git a/drivers/staging/rtl8188eu/hal/rtl8188eu_led.c b/drivers/staging/rtl8188eu/hal/rtl8188eu_led.c index 81d691ddd6c6..564cf53bff1b 100644 --- a/drivers/staging/rtl8188eu/hal/rtl8188eu_led.c +++ b/drivers/staging/rtl8188eu/hal/rtl8188eu_led.c @@ -36,7 +36,7 @@ void SwLedOn(struct adapter *padapter, struct LED_871x *pLed) if (padapter->bSurpriseRemoved || padapter->bDriverStopped) return; LedCfg = usb_read8(padapter, REG_LEDCFG2); - usb_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); /* SW control led0 on. */ + usb_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0) | BIT(5) | BIT(6)); /* SW control led0 on. */ pLed->bLedOn = true; } @@ -55,12 +55,12 @@ void SwLedOff(struct adapter *padapter, struct LED_871x *pLed) if (pHalData->bLedOpenDrain) { /* Open-drain arrangement for controlling the LED) */ LedCfg &= 0x90; /* Set to software control. */ - usb_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3)); + usb_write8(padapter, REG_LEDCFG2, (LedCfg | BIT(3))); LedCfg = usb_read8(padapter, REG_MAC_PINMUX_CFG); LedCfg &= 0xFE; usb_write8(padapter, REG_MAC_PINMUX_CFG, LedCfg); } else { - usb_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3|BIT5|BIT6)); + usb_write8(padapter, REG_LEDCFG2, (LedCfg | BIT(3) | BIT(5) | BIT(6))); } exit: pLed->bLedOn = false; diff --git a/drivers/staging/rtl8188eu/hal/rtl8188eu_recv.c b/drivers/staging/rtl8188eu/hal/rtl8188eu_recv.c index 06d1e654483e..d6d009aafcf0 100644 --- a/drivers/staging/rtl8188eu/hal/rtl8188eu_recv.c +++ b/drivers/staging/rtl8188eu/hal/rtl8188eu_recv.c @@ -43,7 +43,7 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter) precvpriv->pallocated_recv_buf = kcalloc(NR_RECVBUFF, sizeof(struct recv_buf), GFP_KERNEL); - if (precvpriv->pallocated_recv_buf == NULL) { + if (!precvpriv->pallocated_recv_buf) { res = _FAIL; RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("alloc recv_buf fail!\n")); diff --git a/drivers/staging/rtl8188eu/hal/rtl8188eu_xmit.c b/drivers/staging/rtl8188eu/hal/rtl8188eu_xmit.c index 594c1da9db23..7c5086ecff17 100644 --- a/drivers/staging/rtl8188eu/hal/rtl8188eu_xmit.c +++ b/drivers/staging/rtl8188eu/hal/rtl8188eu_xmit.c @@ -20,6 +20,7 @@ #define _RTL8188E_XMIT_C_ #include <osdep_service.h> #include <drv_types.h> +#include <mon.h> #include <wifi.h> #include <osdep_intf.h> #include <usb_ops_linux.h> @@ -649,7 +650,7 @@ static s32 pre_xmitframe(struct adapter *adapt, struct xmit_frame *pxmitframe) goto enqueue; pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); - if (pxmitbuf == NULL) + if (!pxmitbuf) goto enqueue; spin_unlock_bh(&pxmitpriv->lock); @@ -684,6 +685,9 @@ enqueue: s32 rtl8188eu_mgnt_xmit(struct adapter *adapt, struct xmit_frame *pmgntframe) { + struct xmit_priv *xmitpriv = &adapt->xmitpriv; + + rtl88eu_mon_xmit_hook(adapt->pmondev, pmgntframe, xmitpriv->frag_len); return rtw_dump_xframe(adapt, pmgntframe); } diff --git a/drivers/staging/rtl8188eu/hal/usb_halinit.c b/drivers/staging/rtl8188eu/hal/usb_halinit.c index 1ef878fd997b..7e72259f0e40 100644 --- a/drivers/staging/rtl8188eu/hal/usb_halinit.c +++ b/drivers/staging/rtl8188eu/hal/usb_halinit.c @@ -607,7 +607,7 @@ static void _InitBeaconParameters(struct adapter *Adapter) static void _BeaconFunctionEnable(struct adapter *Adapter, bool Enable, bool Linked) { - usb_write8(Adapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1)); + usb_write8(Adapter, REG_BCN_CTRL, (BIT(4) | BIT(3) | BIT(1))); usb_write8(Adapter, REG_RD_CTRL+1, 0x6F); } @@ -632,8 +632,8 @@ static void _InitAntenna_Selection(struct adapter *Adapter) return; DBG_88E("==> %s ....\n", __func__); - usb_write32(Adapter, REG_LEDCFG0, usb_read32(Adapter, REG_LEDCFG0)|BIT23); - phy_set_bb_reg(Adapter, rFPGA0_XAB_RFParameter, BIT13, 0x01); + usb_write32(Adapter, REG_LEDCFG0, usb_read32(Adapter, REG_LEDCFG0) | BIT(23)); + phy_set_bb_reg(Adapter, rFPGA0_XAB_RFParameter, BIT(13), 0x01); if (phy_query_bb_reg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A) haldata->CurAntenna = Antenna_A; @@ -664,13 +664,13 @@ enum rt_rf_power_state RfOnOffDetect(struct adapter *adapt) if (adapt->pwrctrlpriv.bHWPowerdown) { val8 = usb_read8(adapt, REG_HSISR); - DBG_88E("pwrdown, 0x5c(BIT7)=%02x\n", val8); - rfpowerstate = (val8 & BIT7) ? rf_off : rf_on; + DBG_88E("pwrdown, 0x5c(BIT(7))=%02x\n", val8); + rfpowerstate = (val8 & BIT(7)) ? rf_off : rf_on; } else { /* rf on/off */ - usb_write8(adapt, REG_MAC_PINMUX_CFG, usb_read8(adapt, REG_MAC_PINMUX_CFG)&~(BIT3)); + usb_write8(adapt, REG_MAC_PINMUX_CFG, usb_read8(adapt, REG_MAC_PINMUX_CFG)&~(BIT(3))); val8 = usb_read8(adapt, REG_GPIO_IO_SEL); DBG_88E("GPIO_IN=%02x\n", val8); - rfpowerstate = (val8 & BIT3) ? rf_on : rf_off; + rfpowerstate = (val8 & BIT(3)) ? rf_on : rf_off; } return rfpowerstate; } /* HalDetectPwrDownMode */ @@ -805,7 +805,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter) /* Enable TX Report */ /* Enable Tx Report Timer */ value8 = usb_read8(Adapter, REG_TX_RPT_CTRL); - usb_write8(Adapter, REG_TX_RPT_CTRL, (value8|BIT1|BIT0)); + usb_write8(Adapter, REG_TX_RPT_CTRL, (value8 | BIT(1) | BIT(0))); /* Set MAX RPT MACID */ usb_write8(Adapter, REG_TX_RPT_CTRL+1, 2);/* FOR sta mode ,0: bc/mc ,1:AP */ /* Tx RPT Timer. Unit: 32us */ @@ -898,7 +898,7 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK); usb_write8(Adapter, REG_USB_HRPWM, 0); /* ack for xmit mgmt frames. */ - usb_write32(Adapter, REG_FWHW_TXQ_CTRL, usb_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12)); + usb_write32(Adapter, REG_FWHW_TXQ_CTRL, usb_read32(Adapter, REG_FWHW_TXQ_CTRL) | BIT(12)); exit: HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END); @@ -918,7 +918,7 @@ static void CardDisableRTL8188EU(struct adapter *Adapter) /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */ val8 = usb_read8(Adapter, REG_TX_RPT_CTRL); - usb_write8(Adapter, REG_TX_RPT_CTRL, val8&(~BIT1)); + usb_write8(Adapter, REG_TX_RPT_CTRL, val8&(~BIT(1))); /* stop rx */ usb_write8(Adapter, REG_CR, 0x0); @@ -944,7 +944,7 @@ static void CardDisableRTL8188EU(struct adapter *Adapter) /* YJ,add,111212 */ /* Disable 32k */ val8 = usb_read8(Adapter, REG_32K_CTRL); - usb_write8(Adapter, REG_32K_CTRL, val8&(~BIT0)); + usb_write8(Adapter, REG_32K_CTRL, val8&(~BIT(0))); /* Card disable power action flow */ rtl88eu_pwrseqcmdparsing(Adapter, PWR_CUT_ALL_MSK, @@ -953,9 +953,9 @@ static void CardDisableRTL8188EU(struct adapter *Adapter) /* Reset MCU IO Wrapper */ val8 = usb_read8(Adapter, REG_RSV_CTRL+1); - usb_write8(Adapter, REG_RSV_CTRL+1, (val8&(~BIT3))); + usb_write8(Adapter, REG_RSV_CTRL+1, (val8&(~BIT(3)))); val8 = usb_read8(Adapter, REG_RSV_CTRL+1); - usb_write8(Adapter, REG_RSV_CTRL+1, val8|BIT3); + usb_write8(Adapter, REG_RSV_CTRL+1, val8 | BIT(3)); /* YJ,test add, 111207. For Power Consumption. */ val8 = usb_read8(Adapter, GPIO_IN); @@ -1171,10 +1171,10 @@ static void ResumeTxBeacon(struct adapter *adapt) /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */ /* which should be read from register to a global variable. */ - usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) | BIT6); - haldata->RegFwHwTxQCtrl |= BIT6; + usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) | BIT(6)); + haldata->RegFwHwTxQCtrl |= BIT(6); usb_write8(adapt, REG_TBTT_PROHIBIT+1, 0xff); - haldata->RegReg542 |= BIT0; + haldata->RegReg542 |= BIT(0); usb_write8(adapt, REG_TBTT_PROHIBIT+2, haldata->RegReg542); } @@ -1185,10 +1185,10 @@ static void StopTxBeacon(struct adapter *adapt) /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */ /* which should be read from register to a global variable. */ - usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) & (~BIT6)); - haldata->RegFwHwTxQCtrl &= (~BIT6); + usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) & (~BIT(6))); + haldata->RegFwHwTxQCtrl &= (~BIT(6)); usb_write8(adapt, REG_TBTT_PROHIBIT+1, 0x64); - haldata->RegReg542 &= ~(BIT0); + haldata->RegReg542 &= ~(BIT(0)); usb_write8(adapt, REG_TBTT_PROHIBIT+2, haldata->RegReg542); /* todo: CheckFwRsvdPageContent(Adapter); 2010.06.23. Added by tynli. */ @@ -1200,7 +1200,7 @@ static void hw_var_set_opmode(struct adapter *Adapter, u8 variable, u8 *val) u8 mode = *((u8 *)val); /* disable Port0 TSF update */ - usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)|BIT(4)); + usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(4)); /* set net_type */ val8 = usb_read8(Adapter, MSR)&0x0c; @@ -1378,7 +1378,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val) usb_write32(Adapter, REG_TSFTR+4, tsf>>32); /* enable related TSF function */ - usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)|BIT(3)); + usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(3)); if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) ResumeTxBeacon(Adapter); @@ -1403,10 +1403,10 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val) usb_write16(Adapter, REG_RXFLTMAP2, 0x00); /* reset TSF */ - usb_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1))); + usb_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); /* disable update TSF */ - usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)|BIT(4)); + usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(4)); break; case HW_VAR_MLME_SITESURVEY: if (*((u8 *)val)) { /* under sitesurvey */ @@ -1418,7 +1418,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val) usb_write16(Adapter, REG_RXFLTMAP2, 0x00); /* disable update TSF */ - usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)|BIT(4)); + usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(4)); } else { /* sitesurvey done */ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); @@ -1578,7 +1578,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val) } break; case HW_VAR_CAM_INVALID_ALL: - usb_write32(Adapter, RWCAM, BIT(31)|BIT(30)); + usb_write32(Adapter, RWCAM, BIT(31) | BIT(30)); break; case HW_VAR_CAM_WRITE: { @@ -1795,7 +1795,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val) break; case HW_VAR_BCN_VALID: /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw */ - usb_write8(Adapter, REG_TDECTRL+2, usb_read8(Adapter, REG_TDECTRL+2) | BIT0); + usb_write8(Adapter, REG_TDECTRL+2, usb_read8(Adapter, REG_TDECTRL+2) | BIT(0)); break; default: break; @@ -1815,7 +1815,7 @@ static void GetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val) break; case HW_VAR_BCN_VALID: /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 */ - val[0] = (BIT0 & usb_read8(Adapter, REG_TDECTRL+2)) ? true : false; + val[0] = (BIT(0) & usb_read8(Adapter, REG_TDECTRL+2)) ? true : false; break; case HW_VAR_DM_FLAG: val[0] = podmpriv->SupportAbility; @@ -2052,7 +2052,7 @@ static void SetBeaconRelatedRegisters8188EUsb(struct adapter *adapt) ResumeTxBeacon(adapt); - usb_write8(adapt, bcn_ctrl_reg, usb_read8(adapt, bcn_ctrl_reg)|BIT(1)); + usb_write8(adapt, bcn_ctrl_reg, usb_read8(adapt, bcn_ctrl_reg) | BIT(1)); } static void rtl8188eu_init_default_value(struct adapter *adapt) |