diff options
Diffstat (limited to 'drivers/staging/rtl8188eu/hal')
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/Hal8188ERateAdaptive.c | 83 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/bb_cfg.c | 219 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/fw.c | 3 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/odm.c | 8 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/odm_HWConfig.c | 4 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/phy.c | 184 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/pwrseqcmd.c | 1 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/rf.c | 2 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/rf_cfg.c | 4 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c | 3 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/rtl8188eu_recv.c | 2 | ||||
| -rw-r--r-- | drivers/staging/rtl8188eu/hal/usb_halinit.c | 8 |
12 files changed, 226 insertions, 295 deletions
diff --git a/drivers/staging/rtl8188eu/hal/Hal8188ERateAdaptive.c b/drivers/staging/rtl8188eu/hal/Hal8188ERateAdaptive.c index 3c651d5c6824..082f0ca198ef 100644 --- a/drivers/staging/rtl8188eu/hal/Hal8188ERateAdaptive.c +++ b/drivers/staging/rtl8188eu/hal/Hal8188ERateAdaptive.c @@ -115,17 +115,21 @@ static void odm_SetTxRPTTiming_8188E( } pRaInfo->RptTime = DynamicTxRPTTiming[idx]; - ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("pRaInfo->RptTime = 0x%x\n", pRaInfo->RptTime)); + ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("pRaInfo->RptTime = 0x%x\n", pRaInfo->RptTime)); } -static int odm_RateDown_8188E(struct odm_dm_struct *dm_odm, struct odm_ra_info *pRaInfo) +static int odm_RateDown_8188E(struct odm_dm_struct *dm_odm, + struct odm_ra_info *pRaInfo) { u8 RateID, LowestRate, HighestRate; u8 i; - ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDown_8188E()\n")); + ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, + ODM_DBG_TRACE, ("=====>odm_RateDown_8188E()\n")); if (NULL == pRaInfo) { - ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateDown_8188E(): pRaInfo is NULL\n")); + ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("odm_RateDown_8188E(): pRaInfo is NULL\n")); return -1; } RateID = pRaInfo->PreRate; @@ -167,10 +171,15 @@ RateDownFinish: pRaInfo->DecisionRate = RateID; odm_SetTxRPTTiming_8188E(dm_odm, pRaInfo, 2); - ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate down, RPT Timing default\n")); - ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("RAWaitingCounter %d, RAPendingCounter %d", pRaInfo->RAWaitingCounter, pRaInfo->RAPendingCounter)); - ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate down to RateID %d RateSGI %d\n", RateID, pRaInfo->RateSGI)); - ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("<===== odm_RateDown_8188E()\n")); + ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, + ODM_DBG_LOUD, ("Rate down, RPT Timing default\n")); + ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + ("RAWaitingCounter %d, RAPendingCounter %d", + pRaInfo->RAWaitingCounter, pRaInfo->RAPendingCounter)); + ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("Rate down to RateID %d RateSGI %d\n", RateID, pRaInfo->RateSGI)); + ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + ("<===== odm_RateDown_8188E()\n")); return 0; } @@ -182,9 +191,11 @@ static int odm_RateUp_8188E( u8 RateID, HighestRate; u8 i; - ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateUp_8188E()\n")); + ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, + ODM_DBG_TRACE, ("=====>odm_RateUp_8188E()\n")); if (NULL == pRaInfo) { - ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateUp_8188E(): pRaInfo is NULL\n")); + ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("odm_RateUp_8188E(): pRaInfo is NULL\n")); return -1; } RateID = pRaInfo->PreRate; @@ -200,7 +211,8 @@ static int odm_RateUp_8188E( goto RateUpfinish; } odm_SetTxRPTTiming_8188E(dm_odm, pRaInfo, 0); - ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateUp_8188E():Decrease RPT Timing\n")); + ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("odm_RateUp_8188E():Decrease RPT Timing\n")); if (RateID < HighestRate) { for (i = RateID+1; i <= HighestRate; i++) { @@ -218,15 +230,20 @@ static int odm_RateUp_8188E( RateID = HighestRate; } RateUpfinish: - if (pRaInfo->RAWaitingCounter == (4+PendingForRateUpFail[pRaInfo->RAPendingCounter])) + if (pRaInfo->RAWaitingCounter == + (4+PendingForRateUpFail[pRaInfo->RAPendingCounter])) pRaInfo->RAWaitingCounter = 0; else pRaInfo->RAWaitingCounter++; pRaInfo->DecisionRate = RateID; - ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate up to RateID %d\n", RateID)); - ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("RAWaitingCounter %d, RAPendingCounter %d", pRaInfo->RAWaitingCounter, pRaInfo->RAPendingCounter)); - ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("<===== odm_RateUp_8188E()\n")); + ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("Rate up to RateID %d\n", RateID)); + ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + ("RAWaitingCounter %d, RAPendingCounter %d", + pRaInfo->RAWaitingCounter, pRaInfo->RAPendingCounter)); + ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, + ODM_DBG_TRACE, ("<===== odm_RateUp_8188E()\n")); return 0; } @@ -243,11 +260,12 @@ static void odm_RateDecision_8188E(struct odm_dm_struct *dm_odm, struct odm_ra_info *pRaInfo ) { - u8 RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0; + u8 RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0, i = 0; /* u32 pool_retry; */ static u8 DynamicTxRPTTimingCounter; - ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDecision_8188E()\n")); + ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + ("=====>odm_RateDecision_8188E()\n")); if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) { /* STA used and data packet exits */ if ((pRaInfo->RssiStaRA < (pRaInfo->PreRssiStaRA - 3)) || @@ -268,14 +286,14 @@ static void odm_RateDecision_8188E(struct odm_dm_struct *dm_odm, ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, (" NscDown init is %d\n", pRaInfo->NscDown)); - pRaInfo->NscDown += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID1][0]; - pRaInfo->NscDown += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID1][1]; - pRaInfo->NscDown += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID1][2]; - pRaInfo->NscDown += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID1][3]; - pRaInfo->NscDown += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID1][4]; + + for (i = 0 ; i <= 4 ; i++) + pRaInfo->NscDown += pRaInfo->RTY[i] * RETRY_PENALTY[PenaltyID1][i]; + ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, - (" NscDown is %d, total*penalty[5] is %d\n", - pRaInfo->NscDown, (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]))); + (" NscDown is %d, total*penalty[5] is %d\n", pRaInfo->NscDown, + (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]))); + if (pRaInfo->NscDown > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5])) pRaInfo->NscDown -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]; else @@ -285,14 +303,14 @@ static void odm_RateDecision_8188E(struct odm_dm_struct *dm_odm, PenaltyID2 = RETRY_PENALTY_UP_IDX[RateID]; ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, (" NscUp init is %d\n", pRaInfo->NscUp)); - pRaInfo->NscUp += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID2][0]; - pRaInfo->NscUp += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID2][1]; - pRaInfo->NscUp += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID2][2]; - pRaInfo->NscUp += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID2][3]; - pRaInfo->NscUp += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID2][4]; + + for (i = 0 ; i <= 4 ; i++) + pRaInfo->NscUp += pRaInfo->RTY[i] * RETRY_PENALTY[PenaltyID2][i]; + ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("NscUp is %d, total*up[5] is %d\n", pRaInfo->NscUp, (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]))); + if (pRaInfo->NscUp > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5])) pRaInfo->NscUp -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]; else @@ -487,7 +505,7 @@ static void odm_PTDecision_8188E(struct odm_ra_info *pRaInfo) break; } - j = j >> 1; + j >>= 1; temp_stage = (pRaInfo->PTStage + 1) >> 1; if (temp_stage > j) stage_id = temp_stage-j; @@ -538,6 +556,7 @@ int ODM_RAInfo_Init(struct odm_dm_struct *dm_odm, u8 macid) struct odm_ra_info *pRaInfo = &dm_odm->RAInfo[macid]; u8 WirelessMode = 0xFF; /* invalid value */ u8 max_rate_idx = 0x13; /* MCS7 */ + if (dm_odm->pWirelessMode != NULL) WirelessMode = *(dm_odm->pWirelessMode); @@ -618,7 +637,7 @@ u8 ODM_RA_GetDecisionRate_8188E(struct odm_dm_struct *dm_odm, u8 macid) if ((NULL == dm_odm) || (macid >= ASSOCIATE_ENTRY_NUM)) return 0; - DecisionRate = (dm_odm->RAInfo[macid].DecisionRate); + DecisionRate = dm_odm->RAInfo[macid].DecisionRate; ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, (" macid =%d DecisionRate = 0x%x\n", macid, DecisionRate)); return DecisionRate; @@ -630,7 +649,7 @@ u8 ODM_RA_GetHwPwrStatus_8188E(struct odm_dm_struct *dm_odm, u8 macid) if ((NULL == dm_odm) || (macid >= ASSOCIATE_ENTRY_NUM)) return 0; - PTStage = (dm_odm->RAInfo[macid].PTStage); + PTStage = dm_odm->RAInfo[macid].PTStage; ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("macid =%d PTStage = 0x%x\n", macid, PTStage)); return PTStage; diff --git a/drivers/staging/rtl8188eu/hal/bb_cfg.c b/drivers/staging/rtl8188eu/hal/bb_cfg.c index 1e963bf9e48b..8eb2b39a0b67 100644 --- a/drivers/staging/rtl8188eu/hal/bb_cfg.c +++ b/drivers/staging/rtl8188eu/hal/bb_cfg.c @@ -511,62 +511,71 @@ static u32 array_phy_reg_pg_8188e[] = { static void store_pwrindex_offset(struct adapter *Adapter, u32 regaddr, u32 bitmask, u32 data) { struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter); + u8 pwrGrpCnt = hal_data->pwrGroupCnt; if (regaddr == rTxAGC_A_Rate18_06) - hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][0] = data; + hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][0] = data; if (regaddr == rTxAGC_A_Rate54_24) - hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][1] = data; + hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][1] = data; if (regaddr == rTxAGC_A_CCK1_Mcs32) - hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][6] = data; + hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][6] = data; if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) - hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][7] = data; + hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][7] = data; if (regaddr == rTxAGC_A_Mcs03_Mcs00) - hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][2] = data; + hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][2] = data; if (regaddr == rTxAGC_A_Mcs07_Mcs04) - hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][3] = data; + hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][3] = data; if (regaddr == rTxAGC_A_Mcs11_Mcs08) - hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][4] = data; + hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][4] = data; if (regaddr == rTxAGC_A_Mcs15_Mcs12) { - hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][5] = data; + hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][5] = data; if (hal_data->rf_type == RF_1T1R) hal_data->pwrGroupCnt++; } if (regaddr == rTxAGC_B_Rate18_06) - hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][8] = data; + hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][8] = data; if (regaddr == rTxAGC_B_Rate54_24) - hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][9] = data; + hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][9] = data; if (regaddr == rTxAGC_B_CCK1_55_Mcs32) - hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][14] = data; + hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][14] = data; if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) - hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][15] = data; + hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][15] = data; if (regaddr == rTxAGC_B_Mcs03_Mcs00) - hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][10] = data; + hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][10] = data; if (regaddr == rTxAGC_B_Mcs07_Mcs04) - hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][11] = data; + hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][11] = data; if (regaddr == rTxAGC_B_Mcs11_Mcs08) - hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][12] = data; + hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][12] = data; if (regaddr == rTxAGC_B_Mcs15_Mcs12) { - hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][13] = data; + hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][13] = data; if (hal_data->rf_type != RF_1T1R) hal_data->pwrGroupCnt++; } } -static void rtl_addr_delay(struct adapter *adapt, u32 addr, u32 bit_mask, u32 data) +static void rtl_addr_delay(struct adapter *adapt, + u32 addr, u32 bit_mask, u32 data) { - if (addr == 0xfe) { + switch (addr) { + case 0xfe: msleep(50); - } else if (addr == 0xfd) { + break; + case 0xfd: mdelay(5); - } else if (addr == 0xfc) { + break; + case 0xfc: mdelay(1); - } else if (addr == 0xfb) { + break; + case 0xfb: udelay(50); - } else if (addr == 0xfa) { + break; + case 0xfa: udelay(5); - } else if (addr == 0xf9) { + break; + case 0xf9: udelay(1); - } else{ + break; + default: store_pwrindex_offset(adapt, addr, bit_mask, data); } } @@ -591,84 +600,90 @@ static bool config_bb_with_pgheader(struct adapter *adapt) static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *Adapter) { struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter); - - hal_data->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; - hal_data->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; - hal_data->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; - hal_data->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; - - hal_data->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; - hal_data->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; - hal_data->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; - hal_data->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; - - hal_data->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; - hal_data->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; - - hal_data->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; - hal_data->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; - - hal_data->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; - hal_data->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; - - hal_data->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; - hal_data->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; - hal_data->PHYRegDef[RF_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; - hal_data->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; - - hal_data->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; - hal_data->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; - hal_data->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; - hal_data->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; - - hal_data->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; - hal_data->PHYRegDef[RF_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; - - hal_data->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; - hal_data->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; - - hal_data->PHYRegDef[RF_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; - hal_data->PHYRegDef[RF_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; - hal_data->PHYRegDef[RF_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; - hal_data->PHYRegDef[RF_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; - - hal_data->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; - hal_data->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; - hal_data->PHYRegDef[RF_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; - hal_data->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; - - hal_data->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; - hal_data->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; - hal_data->PHYRegDef[RF_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; - hal_data->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; - - hal_data->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; - hal_data->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; - hal_data->PHYRegDef[RF_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; - hal_data->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; - - hal_data->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE; - hal_data->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; - hal_data->PHYRegDef[RF_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; - hal_data->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; - - hal_data->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; - hal_data->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; - hal_data->PHYRegDef[RF_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; - hal_data->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; - - hal_data->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE; - hal_data->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; - hal_data->PHYRegDef[RF_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; - hal_data->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; - - hal_data->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; - hal_data->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; - hal_data->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; - hal_data->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; - - hal_data->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback; - hal_data->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback; + struct bb_reg_def *reg[4]; + + reg[RF_PATH_A] = &(hal_data->PHYRegDef[RF_PATH_A]); + reg[RF_PATH_B] = &(hal_data->PHYRegDef[RF_PATH_B]); + reg[RF_PATH_C] = &(hal_data->PHYRegDef[RF_PATH_C]); + reg[RF_PATH_D] = &(hal_data->PHYRegDef[RF_PATH_D]); + + reg[RF_PATH_A]->rfintfs = rFPGA0_XAB_RFInterfaceSW; + reg[RF_PATH_B]->rfintfs = rFPGA0_XAB_RFInterfaceSW; + reg[RF_PATH_C]->rfintfs = rFPGA0_XCD_RFInterfaceSW; + reg[RF_PATH_D]->rfintfs = rFPGA0_XCD_RFInterfaceSW; + + reg[RF_PATH_A]->rfintfi = rFPGA0_XAB_RFInterfaceRB; + reg[RF_PATH_B]->rfintfi = rFPGA0_XAB_RFInterfaceRB; + reg[RF_PATH_C]->rfintfi = rFPGA0_XCD_RFInterfaceRB; + reg[RF_PATH_D]->rfintfi = rFPGA0_XCD_RFInterfaceRB; + + reg[RF_PATH_A]->rfintfo = rFPGA0_XA_RFInterfaceOE; + reg[RF_PATH_B]->rfintfo = rFPGA0_XB_RFInterfaceOE; + + reg[RF_PATH_A]->rfintfe = rFPGA0_XA_RFInterfaceOE; + reg[RF_PATH_B]->rfintfe = rFPGA0_XB_RFInterfaceOE; + + reg[RF_PATH_A]->rf3wireOffset = rFPGA0_XA_LSSIParameter; + reg[RF_PATH_B]->rf3wireOffset = rFPGA0_XB_LSSIParameter; + + reg[RF_PATH_A]->rfLSSI_Select = rFPGA0_XAB_RFParameter; + reg[RF_PATH_B]->rfLSSI_Select = rFPGA0_XAB_RFParameter; + reg[RF_PATH_C]->rfLSSI_Select = rFPGA0_XCD_RFParameter; + reg[RF_PATH_D]->rfLSSI_Select = rFPGA0_XCD_RFParameter; + + reg[RF_PATH_A]->rfTxGainStage = rFPGA0_TxGainStage; + reg[RF_PATH_B]->rfTxGainStage = rFPGA0_TxGainStage; + reg[RF_PATH_C]->rfTxGainStage = rFPGA0_TxGainStage; + reg[RF_PATH_D]->rfTxGainStage = rFPGA0_TxGainStage; + + reg[RF_PATH_A]->rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; + reg[RF_PATH_B]->rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; + + reg[RF_PATH_A]->rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; + reg[RF_PATH_B]->rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; + + reg[RF_PATH_A]->rfSwitchControl = rFPGA0_XAB_SwitchControl; + reg[RF_PATH_B]->rfSwitchControl = rFPGA0_XAB_SwitchControl; + reg[RF_PATH_C]->rfSwitchControl = rFPGA0_XCD_SwitchControl; + reg[RF_PATH_D]->rfSwitchControl = rFPGA0_XCD_SwitchControl; + + reg[RF_PATH_A]->rfAGCControl1 = rOFDM0_XAAGCCore1; + reg[RF_PATH_B]->rfAGCControl1 = rOFDM0_XBAGCCore1; + reg[RF_PATH_C]->rfAGCControl1 = rOFDM0_XCAGCCore1; + reg[RF_PATH_D]->rfAGCControl1 = rOFDM0_XDAGCCore1; + + reg[RF_PATH_A]->rfAGCControl2 = rOFDM0_XAAGCCore2; + reg[RF_PATH_B]->rfAGCControl2 = rOFDM0_XBAGCCore2; + reg[RF_PATH_C]->rfAGCControl2 = rOFDM0_XCAGCCore2; + reg[RF_PATH_D]->rfAGCControl2 = rOFDM0_XDAGCCore2; + + reg[RF_PATH_A]->rfRxIQImbalance = rOFDM0_XARxIQImbalance; + reg[RF_PATH_B]->rfRxIQImbalance = rOFDM0_XBRxIQImbalance; + reg[RF_PATH_C]->rfRxIQImbalance = rOFDM0_XCRxIQImbalance; + reg[RF_PATH_D]->rfRxIQImbalance = rOFDM0_XDRxIQImbalance; + + reg[RF_PATH_A]->rfRxAFE = rOFDM0_XARxAFE; + reg[RF_PATH_B]->rfRxAFE = rOFDM0_XBRxAFE; + reg[RF_PATH_C]->rfRxAFE = rOFDM0_XCRxAFE; + reg[RF_PATH_D]->rfRxAFE = rOFDM0_XDRxAFE; + + reg[RF_PATH_A]->rfTxIQImbalance = rOFDM0_XATxIQImbalance; + reg[RF_PATH_B]->rfTxIQImbalance = rOFDM0_XBTxIQImbalance; + reg[RF_PATH_C]->rfTxIQImbalance = rOFDM0_XCTxIQImbalance; + reg[RF_PATH_D]->rfTxIQImbalance = rOFDM0_XDTxIQImbalance; + + reg[RF_PATH_A]->rfTxAFE = rOFDM0_XATxAFE; + reg[RF_PATH_B]->rfTxAFE = rOFDM0_XBTxAFE; + reg[RF_PATH_C]->rfTxAFE = rOFDM0_XCTxAFE; + reg[RF_PATH_D]->rfTxAFE = rOFDM0_XDTxAFE; + + reg[RF_PATH_A]->rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; + reg[RF_PATH_B]->rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; + reg[RF_PATH_C]->rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; + reg[RF_PATH_D]->rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; + + reg[RF_PATH_A]->rfLSSIReadBackPi = TransceiverA_HSPI_Readback; + reg[RF_PATH_B]->rfLSSIReadBackPi = TransceiverB_HSPI_Readback; } static bool config_parafile(struct adapter *adapt) diff --git a/drivers/staging/rtl8188eu/hal/fw.c b/drivers/staging/rtl8188eu/hal/fw.c index 3b2875481fc5..a71c54295508 100644 --- a/drivers/staging/rtl8188eu/hal/fw.c +++ b/drivers/staging/rtl8188eu/hal/fw.c @@ -154,9 +154,8 @@ static int _rtl88e_fw_free_to_go(struct adapter *adapt) break; } while (counter++ < POLLING_READY_TIMEOUT_COUNT); - if (counter >= POLLING_READY_TIMEOUT_COUNT) { + if (counter >= POLLING_READY_TIMEOUT_COUNT) goto exit; - } value32 = usb_read32(adapt, REG_MCUFWDL); value32 |= MCUFWDL_RDY; diff --git a/drivers/staging/rtl8188eu/hal/odm.c b/drivers/staging/rtl8188eu/hal/odm.c index 06477e834653..28b5e7bd4fc0 100644 --- a/drivers/staging/rtl8188eu/hal/odm.c +++ b/drivers/staging/rtl8188eu/hal/odm.c @@ -741,13 +741,13 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); - FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16); + FalseAlmCnt->Cnt_SB_Search_fail = (ret_value & 0xffff0000)>>16; ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff); - FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16); + FalseAlmCnt->Cnt_Parity_Fail = (ret_value & 0xffff0000)>>16; ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff); - FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16); + FalseAlmCnt->Cnt_Crc8_fail = (ret_value & 0xffff0000)>>16; ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff); @@ -757,7 +757,7 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) ret_value = phy_query_bb_reg(adapter, ODM_REG_SC_CNT_11N, bMaskDWord); FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff); - FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16); + FalseAlmCnt->Cnt_BW_USC = (ret_value & 0xffff0000)>>16; /* hold cck counter */ phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1); diff --git a/drivers/staging/rtl8188eu/hal/odm_HWConfig.c b/drivers/staging/rtl8188eu/hal/odm_HWConfig.c index 29f87dffbad3..36afe45d1c9a 100644 --- a/drivers/staging/rtl8188eu/hal/odm_HWConfig.c +++ b/drivers/staging/rtl8188eu/hal/odm_HWConfig.c @@ -123,8 +123,8 @@ static void odm_RxPhyStatus92CSeries_Parsing(struct odm_dm_struct *dm_odm, /* 2011.11.28 LukeLee: 88E use different LNA & VGA gain table */ /* The RSSI formula should be modified according to the gain table */ /* In 88E, cck_highpwr is always set to 1 */ - LNA_idx = ((cck_agc_rpt & 0xE0) >> 5); - VGA_idx = (cck_agc_rpt & 0x1F); + LNA_idx = (cck_agc_rpt & 0xE0) >> 5; + VGA_idx = cck_agc_rpt & 0x1F; switch (LNA_idx) { case 7: if (VGA_idx <= 27) diff --git a/drivers/staging/rtl8188eu/hal/phy.c b/drivers/staging/rtl8188eu/hal/phy.c index 3f663fe151ba..6e4c3ee0399a 100644 --- a/drivers/staging/rtl8188eu/hal/phy.c +++ b/drivers/staging/rtl8188eu/hal/phy.c @@ -60,7 +60,7 @@ void phy_set_bb_reg(struct adapter *adapt, u32 regaddr, u32 bitmask, u32 data) if (bitmask != bMaskDWord) { /* if not "double word" write */ original_value = usb_read32(adapt, regaddr); bit_shift = cal_bit_shift(bitmask); - data = ((original_value & (~bitmask)) | (data << bit_shift)); + data = (original_value & (~bitmask)) | (data << bit_shift); } usb_write32(adapt, regaddr, data); @@ -72,12 +72,10 @@ static u32 rf_serial_read(struct adapter *adapt, u32 ret = 0; struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); struct bb_reg_def *phyreg = &hal_data->PHYRegDef[rfpath]; - u32 newoffset; u32 tmplong, tmplong2; u8 rfpi_enable = 0; offset &= 0xff; - newoffset = offset; tmplong = phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter2, bMaskDWord); if (rfpath == RF_PATH_A) @@ -87,7 +85,7 @@ static u32 rf_serial_read(struct adapter *adapt, bMaskDWord); tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | - (newoffset<<23) | bLSSIReadEdge; + (offset<<23) | bLSSIReadEdge; phy_set_bb_reg(adapt, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge)); @@ -119,10 +117,9 @@ static void rf_serial_write(struct adapter *adapt, u32 data_and_addr = 0; struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); struct bb_reg_def *phyreg = &hal_data->PHYRegDef[rfpath]; - u32 newoffset; - newoffset = offset & 0xff; - data_and_addr = ((newoffset<<20) | (data&0x000fffff)) & 0x0fffffff; + offset &= 0xff; + data_and_addr = ((offset<<20) | (data&0x000fffff)) & 0x0fffffff; phy_set_bb_reg(adapt, phyreg->rf3wireOffset, bMaskDWord, data_and_addr); } @@ -146,7 +143,7 @@ void phy_set_rf_reg(struct adapter *adapt, enum rf_radio_path rf_path, if (bit_mask != bRFRegOffsetMask) { original_value = rf_serial_read(adapt, rf_path, reg_addr); bit_shift = cal_bit_shift(bit_mask); - data = ((original_value & (~bit_mask)) | (data << bit_shift)); + data = (original_value & (~bit_mask)) | (data << bit_shift); } rf_serial_write(adapt, rf_path, reg_addr, data); @@ -304,21 +301,8 @@ static void phy_set_bw_mode_callback(struct adapter *adapt) } /* Set RF related register */ - switch (hal_data->rf_chip) { - case RF_8225: - break; - case RF_8256: - break; - case RF_8258: - break; - case RF_PSEUDO_11N: - break; - case RF_6052: + if (hal_data->rf_chip == RF_6052) rtl88eu_phy_rf6052_set_bandwidth(adapt, hal_data->CurrentChannelBW); - break; - default: - break; - } } void phy_set_bw_mode(struct adapter *adapt, enum ht_channel_width bandwidth, @@ -361,7 +345,6 @@ void phy_sw_chnl(struct adapter *adapt, u8 channel) { struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); u8 tmpchannel = hal_data->CurrentChannel; - bool result = true; if (hal_data->rf_chip == RF_PSEUDO_11N) return; @@ -371,34 +354,28 @@ void phy_sw_chnl(struct adapter *adapt, u8 channel) hal_data->CurrentChannel = channel; - if ((!adapt->bDriverStopped) && (!adapt->bSurpriseRemoved)) { + if ((!adapt->bDriverStopped) && (!adapt->bSurpriseRemoved)) phy_sw_chnl_callback(adapt, channel); - - if (!result) - hal_data->CurrentChannel = tmpchannel; - - } else { + else hal_data->CurrentChannel = tmpchannel; - } } #define ODM_TXPWRTRACK_MAX_IDX_88E 6 static u8 get_right_chnl_for_iqk(u8 chnl) { + u8 place; u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165 }; - u8 place = chnl; if (chnl > 14) { - for (place = 14; place < sizeof(channel_all); place++) { + for (place = 0; place < sizeof(channel_all); place++) { if (channel_all[place] == chnl) - return place-13; + return ++place; } } return 0; @@ -416,12 +393,12 @@ void rtl88eu_dm_txpower_track_adjust(struct odm_dm_struct *dm_odm, u8 type, if (dm_odm->BbSwingIdxOfdm <= dm_odm->BbSwingIdxOfdmBase) { *direction = 1; - pwr_value = (dm_odm->BbSwingIdxOfdmBase - - dm_odm->BbSwingIdxOfdm); + pwr_value = dm_odm->BbSwingIdxOfdmBase - + dm_odm->BbSwingIdxOfdm; } else { *direction = 2; - pwr_value = (dm_odm->BbSwingIdxOfdm - - dm_odm->BbSwingIdxOfdmBase); + pwr_value = dm_odm->BbSwingIdxOfdm - + dm_odm->BbSwingIdxOfdmBase; } } else if (type == 1) { /* For CCK adjust. */ @@ -431,12 +408,12 @@ void rtl88eu_dm_txpower_track_adjust(struct odm_dm_struct *dm_odm, u8 type, if (dm_odm->BbSwingIdxCck <= dm_odm->BbSwingIdxCckBase) { *direction = 1; - pwr_value = (dm_odm->BbSwingIdxCckBase - - dm_odm->BbSwingIdxCck); + pwr_value = dm_odm->BbSwingIdxCckBase - + dm_odm->BbSwingIdxCck; } else { *direction = 2; - pwr_value = (dm_odm->BbSwingIdxCck - - dm_odm->BbSwingIdxCckBase); + pwr_value = dm_odm->BbSwingIdxCck - + dm_odm->BbSwingIdxCckBase; } } @@ -465,15 +442,13 @@ void rtl88eu_dm_txpower_tracking_callback_thermalmeter(struct adapter *adapt) u8 thermal_val = 0, delta, delta_lck, delta_iqk, offset; u8 thermal_avg_count = 0; u32 thermal_avg = 0; - s32 ele_a = 0, ele_d, temp_cck, x, value32; - s32 y, ele_c = 0; + s32 ele_d, temp_cck; s8 ofdm_index[2], cck_index = 0; s8 ofdm_index_old[2] = {0, 0}, cck_index_old = 0; u32 i = 0, j = 0; bool is2t = false; u8 ofdm_min_index = 6, rf; /* OFDM BB Swing should be less than +3.0dB */ - u8 indexforchannel = 0; s8 ofdm_index_mapping[2][index_mapping_NUM_88E] = { /* 2.4G, decrease power */ {0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11}, @@ -529,18 +504,12 @@ void rtl88eu_dm_txpower_tracking_callback_thermalmeter(struct adapter *adapt) temp_cck = dm_odm->RFCalibrateInfo.RegA24; for (i = 0; i < CCK_TABLE_SIZE; i++) { - if (dm_odm->RFCalibrateInfo.bCCKinCH14) { - if (memcmp(&temp_cck, &CCKSwingTable_Ch14[i][2], 4)) { - cck_index_old = (u8)i; - dm_odm->BbSwingIdxCckBase = (u8)i; - break; - } - } else { - if (memcmp(&temp_cck, &CCKSwingTable_Ch1_Ch13[i][2], 4)) { + if ((dm_odm->RFCalibrateInfo.bCCKinCH14 && + memcmp(&temp_cck, &CCKSwingTable_Ch14[i][2], 4)) || + memcmp(&temp_cck, &CCKSwingTable_Ch1_Ch13[i][2], 4)) { cck_index_old = (u8)i; dm_odm->BbSwingIdxCckBase = (u8)i; break; - } } } @@ -570,27 +539,19 @@ void rtl88eu_dm_txpower_tracking_callback_thermalmeter(struct adapter *adapt) if (thermal_avg_count) thermal_val = (u8)(thermal_avg / thermal_avg_count); - if (dm_odm->RFCalibrateInfo.bReloadtxpowerindex) { - delta = thermal_val > hal_data->EEPROMThermalMeter ? - (thermal_val - hal_data->EEPROMThermalMeter) : - (hal_data->EEPROMThermalMeter - thermal_val); - dm_odm->RFCalibrateInfo.bReloadtxpowerindex = false; - dm_odm->RFCalibrateInfo.bDoneTxpower = false; - } else if (dm_odm->RFCalibrateInfo.bDoneTxpower) { - delta = (thermal_val > dm_odm->RFCalibrateInfo.ThermalValue) ? - (thermal_val - dm_odm->RFCalibrateInfo.ThermalValue) : - (dm_odm->RFCalibrateInfo.ThermalValue - thermal_val); - } else { - delta = thermal_val > hal_data->EEPROMThermalMeter ? - (thermal_val - hal_data->EEPROMThermalMeter) : - (hal_data->EEPROMThermalMeter - thermal_val); + if (dm_odm->RFCalibrateInfo.bDoneTxpower && + !dm_odm->RFCalibrateInfo.bReloadtxpowerindex) + delta = abs(thermal_val - dm_odm->RFCalibrateInfo.ThermalValue); + else { + delta = abs(thermal_val - hal_data->EEPROMThermalMeter); + if (dm_odm->RFCalibrateInfo.bReloadtxpowerindex) { + dm_odm->RFCalibrateInfo.bReloadtxpowerindex = false; + dm_odm->RFCalibrateInfo.bDoneTxpower = false; + } } - delta_lck = (thermal_val > dm_odm->RFCalibrateInfo.ThermalValue_LCK) ? - (thermal_val - dm_odm->RFCalibrateInfo.ThermalValue_LCK) : - (dm_odm->RFCalibrateInfo.ThermalValue_LCK - thermal_val); - delta_iqk = (thermal_val > dm_odm->RFCalibrateInfo.ThermalValue_IQK) ? - (thermal_val - dm_odm->RFCalibrateInfo.ThermalValue_IQK) : - (dm_odm->RFCalibrateInfo.ThermalValue_IQK - thermal_val); + + delta_lck = abs(dm_odm->RFCalibrateInfo.ThermalValue_LCK - thermal_val); + delta_iqk = abs(dm_odm->RFCalibrateInfo.ThermalValue_IQK - thermal_val); /* Delta temperature is equal to or larger than 20 centigrade.*/ if ((delta_lck >= 8)) { @@ -599,9 +560,8 @@ void rtl88eu_dm_txpower_tracking_callback_thermalmeter(struct adapter *adapt) } if (delta > 0 && dm_odm->RFCalibrateInfo.TxPowerTrackControl) { - delta = thermal_val > hal_data->EEPROMThermalMeter ? - (thermal_val - hal_data->EEPROMThermalMeter) : - (hal_data->EEPROMThermalMeter - thermal_val); + delta = abs(hal_data->EEPROMThermalMeter - thermal_val); + /* calculate new OFDM / CCK offset */ if (thermal_val > hal_data->EEPROMThermalMeter) j = 1; @@ -616,17 +576,17 @@ void rtl88eu_dm_txpower_tracking_callback_thermalmeter(struct adapter *adapt) } if (offset >= index_mapping_NUM_88E) offset = index_mapping_NUM_88E-1; - for (i = 0; i < rf; i++) - ofdm_index[i] = dm_odm->RFCalibrateInfo.OFDM_index[i] + ofdm_index_mapping[j][offset]; - cck_index = dm_odm->RFCalibrateInfo.CCK_index + ofdm_index_mapping[j][offset]; + /* Updating ofdm_index values with new OFDM / CCK offset */ for (i = 0; i < rf; i++) { + ofdm_index[i] = dm_odm->RFCalibrateInfo.OFDM_index[i] + ofdm_index_mapping[j][offset]; if (ofdm_index[i] > OFDM_TABLE_SIZE_92D-1) ofdm_index[i] = OFDM_TABLE_SIZE_92D-1; else if (ofdm_index[i] < ofdm_min_index) ofdm_index[i] = ofdm_min_index; } + cck_index = dm_odm->RFCalibrateInfo.CCK_index + ofdm_index_mapping[j][offset]; if (cck_index > CCK_TABLE_SIZE-1) cck_index = CCK_TABLE_SIZE-1; else if (cck_index < 0) @@ -637,11 +597,6 @@ void rtl88eu_dm_txpower_tracking_callback_thermalmeter(struct adapter *adapt) if (dm_odm->RFCalibrateInfo.TxPowerTrackControl) { dm_odm->RFCalibrateInfo.bDoneTxpower = true; - /* Adujst OFDM Ant_A according to IQK result */ - ele_d = (OFDMSwingTable[(u8)ofdm_index[0]] & 0xFFC00000)>>22; - x = dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[indexforchannel].Value[0][0]; - y = dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[indexforchannel].Value[0][1]; - /* Revse TX power table. */ dm_odm->BbSwingIdxOfdm = (u8)ofdm_index[0]; dm_odm->BbSwingIdxCck = (u8)cck_index; @@ -655,53 +610,6 @@ void rtl88eu_dm_txpower_tracking_callback_thermalmeter(struct adapter *adapt) dm_odm->BbSwingIdxCckCurrent = dm_odm->BbSwingIdxCck; dm_odm->BbSwingFlagCck = true; } - - if (x != 0) { - if ((x & 0x00000200) != 0) - x = x | 0xFFFFFC00; - ele_a = ((x * ele_d)>>8)&0x000003FF; - - /* new element C = element D x Y */ - if ((y & 0x00000200) != 0) - y = y | 0xFFFFFC00; - ele_c = ((y * ele_d)>>8)&0x000003FF; - - } - - if (is2t) { - ele_d = (OFDMSwingTable[(u8)ofdm_index[1]] & 0xFFC00000)>>22; - - /* new element A = element D x X */ - x = dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[indexforchannel].Value[0][4]; - y = dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[indexforchannel].Value[0][5]; - - if ((x != 0) && (*(dm_odm->pBandType) == ODM_BAND_2_4G)) { - if ((x & 0x00000200) != 0) /* consider minus */ - x = x | 0xFFFFFC00; - ele_a = ((x * ele_d)>>8)&0x000003FF; - - /* new element C = element D x Y */ - if ((y & 0x00000200) != 0) - y = y | 0xFFFFFC00; - ele_c = ((y * ele_d)>>8)&0x00003FF; - - /* wtite new elements A, C, D to regC88 and regC9C, element B is always 0 */ - value32 = (ele_d<<22) | ((ele_c&0x3F)<<16) | ele_a; - phy_set_bb_reg(adapt, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); - - value32 = (ele_c&0x000003C0)>>6; - phy_set_bb_reg(adapt, rOFDM0_XDTxAFE, bMaskH4Bits, value32); - - value32 = ((x * ele_d)>>7)&0x01; - phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT28, value32); - } else { - phy_set_bb_reg(adapt, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[(u8)ofdm_index[1]]); - phy_set_bb_reg(adapt, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); - phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT28, 0x00); - } - - } - } } @@ -1033,11 +941,11 @@ static void path_adda_on(struct adapter *adapt, u32 *adda_reg, u32 path_on; u32 i; - path_on = is_path_a_on ? 0x04db25a4 : 0x0b1b25a4; if (!is2t) { path_on = 0x0bdb25a0; phy_set_bb_reg(adapt, adda_reg[0], bMaskDWord, 0x0b1b25a0); } else { + path_on = is_path_a_on ? 0x04db25a4 : 0x0b1b25a4; phy_set_bb_reg(adapt, adda_reg[0], bMaskDWord, path_on); } @@ -1077,27 +985,19 @@ static void pi_mode_switch(struct adapter *adapt, bool pi_mode) static bool simularity_compare(struct adapter *adapt, s32 resulta[][8], u8 c1, u8 c2) { - u32 i, j, diff, sim_bitmap, bound = 0; + u32 i, j, diff, sim_bitmap = 0, bound; struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); struct odm_dm_struct *dm_odm = &hal_data->odmpriv; u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ bool result = true; - bool is2t; s32 tmp1 = 0, tmp2 = 0; if ((dm_odm->RFType == ODM_2T2R) || (dm_odm->RFType == ODM_2T3R) || (dm_odm->RFType == ODM_2T4R)) - is2t = true; - else - is2t = false; - - if (is2t) bound = 8; else bound = 4; - sim_bitmap = 0; - for (i = 0; i < bound; i++) { if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { if ((resulta[c1][i] & 0x00000200) != 0) diff --git a/drivers/staging/rtl8188eu/hal/pwrseqcmd.c b/drivers/staging/rtl8188eu/hal/pwrseqcmd.c index be0663e93f61..73e1f8b36b37 100644 --- a/drivers/staging/rtl8188eu/hal/pwrseqcmd.c +++ b/drivers/staging/rtl8188eu/hal/pwrseqcmd.c @@ -109,7 +109,6 @@ u8 rtl88eu_pwrseqcmdparsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers, RT_TRACE(_module_hal_init_c_, _drv_info_, ("rtl88eu_pwrseqcmdparsing: PWR_CMD_END\n")); return true; - break; default: RT_TRACE(_module_hal_init_c_, _drv_err_, ("rtl88eu_pwrseqcmdparsing: Unknown CMD!!\n")); diff --git a/drivers/staging/rtl8188eu/hal/rf.c b/drivers/staging/rtl8188eu/hal/rf.c index eea4c8a6022b..097092772a86 100644 --- a/drivers/staging/rtl8188eu/hal/rf.c +++ b/drivers/staging/rtl8188eu/hal/rf.c @@ -201,7 +201,7 @@ static void get_rx_power_val_by_reg(struct adapter *adapt, u8 channel, break; case 2: /* Better regulatory */ /* don't increase any power diff */ - write_val = ((index < 2) ? powerbase0[rf] : powerbase1[rf]); + write_val = (index < 2) ? powerbase0[rf] : powerbase1[rf]; break; case 3: /* Customer defined power diff. */ /* increase power diff defined by customer. */ diff --git a/drivers/staging/rtl8188eu/hal/rf_cfg.c b/drivers/staging/rtl8188eu/hal/rf_cfg.c index 5dc11cae2ef9..455ecdc8d9fa 100644 --- a/drivers/staging/rtl8188eu/hal/rf_cfg.c +++ b/drivers/staging/rtl8188eu/hal/rf_cfg.c @@ -38,12 +38,12 @@ static bool check_condition(struct adapter *adapt, const u32 condition) return false; cond = condition & 0x0000FF00; - cond = cond >> 8; + cond >>= 8; if ((_interface & cond) == 0 && cond != 0x07) return false; cond = condition & 0x00FF0000; - cond = cond >> 16; + cond >>= 16; if ((_platform & cond) == 0 && cond != 0x0F) return false; return true; diff --git a/drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c b/drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c index 3222d8d08b5b..7904d2260f2c 100644 --- a/drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c +++ b/drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c @@ -596,7 +596,8 @@ void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo, bool AutoL struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter); if (!AutoLoadFail) - pHalData->BoardType = ((hwinfo[EEPROM_RF_BOARD_OPTION_88E]&0xE0)>>5); + pHalData->BoardType = (hwinfo[EEPROM_RF_BOARD_OPTION_88E] + & 0xE0) >> 5; else pHalData->BoardType = 0; DBG_88E("Board Type: 0x%2x\n", pHalData->BoardType); diff --git a/drivers/staging/rtl8188eu/hal/rtl8188eu_recv.c b/drivers/staging/rtl8188eu/hal/rtl8188eu_recv.c index bc275b2a7d37..06d1e654483e 100644 --- a/drivers/staging/rtl8188eu/hal/rtl8188eu_recv.c +++ b/drivers/staging/rtl8188eu/hal/rtl8188eu_recv.c @@ -42,7 +42,7 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter) _rtw_init_queue(&precvpriv->free_recv_buf_queue); precvpriv->pallocated_recv_buf = - kzalloc(NR_RECVBUFF * sizeof(struct recv_buf), GFP_KERNEL); + kcalloc(NR_RECVBUFF, sizeof(struct recv_buf), GFP_KERNEL); if (precvpriv->pallocated_recv_buf == NULL) { res = _FAIL; RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, diff --git a/drivers/staging/rtl8188eu/hal/usb_halinit.c b/drivers/staging/rtl8188eu/hal/usb_halinit.c index 14650e91c78a..7b01d5aa6b23 100644 --- a/drivers/staging/rtl8188eu/hal/usb_halinit.c +++ b/drivers/staging/rtl8188eu/hal/usb_halinit.c @@ -1096,10 +1096,8 @@ static void Hal_EfuseParseMACAddr_8188EU(struct adapter *adapt, u8 *hwinfo, bool memcpy(eeprom->mac_addr, &hwinfo[EEPROM_MAC_ADDR_88EU], ETH_ALEN); } RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, - ("Hal_EfuseParseMACAddr_8188EU: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n", - eeprom->mac_addr[0], eeprom->mac_addr[1], - eeprom->mac_addr[2], eeprom->mac_addr[3], - eeprom->mac_addr[4], eeprom->mac_addr[5])); + ("Hal_EfuseParseMACAddr_8188EU: Permanent Address = %pM\n", + eeprom->mac_addr)); } static void @@ -1352,7 +1350,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val) /* Set RTS initial rate */ while (BrateCfg > 0x1) { - BrateCfg = (BrateCfg >> 1); + BrateCfg >>= 1; RateIndex++; } /* Ziv - Check */ |