diff options
Diffstat (limited to 'drivers/staging/rtl8188eu/include')
-rw-r--r-- | drivers/staging/rtl8188eu/include/Hal8188EPhyCfg.h | 14 | ||||
-rw-r--r-- | drivers/staging/rtl8188eu/include/basic_types.h | 6 | ||||
-rw-r--r-- | drivers/staging/rtl8188eu/include/drv_types.h | 2 | ||||
-rw-r--r-- | drivers/staging/rtl8188eu/include/hal_intf.h | 16 | ||||
-rw-r--r-- | drivers/staging/rtl8188eu/include/ieee80211.h | 4 | ||||
-rw-r--r-- | drivers/staging/rtl8188eu/include/mon.h | 36 | ||||
-rw-r--r-- | drivers/staging/rtl8188eu/include/odm.h | 90 | ||||
-rw-r--r-- | drivers/staging/rtl8188eu/include/odm_debug.h | 42 | ||||
-rw-r--r-- | drivers/staging/rtl8188eu/include/odm_reg.h | 2 | ||||
-rw-r--r-- | drivers/staging/rtl8188eu/include/osdep_service.h | 48 | ||||
-rw-r--r-- | drivers/staging/rtl8188eu/include/pwrseq.h | 84 | ||||
-rw-r--r-- | drivers/staging/rtl8188eu/include/rtl8188e_spec.h | 415 | ||||
-rw-r--r-- | drivers/staging/rtl8188eu/include/rtw_security.h | 3 | ||||
-rw-r--r-- | drivers/staging/rtl8188eu/include/rtw_sreset.h | 14 | ||||
-rw-r--r-- | drivers/staging/rtl8188eu/include/wifi.h | 12 |
15 files changed, 360 insertions, 428 deletions
diff --git a/drivers/staging/rtl8188eu/include/Hal8188EPhyCfg.h b/drivers/staging/rtl8188eu/include/Hal8188EPhyCfg.h index 20e6b40fc35c..e058162fe2ba 100644 --- a/drivers/staging/rtl8188eu/include/Hal8188EPhyCfg.h +++ b/drivers/staging/rtl8188eu/include/Hal8188EPhyCfg.h @@ -87,13 +87,13 @@ enum rf_radio_path { enum wireless_mode { WIRELESS_MODE_UNKNOWN = 0x00, - WIRELESS_MODE_A = BIT2, - WIRELESS_MODE_B = BIT0, - WIRELESS_MODE_G = BIT1, - WIRELESS_MODE_AUTO = BIT5, - WIRELESS_MODE_N_24G = BIT3, - WIRELESS_MODE_N_5G = BIT4, - WIRELESS_MODE_AC = BIT6 + WIRELESS_MODE_A = BIT(2), + WIRELESS_MODE_B = BIT(0), + WIRELESS_MODE_G = BIT(1), + WIRELESS_MODE_AUTO = BIT(5), + WIRELESS_MODE_N_24G = BIT(3), + WIRELESS_MODE_N_5G = BIT(4), + WIRELESS_MODE_AC = BIT(6) }; enum phy_rate_tx_offset_area { diff --git a/drivers/staging/rtl8188eu/include/basic_types.h b/drivers/staging/rtl8188eu/include/basic_types.h index 8a7ca992674a..6a2a147e6d15 100644 --- a/drivers/staging/rtl8188eu/include/basic_types.h +++ b/drivers/staging/rtl8188eu/include/basic_types.h @@ -20,9 +20,6 @@ #ifndef __BASIC_TYPES_H__ #define __BASIC_TYPES_H__ -#define SUCCESS 0 -#define FAIL (-1) - #include <linux/types.h> #define NDIS_OID uint @@ -30,9 +27,6 @@ typedef void (*proc_t)(void *); #define FIELD_OFFSET(s, field) ((ssize_t)&((s *)(0))->field) -#define MEM_ALIGNMENT_OFFSET (sizeof(size_t)) -#define MEM_ALIGNMENT_PADDING (sizeof(size_t) - 1) - /* port from fw */ /* TODO: Macros Below are Sync from SD7-Driver. It is necessary * to check correctness */ diff --git a/drivers/staging/rtl8188eu/include/drv_types.h b/drivers/staging/rtl8188eu/include/drv_types.h index bcc74dcd8207..0729bd40b02a 100644 --- a/drivers/staging/rtl8188eu/include/drv_types.h +++ b/drivers/staging/rtl8188eu/include/drv_types.h @@ -131,6 +131,7 @@ struct registry_priv { u8 if2name[16]; u8 notch_filter; + bool monitor_enable; }; /* For registry parameters */ @@ -209,6 +210,7 @@ struct adapter { void (*intf_start)(struct adapter *adapter); void (*intf_stop)(struct adapter *adapter); struct net_device *pnetdev; + struct net_device *pmondev; /* used by rtw_rereg_nd_name related function */ struct rereg_nd_name_data { diff --git a/drivers/staging/rtl8188eu/include/hal_intf.h b/drivers/staging/rtl8188eu/include/hal_intf.h index e73c6341248e..1b1c10292456 100644 --- a/drivers/staging/rtl8188eu/include/hal_intf.h +++ b/drivers/staging/rtl8188eu/include/hal_intf.h @@ -25,10 +25,10 @@ #include <Hal8188EPhyCfg.h> enum RTL871X_HCI_TYPE { - RTW_PCIE = BIT0, - RTW_USB = BIT1, - RTW_SDIO = BIT2, - RTW_GSPI = BIT3, + RTW_PCIE = BIT(0), + RTW_USB = BIT(1), + RTW_SDIO = BIT(2), + RTW_GSPI = BIT(3), }; enum _CHIP_TYPE { @@ -226,10 +226,10 @@ enum rt_eeprom_type { }; #define RF_CHANGE_BY_INIT 0 -#define RF_CHANGE_BY_IPS BIT28 -#define RF_CHANGE_BY_PS BIT29 -#define RF_CHANGE_BY_HW BIT30 -#define RF_CHANGE_BY_SW BIT31 +#define RF_CHANGE_BY_IPS BIT(28) +#define RF_CHANGE_BY_PS BIT(29) +#define RF_CHANGE_BY_HW BIT(30) +#define RF_CHANGE_BY_SW BIT(31) enum hardware_type { HARDWARE_TYPE_RTL8188EU, diff --git a/drivers/staging/rtl8188eu/include/ieee80211.h b/drivers/staging/rtl8188eu/include/ieee80211.h index 6400f75707bd..f8f5eb6b7976 100644 --- a/drivers/staging/rtl8188eu/include/ieee80211.h +++ b/drivers/staging/rtl8188eu/include/ieee80211.h @@ -1092,8 +1092,8 @@ enum parse_res rtw_ieee802_11_parse_elems(u8 *start, uint len, struct rtw_ieee802_11_elems *elems, int show_errors); -u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, - unsigned char *source, unsigned int *frlen); +u8 *rtw_set_fixed_ie(void *pbuf, unsigned int len, + void *source, unsigned int *frlen); u8 *rtw_set_ie(u8 *pbuf, int index, uint len, u8 *source, uint *frlen); enum secondary_ch_offset { diff --git a/drivers/staging/rtl8188eu/include/mon.h b/drivers/staging/rtl8188eu/include/mon.h new file mode 100644 index 000000000000..f31fa688e092 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/mon.h @@ -0,0 +1,36 @@ +/* + * RTL8188EU monitor interface + * + * Copyright (C) 2015 Jakub Sitnicki + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more + * details. + */ + +/* + * Monitor interface receives all transmitted and received IEEE 802.11 + * frames, both Data and Management, and passes them up to userspace + * preserving the WLAN headers. + */ + +#ifndef _MON_H_ +#define _MON_H_ + +struct net_device; +struct recv_frame; +struct xmit_frame; + +struct net_device *rtl88eu_mon_init(void); +void rtl88eu_mon_deinit(struct net_device *dev); + +void rtl88eu_mon_recv_hook(struct net_device *dev, struct recv_frame *frame); +void rtl88eu_mon_xmit_hook(struct net_device *dev, struct xmit_frame *frame, + uint frag_len); + +#endif /* _MON_H_ */ diff --git a/drivers/staging/rtl8188eu/include/odm.h b/drivers/staging/rtl8188eu/include/odm.h index 73ef9c7596c1..bc970caf7eda 100644 --- a/drivers/staging/rtl8188eu/include/odm.h +++ b/drivers/staging/rtl8188eu/include/odm.h @@ -414,31 +414,31 @@ enum odm_common_info_def { enum odm_ability_def { /* BB ODM section BIT 0-15 */ - ODM_BB_DIG = BIT0, - ODM_BB_RA_MASK = BIT1, - ODM_BB_DYNAMIC_TXPWR = BIT2, - ODM_BB_FA_CNT = BIT3, - ODM_BB_RSSI_MONITOR = BIT4, - ODM_BB_CCK_PD = BIT5, - ODM_BB_ANT_DIV = BIT6, - ODM_BB_PWR_SAVE = BIT7, - ODM_BB_PWR_TRA = BIT8, - ODM_BB_RATE_ADAPTIVE = BIT9, - ODM_BB_PATH_DIV = BIT10, - ODM_BB_PSD = BIT11, - ODM_BB_RXHP = BIT12, + ODM_BB_DIG = BIT(0), + ODM_BB_RA_MASK = BIT(1), + ODM_BB_DYNAMIC_TXPWR = BIT(2), + ODM_BB_FA_CNT = BIT(3), + ODM_BB_RSSI_MONITOR = BIT(4), + ODM_BB_CCK_PD = BIT(5), + ODM_BB_ANT_DIV = BIT(6), + ODM_BB_PWR_SAVE = BIT(7), + ODM_BB_PWR_TRA = BIT(8), + ODM_BB_RATE_ADAPTIVE = BIT(9), + ODM_BB_PATH_DIV = BIT(10), + ODM_BB_PSD = BIT(11), + ODM_BB_RXHP = BIT(12), /* MAC DM section BIT 16-23 */ - ODM_MAC_EDCA_TURBO = BIT16, - ODM_MAC_EARLY_MODE = BIT17, + ODM_MAC_EDCA_TURBO = BIT(16), + ODM_MAC_EARLY_MODE = BIT(17), /* RF ODM section BIT 24-31 */ - ODM_RF_TX_PWR_TRACK = BIT24, - ODM_RF_RX_GAIN_TRACK = BIT25, - ODM_RF_CALIBRATION = BIT26, + ODM_RF_TX_PWR_TRACK = BIT(24), + ODM_RF_RX_GAIN_TRACK = BIT(25), + ODM_RF_CALIBRATION = BIT(26), }; -#define ODM_RTL8188E BIT4 +#define ODM_RTL8188E BIT(4) /* ODM_CMNINFO_CUT_VER */ enum odm_cut_version { @@ -460,14 +460,14 @@ enum odm_fab_Version { /* ODM_CMNINFO_RF_TYPE */ /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ enum odm_rf_path { - ODM_RF_TX_A = BIT0, - ODM_RF_TX_B = BIT1, - ODM_RF_TX_C = BIT2, - ODM_RF_TX_D = BIT3, - ODM_RF_RX_A = BIT4, - ODM_RF_RX_B = BIT5, - ODM_RF_RX_C = BIT6, - ODM_RF_RX_D = BIT7, + ODM_RF_TX_A = BIT(0), + ODM_RF_TX_B = BIT(1), + ODM_RF_TX_C = BIT(2), + ODM_RF_TX_D = BIT(3), + ODM_RF_RX_A = BIT(4), + ODM_RF_RX_B = BIT(5), + ODM_RF_RX_C = BIT(6), + ODM_RF_RX_D = BIT(7), }; enum odm_rf_type { @@ -498,33 +498,33 @@ enum odm_bt_coexist { /* ODM_CMNINFO_OP_MODE */ enum odm_operation_mode { - ODM_NO_LINK = BIT0, - ODM_LINK = BIT1, - ODM_SCAN = BIT2, - ODM_POWERSAVE = BIT3, - ODM_AP_MODE = BIT4, - ODM_CLIENT_MODE = BIT5, - ODM_AD_HOC = BIT6, - ODM_WIFI_DIRECT = BIT7, - ODM_WIFI_DISPLAY = BIT8, + ODM_NO_LINK = BIT(0), + ODM_LINK = BIT(1), + ODM_SCAN = BIT(2), + ODM_POWERSAVE = BIT(3), + ODM_AP_MODE = BIT(4), + ODM_CLIENT_MODE = BIT(5), + ODM_AD_HOC = BIT(6), + ODM_WIFI_DIRECT = BIT(7), + ODM_WIFI_DISPLAY = BIT(8), }; /* ODM_CMNINFO_WM_MODE */ enum odm_wireless_mode { ODM_WM_UNKNOW = 0x0, - ODM_WM_B = BIT0, - ODM_WM_G = BIT1, - ODM_WM_A = BIT2, - ODM_WM_N24G = BIT3, - ODM_WM_N5G = BIT4, - ODM_WM_AUTO = BIT5, - ODM_WM_AC = BIT6, + ODM_WM_B = BIT(0), + ODM_WM_G = BIT(1), + ODM_WM_A = BIT(2), + ODM_WM_N24G = BIT(3), + ODM_WM_N5G = BIT(4), + ODM_WM_AUTO = BIT(5), + ODM_WM_AC = BIT(6), }; /* ODM_CMNINFO_BAND */ enum odm_band_type { - ODM_BAND_2_4G = BIT0, - ODM_BAND_5G = BIT1, + ODM_BAND_2_4G = BIT(0), + ODM_BAND_5G = BIT(1), }; /* ODM_CMNINFO_SEC_CHNL_OFFSET */ diff --git a/drivers/staging/rtl8188eu/include/odm_debug.h b/drivers/staging/rtl8188eu/include/odm_debug.h index 914f831a5b77..e9390963d6ff 100644 --- a/drivers/staging/rtl8188eu/include/odm_debug.h +++ b/drivers/staging/rtl8188eu/include/odm_debug.h @@ -57,30 +57,30 @@ /* Define the tracing components */ /* BB Functions */ -#define ODM_COMP_DIG BIT0 -#define ODM_COMP_RA_MASK BIT1 -#define ODM_COMP_DYNAMIC_TXPWR BIT2 -#define ODM_COMP_FA_CNT BIT3 -#define ODM_COMP_RSSI_MONITOR BIT4 -#define ODM_COMP_CCK_PD BIT5 -#define ODM_COMP_ANT_DIV BIT6 -#define ODM_COMP_PWR_SAVE BIT7 -#define ODM_COMP_PWR_TRA BIT8 -#define ODM_COMP_RATE_ADAPTIVE BIT9 -#define ODM_COMP_PATH_DIV BIT10 -#define ODM_COMP_PSD BIT11 -#define ODM_COMP_DYNAMIC_PRICCA BIT12 -#define ODM_COMP_RXHP BIT13 +#define ODM_COMP_DIG BIT(0) +#define ODM_COMP_RA_MASK BIT(1) +#define ODM_COMP_DYNAMIC_TXPWR BIT(2) +#define ODM_COMP_FA_CNT BIT(3) +#define ODM_COMP_RSSI_MONITOR BIT(4) +#define ODM_COMP_CCK_PD BIT(5) +#define ODM_COMP_ANT_DIV BIT(6) +#define ODM_COMP_PWR_SAVE BIT(7) +#define ODM_COMP_PWR_TRA BIT(8) +#define ODM_COMP_RATE_ADAPTIVE BIT(9) +#define ODM_COMP_PATH_DIV BIT(10) +#define ODM_COMP_PSD BIT(11) +#define ODM_COMP_DYNAMIC_PRICCA BIT(12) +#define ODM_COMP_RXHP BIT(13) /* MAC Functions */ -#define ODM_COMP_EDCA_TURBO BIT16 -#define ODM_COMP_EARLY_MODE BIT17 +#define ODM_COMP_EDCA_TURBO BIT(16) +#define ODM_COMP_EARLY_MODE BIT(17) /* RF Functions */ -#define ODM_COMP_TX_PWR_TRACK BIT24 -#define ODM_COMP_RX_GAIN_TRACK BIT25 -#define ODM_COMP_CALIBRATION BIT26 +#define ODM_COMP_TX_PWR_TRACK BIT(24) +#define ODM_COMP_RX_GAIN_TRACK BIT(25) +#define ODM_COMP_CALIBRATION BIT(26) /* Common Functions */ -#define ODM_COMP_COMMON BIT30 -#define ODM_COMP_INIT BIT31 +#define ODM_COMP_COMMON BIT(30) +#define ODM_COMP_INIT BIT(31) /*------------------------Export Marco Definition---------------------------*/ #define RT_PRINTK(fmt, args...) \ diff --git a/drivers/staging/rtl8188eu/include/odm_reg.h b/drivers/staging/rtl8188eu/include/odm_reg.h index 89bc46bc71b0..7f10b695cf9d 100644 --- a/drivers/staging/rtl8188eu/include/odm_reg.h +++ b/drivers/staging/rtl8188eu/include/odm_reg.h @@ -112,7 +112,7 @@ /* Bitmap Definition */ /* */ -#define BIT_FA_RESET BIT0 +#define BIT_FA_RESET BIT(0) diff --git a/drivers/staging/rtl8188eu/include/osdep_service.h b/drivers/staging/rtl8188eu/include/osdep_service.h index cf9ca685eb77..e24fe8cc3d0b 100644 --- a/drivers/staging/rtl8188eu/include/osdep_service.h +++ b/drivers/staging/rtl8188eu/include/osdep_service.h @@ -67,15 +67,6 @@ static inline struct list_head *get_list_head(struct __queue *queue) return &(queue->queue); } -static inline int _enter_critical_mutex(struct mutex *pmutex, - unsigned long *pirqL) -{ - int ret; - - ret = mutex_lock_interruptible(pmutex); - return ret; -} - static inline int rtw_netif_queue_stopped(struct net_device *pnetdev) { return netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 0)) && @@ -84,45 +75,6 @@ static inline int rtw_netif_queue_stopped(struct net_device *pnetdev) netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3)); } - -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 -#define BIT10 0x00000400 -#define BIT11 0x00000800 -#define BIT12 0x00001000 -#define BIT13 0x00002000 -#define BIT14 0x00004000 -#define BIT15 0x00008000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 -#define BIT32 0x0100000000 -#define BIT33 0x0200000000 -#define BIT34 0x0400000000 -#define BIT35 0x0800000000 -#define BIT36 0x1000000000 - int RTW_STATUS_CODE(int error_code); #define rtw_update_mem_stat(flag, sz) do {} while (0) diff --git a/drivers/staging/rtl8188eu/include/pwrseq.h b/drivers/staging/rtl8188eu/include/pwrseq.h index 43db92dcb8b3..8c876c6c7a4f 100644 --- a/drivers/staging/rtl8188eu/include/pwrseq.h +++ b/drivers/staging/rtl8188eu/include/pwrseq.h @@ -65,31 +65,31 @@ * comment here */ \ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1}, \ + PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ /* wait till 0x04[17] = 1 power ready*/ \ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0|BIT1, 0}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) | BIT(1), 0}, \ /* 0x02[1:0] = 0 reset BB*/ \ {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \ /*0x24[23] = 2b'01 schmit trigger */ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \ /* 0x04[15] = 0 disable HWPDN (control by DRV)*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, 0}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, \ /*0x04[12:11] = 2b'00 disable WL suspend*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ /*0x04[8] = 1 polling until return 0*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, \ + PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \ /*wait till 0x04[8] = 0*/ \ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ /*LDO normal mode*/ \ {0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ /*SDIO Driving*/ #define RTL8188E_TRANS_ACT_TO_CARDEMU \ @@ -102,13 +102,13 @@ PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \ /*0x1F[7:0] = 0 turn off RF*/ \ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ /*LDO Sleep mode*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ /*0x04[9] = 1 turn off MAC by HW state machine*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, \ + PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \ /*wait till 0x04[9] = 0 polling until return 0 to disable*/ #define RTL8188E_TRANS_CARDEMU_TO_SUS \ @@ -119,28 +119,28 @@ */ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ - PWR_CMD_WRITE, BIT3|BIT4, BIT3}, \ + PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \ /* 0x04[12:11] = 2b'01enable WL suspend */ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)}, \ /* 0x04[12:11] = 2b'11enable WL suspend for PCIe */ \ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ - PWR_CMD_WRITE, 0xFF, BIT7}, \ + PWR_CMD_WRITE, 0xFF, BIT(7)}, \ /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\ {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ - PWR_CMD_WRITE, BIT4, 0}, \ + PWR_CMD_WRITE, BIT(4), 0}, \ /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ - PWR_CMD_WRITE, BIT4, BIT4}, \ + PWR_CMD_WRITE, BIT(4), BIT(4)}, \ /*Set USB suspend enable local register 0xfe10[4]=1 */ \ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, \ + PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ /*Set SDIO suspend local register*/ \ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, \ + PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, \ /*wait power state to suspend*/ #define RTL8188E_TRANS_SUS_TO_CARDEMU \ @@ -150,13 +150,13 @@ * comments here */ \ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, \ + PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \ /*Set SDIO suspend local register*/ \ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, \ + PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ /*wait power state to suspend*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \ /*0x04[12:11] = 2b'01enable WL suspend*/ #define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \ @@ -166,11 +166,11 @@ * comments here */ \ {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \ /*0x24[23] = 2b'01 schmit trigger */ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ - PWR_CMD_WRITE, BIT3|BIT4, BIT3}, \ + PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \ /*0x04[12:11] = 2b'01 enable WL suspend*/ \ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ @@ -178,16 +178,16 @@ /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\ {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ - PWR_CMD_WRITE, BIT4, 0}, \ + PWR_CMD_WRITE, BIT(4), 0}, \ /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ /*Set USB suspend enable local register 0xfe10[4]=1 */ \ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, \ + PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ /*Set SDIO suspend local register*/ \ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, \ + PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, \ /*wait power state to suspend*/ #define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \ @@ -197,13 +197,13 @@ * comments here */ \ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, \ + PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \ /*Set SDIO suspend local register*/ \ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, \ + PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ /*wait power state to suspend*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \ /*0x04[12:11] = 2b'01enable WL suspend*/ #define RTL8188E_TRANS_CARDEMU_TO_PDN \ @@ -213,10 +213,10 @@ * comments here */ \ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ /* 0x04[16] = 0*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \ /* 0x04[15] = 1*/ #define RTL8188E_TRANS_PDN_TO_CARDEMU \ @@ -226,7 +226,7 @@ * comments here */ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \ /* 0x04[15] = 0*/ /* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */ @@ -251,7 +251,7 @@ PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ /*Should be zero if no packet is transmitting*/ \ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ /*CCK and OFDM are disabled,and clock are gated*/ \ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, \ @@ -259,9 +259,9 @@ {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \ {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/\ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/\ {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)}, \ /*Respond TxOK to scheduler*/ @@ -280,22 +280,22 @@ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ /* 0x08[4] = 0 switch TSF to 40M */ \ {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, \ + PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \ /* Polling 0x109[7]=0 TSF in 40M */ \ {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, \ /* 0x29[7:6] = 2b'00 enable BB clock */ \ {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ /* 0x101[1] = 1 */ \ {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \ /* 0x100[7:0] = 0xFF enable WMAC TRX */ \ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, \ + PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \ /* 0x02[1:0] = 2b'11 enable BB macro */ \ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_spec.h b/drivers/staging/rtl8188eu/include/rtl8188e_spec.h index 2c33eb30d31b..beeee4a6b0bc 100644 --- a/drivers/staging/rtl8188eu/include/rtl8188e_spec.h +++ b/drivers/staging/rtl8188eu/include/rtl8188e_spec.h @@ -19,43 +19,6 @@ #ifndef __RTL8188E_SPEC_H__ #define __RTL8188E_SPEC_H__ -#ifndef BIT -#define BIT(x) (1 << (x)) -#endif - -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 -#define BIT10 0x00000400 -#define BIT11 0x00000800 -#define BIT12 0x00001000 -#define BIT13 0x00002000 -#define BIT14 0x00004000 -#define BIT15 0x00008000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - /* 8192C Regsiter offset definition */ #define HAL_PS_TIMER_INT_DELAY 50 /* 50 microseconds */ @@ -481,14 +444,14 @@ #define MAX_MSS_DENSITY_1T 0x0A /* EEPROM enable when set 1 */ -#define CmdEEPROM_En BIT5 +#define CmdEEPROM_En BIT(5) /* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */ -#define CmdEERPOMSEL BIT4 -#define Cmd9346CR_9356SEL BIT4 +#define CmdEERPOMSEL BIT(4) +#define Cmd9346CR_9356SEL BIT(4) /* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */ #define GPIOSEL_GPIO 0 -#define GPIOSEL_ENBT BIT5 +#define GPIOSEL_ENBT BIT(5) /* 8192C GPIO PIN Control Register (offset 0x44, 4 byte) */ /* GPIO pins input value */ @@ -501,18 +464,18 @@ #define GPIO_MOD (REG_GPIO_PIN_CTRL+3) /* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */ -#define HSIMR_GPIO12_0_INT_EN BIT0 -#define HSIMR_SPS_OCP_INT_EN BIT5 -#define HSIMR_RON_INT_EN BIT6 -#define HSIMR_PDN_INT_EN BIT7 -#define HSIMR_GPIO9_INT_EN BIT25 +#define HSIMR_GPIO12_0_INT_EN BIT(0) +#define HSIMR_SPS_OCP_INT_EN BIT(5) +#define HSIMR_RON_INT_EN BIT(6) +#define HSIMR_PDN_INT_EN BIT(7) +#define HSIMR_GPIO9_INT_EN BIT(25) /* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */ -#define HSISR_GPIO12_0_INT BIT0 -#define HSISR_SPS_OCP_INT BIT5 -#define HSISR_RON_INT_EN BIT6 -#define HSISR_PDNINT BIT7 -#define HSISR_GPIO9_INT BIT25 +#define HSISR_GPIO12_0_INT BIT(0) +#define HSISR_SPS_OCP_INT BIT(5) +#define HSISR_RON_INT_EN BIT(6) +#define HSISR_PDNINT BIT(7) +#define HSISR_GPIO9_INT BIT(25) /* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) */ /* @@ -537,51 +500,51 @@ Default: 00b. /* 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits) */ /* IOL config for REG_FDHM0(Reg0x88) */ -#define CMD_INIT_LLT BIT0 -#define CMD_READ_EFUSE_MAP BIT1 -#define CMD_EFUSE_PATCH BIT2 -#define CMD_IOCONFIG BIT3 -#define CMD_INIT_LLT_ERR BIT4 -#define CMD_READ_EFUSE_MAP_ERR BIT5 -#define CMD_EFUSE_PATCH_ERR BIT6 -#define CMD_IOCONFIG_ERR BIT7 +#define CMD_INIT_LLT BIT(0) +#define CMD_READ_EFUSE_MAP BIT(1) +#define CMD_EFUSE_PATCH BIT(2) +#define CMD_IOCONFIG BIT(3) +#define CMD_INIT_LLT_ERR BIT(4) +#define CMD_READ_EFUSE_MAP_ERR BIT(5) +#define CMD_EFUSE_PATCH_ERR BIT(6) +#define CMD_IOCONFIG_ERR BIT(7) /* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */ /* 8192C Response Rate Set Register (offset 0x181, 24bits) */ -#define RRSR_1M BIT0 -#define RRSR_2M BIT1 -#define RRSR_5_5M BIT2 -#define RRSR_11M BIT3 -#define RRSR_6M BIT4 -#define RRSR_9M BIT5 -#define RRSR_12M BIT6 -#define RRSR_18M BIT7 -#define RRSR_24M BIT8 -#define RRSR_36M BIT9 -#define RRSR_48M BIT10 -#define RRSR_54M BIT11 -#define RRSR_MCS0 BIT12 -#define RRSR_MCS1 BIT13 -#define RRSR_MCS2 BIT14 -#define RRSR_MCS3 BIT15 -#define RRSR_MCS4 BIT16 -#define RRSR_MCS5 BIT17 -#define RRSR_MCS6 BIT18 -#define RRSR_MCS7 BIT19 +#define RRSR_1M BIT(0) +#define RRSR_2M BIT(1) +#define RRSR_5_5M BIT(2) +#define RRSR_11M BIT(3) +#define RRSR_6M BIT(4) +#define RRSR_9M BIT(5) +#define RRSR_12M BIT(6) +#define RRSR_18M BIT(7) +#define RRSR_24M BIT(8) +#define RRSR_36M BIT(9) +#define RRSR_48M BIT(10) +#define RRSR_54M BIT(11) +#define RRSR_MCS0 BIT(12) +#define RRSR_MCS1 BIT(13) +#define RRSR_MCS2 BIT(14) +#define RRSR_MCS3 BIT(15) +#define RRSR_MCS4 BIT(16) +#define RRSR_MCS5 BIT(17) +#define RRSR_MCS6 BIT(18) +#define RRSR_MCS7 BIT(19) /* 8192C Response Rate Set Register (offset 0x1BF, 8bits) */ /* WOL bit information */ -#define HAL92C_WOL_PTK_UPDATE_EVENT BIT0 -#define HAL92C_WOL_GTK_UPDATE_EVENT BIT1 +#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0) +#define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1) /* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */ -#define BW_OPMODE_20MHZ BIT2 -#define BW_OPMODE_5G BIT1 +#define BW_OPMODE_20MHZ BIT(2) +#define BW_OPMODE_5G BIT(1) /* 8192C CAM Config Setting (offset 0x250, 1 byte) */ -#define CAM_VALID BIT15 +#define CAM_VALID BIT(15) #define CAM_NOTVALID 0x0000 -#define CAM_USEDK BIT5 +#define CAM_USEDK BIT(5) #define CAM_CONTENT_COUNT 8 @@ -598,69 +561,69 @@ Default: 00b. #define CAM_CONFIG_USEDK true #define CAM_CONFIG_NO_USEDK false -#define CAM_WRITE BIT16 +#define CAM_WRITE BIT(16) #define CAM_READ 0x00000000 -#define CAM_POLLINIG BIT31 +#define CAM_POLLINIG BIT(31) #define SCR_UseDK 0x01 #define SCR_TxSecEnable 0x02 #define SCR_RxSecEnable 0x04 /* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */ -#define WOW_PMEN BIT0 /* Power management Enable. */ -#define WOW_WOMEN BIT1 /* WoW function on or off. */ -#define WOW_MAGIC BIT2 /* Magic packet */ -#define WOW_UWF BIT3 /* Unicast Wakeup frame. */ +#define WOW_PMEN BIT(0) /* Power management Enable. */ +#define WOW_WOMEN BIT(1) /* WoW function on or off. */ +#define WOW_MAGIC BIT(2) /* Magic packet */ +#define WOW_UWF BIT(3) /* Unicast Wakeup frame. */ /* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */ /* 8188 IMR/ISR bits */ #define IMR_DISABLED_88E 0x0 /* IMR DW0(0x0060-0063) Bit 0-31 */ -#define IMR_TXCCK_88E BIT30 /* TXRPT interrupt when CCX bit of the packet is set */ -#define IMR_PSTIMEOUT_88E BIT29 /* Power Save Time Out Interrupt */ -#define IMR_GTINT4_88E BIT28 /* When GTIMER4 expires, this bit is set to 1 */ -#define IMR_GTINT3_88E BIT27 /* When GTIMER3 expires, this bit is set to 1 */ -#define IMR_TBDER_88E BIT26 /* Transmit Beacon0 Error */ -#define IMR_TBDOK_88E BIT25 /* Transmit Beacon0 OK */ -#define IMR_TSF_BIT32_TOGGLE_88E BIT24 /* TSF Timer BIT32 toggle indication interrupt */ -#define IMR_BCNDMAINT0_88E BIT20 /* Beacon DMA Interrupt 0 */ -#define IMR_BCNDERR0_88E BIT16 /* Beacon Queue DMA Error 0 */ -#define IMR_HSISR_IND_ON_INT_88E BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ -#define IMR_BCNDMAINT_E_88E BIT14 /* Beacon DMA Interrupt Extension for Win7 */ -#define IMR_ATIMEND_88E BIT12 /* CTWidnow End or ATIM Window End */ -#define IMR_HISR1_IND_INT_88E BIT11 /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */ -#define IMR_C2HCMD_88E BIT10 /* CPU to Host Command INT Status, Write 1 clear */ -#define IMR_CPWM2_88E BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_CPWM_88E BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_HIGHDOK_88E BIT7 /* High Queue DMA OK */ -#define IMR_MGNTDOK_88E BIT6 /* Management Queue DMA OK */ -#define IMR_BKDOK_88E BIT5 /* AC_BK DMA OK */ -#define IMR_BEDOK_88E BIT4 /* AC_BE DMA OK */ -#define IMR_VIDOK_88E BIT3 /* AC_VI DMA OK */ -#define IMR_VODOK_88E BIT2 /* AC_VO DMA OK */ -#define IMR_RDU_88E BIT1 /* Rx Descriptor Unavailable */ -#define IMR_ROK_88E BIT0 /* Receive DMA OK */ +#define IMR_TXCCK_88E BIT(30) /* TXRPT interrupt when CCX bit of the packet is set */ +#define IMR_PSTIMEOUT_88E BIT(29) /* Power Save Time Out Interrupt */ +#define IMR_GTINT4_88E BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ +#define IMR_GTINT3_88E BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ +#define IMR_TBDER_88E BIT(26) /* Transmit Beacon0 Error */ +#define IMR_TBDOK_88E BIT(25) /* Transmit Beacon0 OK */ +#define IMR_TSF_BIT32_TOGGLE_88E BIT(24) /* TSF Timer BIT32 toggle indication interrupt */ +#define IMR_BCNDMAINT0_88E BIT(20) /* Beacon DMA Interrupt 0 */ +#define IMR_BCNDERR0_88E BIT(16) /* Beacon Queue DMA Error 0 */ +#define IMR_HSISR_IND_ON_INT_88E BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ +#define IMR_BCNDMAINT_E_88E BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ +#define IMR_ATIMEND_88E BIT(12) /* CTWidnow End or ATIM Window End */ +#define IMR_HISR1_IND_INT_88E BIT(11) /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */ +#define IMR_C2HCMD_88E BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ +#define IMR_CPWM2_88E BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_CPWM_88E BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_HIGHDOK_88E BIT(7) /* High Queue DMA OK */ +#define IMR_MGNTDOK_88E BIT(6) /* Management Queue DMA OK */ +#define IMR_BKDOK_88E BIT(5) /* AC_BK DMA OK */ +#define IMR_BEDOK_88E BIT(4) /* AC_BE DMA OK */ +#define IMR_VIDOK_88E BIT(3) /* AC_VI DMA OK */ +#define IMR_VODOK_88E BIT(2) /* AC_VO DMA OK */ +#define IMR_RDU_88E BIT(1) /* Rx Descriptor Unavailable */ +#define IMR_ROK_88E BIT(0) /* Receive DMA OK */ /* IMR DW1(0x00B4-00B7) Bit 0-31 */ -#define IMR_BCNDMAINT7_88E BIT27 /* Beacon DMA Interrupt 7 */ -#define IMR_BCNDMAINT6_88E BIT26 /* Beacon DMA Interrupt 6 */ -#define IMR_BCNDMAINT5_88E BIT25 /* Beacon DMA Interrupt 5 */ -#define IMR_BCNDMAINT4_88E BIT24 /* Beacon DMA Interrupt 4 */ -#define IMR_BCNDMAINT3_88E BIT23 /* Beacon DMA Interrupt 3 */ -#define IMR_BCNDMAINT2_88E BIT22 /* Beacon DMA Interrupt 2 */ -#define IMR_BCNDMAINT1_88E BIT21 /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDERR7_88E BIT20 /* Beacon DMA Error Int 7 */ -#define IMR_BCNDERR6_88E BIT19 /* Beacon DMA Error Int 6 */ -#define IMR_BCNDERR5_88E BIT18 /* Beacon DMA Error Int 5 */ -#define IMR_BCNDERR4_88E BIT17 /* Beacon DMA Error Int 4 */ -#define IMR_BCNDERR3_88E BIT16 /* Beacon DMA Error Int 3 */ -#define IMR_BCNDERR2_88E BIT15 /* Beacon DMA Error Int 2 */ -#define IMR_BCNDERR1_88E BIT14 /* Beacon DMA Error Int 1 */ -#define IMR_ATIMEND_E_88E BIT13 /* ATIM Window End Ext for Win7 */ -#define IMR_TXERR_88E BIT11 /* Tx Err Flag Int Status, write 1 clear. */ -#define IMR_RXERR_88E BIT10 /* Rx Err Flag INT Status, Write 1 clear */ -#define IMR_TXFOVW_88E BIT9 /* Transmit FIFO Overflow */ -#define IMR_RXFOVW_88E BIT8 /* Receive FIFO Overflow */ +#define IMR_BCNDMAINT7_88E BIT(27) /* Beacon DMA Interrupt 7 */ +#define IMR_BCNDMAINT6_88E BIT(26) /* Beacon DMA Interrupt 6 */ +#define IMR_BCNDMAINT5_88E BIT(25) /* Beacon DMA Interrupt 5 */ +#define IMR_BCNDMAINT4_88E BIT(24) /* Beacon DMA Interrupt 4 */ +#define IMR_BCNDMAINT3_88E BIT(23) /* Beacon DMA Interrupt 3 */ +#define IMR_BCNDMAINT2_88E BIT(22) /* Beacon DMA Interrupt 2 */ +#define IMR_BCNDMAINT1_88E BIT(21) /* Beacon DMA Interrupt 1 */ +#define IMR_BCNDERR7_88E BIT(20) /* Beacon DMA Error Int 7 */ +#define IMR_BCNDERR6_88E BIT(19) /* Beacon DMA Error Int 6 */ +#define IMR_BCNDERR5_88E BIT(18) /* Beacon DMA Error Int 5 */ +#define IMR_BCNDERR4_88E BIT(17) /* Beacon DMA Error Int 4 */ +#define IMR_BCNDERR3_88E BIT(16) /* Beacon DMA Error Int 3 */ +#define IMR_BCNDERR2_88E BIT(15) /* Beacon DMA Error Int 2 */ +#define IMR_BCNDERR1_88E BIT(14) /* Beacon DMA Error Int 1 */ +#define IMR_ATIMEND_E_88E BIT(13) /* ATIM Window End Ext for Win7 */ +#define IMR_TXERR_88E BIT(11) /* Tx Err Flag Int Status, write 1 clear. */ +#define IMR_RXERR_88E BIT(10) /* Rx Err Flag INT Status, Write 1 clear */ +#define IMR_TXFOVW_88E BIT(9) /* Transmit FIFO Overflow */ +#define IMR_RXFOVW_88E BIT(8) /* Receive FIFO Overflow */ #define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF /* The value when the NIC is unplugged for PCI. */ @@ -696,40 +659,40 @@ Current IOREG MAP /* the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, * and BK - Bit3. */ /* 8723 and 88E may be not correct either in the earlier version. */ -#define StopBecon BIT6 -#define StopHigh BIT5 -#define StopMgt BIT4 -#define StopBK BIT3 -#define StopBE BIT2 -#define StopVI BIT1 -#define StopVO BIT0 +#define StopBecon BIT(6) +#define StopHigh BIT(5) +#define StopMgt BIT(4) +#define StopBK BIT(3) +#define StopBE BIT(2) +#define StopVI BIT(1) +#define StopVO BIT(0) /* 8192C (RCR) Receive Configuration Register(Offset 0x608, 32 bits) */ -#define RCR_APPFCS BIT31 /* WMAC append FCS after payload */ -#define RCR_APP_MIC BIT30 -#define RCR_APP_PHYSTS BIT28 -#define RCR_APP_ICV BIT29 -#define RCR_APP_PHYST_RXFF BIT28 -#define RCR_APP_BA_SSN BIT27 /* Accept BA SSN */ -#define RCR_ENMBID BIT24 /* Enable Multiple BssId. */ -#define RCR_LSIGEN BIT23 -#define RCR_MFBEN BIT22 -#define RCR_HTC_LOC_CTRL BIT14 /* MFC<--HTC=1 MFC-->HTC=0 */ -#define RCR_AMF BIT13 /* Accept management type frame */ -#define RCR_ACF BIT12 /* Accept control type frame */ -#define RCR_ADF BIT11 /* Accept data type frame */ -#define RCR_AICV BIT9 /* Accept ICV error packet */ -#define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */ -#define RCR_CBSSID_BCN BIT7 /* Accept BSSID match packet +#define RCR_APPFCS BIT(31) /* WMAC append FCS after payload */ +#define RCR_APP_MIC BIT(30) +#define RCR_APP_PHYSTS BIT(28) +#define RCR_APP_ICV BIT(29) +#define RCR_APP_PHYST_RXFF BIT(28) +#define RCR_APP_BA_SSN BIT(27) /* Accept BA SSN */ +#define RCR_ENMBID BIT(24) /* Enable Multiple BssId. */ +#define RCR_LSIGEN BIT(23) +#define RCR_MFBEN BIT(22) +#define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */ +#define RCR_AMF BIT(13) /* Accept management type frame */ +#define RCR_ACF BIT(12) /* Accept control type frame */ +#define RCR_ADF BIT(11) /* Accept data type frame */ +#define RCR_AICV BIT(9) /* Accept ICV error packet */ +#define RCR_ACRC32 BIT(8) /* Accept CRC32 error packet */ +#define RCR_CBSSID_BCN BIT(7) /* Accept BSSID match packet * (Rx beacon, probe rsp) */ -#define RCR_CBSSID_DATA BIT6 /* Accept BSSID match (Data)*/ +#define RCR_CBSSID_DATA BIT(6) /* Accept BSSID match (Data)*/ #define RCR_CBSSID RCR_CBSSID_DATA /* Accept BSSID match */ -#define RCR_APWRMGT BIT5 /* Accept power management pkt*/ -#define RCR_ADD3 BIT4 /* Accept address 3 match pkt */ -#define RCR_AB BIT3 /* Accept broadcast packet */ -#define RCR_AM BIT2 /* Accept multicast packet */ -#define RCR_APM BIT1 /* Accept physical match pkt */ -#define RCR_AAP BIT0 /* Accept all unicast packet */ +#define RCR_APWRMGT BIT(5) /* Accept power management pkt*/ +#define RCR_ADD3 BIT(4) /* Accept address 3 match pkt */ +#define RCR_AB BIT(3) /* Accept broadcast packet */ +#define RCR_AM BIT(2) /* Accept multicast packet */ +#define RCR_APM BIT(1) /* Accept physical match pkt */ +#define RCR_AAP BIT(0) /* Accept all unicast packet */ #define RCR_MXDMA_OFFSET 8 #define RCR_FIFO_OFFSET 13 @@ -1197,56 +1160,56 @@ Current IOREG MAP #define SDIO_HIMR_DISABLED 0 /* RTL8188E SDIO Host Interrupt Mask Register */ -#define SDIO_HIMR_RX_REQUEST_MSK BIT0 -#define SDIO_HIMR_AVAL_MSK BIT1 -#define SDIO_HIMR_TXERR_MSK BIT2 -#define SDIO_HIMR_RXERR_MSK BIT3 -#define SDIO_HIMR_TXFOVW_MSK BIT4 -#define SDIO_HIMR_RXFOVW_MSK BIT5 -#define SDIO_HIMR_TXBCNOK_MSK BIT6 -#define SDIO_HIMR_TXBCNERR_MSK BIT7 -#define SDIO_HIMR_BCNERLY_INT_MSK BIT16 -#define SDIO_HIMR_C2HCMD_MSK BIT17 -#define SDIO_HIMR_CPWM1_MSK BIT18 -#define SDIO_HIMR_CPWM2_MSK BIT19 -#define SDIO_HIMR_HSISR_IND_MSK BIT20 -#define SDIO_HIMR_GTINT3_IND_MSK BIT21 -#define SDIO_HIMR_GTINT4_IND_MSK BIT22 -#define SDIO_HIMR_PSTIMEOUT_MSK BIT23 -#define SDIO_HIMR_OCPINT_MSK BIT24 -#define SDIO_HIMR_ATIMEND_MSK BIT25 -#define SDIO_HIMR_ATIMEND_E_MSK BIT26 -#define SDIO_HIMR_CTWEND_MSK BIT27 +#define SDIO_HIMR_RX_REQUEST_MSK BIT(0) +#define SDIO_HIMR_AVAL_MSK BIT(1) +#define SDIO_HIMR_TXERR_MSK BIT(2) +#define SDIO_HIMR_RXERR_MSK BIT(3) +#define SDIO_HIMR_TXFOVW_MSK BIT(4) +#define SDIO_HIMR_RXFOVW_MSK BIT(5) +#define SDIO_HIMR_TXBCNOK_MSK BIT(6) +#define SDIO_HIMR_TXBCNERR_MSK BIT(7) +#define SDIO_HIMR_BCNERLY_INT_MSK BIT(16) +#define SDIO_HIMR_C2HCMD_MSK BIT(17) +#define SDIO_HIMR_CPWM1_MSK BIT(18) +#define SDIO_HIMR_CPWM2_MSK BIT(19) +#define SDIO_HIMR_HSISR_IND_MSK BIT(20) +#define SDIO_HIMR_GTINT3_IND_MSK BIT(21) +#define SDIO_HIMR_GTINT4_IND_MSK BIT(22) +#define SDIO_HIMR_PSTIMEOUT_MSK BIT(23) +#define SDIO_HIMR_OCPINT_MSK BIT(24) +#define SDIO_HIMR_ATIMEND_MSK BIT(25) +#define SDIO_HIMR_ATIMEND_E_MSK BIT(26) +#define SDIO_HIMR_CTWEND_MSK BIT(27) /* RTL8188E SDIO Specific */ -#define SDIO_HIMR_MCU_ERR_MSK BIT28 -#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29 +#define SDIO_HIMR_MCU_ERR_MSK BIT(28) +#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT(29) /* SDIO Host Interrupt Service Routine */ -#define SDIO_HISR_RX_REQUEST BIT0 -#define SDIO_HISR_AVAL BIT1 -#define SDIO_HISR_TXERR BIT2 -#define SDIO_HISR_RXERR BIT3 -#define SDIO_HISR_TXFOVW BIT4 -#define SDIO_HISR_RXFOVW BIT5 -#define SDIO_HISR_TXBCNOK BIT6 -#define SDIO_HISR_TXBCNERR BIT7 -#define SDIO_HISR_BCNERLY_INT BIT16 -#define SDIO_HISR_C2HCMD BIT17 -#define SDIO_HISR_CPWM1 BIT18 -#define SDIO_HISR_CPWM2 BIT19 -#define SDIO_HISR_HSISR_IND BIT20 -#define SDIO_HISR_GTINT3_IND BIT21 -#define SDIO_HISR_GTINT4_IND BIT22 -#define SDIO_HISR_PSTIME BIT23 -#define SDIO_HISR_OCPINT BIT24 -#define SDIO_HISR_ATIMEND BIT25 -#define SDIO_HISR_ATIMEND_E BIT26 -#define SDIO_HISR_CTWEND BIT27 +#define SDIO_HISR_RX_REQUEST BIT(0) +#define SDIO_HISR_AVAL BIT(1) +#define SDIO_HISR_TXERR BIT(2) +#define SDIO_HISR_RXERR BIT(3) +#define SDIO_HISR_TXFOVW BIT(4) +#define SDIO_HISR_RXFOVW BIT(5) +#define SDIO_HISR_TXBCNOK BIT(6) +#define SDIO_HISR_TXBCNERR BIT(7) +#define SDIO_HISR_BCNERLY_INT BIT(16) +#define SDIO_HISR_C2HCMD BIT(17) +#define SDIO_HISR_CPWM1 BIT(18) +#define SDIO_HISR_CPWM2 BIT(19) +#define SDIO_HISR_HSISR_IND BIT(20) +#define SDIO_HISR_GTINT3_IND BIT(21) +#define SDIO_HISR_GTINT4_IND BIT(22) +#define SDIO_HISR_PSTIME BIT(23) +#define SDIO_HISR_OCPINT BIT(24) +#define SDIO_HISR_ATIMEND BIT(25) +#define SDIO_HISR_ATIMEND_E BIT(26) +#define SDIO_HISR_CTWEND BIT(27) /* RTL8188E SDIO Specific */ -#define SDIO_HISR_MCU_ERR BIT28 -#define SDIO_HISR_TSF_BIT32_TOGGLE BIT29 +#define SDIO_HISR_MCU_ERR BIT(28) +#define SDIO_HISR_TSF_BIT32_TOGGLE BIT(29) #define MASK_SDIO_HISR_CLEAR \ (SDIO_HISR_TXERR | SDIO_HISR_RXERR | SDIO_HISR_TXFOVW |\ @@ -1256,8 +1219,8 @@ Current IOREG MAP SDIO_HISR_PSTIMEOUT | SDIO_HISR_OCPINT) /* SDIO HCI Suspend Control Register */ -#define HCI_RESUME_PWR_RDY BIT1 -#define HCI_SUS_CTRL BIT0 +#define HCI_RESUME_PWR_RDY BIT(1) +#define HCI_SUS_CTRL BIT(0) /* SDIO Tx FIFO related */ /* The number of Tx FIFO free page */ @@ -1291,33 +1254,33 @@ Current IOREG MAP /* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */ /* Enable GPIO[9] as WiFi HW PDn source */ -#define WL_HWPDN_EN BIT0 +#define WL_HWPDN_EN BIT(0) /* WiFi HW PDn polarity control */ -#define WL_HWPDN_SL BIT1 +#define WL_HWPDN_SL BIT(1) /* WiFi function enable */ -#define WL_FUNC_EN BIT2 +#define WL_FUNC_EN BIT(2) /* Enable GPIO[9] as WiFi RF HW PDn source */ -#define WL_HWROF_EN BIT3 +#define WL_HWROF_EN BIT(3) /* Enable GPIO[11] as BT HW PDn source */ -#define BT_HWPDN_EN BIT16 +#define BT_HWPDN_EN BIT(16) /* BT HW PDn polarity control */ -#define BT_HWPDN_SL BIT17 +#define BT_HWPDN_SL BIT(17) /* BT function enable */ -#define BT_FUNC_EN BIT18 +#define BT_FUNC_EN BIT(18) /* Enable GPIO[11] as BT/GPS RF HW PDn source */ -#define BT_HWROF_EN BIT19 +#define BT_HWROF_EN BIT(19) /* Enable GPIO[10] as GPS HW PDn source */ -#define GPS_HWPDN_EN BIT20 +#define GPS_HWPDN_EN BIT(20) /* GPS HW PDn polarity control */ -#define GPS_HWPDN_SL BIT21 +#define GPS_HWPDN_SL BIT(21) /* GPS function enable */ -#define GPS_FUNC_EN BIT22 +#define GPS_FUNC_EN BIT(22) /* 3 REG_LIFECTRL_CTRL */ -#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 -#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 -#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 -#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 +#define HAL92C_EN_PKT_LIFE_TIME_BK BIT(3) +#define HAL92C_EN_PKT_LIFE_TIME_BE BIT(2) +#define HAL92C_EN_PKT_LIFE_TIME_VI BIT(1) +#define HAL92C_EN_PKT_LIFE_TIME_VO BIT(0) #define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us */ @@ -1327,7 +1290,7 @@ Current IOREG MAP #define POLLING_LLT_THRESHOLD 20 #define POLLING_READY_TIMEOUT_COUNT 1000 /* GPIO BIT */ -#define HAL_8192C_HW_GPIO_WPS_BIT BIT2 +#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) /* 8192C EEPROM/EFUSE share register definition. */ diff --git a/drivers/staging/rtl8188eu/include/rtw_security.h b/drivers/staging/rtl8188eu/include/rtw_security.h index abe7e21e6e20..a1aebe6c8452 100644 --- a/drivers/staging/rtl8188eu/include/rtw_security.h +++ b/drivers/staging/rtl8188eu/include/rtw_security.h @@ -336,9 +336,6 @@ static const unsigned long K[64] = { #define Sigma1(x) (S(x, 6) ^ S(x, 11) ^ S(x, 25)) #define Gamma0(x) (S(x, 7) ^ S(x, 18) ^ R(x, 3)) #define Gamma1(x) (S(x, 17) ^ S(x, 19) ^ R(x, 10)) -#ifndef MIN -#define MIN(x, y) (((x) < (y)) ? (x) : (y)) -#endif void rtw_secmicsetkey(struct mic_data *pmicdata, u8 *key); void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b); diff --git a/drivers/staging/rtl8188eu/include/rtw_sreset.h b/drivers/staging/rtl8188eu/include/rtw_sreset.h index 580e850511a7..3a62ed010875 100644 --- a/drivers/staging/rtl8188eu/include/rtw_sreset.h +++ b/drivers/staging/rtl8188eu/include/rtw_sreset.h @@ -30,13 +30,13 @@ struct sreset_priv { #include <rtl8188e_hal.h> #define WIFI_STATUS_SUCCESS 0 -#define USB_VEN_REQ_CMD_FAIL BIT0 -#define USB_READ_PORT_FAIL BIT1 -#define USB_WRITE_PORT_FAIL BIT2 -#define WIFI_MAC_TXDMA_ERROR BIT3 -#define WIFI_TX_HANG BIT4 -#define WIFI_RX_HANG BIT5 -#define WIFI_IF_NOT_EXIST BIT6 +#define USB_VEN_REQ_CMD_FAIL BIT(0) +#define USB_READ_PORT_FAIL BIT(1) +#define USB_WRITE_PORT_FAIL BIT(2) +#define WIFI_MAC_TXDMA_ERROR BIT(3) +#define WIFI_TX_HANG BIT(4) +#define WIFI_RX_HANG BIT(5) +#define WIFI_IF_NOT_EXIST BIT(6) void sreset_init_value(struct adapter *padapter); u8 sreset_get_wifi_status(struct adapter *padapter); diff --git a/drivers/staging/rtl8188eu/include/wifi.h b/drivers/staging/rtl8188eu/include/wifi.h index dba8af1ec41e..6cb5beca1672 100644 --- a/drivers/staging/rtl8188eu/include/wifi.h +++ b/drivers/staging/rtl8188eu/include/wifi.h @@ -20,18 +20,7 @@ #ifndef _WIFI_H_ #define _WIFI_H_ - -#ifdef BIT -/* error "BIT define occurred earlier elsewhere!\n" */ -#undef BIT -#endif -#define BIT(x) (1 << (x)) - - -#define WLAN_ETHHDR_LEN 14 -#define WLAN_ETHADDR_LEN 6 #define WLAN_IEEE_OUI_LEN 3 -#define WLAN_ADDR_LEN 6 #define WLAN_CRC_LEN 4 #define WLAN_BSSID_LEN 6 #define WLAN_BSS_TS_LEN 8 @@ -47,7 +36,6 @@ #define WLAN_MIN_ETHFRM_LEN 60 #define WLAN_MAX_ETHFRM_LEN 1514 -#define WLAN_ETHHDR_LEN 14 #define P80211CAPTURE_VERSION 0x80211001 |