diff options
Diffstat (limited to 'drivers/staging/rtl8192u/r8192U.h')
| -rw-r--r-- | drivers/staging/rtl8192u/r8192U.h | 299 |
1 files changed, 145 insertions, 154 deletions
diff --git a/drivers/staging/rtl8192u/r8192U.h b/drivers/staging/rtl8192u/r8192U.h index 57e3383cc935..e538e026b512 100644 --- a/drivers/staging/rtl8192u/r8192U.h +++ b/drivers/staging/rtl8192u/r8192U.h @@ -110,7 +110,7 @@ do { if(rt_global_debug_component & component) \ #define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_RM BIT13 // For Radio Measurement. #define COMP_DIG BIT14 // For DIG, 2006.09.25, by rcnjko. -#define COMP_PHY BIT15 +#define COMP_PHY BIT15 #define COMP_CH BIT16 //channel setting debug #define COMP_TXAGC BIT17 // For Tx power, 060928, by rcnjko. #define COMP_HIPWR BIT18 // For High Power Mechanism, 060928, by rcnjko. @@ -136,26 +136,26 @@ do { if(rt_global_debug_component & component) \ #define RTL819x_DEBUG #ifdef RTL819x_DEBUG #define assert(expr) \ - if (!(expr)) { \ - printk( "Assertion failed! %s,%s,%s,line=%d\n", \ - #expr,__FILE__,__FUNCTION__,__LINE__); \ - } + if (!(expr)) { \ + printk( "Assertion failed! %s,%s,%s,line=%d\n", \ + #expr,__FILE__,__FUNCTION__,__LINE__); \ + } //wb added to debug out data buf //if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA #define RT_DEBUG_DATA(level, data, datalen) \ - do{ if ((rt_global_debug_component & (level)) == (level)) \ - { \ - int i; \ - u8* pdata = (u8*) data; \ - printk(KERN_DEBUG RTL819xU_MODULE_NAME ": %s()\n", __FUNCTION__); \ - for(i=0; i<(int)(datalen); i++) \ - { \ - printk("%2x ", pdata[i]); \ - if ((i+1)%16 == 0) printk("\n"); \ - } \ - printk("\n"); \ - } \ - } while (0) + do{ if ((rt_global_debug_component & (level)) == (level)) \ + { \ + int i; \ + u8* pdata = (u8*) data; \ + printk(KERN_DEBUG RTL819xU_MODULE_NAME ": %s()\n", __FUNCTION__); \ + for(i=0; i<(int)(datalen); i++) \ + { \ + printk("%2x ", pdata[i]); \ + if ((i+1)%16 == 0) printk("\n"); \ + } \ + printk("\n"); \ + } \ + } while (0) #else #define assert(expr) do {} while (0) #define RT_DEBUG_DATA(level, data, datalen) do {} while(0) @@ -209,47 +209,47 @@ do { if(rt_global_debug_component & component) \ #define IEEE80211_WATCH_DOG_TIME 2000 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10 //for txpowertracking by amy -#define OFDM_Table_Length 19 +#define OFDM_Table_Length 19 #define CCK_Table_length 12 /* for rtl819x */ typedef struct _tx_desc_819x_usb { - //DWORD 0 - u16 PktSize; - u8 Offset; - u8 Reserved0:3; - u8 CmdInit:1; - u8 LastSeg:1; - u8 FirstSeg:1; - u8 LINIP:1; - u8 OWN:1; - - //DWORD 1 - u8 TxFWInfoSize; - u8 RATid:3; - u8 DISFB:1; - u8 USERATE:1; - u8 MOREFRAG:1; - u8 NoEnc:1; - u8 PIFS:1; - u8 QueueSelect:5; - u8 NoACM:1; - u8 Reserved1:2; - u8 SecCAMID:5; - u8 SecDescAssign:1; - u8 SecType:2; - - //DWORD 2 - u16 TxBufferSize; - //u16 Reserved2; - u8 ResvForPaddingLen:7; - u8 Reserved3:1; - u8 Reserved4; - - //DWORD 3, 4, 5 - u32 Reserved5; - u32 Reserved6; - u32 Reserved7; + //DWORD 0 + u16 PktSize; + u8 Offset; + u8 Reserved0:3; + u8 CmdInit:1; + u8 LastSeg:1; + u8 FirstSeg:1; + u8 LINIP:1; + u8 OWN:1; + + //DWORD 1 + u8 TxFWInfoSize; + u8 RATid:3; + u8 DISFB:1; + u8 USERATE:1; + u8 MOREFRAG:1; + u8 NoEnc:1; + u8 PIFS:1; + u8 QueueSelect:5; + u8 NoACM:1; + u8 Reserved1:2; + u8 SecCAMID:5; + u8 SecDescAssign:1; + u8 SecType:2; + + //DWORD 2 + u16 TxBufferSize; + //u16 Reserved2; + u8 ResvForPaddingLen:7; + u8 Reserved3:1; + u8 Reserved4; + + //DWORD 3, 4, 5 + u32 Reserved5; + u32 Reserved6; + u32 Reserved7; }tx_desc_819x_usb, *ptx_desc_819x_usb; #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE @@ -280,7 +280,7 @@ typedef struct _tx_desc_819x_usb_aggr_subframe { typedef struct _tx_desc_cmd_819x_usb { - //DWORD 0 + //DWORD 0 u16 Reserved0; u8 Reserved1; u8 Reserved2:3; @@ -290,15 +290,15 @@ typedef struct _tx_desc_cmd_819x_usb { u8 LINIP:1; u8 OWN:1; - //DOWRD 1 + //DOWRD 1 //u32 Reserved3; u8 TxFWInfoSize; u8 Reserved3; u8 QueueSelect; u8 Reserved4; - //DOWRD 2 - u16 TxBufferSize; + //DOWRD 2 + u16 TxBufferSize; u16 Reserved5; //DWORD 3,4,5 @@ -311,34 +311,34 @@ typedef struct _tx_desc_cmd_819x_usb { typedef struct _tx_fwinfo_819x_usb { - //DOWRD 0 - u8 TxRate:7; - u8 CtsEnable:1; - u8 RtsRate:7; - u8 RtsEnable:1; - u8 TxHT:1; - u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS - u8 TxBandwidth:1; // This is used for HT MCS rate only. - u8 TxSubCarrier:2; // This is used for legacy OFDM rate only. - u8 STBC:2; - u8 AllowAggregation:1; - u8 RtsHT:1; //Interpret RtsRate field as high throughput data rate - u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS - u8 RtsBandwidth:1; // This is used for HT MCS rate only. - u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only. - u8 RtsSTBC:2; - u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration - - //DWORD 1 - u32 RxMF:2; - u32 RxAMD:3; - u32 TxPerPktInfoFeedback:1;//1 indicate Tx info gathtered by firmware and returned by Rx Cmd - u32 Reserved1:2; - u32 TxAGCOffSet:4; - u32 TxAGCSign:1; - u32 Tx_INFO_RSVD:6; + //DOWRD 0 + u8 TxRate:7; + u8 CtsEnable:1; + u8 RtsRate:7; + u8 RtsEnable:1; + u8 TxHT:1; + u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS + u8 TxBandwidth:1; // This is used for HT MCS rate only. + u8 TxSubCarrier:2; // This is used for legacy OFDM rate only. + u8 STBC:2; + u8 AllowAggregation:1; + u8 RtsHT:1; //Interpret RtsRate field as high throughput data rate + u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS + u8 RtsBandwidth:1; // This is used for HT MCS rate only. + u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only. + u8 RtsSTBC:2; + u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration + + //DWORD 1 + u32 RxMF:2; + u32 RxAMD:3; + u32 TxPerPktInfoFeedback:1;//1 indicate Tx info gathtered by firmware and returned by Rx Cmd + u32 Reserved1:2; + u32 TxAGCOffSet:4; + u32 TxAGCSign:1; + u32 Tx_INFO_RSVD:6; u32 PacketID:13; - //u32 Reserved; + //u32 Reserved; }tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb; typedef struct rtl8192_rx_info { @@ -391,7 +391,7 @@ typedef struct _rx_desc_819x_usb_aggr_subframe{ //DWORD 2 //u4Byte Reserved3; //DWORD 3 - //u4Byte BufferAddress; + //u4Byte BufferAddress; }rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe; #endif @@ -424,7 +424,7 @@ typedef struct rx_drvinfo_819x_usb{ #define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE) #define ENCRYPTION_MAX_OVERHEAD 128 #define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb) -#define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb)) +#define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb)) #define MAX_FRAGMENT_COUNT 8 #ifdef RTL8192U #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE @@ -433,7 +433,7 @@ typedef struct rx_drvinfo_819x_usb{ #define MAX_TRANSMIT_BUFFER_SIZE 8000 #endif #else -#define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT) +#define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT) #endif #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE #define TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES (sizeof(tx_desc_819x_usb_aggr_subframe) + sizeof(tx_fwinfo_819x_usb)) @@ -559,22 +559,21 @@ typedef enum _WIRELESS_MODE { #define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30 -typedef struct buffer -{ +typedef struct buffer { struct buffer *next; u32 *buf; } buffer; typedef struct rtl_reg_debug{ - unsigned int cmd; - struct { - unsigned char type; - unsigned char addr; - unsigned char page; - unsigned char length; - } head; - unsigned char buf[0xff]; + unsigned int cmd; + struct { + unsigned char type; + unsigned char addr; + unsigned char page; + unsigned char length; + } head; + unsigned char buf[0xff]; }rtl_reg_debug; @@ -600,8 +599,7 @@ typedef struct _RT_SMOOTH_DATA_4RF { #define MAX_8192U_RX_SIZE 8192 // This maybe changed for D-cut larger aggregation size //stats seems messed up, clean it ASAP -typedef struct Stats -{ +typedef struct Stats { unsigned long txrdu; // unsigned long rxrdu; //unsigned long rxnolast; @@ -711,7 +709,7 @@ typedef struct Stats //+by amy 080507 -typedef struct ChnlAccessSetting { +typedef struct ChnlAccessSetting { u16 SIFS_Timer; u16 DIFS_Timer; u16 SlotTimeTimer; @@ -721,35 +719,34 @@ typedef struct ChnlAccessSetting { }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING; typedef struct _BB_REGISTER_DEFINITION{ - u32 rfintfs; // set software control: // 0x870~0x877[8 bytes] - u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes] - u32 rfintfo; // output data: // 0x860~0x86f [16 bytes] - u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes] - u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes] - u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes] + u32 rfintfs; // set software control: // 0x870~0x877[8 bytes] + u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes] + u32 rfintfo; // output data: // 0x860~0x86f [16 bytes] + u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes] + u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes] + u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes] u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes] - u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] - u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] - u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes] - u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] - u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] - u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] - u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] - u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] - u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] - u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes] + u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] + u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] + u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes] + u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] + u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] + u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] + u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] + u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] + u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] + u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes] }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; typedef enum _RT_RF_TYPE_819xU{ - RF_TYPE_MIN = 0, - RF_8225, - RF_8256, - RF_8258, - RF_PSEUDO_11N = 4, + RF_TYPE_MIN = 0, + RF_8225, + RF_8256, + RF_8258, + RF_PSEUDO_11N = 4, }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU; -typedef struct _rate_adaptive -{ +typedef struct _rate_adaptive { u8 rate_adaptive_disabled; u8 ratr_state; u16 reserve; @@ -775,21 +772,18 @@ typedef struct _rate_adaptive #define TxBBGainTableLength 37 #define CCKTxBBGainTableLength 23 -typedef struct _txbbgain_struct -{ +typedef struct _txbbgain_struct { long txbb_iq_amplifygain; u32 txbbgain_value; } txbbgain_struct, *ptxbbgain_struct; -typedef struct _ccktxbbgain_struct -{ +typedef struct _ccktxbbgain_struct { //The Value is from a22 to a29 one Byte one time is much Safer u8 ccktxbb_valuearray[8]; } ccktxbbgain_struct,*pccktxbbgain_struct; -typedef struct _init_gain -{ +typedef struct _init_gain { u8 xaagccore1; u8 xbagccore1; u8 xcagccore1; @@ -799,8 +793,7 @@ typedef struct _init_gain } init_gain, *pinit_gain; //by amy 0606 -typedef struct _phy_ofdm_rx_status_report_819xusb -{ +typedef struct _phy_ofdm_rx_status_report_819xusb { u8 trsw_gain_X[4]; u8 pwdb_all; u8 cfosho_X[4]; @@ -816,8 +809,7 @@ typedef struct _phy_ofdm_rx_status_report_819xusb u8 rxsc_sgien_exflg; }phy_sts_ofdm_819xusb_t; -typedef struct _phy_cck_rx_status_report_819xusb -{ +typedef struct _phy_cck_rx_status_report_819xusb { /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */ u8 adc_pwdb_X[4]; @@ -881,8 +873,7 @@ typedef enum _tag_TxCmd_Config_Index{ TXCMD_XXXX_CTRL, }DCMD_TXCMD_OP; -typedef struct r8192_priv -{ +typedef struct r8192_priv { struct usb_device *udev; //added for maintain info from eeprom short epromtype; @@ -907,7 +898,7 @@ typedef struct r8192_priv spinlock_t irq_lock; // spinlock_t irq_th_lock; spinlock_t tx_lock; - struct mutex mutex; + struct mutex mutex; //spinlock_t rf_lock; //used to lock rf write operation added by wb u16 irq_mask; @@ -970,8 +961,8 @@ typedef struct r8192_priv atomic_t irt_counter;//count for irq_rx_tasklet #endif #ifdef JACKSON_NEW_RX - struct sk_buff **pp_rxskb; - int rx_inx; + struct sk_buff **pp_rxskb; + int rx_inx; #endif /* modified by davad for Rx process */ @@ -1006,7 +997,7 @@ typedef struct r8192_priv u8 retry_rts; u16 rts; - struct ChnlAccessSetting ChannelAccessSetting; + struct ChnlAccessSetting ChannelAccessSetting; struct work_struct reset_wq; /**********************************************************/ @@ -1014,7 +1005,7 @@ typedef struct r8192_priv u16 basic_rate; u8 short_preamble; u8 slot_time; - bool bDcut; + bool bDcut; bool bCurrentRxAggrEnable; u8 Rf_Mode; //add for Firmware RF -R/W switch prt_firmware pFirmware; @@ -1050,7 +1041,7 @@ typedef struct r8192_priv //for set channel u8 SwChnlInProgress; - u8 SwChnlStage; + u8 SwChnlStage; u8 SwChnlStep; u8 SetBWModeInProgress; HT_CHANNEL_WIDTH CurrentChannelBW; @@ -1062,8 +1053,8 @@ typedef struct r8192_priv // We save RF reg0 in this variable to reduce RF reading. // u32 RfReg0Value[4]; - u8 NumTotalRFPath; - bool brfpath_rxenable[4]; + u8 NumTotalRFPath; + bool brfpath_rxenable[4]; //RF set related bool SetRFPowerStateInProgress; //+by amy 080507 @@ -1104,7 +1095,7 @@ typedef struct r8192_priv bool btxpower_tracking; bool bcck_in_ch14; bool btxpowerdata_readfromEEPORM; - u16 TSSI_13dBm; + u16 TSSI_13dBm; //For Backup Initial Gain init_gain initgain_backup; u8 DefaultInitialGain[4]; @@ -1114,17 +1105,17 @@ typedef struct r8192_priv bool bis_cur_rdlstate; struct timer_list fsync_timer; bool bfsync_processing; // 500ms Fsync timer is active or not - u32 rate_record; - u32 rateCountDiffRecord; + u32 rate_record; + u32 rateCountDiffRecord; u32 ContinueDiffCount; bool bswitch_fsync; u8 framesync; - u32 framesyncC34; - u8 framesyncMonitor; - //Added by amy 080516 for RX related - u16 nrxAMPDU_size; - u8 nrxAMPDU_aggr_num; + u32 framesyncC34; + u8 framesyncMonitor; + //Added by amy 080516 for RX related + u16 nrxAMPDU_size; + u8 nrxAMPDU_aggr_num; //by amy for gpio bool bHwRadioOff; @@ -1204,7 +1195,7 @@ typedef enum{ #ifdef JOHN_HWSEC struct ssid_thread { struct net_device *dev; - u8 name[IW_ESSID_MAX_SIZE + 1]; + u8 name[IW_ESSID_MAX_SIZE + 1]; }; #endif |