diff options
Diffstat (limited to 'drivers/staging/sm750fb/ddk750_chip.c')
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_chip.c | 106 |
1 files changed, 61 insertions, 45 deletions
diff --git a/drivers/staging/sm750fb/ddk750_chip.c b/drivers/staging/sm750fb/ddk750_chip.c index f80ee776677f..839d6730bde9 100644 --- a/drivers/staging/sm750fb/ddk750_chip.c +++ b/drivers/staging/sm750fb/ddk750_chip.c @@ -6,11 +6,9 @@ #include "ddk750_chip.h" #include "ddk750_power.h" -/* n / d + 1 / 2 = (2n + d) / 2d */ -#define roundedDiv(num, denom) ((2 * (num) + (denom)) / (2 * (denom))) #define MHz(x) ((x) * 1000000) -logical_chip_type_t getChipType(void) +logical_chip_type_t sm750_get_chip_type(void) { unsigned short physicalID; char physicalRev; @@ -37,7 +35,7 @@ static unsigned int get_mxclk_freq(void) unsigned int pll_reg; unsigned int M, N, OD, POD; - if (getChipType() == SM750LE) + if (sm750_get_chip_type() == SM750LE) return MHz(130); pll_reg = PEEK32(MXCLK_PLL_CTRL); @@ -60,7 +58,7 @@ static void setChipClock(unsigned int frequency) unsigned int ulActualMxClk; /* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */ - if (getChipType() == SM750LE) + if (sm750_get_chip_type() == SM750LE) return; if (frequency) { @@ -71,9 +69,10 @@ static void setChipClock(unsigned int frequency) pll.clockType = MXCLK_PLL; /* - * Call calcPllValue() to fill up the other fields for PLL structure. - * Sometime, the chip cannot set up the exact clock required by User. - * Return value from calcPllValue() gives the actual possible clock. + * Call calcPllValue() to fill the other fields of PLL structure. + * Sometime, the chip cannot set up the exact clock + * required by the User. + * Return value of calcPllValue gives the actual possible clock. */ ulActualMxClk = calcPllValue(frequency, &pll); @@ -86,18 +85,22 @@ static void setMemoryClock(unsigned int frequency) { unsigned int reg, divisor; - /* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */ - if (getChipType() == SM750LE) + /* Cheok_0509: For SM750LE, the memory clock is fixed. + * Nothing to set. + */ + if (sm750_get_chip_type() == SM750LE) return; if (frequency) { - /* Set the frequency to the maximum frequency that the DDR Memory can take - which is 336MHz. */ + /* + * Set the frequency to the maximum frequency + * that the DDR Memory can take which is 336MHz. + */ if (frequency > MHz(336)) frequency = MHz(336); /* Calculate the divisor */ - divisor = roundedDiv(get_mxclk_freq(), frequency); + divisor = DIV_ROUND_CLOSEST(get_mxclk_freq(), frequency); /* Set the corresponding divisor in the register. */ reg = PEEK32(CURRENT_GATE) & ~CURRENT_GATE_M2XCLK_MASK; @@ -133,18 +136,21 @@ static void setMasterClock(unsigned int frequency) { unsigned int reg, divisor; - /* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */ - if (getChipType() == SM750LE) + /* Cheok_0509: For SM750LE, the memory clock is fixed. + * Nothing to set. + */ + if (sm750_get_chip_type() == SM750LE) return; if (frequency) { - /* Set the frequency to the maximum frequency that the SM750 engine can - run, which is about 190 MHz. */ + /* Set the frequency to the maximum frequency + * that the SM750 engine can run, which is about 190 MHz. + */ if (frequency > MHz(190)) frequency = MHz(190); /* Calculate the divisor */ - divisor = roundedDiv(get_mxclk_freq(), frequency); + divisor = DIV_ROUND_CLOSEST(get_mxclk_freq(), frequency); /* Set the corresponding divisor in the register. */ reg = PEEK32(CURRENT_GATE) & ~CURRENT_GATE_MCLK_MASK; @@ -174,7 +180,7 @@ unsigned int ddk750_getVMSize(void) unsigned int data; /* sm750le only use 64 mb memory*/ - if (getChipType() == SM750LE) + if (sm750_get_chip_type() == SM750LE) return SZ_64M; /* for 750,always use power mode0*/ @@ -213,7 +219,7 @@ int ddk750_initHw(initchip_param_t *pInitParam) reg |= (CURRENT_GATE_DISPLAY | CURRENT_GATE_LOCALMEM); setCurrentGate(reg); - if (getChipType() != SM750LE) { + if (sm750_get_chip_type() != SM750LE) { /* set panel pll and graphic mode via mmio_88 */ reg = PEEK32(VGA_CONFIGURATION); reg |= (VGA_CONFIGURATION_PLL | VGA_CONFIGURATION_MODE); @@ -236,9 +242,10 @@ int ddk750_initHw(initchip_param_t *pInitParam) setMasterClock(MHz(pInitParam->masterClock)); - /* Reset the memory controller. If the memory controller is not reset in SM750, - the system might hang when sw accesses the memory. - The memory should be resetted after changing the MXCLK. + /* Reset the memory controller. + * If the memory controller is not reset in SM750, + * the system might hang when sw accesses the memory. + * The memory should be resetted after changing the MXCLK. */ if (pInitParam->resetMemory == 1) { reg = PEEK32(MISC_CTRL); @@ -282,24 +289,27 @@ int ddk750_initHw(initchip_param_t *pInitParam) } /* - monk liu @ 4/6/2011: - re-write the calculatePLL function of ddk750. - the original version function does not use some mathematics tricks and shortcut - when it doing the calculation of the best N,M,D combination - I think this version gives a little upgrade in speed - - 750 pll clock formular: - Request Clock = (Input Clock * M )/(N * X) - - Input Clock = 14318181 hz - X = 2 power D - D ={0,1,2,3,4,5,6} - M = {1,...,255} - N = {2,...,15} -*/ + * monk liu @ 4/6/2011: + * re-write the calculatePLL function of ddk750. + * the original version function does not use + * some mathematics tricks and shortcut + * when it doing the calculation of the best N,M,D combination + * I think this version gives a little upgrade in speed + * + * 750 pll clock formular: + * Request Clock = (Input Clock * M )/(N * X) + * + * Input Clock = 14318181 hz + * X = 2 power D + * D ={0,1,2,3,4,5,6} + * M = {1,...,255} + * N = {2,...,15} + */ unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll) { - /* as sm750 register definition, N located in 2,15 and M located in 1,255 */ + /* as sm750 register definition, + * N located in 2,15 and M located in 1,255 + */ int N, M, X, d; int mini_diff; unsigned int RN, quo, rem, fl_quo; @@ -308,9 +318,11 @@ unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll) const int max_OD = 3; int max_d = 6; - if (getChipType() == SM750LE) { - /* SM750LE don't have prgrammable PLL and M/N values to work on. - Just return the requested clock. */ + if (sm750_get_chip_type() == SM750LE) { + /* SM750LE don't have + * programmable PLL and M/N values to work on. + * Just return the requested clock. + */ return request_orig; } @@ -319,19 +331,23 @@ unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll) request = request_orig / 1000; input = pll->inputFreq / 1000; - /* for MXCLK register , no POD provided, so need be treated differently */ + /* for MXCLK register, + * no POD provided, so need be treated differently + */ if (pll->clockType == MXCLK_PLL) max_d = 3; for (N = 15; N > 1; N--) { - /* RN will not exceed maximum long if @request <= 285 MHZ (for 32bit cpu) */ + /* RN will not exceed maximum long + * if @request <= 285 MHZ (for 32bit cpu) + */ RN = N * request; quo = RN / input; rem = RN % input;/* rem always small than 14318181 */ fl_quo = (rem * 10000 / input); for (d = max_d; d >= 0; d--) { - X = (1 << d); + X = BIT(d); M = quo * X; M += fl_quo * X / 10000; /* round step */ |