diff options
Diffstat (limited to 'drivers/staging/sm750fb/ddk750_mode.c')
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_mode.c | 37 |
1 files changed, 20 insertions, 17 deletions
diff --git a/drivers/staging/sm750fb/ddk750_mode.c b/drivers/staging/sm750fb/ddk750_mode.c index 05b83646c2d5..4a4b1de97a87 100644 --- a/drivers/staging/sm750fb/ddk750_mode.c +++ b/drivers/staging/sm750fb/ddk750_mode.c @@ -1,10 +1,10 @@ -#include "ddk750_help.h" #include "ddk750_reg.h" #include "ddk750_mode.h" #include "ddk750_chip.h" -/* SM750LE only: +/* + * SM750LE only: * This function takes care extra registers and bit fields required to set * up a mode in SM750LE * @@ -19,7 +19,8 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam, x = pModeParam->horizontal_display_end; y = pModeParam->vertical_display_end; - /* SM750LE has to set up the top-left and bottom-right + /* + * SM750LE has to set up the top-left and bottom-right * registers as well. * Note that normal SM750/SM718 only use those two register for * auto-centering mode. @@ -31,7 +32,8 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam, CRT_AUTO_CENTERING_BR_BOTTOM_MASK) | ((x - 1) & CRT_AUTO_CENTERING_BR_RIGHT_MASK)); - /* Assume common fields in dispControl have been properly set before + /* + * Assume common fields in dispControl have been properly set before * calling this function. * This function only sets the extra fields in dispControl. */ @@ -72,7 +74,8 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam, /* only timing related registers will be programed */ -static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll) +static int programModeRegisters(mode_parameter_t *pModeParam, + struct pll_value *pll) { int ret = 0; int cnt = 0; @@ -80,7 +83,7 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll) if (pll->clockType == SECONDARY_PLL) { /* programe secondary pixel clock */ - POKE32(CRT_PLL_CTRL, formatPllReg(pll)); + POKE32(CRT_PLL_CTRL, sm750_format_pll_reg(pll)); POKE32(CRT_HORIZONTAL_TOTAL, (((pModeParam->horizontal_total - 1) << CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT) & @@ -130,7 +133,7 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll) } else if (pll->clockType == PRIMARY_PLL) { unsigned int reserved; - POKE32(PANEL_PLL_CTRL, formatPllReg(pll)); + POKE32(PANEL_PLL_CTRL, sm750_format_pll_reg(pll)); reg = ((pModeParam->horizontal_total - 1) << PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT) & @@ -176,14 +179,14 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll) DISPLAY_CTRL_HSYNC_PHASE | DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE); - /* May a hardware bug or just my test chip (not confirmed). - * PANEL_DISPLAY_CTRL register seems requiring few writes - * before a value can be successfully written in. - * Added some masks to mask out the reserved bits. - * Note: This problem happens by design. The hardware will wait for the - * next vertical sync to turn on/off the plane. - */ - + /* + * May a hardware bug or just my test chip (not confirmed). + * PANEL_DISPLAY_CTRL register seems requiring few writes + * before a value can be successfully written in. + * Added some masks to mask out the reserved bits. + * Note: This problem happens by design. The hardware will wait + * for the next vertical sync to turn on/off the plane. + */ POKE32(PANEL_DISPLAY_CTRL, tmp | reg); while ((PEEK32(PANEL_DISPLAY_CTRL) & ~reserved) != @@ -201,13 +204,13 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll) int ddk750_setModeTiming(mode_parameter_t *parm, clock_type_t clock) { - pll_value_t pll; + struct pll_value pll; unsigned int uiActualPixelClk; pll.inputFreq = DEFAULT_INPUT_CLOCK; pll.clockType = clock; - uiActualPixelClk = calcPllValue(parm->pixel_clock, &pll); + uiActualPixelClk = sm750_calc_pll_value(parm->pixel_clock, &pll); if (sm750_get_chip_type() == SM750LE) { /* set graphic mode via IO method */ outb_p(0x88, 0x3d4); |