diff options
Diffstat (limited to 'drivers/staging/sm750fb/ddk750_mode.c')
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_mode.c | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/drivers/staging/sm750fb/ddk750_mode.c b/drivers/staging/sm750fb/ddk750_mode.c index 2e418fb6ffde..74313ff84e45 100644 --- a/drivers/staging/sm750fb/ddk750_mode.c +++ b/drivers/staging/sm750fb/ddk750_mode.c @@ -75,15 +75,15 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam, /* only timing related registers will be programed */ -static int programModeRegisters(mode_parameter_t * pModeParam,pll_value_t * pll) +static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll) { int ret = 0; int cnt = 0; - unsigned int ulTmpValue,ulReg; + unsigned int ulTmpValue, ulReg; if(pll->clockType == SECONDARY_PLL) { /* programe secondary pixel clock */ - POKE32(CRT_PLL_CTRL,formatPllReg(pll)); + POKE32(CRT_PLL_CTRL, formatPllReg(pll)); POKE32(CRT_HORIZONTAL_TOTAL, FIELD_VALUE(0, CRT_HORIZONTAL_TOTAL, TOTAL, pModeParam->horizontal_total - 1) | FIELD_VALUE(0, CRT_HORIZONTAL_TOTAL, DISPLAY_END, pModeParam->horizontal_display_end - 1)); @@ -101,29 +101,29 @@ static int programModeRegisters(mode_parameter_t * pModeParam,pll_value_t * pll) | FIELD_VALUE(0, CRT_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1)); - ulTmpValue = FIELD_VALUE(0,CRT_DISPLAY_CTRL,VSYNC_PHASE,pModeParam->vertical_sync_polarity)| - FIELD_VALUE(0,CRT_DISPLAY_CTRL,HSYNC_PHASE,pModeParam->horizontal_sync_polarity)| - FIELD_SET(0,CRT_DISPLAY_CTRL,TIMING,ENABLE)| - FIELD_SET(0,CRT_DISPLAY_CTRL,PLANE,ENABLE); + ulTmpValue = FIELD_VALUE(0, CRT_DISPLAY_CTRL, VSYNC_PHASE, pModeParam->vertical_sync_polarity)| + FIELD_VALUE(0, CRT_DISPLAY_CTRL, HSYNC_PHASE, pModeParam->horizontal_sync_polarity)| + FIELD_SET(0, CRT_DISPLAY_CTRL, TIMING, ENABLE)| + FIELD_SET(0, CRT_DISPLAY_CTRL, PLANE, ENABLE); if(getChipType() == SM750LE){ - displayControlAdjust_SM750LE(pModeParam,ulTmpValue); + displayControlAdjust_SM750LE(pModeParam, ulTmpValue); }else{ ulReg = PEEK32(CRT_DISPLAY_CTRL) - & FIELD_CLEAR(CRT_DISPLAY_CTRL,VSYNC_PHASE) - & FIELD_CLEAR(CRT_DISPLAY_CTRL,HSYNC_PHASE) - & FIELD_CLEAR(CRT_DISPLAY_CTRL,TIMING) - & FIELD_CLEAR(CRT_DISPLAY_CTRL,PLANE); + & FIELD_CLEAR(CRT_DISPLAY_CTRL, VSYNC_PHASE) + & FIELD_CLEAR(CRT_DISPLAY_CTRL, HSYNC_PHASE) + & FIELD_CLEAR(CRT_DISPLAY_CTRL, TIMING) + & FIELD_CLEAR(CRT_DISPLAY_CTRL, PLANE); - POKE32(CRT_DISPLAY_CTRL,ulTmpValue|ulReg); + POKE32(CRT_DISPLAY_CTRL, ulTmpValue|ulReg); } } else if(pll->clockType == PRIMARY_PLL) { unsigned int ulReservedBits; - POKE32(PANEL_PLL_CTRL,formatPllReg(pll)); + POKE32(PANEL_PLL_CTRL, formatPllReg(pll)); POKE32(PANEL_HORIZONTAL_TOTAL, FIELD_VALUE(0, PANEL_HORIZONTAL_TOTAL, TOTAL, pModeParam->horizontal_total - 1) @@ -141,16 +141,16 @@ static int programModeRegisters(mode_parameter_t * pModeParam,pll_value_t * pll) FIELD_VALUE(0, PANEL_VERTICAL_SYNC, HEIGHT, pModeParam->vertical_sync_height) | FIELD_VALUE(0, PANEL_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1)); - ulTmpValue = FIELD_VALUE(0,PANEL_DISPLAY_CTRL,VSYNC_PHASE,pModeParam->vertical_sync_polarity)| - FIELD_VALUE(0,PANEL_DISPLAY_CTRL,HSYNC_PHASE,pModeParam->horizontal_sync_polarity)| - FIELD_VALUE(0,PANEL_DISPLAY_CTRL,CLOCK_PHASE,pModeParam->clock_phase_polarity)| - FIELD_SET(0,PANEL_DISPLAY_CTRL,TIMING,ENABLE)| - FIELD_SET(0,PANEL_DISPLAY_CTRL,PLANE,ENABLE); + ulTmpValue = FIELD_VALUE(0, PANEL_DISPLAY_CTRL, VSYNC_PHASE, pModeParam->vertical_sync_polarity)| + FIELD_VALUE(0, PANEL_DISPLAY_CTRL, HSYNC_PHASE, pModeParam->horizontal_sync_polarity)| + FIELD_VALUE(0, PANEL_DISPLAY_CTRL, CLOCK_PHASE, pModeParam->clock_phase_polarity)| + FIELD_SET(0, PANEL_DISPLAY_CTRL, TIMING, ENABLE)| + FIELD_SET(0, PANEL_DISPLAY_CTRL, PLANE, ENABLE); ulReservedBits = FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) | FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) | FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE)| - FIELD_SET(0,PANEL_DISPLAY_CTRL,VSYNC,ACTIVE_LOW); + FIELD_SET(0, PANEL_DISPLAY_CTRL, VSYNC, ACTIVE_LOW); ulReg = (PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) & FIELD_CLEAR(PANEL_DISPLAY_CTRL, CLOCK_PHASE) @@ -162,20 +162,20 @@ static int programModeRegisters(mode_parameter_t * pModeParam,pll_value_t * pll) /* May a hardware bug or just my test chip (not confirmed). * PANEL_DISPLAY_CTRL register seems requiring few writes - * before a value can be succesfully written in. + * before a value can be successfully written in. * Added some masks to mask out the reserved bits. * Note: This problem happens by design. The hardware will wait for the * next vertical sync to turn on/off the plane. */ - POKE32(PANEL_DISPLAY_CTRL,ulTmpValue|ulReg); + POKE32(PANEL_DISPLAY_CTRL, ulTmpValue|ulReg); #if 1 while((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) != (ulTmpValue|ulReg)) { cnt++; if(cnt > 1000) break; - POKE32(PANEL_DISPLAY_CTRL,ulTmpValue|ulReg); + POKE32(PANEL_DISPLAY_CTRL, ulTmpValue|ulReg); } #endif } @@ -185,20 +185,20 @@ static int programModeRegisters(mode_parameter_t * pModeParam,pll_value_t * pll) return ret; } -int ddk750_setModeTiming(mode_parameter_t * parm,clock_type_t clock) +int ddk750_setModeTiming(mode_parameter_t *parm, clock_type_t clock) { pll_value_t pll; unsigned int uiActualPixelClk; pll.inputFreq = DEFAULT_INPUT_CLOCK; pll.clockType = clock; - uiActualPixelClk = calcPllValue(parm->pixel_clock,&pll); + uiActualPixelClk = calcPllValue(parm->pixel_clock, &pll); if(getChipType() == SM750LE){ /* set graphic mode via IO method */ - outb_p(0x88,0x3d4); - outb_p(0x06,0x3d5); + outb_p(0x88, 0x3d4); + outb_p(0x06, 0x3d5); } - programModeRegisters(parm,&pll); + programModeRegisters(parm, &pll); return 0; } |