diff options
Diffstat (limited to 'drivers/staging/sm750fb/ddk750_sii164.c')
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_sii164.c | 114 |
1 files changed, 57 insertions, 57 deletions
diff --git a/drivers/staging/sm750fb/ddk750_sii164.c b/drivers/staging/sm750fb/ddk750_sii164.c index 8391f57d5383..c8e856c13912 100644 --- a/drivers/staging/sm750fb/ddk750_sii164.c +++ b/drivers/staging/sm750fb/ddk750_sii164.c @@ -69,58 +69,58 @@ unsigned short sii164GetDeviceID(void) * This function initialize and detect the DVI controller chip. * * Input: - * edgeSelect - Edge Select: - * 0 = Input data is falling edge latched (falling edge - * latched first in dual edge mode) - * 1 = Input data is rising edge latched (rising edge - * latched first in dual edge mode) - * busSelect - Input Bus Select: - * 0 = Input data bus is 12-bits wide - * 1 = Input data bus is 24-bits wide - * dualEdgeClkSelect - Dual Edge Clock Select - * 0 = Input data is single edge latched - * 1 = Input data is dual edge latched - * hsyncEnable - Horizontal Sync Enable: - * 0 = HSYNC input is transmitted as fixed LOW - * 1 = HSYNC input is transmitted as is - * vsyncEnable - Vertical Sync Enable: - * 0 = VSYNC input is transmitted as fixed LOW - * 1 = VSYNC input is transmitted as is - * deskewEnable - De-skewing Enable: - * 0 = De-skew disabled - * 1 = De-skew enabled - * deskewSetting - De-skewing Setting (increment of 260psec) - * 0 = 1 step --> minimum setup / maximum hold - * 1 = 2 step - * 2 = 3 step - * 3 = 4 step - * 4 = 5 step - * 5 = 6 step - * 6 = 7 step - * 7 = 8 step --> maximum setup / minimum hold - * continuousSyncEnable- SYNC Continuous: - * 0 = Disable - * 1 = Enable - * pllFilterEnable - PLL Filter Enable - * 0 = Disable PLL Filter - * 1 = Enable PLL Filter - * pllFilterValue - PLL Filter characteristics: - * 0~7 (recommended value is 4) + * edge_select - Edge Select: + * 0 = Input data is falling edge latched (falling + * edge latched first in dual edge mode) + * 1 = Input data is rising edge latched (rising + * edge latched first in dual edge mode) + * bus_select - Input Bus Select: + * 0 = Input data bus is 12-bits wide + * 1 = Input data bus is 24-bits wide + * dual_edge_clk_select - Dual Edge Clock Select + * 0 = Input data is single edge latched + * 1 = Input data is dual edge latched + * hsync_enable - Horizontal Sync Enable: + * 0 = HSYNC input is transmitted as fixed LOW + * 1 = HSYNC input is transmitted as is + * vsync_enable - Vertical Sync Enable: + * 0 = VSYNC input is transmitted as fixed LOW + * 1 = VSYNC input is transmitted as is + * deskew_enable - De-skewing Enable: + * 0 = De-skew disabled + * 1 = De-skew enabled + * deskew_setting - De-skewing Setting (increment of 260psec) + * 0 = 1 step --> minimum setup / maximum hold + * 1 = 2 step + * 2 = 3 step + * 3 = 4 step + * 4 = 5 step + * 5 = 6 step + * 6 = 7 step + * 7 = 8 step --> maximum setup / minimum hold + * continuous_sync_enable- SYNC Continuous: + * 0 = Disable + * 1 = Enable + * pll_filter_enable - PLL Filter Enable + * 0 = Disable PLL Filter + * 1 = Enable PLL Filter + * pll_filter_value - PLL Filter characteristics: + * 0~7 (recommended value is 4) * * Output: * 0 - Success * -1 - Fail. */ -long sii164InitChip(unsigned char edgeSelect, - unsigned char busSelect, - unsigned char dualEdgeClkSelect, - unsigned char hsyncEnable, - unsigned char vsyncEnable, - unsigned char deskewEnable, - unsigned char deskewSetting, - unsigned char continuousSyncEnable, - unsigned char pllFilterEnable, - unsigned char pllFilterValue) +long sii164InitChip(unsigned char edge_select, + unsigned char bus_select, + unsigned char dual_edge_clk_select, + unsigned char hsync_enable, + unsigned char vsync_enable, + unsigned char deskew_enable, + unsigned char deskew_setting, + unsigned char continuous_sync_enable, + unsigned char pll_filter_enable, + unsigned char pll_filter_value) { unsigned char config; @@ -139,31 +139,31 @@ long sii164InitChip(unsigned char edgeSelect, */ /* Select the edge */ - if (edgeSelect == 0) + if (edge_select == 0) config = SII164_CONFIGURATION_LATCH_FALLING; else config = SII164_CONFIGURATION_LATCH_RISING; /* Select bus wide */ - if (busSelect == 0) + if (bus_select == 0) config |= SII164_CONFIGURATION_BUS_12BITS; else config |= SII164_CONFIGURATION_BUS_24BITS; /* Select Dual/Single Edge Clock */ - if (dualEdgeClkSelect == 0) + if (dual_edge_clk_select == 0) config |= SII164_CONFIGURATION_CLOCK_SINGLE; else config |= SII164_CONFIGURATION_CLOCK_DUAL; /* Select HSync Enable */ - if (hsyncEnable == 0) + if (hsync_enable == 0) config |= SII164_CONFIGURATION_HSYNC_FORCE_LOW; else config |= SII164_CONFIGURATION_HSYNC_AS_IS; /* Select VSync Enable */ - if (vsyncEnable == 0) + if (vsync_enable == 0) config |= SII164_CONFIGURATION_VSYNC_FORCE_LOW; else config |= SII164_CONFIGURATION_VSYNC_AS_IS; @@ -175,12 +175,12 @@ long sii164InitChip(unsigned char edgeSelect, * This fixes some artifacts problem in some mode on board 2.2. * Somehow this fix does not affect board 2.1. */ - if (deskewEnable == 0) + if (deskew_enable == 0) config = SII164_DESKEW_DISABLE; else config = SII164_DESKEW_ENABLE; - switch (deskewSetting) { + switch (deskew_setting) { case 0: config |= SII164_DESKEW_1_STEP; break; @@ -209,19 +209,19 @@ long sii164InitChip(unsigned char edgeSelect, i2cWriteReg(SII164_I2C_ADDRESS, SII164_DESKEW, config); /* Enable/Disable Continuous Sync. */ - if (continuousSyncEnable == 0) + if (continuous_sync_enable == 0) config = SII164_PLL_FILTER_SYNC_CONTINUOUS_DISABLE; else config = SII164_PLL_FILTER_SYNC_CONTINUOUS_ENABLE; /* Enable/Disable PLL Filter */ - if (pllFilterEnable == 0) + if (pll_filter_enable == 0) config |= SII164_PLL_FILTER_DISABLE; else config |= SII164_PLL_FILTER_ENABLE; /* Set the PLL Filter value */ - config |= ((pllFilterValue & 0x07) << 1); + config |= ((pll_filter_value & 0x07) << 1); i2cWriteReg(SII164_I2C_ADDRESS, SII164_PLL, config); |