diff options
Diffstat (limited to 'drivers/staging/sm750fb')
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_chip.c | 132 | ||||
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_display.c | 200 | ||||
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_dvi.c | 38 | ||||
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_dvi.h | 3 | ||||
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_help.h | 1 | ||||
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_hwi2c.c | 38 | ||||
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_mode.c | 161 | ||||
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_power.c | 54 | ||||
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_power.h | 11 | ||||
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_reg.h | 3002 | ||||
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_sii164.c | 6 | ||||
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_sii164.h | 5 | ||||
| -rw-r--r-- | drivers/staging/sm750fb/sm750.c | 204 | ||||
| -rw-r--r-- | drivers/staging/sm750fb/sm750.h | 4 | ||||
| -rw-r--r-- | drivers/staging/sm750fb/sm750_accel.c | 148 | ||||
| -rw-r--r-- | drivers/staging/sm750fb/sm750_accel.h | 278 | ||||
| -rw-r--r-- | drivers/staging/sm750fb/sm750_cursor.c | 62 | ||||
| -rw-r--r-- | drivers/staging/sm750fb/sm750_help.h | 56 | ||||
| -rw-r--r-- | drivers/staging/sm750fb/sm750_hw.c | 211 |
19 files changed, 1716 insertions, 2898 deletions
diff --git a/drivers/staging/sm750fb/ddk750_chip.c b/drivers/staging/sm750fb/ddk750_chip.c index 0331d34458ae..95f7cae3cc23 100644 --- a/drivers/staging/sm750fb/ddk750_chip.c +++ b/drivers/staging/sm750fb/ddk750_chip.c @@ -1,3 +1,4 @@ +#include <linux/kernel.h> #include <linux/sizes.h> #include "ddk750_help.h" @@ -5,6 +6,10 @@ #include "ddk750_chip.h" #include "ddk750_power.h" +/* n / d + 1 / 2 = (2n + d) / 2d */ +#define roundedDiv(num, denom) ((2 * (num) + (denom)) / (2 * (denom))) +#define MHz(x) ((x) * 1000000) + logical_chip_type_t getChipType(void) { unsigned short physicalID; @@ -36,10 +41,10 @@ static unsigned int get_mxclk_freq(void) return MHz(130); pll_reg = PEEK32(MXCLK_PLL_CTRL); - M = FIELD_GET(pll_reg, PANEL_PLL_CTRL, M); - N = FIELD_GET(pll_reg, PANEL_PLL_CTRL, N); - OD = FIELD_GET(pll_reg, PANEL_PLL_CTRL, OD); - POD = FIELD_GET(pll_reg, PANEL_PLL_CTRL, POD); + M = (pll_reg & PLL_CTRL_M_MASK) >> PLL_CTRL_M_SHIFT; + N = (pll_reg & PLL_CTRL_N_MASK) >> PLL_CTRL_M_SHIFT; + OD = (pll_reg & PLL_CTRL_OD_MASK) >> PLL_CTRL_OD_SHIFT; + POD = (pll_reg & PLL_CTRL_POD_MASK) >> PLL_CTRL_POD_SHIFT; return DEFAULT_INPUT_CLOCK * M / N / (1 << OD) / (1 << POD); } @@ -79,7 +84,7 @@ static void setChipClock(unsigned int frequency) static void setMemoryClock(unsigned int frequency) { - unsigned int ulReg, divisor; + unsigned int reg, divisor; /* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */ if (getChipType() == SM750LE) @@ -95,24 +100,24 @@ static void setMemoryClock(unsigned int frequency) divisor = roundedDiv(get_mxclk_freq(), frequency); /* Set the corresponding divisor in the register. */ - ulReg = PEEK32(CURRENT_GATE); + reg = PEEK32(CURRENT_GATE) & ~CURRENT_GATE_M2XCLK_MASK; switch (divisor) { default: case 1: - ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_1); + reg |= CURRENT_GATE_M2XCLK_DIV_1; break; case 2: - ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_2); + reg |= CURRENT_GATE_M2XCLK_DIV_2; break; case 3: - ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_3); + reg |= CURRENT_GATE_M2XCLK_DIV_3; break; case 4: - ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_4); + reg |= CURRENT_GATE_M2XCLK_DIV_4; break; } - setCurrentGate(ulReg); + setCurrentGate(reg); } } @@ -126,7 +131,7 @@ static void setMemoryClock(unsigned int frequency) */ static void setMasterClock(unsigned int frequency) { - unsigned int ulReg, divisor; + unsigned int reg, divisor; /* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */ if (getChipType() == SM750LE) @@ -142,24 +147,24 @@ static void setMasterClock(unsigned int frequency) divisor = roundedDiv(get_mxclk_freq(), frequency); /* Set the corresponding divisor in the register. */ - ulReg = PEEK32(CURRENT_GATE); + reg = PEEK32(CURRENT_GATE) & ~CURRENT_GATE_MCLK_MASK; switch (divisor) { default: case 3: - ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_3); + reg |= CURRENT_GATE_MCLK_DIV_3; break; case 4: - ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_4); + reg |= CURRENT_GATE_MCLK_DIV_4; break; case 6: - ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_6); + reg |= CURRENT_GATE_MCLK_DIV_6; break; case 8: - ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_8); + reg |= CURRENT_GATE_MCLK_DIV_8; break; } - setCurrentGate(ulReg); + setCurrentGate(reg); } } @@ -174,11 +179,11 @@ unsigned int ddk750_getVMSize(void) /* for 750,always use power mode0*/ reg = PEEK32(MODE0_GATE); - reg = FIELD_SET(reg, MODE0_GATE, GPIO, ON); + reg |= MODE0_GATE_GPIO; POKE32(MODE0_GATE, reg); /* get frame buffer size from GPIO */ - reg = FIELD_GET(PEEK32(MISC_CTRL), MISC_CTRL, LOCALMEM_SIZE); + reg = PEEK32(MISC_CTRL) & MISC_CTRL_LOCALMEM_SIZE_MASK; switch (reg) { case MISC_CTRL_LOCALMEM_SIZE_8M: data = SZ_8M; break; /* 8 Mega byte */ @@ -197,24 +202,22 @@ unsigned int ddk750_getVMSize(void) int ddk750_initHw(initchip_param_t *pInitParam) { - unsigned int ulReg; + unsigned int reg; if (pInitParam->powerMode != 0) pInitParam->powerMode = 0; setPowerMode(pInitParam->powerMode); /* Enable display power gate & LOCALMEM power gate*/ - ulReg = PEEK32(CURRENT_GATE); - ulReg = FIELD_SET(ulReg, CURRENT_GATE, DISPLAY, ON); - ulReg = FIELD_SET(ulReg, CURRENT_GATE, LOCALMEM, ON); - setCurrentGate(ulReg); + reg = PEEK32(CURRENT_GATE); + reg |= (CURRENT_GATE_DISPLAY | CURRENT_GATE_LOCALMEM); + setCurrentGate(reg); if (getChipType() != SM750LE) { /* set panel pll and graphic mode via mmio_88 */ - ulReg = PEEK32(VGA_CONFIGURATION); - ulReg = FIELD_SET(ulReg, VGA_CONFIGURATION, PLL, PANEL); - ulReg = FIELD_SET(ulReg, VGA_CONFIGURATION, MODE, GRAPHIC); - POKE32(VGA_CONFIGURATION, ulReg); + reg = PEEK32(VGA_CONFIGURATION); + reg |= (VGA_CONFIGURATION_PLL | VGA_CONFIGURATION_MODE); + POKE32(VGA_CONFIGURATION, reg); } else { #if defined(__i386__) || defined(__x86_64__) /* set graphic mode via IO method */ @@ -238,36 +241,36 @@ int ddk750_initHw(initchip_param_t *pInitParam) The memory should be resetted after changing the MXCLK. */ if (pInitParam->resetMemory == 1) { - ulReg = PEEK32(MISC_CTRL); - ulReg = FIELD_SET(ulReg, MISC_CTRL, LOCALMEM_RESET, RESET); - POKE32(MISC_CTRL, ulReg); + reg = PEEK32(MISC_CTRL); + reg &= ~MISC_CTRL_LOCALMEM_RESET; + POKE32(MISC_CTRL, reg); - ulReg = FIELD_SET(ulReg, MISC_CTRL, LOCALMEM_RESET, NORMAL); - POKE32(MISC_CTRL, ulReg); + reg |= MISC_CTRL_LOCALMEM_RESET; + POKE32(MISC_CTRL, reg); } if (pInitParam->setAllEngOff == 1) { enable2DEngine(0); /* Disable Overlay, if a former application left it on */ - ulReg = PEEK32(VIDEO_DISPLAY_CTRL); - ulReg = FIELD_SET(ulReg, VIDEO_DISPLAY_CTRL, PLANE, DISABLE); - POKE32(VIDEO_DISPLAY_CTRL, ulReg); + reg = PEEK32(VIDEO_DISPLAY_CTRL); + reg &= ~DISPLAY_CTRL_PLANE; + POKE32(VIDEO_DISPLAY_CTRL, reg); /* Disable video alpha, if a former application left it on */ - ulReg = PEEK32(VIDEO_ALPHA_DISPLAY_CTRL); - ulReg = FIELD_SET(ulReg, VIDEO_ALPHA_DISPLAY_CTRL, PLANE, DISABLE); - POKE32(VIDEO_ALPHA_DISPLAY_CTRL, ulReg); + reg = PEEK32(VIDEO_ALPHA_DISPLAY_CTRL); + reg &= ~DISPLAY_CTRL_PLANE; + POKE32(VIDEO_ALPHA_DISPLAY_CTRL, reg); /* Disable alpha plane, if a former application left it on */ - ulReg = PEEK32(ALPHA_DISPLAY_CTRL); - ulReg = FIELD_SET(ulReg, ALPHA_DISPLAY_CTRL, PLANE, DISABLE); - POKE32(ALPHA_DISPLAY_CTRL, ulReg); + reg = PEEK32(ALPHA_DISPLAY_CTRL); + reg &= ~DISPLAY_CTRL_PLANE; + POKE32(ALPHA_DISPLAY_CTRL, reg); /* Disable DMA Channel, if a former application left it on */ - ulReg = PEEK32(DMA_ABORT_INTERRUPT); - ulReg = FIELD_SET(ulReg, DMA_ABORT_INTERRUPT, ABORT_1, ABORT); - POKE32(DMA_ABORT_INTERRUPT, ulReg); + reg = PEEK32(DMA_ABORT_INTERRUPT); + reg |= DMA_ABORT_INTERRUPT_ABORT_1; + POKE32(DMA_ABORT_INTERRUPT, reg); /* Disable DMA Power, if a former application left it on */ enableDMA(0); @@ -337,7 +340,7 @@ unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll) unsigned int diff; tmpClock = pll->inputFreq * M / N / X; - diff = absDiff(tmpClock, request_orig); + diff = abs(tmpClock - request_orig); if (diff < mini_diff) { pll->M = M; pll->N = N; @@ -356,24 +359,29 @@ unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll) unsigned int formatPllReg(pll_value_t *pPLL) { - unsigned int ulPllReg = 0; - - /* Note that all PLL's have the same format. Here, we just use Panel PLL parameter - to work out the bit fields in the register. - On returning a 32 bit number, the value can be applied to any PLL in the calling function. - */ - ulPllReg = - FIELD_SET(0, PANEL_PLL_CTRL, BYPASS, OFF) - | FIELD_SET(0, PANEL_PLL_CTRL, POWER, ON) - | FIELD_SET(0, PANEL_PLL_CTRL, INPUT, OSC) #ifndef VALIDATION_CHIP - | FIELD_VALUE(0, PANEL_PLL_CTRL, POD, pPLL->POD) + unsigned int POD = pPLL->POD; +#endif + unsigned int OD = pPLL->OD; + unsigned int M = pPLL->M; + unsigned int N = pPLL->N; + unsigned int reg = 0; + + /* + * Note that all PLL's have the same format. Here, we just use + * Panel PLL parameter to work out the bit fields in the + * register. On returning a 32 bit number, the value can be + * applied to any PLL in the calling function. + */ + reg = PLL_CTRL_POWER | +#ifndef VALIDATION_CHIP + ((POD << PLL_CTRL_POD_SHIFT) & PLL_CTRL_POD_MASK) | #endif - | FIELD_VALUE(0, PANEL_PLL_CTRL, OD, pPLL->OD) - | FIELD_VALUE(0, PANEL_PLL_CTRL, N, pPLL->N) - | FIELD_VALUE(0, PANEL_PLL_CTRL, M, pPLL->M); + ((OD << PLL_CTRL_OD_SHIFT) & PLL_CTRL_OD_MASK) | + ((N << PLL_CTRL_N_SHIFT) & PLL_CTRL_N_MASK) | + ((M << PLL_CTRL_M_SHIFT) & PLL_CTRL_M_MASK); - return ulPllReg; + return reg; } diff --git a/drivers/staging/sm750fb/ddk750_display.c b/drivers/staging/sm750fb/ddk750_display.c index 84f6e8b8c0e2..ca4973ee49e4 100644 --- a/drivers/staging/sm750fb/ddk750_display.c +++ b/drivers/staging/sm750fb/ddk750_display.c @@ -9,111 +9,55 @@ static void setDisplayControl(int ctrl, int disp_state) { /* state != 0 means turn on both timing & plane en_bit */ - unsigned long ulDisplayCtrlReg, ulReservedBits; - int cnt; + unsigned long reg, val, reserved; + int cnt = 0; - cnt = 0; - - /* Set the primary display control */ if (!ctrl) { - ulDisplayCtrlReg = PEEK32(PANEL_DISPLAY_CTRL); - /* Turn on/off the Panel display control */ - if (disp_state) { - /* Timing should be enabled first before enabling the plane - * because changing at the same time does not guarantee that - * the plane will also enabled or disabled. - */ - ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg, - PANEL_DISPLAY_CTRL, TIMING, ENABLE); - POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg); - - ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg, - PANEL_DISPLAY_CTRL, PLANE, ENABLE); - - /* Added some masks to mask out the reserved bits. - * Sometimes, the reserved bits are set/reset randomly when - * writing to the PRIMARY_DISPLAY_CTRL, therefore, the register - * reserved bits are needed to be masked out. - */ - ulReservedBits = FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) | - FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) | - FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE); - - /* Somehow the register value on the plane is not set - * until a few delay. Need to write - * and read it a couple times - */ - do { - cnt++; - POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg); - } while ((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) != - (ulDisplayCtrlReg & ~ulReservedBits)); - printk("Set Panel Plane enbit:after tried %d times\n", cnt); - } else { - /* When turning off, there is no rule on the programming - * sequence since whenever the clock is off, then it does not - * matter whether the plane is enabled or disabled. - * Note: Modifying the plane bit will take effect on the - * next vertical sync. Need to find out if it is necessary to - * wait for 1 vsync before modifying the timing enable bit. - * */ - ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg, - PANEL_DISPLAY_CTRL, PLANE, DISABLE); - POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg); - - ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg, - PANEL_DISPLAY_CTRL, TIMING, DISABLE); - POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg); - } - + reg = PANEL_DISPLAY_CTRL; + reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK; } else { - /* Set the secondary display control */ - ulDisplayCtrlReg = PEEK32(CRT_DISPLAY_CTRL); - - if (disp_state) { - /* Timing should be enabled first before enabling the plane because changing at the - same time does not guarantee that the plane will also enabled or disabled. - */ - ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg, - CRT_DISPLAY_CTRL, TIMING, ENABLE); - POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg); - - ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg, - CRT_DISPLAY_CTRL, PLANE, ENABLE); - - /* Added some masks to mask out the reserved bits. - * Sometimes, the reserved bits are set/reset randomly when - * writing to the PRIMARY_DISPLAY_CTRL, therefore, the register - * reserved bits are needed to be masked out. - */ - - ulReservedBits = FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) | - FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) | - FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE) | - FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_4_MASK, ENABLE); + reg = CRT_DISPLAY_CTRL; + reserved = CRT_DISPLAY_CTRL_RESERVED_MASK; + } - do { - cnt++; - POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg); - } while ((PEEK32(CRT_DISPLAY_CTRL) & ~ulReservedBits) != - (ulDisplayCtrlReg & ~ulReservedBits)); - printk("Set Crt Plane enbit:after tried %d times\n", cnt); - } else { - /* When turning off, there is no rule on the programming - * sequence since whenever the clock is off, then it does not - * matter whether the plane is enabled or disabled. - * Note: Modifying the plane bit will take effect on the next - * vertical sync. Need to find out if it is necessary to - * wait for 1 vsync before modifying the timing enable bit. - */ - ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg, - CRT_DISPLAY_CTRL, PLANE, DISABLE); - POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg); - - ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg, - CRT_DISPLAY_CTRL, TIMING, DISABLE); - POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg); - } + val = PEEK32(reg); + if (disp_state) { + /* + * Timing should be enabled first before enabling the + * plane because changing at the same time does not + * guarantee that the plane will also enabled or + * disabled. + */ + val |= DISPLAY_CTRL_TIMING; + POKE32(reg, val); + + val |= DISPLAY_CTRL_PLANE; + + /* + * Somehow the register value on the plane is not set + * until a few delay. Need to write and read it a + * couple times + */ + do { + cnt++; + POKE32(reg, val); + } while ((PEEK32(reg) & ~reserved) != (val & ~reserved)); + pr_debug("Set Plane enbit:after tried %d times\n", cnt); + } else { + /* + * When turning off, there is no rule on the + * programming sequence since whenever the clock is + * off, then it does not matter whether the plane is + * enabled or disabled. Note: Modifying the plane bit + * will take effect on the next vertical sync. Need to + * find out if it is necessary to wait for 1 vsync + * before modifying the timing enable bit. + */ + val &= ~DISPLAY_CTRL_PLANE; + POKE32(reg, val); + + val &= ~DISPLAY_CTRL_TIMING; + POKE32(reg, val); } } @@ -126,54 +70,42 @@ static void waitNextVerticalSync(int ctrl, int delay) /* Do not wait when the Primary PLL is off or display control is already off. This will prevent the software to wait forever. */ - if ((FIELD_GET(PEEK32(PANEL_PLL_CTRL), PANEL_PLL_CTRL, POWER) == - PANEL_PLL_CTRL_POWER_OFF) || - (FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, TIMING) == - PANEL_DISPLAY_CTRL_TIMING_DISABLE)) { + if (!(PEEK32(PANEL_PLL_CTRL) & PLL_CTRL_POWER) || + !(PEEK32(PANEL_DISPLAY_CTRL) & DISPLAY_CTRL_TIMING)) { return; } while (delay-- > 0) { /* Wait for end of vsync. */ do { - status = FIELD_GET(PEEK32(SYSTEM_CTRL), - SYSTEM_CTRL, - PANEL_VSYNC); - } while (status == SYSTEM_CTRL_PANEL_VSYNC_ACTIVE); + status = PEEK32(SYSTEM_CTRL); + } while (status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE); /* Wait for start of vsync. */ do { - status = FIELD_GET(PEEK32(SYSTEM_CTRL), - SYSTEM_CTRL, - PANEL_VSYNC); - } while (status == SYSTEM_CTRL_PANEL_VSYNC_INACTIVE); + status = PEEK32(SYSTEM_CTRL); + } while (!(status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE)); } } else { /* Do not wait when the Primary PLL is off or display control is already off. This will prevent the software to wait forever. */ - if ((FIELD_GET(PEEK32(CRT_PLL_CTRL), CRT_PLL_CTRL, POWER) == - CRT_PLL_CTRL_POWER_OFF) || - (FIELD_GET(PEEK32(CRT_DISPLAY_CTRL), CRT_DISPLAY_CTRL, TIMING) == - CRT_DISPLAY_CTRL_TIMING_DISABLE)) { + if (!(PEEK32(CRT_PLL_CTRL) & PLL_CTRL_POWER) || + !(PEEK32(CRT_DISPLAY_CTRL) & DISPLAY_CTRL_TIMING)) { return; } while (delay-- > 0) { /* Wait for end of vsync. */ do { - status = FIELD_GET(PEEK32(SYSTEM_CTRL), - SYSTEM_CTRL, - CRT_VSYNC); - } while (status == SYSTEM_CTRL_CRT_VSYNC_ACTIVE); + status = PEEK32(SYSTEM_CTRL); + } while (status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE); /* Wait for start of vsync. */ do { - status = FIELD_GET(PEEK32(SYSTEM_CTRL), - SYSTEM_CTRL, - CRT_VSYNC); - } while (status == SYSTEM_CTRL_CRT_VSYNC_INACTIVE); + status = PEEK32(SYSTEM_CTRL); + } while (!(status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE)); } } } @@ -184,22 +116,22 @@ static void swPanelPowerSequence(int disp, int delay) /* disp should be 1 to open sequence */ reg = PEEK32(PANEL_DISPLAY_CTRL); - reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, FPEN, disp); + reg |= (disp ? PANEL_DISPLAY_CTRL_FPEN : 0); POKE32(PANEL_DISPLAY_CTRL, reg); primaryWaitVerticalSync(delay); reg = PEEK32(PANEL_DISPLAY_CTRL); - reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, DATA, disp); + reg |= (disp ? PANEL_DISPLAY_CTRL_DATA : 0); POKE32(PANEL_DISPLAY_CTRL, reg); primaryWaitVerticalSync(delay); reg = PEEK32(PANEL_DISPLAY_CTRL); - reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, VBIASEN, disp); + reg |= (disp ? PANEL_DISPLAY_CTRL_VBIASEN : 0); POKE32(PANEL_DISPLAY_CTRL, reg); primaryWaitVerticalSync(delay); reg = PEEK32(PANEL_DISPLAY_CTRL); - reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, FPEN, disp); + reg |= (disp ? PANEL_DISPLAY_CTRL_FPEN : 0); POKE32(PANEL_DISPLAY_CTRL, reg); primaryWaitVerticalSync(delay); @@ -212,16 +144,20 @@ void ddk750_setLogicalDispOut(disp_output_t output) if (output & PNL_2_USAGE) { /* set panel path controller select */ reg = PEEK32(PANEL_DISPLAY_CTRL); - reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, SELECT, (output & PNL_2_MASK)>>PNL_2_OFFSET); + reg &= ~PANEL_DISPLAY_CTRL_SELECT_MASK; + reg |= (((output & PNL_2_MASK) >> PNL_2_OFFSET) << + PANEL_DISPLAY_CTRL_SELECT_SHIFT); POKE32(PANEL_DISPLAY_CTRL, reg); } if (output & CRT_2_USAGE) { /* set crt path controller select */ reg = PEEK32(CRT_DISPLAY_CTRL); - reg = FIELD_VALUE(reg, CRT_DISPLAY_CTRL, SELECT, (output & CRT_2_MASK)>>CRT_2_OFFSET); + reg &= ~CRT_DISPLAY_CTRL_SELECT_MASK; + reg |= (((output & CRT_2_MASK) >> CRT_2_OFFSET) << + CRT_DISPLAY_CTRL_SELECT_SHIFT); /*se blank off */ - reg = FIELD_SET(reg, CRT_DISPLAY_CTRL, BLANK, OFF); + reg &= ~CRT_DISPLAY_CTRL_BLANK; POKE32(CRT_DISPLAY_CTRL, reg); } diff --git a/drivers/staging/sm750fb/ddk750_dvi.c b/drivers/staging/sm750fb/ddk750_dvi.c index a7a23514ac39..a4a255007c8d 100644 --- a/drivers/staging/sm750fb/ddk750_dvi.c +++ b/drivers/staging/sm750fb/ddk750_dvi.c @@ -53,44 +53,6 @@ int dviInit( return -1; /* error */ } - -/* - * dviGetVendorID - * This function gets the vendor ID of the DVI controller chip. - * - * Output: - * Vendor ID - */ -unsigned short dviGetVendorID(void) -{ - dvi_ctrl_device_t *pCurrentDviCtrl; - - pCurrentDviCtrl = g_dcftSupportedDviController; - if (pCurrentDviCtrl != (dvi_ctrl_device_t *)0) - return pCurrentDviCtrl->pfnGetVendorId(); - - return 0x0000; -} - - -/* - * dviGetDeviceID - * This function gets the device ID of the DVI controller chip. - * - * Output: - * Device ID - */ -unsigned short dviGetDeviceID(void) -{ - dvi_ctrl_device_t *pCurrentDviCtrl; - - pCurrentDviCtrl = g_dcftSupportedDviController; - if (pCurrentDviCtrl != (dvi_ctrl_device_t *)0) - return pCurrentDviCtrl->pfnGetDeviceId(); - - return 0x0000; -} - #endif diff --git a/drivers/staging/sm750fb/ddk750_dvi.h b/drivers/staging/sm750fb/ddk750_dvi.h index e1d4c9a2d50a..677939cb5130 100644 --- a/drivers/staging/sm750fb/ddk750_dvi.h +++ b/drivers/staging/sm750fb/ddk750_dvi.h @@ -55,8 +55,5 @@ int dviInit( unsigned char pllFilterValue ); -unsigned short dviGetVendorID(void); -unsigned short dviGetDeviceID(void); - #endif diff --git a/drivers/staging/sm750fb/ddk750_help.h b/drivers/staging/sm750fb/ddk750_help.h index 5be814eed735..009db9213a73 100644 --- a/drivers/staging/sm750fb/ddk750_help.h +++ b/drivers/staging/sm750fb/ddk750_help.h @@ -6,7 +6,6 @@ #include <linux/ioport.h> #include <linux/io.h> #include <linux/uaccess.h> -#include "sm750_help.h" /* software control endianness */ #define PEEK32(addr) readl(addr + mmio750) diff --git a/drivers/staging/sm750fb/ddk750_hwi2c.c b/drivers/staging/sm750fb/ddk750_hwi2c.c index 7be2111284f4..39c3e1cdbc0c 100644 --- a/drivers/staging/sm750fb/ddk750_hwi2c.c +++ b/drivers/staging/sm750fb/ddk750_hwi2c.c @@ -17,8 +17,7 @@ unsigned char bus_speed_mode /* Enable GPIO 30 & 31 as IIC clock & data */ value = PEEK32(GPIO_MUX); - value = FIELD_SET(value, GPIO_MUX, 30, I2C) | - FIELD_SET(0, GPIO_MUX, 31, I2C); + value |= (GPIO_MUX_30 | GPIO_MUX_31); POKE32(GPIO_MUX, value); /* Enable Hardware I2C power. @@ -27,12 +26,10 @@ unsigned char bus_speed_mode enableI2C(1); /* Enable the I2C Controller and set the bus speed mode */ - value = PEEK32(I2C_CTRL); - if (bus_speed_mode == 0) - value = FIELD_SET(value, I2C_CTRL, MODE, STANDARD); - else - value = FIELD_SET(value, I2C_CTRL, MODE, FAST); - value = FIELD_SET(value, I2C_CTRL, EN, ENABLE); + value = PEEK32(I2C_CTRL) & ~(I2C_CTRL_MODE | I2C_CTRL_EN); + if (bus_speed_mode) + value |= I2C_CTRL_MODE; + value |= I2C_CTRL_EN; POKE32(I2C_CTRL, value); return 0; @@ -43,8 +40,7 @@ void sm750_hw_i2c_close(void) unsigned int value; /* Disable I2C controller */ - value = PEEK32(I2C_CTRL); - value = FIELD_SET(value, I2C_CTRL, EN, DISABLE); + value = PEEK32(I2C_CTRL) & ~I2C_CTRL_EN; POKE32(I2C_CTRL, value); /* Disable I2C Power */ @@ -52,8 +48,8 @@ void sm750_hw_i2c_close(void) /* Set GPIO 30 & 31 back as GPIO pins */ value = PEEK32(GPIO_MUX); - value = FIELD_SET(value, GPIO_MUX, 30, GPIO); - value = FIELD_SET(value, GPIO_MUX, 31, GPIO); + value &= ~GPIO_MUX_30; + value &= ~GPIO_MUX_31; POKE32(GPIO_MUX, value); } @@ -63,13 +59,11 @@ static long hw_i2c_wait_tx_done(void) /* Wait until the transfer is completed. */ timeout = HWI2C_WAIT_TIMEOUT; - while ((FIELD_GET(PEEK32(I2C_STATUS), - I2C_STATUS, TX) != I2C_STATUS_TX_COMPLETED) && - (timeout != 0)) + while (!(PEEK32(I2C_STATUS) & I2C_STATUS_TX) && (timeout != 0)) timeout--; if (timeout == 0) - return (-1); + return -1; return 0; } @@ -121,14 +115,13 @@ static unsigned int hw_i2c_write_data( POKE32(I2C_DATA0 + i, *buf++); /* Start the I2C */ - POKE32(I2C_CTRL, - FIELD_SET(PEEK32(I2C_CTRL), I2C_CTRL, CTRL, START)); + POKE32(I2C_CTRL, PEEK32(I2C_CTRL) | I2C_CTRL_CTRL); /* Wait until the transfer is completed. */ if (hw_i2c_wait_tx_done() != 0) break; - /* Substract length */ + /* Subtract length */ length -= (count + 1); /* Total byte written */ @@ -184,8 +177,7 @@ static unsigned int hw_i2c_read_data( POKE32(I2C_BYTE_COUNT, count); /* Start the I2C */ - POKE32(I2C_CTRL, - FIELD_SET(PEEK32(I2C_CTRL), I2C_CTRL, CTRL, START)); + POKE32(I2C_CTRL, PEEK32(I2C_CTRL) | I2C_CTRL_CTRL); /* Wait until transaction done. */ if (hw_i2c_wait_tx_done() != 0) @@ -195,7 +187,7 @@ static unsigned int hw_i2c_read_data( for (i = 0; i <= count; i++) *buf++ = PEEK32(I2C_DATA0 + i); - /* Substract length by 16 */ + /* Subtract length by 16 */ length -= (count + 1); /* Number of bytes read. */ @@ -256,7 +248,7 @@ int sm750_hw_i2c_write_reg( if (hw_i2c_write_data(addr, 2, value) == 2) return 0; - return (-1); + return -1; } #endif diff --git a/drivers/staging/sm750fb/ddk750_mode.c b/drivers/staging/sm750fb/ddk750_mode.c index fa35926680ab..ccb4e067661a 100644 --- a/drivers/staging/sm750fb/ddk750_mode.c +++ b/drivers/staging/sm750fb/ddk750_mode.c @@ -25,13 +25,12 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam, Note that normal SM750/SM718 only use those two register for auto-centering mode. */ - POKE32(CRT_AUTO_CENTERING_TL, - FIELD_VALUE(0, CRT_AUTO_CENTERING_TL, TOP, 0) - | FIELD_VALUE(0, CRT_AUTO_CENTERING_TL, LEFT, 0)); + POKE32(CRT_AUTO_CENTERING_TL, 0); POKE32(CRT_AUTO_CENTERING_BR, - FIELD_VALUE(0, CRT_AUTO_CENTERING_BR, BOTTOM, y-1) - | FIELD_VALUE(0, CRT_AUTO_CENTERING_BR, RIGHT, x-1)); + (((y - 1) << CRT_AUTO_CENTERING_BR_BOTTOM_SHIFT) & + CRT_AUTO_CENTERING_BR_BOTTOM_MASK) | + ((x - 1) & CRT_AUTO_CENTERING_BR_RIGHT_MASK)); /* Assume common fields in dispControl have been properly set before calling this function. @@ -39,33 +38,32 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam, */ /* Clear bit 29:27 of display control register */ - dispControl &= FIELD_CLEAR(CRT_DISPLAY_CTRL, CLK); + dispControl &= ~CRT_DISPLAY_CTRL_CLK_MASK; /* Set bit 29:27 of display control register for the right clock */ - /* Note that SM750LE only need to supported 7 resoluitons. */ + /* Note that SM750LE only need to supported 7 resolutions. */ if (x == 800 && y == 600) - dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL41); + dispControl |= CRT_DISPLAY_CTRL_CLK_PLL41; else if (x == 1024 && y == 768) - dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL65); + dispControl |= CRT_DISPLAY_CTRL_CLK_PLL65; else if (x == 1152 && y == 864) - dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL80); + dispControl |= CRT_DISPLAY_CTRL_CLK_PLL80; else if (x == 1280 && y == 768) - dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL80); + dispControl |= CRT_DISPLAY_CTRL_CLK_PLL80; else if (x == 1280 && y == 720) - dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL74); + dispControl |= CRT_DISPLAY_CTRL_CLK_PLL74; else if (x == 1280 && y == 960) - dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL108); + dispControl |= CRT_DISPLAY_CTRL_CLK_PLL108; else if (x == 1280 && y == 1024) - dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL108); + dispControl |= CRT_DISPLAY_CTRL_CLK_PLL108; else /* default to VGA clock */ - dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL25); + dispControl |= CRT_DISPLAY_CTRL_CLK_PLL25; /* Set bit 25:24 of display controller */ - dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CRTSELECT, CRT); - dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, RGBBIT, 24BIT); + dispControl |= (CRT_DISPLAY_CTRL_CRTSELECT | CRT_DISPLAY_CTRL_RGBBIT); /* Set bit 14 of display controller */ - dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLOCK_PHASE, ACTIVE_LOW); + dispControl = DISPLAY_CTRL_CLOCK_PHASE; POKE32(CRT_DISPLAY_CTRL, dispControl); @@ -79,85 +77,105 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll) { int ret = 0; int cnt = 0; - unsigned int ulTmpValue, ulReg; + unsigned int tmp, reg; if (pll->clockType == SECONDARY_PLL) { /* programe secondary pixel clock */ POKE32(CRT_PLL_CTRL, formatPllReg(pll)); POKE32(CRT_HORIZONTAL_TOTAL, - FIELD_VALUE(0, CRT_HORIZONTAL_TOTAL, TOTAL, pModeParam->horizontal_total - 1) - | FIELD_VALUE(0, CRT_HORIZONTAL_TOTAL, DISPLAY_END, pModeParam->horizontal_display_end - 1)); + (((pModeParam->horizontal_total - 1) << + CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT) & + CRT_HORIZONTAL_TOTAL_TOTAL_MASK) | + ((pModeParam->horizontal_display_end - 1) & + CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK)); POKE32(CRT_HORIZONTAL_SYNC, - FIELD_VALUE(0, CRT_HORIZONTAL_SYNC, WIDTH, pModeParam->horizontal_sync_width) - | FIELD_VALUE(0, CRT_HORIZONTAL_SYNC, START, pModeParam->horizontal_sync_start - 1)); + ((pModeParam->horizontal_sync_width << + CRT_HORIZONTAL_SYNC_WIDTH_SHIFT) & + CRT_HORIZONTAL_SYNC_WIDTH_MASK) | + ((pModeParam->horizontal_sync_start - 1) & + CRT_HORIZONTAL_SYNC_START_MASK)); POKE32(CRT_VERTICAL_TOTAL, - FIELD_VALUE(0, CRT_VERTICAL_TOTAL, TOTAL, pModeParam->vertical_total - 1) - | FIELD_VALUE(0, CRT_VERTICAL_TOTAL, DISPLAY_END, pModeParam->vertical_display_end - 1)); + (((pModeParam->vertical_total - 1) << + CRT_VERTICAL_TOTAL_TOTAL_SHIFT) & + CRT_VERTICAL_TOTAL_TOTAL_MASK) | + ((pModeParam->vertical_display_end - 1) & + CRT_VERTICAL_TOTAL_DISPLAY_END_MASK)); POKE32(CRT_VERTICAL_SYNC, - FIELD_VALUE(0, CRT_VERTICAL_SYNC, HEIGHT, pModeParam->vertical_sync_height) - | FIELD_VALUE(0, CRT_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1)); + ((pModeParam->vertical_sync_height << + CRT_VERTICAL_SYNC_HEIGHT_SHIFT) & + CRT_VERTICAL_SYNC_HEIGHT_MASK) | + ((pModeParam->vertical_sync_start - 1) & + CRT_VERTICAL_SYNC_START_MASK)); - ulTmpValue = FIELD_VALUE(0, CRT_DISPLAY_CTRL, VSYNC_PHASE, pModeParam->vertical_sync_polarity)| - FIELD_VALUE(0, CRT_DISPLAY_CTRL, HSYNC_PHASE, pModeParam->horizontal_sync_polarity)| - FIELD_SET(0, CRT_DISPLAY_CTRL, TIMING, ENABLE)| - FIELD_SET(0, CRT_DISPLAY_CTRL, PLANE, ENABLE); - + tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE; + if (pModeParam->vertical_sync_polarity) + tmp |= DISPLAY_CTRL_VSYNC_PHASE; + if (pModeParam->horizontal_sync_polarity) + tmp |= DISPLAY_CTRL_HSYNC_PHASE; if (getChipType() == SM750LE) { - displayControlAdjust_SM750LE(pModeParam, ulTmpValue); + displayControlAdjust_SM750LE(pModeParam, tmp); } else { - ulReg = PEEK32(CRT_DISPLAY_CTRL) - & FIELD_CLEAR(CRT_DISPLAY_CTRL, VSYNC_PHASE) - & FIELD_CLEAR(CRT_DISPLAY_CTRL, HSYNC_PHASE) - & FIELD_CLEAR(CRT_DISPLAY_CTRL, TIMING) - & FIELD_CLEAR(CRT_DISPLAY_CTRL, PLANE); + reg = PEEK32(CRT_DISPLAY_CTRL) & + ~(DISPLAY_CTRL_VSYNC_PHASE | + DISPLAY_CTRL_HSYNC_PHASE | + DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE); - POKE32(CRT_DISPLAY_CTRL, ulTmpValue|ulReg); + POKE32(CRT_DISPLAY_CTRL, tmp | reg); } } else if (pll->clockType == PRIMARY_PLL) { - unsigned int ulReservedBits; + unsigned int reserved; POKE32(PANEL_PLL_CTRL, formatPllReg(pll)); - POKE32(PANEL_HORIZONTAL_TOTAL, - FIELD_VALUE(0, PANEL_HORIZONTAL_TOTAL, TOTAL, pModeParam->horizontal_total - 1) - | FIELD_VALUE(0, PANEL_HORIZONTAL_TOTAL, DISPLAY_END, pModeParam->horizontal_display_end - 1)); + reg = ((pModeParam->horizontal_total - 1) << + PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT) & + PANEL_HORIZONTAL_TOTAL_TOTAL_MASK; + reg |= ((pModeParam->horizontal_display_end - 1) & + PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK); + POKE32(PANEL_HORIZONTAL_TOTAL, reg); POKE32(PANEL_HORIZONTAL_SYNC, - FIELD_VALUE(0, PANEL_HORIZONTAL_SYNC, WIDTH, pModeParam->horizontal_sync_width) - | FIELD_VALUE(0, PANEL_HORIZONTAL_SYNC, START, pModeParam->horizontal_sync_start - 1)); + ((pModeParam->horizontal_sync_width << + PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT) & + PANEL_HORIZONTAL_SYNC_WIDTH_MASK) | + ((pModeParam->horizontal_sync_start - 1) & + PANEL_HORIZONTAL_SYNC_START_MASK)); POKE32(PANEL_VERTICAL_TOTAL, - FIELD_VALUE(0, PANEL_VERTICAL_TOTAL, TOTAL, pModeParam->vertical_total - 1) - | FIELD_VALUE(0, PANEL_VERTICAL_TOTAL, DISPLAY_END, pModeParam->vertical_display_end - 1)); + (((pModeParam->vertical_total - 1) << + PANEL_VERTICAL_TOTAL_TOTAL_SHIFT) & + PANEL_VERTICAL_TOTAL_TOTAL_MASK) | + ((pModeParam->vertical_display_end - 1) & + PANEL_VERTICAL_TOTAL_DISPLAY_END_MASK)); POKE32(PANEL_VERTICAL_SYNC, - FIELD_VALUE(0, PANEL_VERTICAL_SYNC, HEIGHT, pModeParam->vertical_sync_height) - | FIELD_VALUE(0, PANEL_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1)); - - ulTmpValue = FIELD_VALUE(0, PANEL_DISPLAY_CTRL, VSYNC_PHASE, pModeParam->vertical_sync_polarity)| - FIELD_VALUE(0, PANEL_DISPLAY_CTRL, HSYNC_PHASE, pModeParam->horizontal_sync_polarity)| - FIELD_VALUE(0, PANEL_DISPLAY_CTRL, CLOCK_PHASE, pModeParam->clock_phase_polarity)| - FIELD_SET(0, PANEL_DISPLAY_CTRL, TIMING, ENABLE)| - FIELD_SET(0, PANEL_DISPLAY_CTRL, PLANE, ENABLE); - - ulReservedBits = FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) | - FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) | - FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE)| - FIELD_SET(0, PANEL_DISPLAY_CTRL, VSYNC, ACTIVE_LOW); - - ulReg = (PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) - & FIELD_CLEAR(PANEL_DISPLAY_CTRL, CLOCK_PHASE) - & FIELD_CLEAR(PANEL_DISPLAY_CTRL, VSYNC_PHASE) - & FIELD_CLEAR(PANEL_DISPLAY_CTRL, HSYNC_PHASE) - & FIELD_CLEAR(PANEL_DISPLAY_CTRL, TIMING) - & FIELD_CLEAR(PANEL_DISPLAY_CTRL, PLANE); - + ((pModeParam->vertical_sync_height << + PANEL_VERTICAL_SYNC_HEIGHT_SHIFT) & + PANEL_VERTICAL_SYNC_HEIGHT_MASK) | + ((pModeParam->vertical_sync_start - 1) & + PANEL_VERTICAL_SYNC_START_MASK)); + + tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE; + if (pModeParam->vertical_sync_polarity) + tmp |= DISPLAY_CTRL_VSYNC_PHASE; + if (pModeParam->horizontal_sync_polarity) + tmp |= DISPLAY_CTRL_HSYNC_PHASE; + if (pModeParam->clock_phase_polarity) + tmp |= DISPLAY_CTRL_CLOCK_PHASE; + + reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK | + PANEL_DISPLAY_CTRL_VSYNC; + + reg = (PEEK32(PANEL_DISPLAY_CTRL) & ~reserved) & + ~(DISPLAY_CTRL_CLOCK_PHASE | DISPLAY_CTRL_VSYNC_PHASE | + DISPLAY_CTRL_HSYNC_PHASE | DISPLAY_CTRL_TIMING | + DISPLAY_CTRL_PLANE); /* May a hardware bug or just my test chip (not confirmed). * PANEL_DISPLAY_CTRL register seems requiring few writes @@ -167,13 +185,14 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll) * next vertical sync to turn on/off the plane. */ - POKE32(PANEL_DISPLAY_CTRL, ulTmpValue|ulReg); + POKE32(PANEL_DISPLAY_CTRL, tmp | reg); - while ((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) != (ulTmpValue|ulReg)) { + while ((PEEK32(PANEL_DISPLAY_CTRL) & ~reserved) != + (tmp | reg)) { cnt++; if (cnt > 1000) break; - POKE32(PANEL_DISPLAY_CTRL, ulTmpValue|ulReg); + POKE32(PANEL_DISPLAY_CTRL, tmp | reg); } } else { ret = -1; diff --git a/drivers/staging/sm750fb/ddk750_power.c b/drivers/staging/sm750fb/ddk750_power.c index 667e4f822544..b3c3791b95bd 100644 --- a/drivers/staging/sm750fb/ddk750_power.c +++ b/drivers/staging/sm750fb/ddk750_power.c @@ -7,12 +7,12 @@ void ddk750_setDPMS(DPMS_t state) unsigned int value; if (getChipType() == SM750LE) { - value = PEEK32(CRT_DISPLAY_CTRL); - POKE32(CRT_DISPLAY_CTRL, FIELD_VALUE(value, CRT_DISPLAY_CTRL, - DPMS, state)); + value = PEEK32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_DPMS_MASK; + value |= (state << CRT_DISPLAY_CTRL_DPMS_SHIFT); + POKE32(CRT_DISPLAY_CTRL, value); } else { value = PEEK32(SYSTEM_CTRL); - value = FIELD_VALUE(value, SYSTEM_CTRL, DPMS, state); + value = (value & ~SYSTEM_CTRL_DPMS_MASK) | state; POKE32(SYSTEM_CTRL, value); } } @@ -21,7 +21,7 @@ static unsigned int getPowerMode(void) { if (getChipType() == SM750LE) return 0; - return FIELD_GET(PEEK32(POWER_MODE_CTRL), POWER_MODE_CTRL, MODE); + return PEEK32(POWER_MODE_CTRL) & POWER_MODE_CTRL_MODE_MASK; } @@ -33,25 +33,22 @@ void setPowerMode(unsigned int powerMode) { unsigned int control_value = 0; - control_value = PEEK32(POWER_MODE_CTRL); + control_value = PEEK32(POWER_MODE_CTRL) & ~POWER_MODE_CTRL_MODE_MASK; if (getChipType() == SM750LE) return; switch (powerMode) { case POWER_MODE_CTRL_MODE_MODE0: - control_value = FIELD_SET(control_value, POWER_MODE_CTRL, MODE, - MODE0); + control_value |= POWER_MODE_CTRL_MODE_MODE0; break; case POWER_MODE_CTRL_MODE_MODE1: - control_value = FIELD_SET(control_value, POWER_MODE_CTRL, MODE, - MODE1); + control_value |= POWER_MODE_CTRL_MODE_MODE1; break; case POWER_MODE_CTRL_MODE_SLEEP: - control_value = FIELD_SET(control_value, POWER_MODE_CTRL, MODE, - SLEEP); + control_value |= POWER_MODE_CTRL_MODE_SLEEP; break; default: @@ -60,17 +57,15 @@ void setPowerMode(unsigned int powerMode) /* Set up other fields in Power Control Register */ if (powerMode == POWER_MODE_CTRL_MODE_SLEEP) { - control_value = + control_value &= ~POWER_MODE_CTRL_OSC_INPUT; #ifdef VALIDATION_CHIP - FIELD_SET(control_value, POWER_MODE_CTRL, 336CLK, OFF) | + control_value &= ~POWER_MODE_CTRL_336CLK; #endif - FIELD_SET(control_value, POWER_MODE_CTRL, OSC_INPUT, OFF); } else { - control_value = + control_value |= POWER_MODE_CTRL_OSC_INPUT; #ifdef VALIDATION_CHIP - FIELD_SET(control_value, POWER_MODE_CTRL, 336CLK, ON) | + control_value |= POWER_MODE_CTRL_336CLK; #endif - FIELD_SET(control_value, POWER_MODE_CTRL, OSC_INPUT, ON); } /* Program new power mode. */ @@ -111,13 +106,10 @@ void enable2DEngine(unsigned int enable) u32 gate; gate = PEEK32(CURRENT_GATE); - if (enable) { - gate = FIELD_SET(gate, CURRENT_GATE, DE, ON); - gate = FIELD_SET(gate, CURRENT_GATE, CSC, ON); - } else { - gate = FIELD_SET(gate, CURRENT_GATE, DE, OFF); - gate = FIELD_SET(gate, CURRENT_GATE, CSC, OFF); - } + if (enable) + gate |= (CURRENT_GATE_DE | CURRENT_GATE_CSC); + else + gate &= ~(CURRENT_GATE_DE | CURRENT_GATE_CSC); setCurrentGate(gate); } @@ -129,9 +121,9 @@ void enableDMA(unsigned int enable) /* Enable DMA Gate */ gate = PEEK32(CURRENT_GATE); if (enable) - gate = FIELD_SET(gate, CURRENT_GATE, DMA, ON); + gate |= CURRENT_GATE_DMA; else - gate = FIELD_SET(gate, CURRENT_GATE, DMA, OFF); + gate &= ~CURRENT_GATE_DMA; setCurrentGate(gate); } @@ -146,9 +138,9 @@ void enableGPIO(unsigned int enable) /* Enable GPIO Gate */ gate = PEEK32(CURRENT_GATE); if (enable) - gate = FIELD_SET(gate, CURRENT_GATE, GPIO, ON); + gate |= CURRENT_GATE_GPIO; else - gate = FIELD_SET(gate, CURRENT_GATE, GPIO, OFF); + gate &= ~CURRENT_GATE_GPIO; setCurrentGate(gate); } @@ -163,9 +155,9 @@ void enableI2C(unsigned int enable) /* Enable I2C Gate */ gate = PEEK32(CURRENT_GATE); if (enable) - gate = FIELD_SET(gate, CURRENT_GATE, I2C, ON); + gate |= CURRENT_GATE_I2C; else - gate = FIELD_SET(gate, CURRENT_GATE, I2C, OFF); + gate &= ~CURRENT_GATE_I2C; setCurrentGate(gate); } diff --git a/drivers/staging/sm750fb/ddk750_power.h b/drivers/staging/sm750fb/ddk750_power.h index 6e804d990cff..5963691f9a68 100644 --- a/drivers/staging/sm750fb/ddk750_power.h +++ b/drivers/staging/sm750fb/ddk750_power.h @@ -9,13 +9,10 @@ typedef enum _DPMS_t { } DPMS_t; -#define setDAC(off) \ - { \ - POKE32(MISC_CTRL, FIELD_VALUE(PEEK32(MISC_CTRL), \ - MISC_CTRL, \ - DAC_POWER, \ - off)); \ - } +#define setDAC(off) { \ + POKE32(MISC_CTRL, \ + (PEEK32(MISC_CTRL) & ~MISC_CTRL_DAC_POWER_OFF) | (off)); \ +} void ddk750_setDPMS(DPMS_t); diff --git a/drivers/staging/sm750fb/ddk750_reg.h b/drivers/staging/sm750fb/ddk750_reg.h index 16a01c25442c..955247979aaa 100644 --- a/drivers/staging/sm750fb/ddk750_reg.h +++ b/drivers/staging/sm750fb/ddk750_reg.h @@ -3,1865 +3,1149 @@ /* New register for SM750LE */ #define DE_STATE1 0x100054 -#define DE_STATE1_DE_ABORT 0:0 -#define DE_STATE1_DE_ABORT_OFF 0 -#define DE_STATE1_DE_ABORT_ON 1 +#define DE_STATE1_DE_ABORT BIT(0) #define DE_STATE2 0x100058 -#define DE_STATE2_DE_FIFO 3:3 -#define DE_STATE2_DE_FIFO_NOTEMPTY 0 -#define DE_STATE2_DE_FIFO_EMPTY 1 -#define DE_STATE2_DE_STATUS 2:2 -#define DE_STATE2_DE_STATUS_IDLE 0 -#define DE_STATE2_DE_STATUS_BUSY 1 -#define DE_STATE2_DE_MEM_FIFO 1:1 -#define DE_STATE2_DE_MEM_FIFO_NOTEMPTY 0 -#define DE_STATE2_DE_MEM_FIFO_EMPTY 1 -#define DE_STATE2_DE_RESERVED 0:0 - - +#define DE_STATE2_DE_FIFO_EMPTY BIT(3) +#define DE_STATE2_DE_STATUS_BUSY BIT(2) +#define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1) #define SYSTEM_CTRL 0x000000 -#define SYSTEM_CTRL_DPMS 31:30 -#define SYSTEM_CTRL_DPMS_VPHP 0 -#define SYSTEM_CTRL_DPMS_VPHN 1 -#define SYSTEM_CTRL_DPMS_VNHP 2 -#define SYSTEM_CTRL_DPMS_VNHN 3 -#define SYSTEM_CTRL_PCI_BURST 29:29 -#define SYSTEM_CTRL_PCI_BURST_OFF 0 -#define SYSTEM_CTRL_PCI_BURST_ON 1 -#define SYSTEM_CTRL_PCI_MASTER 25:25 -#define SYSTEM_CTRL_PCI_MASTER_OFF 0 -#define SYSTEM_CTRL_PCI_MASTER_ON 1 -#define SYSTEM_CTRL_LATENCY_TIMER 24:24 -#define SYSTEM_CTRL_LATENCY_TIMER_ON 0 -#define SYSTEM_CTRL_LATENCY_TIMER_OFF 1 -#define SYSTEM_CTRL_DE_FIFO 23:23 -#define SYSTEM_CTRL_DE_FIFO_NOTEMPTY 0 -#define SYSTEM_CTRL_DE_FIFO_EMPTY 1 -#define SYSTEM_CTRL_DE_STATUS 22:22 -#define SYSTEM_CTRL_DE_STATUS_IDLE 0 -#define SYSTEM_CTRL_DE_STATUS_BUSY 1 -#define SYSTEM_CTRL_DE_MEM_FIFO 21:21 -#define SYSTEM_CTRL_DE_MEM_FIFO_NOTEMPTY 0 -#define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY 1 -#define SYSTEM_CTRL_CSC_STATUS 20:20 -#define SYSTEM_CTRL_CSC_STATUS_IDLE 0 -#define SYSTEM_CTRL_CSC_STATUS_BUSY 1 -#define SYSTEM_CTRL_CRT_VSYNC 19:19 -#define SYSTEM_CTRL_CRT_VSYNC_INACTIVE 0 -#define SYSTEM_CTRL_CRT_VSYNC_ACTIVE 1 -#define SYSTEM_CTRL_PANEL_VSYNC 18:18 -#define SYSTEM_CTRL_PANEL_VSYNC_INACTIVE 0 -#define SYSTEM_CTRL_PANEL_VSYNC_ACTIVE 1 -#define SYSTEM_CTRL_CURRENT_BUFFER 17:17 -#define SYSTEM_CTRL_CURRENT_BUFFER_NORMAL 0 -#define SYSTEM_CTRL_CURRENT_BUFFER_FLIP_PENDING 1 -#define SYSTEM_CTRL_DMA_STATUS 16:16 -#define SYSTEM_CTRL_DMA_STATUS_IDLE 0 -#define SYSTEM_CTRL_DMA_STATUS_BUSY 1 -#define SYSTEM_CTRL_PCI_BURST_READ 15:15 -#define SYSTEM_CTRL_PCI_BURST_READ_OFF 0 -#define SYSTEM_CTRL_PCI_BURST_READ_ON 1 -#define SYSTEM_CTRL_DE_ABORT 13:13 -#define SYSTEM_CTRL_DE_ABORT_OFF 0 -#define SYSTEM_CTRL_DE_ABORT_ON 1 -#define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK 11:11 -#define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK_OFF 0 -#define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK_ON 1 -#define SYSTEM_CTRL_PCI_RETRY 7:7 -#define SYSTEM_CTRL_PCI_RETRY_ON 0 -#define SYSTEM_CTRL_PCI_RETRY_OFF 1 -#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE 5:4 -#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_1 0 -#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_2 1 -#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_4 2 -#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_8 3 -#define SYSTEM_CTRL_CRT_TRISTATE 3:3 -#define SYSTEM_CTRL_CRT_TRISTATE_OFF 0 -#define SYSTEM_CTRL_CRT_TRISTATE_ON 1 -#define SYSTEM_CTRL_PCIMEM_TRISTATE 2:2 -#define SYSTEM_CTRL_PCIMEM_TRISTATE_OFF 0 -#define SYSTEM_CTRL_PCIMEM_TRISTATE_ON 1 -#define SYSTEM_CTRL_LOCALMEM_TRISTATE 1:1 -#define SYSTEM_CTRL_LOCALMEM_TRISTATE_OFF 0 -#define SYSTEM_CTRL_LOCALMEM_TRISTATE_ON 1 -#define SYSTEM_CTRL_PANEL_TRISTATE 0:0 -#define SYSTEM_CTRL_PANEL_TRISTATE_OFF 0 -#define SYSTEM_CTRL_PANEL_TRISTATE_ON 1 +#define SYSTEM_CTRL_DPMS_MASK (0x3 << 30) +#define SYSTEM_CTRL_DPMS_VPHP (0x0 << 30) +#define SYSTEM_CTRL_DPMS_VPHN (0x1 << 30) +#define SYSTEM_CTRL_DPMS_VNHP (0x2 << 30) +#define SYSTEM_CTRL_DPMS_VNHN (0x3 << 30) +#define SYSTEM_CTRL_PCI_BURST BIT(29) +#define SYSTEM_CTRL_PCI_MASTER BIT(25) +#define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24) +#define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23) +#define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22) +#define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(21) +#define SYSTEM_CTRL_CSC_STATUS_BUSY BIT(20) +#define SYSTEM_CTRL_CRT_VSYNC_ACTIVE BIT(19) +#define SYSTEM_CTRL_PANEL_VSYNC_ACTIVE BIT(18) +#define SYSTEM_CTRL_CURRENT_BUFFER_FLIP_PENDING BIT(17) +#define SYSTEM_CTRL_DMA_STATUS_BUSY BIT(16) +#define SYSTEM_CTRL_PCI_BURST_READ BIT(15) +#define SYSTEM_CTRL_DE_ABORT BIT(13) +#define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK BIT(11) +#define SYSTEM_CTRL_PCI_RETRY_OFF BIT(7) +#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_MASK (0x3 << 4) +#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_1 (0x0 << 4) +#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_2 (0x1 << 4) +#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_4 (0x2 << 4) +#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_8 (0x3 << 4) +#define SYSTEM_CTRL_CRT_TRISTATE BIT(3) +#define SYSTEM_CTRL_PCIMEM_TRISTATE BIT(2) +#define SYSTEM_CTRL_LOCALMEM_TRISTATE BIT(1) +#define SYSTEM_CTRL_PANEL_TRISTATE BIT(0) #define MISC_CTRL 0x000004 -#define MISC_CTRL_DRAM_RERESH_COUNT 27:27 -#define MISC_CTRL_DRAM_RERESH_COUNT_1ROW 0 -#define MISC_CTRL_DRAM_RERESH_COUNT_3ROW 1 -#define MISC_CTRL_DRAM_REFRESH_TIME 26:25 -#define MISC_CTRL_DRAM_REFRESH_TIME_8 0 -#define MISC_CTRL_DRAM_REFRESH_TIME_16 1 -#define MISC_CTRL_DRAM_REFRESH_TIME_32 2 -#define MISC_CTRL_DRAM_REFRESH_TIME_64 3 -#define MISC_CTRL_INT_OUTPUT 24:24 -#define MISC_CTRL_INT_OUTPUT_NORMAL 0 -#define MISC_CTRL_INT_OUTPUT_INVERT 1 -#define MISC_CTRL_PLL_CLK_COUNT 23:23 -#define MISC_CTRL_PLL_CLK_COUNT_OFF 0 -#define MISC_CTRL_PLL_CLK_COUNT_ON 1 -#define MISC_CTRL_DAC_POWER 20:20 -#define MISC_CTRL_DAC_POWER_ON 0 -#define MISC_CTRL_DAC_POWER_OFF 1 -#define MISC_CTRL_CLK_SELECT 16:16 -#define MISC_CTRL_CLK_SELECT_OSC 0 -#define MISC_CTRL_CLK_SELECT_TESTCLK 1 -#define MISC_CTRL_DRAM_COLUMN_SIZE 15:14 -#define MISC_CTRL_DRAM_COLUMN_SIZE_256 0 -#define MISC_CTRL_DRAM_COLUMN_SIZE_512 1 -#define MISC_CTRL_DRAM_COLUMN_SIZE_1024 2 -#define MISC_CTRL_LOCALMEM_SIZE 13:12 -#define MISC_CTRL_LOCALMEM_SIZE_8M 3 -#define MISC_CTRL_LOCALMEM_SIZE_16M 0 -#define MISC_CTRL_LOCALMEM_SIZE_32M 1 -#define MISC_CTRL_LOCALMEM_SIZE_64M 2 -#define MISC_CTRL_DRAM_TWTR 11:11 -#define MISC_CTRL_DRAM_TWTR_2CLK 0 -#define MISC_CTRL_DRAM_TWTR_1CLK 1 -#define MISC_CTRL_DRAM_TWR 10:10 -#define MISC_CTRL_DRAM_TWR_3CLK 0 -#define MISC_CTRL_DRAM_TWR_2CLK 1 -#define MISC_CTRL_DRAM_TRP 9:9 -#define MISC_CTRL_DRAM_TRP_3CLK 0 -#define MISC_CTRL_DRAM_TRP_4CLK 1 -#define MISC_CTRL_DRAM_TRFC 8:8 -#define MISC_CTRL_DRAM_TRFC_12CLK 0 -#define MISC_CTRL_DRAM_TRFC_14CLK 1 -#define MISC_CTRL_DRAM_TRAS 7:7 -#define MISC_CTRL_DRAM_TRAS_7CLK 0 -#define MISC_CTRL_DRAM_TRAS_8CLK 1 -#define MISC_CTRL_LOCALMEM_RESET 6:6 -#define MISC_CTRL_LOCALMEM_RESET_RESET 0 -#define MISC_CTRL_LOCALMEM_RESET_NORMAL 1 -#define MISC_CTRL_LOCALMEM_STATE 5:5 -#define MISC_CTRL_LOCALMEM_STATE_ACTIVE 0 -#define MISC_CTRL_LOCALMEM_STATE_INACTIVE 1 -#define MISC_CTRL_CPU_CAS_LATENCY 4:4 -#define MISC_CTRL_CPU_CAS_LATENCY_2CLK 0 -#define MISC_CTRL_CPU_CAS_LATENCY_3CLK 1 -#define MISC_CTRL_DLL 3:3 -#define MISC_CTRL_DLL_ON 0 -#define MISC_CTRL_DLL_OFF 1 -#define MISC_CTRL_DRAM_OUTPUT 2:2 -#define MISC_CTRL_DRAM_OUTPUT_LOW 0 -#define MISC_CTRL_DRAM_OUTPUT_HIGH 1 -#define MISC_CTRL_LOCALMEM_BUS_SIZE 1:1 -#define MISC_CTRL_LOCALMEM_BUS_SIZE_32 0 -#define MISC_CTRL_LOCALMEM_BUS_SIZE_64 1 -#define MISC_CTRL_EMBEDDED_LOCALMEM 0:0 -#define MISC_CTRL_EMBEDDED_LOCALMEM_ON 0 -#define MISC_CTRL_EMBEDDED_LOCALMEM_OFF 1 +#define MISC_CTRL_DRAM_RERESH_COUNT BIT(27) +#define MISC_CTRL_DRAM_REFRESH_TIME_MASK (0x3 << 25) +#define MISC_CTRL_DRAM_REFRESH_TIME_8 (0x0 << 25) +#define MISC_CTRL_DRAM_REFRESH_TIME_16 (0x1 << 25) +#define MISC_CTRL_DRAM_REFRESH_TIME_32 (0x2 << 25) +#define MISC_CTRL_DRAM_REFRESH_TIME_64 (0x3 << 25) +#define MISC_CTRL_INT_OUTPUT_INVERT BIT(24) +#define MISC_CTRL_PLL_CLK_COUNT BIT(23) +#define MISC_CTRL_DAC_POWER_OFF BIT(20) +#define MISC_CTRL_CLK_SELECT_TESTCLK BIT(16) +#define MISC_CTRL_DRAM_COLUMN_SIZE_MASK (0x3 << 14) +#define MISC_CTRL_DRAM_COLUMN_SIZE_256 (0x0 << 14) +#define MISC_CTRL_DRAM_COLUMN_SIZE_512 (0x1 << 14) +#define MISC_CTRL_DRAM_COLUMN_SIZE_1024 (0x2 << 14) +#define MISC_CTRL_LOCALMEM_SIZE_MASK (0x3 << 12) +#define MISC_CTRL_LOCALMEM_SIZE_8M (0x3 << 12) +#define MISC_CTRL_LOCALMEM_SIZE_16M (0x0 << 12) +#define MISC_CTRL_LOCALMEM_SIZE_32M (0x1 << 12) +#define MISC_CTRL_LOCALMEM_SIZE_64M (0x2 << 12) +#define MISC_CTRL_DRAM_TWTR BIT(11) +#define MISC_CTRL_DRAM_TWR BIT(10) +#define MISC_CTRL_DRAM_TRP BIT(9) +#define MISC_CTRL_DRAM_TRFC BIT(8) +#define MISC_CTRL_DRAM_TRAS BIT(7) +#define MISC_CTRL_LOCALMEM_RESET BIT(6) +#define MISC_CTRL_LOCALMEM_STATE_INACTIVE BIT(5) +#define MISC_CTRL_CPU_CAS_LATENCY BIT(4) +#define MISC_CTRL_DLL_OFF BIT(3) +#define MISC_CTRL_DRAM_OUTPUT_HIGH BIT(2) +#define MISC_CTRL_LOCALMEM_BUS_SIZE BIT(1) +#define MISC_CTRL_EMBEDDED_LOCALMEM_OFF BIT(0) #define GPIO_MUX 0x000008 -#define GPIO_MUX_31 31:31 -#define GPIO_MUX_31_GPIO 0 -#define GPIO_MUX_31_I2C 1 -#define GPIO_MUX_30 30:30 -#define GPIO_MUX_30_GPIO 0 -#define GPIO_MUX_30_I2C 1 -#define GPIO_MUX_29 29:29 -#define GPIO_MUX_29_GPIO 0 -#define GPIO_MUX_29_SSP1 1 -#define GPIO_MUX_28 28:28 -#define GPIO_MUX_28_GPIO 0 -#define GPIO_MUX_28_SSP1 1 -#define GPIO_MUX_27 27:27 -#define GPIO_MUX_27_GPIO 0 -#define GPIO_MUX_27_SSP1 1 -#define GPIO_MUX_26 26:26 -#define GPIO_MUX_26_GPIO 0 -#define GPIO_MUX_26_SSP1 1 -#define GPIO_MUX_25 25:25 -#define GPIO_MUX_25_GPIO 0 -#define GPIO_MUX_25_SSP1 1 -#define GPIO_MUX_24 24:24 -#define GPIO_MUX_24_GPIO 0 -#define GPIO_MUX_24_SSP0 1 -#define GPIO_MUX_23 23:23 -#define GPIO_MUX_23_GPIO 0 -#define GPIO_MUX_23_SSP0 1 -#define GPIO_MUX_22 22:22 -#define GPIO_MUX_22_GPIO 0 -#define GPIO_MUX_22_SSP0 1 -#define GPIO_MUX_21 21:21 -#define GPIO_MUX_21_GPIO 0 -#define GPIO_MUX_21_SSP0 1 -#define GPIO_MUX_20 20:20 -#define GPIO_MUX_20_GPIO 0 -#define GPIO_MUX_20_SSP0 1 -#define GPIO_MUX_19 19:19 -#define GPIO_MUX_19_GPIO 0 -#define GPIO_MUX_19_PWM 1 -#define GPIO_MUX_18 18:18 -#define GPIO_MUX_18_GPIO 0 -#define GPIO_MUX_18_PWM 1 -#define GPIO_MUX_17 17:17 -#define GPIO_MUX_17_GPIO 0 -#define GPIO_MUX_17_PWM 1 -#define GPIO_MUX_16 16:16 -#define GPIO_MUX_16_GPIO_ZVPORT 0 -#define GPIO_MUX_16_TEST_DATA 1 -#define GPIO_MUX_15 15:15 -#define GPIO_MUX_15_GPIO_ZVPORT 0 -#define GPIO_MUX_15_TEST_DATA 1 -#define GPIO_MUX_14 14:14 -#define GPIO_MUX_14_GPIO_ZVPORT 0 -#define GPIO_MUX_14_TEST_DATA 1 -#define GPIO_MUX_13 13:13 -#define GPIO_MUX_13_GPIO_ZVPORT 0 -#define GPIO_MUX_13_TEST_DATA 1 -#define GPIO_MUX_12 12:12 -#define GPIO_MUX_12_GPIO_ZVPORT 0 -#define GPIO_MUX_12_TEST_DATA 1 -#define GPIO_MUX_11 11:11 -#define GPIO_MUX_11_GPIO_ZVPORT 0 -#define GPIO_MUX_11_TEST_DATA 1 -#define GPIO_MUX_10 10:10 -#define GPIO_MUX_10_GPIO_ZVPORT 0 -#define GPIO_MUX_10_TEST_DATA 1 -#define GPIO_MUX_9 9:9 -#define GPIO_MUX_9_GPIO_ZVPORT 0 -#define GPIO_MUX_9_TEST_DATA 1 -#define GPIO_MUX_8 8:8 -#define GPIO_MUX_8_GPIO_ZVPORT 0 -#define GPIO_MUX_8_TEST_DATA 1 -#define GPIO_MUX_7 7:7 -#define GPIO_MUX_7_GPIO_ZVPORT 0 -#define GPIO_MUX_7_TEST_DATA 1 -#define GPIO_MUX_6 6:6 -#define GPIO_MUX_6_GPIO_ZVPORT 0 -#define GPIO_MUX_6_TEST_DATA 1 -#define GPIO_MUX_5 5:5 -#define GPIO_MUX_5_GPIO_ZVPORT 0 -#define GPIO_MUX_5_TEST_DATA 1 -#define GPIO_MUX_4 4:4 -#define GPIO_MUX_4_GPIO_ZVPORT 0 -#define GPIO_MUX_4_TEST_DATA 1 -#define GPIO_MUX_3 3:3 -#define GPIO_MUX_3_GPIO_ZVPORT 0 -#define GPIO_MUX_3_TEST_DATA 1 -#define GPIO_MUX_2 2:2 -#define GPIO_MUX_2_GPIO_ZVPORT 0 -#define GPIO_MUX_2_TEST_DATA 1 -#define GPIO_MUX_1 1:1 -#define GPIO_MUX_1_GPIO_ZVPORT 0 -#define GPIO_MUX_1_TEST_DATA 1 -#define GPIO_MUX_0 0:0 -#define GPIO_MUX_0_GPIO_ZVPORT 0 -#define GPIO_MUX_0_TEST_DATA 1 +#define GPIO_MUX_31 BIT(31) +#define GPIO_MUX_30 BIT(30) +#define GPIO_MUX_29 BIT(29) +#define GPIO_MUX_28 BIT(28) +#define GPIO_MUX_27 BIT(27) +#define GPIO_MUX_26 BIT(26) +#define GPIO_MUX_25 BIT(25) +#define GPIO_MUX_24 BIT(24) +#define GPIO_MUX_23 BIT(23) +#define GPIO_MUX_22 BIT(22) +#define GPIO_MUX_21 BIT(21) +#define GPIO_MUX_20 BIT(20) +#define GPIO_MUX_19 BIT(19) +#define GPIO_MUX_18 BIT(18) +#define GPIO_MUX_17 BIT(17) +#define GPIO_MUX_16 BIT(16) +#define GPIO_MUX_15 BIT(15) +#define GPIO_MUX_14 BIT(14) +#define GPIO_MUX_13 BIT(13) +#define GPIO_MUX_12 BIT(12) +#define GPIO_MUX_11 BIT(11) +#define GPIO_MUX_10 BIT(10) +#define GPIO_MUX_9 BIT(9) +#define GPIO_MUX_8 BIT(8) +#define GPIO_MUX_7 BIT(7) +#define GPIO_MUX_6 BIT(6) +#define GPIO_MUX_5 BIT(5) +#define GPIO_MUX_4 BIT(4) +#define GPIO_MUX_3 BIT(3) +#define GPIO_MUX_2 BIT(2) +#define GPIO_MUX_1 BIT(1) +#define GPIO_MUX_0 BIT(0) #define LOCALMEM_ARBITRATION 0x00000C -#define LOCALMEM_ARBITRATION_ROTATE 28:28 -#define LOCALMEM_ARBITRATION_ROTATE_OFF 0 -#define LOCALMEM_ARBITRATION_ROTATE_ON 1 -#define LOCALMEM_ARBITRATION_VGA 26:24 -#define LOCALMEM_ARBITRATION_VGA_OFF 0 -#define LOCALMEM_ARBITRATION_VGA_PRIORITY_1 1 -#define LOCALMEM_ARBITRATION_VGA_PRIORITY_2 2 -#define LOCALMEM_ARBITRATION_VGA_PRIORITY_3 3 -#define LOCALMEM_ARBITRATION_VGA_PRIORITY_4 4 -#define LOCALMEM_ARBITRATION_VGA_PRIORITY_5 5 -#define LOCALMEM_ARBITRATION_VGA_PRIORITY_6 6 -#define LOCALMEM_ARBITRATION_VGA_PRIORITY_7 7 -#define LOCALMEM_ARBITRATION_DMA 22:20 -#define LOCALMEM_ARBITRATION_DMA_OFF 0 -#define LOCALMEM_ARBITRATION_DMA_PRIORITY_1 1 -#define LOCALMEM_ARBITRATION_DMA_PRIORITY_2 2 -#define LOCALMEM_ARBITRATION_DMA_PRIORITY_3 3 -#define LOCALMEM_ARBITRATION_DMA_PRIORITY_4 4 -#define LOCALMEM_ARBITRATION_DMA_PRIORITY_5 5 -#define LOCALMEM_ARBITRATION_DMA_PRIORITY_6 6 -#define LOCALMEM_ARBITRATION_DMA_PRIORITY_7 7 -#define LOCALMEM_ARBITRATION_ZVPORT1 18:16 -#define LOCALMEM_ARBITRATION_ZVPORT1_OFF 0 -#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_1 1 -#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_2 2 -#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_3 3 -#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_4 4 -#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_5 5 -#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_6 6 -#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_7 7 -#define LOCALMEM_ARBITRATION_ZVPORT0 14:12 -#define LOCALMEM_ARBITRATION_ZVPORT0_OFF 0 -#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_1 1 -#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_2 2 -#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_3 3 -#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_4 4 -#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_5 5 -#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_6 6 -#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_7 7 -#define LOCALMEM_ARBITRATION_VIDEO 10:8 -#define LOCALMEM_ARBITRATION_VIDEO_OFF 0 -#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_1 1 -#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_2 2 -#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_3 3 -#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_4 4 -#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_5 5 -#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_6 6 -#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_7 7 -#define LOCALMEM_ARBITRATION_PANEL 6:4 -#define LOCALMEM_ARBITRATION_PANEL_OFF 0 -#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_1 1 -#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_2 2 -#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_3 3 -#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_4 4 -#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_5 5 -#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_6 6 -#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_7 7 -#define LOCALMEM_ARBITRATION_CRT 2:0 -#define LOCALMEM_ARBITRATION_CRT_OFF 0 -#define LOCALMEM_ARBITRATION_CRT_PRIORITY_1 1 -#define LOCALMEM_ARBITRATION_CRT_PRIORITY_2 2 -#define LOCALMEM_ARBITRATION_CRT_PRIORITY_3 3 -#define LOCALMEM_ARBITRATION_CRT_PRIORITY_4 4 -#define LOCALMEM_ARBITRATION_CRT_PRIORITY_5 5 -#define LOCALMEM_ARBITRATION_CRT_PRIORITY_6 6 -#define LOCALMEM_ARBITRATION_CRT_PRIORITY_7 7 +#define LOCALMEM_ARBITRATION_ROTATE BIT(28) +#define LOCALMEM_ARBITRATION_VGA_MASK (0x7 << 24) +#define LOCALMEM_ARBITRATION_VGA_OFF (0x0 << 24) +#define LOCALMEM_ARBITRATION_VGA_PRIORITY_1 (0x1 << 24) +#define LOCALMEM_ARBITRATION_VGA_PRIORITY_2 (0x2 << 24) +#define LOCALMEM_ARBITRATION_VGA_PRIORITY_3 (0x3 << 24) +#define LOCALMEM_ARBITRATION_VGA_PRIORITY_4 (0x4 << 24) +#define LOCALMEM_ARBITRATION_VGA_PRIORITY_5 (0x5 << 24) +#define LOCALMEM_ARBITRATION_VGA_PRIORITY_6 (0x6 << 24) +#define LOCALMEM_ARBITRATION_VGA_PRIORITY_7 (0x7 << 24) +#define LOCALMEM_ARBITRATION_DMA_MASK (0x7 << 20) +#define LOCALMEM_ARBITRATION_DMA_OFF (0x0 << 20) +#define LOCALMEM_ARBITRATION_DMA_PRIORITY_1 (0x1 << 20) +#define LOCALMEM_ARBITRATION_DMA_PRIORITY_2 (0x2 << 20) +#define LOCALMEM_ARBITRATION_DMA_PRIORITY_3 (0x3 << 20) +#define LOCALMEM_ARBITRATION_DMA_PRIORITY_4 (0x4 << 20) +#define LOCALMEM_ARBITRATION_DMA_PRIORITY_5 (0x5 << 20) +#define LOCALMEM_ARBITRATION_DMA_PRIORITY_6 (0x6 << 20) +#define LOCALMEM_ARBITRATION_DMA_PRIORITY_7 (0x7 << 20) +#define LOCALMEM_ARBITRATION_ZVPORT1_MASK (0x7 << 16) +#define LOCALMEM_ARBITRATION_ZVPORT1_OFF (0x0 << 16) +#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_1 (0x1 << 16) +#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_2 (0x2 << 16) +#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_3 (0x3 << 16) +#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_4 (0x4 << 16) +#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_5 (0x5 << 16) +#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_6 (0x6 << 16) +#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_7 (0x7 << 16) +#define LOCALMEM_ARBITRATION_ZVPORT0_MASK (0x7 << 12) +#define LOCALMEM_ARBITRATION_ZVPORT0_OFF (0x0 << 12) +#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_1 (0x1 << 12) +#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_2 (0x2 << 12) +#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_3 (0x3 << 12) +#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_4 (0x4 << 12) +#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_5 (0x5 << 12) +#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_6 (0x6 << 12) +#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_7 (0x7 << 12) +#define LOCALMEM_ARBITRATION_VIDEO_MASK (0x7 << 8) +#define LOCALMEM_ARBITRATION_VIDEO_OFF (0x0 << 8) +#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_1 (0x1 << 8) +#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_2 (0x2 << 8) +#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_3 (0x3 << 8) +#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_4 (0x4 << 8) +#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_5 (0x5 << 8) +#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_6 (0x6 << 8) +#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_7 (0x7 << 8) +#define LOCALMEM_ARBITRATION_PANEL_MASK (0x7 << 4) +#define LOCALMEM_ARBITRATION_PANEL_OFF (0x0 << 4) +#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_1 (0x1 << 4) +#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_2 (0x2 << 4) +#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_3 (0x3 << 4) +#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_4 (0x4 << 4) +#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_5 (0x5 << 4) +#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_6 (0x6 << 4) +#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_7 (0x7 << 4) +#define LOCALMEM_ARBITRATION_CRT_MASK 0x7 +#define LOCALMEM_ARBITRATION_CRT_OFF 0x0 +#define LOCALMEM_ARBITRATION_CRT_PRIORITY_1 0x1 +#define LOCALMEM_ARBITRATION_CRT_PRIORITY_2 0x2 +#define LOCALMEM_ARBITRATION_CRT_PRIORITY_3 0x3 +#define LOCALMEM_ARBITRATION_CRT_PRIORITY_4 0x4 +#define LOCALMEM_ARBITRATION_CRT_PRIORITY_5 0x5 +#define LOCALMEM_ARBITRATION_CRT_PRIORITY_6 0x6 +#define LOCALMEM_ARBITRATION_CRT_PRIORITY_7 0x7 #define PCIMEM_ARBITRATION 0x000010 -#define PCIMEM_ARBITRATION_ROTATE 28:28 -#define PCIMEM_ARBITRATION_ROTATE_OFF 0 -#define PCIMEM_ARBITRATION_ROTATE_ON 1 -#define PCIMEM_ARBITRATION_VGA 26:24 -#define PCIMEM_ARBITRATION_VGA_OFF 0 -#define PCIMEM_ARBITRATION_VGA_PRIORITY_1 1 -#define PCIMEM_ARBITRATION_VGA_PRIORITY_2 2 -#define PCIMEM_ARBITRATION_VGA_PRIORITY_3 3 -#define PCIMEM_ARBITRATION_VGA_PRIORITY_4 4 -#define PCIMEM_ARBITRATION_VGA_PRIORITY_5 5 -#define PCIMEM_ARBITRATION_VGA_PRIORITY_6 6 -#define PCIMEM_ARBITRATION_VGA_PRIORITY_7 7 -#define PCIMEM_ARBITRATION_DMA 22:20 -#define PCIMEM_ARBITRATION_DMA_OFF 0 -#define PCIMEM_ARBITRATION_DMA_PRIORITY_1 1 -#define PCIMEM_ARBITRATION_DMA_PRIORITY_2 2 -#define PCIMEM_ARBITRATION_DMA_PRIORITY_3 3 -#define PCIMEM_ARBITRATION_DMA_PRIORITY_4 4 -#define PCIMEM_ARBITRATION_DMA_PRIORITY_5 5 -#define PCIMEM_ARBITRATION_DMA_PRIORITY_6 6 -#define PCIMEM_ARBITRATION_DMA_PRIORITY_7 7 -#define PCIMEM_ARBITRATION_ZVPORT1 18:16 -#define PCIMEM_ARBITRATION_ZVPORT1_OFF 0 -#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_1 1 -#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_2 2 -#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_3 3 -#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_4 4 -#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_5 5 -#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_6 6 -#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_7 7 -#define PCIMEM_ARBITRATION_ZVPORT0 14:12 -#define PCIMEM_ARBITRATION_ZVPORT0_OFF 0 -#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_1 1 -#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_2 2 -#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_3 3 -#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_4 4 -#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_5 5 -#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_6 6 -#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_7 7 -#define PCIMEM_ARBITRATION_VIDEO 10:8 -#define PCIMEM_ARBITRATION_VIDEO_OFF 0 -#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_1 1 -#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_2 2 -#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_3 3 -#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_4 4 -#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_5 5 -#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_6 6 -#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_7 7 -#define PCIMEM_ARBITRATION_PANEL 6:4 -#define PCIMEM_ARBITRATION_PANEL_OFF 0 -#define PCIMEM_ARBITRATION_PANEL_PRIORITY_1 1 -#define PCIMEM_ARBITRATION_PANEL_PRIORITY_2 2 -#define PCIMEM_ARBITRATION_PANEL_PRIORITY_3 3 -#define PCIMEM_ARBITRATION_PANEL_PRIORITY_4 4 -#define PCIMEM_ARBITRATION_PANEL_PRIORITY_5 5 -#define PCIMEM_ARBITRATION_PANEL_PRIORITY_6 6 -#define PCIMEM_ARBITRATION_PANEL_PRIORITY_7 7 -#define PCIMEM_ARBITRATION_CRT 2:0 -#define PCIMEM_ARBITRATION_CRT_OFF 0 -#define PCIMEM_ARBITRATION_CRT_PRIORITY_1 1 -#define PCIMEM_ARBITRATION_CRT_PRIORITY_2 2 -#define PCIMEM_ARBITRATION_CRT_PRIORITY_3 3 -#define PCIMEM_ARBITRATION_CRT_PRIORITY_4 4 -#define PCIMEM_ARBITRATION_CRT_PRIORITY_5 5 -#define PCIMEM_ARBITRATION_CRT_PRIORITY_6 6 -#define PCIMEM_ARBITRATION_CRT_PRIORITY_7 7 +#define PCIMEM_ARBITRATION_ROTATE BIT(28) +#define PCIMEM_ARBITRATION_VGA_MASK (0x7 << 24) +#define PCIMEM_ARBITRATION_VGA_OFF (0x0 << 24) +#define PCIMEM_ARBITRATION_VGA_PRIORITY_1 (0x1 << 24) +#define PCIMEM_ARBITRATION_VGA_PRIORITY_2 (0x2 << 24) +#define PCIMEM_ARBITRATION_VGA_PRIORITY_3 (0x3 << 24) +#define PCIMEM_ARBITRATION_VGA_PRIORITY_4 (0x4 << 24) +#define PCIMEM_ARBITRATION_VGA_PRIORITY_5 (0x5 << 24) +#define PCIMEM_ARBITRATION_VGA_PRIORITY_6 (0x6 << 24) +#define PCIMEM_ARBITRATION_VGA_PRIORITY_7 (0x7 << 24) +#define PCIMEM_ARBITRATION_DMA_MASK (0x7 << 20) +#define PCIMEM_ARBITRATION_DMA_OFF (0x0 << 20) +#define PCIMEM_ARBITRATION_DMA_PRIORITY_1 (0x1 << 20) +#define PCIMEM_ARBITRATION_DMA_PRIORITY_2 (0x2 << 20) +#define PCIMEM_ARBITRATION_DMA_PRIORITY_3 (0x3 << 20) +#define PCIMEM_ARBITRATION_DMA_PRIORITY_4 (0x4 << 20) +#define PCIMEM_ARBITRATION_DMA_PRIORITY_5 (0x5 << 20) +#define PCIMEM_ARBITRATION_DMA_PRIORITY_6 (0x6 << 20) +#define PCIMEM_ARBITRATION_DMA_PRIORITY_7 (0x7 << 20) +#define PCIMEM_ARBITRATION_ZVPORT1_MASK (0x7 << 16) +#define PCIMEM_ARBITRATION_ZVPORT1_OFF (0x0 << 16) +#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_1 (0x1 << 16) +#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_2 (0x2 << 16) +#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_3 (0x3 << 16) +#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_4 (0x4 << 16) +#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_5 (0x5 << 16) +#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_6 (0x6 << 16) +#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_7 (0x7 << 16) +#define PCIMEM_ARBITRATION_ZVPORT0_MASK (0x7 << 12) +#define PCIMEM_ARBITRATION_ZVPORT0_OFF (0x0 << 12) +#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_1 (0x1 << 12) +#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_2 (0x2 << 12) +#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_3 (0x3 << 12) +#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_4 (0x4 << 12) +#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_5 (0x5 << 12) +#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_6 (0x6 << 12) +#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_7 (0x7 << 12) +#define PCIMEM_ARBITRATION_VIDEO_MASK (0x7 << 8) +#define PCIMEM_ARBITRATION_VIDEO_OFF (0x0 << 8) +#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_1 (0x1 << 8) +#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_2 (0x2 << 8) +#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_3 (0x3 << 8) +#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_4 (0x4 << 8) +#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_5 (0x5 << 8) +#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_6 (0x6 << 8) +#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_7 (0x7 << 8) +#define PCIMEM_ARBITRATION_PANEL_MASK (0x7 << 4) +#define PCIMEM_ARBITRATION_PANEL_OFF (0x0 << 4) +#define PCIMEM_ARBITRATION_PANEL_PRIORITY_1 (0x1 << 4) +#define PCIMEM_ARBITRATION_PANEL_PRIORITY_2 (0x2 << 4) +#define PCIMEM_ARBITRATION_PANEL_PRIORITY_3 (0x3 << 4) +#define PCIMEM_ARBITRATION_PANEL_PRIORITY_4 (0x4 << 4) +#define PCIMEM_ARBITRATION_PANEL_PRIORITY_5 (0x5 << 4) +#define PCIMEM_ARBITRATION_PANEL_PRIORITY_6 (0x6 << 4) +#define PCIMEM_ARBITRATION_PANEL_PRIORITY_7 (0x7 << 4) +#define PCIMEM_ARBITRATION_CRT_MASK 0x7 +#define PCIMEM_ARBITRATION_CRT_OFF 0x0 +#define PCIMEM_ARBITRATION_CRT_PRIORITY_1 0x1 +#define PCIMEM_ARBITRATION_CRT_PRIORITY_2 0x2 +#define PCIMEM_ARBITRATION_CRT_PRIORITY_3 0x3 +#define PCIMEM_ARBITRATION_CRT_PRIORITY_4 0x4 +#define PCIMEM_ARBITRATION_CRT_PRIORITY_5 0x5 +#define PCIMEM_ARBITRATION_CRT_PRIORITY_6 0x6 +#define PCIMEM_ARBITRATION_CRT_PRIORITY_7 0x7 #define RAW_INT 0x000020 -#define RAW_INT_ZVPORT1_VSYNC 4:4 -#define RAW_INT_ZVPORT1_VSYNC_INACTIVE 0 -#define RAW_INT_ZVPORT1_VSYNC_ACTIVE 1 -#define RAW_INT_ZVPORT1_VSYNC_CLEAR 1 -#define RAW_INT_ZVPORT0_VSYNC 3:3 -#define RAW_INT_ZVPORT0_VSYNC_INACTIVE 0 -#define RAW_INT_ZVPORT0_VSYNC_ACTIVE 1 -#define RAW_INT_ZVPORT0_VSYNC_CLEAR 1 -#define RAW_INT_CRT_VSYNC 2:2 -#define RAW_INT_CRT_VSYNC_INACTIVE 0 -#define RAW_INT_CRT_VSYNC_ACTIVE 1 -#define RAW_INT_CRT_VSYNC_CLEAR 1 -#define RAW_INT_PANEL_VSYNC 1:1 -#define RAW_INT_PANEL_VSYNC_INACTIVE 0 -#define RAW_INT_PANEL_VSYNC_ACTIVE 1 -#define RAW_INT_PANEL_VSYNC_CLEAR 1 -#define RAW_INT_VGA_VSYNC 0:0 -#define RAW_INT_VGA_VSYNC_INACTIVE 0 -#define RAW_INT_VGA_VSYNC_ACTIVE 1 -#define RAW_INT_VGA_VSYNC_CLEAR 1 +#define RAW_INT_ZVPORT1_VSYNC BIT(4) +#define RAW_INT_ZVPORT0_VSYNC BIT(3) +#define RAW_INT_CRT_VSYNC BIT(2) +#define RAW_INT_PANEL_VSYNC BIT(1) +#define RAW_INT_VGA_VSYNC BIT(0) #define INT_STATUS 0x000024 -#define INT_STATUS_GPIO31 31:31 -#define INT_STATUS_GPIO31_INACTIVE 0 -#define INT_STATUS_GPIO31_ACTIVE 1 -#define INT_STATUS_GPIO30 30:30 -#define INT_STATUS_GPIO30_INACTIVE 0 -#define INT_STATUS_GPIO30_ACTIVE 1 -#define INT_STATUS_GPIO29 29:29 -#define INT_STATUS_GPIO29_INACTIVE 0 -#define INT_STATUS_GPIO29_ACTIVE 1 -#define INT_STATUS_GPIO28 28:28 -#define INT_STATUS_GPIO28_INACTIVE 0 -#define INT_STATUS_GPIO28_ACTIVE 1 -#define INT_STATUS_GPIO27 27:27 -#define INT_STATUS_GPIO27_INACTIVE 0 -#define INT_STATUS_GPIO27_ACTIVE 1 -#define INT_STATUS_GPIO26 26:26 -#define INT_STATUS_GPIO26_INACTIVE 0 -#define INT_STATUS_GPIO26_ACTIVE 1 -#define INT_STATUS_GPIO25 25:25 -#define INT_STATUS_GPIO25_INACTIVE 0 -#define INT_STATUS_GPIO25_ACTIVE 1 -#define INT_STATUS_I2C 12:12 -#define INT_STATUS_I2C_INACTIVE 0 -#define INT_STATUS_I2C_ACTIVE 1 -#define INT_STATUS_PWM 11:11 -#define INT_STATUS_PWM_INACTIVE 0 -#define INT_STATUS_PWM_ACTIVE 1 -#define INT_STATUS_DMA1 10:10 -#define INT_STATUS_DMA1_INACTIVE 0 -#define INT_STATUS_DMA1_ACTIVE 1 -#define INT_STATUS_DMA0 9:9 -#define INT_STATUS_DMA0_INACTIVE 0 -#define INT_STATUS_DMA0_ACTIVE 1 -#define INT_STATUS_PCI 8:8 -#define INT_STATUS_PCI_INACTIVE 0 -#define INT_STATUS_PCI_ACTIVE 1 -#define INT_STATUS_SSP1 7:7 -#define INT_STATUS_SSP1_INACTIVE 0 -#define INT_STATUS_SSP1_ACTIVE 1 -#define INT_STATUS_SSP0 6:6 -#define INT_STATUS_SSP0_INACTIVE 0 -#define INT_STATUS_SSP0_ACTIVE 1 -#define INT_STATUS_DE 5:5 -#define INT_STATUS_DE_INACTIVE 0 -#define INT_STATUS_DE_ACTIVE 1 -#define INT_STATUS_ZVPORT1_VSYNC 4:4 -#define INT_STATUS_ZVPORT1_VSYNC_INACTIVE 0 -#define INT_STATUS_ZVPORT1_VSYNC_ACTIVE 1 -#define INT_STATUS_ZVPORT0_VSYNC 3:3 -#define INT_STATUS_ZVPORT0_VSYNC_INACTIVE 0 -#define INT_STATUS_ZVPORT0_VSYNC_ACTIVE 1 -#define INT_STATUS_CRT_VSYNC 2:2 -#define INT_STATUS_CRT_VSYNC_INACTIVE 0 -#define INT_STATUS_CRT_VSYNC_ACTIVE 1 -#define INT_STATUS_PANEL_VSYNC 1:1 -#define INT_STATUS_PANEL_VSYNC_INACTIVE 0 -#define INT_STATUS_PANEL_VSYNC_ACTIVE 1 -#define INT_STATUS_VGA_VSYNC 0:0 -#define INT_STATUS_VGA_VSYNC_INACTIVE 0 -#define INT_STATUS_VGA_VSYNC_ACTIVE 1 +#define INT_STATUS_GPIO31 BIT(31) +#define INT_STATUS_GPIO30 BIT(30) +#define INT_STATUS_GPIO29 BIT(29) +#define INT_STATUS_GPIO28 BIT(28) +#define INT_STATUS_GPIO27 BIT(27) +#define INT_STATUS_GPIO26 BIT(26) +#define INT_STATUS_GPIO25 BIT(25) +#define INT_STATUS_I2C BIT(12) +#define INT_STATUS_PWM BIT(11) +#define INT_STATUS_DMA1 BIT(10) +#define INT_STATUS_DMA0 BIT(9) +#define INT_STATUS_PCI BIT(8) +#define INT_STATUS_SSP1 BIT(7) +#define INT_STATUS_SSP0 BIT(6) +#define INT_STATUS_DE BIT(5) +#define INT_STATUS_ZVPORT1_VSYNC BIT(4) +#define INT_STATUS_ZVPORT0_VSYNC BIT(3) +#define INT_STATUS_CRT_VSYNC BIT(2) +#define INT_STATUS_PANEL_VSYNC BIT(1) +#define INT_STATUS_VGA_VSYNC BIT(0) #define INT_MASK 0x000028 -#define INT_MASK_GPIO31 31:31 -#define INT_MASK_GPIO31_DISABLE 0 -#define INT_MASK_GPIO31_ENABLE 1 -#define INT_MASK_GPIO30 30:30 -#define INT_MASK_GPIO30_DISABLE 0 -#define INT_MASK_GPIO30_ENABLE 1 -#define INT_MASK_GPIO29 29:29 -#define INT_MASK_GPIO29_DISABLE 0 -#define INT_MASK_GPIO29_ENABLE 1 -#define INT_MASK_GPIO28 28:28 -#define INT_MASK_GPIO28_DISABLE 0 -#define INT_MASK_GPIO28_ENABLE 1 -#define INT_MASK_GPIO27 27:27 -#define INT_MASK_GPIO27_DISABLE 0 -#define INT_MASK_GPIO27_ENABLE 1 -#define INT_MASK_GPIO26 26:26 -#define INT_MASK_GPIO26_DISABLE 0 -#define INT_MASK_GPIO26_ENABLE 1 -#define INT_MASK_GPIO25 25:25 -#define INT_MASK_GPIO25_DISABLE 0 -#define INT_MASK_GPIO25_ENABLE 1 -#define INT_MASK_I2C 12:12 -#define INT_MASK_I2C_DISABLE 0 -#define INT_MASK_I2C_ENABLE 1 -#define INT_MASK_PWM 11:11 -#define INT_MASK_PWM_DISABLE 0 -#define INT_MASK_PWM_ENABLE 1 -#define INT_MASK_DMA1 10:10 -#define INT_MASK_DMA1_DISABLE 0 -#define INT_MASK_DMA1_ENABLE 1 -#define INT_MASK_DMA 9:9 -#define INT_MASK_DMA_DISABLE 0 -#define INT_MASK_DMA_ENABLE 1 -#define INT_MASK_PCI 8:8 -#define INT_MASK_PCI_DISABLE 0 -#define INT_MASK_PCI_ENABLE 1 -#define INT_MASK_SSP1 7:7 -#define INT_MASK_SSP1_DISABLE 0 -#define INT_MASK_SSP1_ENABLE 1 -#define INT_MASK_SSP0 6:6 -#define INT_MASK_SSP0_DISABLE 0 -#define INT_MASK_SSP0_ENABLE 1 -#define INT_MASK_DE 5:5 -#define INT_MASK_DE_DISABLE 0 -#define INT_MASK_DE_ENABLE 1 -#define INT_MASK_ZVPORT1_VSYNC 4:4 -#define INT_MASK_ZVPORT1_VSYNC_DISABLE 0 -#define INT_MASK_ZVPORT1_VSYNC_ENABLE 1 -#define INT_MASK_ZVPORT0_VSYNC 3:3 -#define INT_MASK_ZVPORT0_VSYNC_DISABLE 0 -#define INT_MASK_ZVPORT0_VSYNC_ENABLE 1 -#define INT_MASK_CRT_VSYNC 2:2 -#define INT_MASK_CRT_VSYNC_DISABLE 0 -#define INT_MASK_CRT_VSYNC_ENABLE 1 -#define INT_MASK_PANEL_VSYNC 1:1 -#define INT_MASK_PANEL_VSYNC_DISABLE 0 -#define INT_MASK_PANEL_VSYNC_ENABLE 1 -#define INT_MASK_VGA_VSYNC 0:0 -#define INT_MASK_VGA_VSYNC_DISABLE 0 -#define INT_MASK_VGA_VSYNC_ENABLE 1 +#define INT_MASK_GPIO31 BIT(31) +#define INT_MASK_GPIO30 BIT(30) +#define INT_MASK_GPIO29 BIT(29) +#define INT_MASK_GPIO28 BIT(28) +#define INT_MASK_GPIO27 BIT(27) +#define INT_MASK_GPIO26 BIT(26) +#define INT_MASK_GPIO25 BIT(25) +#define INT_MASK_I2C BIT(12) +#define INT_MASK_PWM BIT(11) +#define INT_MASK_DMA1 BIT(10) +#define INT_MASK_DMA BIT(9) +#define INT_MASK_PCI BIT(8) +#define INT_MASK_SSP1 BIT(7) +#define INT_MASK_SSP0 BIT(6) +#define INT_MASK_DE BIT(5) +#define INT_MASK_ZVPORT1_VSYNC BIT(4) +#define INT_MASK_ZVPORT0_VSYNC BIT(3) +#define INT_MASK_CRT_VSYNC BIT(2) +#define INT_MASK_PANEL_VSYNC BIT(1) +#define INT_MASK_VGA_VSYNC BIT(0) #define CURRENT_GATE 0x000040 -#define CURRENT_GATE_MCLK 15:14 +#define CURRENT_GATE_MCLK_MASK (0x3 << 14) #ifdef VALIDATION_CHIP - #define CURRENT_GATE_MCLK_112MHZ 0 - #define CURRENT_GATE_MCLK_84MHZ 1 - #define CURRENT_GATE_MCLK_56MHZ 2 - #define CURRENT_GATE_MCLK_42MHZ 3 + #define CURRENT_GATE_MCLK_112MHZ (0x0 << 14) + #define CURRENT_GATE_MCLK_84MHZ (0x1 << 14) + #define CURRENT_GATE_MCLK_56MHZ (0x2 << 14) + #define CURRENT_GATE_MCLK_42MHZ (0x3 << 14) #else - #define CURRENT_GATE_MCLK_DIV_3 0 - #define CURRENT_GATE_MCLK_DIV_4 1 - #define CURRENT_GATE_MCLK_DIV_6 2 - #define CURRENT_GATE_MCLK_DIV_8 3 + #define CURRENT_GATE_MCLK_DIV_3 (0x0 << 14) + #define CURRENT_GATE_MCLK_DIV_4 (0x1 << 14) + #define CURRENT_GATE_MCLK_DIV_6 (0x2 << 14) + #define CURRENT_GATE_MCLK_DIV_8 (0x3 << 14) #endif -#define CURRENT_GATE_M2XCLK 13:12 +#define CURRENT_GATE_M2XCLK_MASK (0x3 << 12) #ifdef VALIDATION_CHIP - #define CURRENT_GATE_M2XCLK_336MHZ 0 - #define CURRENT_GATE_M2XCLK_168MHZ 1 - #define CURRENT_GATE_M2XCLK_112MHZ 2 - #define CURRENT_GATE_M2XCLK_84MHZ 3 + #define CURRENT_GATE_M2XCLK_336MHZ (0x0 << 12) + #define CURRENT_GATE_M2XCLK_168MHZ (0x1 << 12) + #define CURRENT_GATE_M2XCLK_112MHZ (0x2 << 12) + #define CURRENT_GATE_M2XCLK_84MHZ (0x3 << 12) #else - #define CURRENT_GATE_M2XCLK_DIV_1 0 - #define CURRENT_GATE_M2XCLK_DIV_2 1 - #define CURRENT_GATE_M2XCLK_DIV_3 2 - #define CURRENT_GATE_M2XCLK_DIV_4 3 + #define CURRENT_GATE_M2XCLK_DIV_1 (0x0 << 12) + #define CURRENT_GATE_M2XCLK_DIV_2 (0x1 << 12) + #define CURRENT_GATE_M2XCLK_DIV_3 (0x2 << 12) + #define CURRENT_GATE_M2XCLK_DIV_4 (0x3 << 12) #endif -#define CURRENT_GATE_VGA 10:10 -#define CURRENT_GATE_VGA_OFF 0 -#define CURRENT_GATE_VGA_ON 1 -#define CURRENT_GATE_PWM 9:9 -#define CURRENT_GATE_PWM_OFF 0 -#define CURRENT_GATE_PWM_ON 1 -#define CURRENT_GATE_I2C 8:8 -#define CURRENT_GATE_I2C_OFF 0 -#define CURRENT_GATE_I2C_ON 1 -#define CURRENT_GATE_SSP 7:7 -#define CURRENT_GATE_SSP_OFF 0 -#define CURRENT_GATE_SSP_ON 1 -#define CURRENT_GATE_GPIO 6:6 -#define CURRENT_GATE_GPIO_OFF 0 -#define CURRENT_GATE_GPIO_ON 1 -#define CURRENT_GATE_ZVPORT 5:5 -#define CURRENT_GATE_ZVPORT_OFF 0 -#define CURRENT_GATE_ZVPORT_ON 1 -#define CURRENT_GATE_CSC 4:4 -#define CURRENT_GATE_CSC_OFF 0 -#define CURRENT_GATE_CSC_ON 1 -#define CURRENT_GATE_DE 3:3 -#define CURRENT_GATE_DE_OFF 0 -#define CURRENT_GATE_DE_ON 1 -#define CURRENT_GATE_DISPLAY 2:2 -#define CURRENT_GATE_DISPLAY_OFF 0 -#define CURRENT_GATE_DISPLAY_ON 1 -#define CURRENT_GATE_LOCALMEM 1:1 -#define CURRENT_GATE_LOCALMEM_OFF 0 -#define CURRENT_GATE_LOCALMEM_ON 1 -#define CURRENT_GATE_DMA 0:0 -#define CURRENT_GATE_DMA_OFF 0 -#define CURRENT_GATE_DMA_ON 1 +#define CURRENT_GATE_VGA BIT(10) +#define CURRENT_GATE_PWM BIT(9) +#define CURRENT_GATE_I2C BIT(8) +#define CURRENT_GATE_SSP BIT(7) +#define CURRENT_GATE_GPIO BIT(6) +#define CURRENT_GATE_ZVPORT BIT(5) +#define CURRENT_GATE_CSC BIT(4) +#define CURRENT_GATE_DE BIT(3) +#define CURRENT_GATE_DISPLAY BIT(2) +#define CURRENT_GATE_LOCALMEM BIT(1) +#define CURRENT_GATE_DMA BIT(0) #define MODE0_GATE 0x000044 -#define MODE0_GATE_MCLK 15:14 -#define MODE0_GATE_MCLK_112MHZ 0 -#define MODE0_GATE_MCLK_84MHZ 1 -#define MODE0_GATE_MCLK_56MHZ 2 -#define MODE0_GATE_MCLK_42MHZ 3 -#define MODE0_GATE_M2XCLK 13:12 -#define MODE0_GATE_M2XCLK_336MHZ 0 -#define MODE0_GATE_M2XCLK_168MHZ 1 -#define MODE0_GATE_M2XCLK_112MHZ 2 -#define MODE0_GATE_M2XCLK_84MHZ 3 -#define MODE0_GATE_VGA 10:10 -#define MODE0_GATE_VGA_OFF 0 -#define MODE0_GATE_VGA_ON 1 -#define MODE0_GATE_PWM 9:9 -#define MODE0_GATE_PWM_OFF 0 -#define MODE0_GATE_PWM_ON 1 -#define MODE0_GATE_I2C 8:8 -#define MODE0_GATE_I2C_OFF 0 -#define MODE0_GATE_I2C_ON 1 -#define MODE0_GATE_SSP 7:7 -#define MODE0_GATE_SSP_OFF 0 -#define MODE0_GATE_SSP_ON 1 -#define MODE0_GATE_GPIO 6:6 -#define MODE0_GATE_GPIO_OFF 0 -#define MODE0_GATE_GPIO_ON 1 -#define MODE0_GATE_ZVPORT 5:5 -#define MODE0_GATE_ZVPORT_OFF 0 -#define MODE0_GATE_ZVPORT_ON 1 -#define MODE0_GATE_CSC 4:4 -#define MODE0_GATE_CSC_OFF 0 -#define MODE0_GATE_CSC_ON 1 -#define MODE0_GATE_DE 3:3 -#define MODE0_GATE_DE_OFF 0 -#define MODE0_GATE_DE_ON 1 -#define MODE0_GATE_DISPLAY 2:2 -#define MODE0_GATE_DISPLAY_OFF 0 -#define MODE0_GATE_DISPLAY_ON 1 -#define MODE0_GATE_LOCALMEM 1:1 -#define MODE0_GATE_LOCALMEM_OFF 0 -#define MODE0_GATE_LOCALMEM_ON 1 -#define MODE0_GATE_DMA 0:0 -#define MODE0_GATE_DMA_OFF 0 -#define MODE0_GATE_DMA_ON 1 +#define MODE0_GATE_MCLK_MASK (0x3 << 14) +#define MODE0_GATE_MCLK_112MHZ (0x0 << 14) +#define MODE0_GATE_MCLK_84MHZ (0x1 << 14) +#define MODE0_GATE_MCLK_56MHZ (0x2 << 14) +#define MODE0_GATE_MCLK_42MHZ (0x3 << 14) +#define MODE0_GATE_M2XCLK_MASK (0x3 << 12) +#define MODE0_GATE_M2XCLK_336MHZ (0x0 << 12) +#define MODE0_GATE_M2XCLK_168MHZ (0x1 << 12) +#define MODE0_GATE_M2XCLK_112MHZ (0x2 << 12) +#define MODE0_GATE_M2XCLK_84MHZ (0x3 << 12) +#define MODE0_GATE_VGA BIT(10) +#define MODE0_GATE_PWM BIT(9) +#define MODE0_GATE_I2C BIT(8) +#define MODE0_GATE_SSP BIT(7) +#define MODE0_GATE_GPIO BIT(6) +#define MODE0_GATE_ZVPORT BIT(5) +#define MODE0_GATE_CSC BIT(4) +#define MODE0_GATE_DE BIT(3) +#define MODE0_GATE_DISPLAY BIT(2) +#define MODE0_GATE_LOCALMEM BIT(1) +#define MODE0_GATE_DMA BIT(0) #define MODE1_GATE 0x000048 -#define MODE1_GATE_MCLK 15:14 -#define MODE1_GATE_MCLK_112MHZ 0 -#define MODE1_GATE_MCLK_84MHZ 1 -#define MODE1_GATE_MCLK_56MHZ 2 -#define MODE1_GATE_MCLK_42MHZ 3 -#define MODE1_GATE_M2XCLK 13:12 -#define MODE1_GATE_M2XCLK_336MHZ 0 -#define MODE1_GATE_M2XCLK_168MHZ 1 -#define MODE1_GATE_M2XCLK_112MHZ 2 -#define MODE1_GATE_M2XCLK_84MHZ 3 -#define MODE1_GATE_VGA 10:10 -#define MODE1_GATE_VGA_OFF 0 -#define MODE1_GATE_VGA_ON 1 -#define MODE1_GATE_PWM 9:9 -#define MODE1_GATE_PWM_OFF 0 -#define MODE1_GATE_PWM_ON 1 -#define MODE1_GATE_I2C 8:8 -#define MODE1_GATE_I2C_OFF 0 -#define MODE1_GATE_I2C_ON 1 -#define MODE1_GATE_SSP 7:7 -#define MODE1_GATE_SSP_OFF 0 -#define MODE1_GATE_SSP_ON 1 -#define MODE1_GATE_GPIO 6:6 -#define MODE1_GATE_GPIO_OFF 0 -#define MODE1_GATE_GPIO_ON 1 -#define MODE1_GATE_ZVPORT 5:5 -#define MODE1_GATE_ZVPORT_OFF 0 -#define MODE1_GATE_ZVPORT_ON 1 -#define MODE1_GATE_CSC 4:4 -#define MODE1_GATE_CSC_OFF 0 -#define MODE1_GATE_CSC_ON 1 -#define MODE1_GATE_DE 3:3 -#define MODE1_GATE_DE_OFF 0 -#define MODE1_GATE_DE_ON 1 -#define MODE1_GATE_DISPLAY 2:2 -#define MODE1_GATE_DISPLAY_OFF 0 -#define MODE1_GATE_DISPLAY_ON 1 -#define MODE1_GATE_LOCALMEM 1:1 -#define MODE1_GATE_LOCALMEM_OFF 0 -#define MODE1_GATE_LOCALMEM_ON 1 -#define MODE1_GATE_DMA 0:0 -#define MODE1_GATE_DMA_OFF 0 -#define MODE1_GATE_DMA_ON 1 +#define MODE1_GATE_MCLK_MASK (0x3 << 14) +#define MODE1_GATE_MCLK_112MHZ (0x0 << 14) +#define MODE1_GATE_MCLK_84MHZ (0x1 << 14) +#define MODE1_GATE_MCLK_56MHZ (0x2 << 14) +#define MODE1_GATE_MCLK_42MHZ (0x3 << 14) +#define MODE1_GATE_M2XCLK_MASK (0x3 << 12) +#define MODE1_GATE_M2XCLK_336MHZ (0x0 << 12) +#define MODE1_GATE_M2XCLK_168MHZ (0x1 << 12) +#define MODE1_GATE_M2XCLK_112MHZ (0x2 << 12) +#define MODE1_GATE_M2XCLK_84MHZ (0x3 << 12) +#define MODE1_GATE_VGA BIT(10) +#define MODE1_GATE_PWM BIT(9) +#define MODE1_GATE_I2C BIT(8) +#define MODE1_GATE_SSP BIT(7) +#define MODE1_GATE_GPIO BIT(6) +#define MODE1_GATE_ZVPORT BIT(5) +#define MODE1_GATE_CSC BIT(4) +#define MODE1_GATE_DE BIT(3) +#define MODE1_GATE_DISPLAY BIT(2) +#define MODE1_GATE_LOCALMEM BIT(1) +#define MODE1_GATE_DMA BIT(0) #define POWER_MODE_CTRL 0x00004C #ifdef VALIDATION_CHIP - #define POWER_MODE_CTRL_336CLK 4:4 - #define POWER_MODE_CTRL_336CLK_OFF 0 - #define POWER_MODE_CTRL_336CLK_ON 1 + #define POWER_MODE_CTRL_336CLK BIT(4) #endif -#define POWER_MODE_CTRL_OSC_INPUT 3:3 -#define POWER_MODE_CTRL_OSC_INPUT_OFF 0 -#define POWER_MODE_CTRL_OSC_INPUT_ON 1 -#define POWER_MODE_CTRL_ACPI 2:2 -#define POWER_MODE_CTRL_ACPI_OFF 0 -#define POWER_MODE_CTRL_ACPI_ON 1 -#define POWER_MODE_CTRL_MODE 1:0 -#define POWER_MODE_CTRL_MODE_MODE0 0 -#define POWER_MODE_CTRL_MODE_MODE1 1 -#define POWER_MODE_CTRL_MODE_SLEEP 2 +#define POWER_MODE_CTRL_OSC_INPUT BIT(3) +#define POWER_MODE_CTRL_ACPI BIT(2) +#define POWER_MODE_CTRL_MODE_MASK (0x3 << 0) +#define POWER_MODE_CTRL_MODE_MODE0 (0x0 << 0) +#define POWER_MODE_CTRL_MODE_MODE1 (0x1 << 0) +#define POWER_MODE_CTRL_MODE_SLEEP (0x2 << 0) #define PCI_MASTER_BASE 0x000050 -#define PCI_MASTER_BASE_ADDRESS 7:0 +#define PCI_MASTER_BASE_ADDRESS_MASK 0xff #define DEVICE_ID 0x000054 -#define DEVICE_ID_DEVICE_ID 31:16 -#define DEVICE_ID_REVISION_ID 7:0 +#define DEVICE_ID_DEVICE_ID_MASK (0xffff << 16) +#define DEVICE_ID_REVISION_ID_MASK 0xff #define PLL_CLK_COUNT 0x000058 -#define PLL_CLK_COUNT_COUNTER 15:0 +#define PLL_CLK_COUNT_COUNTER_MASK 0xffff #define PANEL_PLL_CTRL 0x00005C -#define PANEL_PLL_CTRL_BYPASS 18:18 -#define PANEL_PLL_CTRL_BYPASS_OFF 0 -#define PANEL_PLL_CTRL_BYPASS_ON 1 -#define PANEL_PLL_CTRL_POWER 17:17 -#define PANEL_PLL_CTRL_POWER_OFF 0 -#define PANEL_PLL_CTRL_POWER_ON 1 -#define PANEL_PLL_CTRL_INPUT 16:16 -#define PANEL_PLL_CTRL_INPUT_OSC 0 -#define PANEL_PLL_CTRL_INPUT_TESTCLK 1 +#define PLL_CTRL_BYPASS BIT(18) +#define PLL_CTRL_POWER BIT(17) +#define PLL_CTRL_INPUT BIT(16) #ifdef VALIDATION_CHIP - #define PANEL_PLL_CTRL_OD 15:14 + #define PLL_CTRL_OD_SHIFT 14 + #define PLL_CTRL_OD_MASK (0x3 << 14) #else - #define PANEL_PLL_CTRL_POD 15:14 - #define PANEL_PLL_CTRL_OD 13:12 + #define PLL_CTRL_POD_SHIFT 14 + #define PLL_CTRL_POD_MASK (0x3 << 14) + #define PLL_CTRL_OD_SHIFT 12 + #define PLL_CTRL_OD_MASK (0x3 << 12) #endif -#define PANEL_PLL_CTRL_N 11:8 -#define PANEL_PLL_CTRL_M 7:0 +#define PLL_CTRL_N_SHIFT 8 +#define PLL_CTRL_N_MASK (0xf << 8) +#define PLL_CTRL_M_SHIFT 0 +#define PLL_CTRL_M_MASK 0xff #define CRT_PLL_CTRL 0x000060 -#define CRT_PLL_CTRL_BYPASS 18:18 -#define CRT_PLL_CTRL_BYPASS_OFF 0 -#define CRT_PLL_CTRL_BYPASS_ON 1 -#define CRT_PLL_CTRL_POWER 17:17 -#define CRT_PLL_CTRL_POWER_OFF 0 -#define CRT_PLL_CTRL_POWER_ON 1 -#define CRT_PLL_CTRL_INPUT 16:16 -#define CRT_PLL_CTRL_INPUT_OSC 0 -#define CRT_PLL_CTRL_INPUT_TESTCLK 1 -#ifdef VALIDATION_CHIP - #define CRT_PLL_CTRL_OD 15:14 -#else - #define CRT_PLL_CTRL_POD 15:14 - #define CRT_PLL_CTRL_OD 13:12 -#endif -#define CRT_PLL_CTRL_N 11:8 -#define CRT_PLL_CTRL_M 7:0 #define VGA_PLL0_CTRL 0x000064 -#define VGA_PLL0_CTRL_BYPASS 18:18 -#define VGA_PLL0_CTRL_BYPASS_OFF 0 -#define VGA_PLL0_CTRL_BYPASS_ON 1 -#define VGA_PLL0_CTRL_POWER 17:17 -#define VGA_PLL0_CTRL_POWER_OFF 0 -#define VGA_PLL0_CTRL_POWER_ON 1 -#define VGA_PLL0_CTRL_INPUT 16:16 -#define VGA_PLL0_CTRL_INPUT_OSC 0 -#define VGA_PLL0_CTRL_INPUT_TESTCLK 1 -#ifdef VALIDATION_CHIP - #define VGA_PLL0_CTRL_OD 15:14 -#else - #define VGA_PLL0_CTRL_POD 15:14 - #define VGA_PLL0_CTRL_OD 13:12 -#endif -#define VGA_PLL0_CTRL_N 11:8 -#define VGA_PLL0_CTRL_M 7:0 #define VGA_PLL1_CTRL 0x000068 -#define VGA_PLL1_CTRL_BYPASS 18:18 -#define VGA_PLL1_CTRL_BYPASS_OFF 0 -#define VGA_PLL1_CTRL_BYPASS_ON 1 -#define VGA_PLL1_CTRL_POWER 17:17 -#define VGA_PLL1_CTRL_POWER_OFF 0 -#define VGA_PLL1_CTRL_POWER_ON 1 -#define VGA_PLL1_CTRL_INPUT 16:16 -#define VGA_PLL1_CTRL_INPUT_OSC 0 -#define VGA_PLL1_CTRL_INPUT_TESTCLK 1 -#ifdef VALIDATION_CHIP - #define VGA_PLL1_CTRL_OD 15:14 -#else - #define VGA_PLL1_CTRL_POD 15:14 - #define VGA_PLL1_CTRL_OD 13:12 -#endif -#define VGA_PLL1_CTRL_N 11:8 -#define VGA_PLL1_CTRL_M 7:0 #define SCRATCH_DATA 0x00006c #ifndef VALIDATION_CHIP #define MXCLK_PLL_CTRL 0x000070 -#define MXCLK_PLL_CTRL_BYPASS 18:18 -#define MXCLK_PLL_CTRL_BYPASS_OFF 0 -#define MXCLK_PLL_CTRL_BYPASS_ON 1 -#define MXCLK_PLL_CTRL_POWER 17:17 -#define MXCLK_PLL_CTRL_POWER_OFF 0 -#define MXCLK_PLL_CTRL_POWER_ON 1 -#define MXCLK_PLL_CTRL_INPUT 16:16 -#define MXCLK_PLL_CTRL_INPUT_OSC 0 -#define MXCLK_PLL_CTRL_INPUT_TESTCLK 1 -#define MXCLK_PLL_CTRL_POD 15:14 -#define MXCLK_PLL_CTRL_OD 13:12 -#define MXCLK_PLL_CTRL_N 11:8 -#define MXCLK_PLL_CTRL_M 7:0 #define VGA_CONFIGURATION 0x000088 -#define VGA_CONFIGURATION_USER_DEFINE 5:4 -#define VGA_CONFIGURATION_PLL 2:2 -#define VGA_CONFIGURATION_PLL_VGA 0 -#define VGA_CONFIGURATION_PLL_PANEL 1 -#define VGA_CONFIGURATION_MODE 1:1 -#define VGA_CONFIGURATION_MODE_TEXT 0 -#define VGA_CONFIGURATION_MODE_GRAPHIC 1 +#define VGA_CONFIGURATION_USER_DEFINE_MASK (0x3 << 4) +#define VGA_CONFIGURATION_PLL BIT(2) +#define VGA_CONFIGURATION_MODE BIT(1) #endif #define GPIO_DATA 0x010000 -#define GPIO_DATA_31 31:31 -#define GPIO_DATA_30 30:30 -#define GPIO_DATA_29 29:29 -#define GPIO_DATA_28 28:28 -#define GPIO_DATA_27 27:27 -#define GPIO_DATA_26 26:26 -#define GPIO_DATA_25 25:25 -#define GPIO_DATA_24 24:24 -#define GPIO_DATA_23 23:23 -#define GPIO_DATA_22 22:22 -#define GPIO_DATA_21 21:21 -#define GPIO_DATA_20 20:20 -#define GPIO_DATA_19 19:19 -#define GPIO_DATA_18 18:18 -#define GPIO_DATA_17 17:17 -#define GPIO_DATA_16 16:16 -#define GPIO_DATA_15 15:15 -#define GPIO_DATA_14 14:14 -#define GPIO_DATA_13 13:13 -#define GPIO_DATA_12 12:12 -#define GPIO_DATA_11 11:11 -#define GPIO_DATA_10 10:10 -#define GPIO_DATA_9 9:9 -#define GPIO_DATA_8 8:8 -#define GPIO_DATA_7 7:7 -#define GPIO_DATA_6 6:6 -#define GPIO_DATA_5 5:5 -#define GPIO_DATA_4 4:4 -#define GPIO_DATA_3 3:3 -#define GPIO_DATA_2 2:2 -#define GPIO_DATA_1 1:1 -#define GPIO_DATA_0 0:0 +#define GPIO_DATA_31 BIT(31) +#define GPIO_DATA_30 BIT(30) +#define GPIO_DATA_29 BIT(29) +#define GPIO_DATA_28 BIT(28) +#define GPIO_DATA_27 BIT(27) +#define GPIO_DATA_26 BIT(26) +#define GPIO_DATA_25 BIT(25) +#define GPIO_DATA_24 BIT(24) +#define GPIO_DATA_23 BIT(23) +#define GPIO_DATA_22 BIT(22) +#define GPIO_DATA_21 BIT(21) +#define GPIO_DATA_20 BIT(20) +#define GPIO_DATA_19 BIT(19) +#define GPIO_DATA_18 BIT(18) +#define GPIO_DATA_17 BIT(17) +#define GPIO_DATA_16 BIT(16) +#define GPIO_DATA_15 BIT(15) +#define GPIO_DATA_14 BIT(14) +#define GPIO_DATA_13 BIT(13) +#define GPIO_DATA_12 BIT(12) +#define GPIO_DATA_11 BIT(11) +#define GPIO_DATA_10 BIT(10) +#define GPIO_DATA_9 BIT(9) +#define GPIO_DATA_8 BIT(8) +#define GPIO_DATA_7 BIT(7) +#define GPIO_DATA_6 BIT(6) +#define GPIO_DATA_5 BIT(5) +#define GPIO_DATA_4 BIT(4) +#define GPIO_DATA_3 BIT(3) +#define GPIO_DATA_2 BIT(2) +#define GPIO_DATA_1 BIT(1) +#define GPIO_DATA_0 BIT(0) #define GPIO_DATA_DIRECTION 0x010004 -#define GPIO_DATA_DIRECTION_31 31:31 -#define GPIO_DATA_DIRECTION_31_INPUT 0 -#define GPIO_DATA_DIRECTION_31_OUTPUT 1 -#define GPIO_DATA_DIRECTION_30 30:30 -#define GPIO_DATA_DIRECTION_30_INPUT 0 -#define GPIO_DATA_DIRECTION_30_OUTPUT 1 -#define GPIO_DATA_DIRECTION_29 29:29 -#define GPIO_DATA_DIRECTION_29_INPUT 0 -#define GPIO_DATA_DIRECTION_29_OUTPUT 1 -#define GPIO_DATA_DIRECTION_28 28:28 -#define GPIO_DATA_DIRECTION_28_INPUT 0 -#define GPIO_DATA_DIRECTION_28_OUTPUT 1 -#define GPIO_DATA_DIRECTION_27 27:27 -#define GPIO_DATA_DIRECTION_27_INPUT 0 -#define GPIO_DATA_DIRECTION_27_OUTPUT 1 -#define GPIO_DATA_DIRECTION_26 26:26 -#define GPIO_DATA_DIRECTION_26_INPUT 0 -#define GPIO_DATA_DIRECTION_26_OUTPUT 1 -#define GPIO_DATA_DIRECTION_25 25:25 -#define GPIO_DATA_DIRECTION_25_INPUT 0 -#define GPIO_DATA_DIRECTION_25_OUTPUT 1 -#define GPIO_DATA_DIRECTION_24 24:24 -#define GPIO_DATA_DIRECTION_24_INPUT 0 -#define GPIO_DATA_DIRECTION_24_OUTPUT 1 -#define GPIO_DATA_DIRECTION_23 23:23 -#define GPIO_DATA_DIRECTION_23_INPUT 0 -#define GPIO_DATA_DIRECTION_23_OUTPUT 1 -#define GPIO_DATA_DIRECTION_22 22:22 -#define GPIO_DATA_DIRECTION_22_INPUT 0 -#define GPIO_DATA_DIRECTION_22_OUTPUT 1 -#define GPIO_DATA_DIRECTION_21 21:21 -#define GPIO_DATA_DIRECTION_21_INPUT 0 -#define GPIO_DATA_DIRECTION_21_OUTPUT 1 -#define GPIO_DATA_DIRECTION_20 20:20 -#define GPIO_DATA_DIRECTION_20_INPUT 0 -#define GPIO_DATA_DIRECTION_20_OUTPUT 1 -#define GPIO_DATA_DIRECTION_19 19:19 -#define GPIO_DATA_DIRECTION_19_INPUT 0 -#define GPIO_DATA_DIRECTION_19_OUTPUT 1 -#define GPIO_DATA_DIRECTION_18 18:18 -#define GPIO_DATA_DIRECTION_18_INPUT 0 -#define GPIO_DATA_DIRECTION_18_OUTPUT 1 -#define GPIO_DATA_DIRECTION_17 17:17 -#define GPIO_DATA_DIRECTION_17_INPUT 0 -#define GPIO_DATA_DIRECTION_17_OUTPUT 1 -#define GPIO_DATA_DIRECTION_16 16:16 -#define GPIO_DATA_DIRECTION_16_INPUT 0 -#define GPIO_DATA_DIRECTION_16_OUTPUT 1 -#define GPIO_DATA_DIRECTION_15 15:15 -#define GPIO_DATA_DIRECTION_15_INPUT 0 -#define GPIO_DATA_DIRECTION_15_OUTPUT 1 -#define GPIO_DATA_DIRECTION_14 14:14 -#define GPIO_DATA_DIRECTION_14_INPUT 0 -#define GPIO_DATA_DIRECTION_14_OUTPUT 1 -#define GPIO_DATA_DIRECTION_13 13:13 -#define GPIO_DATA_DIRECTION_13_INPUT 0 -#define GPIO_DATA_DIRECTION_13_OUTPUT 1 -#define GPIO_DATA_DIRECTION_12 12:12 -#define GPIO_DATA_DIRECTION_12_INPUT 0 -#define GPIO_DATA_DIRECTION_12_OUTPUT 1 -#define GPIO_DATA_DIRECTION_11 11:11 -#define GPIO_DATA_DIRECTION_11_INPUT 0 -#define GPIO_DATA_DIRECTION_11_OUTPUT 1 -#define GPIO_DATA_DIRECTION_10 10:10 -#define GPIO_DATA_DIRECTION_10_INPUT 0 -#define GPIO_DATA_DIRECTION_10_OUTPUT 1 -#define GPIO_DATA_DIRECTION_9 9:9 -#define GPIO_DATA_DIRECTION_9_INPUT 0 -#define GPIO_DATA_DIRECTION_9_OUTPUT 1 -#define GPIO_DATA_DIRECTION_8 8:8 -#define GPIO_DATA_DIRECTION_8_INPUT 0 -#define GPIO_DATA_DIRECTION_8_OUTPUT 1 -#define GPIO_DATA_DIRECTION_7 7:7 -#define GPIO_DATA_DIRECTION_7_INPUT 0 -#define GPIO_DATA_DIRECTION_7_OUTPUT 1 -#define GPIO_DATA_DIRECTION_6 6:6 -#define GPIO_DATA_DIRECTION_6_INPUT 0 -#define GPIO_DATA_DIRECTION_6_OUTPUT 1 -#define GPIO_DATA_DIRECTION_5 5:5 -#define GPIO_DATA_DIRECTION_5_INPUT 0 -#define GPIO_DATA_DIRECTION_5_OUTPUT 1 -#define GPIO_DATA_DIRECTION_4 4:4 -#define GPIO_DATA_DIRECTION_4_INPUT 0 -#define GPIO_DATA_DIRECTION_4_OUTPUT 1 -#define GPIO_DATA_DIRECTION_3 3:3 -#define GPIO_DATA_DIRECTION_3_INPUT 0 -#define GPIO_DATA_DIRECTION_3_OUTPUT 1 -#define GPIO_DATA_DIRECTION_2 2:2 -#define GPIO_DATA_DIRECTION_2_INPUT 0 -#define GPIO_DATA_DIRECTION_2_OUTPUT 1 -#define GPIO_DATA_DIRECTION_1 131 -#define GPIO_DATA_DIRECTION_1_INPUT 0 -#define GPIO_DATA_DIRECTION_1_OUTPUT 1 -#define GPIO_DATA_DIRECTION_0 0:0 -#define GPIO_DATA_DIRECTION_0_INPUT 0 -#define GPIO_DATA_DIRECTION_0_OUTPUT 1 +#define GPIO_DATA_DIRECTION_31 BIT(31) +#define GPIO_DATA_DIRECTION_30 BIT(30) +#define GPIO_DATA_DIRECTION_29 BIT(29) +#define GPIO_DATA_DIRECTION_28 BIT(28) +#define GPIO_DATA_DIRECTION_27 BIT(27) +#define GPIO_DATA_DIRECTION_26 BIT(26) +#define GPIO_DATA_DIRECTION_25 BIT(25) +#define GPIO_DATA_DIRECTION_24 BIT(24) +#define GPIO_DATA_DIRECTION_23 BIT(23) +#define GPIO_DATA_DIRECTION_22 BIT(22) +#define GPIO_DATA_DIRECTION_21 BIT(21) +#define GPIO_DATA_DIRECTION_20 BIT(20) +#define GPIO_DATA_DIRECTION_19 BIT(19) +#define GPIO_DATA_DIRECTION_18 BIT(18) +#define GPIO_DATA_DIRECTION_17 BIT(17) +#define GPIO_DATA_DIRECTION_16 BIT(16) +#define GPIO_DATA_DIRECTION_15 BIT(15) +#define GPIO_DATA_DIRECTION_14 BIT(14) +#define GPIO_DATA_DIRECTION_13 BIT(13) +#define GPIO_DATA_DIRECTION_12 BIT(12) +#define GPIO_DATA_DIRECTION_11 BIT(11) +#define GPIO_DATA_DIRECTION_10 BIT(10) +#define GPIO_DATA_DIRECTION_9 BIT(9) +#define GPIO_DATA_DIRECTION_8 BIT(8) +#define GPIO_DATA_DIRECTION_7 BIT(7) +#define GPIO_DATA_DIRECTION_6 BIT(6) +#define GPIO_DATA_DIRECTION_5 BIT(5) +#define GPIO_DATA_DIRECTION_4 BIT(4) +#define GPIO_DATA_DIRECTION_3 BIT(3) +#define GPIO_DATA_DIRECTION_2 BIT(2) +#define GPIO_DATA_DIRECTION_1 BIT(1) +#define GPIO_DATA_DIRECTION_0 BIT(0) #define GPIO_INTERRUPT_SETUP 0x010008 -#define GPIO_INTERRUPT_SETUP_TRIGGER_31 22:22 -#define GPIO_INTERRUPT_SETUP_TRIGGER_31_EDGE 0 -#define GPIO_INTERRUPT_SETUP_TRIGGER_31_LEVEL 1 -#define GPIO_INTERRUPT_SETUP_TRIGGER_30 21:21 -#define GPIO_INTERRUPT_SETUP_TRIGGER_30_EDGE 0 -#define GPIO_INTERRUPT_SETUP_TRIGGER_30_LEVEL 1 -#define GPIO_INTERRUPT_SETUP_TRIGGER_29 20:20 -#define GPIO_INTERRUPT_SETUP_TRIGGER_29_EDGE 0 -#define GPIO_INTERRUPT_SETUP_TRIGGER_29_LEVEL 1 -#define GPIO_INTERRUPT_SETUP_TRIGGER_28 19:19 -#define GPIO_INTERRUPT_SETUP_TRIGGER_28_EDGE 0 -#define GPIO_INTERRUPT_SETUP_TRIGGER_28_LEVEL 1 -#define GPIO_INTERRUPT_SETUP_TRIGGER_27 18:18 -#define GPIO_INTERRUPT_SETUP_TRIGGER_27_EDGE 0 -#define GPIO_INTERRUPT_SETUP_TRIGGER_27_LEVEL 1 -#define GPIO_INTERRUPT_SETUP_TRIGGER_26 17:17 -#define GPIO_INTERRUPT_SETUP_TRIGGER_26_EDGE 0 -#define GPIO_INTERRUPT_SETUP_TRIGGER_26_LEVEL 1 -#define GPIO_INTERRUPT_SETUP_TRIGGER_25 16:16 -#define GPIO_INTERRUPT_SETUP_TRIGGER_25_EDGE 0 -#define GPIO_INTERRUPT_SETUP_TRIGGER_25_LEVEL 1 -#define GPIO_INTERRUPT_SETUP_ACTIVE_31 14:14 -#define GPIO_INTERRUPT_SETUP_ACTIVE_31_LOW 0 -#define GPIO_INTERRUPT_SETUP_ACTIVE_31_HIGH 1 -#define GPIO_INTERRUPT_SETUP_ACTIVE_30 13:13 -#define GPIO_INTERRUPT_SETUP_ACTIVE_30_LOW 0 -#define GPIO_INTERRUPT_SETUP_ACTIVE_30_HIGH 1 -#define GPIO_INTERRUPT_SETUP_ACTIVE_29 12:12 -#define GPIO_INTERRUPT_SETUP_ACTIVE_29_LOW 0 -#define GPIO_INTERRUPT_SETUP_ACTIVE_29_HIGH 1 -#define GPIO_INTERRUPT_SETUP_ACTIVE_28 11:11 -#define GPIO_INTERRUPT_SETUP_ACTIVE_28_LOW 0 -#define GPIO_INTERRUPT_SETUP_ACTIVE_28_HIGH 1 -#define GPIO_INTERRUPT_SETUP_ACTIVE_27 10:10 -#define GPIO_INTERRUPT_SETUP_ACTIVE_27_LOW 0 -#define GPIO_INTERRUPT_SETUP_ACTIVE_27_HIGH 1 -#define GPIO_INTERRUPT_SETUP_ACTIVE_26 9:9 -#define GPIO_INTERRUPT_SETUP_ACTIVE_26_LOW 0 -#define GPIO_INTERRUPT_SETUP_ACTIVE_26_HIGH 1 -#define GPIO_INTERRUPT_SETUP_ACTIVE_25 8:8 -#define GPIO_INTERRUPT_SETUP_ACTIVE_25_LOW 0 -#define GPIO_INTERRUPT_SETUP_ACTIVE_25_HIGH 1 -#define GPIO_INTERRUPT_SETUP_ENABLE_31 6:6 -#define GPIO_INTERRUPT_SETUP_ENABLE_31_GPIO 0 -#define GPIO_INTERRUPT_SETUP_ENABLE_31_INTERRUPT 1 -#define GPIO_INTERRUPT_SETUP_ENABLE_30 5:5 -#define GPIO_INTERRUPT_SETUP_ENABLE_30_GPIO 0 -#define GPIO_INTERRUPT_SETUP_ENABLE_30_INTERRUPT 1 -#define GPIO_INTERRUPT_SETUP_ENABLE_29 4:4 -#define GPIO_INTERRUPT_SETUP_ENABLE_29_GPIO 0 -#define GPIO_INTERRUPT_SETUP_ENABLE_29_INTERRUPT 1 -#define GPIO_INTERRUPT_SETUP_ENABLE_28 3:3 -#define GPIO_INTERRUPT_SETUP_ENABLE_28_GPIO 0 -#define GPIO_INTERRUPT_SETUP_ENABLE_28_INTERRUPT 1 -#define GPIO_INTERRUPT_SETUP_ENABLE_27 2:2 -#define GPIO_INTERRUPT_SETUP_ENABLE_27_GPIO 0 -#define GPIO_INTERRUPT_SETUP_ENABLE_27_INTERRUPT 1 -#define GPIO_INTERRUPT_SETUP_ENABLE_26 1:1 -#define GPIO_INTERRUPT_SETUP_ENABLE_26_GPIO 0 -#define GPIO_INTERRUPT_SETUP_ENABLE_26_INTERRUPT 1 -#define GPIO_INTERRUPT_SETUP_ENABLE_25 0:0 -#define GPIO_INTERRUPT_SETUP_ENABLE_25_GPIO 0 -#define GPIO_INTERRUPT_SETUP_ENABLE_25_INTERRUPT 1 +#define GPIO_INTERRUPT_SETUP_TRIGGER_31 BIT(22) +#define GPIO_INTERRUPT_SETUP_TRIGGER_30 BIT(21) +#define GPIO_INTERRUPT_SETUP_TRIGGER_29 BIT(20) +#define GPIO_INTERRUPT_SETUP_TRIGGER_28 BIT(19) +#define GPIO_INTERRUPT_SETUP_TRIGGER_27 BIT(18) +#define GPIO_INTERRUPT_SETUP_TRIGGER_26 BIT(17) +#define GPIO_INTERRUPT_SETUP_TRIGGER_25 BIT(16) +#define GPIO_INTERRUPT_SETUP_ACTIVE_31 BIT(14) +#define GPIO_INTERRUPT_SETUP_ACTIVE_30 BIT(13) +#define GPIO_INTERRUPT_SETUP_ACTIVE_29 BIT(12) +#define GPIO_INTERRUPT_SETUP_ACTIVE_28 BIT(11) +#define GPIO_INTERRUPT_SETUP_ACTIVE_27 BIT(10) +#define GPIO_INTERRUPT_SETUP_ACTIVE_26 BIT(9) +#define GPIO_INTERRUPT_SETUP_ACTIVE_25 BIT(8) +#define GPIO_INTERRUPT_SETUP_ENABLE_31 BIT(6) +#define GPIO_INTERRUPT_SETUP_ENABLE_30 BIT(5) +#define GPIO_INTERRUPT_SETUP_ENABLE_29 BIT(4) +#define GPIO_INTERRUPT_SETUP_ENABLE_28 BIT(3) +#define GPIO_INTERRUPT_SETUP_ENABLE_27 BIT(2) +#define GPIO_INTERRUPT_SETUP_ENABLE_26 BIT(1) +#define GPIO_INTERRUPT_SETUP_ENABLE_25 BIT(0) #define GPIO_INTERRUPT_STATUS 0x01000C -#define GPIO_INTERRUPT_STATUS_31 22:22 -#define GPIO_INTERRUPT_STATUS_31_INACTIVE 0 -#define GPIO_INTERRUPT_STATUS_31_ACTIVE 1 -#define GPIO_INTERRUPT_STATUS_31_RESET 1 -#define GPIO_INTERRUPT_STATUS_30 21:21 -#define GPIO_INTERRUPT_STATUS_30_INACTIVE 0 -#define GPIO_INTERRUPT_STATUS_30_ACTIVE 1 -#define GPIO_INTERRUPT_STATUS_30_RESET 1 -#define GPIO_INTERRUPT_STATUS_29 20:20 -#define GPIO_INTERRUPT_STATUS_29_INACTIVE 0 -#define GPIO_INTERRUPT_STATUS_29_ACTIVE 1 -#define GPIO_INTERRUPT_STATUS_29_RESET 1 -#define GPIO_INTERRUPT_STATUS_28 19:19 -#define GPIO_INTERRUPT_STATUS_28_INACTIVE 0 -#define GPIO_INTERRUPT_STATUS_28_ACTIVE 1 -#define GPIO_INTERRUPT_STATUS_28_RESET 1 -#define GPIO_INTERRUPT_STATUS_27 18:18 -#define GPIO_INTERRUPT_STATUS_27_INACTIVE 0 -#define GPIO_INTERRUPT_STATUS_27_ACTIVE 1 -#define GPIO_INTERRUPT_STATUS_27_RESET 1 -#define GPIO_INTERRUPT_STATUS_26 17:17 -#define GPIO_INTERRUPT_STATUS_26_INACTIVE 0 -#define GPIO_INTERRUPT_STATUS_26_ACTIVE 1 -#define GPIO_INTERRUPT_STATUS_26_RESET 1 -#define GPIO_INTERRUPT_STATUS_25 16:16 -#define GPIO_INTERRUPT_STATUS_25_INACTIVE 0 -#define GPIO_INTERRUPT_STATUS_25_ACTIVE 1 -#define GPIO_INTERRUPT_STATUS_25_RESET 1 +#define GPIO_INTERRUPT_STATUS_31 BIT(22) +#define GPIO_INTERRUPT_STATUS_30 BIT(21) +#define GPIO_INTERRUPT_STATUS_29 BIT(20) +#define GPIO_INTERRUPT_STATUS_28 BIT(19) +#define GPIO_INTERRUPT_STATUS_27 BIT(18) +#define GPIO_INTERRUPT_STATUS_26 BIT(17) +#define GPIO_INTERRUPT_STATUS_25 BIT(16) #define PANEL_DISPLAY_CTRL 0x080000 -#define PANEL_DISPLAY_CTRL_RESERVED_1_MASK 31:30 -#define PANEL_DISPLAY_CTRL_RESERVED_1_MASK_DISABLE 0 -#define PANEL_DISPLAY_CTRL_RESERVED_1_MASK_ENABLE 3 -#define PANEL_DISPLAY_CTRL_SELECT 29:28 -#define PANEL_DISPLAY_CTRL_SELECT_PANEL 0 -#define PANEL_DISPLAY_CTRL_SELECT_VGA 1 -#define PANEL_DISPLAY_CTRL_SELECT_CRT 2 -#define PANEL_DISPLAY_CTRL_FPEN 27:27 -#define PANEL_DISPLAY_CTRL_FPEN_LOW 0 -#define PANEL_DISPLAY_CTRL_FPEN_HIGH 1 -#define PANEL_DISPLAY_CTRL_VBIASEN 26:26 -#define PANEL_DISPLAY_CTRL_VBIASEN_LOW 0 -#define PANEL_DISPLAY_CTRL_VBIASEN_HIGH 1 -#define PANEL_DISPLAY_CTRL_DATA 25:25 -#define PANEL_DISPLAY_CTRL_DATA_DISABLE 0 -#define PANEL_DISPLAY_CTRL_DATA_ENABLE 1 -#define PANEL_DISPLAY_CTRL_FPVDDEN 24:24 -#define PANEL_DISPLAY_CTRL_FPVDDEN_LOW 0 -#define PANEL_DISPLAY_CTRL_FPVDDEN_HIGH 1 -#define PANEL_DISPLAY_CTRL_RESERVED_2_MASK 23:20 -#define PANEL_DISPLAY_CTRL_RESERVED_2_MASK_DISABLE 0 -#define PANEL_DISPLAY_CTRL_RESERVED_2_MASK_ENABLE 15 - -#define PANEL_DISPLAY_CTRL_TFT_DISP 19:18 -#define PANEL_DISPLAY_CTRL_TFT_DISP_24 0 -#define PANEL_DISPLAY_CTRL_TFT_DISP_36 1 -#define PANEL_DISPLAY_CTRL_TFT_DISP_18 2 - - -#define PANEL_DISPLAY_CTRL_DUAL_DISPLAY 19:19 -#define PANEL_DISPLAY_CTRL_DUAL_DISPLAY_DISABLE 0 -#define PANEL_DISPLAY_CTRL_DUAL_DISPLAY_ENABLE 1 -#define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL 18:18 -#define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL_DISABLE 0 -#define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL_ENABLE 1 -#define PANEL_DISPLAY_CTRL_FIFO 17:16 -#define PANEL_DISPLAY_CTRL_FIFO_1 0 -#define PANEL_DISPLAY_CTRL_FIFO_3 1 -#define PANEL_DISPLAY_CTRL_FIFO_7 2 -#define PANEL_DISPLAY_CTRL_FIFO_11 3 -#define PANEL_DISPLAY_CTRL_RESERVED_3_MASK 15:15 -#define PANEL_DISPLAY_CTRL_RESERVED_3_MASK_DISABLE 0 -#define PANEL_DISPLAY_CTRL_RESERVED_3_MASK_ENABLE 1 -#define PANEL_DISPLAY_CTRL_CLOCK_PHASE 14:14 -#define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH 0 -#define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW 1 -#define PANEL_DISPLAY_CTRL_VSYNC_PHASE 13:13 -#define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH 0 -#define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW 1 -#define PANEL_DISPLAY_CTRL_HSYNC_PHASE 12:12 -#define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH 0 -#define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW 1 -#define PANEL_DISPLAY_CTRL_VSYNC 11:11 -#define PANEL_DISPLAY_CTRL_VSYNC_ACTIVE_HIGH 0 -#define PANEL_DISPLAY_CTRL_VSYNC_ACTIVE_LOW 1 -#define PANEL_DISPLAY_CTRL_CAPTURE_TIMING 10:10 -#define PANEL_DISPLAY_CTRL_CAPTURE_TIMING_DISABLE 0 -#define PANEL_DISPLAY_CTRL_CAPTURE_TIMING_ENABLE 1 -#define PANEL_DISPLAY_CTRL_COLOR_KEY 9:9 -#define PANEL_DISPLAY_CTRL_COLOR_KEY_DISABLE 0 -#define PANEL_DISPLAY_CTRL_COLOR_KEY_ENABLE 1 -#define PANEL_DISPLAY_CTRL_TIMING 8:8 -#define PANEL_DISPLAY_CTRL_TIMING_DISABLE 0 -#define PANEL_DISPLAY_CTRL_TIMING_ENABLE 1 -#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR 7:7 -#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_DOWN 0 -#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_UP 1 -#define PANEL_DISPLAY_CTRL_VERTICAL_PAN 6:6 -#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DISABLE 0 -#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_ENABLE 1 -#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR 5:5 -#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_RIGHT 0 -#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_LEFT 1 -#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN 4:4 -#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DISABLE 0 -#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_ENABLE 1 -#define PANEL_DISPLAY_CTRL_GAMMA 3:3 -#define PANEL_DISPLAY_CTRL_GAMMA_DISABLE 0 -#define PANEL_DISPLAY_CTRL_GAMMA_ENABLE 1 -#define PANEL_DISPLAY_CTRL_PLANE 2:2 -#define PANEL_DISPLAY_CTRL_PLANE_DISABLE 0 -#define PANEL_DISPLAY_CTRL_PLANE_ENABLE 1 -#define PANEL_DISPLAY_CTRL_FORMAT 1:0 -#define PANEL_DISPLAY_CTRL_FORMAT_8 0 -#define PANEL_DISPLAY_CTRL_FORMAT_16 1 -#define PANEL_DISPLAY_CTRL_FORMAT_32 2 +#define PANEL_DISPLAY_CTRL_RESERVED_MASK 0xc0f08000 +#define PANEL_DISPLAY_CTRL_SELECT_SHIFT 28 +#define PANEL_DISPLAY_CTRL_SELECT_MASK (0x3 << 28) +#define PANEL_DISPLAY_CTRL_SELECT_PANEL (0x0 << 28) +#define PANEL_DISPLAY_CTRL_SELECT_VGA (0x1 << 28) +#define PANEL_DISPLAY_CTRL_SELECT_CRT (0x2 << 28) +#define PANEL_DISPLAY_CTRL_FPEN BIT(27) +#define PANEL_DISPLAY_CTRL_VBIASEN BIT(26) +#define PANEL_DISPLAY_CTRL_DATA BIT(25) +#define PANEL_DISPLAY_CTRL_FPVDDEN BIT(24) +#define PANEL_DISPLAY_CTRL_DUAL_DISPLAY BIT(19) +#define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL BIT(18) +#define PANEL_DISPLAY_CTRL_FIFO (0x3 << 16) +#define PANEL_DISPLAY_CTRL_FIFO_1 (0x0 << 16) +#define PANEL_DISPLAY_CTRL_FIFO_3 (0x1 << 16) +#define PANEL_DISPLAY_CTRL_FIFO_7 (0x2 << 16) +#define PANEL_DISPLAY_CTRL_FIFO_11 (0x3 << 16) +#define DISPLAY_CTRL_CLOCK_PHASE BIT(14) +#define DISPLAY_CTRL_VSYNC_PHASE BIT(13) +#define DISPLAY_CTRL_HSYNC_PHASE BIT(12) +#define PANEL_DISPLAY_CTRL_VSYNC BIT(11) +#define PANEL_DISPLAY_CTRL_CAPTURE_TIMING BIT(10) +#define PANEL_DISPLAY_CTRL_COLOR_KEY BIT(9) +#define DISPLAY_CTRL_TIMING BIT(8) +#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR BIT(7) +#define PANEL_DISPLAY_CTRL_VERTICAL_PAN BIT(6) +#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR BIT(5) +#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN BIT(4) +#define DISPLAY_CTRL_GAMMA BIT(3) +#define DISPLAY_CTRL_PLANE BIT(2) +#define PANEL_DISPLAY_CTRL_FORMAT (0x3 << 0) +#define PANEL_DISPLAY_CTRL_FORMAT_8 (0x0 << 0) +#define PANEL_DISPLAY_CTRL_FORMAT_16 (0x1 << 0) +#define PANEL_DISPLAY_CTRL_FORMAT_32 (0x2 << 0) #define PANEL_PAN_CTRL 0x080004 -#define PANEL_PAN_CTRL_VERTICAL_PAN 31:24 -#define PANEL_PAN_CTRL_VERTICAL_VSYNC 21:16 -#define PANEL_PAN_CTRL_HORIZONTAL_PAN 15:8 -#define PANEL_PAN_CTRL_HORIZONTAL_VSYNC 5:0 +#define PANEL_PAN_CTRL_VERTICAL_PAN_MASK (0xff << 24) +#define PANEL_PAN_CTRL_VERTICAL_VSYNC_MASK (0x3f << 16) +#define PANEL_PAN_CTRL_HORIZONTAL_PAN_MASK (0xff << 8) +#define PANEL_PAN_CTRL_HORIZONTAL_VSYNC_MASK 0x3f #define PANEL_COLOR_KEY 0x080008 -#define PANEL_COLOR_KEY_MASK 31:16 -#define PANEL_COLOR_KEY_VALUE 15:0 +#define PANEL_COLOR_KEY_MASK_MASK (0xffff << 16) +#define PANEL_COLOR_KEY_VALUE_MASK 0xffff #define PANEL_FB_ADDRESS 0x08000C -#define PANEL_FB_ADDRESS_STATUS 31:31 -#define PANEL_FB_ADDRESS_STATUS_CURRENT 0 -#define PANEL_FB_ADDRESS_STATUS_PENDING 1 -#define PANEL_FB_ADDRESS_EXT 27:27 -#define PANEL_FB_ADDRESS_EXT_LOCAL 0 -#define PANEL_FB_ADDRESS_EXT_EXTERNAL 1 -#define PANEL_FB_ADDRESS_ADDRESS 25:0 +#define PANEL_FB_ADDRESS_STATUS BIT(31) +#define PANEL_FB_ADDRESS_EXT BIT(27) +#define PANEL_FB_ADDRESS_ADDRESS_MASK 0x1ffffff #define PANEL_FB_WIDTH 0x080010 -#define PANEL_FB_WIDTH_WIDTH 29:16 -#define PANEL_FB_WIDTH_OFFSET 13:0 +#define PANEL_FB_WIDTH_WIDTH_SHIFT 16 +#define PANEL_FB_WIDTH_WIDTH_MASK (0x3fff << 16) +#define PANEL_FB_WIDTH_OFFSET_MASK 0x3fff #define PANEL_WINDOW_WIDTH 0x080014 -#define PANEL_WINDOW_WIDTH_WIDTH 27:16 -#define PANEL_WINDOW_WIDTH_X 11:0 +#define PANEL_WINDOW_WIDTH_WIDTH_SHIFT 16 +#define PANEL_WINDOW_WIDTH_WIDTH_MASK (0xfff << 16) +#define PANEL_WINDOW_WIDTH_X_MASK 0xfff #define PANEL_WINDOW_HEIGHT 0x080018 -#define PANEL_WINDOW_HEIGHT_HEIGHT 27:16 -#define PANEL_WINDOW_HEIGHT_Y 11:0 +#define PANEL_WINDOW_HEIGHT_HEIGHT_SHIFT 16 +#define PANEL_WINDOW_HEIGHT_HEIGHT_MASK (0xfff << 16) +#define PANEL_WINDOW_HEIGHT_Y_MASK 0xfff #define PANEL_PLANE_TL 0x08001C -#define PANEL_PLANE_TL_TOP 26:16 -#define PANEL_PLANE_TL_LEFT 10:0 +#define PANEL_PLANE_TL_TOP_SHIFT 16 +#define PANEL_PLANE_TL_TOP_MASK (0xeff << 16) +#define PANEL_PLANE_TL_LEFT_MASK 0xeff #define PANEL_PLANE_BR 0x080020 -#define PANEL_PLANE_BR_BOTTOM 26:16 -#define PANEL_PLANE_BR_RIGHT 10:0 +#define PANEL_PLANE_BR_BOTTOM_SHIFT 16 +#define PANEL_PLANE_BR_BOTTOM_MASK (0xeff << 16) +#define PANEL_PLANE_BR_RIGHT_MASK 0xeff #define PANEL_HORIZONTAL_TOTAL 0x080024 -#define PANEL_HORIZONTAL_TOTAL_TOTAL 27:16 -#define PANEL_HORIZONTAL_TOTAL_DISPLAY_END 11:0 +#define PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT 16 +#define PANEL_HORIZONTAL_TOTAL_TOTAL_MASK (0xfff << 16) +#define PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK 0xfff #define PANEL_HORIZONTAL_SYNC 0x080028 -#define PANEL_HORIZONTAL_SYNC_WIDTH 23:16 -#define PANEL_HORIZONTAL_SYNC_START 11:0 +#define PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT 16 +#define PANEL_HORIZONTAL_SYNC_WIDTH_MASK (0xff << 16) +#define PANEL_HORIZONTAL_SYNC_START_MASK 0xfff #define PANEL_VERTICAL_TOTAL 0x08002C -#define PANEL_VERTICAL_TOTAL_TOTAL 26:16 -#define PANEL_VERTICAL_TOTAL_DISPLAY_END 10:0 +#define PANEL_VERTICAL_TOTAL_TOTAL_SHIFT 16 +#define PANEL_VERTICAL_TOTAL_TOTAL_MASK (0x7ff << 16) +#define PANEL_VERTICAL_TOTAL_DISPLAY_END_MASK 0x7ff #define PANEL_VERTICAL_SYNC 0x080030 -#define PANEL_VERTICAL_SYNC_HEIGHT 21:16 -#define PANEL_VERTICAL_SYNC_START 10:0 +#define PANEL_VERTICAL_SYNC_HEIGHT_SHIFT 16 +#define PANEL_VERTICAL_SYNC_HEIGHT_MASK (0x3f << 16) +#define PANEL_VERTICAL_SYNC_START_MASK 0x7ff #define PANEL_CURRENT_LINE 0x080034 -#define PANEL_CURRENT_LINE_LINE 10:0 +#define PANEL_CURRENT_LINE_LINE_MASK 0x7ff /* Video Control */ #define VIDEO_DISPLAY_CTRL 0x080040 -#define VIDEO_DISPLAY_CTRL_LINE_BUFFER 18:18 -#define VIDEO_DISPLAY_CTRL_LINE_BUFFER_DISABLE 0 -#define VIDEO_DISPLAY_CTRL_LINE_BUFFER_ENABLE 1 -#define VIDEO_DISPLAY_CTRL_FIFO 17:16 -#define VIDEO_DISPLAY_CTRL_FIFO_1 0 -#define VIDEO_DISPLAY_CTRL_FIFO_3 1 -#define VIDEO_DISPLAY_CTRL_FIFO_7 2 -#define VIDEO_DISPLAY_CTRL_FIFO_11 3 -#define VIDEO_DISPLAY_CTRL_BUFFER 15:15 -#define VIDEO_DISPLAY_CTRL_BUFFER_0 0 -#define VIDEO_DISPLAY_CTRL_BUFFER_1 1 -#define VIDEO_DISPLAY_CTRL_CAPTURE 14:14 -#define VIDEO_DISPLAY_CTRL_CAPTURE_DISABLE 0 -#define VIDEO_DISPLAY_CTRL_CAPTURE_ENABLE 1 -#define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER 13:13 -#define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER_DISABLE 0 -#define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER_ENABLE 1 -#define VIDEO_DISPLAY_CTRL_BYTE_SWAP 12:12 -#define VIDEO_DISPLAY_CTRL_BYTE_SWAP_DISABLE 0 -#define VIDEO_DISPLAY_CTRL_BYTE_SWAP_ENABLE 1 -#define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE 11:11 -#define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE_NORMAL 0 -#define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE_HALF 1 -#define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE 10:10 -#define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE_NORMAL 0 -#define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE_HALF 1 -#define VIDEO_DISPLAY_CTRL_VERTICAL_MODE 9:9 -#define VIDEO_DISPLAY_CTRL_VERTICAL_MODE_REPLICATE 0 -#define VIDEO_DISPLAY_CTRL_VERTICAL_MODE_INTERPOLATE 1 -#define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE 8:8 -#define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE_REPLICATE 0 -#define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE_INTERPOLATE 1 -#define VIDEO_DISPLAY_CTRL_PIXEL 7:4 -#define VIDEO_DISPLAY_CTRL_GAMMA 3:3 -#define VIDEO_DISPLAY_CTRL_GAMMA_DISABLE 0 -#define VIDEO_DISPLAY_CTRL_GAMMA_ENABLE 1 -#define VIDEO_DISPLAY_CTRL_PLANE 2:2 -#define VIDEO_DISPLAY_CTRL_PLANE_DISABLE 0 -#define VIDEO_DISPLAY_CTRL_PLANE_ENABLE 1 -#define VIDEO_DISPLAY_CTRL_FORMAT 1:0 -#define VIDEO_DISPLAY_CTRL_FORMAT_8 0 -#define VIDEO_DISPLAY_CTRL_FORMAT_16 1 -#define VIDEO_DISPLAY_CTRL_FORMAT_32 2 -#define VIDEO_DISPLAY_CTRL_FORMAT_YUV 3 +#define VIDEO_DISPLAY_CTRL_LINE_BUFFER BIT(18) +#define VIDEO_DISPLAY_CTRL_FIFO_MASK (0x3 << 16) +#define VIDEO_DISPLAY_CTRL_FIFO_1 (0x0 << 16) +#define VIDEO_DISPLAY_CTRL_FIFO_3 (0x1 << 16) +#define VIDEO_DISPLAY_CTRL_FIFO_7 (0x2 << 16) +#define VIDEO_DISPLAY_CTRL_FIFO_11 (0x3 << 16) +#define VIDEO_DISPLAY_CTRL_BUFFER BIT(15) +#define VIDEO_DISPLAY_CTRL_CAPTURE BIT(14) +#define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER BIT(13) +#define VIDEO_DISPLAY_CTRL_BYTE_SWAP BIT(12) +#define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE BIT(11) +#define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE BIT(10) +#define VIDEO_DISPLAY_CTRL_VERTICAL_MODE BIT(9) +#define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE BIT(8) +#define VIDEO_DISPLAY_CTRL_PIXEL_MASK (0xf << 4) +#define VIDEO_DISPLAY_CTRL_GAMMA BIT(3) +#define VIDEO_DISPLAY_CTRL_FORMAT_MASK 0x3 +#define VIDEO_DISPLAY_CTRL_FORMAT_8 0x0 +#define VIDEO_DISPLAY_CTRL_FORMAT_16 0x1 +#define VIDEO_DISPLAY_CTRL_FORMAT_32 0x2 +#define VIDEO_DISPLAY_CTRL_FORMAT_YUV 0x3 #define VIDEO_FB_0_ADDRESS 0x080044 -#define VIDEO_FB_0_ADDRESS_STATUS 31:31 -#define VIDEO_FB_0_ADDRESS_STATUS_CURRENT 0 -#define VIDEO_FB_0_ADDRESS_STATUS_PENDING 1 -#define VIDEO_FB_0_ADDRESS_EXT 27:27 -#define VIDEO_FB_0_ADDRESS_EXT_LOCAL 0 -#define VIDEO_FB_0_ADDRESS_EXT_EXTERNAL 1 -#define VIDEO_FB_0_ADDRESS_ADDRESS 25:0 +#define VIDEO_FB_0_ADDRESS_STATUS BIT(31) +#define VIDEO_FB_0_ADDRESS_EXT BIT(27) +#define VIDEO_FB_0_ADDRESS_ADDRESS_MASK 0x3ffffff #define VIDEO_FB_WIDTH 0x080048 -#define VIDEO_FB_WIDTH_WIDTH 29:16 -#define VIDEO_FB_WIDTH_OFFSET 13:0 +#define VIDEO_FB_WIDTH_WIDTH_MASK (0x3fff << 16) +#define VIDEO_FB_WIDTH_OFFSET_MASK 0x3fff #define VIDEO_FB_0_LAST_ADDRESS 0x08004C -#define VIDEO_FB_0_LAST_ADDRESS_EXT 27:27 -#define VIDEO_FB_0_LAST_ADDRESS_EXT_LOCAL 0 -#define VIDEO_FB_0_LAST_ADDRESS_EXT_EXTERNAL 1 -#define VIDEO_FB_0_LAST_ADDRESS_ADDRESS 25:0 +#define VIDEO_FB_0_LAST_ADDRESS_EXT BIT(27) +#define VIDEO_FB_0_LAST_ADDRESS_ADDRESS_MASK 0x3ffffff #define VIDEO_PLANE_TL 0x080050 -#define VIDEO_PLANE_TL_TOP 26:16 -#define VIDEO_PLANE_TL_LEFT 10:0 +#define VIDEO_PLANE_TL_TOP_MASK (0x7ff << 16) +#define VIDEO_PLANE_TL_LEFT_MASK 0x7ff #define VIDEO_PLANE_BR 0x080054 -#define VIDEO_PLANE_BR_BOTTOM 26:16 -#define VIDEO_PLANE_BR_RIGHT 10:0 +#define VIDEO_PLANE_BR_BOTTOM_MASK (0x7ff << 16) +#define VIDEO_PLANE_BR_RIGHT_MASK 0x7ff #define VIDEO_SCALE 0x080058 -#define VIDEO_SCALE_VERTICAL_MODE 31:31 -#define VIDEO_SCALE_VERTICAL_MODE_EXPAND 0 -#define VIDEO_SCALE_VERTICAL_MODE_SHRINK 1 -#define VIDEO_SCALE_VERTICAL_SCALE 27:16 -#define VIDEO_SCALE_HORIZONTAL_MODE 15:15 -#define VIDEO_SCALE_HORIZONTAL_MODE_EXPAND 0 -#define VIDEO_SCALE_HORIZONTAL_MODE_SHRINK 1 -#define VIDEO_SCALE_HORIZONTAL_SCALE 11:0 +#define VIDEO_SCALE_VERTICAL_MODE BIT(31) +#define VIDEO_SCALE_VERTICAL_SCALE_MASK (0xfff << 16) +#define VIDEO_SCALE_HORIZONTAL_MODE BIT(15) +#define VIDEO_SCALE_HORIZONTAL_SCALE_MASK 0xfff #define VIDEO_INITIAL_SCALE 0x08005C -#define VIDEO_INITIAL_SCALE_FB_1 27:16 -#define VIDEO_INITIAL_SCALE_FB_0 11:0 +#define VIDEO_INITIAL_SCALE_FB_1_MASK (0xfff << 16) +#define VIDEO_INITIAL_SCALE_FB_0_MASK 0xfff #define VIDEO_YUV_CONSTANTS 0x080060 -#define VIDEO_YUV_CONSTANTS_Y 31:24 -#define VIDEO_YUV_CONSTANTS_R 23:16 -#define VIDEO_YUV_CONSTANTS_G 15:8 -#define VIDEO_YUV_CONSTANTS_B 7:0 +#define VIDEO_YUV_CONSTANTS_Y_MASK (0xff << 24) +#define VIDEO_YUV_CONSTANTS_R_MASK (0xff << 16) +#define VIDEO_YUV_CONSTANTS_G_MASK (0xff << 8) +#define VIDEO_YUV_CONSTANTS_B_MASK 0xff #define VIDEO_FB_1_ADDRESS 0x080064 -#define VIDEO_FB_1_ADDRESS_STATUS 31:31 -#define VIDEO_FB_1_ADDRESS_STATUS_CURRENT 0 -#define VIDEO_FB_1_ADDRESS_STATUS_PENDING 1 -#define VIDEO_FB_1_ADDRESS_EXT 27:27 -#define VIDEO_FB_1_ADDRESS_EXT_LOCAL 0 -#define VIDEO_FB_1_ADDRESS_EXT_EXTERNAL 1 -#define VIDEO_FB_1_ADDRESS_ADDRESS 25:0 +#define VIDEO_FB_1_ADDRESS_STATUS BIT(31) +#define VIDEO_FB_1_ADDRESS_EXT BIT(27) +#define VIDEO_FB_1_ADDRESS_ADDRESS_MASK 0x3ffffff #define VIDEO_FB_1_LAST_ADDRESS 0x080068 -#define VIDEO_FB_1_LAST_ADDRESS_EXT 27:27 -#define VIDEO_FB_1_LAST_ADDRESS_EXT_LOCAL 0 -#define VIDEO_FB_1_LAST_ADDRESS_EXT_EXTERNAL 1 -#define VIDEO_FB_1_LAST_ADDRESS_ADDRESS 25:0 +#define VIDEO_FB_1_LAST_ADDRESS_EXT BIT(27) +#define VIDEO_FB_1_LAST_ADDRESS_ADDRESS_MASK 0x3ffffff /* Video Alpha Control */ #define VIDEO_ALPHA_DISPLAY_CTRL 0x080080 -#define VIDEO_ALPHA_DISPLAY_CTRL_SELECT 28:28 -#define VIDEO_ALPHA_DISPLAY_CTRL_SELECT_PER_PIXEL 0 -#define VIDEO_ALPHA_DISPLAY_CTRL_SELECT_ALPHA 1 -#define VIDEO_ALPHA_DISPLAY_CTRL_ALPHA 27:24 -#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO 17:16 -#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_1 0 -#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_3 1 -#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_7 2 -#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_11 3 -#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE 11:11 -#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE_NORMAL 0 -#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE_HALF 1 -#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE 10:10 -#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE_NORMAL 0 -#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE_HALF 1 -#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE 9:9 -#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE_REPLICATE 0 -#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE_INTERPOLATE 1 -#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE 8:8 -#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE_REPLICATE 0 -#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE_INTERPOLATE 1 -#define VIDEO_ALPHA_DISPLAY_CTRL_PIXEL 7:4 -#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY 3:3 -#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE 0 -#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE 1 -#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE 2:2 -#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE_DISABLE 0 -#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE_ENABLE 1 -#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT 1:0 -#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_8 0 -#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_16 1 -#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4 2 -#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4 3 +#define VIDEO_ALPHA_DISPLAY_CTRL_SELECT BIT(28) +#define VIDEO_ALPHA_DISPLAY_CTRL_ALPHA_MASK (0xf << 24) +#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_MASK (0x3 << 16) +#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_1 (0x0 << 16) +#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_3 (0x1 << 16) +#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_7 (0x2 << 16) +#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_11 (0x3 << 16) +#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE BIT(11) +#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE BIT(10) +#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE BIT(9) +#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE BIT(8) +#define VIDEO_ALPHA_DISPLAY_CTRL_PIXEL_MASK (0xf << 4) +#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY BIT(3) +#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_MASK 0x3 +#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_8 0x0 +#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_16 0x1 +#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4 0x2 +#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4 0x3 #define VIDEO_ALPHA_FB_ADDRESS 0x080084 -#define VIDEO_ALPHA_FB_ADDRESS_STATUS 31:31 -#define VIDEO_ALPHA_FB_ADDRESS_STATUS_CURRENT 0 -#define VIDEO_ALPHA_FB_ADDRESS_STATUS_PENDING 1 -#define VIDEO_ALPHA_FB_ADDRESS_EXT 27:27 -#define VIDEO_ALPHA_FB_ADDRESS_EXT_LOCAL 0 -#define VIDEO_ALPHA_FB_ADDRESS_EXT_EXTERNAL 1 -#define VIDEO_ALPHA_FB_ADDRESS_ADDRESS 25:0 +#define VIDEO_ALPHA_FB_ADDRESS_STATUS BIT(31) +#define VIDEO_ALPHA_FB_ADDRESS_EXT BIT(27) +#define VIDEO_ALPHA_FB_ADDRESS_ADDRESS_MASK 0x3ffffff #define VIDEO_ALPHA_FB_WIDTH 0x080088 -#define VIDEO_ALPHA_FB_WIDTH_WIDTH 29:16 -#define VIDEO_ALPHA_FB_WIDTH_OFFSET 13:0 +#define VIDEO_ALPHA_FB_WIDTH_WIDTH_MASK (0x3fff << 16) +#define VIDEO_ALPHA_FB_WIDTH_OFFSET_MASK 0x3fff #define VIDEO_ALPHA_FB_LAST_ADDRESS 0x08008C -#define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT 27:27 -#define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT_LOCAL 0 -#define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT_EXTERNAL 1 -#define VIDEO_ALPHA_FB_LAST_ADDRESS_ADDRESS 25:0 +#define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT BIT(27) +#define VIDEO_ALPHA_FB_LAST_ADDRESS_ADDRESS_MASK 0x3ffffff #define VIDEO_ALPHA_PLANE_TL 0x080090 -#define VIDEO_ALPHA_PLANE_TL_TOP 26:16 -#define VIDEO_ALPHA_PLANE_TL_LEFT 10:0 +#define VIDEO_ALPHA_PLANE_TL_TOP_MASK (0x7ff << 16) +#define VIDEO_ALPHA_PLANE_TL_LEFT_MASK 0x7ff #define VIDEO_ALPHA_PLANE_BR 0x080094 -#define VIDEO_ALPHA_PLANE_BR_BOTTOM 26:16 -#define VIDEO_ALPHA_PLANE_BR_RIGHT 10:0 +#define VIDEO_ALPHA_PLANE_BR_BOTTOM_MASK (0x7ff << 16) +#define VIDEO_ALPHA_PLANE_BR_RIGHT_MASK 0x7ff #define VIDEO_ALPHA_SCALE 0x080098 -#define VIDEO_ALPHA_SCALE_VERTICAL_MODE 31:31 -#define VIDEO_ALPHA_SCALE_VERTICAL_MODE_EXPAND 0 -#define VIDEO_ALPHA_SCALE_VERTICAL_MODE_SHRINK 1 -#define VIDEO_ALPHA_SCALE_VERTICAL_SCALE 27:16 -#define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE 15:15 -#define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE_EXPAND 0 -#define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE_SHRINK 1 -#define VIDEO_ALPHA_SCALE_HORIZONTAL_SCALE 11:0 +#define VIDEO_ALPHA_SCALE_VERTICAL_MODE BIT(31) +#define VIDEO_ALPHA_SCALE_VERTICAL_SCALE_MASK (0xfff << 16) +#define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE BIT(15) +#define VIDEO_ALPHA_SCALE_HORIZONTAL_SCALE_MASK 0xfff #define VIDEO_ALPHA_INITIAL_SCALE 0x08009C -#define VIDEO_ALPHA_INITIAL_SCALE_VERTICAL 27:16 -#define VIDEO_ALPHA_INITIAL_SCALE_HORIZONTAL 11:0 +#define VIDEO_ALPHA_INITIAL_SCALE_VERTICAL_MASK (0xfff << 16) +#define VIDEO_ALPHA_INITIAL_SCALE_HORIZONTAL_MASK 0xfff #define VIDEO_ALPHA_CHROMA_KEY 0x0800A0 -#define VIDEO_ALPHA_CHROMA_KEY_MASK 31:16 -#define VIDEO_ALPHA_CHROMA_KEY_VALUE 15:0 +#define VIDEO_ALPHA_CHROMA_KEY_MASK_MASK (0xffff << 16) +#define VIDEO_ALPHA_CHROMA_KEY_VALUE_MASK 0xffff #define VIDEO_ALPHA_COLOR_LOOKUP_01 0x0800A4 -#define VIDEO_ALPHA_COLOR_LOOKUP_01_1 31:16 -#define VIDEO_ALPHA_COLOR_LOOKUP_01_1_RED 31:27 -#define VIDEO_ALPHA_COLOR_LOOKUP_01_1_GREEN 26:21 -#define VIDEO_ALPHA_COLOR_LOOKUP_01_1_BLUE 20:16 -#define VIDEO_ALPHA_COLOR_LOOKUP_01_0 15:0 -#define VIDEO_ALPHA_COLOR_LOOKUP_01_0_RED 15:11 -#define VIDEO_ALPHA_COLOR_LOOKUP_01_0_GREEN 10:5 -#define VIDEO_ALPHA_COLOR_LOOKUP_01_0_BLUE 4:0 +#define VIDEO_ALPHA_COLOR_LOOKUP_01_1_MASK (0xffff << 16) +#define VIDEO_ALPHA_COLOR_LOOKUP_01_1_RED_MASK (0x1f << 27) +#define VIDEO_ALPHA_COLOR_LOOKUP_01_1_GREEN_MASK (0x3f << 21) +#define VIDEO_ALPHA_COLOR_LOOKUP_01_1_BLUE_MASK (0x1f << 16) +#define VIDEO_ALPHA_COLOR_LOOKUP_01_0_MASK 0xffff +#define VIDEO_ALPHA_COLOR_LOOKUP_01_0_RED_MASK (0x1f << 11) +#define VIDEO_ALPHA_COLOR_LOOKUP_01_0_GREEN_MASK (0x3f << 5) +#define VIDEO_ALPHA_COLOR_LOOKUP_01_0_BLUE_MASK 0x1f #define VIDEO_ALPHA_COLOR_LOOKUP_23 0x0800A8 -#define VIDEO_ALPHA_COLOR_LOOKUP_23_3 31:16 -#define VIDEO_ALPHA_COLOR_LOOKUP_23_3_RED 31:27 -#define VIDEO_ALPHA_COLOR_LOOKUP_23_3_GREEN 26:21 -#define VIDEO_ALPHA_COLOR_LOOKUP_23_3_BLUE 20:16 -#define VIDEO_ALPHA_COLOR_LOOKUP_23_2 15:0 -#define VIDEO_ALPHA_COLOR_LOOKUP_23_2_RED 15:11 -#define VIDEO_ALPHA_COLOR_LOOKUP_23_2_GREEN 10:5 -#define VIDEO_ALPHA_COLOR_LOOKUP_23_2_BLUE 4:0 +#define VIDEO_ALPHA_COLOR_LOOKUP_23_3_MASK (0xffff << 16) +#define VIDEO_ALPHA_COLOR_LOOKUP_23_3_RED_MASK (0x1f << 27) +#define VIDEO_ALPHA_COLOR_LOOKUP_23_3_GREEN_MASK (0x3f << 21) +#define VIDEO_ALPHA_COLOR_LOOKUP_23_3_BLUE_MASK (0x1f << 16) +#define VIDEO_ALPHA_COLOR_LOOKUP_23_2_MASK 0xffff +#define VIDEO_ALPHA_COLOR_LOOKUP_23_2_RED_MASK (0x1f << 11) +#define VIDEO_ALPHA_COLOR_LOOKUP_23_2_GREEN_MASK (0x3f << 5) +#define VIDEO_ALPHA_COLOR_LOOKUP_23_2_BLUE_MASK 0x1f #define VIDEO_ALPHA_COLOR_LOOKUP_45 0x0800AC -#define VIDEO_ALPHA_COLOR_LOOKUP_45_5 31:16 -#define VIDEO_ALPHA_COLOR_LOOKUP_45_5_RED 31:27 -#define VIDEO_ALPHA_COLOR_LOOKUP_45_5_GREEN 26:21 -#define VIDEO_ALPHA_COLOR_LOOKUP_45_5_BLUE 20:16 -#define VIDEO_ALPHA_COLOR_LOOKUP_45_4 15:0 -#define VIDEO_ALPHA_COLOR_LOOKUP_45_4_RED 15:11 -#define VIDEO_ALPHA_COLOR_LOOKUP_45_4_GREEN 10:5 -#define VIDEO_ALPHA_COLOR_LOOKUP_45_4_BLUE 4:0 +#define VIDEO_ALPHA_COLOR_LOOKUP_45_5_MASK (0xffff << 16) +#define VIDEO_ALPHA_COLOR_LOOKUP_45_5_RED_MASK (0x1f << 27) +#define VIDEO_ALPHA_COLOR_LOOKUP_45_5_GREEN_MASK (0x3f << 21) +#define VIDEO_ALPHA_COLOR_LOOKUP_45_5_BLUE_MASK (0x1f << 16) +#define VIDEO_ALPHA_COLOR_LOOKUP_45_4_MASK 0xffff +#define VIDEO_ALPHA_COLOR_LOOKUP_45_4_RED_MASK (0x1f << 11) +#define VIDEO_ALPHA_COLOR_LOOKUP_45_4_GREEN_MASK (0x3f << 5) +#define VIDEO_ALPHA_COLOR_LOOKUP_45_4_BLUE_MASK 0x1f #define VIDEO_ALPHA_COLOR_LOOKUP_67 0x0800B0 -#define VIDEO_ALPHA_COLOR_LOOKUP_67_7 31:16 -#define VIDEO_ALPHA_COLOR_LOOKUP_67_7_RED 31:27 -#define VIDEO_ALPHA_COLOR_LOOKUP_67_7_GREEN 26:21 -#define VIDEO_ALPHA_COLOR_LOOKUP_67_7_BLUE 20:16 -#define VIDEO_ALPHA_COLOR_LOOKUP_67_6 15:0 -#define VIDEO_ALPHA_COLOR_LOOKUP_67_6_RED 15:11 -#define VIDEO_ALPHA_COLOR_LOOKUP_67_6_GREEN 10:5 -#define VIDEO_ALPHA_COLOR_LOOKUP_67_6_BLUE 4:0 +#define VIDEO_ALPHA_COLOR_LOOKUP_67_7_MASK (0xffff << 16) +#define VIDEO_ALPHA_COLOR_LOOKUP_67_7_RED_MASK (0x1f << 27) +#define VIDEO_ALPHA_COLOR_LOOKUP_67_7_GREEN_MASK (0x3f << 21) +#define VIDEO_ALPHA_COLOR_LOOKUP_67_7_BLUE_MASK (0x1f << 16) +#define VIDEO_ALPHA_COLOR_LOOKUP_67_6_MASK 0xffff +#define VIDEO_ALPHA_COLOR_LOOKUP_67_6_RED_MASK (0x1f << 11) +#define VIDEO_ALPHA_COLOR_LOOKUP_67_6_GREEN_MASK (0x3f << 5) +#define VIDEO_ALPHA_COLOR_LOOKUP_67_6_BLUE_MASK 0x1f #define VIDEO_ALPHA_COLOR_LOOKUP_89 0x0800B4 -#define VIDEO_ALPHA_COLOR_LOOKUP_89_9 31:16 -#define VIDEO_ALPHA_COLOR_LOOKUP_89_9_RED 31:27 -#define VIDEO_ALPHA_COLOR_LOOKUP_89_9_GREEN 26:21 -#define VIDEO_ALPHA_COLOR_LOOKUP_89_9_BLUE 20:16 -#define VIDEO_ALPHA_COLOR_LOOKUP_89_8 15:0 -#define VIDEO_ALPHA_COLOR_LOOKUP_89_8_RED 15:11 -#define VIDEO_ALPHA_COLOR_LOOKUP_89_8_GREEN 10:5 -#define VIDEO_ALPHA_COLOR_LOOKUP_89_8_BLUE 4:0 +#define VIDEO_ALPHA_COLOR_LOOKUP_89_9_MASK (0xffff << 16) +#define VIDEO_ALPHA_COLOR_LOOKUP_89_9_RED_MASK (0x1f << 27) +#define VIDEO_ALPHA_COLOR_LOOKUP_89_9_GREEN_MASK (0x3f << 21) +#define VIDEO_ALPHA_COLOR_LOOKUP_89_9_BLUE_MASK (0x1f << 16) +#define VIDEO_ALPHA_COLOR_LOOKUP_89_8_MASK 0xffff +#define VIDEO_ALPHA_COLOR_LOOKUP_89_8_RED_MASK (0x1f << 11) +#define VIDEO_ALPHA_COLOR_LOOKUP_89_8_GREEN_MASK (0x3f << 5) +#define VIDEO_ALPHA_COLOR_LOOKUP_89_8_BLUE_MASK 0x1f #define VIDEO_ALPHA_COLOR_LOOKUP_AB 0x0800B8 -#define VIDEO_ALPHA_COLOR_LOOKUP_AB_B 31:16 -#define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_RED 31:27 -#define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_GREEN 26:21 -#define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_BLUE 20:16 -#define VIDEO_ALPHA_COLOR_LOOKUP_AB_A 15:0 -#define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_RED 15:11 -#define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_GREEN 10:5 -#define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_BLUE 4:0 +#define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_MASK (0xffff << 16) +#define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_RED_MASK (0x1f << 27) +#define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_GREEN_MASK (0x3f << 21) +#define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_BLUE_MASK (0x1f << 16) +#define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_MASK 0xffff +#define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_RED_MASK (0x1f << 11) +#define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_GREEN_MASK (0x3f << 5) +#define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_BLUE_MASK 0x1f #define VIDEO_ALPHA_COLOR_LOOKUP_CD 0x0800BC -#define VIDEO_ALPHA_COLOR_LOOKUP_CD_D 31:16 -#define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_RED 31:27 -#define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_GREEN 26:21 -#define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_BLUE 20:16 -#define VIDEO_ALPHA_COLOR_LOOKUP_CD_C 15:0 -#define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_RED 15:11 -#define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_GREEN 10:5 -#define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_BLUE 4:0 +#define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_MASK (0xffff << 16) +#define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_RED_MASK (0x1f << 27) +#define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_GREEN_MASK (0x3f << 21) +#define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_BLUE_MASK (0x1f << 16) +#define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_MASK 0xffff +#define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_RED_MASK (0x1f << 11) +#define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_GREEN_MASK (0x3f << 5) +#define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_BLUE_MASK 0x1f #define VIDEO_ALPHA_COLOR_LOOKUP_EF 0x0800C0 -#define VIDEO_ALPHA_COLOR_LOOKUP_EF_F 31:16 -#define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_RED 31:27 -#define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_GREEN 26:21 -#define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_BLUE 20:16 -#define VIDEO_ALPHA_COLOR_LOOKUP_EF_E 15:0 -#define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_RED 15:11 -#define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_GREEN 10:5 -#define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_BLUE 4:0 +#define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_MASK (0xffff << 16) +#define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_RED_MASK (0x1f << 27) +#define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_GREEN_MASK (0x3f << 21) +#define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_BLUE_MASK (0x1f << 16) +#define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_MASK 0xffff +#define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_RED_MASK (0x1f << 11) +#define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_GREEN_MASK (0x3f << 5) +#define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_BLUE_MASK 0x1f /* Panel Cursor Control */ #define PANEL_HWC_ADDRESS 0x0800F0 -#define PANEL_HWC_ADDRESS_ENABLE 31:31 -#define PANEL_HWC_ADDRESS_ENABLE_DISABLE 0 -#define PANEL_HWC_ADDRESS_ENABLE_ENABLE 1 -#define PANEL_HWC_ADDRESS_EXT 27:27 -#define PANEL_HWC_ADDRESS_EXT_LOCAL 0 -#define PANEL_HWC_ADDRESS_EXT_EXTERNAL 1 -#define PANEL_HWC_ADDRESS_ADDRESS 25:0 +#define PANEL_HWC_ADDRESS_ENABLE BIT(31) +#define PANEL_HWC_ADDRESS_EXT BIT(27) +#define PANEL_HWC_ADDRESS_ADDRESS_MASK 0x3ffffff #define PANEL_HWC_LOCATION 0x0800F4 -#define PANEL_HWC_LOCATION_TOP 27:27 -#define PANEL_HWC_LOCATION_TOP_INSIDE 0 -#define PANEL_HWC_LOCATION_TOP_OUTSIDE 1 -#define PANEL_HWC_LOCATION_Y 26:16 -#define PANEL_HWC_LOCATION_LEFT 11:11 -#define PANEL_HWC_LOCATION_LEFT_INSIDE 0 -#define PANEL_HWC_LOCATION_LEFT_OUTSIDE 1 -#define PANEL_HWC_LOCATION_X 10:0 +#define PANEL_HWC_LOCATION_TOP BIT(27) +#define PANEL_HWC_LOCATION_Y_MASK (0x7ff << 16) +#define PANEL_HWC_LOCATION_LEFT BIT(11) +#define PANEL_HWC_LOCATION_X_MASK 0x7ff #define PANEL_HWC_COLOR_12 0x0800F8 -#define PANEL_HWC_COLOR_12_2_RGB565 31:16 -#define PANEL_HWC_COLOR_12_1_RGB565 15:0 +#define PANEL_HWC_COLOR_12_2_RGB565_MASK (0xffff << 16) +#define PANEL_HWC_COLOR_12_1_RGB565_MASK 0xffff #define PANEL_HWC_COLOR_3 0x0800FC -#define PANEL_HWC_COLOR_3_RGB565 15:0 +#define PANEL_HWC_COLOR_3_RGB565_MASK 0xffff /* Old Definitions +++ */ #define PANEL_HWC_COLOR_01 0x0800F8 -#define PANEL_HWC_COLOR_01_1_RED 31:27 -#define PANEL_HWC_COLOR_01_1_GREEN 26:21 -#define PANEL_HWC_COLOR_01_1_BLUE 20:16 -#define PANEL_HWC_COLOR_01_0_RED 15:11 -#define PANEL_HWC_COLOR_01_0_GREEN 10:5 -#define PANEL_HWC_COLOR_01_0_BLUE 4:0 +#define PANEL_HWC_COLOR_01_1_RED_MASK (0x1f << 27) +#define PANEL_HWC_COLOR_01_1_GREEN_MASK (0x3f << 21) +#define PANEL_HWC_COLOR_01_1_BLUE_MASK (0x1f << 16) +#define PANEL_HWC_COLOR_01_0_RED_MASK (0x1f << 11) +#define PANEL_HWC_COLOR_01_0_GREEN_MASK (0x3f << 5) +#define PANEL_HWC_COLOR_01_0_BLUE_MASK 0x1f #define PANEL_HWC_COLOR_2 0x0800FC -#define PANEL_HWC_COLOR_2_RED 15:11 -#define PANEL_HWC_COLOR_2_GREEN 10:5 -#define PANEL_HWC_COLOR_2_BLUE 4:0 +#define PANEL_HWC_COLOR_2_RED_MASK (0x1f << 11) +#define PANEL_HWC_COLOR_2_GREEN_MASK (0x3f << 5) +#define PANEL_HWC_COLOR_2_BLUE_MASK 0x1f /* Old Definitions --- */ /* Alpha Control */ #define ALPHA_DISPLAY_CTRL 0x080100 -#define ALPHA_DISPLAY_CTRL_SELECT 28:28 -#define ALPHA_DISPLAY_CTRL_SELECT_PER_PIXEL 0 -#define ALPHA_DISPLAY_CTRL_SELECT_ALPHA 1 -#define ALPHA_DISPLAY_CTRL_ALPHA 27:24 -#define ALPHA_DISPLAY_CTRL_FIFO 17:16 -#define ALPHA_DISPLAY_CTRL_FIFO_1 0 -#define ALPHA_DISPLAY_CTRL_FIFO_3 1 -#define ALPHA_DISPLAY_CTRL_FIFO_7 2 -#define ALPHA_DISPLAY_CTRL_FIFO_11 3 -#define ALPHA_DISPLAY_CTRL_PIXEL 7:4 -#define ALPHA_DISPLAY_CTRL_CHROMA_KEY 3:3 -#define ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE 0 -#define ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE 1 -#define ALPHA_DISPLAY_CTRL_PLANE 2:2 -#define ALPHA_DISPLAY_CTRL_PLANE_DISABLE 0 -#define ALPHA_DISPLAY_CTRL_PLANE_ENABLE 1 -#define ALPHA_DISPLAY_CTRL_FORMAT 1:0 -#define ALPHA_DISPLAY_CTRL_FORMAT_16 1 -#define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4 2 -#define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4 3 +#define ALPHA_DISPLAY_CTRL_SELECT BIT(28) +#define ALPHA_DISPLAY_CTRL_ALPHA_MASK (0xf << 24) +#define ALPHA_DISPLAY_CTRL_FIFO_MASK (0x3 << 16) +#define ALPHA_DISPLAY_CTRL_FIFO_1 (0x0 << 16) +#define ALPHA_DISPLAY_CTRL_FIFO_3 (0x1 << 16) +#define ALPHA_DISPLAY_CTRL_FIFO_7 (0x2 << 16) +#define ALPHA_DISPLAY_CTRL_FIFO_11 (0x3 << 16) +#define ALPHA_DISPLAY_CTRL_PIXEL_MASK (0xf << 4) +#define ALPHA_DISPLAY_CTRL_CHROMA_KEY BIT(3) +#define ALPHA_DISPLAY_CTRL_FORMAT_MASK 0x3 +#define ALPHA_DISPLAY_CTRL_FORMAT_16 0x1 +#define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4 0x2 +#define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4 0x3 #define ALPHA_FB_ADDRESS 0x080104 -#define ALPHA_FB_ADDRESS_STATUS 31:31 -#define ALPHA_FB_ADDRESS_STATUS_CURRENT 0 -#define ALPHA_FB_ADDRESS_STATUS_PENDING 1 -#define ALPHA_FB_ADDRESS_EXT 27:27 -#define ALPHA_FB_ADDRESS_EXT_LOCAL 0 -#define ALPHA_FB_ADDRESS_EXT_EXTERNAL 1 -#define ALPHA_FB_ADDRESS_ADDRESS 25:0 +#define ALPHA_FB_ADDRESS_STATUS BIT(31) +#define ALPHA_FB_ADDRESS_EXT BIT(27) +#define ALPHA_FB_ADDRESS_ADDRESS_MASK 0x3ffffff #define ALPHA_FB_WIDTH 0x080108 -#define ALPHA_FB_WIDTH_WIDTH 29:16 -#define ALPHA_FB_WIDTH_OFFSET 13:0 +#define ALPHA_FB_WIDTH_WIDTH_MASK (0x3fff << 16) +#define ALPHA_FB_WIDTH_OFFSET_MASK 0x3fff #define ALPHA_PLANE_TL 0x08010C -#define ALPHA_PLANE_TL_TOP 26:16 -#define ALPHA_PLANE_TL_LEFT 10:0 +#define ALPHA_PLANE_TL_TOP_MASK (0x7ff << 16) +#define ALPHA_PLANE_TL_LEFT_MASK 0x7ff #define ALPHA_PLANE_BR 0x080110 -#define ALPHA_PLANE_BR_BOTTOM 26:16 -#define ALPHA_PLANE_BR_RIGHT 10:0 +#define ALPHA_PLANE_BR_BOTTOM_MASK (0x7ff << 16) +#define ALPHA_PLANE_BR_RIGHT_MASK 0x7ff #define ALPHA_CHROMA_KEY 0x080114 -#define ALPHA_CHROMA_KEY_MASK 31:16 -#define ALPHA_CHROMA_KEY_VALUE 15:0 +#define ALPHA_CHROMA_KEY_MASK_MASK (0xffff << 16) +#define ALPHA_CHROMA_KEY_VALUE_MASK 0xffff #define ALPHA_COLOR_LOOKUP_01 0x080118 -#define ALPHA_COLOR_LOOKUP_01_1 31:16 -#define ALPHA_COLOR_LOOKUP_01_1_RED 31:27 -#define ALPHA_COLOR_LOOKUP_01_1_GREEN 26:21 -#define ALPHA_COLOR_LOOKUP_01_1_BLUE 20:16 -#define ALPHA_COLOR_LOOKUP_01_0 15:0 -#define ALPHA_COLOR_LOOKUP_01_0_RED 15:11 -#define ALPHA_COLOR_LOOKUP_01_0_GREEN 10:5 -#define ALPHA_COLOR_LOOKUP_01_0_BLUE 4:0 +#define ALPHA_COLOR_LOOKUP_01_1_MASK (0xffff << 16) +#define ALPHA_COLOR_LOOKUP_01_1_RED_MASK (0x1f << 27) +#define ALPHA_COLOR_LOOKUP_01_1_GREEN_MASK (0x3f << 21) +#define ALPHA_COLOR_LOOKUP_01_1_BLUE_MASK (0x1f << 16) +#define ALPHA_COLOR_LOOKUP_01_0_MASK 0xffff +#define ALPHA_COLOR_LOOKUP_01_0_RED_MASK (0x1f << 11) +#define ALPHA_COLOR_LOOKUP_01_0_GREEN_MASK (0x3f << 5) +#define ALPHA_COLOR_LOOKUP_01_0_BLUE_MASK 0x1f #define ALPHA_COLOR_LOOKUP_23 0x08011C -#define ALPHA_COLOR_LOOKUP_23_3 31:16 -#define ALPHA_COLOR_LOOKUP_23_3_RED 31:27 -#define ALPHA_COLOR_LOOKUP_23_3_GREEN 26:21 -#define ALPHA_COLOR_LOOKUP_23_3_BLUE 20:16 -#define ALPHA_COLOR_LOOKUP_23_2 15:0 -#define ALPHA_COLOR_LOOKUP_23_2_RED 15:11 -#define ALPHA_COLOR_LOOKUP_23_2_GREEN 10:5 -#define ALPHA_COLOR_LOOKUP_23_2_BLUE 4:0 +#define ALPHA_COLOR_LOOKUP_23_3_MASK (0xffff << 16) +#define ALPHA_COLOR_LOOKUP_23_3_RED_MASK (0x1f << 27) +#define ALPHA_COLOR_LOOKUP_23_3_GREEN_MASK (0x3f << 21) +#define ALPHA_COLOR_LOOKUP_23_3_BLUE_MASK (0x1f << 16) +#define ALPHA_COLOR_LOOKUP_23_2_MASK 0xffff +#define ALPHA_COLOR_LOOKUP_23_2_RED_MASK (0x1f << 11) +#define ALPHA_COLOR_LOOKUP_23_2_GREEN_MASK (0x3f << 5) +#define ALPHA_COLOR_LOOKUP_23_2_BLUE_MASK 0x1f #define ALPHA_COLOR_LOOKUP_45 0x080120 -#define ALPHA_COLOR_LOOKUP_45_5 31:16 -#define ALPHA_COLOR_LOOKUP_45_5_RED 31:27 -#define ALPHA_COLOR_LOOKUP_45_5_GREEN 26:21 -#define ALPHA_COLOR_LOOKUP_45_5_BLUE 20:16 -#define ALPHA_COLOR_LOOKUP_45_4 15:0 -#define ALPHA_COLOR_LOOKUP_45_4_RED 15:11 -#define ALPHA_COLOR_LOOKUP_45_4_GREEN 10:5 -#define ALPHA_COLOR_LOOKUP_45_4_BLUE 4:0 +#define ALPHA_COLOR_LOOKUP_45_5_MASK (0xffff << 16) +#define ALPHA_COLOR_LOOKUP_45_5_RED_MASK (0x1f << 27) +#define ALPHA_COLOR_LOOKUP_45_5_GREEN_MASK (0x3f << 21) +#define ALPHA_COLOR_LOOKUP_45_5_BLUE_MASK (0x1f << 16) +#define ALPHA_COLOR_LOOKUP_45_4_MASK 0xffff +#define ALPHA_COLOR_LOOKUP_45_4_RED_MASK (0x1f << 11) +#define ALPHA_COLOR_LOOKUP_45_4_GREEN_MASK (0x3f << 5) +#define ALPHA_COLOR_LOOKUP_45_4_BLUE_MASK 0x1f #define ALPHA_COLOR_LOOKUP_67 0x080124 -#define ALPHA_COLOR_LOOKUP_67_7 31:16 -#define ALPHA_COLOR_LOOKUP_67_7_RED 31:27 -#define ALPHA_COLOR_LOOKUP_67_7_GREEN 26:21 -#define ALPHA_COLOR_LOOKUP_67_7_BLUE 20:16 -#define ALPHA_COLOR_LOOKUP_67_6 15:0 -#define ALPHA_COLOR_LOOKUP_67_6_RED 15:11 -#define ALPHA_COLOR_LOOKUP_67_6_GREEN 10:5 -#define ALPHA_COLOR_LOOKUP_67_6_BLUE 4:0 +#define ALPHA_COLOR_LOOKUP_67_7_MASK (0xffff << 16) +#define ALPHA_COLOR_LOOKUP_67_7_RED_MASK (0x1f << 27) +#define ALPHA_COLOR_LOOKUP_67_7_GREEN_MASK (0x3f << 21) +#define ALPHA_COLOR_LOOKUP_67_7_BLUE_MASK (0x1f << 16) +#define ALPHA_COLOR_LOOKUP_67_6_MASK 0xffff +#define ALPHA_COLOR_LOOKUP_67_6_RED_MASK (0x1f << 11) +#define ALPHA_COLOR_LOOKUP_67_6_GREEN_MASK (0x3f << 5) +#define ALPHA_COLOR_LOOKUP_67_6_BLUE_MASK 0x1f #define ALPHA_COLOR_LOOKUP_89 0x080128 -#define ALPHA_COLOR_LOOKUP_89_9 31:16 -#define ALPHA_COLOR_LOOKUP_89_9_RED 31:27 -#define ALPHA_COLOR_LOOKUP_89_9_GREEN 26:21 -#define ALPHA_COLOR_LOOKUP_89_9_BLUE 20:16 -#define ALPHA_COLOR_LOOKUP_89_8 15:0 -#define ALPHA_COLOR_LOOKUP_89_8_RED 15:11 -#define ALPHA_COLOR_LOOKUP_89_8_GREEN 10:5 -#define ALPHA_COLOR_LOOKUP_89_8_BLUE 4:0 +#define ALPHA_COLOR_LOOKUP_89_9_MASK (0xffff << 16) +#define ALPHA_COLOR_LOOKUP_89_9_RED_MASK (0x1f << 27) +#define ALPHA_COLOR_LOOKUP_89_9_GREEN_MASK (0x3f << 21) +#define ALPHA_COLOR_LOOKUP_89_9_BLUE_MASK (0x1f << 16) +#define ALPHA_COLOR_LOOKUP_89_8_MASK 0xffff +#define ALPHA_COLOR_LOOKUP_89_8_RED_MASK (0x1f << 11) +#define ALPHA_COLOR_LOOKUP_89_8_GREEN_MASK (0x3f << 5) +#define ALPHA_COLOR_LOOKUP_89_8_BLUE_MASK 0x1f #define ALPHA_COLOR_LOOKUP_AB 0x08012C -#define ALPHA_COLOR_LOOKUP_AB_B 31:16 -#define ALPHA_COLOR_LOOKUP_AB_B_RED 31:27 -#define ALPHA_COLOR_LOOKUP_AB_B_GREEN 26:21 -#define ALPHA_COLOR_LOOKUP_AB_B_BLUE 20:16 -#define ALPHA_COLOR_LOOKUP_AB_A 15:0 -#define ALPHA_COLOR_LOOKUP_AB_A_RED 15:11 -#define ALPHA_COLOR_LOOKUP_AB_A_GREEN 10:5 -#define ALPHA_COLOR_LOOKUP_AB_A_BLUE 4:0 +#define ALPHA_COLOR_LOOKUP_AB_B_MASK (0xffff << 16) +#define ALPHA_COLOR_LOOKUP_AB_B_RED_MASK (0x1f << 27) +#define ALPHA_COLOR_LOOKUP_AB_B_GREEN_MASK (0x3f << 21) +#define ALPHA_COLOR_LOOKUP_AB_B_BLUE_MASK (0x1f << 16) +#define ALPHA_COLOR_LOOKUP_AB_A_MASK 0xffff +#define ALPHA_COLOR_LOOKUP_AB_A_RED_MASK (0x1f << 11) +#define ALPHA_COLOR_LOOKUP_AB_A_GREEN_MASK (0x3f << 5) +#define ALPHA_COLOR_LOOKUP_AB_A_BLUE_MASK 0x1f #define ALPHA_COLOR_LOOKUP_CD 0x080130 -#define ALPHA_COLOR_LOOKUP_CD_D 31:16 -#define ALPHA_COLOR_LOOKUP_CD_D_RED 31:27 -#define ALPHA_COLOR_LOOKUP_CD_D_GREEN 26:21 -#define ALPHA_COLOR_LOOKUP_CD_D_BLUE 20:16 -#define ALPHA_COLOR_LOOKUP_CD_C 15:0 -#define ALPHA_COLOR_LOOKUP_CD_C_RED 15:11 -#define ALPHA_COLOR_LOOKUP_CD_C_GREEN 10:5 -#define ALPHA_COLOR_LOOKUP_CD_C_BLUE 4:0 +#define ALPHA_COLOR_LOOKUP_CD_D_MASK (0xffff << 16) +#define ALPHA_COLOR_LOOKUP_CD_D_RED_MASK (0x1f << 27) +#define ALPHA_COLOR_LOOKUP_CD_D_GREEN_MASK (0x3f << 21) +#define ALPHA_COLOR_LOOKUP_CD_D_BLUE_MASK (0x1f << 16) +#define ALPHA_COLOR_LOOKUP_CD_C_MASK 0xffff +#define ALPHA_COLOR_LOOKUP_CD_C_RED_MASK (0x1f << 11) +#define ALPHA_COLOR_LOOKUP_CD_C_GREEN_MASK (0x3f << 5) +#define ALPHA_COLOR_LOOKUP_CD_C_BLUE_MASK 0x1f #define ALPHA_COLOR_LOOKUP_EF 0x080134 -#define ALPHA_COLOR_LOOKUP_EF_F 31:16 -#define ALPHA_COLOR_LOOKUP_EF_F_RED 31:27 -#define ALPHA_COLOR_LOOKUP_EF_F_GREEN 26:21 -#define ALPHA_COLOR_LOOKUP_EF_F_BLUE 20:16 -#define ALPHA_COLOR_LOOKUP_EF_E 15:0 -#define ALPHA_COLOR_LOOKUP_EF_E_RED 15:11 -#define ALPHA_COLOR_LOOKUP_EF_E_GREEN 10:5 -#define ALPHA_COLOR_LOOKUP_EF_E_BLUE 4:0 +#define ALPHA_COLOR_LOOKUP_EF_F_MASK (0xffff << 16) +#define ALPHA_COLOR_LOOKUP_EF_F_RED_MASK (0x1f << 27) +#define ALPHA_COLOR_LOOKUP_EF_F_GREEN_MASK (0x3f << 21) +#define ALPHA_COLOR_LOOKUP_EF_F_BLUE_MASK (0x1f << 16) +#define ALPHA_COLOR_LOOKUP_EF_E_MASK 0xffff +#define ALPHA_COLOR_LOOKUP_EF_E_RED_MASK (0x1f << 11) +#define ALPHA_COLOR_LOOKUP_EF_E_GREEN_MASK (0x3f << 5) +#define ALPHA_COLOR_LOOKUP_EF_E_BLUE_MASK 0x1f /* CRT Graphics Control */ #define CRT_DISPLAY_CTRL 0x080200 -#define CRT_DISPLAY_CTRL_RESERVED_1_MASK 31:27 -#define CRT_DISPLAY_CTRL_RESERVED_1_MASK_DISABLE 0 -#define CRT_DISPLAY_CTRL_RESERVED_1_MASK_ENABLE 0x1F +#define CRT_DISPLAY_CTRL_RESERVED_MASK 0xfb008200 /* SM750LE definition */ -#define CRT_DISPLAY_CTRL_DPMS 31:30 -#define CRT_DISPLAY_CTRL_DPMS_0 0 -#define CRT_DISPLAY_CTRL_DPMS_1 1 -#define CRT_DISPLAY_CTRL_DPMS_2 2 -#define CRT_DISPLAY_CTRL_DPMS_3 3 -#define CRT_DISPLAY_CTRL_CLK 29:27 -#define CRT_DISPLAY_CTRL_CLK_PLL25 0 -#define CRT_DISPLAY_CTRL_CLK_PLL41 1 -#define CRT_DISPLAY_CTRL_CLK_PLL62 2 -#define CRT_DISPLAY_CTRL_CLK_PLL65 3 -#define CRT_DISPLAY_CTRL_CLK_PLL74 4 -#define CRT_DISPLAY_CTRL_CLK_PLL80 5 -#define CRT_DISPLAY_CTRL_CLK_PLL108 6 -#define CRT_DISPLAY_CTRL_CLK_RESERVED 7 -#define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC 26:26 -#define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_DISABLE 1 -#define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_ENABLE 0 - - -#define CRT_DISPLAY_CTRL_RESERVED_2_MASK 25:24 -#define CRT_DISPLAY_CTRL_RESERVED_2_MASK_ENABLE 3 -#define CRT_DISPLAY_CTRL_RESERVED_2_MASK_DISABLE 0 +#define CRT_DISPLAY_CTRL_DPMS_SHIFT 30 +#define CRT_DISPLAY_CTRL_DPMS_MASK (0x3 << 30) +#define CRT_DISPLAY_CTRL_DPMS_0 (0x0 << 30) +#define CRT_DISPLAY_CTRL_DPMS_1 (0x1 << 30) +#define CRT_DISPLAY_CTRL_DPMS_2 (0x2 << 30) +#define CRT_DISPLAY_CTRL_DPMS_3 (0x3 << 30) +#define CRT_DISPLAY_CTRL_CLK_MASK (0x7 << 27) +#define CRT_DISPLAY_CTRL_CLK_PLL25 (0x0 << 27) +#define CRT_DISPLAY_CTRL_CLK_PLL41 (0x1 << 27) +#define CRT_DISPLAY_CTRL_CLK_PLL62 (0x2 << 27) +#define CRT_DISPLAY_CTRL_CLK_PLL65 (0x3 << 27) +#define CRT_DISPLAY_CTRL_CLK_PLL74 (0x4 << 27) +#define CRT_DISPLAY_CTRL_CLK_PLL80 (0x5 << 27) +#define CRT_DISPLAY_CTRL_CLK_PLL108 (0x6 << 27) +#define CRT_DISPLAY_CTRL_CLK_RESERVED (0x7 << 27) +#define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC BIT(26) /* SM750LE definition */ -#define CRT_DISPLAY_CTRL_CRTSELECT 25:25 -#define CRT_DISPLAY_CTRL_CRTSELECT_VGA 0 -#define CRT_DISPLAY_CTRL_CRTSELECT_CRT 1 -#define CRT_DISPLAY_CTRL_RGBBIT 24:24 -#define CRT_DISPLAY_CTRL_RGBBIT_24BIT 0 -#define CRT_DISPLAY_CTRL_RGBBIT_12BIT 1 - - -#define CRT_DISPLAY_CTRL_RESERVED_3_MASK 15:15 -#define CRT_DISPLAY_CTRL_RESERVED_3_MASK_DISABLE 0 -#define CRT_DISPLAY_CTRL_RESERVED_3_MASK_ENABLE 1 - -#define CRT_DISPLAY_CTRL_RESERVED_4_MASK 9:9 -#define CRT_DISPLAY_CTRL_RESERVED_4_MASK_DISABLE 0 -#define CRT_DISPLAY_CTRL_RESERVED_4_MASK_ENABLE 1 +#define CRT_DISPLAY_CTRL_CRTSELECT BIT(25) +#define CRT_DISPLAY_CTRL_RGBBIT BIT(24) #ifndef VALIDATION_CHIP - #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC 26:26 - #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_DISABLE 1 - #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_ENABLE 0 - #define CRT_DISPLAY_CTRL_CENTERING 24:24 - #define CRT_DISPLAY_CTRL_CENTERING_DISABLE 0 - #define CRT_DISPLAY_CTRL_CENTERING_ENABLE 1 + #define CRT_DISPLAY_CTRL_CENTERING BIT(24) #endif -#define CRT_DISPLAY_CTRL_LOCK_TIMING 23:23 -#define CRT_DISPLAY_CTRL_LOCK_TIMING_DISABLE 0 -#define CRT_DISPLAY_CTRL_LOCK_TIMING_ENABLE 1 -#define CRT_DISPLAY_CTRL_EXPANSION 22:22 -#define CRT_DISPLAY_CTRL_EXPANSION_DISABLE 0 -#define CRT_DISPLAY_CTRL_EXPANSION_ENABLE 1 -#define CRT_DISPLAY_CTRL_VERTICAL_MODE 21:21 -#define CRT_DISPLAY_CTRL_VERTICAL_MODE_REPLICATE 0 -#define CRT_DISPLAY_CTRL_VERTICAL_MODE_INTERPOLATE 1 -#define CRT_DISPLAY_CTRL_HORIZONTAL_MODE 20:20 -#define CRT_DISPLAY_CTRL_HORIZONTAL_MODE_REPLICATE 0 -#define CRT_DISPLAY_CTRL_HORIZONTAL_MODE_INTERPOLATE 1 -#define CRT_DISPLAY_CTRL_SELECT 19:18 -#define CRT_DISPLAY_CTRL_SELECT_PANEL 0 -#define CRT_DISPLAY_CTRL_SELECT_VGA 1 -#define CRT_DISPLAY_CTRL_SELECT_CRT 2 -#define CRT_DISPLAY_CTRL_FIFO 17:16 -#define CRT_DISPLAY_CTRL_FIFO_1 0 -#define CRT_DISPLAY_CTRL_FIFO_3 1 -#define CRT_DISPLAY_CTRL_FIFO_7 2 -#define CRT_DISPLAY_CTRL_FIFO_11 3 -#define CRT_DISPLAY_CTRL_CLOCK_PHASE 14:14 -#define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH 0 -#define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW 1 -#define CRT_DISPLAY_CTRL_VSYNC_PHASE 13:13 -#define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH 0 -#define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW 1 -#define CRT_DISPLAY_CTRL_HSYNC_PHASE 12:12 -#define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH 0 -#define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW 1 -#define CRT_DISPLAY_CTRL_BLANK 10:10 -#define CRT_DISPLAY_CTRL_BLANK_OFF 0 -#define CRT_DISPLAY_CTRL_BLANK_ON 1 -#define CRT_DISPLAY_CTRL_TIMING 8:8 -#define CRT_DISPLAY_CTRL_TIMING_DISABLE 0 -#define CRT_DISPLAY_CTRL_TIMING_ENABLE 1 -#define CRT_DISPLAY_CTRL_PIXEL 7:4 -#define CRT_DISPLAY_CTRL_GAMMA 3:3 -#define CRT_DISPLAY_CTRL_GAMMA_DISABLE 0 -#define CRT_DISPLAY_CTRL_GAMMA_ENABLE 1 -#define CRT_DISPLAY_CTRL_PLANE 2:2 -#define CRT_DISPLAY_CTRL_PLANE_DISABLE 0 -#define CRT_DISPLAY_CTRL_PLANE_ENABLE 1 -#define CRT_DISPLAY_CTRL_FORMAT 1:0 -#define CRT_DISPLAY_CTRL_FORMAT_8 0 -#define CRT_DISPLAY_CTRL_FORMAT_16 1 -#define CRT_DISPLAY_CTRL_FORMAT_32 2 -#define CRT_DISPLAY_CTRL_RESERVED_BITS_MASK 0xFF000200 +#define CRT_DISPLAY_CTRL_LOCK_TIMING BIT(23) +#define CRT_DISPLAY_CTRL_EXPANSION BIT(22) +#define CRT_DISPLAY_CTRL_VERTICAL_MODE BIT(21) +#define CRT_DISPLAY_CTRL_HORIZONTAL_MODE BIT(20) +#define CRT_DISPLAY_CTRL_SELECT_SHIFT 18 +#define CRT_DISPLAY_CTRL_SELECT_MASK (0x3 << 18) +#define CRT_DISPLAY_CTRL_SELECT_PANEL (0x0 << 18) +#define CRT_DISPLAY_CTRL_SELECT_VGA (0x1 << 18) +#define CRT_DISPLAY_CTRL_SELECT_CRT (0x2 << 18) +#define CRT_DISPLAY_CTRL_FIFO_MASK (0x3 << 16) +#define CRT_DISPLAY_CTRL_FIFO_1 (0x0 << 16) +#define CRT_DISPLAY_CTRL_FIFO_3 (0x1 << 16) +#define CRT_DISPLAY_CTRL_FIFO_7 (0x2 << 16) +#define CRT_DISPLAY_CTRL_FIFO_11 (0x3 << 16) +#define CRT_DISPLAY_CTRL_BLANK BIT(10) +#define CRT_DISPLAY_CTRL_PIXEL_MASK (0xf << 4) +#define CRT_DISPLAY_CTRL_FORMAT_MASK (0x3 << 0) +#define CRT_DISPLAY_CTRL_FORMAT_8 (0x0 << 0) +#define CRT_DISPLAY_CTRL_FORMAT_16 (0x1 << 0) +#define CRT_DISPLAY_CTRL_FORMAT_32 (0x2 << 0) #define CRT_FB_ADDRESS 0x080204 -#define CRT_FB_ADDRESS_STATUS 31:31 -#define CRT_FB_ADDRESS_STATUS_CURRENT 0 -#define CRT_FB_ADDRESS_STATUS_PENDING 1 -#define CRT_FB_ADDRESS_EXT 27:27 -#define CRT_FB_ADDRESS_EXT_LOCAL 0 -#define CRT_FB_ADDRESS_EXT_EXTERNAL 1 -#define CRT_FB_ADDRESS_ADDRESS 25:0 +#define CRT_FB_ADDRESS_STATUS BIT(31) +#define CRT_FB_ADDRESS_EXT BIT(27) +#define CRT_FB_ADDRESS_ADDRESS_MASK 0x3ffffff #define CRT_FB_WIDTH 0x080208 -#define CRT_FB_WIDTH_WIDTH 29:16 -#define CRT_FB_WIDTH_OFFSET 13:0 +#define CRT_FB_WIDTH_WIDTH_SHIFT 16 +#define CRT_FB_WIDTH_WIDTH_MASK (0x3fff << 16) +#define CRT_FB_WIDTH_OFFSET_MASK 0x3fff #define CRT_HORIZONTAL_TOTAL 0x08020C -#define CRT_HORIZONTAL_TOTAL_TOTAL 27:16 -#define CRT_HORIZONTAL_TOTAL_DISPLAY_END 11:0 +#define CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT 16 +#define CRT_HORIZONTAL_TOTAL_TOTAL_MASK (0xfff << 16) +#define CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK 0xfff #define CRT_HORIZONTAL_SYNC 0x080210 -#define CRT_HORIZONTAL_SYNC_WIDTH 23:16 -#define CRT_HORIZONTAL_SYNC_START 11:0 +#define CRT_HORIZONTAL_SYNC_WIDTH_SHIFT 16 +#define CRT_HORIZONTAL_SYNC_WIDTH_MASK (0xff << 16) +#define CRT_HORIZONTAL_SYNC_START_MASK 0xfff #define CRT_VERTICAL_TOTAL 0x080214 -#define CRT_VERTICAL_TOTAL_TOTAL 26:16 -#define CRT_VERTICAL_TOTAL_DISPLAY_END 10:0 +#define CRT_VERTICAL_TOTAL_TOTAL_SHIFT 16 +#define CRT_VERTICAL_TOTAL_TOTAL_MASK (0x7ff << 16) +#define CRT_VERTICAL_TOTAL_DISPLAY_END_MASK (0x7ff) #define CRT_VERTICAL_SYNC 0x080218 -#define CRT_VERTICAL_SYNC_HEIGHT 21:16 -#define CRT_VERTICAL_SYNC_START 10:0 +#define CRT_VERTICAL_SYNC_HEIGHT_SHIFT 16 +#define CRT_VERTICAL_SYNC_HEIGHT_MASK (0x3f << 16) +#define CRT_VERTICAL_SYNC_START_MASK 0x7ff #define CRT_SIGNATURE_ANALYZER 0x08021C -#define CRT_SIGNATURE_ANALYZER_STATUS 31:16 -#define CRT_SIGNATURE_ANALYZER_ENABLE 3:3 -#define CRT_SIGNATURE_ANALYZER_ENABLE_DISABLE 0 -#define CRT_SIGNATURE_ANALYZER_ENABLE_ENABLE 1 -#define CRT_SIGNATURE_ANALYZER_RESET 2:2 -#define CRT_SIGNATURE_ANALYZER_RESET_NORMAL 0 -#define CRT_SIGNATURE_ANALYZER_RESET_RESET 1 -#define CRT_SIGNATURE_ANALYZER_SOURCE 1:0 +#define CRT_SIGNATURE_ANALYZER_STATUS_MASK (0xffff << 16) +#define CRT_SIGNATURE_ANALYZER_ENABLE BIT(3) +#define CRT_SIGNATURE_ANALYZER_RESET BIT(2) +#define CRT_SIGNATURE_ANALYZER_SOURCE_MASK 0x3 #define CRT_SIGNATURE_ANALYZER_SOURCE_RED 0 #define CRT_SIGNATURE_ANALYZER_SOURCE_GREEN 1 #define CRT_SIGNATURE_ANALYZER_SOURCE_BLUE 2 #define CRT_CURRENT_LINE 0x080220 -#define CRT_CURRENT_LINE_LINE 10:0 +#define CRT_CURRENT_LINE_LINE_MASK 0x7ff #define CRT_MONITOR_DETECT 0x080224 -#define CRT_MONITOR_DETECT_VALUE 25:25 -#define CRT_MONITOR_DETECT_VALUE_DISABLE 0 -#define CRT_MONITOR_DETECT_VALUE_ENABLE 1 -#define CRT_MONITOR_DETECT_ENABLE 24:24 -#define CRT_MONITOR_DETECT_ENABLE_DISABLE 0 -#define CRT_MONITOR_DETECT_ENABLE_ENABLE 1 -#define CRT_MONITOR_DETECT_RED 23:16 -#define CRT_MONITOR_DETECT_GREEN 15:8 -#define CRT_MONITOR_DETECT_BLUE 7:0 +#define CRT_MONITOR_DETECT_VALUE BIT(25) +#define CRT_MONITOR_DETECT_ENABLE BIT(24) +#define CRT_MONITOR_DETECT_RED_MASK (0xff << 16) +#define CRT_MONITOR_DETECT_GREEN_MASK (0xff << 8) +#define CRT_MONITOR_DETECT_BLUE_MASK 0xff #define CRT_SCALE 0x080228 -#define CRT_SCALE_VERTICAL_MODE 31:31 -#define CRT_SCALE_VERTICAL_MODE_EXPAND 0 -#define CRT_SCALE_VERTICAL_MODE_SHRINK 1 -#define CRT_SCALE_VERTICAL_SCALE 27:16 -#define CRT_SCALE_HORIZONTAL_MODE 15:15 -#define CRT_SCALE_HORIZONTAL_MODE_EXPAND 0 -#define CRT_SCALE_HORIZONTAL_MODE_SHRINK 1 -#define CRT_SCALE_HORIZONTAL_SCALE 11:0 +#define CRT_SCALE_VERTICAL_MODE BIT(31) +#define CRT_SCALE_VERTICAL_SCALE_MASK (0xfff << 16) +#define CRT_SCALE_HORIZONTAL_MODE BIT(15) +#define CRT_SCALE_HORIZONTAL_SCALE_MASK 0xfff /* CRT Cursor Control */ #define CRT_HWC_ADDRESS 0x080230 -#define CRT_HWC_ADDRESS_ENABLE 31:31 -#define CRT_HWC_ADDRESS_ENABLE_DISABLE 0 -#define CRT_HWC_ADDRESS_ENABLE_ENABLE 1 -#define CRT_HWC_ADDRESS_EXT 27:27 -#define CRT_HWC_ADDRESS_EXT_LOCAL 0 -#define CRT_HWC_ADDRESS_EXT_EXTERNAL 1 -#define CRT_HWC_ADDRESS_ADDRESS 25:0 +#define CRT_HWC_ADDRESS_ENABLE BIT(31) +#define CRT_HWC_ADDRESS_EXT BIT(27) +#define CRT_HWC_ADDRESS_ADDRESS_MASK 0x3ffffff #define CRT_HWC_LOCATION 0x080234 -#define CRT_HWC_LOCATION_TOP 27:27 -#define CRT_HWC_LOCATION_TOP_INSIDE 0 -#define CRT_HWC_LOCATION_TOP_OUTSIDE 1 -#define CRT_HWC_LOCATION_Y 26:16 -#define CRT_HWC_LOCATION_LEFT 11:11 -#define CRT_HWC_LOCATION_LEFT_INSIDE 0 -#define CRT_HWC_LOCATION_LEFT_OUTSIDE 1 -#define CRT_HWC_LOCATION_X 10:0 +#define CRT_HWC_LOCATION_TOP BIT(27) +#define CRT_HWC_LOCATION_Y_MASK (0x7ff << 16) +#define CRT_HWC_LOCATION_LEFT BIT(11) +#define CRT_HWC_LOCATION_X_MASK 0x7ff #define CRT_HWC_COLOR_12 0x080238 -#define CRT_HWC_COLOR_12_2_RGB565 31:16 -#define CRT_HWC_COLOR_12_1_RGB565 15:0 +#define CRT_HWC_COLOR_12_2_RGB565_MASK (0xffff << 16) +#define CRT_HWC_COLOR_12_1_RGB565_MASK 0xffff #define CRT_HWC_COLOR_3 0x08023C -#define CRT_HWC_COLOR_3_RGB565 15:0 +#define CRT_HWC_COLOR_3_RGB565_MASK 0xffff /* This vertical expansion below start at 0x080240 ~ 0x080264 */ #define CRT_VERTICAL_EXPANSION 0x080240 #ifndef VALIDATION_CHIP - #define CRT_VERTICAL_CENTERING_VALUE 31:24 + #define CRT_VERTICAL_CENTERING_VALUE_MASK (0xff << 24) #endif -#define CRT_VERTICAL_EXPANSION_COMPARE_VALUE 23:16 -#define CRT_VERTICAL_EXPANSION_LINE_BUFFER 15:12 -#define CRT_VERTICAL_EXPANSION_SCALE_FACTOR 11:0 +#define CRT_VERTICAL_EXPANSION_COMPARE_VALUE_MASK (0xff << 16) +#define CRT_VERTICAL_EXPANSION_LINE_BUFFER_MASK (0xf << 12) +#define CRT_VERTICAL_EXPANSION_SCALE_FACTOR_MASK 0xfff /* This horizontal expansion below start at 0x080268 ~ 0x08027C */ #define CRT_HORIZONTAL_EXPANSION 0x080268 #ifndef VALIDATION_CHIP - #define CRT_HORIZONTAL_CENTERING_VALUE 31:24 + #define CRT_HORIZONTAL_CENTERING_VALUE_MASK (0xff << 24) #endif -#define CRT_HORIZONTAL_EXPANSION_COMPARE_VALUE 23:16 -#define CRT_HORIZONTAL_EXPANSION_SCALE_FACTOR 11:0 +#define CRT_HORIZONTAL_EXPANSION_COMPARE_VALUE_MASK (0xff << 16) +#define CRT_HORIZONTAL_EXPANSION_SCALE_FACTOR_MASK 0xfff #ifndef VALIDATION_CHIP /* Auto Centering */ #define CRT_AUTO_CENTERING_TL 0x080280 - #define CRT_AUTO_CENTERING_TL_TOP 26:16 - #define CRT_AUTO_CENTERING_TL_LEFT 10:0 + #define CRT_AUTO_CENTERING_TL_TOP_MASK (0x7ff << 16) + #define CRT_AUTO_CENTERING_TL_LEFT_MASK 0x7ff #define CRT_AUTO_CENTERING_BR 0x080284 - #define CRT_AUTO_CENTERING_BR_BOTTOM 26:16 - #define CRT_AUTO_CENTERING_BR_RIGHT 10:0 + #define CRT_AUTO_CENTERING_BR_BOTTOM_MASK (0x7ff << 16) + #define CRT_AUTO_CENTERING_BR_BOTTOM_SHIFT 16 + #define CRT_AUTO_CENTERING_BR_RIGHT_MASK 0x7ff #endif /* sm750le new register to control panel output */ @@ -1877,155 +1161,106 @@ /* Color Space Conversion registers. */ #define CSC_Y_SOURCE_BASE 0x1000C8 -#define CSC_Y_SOURCE_BASE_EXT 27:27 -#define CSC_Y_SOURCE_BASE_EXT_LOCAL 0 -#define CSC_Y_SOURCE_BASE_EXT_EXTERNAL 1 -#define CSC_Y_SOURCE_BASE_CS 26:26 -#define CSC_Y_SOURCE_BASE_CS_0 0 -#define CSC_Y_SOURCE_BASE_CS_1 1 -#define CSC_Y_SOURCE_BASE_ADDRESS 25:0 +#define CSC_Y_SOURCE_BASE_EXT BIT(27) +#define CSC_Y_SOURCE_BASE_CS BIT(26) +#define CSC_Y_SOURCE_BASE_ADDRESS_MASK 0x3ffffff #define CSC_CONSTANTS 0x1000CC -#define CSC_CONSTANTS_Y 31:24 -#define CSC_CONSTANTS_R 23:16 -#define CSC_CONSTANTS_G 15:8 -#define CSC_CONSTANTS_B 7:0 +#define CSC_CONSTANTS_Y_MASK (0xff << 24) +#define CSC_CONSTANTS_R_MASK (0xff << 16) +#define CSC_CONSTANTS_G_MASK (0xff << 8) +#define CSC_CONSTANTS_B_MASK 0xff #define CSC_Y_SOURCE_X 0x1000D0 -#define CSC_Y_SOURCE_X_INTEGER 26:16 -#define CSC_Y_SOURCE_X_FRACTION 15:3 +#define CSC_Y_SOURCE_X_INTEGER_MASK (0x7ff << 16) +#define CSC_Y_SOURCE_X_FRACTION_MASK (0x1fff << 3) #define CSC_Y_SOURCE_Y 0x1000D4 -#define CSC_Y_SOURCE_Y_INTEGER 27:16 -#define CSC_Y_SOURCE_Y_FRACTION 15:3 +#define CSC_Y_SOURCE_Y_INTEGER_MASK (0xfff << 16) +#define CSC_Y_SOURCE_Y_FRACTION_MASK (0x1fff << 3) #define CSC_U_SOURCE_BASE 0x1000D8 -#define CSC_U_SOURCE_BASE_EXT 27:27 -#define CSC_U_SOURCE_BASE_EXT_LOCAL 0 -#define CSC_U_SOURCE_BASE_EXT_EXTERNAL 1 -#define CSC_U_SOURCE_BASE_CS 26:26 -#define CSC_U_SOURCE_BASE_CS_0 0 -#define CSC_U_SOURCE_BASE_CS_1 1 -#define CSC_U_SOURCE_BASE_ADDRESS 25:0 +#define CSC_U_SOURCE_BASE_EXT BIT(27) +#define CSC_U_SOURCE_BASE_CS BIT(26) +#define CSC_U_SOURCE_BASE_ADDRESS_MASK 0x3ffffff #define CSC_V_SOURCE_BASE 0x1000DC -#define CSC_V_SOURCE_BASE_EXT 27:27 -#define CSC_V_SOURCE_BASE_EXT_LOCAL 0 -#define CSC_V_SOURCE_BASE_EXT_EXTERNAL 1 -#define CSC_V_SOURCE_BASE_CS 26:26 -#define CSC_V_SOURCE_BASE_CS_0 0 -#define CSC_V_SOURCE_BASE_CS_1 1 -#define CSC_V_SOURCE_BASE_ADDRESS 25:0 +#define CSC_V_SOURCE_BASE_EXT BIT(27) +#define CSC_V_SOURCE_BASE_CS BIT(26) +#define CSC_V_SOURCE_BASE_ADDRESS_MASK 0x3ffffff #define CSC_SOURCE_DIMENSION 0x1000E0 -#define CSC_SOURCE_DIMENSION_X 31:16 -#define CSC_SOURCE_DIMENSION_Y 15:0 +#define CSC_SOURCE_DIMENSION_X_MASK (0xffff << 16) +#define CSC_SOURCE_DIMENSION_Y_MASK 0xffff #define CSC_SOURCE_PITCH 0x1000E4 -#define CSC_SOURCE_PITCH_Y 31:16 -#define CSC_SOURCE_PITCH_UV 15:0 +#define CSC_SOURCE_PITCH_Y_MASK (0xffff << 16) +#define CSC_SOURCE_PITCH_UV_MASK 0xffff #define CSC_DESTINATION 0x1000E8 -#define CSC_DESTINATION_WRAP 31:31 -#define CSC_DESTINATION_WRAP_DISABLE 0 -#define CSC_DESTINATION_WRAP_ENABLE 1 -#define CSC_DESTINATION_X 27:16 -#define CSC_DESTINATION_Y 11:0 +#define CSC_DESTINATION_WRAP BIT(31) +#define CSC_DESTINATION_X_MASK (0xfff << 16) +#define CSC_DESTINATION_Y_MASK 0xfff #define CSC_DESTINATION_DIMENSION 0x1000EC -#define CSC_DESTINATION_DIMENSION_X 31:16 -#define CSC_DESTINATION_DIMENSION_Y 15:0 +#define CSC_DESTINATION_DIMENSION_X_MASK (0xffff << 16) +#define CSC_DESTINATION_DIMENSION_Y_MASK 0xffff #define CSC_DESTINATION_PITCH 0x1000F0 -#define CSC_DESTINATION_PITCH_X 31:16 -#define CSC_DESTINATION_PITCH_Y 15:0 +#define CSC_DESTINATION_PITCH_X_MASK (0xffff << 16) +#define CSC_DESTINATION_PITCH_Y_MASK 0xffff #define CSC_SCALE_FACTOR 0x1000F4 -#define CSC_SCALE_FACTOR_HORIZONTAL 31:16 -#define CSC_SCALE_FACTOR_VERTICAL 15:0 +#define CSC_SCALE_FACTOR_HORIZONTAL_MASK (0xffff << 16) +#define CSC_SCALE_FACTOR_VERTICAL_MASK 0xffff #define CSC_DESTINATION_BASE 0x1000F8 -#define CSC_DESTINATION_BASE_EXT 27:27 -#define CSC_DESTINATION_BASE_EXT_LOCAL 0 -#define CSC_DESTINATION_BASE_EXT_EXTERNAL 1 -#define CSC_DESTINATION_BASE_CS 26:26 -#define CSC_DESTINATION_BASE_CS_0 0 -#define CSC_DESTINATION_BASE_CS_1 1 -#define CSC_DESTINATION_BASE_ADDRESS 25:0 +#define CSC_DESTINATION_BASE_EXT BIT(27) +#define CSC_DESTINATION_BASE_CS BIT(26) +#define CSC_DESTINATION_BASE_ADDRESS_MASK 0x3ffffff #define CSC_CONTROL 0x1000FC -#define CSC_CONTROL_STATUS 31:31 -#define CSC_CONTROL_STATUS_STOP 0 -#define CSC_CONTROL_STATUS_START 1 -#define CSC_CONTROL_SOURCE_FORMAT 30:28 -#define CSC_CONTROL_SOURCE_FORMAT_YUV422 0 -#define CSC_CONTROL_SOURCE_FORMAT_YUV420I 1 -#define CSC_CONTROL_SOURCE_FORMAT_YUV420 2 -#define CSC_CONTROL_SOURCE_FORMAT_YVU9 3 -#define CSC_CONTROL_SOURCE_FORMAT_IYU1 4 -#define CSC_CONTROL_SOURCE_FORMAT_IYU2 5 -#define CSC_CONTROL_SOURCE_FORMAT_RGB565 6 -#define CSC_CONTROL_SOURCE_FORMAT_RGB8888 7 -#define CSC_CONTROL_DESTINATION_FORMAT 27:26 -#define CSC_CONTROL_DESTINATION_FORMAT_RGB565 0 -#define CSC_CONTROL_DESTINATION_FORMAT_RGB8888 1 -#define CSC_CONTROL_HORIZONTAL_FILTER 25:25 -#define CSC_CONTROL_HORIZONTAL_FILTER_DISABLE 0 -#define CSC_CONTROL_HORIZONTAL_FILTER_ENABLE 1 -#define CSC_CONTROL_VERTICAL_FILTER 24:24 -#define CSC_CONTROL_VERTICAL_FILTER_DISABLE 0 -#define CSC_CONTROL_VERTICAL_FILTER_ENABLE 1 -#define CSC_CONTROL_BYTE_ORDER 23:23 -#define CSC_CONTROL_BYTE_ORDER_YUYV 0 -#define CSC_CONTROL_BYTE_ORDER_UYVY 1 +#define CSC_CONTROL_STATUS BIT(31) +#define CSC_CONTROL_SOURCE_FORMAT_MASK (0x7 << 28) +#define CSC_CONTROL_SOURCE_FORMAT_YUV422 (0x0 << 28) +#define CSC_CONTROL_SOURCE_FORMAT_YUV420I (0x1 << 28) +#define CSC_CONTROL_SOURCE_FORMAT_YUV420 (0x2 << 28) +#define CSC_CONTROL_SOURCE_FORMAT_YVU9 (0x3 << 28) +#define CSC_CONTROL_SOURCE_FORMAT_IYU1 (0x4 << 28) +#define CSC_CONTROL_SOURCE_FORMAT_IYU2 (0x5 << 28) +#define CSC_CONTROL_SOURCE_FORMAT_RGB565 (0x6 << 28) +#define CSC_CONTROL_SOURCE_FORMAT_RGB8888 (0x7 << 28) +#define CSC_CONTROL_DESTINATION_FORMAT_MASK (0x3 << 26) +#define CSC_CONTROL_DESTINATION_FORMAT_RGB565 (0x0 << 26) +#define CSC_CONTROL_DESTINATION_FORMAT_RGB8888 (0x1 << 26) +#define CSC_CONTROL_HORIZONTAL_FILTER BIT(25) +#define CSC_CONTROL_VERTICAL_FILTER BIT(24) +#define CSC_CONTROL_BYTE_ORDER BIT(23) #define DE_DATA_PORT 0x110000 #define I2C_BYTE_COUNT 0x010040 -#define I2C_BYTE_COUNT_COUNT 3:0 +#define I2C_BYTE_COUNT_COUNT_MASK 0xf #define I2C_CTRL 0x010041 -#define I2C_CTRL_INT 4:4 -#define I2C_CTRL_INT_DISABLE 0 -#define I2C_CTRL_INT_ENABLE 1 -#define I2C_CTRL_DIR 3:3 -#define I2C_CTRL_DIR_WR 0 -#define I2C_CTRL_DIR_RD 1 -#define I2C_CTRL_CTRL 2:2 -#define I2C_CTRL_CTRL_STOP 0 -#define I2C_CTRL_CTRL_START 1 -#define I2C_CTRL_MODE 1:1 -#define I2C_CTRL_MODE_STANDARD 0 -#define I2C_CTRL_MODE_FAST 1 -#define I2C_CTRL_EN 0:0 -#define I2C_CTRL_EN_DISABLE 0 -#define I2C_CTRL_EN_ENABLE 1 +#define I2C_CTRL_INT BIT(4) +#define I2C_CTRL_DIR BIT(3) +#define I2C_CTRL_CTRL BIT(2) +#define I2C_CTRL_MODE BIT(1) +#define I2C_CTRL_EN BIT(0) #define I2C_STATUS 0x010042 -#define I2C_STATUS_TX 3:3 -#define I2C_STATUS_TX_PROGRESS 0 -#define I2C_STATUS_TX_COMPLETED 1 -#define I2C_TX_DONE 0x08 -#define I2C_STATUS_ERR 2:2 -#define I2C_STATUS_ERR_NORMAL 0 -#define I2C_STATUS_ERR_ERROR 1 -#define I2C_STATUS_ERR_CLEAR 0 -#define I2C_STATUS_ACK 1:1 -#define I2C_STATUS_ACK_RECEIVED 0 -#define I2C_STATUS_ACK_NOT 1 -#define I2C_STATUS_BSY 0:0 -#define I2C_STATUS_BSY_IDLE 0 -#define I2C_STATUS_BSY_BUSY 1 +#define I2C_STATUS_TX BIT(3) +#define I2C_STATUS_ERR BIT(2) +#define I2C_STATUS_ACK BIT(1) +#define I2C_STATUS_BSY BIT(0) #define I2C_RESET 0x010042 -#define I2C_RESET_BUS_ERROR 2:2 -#define I2C_RESET_BUS_ERROR_CLEAR 0 +#define I2C_RESET_BUS_ERROR BIT(2) #define I2C_SLAVE_ADDRESS 0x010043 -#define I2C_SLAVE_ADDRESS_ADDRESS 7:1 -#define I2C_SLAVE_ADDRESS_RW 0:0 -#define I2C_SLAVE_ADDRESS_RW_W 0 -#define I2C_SLAVE_ADDRESS_RW_R 1 +#define I2C_SLAVE_ADDRESS_ADDRESS_MASK (0x7f << 1) +#define I2C_SLAVE_ADDRESS_RW BIT(0) #define I2C_DATA0 0x010044 #define I2C_DATA1 0x010045 @@ -2046,120 +1281,59 @@ #define ZV0_CAPTURE_CTRL 0x090000 -#define ZV0_CAPTURE_CTRL_FIELD_INPUT 27:27 -#define ZV0_CAPTURE_CTRL_FIELD_INPUT_EVEN_FIELD 0 -#define ZV0_CAPTURE_CTRL_FIELD_INPUT_ODD_FIELD 1 -#define ZV0_CAPTURE_CTRL_SCAN 26:26 -#define ZV0_CAPTURE_CTRL_SCAN_PROGRESSIVE 0 -#define ZV0_CAPTURE_CTRL_SCAN_INTERLACE 1 -#define ZV0_CAPTURE_CTRL_CURRENT_BUFFER 25:25 -#define ZV0_CAPTURE_CTRL_CURRENT_BUFFER_0 0 -#define ZV0_CAPTURE_CTRL_CURRENT_BUFFER_1 1 -#define ZV0_CAPTURE_CTRL_VERTICAL_SYNC 24:24 -#define ZV0_CAPTURE_CTRL_VERTICAL_SYNC_INACTIVE 0 -#define ZV0_CAPTURE_CTRL_VERTICAL_SYNC_ACTIVE 1 -#define ZV0_CAPTURE_CTRL_ADJ 19:19 -#define ZV0_CAPTURE_CTRL_ADJ_NORMAL 0 -#define ZV0_CAPTURE_CTRL_ADJ_DELAY 1 -#define ZV0_CAPTURE_CTRL_HA 18:18 -#define ZV0_CAPTURE_CTRL_HA_DISABLE 0 -#define ZV0_CAPTURE_CTRL_HA_ENABLE 1 -#define ZV0_CAPTURE_CTRL_VSK 17:17 -#define ZV0_CAPTURE_CTRL_VSK_DISABLE 0 -#define ZV0_CAPTURE_CTRL_VSK_ENABLE 1 -#define ZV0_CAPTURE_CTRL_HSK 16:16 -#define ZV0_CAPTURE_CTRL_HSK_DISABLE 0 -#define ZV0_CAPTURE_CTRL_HSK_ENABLE 1 -#define ZV0_CAPTURE_CTRL_FD 15:15 -#define ZV0_CAPTURE_CTRL_FD_RISING 0 -#define ZV0_CAPTURE_CTRL_FD_FALLING 1 -#define ZV0_CAPTURE_CTRL_VP 14:14 -#define ZV0_CAPTURE_CTRL_VP_HIGH 0 -#define ZV0_CAPTURE_CTRL_VP_LOW 1 -#define ZV0_CAPTURE_CTRL_HP 13:13 -#define ZV0_CAPTURE_CTRL_HP_HIGH 0 -#define ZV0_CAPTURE_CTRL_HP_LOW 1 -#define ZV0_CAPTURE_CTRL_CP 12:12 -#define ZV0_CAPTURE_CTRL_CP_HIGH 0 -#define ZV0_CAPTURE_CTRL_CP_LOW 1 -#define ZV0_CAPTURE_CTRL_UVS 11:11 -#define ZV0_CAPTURE_CTRL_UVS_DISABLE 0 -#define ZV0_CAPTURE_CTRL_UVS_ENABLE 1 -#define ZV0_CAPTURE_CTRL_BS 10:10 -#define ZV0_CAPTURE_CTRL_BS_DISABLE 0 -#define ZV0_CAPTURE_CTRL_BS_ENABLE 1 -#define ZV0_CAPTURE_CTRL_CS 9:9 -#define ZV0_CAPTURE_CTRL_CS_16 0 -#define ZV0_CAPTURE_CTRL_CS_8 1 -#define ZV0_CAPTURE_CTRL_CF 8:8 -#define ZV0_CAPTURE_CTRL_CF_YUV 0 -#define ZV0_CAPTURE_CTRL_CF_RGB 1 -#define ZV0_CAPTURE_CTRL_FS 7:7 -#define ZV0_CAPTURE_CTRL_FS_DISABLE 0 -#define ZV0_CAPTURE_CTRL_FS_ENABLE 1 -#define ZV0_CAPTURE_CTRL_WEAVE 6:6 -#define ZV0_CAPTURE_CTRL_WEAVE_DISABLE 0 -#define ZV0_CAPTURE_CTRL_WEAVE_ENABLE 1 -#define ZV0_CAPTURE_CTRL_BOB 5:5 -#define ZV0_CAPTURE_CTRL_BOB_DISABLE 0 -#define ZV0_CAPTURE_CTRL_BOB_ENABLE 1 -#define ZV0_CAPTURE_CTRL_DB 4:4 -#define ZV0_CAPTURE_CTRL_DB_DISABLE 0 -#define ZV0_CAPTURE_CTRL_DB_ENABLE 1 -#define ZV0_CAPTURE_CTRL_CC 3:3 -#define ZV0_CAPTURE_CTRL_CC_CONTINUE 0 -#define ZV0_CAPTURE_CTRL_CC_CONDITION 1 -#define ZV0_CAPTURE_CTRL_RGB 2:2 -#define ZV0_CAPTURE_CTRL_RGB_DISABLE 0 -#define ZV0_CAPTURE_CTRL_RGB_ENABLE 1 -#define ZV0_CAPTURE_CTRL_656 1:1 -#define ZV0_CAPTURE_CTRL_656_DISABLE 0 -#define ZV0_CAPTURE_CTRL_656_ENABLE 1 -#define ZV0_CAPTURE_CTRL_CAP 0:0 -#define ZV0_CAPTURE_CTRL_CAP_DISABLE 0 -#define ZV0_CAPTURE_CTRL_CAP_ENABLE 1 +#define ZV0_CAPTURE_CTRL_FIELD_INPUT BIT(27) +#define ZV0_CAPTURE_CTRL_SCAN BIT(26) +#define ZV0_CAPTURE_CTRL_CURRENT_BUFFER BIT(25) +#define ZV0_CAPTURE_CTRL_VERTICAL_SYNC BIT(24) +#define ZV0_CAPTURE_CTRL_ADJ BIT(19) +#define ZV0_CAPTURE_CTRL_HA BIT(18) +#define ZV0_CAPTURE_CTRL_VSK BIT(17) +#define ZV0_CAPTURE_CTRL_HSK BIT(16) +#define ZV0_CAPTURE_CTRL_FD BIT(15) +#define ZV0_CAPTURE_CTRL_VP BIT(14) +#define ZV0_CAPTURE_CTRL_HP BIT(13) +#define ZV0_CAPTURE_CTRL_CP BIT(12) +#define ZV0_CAPTURE_CTRL_UVS BIT(11) +#define ZV0_CAPTURE_CTRL_BS BIT(10) +#define ZV0_CAPTURE_CTRL_CS BIT(9) +#define ZV0_CAPTURE_CTRL_CF BIT(8) +#define ZV0_CAPTURE_CTRL_FS BIT(7) +#define ZV0_CAPTURE_CTRL_WEAVE BIT(6) +#define ZV0_CAPTURE_CTRL_BOB BIT(5) +#define ZV0_CAPTURE_CTRL_DB BIT(4) +#define ZV0_CAPTURE_CTRL_CC BIT(3) +#define ZV0_CAPTURE_CTRL_RGB BIT(2) +#define ZV0_CAPTURE_CTRL_656 BIT(1) +#define ZV0_CAPTURE_CTRL_CAP BIT(0) #define ZV0_CAPTURE_CLIP 0x090004 -#define ZV0_CAPTURE_CLIP_YCLIP_EVEN_FIELD 25:16 -#define ZV0_CAPTURE_CLIP_YCLIP 25:16 -#define ZV0_CAPTURE_CLIP_XCLIP 9:0 +#define ZV0_CAPTURE_CLIP_EYCLIP_MASK (0x3ff << 16) +#define ZV0_CAPTURE_CLIP_XCLIP_MASK 0x3ff #define ZV0_CAPTURE_SIZE 0x090008 -#define ZV0_CAPTURE_SIZE_HEIGHT 26:16 -#define ZV0_CAPTURE_SIZE_WIDTH 10:0 +#define ZV0_CAPTURE_SIZE_HEIGHT_MASK (0x7ff << 16) +#define ZV0_CAPTURE_SIZE_WIDTH_MASK 0x7ff #define ZV0_CAPTURE_BUF0_ADDRESS 0x09000C -#define ZV0_CAPTURE_BUF0_ADDRESS_STATUS 31:31 -#define ZV0_CAPTURE_BUF0_ADDRESS_STATUS_CURRENT 0 -#define ZV0_CAPTURE_BUF0_ADDRESS_STATUS_PENDING 1 -#define ZV0_CAPTURE_BUF0_ADDRESS_EXT 27:27 -#define ZV0_CAPTURE_BUF0_ADDRESS_EXT_LOCAL 0 -#define ZV0_CAPTURE_BUF0_ADDRESS_EXT_EXTERNAL 1 -#define ZV0_CAPTURE_BUF0_ADDRESS_CS 26:26 -#define ZV0_CAPTURE_BUF0_ADDRESS_CS_0 0 -#define ZV0_CAPTURE_BUF0_ADDRESS_CS_1 1 -#define ZV0_CAPTURE_BUF0_ADDRESS_ADDRESS 25:0 +#define ZV0_CAPTURE_BUF0_ADDRESS_STATUS BIT(31) +#define ZV0_CAPTURE_BUF0_ADDRESS_EXT BIT(27) +#define ZV0_CAPTURE_BUF0_ADDRESS_CS BIT(26) +#define ZV0_CAPTURE_BUF0_ADDRESS_ADDRESS_MASK 0x3ffffff #define ZV0_CAPTURE_BUF1_ADDRESS 0x090010 -#define ZV0_CAPTURE_BUF1_ADDRESS_STATUS 31:31 -#define ZV0_CAPTURE_BUF1_ADDRESS_STATUS_CURRENT 0 -#define ZV0_CAPTURE_BUF1_ADDRESS_STATUS_PENDING 1 -#define ZV0_CAPTURE_BUF1_ADDRESS_EXT 27:27 -#define ZV0_CAPTURE_BUF1_ADDRESS_EXT_LOCAL 0 -#define ZV0_CAPTURE_BUF1_ADDRESS_EXT_EXTERNAL 1 -#define ZV0_CAPTURE_BUF1_ADDRESS_CS 26:26 -#define ZV0_CAPTURE_BUF1_ADDRESS_CS_0 0 -#define ZV0_CAPTURE_BUF1_ADDRESS_CS_1 1 -#define ZV0_CAPTURE_BUF1_ADDRESS_ADDRESS 25:0 +#define ZV0_CAPTURE_BUF1_ADDRESS_STATUS BIT(31) +#define ZV0_CAPTURE_BUF1_ADDRESS_EXT BIT(27) +#define ZV0_CAPTURE_BUF1_ADDRESS_CS BIT(26) +#define ZV0_CAPTURE_BUF1_ADDRESS_ADDRESS_MASK 0x3ffffff #define ZV0_CAPTURE_BUF_OFFSET 0x090014 #ifndef VALIDATION_CHIP - #define ZV0_CAPTURE_BUF_OFFSET_YCLIP_ODD_FIELD 25:16 + #define ZV0_CAPTURE_BUF_OFFSET_YCLIP_ODD_FIELD (0x3ff << 16) #endif -#define ZV0_CAPTURE_BUF_OFFSET_OFFSET 15:0 +#define ZV0_CAPTURE_BUF_OFFSET_OFFSET_MASK 0xffff #define ZV0_CAPTURE_FIFO_CTRL 0x090018 -#define ZV0_CAPTURE_FIFO_CTRL_FIFO 2:0 +#define ZV0_CAPTURE_FIFO_CTRL_FIFO_MASK 0x7 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_0 0 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_1 1 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_2 2 @@ -2170,130 +1344,68 @@ #define ZV0_CAPTURE_FIFO_CTRL_FIFO_7 7 #define ZV0_CAPTURE_YRGB_CONST 0x09001C -#define ZV0_CAPTURE_YRGB_CONST_Y 31:24 -#define ZV0_CAPTURE_YRGB_CONST_R 23:16 -#define ZV0_CAPTURE_YRGB_CONST_G 15:8 -#define ZV0_CAPTURE_YRGB_CONST_B 7:0 +#define ZV0_CAPTURE_YRGB_CONST_Y_MASK (0xff << 24) +#define ZV0_CAPTURE_YRGB_CONST_R_MASK (0xff << 16) +#define ZV0_CAPTURE_YRGB_CONST_G_MASK (0xff << 8) +#define ZV0_CAPTURE_YRGB_CONST_B_MASK 0xff #define ZV0_CAPTURE_LINE_COMP 0x090020 -#define ZV0_CAPTURE_LINE_COMP_LC 10:0 +#define ZV0_CAPTURE_LINE_COMP_LC_MASK 0x7ff /* ZV1 */ #define ZV1_CAPTURE_CTRL 0x098000 -#define ZV1_CAPTURE_CTRL_FIELD_INPUT 27:27 -#define ZV1_CAPTURE_CTRL_FIELD_INPUT_EVEN_FIELD 0 -#define ZV1_CAPTURE_CTRL_FIELD_INPUT_ODD_FIELD 0 -#define ZV1_CAPTURE_CTRL_SCAN 26:26 -#define ZV1_CAPTURE_CTRL_SCAN_PROGRESSIVE 0 -#define ZV1_CAPTURE_CTRL_SCAN_INTERLACE 1 -#define ZV1_CAPTURE_CTRL_CURRENT_BUFFER 25:25 -#define ZV1_CAPTURE_CTRL_CURRENT_BUFFER_0 0 -#define ZV1_CAPTURE_CTRL_CURRENT_BUFFER_1 1 -#define ZV1_CAPTURE_CTRL_VERTICAL_SYNC 24:24 -#define ZV1_CAPTURE_CTRL_VERTICAL_SYNC_INACTIVE 0 -#define ZV1_CAPTURE_CTRL_VERTICAL_SYNC_ACTIVE 1 -#define ZV1_CAPTURE_CTRL_PANEL 20:20 -#define ZV1_CAPTURE_CTRL_PANEL_DISABLE 0 -#define ZV1_CAPTURE_CTRL_PANEL_ENABLE 1 -#define ZV1_CAPTURE_CTRL_ADJ 19:19 -#define ZV1_CAPTURE_CTRL_ADJ_NORMAL 0 -#define ZV1_CAPTURE_CTRL_ADJ_DELAY 1 -#define ZV1_CAPTURE_CTRL_HA 18:18 -#define ZV1_CAPTURE_CTRL_HA_DISABLE 0 -#define ZV1_CAPTURE_CTRL_HA_ENABLE 1 -#define ZV1_CAPTURE_CTRL_VSK 17:17 -#define ZV1_CAPTURE_CTRL_VSK_DISABLE 0 -#define ZV1_CAPTURE_CTRL_VSK_ENABLE 1 -#define ZV1_CAPTURE_CTRL_HSK 16:16 -#define ZV1_CAPTURE_CTRL_HSK_DISABLE 0 -#define ZV1_CAPTURE_CTRL_HSK_ENABLE 1 -#define ZV1_CAPTURE_CTRL_FD 15:15 -#define ZV1_CAPTURE_CTRL_FD_RISING 0 -#define ZV1_CAPTURE_CTRL_FD_FALLING 1 -#define ZV1_CAPTURE_CTRL_VP 14:14 -#define ZV1_CAPTURE_CTRL_VP_HIGH 0 -#define ZV1_CAPTURE_CTRL_VP_LOW 1 -#define ZV1_CAPTURE_CTRL_HP 13:13 -#define ZV1_CAPTURE_CTRL_HP_HIGH 0 -#define ZV1_CAPTURE_CTRL_HP_LOW 1 -#define ZV1_CAPTURE_CTRL_CP 12:12 -#define ZV1_CAPTURE_CTRL_CP_HIGH 0 -#define ZV1_CAPTURE_CTRL_CP_LOW 1 -#define ZV1_CAPTURE_CTRL_UVS 11:11 -#define ZV1_CAPTURE_CTRL_UVS_DISABLE 0 -#define ZV1_CAPTURE_CTRL_UVS_ENABLE 1 -#define ZV1_CAPTURE_CTRL_BS 10:10 -#define ZV1_CAPTURE_CTRL_BS_DISABLE 0 -#define ZV1_CAPTURE_CTRL_BS_ENABLE 1 -#define ZV1_CAPTURE_CTRL_CS 9:9 -#define ZV1_CAPTURE_CTRL_CS_16 0 -#define ZV1_CAPTURE_CTRL_CS_8 1 -#define ZV1_CAPTURE_CTRL_CF 8:8 -#define ZV1_CAPTURE_CTRL_CF_YUV 0 -#define ZV1_CAPTURE_CTRL_CF_RGB 1 -#define ZV1_CAPTURE_CTRL_FS 7:7 -#define ZV1_CAPTURE_CTRL_FS_DISABLE 0 -#define ZV1_CAPTURE_CTRL_FS_ENABLE 1 -#define ZV1_CAPTURE_CTRL_WEAVE 6:6 -#define ZV1_CAPTURE_CTRL_WEAVE_DISABLE 0 -#define ZV1_CAPTURE_CTRL_WEAVE_ENABLE 1 -#define ZV1_CAPTURE_CTRL_BOB 5:5 -#define ZV1_CAPTURE_CTRL_BOB_DISABLE 0 -#define ZV1_CAPTURE_CTRL_BOB_ENABLE 1 -#define ZV1_CAPTURE_CTRL_DB 4:4 -#define ZV1_CAPTURE_CTRL_DB_DISABLE 0 -#define ZV1_CAPTURE_CTRL_DB_ENABLE 1 -#define ZV1_CAPTURE_CTRL_CC 3:3 -#define ZV1_CAPTURE_CTRL_CC_CONTINUE 0 -#define ZV1_CAPTURE_CTRL_CC_CONDITION 1 -#define ZV1_CAPTURE_CTRL_RGB 2:2 -#define ZV1_CAPTURE_CTRL_RGB_DISABLE 0 -#define ZV1_CAPTURE_CTRL_RGB_ENABLE 1 -#define ZV1_CAPTURE_CTRL_656 1:1 -#define ZV1_CAPTURE_CTRL_656_DISABLE 0 -#define ZV1_CAPTURE_CTRL_656_ENABLE 1 -#define ZV1_CAPTURE_CTRL_CAP 0:0 -#define ZV1_CAPTURE_CTRL_CAP_DISABLE 0 -#define ZV1_CAPTURE_CTRL_CAP_ENABLE 1 +#define ZV1_CAPTURE_CTRL_FIELD_INPUT BIT(27) +#define ZV1_CAPTURE_CTRL_SCAN BIT(26) +#define ZV1_CAPTURE_CTRL_CURRENT_BUFFER BIT(25) +#define ZV1_CAPTURE_CTRL_VERTICAL_SYNC BIT(24) +#define ZV1_CAPTURE_CTRL_PANEL BIT(20) +#define ZV1_CAPTURE_CTRL_ADJ BIT(19) +#define ZV1_CAPTURE_CTRL_HA BIT(18) +#define ZV1_CAPTURE_CTRL_VSK BIT(17) +#define ZV1_CAPTURE_CTRL_HSK BIT(16) +#define ZV1_CAPTURE_CTRL_FD BIT(15) +#define ZV1_CAPTURE_CTRL_VP BIT(14) +#define ZV1_CAPTURE_CTRL_HP BIT(13) +#define ZV1_CAPTURE_CTRL_CP BIT(12) +#define ZV1_CAPTURE_CTRL_UVS BIT(11) +#define ZV1_CAPTURE_CTRL_BS BIT(10) +#define ZV1_CAPTURE_CTRL_CS BIT(9) +#define ZV1_CAPTURE_CTRL_CF BIT(8) +#define ZV1_CAPTURE_CTRL_FS BIT(7) +#define ZV1_CAPTURE_CTRL_WEAVE BIT(6) +#define ZV1_CAPTURE_CTRL_BOB BIT(5) +#define ZV1_CAPTURE_CTRL_DB BIT(4) +#define ZV1_CAPTURE_CTRL_CC BIT(3) +#define ZV1_CAPTURE_CTRL_RGB BIT(2) +#define ZV1_CAPTURE_CTRL_656 BIT(1) +#define ZV1_CAPTURE_CTRL_CAP BIT(0) #define ZV1_CAPTURE_CLIP 0x098004 -#define ZV1_CAPTURE_CLIP_YCLIP 25:16 -#define ZV1_CAPTURE_CLIP_XCLIP 9:0 +#define ZV1_CAPTURE_CLIP_YCLIP_MASK (0x3ff << 16) +#define ZV1_CAPTURE_CLIP_XCLIP_MASK 0x3ff #define ZV1_CAPTURE_SIZE 0x098008 -#define ZV1_CAPTURE_SIZE_HEIGHT 26:16 -#define ZV1_CAPTURE_SIZE_WIDTH 10:0 +#define ZV1_CAPTURE_SIZE_HEIGHT_MASK (0x7ff << 16) +#define ZV1_CAPTURE_SIZE_WIDTH_MASK 0x7ff #define ZV1_CAPTURE_BUF0_ADDRESS 0x09800C -#define ZV1_CAPTURE_BUF0_ADDRESS_STATUS 31:31 -#define ZV1_CAPTURE_BUF0_ADDRESS_STATUS_CURRENT 0 -#define ZV1_CAPTURE_BUF0_ADDRESS_STATUS_PENDING 1 -#define ZV1_CAPTURE_BUF0_ADDRESS_EXT 27:27 -#define ZV1_CAPTURE_BUF0_ADDRESS_EXT_LOCAL 0 -#define ZV1_CAPTURE_BUF0_ADDRESS_EXT_EXTERNAL 1 -#define ZV1_CAPTURE_BUF0_ADDRESS_CS 26:26 -#define ZV1_CAPTURE_BUF0_ADDRESS_CS_0 0 -#define ZV1_CAPTURE_BUF0_ADDRESS_CS_1 1 -#define ZV1_CAPTURE_BUF0_ADDRESS_ADDRESS 25:0 +#define ZV1_CAPTURE_BUF0_ADDRESS_STATUS BIT(31) +#define ZV1_CAPTURE_BUF0_ADDRESS_EXT BIT(27) +#define ZV1_CAPTURE_BUF0_ADDRESS_CS BIT(26) +#define ZV1_CAPTURE_BUF0_ADDRESS_ADDRESS_MASK 0x3ffffff #define ZV1_CAPTURE_BUF1_ADDRESS 0x098010 -#define ZV1_CAPTURE_BUF1_ADDRESS_STATUS 31:31 -#define ZV1_CAPTURE_BUF1_ADDRESS_STATUS_CURRENT 0 -#define ZV1_CAPTURE_BUF1_ADDRESS_STATUS_PENDING 1 -#define ZV1_CAPTURE_BUF1_ADDRESS_EXT 27:27 -#define ZV1_CAPTURE_BUF1_ADDRESS_EXT_LOCAL 0 -#define ZV1_CAPTURE_BUF1_ADDRESS_EXT_EXTERNAL 1 -#define ZV1_CAPTURE_BUF1_ADDRESS_CS 26:26 -#define ZV1_CAPTURE_BUF1_ADDRESS_CS_0 0 -#define ZV1_CAPTURE_BUF1_ADDRESS_CS_1 1 -#define ZV1_CAPTURE_BUF1_ADDRESS_ADDRESS 25:0 +#define ZV1_CAPTURE_BUF1_ADDRESS_STATUS BIT(31) +#define ZV1_CAPTURE_BUF1_ADDRESS_EXT BIT(27) +#define ZV1_CAPTURE_BUF1_ADDRESS_CS BIT(26) +#define ZV1_CAPTURE_BUF1_ADDRESS_ADDRESS_MASK 0x3ffffff #define ZV1_CAPTURE_BUF_OFFSET 0x098014 -#define ZV1_CAPTURE_BUF_OFFSET_OFFSET 15:0 +#define ZV1_CAPTURE_BUF_OFFSET_OFFSET_MASK 0xffff #define ZV1_CAPTURE_FIFO_CTRL 0x098018 -#define ZV1_CAPTURE_FIFO_CTRL_FIFO 2:0 +#define ZV1_CAPTURE_FIFO_CTRL_FIFO_MASK 0x7 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_0 0 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_1 1 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_2 2 @@ -2304,52 +1416,30 @@ #define ZV1_CAPTURE_FIFO_CTRL_FIFO_7 7 #define ZV1_CAPTURE_YRGB_CONST 0x09801C -#define ZV1_CAPTURE_YRGB_CONST_Y 31:24 -#define ZV1_CAPTURE_YRGB_CONST_R 23:16 -#define ZV1_CAPTURE_YRGB_CONST_G 15:8 -#define ZV1_CAPTURE_YRGB_CONST_B 7:0 +#define ZV1_CAPTURE_YRGB_CONST_Y_MASK (0xff << 24) +#define ZV1_CAPTURE_YRGB_CONST_R_MASK (0xff << 16) +#define ZV1_CAPTURE_YRGB_CONST_G_MASK (0xff << 8) +#define ZV1_CAPTURE_YRGB_CONST_B_MASK 0xff #define DMA_1_SOURCE 0x0D0010 -#define DMA_1_SOURCE_ADDRESS_EXT 27:27 -#define DMA_1_SOURCE_ADDRESS_EXT_LOCAL 0 -#define DMA_1_SOURCE_ADDRESS_EXT_EXTERNAL 1 -#define DMA_1_SOURCE_ADDRESS_CS 26:26 -#define DMA_1_SOURCE_ADDRESS_CS_0 0 -#define DMA_1_SOURCE_ADDRESS_CS_1 1 -#define DMA_1_SOURCE_ADDRESS 25:0 +#define DMA_1_SOURCE_ADDRESS_EXT BIT(27) +#define DMA_1_SOURCE_ADDRESS_CS BIT(26) +#define DMA_1_SOURCE_ADDRESS_MASK 0x3ffffff #define DMA_1_DESTINATION 0x0D0014 -#define DMA_1_DESTINATION_ADDRESS_EXT 27:27 -#define DMA_1_DESTINATION_ADDRESS_EXT_LOCAL 0 -#define DMA_1_DESTINATION_ADDRESS_EXT_EXTERNAL 1 -#define DMA_1_DESTINATION_ADDRESS_CS 26:26 -#define DMA_1_DESTINATION_ADDRESS_CS_0 0 -#define DMA_1_DESTINATION_ADDRESS_CS_1 1 -#define DMA_1_DESTINATION_ADDRESS 25:0 +#define DMA_1_DESTINATION_ADDRESS_EXT BIT(27) +#define DMA_1_DESTINATION_ADDRESS_CS BIT(26) +#define DMA_1_DESTINATION_ADDRESS_MASK 0x3ffffff #define DMA_1_SIZE_CONTROL 0x0D0018 -#define DMA_1_SIZE_CONTROL_STATUS 31:31 -#define DMA_1_SIZE_CONTROL_STATUS_IDLE 0 -#define DMA_1_SIZE_CONTROL_STATUS_ACTIVE 1 -#define DMA_1_SIZE_CONTROL_SIZE 23:0 +#define DMA_1_SIZE_CONTROL_STATUS BIT(31) +#define DMA_1_SIZE_CONTROL_SIZE_MASK 0xffffff #define DMA_ABORT_INTERRUPT 0x0D0020 -#define DMA_ABORT_INTERRUPT_ABORT_1 5:5 -#define DMA_ABORT_INTERRUPT_ABORT_1_ENABLE 0 -#define DMA_ABORT_INTERRUPT_ABORT_1_ABORT 1 -#define DMA_ABORT_INTERRUPT_ABORT_0 4:4 -#define DMA_ABORT_INTERRUPT_ABORT_0_ENABLE 0 -#define DMA_ABORT_INTERRUPT_ABORT_0_ABORT 1 -#define DMA_ABORT_INTERRUPT_INT_1 1:1 -#define DMA_ABORT_INTERRUPT_INT_1_CLEAR 0 -#define DMA_ABORT_INTERRUPT_INT_1_FINISHED 1 -#define DMA_ABORT_INTERRUPT_INT_0 0:0 -#define DMA_ABORT_INTERRUPT_INT_0_CLEAR 0 -#define DMA_ABORT_INTERRUPT_INT_0_FINISHED 1 - - - - +#define DMA_ABORT_INTERRUPT_ABORT_1 BIT(5) +#define DMA_ABORT_INTERRUPT_ABORT_0 BIT(4) +#define DMA_ABORT_INTERRUPT_INT_1 BIT(1) +#define DMA_ABORT_INTERRUPT_INT_0 BIT(0) /* Default i2c CLK and Data GPIO. These are the default i2c pins */ #define DEFAULT_I2C_SCL 30 @@ -2357,16 +1447,12 @@ #define GPIO_DATA_SM750LE 0x020018 -#define GPIO_DATA_SM750LE_1 1:1 -#define GPIO_DATA_SM750LE_0 0:0 +#define GPIO_DATA_SM750LE_1 BIT(1) +#define GPIO_DATA_SM750LE_0 BIT(0) #define GPIO_DATA_DIRECTION_SM750LE 0x02001C -#define GPIO_DATA_DIRECTION_SM750LE_1 1:1 -#define GPIO_DATA_DIRECTION_SM750LE_1_INPUT 0 -#define GPIO_DATA_DIRECTION_SM750LE_1_OUTPUT 1 -#define GPIO_DATA_DIRECTION_SM750LE_0 0:0 -#define GPIO_DATA_DIRECTION_SM750LE_0_INPUT 0 -#define GPIO_DATA_DIRECTION_SM750LE_0_OUTPUT 1 +#define GPIO_DATA_DIRECTION_SM750LE_1 BIT(1) +#define GPIO_DATA_DIRECTION_SM750LE_0 BIT(0) #endif diff --git a/drivers/staging/sm750fb/ddk750_sii164.c b/drivers/staging/sm750fb/ddk750_sii164.c index 241b77b927ee..67f36e71da7e 100644 --- a/drivers/staging/sm750fb/ddk750_sii164.c +++ b/drivers/staging/sm750fb/ddk750_sii164.c @@ -14,8 +14,8 @@ #define i2cWriteReg sm750_hw_i2c_write_reg #define i2cReadReg sm750_hw_i2c_read_reg #else - #define i2cWriteReg swI2CWriteReg - #define i2cReadReg swI2CReadReg + #define i2cWriteReg sm750_sw_i2c_write_reg + #define i2cReadReg sm750_sw_i2c_read_reg #endif /* SII164 Vendor and Device ID */ @@ -236,7 +236,7 @@ long sii164InitChip( } /* Return -1 if initialization fails. */ - return (-1); + return -1; } diff --git a/drivers/staging/sm750fb/ddk750_sii164.h b/drivers/staging/sm750fb/ddk750_sii164.h index f2610c90eeb4..664ad089f753 100644 --- a/drivers/staging/sm750fb/ddk750_sii164.h +++ b/drivers/staging/sm750fb/ddk750_sii164.h @@ -39,7 +39,10 @@ unsigned char sii164IsConnected(void); unsigned char sii164CheckInterrupt(void); void sii164ClearInterrupt(void); #endif -/* below register definination is used for Silicon Image SiI164 DVI controller chip */ +/* + * below register definition is used for + * Silicon Image SiI164 DVI controller chip + */ /* * Vendor ID registers */ diff --git a/drivers/staging/sm750fb/sm750.c b/drivers/staging/sm750fb/sm750.c index c78421b5b0e7..6ed004e40855 100644 --- a/drivers/staging/sm750fb/sm750.c +++ b/drivers/staging/sm750fb/sm750.c @@ -13,8 +13,6 @@ #include <linux/vmalloc.h> #include <linux/pagemap.h> #include <linux/screen_info.h> -#include <linux/vmalloc.h> -#include <linux/pagemap.h> #include <linux/console.h> #include <asm/fb.h> #include "sm750.h" @@ -189,7 +187,7 @@ static void lynxfb_ops_fillrect(struct fb_info *info, * If not use spin_lock,system will die if user load driver * and immediately unload driver frequently (dual) */ - if (sm750_dev->dual) + if (sm750_dev->fb_count > 1) spin_lock(&sm750_dev->slock); sm750_dev->accel.de_fillrect(&sm750_dev->accel, @@ -197,7 +195,7 @@ static void lynxfb_ops_fillrect(struct fb_info *info, region->dx, region->dy, region->width, region->height, color, rop); - if (sm750_dev->dual) + if (sm750_dev->fb_count > 1) spin_unlock(&sm750_dev->slock); } @@ -223,7 +221,7 @@ static void lynxfb_ops_copyarea(struct fb_info *info, * If not use spin_lock, system will die if user load driver * and immediately unload driver frequently (dual) */ - if (sm750_dev->dual) + if (sm750_dev->fb_count > 1) spin_lock(&sm750_dev->slock); sm750_dev->accel.de_copyarea(&sm750_dev->accel, @@ -231,7 +229,7 @@ static void lynxfb_ops_copyarea(struct fb_info *info, base, pitch, Bpp, region->dx, region->dy, region->width, region->height, HW_ROP2_COPY); - if (sm750_dev->dual) + if (sm750_dev->fb_count > 1) spin_unlock(&sm750_dev->slock); } @@ -272,7 +270,7 @@ static void lynxfb_ops_imageblit(struct fb_info *info, * If not use spin_lock, system will die if user load driver * and immediately unload driver frequently (dual) */ - if (sm750_dev->dual) + if (sm750_dev->fb_count > 1) spin_lock(&sm750_dev->slock); sm750_dev->accel.de_imageblit(&sm750_dev->accel, @@ -281,7 +279,7 @@ static void lynxfb_ops_imageblit(struct fb_info *info, image->dx, image->dy, image->width, image->height, fgcol, bgcol, HW_ROP2_COPY); - if (sm750_dev->dual) + if (sm750_dev->fb_count > 1) spin_unlock(&sm750_dev->slock); } @@ -319,7 +317,7 @@ static int lynxfb_ops_set_par(struct fb_info *info) var = &info->var; fix = &info->fix; - /* fix structur is not so FIX ... */ + /* fix structure is not so FIX ... */ line_length = var->xres_virtual * var->bits_per_pixel / 8; line_length = ALIGN(line_length, crtc->line_pad); fix->line_length = line_length; @@ -420,14 +418,16 @@ static int lynxfb_suspend(struct pci_dev *pdev, pm_message_t mesg) ret = pci_save_state(pdev); if (ret) { - pr_err("error:%d occurred in pci_save_state\n", ret); + dev_err(&pdev->dev, + "error:%d occurred in pci_save_state\n", ret); return ret; } - pci_disable_device(pdev); ret = pci_set_power_state(pdev, pci_choose_state(pdev, mesg)); if (ret) { - pr_err("error:%d occurred in pci_set_power_state\n", ret); + dev_err(&pdev->dev, + "error:%d occurred in pci_set_power_state\n", + ret); return ret; } } @@ -455,7 +455,8 @@ static int lynxfb_resume(struct pci_dev *pdev) ret = pci_set_power_state(pdev, PCI_D0); if (ret) { - pr_err("error:%d occurred in pci_set_power_state\n", ret); + dev_err(&pdev->dev, + "error:%d occurred in pci_set_power_state\n", ret); return ret; } @@ -463,7 +464,9 @@ static int lynxfb_resume(struct pci_dev *pdev) pci_restore_state(pdev); ret = pci_enable_device(pdev); if (ret) { - pr_err("error:%d occurred in pci_enable_device\n", ret); + dev_err(&pdev->dev, + "error:%d occurred in pci_enable_device\n", + ret); return ret; } pci_set_master(pdev); @@ -650,8 +653,10 @@ static int sm750fb_set_drv(struct lynxfb_par *par) output = &par->output; crtc = &par->crtc; - crtc->vidmem_size = (sm750_dev->dual) ? sm750_dev->vidmem_size >> 1 : - sm750_dev->vidmem_size; + crtc->vidmem_size = sm750_dev->vidmem_size; + if (sm750_dev->fb_count > 1) + crtc->vidmem_size >>= 1; + /* setup crtc and output member */ sm750_dev->hwCursor = g_hwcursor; @@ -981,7 +986,7 @@ static void sm750fb_setup(struct sm750_dev *sm750_dev, char *src) NO_PARAM: if (sm750_dev->revid != SM750LE_REVISION_ID) { - if (sm750_dev->dual) { + if (sm750_dev->fb_count > 1) { if (swap) sm750_dev->dataflow = sm750_dual_swap; else @@ -1000,35 +1005,75 @@ NO_PARAM: } } +static void sm750fb_frambuffer_release(struct sm750_dev *sm750_dev) +{ + struct fb_info *fb_info; + + while (sm750_dev->fb_count) { + fb_info = sm750_dev->fbinfo[sm750_dev->fb_count - 1]; + unregister_framebuffer(fb_info); + framebuffer_release(fb_info); + sm750_dev->fb_count--; + } +} + +static int sm750fb_frambuffer_alloc(struct sm750_dev *sm750_dev, int fbidx) +{ + struct fb_info *fb_info; + struct lynxfb_par *par; + int err; + + fb_info = framebuffer_alloc(sizeof(struct lynxfb_par), + &sm750_dev->pdev->dev); + if (!fb_info) + return -ENOMEM; + + sm750_dev->fbinfo[fbidx] = fb_info; + par = fb_info->par; + par->dev = sm750_dev; + + err = lynxfb_set_fbinfo(fb_info, fbidx); + if (err) + goto release_fb; + + err = register_framebuffer(fb_info); + if (err < 0) + goto release_fb; + + sm750_dev->fb_count++; + + return 0; + +release_fb: + framebuffer_release(fb_info); + return err; +} + static int lynxfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { - struct fb_info *info[] = {NULL, NULL}; struct sm750_dev *sm750_dev = NULL; + int max_fb; int fbidx; + int err; /* enable device */ - if (pci_enable_device(pdev)) { - pr_err("can not enable device.\n"); - goto err_enable; - } + err = pcim_enable_device(pdev); + if (err) + return err; - sm750_dev = kzalloc(sizeof(*sm750_dev), GFP_KERNEL); - if (!sm750_dev) { - pr_err("Could not allocate memory for share.\n"); - goto err_share; - } + err = -ENOMEM; + sm750_dev = devm_kzalloc(&pdev->dev, sizeof(*sm750_dev), GFP_KERNEL); + if (!sm750_dev) + return err; sm750_dev->fbinfo[0] = sm750_dev->fbinfo[1] = NULL; sm750_dev->devid = pdev->device; sm750_dev->revid = pdev->revision; - - pr_info("share->revid = %02x\n", sm750_dev->revid); sm750_dev->pdev = pdev; sm750_dev->mtrr_off = g_nomtrr; sm750_dev->mtrr.vram = 0; sm750_dev->accel_off = g_noaccel; - sm750_dev->dual = g_dualview; spin_lock_init(&sm750_dev->slock); if (!sm750_dev->accel_off) { @@ -1042,19 +1087,15 @@ static int lynxfb_pci_probe(struct pci_dev *pdev, sm750_dev->accel.de_fillrect = hw_fillrect; sm750_dev->accel.de_copyarea = hw_copyarea; sm750_dev->accel.de_imageblit = hw_imageblit; - pr_info("enable 2d acceleration\n"); - } else { - pr_info("disable 2d acceleration\n"); } /* call chip specific setup routine */ sm750fb_setup(sm750_dev, g_settings); /* call chip specific mmap routine */ - if (hw_sm750_map(sm750_dev, pdev)) { - pr_err("Memory map failed\n"); - goto err_map; - } + err = hw_sm750_map(sm750_dev, pdev); + if (err) + return err; if (!sm750_dev->mtrr_off) sm750_dev->mtrr.vram = arch_phys_wc_add(sm750_dev->vidmem_start, @@ -1062,107 +1103,38 @@ static int lynxfb_pci_probe(struct pci_dev *pdev, memset_io(sm750_dev->pvMem, 0, sm750_dev->vidmem_size); - pr_info("sm%3x mmio address = %p\n", sm750_dev->devid, - sm750_dev->pvReg); - pci_set_drvdata(pdev, sm750_dev); /* call chipInit routine */ hw_sm750_inithw(sm750_dev, pdev); - /* allocate frame buffer info structor according to g_dualview */ - fbidx = 0; -ALLOC_FB: - info[fbidx] = framebuffer_alloc(sizeof(struct lynxfb_par), &pdev->dev); - if (!info[fbidx]) { - pr_err("Could not allocate framebuffer #%d.\n", fbidx); - if (fbidx == 0) - goto err_info0_alloc; - else - goto err_info1_alloc; - } else { - struct lynxfb_par *par; - int errno; - - pr_info("framebuffer #%d alloc okay\n", fbidx); - sm750_dev->fbinfo[fbidx] = info[fbidx]; - par = info[fbidx]->par; - par->dev = sm750_dev; - - /* set fb_info structure */ - if (lynxfb_set_fbinfo(info[fbidx], fbidx)) { - pr_err("Failed to initial fb_info #%d.\n", fbidx); - if (fbidx == 0) - goto err_info0_set; - else - goto err_info1_set; - } - - /* register frame buffer */ - pr_info("Ready to register framebuffer #%d.\n", fbidx); - errno = register_framebuffer(info[fbidx]); - if (errno < 0) { - pr_err("Failed to register fb_info #%d. err %d\n", - fbidx, - errno); - if (fbidx == 0) - goto err_register0; - else - goto err_register1; - } - pr_info("Accomplished register framebuffer #%d.\n", fbidx); + /* allocate frame buffer info structures according to g_dualview */ + max_fb = g_dualview ? 2 : 1; + for (fbidx = 0; fbidx < max_fb; fbidx++) { + err = sm750fb_frambuffer_alloc(sm750_dev, fbidx); + if (err) + goto release_fb; } - /* no dual view by far */ - fbidx++; - if (sm750_dev->dual && fbidx < 2) - goto ALLOC_FB; - return 0; -err_register1: -err_info1_set: - framebuffer_release(info[1]); -err_info1_alloc: - unregister_framebuffer(info[0]); -err_register0: -err_info0_set: - framebuffer_release(info[0]); -err_info0_alloc: -err_map: - kfree(sm750_dev); -err_share: -err_enable: - return -ENODEV; +release_fb: + sm750fb_frambuffer_release(sm750_dev); + return err; } static void lynxfb_pci_remove(struct pci_dev *pdev) { - struct fb_info *info; struct sm750_dev *sm750_dev; - struct lynxfb_par *par; - int cnt; - cnt = 2; sm750_dev = pci_get_drvdata(pdev); - while (cnt-- > 0) { - info = sm750_dev->fbinfo[cnt]; - if (!info) - continue; - par = info->par; - - unregister_framebuffer(info); - /* release frame buffer */ - framebuffer_release(info); - } + sm750fb_frambuffer_release(sm750_dev); arch_phys_wc_del(sm750_dev->mtrr.vram); iounmap(sm750_dev->pvReg); iounmap(sm750_dev->pvMem); kfree(g_settings); - kfree(sm750_dev); - pci_set_drvdata(pdev, NULL); } static int __init lynxfb_setup(char *options) diff --git a/drivers/staging/sm750fb/sm750.h b/drivers/staging/sm750fb/sm750.h index b0a93cdc7292..8e70ce0d6da4 100644 --- a/drivers/staging/sm750fb/sm750.h +++ b/drivers/staging/sm750fb/sm750.h @@ -53,7 +53,7 @@ struct lynx_accel { /* base virtual address of de data port */ volatile unsigned char __iomem *dpPortBase; - /* function fointers */ + /* function pointers */ void (*de_init)(struct lynx_accel *); int (*de_wait)(void);/* see if hardware ready to work */ @@ -79,7 +79,7 @@ struct sm750_dev { struct fb_info *fbinfo[2]; struct lynx_accel accel; int accel_off; - int dual; + int fb_count; int mtrr_off; struct{ int vram; diff --git a/drivers/staging/sm750fb/sm750_accel.c b/drivers/staging/sm750fb/sm750_accel.c index 43e59725920c..9aa4066ac86d 100644 --- a/drivers/staging/sm750fb/sm750_accel.c +++ b/drivers/staging/sm750fb/sm750_accel.c @@ -17,7 +17,6 @@ #include "sm750.h" #include "sm750_accel.h" -#include "sm750_help.h" static inline void write_dpr(struct lynx_accel *accel, int offset, u32 regValue) { writel(regValue, accel->dprBase + offset); @@ -41,20 +40,16 @@ void hw_de_init(struct lynx_accel *accel) write_dpr(accel, DE_MASKS, 0xFFFFFFFF); /* dpr1c */ - reg = FIELD_SET(0, DE_STRETCH_FORMAT, PATTERN_XY, NORMAL)| - FIELD_VALUE(0, DE_STRETCH_FORMAT, PATTERN_Y, 0)| - FIELD_VALUE(0, DE_STRETCH_FORMAT, PATTERN_X, 0)| - FIELD_SET(0, DE_STRETCH_FORMAT, ADDRESSING, XY)| - FIELD_VALUE(0, DE_STRETCH_FORMAT, SOURCE_HEIGHT, 3); + reg = 0x3; - clr = FIELD_CLEAR(DE_STRETCH_FORMAT, PATTERN_XY)& - FIELD_CLEAR(DE_STRETCH_FORMAT, PATTERN_Y)& - FIELD_CLEAR(DE_STRETCH_FORMAT, PATTERN_X)& - FIELD_CLEAR(DE_STRETCH_FORMAT, ADDRESSING)& - FIELD_CLEAR(DE_STRETCH_FORMAT, SOURCE_HEIGHT); + clr = DE_STRETCH_FORMAT_PATTERN_XY | DE_STRETCH_FORMAT_PATTERN_Y_MASK | + DE_STRETCH_FORMAT_PATTERN_X_MASK | + DE_STRETCH_FORMAT_ADDRESSING_MASK | + DE_STRETCH_FORMAT_SOURCE_HEIGHT_MASK; - /* DE_STRETCH bpp format need be initilized in setMode routine */ - write_dpr(accel, DE_STRETCH_FORMAT, (read_dpr(accel, DE_STRETCH_FORMAT) & clr) | reg); + /* DE_STRETCH bpp format need be initialized in setMode routine */ + write_dpr(accel, DE_STRETCH_FORMAT, + (read_dpr(accel, DE_STRETCH_FORMAT) & ~clr) | reg); /* disable clipping and transparent */ write_dpr(accel, DE_CLIP_TL, 0); /* dpr2c */ @@ -63,16 +58,11 @@ void hw_de_init(struct lynx_accel *accel) write_dpr(accel, DE_COLOR_COMPARE_MASK, 0); /* dpr24 */ write_dpr(accel, DE_COLOR_COMPARE, 0); - reg = FIELD_SET(0, DE_CONTROL, TRANSPARENCY, DISABLE)| - FIELD_SET(0, DE_CONTROL, TRANSPARENCY_MATCH, OPAQUE)| - FIELD_SET(0, DE_CONTROL, TRANSPARENCY_SELECT, SOURCE); - - clr = FIELD_CLEAR(DE_CONTROL, TRANSPARENCY)& - FIELD_CLEAR(DE_CONTROL, TRANSPARENCY_MATCH)& - FIELD_CLEAR(DE_CONTROL, TRANSPARENCY_SELECT); + clr = DE_CONTROL_TRANSPARENCY | DE_CONTROL_TRANSPARENCY_MATCH | + DE_CONTROL_TRANSPARENCY_SELECT; /* dpr0c */ - write_dpr(accel, DE_CONTROL, (read_dpr(accel, DE_CONTROL)&clr)|reg); + write_dpr(accel, DE_CONTROL, read_dpr(accel, DE_CONTROL) & ~clr); } /* set2dformat only be called from setmode functions @@ -85,7 +75,9 @@ void hw_set2dformat(struct lynx_accel *accel, int fmt) /* fmt=0,1,2 for 8,16,32,bpp on sm718/750/502 */ reg = read_dpr(accel, DE_STRETCH_FORMAT); - reg = FIELD_VALUE(reg, DE_STRETCH_FORMAT, PIXEL_FORMAT, fmt); + reg &= ~DE_STRETCH_FORMAT_PIXEL_FORMAT_MASK; + reg |= ((fmt << DE_STRETCH_FORMAT_PIXEL_FORMAT_SHIFT) & + DE_STRETCH_FORMAT_PIXEL_FORMAT_MASK); write_dpr(accel, DE_STRETCH_FORMAT, reg); } @@ -105,31 +97,28 @@ int hw_fillrect(struct lynx_accel *accel, write_dpr(accel, DE_WINDOW_DESTINATION_BASE, base); /* dpr40 */ write_dpr(accel, DE_PITCH, - FIELD_VALUE(0, DE_PITCH, DESTINATION, pitch/Bpp)| - FIELD_VALUE(0, DE_PITCH, SOURCE, pitch/Bpp)); /* dpr10 */ + ((pitch / Bpp << DE_PITCH_DESTINATION_SHIFT) & + DE_PITCH_DESTINATION_MASK) | + (pitch / Bpp & DE_PITCH_SOURCE_MASK)); /* dpr10 */ write_dpr(accel, DE_WINDOW_WIDTH, - FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, pitch/Bpp)| - FIELD_VALUE(0, DE_WINDOW_WIDTH, SOURCE, pitch/Bpp)); /* dpr44 */ + ((pitch / Bpp << DE_WINDOW_WIDTH_DST_SHIFT) & + DE_WINDOW_WIDTH_DST_MASK) | + (pitch / Bpp & DE_WINDOW_WIDTH_SRC_MASK)); /* dpr44 */ write_dpr(accel, DE_FOREGROUND, color); /* DPR14 */ write_dpr(accel, DE_DESTINATION, - FIELD_SET(0, DE_DESTINATION, WRAP, DISABLE)| - FIELD_VALUE(0, DE_DESTINATION, X, x)| - FIELD_VALUE(0, DE_DESTINATION, Y, y)); /* dpr4 */ + ((x << DE_DESTINATION_X_SHIFT) & DE_DESTINATION_X_MASK) | + (y & DE_DESTINATION_Y_MASK)); /* dpr4 */ write_dpr(accel, DE_DIMENSION, - FIELD_VALUE(0, DE_DIMENSION, X, width)| - FIELD_VALUE(0, DE_DIMENSION, Y_ET, height)); /* dpr8 */ + ((width << DE_DIMENSION_X_SHIFT) & DE_DIMENSION_X_MASK) | + (height & DE_DIMENSION_Y_ET_MASK)); /* dpr8 */ - deCtrl = - FIELD_SET(0, DE_CONTROL, STATUS, START)| - FIELD_SET(0, DE_CONTROL, DIRECTION, LEFT_TO_RIGHT)| - FIELD_SET(0, DE_CONTROL, LAST_PIXEL, ON)| - FIELD_SET(0, DE_CONTROL, COMMAND, RECTANGLE_FILL)| - FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2)| - FIELD_VALUE(0, DE_CONTROL, ROP, rop); /* dpr0xc */ + deCtrl = DE_CONTROL_STATUS | DE_CONTROL_LAST_PIXEL | + DE_CONTROL_COMMAND_RECTANGLE_FILL | DE_CONTROL_ROP_SELECT | + (rop & DE_CONTROL_ROP_MASK); /* dpr0xc */ write_dpr(accel, DE_CONTROL, deCtrl); return 0; @@ -237,18 +226,18 @@ unsigned int rop2) /* ROP value */ Note that input pitch is BYTE value, but the 2D Pitch register uses pixel values. Need Byte to pixel conversion. */ - { - write_dpr(accel, DE_PITCH, - FIELD_VALUE(0, DE_PITCH, DESTINATION, (dPitch/Bpp)) | - FIELD_VALUE(0, DE_PITCH, SOURCE, (sPitch/Bpp))); /* dpr10 */ - } + write_dpr(accel, DE_PITCH, + ((dPitch / Bpp << DE_PITCH_DESTINATION_SHIFT) & + DE_PITCH_DESTINATION_MASK) | + (sPitch / Bpp & DE_PITCH_SOURCE_MASK)); /* dpr10 */ /* Screen Window width in Pixels. 2D engine uses this value to calculate the linear address in frame buffer for a given point. */ write_dpr(accel, DE_WINDOW_WIDTH, - FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, (dPitch/Bpp)) | - FIELD_VALUE(0, DE_WINDOW_WIDTH, SOURCE, (sPitch/Bpp))); /* dpr3c */ + ((dPitch / Bpp << DE_WINDOW_WIDTH_DST_SHIFT) & + DE_WINDOW_WIDTH_DST_MASK) | + (sPitch / Bpp & DE_WINDOW_WIDTH_SRC_MASK)); /* dpr3c */ if (accel->de_wait() != 0) return -1; @@ -256,24 +245,18 @@ unsigned int rop2) /* ROP value */ { write_dpr(accel, DE_SOURCE, - FIELD_SET(0, DE_SOURCE, WRAP, DISABLE) | - FIELD_VALUE(0, DE_SOURCE, X_K1, sx) | - FIELD_VALUE(0, DE_SOURCE, Y_K2, sy)); /* dpr0 */ + ((sx << DE_SOURCE_X_K1_SHIFT) & DE_SOURCE_X_K1_MASK) | + (sy & DE_SOURCE_Y_K2_MASK)); /* dpr0 */ write_dpr(accel, DE_DESTINATION, - FIELD_SET(0, DE_DESTINATION, WRAP, DISABLE) | - FIELD_VALUE(0, DE_DESTINATION, X, dx) | - FIELD_VALUE(0, DE_DESTINATION, Y, dy)); /* dpr04 */ + ((dx << DE_DESTINATION_X_SHIFT) & DE_DESTINATION_X_MASK) | + (dy & DE_DESTINATION_Y_MASK)); /* dpr04 */ write_dpr(accel, DE_DIMENSION, - FIELD_VALUE(0, DE_DIMENSION, X, width) | - FIELD_VALUE(0, DE_DIMENSION, Y_ET, height)); /* dpr08 */ - - de_ctrl = FIELD_VALUE(0, DE_CONTROL, ROP, rop2) | - FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2) | - FIELD_SET(0, DE_CONTROL, COMMAND, BITBLT) | - ((nDirection == RIGHT_TO_LEFT) ? - FIELD_SET(0, DE_CONTROL, DIRECTION, RIGHT_TO_LEFT) - : FIELD_SET(0, DE_CONTROL, DIRECTION, LEFT_TO_RIGHT)) | - FIELD_SET(0, DE_CONTROL, STATUS, START); + ((width << DE_DIMENSION_X_SHIFT) & DE_DIMENSION_X_MASK) | + (height & DE_DIMENSION_Y_ET_MASK)); /* dpr08 */ + + de_ctrl = (rop2 & DE_CONTROL_ROP_MASK) | DE_CONTROL_ROP_SELECT | + ((nDirection == RIGHT_TO_LEFT) ? DE_CONTROL_DIRECTION : 0) | + DE_CONTROL_COMMAND_BITBLT | DE_CONTROL_STATUS; write_dpr(accel, DE_CONTROL, de_ctrl); /* dpr0c */ } @@ -287,10 +270,8 @@ static unsigned int deGetTransparency(struct lynx_accel *accel) de_ctrl = read_dpr(accel, DE_CONTROL); - de_ctrl &= - FIELD_MASK(DE_CONTROL_TRANSPARENCY_MATCH) | - FIELD_MASK(DE_CONTROL_TRANSPARENCY_SELECT)| - FIELD_MASK(DE_CONTROL_TRANSPARENCY); + de_ctrl &= (DE_CONTROL_TRANSPARENCY_MATCH | + DE_CONTROL_TRANSPARENCY_SELECT | DE_CONTROL_TRANSPARENCY); return de_ctrl; } @@ -305,7 +286,7 @@ int hw_imageblit(struct lynx_accel *accel, u32 dx, u32 dy, /* Starting coordinate of destination surface */ u32 width, - u32 height, /* width and height of rectange in pixel value */ + u32 height, /* width and height of rectangle in pixel value */ u32 fColor, /* Foreground color (corresponding to a 1 in the monochrome data */ u32 bColor, /* Background color (corresponding to a 0 in the monochrome data */ u32 rop2) /* ROP value */ @@ -338,42 +319,39 @@ int hw_imageblit(struct lynx_accel *accel, Note that input pitch is BYTE value, but the 2D Pitch register uses pixel values. Need Byte to pixel conversion. */ - { - write_dpr(accel, DE_PITCH, - FIELD_VALUE(0, DE_PITCH, DESTINATION, dPitch/bytePerPixel) | - FIELD_VALUE(0, DE_PITCH, SOURCE, dPitch/bytePerPixel)); /* dpr10 */ - } + write_dpr(accel, DE_PITCH, + ((dPitch / bytePerPixel << DE_PITCH_DESTINATION_SHIFT) & + DE_PITCH_DESTINATION_MASK) | + (dPitch / bytePerPixel & DE_PITCH_SOURCE_MASK)); /* dpr10 */ /* Screen Window width in Pixels. 2D engine uses this value to calculate the linear address in frame buffer for a given point. */ write_dpr(accel, DE_WINDOW_WIDTH, - FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, (dPitch/bytePerPixel)) | - FIELD_VALUE(0, DE_WINDOW_WIDTH, SOURCE, (dPitch/bytePerPixel))); + ((dPitch / bytePerPixel << DE_WINDOW_WIDTH_DST_SHIFT) & + DE_WINDOW_WIDTH_DST_MASK) | + (dPitch / bytePerPixel & DE_WINDOW_WIDTH_SRC_MASK)); /* Note: For 2D Source in Host Write, only X_K1_MONO field is needed, and Y_K2 field is not used. For mono bitmap, use startBit for X_K1. */ write_dpr(accel, DE_SOURCE, - FIELD_SET(0, DE_SOURCE, WRAP, DISABLE) | - FIELD_VALUE(0, DE_SOURCE, X_K1_MONO, startBit)); /* dpr00 */ + (startBit << DE_SOURCE_X_K1_SHIFT) & + DE_SOURCE_X_K1_MONO_MASK); /* dpr00 */ write_dpr(accel, DE_DESTINATION, - FIELD_SET(0, DE_DESTINATION, WRAP, DISABLE) | - FIELD_VALUE(0, DE_DESTINATION, X, dx) | - FIELD_VALUE(0, DE_DESTINATION, Y, dy)); /* dpr04 */ + ((dx << DE_DESTINATION_X_SHIFT) & DE_DESTINATION_X_MASK) | + (dy & DE_DESTINATION_Y_MASK)); /* dpr04 */ write_dpr(accel, DE_DIMENSION, - FIELD_VALUE(0, DE_DIMENSION, X, width) | - FIELD_VALUE(0, DE_DIMENSION, Y_ET, height)); /* dpr08 */ + ((width << DE_DIMENSION_X_SHIFT) & DE_DIMENSION_X_MASK) | + (height & DE_DIMENSION_Y_ET_MASK)); /* dpr08 */ write_dpr(accel, DE_FOREGROUND, fColor); write_dpr(accel, DE_BACKGROUND, bColor); - de_ctrl = FIELD_VALUE(0, DE_CONTROL, ROP, rop2) | - FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2) | - FIELD_SET(0, DE_CONTROL, COMMAND, HOST_WRITE) | - FIELD_SET(0, DE_CONTROL, HOST, MONO) | - FIELD_SET(0, DE_CONTROL, STATUS, START); + de_ctrl = (rop2 & DE_CONTROL_ROP_MASK) | + DE_CONTROL_ROP_SELECT | DE_CONTROL_COMMAND_HOST_WRITE | + DE_CONTROL_HOST | DE_CONTROL_STATUS; write_dpr(accel, DE_CONTROL, de_ctrl | deGetTransparency(accel)); diff --git a/drivers/staging/sm750fb/sm750_accel.h b/drivers/staging/sm750fb/sm750_accel.h index f252e47d5ee9..d59d005e0add 100644 --- a/drivers/staging/sm750fb/sm750_accel.h +++ b/drivers/staging/sm750fb/sm750_accel.h @@ -21,212 +21,162 @@ #define DE_PORT_ADDR_TYPE3 0x100000 #define DE_SOURCE 0x0 -#define DE_SOURCE_WRAP 31:31 -#define DE_SOURCE_WRAP_DISABLE 0 -#define DE_SOURCE_WRAP_ENABLE 1 -#define DE_SOURCE_X_K1 29:16 -#define DE_SOURCE_Y_K2 15:0 -#define DE_SOURCE_X_K1_MONO 20:16 +#define DE_SOURCE_WRAP BIT(31) +#define DE_SOURCE_X_K1_SHIFT 16 +#define DE_SOURCE_X_K1_MASK (0x3fff << 16) +#define DE_SOURCE_X_K1_MONO_MASK (0x1f << 16) +#define DE_SOURCE_Y_K2_MASK 0xffff #define DE_DESTINATION 0x4 -#define DE_DESTINATION_WRAP 31:31 -#define DE_DESTINATION_WRAP_DISABLE 0 -#define DE_DESTINATION_WRAP_ENABLE 1 -#define DE_DESTINATION_X 28:16 -#define DE_DESTINATION_Y 15:0 +#define DE_DESTINATION_WRAP BIT(31) +#define DE_DESTINATION_X_SHIFT 16 +#define DE_DESTINATION_X_MASK (0x1fff << 16) +#define DE_DESTINATION_Y_MASK 0xffff #define DE_DIMENSION 0x8 -#define DE_DIMENSION_X 28:16 -#define DE_DIMENSION_Y_ET 15:0 +#define DE_DIMENSION_X_SHIFT 16 +#define DE_DIMENSION_X_MASK (0x1fff << 16) +#define DE_DIMENSION_Y_ET_MASK 0x1fff #define DE_CONTROL 0xC -#define DE_CONTROL_STATUS 31:31 -#define DE_CONTROL_STATUS_STOP 0 -#define DE_CONTROL_STATUS_START 1 -#define DE_CONTROL_PATTERN 30:30 -#define DE_CONTROL_PATTERN_MONO 0 -#define DE_CONTROL_PATTERN_COLOR 1 -#define DE_CONTROL_UPDATE_DESTINATION_X 29:29 -#define DE_CONTROL_UPDATE_DESTINATION_X_DISABLE 0 -#define DE_CONTROL_UPDATE_DESTINATION_X_ENABLE 1 -#define DE_CONTROL_QUICK_START 28:28 -#define DE_CONTROL_QUICK_START_DISABLE 0 -#define DE_CONTROL_QUICK_START_ENABLE 1 -#define DE_CONTROL_DIRECTION 27:27 -#define DE_CONTROL_DIRECTION_LEFT_TO_RIGHT 0 -#define DE_CONTROL_DIRECTION_RIGHT_TO_LEFT 1 -#define DE_CONTROL_MAJOR 26:26 -#define DE_CONTROL_MAJOR_X 0 -#define DE_CONTROL_MAJOR_Y 1 -#define DE_CONTROL_STEP_X 25:25 -#define DE_CONTROL_STEP_X_POSITIVE 1 -#define DE_CONTROL_STEP_X_NEGATIVE 0 -#define DE_CONTROL_STEP_Y 24:24 -#define DE_CONTROL_STEP_Y_POSITIVE 1 -#define DE_CONTROL_STEP_Y_NEGATIVE 0 -#define DE_CONTROL_STRETCH 23:23 -#define DE_CONTROL_STRETCH_DISABLE 0 -#define DE_CONTROL_STRETCH_ENABLE 1 -#define DE_CONTROL_HOST 22:22 -#define DE_CONTROL_HOST_COLOR 0 -#define DE_CONTROL_HOST_MONO 1 -#define DE_CONTROL_LAST_PIXEL 21:21 -#define DE_CONTROL_LAST_PIXEL_OFF 0 -#define DE_CONTROL_LAST_PIXEL_ON 1 -#define DE_CONTROL_COMMAND 20:16 -#define DE_CONTROL_COMMAND_BITBLT 0 -#define DE_CONTROL_COMMAND_RECTANGLE_FILL 1 -#define DE_CONTROL_COMMAND_DE_TILE 2 -#define DE_CONTROL_COMMAND_TRAPEZOID_FILL 3 -#define DE_CONTROL_COMMAND_ALPHA_BLEND 4 -#define DE_CONTROL_COMMAND_RLE_STRIP 5 -#define DE_CONTROL_COMMAND_SHORT_STROKE 6 -#define DE_CONTROL_COMMAND_LINE_DRAW 7 -#define DE_CONTROL_COMMAND_HOST_WRITE 8 -#define DE_CONTROL_COMMAND_HOST_READ 9 -#define DE_CONTROL_COMMAND_HOST_WRITE_BOTTOM_UP 10 -#define DE_CONTROL_COMMAND_ROTATE 11 -#define DE_CONTROL_COMMAND_FONT 12 -#define DE_CONTROL_COMMAND_TEXTURE_LOAD 15 -#define DE_CONTROL_ROP_SELECT 15:15 -#define DE_CONTROL_ROP_SELECT_ROP3 0 -#define DE_CONTROL_ROP_SELECT_ROP2 1 -#define DE_CONTROL_ROP2_SOURCE 14:14 -#define DE_CONTROL_ROP2_SOURCE_BITMAP 0 -#define DE_CONTROL_ROP2_SOURCE_PATTERN 1 -#define DE_CONTROL_MONO_DATA 13:12 -#define DE_CONTROL_MONO_DATA_NOT_PACKED 0 -#define DE_CONTROL_MONO_DATA_8_PACKED 1 -#define DE_CONTROL_MONO_DATA_16_PACKED 2 -#define DE_CONTROL_MONO_DATA_32_PACKED 3 -#define DE_CONTROL_REPEAT_ROTATE 11:11 -#define DE_CONTROL_REPEAT_ROTATE_DISABLE 0 -#define DE_CONTROL_REPEAT_ROTATE_ENABLE 1 -#define DE_CONTROL_TRANSPARENCY_MATCH 10:10 -#define DE_CONTROL_TRANSPARENCY_MATCH_OPAQUE 0 -#define DE_CONTROL_TRANSPARENCY_MATCH_TRANSPARENT 1 -#define DE_CONTROL_TRANSPARENCY_SELECT 9:9 -#define DE_CONTROL_TRANSPARENCY_SELECT_SOURCE 0 -#define DE_CONTROL_TRANSPARENCY_SELECT_DESTINATION 1 -#define DE_CONTROL_TRANSPARENCY 8:8 -#define DE_CONTROL_TRANSPARENCY_DISABLE 0 -#define DE_CONTROL_TRANSPARENCY_ENABLE 1 -#define DE_CONTROL_ROP 7:0 +#define DE_CONTROL_STATUS BIT(31) +#define DE_CONTROL_PATTERN BIT(30) +#define DE_CONTROL_UPDATE_DESTINATION_X BIT(29) +#define DE_CONTROL_QUICK_START BIT(28) +#define DE_CONTROL_DIRECTION BIT(27) +#define DE_CONTROL_MAJOR BIT(26) +#define DE_CONTROL_STEP_X BIT(25) +#define DE_CONTROL_STEP_Y BIT(24) +#define DE_CONTROL_STRETCH BIT(23) +#define DE_CONTROL_HOST BIT(22) +#define DE_CONTROL_LAST_PIXEL BIT(21) +#define DE_CONTROL_COMMAND_SHIFT 16 +#define DE_CONTROL_COMMAND_MASK (0x1f << 16) +#define DE_CONTROL_COMMAND_BITBLT (0x0 << 16) +#define DE_CONTROL_COMMAND_RECTANGLE_FILL (0x1 << 16) +#define DE_CONTROL_COMMAND_DE_TILE (0x2 << 16) +#define DE_CONTROL_COMMAND_TRAPEZOID_FILL (0x3 << 16) +#define DE_CONTROL_COMMAND_ALPHA_BLEND (0x4 << 16) +#define DE_CONTROL_COMMAND_RLE_STRIP (0x5 << 16) +#define DE_CONTROL_COMMAND_SHORT_STROKE (0x6 << 16) +#define DE_CONTROL_COMMAND_LINE_DRAW (0x7 << 16) +#define DE_CONTROL_COMMAND_HOST_WRITE (0x8 << 16) +#define DE_CONTROL_COMMAND_HOST_READ (0x9 << 16) +#define DE_CONTROL_COMMAND_HOST_WRITE_BOTTOM_UP (0xa << 16) +#define DE_CONTROL_COMMAND_ROTATE (0xb << 16) +#define DE_CONTROL_COMMAND_FONT (0xc << 16) +#define DE_CONTROL_COMMAND_TEXTURE_LOAD (0xe << 16) +#define DE_CONTROL_ROP_SELECT BIT(15) +#define DE_CONTROL_ROP2_SOURCE BIT(14) +#define DE_CONTROL_MONO_DATA_SHIFT 12 +#define DE_CONTROL_MONO_DATA_MASK (0x3 << 12) +#define DE_CONTROL_MONO_DATA_NOT_PACKED (0x0 << 12) +#define DE_CONTROL_MONO_DATA_8_PACKED (0x1 << 12) +#define DE_CONTROL_MONO_DATA_16_PACKED (0x2 << 12) +#define DE_CONTROL_MONO_DATA_32_PACKED (0x3 << 12) +#define DE_CONTROL_REPEAT_ROTATE BIT(11) +#define DE_CONTROL_TRANSPARENCY_MATCH BIT(10) +#define DE_CONTROL_TRANSPARENCY_SELECT BIT(9) +#define DE_CONTROL_TRANSPARENCY BIT(8) +#define DE_CONTROL_ROP_MASK 0xff /* Pseudo fields. */ -#define DE_CONTROL_SHORT_STROKE_DIR 27:24 -#define DE_CONTROL_SHORT_STROKE_DIR_225 0 -#define DE_CONTROL_SHORT_STROKE_DIR_135 1 -#define DE_CONTROL_SHORT_STROKE_DIR_315 2 -#define DE_CONTROL_SHORT_STROKE_DIR_45 3 -#define DE_CONTROL_SHORT_STROKE_DIR_270 4 -#define DE_CONTROL_SHORT_STROKE_DIR_90 5 -#define DE_CONTROL_SHORT_STROKE_DIR_180 8 -#define DE_CONTROL_SHORT_STROKE_DIR_0 10 -#define DE_CONTROL_ROTATION 25:24 -#define DE_CONTROL_ROTATION_0 0 -#define DE_CONTROL_ROTATION_270 1 -#define DE_CONTROL_ROTATION_90 2 -#define DE_CONTROL_ROTATION_180 3 +#define DE_CONTROL_SHORT_STROKE_DIR_MASK (0xf << 24) +#define DE_CONTROL_SHORT_STROKE_DIR_225 (0x0 << 24) +#define DE_CONTROL_SHORT_STROKE_DIR_135 (0x1 << 24) +#define DE_CONTROL_SHORT_STROKE_DIR_315 (0x2 << 24) +#define DE_CONTROL_SHORT_STROKE_DIR_45 (0x3 << 24) +#define DE_CONTROL_SHORT_STROKE_DIR_270 (0x4 << 24) +#define DE_CONTROL_SHORT_STROKE_DIR_90 (0x5 << 24) +#define DE_CONTROL_SHORT_STROKE_DIR_180 (0x8 << 24) +#define DE_CONTROL_SHORT_STROKE_DIR_0 (0xa << 24) +#define DE_CONTROL_ROTATION_MASK (0x3 << 24) +#define DE_CONTROL_ROTATION_0 (0x0 << 24) +#define DE_CONTROL_ROTATION_270 (0x1 << 24) +#define DE_CONTROL_ROTATION_90 (0x2 << 24) +#define DE_CONTROL_ROTATION_180 (0x3 << 24) #define DE_PITCH 0x000010 -#define DE_PITCH_DESTINATION 28:16 -#define DE_PITCH_SOURCE 12:0 +#define DE_PITCH_DESTINATION_SHIFT 16 +#define DE_PITCH_DESTINATION_MASK (0x1fff << 16) +#define DE_PITCH_SOURCE_MASK 0x1fff #define DE_FOREGROUND 0x000014 -#define DE_FOREGROUND_COLOR 31:0 +#define DE_FOREGROUND_COLOR_MASK 0xffffffff #define DE_BACKGROUND 0x000018 -#define DE_BACKGROUND_COLOR 31:0 +#define DE_BACKGROUND_COLOR_MASK 0xffffffff #define DE_STRETCH_FORMAT 0x00001C -#define DE_STRETCH_FORMAT_PATTERN_XY 30:30 -#define DE_STRETCH_FORMAT_PATTERN_XY_NORMAL 0 -#define DE_STRETCH_FORMAT_PATTERN_XY_OVERWRITE 1 -#define DE_STRETCH_FORMAT_PATTERN_Y 29:27 -#define DE_STRETCH_FORMAT_PATTERN_X 25:23 -#define DE_STRETCH_FORMAT_PIXEL_FORMAT 21:20 -#define DE_STRETCH_FORMAT_PIXEL_FORMAT_8 0 -#define DE_STRETCH_FORMAT_PIXEL_FORMAT_16 1 -#define DE_STRETCH_FORMAT_PIXEL_FORMAT_32 2 -#define DE_STRETCH_FORMAT_PIXEL_FORMAT_24 3 - -#define DE_STRETCH_FORMAT_ADDRESSING 19:16 -#define DE_STRETCH_FORMAT_ADDRESSING_XY 0 -#define DE_STRETCH_FORMAT_ADDRESSING_LINEAR 15 -#define DE_STRETCH_FORMAT_SOURCE_HEIGHT 11:0 +#define DE_STRETCH_FORMAT_PATTERN_XY BIT(30) +#define DE_STRETCH_FORMAT_PATTERN_Y_SHIFT 27 +#define DE_STRETCH_FORMAT_PATTERN_Y_MASK (0x7 << 27) +#define DE_STRETCH_FORMAT_PATTERN_X_SHIFT 23 +#define DE_STRETCH_FORMAT_PATTERN_X_MASK (0x7 << 23) +#define DE_STRETCH_FORMAT_PIXEL_FORMAT_SHIFT 20 +#define DE_STRETCH_FORMAT_PIXEL_FORMAT_MASK (0x3 << 20) +#define DE_STRETCH_FORMAT_PIXEL_FORMAT_8 (0x0 << 20) +#define DE_STRETCH_FORMAT_PIXEL_FORMAT_16 (0x1 << 20) +#define DE_STRETCH_FORMAT_PIXEL_FORMAT_32 (0x2 << 20) +#define DE_STRETCH_FORMAT_PIXEL_FORMAT_24 (0x3 << 20) +#define DE_STRETCH_FORMAT_ADDRESSING_SHIFT 16 +#define DE_STRETCH_FORMAT_ADDRESSING_MASK (0xf << 16) +#define DE_STRETCH_FORMAT_ADDRESSING_XY (0x0 << 16) +#define DE_STRETCH_FORMAT_ADDRESSING_LINEAR (0xf << 16) +#define DE_STRETCH_FORMAT_SOURCE_HEIGHT_MASK 0xfff #define DE_COLOR_COMPARE 0x000020 -#define DE_COLOR_COMPARE_COLOR 23:0 +#define DE_COLOR_COMPARE_COLOR_MASK 0xffffff #define DE_COLOR_COMPARE_MASK 0x000024 -#define DE_COLOR_COMPARE_MASK_MASKS 23:0 +#define DE_COLOR_COMPARE_MASK_MASK 0xffffff #define DE_MASKS 0x000028 -#define DE_MASKS_BYTE_MASK 31:16 -#define DE_MASKS_BIT_MASK 15:0 +#define DE_MASKS_BYTE_MASK (0xffff << 16) +#define DE_MASKS_BIT_MASK 0xffff #define DE_CLIP_TL 0x00002C -#define DE_CLIP_TL_TOP 31:16 -#define DE_CLIP_TL_STATUS 13:13 -#define DE_CLIP_TL_STATUS_DISABLE 0 -#define DE_CLIP_TL_STATUS_ENABLE 1 -#define DE_CLIP_TL_INHIBIT 12:12 -#define DE_CLIP_TL_INHIBIT_OUTSIDE 0 -#define DE_CLIP_TL_INHIBIT_INSIDE 1 -#define DE_CLIP_TL_LEFT 11:0 +#define DE_CLIP_TL_TOP_MASK (0xffff << 16) +#define DE_CLIP_TL_STATUS BIT(13) +#define DE_CLIP_TL_INHIBIT BIT(12) +#define DE_CLIP_TL_LEFT_MASK 0xfff #define DE_CLIP_BR 0x000030 -#define DE_CLIP_BR_BOTTOM 31:16 -#define DE_CLIP_BR_RIGHT 12:0 +#define DE_CLIP_BR_BOTTOM_MASK (0xffff << 16) +#define DE_CLIP_BR_RIGHT_MASK 0x1fff #define DE_MONO_PATTERN_LOW 0x000034 -#define DE_MONO_PATTERN_LOW_PATTERN 31:0 +#define DE_MONO_PATTERN_LOW_PATTERN_MASK 0xffffffff #define DE_MONO_PATTERN_HIGH 0x000038 -#define DE_MONO_PATTERN_HIGH_PATTERN 31:0 +#define DE_MONO_PATTERN_HIGH_PATTERN_MASK 0xffffffff #define DE_WINDOW_WIDTH 0x00003C -#define DE_WINDOW_WIDTH_DESTINATION 28:16 -#define DE_WINDOW_WIDTH_SOURCE 12:0 +#define DE_WINDOW_WIDTH_DST_SHIFT 16 +#define DE_WINDOW_WIDTH_DST_MASK (0x1fff << 16) +#define DE_WINDOW_WIDTH_SRC_MASK 0x1fff #define DE_WINDOW_SOURCE_BASE 0x000040 -#define DE_WINDOW_SOURCE_BASE_EXT 27:27 -#define DE_WINDOW_SOURCE_BASE_EXT_LOCAL 0 -#define DE_WINDOW_SOURCE_BASE_EXT_EXTERNAL 1 -#define DE_WINDOW_SOURCE_BASE_CS 26:26 -#define DE_WINDOW_SOURCE_BASE_CS_0 0 -#define DE_WINDOW_SOURCE_BASE_CS_1 1 -#define DE_WINDOW_SOURCE_BASE_ADDRESS 25:0 +#define DE_WINDOW_SOURCE_BASE_EXT BIT(27) +#define DE_WINDOW_SOURCE_BASE_CS BIT(26) +#define DE_WINDOW_SOURCE_BASE_ADDRESS_MASK 0x3ffffff #define DE_WINDOW_DESTINATION_BASE 0x000044 -#define DE_WINDOW_DESTINATION_BASE_EXT 27:27 -#define DE_WINDOW_DESTINATION_BASE_EXT_LOCAL 0 -#define DE_WINDOW_DESTINATION_BASE_EXT_EXTERNAL 1 -#define DE_WINDOW_DESTINATION_BASE_CS 26:26 -#define DE_WINDOW_DESTINATION_BASE_CS_0 0 -#define DE_WINDOW_DESTINATION_BASE_CS_1 1 -#define DE_WINDOW_DESTINATION_BASE_ADDRESS 25:0 +#define DE_WINDOW_DESTINATION_BASE_EXT BIT(27) +#define DE_WINDOW_DESTINATION_BASE_CS BIT(26) +#define DE_WINDOW_DESTINATION_BASE_ADDRESS_MASK 0x3ffffff #define DE_ALPHA 0x000048 -#define DE_ALPHA_VALUE 7:0 +#define DE_ALPHA_VALUE_MASK 0xff #define DE_WRAP 0x00004C -#define DE_WRAP_X 31:16 -#define DE_WRAP_Y 15:0 +#define DE_WRAP_X_MASK (0xffff << 16) +#define DE_WRAP_Y_MASK 0xffff #define DE_STATUS 0x000050 -#define DE_STATUS_CSC 1:1 -#define DE_STATUS_CSC_CLEAR 0 -#define DE_STATUS_CSC_NOT_ACTIVE 0 -#define DE_STATUS_CSC_ACTIVE 1 -#define DE_STATUS_2D 0:0 -#define DE_STATUS_2D_CLEAR 0 -#define DE_STATUS_2D_NOT_ACTIVE 0 -#define DE_STATUS_2D_ACTIVE 1 - - +#define DE_STATUS_CSC BIT(1) +#define DE_STATUS_2D BIT(0) /* blt direction */ #define TOP_TO_BOTTOM 0 @@ -268,7 +218,7 @@ int hw_imageblit(struct lynx_accel *accel, u32 dx, u32 dy, /* Starting coordinate of destination surface */ u32 width, - u32 height, /* width and height of rectange in pixel value */ + u32 height, /* width and height of rectangle in pixel value */ u32 fColor, /* Foreground color (corresponding to a 1 in the monochrome data */ u32 bColor, /* Background color (corresponding to a 0 in the monochrome data */ u32 rop2); diff --git a/drivers/staging/sm750fb/sm750_cursor.c b/drivers/staging/sm750fb/sm750_cursor.c index 3b7ce9275f51..d622d65b6cee 100644 --- a/drivers/staging/sm750fb/sm750_cursor.c +++ b/drivers/staging/sm750fb/sm750_cursor.c @@ -16,45 +16,34 @@ #include <linux/screen_info.h> #include "sm750.h" -#include "sm750_help.h" #include "sm750_cursor.h" -#define PEEK32(addr) \ -readl(cursor->mmio + (addr)) #define POKE32(addr, data) \ writel((data), cursor->mmio + (addr)) /* cursor control for voyager and 718/750*/ #define HWC_ADDRESS 0x0 -#define HWC_ADDRESS_ENABLE 31:31 -#define HWC_ADDRESS_ENABLE_DISABLE 0 -#define HWC_ADDRESS_ENABLE_ENABLE 1 -#define HWC_ADDRESS_EXT 27:27 -#define HWC_ADDRESS_EXT_LOCAL 0 -#define HWC_ADDRESS_EXT_EXTERNAL 1 -#define HWC_ADDRESS_CS 26:26 -#define HWC_ADDRESS_CS_0 0 -#define HWC_ADDRESS_CS_1 1 -#define HWC_ADDRESS_ADDRESS 25:0 +#define HWC_ADDRESS_ENABLE BIT(31) +#define HWC_ADDRESS_EXT BIT(27) +#define HWC_ADDRESS_CS BIT(26) +#define HWC_ADDRESS_ADDRESS_MASK 0x3ffffff #define HWC_LOCATION 0x4 -#define HWC_LOCATION_TOP 27:27 -#define HWC_LOCATION_TOP_INSIDE 0 -#define HWC_LOCATION_TOP_OUTSIDE 1 -#define HWC_LOCATION_Y 26:16 -#define HWC_LOCATION_LEFT 11:11 -#define HWC_LOCATION_LEFT_INSIDE 0 -#define HWC_LOCATION_LEFT_OUTSIDE 1 -#define HWC_LOCATION_X 10:0 +#define HWC_LOCATION_TOP BIT(27) +#define HWC_LOCATION_Y_SHIFT 16 +#define HWC_LOCATION_Y_MASK (0x7ff << 16) +#define HWC_LOCATION_LEFT BIT(11) +#define HWC_LOCATION_X_MASK 0x7ff #define HWC_COLOR_12 0x8 -#define HWC_COLOR_12_2_RGB565 31:16 -#define HWC_COLOR_12_1_RGB565 15:0 +#define HWC_COLOR_12_2_RGB565_SHIFT 16 +#define HWC_COLOR_12_2_RGB565_MASK (0xffff << 16) +#define HWC_COLOR_12_1_RGB565_MASK 0xffff #define HWC_COLOR_3 0xC -#define HWC_COLOR_3_RGB565 15:0 +#define HWC_COLOR_3_RGB565_MASK 0xffff /* hw_cursor_xxx works for voyager,718 and 750 */ @@ -62,9 +51,7 @@ void hw_cursor_enable(struct lynx_cursor *cursor) { u32 reg; - reg = FIELD_VALUE(0, HWC_ADDRESS, ADDRESS, cursor->offset)| - FIELD_SET(0, HWC_ADDRESS, EXT, LOCAL)| - FIELD_SET(0, HWC_ADDRESS, ENABLE, ENABLE); + reg = (cursor->offset & HWC_ADDRESS_ADDRESS_MASK) | HWC_ADDRESS_ENABLE; POKE32(HWC_ADDRESS, reg); } void hw_cursor_disable(struct lynx_cursor *cursor) @@ -83,14 +70,17 @@ void hw_cursor_setPos(struct lynx_cursor *cursor, { u32 reg; - reg = FIELD_VALUE(0, HWC_LOCATION, Y, y)| - FIELD_VALUE(0, HWC_LOCATION, X, x); + reg = (((y << HWC_LOCATION_Y_SHIFT) & HWC_LOCATION_Y_MASK) | + (x & HWC_LOCATION_X_MASK)); POKE32(HWC_LOCATION, reg); } void hw_cursor_setColor(struct lynx_cursor *cursor, u32 fg, u32 bg) { - POKE32(HWC_COLOR_12, (fg<<16)|(bg&0xffff)); + u32 reg = (fg << HWC_COLOR_12_2_RGB565_SHIFT) & + HWC_COLOR_12_2_RGB565_MASK; + + POKE32(HWC_COLOR_12, reg | (bg & HWC_COLOR_12_1_RGB565_MASK)); POKE32(HWC_COLOR_3, 0xffe0); } @@ -115,15 +105,6 @@ void hw_cursor_setData(struct lynx_cursor *cursor, pstart = cursor->vstart; pbuffer = pstart; -/* - if(odd &1){ - hw_cursor_setData2(cursor,rop,pcol,pmsk); - } - odd++; - if(odd > 0xfffffff0) - odd=0; -*/ - for (i = 0; i < count; i++) { color = *pcol++; mask = *pmsk++; @@ -143,8 +124,7 @@ void hw_cursor_setData(struct lynx_cursor *cursor, iowrite16(data, pbuffer); /* assume pitch is 1,2,4,8,...*/ - if ((i+1) % pitch == 0) - { + if ((i + 1) % pitch == 0) { /* need a return */ pstart += offset; pbuffer = pstart; diff --git a/drivers/staging/sm750fb/sm750_help.h b/drivers/staging/sm750fb/sm750_help.h deleted file mode 100644 index c070cf25a7d6..000000000000 --- a/drivers/staging/sm750fb/sm750_help.h +++ /dev/null @@ -1,56 +0,0 @@ -#ifndef LYNX_HELP_H__ -#define LYNX_HELP_H__ - -/* Internal macros */ -#define _F_START(f) (0 ? f) -#define _F_END(f) (1 ? f) -#define _F_SIZE(f) (1 + _F_END(f) - _F_START(f)) -#define _F_MASK(f) (((1 << _F_SIZE(f)) - 1) << _F_START(f)) -#define _F_NORMALIZE(v, f) (((v) & _F_MASK(f)) >> _F_START(f)) -#define _F_DENORMALIZE(v, f) (((v) << _F_START(f)) & _F_MASK(f)) - -/* Global macros */ -#define FIELD_GET(x, reg, field) \ -( \ - _F_NORMALIZE((x), reg ## _ ## field) \ -) - -#define FIELD_SET(x, reg, field, value) \ -( \ - (x & ~_F_MASK(reg ## _ ## field)) \ - | _F_DENORMALIZE(reg ## _ ## field ## _ ## value, reg ## _ ## field) \ -) - -#define FIELD_VALUE(x, reg, field, value) \ -( \ - (x & ~_F_MASK(reg ## _ ## field)) \ - | _F_DENORMALIZE(value, reg ## _ ## field) \ -) - -#define FIELD_CLEAR(reg, field) \ -( \ - ~_F_MASK(reg ## _ ## field) \ -) - -/* Field Macros */ -#define FIELD_START(field) (0 ? field) -#define FIELD_END(field) (1 ? field) -#define FIELD_SIZE(field) (1 + FIELD_END(field) - FIELD_START(field)) -#define FIELD_MASK(field) (((1 << (FIELD_SIZE(field)-1)) | ((1 << (FIELD_SIZE(field)-1)) - 1)) << FIELD_START(field)) - -static inline unsigned int absDiff(unsigned int a, unsigned int b) -{ - if (a < b) - return b-a; - else - return a-b; -} - -/* n / d + 1 / 2 = (2n + d) / 2d */ -#define roundedDiv(num, denom) ((2 * (num) + (denom)) / (2 * (denom))) -#define MHz(x) ((x) * 1000000) - - - - -#endif diff --git a/drivers/staging/sm750fb/sm750_hw.c b/drivers/staging/sm750fb/sm750_hw.c index 41822c6c0380..2daeedd88c30 100644 --- a/drivers/staging/sm750fb/sm750_hw.c +++ b/drivers/staging/sm750fb/sm750_hw.c @@ -1,4 +1,3 @@ -#include <linux/version.h> #include <linux/module.h> #include <linux/kernel.h> #include <linux/errno.h> @@ -108,65 +107,62 @@ int hw_sm750_inithw(struct sm750_dev *sm750_dev, struct pci_dev *pdev) /* for sm718,open pci burst */ if (sm750_dev->devid == 0x718) { POKE32(SYSTEM_CTRL, - FIELD_SET(PEEK32(SYSTEM_CTRL), SYSTEM_CTRL, PCI_BURST, ON)); + PEEK32(SYSTEM_CTRL) | SYSTEM_CTRL_PCI_BURST); } if (getChipType() != SM750LE) { + unsigned int val; /* does user need CRT ?*/ if (sm750_dev->nocrt) { POKE32(MISC_CTRL, - FIELD_SET(PEEK32(MISC_CTRL), - MISC_CTRL, - DAC_POWER, OFF)); + PEEK32(MISC_CTRL) | MISC_CTRL_DAC_POWER_OFF); /* shut off dpms */ - POKE32(SYSTEM_CTRL, - FIELD_SET(PEEK32(SYSTEM_CTRL), - SYSTEM_CTRL, - DPMS, VNHN)); + val = PEEK32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK; + val |= SYSTEM_CTRL_DPMS_VPHN; + POKE32(SYSTEM_CTRL, val); } else { POKE32(MISC_CTRL, - FIELD_SET(PEEK32(MISC_CTRL), - MISC_CTRL, - DAC_POWER, ON)); + PEEK32(MISC_CTRL) & ~MISC_CTRL_DAC_POWER_OFF); /* turn on dpms */ - POKE32(SYSTEM_CTRL, - FIELD_SET(PEEK32(SYSTEM_CTRL), - SYSTEM_CTRL, - DPMS, VPHP)); + val = PEEK32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK; + val |= SYSTEM_CTRL_DPMS_VPHP; + POKE32(SYSTEM_CTRL, val); } + val = PEEK32(PANEL_DISPLAY_CTRL) & + ~(PANEL_DISPLAY_CTRL_DUAL_DISPLAY | + PANEL_DISPLAY_CTRL_DOUBLE_PIXEL); switch (sm750_dev->pnltype) { - case sm750_doubleTFT: case sm750_24TFT: + break; + case sm750_doubleTFT: + val |= PANEL_DISPLAY_CTRL_DOUBLE_PIXEL; + break; case sm750_dualTFT: - POKE32(PANEL_DISPLAY_CTRL, - FIELD_VALUE(PEEK32(PANEL_DISPLAY_CTRL), - PANEL_DISPLAY_CTRL, - TFT_DISP, - sm750_dev->pnltype)); - break; + val |= PANEL_DISPLAY_CTRL_DUAL_DISPLAY; + break; } + POKE32(PANEL_DISPLAY_CTRL, val); } else { - /* for 750LE ,no DVI chip initilization makes Monitor no signal */ + /* for 750LE ,no DVI chip initialization makes Monitor no signal */ /* Set up GPIO for software I2C to program DVI chip in the Xilinx SP605 board, in order to have video signal. */ - sm750_sw_i2c_init(0, 1); + sm750_sw_i2c_init(0, 1); - - /* Customer may NOT use CH7301 DVI chip, which has to be - initialized differently. - */ - if (sm750_sw_i2c_read_reg(0xec, 0x4a) == 0x95) { + /* Customer may NOT use CH7301 DVI chip, which has to be + initialized differently. + */ + if (sm750_sw_i2c_read_reg(0xec, 0x4a) == 0x95) { /* The following register values for CH7301 are from Chrontel app note and our experiment. */ pr_info("yes,CH7301 DVI chip found\n"); - sm750_sw_i2c_write_reg(0xec, 0x1d, 0x16); - sm750_sw_i2c_write_reg(0xec, 0x21, 0x9); - sm750_sw_i2c_write_reg(0xec, 0x49, 0xC0); + sm750_sw_i2c_write_reg(0xec, 0x1d, 0x16); + sm750_sw_i2c_write_reg(0xec, 0x21, 0x9); + sm750_sw_i2c_write_reg(0xec, 0x49, 0xC0); pr_info("okay,CH7301 DVI chip setup done\n"); - } + } } /* init 2d engine */ @@ -310,53 +306,51 @@ int hw_sm750_crtc_setMode(struct lynxfb_crtc *crtc, if (crtc->channel != sm750_secondary) { /* set pitch, offset ,width,start address ,etc... */ POKE32(PANEL_FB_ADDRESS, - FIELD_SET(0, PANEL_FB_ADDRESS, STATUS, CURRENT)| - FIELD_SET(0, PANEL_FB_ADDRESS, EXT, LOCAL)| - FIELD_VALUE(0, PANEL_FB_ADDRESS, ADDRESS, crtc->oScreen)); + crtc->oScreen & PANEL_FB_ADDRESS_ADDRESS_MASK); reg = var->xres * (var->bits_per_pixel >> 3); /* crtc->channel is not equal to par->index on numeric,be aware of that */ reg = ALIGN(reg, crtc->line_pad); - - POKE32(PANEL_FB_WIDTH, - FIELD_VALUE(0, PANEL_FB_WIDTH, WIDTH, reg)| - FIELD_VALUE(0, PANEL_FB_WIDTH, OFFSET, fix->line_length)); - - POKE32(PANEL_WINDOW_WIDTH, - FIELD_VALUE(0, PANEL_WINDOW_WIDTH, WIDTH, var->xres - 1)| - FIELD_VALUE(0, PANEL_WINDOW_WIDTH, X, var->xoffset)); - - POKE32(PANEL_WINDOW_HEIGHT, - FIELD_VALUE(0, PANEL_WINDOW_HEIGHT, HEIGHT, var->yres_virtual - 1)| - FIELD_VALUE(0, PANEL_WINDOW_HEIGHT, Y, var->yoffset)); + reg = (reg << PANEL_FB_WIDTH_WIDTH_SHIFT) & + PANEL_FB_WIDTH_WIDTH_MASK; + reg |= (fix->line_length & PANEL_FB_WIDTH_OFFSET_MASK); + POKE32(PANEL_FB_WIDTH, reg); + + reg = ((var->xres - 1) << PANEL_WINDOW_WIDTH_WIDTH_SHIFT) & + PANEL_WINDOW_WIDTH_WIDTH_MASK; + reg |= (var->xoffset & PANEL_WINDOW_WIDTH_X_MASK); + POKE32(PANEL_WINDOW_WIDTH, reg); + + reg = ((var->yres_virtual - 1) << + PANEL_WINDOW_HEIGHT_HEIGHT_SHIFT); + reg &= PANEL_WINDOW_HEIGHT_HEIGHT_MASK; + reg |= (var->yoffset & PANEL_WINDOW_HEIGHT_Y_MASK); + POKE32(PANEL_WINDOW_HEIGHT, reg); POKE32(PANEL_PLANE_TL, 0); - POKE32(PANEL_PLANE_BR, - FIELD_VALUE(0, PANEL_PLANE_BR, BOTTOM, var->yres - 1)| - FIELD_VALUE(0, PANEL_PLANE_BR, RIGHT, var->xres - 1)); + reg = ((var->yres - 1) << PANEL_PLANE_BR_BOTTOM_SHIFT) & + PANEL_PLANE_BR_BOTTOM_MASK; + reg |= ((var->xres - 1) & PANEL_PLANE_BR_RIGHT_MASK); + POKE32(PANEL_PLANE_BR, reg); /* set pixel format */ reg = PEEK32(PANEL_DISPLAY_CTRL); - POKE32(PANEL_DISPLAY_CTRL, - FIELD_VALUE(reg, - PANEL_DISPLAY_CTRL, FORMAT, - (var->bits_per_pixel >> 4) - )); + POKE32(PANEL_DISPLAY_CTRL, reg | (var->bits_per_pixel >> 4)); } else { /* not implemented now */ POKE32(CRT_FB_ADDRESS, crtc->oScreen); reg = var->xres * (var->bits_per_pixel >> 3); /* crtc->channel is not equal to par->index on numeric,be aware of that */ - reg = ALIGN(reg, crtc->line_pad); - - POKE32(CRT_FB_WIDTH, - FIELD_VALUE(0, CRT_FB_WIDTH, WIDTH, reg)| - FIELD_VALUE(0, CRT_FB_WIDTH, OFFSET, fix->line_length)); + reg = ALIGN(reg, crtc->line_pad) << CRT_FB_WIDTH_WIDTH_SHIFT; + reg &= CRT_FB_WIDTH_WIDTH_MASK; + reg |= (fix->line_length & CRT_FB_WIDTH_OFFSET_MASK); + POKE32(CRT_FB_WIDTH, reg); /* SET PIXEL FORMAT */ reg = PEEK32(CRT_DISPLAY_CTRL); - reg = FIELD_VALUE(reg, CRT_DISPLAY_CTRL, FORMAT, var->bits_per_pixel >> 4); + reg |= ((var->bits_per_pixel >> 4) & + CRT_DISPLAY_CTRL_FORMAT_MASK); POKE32(CRT_DISPLAY_CTRL, reg); } @@ -382,31 +376,36 @@ int hw_sm750le_setBLANK(struct lynxfb_output *output, int blank) switch (blank) { case FB_BLANK_UNBLANK: dpms = CRT_DISPLAY_CTRL_DPMS_0; - crtdb = CRT_DISPLAY_CTRL_BLANK_OFF; + crtdb = 0; break; case FB_BLANK_NORMAL: dpms = CRT_DISPLAY_CTRL_DPMS_0; - crtdb = CRT_DISPLAY_CTRL_BLANK_ON; + crtdb = CRT_DISPLAY_CTRL_BLANK; break; case FB_BLANK_VSYNC_SUSPEND: dpms = CRT_DISPLAY_CTRL_DPMS_2; - crtdb = CRT_DISPLAY_CTRL_BLANK_ON; + crtdb = CRT_DISPLAY_CTRL_BLANK; break; case FB_BLANK_HSYNC_SUSPEND: dpms = CRT_DISPLAY_CTRL_DPMS_1; - crtdb = CRT_DISPLAY_CTRL_BLANK_ON; + crtdb = CRT_DISPLAY_CTRL_BLANK; break; case FB_BLANK_POWERDOWN: dpms = CRT_DISPLAY_CTRL_DPMS_3; - crtdb = CRT_DISPLAY_CTRL_BLANK_ON; + crtdb = CRT_DISPLAY_CTRL_BLANK; break; default: return -EINVAL; } if (output->paths & sm750_crt) { - POKE32(CRT_DISPLAY_CTRL, FIELD_VALUE(PEEK32(CRT_DISPLAY_CTRL), CRT_DISPLAY_CTRL, DPMS, dpms)); - POKE32(CRT_DISPLAY_CTRL, FIELD_VALUE(PEEK32(CRT_DISPLAY_CTRL), CRT_DISPLAY_CTRL, BLANK, crtdb)); + unsigned int val; + + val = PEEK32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_DPMS_MASK; + POKE32(CRT_DISPLAY_CTRL, val | dpms); + + val = PEEK32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_BLANK; + POKE32(CRT_DISPLAY_CTRL, val | crtdb); } return 0; } @@ -419,42 +418,45 @@ int hw_sm750_setBLANK(struct lynxfb_output *output, int blank) switch (blank) { case FB_BLANK_UNBLANK: - pr_info("flag = FB_BLANK_UNBLANK\n"); + pr_debug("flag = FB_BLANK_UNBLANK\n"); dpms = SYSTEM_CTRL_DPMS_VPHP; - pps = PANEL_DISPLAY_CTRL_DATA_ENABLE; - crtdb = CRT_DISPLAY_CTRL_BLANK_OFF; + pps = PANEL_DISPLAY_CTRL_DATA; break; case FB_BLANK_NORMAL: - pr_info("flag = FB_BLANK_NORMAL\n"); + pr_debug("flag = FB_BLANK_NORMAL\n"); dpms = SYSTEM_CTRL_DPMS_VPHP; - pps = PANEL_DISPLAY_CTRL_DATA_DISABLE; - crtdb = CRT_DISPLAY_CTRL_BLANK_ON; + crtdb = CRT_DISPLAY_CTRL_BLANK; break; case FB_BLANK_VSYNC_SUSPEND: dpms = SYSTEM_CTRL_DPMS_VNHP; - pps = PANEL_DISPLAY_CTRL_DATA_DISABLE; - crtdb = CRT_DISPLAY_CTRL_BLANK_ON; + crtdb = CRT_DISPLAY_CTRL_BLANK; break; case FB_BLANK_HSYNC_SUSPEND: dpms = SYSTEM_CTRL_DPMS_VPHN; - pps = PANEL_DISPLAY_CTRL_DATA_DISABLE; - crtdb = CRT_DISPLAY_CTRL_BLANK_ON; + crtdb = CRT_DISPLAY_CTRL_BLANK; break; case FB_BLANK_POWERDOWN: dpms = SYSTEM_CTRL_DPMS_VNHN; - pps = PANEL_DISPLAY_CTRL_DATA_DISABLE; - crtdb = CRT_DISPLAY_CTRL_BLANK_ON; + crtdb = CRT_DISPLAY_CTRL_BLANK; break; } if (output->paths & sm750_crt) { + unsigned int val = PEEK32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK; - POKE32(SYSTEM_CTRL, FIELD_VALUE(PEEK32(SYSTEM_CTRL), SYSTEM_CTRL, DPMS, dpms)); - POKE32(CRT_DISPLAY_CTRL, FIELD_VALUE(PEEK32(CRT_DISPLAY_CTRL), CRT_DISPLAY_CTRL, BLANK, crtdb)); + POKE32(SYSTEM_CTRL, val | dpms); + + val = PEEK32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_BLANK; + POKE32(CRT_DISPLAY_CTRL, val | crtdb); } - if (output->paths & sm750_panel) - POKE32(PANEL_DISPLAY_CTRL, FIELD_VALUE(PEEK32(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, DATA, pps)); + if (output->paths & sm750_panel) { + unsigned int val = PEEK32(PANEL_DISPLAY_CTRL); + + val &= ~PANEL_DISPLAY_CTRL_DATA; + val |= pps; + POKE32(PANEL_DISPLAY_CTRL, val); + } return 0; } @@ -468,21 +470,21 @@ void hw_sm750_initAccel(struct sm750_dev *sm750_dev) if (getChipType() == SM750LE) { reg = PEEK32(DE_STATE1); - reg = FIELD_SET(reg, DE_STATE1, DE_ABORT, ON); + reg |= DE_STATE1_DE_ABORT; POKE32(DE_STATE1, reg); reg = PEEK32(DE_STATE1); - reg = FIELD_SET(reg, DE_STATE1, DE_ABORT, OFF); + reg &= ~DE_STATE1_DE_ABORT; POKE32(DE_STATE1, reg); } else { /* engine reset */ reg = PEEK32(SYSTEM_CTRL); - reg = FIELD_SET(reg, SYSTEM_CTRL, DE_ABORT, ON); + reg |= SYSTEM_CTRL_DE_ABORT; POKE32(SYSTEM_CTRL, reg); reg = PEEK32(SYSTEM_CTRL); - reg = FIELD_SET(reg, SYSTEM_CTRL, DE_ABORT, OFF); + reg &= ~SYSTEM_CTRL_DE_ABORT; POKE32(SYSTEM_CTRL, reg); } @@ -493,15 +495,15 @@ void hw_sm750_initAccel(struct sm750_dev *sm750_dev) int hw_sm750le_deWait(void) { int i = 0x10000000; + unsigned int mask = DE_STATE2_DE_STATUS_BUSY | DE_STATE2_DE_FIFO_EMPTY | + DE_STATE2_DE_MEM_FIFO_EMPTY; while (i--) { - unsigned int dwVal = PEEK32(DE_STATE2); + unsigned int val = PEEK32(DE_STATE2); - if ((FIELD_GET(dwVal, DE_STATE2, DE_STATUS) == DE_STATE2_DE_STATUS_IDLE) && - (FIELD_GET(dwVal, DE_STATE2, DE_FIFO) == DE_STATE2_DE_FIFO_EMPTY) && - (FIELD_GET(dwVal, DE_STATE2, DE_MEM_FIFO) == DE_STATE2_DE_MEM_FIFO_EMPTY)) { + if ((val & mask) == + (DE_STATE2_DE_FIFO_EMPTY | DE_STATE2_DE_MEM_FIFO_EMPTY)) return 0; - } } /* timeout error */ return -1; @@ -511,15 +513,16 @@ int hw_sm750le_deWait(void) int hw_sm750_deWait(void) { int i = 0x10000000; + unsigned int mask = SYSTEM_CTRL_DE_STATUS_BUSY | + SYSTEM_CTRL_DE_FIFO_EMPTY | + SYSTEM_CTRL_DE_MEM_FIFO_EMPTY; while (i--) { - unsigned int dwVal = PEEK32(SYSTEM_CTRL); + unsigned int val = PEEK32(SYSTEM_CTRL); - if ((FIELD_GET(dwVal, SYSTEM_CTRL, DE_STATUS) == SYSTEM_CTRL_DE_STATUS_IDLE) && - (FIELD_GET(dwVal, SYSTEM_CTRL, DE_FIFO) == SYSTEM_CTRL_DE_FIFO_EMPTY) && - (FIELD_GET(dwVal, SYSTEM_CTRL, DE_MEM_FIFO) == SYSTEM_CTRL_DE_MEM_FIFO_EMPTY)) { + if ((val & mask) == + (SYSTEM_CTRL_DE_FIFO_EMPTY | SYSTEM_CTRL_DE_MEM_FIFO_EMPTY)) return 0; - } } /* timeout error */ return -1; @@ -541,12 +544,12 @@ int hw_sm750_pan_display(struct lynxfb_crtc *crtc, total += crtc->oScreen; if (crtc->channel == sm750_primary) { POKE32(PANEL_FB_ADDRESS, - FIELD_VALUE(PEEK32(PANEL_FB_ADDRESS), - PANEL_FB_ADDRESS, ADDRESS, total)); + PEEK32(PANEL_FB_ADDRESS) | + (total & PANEL_FB_ADDRESS_ADDRESS_MASK)); } else { POKE32(CRT_FB_ADDRESS, - FIELD_VALUE(PEEK32(CRT_FB_ADDRESS), - CRT_FB_ADDRESS, ADDRESS, total)); + PEEK32(CRT_FB_ADDRESS) | + (total & CRT_FB_ADDRESS_ADDRESS_MASK)); } return 0; } |