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path: root/drivers/staging/vt6655/baseband.c
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Diffstat (limited to 'drivers/staging/vt6655/baseband.c')
-rw-r--r--drivers/staging/vt6655/baseband.c107
1 files changed, 13 insertions, 94 deletions
diff --git a/drivers/staging/vt6655/baseband.c b/drivers/staging/vt6655/baseband.c
index 84fa6ea3e2e6..6ce41983dcf4 100644
--- a/drivers/staging/vt6655/baseband.c
+++ b/drivers/staging/vt6655/baseband.c
@@ -29,7 +29,6 @@
*
*/
-#include "tmacro.h"
#include "mac.h"
#include "baseband.h"
#include "srom.h"
@@ -1910,19 +1909,19 @@ bool bb_read_embedded(struct vnt_private *priv, unsigned char by_bb_addr,
unsigned char by_value;
/* BB reg offset */
- VNSvOutPortB(iobase + MAC_REG_BBREGADR, by_bb_addr);
+ iowrite8(by_bb_addr, iobase + MAC_REG_BBREGADR);
/* turn on REGR */
- MACvRegBitsOn(iobase, MAC_REG_BBREGCTL, BBREGCTL_REGR);
+ vt6655_mac_reg_bits_on(iobase, MAC_REG_BBREGCTL, BBREGCTL_REGR);
/* W_MAX_TIMEOUT is the timeout period */
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
- VNSvInPortB(iobase + MAC_REG_BBREGCTL, &by_value);
+ by_value = ioread8(iobase + MAC_REG_BBREGCTL);
if (by_value & BBREGCTL_DONE)
break;
}
/* get BB data */
- VNSvInPortB(iobase + MAC_REG_BBREGDATA, pby_data);
+ *pby_data = ioread8(iobase + MAC_REG_BBREGDATA);
if (ww == W_MAX_TIMEOUT) {
pr_debug(" DBG_PORT80(0x30)\n");
@@ -1953,15 +1952,15 @@ bool bb_write_embedded(struct vnt_private *priv, unsigned char by_bb_addr,
unsigned char by_value;
/* BB reg offset */
- VNSvOutPortB(iobase + MAC_REG_BBREGADR, by_bb_addr);
+ iowrite8(by_bb_addr, iobase + MAC_REG_BBREGADR);
/* set BB data */
- VNSvOutPortB(iobase + MAC_REG_BBREGDATA, by_data);
+ iowrite8(by_data, iobase + MAC_REG_BBREGDATA);
/* turn on BBREGCTL_REGW */
- MACvRegBitsOn(iobase, MAC_REG_BBREGCTL, BBREGCTL_REGW);
+ vt6655_mac_reg_bits_on(iobase, MAC_REG_BBREGCTL, BBREGCTL_REGW);
/* W_MAX_TIMEOUT is the timeout period */
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
- VNSvInPortB(iobase + MAC_REG_BBREGCTL, &by_value);
+ by_value = ioread8(iobase + MAC_REG_BBREGCTL);
if (by_value & BBREGCTL_DONE)
break;
}
@@ -2014,8 +2013,8 @@ bool bb_vt3253_init(struct vnt_private *priv)
byVT3253B0_AGC4_RFMD2959[ii][0],
byVT3253B0_AGC4_RFMD2959[ii][1]);
- VNSvOutPortD(iobase + MAC_REG_ITRTMSET, 0x23);
- MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0));
+ iowrite32(0x23, iobase + MAC_REG_ITRTMSET);
+ vt6655_mac_reg_bits_on(iobase, MAC_REG_PAPEDELAY, BIT(0));
}
priv->abyBBVGA[0] = 0x18;
priv->abyBBVGA[1] = 0x0A;
@@ -2054,8 +2053,8 @@ bool bb_vt3253_init(struct vnt_private *priv)
byVT3253B0_AGC[ii][0],
byVT3253B0_AGC[ii][1]);
- VNSvOutPortB(iobase + MAC_REG_ITRTMSET, 0x23);
- MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0));
+ iowrite8(0x23, iobase + MAC_REG_ITRTMSET);
+ vt6655_mac_reg_bits_on(iobase, MAC_REG_PAPEDELAY, BIT(0));
priv->abyBBVGA[0] = 0x14;
priv->abyBBVGA[1] = 0x0A;
@@ -2065,54 +2064,6 @@ bool bb_vt3253_init(struct vnt_private *priv)
priv->dbm_threshold[1] = -50;
priv->dbm_threshold[2] = 0;
priv->dbm_threshold[3] = 0;
- } else if (by_rf_type == RF_UW2452) {
- for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++)
- result &= bb_write_embedded(priv,
- byVT3253B0_UW2451[ii][0],
- byVT3253B0_UW2451[ii][1]);
-
- /* Init ANT B select,
- * TX Config CR09 = 0x61->0x45,
- * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
- */
-
- /*bResult &= bb_write_embedded(iobase,0x09,0x41);*/
-
- /* Init ANT B select,
- * RX Config CR10 = 0x28->0x2A,
- * 0x2A->0x28(VC1/VC2 define,
- * make the ANT_A, ANT_B inverted)
- */
-
- /*bResult &= bb_write_embedded(iobase,0x0a,0x28);*/
- /* Select VC1/VC2, CR215 = 0x02->0x06 */
- result &= bb_write_embedded(priv, 0xd7, 0x06);
-
- /* {{RobertYu:20050125, request by Jack */
- result &= bb_write_embedded(priv, 0x90, 0x20);
- result &= bb_write_embedded(priv, 0x97, 0xeb);
- /* }} */
-
- /* {{RobertYu:20050221, request by Jack */
- result &= bb_write_embedded(priv, 0xa6, 0x00);
- result &= bb_write_embedded(priv, 0xa8, 0x30);
- /* }} */
- result &= bb_write_embedded(priv, 0xb0, 0x58);
-
- for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
- result &= bb_write_embedded(priv,
- byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
-
- priv->abyBBVGA[0] = 0x14;
- priv->abyBBVGA[1] = 0x0A;
- priv->abyBBVGA[2] = 0x0;
- priv->abyBBVGA[3] = 0x0;
- priv->dbm_threshold[0] = -60;
- priv->dbm_threshold[1] = -50;
- priv->dbm_threshold[2] = 0;
- priv->dbm_threshold[3] = 0;
- /* }} RobertYu */
-
} else if (by_rf_type == RF_VT3226) {
for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
result &= bb_write_embedded(priv,
@@ -2132,40 +2083,8 @@ bool bb_vt3253_init(struct vnt_private *priv)
priv->dbm_threshold[2] = 0;
priv->dbm_threshold[3] = 0;
/* Fix VT3226 DFC system timing issue */
- MACvSetRFLE_LatchBase(iobase);
+ vt6655_mac_word_reg_bits_on(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT);
/* {{ RobertYu: 20050104 */
- } else if (by_rf_type == RF_AIROHA7230) {
- for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
- result &= bb_write_embedded(priv,
- byVT3253B0_AIROHA2230[ii][0],
- byVT3253B0_AIROHA2230[ii][1]);
-
- /* {{ RobertYu:20050223, request by JerryChung */
- /* Init ANT B select,TX Config CR09 = 0x61->0x45,
- * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
- */
- /* bResult &= bb_write_embedded(iobase,0x09,0x41);*/
- /* Init ANT B select,RX Config CR10 = 0x28->0x2A,
- * 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
- */
- /* bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/
- /* Select VC1/VC2, CR215 = 0x02->0x06 */
- result &= bb_write_embedded(priv, 0xd7, 0x06);
- /* }} */
-
- for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
- result &= bb_write_embedded(priv,
- byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
-
- priv->abyBBVGA[0] = 0x1C;
- priv->abyBBVGA[1] = 0x10;
- priv->abyBBVGA[2] = 0x0;
- priv->abyBBVGA[3] = 0x0;
- priv->dbm_threshold[0] = -70;
- priv->dbm_threshold[1] = -48;
- priv->dbm_threshold[2] = 0;
- priv->dbm_threshold[3] = 0;
- /* }} RobertYu */
} else {
/* No VGA Table now */
priv->bUpdateBBVGA = false;